LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMISelLowering.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 6807 7321 93.0 %
Date: 2017-09-14 15:23:50 Functions: 284 285 99.6 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the interfaces that ARM uses to lower LLVM code into a
      11             : // selection DAG.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #include "ARMISelLowering.h"
      16             : #include "ARMBaseInstrInfo.h"
      17             : #include "ARMBaseRegisterInfo.h"
      18             : #include "ARMCallingConv.h"
      19             : #include "ARMConstantPoolValue.h"
      20             : #include "ARMMachineFunctionInfo.h"
      21             : #include "ARMPerfectShuffle.h"
      22             : #include "ARMRegisterInfo.h"
      23             : #include "ARMSelectionDAGInfo.h"
      24             : #include "ARMSubtarget.h"
      25             : #include "MCTargetDesc/ARMAddressingModes.h"
      26             : #include "MCTargetDesc/ARMBaseInfo.h"
      27             : #include "llvm/ADT/APFloat.h"
      28             : #include "llvm/ADT/APInt.h"
      29             : #include "llvm/ADT/ArrayRef.h"
      30             : #include "llvm/ADT/BitVector.h"
      31             : #include "llvm/ADT/DenseMap.h"
      32             : #include "llvm/ADT/STLExtras.h"
      33             : #include "llvm/ADT/SmallPtrSet.h"
      34             : #include "llvm/ADT/SmallVector.h"
      35             : #include "llvm/ADT/Statistic.h"
      36             : #include "llvm/ADT/StringExtras.h"
      37             : #include "llvm/ADT/StringRef.h"
      38             : #include "llvm/ADT/StringSwitch.h"
      39             : #include "llvm/ADT/Triple.h"
      40             : #include "llvm/ADT/Twine.h"
      41             : #include "llvm/Analysis/VectorUtils.h"
      42             : #include "llvm/CodeGen/CallingConvLower.h"
      43             : #include "llvm/CodeGen/ISDOpcodes.h"
      44             : #include "llvm/CodeGen/IntrinsicLowering.h"
      45             : #include "llvm/CodeGen/MachineBasicBlock.h"
      46             : #include "llvm/CodeGen/MachineConstantPool.h"
      47             : #include "llvm/CodeGen/MachineFrameInfo.h"
      48             : #include "llvm/CodeGen/MachineFunction.h"
      49             : #include "llvm/CodeGen/MachineInstr.h"
      50             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      51             : #include "llvm/CodeGen/MachineJumpTableInfo.h"
      52             : #include "llvm/CodeGen/MachineMemOperand.h"
      53             : #include "llvm/CodeGen/MachineOperand.h"
      54             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      55             : #include "llvm/CodeGen/MachineValueType.h"
      56             : #include "llvm/CodeGen/RuntimeLibcalls.h"
      57             : #include "llvm/CodeGen/SelectionDAG.h"
      58             : #include "llvm/CodeGen/SelectionDAGNodes.h"
      59             : #include "llvm/CodeGen/ValueTypes.h"
      60             : #include "llvm/IR/Attributes.h"
      61             : #include "llvm/IR/CallingConv.h"
      62             : #include "llvm/IR/Constant.h"
      63             : #include "llvm/IR/Constants.h"
      64             : #include "llvm/IR/DataLayout.h"
      65             : #include "llvm/IR/DebugLoc.h"
      66             : #include "llvm/IR/DerivedTypes.h"
      67             : #include "llvm/IR/Function.h"
      68             : #include "llvm/IR/GlobalAlias.h"
      69             : #include "llvm/IR/GlobalValue.h"
      70             : #include "llvm/IR/GlobalVariable.h"
      71             : #include "llvm/IR/IRBuilder.h"
      72             : #include "llvm/IR/InlineAsm.h"
      73             : #include "llvm/IR/Instruction.h"
      74             : #include "llvm/IR/Instructions.h"
      75             : #include "llvm/IR/IntrinsicInst.h"
      76             : #include "llvm/IR/Intrinsics.h"
      77             : #include "llvm/IR/Module.h"
      78             : #include "llvm/IR/Type.h"
      79             : #include "llvm/IR/User.h"
      80             : #include "llvm/IR/Value.h"
      81             : #include "llvm/MC/MCInstrDesc.h"
      82             : #include "llvm/MC/MCInstrItineraries.h"
      83             : #include "llvm/MC/MCRegisterInfo.h"
      84             : #include "llvm/MC/MCSchedule.h"
      85             : #include "llvm/Support/AtomicOrdering.h"
      86             : #include "llvm/Support/BranchProbability.h"
      87             : #include "llvm/Support/Casting.h"
      88             : #include "llvm/Support/CodeGen.h"
      89             : #include "llvm/Support/CommandLine.h"
      90             : #include "llvm/Support/Compiler.h"
      91             : #include "llvm/Support/Debug.h"
      92             : #include "llvm/Support/ErrorHandling.h"
      93             : #include "llvm/Support/KnownBits.h"
      94             : #include "llvm/Support/MathExtras.h"
      95             : #include "llvm/Support/raw_ostream.h"
      96             : #include "llvm/Target/TargetInstrInfo.h"
      97             : #include "llvm/Target/TargetMachine.h"
      98             : #include "llvm/Target/TargetOptions.h"
      99             : #include <algorithm>
     100             : #include <cassert>
     101             : #include <cstdint>
     102             : #include <cstdlib>
     103             : #include <iterator>
     104             : #include <limits>
     105             : #include <string>
     106             : #include <tuple>
     107             : #include <utility>
     108             : #include <vector>
     109             : 
     110             : using namespace llvm;
     111             : 
     112             : #define DEBUG_TYPE "arm-isel"
     113             : 
     114             : STATISTIC(NumTailCalls, "Number of tail calls");
     115             : STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
     116             : STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
     117             : STATISTIC(NumConstpoolPromoted,
     118             :   "Number of constants with their storage promoted into constant pools");
     119             : 
     120             : static cl::opt<bool>
     121       72306 : ARMInterworking("arm-interworking", cl::Hidden,
     122      216918 :   cl::desc("Enable / disable ARM interworking (for debugging only)"),
     123      289224 :   cl::init(true));
     124             : 
     125       72306 : static cl::opt<bool> EnableConstpoolPromotion(
     126             :     "arm-promote-constant", cl::Hidden,
     127      216918 :     cl::desc("Enable / disable promotion of unnamed_addr constants into "
     128             :              "constant pools"),
     129      289224 :     cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
     130       72306 : static cl::opt<unsigned> ConstpoolPromotionMaxSize(
     131             :     "arm-promote-constant-max-size", cl::Hidden,
     132      216918 :     cl::desc("Maximum size of constant to promote into a constant pool"),
     133      289224 :     cl::init(64));
     134       72306 : static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
     135             :     "arm-promote-constant-max-total", cl::Hidden,
     136      216918 :     cl::desc("Maximum size of ALL constants to promote into a constant pool"),
     137      289224 :     cl::init(128));
     138             : 
     139             : // The APCS parameter registers.
     140             : static const MCPhysReg GPRArgRegs[] = {
     141             :   ARM::R0, ARM::R1, ARM::R2, ARM::R3
     142             : };
     143             : 
     144       25960 : void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
     145             :                                        MVT PromotedBitwiseVT) {
     146       25960 :   if (VT != PromotedLdStVT) {
     147       47200 :     setOperationAction(ISD::LOAD, VT, Promote);
     148       47200 :     AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
     149             : 
     150       47200 :     setOperationAction(ISD::STORE, VT, Promote);
     151       23600 :     AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
     152             :   }
     153             : 
     154       25960 :   MVT ElemTy = VT.getVectorElementType();
     155       25960 :   if (ElemTy != MVT::f64)
     156       23600 :     setOperationAction(ISD::SETCC, VT, Custom);
     157       51920 :   setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
     158       51920 :   setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
     159       25960 :   if (ElemTy == MVT::i32) {
     160        9440 :     setOperationAction(ISD::SINT_TO_FP, VT, Custom);
     161        9440 :     setOperationAction(ISD::UINT_TO_FP, VT, Custom);
     162        9440 :     setOperationAction(ISD::FP_TO_SINT, VT, Custom);
     163        4720 :     setOperationAction(ISD::FP_TO_UINT, VT, Custom);
     164             :   } else {
     165       42480 :     setOperationAction(ISD::SINT_TO_FP, VT, Expand);
     166       42480 :     setOperationAction(ISD::UINT_TO_FP, VT, Expand);
     167       42480 :     setOperationAction(ISD::FP_TO_SINT, VT, Expand);
     168       21240 :     setOperationAction(ISD::FP_TO_UINT, VT, Expand);
     169             :   }
     170       51920 :   setOperationAction(ISD::BUILD_VECTOR,      VT, Custom);
     171       51920 :   setOperationAction(ISD::VECTOR_SHUFFLE,    VT, Custom);
     172       51920 :   setOperationAction(ISD::CONCAT_VECTORS,    VT, Legal);
     173       51920 :   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
     174       51920 :   setOperationAction(ISD::SELECT,            VT, Expand);
     175       51920 :   setOperationAction(ISD::SELECT_CC,         VT, Expand);
     176       51920 :   setOperationAction(ISD::VSELECT,           VT, Expand);
     177       51920 :   setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
     178       25960 :   if (VT.isInteger()) {
     179       37760 :     setOperationAction(ISD::SHL, VT, Custom);
     180       37760 :     setOperationAction(ISD::SRA, VT, Custom);
     181       18880 :     setOperationAction(ISD::SRL, VT, Custom);
     182             :   }
     183             : 
     184             :   // Promote all bit-wise operations.
     185       44840 :   if (VT.isInteger() && VT != PromotedBitwiseVT) {
     186       28320 :     setOperationAction(ISD::AND, VT, Promote);
     187       28320 :     AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
     188       28320 :     setOperationAction(ISD::OR,  VT, Promote);
     189       28320 :     AddPromotedToType (ISD::OR,  VT, PromotedBitwiseVT);
     190       28320 :     setOperationAction(ISD::XOR, VT, Promote);
     191       14160 :     AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
     192             :   }
     193             : 
     194             :   // Neon does not support vector divide/remainder operations.
     195       51920 :   setOperationAction(ISD::SDIV, VT, Expand);
     196       51920 :   setOperationAction(ISD::UDIV, VT, Expand);
     197       51920 :   setOperationAction(ISD::FDIV, VT, Expand);
     198       51920 :   setOperationAction(ISD::SREM, VT, Expand);
     199       51920 :   setOperationAction(ISD::UREM, VT, Expand);
     200       51920 :   setOperationAction(ISD::FREM, VT, Expand);
     201             : 
     202       44840 :   if (!VT.isFloatingPoint() &&
     203       42480 :       VT != MVT::v2i64 && VT != MVT::v1i64)
     204      155760 :     for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
     205      141600 :       setOperationAction(Opcode, VT, Legal);
     206       25960 : }
     207             : 
     208       11800 : void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
     209       23600 :   addRegisterClass(VT, &ARM::DPRRegClass);
     210       23600 :   addTypeForNEON(VT, MVT::f64, MVT::v2i32);
     211       11800 : }
     212             : 
     213       14160 : void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
     214       28320 :   addRegisterClass(VT, &ARM::DPairRegClass);
     215       28320 :   addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
     216       14160 : }
     217             : 
     218        4487 : ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
     219        4487 :                                      const ARMSubtarget &STI)
     220        4487 :     : TargetLowering(TM), Subtarget(&STI) {
     221        4487 :   RegInfo = Subtarget->getRegisterInfo();
     222        4487 :   Itins = Subtarget->getInstrItineraryData();
     223             : 
     224        8974 :   setBooleanContents(ZeroOrOneBooleanContent);
     225        8974 :   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
     226             : 
     227       11939 :   if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
     228        7452 :       !Subtarget->isTargetWatchOS()) {
     229        3726 :     const auto &E = Subtarget->getTargetTriple().getEnvironment();
     230             : 
     231        3726 :     bool IsHFTarget = E == Triple::EABIHF || E == Triple::GNUEABIHF ||
     232             :                       E == Triple::MuslEABIHF;
     233             :     // Windows is a special case.  Technically, we will replace all of the "GNU"
     234             :     // calls with calls to MSVCRT if appropriate and adjust the calling
     235             :     // convention then.
     236        6854 :     IsHFTarget = IsHFTarget || Subtarget->isTargetWindows();
     237             : 
     238     1594728 :     for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
     239     3182004 :       setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
     240             :                             IsHFTarget ? CallingConv::ARM_AAPCS_VFP
     241             :                                        : CallingConv::ARM_AAPCS);
     242             :   }
     243             : 
     244        8974 :   if (Subtarget->isTargetMachO()) {
     245             :     // Uses VFP for Thumb libfuncs if available.
     246        1609 :     if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
     247        1502 :         Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
     248             :       static const struct {
     249             :         const RTLIB::Libcall Op;
     250             :         const char * const Name;
     251             :         const ISD::CondCode Cond;
     252             :       } LibraryCalls[] = {
     253             :         // Single-precision floating-point arithmetic.
     254             :         { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
     255             :         { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
     256             :         { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
     257             :         { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
     258             : 
     259             :         // Double-precision floating-point arithmetic.
     260             :         { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
     261             :         { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
     262             :         { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
     263             :         { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
     264             : 
     265             :         // Single-precision comparisons.
     266             :         { RTLIB::OEQ_F32, "__eqsf2vfp",    ISD::SETNE },
     267             :         { RTLIB::UNE_F32, "__nesf2vfp",    ISD::SETNE },
     268             :         { RTLIB::OLT_F32, "__ltsf2vfp",    ISD::SETNE },
     269             :         { RTLIB::OLE_F32, "__lesf2vfp",    ISD::SETNE },
     270             :         { RTLIB::OGE_F32, "__gesf2vfp",    ISD::SETNE },
     271             :         { RTLIB::OGT_F32, "__gtsf2vfp",    ISD::SETNE },
     272             :         { RTLIB::UO_F32,  "__unordsf2vfp", ISD::SETNE },
     273             :         { RTLIB::O_F32,   "__unordsf2vfp", ISD::SETEQ },
     274             : 
     275             :         // Double-precision comparisons.
     276             :         { RTLIB::OEQ_F64, "__eqdf2vfp",    ISD::SETNE },
     277             :         { RTLIB::UNE_F64, "__nedf2vfp",    ISD::SETNE },
     278             :         { RTLIB::OLT_F64, "__ltdf2vfp",    ISD::SETNE },
     279             :         { RTLIB::OLE_F64, "__ledf2vfp",    ISD::SETNE },
     280             :         { RTLIB::OGE_F64, "__gedf2vfp",    ISD::SETNE },
     281             :         { RTLIB::OGT_F64, "__gtdf2vfp",    ISD::SETNE },
     282             :         { RTLIB::UO_F64,  "__unorddf2vfp", ISD::SETNE },
     283             :         { RTLIB::O_F64,   "__unorddf2vfp", ISD::SETEQ },
     284             : 
     285             :         // Floating-point to integer conversions.
     286             :         // i64 conversions are done via library routines even when generating VFP
     287             :         // instructions, so use the same ones.
     288             :         { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp",    ISD::SETCC_INVALID },
     289             :         { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
     290             :         { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp",    ISD::SETCC_INVALID },
     291             :         { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
     292             : 
     293             :         // Conversions between floating types.
     294             :         { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp",  ISD::SETCC_INVALID },
     295             :         { RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp", ISD::SETCC_INVALID },
     296             : 
     297             :         // Integer to floating-point conversions.
     298             :         // i64 conversions are done via library routines even when generating VFP
     299             :         // instructions, so use the same ones.
     300             :         // FIXME: There appears to be some naming inconsistency in ARM libgcc:
     301             :         // e.g., __floatunsidf vs. __floatunssidfvfp.
     302             :         { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp",    ISD::SETCC_INVALID },
     303             :         { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
     304             :         { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp",    ISD::SETCC_INVALID },
     305             :         { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
     306             :       };
     307             : 
     308       24081 :       for (const auto &LC : LibraryCalls) {
     309       23732 :         setLibcallName(LC.Op, LC.Name);
     310       11866 :         if (LC.Cond != ISD::SETCC_INVALID)
     311        5584 :           setCmpLibcallCC(LC.Op, LC.Cond);
     312             :       }
     313             :     }
     314             : 
     315             :     // Set the correct calling convention for ARMv7k WatchOS. It's just
     316             :     // AAPCS_VFP for functions as simple as libcalls.
     317        1592 :     if (Subtarget->isTargetWatchABI()) {
     318       19665 :       for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i)
     319       19642 :         setLibcallCallingConv((RTLIB::Libcall)i, CallingConv::ARM_AAPCS_VFP);
     320             :     }
     321             :   }
     322             : 
     323             :   // These libcalls are not available in 32-bit.
     324        8974 :   setLibcallName(RTLIB::SHL_I128, nullptr);
     325        8974 :   setLibcallName(RTLIB::SRL_I128, nullptr);
     326        8974 :   setLibcallName(RTLIB::SRA_I128, nullptr);
     327             : 
     328             :   // RTLIB
     329        4487 :   if (Subtarget->isAAPCS_ABI() &&
     330        5831 :       (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
     331        2467 :        Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
     332             :     static const struct {
     333             :       const RTLIB::Libcall Op;
     334             :       const char * const Name;
     335             :       const CallingConv::ID CC;
     336             :       const ISD::CondCode Cond;
     337             :     } LibraryCalls[] = {
     338             :       // Double-precision floating-point arithmetic helper functions
     339             :       // RTABI chapter 4.1.2, Table 2
     340             :       { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     341             :       { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     342             :       { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     343             :       { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     344             : 
     345             :       // Double-precision floating-point comparison helper functions
     346             :       // RTABI chapter 4.1.2, Table 3
     347             :       { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
     348             :       { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
     349             :       { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
     350             :       { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
     351             :       { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
     352             :       { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
     353             :       { RTLIB::UO_F64,  "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
     354             :       { RTLIB::O_F64,   "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
     355             : 
     356             :       // Single-precision floating-point arithmetic helper functions
     357             :       // RTABI chapter 4.1.2, Table 4
     358             :       { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     359             :       { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     360             :       { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     361             :       { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     362             : 
     363             :       // Single-precision floating-point comparison helper functions
     364             :       // RTABI chapter 4.1.2, Table 5
     365             :       { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
     366             :       { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
     367             :       { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
     368             :       { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
     369             :       { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
     370             :       { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
     371             :       { RTLIB::UO_F32,  "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
     372             :       { RTLIB::O_F32,   "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
     373             : 
     374             :       // Floating-point to integer conversions.
     375             :       // RTABI chapter 4.1.2, Table 6
     376             :       { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     377             :       { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     378             :       { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     379             :       { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     380             :       { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     381             :       { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     382             :       { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     383             :       { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     384             : 
     385             :       // Conversions between floating types.
     386             :       // RTABI chapter 4.1.2, Table 7
     387             :       { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     388             :       { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     389             :       { RTLIB::FPEXT_F32_F64,   "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     390             : 
     391             :       // Integer to floating-point conversions.
     392             :       // RTABI chapter 4.1.2, Table 8
     393             :       { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     394             :       { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     395             :       { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     396             :       { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     397             :       { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     398             :       { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     399             :       { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     400             :       { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     401             : 
     402             :       // Long long helper functions
     403             :       // RTABI chapter 4.2, Table 9
     404             :       { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     405             :       { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     406             :       { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     407             :       { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     408             : 
     409             :       // Integer division functions
     410             :       // RTABI chapter 4.3.1
     411             :       { RTLIB::SDIV_I8,  "__aeabi_idiv",     CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     412             :       { RTLIB::SDIV_I16, "__aeabi_idiv",     CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     413             :       { RTLIB::SDIV_I32, "__aeabi_idiv",     CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     414             :       { RTLIB::SDIV_I64, "__aeabi_ldivmod",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     415             :       { RTLIB::UDIV_I8,  "__aeabi_uidiv",    CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     416             :       { RTLIB::UDIV_I16, "__aeabi_uidiv",    CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     417             :       { RTLIB::UDIV_I32, "__aeabi_uidiv",    CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     418             :       { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     419             :     };
     420             : 
     421      335109 :     for (const auto &LC : LibraryCalls) {
     422      332090 :       setLibcallName(LC.Op, LC.Name);
     423      332090 :       setLibcallCallingConv(LC.Op, LC.CC);
     424      166045 :       if (LC.Cond != ISD::SETCC_INVALID)
     425       48304 :         setCmpLibcallCC(LC.Op, LC.Cond);
     426             :     }
     427             : 
     428             :     // EABI dependent RTLIB
     429        3019 :     if (TM.Options.EABIVersion == EABI::EABI4 ||
     430             :         TM.Options.EABIVersion == EABI::EABI5) {
     431             :       static const struct {
     432             :         const RTLIB::Libcall Op;
     433             :         const char *const Name;
     434             :         const CallingConv::ID CC;
     435             :         const ISD::CondCode Cond;
     436             :       } MemOpsLibraryCalls[] = {
     437             :         // Memory operations
     438             :         // RTABI chapter 4.3.4
     439             :         { RTLIB::MEMCPY,  "__aeabi_memcpy",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     440             :         { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     441             :         { RTLIB::MEMSET,  "__aeabi_memset",  CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
     442             :       };
     443             : 
     444       12236 :       for (const auto &LC : MemOpsLibraryCalls) {
     445       10488 :         setLibcallName(LC.Op, LC.Name);
     446       10488 :         setLibcallCallingConv(LC.Op, LC.CC);
     447        5244 :         if (LC.Cond != ISD::SETCC_INVALID)
     448           0 :           setCmpLibcallCC(LC.Op, LC.Cond);
     449             :       }
     450             :     }
     451             :   }
     452             : 
     453        8974 :   if (Subtarget->isTargetWindows()) {
     454             :     static const struct {
     455             :       const RTLIB::Libcall Op;
     456             :       const char * const Name;
     457             :       const CallingConv::ID CC;
     458             :     } LibraryCalls[] = {
     459             :       { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
     460             :       { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
     461             :       { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
     462             :       { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
     463             :       { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
     464             :       { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
     465             :       { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
     466             :       { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
     467             :     };
     468             : 
     469        1224 :     for (const auto &LC : LibraryCalls) {
     470        1152 :       setLibcallName(LC.Op, LC.Name);
     471        1152 :       setLibcallCallingConv(LC.Op, LC.CC);
     472             :     }
     473             :   }
     474             : 
     475             :   // Use divmod compiler-rt calls for iOS 5.0 and later.
     476        8974 :   if (Subtarget->isTargetMachO() &&
     477        1166 :       !(Subtarget->isTargetIOS() &&
     478         740 :         Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
     479        1030 :     setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
     480         515 :     setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
     481             :   }
     482             : 
     483             :   // The half <-> float conversion functions are always soft-float on
     484             :   // non-watchos platforms, but are needed for some targets which use a
     485             :   // hard-float calling convention by default.
     486        8974 :   if (!Subtarget->isTargetWatchABI()) {
     487        4464 :     if (Subtarget->isAAPCS_ABI()) {
     488        7456 :       setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
     489        7456 :       setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
     490        3728 :       setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
     491             :     } else {
     492        1472 :       setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
     493        1472 :       setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
     494         736 :       setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
     495             :     }
     496             :   }
     497             : 
     498             :   // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
     499             :   // a __gnu_ prefix (which is the default).
     500        4487 :   if (Subtarget->isTargetAEABI()) {
     501             :     static const struct {
     502             :       const RTLIB::Libcall Op;
     503             :       const char * const Name;
     504             :       const CallingConv::ID CC;
     505             :     } LibraryCalls[] = {
     506             :       { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
     507             :       { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
     508             :       { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
     509             :     };
     510             : 
     511       11697 :     for (const auto &LC : LibraryCalls) {
     512       10026 :       setLibcallName(LC.Op, LC.Name);
     513       10026 :       setLibcallCallingConv(LC.Op, LC.CC);
     514             :     }
     515             :   }
     516             : 
     517        4487 :   if (Subtarget->isThumb1Only())
     518         846 :     addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
     519             :   else
     520        8128 :     addRegisterClass(MVT::i32, &ARM::GPRRegClass);
     521             : 
     522        4487 :   if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
     523        2693 :       !Subtarget->isThumb1Only()) {
     524        5372 :     addRegisterClass(MVT::f32, &ARM::SPRRegClass);
     525        5372 :     addRegisterClass(MVT::f64, &ARM::DPRRegClass);
     526             :   }
     527             : 
     528      426265 :   for (MVT VT : MVT::vector_valuetypes()) {
     529    79716042 :     for (MVT InnerVT : MVT::vector_valuetypes()) {
     530    79294264 :       setTruncStoreAction(VT, InnerVT, Expand);
     531    79294264 :       setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
     532    79294264 :       setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
     533    79294264 :       setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
     534             :     }
     535             : 
     536      843556 :     setOperationAction(ISD::MULHS, VT, Expand);
     537      843556 :     setOperationAction(ISD::SMUL_LOHI, VT, Expand);
     538      843556 :     setOperationAction(ISD::MULHU, VT, Expand);
     539      843556 :     setOperationAction(ISD::UMUL_LOHI, VT, Expand);
     540             : 
     541      843556 :     setOperationAction(ISD::BSWAP, VT, Expand);
     542             :   }
     543             : 
     544        8974 :   setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
     545        8974 :   setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
     546             : 
     547        8974 :   setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
     548        8974 :   setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
     549             : 
     550        4487 :   if (Subtarget->hasNEON()) {
     551        2360 :     addDRTypeForNEON(MVT::v2f32);
     552        2360 :     addDRTypeForNEON(MVT::v8i8);
     553        2360 :     addDRTypeForNEON(MVT::v4i16);
     554        2360 :     addDRTypeForNEON(MVT::v2i32);
     555        2360 :     addDRTypeForNEON(MVT::v1i64);
     556             : 
     557        2360 :     addQRTypeForNEON(MVT::v4f32);
     558        2360 :     addQRTypeForNEON(MVT::v2f64);
     559        2360 :     addQRTypeForNEON(MVT::v16i8);
     560        2360 :     addQRTypeForNEON(MVT::v8i16);
     561        2360 :     addQRTypeForNEON(MVT::v4i32);
     562        2360 :     addQRTypeForNEON(MVT::v2i64);
     563             : 
     564             :     // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
     565             :     // neither Neon nor VFP support any arithmetic operations on it.
     566             :     // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
     567             :     // supported for v4f32.
     568        4720 :     setOperationAction(ISD::FADD, MVT::v2f64, Expand);
     569        4720 :     setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
     570        4720 :     setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
     571             :     // FIXME: Code duplication: FDIV and FREM are expanded always, see
     572             :     // ARMTargetLowering::addTypeForNEON method for details.
     573        4720 :     setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
     574        4720 :     setOperationAction(ISD::FREM, MVT::v2f64, Expand);
     575             :     // FIXME: Create unittest.
     576             :     // In another words, find a way when "copysign" appears in DAG with vector
     577             :     // operands.
     578        4720 :     setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
     579             :     // FIXME: Code duplication: SETCC has custom operation action, see
     580             :     // ARMTargetLowering::addTypeForNEON method for details.
     581        4720 :     setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
     582             :     // FIXME: Create unittest for FNEG and for FABS.
     583        4720 :     setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
     584        4720 :     setOperationAction(ISD::FABS, MVT::v2f64, Expand);
     585        4720 :     setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
     586        4720 :     setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
     587        4720 :     setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
     588        4720 :     setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
     589        4720 :     setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
     590        4720 :     setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
     591        4720 :     setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
     592        4720 :     setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
     593        4720 :     setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
     594             :     // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
     595        4720 :     setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
     596        4720 :     setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
     597        4720 :     setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
     598        4720 :     setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
     599        4720 :     setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
     600        4720 :     setOperationAction(ISD::FMA, MVT::v2f64, Expand);
     601             : 
     602        4720 :     setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
     603        4720 :     setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
     604        4720 :     setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
     605        4720 :     setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
     606        4720 :     setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
     607        4720 :     setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
     608        4720 :     setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
     609        4720 :     setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
     610        4720 :     setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
     611        4720 :     setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
     612        4720 :     setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
     613        4720 :     setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
     614        4720 :     setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
     615        4720 :     setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
     616             : 
     617             :     // Mark v2f32 intrinsics.
     618        4720 :     setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
     619        4720 :     setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
     620        4720 :     setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
     621        4720 :     setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
     622        4720 :     setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
     623        4720 :     setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
     624        4720 :     setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
     625        4720 :     setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
     626        4720 :     setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
     627        4720 :     setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
     628        4720 :     setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
     629        4720 :     setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
     630        4720 :     setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
     631        4720 :     setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
     632             : 
     633             :     // Neon does not support some operations on v1i64 and v2i64 types.
     634        4720 :     setOperationAction(ISD::MUL, MVT::v1i64, Expand);
     635             :     // Custom handling for some quad-vector types to detect VMULL.
     636        4720 :     setOperationAction(ISD::MUL, MVT::v8i16, Custom);
     637        4720 :     setOperationAction(ISD::MUL, MVT::v4i32, Custom);
     638        4720 :     setOperationAction(ISD::MUL, MVT::v2i64, Custom);
     639             :     // Custom handling for some vector types to avoid expensive expansions
     640        4720 :     setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
     641        4720 :     setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
     642        4720 :     setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
     643        4720 :     setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
     644             :     // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
     645             :     // a destination type that is wider than the source, and nor does
     646             :     // it have a FP_TO_[SU]INT instruction with a narrower destination than
     647             :     // source.
     648        4720 :     setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
     649        4720 :     setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
     650        4720 :     setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
     651        4720 :     setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
     652             : 
     653        4720 :     setOperationAction(ISD::FP_ROUND,   MVT::v2f32, Expand);
     654        4720 :     setOperationAction(ISD::FP_EXTEND,  MVT::v2f64, Expand);
     655             : 
     656             :     // NEON does not have single instruction CTPOP for vectors with element
     657             :     // types wider than 8-bits.  However, custom lowering can leverage the
     658             :     // v8i8/v16i8 vcnt instruction.
     659        4720 :     setOperationAction(ISD::CTPOP,      MVT::v2i32, Custom);
     660        4720 :     setOperationAction(ISD::CTPOP,      MVT::v4i32, Custom);
     661        4720 :     setOperationAction(ISD::CTPOP,      MVT::v4i16, Custom);
     662        4720 :     setOperationAction(ISD::CTPOP,      MVT::v8i16, Custom);
     663        4720 :     setOperationAction(ISD::CTPOP,      MVT::v1i64, Expand);
     664        4720 :     setOperationAction(ISD::CTPOP,      MVT::v2i64, Expand);
     665             : 
     666        4720 :     setOperationAction(ISD::CTLZ,       MVT::v1i64, Expand);
     667        4720 :     setOperationAction(ISD::CTLZ,       MVT::v2i64, Expand);
     668             : 
     669             :     // NEON does not have single instruction CTTZ for vectors.
     670        4720 :     setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
     671        4720 :     setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
     672        4720 :     setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
     673        4720 :     setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
     674             : 
     675        4720 :     setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
     676        4720 :     setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
     677        4720 :     setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
     678        4720 :     setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
     679             : 
     680        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
     681        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
     682        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
     683        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
     684             : 
     685        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
     686        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
     687        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
     688        4720 :     setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
     689             : 
     690             :     // NEON only has FMA instructions as of VFP4.
     691        2360 :     if (!Subtarget->hasVFP4()) {
     692        3654 :       setOperationAction(ISD::FMA, MVT::v2f32, Expand);
     693        3654 :       setOperationAction(ISD::FMA, MVT::v4f32, Expand);
     694             :     }
     695             : 
     696        4720 :     setTargetDAGCombine(ISD::INTRINSIC_VOID);
     697        4720 :     setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
     698        4720 :     setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
     699        4720 :     setTargetDAGCombine(ISD::SHL);
     700        4720 :     setTargetDAGCombine(ISD::SRL);
     701        4720 :     setTargetDAGCombine(ISD::SRA);
     702        4720 :     setTargetDAGCombine(ISD::SIGN_EXTEND);
     703        4720 :     setTargetDAGCombine(ISD::ZERO_EXTEND);
     704        4720 :     setTargetDAGCombine(ISD::ANY_EXTEND);
     705        4720 :     setTargetDAGCombine(ISD::BUILD_VECTOR);
     706        4720 :     setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
     707        4720 :     setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
     708        4720 :     setTargetDAGCombine(ISD::STORE);
     709        4720 :     setTargetDAGCombine(ISD::FP_TO_SINT);
     710        4720 :     setTargetDAGCombine(ISD::FP_TO_UINT);
     711        4720 :     setTargetDAGCombine(ISD::FDIV);
     712        4720 :     setTargetDAGCombine(ISD::LOAD);
     713             : 
     714             :     // It is legal to extload from v4i8 to v4i16 or v4i32.
     715       14160 :     for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
     716       18880 :                    MVT::v2i32}) {
     717     1005360 :       for (MVT VT : MVT::integer_vector_valuetypes()) {
     718     1982400 :         setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
     719     1982400 :         setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
     720     1982400 :         setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
     721             :       }
     722             :     }
     723             :   }
     724             : 
     725        4487 :   if (Subtarget->isFPOnlySP()) {
     726             :     // When targeting a floating-point unit with only single-precision
     727             :     // operations, f64 is legal for the few double-precision instructions which
     728             :     // are present However, no double-precision operations other than moves,
     729             :     // loads and stores are provided by the hardware.
     730         172 :     setOperationAction(ISD::FADD,       MVT::f64, Expand);
     731         172 :     setOperationAction(ISD::FSUB,       MVT::f64, Expand);
     732         172 :     setOperationAction(ISD::FMUL,       MVT::f64, Expand);
     733         172 :     setOperationAction(ISD::FMA,        MVT::f64, Expand);
     734         172 :     setOperationAction(ISD::FDIV,       MVT::f64, Expand);
     735         172 :     setOperationAction(ISD::FREM,       MVT::f64, Expand);
     736         172 :     setOperationAction(ISD::FCOPYSIGN,  MVT::f64, Expand);
     737         172 :     setOperationAction(ISD::FGETSIGN,   MVT::f64, Expand);
     738         172 :     setOperationAction(ISD::FNEG,       MVT::f64, Expand);
     739         172 :     setOperationAction(ISD::FABS,       MVT::f64, Expand);
     740         172 :     setOperationAction(ISD::FSQRT,      MVT::f64, Expand);
     741         172 :     setOperationAction(ISD::FSIN,       MVT::f64, Expand);
     742         172 :     setOperationAction(ISD::FCOS,       MVT::f64, Expand);
     743         172 :     setOperationAction(ISD::FPOW,       MVT::f64, Expand);
     744         172 :     setOperationAction(ISD::FLOG,       MVT::f64, Expand);
     745         172 :     setOperationAction(ISD::FLOG2,      MVT::f64, Expand);
     746         172 :     setOperationAction(ISD::FLOG10,     MVT::f64, Expand);
     747         172 :     setOperationAction(ISD::FEXP,       MVT::f64, Expand);
     748         172 :     setOperationAction(ISD::FEXP2,      MVT::f64, Expand);
     749         172 :     setOperationAction(ISD::FCEIL,      MVT::f64, Expand);
     750         172 :     setOperationAction(ISD::FTRUNC,     MVT::f64, Expand);
     751         172 :     setOperationAction(ISD::FRINT,      MVT::f64, Expand);
     752         172 :     setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
     753         172 :     setOperationAction(ISD::FFLOOR,     MVT::f64, Expand);
     754         172 :     setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
     755         172 :     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
     756         172 :     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     757         172 :     setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
     758         172 :     setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
     759         172 :     setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
     760         172 :     setOperationAction(ISD::FP_ROUND,   MVT::f32, Custom);
     761         172 :     setOperationAction(ISD::FP_EXTEND,  MVT::f64, Custom);
     762             :   }
     763             : 
     764        4487 :   computeRegisterProperties(Subtarget->getRegisterInfo());
     765             : 
     766             :   // ARM does not have floating-point extending loads.
     767       31409 :   for (MVT VT : MVT::fp_valuetypes()) {
     768       53844 :     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
     769       53844 :     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
     770             :   }
     771             : 
     772             :   // ... or truncating stores
     773        8974 :   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
     774        8974 :   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
     775        8974 :   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
     776             : 
     777             :   // ARM does not have i1 sign extending load.
     778       31409 :   for (MVT VT : MVT::integer_valuetypes())
     779       53844 :     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
     780             : 
     781             :   // ARM supports all 4 flavors of integer indexed load / store.
     782        4487 :   if (!Subtarget->isThumb1Only()) {
     783       16256 :     for (unsigned im = (unsigned)ISD::PRE_INC;
     784       20320 :          im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
     785       32512 :       setIndexedLoadAction(im,  MVT::i1,  Legal);
     786       32512 :       setIndexedLoadAction(im,  MVT::i8,  Legal);
     787       32512 :       setIndexedLoadAction(im,  MVT::i16, Legal);
     788       32512 :       setIndexedLoadAction(im,  MVT::i32, Legal);
     789       32512 :       setIndexedStoreAction(im, MVT::i1,  Legal);
     790       32512 :       setIndexedStoreAction(im, MVT::i8,  Legal);
     791       32512 :       setIndexedStoreAction(im, MVT::i16, Legal);
     792       32512 :       setIndexedStoreAction(im, MVT::i32, Legal);
     793             :     }
     794             :   } else {
     795             :     // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
     796         423 :     setIndexedLoadAction(ISD::POST_INC, MVT::i32,  Legal);
     797         846 :     setIndexedStoreAction(ISD::POST_INC, MVT::i32,  Legal);
     798             :   }
     799             : 
     800        8974 :   setOperationAction(ISD::SADDO, MVT::i32, Custom);
     801        8974 :   setOperationAction(ISD::UADDO, MVT::i32, Custom);
     802        8974 :   setOperationAction(ISD::SSUBO, MVT::i32, Custom);
     803        8974 :   setOperationAction(ISD::USUBO, MVT::i32, Custom);
     804             : 
     805             :   // i64 operation support.
     806        8974 :   setOperationAction(ISD::MUL,     MVT::i64, Expand);
     807        8974 :   setOperationAction(ISD::MULHU,   MVT::i32, Expand);
     808        4487 :   if (Subtarget->isThumb1Only()) {
     809         846 :     setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
     810         846 :     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
     811             :   }
     812        8551 :   if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
     813        4311 :       || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
     814        3336 :     setOperationAction(ISD::MULHS, MVT::i32, Expand);
     815             : 
     816        8974 :   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
     817        8974 :   setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
     818        8974 :   setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
     819        8974 :   setOperationAction(ISD::SRL,       MVT::i64, Custom);
     820        8974 :   setOperationAction(ISD::SRA,       MVT::i64, Custom);
     821        8974 :   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
     822             : 
     823        8974 :   setOperationAction(ISD::ADDC,      MVT::i32, Custom);
     824        8974 :   setOperationAction(ISD::ADDE,      MVT::i32, Custom);
     825        8974 :   setOperationAction(ISD::SUBC,      MVT::i32, Custom);
     826        8974 :   setOperationAction(ISD::SUBE,      MVT::i32, Custom);
     827             : 
     828        8551 :   if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
     829        5556 :     setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
     830             : 
     831             :   // ARM does not have ROTL.
     832        8974 :   setOperationAction(ISD::ROTL, MVT::i32, Expand);
     833      426265 :   for (MVT VT : MVT::vector_valuetypes()) {
     834      843556 :     setOperationAction(ISD::ROTL, VT, Expand);
     835      843556 :     setOperationAction(ISD::ROTR, VT, Expand);
     836             :   }
     837        8974 :   setOperationAction(ISD::CTTZ,  MVT::i32, Custom);
     838        8974 :   setOperationAction(ISD::CTPOP, MVT::i32, Expand);
     839        4487 :   if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
     840        2934 :     setOperationAction(ISD::CTLZ, MVT::i32, Expand);
     841             : 
     842             :   // @llvm.readcyclecounter requires the Performance Monitors extension.
     843             :   // Default to the 0 expansion on unsupported platforms.
     844             :   // FIXME: Technically there are older ARM CPUs that have
     845             :   // implementation-specific ways of obtaining this information.
     846        4487 :   if (Subtarget->hasPerfMon())
     847        5126 :     setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
     848             : 
     849             :   // Only ARMv6 has BSWAP.
     850        4487 :   if (!Subtarget->hasV6Ops())
     851        2506 :     setOperationAction(ISD::BSWAP, MVT::i32, Expand);
     852             : 
     853        4487 :   bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
     854        4487 :                                         : Subtarget->hasDivideInARMMode();
     855        4487 :   if (!hasDivide) {
     856             :     // These are expanded into libcalls if the cpu doesn't have HW divider.
     857        7164 :     setOperationAction(ISD::SDIV,  MVT::i32, LibCall);
     858        7164 :     setOperationAction(ISD::UDIV,  MVT::i32, LibCall);
     859             :   }
     860             : 
     861        8974 :   if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
     862         144 :     setOperationAction(ISD::SDIV, MVT::i32, Custom);
     863         144 :     setOperationAction(ISD::UDIV, MVT::i32, Custom);
     864             : 
     865         144 :     setOperationAction(ISD::SDIV, MVT::i64, Custom);
     866         144 :     setOperationAction(ISD::UDIV, MVT::i64, Custom);
     867             :   }
     868             : 
     869        8974 :   setOperationAction(ISD::SREM,  MVT::i32, Expand);
     870        8974 :   setOperationAction(ISD::UREM,  MVT::i32, Expand);
     871             : 
     872             :   // Register based DivRem for AEABI (RTABI 4.2)
     873       10119 :   if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
     874        5735 :       Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
     875        2932 :       Subtarget->isTargetWindows()) {
     876        6186 :     setOperationAction(ISD::SREM, MVT::i64, Custom);
     877        6186 :     setOperationAction(ISD::UREM, MVT::i64, Custom);
     878        3093 :     HasStandaloneRem = false;
     879             : 
     880        6186 :     if (Subtarget->isTargetWindows()) {
     881             :       const struct {
     882             :         const RTLIB::Libcall Op;
     883             :         const char * const Name;
     884             :         const CallingConv::ID CC;
     885          72 :       } LibraryCalls[] = {
     886             :         { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
     887             :         { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
     888             :         { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
     889             :         { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
     890             : 
     891             :         { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
     892             :         { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
     893             :         { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
     894             :         { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
     895             :       };
     896             : 
     897         648 :       for (const auto &LC : LibraryCalls) {
     898        1152 :         setLibcallName(LC.Op, LC.Name);
     899        1152 :         setLibcallCallingConv(LC.Op, LC.CC);
     900             :       }
     901             :     } else {
     902             :       const struct {
     903             :         const RTLIB::Libcall Op;
     904             :         const char * const Name;
     905             :         const CallingConv::ID CC;
     906        3021 :       } LibraryCalls[] = {
     907             :         { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
     908             :         { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
     909             :         { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
     910             :         { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
     911             : 
     912             :         { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
     913             :         { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
     914             :         { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
     915             :         { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
     916             :       };
     917             : 
     918       27189 :       for (const auto &LC : LibraryCalls) {
     919       48336 :         setLibcallName(LC.Op, LC.Name);
     920       48336 :         setLibcallCallingConv(LC.Op, LC.CC);
     921             :       }
     922             :     }
     923             : 
     924        6186 :     setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
     925        6186 :     setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
     926        6186 :     setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
     927        6186 :     setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
     928             :   } else {
     929        2788 :     setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
     930        2788 :     setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
     931             :   }
     932             : 
     933        8974 :   if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
     934         360 :     for (auto &VT : {MVT::f32, MVT::f64})
     935         288 :       setOperationAction(ISD::FPOWI, VT, Custom);
     936             : 
     937        8974 :   setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
     938        8974 :   setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
     939        8974 :   setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
     940        8974 :   setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
     941             : 
     942        8974 :   setOperationAction(ISD::TRAP, MVT::Other, Legal);
     943             : 
     944             :   // Use the default implementation.
     945        8974 :   setOperationAction(ISD::VASTART,            MVT::Other, Custom);
     946        8974 :   setOperationAction(ISD::VAARG,              MVT::Other, Expand);
     947        8974 :   setOperationAction(ISD::VACOPY,             MVT::Other, Expand);
     948        8974 :   setOperationAction(ISD::VAEND,              MVT::Other, Expand);
     949        8974 :   setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
     950        8974 :   setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
     951             : 
     952        4522 :   if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
     953          70 :     setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
     954             :   else
     955        8904 :     setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
     956             : 
     957             :   // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
     958             :   // the default expansion.
     959        4487 :   InsertFencesForAtomic = false;
     960        7475 :   if (Subtarget->hasAnyDataBarrier() &&
     961        4325 :       (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
     962             :     // ATOMIC_FENCE needs custom lowering; the others should have been expanded
     963             :     // to ldrex/strex loops already.
     964        5658 :     setOperationAction(ISD::ATOMIC_FENCE,     MVT::Other, Custom);
     965        4007 :     if (!Subtarget->isThumb() || !Subtarget->isMClass())
     966        5010 :       setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i64, Custom);
     967             : 
     968             :     // On v8, we have particularly efficient implementations of atomic fences
     969             :     // if they can be combined with nearby atomic loads and stores.
     970        2829 :     if (!Subtarget->hasV8Ops() || getTargetMachine().getOptLevel() == 0) {
     971             :       // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
     972        2593 :       InsertFencesForAtomic = true;
     973             :     }
     974             :   } else {
     975             :     // If there's anything we can use as a barrier, go through custom lowering
     976             :     // for ATOMIC_FENCE.
     977             :     // If target has DMB in thumb, Fences can be inserted.
     978        1658 :     if (Subtarget->hasDataBarrier())
     979         159 :       InsertFencesForAtomic = true;
     980             : 
     981        3316 :     setOperationAction(ISD::ATOMIC_FENCE,   MVT::Other,
     982        1904 :                        Subtarget->hasAnyDataBarrier() ? Custom : Expand);
     983             : 
     984             :     // Set them all for expansion, which will force libcalls.
     985        3316 :     setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Expand);
     986        3316 :     setOperationAction(ISD::ATOMIC_SWAP,      MVT::i32, Expand);
     987        3316 :     setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Expand);
     988        3316 :     setOperationAction(ISD::ATOMIC_LOAD_SUB,  MVT::i32, Expand);
     989        3316 :     setOperationAction(ISD::ATOMIC_LOAD_AND,  MVT::i32, Expand);
     990        3316 :     setOperationAction(ISD::ATOMIC_LOAD_OR,   MVT::i32, Expand);
     991        3316 :     setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Expand);
     992        3316 :     setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
     993        3316 :     setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
     994        3316 :     setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
     995        3316 :     setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
     996        3316 :     setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
     997             :     // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
     998             :     // Unordered/Monotonic case.
     999        1658 :     if (!InsertFencesForAtomic) {
    1000        2998 :       setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
    1001        2998 :       setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
    1002             :     }
    1003             :   }
    1004             : 
    1005        8974 :   setOperationAction(ISD::PREFETCH,         MVT::Other, Custom);
    1006             : 
    1007             :   // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
    1008        4487 :   if (!Subtarget->hasV6Ops()) {
    1009        2506 :     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
    1010        2506 :     setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
    1011             :   }
    1012        8974 :   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
    1013             : 
    1014        4487 :   if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
    1015        2693 :       !Subtarget->isThumb1Only()) {
    1016             :     // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
    1017             :     // iff target supports vfp2.
    1018        5372 :     setOperationAction(ISD::BITCAST, MVT::i64, Custom);
    1019        5372 :     setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
    1020             :   }
    1021             : 
    1022             :   // We want to custom lower some of our intrinsics.
    1023        8974 :   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
    1024        8974 :   setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
    1025        8974 :   setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
    1026        8974 :   setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
    1027        4487 :   if (Subtarget->useSjLjEH())
    1028         738 :     setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
    1029             : 
    1030        8974 :   setOperationAction(ISD::SETCC,     MVT::i32, Expand);
    1031        8974 :   setOperationAction(ISD::SETCC,     MVT::f32, Expand);
    1032        8974 :   setOperationAction(ISD::SETCC,     MVT::f64, Expand);
    1033        8974 :   setOperationAction(ISD::SELECT,    MVT::i32, Custom);
    1034        8974 :   setOperationAction(ISD::SELECT,    MVT::f32, Custom);
    1035        8974 :   setOperationAction(ISD::SELECT,    MVT::f64, Custom);
    1036        8974 :   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
    1037        8974 :   setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
    1038        8974 :   setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
    1039             : 
    1040             :   // Thumb-1 cannot currently select ARMISD::SUBE.
    1041        4487 :   if (!Subtarget->isThumb1Only())
    1042        8128 :     setOperationAction(ISD::SETCCE, MVT::i32, Custom);
    1043             : 
    1044        8974 :   setOperationAction(ISD::BRCOND,    MVT::Other, Expand);
    1045        8974 :   setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
    1046        8974 :   setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
    1047        8974 :   setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
    1048        8974 :   setOperationAction(ISD::BR_JT,     MVT::Other, Custom);
    1049             : 
    1050             :   // We don't support sin/cos/fmod/copysign/pow
    1051        8974 :   setOperationAction(ISD::FSIN,      MVT::f64, Expand);
    1052        8974 :   setOperationAction(ISD::FSIN,      MVT::f32, Expand);
    1053        8974 :   setOperationAction(ISD::FCOS,      MVT::f32, Expand);
    1054        8974 :   setOperationAction(ISD::FCOS,      MVT::f64, Expand);
    1055        8974 :   setOperationAction(ISD::FSINCOS,   MVT::f64, Expand);
    1056        8974 :   setOperationAction(ISD::FSINCOS,   MVT::f32, Expand);
    1057        8974 :   setOperationAction(ISD::FREM,      MVT::f64, Expand);
    1058        8974 :   setOperationAction(ISD::FREM,      MVT::f32, Expand);
    1059        4487 :   if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
    1060        2693 :       !Subtarget->isThumb1Only()) {
    1061        5372 :     setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
    1062        5372 :     setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
    1063             :   }
    1064        8974 :   setOperationAction(ISD::FPOW,      MVT::f64, Expand);
    1065        8974 :   setOperationAction(ISD::FPOW,      MVT::f32, Expand);
    1066             : 
    1067        4487 :   if (!Subtarget->hasVFP4()) {
    1068        7680 :     setOperationAction(ISD::FMA, MVT::f64, Expand);
    1069        7680 :     setOperationAction(ISD::FMA, MVT::f32, Expand);
    1070             :   }
    1071             : 
    1072             :   // Various VFP goodness
    1073        4487 :   if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
    1074             :     // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
    1075        4036 :     if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
    1076        7524 :       setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
    1077        7524 :       setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
    1078             :     }
    1079             : 
    1080             :     // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
    1081        4036 :     if (!Subtarget->hasFP16()) {
    1082        6460 :       setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
    1083        6460 :       setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
    1084             :     }
    1085             :   }
    1086             : 
    1087             :   // Combine sin / cos into one node or libcall if possible.
    1088        4487 :   if (Subtarget->hasSinCos()) {
    1089         136 :     setLibcallName(RTLIB::SINCOS_F32, "sincosf");
    1090         136 :     setLibcallName(RTLIB::SINCOS_F64, "sincos");
    1091         136 :     if (Subtarget->isTargetWatchABI()) {
    1092          38 :       setLibcallCallingConv(RTLIB::SINCOS_F32, CallingConv::ARM_AAPCS_VFP);
    1093          19 :       setLibcallCallingConv(RTLIB::SINCOS_F64, CallingConv::ARM_AAPCS_VFP);
    1094             :     }
    1095         104 :     if (Subtarget->isTargetIOS() || Subtarget->isTargetWatchOS()) {
    1096             :       // For iOS, we don't want to the normal expansion of a libcall to
    1097             :       // sincos. We want to issue a libcall to __sincos_stret.
    1098         136 :       setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
    1099         136 :       setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
    1100             :     }
    1101             :   }
    1102             : 
    1103             :   // FP-ARMv8 implements a lot of rounding-like FP operations.
    1104        4487 :   if (Subtarget->hasFPARMv8()) {
    1105         598 :     setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
    1106         598 :     setOperationAction(ISD::FCEIL, MVT::f32, Legal);
    1107         598 :     setOperationAction(ISD::FROUND, MVT::f32, Legal);
    1108         598 :     setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
    1109         598 :     setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
    1110         598 :     setOperationAction(ISD::FRINT, MVT::f32, Legal);
    1111         598 :     setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
    1112         598 :     setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
    1113         598 :     setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
    1114         598 :     setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
    1115         598 :     setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
    1116         598 :     setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
    1117             : 
    1118         299 :     if (!Subtarget->isFPOnlySP()) {
    1119         548 :       setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
    1120         548 :       setOperationAction(ISD::FCEIL, MVT::f64, Legal);
    1121         548 :       setOperationAction(ISD::FROUND, MVT::f64, Legal);
    1122         548 :       setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
    1123         548 :       setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
    1124         548 :       setOperationAction(ISD::FRINT, MVT::f64, Legal);
    1125         548 :       setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
    1126         548 :       setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
    1127             :     }
    1128             :   }
    1129             : 
    1130        4487 :   if (Subtarget->hasNEON()) {
    1131             :     // vmin and vmax aren't available in a scalar form, so we use
    1132             :     // a NEON instruction with an undef lane instead.
    1133        4720 :     setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
    1134        4720 :     setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
    1135        4720 :     setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
    1136        4720 :     setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
    1137        4720 :     setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
    1138        4720 :     setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
    1139             :   }
    1140             : 
    1141             :   // We have target-specific dag combine patterns for the following nodes:
    1142             :   // ARMISD::VMOVRRD  - No need to call setTargetDAGCombine
    1143        8974 :   setTargetDAGCombine(ISD::ADD);
    1144        8974 :   setTargetDAGCombine(ISD::SUB);
    1145        8974 :   setTargetDAGCombine(ISD::MUL);
    1146        8974 :   setTargetDAGCombine(ISD::AND);
    1147        8974 :   setTargetDAGCombine(ISD::OR);
    1148        8974 :   setTargetDAGCombine(ISD::XOR);
    1149             : 
    1150        4487 :   if (Subtarget->hasV6Ops())
    1151        3234 :     setTargetDAGCombine(ISD::SRL);
    1152             : 
    1153        8974 :   setStackPointerRegisterToSaveRestore(ARM::SP);
    1154             : 
    1155        8523 :   if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
    1156        4036 :       !Subtarget->hasVFP2())
    1157        1801 :     setSchedulingPreference(Sched::RegPressure);
    1158             :   else
    1159        2686 :     setSchedulingPreference(Sched::Hybrid);
    1160             : 
    1161             :   //// temporary - rewrite interface to use type
    1162        4487 :   MaxStoresPerMemset = 8;
    1163        4487 :   MaxStoresPerMemsetOptSize = 4;
    1164        4487 :   MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
    1165        4487 :   MaxStoresPerMemcpyOptSize = 2;
    1166        4487 :   MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
    1167        4487 :   MaxStoresPerMemmoveOptSize = 2;
    1168             : 
    1169             :   // On ARM arguments smaller than 4 bytes are extended, so all arguments
    1170             :   // are at least 4 bytes aligned.
    1171        8974 :   setMinStackArgumentAlignment(4);
    1172             : 
    1173             :   // Prefer likely predicted branches to selects on out-of-order cores.
    1174        8974 :   PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
    1175             : 
    1176        8974 :   setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
    1177        4487 : }
    1178             : 
    1179        3032 : bool ARMTargetLowering::useSoftFloat() const {
    1180        3032 :   return Subtarget->useSoftFloat();
    1181             : }
    1182             : 
    1183             : // FIXME: It might make sense to define the representative register class as the
    1184             : // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
    1185             : // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
    1186             : // SPR's representative would be DPR_VFP2. This should work well if register
    1187             : // pressure tracking were modified such that a register use would increment the
    1188             : // pressure of the register class's representative and all of it's super
    1189             : // classes' representatives transitively. We have not implemented this because
    1190             : // of the difficulty prior to coalescing of modeling operand register classes
    1191             : // due to the common occurrence of cross class copies and subregister insertions
    1192             : // and extractions.
    1193             : std::pair<const TargetRegisterClass *, uint8_t>
    1194      502544 : ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
    1195             :                                            MVT VT) const {
    1196      502544 :   const TargetRegisterClass *RRC = nullptr;
    1197      502544 :   uint8_t Cost = 1;
    1198      502544 :   switch (VT.SimpleTy) {
    1199      435239 :   default:
    1200      435239 :     return TargetLowering::findRepresentativeClass(TRI, VT);
    1201             :   // Use DPR as representative register class for all floating point
    1202             :   // and vector types. Since there are 32 SPR registers and 32 DPR registers so
    1203             :   // the cost is 1 for both f32 and f64.
    1204       31409 :   case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
    1205             :   case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
    1206       31409 :     RRC = &ARM::DPRRegClass;
    1207             :     // When NEON is used for SP, only half of the register file is available
    1208             :     // because operations that define both SP and DP results will be constrained
    1209             :     // to the VFP2 class (D0-D15). We currently model this constraint prior to
    1210             :     // coalescing by double-counting the SP regs. See the FIXME above.
    1211       61005 :     if (Subtarget->useNEONForSinglePrecisionFP())
    1212             :       Cost = 2;
    1213             :     break;
    1214             :   case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
    1215             :   case MVT::v4f32: case MVT::v2f64:
    1216             :     RRC = &ARM::DPRRegClass;
    1217             :     Cost = 2;
    1218             :     break;
    1219        4487 :   case MVT::v4i64:
    1220        4487 :     RRC = &ARM::DPRRegClass;
    1221        4487 :     Cost = 4;
    1222        4487 :     break;
    1223        4487 :   case MVT::v8i64:
    1224        4487 :     RRC = &ARM::DPRRegClass;
    1225        4487 :     Cost = 8;
    1226        4487 :     break;
    1227             :   }
    1228       67305 :   return std::make_pair(RRC, Cost);
    1229             : }
    1230             : 
    1231           0 : const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
    1232           0 :   switch ((ARMISD::NodeType)Opcode) {
    1233             :   case ARMISD::FIRST_NUMBER:  break;
    1234             :   case ARMISD::Wrapper:       return "ARMISD::Wrapper";
    1235           0 :   case ARMISD::WrapperPIC:    return "ARMISD::WrapperPIC";
    1236           0 :   case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
    1237           0 :   case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
    1238           0 :   case ARMISD::CALL:          return "ARMISD::CALL";
    1239           0 :   case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
    1240           0 :   case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
    1241           0 :   case ARMISD::BRCOND:        return "ARMISD::BRCOND";
    1242           0 :   case ARMISD::BR_JT:         return "ARMISD::BR_JT";
    1243           0 :   case ARMISD::BR2_JT:        return "ARMISD::BR2_JT";
    1244           0 :   case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
    1245           0 :   case ARMISD::INTRET_FLAG:   return "ARMISD::INTRET_FLAG";
    1246           0 :   case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
    1247           0 :   case ARMISD::CMP:           return "ARMISD::CMP";
    1248           0 :   case ARMISD::CMN:           return "ARMISD::CMN";
    1249           0 :   case ARMISD::CMPZ:          return "ARMISD::CMPZ";
    1250           0 :   case ARMISD::CMPFP:         return "ARMISD::CMPFP";
    1251           0 :   case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
    1252           0 :   case ARMISD::BCC_i64:       return "ARMISD::BCC_i64";
    1253           0 :   case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
    1254             : 
    1255           0 :   case ARMISD::CMOV:          return "ARMISD::CMOV";
    1256             : 
    1257           0 :   case ARMISD::SSAT:          return "ARMISD::SSAT";
    1258             : 
    1259           0 :   case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
    1260           0 :   case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
    1261           0 :   case ARMISD::RRX:           return "ARMISD::RRX";
    1262             : 
    1263           0 :   case ARMISD::ADDC:          return "ARMISD::ADDC";
    1264           0 :   case ARMISD::ADDE:          return "ARMISD::ADDE";
    1265           0 :   case ARMISD::SUBC:          return "ARMISD::SUBC";
    1266           0 :   case ARMISD::SUBE:          return "ARMISD::SUBE";
    1267             : 
    1268           0 :   case ARMISD::VMOVRRD:       return "ARMISD::VMOVRRD";
    1269           0 :   case ARMISD::VMOVDRR:       return "ARMISD::VMOVDRR";
    1270             : 
    1271           0 :   case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
    1272           0 :   case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
    1273           0 :   case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
    1274             : 
    1275           0 :   case ARMISD::TC_RETURN:     return "ARMISD::TC_RETURN";
    1276             : 
    1277           0 :   case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
    1278             : 
    1279           0 :   case ARMISD::DYN_ALLOC:     return "ARMISD::DYN_ALLOC";
    1280             : 
    1281           0 :   case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
    1282             : 
    1283           0 :   case ARMISD::PRELOAD:       return "ARMISD::PRELOAD";
    1284             : 
    1285           0 :   case ARMISD::WIN__CHKSTK:   return "ARMISD::WIN__CHKSTK";
    1286           0 :   case ARMISD::WIN__DBZCHK:   return "ARMISD::WIN__DBZCHK";
    1287             : 
    1288           0 :   case ARMISD::VCEQ:          return "ARMISD::VCEQ";
    1289           0 :   case ARMISD::VCEQZ:         return "ARMISD::VCEQZ";
    1290           0 :   case ARMISD::VCGE:          return "ARMISD::VCGE";
    1291           0 :   case ARMISD::VCGEZ:         return "ARMISD::VCGEZ";
    1292           0 :   case ARMISD::VCLEZ:         return "ARMISD::VCLEZ";
    1293           0 :   case ARMISD::VCGEU:         return "ARMISD::VCGEU";
    1294           0 :   case ARMISD::VCGT:          return "ARMISD::VCGT";
    1295           0 :   case ARMISD::VCGTZ:         return "ARMISD::VCGTZ";
    1296           0 :   case ARMISD::VCLTZ:         return "ARMISD::VCLTZ";
    1297           0 :   case ARMISD::VCGTU:         return "ARMISD::VCGTU";
    1298           0 :   case ARMISD::VTST:          return "ARMISD::VTST";
    1299             : 
    1300           0 :   case ARMISD::VSHL:          return "ARMISD::VSHL";
    1301           0 :   case ARMISD::VSHRs:         return "ARMISD::VSHRs";
    1302           0 :   case ARMISD::VSHRu:         return "ARMISD::VSHRu";
    1303           0 :   case ARMISD::VRSHRs:        return "ARMISD::VRSHRs";
    1304           0 :   case ARMISD::VRSHRu:        return "ARMISD::VRSHRu";
    1305           0 :   case ARMISD::VRSHRN:        return "ARMISD::VRSHRN";
    1306           0 :   case ARMISD::VQSHLs:        return "ARMISD::VQSHLs";
    1307           0 :   case ARMISD::VQSHLu:        return "ARMISD::VQSHLu";
    1308           0 :   case ARMISD::VQSHLsu:       return "ARMISD::VQSHLsu";
    1309           0 :   case ARMISD::VQSHRNs:       return "ARMISD::VQSHRNs";
    1310           0 :   case ARMISD::VQSHRNu:       return "ARMISD::VQSHRNu";
    1311           0 :   case ARMISD::VQSHRNsu:      return "ARMISD::VQSHRNsu";
    1312           0 :   case ARMISD::VQRSHRNs:      return "ARMISD::VQRSHRNs";
    1313           0 :   case ARMISD::VQRSHRNu:      return "ARMISD::VQRSHRNu";
    1314           0 :   case ARMISD::VQRSHRNsu:     return "ARMISD::VQRSHRNsu";
    1315           0 :   case ARMISD::VSLI:          return "ARMISD::VSLI";
    1316           0 :   case ARMISD::VSRI:          return "ARMISD::VSRI";
    1317           0 :   case ARMISD::VGETLANEu:     return "ARMISD::VGETLANEu";
    1318           0 :   case ARMISD::VGETLANEs:     return "ARMISD::VGETLANEs";
    1319           0 :   case ARMISD::VMOVIMM:       return "ARMISD::VMOVIMM";
    1320           0 :   case ARMISD::VMVNIMM:       return "ARMISD::VMVNIMM";
    1321           0 :   case ARMISD::VMOVFPIMM:     return "ARMISD::VMOVFPIMM";
    1322           0 :   case ARMISD::VDUP:          return "ARMISD::VDUP";
    1323           0 :   case ARMISD::VDUPLANE:      return "ARMISD::VDUPLANE";
    1324           0 :   case ARMISD::VEXT:          return "ARMISD::VEXT";
    1325           0 :   case ARMISD::VREV64:        return "ARMISD::VREV64";
    1326           0 :   case ARMISD::VREV32:        return "ARMISD::VREV32";
    1327           0 :   case ARMISD::VREV16:        return "ARMISD::VREV16";
    1328           0 :   case ARMISD::VZIP:          return "ARMISD::VZIP";
    1329           0 :   case ARMISD::VUZP:          return "ARMISD::VUZP";
    1330           0 :   case ARMISD::VTRN:          return "ARMISD::VTRN";
    1331           0 :   case ARMISD::VTBL1:         return "ARMISD::VTBL1";
    1332           0 :   case ARMISD::VTBL2:         return "ARMISD::VTBL2";
    1333           0 :   case ARMISD::VMULLs:        return "ARMISD::VMULLs";
    1334           0 :   case ARMISD::VMULLu:        return "ARMISD::VMULLu";
    1335           0 :   case ARMISD::UMAAL:         return "ARMISD::UMAAL";
    1336           0 :   case ARMISD::UMLAL:         return "ARMISD::UMLAL";
    1337           0 :   case ARMISD::SMLAL:         return "ARMISD::SMLAL";
    1338           0 :   case ARMISD::SMLALBB:       return "ARMISD::SMLALBB";
    1339           0 :   case ARMISD::SMLALBT:       return "ARMISD::SMLALBT";
    1340           0 :   case ARMISD::SMLALTB:       return "ARMISD::SMLALTB";
    1341           0 :   case ARMISD::SMLALTT:       return "ARMISD::SMLALTT";
    1342           0 :   case ARMISD::SMULWB:        return "ARMISD::SMULWB";
    1343           0 :   case ARMISD::SMULWT:        return "ARMISD::SMULWT";
    1344           0 :   case ARMISD::SMLALD:        return "ARMISD::SMLALD";
    1345           0 :   case ARMISD::SMLALDX:       return "ARMISD::SMLALDX";
    1346           0 :   case ARMISD::SMLSLD:        return "ARMISD::SMLSLD";
    1347           0 :   case ARMISD::SMLSLDX:       return "ARMISD::SMLSLDX";
    1348           0 :   case ARMISD::BUILD_VECTOR:  return "ARMISD::BUILD_VECTOR";
    1349           0 :   case ARMISD::BFI:           return "ARMISD::BFI";
    1350           0 :   case ARMISD::VORRIMM:       return "ARMISD::VORRIMM";
    1351           0 :   case ARMISD::VBICIMM:       return "ARMISD::VBICIMM";
    1352           0 :   case ARMISD::VBSL:          return "ARMISD::VBSL";
    1353           0 :   case ARMISD::MEMCPY:        return "ARMISD::MEMCPY";
    1354           0 :   case ARMISD::VLD1DUP:       return "ARMISD::VLD1DUP";
    1355           0 :   case ARMISD::VLD2DUP:       return "ARMISD::VLD2DUP";
    1356           0 :   case ARMISD::VLD3DUP:       return "ARMISD::VLD3DUP";
    1357           0 :   case ARMISD::VLD4DUP:       return "ARMISD::VLD4DUP";
    1358           0 :   case ARMISD::VLD1_UPD:      return "ARMISD::VLD1_UPD";
    1359           0 :   case ARMISD::VLD2_UPD:      return "ARMISD::VLD2_UPD";
    1360           0 :   case ARMISD::VLD3_UPD:      return "ARMISD::VLD3_UPD";
    1361           0 :   case ARMISD::VLD4_UPD:      return "ARMISD::VLD4_UPD";
    1362           0 :   case ARMISD::VLD2LN_UPD:    return "ARMISD::VLD2LN_UPD";
    1363           0 :   case ARMISD::VLD3LN_UPD:    return "ARMISD::VLD3LN_UPD";
    1364           0 :   case ARMISD::VLD4LN_UPD:    return "ARMISD::VLD4LN_UPD";
    1365           0 :   case ARMISD::VLD1DUP_UPD:   return "ARMISD::VLD1DUP_UPD";
    1366           0 :   case ARMISD::VLD2DUP_UPD:   return "ARMISD::VLD2DUP_UPD";
    1367           0 :   case ARMISD::VLD3DUP_UPD:   return "ARMISD::VLD3DUP_UPD";
    1368           0 :   case ARMISD::VLD4DUP_UPD:   return "ARMISD::VLD4DUP_UPD";
    1369           0 :   case ARMISD::VST1_UPD:      return "ARMISD::VST1_UPD";
    1370           0 :   case ARMISD::VST2_UPD:      return "ARMISD::VST2_UPD";
    1371           0 :   case ARMISD::VST3_UPD:      return "ARMISD::VST3_UPD";
    1372           0 :   case ARMISD::VST4_UPD:      return "ARMISD::VST4_UPD";
    1373           0 :   case ARMISD::VST2LN_UPD:    return "ARMISD::VST2LN_UPD";
    1374           0 :   case ARMISD::VST3LN_UPD:    return "ARMISD::VST3LN_UPD";
    1375           0 :   case ARMISD::VST4LN_UPD:    return "ARMISD::VST4LN_UPD";
    1376             :   }
    1377           0 :   return nullptr;
    1378             : }
    1379             : 
    1380        6034 : EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
    1381             :                                           EVT VT) const {
    1382        6034 :   if (!VT.isVector())
    1383       11738 :     return getPointerTy(DL);
    1384         165 :   return VT.changeVectorElementTypeToInteger();
    1385             : }
    1386             : 
    1387             : /// getRegClassFor - Return the register class that should be used for the
    1388             : /// specified value type.
    1389       69927 : const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
    1390             :   // Map v4i64 to QQ registers but do not make the type legal. Similarly map
    1391             :   // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
    1392             :   // load / store 4 to 8 consecutive D registers.
    1393       69927 :   if (Subtarget->hasNEON()) {
    1394       51290 :     if (VT == MVT::v4i64)
    1395             :       return &ARM::QQPRRegClass;
    1396       51290 :     if (VT == MVT::v8i64)
    1397             :       return &ARM::QQQQPRRegClass;
    1398             :   }
    1399      139814 :   return TargetLowering::getRegClassFor(VT);
    1400             : }
    1401             : 
    1402             : // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
    1403             : // source/dest is aligned and the copy size is large enough. We therefore want
    1404             : // to align such objects passed to memory intrinsics.
    1405        9914 : bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
    1406             :                                                unsigned &PrefAlign) const {
    1407       19828 :   if (!isa<MemIntrinsic>(CI))
    1408             :     return false;
    1409         631 :   MinSize = 8;
    1410             :   // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
    1411             :   // cycle faster than 4-byte aligned LDM.
    1412         631 :   PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
    1413         631 :   return true;
    1414             : }
    1415             : 
    1416             : // Create a fast isel object.
    1417             : FastISel *
    1418        1131 : ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
    1419             :                                   const TargetLibraryInfo *libInfo) const {
    1420        1131 :   return ARM::createFastISel(funcInfo, libInfo);
    1421             : }
    1422             : 
    1423      120130 : Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
    1424      240260 :   unsigned NumVals = N->getNumValues();
    1425      120130 :   if (!NumVals)
    1426             :     return Sched::RegPressure;
    1427             : 
    1428      440608 :   for (unsigned i = 0; i != NumVals; ++i) {
    1429      364916 :     EVT VT = N->getValueType(i);
    1430      441007 :     if (VT == MVT::Glue || VT == MVT::Other)
    1431       94619 :       continue;
    1432      158103 :     if (VT.isFloatingPoint() || VT.isVector())
    1433       22219 :       return Sched::ILP;
    1434             :   }
    1435             : 
    1436       97911 :   if (!N->isMachineOpcode())
    1437             :     return Sched::RegPressure;
    1438             : 
    1439             :   // Load are scheduled for latency even if there instruction itinerary
    1440             :   // is not available.
    1441       62513 :   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    1442      187539 :   const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
    1443             : 
    1444       62513 :   if (MCID.getNumDefs() == 0)
    1445             :     return Sched::RegPressure;
    1446       55204 :   if (!Itins->isEmpty() &&
    1447       53424 :       Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
    1448             :     return Sched::ILP;
    1449             : 
    1450             :   return Sched::RegPressure;
    1451             : }
    1452             : 
    1453             : //===----------------------------------------------------------------------===//
    1454             : // Lowering Code
    1455             : //===----------------------------------------------------------------------===//
    1456             : 
    1457        1310 : static bool isSRL16(const SDValue &Op) {
    1458        2620 :   if (Op.getOpcode() != ISD::SRL)
    1459             :     return false;
    1460         143 :   if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
    1461          47 :     return Const->getZExtValue() == 16;
    1462             :   return false;
    1463             : }
    1464             : 
    1465         228 : static bool isSRA16(const SDValue &Op) {
    1466         456 :   if (Op.getOpcode() != ISD::SRA)
    1467             :     return false;
    1468         423 :   if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
    1469         141 :     return Const->getZExtValue() == 16;
    1470             :   return false;
    1471             : }
    1472             : 
    1473         108 : static bool isSHL16(const SDValue &Op) {
    1474         216 :   if (Op.getOpcode() != ISD::SHL)
    1475             :     return false;
    1476          87 :   if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
    1477          29 :     return Const->getZExtValue() == 16;
    1478             :   return false;
    1479             : }
    1480             : 
    1481             : // Check for a signed 16-bit value. We special case SRA because it makes it
    1482             : // more simple when also looking for SRAs that aren't sign extending a
    1483             : // smaller value. Without the check, we'd need to take extra care with
    1484             : // checking order for some operations.
    1485         167 : static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
    1486         167 :   if (isSRA16(Op))
    1487         160 :     return isSHL16(Op.getOperand(0));
    1488          87 :   return DAG.ComputeNumSignBits(Op) == 17;
    1489             : }
    1490             : 
    1491             : /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
    1492        2648 : static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
    1493        2648 :   switch (CC) {
    1494           0 :   default: llvm_unreachable("Unknown condition code!");
    1495             :   case ISD::SETNE:  return ARMCC::NE;
    1496         724 :   case ISD::SETEQ:  return ARMCC::EQ;
    1497         130 :   case ISD::SETGT:  return ARMCC::GT;
    1498         103 :   case ISD::SETGE:  return ARMCC::GE;
    1499         188 :   case ISD::SETLT:  return ARMCC::LT;
    1500          36 :   case ISD::SETLE:  return ARMCC::LE;
    1501          85 :   case ISD::SETUGT: return ARMCC::HI;
    1502          24 :   case ISD::SETUGE: return ARMCC::HS;
    1503          55 :   case ISD::SETULT: return ARMCC::LO;
    1504          40 :   case ISD::SETULE: return ARMCC::LS;
    1505             :   }
    1506             : }
    1507             : 
    1508             : /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
    1509         297 : static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
    1510             :                         ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
    1511         297 :   CondCode2 = ARMCC::AL;
    1512         297 :   InvalidOnQNaN = true;
    1513         297 :   switch (CC) {
    1514           0 :   default: llvm_unreachable("Unknown FP condition!");
    1515          32 :   case ISD::SETEQ:
    1516             :   case ISD::SETOEQ:
    1517          32 :     CondCode = ARMCC::EQ;
    1518          32 :     InvalidOnQNaN = false;
    1519          32 :     break;
    1520          32 :   case ISD::SETGT:
    1521          32 :   case ISD::SETOGT: CondCode = ARMCC::GT; break;
    1522          26 :   case ISD::SETGE:
    1523          26 :   case ISD::SETOGE: CondCode = ARMCC::GE; break;
    1524          51 :   case ISD::SETOLT: CondCode = ARMCC::MI; break;
    1525          22 :   case ISD::SETOLE: CondCode = ARMCC::LS; break;
    1526           7 :   case ISD::SETONE:
    1527           7 :     CondCode = ARMCC::MI;
    1528           7 :     CondCode2 = ARMCC::GT;
    1529           7 :     InvalidOnQNaN = false;
    1530           7 :     break;
    1531           7 :   case ISD::SETO:   CondCode = ARMCC::VC; break;
    1532          17 :   case ISD::SETUO:  CondCode = ARMCC::VS; break;
    1533           8 :   case ISD::SETUEQ:
    1534           8 :     CondCode = ARMCC::EQ;
    1535           8 :     CondCode2 = ARMCC::VS;
    1536           8 :     InvalidOnQNaN = false;
    1537           8 :     break;
    1538          10 :   case ISD::SETUGT: CondCode = ARMCC::HI; break;
    1539          20 :   case ISD::SETUGE: CondCode = ARMCC::PL; break;
    1540          11 :   case ISD::SETLT:
    1541          11 :   case ISD::SETULT: CondCode = ARMCC::LT; break;
    1542          26 :   case ISD::SETLE:
    1543          26 :   case ISD::SETULE: CondCode = ARMCC::LE; break;
    1544          28 :   case ISD::SETNE:
    1545             :   case ISD::SETUNE:
    1546          28 :     CondCode = ARMCC::NE;
    1547          28 :     InvalidOnQNaN = false;
    1548          28 :     break;
    1549             :   }
    1550         297 : }
    1551             : 
    1552             : //===----------------------------------------------------------------------===//
    1553             : //                      Calling Convention Implementation
    1554             : //===----------------------------------------------------------------------===//
    1555             : 
    1556             : #include "ARMGenCallingConv.inc"
    1557             : 
    1558             : /// getEffectiveCallingConv - Get the effective calling convention, taking into
    1559             : /// account presence of floating point hardware and calling convention
    1560             : /// limitations, such as support for variadic functions.
    1561             : CallingConv::ID
    1562       85640 : ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
    1563             :                                            bool isVarArg) const {
    1564       85640 :   switch (CC) {
    1565           0 :   default:
    1566           0 :     report_fatal_error("Unsupported calling convention");
    1567             :   case CallingConv::ARM_AAPCS:
    1568             :   case CallingConv::ARM_APCS:
    1569             :   case CallingConv::GHC:
    1570             :     return CC;
    1571           0 :   case CallingConv::PreserveMost:
    1572           0 :     return CallingConv::PreserveMost;
    1573        4896 :   case CallingConv::ARM_AAPCS_VFP:
    1574             :   case CallingConv::Swift:
    1575        4896 :     return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
    1576       70714 :   case CallingConv::C:
    1577       70714 :     if (!Subtarget->isAAPCS_ABI())
    1578             :       return CallingConv::ARM_APCS;
    1579      110017 :     else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
    1580       87791 :              getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
    1581             :              !isVarArg)
    1582             :       return CallingConv::ARM_AAPCS_VFP;
    1583             :     else
    1584             :       return CallingConv::ARM_AAPCS;
    1585         833 :   case CallingConv::Fast:
    1586             :   case CallingConv::CXX_FAST_TLS:
    1587         833 :     if (!Subtarget->isAAPCS_ABI()) {
    1588         957 :       if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
    1589             :         return CallingConv::Fast;
    1590             :       return CallingConv::ARM_APCS;
    1591         433 :     } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
    1592             :       return CallingConv::ARM_AAPCS_VFP;
    1593             :     else
    1594             :       return CallingConv::ARM_AAPCS;
    1595             :   }
    1596             : }
    1597             : 
    1598       18564 : CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
    1599             :                                                  bool isVarArg) const {
    1600       18564 :   return CCAssignFnForNode(CC, false, isVarArg);
    1601             : }
    1602             : 
    1603       37582 : CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
    1604             :                                                    bool isVarArg) const {
    1605       37582 :   return CCAssignFnForNode(CC, true, isVarArg);
    1606             : }
    1607             : 
    1608             : /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
    1609             : /// CallingConvention.
    1610       56146 : CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
    1611             :                                                  bool Return,
    1612             :                                                  bool isVarArg) const {
    1613       56146 :   switch (getEffectiveCallingConv(CC, isVarArg)) {
    1614           0 :   default:
    1615           0 :     report_fatal_error("Unsupported calling convention");
    1616       13282 :   case CallingConv::ARM_APCS:
    1617       13282 :     return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
    1618       33688 :   case CallingConv::ARM_AAPCS:
    1619       33688 :     return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
    1620        8891 :   case CallingConv::ARM_AAPCS_VFP:
    1621        8891 :     return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
    1622         273 :   case CallingConv::Fast:
    1623         273 :     return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
    1624          12 :   case CallingConv::GHC:
    1625          12 :     return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
    1626           0 :   case CallingConv::PreserveMost:
    1627           0 :     return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
    1628             :   }
    1629             : }
    1630             : 
    1631             : /// LowerCallResult - Lower the result values of a call into the
    1632             : /// appropriate copies out of appropriate physical registers.
    1633        6120 : SDValue ARMTargetLowering::LowerCallResult(
    1634             :     SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
    1635             :     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
    1636             :     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
    1637             :     SDValue ThisVal) const {
    1638             : 
    1639             :   // Assign locations to each value returned by this call.
    1640       12240 :   SmallVector<CCValAssign, 16> RVLocs;
    1641             :   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
    1642       12240 :                  *DAG.getContext());
    1643        6120 :   CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
    1644             : 
    1645             :   // Copy all of the result registers out of their specified physreg.
    1646       21332 :   for (unsigned i = 0; i != RVLocs.size(); ++i) {
    1647        9092 :     CCValAssign VA = RVLocs[i];
    1648             : 
    1649             :     // Pass 'this' value directly from the argument to return value, to avoid
    1650             :     // reg unit interference
    1651        4596 :     if (i == 0 && isThisReturn) {
    1652             :       assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
    1653             :              "unexpected return calling convention register assignment");
    1654          50 :       InVals.push_back(ThisVal);
    1655          50 :       continue;
    1656             :     }
    1657             : 
    1658        4496 :     SDValue Val;
    1659        4496 :     if (VA.needsCustom()) {
    1660             :       // Handle f64 or half of a v2f64.
    1661             :       SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
    1662         192 :                                       InFlag);
    1663         384 :       Chain = Lo.getValue(1);
    1664         384 :       InFlag = Lo.getValue(2);
    1665         384 :       VA = RVLocs[++i]; // skip ahead to next loc
    1666             :       SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
    1667         192 :                                       InFlag);
    1668         384 :       Chain = Hi.getValue(1);
    1669         384 :       InFlag = Hi.getValue(2);
    1670         192 :       if (!Subtarget->isLittle())
    1671             :         std::swap (Lo, Hi);
    1672         384 :       Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
    1673             : 
    1674         192 :       if (VA.getLocVT() == MVT::v2f64) {
    1675          43 :         SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
    1676          43 :         Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
    1677         129 :                           DAG.getConstant(0, dl, MVT::i32));
    1678             : 
    1679          86 :         VA = RVLocs[++i]; // skip ahead to next loc
    1680          43 :         Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
    1681          86 :         Chain = Lo.getValue(1);
    1682          86 :         InFlag = Lo.getValue(2);
    1683          86 :         VA = RVLocs[++i]; // skip ahead to next loc
    1684          43 :         Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
    1685          86 :         Chain = Hi.getValue(1);
    1686          86 :         InFlag = Hi.getValue(2);
    1687          43 :         if (!Subtarget->isLittle())
    1688             :           std::swap (Lo, Hi);
    1689          86 :         Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
    1690          43 :         Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
    1691         129 :                           DAG.getConstant(1, dl, MVT::i32));
    1692             :       }
    1693             :     } else {
    1694        4304 :       Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
    1695       12912 :                                InFlag);
    1696        8608 :       Chain = Val.getValue(1);
    1697        8608 :       InFlag = Val.getValue(2);
    1698             :     }
    1699             : 
    1700        4496 :     switch (VA.getLocInfo()) {
    1701           0 :     default: llvm_unreachable("Unknown loc info!");
    1702             :     case CCValAssign::Full: break;
    1703         420 :     case CCValAssign::BCvt:
    1704         840 :       Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
    1705         420 :       break;
    1706             :     }
    1707             : 
    1708        4496 :     InVals.push_back(Val);
    1709             :   }
    1710             : 
    1711       12240 :   return Chain;
    1712             : }
    1713             : 
    1714             : /// LowerMemOpCallTo - Store the argument to the stack.
    1715         871 : SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
    1716             :                                             SDValue Arg, const SDLoc &dl,
    1717             :                                             SelectionDAG &DAG,
    1718             :                                             const CCValAssign &VA,
    1719             :                                             ISD::ArgFlagsTy Flags) const {
    1720         871 :   unsigned LocMemOffset = VA.getLocMemOffset();
    1721         871 :   SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
    1722         871 :   PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
    1723        4355 :                        StackPtr, PtrOff);
    1724             :   return DAG.getStore(
    1725             :       Chain, dl, Arg, PtrOff,
    1726         871 :       MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
    1727             : }
    1728             : 
    1729         429 : void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
    1730             :                                          SDValue Chain, SDValue &Arg,
    1731             :                                          RegsToPassVector &RegsToPass,
    1732             :                                          CCValAssign &VA, CCValAssign &NextVA,
    1733             :                                          SDValue &StackPtr,
    1734             :                                          SmallVectorImpl<SDValue> &MemOpChains,
    1735             :                                          ISD::ArgFlagsTy Flags) const {
    1736             : 
    1737             :   SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
    1738         858 :                               DAG.getVTList(MVT::i32, MVT::i32), Arg);
    1739         429 :   unsigned id = Subtarget->isLittle() ? 0 : 1;
    1740        1287 :   RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
    1741             : 
    1742         429 :   if (NextVA.isRegLoc())
    1743        1266 :     RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
    1744             :   else {
    1745             :     assert(NextVA.isMemLoc());
    1746           7 :     if (!StackPtr.getNode())
    1747           0 :       StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
    1748           0 :                                     getPointerTy(DAG.getDataLayout()));
    1749             : 
    1750          14 :     MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
    1751             :                                            dl, DAG, NextVA,
    1752          14 :                                            Flags));
    1753             :   }
    1754         429 : }
    1755             : 
    1756             : /// LowerCall - Lowering a call into a callseq_start <-
    1757             : /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
    1758             : /// nodes.
    1759             : SDValue
    1760        6625 : ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
    1761             :                              SmallVectorImpl<SDValue> &InVals) const {
    1762        6625 :   SelectionDAG &DAG                     = CLI.DAG;
    1763        6625 :   SDLoc &dl                             = CLI.DL;
    1764        6625 :   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
    1765        6625 :   SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
    1766        6625 :   SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
    1767        6625 :   SDValue Chain                         = CLI.Chain;
    1768        6625 :   SDValue Callee                        = CLI.Callee;
    1769        6625 :   bool &isTailCall                      = CLI.IsTailCall;
    1770        6625 :   CallingConv::ID CallConv              = CLI.CallConv;
    1771        6625 :   bool doesNotRet                       = CLI.DoesNotReturn;
    1772        6625 :   bool isVarArg                         = CLI.IsVarArg;
    1773             : 
    1774        6625 :   MachineFunction &MF = DAG.getMachineFunction();
    1775       17981 :   bool isStructRet    = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
    1776        6625 :   bool isThisReturn   = false;
    1777        6625 :   bool isSibCall      = false;
    1778       13250 :   auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
    1779             : 
    1780             :   // Disable tail calls if they're not supported.
    1781        6625 :   if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
    1782        2147 :     isTailCall = false;
    1783             : 
    1784        6625 :   if (isTailCall) {
    1785             :     // Check if it's really possible to do a tail call.
    1786         584 :     isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
    1787         584 :                     isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
    1788             :                                                    Outs, OutVals, Ins, DAG);
    1789         663 :     if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
    1790           0 :       report_fatal_error("failed to perform tail call elimination on a call "
    1791             :                          "site marked musttail");
    1792             :     // We don't support GuaranteedTailCallOpt for ARM, only automatically
    1793             :     // detected sibcalls.
    1794         584 :     if (isTailCall) {
    1795         505 :       ++NumTailCalls;
    1796         505 :       isSibCall = true;
    1797             :     }
    1798             :   }
    1799             : 
    1800             :   // Analyze operands of the call, assigning locations to each operand.
    1801       13250 :   SmallVector<CCValAssign, 16> ArgLocs;
    1802             :   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
    1803       13250 :                  *DAG.getContext());
    1804        6625 :   CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
    1805             : 
    1806             :   // Get a count of how many bytes are to be pushed on the stack.
    1807        6625 :   unsigned NumBytes = CCInfo.getNextStackOffset();
    1808             : 
    1809             :   // For tail calls, memory operands are available in our caller's stack.
    1810        6625 :   if (isSibCall)
    1811         505 :     NumBytes = 0;
    1812             : 
    1813             :   // Adjust the stack pointer for the new arguments...
    1814             :   // These operations are automatically eliminated by the prolog/epilog pass
    1815        6625 :   if (!isSibCall)
    1816        6120 :     Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
    1817             : 
    1818             :   SDValue StackPtr =
    1819       26500 :       DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
    1820             : 
    1821       13250 :   RegsToPassVector RegsToPass;
    1822       13250 :   SmallVector<SDValue, 8> MemOpChains;
    1823             : 
    1824             :   // Walk the register/memloc assignments, inserting copies/loads.  In the case
    1825             :   // of tail call optimization, arguments are handled later.
    1826       25552 :   for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
    1827       18927 :        i != e;
    1828             :        ++i, ++realArgIdx) {
    1829       24604 :     CCValAssign &VA = ArgLocs[i];
    1830       24604 :     SDValue Arg = OutVals[realArgIdx];
    1831       24604 :     ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
    1832       12302 :     bool isByVal = Flags.isByVal();
    1833             : 
    1834             :     // Promote the value if needed.
    1835       12302 :     switch (VA.getLocInfo()) {
    1836           0 :     default: llvm_unreachable("Unknown loc info!");
    1837             :     case CCValAssign::Full: break;
    1838           0 :     case CCValAssign::SExt:
    1839           0 :       Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
    1840           0 :       break;
    1841           0 :     case CCValAssign::ZExt:
    1842           0 :       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
    1843           0 :       break;
    1844           0 :     case CCValAssign::AExt:
    1845           0 :       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
    1846           0 :       break;
    1847        1087 :     case CCValAssign::BCvt:
    1848        2174 :       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
    1849        1087 :       break;
    1850             :     }
    1851             : 
    1852             :     // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
    1853       12302 :     if (VA.needsCustom()) {
    1854         382 :       if (VA.getLocVT() == MVT::v2f64) {
    1855             :         SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
    1856         144 :                                   DAG.getConstant(0, dl, MVT::i32));
    1857             :         SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
    1858         144 :                                   DAG.getConstant(1, dl, MVT::i32));
    1859             : 
    1860          96 :         PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
    1861          96 :                          VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
    1862             : 
    1863          96 :         VA = ArgLocs[++i]; // skip ahead to next loc
    1864          48 :         if (VA.isRegLoc()) {
    1865          94 :           PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
    1866          94 :                            VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
    1867             :         } else {
    1868             :           assert(VA.isMemLoc());
    1869             : 
    1870           1 :           MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
    1871             :                                                  dl, DAG, VA, Flags));
    1872             :         }
    1873             :       } else {
    1874         668 :         PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
    1875             :                          StackPtr, MemOpChains, Flags);
    1876             :       }
    1877       11920 :     } else if (VA.isRegLoc()) {
    1878       15892 :       if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
    1879         171 :           Outs[0].VT == MVT::i32) {
    1880             :         assert(VA.getLocVT() == MVT::i32 &&
    1881             :                "unexpected calling convention register assignment");
    1882             :         assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
    1883             :                "unexpected use of 'returned'");
    1884             :         isThisReturn = true;
    1885             :       }
    1886       21390 :       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
    1887        1225 :     } else if (isByVal) {
    1888             :       assert(VA.isMemLoc());
    1889         358 :       unsigned offset = 0;
    1890             : 
    1891             :       // True if this byval aggregate will be split between registers
    1892             :       // and memory.
    1893         358 :       unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
    1894         358 :       unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
    1895             : 
    1896         358 :       if (CurByValIdx < ByValArgsCount) {
    1897             : 
    1898             :         unsigned RegBegin, RegEnd;
    1899         349 :         CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
    1900             : 
    1901             :         EVT PtrVT =
    1902        1396 :             DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
    1903             :         unsigned int i, j;
    1904        1705 :         for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
    1905        1356 :           SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
    1906        1356 :           SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
    1907             :           SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
    1908             :                                      MachinePointerInfo(),
    1909        2712 :                                      DAG.InferPtrAlignment(AddArg));
    1910        2712 :           MemOpChains.push_back(Load.getValue(1));
    1911        2712 :           RegsToPass.push_back(std::make_pair(j, Load));
    1912             :         }
    1913             : 
    1914             :         // If parameter size outsides register area, "offset" value
    1915             :         // helps us to calculate stack slot for remained part properly.
    1916         349 :         offset = RegEnd - RegBegin;
    1917             : 
    1918         349 :         CCInfo.nextInRegsParam();
    1919             :       }
    1920             : 
    1921         358 :       if (Flags.getByValSize() > 4*offset) {
    1922        1062 :         auto PtrVT = getPointerTy(DAG.getDataLayout());
    1923         354 :         unsigned LocMemOffset = VA.getLocMemOffset();
    1924         354 :         SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
    1925         708 :         SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
    1926         354 :         SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
    1927         708 :         SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
    1928         354 :         SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
    1929         708 :                                            MVT::i32);
    1930         354 :         SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
    1931         708 :                                             MVT::i32);
    1932             : 
    1933         708 :         SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
    1934         354 :         SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
    1935         354 :         MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
    1936         708 :                                           Ops));
    1937             :       }
    1938         867 :     } else if (!isSibCall) {
    1939             :       assert(VA.isMemLoc());
    1940             : 
    1941         863 :       MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
    1942             :                                              dl, DAG, VA, Flags));
    1943             :     }
    1944             :   }
    1945             : 
    1946        6625 :   if (!MemOpChains.empty())
    1947        2028 :     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
    1948             : 
    1949             :   // Build a sequence of copy-to-reg nodes chained together with token chain
    1950             :   // and flag operands which copy the outgoing args into the appropriate regs.
    1951        6625 :   SDValue InFlag;
    1952             :   // Tail call byval lowering might overwrite argument registers so in case of
    1953             :   // tail call optimization the copies to registers are lowered later.
    1954        6625 :   if (!isTailCall)
    1955       24641 :     for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
    1956       37203 :       Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
    1957       37203 :                                RegsToPass[i].second, InFlag);
    1958       24802 :       InFlag = Chain.getValue(1);
    1959             :     }
    1960             : 
    1961             :   // For tail calls lower the arguments to the 'real' stack slot.
    1962        6625 :   if (isTailCall) {
    1963             :     // Force all the incoming stack arguments to be loaded from the stack
    1964             :     // before any new outgoing arguments are stored to the stack, because the
    1965             :     // outgoing stack slots may alias the incoming argument stack slots, and
    1966             :     // the alias isn't otherwise explicit. This is slightly more conservative
    1967             :     // than necessary, because it means that each store effectively depends
    1968             :     // on every argument instead of just those arguments it would clobber.
    1969             : 
    1970             :     // Do not flag preceding copytoreg stuff together with the following stuff.
    1971         505 :     InFlag = SDValue();
    1972        1511 :     for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
    1973        1503 :       Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
    1974        1503 :                                RegsToPass[i].second, InFlag);
    1975        1002 :       InFlag = Chain.getValue(1);
    1976             :     }
    1977         505 :     InFlag = SDValue();
    1978             :   }
    1979             : 
    1980             :   // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
    1981             :   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
    1982             :   // node so that legalize doesn't hack it.
    1983        6625 :   bool isDirect = false;
    1984             : 
    1985        6625 :   const TargetMachine &TM = getTargetMachine();
    1986        6625 :   const Module *Mod = MF.getFunction()->getParent();
    1987        6625 :   const GlobalValue *GV = nullptr;
    1988        4082 :   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
    1989        4082 :     GV = G->getGlobal();
    1990             :   bool isStub =
    1991        9491 :       !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
    1992             : 
    1993        6625 :   bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
    1994        6625 :   bool isLocalARMFunc = false;
    1995        6625 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    1996       19875 :   auto PtrVt = getPointerTy(DAG.getDataLayout());
    1997             : 
    1998        6625 :   if (Subtarget->genLongCalls()) {
    1999             :     assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&
    2000             :            "long-calls codegen is not position independent!");
    2001             :     // Handle a global address or an external symbol. If it's not one of
    2002             :     // those, the target's already in a register, so we don't need to do
    2003             :     // anything extra.
    2004           0 :     if (isa<GlobalAddressSDNode>(Callee)) {
    2005             :       // Create a constant pool entry for the callee address
    2006          14 :       unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    2007             :       ARMConstantPoolValue *CPV =
    2008           7 :         ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
    2009             : 
    2010             :       // Get the address of the callee into a register
    2011          14 :       SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
    2012          14 :       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    2013           7 :       Callee = DAG.getLoad(
    2014             :           PtrVt, dl, DAG.getEntryNode(), CPAddr,
    2015          28 :           MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2016           0 :     } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
    2017           0 :       const char *Sym = S->getSymbol();
    2018             : 
    2019             :       // Create a constant pool entry for the callee address
    2020           0 :       unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    2021             :       ARMConstantPoolValue *CPV =
    2022           0 :         ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
    2023           0 :                                       ARMPCLabelIndex, 0);
    2024             :       // Get the address of the callee into a register
    2025           0 :       SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
    2026           0 :       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    2027           0 :       Callee = DAG.getLoad(
    2028             :           PtrVt, dl, DAG.getEntryNode(), CPAddr,
    2029           0 :           MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2030             :     }
    2031        2543 :   } else if (isa<GlobalAddressSDNode>(Callee)) {
    2032             :     // If we're optimizing for minimum size and the function is called three or
    2033             :     // more times in this block, we can improve codesize by calling indirectly
    2034             :     // as BLXr has a 16-bit encoding.
    2035        4075 :     auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
    2036        8150 :     auto *BB = CLI.CS.getParent();
    2037             :     bool PreferIndirect =
    2038        6130 :         Subtarget->isThumb() && MF.getFunction()->optForMinSize() &&
    2039         545 :         count_if(GV->users(), [&BB](const User *U) {
    2040        1362 :           return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
    2041        4072 :         }) > 2;
    2042             : 
    2043             :     if (!PreferIndirect) {
    2044        4072 :       isDirect = true;
    2045        4072 :       bool isDef = GV->isStrongDefinitionForLinker();
    2046             : 
    2047             :       // ARM call to a local ARM function is predicable.
    2048        6022 :       isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
    2049             :       // tBX takes a register source operand.
    2050        4217 :       if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
    2051             :         assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
    2052          50 :         Callee = DAG.getNode(
    2053             :             ARMISD::WrapperPIC, dl, PtrVt,
    2054         200 :             DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
    2055          50 :         Callee = DAG.getLoad(
    2056             :             PtrVt, dl, DAG.getEntryNode(), Callee,
    2057             :             MachinePointerInfo::getGOT(DAG.getMachineFunction()),
    2058          50 :             /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
    2059         250 :                                      MachineMemOperand::MOInvariant);
    2060        8044 :       } else if (Subtarget->isTargetCOFF()) {
    2061             :         assert(Subtarget->isTargetWindows() &&
    2062             :                "Windows is the only supported COFF target");
    2063          32 :         unsigned TargetFlags = GV->hasDLLImportStorageClass()
    2064          32 :                                    ? ARMII::MO_DLLIMPORT
    2065          32 :                                    : ARMII::MO_NO_FLAG;
    2066          32 :         Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
    2067          64 :                                             TargetFlags);
    2068          32 :         if (GV->hasDLLImportStorageClass())
    2069           3 :           Callee =
    2070           6 :               DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
    2071             :                           DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
    2072          18 :                           MachinePointerInfo::getGOT(DAG.getMachineFunction()));
    2073             :       } else {
    2074        7980 :         Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
    2075             :       }
    2076             :     }
    2077        2459 :   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
    2078        2459 :     isDirect = true;
    2079             :     // tBX takes a register source operand.
    2080        2459 :     const char *Sym = S->getSymbol();
    2081        2526 :     if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
    2082          18 :       unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    2083             :       ARMConstantPoolValue *CPV =
    2084          18 :         ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
    2085           9 :                                       ARMPCLabelIndex, 4);
    2086          18 :       SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
    2087          18 :       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    2088           9 :       Callee = DAG.getLoad(
    2089             :           PtrVt, dl, DAG.getEntryNode(), CPAddr,
    2090          36 :           MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2091           9 :       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
    2092          18 :       Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
    2093             :     } else {
    2094        2450 :       Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
    2095             :     }
    2096             :   }
    2097             : 
    2098             :   // FIXME: handle tail calls differently.
    2099             :   unsigned CallOpc;
    2100        6625 :   if (Subtarget->isThumb()) {
    2101        2763 :     if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
    2102             :       CallOpc = ARMISD::CALL_NOLINK;
    2103             :     else
    2104             :       CallOpc = ARMISD::CALL;
    2105             :   } else {
    2106        3862 :     if (!isDirect && !Subtarget->hasV5TOps())
    2107             :       CallOpc = ARMISD::CALL_NOLINK;
    2108        3863 :     else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
    2109             :              // Emit regular call when code size is the priority
    2110          36 :              !MF.getFunction()->optForMinSize())
    2111             :       // "mov lr, pc; b _foo" to avoid confusing the RSP
    2112             :       CallOpc = ARMISD::CALL_NOLINK;
    2113             :     else
    2114        3831 :       CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
    2115             :   }
    2116             : 
    2117       13250 :   std::vector<SDValue> Ops;
    2118        6625 :   Ops.push_back(Chain);
    2119        6625 :   Ops.push_back(Callee);
    2120             : 
    2121             :   // Add argument registers to the end of the list so that they are known live
    2122             :   // into the call.
    2123       26152 :   for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
    2124       51608 :     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
    2125       38706 :                                   RegsToPass[i].second.getValueType()));
    2126             : 
    2127             :   // Add a register mask operand representing the call-preserved registers.
    2128        6625 :   if (!isTailCall) {
    2129             :     const uint32_t *Mask;
    2130        6120 :     const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
    2131        6120 :     if (isThisReturn) {
    2132             :       // For 'this' returns, use the R0-preserving mask if applicable
    2133          50 :       Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
    2134          50 :       if (!Mask) {
    2135             :         // Set isThisReturn to false if the calling convention is not one that
    2136             :         // allows 'returned' to be modeled in this way, so LowerCallResult does
    2137             :         // not try to pass 'this' straight through
    2138           0 :         isThisReturn = false;
    2139           0 :         Mask = ARI->getCallPreservedMask(MF, CallConv);
    2140             :       }
    2141             :     } else
    2142        6070 :       Mask = ARI->getCallPreservedMask(MF, CallConv);
    2143             : 
    2144             :     assert(Mask && "Missing call preserved mask for calling convention");
    2145       12240 :     Ops.push_back(DAG.getRegisterMask(Mask));
    2146             :   }
    2147             : 
    2148        6625 :   if (InFlag.getNode())
    2149        5318 :     Ops.push_back(InFlag);
    2150             : 
    2151       13250 :   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
    2152        6625 :   if (isTailCall) {
    2153         505 :     MF.getFrameInfo().setHasTailCall();
    2154         505 :     return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
    2155             :   }
    2156             : 
    2157             :   // Returns a chain and a flag for retval copy to use.
    2158        6120 :   Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
    2159       12240 :   InFlag = Chain.getValue(1);
    2160             : 
    2161        6120 :   Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
    2162        6120 :                              DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
    2163        6120 :   if (!Ins.empty())
    2164        7342 :     InFlag = Chain.getValue(1);
    2165             : 
    2166             :   // Handle result values, copying them out of physregs into vregs that we
    2167             :   // return.
    2168             :   return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
    2169             :                          InVals, isThisReturn,
    2170        6170 :                          isThisReturn ? OutVals[0] : SDValue());
    2171             : }
    2172             : 
    2173             : /// HandleByVal - Every parameter *after* a byval parameter is passed
    2174             : /// on the stack.  Remember the next parameter register to allocate,
    2175             : /// and then confiscate the rest of the parameter registers to insure
    2176             : /// this.
    2177         403 : void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
    2178             :                                     unsigned Align) const {
    2179             :   // Byval (as with any stack) slots are always at least 4 byte aligned.
    2180         806 :   Align = std::max(Align, 4U);
    2181             : 
    2182         403 :   unsigned Reg = State->AllocateReg(GPRArgRegs);
    2183         403 :   if (!Reg)
    2184             :     return;
    2185             : 
    2186         387 :   unsigned AlignInRegs = Align / 4;
    2187         387 :   unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
    2188         403 :   for (unsigned i = 0; i < Waste; ++i)
    2189          16 :     Reg = State->AllocateReg(GPRArgRegs);
    2190             : 
    2191         387 :   if (!Reg)
    2192             :     return;
    2193             : 
    2194         383 :   unsigned Excess = 4 * (ARM::R4 - Reg);
    2195             : 
    2196             :   // Special case when NSAA != SP and parameter size greater than size of
    2197             :   // all remained GPR regs. In that case we can't split parameter, we must
    2198             :   // send it to stack. We also must set NCRN to R4, so waste all
    2199             :   // remained registers.
    2200         383 :   const unsigned NSAAOffset = State->getNextStackOffset();
    2201         383 :   if (NSAAOffset != 0 && Size > Excess) {
    2202          15 :     while (State->AllocateReg(GPRArgRegs))
    2203             :       ;
    2204             :     return;
    2205             :   }
    2206             : 
    2207             :   // First register for byval parameter is the first register that wasn't
    2208             :   // allocated before this method call, so it would be "reg".
    2209             :   // If parameter is small enough to be saved in range [reg, r4), then
    2210             :   // the end (first after last) register would be reg + param-size-in-regs,
    2211             :   // else parameter would be splitted between registers and stack,
    2212             :   // end register would be r4 in this case.
    2213         378 :   unsigned ByValRegBegin = Reg;
    2214         756 :   unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
    2215         378 :   State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
    2216             :   // Note, first register is allocated in the beginning of function already,
    2217             :   // allocate remained amount of registers we need.
    2218        1427 :   for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
    2219        1049 :     State->AllocateReg(GPRArgRegs);
    2220             :   // A byval parameter that is split between registers and memory needs its
    2221             :   // size truncated here.
    2222             :   // In the case where the entire structure fits in registers, we set the
    2223             :   // size in memory to zero.
    2224         756 :   Size = std::max<int>(Size - Excess, 0);
    2225             : }
    2226             : 
    2227             : /// MatchingStackOffset - Return true if the given stack call argument is
    2228             : /// already available in the same position (relatively) of the caller's
    2229             : /// incoming argument stack.
    2230             : static
    2231          22 : bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
    2232             :                          MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
    2233             :                          const TargetInstrInfo *TII) {
    2234          22 :   unsigned Bytes = Arg.getValueSizeInBits() / 8;
    2235          22 :   int FI = std::numeric_limits<int>::max();
    2236          44 :   if (Arg.getOpcode() == ISD::CopyFromReg) {
    2237          15 :     unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
    2238           5 :     if (!TargetRegisterInfo::isVirtualRegister(VR))
    2239             :       return false;
    2240           5 :     MachineInstr *Def = MRI->getVRegDef(VR);
    2241           5 :     if (!Def)
    2242             :       return false;
    2243           0 :     if (!Flags.isByVal()) {
    2244           0 :       if (!TII->isLoadFromStackSlot(*Def, FI))
    2245             :         return false;
    2246             :     } else {
    2247             :       return false;
    2248             :     }
    2249           5 :   } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
    2250           5 :     if (Flags.isByVal())
    2251             :       // ByVal argument is passed in as a pointer but it's now being
    2252             :       // dereferenced. e.g.
    2253             :       // define @foo(%struct.X* %A) {
    2254             :       //   tail call @bar(%struct.X* byval %A)
    2255             :       // }
    2256           0 :       return false;
    2257           5 :     SDValue Ptr = Ld->getBasePtr();
    2258           5 :     FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
    2259             :     if (!FINode)
    2260             :       return false;
    2261           5 :     FI = FINode->getIndex();
    2262             :   } else
    2263             :     return false;
    2264             : 
    2265             :   assert(FI != std::numeric_limits<int>::max());
    2266          10 :   if (!MFI.isFixedObjectIndex(FI))
    2267             :     return false;
    2268          14 :   return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
    2269             : }
    2270             : 
    2271             : /// IsEligibleForTailCallOptimization - Check whether the call is eligible
    2272             : /// for tail call optimization. Targets which want to do tail call
    2273             : /// optimization should implement this function.
    2274             : bool
    2275         584 : ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
    2276             :                                                      CallingConv::ID CalleeCC,
    2277             :                                                      bool isVarArg,
    2278             :                                                      bool isCalleeStructRet,
    2279             :                                                      bool isCallerStructRet,
    2280             :                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
    2281             :                                     const SmallVectorImpl<SDValue> &OutVals,
    2282             :                                     const SmallVectorImpl<ISD::InputArg> &Ins,
    2283             :                                                      SelectionDAG& DAG) const {
    2284         584 :   MachineFunction &MF = DAG.getMachineFunction();
    2285         584 :   const Function *CallerF = MF.getFunction();
    2286         584 :   CallingConv::ID CallerCC = CallerF->getCallingConv();
    2287             : 
    2288             :   assert(Subtarget->supportsTailCall());
    2289             : 
    2290             :   // Look for obvious safe cases to perform tail call optimization that do not
    2291             :   // require ABI changes. This is what gcc calls sibcall.
    2292             : 
    2293             :   // Exception-handling functions need a special set of instructions to indicate
    2294             :   // a return to the hardware. Tail-calling another function would probably
    2295             :   // break this.
    2296        1168 :   if (CallerF->hasFnAttribute("interrupt"))
    2297             :     return false;
    2298             : 
    2299             :   // Also avoid sibcall optimization if either caller or callee uses struct
    2300             :   // return semantics.
    2301         584 :   if (isCalleeStructRet || isCallerStructRet)
    2302             :     return false;
    2303             : 
    2304             :   // Externally-defined functions with weak linkage should not be
    2305             :   // tail-called on ARM when the OS does not support dynamic
    2306             :   // pre-emption of symbols, as the AAELF spec requires normal calls
    2307             :   // to undefined weak functions to be replaced with a NOP or jump to the
    2308             :   // next instruction. The behaviour of branch instructions in this
    2309             :   // situation (as used for tail calls) is implementation-defined, so we
    2310             :   // cannot rely on the linker replacing the tail call with a return.
    2311         363 :   if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
    2312         363 :     const GlobalValue *GV = G->getGlobal();
    2313         726 :     const Triple &TT = getTargetMachine().getTargetTriple();
    2314         369 :     if (GV->hasExternalWeakLinkage() &&
    2315           8 :         (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
    2316             :       return false;
    2317             :   }
    2318             : 
    2319             :   // Check that the call results are passed in the same way.
    2320         579 :   LLVMContext &C = *DAG.getContext();
    2321         579 :   if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
    2322             :                                   CCAssignFnForReturn(CalleeCC, isVarArg),
    2323             :                                   CCAssignFnForReturn(CallerCC, isVarArg)))
    2324             :     return false;
    2325             :   // The callee has to preserve all registers the caller needs to preserve.
    2326         551 :   const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
    2327         551 :   const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
    2328         551 :   if (CalleeCC != CallerCC) {
    2329         183 :     const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
    2330         183 :     if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
    2331             :       return false;
    2332             :   }
    2333             : 
    2334             :   // If Caller's vararg or byval argument has been split between registers and
    2335             :   // stack, do not perform tail call, since part of the argument is in caller's
    2336             :   // local frame.
    2337         537 :   const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
    2338         537 :   if (AFI_Caller->getArgRegsSaveSize())
    2339             :     return false;
    2340             : 
    2341             :   // If the callee takes no arguments then go on to check the results of the
    2342             :   // call.
    2343         526 :   if (!Outs.empty()) {
    2344             :     // Check if stack adjustment is needed. For now, do not do this if any
    2345             :     // argument is passed on the stack.
    2346         741 :     SmallVector<CCValAssign, 16> ArgLocs;
    2347         741 :     CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
    2348         381 :     CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
    2349         381 :     if (CCInfo.getNextStackOffset()) {
    2350             :       // Check if the arguments are already laid out in the right way as
    2351             :       // the caller's fixed stack objects.
    2352          20 :       MachineFrameInfo &MFI = MF.getFrameInfo();
    2353          20 :       const MachineRegisterInfo *MRI = &MF.getRegInfo();
    2354          20 :       const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    2355         135 :       for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
    2356         115 :            i != e;
    2357             :            ++i, ++realArgIdx) {
    2358         226 :         CCValAssign &VA = ArgLocs[i];
    2359         226 :         EVT RegVT = VA.getLocVT();
    2360         226 :         SDValue Arg = OutVals[realArgIdx];
    2361         226 :         ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
    2362         113 :         if (VA.getLocInfo() == CCValAssign::Indirect)
    2363          18 :           return false;
    2364         113 :         if (VA.needsCustom()) {
    2365             :           // f64 and vector types are split into multiple registers or
    2366             :           // register/stack-slot combinations.  The types will not match
    2367             :           // the registers; give up on memory f64 refs until we figure
    2368             :           // out what to do about this.
    2369           2 :           if (!VA.isRegLoc())
    2370             :             return false;
    2371           6 :           if (!ArgLocs[++i].isRegLoc())
    2372             :             return false;
    2373           4 :           if (RegVT == MVT::v2f64) {
    2374           0 :             if (!ArgLocs[++i].isRegLoc())
    2375             :               return false;
    2376           0 :             if (!ArgLocs[++i].isRegLoc())
    2377             :               return false;
    2378             :           }
    2379         111 :         } else if (!VA.isRegLoc()) {
    2380          22 :           if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
    2381             :                                    MFI, MRI, TII))
    2382             :             return false;
    2383             :         }
    2384             :       }
    2385             :     }
    2386             : 
    2387         363 :     const MachineRegisterInfo &MRI = MF.getRegInfo();
    2388         363 :     if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
    2389             :       return false;
    2390             :   }
    2391             : 
    2392             :   return true;
    2393             : }
    2394             : 
    2395             : bool
    2396       19056 : ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
    2397             :                                   MachineFunction &MF, bool isVarArg,
    2398             :                                   const SmallVectorImpl<ISD::OutputArg> &Outs,
    2399             :                                   LLVMContext &Context) const {
    2400       38112 :   SmallVector<CCValAssign, 16> RVLocs;
    2401       38112 :   CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
    2402       38112 :   return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
    2403             : }
    2404             : 
    2405          12 : static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
    2406             :                                     const SDLoc &DL, SelectionDAG &DAG) {
    2407          12 :   const MachineFunction &MF = DAG.getMachineFunction();
    2408          12 :   const Function *F = MF.getFunction();
    2409             : 
    2410          24 :   StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
    2411             : 
    2412             :   // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
    2413             :   // version of the "preferred return address". These offsets affect the return
    2414             :   // instruction if this is a return from PL1 without hypervisor extensions.
    2415             :   //    IRQ/FIQ: +4     "subs pc, lr, #4"
    2416             :   //    SWI:     0      "subs pc, lr, #0"
    2417             :   //    ABORT:   +4     "subs pc, lr, #4"
    2418             :   //    UNDEF:   +4/+2  "subs pc, lr, #0"
    2419             :   // UNDEF varies depending on where the exception came from ARM or Thumb
    2420             :   // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
    2421             : 
    2422             :   int64_t LROffset;
    2423          32 :   if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
    2424           6 :       IntKind == "ABORT")
    2425             :     LROffset = 4;
    2426           6 :   else if (IntKind == "SWI" || IntKind == "UNDEF")
    2427             :     LROffset = 0;
    2428             :   else
    2429           0 :     report_fatal_error("Unsupported interrupt attribute. If present, value "
    2430             :                        "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
    2431             : 
    2432          24 :   RetOps.insert(RetOps.begin() + 1,
    2433          24 :                 DAG.getConstant(LROffset, DL, MVT::i32, false));
    2434             : 
    2435          36 :   return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
    2436             : }
    2437             : 
    2438             : SDValue
    2439       10819 : ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
    2440             :                                bool isVarArg,
    2441             :                                const SmallVectorImpl<ISD::OutputArg> &Outs,
    2442             :                                const SmallVectorImpl<SDValue> &OutVals,
    2443             :                                const SDLoc &dl, SelectionDAG &DAG) const {
    2444             : 
    2445             :   // CCValAssign - represent the assignment of the return value to a location.
    2446       21638 :   SmallVector<CCValAssign, 16> RVLocs;
    2447             : 
    2448             :   // CCState - Info about the registers and stack slots.
    2449             :   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
    2450       21638 :                  *DAG.getContext());
    2451             : 
    2452             :   // Analyze outgoing return values.
    2453       10819 :   CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
    2454             : 
    2455       10819 :   SDValue Flag;
    2456       21638 :   SmallVector<SDValue, 4> RetOps;
    2457       10819 :   RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
    2458       10819 :   bool isLittleEndian = Subtarget->isLittle();
    2459             : 
    2460       10819 :   MachineFunction &MF = DAG.getMachineFunction();
    2461       10819 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    2462       21638 :   AFI->setReturnRegsCount(RVLocs.size());
    2463             : 
    2464             :   // Copy the result values into the output registers.
    2465       19589 :   for (unsigned i = 0, realRVLocIdx = 0;
    2466       39178 :        i != RVLocs.size();
    2467             :        ++i, ++realRVLocIdx) {
    2468       17540 :     CCValAssign &VA = RVLocs[i];
    2469             :     assert(VA.isRegLoc() && "Can only return in registers!");
    2470             : 
    2471       17540 :     SDValue Arg = OutVals[realRVLocIdx];
    2472             : 
    2473        8770 :     switch (VA.getLocInfo()) {
    2474           0 :     default: llvm_unreachable("Unknown loc info!");
    2475             :     case CCValAssign::Full: break;
    2476        2003 :     case CCValAssign::BCvt:
    2477        4006 :       Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
    2478        2003 :       break;
    2479             :     }
    2480             : 
    2481        8770 :     if (VA.needsCustom()) {
    2482        1722 :       if (VA.getLocVT() == MVT::v2f64) {
    2483             :         // Extract the first half and return it in two registers.
    2484             :         SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
    2485        2358 :                                    DAG.getConstant(0, dl, MVT::i32));
    2486             :         SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
    2487        1572 :                                        DAG.getVTList(MVT::i32, MVT::i32), Half);
    2488             : 
    2489         786 :         Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
    2490             :                                  HalfGPRs.getValue(isLittleEndian ? 0 : 1),
    2491        1572 :                                  Flag);
    2492        1572 :         Flag = Chain.getValue(1);
    2493        1572 :         RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
    2494        1572 :         VA = RVLocs[++i]; // skip ahead to next loc
    2495         786 :         Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
    2496             :                                  HalfGPRs.getValue(isLittleEndian ? 1 : 0),
    2497        1572 :                                  Flag);
    2498        1572 :         Flag = Chain.getValue(1);
    2499        1572 :         RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
    2500        1572 :         VA = RVLocs[++i]; // skip ahead to next loc
    2501             : 
    2502             :         // Extract the 2nd half and fall through to handle it as an f64 value.
    2503         786 :         Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
    2504        3144 :                           DAG.getConstant(1, dl, MVT::i32));
    2505             :       }
    2506             :       // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
    2507             :       // available.
    2508             :       SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
    2509        3444 :                                   DAG.getVTList(MVT::i32, MVT::i32), Arg);
    2510        1722 :       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
    2511             :                                fmrrd.getValue(isLittleEndian ? 0 : 1),
    2512        3444 :                                Flag);
    2513        3444 :       Flag = Chain.getValue(1);
    2514        3444 :       RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
    2515        3444 :       VA = RVLocs[++i]; // skip ahead to next loc
    2516        1722 :       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
    2517             :                                fmrrd.getValue(isLittleEndian ? 1 : 0),
    2518        3444 :                                Flag);
    2519             :     } else
    2520        7048 :       Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
    2521             : 
    2522             :     // Guarantee that all emitted copies are
    2523             :     // stuck together, avoiding something bad.
    2524       17540 :     Flag = Chain.getValue(1);
    2525       17540 :     RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
    2526             :   }
    2527       10819 :   const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
    2528             :   const MCPhysReg *I =
    2529       10819 :       TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
    2530       10819 :   if (I) {
    2531        1185 :     for (; *I; ++I) {
    2532        1170 :       if (ARM::GPRRegClass.contains(*I))
    2533         105 :         RetOps.push_back(DAG.getRegister(*I, MVT::i32));
    2534         960 :       else if (ARM::DPRRegClass.contains(*I))
    2535         960 :         RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
    2536             :       else
    2537           0 :         llvm_unreachable("Unexpected register class in CSRsViaCopy!");
    2538             :     }
    2539             :   }
    2540             : 
    2541             :   // Update chain and glue.
    2542       10819 :   RetOps[0] = Chain;
    2543       10819 :   if (Flag.getNode())
    2544        7863 :     RetOps.push_back(Flag);
    2545             : 
    2546             :   // CPUs which aren't M-class use a special sequence to return from
    2547             :   // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
    2548             :   // though we use "subs pc, lr, #N").
    2549             :   //
    2550             :   // M-class CPUs actually use a normal return sequence with a special
    2551             :   // (hardware-provided) value in LR, so the normal code path works.
    2552       21656 :   if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
    2553          18 :       !Subtarget->isMClass()) {
    2554          12 :     if (Subtarget->isThumb1Only())
    2555           0 :       report_fatal_error("interrupt attribute is not supported in Thumb1");
    2556          12 :     return LowerInterruptReturn(RetOps, dl, DAG);
    2557             :   }
    2558             : 
    2559       32421 :   return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
    2560             : }
    2561             : 
    2562         613 : bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
    2563         613 :   if (N->getNumValues() != 1)
    2564             :     return false;
    2565         613 :   if (!N->hasNUsesOfValue(1, 0))
    2566             :     return false;
    2567             : 
    2568         594 :   SDValue TCChain = Chain;
    2569        1782 :   SDNode *Copy = *N->use_begin();
    2570         594 :   if (Copy->getOpcode() == ISD::CopyToReg) {
    2571             :     // If the copy has a glue operand, we conservatively assume it isn't safe to
    2572             :     // perform a tail call.
    2573        1150 :     if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
    2574             :       return false;
    2575         446 :     TCChain = Copy->getOperand(0);
    2576         364 :   } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
    2577          16 :     SDNode *VMov = Copy;
    2578             :     // f64 returned in a pair of GPRs.
    2579          32 :     SmallPtrSet<SDNode*, 2> Copies;
    2580          16 :     for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
    2581          48 :          UI != UE; ++UI) {
    2582          32 :       if (UI->getOpcode() != ISD::CopyToReg)
    2583             :         return false;
    2584          32 :       Copies.insert(*UI);
    2585             :     }
    2586          32 :     if (Copies.size() > 2)
    2587             :       return false;
    2588             : 
    2589          16 :     for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
    2590          48 :          UI != UE; ++UI) {
    2591          64 :       SDValue UseChain = UI->getOperand(0);
    2592          32 :       if (Copies.count(UseChain.getNode()))
    2593             :         // Second CopyToReg
    2594          16 :         Copy = *UI;
    2595             :       else {
    2596             :         // We are at the top of this chain.
    2597             :         // If the copy has a glue operand, we conservatively assume it
    2598             :         // isn't safe to perform a tail call.
    2599         112 :         if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
    2600           0 :           return false;
    2601             :         // First CopyToReg
    2602          16 :         TCChain = UseChain;
    2603             :       }
    2604             :     }
    2605         348 :   } else if (Copy->getOpcode() == ISD::BITCAST) {
    2606             :     // f32 returned in a single GPR.
    2607          38 :     if (!Copy->hasOneUse())
    2608             :       return false;
    2609          76 :     Copy = *Copy->use_begin();
    2610          38 :     if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
    2611             :       return false;
    2612             :     // If the copy has a glue operand, we conservatively assume it isn't safe to
    2613             :     // perform a tail call.
    2614         180 :     if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
    2615             :       return false;
    2616          68 :     TCChain = Copy->getOperand(0);
    2617             :   } else {
    2618             :     return false;
    2619             :   }
    2620             : 
    2621         273 :   bool HasRet = false;
    2622         273 :   for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
    2623         713 :        UI != UE; ++UI) {
    2624        1036 :     if (UI->getOpcode() != ARMISD::RET_FLAG &&
    2625          52 :         UI->getOpcode() != ARMISD::INTRET_FLAG)
    2626             :       return false;
    2627         440 :     HasRet = true;
    2628             :   }
    2629             : 
    2630         221 :   if (!HasRet)
    2631             :     return false;
    2632             : 
    2633         220 :   Chain = TCChain;
    2634         220 :   return true;
    2635             : }
    2636             : 
    2637         111 : bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
    2638         111 :   if (!Subtarget->supportsTailCall())
    2639             :     return false;
    2640             : 
    2641             :   auto Attr =
    2642         184 :       CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
    2643          92 :   if (!CI->isTailCall() || Attr.getValueAsString() == "true")
    2644             :     return false;
    2645             : 
    2646             :   return true;
    2647             : }
    2648             : 
    2649             : // Trying to write a 64 bit value so need to split into two 32 bit values first,
    2650             : // and pass the lower and high parts through.
    2651           2 : static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
    2652           4 :   SDLoc DL(Op);
    2653           4 :   SDValue WriteValue = Op->getOperand(2);
    2654             : 
    2655             :   // This function is only supposed to be called for i64 type argument.
    2656             :   assert(WriteValue.getValueType() == MVT::i64
    2657             :           && "LowerWRITE_REGISTER called for non-i64 type argument.");
    2658             : 
    2659             :   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
    2660           6 :                            DAG.getConstant(0, DL, MVT::i32));
    2661             :   SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
    2662           6 :                            DAG.getConstant(1, DL, MVT::i32));
    2663           6 :   SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
    2664           8 :   return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
    2665             : }
    2666             : 
    2667             : // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
    2668             : // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
    2669             : // one of the above mentioned nodes. It has to be wrapped because otherwise
    2670             : // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
    2671             : // be used to form addressing mode. These wrapped nodes will be selected
    2672             : // into MOVi.
    2673         862 : SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
    2674             :                                              SelectionDAG &DAG) const {
    2675        1724 :   EVT PtrVT = Op.getValueType();
    2676             :   // FIXME there is no actual debug info here
    2677        1724 :   SDLoc dl(Op);
    2678         862 :   ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
    2679         862 :   SDValue Res;
    2680             : 
    2681             :   // When generating execute-only code Constant Pools must be promoted to the
    2682             :   // global data section. It's a bit ugly that we can't share them across basic
    2683             :   // blocks, but this way we guarantee that execute-only behaves correct with
    2684             :   // position-independent addressing modes.
    2685         862 :   if (Subtarget->genExecuteOnly()) {
    2686           6 :     auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
    2687           6 :     auto T = const_cast<Type*>(CP->getType());
    2688           6 :     auto C = const_cast<Constant*>(CP->getConstVal());
    2689           6 :     auto M = const_cast<Module*>(DAG.getMachineFunction().
    2690           6 :                                  getFunction()->getParent());
    2691             :     auto GV = new GlobalVariable(
    2692             :                     *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
    2693          36 :                     Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
    2694          36 :                     Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
    2695          24 :                     Twine(AFI->createPICLabelUId())
    2696          12 :                   );
    2697           6 :     SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
    2698           6 :                                             dl, PtrVT);
    2699           6 :     return LowerGlobalAddress(GA, DAG);
    2700             :   }
    2701             : 
    2702         856 :   if (CP->isMachineConstantPoolEntry())
    2703           0 :     Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
    2704           0 :                                     CP->getAlignment());
    2705             :   else
    2706         856 :     Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
    2707         856 :                                     CP->getAlignment());
    2708        1712 :   return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
    2709             : }
    2710             : 
    2711          37 : unsigned ARMTargetLowering::getJumpTableEncoding() const {
    2712          37 :   return MachineJumpTableInfo::EK_Inline;
    2713             : }
    2714             : 
    2715          37 : SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
    2716             :                                              SelectionDAG &DAG) const {
    2717          37 :   MachineFunction &MF = DAG.getMachineFunction();
    2718          37 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    2719          37 :   unsigned ARMPCLabelIndex = 0;
    2720          74 :   SDLoc DL(Op);
    2721         148 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    2722          37 :   const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
    2723          37 :   SDValue CPAddr;
    2724          56 :   bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
    2725             :   if (!IsPositionIndependent) {
    2726          19 :     CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
    2727             :   } else {
    2728          36 :     unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
    2729          36 :     ARMPCLabelIndex = AFI->createPICLabelUId();
    2730             :     ARMConstantPoolValue *CPV =
    2731          18 :       ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
    2732          18 :                                       ARMCP::CPBlockAddress, PCAdj);
    2733          18 :     CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    2734             :   }
    2735          37 :   CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
    2736             :   SDValue Result = DAG.getLoad(
    2737             :       PtrVT, DL, DAG.getEntryNode(), CPAddr,
    2738          74 :       MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2739          37 :   if (!IsPositionIndependent)
    2740          19 :     return Result;
    2741          18 :   SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
    2742          18 :   return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
    2743             : }
    2744             : 
    2745             : /// \brief Convert a TLS address reference into the correct sequence of loads
    2746             : /// and calls to compute the variable's address for Darwin, and return an
    2747             : /// SDValue containing the final node.
    2748             : 
    2749             : /// Darwin only has one TLS scheme which must be capable of dealing with the
    2750             : /// fully general situation, in the worst case. This means:
    2751             : ///     + "extern __thread" declaration.
    2752             : ///     + Defined in a possibly unknown dynamic library.
    2753             : ///
    2754             : /// The general system is that each __thread variable has a [3 x i32] descriptor
    2755             : /// which contains information used by the runtime to calculate the address. The
    2756             : /// only part of this the compiler needs to know about is the first word, which
    2757             : /// contains a function pointer that must be called with the address of the
    2758             : /// entire descriptor in "r0".
    2759             : ///
    2760             : /// Since this descriptor may be in a different unit, in general access must
    2761             : /// proceed along the usual ARM rules. A common sequence to produce is:
    2762             : ///
    2763             : ///     movw rT1, :lower16:_var$non_lazy_ptr
    2764             : ///     movt rT1, :upper16:_var$non_lazy_ptr
    2765             : ///     ldr r0, [rT1]
    2766             : ///     ldr rT2, [r0]
    2767             : ///     blx rT2
    2768             : ///     [...address now in r0...]
    2769             : SDValue
    2770          79 : ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
    2771             :                                                SelectionDAG &DAG) const {
    2772             :   assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
    2773         158 :   SDLoc DL(Op);
    2774             : 
    2775             :   // First step is to get the address of the actua global symbol. This is where
    2776             :   // the TLS descriptor lives.
    2777          79 :   SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
    2778             : 
    2779             :   // The first entry in the descriptor is a function pointer that we must call
    2780             :   // to obtain the address of the variable.
    2781          79 :   SDValue Chain = DAG.getEntryNode();
    2782             :   SDValue FuncTLVGet = DAG.getLoad(
    2783             :       MVT::i32, DL, Chain, DescAddr,
    2784             :       MachinePointerInfo::getGOT(DAG.getMachineFunction()),
    2785             :       /* Alignment = */ 4,
    2786         158 :       MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
    2787         237 :           MachineMemOperand::MOInvariant);
    2788         158 :   Chain = FuncTLVGet.getValue(1);
    2789             : 
    2790          79 :   MachineFunction &F = DAG.getMachineFunction();
    2791          79 :   MachineFrameInfo &MFI = F.getFrameInfo();
    2792          79 :   MFI.setAdjustsStack(true);
    2793             : 
    2794             :   // TLS calls preserve all registers except those that absolutely must be
    2795             :   // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
    2796             :   // silly).
    2797             :   auto TRI =
    2798          79 :       getTargetMachine().getSubtargetImpl(*F.getFunction())->getRegisterInfo();
    2799          79 :   auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
    2800          79 :   const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
    2801             : 
    2802             :   // Finally, we can make the call. This is just a degenerate version of a
    2803             :   // normal AArch64 call node: r0 takes the address of the descriptor, and
    2804             :   // returns the address of the variable in this thread.
    2805          79 :   Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
    2806          79 :   Chain =
    2807         316 :       DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
    2808          79 :                   Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
    2809         395 :                   DAG.getRegisterMask(Mask), Chain.getValue(1));
    2810         316 :   return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
    2811             : }
    2812             : 
    2813             : SDValue
    2814           7 : ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
    2815             :                                                 SelectionDAG &DAG) const {
    2816             :   assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering");
    2817             : 
    2818           7 :   SDValue Chain = DAG.getEntryNode();
    2819          28 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    2820          14 :   SDLoc DL(Op);
    2821             : 
    2822             :   // Load the current TEB (thread environment block)
    2823             :   SDValue Ops[] = {Chain,
    2824          14 :                    DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
    2825          14 :                    DAG.getConstant(15, DL, MVT::i32),
    2826          14 :                    DAG.getConstant(0, DL, MVT::i32),
    2827          14 :                    DAG.getConstant(13, DL, MVT::i32),
    2828          14 :                    DAG.getConstant(0, DL, MVT::i32),
    2829          84 :                    DAG.getConstant(2, DL, MVT::i32)};
    2830             :   SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
    2831          21 :                                    DAG.getVTList(MVT::i32, MVT::Other), Ops);
    2832             : 
    2833          14 :   SDValue TEB = CurrentTEB.getValue(0);
    2834          14 :   Chain = CurrentTEB.getValue(1);
    2835             : 
    2836             :   // Load the ThreadLocalStoragePointer from the TEB
    2837             :   // A pointer to the TLS array is located at offset 0x2c from the TEB.
    2838             :   SDValue TLSArray =
    2839           7 :       DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
    2840          14 :   TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
    2841             : 
    2842             :   // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
    2843             :   // offset into the TLSArray.
    2844             : 
    2845             :   // Load the TLS index from the C runtime
    2846             :   SDValue TLSIndex =
    2847           7 :       DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
    2848           7 :   TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
    2849          14 :   TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
    2850             : 
    2851             :   SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
    2852          14 :                               DAG.getConstant(2, DL, MVT::i32));
    2853             :   SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
    2854             :                             DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
    2855          21 :                             MachinePointerInfo());
    2856             : 
    2857             :   // Get the offset of the start of the .tls section (section base)
    2858           7 :   const auto *GA = cast<GlobalAddressSDNode>(Op);
    2859           7 :   auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
    2860             :   SDValue Offset = DAG.getLoad(
    2861             :       PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
    2862           7 :                                     DAG.getTargetConstantPool(CPV, PtrVT, 4)),
    2863          28 :       MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2864             : 
    2865          14 :   return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
    2866             : }
    2867             : 
    2868             : // Lower ISD::GlobalTLSAddress using the "general dynamic" model
    2869             : SDValue
    2870          15 : ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
    2871             :                                                  SelectionDAG &DAG) const {
    2872          30 :   SDLoc dl(GA);
    2873          60 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    2874          15 :   unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
    2875          15 :   MachineFunction &MF = DAG.getMachineFunction();
    2876          15 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    2877          30 :   unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    2878             :   ARMConstantPoolValue *CPV =
    2879          15 :     ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
    2880          15 :                                     ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
    2881          15 :   SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    2882          30 :   Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
    2883          15 :   Argument = DAG.getLoad(
    2884             :       PtrVT, dl, DAG.getEntryNode(), Argument,
    2885          45 :       MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2886          30 :   SDValue Chain = Argument.getValue(1);
    2887             : 
    2888          15 :   SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
    2889          15 :   Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
    2890             : 
    2891             :   // call __tls_get_addr.
    2892          30 :   ArgListTy Args;
    2893          15 :   ArgListEntry Entry;
    2894          15 :   Entry.Node = Argument;
    2895          15 :   Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
    2896          15 :   Args.push_back(Entry);
    2897             : 
    2898             :   // FIXME: is there useful debug info available here?
    2899          30 :   TargetLowering::CallLoweringInfo CLI(DAG);
    2900          45 :   CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
    2901          15 :       CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
    2902          15 :       DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
    2903             : 
    2904          15 :   std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
    2905          30 :   return CallResult.first;
    2906             : }
    2907             : 
    2908             : // Lower ISD::GlobalTLSAddress using the "initial exec" or
    2909             : // "local exec" model.
    2910             : SDValue
    2911          39 : ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
    2912             :                                         SelectionDAG &DAG,
    2913             :                                         TLSModel::Model model) const {
    2914          39 :   const GlobalValue *GV = GA->getGlobal();
    2915          78 :   SDLoc dl(GA);
    2916          39 :   SDValue Offset;
    2917          39 :   SDValue Chain = DAG.getEntryNode();
    2918         156 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    2919             :   // Get the Thread Pointer
    2920          39 :   SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
    2921             : 
    2922          39 :   if (model == TLSModel::InitialExec) {
    2923          18 :     MachineFunction &MF = DAG.getMachineFunction();
    2924          18 :     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    2925          36 :     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    2926             :     // Initial exec model.
    2927          18 :     unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
    2928             :     ARMConstantPoolValue *CPV =
    2929          18 :       ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
    2930             :                                       ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
    2931          18 :                                       true);
    2932          18 :     Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    2933          36 :     Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
    2934          18 :     Offset = DAG.getLoad(
    2935             :         PtrVT, dl, Chain, Offset,
    2936          36 :         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2937          36 :     Chain = Offset.getValue(1);
    2938             : 
    2939          18 :     SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
    2940          18 :     Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
    2941             : 
    2942          18 :     Offset = DAG.getLoad(
    2943             :         PtrVT, dl, Chain, Offset,
    2944          36 :         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2945             :   } else {
    2946             :     // local exec model
    2947             :     assert(model == TLSModel::LocalExec);
    2948             :     ARMConstantPoolValue *CPV =
    2949          21 :       ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
    2950          21 :     Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    2951          42 :     Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
    2952          21 :     Offset = DAG.getLoad(
    2953             :         PtrVT, dl, Chain, Offset,
    2954          42 :         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    2955             :   }
    2956             : 
    2957             :   // The address of the thread local variable is the add of the thread
    2958             :   // pointer with the offset of the variable.
    2959          78 :   return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
    2960             : }
    2961             : 
    2962             : SDValue
    2963         187 : ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
    2964         295 :   if (Subtarget->isTargetDarwin())
    2965          79 :     return LowerGlobalTLSAddressDarwin(Op, DAG);
    2966             : 
    2967         216 :   if (Subtarget->isTargetWindows())
    2968           7 :     return LowerGlobalTLSAddressWindows(Op, DAG);
    2969             : 
    2970             :   // TODO: implement the "local dynamic" model
    2971             :   assert(Subtarget->isTargetELF() && "Only ELF implemented here");
    2972         101 :   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
    2973         101 :   if (DAG.getTarget().Options.EmulatedTLS)
    2974          47 :     return LowerToTLSEmulatedModel(GA, DAG);
    2975             : 
    2976          54 :   TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
    2977             : 
    2978          54 :   switch (model) {
    2979          15 :     case TLSModel::GeneralDynamic:
    2980             :     case TLSModel::LocalDynamic:
    2981          15 :       return LowerToTLSGeneralDynamicModel(GA, DAG);
    2982          39 :     case TLSModel::InitialExec:
    2983             :     case TLSModel::LocalExec:
    2984          39 :       return LowerToTLSExecModels(GA, DAG, model);
    2985             :   }
    2986           0 :   llvm_unreachable("bogus TLS model");
    2987             : }
    2988             : 
    2989             : /// Return true if all users of V are within function F, looking through
    2990             : /// ConstantExprs.
    2991         130 : static bool allUsersAreInFunction(const Value *V, const Function *F) {
    2992         260 :   SmallVector<const User*,4> Worklist;
    2993         524 :   for (auto *U : V->users())
    2994         132 :     Worklist.push_back(U);
    2995         340 :   while (!Worklist.empty()) {
    2996         308 :     auto *U = Worklist.pop_back_val();
    2997         616 :     if (isa<ConstantExpr>(U)) {
    2998         933 :       for (auto *UU : U->users())
    2999         273 :         Worklist.push_back(UU);
    3000         129 :       continue;
    3001             :     }
    3002             : 
    3003         346 :     auto *I = dyn_cast<Instruction>(U);
    3004         167 :     if (!I || I->getParent()->getParent() != F)
    3005             :       return false;
    3006             :   }
    3007             :   return true;
    3008             : }
    3009             : 
    3010             : /// Return true if all users of V are within some (any) function, looking through
    3011             : /// ConstantExprs. In other words, are there any global constant users?
    3012          74 : static bool allUsersAreInFunctions(const Value *V) {
    3013         148 :   SmallVector<const User*,4> Worklist;
    3014         300 :   for (auto *U : V->users())
    3015          76 :     Worklist.push_back(U);
    3016         310 :   while (!Worklist.empty()) {
    3017         248 :     auto *U = Worklist.pop_back_val();
    3018         496 :     if (isa<ConstantExpr>(U)) {
    3019         596 :       for (auto *UU : U->users())
    3020         184 :         Worklist.push_back(UU);
    3021          76 :       continue;
    3022             :     }
    3023             : 
    3024         344 :     if (!isa<Instruction>(U))
    3025             :       return false;
    3026             :   }
    3027             :   return true;
    3028             : }
    3029             : 
    3030             : // Return true if T is an integer, float or an array/vector of either.
    3031         194 : static bool isSimpleType(Type *T) {
    3032         386 :   if (T->isIntegerTy() || T->isFloatingPointTy())
    3033             :     return true;
    3034         192 :   Type *SubT = nullptr;
    3035         192 :   if (T->isArrayTy())
    3036         384 :     SubT = T->getArrayElementType();
    3037           0 :   else if (T->isVectorTy())
    3038           0 :     SubT = T->getVectorElementType();
    3039             :   else
    3040             :     return false;
    3041         192 :   return SubT->isIntegerTy() || SubT->isFloatingPointTy();
    3042             : }
    3043             : 
    3044        1269 : static SDValue promoteToConstantPool(const GlobalValue *GV, SelectionDAG &DAG,
    3045             :                                      EVT PtrVT, const SDLoc &dl) {
    3046             :   // If we're creating a pool entry for a constant global with unnamed address,
    3047             :   // and the global is small enough, we can emit it inline into the constant pool
    3048             :   // to save ourselves an indirection.
    3049             :   //
    3050             :   // This is a win if the constant is only used in one function (so it doesn't
    3051             :   // need to be duplicated) or duplicating the constant wouldn't increase code
    3052             :   // size (implying the constant is no larger than 4 bytes).
    3053        1269 :   const Function *F = DAG.getMachineFunction().getFunction();
    3054             :   
    3055             :   // We rely on this decision to inline being idemopotent and unrelated to the
    3056             :   // use-site. We know that if we inline a variable at one use site, we'll
    3057             :   // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
    3058             :   // doesn't know about this optimization, so bail out if it's enabled else
    3059             :   // we could decide to inline here (and thus never emit the GV) but require
    3060             :   // the GV from fast-isel generated code.
    3061        1463 :   if (!EnableConstpoolPromotion ||
    3062         194 :       DAG.getMachineFunction().getTarget().Options.EnableFastISel)
    3063        1075 :       return SDValue();
    3064             : 
    3065         194 :   auto *GVar = dyn_cast<GlobalVariable>(GV);
    3066         388 :   if (!GVar || !GVar->hasInitializer() ||
    3067         582 :       !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
    3068         194 :       !GVar->hasLocalLinkage())
    3069           0 :     return SDValue();
    3070             : 
    3071             :   // Ensure that we don't try and inline any type that contains pointers. If
    3072             :   // we inline a value that contains relocations, we move the relocations from
    3073             :   // .data to .text which is not ideal.
    3074         194 :   auto *Init = GVar->getInitializer();
    3075         194 :   if (!isSimpleType(Init->getType()))
    3076          12 :     return SDValue();
    3077             : 
    3078             :   // The constant islands pass can only really deal with alignment requests
    3079             :   // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
    3080             :   // any type wanting greater alignment requirements than 4 bytes. We also
    3081             :   // can only promote constants that are multiples of 4 bytes in size or
    3082             :   // are paddable to a multiple of 4. Currently we only try and pad constants
    3083             :   // that are strings for simplicity.
    3084         182 :   auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
    3085         364 :   unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
    3086         364 :   unsigned Align = GVar->getAlignment();
    3087         182 :   unsigned RequiredPadding = 4 - (Size % 4);
    3088             :   bool PaddingPossible =
    3089         182 :     RequiredPadding == 4 || (CDAInit && CDAInit->isString());
    3090         336 :   if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
    3091             :       Size == 0)
    3092          52 :     return SDValue();
    3093             : 
    3094         260 :   unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
    3095         130 :   MachineFunction &MF = DAG.getMachineFunction();
    3096         130 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3097             : 
    3098             :   // We can't bloat the constant pool too much, else the ConstantIslands pass
    3099             :   // may fail to converge. If we haven't promoted this global yet (it may have
    3100             :   // multiple uses), and promoting it would increase the constant pool size (Sz
    3101             :   // > 4), ensure we have space to do so up to MaxTotal.
    3102         130 :   if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
    3103         108 :     if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
    3104          54 :         ConstpoolPromotionMaxTotal)
    3105           0 :       return SDValue();
    3106             : 
    3107             :   // This is only valid if all users are in a single function OR it has users
    3108             :   // in multiple functions but it no larger than a pointer. We also check if
    3109             :   // GVar has constant (non-ConstantExpr) users. If so, it essentially has its
    3110             :   // address taken.
    3111         130 :   if (!allUsersAreInFunction(GVar, F) &&
    3112          74 :       !(Size <= 4 && allUsersAreInFunctions(GVar)))
    3113          36 :     return SDValue();
    3114             : 
    3115             :   // We're going to inline this global. Pad it out if needed.
    3116          94 :   if (RequiredPadding != 4) {
    3117          96 :     StringRef S = CDAInit->getAsString();
    3118             : 
    3119         144 :     SmallVector<uint8_t,16> V(S.size());
    3120         144 :     std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
    3121         216 :     while (RequiredPadding--)
    3122          84 :       V.push_back(0);
    3123          48 :     Init = ConstantDataArray::get(*DAG.getContext(), V);
    3124             :   }
    3125             : 
    3126          94 :   auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
    3127             :   SDValue CPAddr =
    3128          94 :     DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
    3129          94 :   if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
    3130          94 :     AFI->markGlobalAsPromotedToConstantPool(GVar);
    3131         188 :     AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
    3132          94 :                                       PaddedSize - 4);
    3133             :   }
    3134          94 :   ++NumConstpoolPromoted;
    3135         188 :   return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    3136             : }
    3137             : 
    3138        1464 : bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
    3139        1468 :   if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
    3140           4 :     GV = GA->getBaseObject();
    3141        6965 :   return (isa<GlobalVariable>(GV) && cast<GlobalVariable>(GV)->isConstant()) ||
    3142        2615 :          isa<Function>(GV);
    3143             : }
    3144             : 
    3145        1954 : SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
    3146             :                                               SelectionDAG &DAG) const {
    3147        1954 :   switch (Subtarget->getTargetTriple().getObjectFormat()) {
    3148           0 :   default: llvm_unreachable("unknown object format");
    3149          32 :   case Triple::COFF:
    3150          32 :     return LowerGlobalAddressWindows(Op, DAG);
    3151        1400 :   case Triple::ELF:
    3152        1400 :     return LowerGlobalAddressELF(Op, DAG);
    3153         522 :   case Triple::MachO:
    3154         522 :     return LowerGlobalAddressDarwin(Op, DAG);
    3155             :   }
    3156             : }
    3157             : 
    3158        1400 : SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
    3159             :                                                  SelectionDAG &DAG) const {
    3160        5600 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    3161        2800 :   SDLoc dl(Op);
    3162        1400 :   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
    3163        1400 :   const TargetMachine &TM = getTargetMachine();
    3164        1400 :   bool IsRO = isReadOnly(GV);
    3165             : 
    3166             :   // promoteToConstantPool only if not generating XO text section
    3167        1400 :   if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
    3168        1269 :     if (SDValue V = promoteToConstantPool(GV, DAG, PtrVT, dl))
    3169          94 :       return V;
    3170             : 
    3171        1306 :   if (isPositionIndependent()) {
    3172          84 :     bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
    3173             : 
    3174          84 :     MachineFunction &MF = DAG.getMachineFunction();
    3175          84 :     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3176         168 :     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    3177         336 :     EVT PtrVT = getPointerTy(DAG.getDataLayout());
    3178         168 :     SDLoc dl(Op);
    3179          84 :     unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
    3180          84 :     ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
    3181             :         GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
    3182             :         UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
    3183          84 :         /*AddCurrentAddress=*/UseGOT_PREL);
    3184          84 :     SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    3185         168 :     CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    3186             :     SDValue Result = DAG.getLoad(
    3187             :         PtrVT, dl, DAG.getEntryNode(), CPAddr,
    3188         168 :         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    3189         168 :     SDValue Chain = Result.getValue(1);
    3190          84 :     SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
    3191          84 :     Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
    3192          84 :     if (UseGOT_PREL)
    3193          41 :       Result =
    3194          82 :           DAG.getLoad(PtrVT, dl, Chain, Result,
    3195          82 :                       MachinePointerInfo::getGOT(DAG.getMachineFunction()));
    3196          84 :     return Result;
    3197        1222 :   } else if (Subtarget->isROPI() && IsRO) {
    3198             :     // PC-relative.
    3199          51 :     SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
    3200          51 :     SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
    3201          51 :     return Result;
    3202        1241 :   } else if (Subtarget->isRWPI() && !IsRO) {
    3203             :     // SB-relative.
    3204          30 :     SDValue RelAddr;
    3205          30 :     if (Subtarget->useMovt(DAG.getMachineFunction())) {
    3206          12 :       ++NumMovwMovt;
    3207          12 :       SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
    3208          12 :       RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
    3209             :     } else { // use literal pool for address constant
    3210             :       ARMConstantPoolValue *CPV =
    3211          18 :         ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
    3212          18 :       SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    3213          36 :       CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    3214          18 :       RelAddr = DAG.getLoad(
    3215             :           PtrVT, dl, DAG.getEntryNode(), CPAddr,
    3216          54 :           MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    3217             :     }
    3218          30 :     SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
    3219          30 :     SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
    3220          30 :     return Result;
    3221             :   }
    3222             : 
    3223             :   // If we have T2 ops, we can materialize the address directly via movt/movw
    3224             :   // pair. This is always cheaper.
    3225        1141 :   if (Subtarget->useMovt(DAG.getMachineFunction())) {
    3226         702 :     ++NumMovwMovt;
    3227             :     // FIXME: Once remat is capable of dealing with instructions with register
    3228             :     // operands, expand this into two nodes.
    3229             :     return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
    3230        1404 :                        DAG.getTargetGlobalAddress(GV, dl, PtrVT));
    3231             :   } else {
    3232         439 :     SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
    3233         878 :     CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    3234             :     return DAG.getLoad(
    3235             :         PtrVT, dl, DAG.getEntryNode(), CPAddr,
    3236         878 :         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    3237             :   }
    3238             : }
    3239             : 
    3240         601 : SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
    3241             :                                                     SelectionDAG &DAG) const {
    3242             :   assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
    3243             :          "ROPI/RWPI not currently supported for Darwin");
    3244        2404 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    3245        1202 :   SDLoc dl(Op);
    3246         601 :   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
    3247             : 
    3248         601 :   if (Subtarget->useMovt(DAG.getMachineFunction()))
    3249             :     ++NumMovwMovt;
    3250             : 
    3251             :   // FIXME: Once remat is capable of dealing with instructions with register
    3252             :   // operands, expand this into multiple nodes
    3253             :   unsigned Wrapper =
    3254         601 :       isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
    3255             : 
    3256         601 :   SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
    3257         601 :   SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
    3258             : 
    3259         601 :   if (Subtarget->isGVIndirectSymbol(GV))
    3260         314 :     Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
    3261         942 :                          MachinePointerInfo::getGOT(DAG.getMachineFunction()));
    3262        1202 :   return Result;
    3263             : }
    3264             : 
    3265          32 : SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
    3266             :                                                      SelectionDAG &DAG) const {
    3267             :   assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
    3268             :   assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
    3269             :          "Windows on ARM expects to use movw/movt");
    3270             :   assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
    3271             :          "ROPI/RWPI not currently supported for Windows");
    3272             : 
    3273          32 :   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
    3274             :   const ARMII::TOF TargetFlags =
    3275          32 :     (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
    3276         128 :   EVT PtrVT = getPointerTy(DAG.getDataLayout());
    3277          32 :   SDValue Result;
    3278          64 :   SDLoc DL(Op);
    3279             : 
    3280          32 :   ++NumMovwMovt;
    3281             : 
    3282             :   // FIXME: Once remat is capable of dealing with instructions with register
    3283             :   // operands, expand this into two nodes.
    3284          32 :   Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
    3285             :                        DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
    3286          96 :                                                   TargetFlags));
    3287          32 :   if (GV->hasDLLImportStorageClass())
    3288           2 :     Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
    3289           6 :                          MachinePointerInfo::getGOT(DAG.getMachineFunction()));
    3290          64 :   return Result;
    3291             : }
    3292             : 
    3293             : SDValue
    3294           4 : ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
    3295           8 :   SDLoc dl(Op);
    3296           4 :   SDValue Val = DAG.getConstant(0, dl, MVT::i32);
    3297             :   return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
    3298          16 :                      DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
    3299          16 :                      Op.getOperand(1), Val);
    3300             : }
    3301             : 
    3302             : SDValue
    3303           5 : ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
    3304          10 :   SDLoc dl(Op);
    3305          10 :   return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
    3306          20 :                      Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
    3307             : }
    3308             : 
    3309          28 : SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
    3310             :                                                       SelectionDAG &DAG) const {
    3311          56 :   SDLoc dl(Op);
    3312             :   return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
    3313         112 :                      Op.getOperand(0));
    3314             : }
    3315             : 
    3316             : SDValue
    3317        2099 : ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
    3318             :                                           const ARMSubtarget *Subtarget) const {
    3319        8396 :   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
    3320        4198 :   SDLoc dl(Op);
    3321        2099 :   switch (IntNo) {
    3322        1996 :   default: return SDValue();    // Don't custom lower most intrinsics.
    3323           1 :   case Intrinsic::thread_pointer: {
    3324           4 :     EVT PtrVT = getPointerTy(DAG.getDataLayout());
    3325           1 :     return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
    3326             :   }
    3327          28 :   case Intrinsic::eh_sjlj_lsda: {
    3328          28 :     MachineFunction &MF = DAG.getMachineFunction();
    3329          28 :     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3330          56 :     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
    3331         112 :     EVT PtrVT = getPointerTy(DAG.getDataLayout());
    3332             :     SDValue CPAddr;
    3333          28 :     bool IsPositionIndependent = isPositionIndependent();
    3334          28 :     unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
    3335             :     ARMConstantPoolValue *CPV =
    3336          28 :       ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
    3337          28 :                                       ARMCP::CPLSDA, PCAdj);
    3338          28 :     CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
    3339          56 :     CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
    3340             :     SDValue Result = DAG.getLoad(
    3341             :         PtrVT, dl, DAG.getEntryNode(), CPAddr,
    3342          56 :         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
    3343             : 
    3344          28 :     if (IsPositionIndependent) {
    3345          24 :       SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
    3346          24 :       Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
    3347             :     }
    3348          28 :     return Result;
    3349             :   }
    3350          16 :   case Intrinsic::arm_neon_vabs:
    3351          32 :     return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
    3352          80 :                         Op.getOperand(1));
    3353          15 :   case Intrinsic::arm_neon_vmulls:
    3354             :   case Intrinsic::arm_neon_vmullu: {
    3355          15 :     unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
    3356          15 :       ? ARMISD::VMULLs : ARMISD::VMULLu;
    3357          30 :     return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
    3358          90 :                        Op.getOperand(1), Op.getOperand(2));
    3359             :   }
    3360           4 :   case Intrinsic::arm_neon_vminnm:
    3361             :   case Intrinsic::arm_neon_vmaxnm: {
    3362           4 :     unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
    3363           4 :       ? ISD::FMINNUM : ISD::FMAXNUM;
    3364           8 :     return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
    3365          24 :                        Op.getOperand(1), Op.getOperand(2));
    3366             :   }
    3367          16 :   case Intrinsic::arm_neon_vminu:
    3368             :   case Intrinsic::arm_neon_vmaxu: {
    3369          32 :     if (Op.getValueType().isFloatingPoint())
    3370           0 :       return SDValue();
    3371          16 :     unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
    3372          16 :       ? ISD::UMIN : ISD::UMAX;
    3373          32 :     return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
    3374          96 :                          Op.getOperand(1), Op.getOperand(2));
    3375             :   }
    3376          18 :   case Intrinsic::arm_neon_vmins:
    3377             :   case Intrinsic::arm_neon_vmaxs: {
    3378             :     // v{min,max}s is overloaded between signed integers and floats.
    3379          36 :     if (!Op.getValueType().isFloatingPoint()) {
    3380          12 :       unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
    3381          12 :         ? ISD::SMIN : ISD::SMAX;
    3382          24 :       return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
    3383          72 :                          Op.getOperand(1), Op.getOperand(2));
    3384             :     }
    3385           6 :     unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
    3386           6 :       ? ISD::FMINNAN : ISD::FMAXNAN;
    3387          12 :     return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
    3388          36 :                        Op.getOperand(1), Op.getOperand(2));
    3389             :   }
    3390           1 :   case Intrinsic::arm_neon_vtbl1:
    3391           2 :     return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
    3392           6 :                        Op.getOperand(1), Op.getOperand(2));
    3393           4 :   case Intrinsic::arm_neon_vtbl2:
    3394           8 :     return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
    3395          24 :                        Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
    3396             :   }
    3397             : }
    3398             : 
    3399          21 : static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
    3400             :                                  const ARMSubtarget *Subtarget) {
    3401          42 :   SDLoc dl(Op);
    3402          63 :   ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
    3403          21 :   auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
    3404          21 :   if (SSID == SyncScope::SingleThread)
    3405           6 :     return Op;
    3406             : 
    3407          15 :   if (!Subtarget->hasDataBarrier()) {
    3408             :     // Some ARMv6 cpus can support data barriers with an mcr instruction.
    3409             :     // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
    3410             :     // here.
    3411             :     assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
    3412             :            "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
    3413           0 :     return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
    3414           0 :                        DAG.getConstant(0, dl, MVT::i32));
    3415             :   }
    3416             : 
    3417          45 :   ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
    3418          15 :   AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
    3419          15 :   ARM_MB::MemBOpt Domain = ARM_MB::ISH;
    3420          15 :   if (Subtarget->isMClass()) {
    3421             :     // Only a full system barrier exists in the M-class architectures.
    3422             :     Domain = ARM_MB::SY;
    3423          13 :   } else if (Subtarget->preferISHSTBarriers() &&
    3424             :              Ord == AtomicOrdering::Release) {
    3425             :     // Swift happens to implement ISHST barriers in a way that's compatible with
    3426             :     // Release semantics but weaker than ISH so we'd be fools not to use
    3427             :     // it. Beware: other processors probably don't!
    3428             :     Domain = ARM_MB::ISHST;
    3429             :   }
    3430             : 
    3431          30 :   return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
    3432          15 :                      DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
    3433          45 :                      DAG.getConstant(Domain, dl, MVT::i32));
    3434             : }
    3435             : 
    3436          32 : static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
    3437             :                              const ARMSubtarget *Subtarget) {
    3438             :   // ARM pre v5TE and Thumb1 does not have preload instructions.
    3439          32 :   if (!(Subtarget->isThumb2() ||
    3440          40 :         (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
    3441             :     // Just preserve the chain.
    3442          16 :     return Op.getOperand(0);
    3443             : 
    3444          24 :   SDLoc dl(Op);
    3445          96 :   unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
    3446          27 :   if (!isRead &&
    3447           6 :       (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
    3448             :     // ARMv7 with MP extension has PLDW.
    3449           4 :     return Op.getOperand(0);
    3450             : 
    3451          88 :   unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
    3452          22 :   if (Subtarget->isThumb()) {
    3453             :     // Invert the bits.
    3454           7 :     isRead = ~isRead & 1;
    3455           7 :     isData = ~isData & 1;
    3456             :   }
    3457             : 
    3458          44 :   return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
    3459          66 :                      Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
    3460          66 :                      DAG.getConstant(isData, dl, MVT::i32));
    3461             : }
    3462             : 
    3463          30 : static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
    3464          30 :   MachineFunction &MF = DAG.getMachineFunction();
    3465          30 :   ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
    3466             : 
    3467             :   // vastart just stores the address of the VarArgsFrameIndex slot into the
    3468             :   // memory location argument.
    3469          60 :   SDLoc dl(Op);
    3470         120 :   EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
    3471          30 :   SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
    3472          90 :   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
    3473          90 :   return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
    3474         120 :                       MachinePointerInfo(SV));
    3475             : }
    3476             : 
    3477         938 : SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
    3478             :                                                 CCValAssign &NextVA,
    3479             :                                                 SDValue &Root,
    3480             :                                                 SelectionDAG &DAG,
    3481             :                                                 const SDLoc &dl) const {
    3482         938 :   MachineFunction &MF = DAG.getMachineFunction();
    3483         938 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3484             : 
    3485             :   const TargetRegisterClass *RC;
    3486         938 :   if (AFI->isThumb1OnlyFunction())
    3487             :     RC = &ARM::tGPRRegClass;
    3488             :   else
    3489             :     RC = &ARM::GPRRegClass;
    3490             : 
    3491             :   // Transform the arguments stored in physical registers into virtual ones.
    3492         938 :   unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
    3493         938 :   SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
    3494             : 
    3495         938 :   SDValue ArgValue2;
    3496         938 :   if (NextVA.isMemLoc()) {
    3497          27 :     MachineFrameInfo &MFI = MF.getFrameInfo();
    3498          27 :     int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
    3499             : 
    3500             :     // Create load node to retrieve arguments from the stack.
    3501         108 :     SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
    3502          27 :     ArgValue2 = DAG.getLoad(
    3503             :         MVT::i32, dl, Root, FIN,
    3504          81 :         MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
    3505             :   } else {
    3506         911 :     Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
    3507         911 :     ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
    3508             :   }
    3509         938 :   if (!Subtarget->isLittle())
    3510             :     std::swap (ArgValue, ArgValue2);
    3511        1876 :   return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
    3512             : }
    3513             : 
    3514             : // The remaining GPRs hold either the beginning of variable-argument
    3515             : // data, or the beginning of an aggregate passed by value (usually
    3516             : // byval).  Either way, we allocate stack slots adjacent to the data
    3517             : // provided by our caller, and store the unallocated registers there.
    3518             : // If this is a variadic function, the va_list pointer will begin with
    3519             : // these values; otherwise, this reassembles a (byval) structure that
    3520             : // was split between registers and memory.
    3521             : // Return: The frame index registers were stored into.
    3522          72 : int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
    3523             :                                       const SDLoc &dl, SDValue &Chain,
    3524             :                                       const Value *OrigArg,
    3525             :                                       unsigned InRegsParamRecordIdx,
    3526             :                                       int ArgOffset, unsigned ArgSize) const {
    3527             :   // Currently, two use-cases possible:
    3528             :   // Case #1. Non-var-args function, and we meet first byval parameter.
    3529             :   //          Setup first unallocated register as first byval register;
    3530             :   //          eat all remained registers
    3531             :   //          (these two actions are performed by HandleByVal method).
    3532             :   //          Then, here, we initialize stack frame with
    3533             :   //          "store-reg" instructions.
    3534             :   // Case #2. Var-args function, that doesn't contain byval parameters.
    3535             :   //          The same: eat all remained unallocated registers,
    3536             :   //          initialize stack frame.
    3537             : 
    3538          72 :   MachineFunction &MF = DAG.getMachineFunction();
    3539          72 :   MachineFrameInfo &MFI = MF.getFrameInfo();
    3540          72 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3541             :   unsigned RBegin, REnd;
    3542          72 :   if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
    3543             :     CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
    3544             :   } else {
    3545          43 :     unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
    3546          43 :     RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
    3547             :     REnd = ARM::R4;
    3548             :   }
    3549             : 
    3550          72 :   if (REnd != RBegin)
    3551          58 :     ArgOffset = -4 * (ARM::R4 - RBegin);
    3552             : 
    3553         216 :   auto PtrVT = getPointerTy(DAG.getDataLayout());
    3554          72 :   int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
    3555          72 :   SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
    3556             : 
    3557         144 :   SmallVector<SDValue, 4> MemOps;
    3558             :   const TargetRegisterClass *RC =
    3559         144 :       AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
    3560             : 
    3561         235 :   for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
    3562         163 :     unsigned VReg = MF.addLiveIn(Reg, RC);
    3563         163 :     SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
    3564             :     SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
    3565         489 :                                  MachinePointerInfo(OrigArg, 4 * i));
    3566         163 :     MemOps.push_back(Store);
    3567         489 :     FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
    3568             :   }
    3569             : 
    3570          72 :   if (!MemOps.empty())
    3571         174 :     Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
    3572         144 :   return FrameIndex;
    3573             : }
    3574             : 
    3575             : // Setup stack frame, the va_list pointer will start from.
    3576          30 : void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
    3577             :                                              const SDLoc &dl, SDValue &Chain,
    3578             :                                              unsigned ArgOffset,
    3579             :                                              unsigned TotalArgRegsSaveSize,
    3580             :                                              bool ForceMutable) const {
    3581          30 :   MachineFunction &MF = DAG.getMachineFunction();
    3582          30 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3583             : 
    3584             :   // Try to store any remaining integer argument regs
    3585             :   // to their spots on the stack so that they may be loaded by dereferencing
    3586             :   // the result of va_next.
    3587             :   // If there is no regs to be stored, just point address after last
    3588             :   // argument passed via stack.
    3589          60 :   int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
    3590             :                                   CCInfo.getInRegsParamsCount(),
    3591          60 :                                   CCInfo.getNextStackOffset(), 4);
    3592          60 :   AFI->setVarArgsFrameIndex(FrameIndex);
    3593          30 : }
    3594             : 
    3595       11158 : SDValue ARMTargetLowering::LowerFormalArguments(
    3596             :     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
    3597             :     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
    3598             :     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
    3599       11158 :   MachineFunction &MF = DAG.getMachineFunction();
    3600       11158 :   MachineFrameInfo &MFI = MF.getFrameInfo();
    3601             : 
    3602       11158 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
    3603             : 
    3604             :   // Assign locations to all of the incoming arguments.
    3605       22316 :   SmallVector<CCValAssign, 16> ArgLocs;
    3606             :   CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
    3607       22316 :                  *DAG.getContext());
    3608       11158 :   CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
    3609             : 
    3610       22316 :   SmallVector<SDValue, 16> ArgValues;
    3611       11158 :   SDValue ArgValue;
    3612       22316 :   Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
    3613       11158 :   unsigned CurArgIdx = 0;
    3614             : 
    3615             :   // Initially ArgRegsSaveSize is zero.
    3616             :   // Then we increase this value each time we meet byval parameter.
    3617             :   // We also increase this value in case of varargs function.
    3618       22316 :   AFI->setArgRegsSaveSize(0);
    3619             : 
    3620             :   // Calculate the amount of stack space that we need to allocate to store
    3621             :   // byval and variadic arguments that are passed in registers.
    3622             :   // We need to know this before we allocate the first byval or variadic
    3623             :   // argument, as they will be allocated a stack slot below the CFA (Canonical
    3624             :   // Frame Address, the stack pointer at entry to the function).
    3625       11158 :   unsigned ArgRegBegin = ARM::R4;
    3626       22365 :   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
    3627       17990 :     if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
    3628             :       break;
    3629             : 
    3630          98 :     CCValAssign &VA = ArgLocs[i];
    3631          49 :     unsigned Index = VA.getValNo();
    3632          98 :     ISD::ArgFlagsTy Flags = Ins[Index].Flags;
    3633          49 :     if (!Flags.isByVal())
    3634          20 :       continue;
    3635             : 
    3636             :     assert(VA.isMemLoc() && "unexpected byval pointer in reg");
    3637             :     unsigned RBegin, REnd;
    3638          58 :     CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
    3639          29 :     ArgRegBegin = std::min(ArgRegBegin, RBegin);
    3640             : 
    3641          29 :     CCInfo.nextInRegsParam();
    3642             :   }
    3643       11158 :   CCInfo.rewindByValRegsInfo();
    3644             : 
    3645       11158 :   int lastInsIndex = -1;
    3646       11158 :   if (isVarArg && MFI.hasVAStart()) {
    3647          30 :     unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
    3648          30 :     if (RegIdx != array_lengthof(GPRArgRegs))
    3649          58 :       ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
    3650             :   }
    3651             : 
    3652       11158 :   unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
    3653       22316 :   AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
    3654       33474 :   auto PtrVT = getPointerTy(DAG.getDataLayout());
    3655             : 
    3656       40829 :   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
    3657       37026 :     CCValAssign &VA = ArgLocs[i];
    3658       37026 :     if (Ins[VA.getValNo()].isOrigArg()) {
    3659       36952 :       std::advance(CurOrigArg,
    3660       36952 :                    Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
    3661       36952 :       CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
    3662             :     }
    3663             :     // Arguments stored in registers.
    3664       18513 :     if (VA.isRegLoc()) {
    3665       34262 :       EVT RegVT = VA.getLocVT();
    3666             : 
    3667       17131 :       if (VA.needsCustom()) {
    3668             :         // f64 and vector types are split up into multiple registers or
    3669             :         // combinations of registers and stack slots.
    3670         746 :         if (VA.getLocVT() == MVT::v2f64) {
    3671         394 :           SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
    3672         394 :                                                    Chain, DAG, dl);
    3673         394 :           VA = ArgLocs[++i]; // skip ahead to next loc
    3674         197 :           SDValue ArgValue2;
    3675         197 :           if (VA.isMemLoc()) {
    3676           5 :             int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
    3677           5 :             SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
    3678           5 :             ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
    3679             :                                     MachinePointerInfo::getFixedStack(
    3680          15 :                                         DAG.getMachineFunction(), FI));
    3681             :           } else {
    3682         384 :             ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
    3683             :                                              Chain, DAG, dl);
    3684             :           }
    3685         197 :           ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
    3686         197 :           ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
    3687             :                                  ArgValue, ArgValue1,
    3688         591 :                                  DAG.getIntPtrConstant(0, dl));
    3689         197 :           ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
    3690             :                                  ArgValue, ArgValue2,
    3691         591 :                                  DAG.getIntPtrConstant(1, dl));
    3692             :         } else
    3693        1098 :           ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
    3694             : 
    3695             :       } else {
    3696             :         const TargetRegisterClass *RC;
    3697             : 
    3698       32066 :         if (RegVT == MVT::f32)
    3699             :           RC = &ARM::SPRRegClass;
    3700       30468 :         else if (RegVT == MVT::f64)
    3701             :           RC = &ARM::DPRRegClass;
    3702       29485 :         else if (RegVT == MVT::v2f64)
    3703             :           RC = &ARM::QPRRegClass;
    3704       29396 :         else if (RegVT == MVT::i32)
    3705       14698 :           RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
    3706             :                                            : &ARM::GPRRegClass;
    3707             :         else
    3708           0 :           llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
    3709             : 
    3710             :         // Transform the arguments in physical registers into virtual ones.
    3711       16385 :         unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
    3712       16385 :         ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
    3713             :       }
    3714             : 
    3715             :       // If this is an 8 or 16-bit value, it is really passed promoted
    3716             :       // to 32 bits.  Insert an assert[sz]ext to capture this, then
    3717             :       // truncate to the right size.
    3718       17131 :       switch (VA.getLocInfo()) {
    3719           0 :       default: llvm_unreachable("Unknown loc info!");
    3720             :       case CCValAssign::Full: break;
    3721        1170 :       case CCValAssign::BCvt:
    3722        2340 :         ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
    3723        1170 :         break;
    3724           0 :       case CCValAssign::SExt:
    3725           0 :         ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
    3726           0 :                                DAG.getValueType(VA.getValVT()));
    3727           0 :         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
    3728           0 :         break;
    3729           0 :       case CCValAssign::ZExt:
    3730           0 :         ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
    3731           0 :                                DAG.getValueType(VA.getValVT()));
    3732           0 :         ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
    3733           0 :         break;
    3734             :       }
    3735             : 
    3736       17131 :       InVals.push_back(ArgValue);
    3737             : 
    3738             :     } else { // VA.isRegLoc()
    3739             :       // sanity check
    3740             :       assert(VA.isMemLoc());
    3741             :       assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
    3742             : 
    3743        1382 :       int index = VA.getValNo();
    3744             : 
    3745             :       // Some Ins[] entries become multiple ArgLoc[] entries.
    3746             :       // Process them only once.
    3747        1382 :       if (index != lastInsIndex)
    3748             :         {
    3749        2764 :           ISD::ArgFlagsTy Flags = Ins[index].Flags;
    3750             :           // FIXME: For now, all byval parameter objects are marked mutable.
    3751             :           // This can be changed with more analysis.
    3752             :           // In case of tail call optimization mark all arguments mutable.
    3753             :           // Since they could be overwritten by lowering of arguments in case of
    3754             :           // a tail call.
    3755        1382 :           if (Flags.isByVal()) {
    3756             :             assert(Ins[index].isOrigArg() &&
    3757             :                    "Byval arguments cannot be implicit");
    3758          42 :             unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
    3759             : 
    3760          42 :             int FrameIndex = StoreByValRegs(
    3761             :                 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
    3762          42 :                 VA.getLocMemOffset(), Flags.getByValSize());
    3763          84 :             InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
    3764             :             CCInfo.nextInRegsParam();
    3765             :           } else {
    3766        1340 :             unsigned FIOffset = VA.getLocMemOffset();
    3767        2680 :             int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
    3768        1340 :                                            FIOffset, true);
    3769             : 
    3770             :             // Create load nodes to retrieve arguments from the stack.
    3771        1340 :             SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
    3772        2680 :             InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
    3773             :                                          MachinePointerInfo::getFixedStack(
    3774        4020 :                                              DAG.getMachineFunction(), FI)));
    3775             :           }
    3776        1382 :           lastInsIndex = index;
    3777             :         }
    3778             :     }
    3779             :   }
    3780             : 
    3781             :   // varargs
    3782       11158 :   if (isVarArg && MFI.hasVAStart())
    3783          30 :     VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
    3784             :                          CCInfo.getNextStackOffset(),
    3785             :                          TotalArgRegsSaveSize);
    3786             : 
    3787       22316 :   AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
    3788             : 
    3789       22316 :   return Chain;
    3790             : }
    3791             : 
    3792             : /// isFloatingPointZero - Return true if this is +0.0.
    3793         320 : static bool isFloatingPointZero(SDValue Op) {
    3794          81 :   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
    3795          81 :     return CFP->getValueAPF().isPosZero();
    3796         478 :   else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
    3797             :     // Maybe this has already been legalized into the constant pool?
    3798          81 :     if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
    3799          45 :       SDValue WrapperOp = Op.getOperand(1).getOperand(0);
    3800          15 :       if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
    3801          30 :         if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
    3802          15 :           return CFP->getValueAPF().isPosZero();
    3803             :     }
    3804         212 :   } else if (Op->getOpcode() == ISD::BITCAST &&
    3805          70 :              Op->getValueType(0) == MVT::f64) {
    3806             :     // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
    3807             :     // created by LowerConstantFP().
    3808           4 :     SDValue BitcastOp = Op->getOperand(0);
    3809           4 :     if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
    3810           4 :         isNullConstant(BitcastOp->getOperand(0)))
    3811             :       return true;
    3812             :   }
    3813             :   return false;
    3814             : }
    3815             : 
    3816             : /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
    3817             : /// the given operands.
    3818        2550 : SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
    3819             :                                      SDValue &ARMcc, SelectionDAG &DAG,
    3820             :                                      const SDLoc &dl) const {
    3821        4698 :   if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
    3822        2148 :     unsigned C = RHSC->getZExtValue();
    3823        2148 :     if (!isLegalICmpImmediate(C)) {
    3824             :       // Constant does not fit, try adjusting it by one?
    3825         105 :       switch (CC) {
    3826             :       default: break;
    3827          23 :       case ISD::SETLT:
    3828             :       case ISD::SETGE:
    3829          23 :         if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
    3830           0 :           CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
    3831           0 :           RHS = DAG.getConstant(C - 1, dl, MVT::i32);
    3832             :         }
    3833             :         break;
    3834           1 :       case ISD::SETULT:
    3835             :       case ISD::SETUGE:
    3836           1 :         if (C != 0 && isLegalICmpImmediate(C-1)) {
    3837           1 :           CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
    3838           1 :           RHS = DAG.getConstant(C - 1, dl, MVT::i32);
    3839             :         }
    3840             :         break;
    3841          42 :       case ISD::SETLE:
    3842             :       case ISD::SETGT:
    3843          42 :         if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
    3844          34 :           CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
    3845          34 :           RHS = DAG.getConstant(C + 1, dl, MVT::i32);
    3846             :         }
    3847             :         break;
    3848           1 :       case ISD::SETULE:
    3849             :       case ISD::SETUGT:
    3850           1 :         if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
    3851           0 :           CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
    3852           0 :           RHS = DAG.getConstant(C + 1, dl, MVT::i32);
    3853             :         }
    3854             :         break;
    3855             :       }
    3856             :     }
    3857             :   }
    3858             : 
    3859        2550 :   ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
    3860             :   ARMISD::NodeType CompareType;
    3861        2550 :   switch (CondCode) {
    3862             :   default:
    3863             :     CompareType = ARMISD::CMP;
    3864             :     break;
    3865        1980 :   case ARMCC::EQ:
    3866             :   case ARMCC::NE:
    3867             :     // Uses only Z Flag
    3868        1980 :     CompareType = ARMISD::CMPZ;
    3869        1980 :     break;
    3870             :   }
    3871        2550 :   ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
    3872        5100 :   return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
    3873             : }
    3874             : 
    3875             : /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
    3876         310 : SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
    3877             :                                      SelectionDAG &DAG, const SDLoc &dl,
    3878             :                                      bool InvalidOnQNaN) const {
    3879             :   assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
    3880         310 :   SDValue Cmp;
    3881         310 :   SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
    3882         310 :   if (!isFloatingPointZero(RHS))
    3883         261 :     Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
    3884             :   else
    3885          98 :     Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
    3886         620 :   return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
    3887             : }
    3888             : 
    3889             : /// duplicateCmp - Glue values can have only one use, so this function
    3890             : /// duplicates a comparison node.
    3891             : SDValue
    3892           2 : ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
    3893           4 :   unsigned Opc = Cmp.getOpcode();
    3894           4 :   SDLoc DL(Cmp);
    3895           2 :   if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
    3896           4 :     return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
    3897             : 
    3898             :   assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
    3899           2 :   Cmp = Cmp.getOperand(0);
    3900           2 :   Opc = Cmp.getOpcode();
    3901           1 :   if (Opc == ARMISD::CMPFP)
    3902           0 :     Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
    3903           0 :                       Cmp.getOperand(1), Cmp.getOperand(2));
    3904             :   else {
    3905             :     assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
    3906           3 :     Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
    3907           4 :                       Cmp.getOperand(1));
    3908             :   }
    3909           2 :   return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
    3910             : }
    3911             : 
    3912             : std::pair<SDValue, SDValue>
    3913           4 : ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
    3914             :                                  SDValue &ARMcc) const {
    3915             :   assert(Op.getValueType() == MVT::i32 &&  "Unsupported value type");
    3916             : 
    3917           4 :   SDValue Value, OverflowCmp;
    3918           8 :   SDValue LHS = Op.getOperand(0);
    3919           8 :   SDValue RHS = Op.getOperand(1);
    3920           8 :   SDLoc dl(Op);
    3921             : 
    3922             :   // FIXME: We are currently always generating CMPs because we don't support
    3923             :   // generating CMN through the backend. This is not as good as the natural
    3924             :   // CMP case because it causes a register dependency and cannot be folded
    3925             :   // later.
    3926             : 
    3927           8 :   switch (Op.getOpcode()) {
    3928           0 :   default:
    3929           0 :     llvm_unreachable("Unknown overflow instruction!");
    3930           1 :   case ISD::SADDO:
    3931           1 :     ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
    3932           2 :     Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
    3933           2 :     OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
    3934           1 :     break;
    3935           1 :   case ISD::UADDO:
    3936           1 :     ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
    3937           2 :     Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
    3938           2 :     OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
    3939           1 :     break;
    3940           1 :   case ISD::SSUBO:
    3941           1 :     ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
    3942           2 :     Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
    3943           2 :     OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
    3944           1 :     break;
    3945           1 :   case ISD::USUBO:
    3946           1 :     ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
    3947           2 :     Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
    3948           2 :     OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
    3949           1 :     break;
    3950             :   } // switch (...)
    3951             : 
    3952           8 :   return std::make_pair(Value, OverflowCmp);
    3953             : }
    3954             : 
    3955             : SDValue
    3956           4 : ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
    3957             :   // Let legalize expand this if it isn't a legal type yet.
    3958          12 :   if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
    3959           0 :     return SDValue();
    3960             : 
    3961             :   SDValue Value, OverflowCmp;
    3962           4 :   SDValue ARMcc;
    3963          12 :   std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
    3964           4 :   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    3965           4 :   SDLoc dl(Op);
    3966             :   // We use 0 and 1 as false and true values.
    3967           4 :   SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
    3968           4 :   SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
    3969           8 :   EVT VT = Op.getValueType();
    3970             : 
    3971             :   SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
    3972           4 :                                  ARMcc, CCR, OverflowCmp);
    3973             : 
    3974           8 :   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
    3975           4 :   return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
    3976             : }
    3977             : 
    3978         142 : SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
    3979         284 :   SDValue Cond = Op.getOperand(0);
    3980         284 :   SDValue SelectTrue = Op.getOperand(1);
    3981         284 :   SDValue SelectFalse = Op.getOperand(2);
    3982         284 :   SDLoc dl(Op);
    3983         284 :   unsigned Opc = Cond.getOpcode();
    3984             : 
    3985         143 :   if (Cond.getResNo() == 1 &&
    3986           1 :       (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
    3987             :        Opc == ISD::USUBO)) {
    3988           0 :     if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
    3989           0 :       return SDValue();
    3990             : 
    3991             :     SDValue Value, OverflowCmp;
    3992           0 :     SDValue ARMcc;
    3993           0 :     std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
    3994           0 :     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    3995           0 :     EVT VT = Op.getValueType();
    3996             : 
    3997             :     return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
    3998           0 :                    OverflowCmp, DAG);
    3999             :   }
    4000             : 
    4001             :   // Convert:
    4002             :   //
    4003             :   //   (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
    4004             :   //   (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
    4005             :   //
    4006         284 :   if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
    4007             :     const ConstantSDNode *CMOVTrue =
    4008           0 :       dyn_cast<ConstantSDNode>(Cond.getOperand(0));
    4009             :     const ConstantSDNode *CMOVFalse =
    4010           0 :       dyn_cast<ConstantSDNode>(Cond.getOperand(1));
    4011             : 
    4012           0 :     if (CMOVTrue && CMOVFalse) {
    4013           0 :       unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
    4014           0 :       unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
    4015             : 
    4016           0 :       SDValue True;
    4017           0 :       SDValue False;
    4018           0 :       if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
    4019           0 :         True = SelectTrue;
    4020           0 :         False = SelectFalse;
    4021           0 :       } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
    4022           0 :         True = SelectFalse;
    4023           0 :         False = SelectTrue;
    4024             :       }
    4025             : 
    4026           0 :       if (True.getNode() && False.getNode()) {
    4027           0 :         EVT VT = Op.getValueType();
    4028           0 :         SDValue ARMcc = Cond.getOperand(2);
    4029           0 :         SDValue CCR = Cond.getOperand(3);
    4030           0 :         SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
    4031             :         assert(True.getValueType() == VT);
    4032           0 :         return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
    4033             :       }
    4034             :     }
    4035             :   }
    4036             : 
    4037             :   // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
    4038             :   // undefined bits before doing a full-word comparison with zero.
    4039         142 :   Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
    4040         426 :                      DAG.getConstant(1, dl, Cond.getValueType()));
    4041             : 
    4042             :   return DAG.getSelectCC(dl, Cond,
    4043             :                          DAG.getConstant(0, dl, Cond.getValueType()),
    4044         284 :                          SelectTrue, SelectFalse, ISD::SETNE);
    4045             : }
    4046             : 
    4047          44 : static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
    4048             :                                  bool &swpCmpOps, bool &swpVselOps) {
    4049             :   // Start by selecting the GE condition code for opcodes that return true for
    4050             :   // 'equality'
    4051          77 :   if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
    4052          33 :       CC == ISD::SETULE)
    4053          20 :     CondCode = ARMCC::GE;
    4054             : 
    4055             :   // and GT for opcodes that return false for 'equality'.
    4056          40 :   else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
    4057          16 :            CC == ISD::SETULT)
    4058          16 :     CondCode = ARMCC::GT;
    4059             : 
    4060             :   // Since we are constrained to GE/GT, if the opcode contains 'less', we need
    4061             :   // to swap the compare operands.
    4062          79 :   if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
    4063          35 :       CC == ISD::SETULT)
    4064          17 :     swpCmpOps = true;
    4065             : 
    4066             :   // Both GT and GE are ordered comparisons, and return false for 'unordered'.
    4067             :   // If we have an unordered opcode, we need to swap the operands to the VSEL
    4068             :   // instruction (effectively negating the condition).
    4069             :   //
    4070             :   // This also has the effect of swapping which one of 'less' or 'greater'
    4071             :   // returns true, so we also swap the compare operands. It also switches
    4072             :   // whether we return true for 'equality', so we compensate by picking the
    4073             :   // opposite condition code to our original choice.
    4074          44 :   if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
    4075             :       CC == ISD::SETUGT) {
    4076          18 :     swpCmpOps = !swpCmpOps;
    4077          18 :     swpVselOps = !swpVselOps;
    4078          18 :     CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
    4079             :   }
    4080             : 
    4081             :   // 'ordered' is 'anything but unordered', so use the VS condition code and
    4082             :   // swap the VSEL operands.
    4083          44 :   if (CC == ISD::SETO) {
    4084           2 :     CondCode = ARMCC::VS;
    4085           2 :     swpVselOps = true;
    4086             :   }
    4087             : 
    4088             :   // 'unordered or not equal' is 'anything but equal', so use the EQ condition
    4089             :   // code and swap the VSEL operands.
    4090          44 :   if (CC == ISD::SETUNE) {
    4091           2 :     CondCode = ARMCC::EQ;
    4092           2 :     swpVselOps = true;
    4093             :   }
    4094          44 : }
    4095             : 
    4096        1094 : SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
    4097             :                                    SDValue TrueVal, SDValue ARMcc, SDValue CCR,
    4098             :                                    SDValue Cmp, SelectionDAG &DAG) const {
    4099        1161 :   if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
    4100           2 :     FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
    4101           6 :                            DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
    4102           2 :     TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
    4103           6 :                           DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
    4104             : 
    4105           4 :     SDValue TrueLow = TrueVal.getValue(0);
    4106           4 :     SDValue TrueHigh = TrueVal.getValue(1);
    4107           4 :     SDValue FalseLow = FalseVal.getValue(0);
    4108           4 :     SDValue FalseHigh = FalseVal.getValue(1);
    4109             : 
    4110             :     SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
    4111           2 :                               ARMcc, CCR, Cmp);
    4112             :     SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
    4113           4 :                                ARMcc, CCR, duplicateCmp(Cmp, DAG));
    4114             : 
    4115           4 :     return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
    4116             :   } else {
    4117             :     return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
    4118        1092 :                        Cmp);
    4119             :   }
    4120             : }
    4121             : 
    4122             : static bool isGTorGE(ISD::CondCode CC) {
    4123          36 :   return CC == ISD::SETGT || CC == ISD::SETGE;
    4124             : }
    4125             : 
    4126             : static bool isLTorLE(ISD::CondCode CC) {
    4127          24 :   return CC == ISD::SETLT || CC == ISD::SETLE;
    4128             : }
    4129             : 
    4130             : // See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
    4131             : // All of these conditions (and their <= and >= counterparts) will do:
    4132             : //          x < k ? k : x
    4133             : //          x > k ? x : k
    4134             : //          k < x ? x : k
    4135             : //          k > x ? k : x
    4136          18 : static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
    4137             :                             const SDValue TrueVal, const SDValue FalseVal,
    4138             :                             const ISD::CondCode CC, const SDValue K) {
    4139          18 :   return (isGTorGE(CC) &&
    4140          42 :           ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
    4141          15 :          (isLTorLE(CC) &&
    4142          27 :           ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
    4143             : }
    4144             : 
    4145             : // Similar to isLowerSaturate(), but checks for upper-saturating conditions.
    4146          18 : static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
    4147             :                             const SDValue TrueVal, const SDValue FalseVal,
    4148             :                             const ISD::CondCode CC, const SDValue K) {
    4149          18 :   return (isGTorGE(CC) &&
    4150          37 :           ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
    4151           9 :          (isLTorLE(CC) &&
    4152          26 :           ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
    4153             : }
    4154             : 
    4155             : // Check if two chained conditionals could be converted into SSAT.
    4156             : //
    4157             : // SSAT can replace a set of two conditional selectors that bound a number to an
    4158             : // interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
    4159             : //
    4160             : //     x < -k ? -k : (x > k ? k : x)
    4161             : //     x < -k ? -k : (x < k ? x : k)
    4162             : //     x > -k ? (x > k ? k : x) : -k
    4163             : //     x < k ? (x < -k ? -k : x) : k
    4164             : //     etc.
    4165             : //
    4166             : // It returns true if the conversion can be done, false otherwise.
    4167             : // Additionally, the variable is returned in parameter V and the constant in K.
    4168         737 : static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
    4169             :                                     uint64_t &K) {
    4170        1474 :   SDValue LHS1 = Op.getOperand(0);
    4171        1474 :   SDValue RHS1 = Op.getOperand(1);
    4172        1474 :   SDValue TrueVal1 = Op.getOperand(2);
    4173        1474 :   SDValue FalseVal1 = Op.getOperand(3);
    4174        2211 :   ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
    4175             : 
    4176         402 :   const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
    4177        1474 :   if (Op2.getOpcode() != ISD::SELECT_CC)
    4178             :     return false;
    4179             : 
    4180          38 :   SDValue LHS2 = Op2.getOperand(0);
    4181          38 :   SDValue RHS2 = Op2.getOperand(1);
    4182          38 :   SDValue TrueVal2 = Op2.getOperand(2);
    4183          38 :   SDValue FalseVal2 = Op2.getOperand(3);
    4184          57 :   ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
    4185             : 
    4186             :   // Find out which are the constants and which are the variables
    4187             :   // in each conditional
    4188          19 :   SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
    4189             :                                                         ? &RHS1
    4190          19 :                                                         : nullptr;
    4191          19 :   SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
    4192             :                                                         ? &RHS2
    4193          19 :                                                         : nullptr;
    4194           5 :   SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
    4195          38 :   SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
    4196          38 :   SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
    4197          14 :   SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
    4198             : 
    4199             :   // We must detect cases where the original operations worked with 16- or
    4200             :   // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
    4201             :   // must work with sign-extended values but the select operations return
    4202             :   // the original non-extended value.
    4203          19 :   SDValue V2TmpReg = V2Tmp;
    4204          19 :   if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
    4205           4 :     V2TmpReg = V2Tmp->getOperand(0);
    4206             : 
    4207             :   // Check that the registers and the constants have the correct values
    4208             :   // in both conditionals
    4209          65 :   if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
    4210          12 :       V2TmpReg != V2)
    4211             :     return false;
    4212             : 
    4213             :   // Figure out which conditional is saturating the lower/upper bound.
    4214             :   const SDValue *LowerCheckOp =
    4215          12 :       isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
    4216          12 :           ? &Op
    4217           6 :           : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
    4218           6 :                 ? &Op2
    4219          12 :                 : nullptr;
    4220             :   const SDValue *UpperCheckOp =
    4221          12 :       isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
    4222          12 :           ? &Op
    4223           6 :           : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
    4224           6 :                 ? &Op2
    4225          12 :                 : nullptr;
    4226             : 
    4227          12 :   if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
    4228             :     return false;
    4229             : 
    4230             :   // Check that the constant in the lower-bound check is
    4231             :   // the opposite of the constant in the upper-bound check
    4232             :   // in 1's complement.
    4233          20 :   int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
    4234          20 :   int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
    4235          10 :   int64_t PosVal = std::max(Val1, Val2);
    4236             : 
    4237           5 :   if (((Val1 > Val2 && UpperCheckOp == &Op) ||
    4238          15 :        (Val1 < Val2 && UpperCheckOp == &Op2)) &&
    4239          38 :       Val1 == ~Val2 && isPowerOf2_64(PosVal + 1)) {
    4240             : 
    4241           9 :     V = V2;
    4242           9 :     K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
    4243           9 :     return true;
    4244             :   }
    4245             : 
    4246             :   return false;
    4247             : }
    4248             : 
    4249        1090 : SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
    4250        2180 :   EVT VT = Op.getValueType();
    4251        2180 :   SDLoc dl(Op);
    4252             : 
    4253             :   // Try to convert two saturating conditional selects into a single SSAT
    4254        1090 :   SDValue SatValue;
    4255             :   uint64_t SatConstant;
    4256        1827 :   if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
    4257         737 :       isSaturatingConditional(Op, SatValue, SatConstant))
    4258             :     return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
    4259          18 :                        DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
    4260             : 
    4261        2162 :   SDValue LHS = Op.getOperand(0);
    4262        2162 :   SDValue RHS = Op.getOperand(1);
    4263        3243 :   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
    4264        2162 :   SDValue TrueVal = Op.getOperand(2);
    4265        2162 :   SDValue FalseVal = Op.getOperand(3);
    4266             : 
    4267        1211 :   if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
    4268          56 :     DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
    4269          28 :                                                     dl);
    4270             : 
    4271             :     // If softenSetCCOperands only returned one value, we should compare it to
    4272             :     // zero.
    4273          28 :     if (!RHS.getNode()) {
    4274           4 :       RHS = DAG.getConstant(0, dl, LHS.getValueType());
    4275           2 :       CC = ISD::SETNE;
    4276             :     }
    4277             :   }
    4278             : 
    4279        3243 :   if (LHS.getValueType() == MVT::i32) {
    4280             :     // Try to generate VSEL on ARMv8.
    4281             :     // The VSEL instruction can't use all the usual ARM condition
    4282             :     // codes: it only has two bits to select the condition code, so it's
    4283             :     // constrained to use only GE, GT, VS and EQ.
    4284             :     //
    4285             :     // To implement all the various ISD::SETXXX opcodes, we sometimes need to
    4286             :     // swap the operands of the previous compare instruction (effectively
    4287             :     // inverting the compare condition, swapping 'less' and 'greater') and
    4288             :     // sometimes need to swap the operands to the VSEL (which inverts the
    4289             :     // condition in the sense of firing whenever the previous condition didn't)
    4290        1093 :     if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
    4291         252 :                                     TrueVal.getValueType() == MVT::f64)) {
    4292          16 :       ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
    4293          16 :       if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
    4294          12 :           CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
    4295           6 :         CC = ISD::getSetCCInverse(CC, true);
    4296             :         std::swap(TrueVal, FalseVal);
    4297             :       }
    4298             :     }
    4299             : 
    4300         827 :     SDValue ARMcc;
    4301         827 :     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4302         827 :     SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
    4303         827 :     return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
    4304             :   }
    4305             : 
    4306             :   ARMCC::CondCodes CondCode, CondCode2;
    4307             :   bool InvalidOnQNaN;
    4308         254 :   FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
    4309             : 
    4310             :   // Try to generate VMAXNM/VMINNM on ARMv8.
    4311         406 :   if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
    4312         104 :                                   TrueVal.getValueType() == MVT::f64)) {
    4313          44 :     bool swpCmpOps = false;
    4314          44 :     bool swpVselOps = false;
    4315          44 :     checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
    4316             : 
    4317          44 :     if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
    4318           4 :         CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
    4319          44 :       if (swpCmpOps)
    4320             :         std::swap(LHS, RHS);
    4321          44 :       if (swpVselOps)
    4322             :         std::swap(TrueVal, FalseVal);
    4323             :     }
    4324             :   }
    4325             : 
    4326         254 :   SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
    4327         254 :   SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
    4328         254 :   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4329         254 :   SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
    4330         254 :   if (CondCode2 != ARMCC::AL) {
    4331          13 :     SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
    4332             :     // FIXME: Needs another CMP because flag can have but one use.
    4333          13 :     SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
    4334          13 :     Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
    4335             :   }
    4336         254 :   return Result;
    4337             : }
    4338             : 
    4339             : /// canChangeToInt - Given the fp compare operand, return true if it is suitable
    4340             : /// to morph to an integer compare sequence.
    4341           6 : static bool canChangeToInt(SDValue Op, bool &SeenZero,
    4342             :                            const ARMSubtarget *Subtarget) {
    4343           6 :   SDNode *N = Op.getNode();
    4344           6 :   if (!N->hasOneUse())
    4345             :     // Otherwise it requires moving the value from fp to integer registers.
    4346             :     return false;
    4347           6 :   if (!N->getNumValues())
    4348             :     return false;
    4349          12 :   EVT VT = Op.getValueType();
    4350           8 :   if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
    4351             :     // f32 case is generally profitable. f64 case only makes sense when vcmpe +
    4352             :     // vmrs are very slow, e.g. cortex-a8.
    4353             :     return false;
    4354             : 
    4355           6 :   if (isFloatingPointZero(Op)) {
    4356           2 :     SeenZero = true;
    4357             :     return true;
    4358             :   }
    4359             :   return ISD::isNormalLoad(N);
    4360             : }
    4361             : 
    4362           2 : static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
    4363           2 :   if (isFloatingPointZero(Op))
    4364           3 :     return DAG.getConstant(0, SDLoc(Op), MVT::i32);
    4365             : 
    4366           1 :   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
    4367           4 :     return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
    4368           2 :                        Ld->getPointerInfo(), Ld->getAlignment(),
    4369           3 :                        Ld->getMemOperand()->getFlags());
    4370             : 
    4371           0 :   llvm_unreachable("Unknown VFP cmp argument!");
    4372             : }
    4373             : 
    4374           2 : static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
    4375             :                            SDValue &RetVal1, SDValue &RetVal2) {
    4376           4 :   SDLoc dl(Op);
    4377             : 
    4378           2 :   if (isFloatingPointZero(Op)) {
    4379           1 :     RetVal1 = DAG.getConstant(0, dl, MVT::i32);
    4380           1 :     RetVal2 = DAG.getConstant(0, dl, MVT::i32);
    4381             :     return;
    4382             :   }
    4383             : 
    4384           1 :   if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
    4385           1 :     SDValue Ptr = Ld->getBasePtr();
    4386           1 :     RetVal1 =
    4387           5 :         DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
    4388           3 :                     Ld->getAlignment(), Ld->getMemOperand()->getFlags());
    4389             : 
    4390           2 :     EVT PtrType = Ptr.getValueType();
    4391           3 :     unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
    4392             :     SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
    4393           1 :                                  PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
    4394           3 :     RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
    4395           2 :                           Ld->getPointerInfo().getWithOffset(4), NewAlign,
    4396           4 :                           Ld->getMemOperand()->getFlags());
    4397             :     return;
    4398             :   }
    4399             : 
    4400           0 :   llvm_unreachable("Unknown VFP cmp argument!");
    4401             : }
    4402             : 
    4403             : /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
    4404             : /// f32 and even f64 comparisons to integer ones.
    4405             : SDValue
    4406           3 : ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
    4407           6 :   SDValue Chain = Op.getOperand(0);
    4408           9 :   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
    4409           6 :   SDValue LHS = Op.getOperand(2);
    4410           6 :   SDValue RHS = Op.getOperand(3);
    4411           6 :   SDValue Dest = Op.getOperand(4);
    4412           6 :   SDLoc dl(Op);
    4413             : 
    4414           3 :   bool LHSSeenZero = false;
    4415           3 :   bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
    4416           3 :   bool RHSSeenZero = false;
    4417           3 :   bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
    4418           3 :   if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
    4419             :     // If unsafe fp math optimization is enabled and there are no other uses of
    4420             :     // the CMP operands, and the condition code is EQ or NE, we can optimize it
    4421             :     // to an integer comparison.
    4422           2 :     if (CC == ISD::SETOEQ)
    4423             :       CC = ISD::SETEQ;
    4424           2 :     else if (CC == ISD::SETUNE)
    4425           2 :       CC = ISD::SETNE;
    4426             : 
    4427           2 :     SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
    4428           2 :     SDValue ARMcc;
    4429           6 :     if (LHS.getValueType() == MVT::f32) {
    4430           1 :       LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
    4431           3 :                         bitcastf32Toi32(LHS, DAG), Mask);
    4432           1 :       RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
    4433           3 :                         bitcastf32Toi32(RHS, DAG), Mask);
    4434           1 :       SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
    4435           1 :       SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4436             :       return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
    4437           1 :                          Chain, Dest, ARMcc, CCR, Cmp);
    4438             :     }
    4439             : 
    4440           1 :     SDValue LHS1, LHS2;
    4441           1 :     SDValue RHS1, RHS2;
    4442           1 :     expandf64Toi32(LHS, DAG, LHS1, LHS2);
    4443           1 :     expandf64Toi32(RHS, DAG, RHS1, RHS2);
    4444           2 :     LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
    4445           2 :     RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
    4446           1 :     ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
    4447           1 :     ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
    4448           2 :     SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
    4449           1 :     SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
    4450           1 :     return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
    4451             :   }
    4452             : 
    4453           1 :   return SDValue();
    4454             : }
    4455             : 
    4456        1737 : SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
    4457        3474 :   SDValue Chain = Op.getOperand(0);
    4458        5211 :   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
    4459        3474 :   SDValue LHS = Op.getOperand(2);
    4460        3474 :   SDValue RHS = Op.getOperand(3);
    4461        3474 :   SDValue Dest = Op.getOperand(4);
    4462        3474 :   SDLoc dl(Op);
    4463             : 
    4464        1739 :   if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
    4465           0 :     DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
    4466           0 :                                                     dl);
    4467             : 
    4468             :     // If softenSetCCOperands only returned one value, we should compare it to
    4469             :     // zero.
    4470           0 :     if (!RHS.getNode()) {
    4471           0 :       RHS = DAG.getConstant(0, dl, LHS.getValueType());
    4472           0 :       CC = ISD::SETNE;
    4473             :     }
    4474             :   }
    4475             : 
    4476        5211 :   if (LHS.getValueType() == MVT::i32) {
    4477        1692 :     SDValue ARMcc;
    4478        1692 :     SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
    4479        1692 :     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4480             :     return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
    4481        1692 :                        Chain, Dest, ARMcc, CCR, Cmp);
    4482             :   }
    4483             : 
    4484             :   assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
    4485             : 
    4486          93 :   if (getTargetMachine().Options.UnsafeFPMath &&
    4487           5 :       (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
    4488          47 :        CC == ISD::SETNE || CC == ISD::SETUNE)) {
    4489           3 :     if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
    4490           2 :       return Result;
    4491             :   }
    4492             : 
    4493             :   ARMCC::CondCodes CondCode, CondCode2;
    4494             :   bool InvalidOnQNaN;
    4495          43 :   FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
    4496             : 
    4497          43 :   SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
    4498          43 :   SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
    4499          43 :   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4500          86 :   SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
    4501          43 :   SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
    4502          43 :   SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
    4503          43 :   if (CondCode2 != ARMCC::AL) {
    4504           2 :     ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
    4505           4 :     SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
    4506           2 :     Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
    4507             :   }
    4508          43 :   return Res;
    4509             : }
    4510             : 
    4511          37 : SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
    4512          74 :   SDValue Chain = Op.getOperand(0);
    4513          74 :   SDValue Table = Op.getOperand(1);
    4514          74 :   SDValue Index = Op.getOperand(2);
    4515          74 :   SDLoc dl(Op);
    4516             : 
    4517         148 :   EVT PTy = getPointerTy(DAG.getDataLayout());
    4518          37 :   JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
    4519          74 :   SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
    4520          74 :   Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
    4521          37 :   Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
    4522          37 :   SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
    4523          59 :   if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
    4524             :     // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
    4525             :     // which does another jump to the destination. This also makes it easier
    4526             :     // to translate it to TBB / TBH later (Thumb2 only).
    4527             :     // FIXME: This might not work if the function is extremely large.
    4528             :     return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
    4529          54 :                        Addr, Op.getOperand(2), JTI);
    4530             :   }
    4531          19 :   if (isPositionIndependent() || Subtarget->isROPI()) {
    4532          11 :     Addr =
    4533          22 :         DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
    4534          33 :                     MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
    4535          22 :     Chain = Addr.getValue(1);
    4536          11 :     Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
    4537          11 :     return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
    4538             :   } else {
    4539           8 :     Addr =
    4540          16 :         DAG.getLoad(PTy, dl, Chain, Addr,
    4541          16 :                     MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
    4542          16 :     Chain = Addr.getValue(1);
    4543           8 :     return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
    4544             :   }
    4545             : }
    4546             : 
    4547          73 : static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
    4548         146 :   EVT VT = Op.getValueType();
    4549         146 :   SDLoc dl(Op);
    4550             : 
    4551         219 :   if (Op.getValueType().getVectorElementType() == MVT::i32) {
    4552         288 :     if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
    4553          66 :       return Op;
    4554           6 :     return DAG.UnrollVectorOp(Op.getNode());
    4555             :   }
    4556             : 
    4557             :   assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
    4558             :          "Invalid type for custom lowering!");
    4559           1 :   if (VT != MVT::v4i16)
    4560           0 :     return DAG.UnrollVectorOp(Op.getNode());
    4561             : 
    4562           4 :   Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
    4563           1 :   return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
    4564             : }
    4565             : 
    4566          93 : SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
    4567         186 :   EVT VT = Op.getValueType();
    4568          93 :   if (VT.isVector())
    4569          73 :     return LowerVectorFP_TO_INT(Op, DAG);
    4570          80 :   if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
    4571             :     RTLIB::Libcall LC;
    4572          16 :     if (Op.getOpcode() == ISD::FP_TO_SINT)
    4573          12 :       LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
    4574             :                               Op.getValueType());
    4575             :     else
    4576          20 :       LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
    4577             :                               Op.getValueType());
    4578          16 :     return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
    4579          56 :                        /*isSigned*/ false, SDLoc(Op)).first;
    4580             :   }
    4581             : 
    4582          12 :   return Op;
    4583             : }
    4584             : 
    4585         145 : static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
    4586         290 :   EVT VT = Op.getValueType();
    4587         290 :   SDLoc dl(Op);
    4588             : 
    4589         580 :   if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
    4590         276 :     if (VT.getVectorElementType() == MVT::f32)
    4591         126 :       return Op;
    4592          12 :     return DAG.UnrollVectorOp(Op.getNode());
    4593             :   }
    4594             : 
    4595             :   assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
    4596             :          "Invalid type for custom lowering!");
    4597           7 :   if (VT != MVT::v4f32)
    4598           0 :     return DAG.UnrollVectorOp(Op.getNode());
    4599             : 
    4600             :   unsigned CastOpc;
    4601             :   unsigned Opc;
    4602          14 :   switch (Op.getOpcode()) {
    4603           0 :   default: llvm_unreachable("Invalid opcode!");
    4604             :   case ISD::SINT_TO_FP:
    4605             :     CastOpc = ISD::SIGN_EXTEND;
    4606             :     Opc = ISD::SINT_TO_FP;
    4607             :     break;
    4608           4 :   case ISD::UINT_TO_FP:
    4609           4 :     CastOpc = ISD::ZERO_EXTEND;
    4610           4 :     Opc = ISD::UINT_TO_FP;
    4611           4 :     break;
    4612             :   }
    4613             : 
    4614          21 :   Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
    4615           7 :   return DAG.getNode(Opc, dl, VT, Op);
    4616             : }
    4617             : 
    4618         165 : SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
    4619         330 :   EVT VT = Op.getValueType();
    4620         165 :   if (VT.isVector())
    4621         145 :     return LowerVectorINT_TO_FP(Op, DAG);
    4622          60 :   if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
    4623             :     RTLIB::Libcall LC;
    4624          16 :     if (Op.getOpcode() == ISD::SINT_TO_FP)
    4625          20 :       LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
    4626             :                               Op.getValueType());
    4627             :     else
    4628          12 :       LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
    4629             :                               Op.getValueType());
    4630          16 :     return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
    4631          56 :                        /*isSigned*/ false, SDLoc(Op)).first;
    4632             :   }
    4633             : 
    4634          12 :   return Op;
    4635             : }
    4636             : 
    4637          22 : SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
    4638             :   // Implement fcopysign with a fabs and a conditional fneg.
    4639          44 :   SDValue Tmp0 = Op.getOperand(0);
    4640          44 :   SDValue Tmp1 = Op.getOperand(1);
    4641          44 :   SDLoc dl(Op);
    4642          44 :   EVT VT = Op.getValueType();
    4643          44 :   EVT SrcVT = Tmp1.getValueType();
    4644          65 :   bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
    4645          41 :     Tmp0.getOpcode() == ARMISD::VMOVDRR;
    4646          32 :   bool UseNEON = !InGPR && Subtarget->hasNEON();
    4647             : 
    4648             :   if (UseNEON) {
    4649             :     // Use VBSL to copy the sign bit.
    4650          12 :     unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
    4651             :     SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
    4652          48 :                                DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
    4653          24 :     EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
    4654          24 :     if (VT == MVT::f64)
    4655           5 :       Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
    4656             :                          DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
    4657          20 :                          DAG.getConstant(32, dl, MVT::i32));
    4658             :     else /*if (VT == MVT::f32)*/
    4659          14 :       Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
    4660          24 :     if (SrcVT == MVT::f32) {
    4661          10 :       Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
    4662          10 :       if (VT == MVT::f64)
    4663           0 :         Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
    4664             :                            DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
    4665           0 :                            DAG.getConstant(32, dl, MVT::i32));
    4666          12 :     } else if (VT == MVT::f32)
    4667           2 :       Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
    4668           2 :                          DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
    4669          12 :                          DAG.getConstant(32, dl, MVT::i32));
    4670          12 :     Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
    4671          12 :     Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
    4672             : 
    4673          12 :     SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
    4674          36 :                                             dl, MVT::i32);
    4675          24 :     AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
    4676             :     SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
    4677          24 :                                   DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
    4678             : 
    4679             :     SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
    4680             :                               DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
    4681          36 :                               DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
    4682          24 :     if (VT == MVT::f32) {
    4683          14 :       Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
    4684           7 :       Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
    4685          28 :                         DAG.getConstant(0, dl, MVT::i32));
    4686             :     } else {
    4687          10 :       Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
    4688             :     }
    4689             : 
    4690          12 :     return Res;
    4691             :   }
    4692             : 
    4693             :   // Bitcast operand 1 to i32.
    4694          14 :   if (SrcVT == MVT::f64)
    4695          24 :     Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
    4696          24 :                        Tmp1).getValue(1);
    4697          20 :   Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
    4698             : 
    4699             :   // Or in the signbit with integer operations.
    4700          10 :   SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
    4701          10 :   SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
    4702          20 :   Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
    4703          20 :   if (VT == MVT::f32) {
    4704           4 :     Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
    4705          20 :                        DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
    4706             :     return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
    4707          16 :                        DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
    4708             :   }
    4709             : 
    4710             :   // f64: Or the high part with signbit and then combine two parts.
    4711          18 :   Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
    4712          12 :                      Tmp0);
    4713          12 :   SDValue Lo = Tmp0.getValue(0);
    4714          18 :   SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
    4715          12 :   Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
    4716          12 :   return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
    4717             : }
    4718             : 
    4719          12 : SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
    4720          12 :   MachineFunction &MF = DAG.getMachineFunction();
    4721          12 :   MachineFrameInfo &MFI = MF.getFrameInfo();
    4722          12 :   MFI.setReturnAddressIsTaken(true);
    4723             : 
    4724          12 :   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
    4725           0 :     return SDValue();
    4726             : 
    4727          24 :   EVT VT = Op.getValueType();
    4728          12 :   SDLoc dl(Op);
    4729          48 :   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
    4730          12 :   if (Depth) {
    4731           4 :     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
    4732           4 :     SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
    4733             :     return DAG.getLoad(VT, dl, DAG.getEntryNode(),
    4734             :                        DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
    4735          16 :                        MachinePointerInfo());
    4736             :   }
    4737             : 
    4738             :   // Return LR, which contains the return address. Mark it an implicit live-in.
    4739          16 :   unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
    4740           8 :   return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
    4741             : }
    4742             : 
    4743          42 : SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
    4744          42 :   const ARMBaseRegisterInfo &ARI =
    4745             :     *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
    4746          42 :   MachineFunction &MF = DAG.getMachineFunction();
    4747          42 :   MachineFrameInfo &MFI = MF.getFrameInfo();
    4748          42 :   MFI.setFrameAddressIsTaken(true);
    4749             : 
    4750          84 :   EVT VT = Op.getValueType();
    4751          84 :   SDLoc dl(Op);  // FIXME probably not meaningful
    4752         168 :   unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
    4753          42 :   unsigned FrameReg = ARI.getFrameRegister(MF);
    4754          42 :   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
    4755          66 :   while (Depth--)
    4756          12 :     FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
    4757          48 :                             MachinePointerInfo());
    4758          84 :   return FrameAddr;
    4759             : }
    4760             : 
    4761             : // FIXME? Maybe this could be a TableGen attribute on some registers and
    4762             : // this table could be generated automatically from RegInfo.
    4763          13 : unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
    4764             :                                               SelectionDAG &DAG) const {
    4765          13 :   unsigned Reg = StringSwitch<unsigned>(RegName)
    4766          39 :                        .Case("sp", ARM::SP)
    4767          26 :                        .Default(0);
    4768           4 :   if (Reg)
    4769           4 :     return Reg;
    4770           9 :   report_fatal_error(Twine("Invalid register name \""
    4771          27 :                               + StringRef(RegName)  + "\"."));
    4772             : }
    4773             : 
    4774             : // Result is 64 bit value so split into two 32 bit values and return as a
    4775             : // pair of values.
    4776           2 : static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
    4777             :                                 SelectionDAG &DAG) {
    4778           4 :   SDLoc DL(N);
    4779             : 
    4780             :   // This function is only supposed to be called for i64 type destination.
    4781             :   assert(N->getValueType(0) == MVT::i64
    4782             :           && "ExpandREAD_REGISTER called for non-i64 type result.");
    4783             : 
    4784             :   SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
    4785           6 :                              DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
    4786           4 :                              N->getOperand(0),
    4787           6 :                              N->getOperand(1));
    4788             : 
    4789           4 :   Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
    4790          10 :                     Read.getValue(1)));
    4791           4 :   Results.push_back(Read.getOperand(0));
    4792           2 : }
    4793             : 
    4794             : /// \p BC is a bitcast that is about to be turned into a VMOVDRR.
    4795             : /// When \p DstVT, the destination type of \p BC, is on the vector
    4796             : /// register bank and the source of bitcast, \p Op, operates on the same bank,
    4797             : /// it might be possible to combine them, such that everything stays on the
    4798             : /// vector register bank.
    4799             : /// \p return The node that would replace \p BT, if the combine
    4800             : /// is possible.
    4801          53 : static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
    4802             :                                                 SelectionDAG &DAG) {
    4803         106 :   SDValue Op = BC->getOperand(0);
    4804         106 :   EVT DstVT = BC->getValueType(0);
    4805             : 
    4806             :   // The only vector instruction that can produce a scalar (remember,
    4807             :   // since the bitcast was about to be turned into VMOVDRR, the source
    4808             :   // type is i64) from a vector is EXTRACT_VECTOR_ELT.
    4809             :   // Moreover, we can do this combine only if there is one use.
    4810             :   // Finally, if the destination type is not a vector, there is not
    4811             :   // much point on forcing everything on the vector bank.
    4812          97 :   if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
    4813           6 :       !Op.hasOneUse())
    4814          48 :     return SDValue();
    4815             : 
    4816             :   // If the index is not constant, we will introduce an additional
    4817             :   // multiply that will stick.
    4818             :   // Give up in that case.
    4819          14 :   ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
    4820             :   if (!Index)
    4821           1 :     return SDValue();
    4822           4 :   unsigned DstNumElt = DstVT.getVectorNumElements();
    4823             : 
    4824             :   // Compute the new index.
    4825           4 :   const APInt &APIntIndex = Index->getAPIntValue();
    4826           8 :   APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
    4827           4 :   NewIndex *= APIntIndex;
    4828             :   // Check if the new constant index fits into i32.
    4829           4 :   if (NewIndex.getBitWidth() > 32)
    4830           0 :     return SDValue();
    4831             : 
    4832             :   // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
    4833             :   // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
    4834           4 :   SDLoc dl(Op);
    4835           8 :   SDValue ExtractSrc = Op.getOperand(0);
    4836             :   EVT VecVT = EVT::getVectorVT(
    4837           4 :       *DAG.getContext(), DstVT.getScalarType(),
    4838          12 :       ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
    4839           4 :   SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
    4840             :   return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
    4841          12 :                      DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
    4842             : }
    4843             : 
    4844             : /// ExpandBITCAST - If the target supports VFP, this function is called to
    4845             : /// expand a bit convert where either the source or destination type is i64 to
    4846             : /// use a VMOVDRR or VMOVRRD node.  This should not be done when the non-i64
    4847             : /// operand type is illegal (e.g., v2f32 for a target that doesn't support
    4848             : /// vectors), since the legalizer won't know what to do with that.
    4849          80 : static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
    4850          80 :   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
    4851         160 :   SDLoc dl(N);
    4852         160 :   SDValue Op = N->getOperand(0);
    4853             : 
    4854             :   // This function is only supposed to be called for i64 types, either as the
    4855             :   // source or destination of the bit convert.
    4856         160 :   EVT SrcVT = Op.getValueType();
    4857         160 :   EVT DstVT = N->getValueType(0);
    4858             :   assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
    4859             :          "ExpandBITCAST called for non-i64 type");
    4860             : 
    4861             :   // Turn i64->f64 into VMOVDRR.
    4862         186 :   if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
    4863             :     // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
    4864             :     // if we can combine the bitcast with its source.
    4865          53 :     if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
    4866           4 :       return Val;
    4867             : 
    4868             :     SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
    4869         147 :                              DAG.getConstant(0, dl, MVT::i32));
    4870             :     SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
    4871         147 :                              DAG.getConstant(1, dl, MVT::i32));
    4872             :     return DAG.getNode(ISD::BITCAST, dl, DstVT,
    4873         147 :                        DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
    4874             :   }
    4875             : 
    4876             :   // Turn f64->i64 into VMOVRRD.
    4877          81 :   if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
    4878          27 :     SDValue Cvt;
    4879          92 :     if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
    4880          18 :         SrcVT.getVectorNumElements() > 1)
    4881          16 :       Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
    4882          32 :                         DAG.getVTList(MVT::i32, MVT::i32),
    4883          48 :                         DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
    4884             :     else
    4885          11 :       Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
    4886          33 :                         DAG.getVTList(MVT::i32, MVT::i32), Op);
    4887             :     // Merge the pieces into a single i64 value.
    4888          81 :     return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
    4889             :   }
    4890             : 
    4891           0 :   return SDValue();
    4892             : }
    4893             : 
    4894             : /// getZeroVector - Returns a vector of specified type with all zero elements.
    4895             : /// Zero vectors are used to represent vector negation and in those cases
    4896             : /// will be implemented with the NEON VNEG instruction.  However, VNEG does
    4897             : /// not support i64 elements, so sometimes the zero vectors will need to be
    4898             : /// explicitly constructed.  Regardless, use a canonical VMOV to create the
    4899             : /// zero vector.
    4900          48 : static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
    4901             :   assert(VT.isVector() && "Expected a vector type");
    4902             :   // The canonical modified immediate encoding of a zero vector is....0!
    4903          96 :   SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
    4904          96 :   EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
    4905          48 :   SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
    4906          48 :   return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
    4907             : }
    4908             : 
    4909             : /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
    4910             : /// i32 values and take a 2 x i32 value to shift plus a shift amount.
    4911           8 : SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
    4912             :                                                 SelectionDAG &DAG) const {
    4913             :   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
    4914          16 :   EVT VT = Op.getValueType();
    4915           8 :   unsigned VTBits = VT.getSizeInBits();
    4916          16 :   SDLoc dl(Op);
    4917          16 :   SDValue ShOpLo = Op.getOperand(0);
    4918          16 :   SDValue ShOpHi = Op.getOperand(1);
    4919          16 :   SDValue ShAmt  = Op.getOperand(2);
    4920           8 :   SDValue ARMcc;
    4921           8 :   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4922          16 :   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
    4923             : 
    4924             :   assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
    4925             : 
    4926             :   SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
    4927          24 :                                  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
    4928           8 :   SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
    4929             :   SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
    4930          24 :                                    DAG.getConstant(VTBits, dl, MVT::i32));
    4931           8 :   SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
    4932           8 :   SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
    4933           8 :   SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
    4934           8 :   SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
    4935           8 :                             ISD::SETGE, ARMcc, DAG, dl);
    4936             :   SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
    4937           8 :                            ARMcc, CCR, CmpLo);
    4938             : 
    4939             : 
    4940           8 :   SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
    4941             :   SDValue HiBigShift = Opc == ISD::SRA
    4942             :                            ? DAG.getNode(Opc, dl, VT, ShOpHi,
    4943          12 :                                          DAG.getConstant(VTBits - 1, dl, VT))
    4944          12 :                            : DAG.getConstant(0, dl, VT);
    4945           8 :   SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
    4946           8 :                             ISD::SETGE, ARMcc, DAG, dl);
    4947             :   SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
    4948           8 :                            ARMcc, CCR, CmpHi);
    4949             : 
    4950           8 :   SDValue Ops[2] = { Lo, Hi };
    4951          16 :   return DAG.getMergeValues(Ops, dl);
    4952             : }
    4953             : 
    4954             : /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
    4955             : /// i32 values and take a 2 x i32 value to shift plus a shift amount.
    4956           4 : SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
    4957             :                                                SelectionDAG &DAG) const {
    4958             :   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
    4959           8 :   EVT VT = Op.getValueType();
    4960           4 :   unsigned VTBits = VT.getSizeInBits();
    4961           8 :   SDLoc dl(Op);
    4962           8 :   SDValue ShOpLo = Op.getOperand(0);
    4963           8 :   SDValue ShOpHi = Op.getOperand(1);
    4964           8 :   SDValue ShAmt  = Op.getOperand(2);
    4965           4 :   SDValue ARMcc;
    4966           4 :   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    4967             : 
    4968             :   assert(Op.getOpcode() == ISD::SHL_PARTS);
    4969             :   SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
    4970          12 :                                  DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
    4971           4 :   SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
    4972           4 :   SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
    4973           4 :   SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
    4974             : 
    4975             :   SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
    4976          12 :                                    DAG.getConstant(VTBits, dl, MVT::i32));
    4977           4 :   SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
    4978           4 :   SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
    4979           4 :                             ISD::SETGE, ARMcc, DAG, dl);
    4980             :   SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
    4981           4 :                            ARMcc, CCR, CmpHi);
    4982             : 
    4983           4 :   SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
    4984           4 :                           ISD::SETGE, ARMcc, DAG, dl);
    4985           4 :   SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
    4986             :   SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
    4987           4 :                            DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
    4988             : 
    4989           4 :   SDValue Ops[2] = { Lo, Hi };
    4990           8 :   return DAG.getMergeValues(Ops, dl);
    4991             : }
    4992             : 
    4993           3 : SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
    4994             :                                             SelectionDAG &DAG) const {
    4995             :   // The rounding mode is in bits 23:22 of the FPSCR.
    4996             :   // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
    4997             :   // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
    4998             :   // so that the shift + and get folded into a bitfield extract.
    4999           6 :   SDLoc dl(Op);
    5000             :   SDValue Ops[] = { DAG.getEntryNode(),
    5001           9 :                     DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
    5002             : 
    5003           9 :   SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
    5004             :   SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
    5005           9 :                                   DAG.getConstant(1U << 22, dl, MVT::i32));
    5006             :   SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
    5007           9 :                               DAG.getConstant(22, dl, MVT::i32));
    5008             :   return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
    5009          12 :                      DAG.getConstant(3, dl, MVT::i32));
    5010             : }
    5011             : 
    5012          48 : static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
    5013             :                          const ARMSubtarget *ST) {
    5014          96 :   SDLoc dl(N);
    5015          96 :   EVT VT = N->getValueType(0);
    5016          48 :   if (VT.isVector()) {
    5017             :     assert(ST->hasNEON());
    5018             : 
    5019             :     // Compute the least significant set bit: LSB = X & -X
    5020          44 :     SDValue X = N->getOperand(0);
    5021          22 :     SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
    5022          22 :     SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
    5023             : 
    5024          22 :     EVT ElemTy = VT.getVectorElementType();
    5025             : 
    5026          44 :     if (ElemTy == MVT::i8) {
    5027             :       // Compute with: cttz(x) = ctpop(lsb - 1)
    5028             :       SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
    5029           8 :                                 DAG.getTargetConstant(1, dl, ElemTy));
    5030           4 :       SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
    5031           4 :       return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
    5032             :     }
    5033             : 
    5034          44 :     if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
    5035          14 :         (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
    5036             :       // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
    5037           7 :       unsigned NumBits = ElemTy.getSizeInBits();
    5038             :       SDValue WidthMinus1 =
    5039             :           DAG.getNode(ARMISD::VMOVIMM, dl, VT,
    5040          14 :                       DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
    5041           7 :       SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
    5042           7 :       return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
    5043             :     }
    5044             : 
    5045             :     // Compute with: cttz(x) = ctpop(lsb - 1)
    5046             : 
    5047             :     // Since we can only compute the number of bits in a byte with vcnt.8, we
    5048             :     // have to gather the result with pairwise addition (vpaddl) for i16, i32,
    5049             :     // and i64.
    5050             : 
    5051             :     // Compute LSB - 1.
    5052          11 :     SDValue Bits;
    5053          22 :     if (ElemTy == MVT::i64) {
    5054             :       // Load constant 0xffff'ffff'ffff'ffff to register.
    5055             :       SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
    5056          12 :                                DAG.getTargetConstant(0x1eff, dl, MVT::i32));
    5057           4 :       Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
    5058             :     } else {
    5059             :       SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
    5060          14 :                                 DAG.getTargetConstant(1, dl, ElemTy));
    5061           7 :       Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
    5062             :     }
    5063             : 
    5064             :     // Count #bits with vcnt.8.
    5065          22 :     EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
    5066          11 :     SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
    5067          11 :     SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
    5068             : 
    5069             :     // Gather the #bits with vpaddl (pairwise add.)
    5070          22 :     EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
    5071             :     SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
    5072          11 :         DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
    5073          22 :         Cnt8);
    5074          22 :     if (ElemTy == MVT::i16)
    5075           3 :       return Cnt16;
    5076             : 
    5077          16 :     EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
    5078             :     SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
    5079           8 :         DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
    5080          16 :         Cnt16);
    5081          16 :     if (ElemTy == MVT::i32)
    5082           4 :       return Cnt32;
    5083             : 
    5084             :     assert(ElemTy == MVT::i64);
    5085             :     SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
    5086           4 :         DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
    5087           8 :         Cnt32);
    5088           4 :     return Cnt64;
    5089             :   }
    5090             : 
    5091          26 :   if (!ST->hasV6T2Ops())
    5092           0 :     return SDValue();
    5093             : 
    5094          52 :   SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
    5095          26 :   return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
    5096             : }
    5097             : 
    5098             : /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
    5099             : /// for each 16-bit element from operand, repeated.  The basic idea is to
    5100             : /// leverage vcnt to get the 8-bit counts, gather and add the results.
    5101             : ///
    5102             : /// Trace for v4i16:
    5103             : /// input    = [v0    v1    v2    v3   ] (vi 16-bit element)
    5104             : /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
    5105             : /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
    5106             : /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
    5107             : ///            [b0 b1 b2 b3 b4 b5 b6 b7]
    5108             : ///           +[b1 b0 b3 b2 b5 b4 b7 b6]
    5109             : /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
    5110             : /// vuzp:    = [k0 k1 k2 k3 k0 k1 k2 k3]  each ki is 8-bits)
    5111           4 : static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
    5112           8 :   EVT VT = N->getValueType(0);
    5113           8 :   SDLoc DL(N);
    5114             : 
    5115           8 :   EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
    5116           8 :   SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
    5117           4 :   SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
    5118           4 :   SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
    5119           4 :   SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
    5120           8 :   return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
    5121             : }
    5122             : 
    5123             : /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
    5124             : /// bit-count for each 16-bit element from the operand.  We need slightly
    5125             : /// different sequencing for v4i16 and v8i16 to stay within NEON's available
    5126             : /// 64/128-bit registers.
    5127             : ///
    5128             : /// Trace for v4i16:
    5129             : /// input           = [v0    v1    v2    v3    ] (vi 16-bit element)
    5130             : /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
    5131             : /// v8i16:Extended  = [k0    k1    k2    k3    k0    k1    k2    k3    ]
    5132             : /// v4i16:Extracted = [k0    k1    k2    k3    ]
    5133           4 : static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
    5134           8 :   EVT VT = N->getValueType(0);
    5135           8 :   SDLoc DL(N);
    5136             : 
    5137           4 :   SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
    5138           4 :   if (VT.is64BitVector()) {
    5139           4 :     SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
    5140             :     return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
    5141           4 :                        DAG.getIntPtrConstant(0, DL));
    5142             :   } else {
    5143             :     SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
    5144           4 :                                     BitCounts, DAG.getIntPtrConstant(0, DL));
    5145           4 :     return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
    5146             :   }
    5147             : }
    5148             : 
    5149             : /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
    5150             : /// bit-count for each 32-bit element from the operand.  The idea here is
    5151             : /// to split the vector into 16-bit elements, leverage the 16-bit count
    5152             : /// routine, and then combine the results.
    5153             : ///
    5154             : /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
    5155             : /// input    = [v0    v1    ] (vi: 32-bit elements)
    5156             : /// Bitcast  = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
    5157             : /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
    5158             : /// vrev: N0 = [k1 k0 k3 k2 ]
    5159             : ///            [k0 k1 k2 k3 ]
    5160             : ///       N1 =+[k1 k0 k3 k2 ]
    5161             : ///            [k0 k2 k1 k3 ]
    5162             : ///       N2 =+[k1 k3 k0 k2 ]
    5163             : ///            [k0    k2    k1    k3    ]
    5164             : /// Extended =+[k1    k3    k0    k2    ]
    5165             : ///            [k0    k2    ]
    5166             : /// Extracted=+[k1    k3    ]
    5167             : ///
    5168           2 : static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
    5169           4 :   EVT VT = N->getValueType(0);
    5170           4 :   SDLoc DL(N);
    5171             : 
    5172           4 :   EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
    5173             : 
    5174           4 :   SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
    5175           2 :   SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
    5176           2 :   SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
    5177           2 :   SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
    5178           2 :   SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
    5179             : 
    5180           2 :   if (VT.is64BitVector()) {
    5181           2 :     SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
    5182             :     return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
    5183           2 :                        DAG.getIntPtrConstant(0, DL));
    5184             :   } else {
    5185             :     SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
    5186           2 :                                     DAG.getIntPtrConstant(0, DL));
    5187           2 :     return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
    5188             :   }
    5189             : }
    5190             : 
    5191           4 : static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
    5192             :                           const ARMSubtarget *ST) {
    5193           8 :   EVT VT = N->getValueType(0);
    5194             : 
    5195             :   assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
    5196             :   assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
    5197             :           VT == MVT::v4i16 || VT == MVT::v8i16) &&
    5198             :          "Unexpected type for custom ctpop lowering");
    5199             : 
    5200           8 :   if (VT.getVectorElementType() == MVT::i32)
    5201           2 :     return lowerCTPOP32BitElements(N, DAG);
    5202             :   else
    5203           2 :     return lowerCTPOP16BitElements(N, DAG);
    5204             : }
    5205             : 
    5206          43 : static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
    5207             :                           const ARMSubtarget *ST) {
    5208          86 :   EVT VT = N->getValueType(0);
    5209          86 :   SDLoc dl(N);
    5210             : 
    5211          43 :   if (!VT.isVector())
    5212           0 :     return SDValue();
    5213             : 
    5214             :   // Lower vector shifts on NEON to use VSHL.
    5215             :   assert(ST->hasNEON() && "unexpected vector shift");
    5216             : 
    5217             :   // Left shifts translate directly to the vshiftu intrinsic.
    5218          43 :   if (N->getOpcode() == ISD::SHL)
    5219             :     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
    5220             :                        DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
    5221          17 :                                        MVT::i32),
    5222          68 :                        N->getOperand(0), N->getOperand(1));
    5223             : 
    5224             :   assert((N->getOpcode() == ISD::SRA ||
    5225             :           N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
    5226             : 
    5227             :   // NEON uses the same intrinsics for both left and right shifts.  For
    5228             :   // right shifts, the shift amounts are negative, so negate the vector of
    5229             :   // shift amounts.
    5230          78 :   EVT ShiftVT = N->getOperand(1).getValueType();
    5231             :   SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
    5232             :                                      getZeroVector(ShiftVT, DAG, dl),
    5233          52 :                                      N->getOperand(1));
    5234          26 :   Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
    5235             :                              Intrinsic::arm_neon_vshifts :
    5236          26 :                              Intrinsic::arm_neon_vshiftu);
    5237             :   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
    5238          26 :                      DAG.getConstant(vshiftInt, dl, MVT::i32),
    5239          78 :                      N->getOperand(0), NegatedCount);
    5240             : }
    5241             : 
    5242         695 : static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
    5243             :                                 const ARMSubtarget *ST) {
    5244        1390 :   EVT VT = N->getValueType(0);
    5245        1390 :   SDLoc dl(N);
    5246             : 
    5247             :   // We can get here for a node like i32 = ISD::SHL i32, i64
    5248         695 :   if (VT != MVT::i64)
    5249           0 :     return SDValue();
    5250             : 
    5251             :   assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
    5252             :          "Unknown shift to lower!");
    5253             : 
    5254             :   // We only lower SRA, SRL of 1 here, all others use generic lowering.
    5255        1390 :   if (!isOneConstant(N->getOperand(1)))
    5256         687 :     return SDValue();
    5257             : 
    5258             :   // If we are in thumb mode, we don't have RRX.
    5259           9 :   if (ST->isThumb1Only()) return SDValue();
    5260             : 
    5261             :   // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
    5262          14 :   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
    5263          21 :                            DAG.getConstant(0, dl, MVT::i32));
    5264          14 :   SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
    5265          21 :                            DAG.getConstant(1, dl, MVT::i32));
    5266             : 
    5267             :   // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
    5268             :   // captures the result into a carry flag.
    5269          14 :   unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
    5270          14 :   Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
    5271             : 
    5272             :   // The low part is an ARMISD::RRX operand, which shifts the carry in.
    5273          21 :   Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
    5274             : 
    5275             :   // Merge the pieces into a single i64 value.
    5276          14 :  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
    5277             : }
    5278             : 
    5279         126 : static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
    5280         126 :   SDValue TmpOp0, TmpOp1;
    5281         126 :   bool Invert = false;
    5282         126 :   bool Swap = false;
    5283         126 :   unsigned Opc = 0;
    5284             : 
    5285         252 :   SDValue Op0 = Op.getOperand(0);
    5286         252 :   SDValue Op1 = Op.getOperand(1);
    5287         252 :   SDValue CC = Op.getOperand(2);
    5288         252 :   EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
    5289         252 :   EVT VT = Op.getValueType();
    5290         126 :   ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
    5291         252 :   SDLoc dl(Op);
    5292             : 
    5293         271 :   if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
    5294          17 :       (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
    5295             :     // Special-case integer 64-bit equality comparisons. They aren't legal,
    5296             :     // but they can be lowered with a few vector instructions.
    5297           2 :     unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
    5298           2 :     EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
    5299           2 :     SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
    5300           2 :     SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
    5301             :     SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
    5302           2 :                               DAG.getCondCode(ISD::SETEQ));
    5303           2 :     SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
    5304           2 :     SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
    5305           2 :     Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
    5306           2 :     if (SetCCOpcode == ISD::SETNE)
    5307           1 :       Merged = DAG.getNOT(dl, Merged, CmpVT);
    5308           2 :     Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
    5309           2 :     return Merged;
    5310             :   }
    5311             : 
    5312         248 :   if (CmpVT.getVectorElementType() == MVT::i64)
    5313             :     // 64-bit comparisons are not legal in general.
    5314          16 :     return SDValue();
    5315             : 
    5316         216 :   if (Op1.getValueType().isFloatingPoint()) {
    5317          24 :     switch (SetCCOpcode) {
    5318           0 :     default: llvm_unreachable("Illegal FP comparison");
    5319           1 :     case ISD::SETUNE:
    5320           1 :     case ISD::SETNE:  Invert = true; LLVM_FALLTHROUGH;
    5321             :     case ISD::SETOEQ:
    5322             :     case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
    5323           1 :     case ISD::SETOLT:
    5324           1 :     case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH;
    5325             :     case ISD::SETOGT:
    5326             :     case ISD::SETGT:  Opc = ARMISD::VCGT; break;
    5327           2 :     case ISD::SETOLE:
    5328           2 :     case ISD::SETLE:  Swap = true; LLVM_FALLTHROUGH;
    5329             :     case ISD::SETOGE:
    5330             :     case ISD::SETGE: Opc = ARMISD::VCGE; break;
    5331           1 :     case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH;
    5332             :     case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
    5333           1 :     case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH;
    5334             :     case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
    5335           1 :     case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH;
    5336           2 :     case ISD::SETONE:
    5337             :       // Expand this to (OLT | OGT).
    5338           2 :       TmpOp0 = Op0;
    5339           2 :       TmpOp1 = Op1;
    5340           2 :       Opc = ISD::OR;
    5341           2 :       Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
    5342           2 :       Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
    5343             :       break;
    5344           1 :     case ISD::SETUO:
    5345           1 :       Invert = true;
    5346             :       LLVM_FALLTHROUGH;
    5347           2 :     case ISD::SETO:
    5348             :       // Expand this to (OLT | OGE).
    5349           2 :       TmpOp0 = Op0;
    5350           2 :       TmpOp1 = Op1;
    5351           2 :       Opc = ISD::OR;
    5352           2 :       Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
    5353           2 :       Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
    5354             :       break;
    5355             :     }
    5356             :   } else {
    5357             :     // Integer comparisons.
    5358          84 :     switch (SetCCOpcode) {
    5359           0 :     default: llvm_unreachable("Illegal integer comparison");
    5360          14 :     case ISD::SETNE:  Invert = true; LLVM_FALLTHROUGH;
    5361             :     case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
    5362           3 :     case ISD::SETLT:  Swap = true; LLVM_FALLTHROUGH;
    5363             :     case ISD::SETGT:  Opc = ARMISD::VCGT; break;
    5364           3 :     case ISD::SETLE:  Swap = true; LLVM_FALLTHROUGH;
    5365             :     case ISD::SETGE:  Opc = ARMISD::VCGE; break;
    5366          11 :     case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH;
    5367             :     case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
    5368           1 :     case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH;
    5369             :     case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
    5370             :     }
    5371             : 
    5372             :     // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
    5373          84 :     if (Opc == ARMISD::VCEQ) {
    5374             : 
    5375          27 :       SDValue AndOp;
    5376          27 :       if (ISD::isBuildVectorAllZeros(Op1.getNode()))
    5377             :         AndOp = Op0;
    5378          20 :       else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
    5379           0 :         AndOp = Op1;
    5380             : 
    5381             :       // Ignore bitconvert.
    5382          34 :       if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
    5383           8 :         AndOp = AndOp.getOperand(0);
    5384             : 
    5385          34 :       if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
    5386           6 :         Opc = ARMISD::VTST;
    5387          12 :         Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
    5388          12 :         Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
    5389           6 :         Invert = !Invert;
    5390             :       }
    5391             :     }
    5392             :   }
    5393             : 
    5394         108 :   if (Swap)
    5395             :     std::swap(Op0, Op1);
    5396             : 
    5397             :   // If one of the operands is a constant vector zero, attempt to fold the
    5398             :   // comparison to a specialized compare-against-zero form.
    5399         108 :   SDValue SingleOp;
    5400         108 :   if (ISD::isBuildVectorAllZeros(Op1.getNode()))
    5401           4 :     SingleOp = Op0;
    5402         104 :   else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
    5403           4 :     if (Opc == ARMISD::VCGE)
    5404             :       Opc = ARMISD::VCLEZ;
    5405           2 :     else if (Opc == ARMISD::VCGT)
    5406           2 :       Opc = ARMISD::VCLTZ;
    5407           4 :     SingleOp = Op1;
    5408             :   }
    5409             : 
    5410         108 :   SDValue Result;
    5411         108 :   if (SingleOp.getNode()) {
    5412           8 :     switch (Opc) {
    5413           1 :     case ARMISD::VCEQ:
    5414           1 :       Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
    5415           1 :     case ARMISD::VCGE:
    5416           1 :       Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
    5417           2 :     case ARMISD::VCLEZ:
    5418           2 :       Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
    5419           2 :     case ARMISD::VCGT:
    5420           2 :       Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
    5421           2 :     case ARMISD::VCLTZ:
    5422           2 :       Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
    5423           0 :     default:
    5424           0 :       Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
    5425             :     }
    5426             :   } else {
    5427         100 :      Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
    5428             :   }
    5429             : 
    5430         108 :   Result = DAG.getSExtOrTrunc(Result, dl, VT);
    5431             : 
    5432         108 :   if (Invert)
    5433          15 :     Result = DAG.getNOT(dl, Result, VT);
    5434             : 
    5435         108 :   return Result;
    5436             : }
    5437             : 
    5438          81 : static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
    5439         162 :   SDValue LHS = Op.getOperand(0);
    5440         162 :   SDValue RHS = Op.getOperand(1);
    5441         162 :   SDValue Carry = Op.getOperand(2);
    5442         162 :   SDValue Cond = Op.getOperand(3);
    5443         162 :   SDLoc DL(Op);
    5444             : 
    5445             :   assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
    5446             : 
    5447             :   assert(Carry.getOpcode() != ISD::CARRY_FALSE);
    5448         162 :   SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
    5449          81 :   SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
    5450             : 
    5451          81 :   SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
    5452          81 :   SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
    5453             :   SDValue ARMcc = DAG.getConstant(
    5454         162 :       IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
    5455          81 :   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
    5456             :   SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
    5457         243 :                                    Cmp.getValue(1), SDValue());
    5458             :   return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
    5459         324 :                      CCR, Chain.getValue(1));
    5460             : }
    5461             : 
    5462             : /// isNEONModifiedImm - Check if the specified splat value corresponds to a
    5463             : /// valid vector constant for a NEON instruction with a "modified immediate"
    5464             : /// operand (e.g., VMOV).  If so, return the encoded value.
    5465        1162 : static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
    5466             :                                  unsigned SplatBitSize, SelectionDAG &DAG,
    5467             :                                  const SDLoc &dl, EVT &VT, bool is128Bits,
    5468             :                                  NEONModImmType type) {
    5469             :   unsigned OpCmode, Imm;
    5470             : 
    5471             :   // SplatBitSize is set to the smallest size that splats the vector, so a
    5472             :   // zero vector will always have SplatBitSize == 8.  However, NEON modified
    5473             :   // immediate instructions others than VMOV do not support the 8-bit encoding
    5474             :   // of a zero vector, and the default encoding of zero is supposed to be the
    5475             :   // 32-bit version.
    5476        1162 :   if (SplatBits == 0)
    5477             :     SplatBitSize = 32;
    5478             : 
    5479        1076 :   switch (SplatBitSize) {
    5480          76 :   case 8:
    5481          76 :     if (type != VMOVModImm)
    5482           0 :       return SDValue();
    5483             :     // Any 1-byte value is OK.  Op=0, Cmode=1110.
    5484             :     assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
    5485          76 :     OpCmode = 0xe;
    5486          76 :     Imm = SplatBits;
    5487         152 :     VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
    5488          76 :     break;
    5489             : 
    5490          34 :   case 16:
    5491             :     // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
    5492          68 :     VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
    5493          34 :     if ((SplatBits & ~0xff) == 0) {
    5494             :       // Value = 0x00nn: Op=x, Cmode=100x.
    5495          16 :       OpCmode = 0x8;
    5496          16 :       Imm = SplatBits;
    5497          16 :       break;
    5498             :     }
    5499          18 :     if ((SplatBits & ~0xff00) == 0) {
    5500             :       // Value = 0xnn00: Op=x, Cmode=101x.
    5501           6 :       OpCmode = 0xa;
    5502           6 :       Imm = SplatBits >> 8;
    5503           6 :       break;
    5504             :     }
    5505          12 :     return SDValue();
    5506             : 
    5507        1003 :   case 32:
    5508             :     // NEON's 32-bit VMOV supports splat values where:
    5509             :     // * only one byte is nonzero, or
    5510             :     // * the least significant byte is 0xff and the second byte is nonzero, or
    5511             :     // * the least significant 2 bytes are 0xff and the third is nonzero.
    5512        2006 :     VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
    5513        1003 :     if ((SplatBits & ~0xff) == 0) {
    5514             :       // Value = 0x000000nn: Op=x, Cmode=000x.
    5515         110 :       OpCmode = 0;
    5516         110 :       Imm = SplatBits;
    5517         110 :       break;
    5518             :     }
    5519         893 :     if ((SplatBits & ~0xff00) == 0) {
    5520             :       // Value = 0x0000nn00: Op=x, Cmode=001x.
    5521           6 :       OpCmode = 0x2;
    5522           6 :       Imm = SplatBits >> 8;
    5523           6 :       break;
    5524             :     }
    5525         887 :     if ((SplatBits & ~0xff0000) == 0) {
    5526             :       // Value = 0x00nn0000: Op=x, Cmode=010x.
    5527           5 :       OpCmode = 0x4;
    5528           5 :       Imm = SplatBits >> 16;
    5529           5 :       break;
    5530             :     }
    5531         882 :     if ((SplatBits & ~0xff000000) == 0) {
    5532             :       // Value = 0xnn000000: Op=x, Cmode=011x.
    5533          16 :       OpCmode = 0x6;
    5534          16 :       Imm = SplatBits >> 24;
    5535          16 :       break;
    5536             :     }
    5537             : 
    5538             :     // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
    5539         866 :     if (type == OtherModImm) return SDValue();
    5540             : 
    5541         849 :     if ((SplatBits & ~0xffff) == 0 &&
    5542           5 :         ((SplatBits | SplatUndef) & 0xff) == 0xff) {
    5543             :       // Value = 0x0000nnff: Op=x, Cmode=1100.
    5544           3 :       OpCmode = 0xc;
    5545           3 :       Imm = SplatBits >> 8;
    5546           3 :       break;
    5547             :     }
    5548             : 
    5549         847 :     if ((SplatBits & ~0xffffff) == 0 &&
    5550           6 :         ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
    5551             :       // Value = 0x00nnffff: Op=x, Cmode=1101.
    5552           4 :       OpCmode = 0xd;
    5553           4 :       Imm = SplatBits >> 16;
    5554           4 :       break;
    5555             :     }
    5556             : 
    5557             :     // Note: there are a few 32-bit splat values (specifically: 00ffff00,
    5558             :     // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
    5559             :     // VMOV.I32.  A (very) minor optimization would be to replicate the value
    5560             :     // and fall through here to test for a valid 64-bit splat.  But, then the
    5561             :     // caller would also need to check and handle the change in size.
    5562         837 :     return SDValue();
    5563             : 
    5564          49 :   case 64: {
    5565          49 :     if (type != VMOVModImm)
    5566          23 :       return SDValue();
    5567             :     // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
    5568             :     uint64_t BitMask = 0xff;
    5569             :     uint64_t Val = 0;
    5570             :     unsigned ImmMask = 1;
    5571             :     Imm = 0;
    5572         148 :     for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
    5573          83 :       if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
    5574          27 :         Val |= BitMask;
    5575          27 :         Imm |= ImmMask;
    5576          56 :       } else if ((SplatBits & BitMask) != 0) {
    5577          22 :         return SDValue();
    5578             :       }
    5579          61 :       BitMask <<= 8;
    5580          61 :       ImmMask <<= 1;
    5581             :     }
    5582             : 
    5583           8 :     if (DAG.getDataLayout().isBigEndian())
    5584             :       // swap higher and lower 32 bit word
    5585           0 :       Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
    5586             : 
    5587             :     // Op=1, Cmode=1110.
    5588           4 :     OpCmode = 0x1e;
    5589           8 :     VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
    5590           4 :     break;
    5591             :   }
    5592             : 
    5593           0 :   default:
    5594           0 :     llvm_unreachable("unexpected size for isNEONModifiedImm");
    5595             :   }
    5596             : 
    5597         246 :   unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
    5598         492 :   return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
    5599             : }
    5600             : 
    5601         976 : SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
    5602             :                                            const ARMSubtarget *ST) const {
    5603        2928 :   bool IsDouble = Op.getValueType() == MVT::f64;
    5604         976 :   ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
    5605         976 :   const APFloat &FPVal = CFP->getValueAPF();
    5606             : 
    5607             :   // Prevent floating-point constants from using literal loads
    5608             :   // when execute-only is enabled.
    5609         976 :   if (ST->genExecuteOnly()) {
    5610         108 :     APInt INTVal = FPVal.bitcastToAPInt();
    5611         108 :     SDLoc DL(CFP);
    5612          54 :     if (IsDouble) {
    5613          60 :       SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
    5614          90 :       SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
    5615          30 :       if (!ST->isLittle())
    5616             :         std::swap(Lo, Hi);
    5617          60 :       return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
    5618             :     } else {
    5619          24 :       return DAG.getConstant(INTVal, DL, MVT::i32);
    5620             :     }
    5621             :   }
    5622             : 
    5623         922 :   if (!ST->hasVFP3())
    5624          28 :     return SDValue();
    5625             : 
    5626             :   // Use the default (constant pool) lowering for double constants when we have
    5627             :   // an SP-only FPU
    5628         894 :   if (IsDouble && Subtarget->isFPOnlySP())
    5629           8 :     return SDValue();
    5630             : 
    5631             :   // Try splatting with a VMOV.f32...
    5632         886 :   int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
    5633             : 
    5634         886 :   if (ImmVal != -1) {
    5635         288 :     if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
    5636             :       // We have code in place to select a valid ConstantFP already, no need to
    5637             :       // do any mangling.
    5638         222 :       return Op;
    5639             :     }
    5640             : 
    5641             :     // It's a float and we are trying to use NEON operations where
    5642             :     // possible. Lower it to a splat followed by an extract.
    5643          33 :     SDLoc DL(Op);
    5644          66 :     SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
    5645             :     SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
    5646          66 :                                       NewVal);
    5647             :     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
    5648          99 :                        DAG.getConstant(0, DL, MVT::i32));
    5649             :   }
    5650             : 
    5651             :   // The rest of our options are NEON only, make sure that's allowed before
    5652             :   // proceeding..
    5653         631 :   if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
    5654         126 :     return SDValue();
    5655             : 
    5656         505 :   EVT VMovVT;
    5657        1515 :   uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
    5658             : 
    5659             :   // It wouldn't really be worth bothering for doubles except for one very
    5660             :   // important value, which does happen to match: 0.0. So make sure we don't do
    5661             :   // anything stupid.
    5662         505 :   if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
    5663          80 :     return SDValue();
    5664             : 
    5665             :   // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
    5666         850 :   SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
    5667         425 :                                      VMovVT, false, VMOVModImm);
    5668         850 :   if (NewVal != SDValue()) {
    5669          40 :     SDLoc DL(Op);
    5670             :     SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
    5671          20 :                                       NewVal);
    5672          20 :     if (IsDouble)
    5673          26 :       return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
    5674             : 
    5675             :     // It's a float: cast and extract a vector element.
    5676             :     SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
    5677          14 :                                        VecConstant);
    5678             :     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
    5679          21 :                        DAG.getConstant(0, DL, MVT::i32));
    5680             :   }
    5681             : 
    5682             :   // Finally, try a VMVN.i32
    5683        1215 :   NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
    5684         405 :                              false, VMVNModImm);
    5685         810 :   if (NewVal != SDValue()) {
    5686           6 :     SDLoc DL(Op);
    5687           3 :     SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
    5688             : 
    5689           3 :     if (IsDouble)
    5690           4 :       return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
    5691             : 
    5692             :     // It's a float: cast and extract a vector element.
    5693             :     SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
    5694           2 :                                        VecConstant);
    5695             :     return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
    5696           3 :                        DAG.getConstant(0, DL, MVT::i32));
    5697             :   }
    5698             : 
    5699         402 :   return SDValue();
    5700             : }
    5701             : 
    5702             : // check if an VEXT instruction can handle the shuffle mask when the
    5703             : // vector sources of the shuffle are the same.
    5704          64 : static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
    5705          64 :   unsigned NumElts = VT.getVectorNumElements();
    5706             : 
    5707             :   // Assume that the first shuffle index is not UNDEF.  Fail if it is.
    5708          64 :   if (M[0] < 0)
    5709             :     return false;
    5710             : 
    5711          56 :   Imm = M[0];
    5712             : 
    5713             :   // If this is a VEXT shuffle, the immediate value is the index of the first
    5714             :   // element.  The other shuffle indices must be the successive elements after
    5715             :   // the first one.
    5716          56 :   unsigned ExpectedElt = Imm;
    5717         108 :   for (unsigned i = 1; i < NumElts; ++i) {
    5718             :     // Increment the expected index.  If it wraps around, just follow it
    5719             :     // back to index zero and keep going.
    5720         104 :     ++ExpectedElt;
    5721         104 :     if (ExpectedElt == NumElts)
    5722           7 :       ExpectedElt = 0;
    5723             : 
    5724         208 :     if (M[i] < 0) continue; // ignore UNDEF indices
    5725          95 :     if (ExpectedElt != static_cast<unsigned>(M[i]))
    5726             :       return false;
    5727             :   }
    5728             : 
    5729             :   return true;
    5730             : }
    5731             : 
    5732         245 : static bool isVEXTMask(ArrayRef<int> M, EVT VT,
    5733             :                        bool &ReverseVEXT, unsigned &Imm) {
    5734         245 :   unsigned NumElts = VT.getVectorNumElements();
    5735         245 :   ReverseVEXT = false;
    5736             : 
    5737             :   // Assume that the first shuffle index is not UNDEF.  Fail if it is.
    5738         245 :   if (M[0] < 0)
    5739             :     return false;
    5740             : 
    5741         226 :   Imm = M[0];
    5742             : 
    5743             :   // If this is a VEXT shuffle, the immediate value is the index of the first
    5744             :   // element.  The other shuffle indices must be the successive elements after
    5745             :   // the first one.
    5746         226 :   unsigned ExpectedElt = Imm;
    5747         410 :   for (unsigned i = 1; i < NumElts; ++i) {
    5748             :     // Increment the expected index.  If it wraps around, it may still be
    5749             :     // a VEXT but the source vectors must be swapped.
    5750         397 :     ExpectedElt += 1;
    5751         397 :     if (ExpectedElt == NumElts * 2) {
    5752           3 :       ExpectedElt = 0;
    5753           3 :       ReverseVEXT = true;
    5754             :     }
    5755             : 
    5756         794 :     if (M[i] < 0) continue; // ignore UNDEF indices
    5757         353 :     if (ExpectedElt != static_cast<unsigned>(M[i]))
    5758             :       return false;
    5759             :   }
    5760             : 
    5761             :   // Adjust the index value if the source operands will be swapped.
    5762          13 :   if (ReverseVEXT)
    5763           3 :     Imm -= NumElts;
    5764             : 
    5765             :   return true;
    5766             : }
    5767             : 
    5768             : /// isVREVMask - Check if a vector shuffle corresponds to a VREV
    5769             : /// instruction with the specified blocksize.  (The order of the elements
    5770             : /// within each block of the vector is reversed.)
    5771         684 : static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
    5772             :   assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
    5773             :          "Only possible block sizes for VREV are: 16, 32, 64");
    5774             : 
    5775         684 :   unsigned EltSz = VT.getScalarSizeInBits();
    5776         684 :   if (EltSz == 64)
    5777             :     return false;
    5778             : 
    5779         684 :   unsigned NumElts = VT.getVectorNumElements();
    5780         684 :   unsigned BlockElts = M[0] + 1;
    5781             :   // If the first shuffle index is UNDEF, be optimistic.
    5782         684 :   if (M[0] < 0)
    5783          56 :     BlockElts = BlockSize / EltSz;
    5784             : 
    5785         684 :   if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
    5786             :     return false;
    5787             : 
    5788         859 :   for (unsigned i = 0; i < NumElts; ++i) {
    5789         934 :     if (M[i] < 0) continue; // ignore UNDEF indices
    5790         317 :     if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
    5791             :       return false;
    5792             :   }
    5793             : 
    5794             :   return true;
    5795             : }
    5796             : 
    5797             : static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
    5798             :   // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
    5799             :   // range, then 0 is placed into the resulting vector. So pretty much any mask
    5800             :   // of 8 elements can work here.
    5801          27 :   return VT == MVT::v8i8 && M.size() == 8;
    5802             : }
    5803             : 
    5804             : static unsigned SelectPairHalf(unsigned Elements, ArrayRef<int> Mask,
    5805             :                                unsigned Index) {
    5806         758 :   if (Mask.size() == Elements * 2)
    5807         130 :     return Index / Elements;
    5808        1256 :   return Mask[Index] == 0 ? 0 : 1;
    5809             : }
    5810             : 
    5811             : // Checks whether the shuffle mask represents a vector transpose (VTRN) by
    5812             : // checking that pairs of elements in the shuffle mask represent the same index
    5813             : // in each vector, incrementing the expected index by 2 at each step.
    5814             : // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
    5815             : //  v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g}
    5816             : //  v2={e,f,g,h}
    5817             : // WhichResult gives the offset for each element in the mask based on which
    5818             : // of the two results it belongs to.
    5819             : //
    5820             : // The transpose can be represented either as:
    5821             : // result1 = shufflevector v1, v2, result1_shuffle_mask
    5822             : // result2 = shufflevector v1, v2, result2_shuffle_mask
    5823             : // where v1/v2 and the shuffle masks have the same number of elements
    5824             : // (here WhichResult (see below) indicates which result is being checked)
    5825             : //
    5826             : // or as:
    5827             : // results = shufflevector v1, v2, shuffle_mask
    5828             : // where both results are returned in one vector and the shuffle mask has twice
    5829             : // as many elements as v1/v2 (here WhichResult will always be 0 if true) here we
    5830             : // want to check the low half and high half of the shuffle mask as if it were
    5831             : // the other case
    5832         225 : static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
    5833         225 :   unsigned EltSz = VT.getScalarSizeInBits();
    5834         225 :   if (EltSz == 64)
    5835             :     return false;
    5836             : 
    5837         225 :   unsigned NumElts = VT.getVectorNumElements();
    5838         225 :   if (M.size() != NumElts && M.size() != NumElts*2)
    5839             :     return false;
    5840             : 
    5841             :   // If the mask is twice as long as the input vector then we need to check the
    5842             :   // upper and lower parts of the mask with a matching value for WhichResult
    5843             :   // FIXME: A mask with only even values will be rejected in case the first
    5844             :   // element is undefined, e.g. [-1, 4, 2, 6] will be rejected, because only
    5845             :   // M[0] is used to determine WhichResult
    5846         343 :   for (unsigned i = 0; i < M.size(); i += NumElts) {
    5847         235 :     WhichResult = SelectPairHalf(NumElts, M, i);
    5848         447 :     for (unsigned j = 0; j < NumElts; j += 2) {
    5849        1100 :       if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
    5850         919 :           (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult))
    5851             :         return false;
    5852             :     }
    5853             :   }
    5854             : 
    5855          49 :   if (M.size() == NumElts*2)
    5856           6 :     WhichResult = 0;
    5857             : 
    5858             :   return true;
    5859             : }
    5860             : 
    5861             : /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
    5862             : /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
    5863             : /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
    5864          74 : static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
    5865          74 :   unsigned EltSz = VT.getScalarSizeInBits();
    5866          74 :   if (EltSz == 64)
    5867             :     return false;
    5868             : 
    5869          74 :   unsigned NumElts = VT.getVectorNumElements();
    5870          74 :   if (M.size() != NumElts && M.size() != NumElts*2)
    5871             :     return false;
    5872             : 
    5873          94 :   for (unsigned i = 0; i < M.size(); i += NumElts) {
    5874          80 :     WhichResult = SelectPairHalf(NumElts, M, i);
    5875         135 :     for (unsigned j = 0; j < NumElts; j += 2) {
    5876         337 :       if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
    5877         231 :           (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult))
    5878             :         return false;
    5879             :     }
    5880             :   }
    5881             : 
    5882           4 :   if (M.size() == NumElts*2)
    5883           0 :     WhichResult = 0;
    5884             : 
    5885             :   return true;
    5886             : }
    5887             : 
    5888             : // Checks whether the shuffle mask represents a vector unzip (VUZP) by checking
    5889             : // that the mask elements are either all even and in steps of size 2 or all odd
    5890             : // and in steps of size 2.
    5891             : // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
    5892             : //  v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g}
    5893             : //  v2={e,f,g,h}
    5894             : // Requires similar checks to that of isVTRNMask with
    5895             : // respect the how results are returned.
    5896         176 : static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
    5897         176 :   unsigned EltSz = VT.getScalarSizeInBits();
    5898         176 :   if (EltSz == 64)
    5899             :     return false;
    5900             : 
    5901         176 :   unsigned NumElts = VT.getVectorNumElements();
    5902         176 :   if (M.size() != NumElts && M.size() != NumElts*2)
    5903             :     return false;
    5904             : 
    5905         328 :   for (unsigned i = 0; i < M.size(); i += NumElts) {
    5906         182 :     WhichResult = SelectPairHalf(NumElts, M, i);
    5907         840 :     for (unsigned j = 0; j < NumElts; ++j) {
    5908        1528 :       if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult)
    5909             :         return false;
    5910             :     }
    5911             :   }
    5912             : 
    5913          70 :   if (M.size() == NumElts*2)
    5914           3 :     WhichResult = 0;
    5915             : 
    5916             :   // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
    5917          70 :   if (VT.is64BitVector() && EltSz == 32)
    5918             :     return false;
    5919             : 
    5920             :   return true;
    5921             : }
    5922             : 
    5923             : /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
    5924             : /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
    5925             : /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
    5926          70 : static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
    5927          70 :   unsigned EltSz = VT.getScalarSizeInBits();
    5928          70 :   if (EltSz == 64)
    5929             :     return false;
    5930             : 
    5931          70 :   unsigned NumElts = VT.getVectorNumElements();
    5932          70 :   if (M.size() != NumElts && M.size() != NumElts*2)
    5933             :     return false;
    5934             : 
    5935          70 :   unsigned Half = NumElts / 2;
    5936          79 :   for (unsigned i = 0; i < M.size(); i += NumElts) {
    5937          76 :     WhichResult = SelectPairHalf(NumElts, M, i);
    5938         116 :     for (unsigned j = 0; j < NumElts; j += Half) {
    5939             :       unsigned Idx = WhichResult;
    5940         403 :       for (unsigned k = 0; k < Half; ++k) {
    5941         430 :         int MIdx = M[i + j + k];
    5942         215 :         if (MIdx >= 0 && (unsigned) MIdx != Idx)
    5943             :           return false;
    5944         148 :         Idx += 2;
    5945             :       }
    5946             :     }
    5947             :   }
    5948             : 
    5949           3 :   if (M.size() == NumElts*2)
    5950           0 :     WhichResult = 0;
    5951             : 
    5952             :   // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
    5953           3 :   if (VT.is64BitVector() && EltSz == 32)
    5954             :     return false;
    5955             : 
    5956             :   return true;
    5957             : }
    5958             : 
    5959             : // Checks whether the shuffle mask represents a vector zip (VZIP) by checking
    5960             : // that pairs of elements of the shufflemask represent the same index in each
    5961             : // vector incrementing sequentially through the vectors.
    5962             : // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
    5963             : //  v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
    5964             : //  v2={e,f,g,h}
    5965             : // Requires similar checks to that of isVTRNMask with respect the how results
    5966             : // are returned.
    5967         106 : static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
    5968         106 :   unsigned EltSz = VT.getScalarSizeInBits();
    5969         106 :   if (EltSz == 64)
    5970             :     return false;
    5971             : 
    5972         106 :   unsigned NumElts = VT.getVectorNumElements();
    5973         106 :   if (M.size() != NumElts && M.size() != NumElts*2)
    5974             :     return false;
    5975             : 
    5976         182 :   for (unsigned i = 0; i < M.size(); i += NumElts) {
    5977         112 :     WhichResult = SelectPairHalf(NumElts, M, i);
    5978         112 :     unsigned Idx = WhichResult * NumElts / 2;
    5979         289 :     for (unsigned j = 0; j < NumElts; j += 2) {
    5980         715 :       if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
    5981         593 :           (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts))
    5982             :         return false;
    5983         177 :       Idx += 1;
    5984             :     }
    5985             :   }
    5986             : 
    5987          32 :   if (M.size() == NumElts*2)
    5988           4 :     WhichResult = 0;
    5989             : 
    5990             :   // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
    5991          32 :   if (VT.is64BitVector() && EltSz == 32)
    5992             :     return false;
    5993             : 
    5994             :   return true;
    5995             : }
    5996             : 
    5997             : /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
    5998             : /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
    5999             : /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
    6000          67 : static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
    6001          67 :   unsigned EltSz = VT.getScalarSizeInBits();
    6002          67 :   if (EltSz == 64)
    6003             :     return false;
    6004             : 
    6005          67 :   unsigned NumElts = VT.getVectorNumElements();
    6006          67 :   if (M.size() != NumElts && M.size() != NumElts*2)
    6007             :     return false;
    6008             : 
    6009          81 :   for (unsigned i = 0; i < M.size(); i += NumElts) {
    6010          73 :     WhichResult = SelectPairHalf(NumElts, M, i);
    6011          73 :     unsigned Idx = WhichResult * NumElts / 2;
    6012         111 :     for (unsigned j = 0; j < NumElts; j += 2) {
    6013         276 :       if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
    6014         176 :           (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx))
    6015             :         return false;
    6016          38 :       Idx += 1;
    6017             :     }
    6018             :   }
    6019             : 
    6020           1 :   if (M.size() == NumElts*2)
    6021           0 :     WhichResult = 0;
    6022             : 
    6023             :   // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
    6024           1 :   if (VT.is64BitVector() && EltSz == 32)
    6025             :     return false;
    6026             : 
    6027             :   return true;
    6028             : }
    6029             : 
    6030             : /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN),
    6031             : /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
    6032         225 : static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,
    6033             :                                            unsigned &WhichResult,
    6034             :                                            bool &isV_UNDEF) {
    6035         225 :   isV_UNDEF = false;
    6036         225 :   if (isVTRNMask(ShuffleMask, VT, WhichResult))
    6037             :     return ARMISD::VTRN;
    6038         176 :   if (isVUZPMask(ShuffleMask, VT, WhichResult))
    6039             :     return ARMISD::VUZP;
    6040         106 :   if (isVZIPMask(ShuffleMask, VT, WhichResult))
    6041             :     return ARMISD::VZIP;
    6042             : 
    6043          74 :   isV_UNDEF = true;
    6044          74 :   if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
    6045             :     return ARMISD::VTRN;
    6046          70 :   if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
    6047             :     return ARMISD::VUZP;
    6048          67 :   if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
    6049             :     return ARMISD::VZIP;
    6050             : 
    6051          66 :   return 0;
    6052             : }
    6053             : 
    6054             : /// \return true if this is a reverse operation on an vector.
    6055          18 : static bool isReverseMask(ArrayRef<int> M, EVT VT) {
    6056          18 :   unsigned NumElts = VT.getVectorNumElements();
    6057             :   // Make sure the mask has the right size.
    6058          18 :   if (NumElts != M.size())
    6059             :       return false;
    6060             : 
    6061             :   // Look for <15, ..., 3, -1, 1, 0>.
    6062         110 :   for (unsigned i = 0; i != NumElts; ++i)
    6063         124 :     if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
    6064             :       return false;
    6065             : 
    6066             :   return true;
    6067             : }
    6068             : 
    6069             : // If N is an integer constant that can be moved into a register in one
    6070             : // instruction, return an SDValue of such a constant (will become a MOV
    6071             : // instruction).  Otherwise return null.
    6072           9 : static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
    6073             :                                      const ARMSubtarget *ST, const SDLoc &dl) {
    6074             :   uint64_t Val;
    6075           2 :   if (!isa<ConstantSDNode>(N))
    6076           2 :     return SDValue();
    6077          14 :   Val = cast<ConstantSDNode>(N)->getZExtValue();
    6078             : 
    6079           7 :   if (ST->isThumb1Only()) {
    6080           0 :     if (Val <= 255 || ~Val <= 255)
    6081           0 :       return DAG.getConstant(Val, dl, MVT::i32);
    6082             :   } else {
    6083          14 :     if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
    6084           0 :       return DAG.getConstant(Val, dl, MVT::i32);
    6085             :   }
    6086           7 :   return SDValue();
    6087             : }
    6088             : 
    6089             : // If this is a case we can't handle, return null and let the default
    6090             : // expansion code take care of it.
    6091        1127 : SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
    6092             :                                              const ARMSubtarget *ST) const {
    6093        2254 :   BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
    6094        2254 :   SDLoc dl(Op);
    6095        2254 :   EVT VT = Op.getValueType();
    6096             : 
    6097        4508 :   APInt SplatBits, SplatUndef;
    6098             :   unsigned SplatBitSize;
    6099             :   bool HasAnyUndefs;
    6100        1127 :   if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
    6101         425 :     if (SplatUndef.isAllOnesValue())
    6102           7 :       return DAG.getUNDEF(VT);
    6103             : 
    6104         418 :     if (SplatBitSize <= 64) {
    6105             :       // Check if an immediate VMOV works.
    6106         247 :       EVT VmovVT;
    6107             :       SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
    6108             :                                       SplatUndef.getZExtValue(), SplatBitSize,
    6109         247 :                                       DAG, dl, VmovVT, VT.is128BitVector(),
    6110         741 :                                       VMOVModImm);
    6111         247 :       if (Val.getNode()) {
    6112         200 :         SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
    6113         200 :         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
    6114             :       }
    6115             : 
    6116             :       // Try an immediate VMVN.
    6117         235 :       uint64_t NegatedImm = (~SplatBits).getZExtValue();
    6118          47 :       Val = isNEONModifiedImm(NegatedImm,
    6119             :                                       SplatUndef.getZExtValue(), SplatBitSize,
    6120          47 :                                       DAG, dl, VmovVT, VT.is128BitVector(),
    6121          94 :                                       VMVNModImm);
    6122          47 :       if (Val.getNode()) {
    6123          10 :         SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
    6124          10 :         return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
    6125             :       }
    6126             : 
    6127             :       // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
    6128          79 :       if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
    6129           8 :         int ImmVal = ARM_AM::getFP32Imm(SplatBits);
    6130           8 :         if (ImmVal != -1) {
    6131          10 :           SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
    6132           5 :           return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
    6133             :         }
    6134             :       }
    6135             :     }
    6136             :   }
    6137             : 
    6138             :   // Scan through the operands to see if only one value is used.
    6139             :   //
    6140             :   // As an optimisation, even if more than one value is used it may be more
    6141             :   // profitable to splat with one value then change some lanes.
    6142             :   //
    6143             :   // Heuristically we decide to do this if the vector has a "dominant" value,
    6144             :   // defined as splatted to more than half of the lanes.
    6145         905 :   unsigned NumElts = VT.getVectorNumElements();
    6146         905 :   bool isOnlyLowElement = true;
    6147         905 :   bool usesOnlyOneValue = true;
    6148         905 :   bool hasDominantValue = false;
    6149         905 :   bool isConstant = true;
    6150             : 
    6151             :   // Map of the number of times a particular SDValue appears in the
    6152             :   // element list.
    6153         905 :   DenseMap<SDValue, unsigned> ValueCounts;
    6154         905 :   SDValue Value;
    6155        3849 :   for (unsigned i = 0; i < NumElts; ++i) {
    6156        5888 :     SDValue V = Op.getOperand(i);
    6157        5888 :     if (V.isUndef())
    6158         274 :       continue;
    6159        2670 :     if (i > 0)
    6160        1820 :       isOnlyLowElement = false;
    6161        2102 :     if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
    6162             :       isConstant = false;
    6163             : 
    6164       10680 :     ValueCounts.insert(std::make_pair(V, 0));
    6165        2670 :     unsigned &Count = ValueCounts[V];
    6166             : 
    6167             :     // Is this value dominant? (takes up more than half of the lanes)
    6168        2670 :     if (++Count > (NumElts / 2)) {
    6169         229 :       hasDominantValue = true;
    6170         229 :       Value = V;
    6171             :     }
    6172             :   }
    6173         905 :   if (ValueCounts.size() != 1)
    6174         730 :     usesOnlyOneValue = false;
    6175        1700 :   if (!Value.getNode() && !ValueCounts.empty())
    6176         795 :     Value = ValueCounts.begin()->first;
    6177             : 
    6178         905 :   if (ValueCounts.empty())
    6179           0 :     return DAG.getUNDEF(VT);
    6180             : 
    6181             :   // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
    6182             :   // Keep going if we are hitting this case.
    6183         905 :   if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
    6184          19 :     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
    6185             : 
    6186         886 :   unsigned EltSize = VT.getScalarSizeInBits();
    6187             : 
    6188             :   // Use VDUP for non-constant splats.  For f32 constant splats, reduce to
    6189             :   // i32 and try again.
    6190         886 :   if (hasDominantValue && EltSize <= 32) {
    6191         109 :     if (!isConstant) {
    6192          94 :       SDValue N;
    6193             : 
    6194             :       // If we are VDUPing a value that comes directly from a vector, that will
    6195             :       // cause an unnecessary move to and from a GPR, where instead we could
    6196             :       // just use VDUPLANE. We can only do this if the lane being extracted
    6197             :       // is at a constant index, as the VDUP from lane instructions only have
    6198             :       // constant-index forms.
    6199             :       ConstantSDNode *constIndex;
    6200          95 :       if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
    6201           4 :           (constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)))) {
    6202             :         // We need to create a new undef vector to use for the VDUPLANE if the
    6203             :         // size of the vector from which we get the value is different than the
    6204             :         // size of the vector that we need to create. We will insert the element
    6205             :         // such that the register coalescer will remove unnecessary copies.
    6206           3 :         if (VT != Value->getOperand(0).getValueType()) {
    6207           0 :           unsigned index = constIndex->getAPIntValue().getLimitedValue() %
    6208           0 :                              VT.getVectorNumElements();
    6209           0 :           N =  DAG.getNode(ARMISD::VDUPLANE, dl, VT,
    6210             :                  DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
    6211           0 :                         Value, DAG.getConstant(index, dl, MVT::i32)),
    6212           0 :                            DAG.getConstant(index, dl, MVT::i32));
    6213             :         } else
    6214           1 :           N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
    6215           4 :                         Value->getOperand(0), Value->getOperand(1));
    6216             :       } else
    6217          93 :         N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
    6218             : 
    6219          94 :       if (!usesOnlyOneValue) {
    6220             :         // The dominant value was splatted as 'N', but we now have to insert
    6221             :         // all differing elements.
    6222          27 :         for (unsigned I = 0; I < NumElts; ++I) {
    6223          36 :           if (Op.getOperand(I) == Value)
    6224           9 :             continue;
    6225           6 :           SmallVector<SDValue, 3> Ops;
    6226           3 :           Ops.push_back(N);
    6227           6 :           Ops.push_back(Op.getOperand(I));
    6228           3 :           Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
    6229           6 :           N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
    6230             :         }
    6231             :       }
    6232          94 :       return N;
    6233             :     }
    6234          15 :     if (VT.getVectorElementType().isFloatingPoint()) {
    6235          10 :       SmallVector<SDValue, 8> Ops;
    6236          23 :       for (unsigned i = 0; i < NumElts; ++i)
    6237          18 :         Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
    6238          72 :                                   Op.getOperand(i)));
    6239           5 :       EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
    6240           5 :       SDValue Val = DAG.getBuildVector(VecVT, dl, Ops);
    6241           5 :       Val = LowerBUILD_VECTOR(Val, DAG, ST);
    6242           5 :       if (Val.getNode())
    6243           0 :         return DAG.getNode(ISD::BITCAST, dl, VT, Val);
    6244             :     }
    6245          15 :     if (usesOnlyOneValue) {
    6246           9 :       SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
    6247           9 :       if (isConstant && Val.getNode())
    6248           0 :         return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
    6249             :     }
    6250             :   }
    6251             : 
    6252             :   // If all elements are constants and the case above didn't get hit, fall back
    6253             :   // to the default expansion, which will generate a load from the constant
    6254             :   // pool.
    6255         792 :   if (isConstant)
    6256         202 :     return SDValue();
    6257             : 
    6258             :   // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
    6259         590 :   if (NumElts >= 4) {
    6260         173 :     SDValue shuffle = ReconstructShuffle(Op, DAG);
    6261         346 :     if (shuffle != SDValue())
    6262          21 :       return shuffle;
    6263             :   }
    6264             : 
    6265        1132 :   if (VT.is128BitVector() && VT != MVT::v2f64 && VT != MVT::v4f32) {
    6266             :     // If we haven't found an efficient lowering, try splitting a 128-bit vector
    6267             :     // into two 64-bit vectors; we might discover a better way to lower it.
    6268         157 :     SmallVector<SDValue, 64> Ops(Op->op_begin(), Op->op_begin() + NumElts);
    6269          78 :     EVT ExtVT = VT.getVectorElementType();
    6270          78 :     EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElts / 2);
    6271             :     SDValue Lower =
    6272         234 :         DAG.getBuildVector(HVT, dl, makeArrayRef(&Ops[0], NumElts / 2));
    6273         156 :     if (Lower.getOpcode() == ISD::BUILD_VECTOR)
    6274          78 :       Lower = LowerBUILD_VECTOR(Lower, DAG, ST);
    6275             :     SDValue Upper = DAG.getBuildVector(
    6276         234 :         HVT, dl, makeArrayRef(&Ops[NumElts / 2], NumElts / 2));
    6277         156 :     if (Upper.getOpcode() == ISD::BUILD_VECTOR)
    6278          78 :       Upper = LowerBUILD_VECTOR(Upper, DAG, ST);
    6279          78 :     if (Lower && Upper)
    6280          77 :       return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lower, Upper);
    6281             :   }
    6282             : 
    6283             :   // Vectors with 32- or 64-bit elements can be built by directly assigning
    6284             :   // the subregisters.  Lower it to an ARMISD::BUILD_VECTOR so the operands
    6285             :   // will be legalized.
    6286         492 :   if (EltSize >= 32) {
    6287             :     // Do the expansion with floating-point types, since that is what the VFP
    6288             :     // registers are defined to use, and since i64 is not legal.
    6289         485 :     EVT EltVT = EVT::getFloatingPointVT(EltSize);
    6290         485 :     EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
    6291         970 :     SmallVector<SDValue, 8> Ops;
    6292        1591 :     for (unsigned i = 0; i < NumElts; ++i)
    6293        2212 :       Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
    6294         970 :     SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
    6295         485 :     return DAG.getNode(ISD::BITCAST, dl, VT, Val);
    6296             :   }
    6297             : 
    6298             :   // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
    6299             :   // know the default expansion would otherwise fall back on something even
    6300             :   // worse. For a vector with one or two non-undef values, that's
    6301             :   // scalar_to_vector for the elements followed by a shuffle (provided the
    6302             :   // shuffle is valid for the target) and materialization element by element
    6303             :   // on the stack followed by a load for everything else.
    6304           7 :   if (!isConstant && !usesOnlyOneValue) {
    6305           4 :     SDValue Vec = DAG.getUNDEF(VT);
    6306          24 :     for (unsigned i = 0 ; i < NumElts; ++i) {
    6307          40 :       SDValue V = Op.getOperand(i);
    6308          40 :       if (V.isUndef())
    6309           8 :         continue;
    6310          12 :       SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
    6311          12 :       Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
    6312             :     }
    6313           4 :     return Vec;
    6314             :   }
    6315             : 
    6316           3 :   return SDValue();
    6317             : }
    6318             : 
    6319             : // Gather data to see if the operation can be modelled as a
    6320             : // shuffle in combination with VEXTs.
    6321         173 : SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
    6322             :                                               SelectionDAG &DAG) const {
    6323             :   assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
    6324         346 :   SDLoc dl(Op);
    6325         346 :   EVT VT = Op.getValueType();
    6326         173 :   unsigned NumElts = VT.getVectorNumElements();
    6327             : 
    6328             :   struct ShuffleSourceInfo {
    6329             :     SDValue Vec;
    6330             :     unsigned MinElt = std::numeric_limits<unsigned>::max();
    6331             :     unsigned MaxElt = 0;
    6332             : 
    6333             :     // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
    6334             :     // be compatible with the shuffle we intend to construct. As a result
    6335             :     // ShuffleVec will be some sliding window into the original Vec.
    6336             :     SDValue ShuffleVec;
    6337             : 
    6338             :     // Code should guarantee that element i in Vec starts at element "WindowBase
    6339             :     // + i * WindowScale in ShuffleVec".
    6340             :     int WindowBase = 0;
    6341             :     int WindowScale = 1;
    6342             : 
    6343          58 :     ShuffleSourceInfo(SDValue Vec) : Vec(Vec), ShuffleVec(Vec) {}
    6344             : 
    6345         442 :     bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
    6346             :   };
    6347             : 
    6348             :   // First gather all vectors used as an immediate source for this BUILD_VECTOR
    6349             :   // node.
    6350         346 :   SmallVector<ShuffleSourceInfo, 2> Sources;
    6351         454 :   for (unsigned i = 0; i < NumElts; ++i) {
    6352         844 :     SDValue V = Op.getOperand(i);
    6353         844 :     if (V.isUndef())
    6354         121 :       continue;
    6355         602 :     else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
    6356             :       // A shuffle can only come from building a vector from various
    6357             :       // elements of other vectors.
    6358         140 :       return SDValue();
    6359         323 :     } else if (!isa<ConstantSDNode>(V.getOperand(1))) {
    6360             :       // Furthermore, shuffles require a constant mask, whereas extractelts
    6361             :       // accept variable indices.
    6362           1 :       return SDValue();
    6363             :     }
    6364             : 
    6365             :     // Add this element source to the list if it's not already there.
    6366         320 :     SDValue SourceVec = V.getOperand(0);
    6367         160 :     auto Source = llvm::find(Sources, SourceVec);
    6368         160 :     if (Source == Sources.end())
    6369          58 :       Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
    6370             : 
    6371             :     // Update the minimum and maximum lane number seen.
    6372         640 :     unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
    6373         320 :     Source->MinElt = std::min(Source->MinElt, EltNo);
    6374         320 :     Source->MaxElt = std::max(Source->MaxElt, EltNo);
    6375             :   }
    6376             : 
    6377             :   // Currently only do something sane when at most two source vectors
    6378             :   // are involved.
    6379          32 :   if (Sources.size() > 2)
    6380           0 :     return SDValue();
    6381             : 
    6382             :   // Find out the smallest element size among result and two sources, and use
    6383             :   // it as element size to build the shuffle_vector.
    6384          32 :   EVT SmallestEltTy = VT.getVectorElementType();
    6385         151 :   for (auto &Source : Sources) {
    6386         110 :     EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
    6387          55 :     if (SrcEltTy.bitsLT(SmallestEltTy))
    6388           4 :       SmallestEltTy = SrcEltTy;
    6389             :   }
    6390             :   unsigned ResMultiplier =
    6391          32 :       VT.getScalarSizeInBits() / SmallestEltTy.getSizeInBits();
    6392          32 :   NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
    6393          32 :   EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
    6394             : 
    6395             :   // If the source vector is too wide or too narrow, we may nevertheless be able
    6396             :   // to construct a compatible shuffle either by concatenating it with UNDEF or
    6397             :   // extracting a suitable range of elements.
    6398         146 :   for (auto &Src : Sources) {
    6399         106 :     EVT SrcVT = Src.ShuffleVec.getValueType();
    6400             : 
    6401          53 :     if (SrcVT.getSizeInBits() == VT.getSizeInBits())
    6402          72 :       continue;
    6403             : 
    6404             :     // This stage of the search produces a source with the same element type as
    6405             :     // the original, but with a total width matching the BUILD_VECTOR output.
    6406          21 :     EVT EltVT = SrcVT.getVectorElementType();
    6407          21 :     unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
    6408          21 :     EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
    6409             : 
    6410          29 :     if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
    6411           8 :       if (2 * SrcVT.getSizeInBits() != VT.getSizeInBits())
    6412           0 :         return SDValue();
    6413             :       // We can pad out the smaller vector for free, so if it's part of a
    6414             :       // shuffle...
    6415           8 :       Src.ShuffleVec =
    6416          16 :           DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
    6417          24 :                       DAG.getUNDEF(Src.ShuffleVec.getValueType()));
    6418           8 :       continue;
    6419             :     }
    6420             : 
    6421          13 :     if (SrcVT.getSizeInBits() != 2 * VT.getSizeInBits())
    6422           0 :       return SDValue();
    6423             : 
    6424          13 :     if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
    6425             :       // Span too large for a VEXT to cope
    6426           3 :       return SDValue();
    6427             :     }
    6428             : 
    6429          10 :     if (Src.MinElt >= NumSrcElts) {
    6430             :       // The extraction can just take the second half
    6431           0 :       Src.ShuffleVec =
    6432           0 :           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
    6433           0 :                       DAG.getConstant(NumSrcElts, dl, MVT::i32));
    6434           0 :       Src.WindowBase = -NumSrcElts;
    6435          10 :     } else if (Src.MaxElt < NumSrcElts) {
    6436             :       // The extraction can just take the first half
    6437           9 :       Src.ShuffleVec =
    6438          18 :           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
    6439          27 :                       DAG.getConstant(0, dl, MVT::i32));
    6440             :     } else {
    6441             :       // An actual VEXT is needed
    6442             :       SDValue VEXTSrc1 =
    6443             :           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
    6444           2 :                       DAG.getConstant(0, dl, MVT::i32));
    6445             :       SDValue VEXTSrc2 =
    6446             :           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
    6447           2 :                       DAG.getConstant(NumSrcElts, dl, MVT::i32));
    6448             : 
    6449           1 :       Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
    6450             :                                    VEXTSrc2,
    6451           2 :                                    DAG.getConstant(Src.MinElt, dl, MVT::i32));
    6452           1 :       Src.WindowBase = -Src.MinElt;
    6453             :     }
    6454             :   }
    6455             : 
    6456             :   // Another possible incompatibility occurs from the vector element types. We
    6457             :   // can fix this by bitcasting the source vectors to the same type we intend
    6458             :   // for the shuffle.
    6459         137 :   for (auto &Src : Sources) {
    6460         100 :     EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
    6461          50 :     if (SrcEltTy == SmallestEltTy)
    6462          36 :       continue;
    6463             :     assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
    6464          14 :     Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
    6465          14 :     Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
    6466          14 :     Src.WindowBase *= Src.WindowScale;
    6467             :   }
    6468             : 
    6469             :   // Final sanity check before we try to actually produce a shuffle.
    6470             :   DEBUG(
    6471             :     for (auto Src : Sources)
    6472             :       assert(Src.ShuffleVec.getValueType() == ShuffleVT);
    6473             :   );
    6474             : 
    6475             :   // The stars all align, our next step is to produce the mask for the shuffle.
    6476          58 :   SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
    6477          29 :   int BitsPerShuffleLane = ShuffleVT.getScalarSizeInBits();
    6478         221 :   for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
    6479         384 :     SDValue Entry = Op.getOperand(i);
    6480         384 :     if (Entry.isUndef())
    6481          52 :       continue;
    6482             : 
    6483         420 :     auto Src = llvm::find(Sources, Entry.getOperand(0));
    6484         560 :     int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
    6485             : 
    6486             :     // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
    6487             :     // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
    6488             :     // segment.
    6489         420 :     EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
    6490         420 :     int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
    6491         560 :                                VT.getScalarSizeInBits());
    6492         140 :     int LanesDefined = BitsDefined / BitsPerShuffleLane;
    6493             : 
    6494             :     // This source is expected to fill ResMultiplier lanes of the final shuffle,
    6495             :     // starting at the appropriate offset.
    6496         280 :     int *LaneMask = &Mask[i * ResMultiplier];
    6497             : 
    6498         140 :     int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
    6499         280 :     ExtractBase += NumElts * (Src - Sources.begin());
    6500         280 :     for (int j = 0; j < LanesDefined; ++j)
    6501         140 :       LaneMask[j] = ExtractBase + j;
    6502             :   }
    6503             : 
    6504             :   // Final check before we try to produce nonsense...
    6505          58 :   if (!isShuffleMaskLegal(Mask, ShuffleVT))
    6506           8 :     return SDValue();
    6507             : 
    6508             :   // We can't handle more than two sources. This should have already
    6509             :   // been checked before this point.
    6510             :   assert(Sources.size() <= 2 && "Too many sources!");
    6511             : 
    6512          21 :   SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
    6513         110 :   for (unsigned i = 0; i < Sources.size(); ++i)
    6514          68 :     ShuffleOps[i] = Sources[i].ShuffleVec;
    6515             : 
    6516             :   SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
    6517          21 :                                          ShuffleOps[1], Mask);
    6518          21 :   return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
    6519             : }
    6520             : 
    6521             : /// isShuffleMaskLegal - Targets can use this to indicate that they only
    6522             : /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
    6523             : /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
    6524             : /// are assumed to be legal.
    6525          64 : bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
    6526          95 :   if (VT.getVectorNumElements() == 4 &&
    6527          39 :       (VT.is128BitVector() || VT.is64BitVector())) {
    6528             :     unsigned PFIndexes[4];
    6529             :     for (unsigned i = 0; i != 4; ++i) {
    6530             :       if (M[i] < 0)
    6531             :         PFIndexes[i] = 8;
    6532             :       else
    6533             :         PFIndexes[i] = M[i];
    6534             :     }
    6535             : 
    6536             :     // Compute the index in the perfect shuffle table.
    6537             :     unsigned PFTableIndex =
    6538             :       PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
    6539             :     unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
    6540             :     unsigned Cost = (PFEntry >> 30);
    6541             : 
    6542             :     if (Cost <= 4)
    6543             :       return true;
    6544             :   }
    6545             : 
    6546             :   bool ReverseVEXT, isV_UNDEF;
    6547             :   unsigned Imm, WhichResult;
    6548             : 
    6549          33 :   unsigned EltSize = VT.getScalarSizeInBits();
    6550          25 :   return (EltSize >= 32 ||
    6551          48 :           ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
    6552          46 :           isVREVMask(M, VT, 64) ||
    6553          45 :           isVREVMask(M, VT, 32) ||
    6554          42 :           isVREVMask(M, VT, 16) ||
    6555          20 :           isVEXTMask(M, VT, ReverseVEXT, Imm) ||
    6556          27 :           isVTBLMask(M, VT) ||
    6557          42 :           isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF) ||
    6558          20 :           ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
    6559             : }
    6560             : 
    6561             : /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
    6562             : /// the specified operations to build the shuffle.
    6563         100 : static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
    6564             :                                       SDValue RHS, SelectionDAG &DAG,
    6565             :                                       const SDLoc &dl) {
    6566         100 :   unsigned OpNum = (PFEntry >> 26) & 0x0F;
    6567         100 :   unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
    6568         100 :   unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1);
    6569             : 
    6570             :   enum {
    6571             :     OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
    6572             :     OP_VREV,
    6573             :     OP_VDUP0,
    6574             :     OP_VDUP1,
    6575             :     OP_VDUP2,
    6576             :     OP_VDUP3,
    6577             :     OP_VEXT1,
    6578             :     OP_VEXT2,
    6579             :     OP_VEXT3,
    6580             :     OP_VUZPL, // VUZP, left result
    6581             :     OP_VUZPR, // VUZP, right result
    6582             :     OP_VZIPL, // VZIP, left result
    6583             :     OP_VZIPR, // VZIP, right result
    6584             :     OP_VTRNL, // VTRN, left result
    6585             :     OP_VTRNR  // VTRN, right result
    6586             :   };
    6587             : 
    6588         100 :   if (OpNum == OP_COPY) {
    6589          58 :     if (LHSID == (1*9+2)*9+3) return LHS;
    6590             :     assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
    6591          13 :     return RHS;
    6592             :   }
    6593             : 
    6594          42 :   SDValue OpLHS, OpRHS;
    6595          42 :   OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
    6596          42 :   OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
    6597          84 :   EVT VT = OpLHS.getValueType();
    6598             : 
    6599          42 :   switch (OpNum) {
    6600           0 :   default: llvm_unreachable("Unknown shuffle opcode!");
    6601           3 :   case OP_VREV:
    6602             :     // VREV divides the vector in half and swaps within the half.
    6603           6 :     if (VT.getVectorElementType() == MVT::i32 ||
    6604           4 :         VT.getVectorElementType() == MVT::f32)
    6605           3 :       return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
    6606             :     // vrev <4 x i16> -> VREV32
    6607           0 :     if (VT.getVectorElementType() == MVT::i16)
    6608           0 :       return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
    6609             :     // vrev <4 x i8> -> VREV16
    6610             :     assert(VT.getVectorElementType() == MVT::i8);
    6611           0 :     return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
    6612           7 :   case OP_VDUP0:
    6613             :   case OP_VDUP1:
    6614             :   case OP_VDUP2:
    6615             :   case OP_VDUP3:
    6616             :     return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
    6617          14 :                        OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
    6618          17 :   case OP_VEXT1:
    6619             :   case OP_VEXT2:
    6620             :   case OP_VEXT3:
    6621             :     return DAG.getNode(ARMISD::VEXT, dl, VT,
    6622             :                        OpLHS, OpRHS,
    6623          17 :                        DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
    6624           6 :   case OP_VUZPL:
    6625             :   case OP_VUZPR:
    6626          12 :     return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
    6627          18 :                        OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
    6628           8 :   case OP_VZIPL:
    6629             :   case OP_VZIPR:
    6630          16 :     return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
    6631          24 :                        OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
    6632           1 :   case OP_VTRNL:
    6633             :   case OP_VTRNR:
    6634           2 :     return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
    6635           3 :                        OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
    6636             :   }
    6637             : }
    6638             : 
    6639           7 : static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
    6640             :                                        ArrayRef<int> ShuffleMask,
    6641             :                                        SelectionDAG &DAG) {
    6642             :   // Check to see if we can use the VTBL instruction.
    6643          14 :   SDValue V1 = Op.getOperand(0);
    6644          14 :   SDValue V2 = Op.getOperand(1);
    6645          14 :   SDLoc DL(Op);
    6646             : 
    6647          14 :   SmallVector<SDValue, 8> VTBLMask;
    6648          56 :   for (ArrayRef<int>::iterator
    6649          14 :          I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
    6650          56 :     VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
    6651             : 
    6652           7 :   if (V2.getNode()->isUndef())
    6653             :     return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
    6654          20 :                        DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
    6655             : 
    6656             :   return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
    6657           6 :                      DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
    6658             : }
    6659             : 
    6660           2 : static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
    6661             :                                                       SelectionDAG &DAG) {
    6662           4 :   SDLoc DL(Op);
    6663           4 :   SDValue OpLHS = Op.getOperand(0);
    6664           4 :   EVT VT = OpLHS.getValueType();
    6665             : 
    6666             :   assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
    6667             :          "Expect an v8i16/v16i8 type");
    6668           2 :   OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
    6669             :   // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
    6670             :   // extract the first 8 bytes into the top double word and the last 8 bytes
    6671             :   // into the bottom double word. The v8i16 case is similar.
    6672           4 :   unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
    6673             :   return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
    6674           4 :                      DAG.getConstant(ExtractNum, DL, MVT::i32));
    6675             : }
    6676             : 
    6677         358 : static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
    6678         716 :   SDValue V1 = Op.getOperand(0);
    6679         716 :   SDValue V2 = Op.getOperand(1);
    6680         716 :   SDLoc dl(Op);
    6681         716 :   EVT VT = Op.getValueType();
    6682         716 :   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
    6683             : 
    6684             :   // Convert shuffles that are directly supported on NEON to target-specific
    6685             :   // DAG nodes, instead of keeping them as shuffles and matching them again
    6686             :   // during code selection.  This is more efficient and avoids the possibility
    6687             :   // of inconsistencies between legalization and selection.
    6688             :   // FIXME: floating-point vectors should be canonicalized to integer vectors
    6689             :   // of the same time so that they get CSEd properly.
    6690         358 :   ArrayRef<int> ShuffleMask = SVN->getMask();
    6691             : 
    6692         358 :   unsigned EltSize = VT.getScalarSizeInBits();
    6693         358 :   if (EltSize <= 32) {
    6694         328 :     if (SVN->isSplat()) {
    6695         103 :       int Lane = SVN->getSplatIndex();
    6696             :       // If this is undef splat, generate it via "just" vdup, if possible.
    6697         103 :       if (Lane == -1) Lane = 0;
    6698             : 
    6699             :       // Test if V1 is a SCALAR_TO_VECTOR.
    6700         142 :       if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
    6701           4 :         return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
    6702             :       }
    6703             :       // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
    6704             :       // (and probably will turn into a SCALAR_TO_VECTOR once legalization
    6705             :       // reaches it).
    6706         175 :       if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
    6707           0 :           !isa<ConstantSDNode>(V1.getOperand(0))) {
    6708           0 :         bool IsScalarToVector = true;
    6709           0 :         for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
    6710           0 :           if (!V1.getOperand(i).isUndef()) {
    6711             :             IsScalarToVector = false;
    6712             :             break;
    6713             :           }
    6714           0 :         if (IsScalarToVector)
    6715           0 :           return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
    6716             :       }
    6717             :       return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
    6718         202 :                          DAG.getConstant(Lane, dl, MVT::i32));
    6719             :     }
    6720             : 
    6721             :     bool ReverseVEXT;
    6722             :     unsigned Imm;
    6723         225 :     if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
    6724          11 :       if (ReverseVEXT)
    6725             :         std::swap(V1, V2);
    6726             :       return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
    6727          11 :                          DAG.getConstant(Imm, dl, MVT::i32));
    6728             :     }
    6729             : 
    6730         214 :     if (isVREVMask(ShuffleMask, VT, 64))
    6731          10 :       return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
    6732         204 :     if (isVREVMask(ShuffleMask, VT, 32))
    6733           6 :       return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
    6734         198 :     if (isVREVMask(ShuffleMask, VT, 16))
    6735           2 :       return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
    6736             : 
    6737         196 :     if (V2->isUndef() && isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
    6738             :       return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
    6739           4 :                          DAG.getConstant(Imm, dl, MVT::i32));
    6740             :     }
    6741             : 
    6742             :     // Check for Neon shuffles that modify both input vectors in place.
    6743             :     // If both results are used, i.e., if there are two shuffles with the same
    6744             :     // source operands and with masks corresponding to both results of one of
    6745             :     // these operations, DAG memoization will ensure that a single node is
    6746             :     // used for both shuffles.
    6747             :     unsigned WhichResult;
    6748             :     bool isV_UNDEF;
    6749         192 :     if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
    6750         192 :             ShuffleMask, VT, WhichResult, isV_UNDEF)) {
    6751         146 :       if (isV_UNDEF)
    6752           8 :         V2 = V1;
    6753         292 :       return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)
    6754         292 :           .getValue(WhichResult);
    6755             :     }
    6756             : 
    6757             :     // Also check for these shuffles through CONCAT_VECTORS: we canonicalize
    6758             :     // shuffles that produce a result larger than their operands with:
    6759             :     //   shuffle(concat(v1, undef), concat(v2, undef))
    6760             :     // ->
    6761             :     //   shuffle(concat(v1, v2), undef)
    6762             :     // because we can access quad vectors (see PerformVECTOR_SHUFFLECombine).
    6763             :     //
    6764             :     // This is useful in the general case, but there are special cases where
    6765             :     // native shuffles produce larger results: the two-result ops.
    6766             :     //
    6767             :     // Look through the concat when lowering them:
    6768             :     //   shuffle(concat(v1, v2), undef)
    6769             :     // ->
    6770             :     //   concat(VZIP(v1, v2):0, :1)
    6771             :     //
    6772          46 :     if (V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) {
    6773          48 :       SDValue SubV1 = V1->getOperand(0);
    6774          48 :       SDValue SubV2 = V1->getOperand(1);
    6775          48 :       EVT SubVT = SubV1.getValueType();
    6776             : 
    6777             :       // We expect these to have been canonicalized to -1.
    6778             :       assert(llvm::all_of(ShuffleMask, [&](int i) {
    6779             :         return i < (int)VT.getVectorNumElements();
    6780             :       }) && "Unexpected shuffle index into UNDEF operand!");
    6781             : 
    6782          24 :       if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
    6783          24 :               ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
    6784          13 :         if (isV_UNDEF)
    6785           0 :           SubV2 = SubV1;
    6786             :         assert((WhichResult == 0) &&
    6787             :                "In-place shuffle of concat can only have one result!");
    6788             :         SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
    6789          13 :                                   SubV1, SubV2);
    6790             :         return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
    6791          39 :                            Res.getValue(1));
    6792             :       }
    6793             :     }
    6794             :   }
    6795             : 
    6796             :   // If the shuffle is not directly supported and it has 4 elements, use
    6797             :   // the PerfectShuffle-generated table to synthesize it from other shuffles.
    6798          63 :   unsigned NumElts = VT.getVectorNumElements();
    6799          63 :   if (NumElts == 4) {
    6800             :     unsigned PFIndexes[4];
    6801         144 :     for (unsigned i = 0; i != 4; ++i) {
    6802         128 :       if (ShuffleMask[i] < 0)
    6803           6 :         PFIndexes[i] = 8;
    6804             :       else
    6805          58 :         PFIndexes[i] = ShuffleMask[i];
    6806             :     }
    6807             : 
    6808             :     // Compute the index in the perfect shuffle table.
    6809          16 :     unsigned PFTableIndex =
    6810          16 :       PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
    6811          16 :     unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
    6812          16 :     unsigned Cost = (PFEntry >> 30);
    6813             : 
    6814             :     if (Cost <= 4)
    6815          16 :       return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
    6816             :   }
    6817             : 
    6818             :   // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
    6819          47 :   if (EltSize >= 32) {
    6820             :     // Do the expansion with floating-point types, since that is what the VFP
    6821             :     // registers are defined to use, and since i64 is not legal.
    6822          31 :     EVT EltVT = EVT::getFloatingPointVT(EltSize);
    6823          31 :     EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
    6824          31 :     V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
    6825          31 :     V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
    6826          62 :     SmallVector<SDValue, 8> Ops;
    6827          93 :     for (unsigned i = 0; i < NumElts; ++i) {
    6828         124 :       if (ShuffleMask[i] < 0)
    6829           8 :         Ops.push_back(DAG.getUNDEF(EltVT));
    6830             :       else
    6831          54 :         Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
    6832          54 :                                   ShuffleMask[i] < (int)NumElts ? V1 : V2,
    6833          54 :                                   DAG.getConstant(ShuffleMask[i] & (NumElts-1),
    6834         216 :                                                   dl, MVT::i32)));
    6835             :     }
    6836          62 :     SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
    6837          31 :     return DAG.getNode(ISD::BITCAST, dl, VT, Val);
    6838             :   }
    6839             : 
    6840          33 :   if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
    6841           2 :     return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
    6842             : 
    6843          21 :   if (VT == MVT::v8i8)
    6844           7 :     if (SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG))
    6845           7 :       return NewOp;
    6846             : 
    6847           7 :   return SDValue();
    6848             : }
    6849             : 
    6850             : static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
    6851             :   // INSERT_VECTOR_ELT is legal only for immediate indexes.
    6852        1896 :   SDValue Lane = Op.getOperand(2);
    6853             :   if (!isa<ConstantSDNode>(Lane))
    6854             :     return SDValue();
    6855             : 
    6856             :   return Op;
    6857             : }
    6858             : 
    6859        5545 : static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
    6860             :   // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
    6861       11090 :   SDValue Lane = Op.getOperand(1);
    6862           8 :   if (!isa<ConstantSDNode>(Lane))
    6863           8 :     return SDValue();
    6864             : 
    6865       11074 :   SDValue Vec = Op.getOperand(0);
    6866       11981 :   if (Op.getValueType() == MVT::i32 && Vec.getScalarValueSizeInBits() < 32) {
    6867         162 :     SDLoc dl(Op);
    6868         162 :     return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
    6869             :   }
    6870             : 
    6871        5456 :   return Op;
    6872             : }
    6873             : 
    6874           4 : static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
    6875             :   // The only time a CONCAT_VECTORS operation can have legal types is when
    6876             :   // two 64-bit vectors are concatenated to a 128-bit vector.
    6877             :   assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
    6878             :          "unexpected CONCAT_VECTORS");
    6879           8 :   SDLoc dl(Op);
    6880           4 :   SDValue Val = DAG.getUNDEF(MVT::v2f64);
    6881           8 :   SDValue Op0 = Op.getOperand(0);
    6882           8 :   SDValue Op1 = Op.getOperand(1);
    6883           8 :   if (!Op0.isUndef())
    6884           4 :     Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
    6885           4 :                       DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
    6886          20 :                       DAG.getIntPtrConstant(0, dl));
    6887           8 :   if (!Op1.isUndef())
    6888           4 :     Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
    6889           4 :                       DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
    6890          20 :                       DAG.getIntPtrConstant(1, dl));
    6891          12 :   return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
    6892             : }
    6893             : 
    6894             : /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
    6895             : /// element has been zero/sign-extended, depending on the isSigned parameter,
    6896             : /// from an integer type half its size.
    6897         518 : static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
    6898             :                                    bool isSigned) {
    6899             :   // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
    6900        1036 :   EVT VT = N->getValueType(0);
    6901         536 :   if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
    6902          10 :     SDNode *BVN = N->getOperand(0).getNode();
    6903          15 :     if (BVN->getValueType(0) != MVT::v4i32 ||
    6904             :         BVN->getOpcode() != ISD::BUILD_VECTOR)
    6905             :       return false;
    6906          10 :     unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
    6907           5 :     unsigned HiElt = 1 - LoElt;
    6908          15 :     ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
    6909          15 :     ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
    6910          15 :     ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
    6911          15 :     ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
    6912           5 :     if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
    6913             :       return false;
    6914           5 :     if (isSigned) {
    6915           8 :       if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
    6916           4 :           Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
    6917             :         return true;
    6918             :     } else {
    6919           2 :       if (Hi0->isNullValue() && Hi1->isNullValue())
    6920             :         return true;
    6921             :     }
    6922             :     return false;
    6923             :   }
    6924             : 
    6925         513 :   if (N->getOpcode() != ISD::BUILD_VECTOR)
    6926             :     return false;
    6927             : 
    6928         118 :   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
    6929         156 :     SDNode *Elt = N->getOperand(i).getNode();
    6930          66 :     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
    6931          66 :       unsigned EltSize = VT.getScalarSizeInBits();
    6932          66 :       unsigned HalfSize = EltSize / 2;
    6933          66 :       if (isSigned) {
    6934          34 :         if (!isIntN(HalfSize, C->getSExtValue()))
    6935             :           return false;
    6936             :       } else {
    6937          32 :         if (!isUIntN(HalfSize, C->getZExtValue()))
    6938             :           return false;
    6939             :       }
    6940          56 :       continue;
    6941             :     }
    6942             :     return false;
    6943             :   }
    6944             : 
    6945             :   return true;
    6946             : }
    6947             : 
    6948             : /// isSignExtended - Check if a node is a vector value that is sign-extended
    6949             : /// or a constant BUILD_VECTOR with sign-extended elements.
    6950         354 : static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
    6951         708 :   if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
    6952             :     return true;
    6953         274 :   if (isExtendedBUILD_VECTOR(N, DAG, true))
    6954             :     return true;
    6955         265 :   return false;
    6956             : }
    6957             : 
    6958             : /// isZeroExtended - Check if a node is a vector value that is zero-extended
    6959             : /// or a constant BUILD_VECTOR with zero-extended elements.
    6960         292 : static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
    6961         584 :   if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
    6962             :     return true;
    6963         244 :   if (isExtendedBUILD_VECTOR(N, DAG, false))
    6964             :     return true;
    6965         239 :   return false;
    6966             : }
    6967             : 
    6968          59 : static EVT getExtensionTo64Bits(const EVT &OrigVT) {
    6969          59 :   if (OrigVT.getSizeInBits() >= 64)
    6970          46 :     return OrigVT;
    6971             : 
    6972             :   assert(OrigVT.isSimple() && "Expecting a simple value type");
    6973             : 
    6974          13 :   MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
    6975          13 :   switch (OrigSimpleTy) {
    6976           0 :   default: llvm_unreachable("Unexpected Vector Type");
    6977           9 :   case MVT::v2i8:
    6978             :   case MVT::v2i16:
    6979           9 :      return MVT::v2i32;
    6980           4 :   case MVT::v4i8:
    6981           4 :     return  MVT::v4i16;
    6982             :   }
    6983             : }
    6984             : 
    6985             : /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
    6986             : /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
    6987             : /// We insert the required extension here to get the vector to fill a D register.
    6988          38 : static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
    6989             :                                             const EVT &OrigTy,
    6990             :                                             const EVT &ExtTy,
    6991             :                                             unsigned ExtOpcode) {
    6992             :   // The vector originally had a size of OrigTy. It was then extended to ExtTy.
    6993             :   // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
    6994             :   // 64-bits we need to insert a new extension so that it will be 64-bits.
    6995             :   assert(ExtTy.is128BitVector() && "Unexpected extension size");
    6996          38 :   if (OrigTy.getSizeInBits() >= 64)
    6997          38 :     return N;
    6998             : 
    6999             :   // Must extend size to at least 64 bits to be used as an operand for VMULL.
    7000           0 :   EVT NewVT = getExtensionTo64Bits(OrigTy);
    7001             : 
    7002           0 :   return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
    7003             : }
    7004             : 
    7005             : /// SkipLoadExtensionForVMULL - return a load of the original vector size that
    7006             : /// does not do any sign/zero extension. If the original vector is less
    7007             : /// than 64 bits, an appropriate extension will be added after the load to
    7008             : /// reach a total size of 64 bits. We have to add the extension separately
    7009             : /// because ARM does not have a sign/zero extending load for vectors.
    7010          59 : static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
    7011          59 :   EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
    7012             : 
    7013             :   // The load already has the right type.
    7014          59 :   if (ExtendedTy == LD->getMemoryVT())
    7015         184 :     return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
    7016         138 :                        LD->getBasePtr(), LD->getPointerInfo(),
    7017         138 :                        LD->getAlignment(), LD->getMemOperand()->getFlags());
    7018             : 
    7019             :   // We need to create a zextload/sextload. We cannot just create a load
    7020             :   // followed by a zext/zext node because LowerMUL is also run during normal
    7021             :   // operation legalization where we can't create illegal types.
    7022          26 :   return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
    7023          52 :                         LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
    7024             :                         LD->getMemoryVT(), LD->getAlignment(),
    7025          52 :                         LD->getMemOperand()->getFlags());
    7026             : }
    7027             : 
    7028             : /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
    7029             : /// extending load, or BUILD_VECTOR with extended elements, return the
    7030             : /// unextended value. The unextended vector should be 64 bits so that it can
    7031             : /// be used as an operand to a VMULL instruction. If the original vector size
    7032             : /// before extension is less than 64 bits we add a an extension to resize
    7033             : /// the vector to 64 bits.
    7034         106 : static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
    7035         212 :   if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
    7036          76 :     return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
    7037         152 :                                         N->getOperand(0)->getValueType(0),
    7038          76 :                                         N->getValueType(0),
    7039          76 :                                         N->getOpcode());
    7040             : 
    7041          59 :   if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
    7042             :     assert((ISD::isSEXTLoad(LD) || ISD::isZEXTLoad(LD)) &&
    7043             :            "Expected extending load");
    7044             : 
    7045          59 :     SDValue newLoad = SkipLoadExtensionForVMULL(LD, DAG);
    7046         177 :     DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), newLoad.getValue(1));
    7047          41 :     unsigned Opcode = ISD::isSEXTLoad(LD) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
    7048             :     SDValue extLoad =
    7049         236 :         DAG.getNode(Opcode, SDLoc(newLoad), LD->getValueType(0), newLoad);
    7050          59 :     DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 0), extLoad);
    7051             : 
    7052          59 :     return newLoad;
    7053             :   }
    7054             : 
    7055             :   // Otherwise, the value must be a BUILD_VECTOR.  For v2i64, it will
    7056             :   // have been legalized as a BITCAST from v4i32.
    7057           9 :   if (N->getOpcode() == ISD::BITCAST) {
    7058           8 :     SDNode *BVN = N->getOperand(0).getNode();
    7059             :     assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
    7060             :            BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
    7061           8 :     unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
    7062             :     return DAG.getBuildVector(
    7063           8 :         MVT::v2i32, SDLoc(N),
    7064          24 :         {BVN->getOperand(LowElt), BVN->getOperand(LowElt + 2)});
    7065             :   }
    7066             :   // Construct a new BUILD_VECTOR with elements truncated to half the size.
    7067             :   assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
    7068          10 :   EVT VT = N->getValueType(0);
    7069           5 :   unsigned EltSize = VT.getScalarSizeInBits() / 2;
    7070           5 :   unsigned NumElts = VT.getVectorNumElements();
    7071           5 :   MVT TruncVT = MVT::getIntegerVT(EltSize);
    7072           5 :   SmallVector<SDValue, 8> Ops;
    7073          10 :   SDLoc dl(N);
    7074          33 :   for (unsigned i = 0; i != NumElts; ++i) {
    7075          84 :     ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
    7076          28 :     const APInt &CInt = C->getAPIntValue();
    7077             :     // Element types smaller than 32 bits are not legal, so use i32 elements.
    7078             :     // The values are implicitly truncated so sext vs. zext doesn't matter.
    7079          56 :     Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
    7080             :   }
    7081          10 :   return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops);
    7082             : }
    7083             : 
    7084          16 : static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
    7085          32 :   unsigned Opcode = N->getOpcode();
    7086          16 :   if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
    7087           0 :     SDNode *N0 = N->getOperand(0).getNode();
    7088           0 :     SDNode *N1 = N->getOperand(1).getNode();
    7089           0 :     return N0->hasOneUse() && N1->hasOneUse() &&
    7090           0 :       isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
    7091             :   }
    7092             :   return false;
    7093             : }
    7094             : 
    7095           6 : static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
    7096          12 :   unsigned Opcode = N->getOpcode();
    7097           6 :   if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
    7098           0 :     SDNode *N0 = N->getOperand(0).getNode();
    7099           0 :     SDNode *N1 = N->getOperand(1).getNode();
    7100           0 :     return N0->hasOneUse() && N1->hasOneUse() &&
    7101           0 :       isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
    7102             :   }
    7103             :   return false;
    7104             : }
    7105             : 
    7106         177 : static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
    7107             :   // Multiplications are only custom-lowered for 128-bit vectors so that
    7108             :   // VMULL can be detected.  Otherwise v2i64 multiplications are not legal.
    7109         354 :   EVT VT = Op.getValueType();
    7110             :   assert(VT.is128BitVector() && VT.isInteger() &&
    7111             :          "unexpected type for custom-lowering ISD::MUL");
    7112         354 :   SDNode *N0 = Op.getOperand(0).getNode();
    7113         354 :   SDNode *N1 = Op.getOperand(1).getNode();
    7114         177 :   unsigned NewOpc = 0;
    7115         177 :   bool isMLA = false;
    7116         177 :   bool isN0SExt = isSignExtended(N0, DAG);
    7117         177 :   bool isN1SExt = isSignExtended(N1, DAG);
    7118         177 :   if (isN0SExt && isN1SExt)
    7119             :     NewOpc = ARMISD::VMULLs;
    7120             :   else {
    7121         146 :     bool isN0ZExt = isZeroExtended(N0, DAG);
    7122         146 :     bool isN1ZExt = isZeroExtended(N1, DAG);
    7123         146 :     if (isN0ZExt && isN1ZExt)
    7124             :       NewOpc = ARMISD::VMULLu;
    7125         124 :     else if (isN1SExt || isN1ZExt) {
    7126             :       // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
    7127             :       // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
    7128          18 :       if (isN1SExt && isAddSubSExt(N0, DAG)) {
    7129             :         NewOpc = ARMISD::VMULLs;
    7130             :         isMLA = true;
    7131          18 :       } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
    7132             :         NewOpc = ARMISD::VMULLu;
    7133             :         isMLA = true;
    7134          18 :       } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
    7135             :         std::swap(N0, N1);
    7136             :         NewOpc = ARMISD::VMULLu;
    7137             :         isMLA = true;
    7138             :       }
    7139             :     }
    7140             : 
    7141         146 :     if (!NewOpc) {
    7142         248 :       if (VT == MVT::v2i64)
    7143             :         // Fall through to expand this.  It is not legal.
    7144           0 :         return SDValue();
    7145             :       else
    7146             :         // Other vector multiplications are legal.
    7147         124 :         return Op;
    7148             :     }
    7149             :   }
    7150             : 
    7151             :   // Legalize to a VMULL instruction.
    7152          53 :   SDLoc DL(Op);
    7153          53 :   SDValue Op0;
    7154          53 :   SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
    7155          53 :   if (!isMLA) {
    7156          53 :     Op0 = SkipExtensionForVMULL(N0, DAG);
    7157             :     assert(Op0.getValueType().is64BitVector() &&
    7158             :            Op1.getValueType().is64BitVector() &&
    7159             :            "unexpected types for extended operands to VMULL");
    7160          53 :     return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
    7161             :   }
    7162             : 
    7163             :   // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
    7164             :   // isel lowering to take advantage of no-stall back to back vmul + vmla.
    7165             :   //   vmull q0, d4, d6
    7166             :   //   vmlal q0, d5, d6
    7167             :   // is faster than
    7168             :   //   vaddl q0, d4, d5
    7169             :   //   vmovl q1, d6
    7170             :   //   vmul  q0, q0, q1
    7171           0 :   SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
    7172           0 :   SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
    7173           0 :   EVT Op1VT = Op1.getValueType();
    7174             :   return DAG.getNode(N0->getOpcode(), DL, VT,
    7175             :                      DAG.getNode(NewOpc, DL, VT,
    7176             :                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
    7177             :                      DAG.getNode(NewOpc, DL, VT,
    7178           0 :                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
    7179             : }
    7180             : 
    7181           4 : static SDValue LowerSDIV_v4i8(SDValue X, SDValue Y, const SDLoc &dl,
    7182             :                               SelectionDAG &DAG) {
    7183             :   // TODO: Should this propagate fast-math-flags?
    7184             : 
    7185             :   // Convert to float
    7186             :   // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
    7187             :   // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
    7188           8 :   X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
    7189           8 :   Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
    7190           8 :   X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
    7191           8 :   Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
    7192             :   // Get reciprocal estimate.
    7193             :   // float4 recip = vrecpeq_f32(yf);
    7194           4 :   Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
    7195           4 :                    DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
    7196          16 :                    Y);
    7197             :   // Because char has a smaller range than uchar, we can actually get away
    7198             :   // without any newton steps.  This requires that we use a weird bias
    7199             :   // of 0xb000, however (again, this has been exhaustively tested).
    7200             :   // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
    7201           8 :   X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
    7202           8 :   X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
    7203           4 :   Y = DAG.getConstant(0xb000, dl, MVT::v4i32);
    7204           8 :   X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
    7205           8 :   X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
    7206             :   // Convert back to short.
    7207           8 :   X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
    7208           8 :   X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
    7209           4 :   return X;
    7210             : }
    7211             : 
    7212           7 : static SDValue LowerSDIV_v4i16(SDValue N0, SDValue N1, const SDLoc &dl,
    7213             :                                SelectionDAG &DAG) {
    7214             :   // TODO: Should this propagate fast-math-flags?
    7215             : 
    7216           7 :   SDValue N2;
    7217             :   // Convert to float.
    7218             :   // float4 yf = vcvt_f32_s32(vmovl_s16(y));
    7219             :   // float4 xf = vcvt_f32_s32(vmovl_s16(x));
    7220          14 :   N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
    7221          14 :   N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
    7222          14 :   N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
    7223          14 :   N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
    7224             : 
    7225             :   // Use reciprocal estimate and one refinement step.
    7226             :   // float4 recip = vrecpeq_f32(yf);
    7227             :   // recip *= vrecpsq_f32(yf, recip);
    7228           7 :   N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
    7229           7 :                    DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
    7230          28 :                    N1);
    7231           7 :   N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
    7232           7 :                    DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
    7233          21 :                    N1, N2);
    7234          14 :   N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
    7235             :   // Because short has a smaller range than ushort, we can actually get away
    7236             :   // with only a single newton step.  This requires that we use a weird bias
    7237             :   // of 89, however (again, this has been exhaustively tested).
    7238             :   // float4 result = as_float4(as_int4(xf*recip) + 0x89);
    7239          14 :   N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
    7240          14 :   N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
    7241           7 :   N1 = DAG.getConstant(0x89, dl, MVT::v4i32);
    7242          14 :   N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
    7243          14 :   N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
    7244             :   // Convert back to integer and return.
    7245             :   // return vmovn_s32(vcvt_s32_f32(result));
    7246          14 :   N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
    7247          14 :   N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
    7248           7 :   return N0;
    7249             : }
    7250             : 
    7251           5 : static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
    7252          10 :   EVT VT = Op.getValueType();
    7253             :   assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
    7254             :          "unexpected type for custom-lowering ISD::SDIV");
    7255             : 
    7256          10 :   SDLoc dl(Op);
    7257          10 :   SDValue N0 = Op.getOperand(0);
    7258          10 :   SDValue N1 = Op.getOperand(1);
    7259           5 :   SDValue N2, N3;
    7260             : 
    7261          10 :   if (VT == MVT::v8i8) {
    7262           4 :     N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
    7263           4 :     N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
    7264             : 
    7265           2 :     N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
    7266           6 :                      DAG.getIntPtrConstant(4, dl));
    7267           2 :     N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
    7268           6 :                      DAG.getIntPtrConstant(4, dl));
    7269           2 :     N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
    7270           6 :                      DAG.getIntPtrConstant(0, dl));
    7271           2 :     N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
    7272           6 :                      DAG.getIntPtrConstant(0, dl));
    7273             : 
    7274           2 :     N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
    7275           2 :     N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
    7276             : 
    7277           4 :     N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
    7278           2 :     N0 = LowerCONCAT_VECTORS(N0, DAG);
    7279             : 
    7280           4 :     N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
    7281           2 :     return N0;
    7282             :   }
    7283           3 :   return LowerSDIV_v4i16(N0, N1, dl, DAG);
    7284             : }
    7285             : 
    7286           4 : static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
    7287             :   // TODO: Should this propagate fast-math-flags?
    7288           8 :   EVT VT = Op.getValueType();
    7289             :   assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
    7290             :          "unexpected type for custom-lowering ISD::UDIV");
    7291             : 
    7292           8 :   SDLoc dl(Op);
    7293           8 :   SDValue N0 = Op.getOperand(0);
    7294           8 :   SDValue N1 = Op.getOperand(1);
    7295           4 :   SDValue N2, N3;
    7296             : 
    7297           8 :   if (VT == MVT::v8i8) {
    7298           4 :     N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
    7299           4 :     N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
    7300             : 
    7301           2 :     N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
    7302           6 :                      DAG.getIntPtrConstant(4, dl));
    7303           2 :     N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
    7304           6 :                      DAG.getIntPtrConstant(4, dl));
    7305           2 :     N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
    7306           6 :                      DAG.getIntPtrConstant(0, dl));
    7307           2 :     N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
    7308           6 :                      DAG.getIntPtrConstant(0, dl));
    7309             : 
    7310           2 :     N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
    7311           2 :     N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
    7312             : 
    7313           4 :     N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
    7314           2 :     N0 = LowerCONCAT_VECTORS(N0, DAG);
    7315             : 
    7316           2 :     N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
    7317             :                      DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
    7318           2 :                                      MVT::i32),
    7319           8 :                      N0);
    7320           2 :     return N0;
    7321             :   }
    7322             : 
    7323             :   // v4i16 sdiv ... Convert to float.
    7324             :   // float4 yf = vcvt_f32_s32(vmovl_u16(y));
    7325             :   // float4 xf = vcvt_f32_s32(vmovl_u16(x));
    7326           4 :   N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
    7327           4 :   N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
    7328           4 :   N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
    7329           4 :   SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
    7330             : 
    7331             :   // Use reciprocal estimate and two refinement steps.
    7332             :   // float4 recip = vrecpeq_f32(yf);
    7333             :   // recip *= vrecpsq_f32(yf, recip);
    7334             :   // recip *= vrecpsq_f32(yf, recip);
    7335           2 :   N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
    7336           2 :                    DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
    7337           8 :                    BN1);
    7338           2 :   N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
    7339           2 :                    DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
    7340           6 :                    BN1, N2);
    7341           4 :   N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
    7342           2 :   N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
    7343           2 :                    DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
    7344           6 :                    BN1, N2);
    7345           4 :   N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
    7346             :   // Simply multiplying by the reciprocal estimate can leave us a few ulps
    7347             :   // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
    7348             :   // and that it will never cause us to return an answer too large).
    7349             :   // float4 result = as_float4(as_int4(xf*recip) + 2);
    7350           4 :   N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
    7351           4 :   N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
    7352           2 :   N1 = DAG.getConstant(2, dl, MVT::v4i32);
    7353           4 :   N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
    7354           4 :   N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
    7355             :   // Convert back to integer and return.
    7356             :   // return vmovn_u32(vcvt_s32_f32(result));
    7357           4 :   N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
    7358           4 :   N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
    7359           2 :   return N0;
    7360             : }
    7361             : 
    7362         996 : static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
    7363        1992 :   EVT VT = Op.getNode()->getValueType(0);
    7364         996 :   SDVTList VTs = DAG.getVTList(VT, MVT::i32);
    7365             : 
    7366             :   unsigned Opc;
    7367         996 :   bool ExtraOp = false;
    7368        1992 :   switch (Op.getOpcode()) {
    7369           0 :   default: llvm_unreachable("Invalid code");
    7370             :   case ISD::ADDC: Opc = ARMISD::ADDC; break;
    7371         436 :   case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
    7372         120 :   case ISD::SUBC: Opc = ARMISD::SUBC; break;
    7373          39 :   case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
    7374             :   }
    7375             : 
    7376         996 :   if (!ExtraOp)
    7377        2084 :     return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
    7378        1563 :                        Op.getOperand(1));
    7379        1900 :   return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
    7380        1900 :                      Op.getOperand(1), Op.getOperand(2));
    7381             : }
    7382             : 
    7383           5 : SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
    7384             :   assert(Subtarget->isTargetDarwin());
    7385             : 
    7386             :   // For iOS, we want to call an alternative entry point: __sincos_stret,
    7387             :   // return values are passed via sret.
    7388          10 :   SDLoc dl(Op);
    7389          10 :   SDValue Arg = Op.getOperand(0);
    7390          10 :   EVT ArgVT = Arg.getValueType();
    7391           5 :   Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
    7392          15 :   auto PtrVT = getPointerTy(DAG.getDataLayout());
    7393             : 
    7394           5 :   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
    7395           5 :   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
    7396             : 
    7397             :   // Pair of floats / doubles used to pass the result.
    7398           5 :   Type *RetTy = StructType::get(ArgTy, ArgTy);
    7399          10 :   auto &DL = DAG.getDataLayout();
    7400             : 
    7401          10 :   ArgListTy Args;
    7402           5 :   bool ShouldUseSRet = Subtarget->isAPCS_ABI();
    7403           5 :   SDValue SRet;
    7404           5 :   if (ShouldUseSRet) {
    7405             :     // Create stack object for sret.
    7406           2 :     const uint64_t ByteSize = DL.getTypeAllocSize(RetTy);
    7407           2 :     const unsigned StackAlign = DL.getPrefTypeAlignment(RetTy);
    7408           2 :     int FrameIdx = MFI.CreateStackObject(ByteSize, StackAlign, false);
    7409           6 :     SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy(DL));
    7410             : 
    7411           2 :     ArgListEntry Entry;
    7412           2 :     Entry.Node = SRet;
    7413           2 :     Entry.Ty = RetTy->getPointerTo();
    7414           2 :     Entry.IsSExt = false;
    7415           2 :     Entry.IsZExt = false;
    7416           2 :     Entry.IsSRet = true;
    7417           2 :     Args.push_back(Entry);
    7418           2 :     RetTy = Type::getVoidTy(*DAG.getContext());
    7419             :   }
    7420             : 
    7421           5 :   ArgListEntry Entry;
    7422           5 :   Entry.Node = Arg;
    7423           5 :   Entry.Ty = ArgTy;
    7424             :   Entry.IsSExt = false;
    7425             :   Entry.IsZExt = false;
    7426           5 :   Args.push_back(Entry);
    7427             : 
    7428             :   const char *LibcallName =
    7429          10 :       (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
    7430             :   RTLIB::Libcall LC =
    7431          10 :       (ArgVT == MVT::f64) ? RTLIB::SINCOS_F64 : RTLIB::SINCOS_F32;
    7432          10 :   CallingConv::ID CC = getLibcallCallingConv(LC);
    7433          15 :   SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL));
    7434             : 
    7435          10 :   TargetLowering::CallLoweringInfo CLI(DAG);
    7436           5 :   CLI.setDebugLoc(dl)
    7437          10 :       .setChain(DAG.getEntryNode())
    7438          10 :       .setCallee(CC, RetTy, Callee, std::move(Args))
    7439          10 :       .setDiscardResult(ShouldUseSRet);
    7440           5 :   std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
    7441             : 
    7442           5 :   if (!ShouldUseSRet)
    7443           3 :     return CallResult.first;
    7444             : 
    7445             :   SDValue LoadSin =
    7446           4 :       DAG.getLoad(ArgVT, dl, CallResult.second, SRet, MachinePointerInfo());
    7447             : 
    7448             :   // Address of cos field.
    7449             :   SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet,
    7450           6 :                             DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
    7451             :   SDValue LoadCos =
    7452           6 :       DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add, MachinePointerInfo());
    7453             : 
    7454           2 :   SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
    7455             :   return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
    7456           6 :                      LoadSin.getValue(0), LoadCos.getValue(0));
    7457             : }
    7458             : 
    7459          27 : SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
    7460             :                                                   bool Signed,
    7461             :                                                   SDValue &Chain) const {
    7462          54 :   EVT VT = Op.getValueType();
    7463             :   assert((VT == MVT::i32 || VT == MVT::i64) &&
    7464             :          "unexpected type for custom lowering DIV");
    7465          54 :   SDLoc dl(Op);
    7466             : 
    7467          54 :   const auto &DL = DAG.getDataLayout();
    7468          27 :   const auto &TLI = DAG.getTargetLoweringInfo();
    7469             : 
    7470          27 :   const char *Name = nullptr;
    7471          27 :   if (Signed)
    7472          42 :     Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64";
    7473             :   else
    7474          12 :     Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";
    7475             : 
    7476          81 :   SDValue ES = DAG.getExternalSymbol(Name, TLI.getPointerTy(DL));
    7477             : 
    7478          54 :   ARMTargetLowering::ArgListTy Args;
    7479             : 
    7480         108 :   for (auto AI : {1, 0}) {
    7481          54 :     ArgListEntry Arg;
    7482         108 :     Arg.Node = Op.getOperand(AI);
    7483         108 :     Arg.Ty = Arg.Node.getValueType().getTypeForEVT(*DAG.getContext());
    7484          54 :     Args.push_back(Arg);
    7485             :   }
    7486             : 
    7487          54 :   CallLoweringInfo CLI(DAG);
    7488          27 :   CLI.setDebugLoc(dl)
    7489          27 :     .setChain(Chain)
    7490          54 :     .setCallee(CallingConv::ARM_AAPCS_VFP, VT.getTypeForEVT(*DAG.getContext()),
    7491          54 :                ES, std::move(Args));
    7492             : 
    7493          54 :   return LowerCallTo(CLI).first;
    7494             : }
    7495             : 
    7496          23 : SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
    7497             :                                             bool Signed) const {
    7498             :   assert(Op.getValueType() == MVT::i32 &&
    7499             :          "unexpected type for custom lowering DIV");
    7500          46 :   SDLoc dl(Op);
    7501             : 
    7502             :   SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other,
    7503          92 :                                DAG.getEntryNode(), Op.getOperand(1));
    7504             : 
    7505          46 :   return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
    7506             : }
    7507             : 
    7508          45 : static SDValue WinDBZCheckDenominator(SelectionDAG &DAG, SDNode *N, SDValue InChain) {
    7509          90 :   SDLoc DL(N);
    7510          90 :   SDValue Op = N->getOperand(1);
    7511         135 :   if (N->getValueType(0) == MVT::i32)
    7512          78 :     return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain, Op);
    7513             :   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op,
    7514          18 :                            DAG.getConstant(0, DL, MVT::i32));
    7515             :   SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op,
    7516          18 :                            DAG.getConstant(1, DL, MVT::i32));
    7517             :   return DAG.getNode(ARMISD::WIN__DBZCHK, DL, MVT::Other, InChain,
    7518          24 :                      DAG.getNode(ISD::OR, DL, MVT::i32, Lo, Hi));
    7519             : }
    7520             : 
    7521           4 : void ARMTargetLowering::ExpandDIV_Windows(
    7522             :     SDValue Op, SelectionDAG &DAG, bool Signed,
    7523             :     SmallVectorImpl<SDValue> &Results) const {
    7524           8 :   const auto &DL = DAG.getDataLayout();
    7525           4 :   const auto &TLI = DAG.getTargetLoweringInfo();
    7526             : 
    7527             :   assert(Op.getValueType() == MVT::i64 &&
    7528             :          "unexpected type for custom lowering DIV");
    7529           8 :   SDLoc dl(Op);
    7530             : 
    7531           4 :   SDValue DBZCHK = WinDBZCheckDenominator(DAG, Op.getNode(), DAG.getEntryNode());
    7532             : 
    7533           4 :   SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
    7534             : 
    7535           8 :   SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
    7536             :   SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
    7537          16 :                               DAG.getConstant(32, dl, TLI.getPointerTy(DL)));
    7538           8 :   Upper = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Upper);
    7539             : 
    7540           4 :   Results.push_back(Lower);
    7541           4 :   Results.push_back(Upper);
    7542           4 : }
    7543             : 
    7544             : static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
    7545          72 :   if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering()))
    7546             :     // Acquire/Release load/store is not legal for targets without a dmb or
    7547             :     // equivalent available.
    7548             :     return SDValue();
    7549             : 
    7550             :   // Monotonic load/store is legal for all targets.
    7551             :   return Op;
    7552             : }
    7553             : 
    7554           2 : static void ReplaceREADCYCLECOUNTER(SDNode *N,
    7555             :                                     SmallVectorImpl<SDValue> &Results,
    7556             :                                     SelectionDAG &DAG,
    7557             :                                     const ARMSubtarget *Subtarget) {
    7558           4 :   SDLoc DL(N);
    7559             :   // Under Power Management extensions, the cycle-count is:
    7560             :   //    mrc p15, #0, <Rt>, c9, c13, #0
    7561           4 :   SDValue Ops[] = { N->getOperand(0), // Chain
    7562           4 :                     DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
    7563           4 :                     DAG.getConstant(15, DL, MVT::i32),
    7564           4 :                     DAG.getConstant(0, DL, MVT::i32),
    7565           4 :                     DAG.getConstant(9, DL, MVT::i32),
    7566           4 :                     DAG.getConstant(13, DL, MVT::i32),
    7567           4 :                     DAG.getConstant(0, DL, MVT::i32)
    7568          26 :   };
    7569             : 
    7570             :   SDValue Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
    7571           6 :                                  DAG.getVTList(MVT::i32, MVT::Other), Ops);
    7572           4 :   Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32,
    7573           8 :                                 DAG.getConstant(0, DL, MVT::i32)));
    7574           4 :   Results.push_back(Cycles32.getValue(1));
    7575           2 : }
    7576             : 
    7577          14 : static SDValue createGPRPairNode(SelectionDAG &DAG, SDValue V) {
    7578          42 :   SDLoc dl(V.getNode());
    7579          14 :   SDValue VLo = DAG.getAnyExtOrTrunc(V, dl, MVT::i32);
    7580             :   SDValue VHi = DAG.getAnyExtOrTrunc(
    7581          28 :       DAG.getNode(ISD::SRL, dl, MVT::i64, V, DAG.getConstant(32, dl, MVT::i32)),
    7582          56 :       dl, MVT::i32);
    7583          28 :   bool isBigEndian = DAG.getDataLayout().isBigEndian();
    7584          14 :   if (isBigEndian)
    7585             :     std::swap (VLo, VHi);
    7586             :   SDValue RegClass =
    7587          28 :       DAG.getTargetConstant(ARM::GPRPairRegClassID, dl, MVT::i32);
    7588          28 :   SDValue SubReg0 = DAG.getTargetConstant(ARM::gsub_0, dl, MVT::i32);
    7589          28 :   SDValue SubReg1 = DAG.getTargetConstant(ARM::gsub_1, dl, MVT::i32);
    7590          14 :   const SDValue Ops[] = { RegClass, VLo, SubReg0, VHi, SubReg1 };
    7591          14 :   return SDValue(
    7592          56 :       DAG.getMachineNode(TargetOpcode::REG_SEQUENCE, dl, MVT::Untyped, Ops), 0);
    7593             : }
    7594             : 
    7595           7 : static void ReplaceCMP_SWAP_64Results(SDNode *N,
    7596             :                                        SmallVectorImpl<SDValue> & Results,
    7597             :                                        SelectionDAG &DAG) {
    7598             :   assert(N->getValueType(0) == MVT::i64 &&
    7599             :          "AtomicCmpSwap on types less than 64 should be legal");
    7600          14 :   SDValue Ops[] = {N->getOperand(1),
    7601          14 :                    createGPRPairNode(DAG, N->getOperand(2)),
    7602          14 :                    createGPRPairNode(DAG, N->getOperand(3)),
    7603          28 :                    N->getOperand(0)};
    7604          14 :   SDNode *CmpSwap = DAG.getMachineNode(
    7605          14 :       ARM::CMP_SWAP_64, SDLoc(N),
    7606          35 :       DAG.getVTList(MVT::Untyped, MVT::i32, MVT::Other), Ops);
    7607             : 
    7608           7 :   MachineFunction &MF = DAG.getMachineFunction();
    7609           7 :   MachineSDNode::mmo_iterator MemOp = MF.allocateMemRefsArray(1);
    7610           7 :   MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
    7611          14 :   cast<MachineSDNode>(CmpSwap)->setMemRefs(MemOp, MemOp + 1);
    7612             : 
    7613          14 :   bool isBigEndian = DAG.getDataLayout().isBigEndian();
    7614             : 
    7615          14 :   Results.push_back(
    7616          14 :       DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_1 : ARM::gsub_0,
    7617          28 :                                  SDLoc(N), MVT::i32, SDValue(CmpSwap, 0)));
    7618          14 :   Results.push_back(
    7619          14 :       DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_0 : ARM::gsub_1,
    7620          28 :                                  SDLoc(N), MVT::i32, SDValue(CmpSwap, 0)));
    7621          14 :   Results.push_back(SDValue(CmpSwap, 2));
    7622           7 : }
    7623             : 
    7624           4 : static SDValue LowerFPOWI(SDValue Op, const ARMSubtarget &Subtarget,
    7625             :                           SelectionDAG &DAG) {
    7626           4 :   const auto &TLI = DAG.getTargetLoweringInfo();
    7627             : 
    7628             :   assert(Subtarget.getTargetTriple().isOSMSVCRT() &&
    7629             :          "Custom lowering is MSVCRT specific!");
    7630             : 
    7631           8 :   SDLoc dl(Op);
    7632           8 :   SDValue Val = Op.getOperand(0);
    7633           8 :   MVT Ty = Val->getSimpleValueType(0);
    7634          12 :   SDValue Exponent = DAG.getNode(ISD::SINT_TO_FP, dl, Ty, Op.getOperand(1));
    7635           4 :   SDValue Callee = DAG.getExternalSymbol(Ty == MVT::f32 ? "powf" : "pow",
    7636          20 :                                          TLI.getPointerTy(DAG.getDataLayout()));
    7637             : 
    7638           8 :   TargetLowering::ArgListTy Args;
    7639           4 :   TargetLowering::ArgListEntry Entry;
    7640             : 
    7641           4 :   Entry.Node = Val;
    7642           8 :   Entry.Ty = Val.getValueType().getTypeForEVT(*DAG.getContext());
    7643           4 :   Entry.IsZExt = true;
    7644           4 :   Args.push_back(Entry);
    7645             : 
    7646           4 :   Entry.Node = Exponent;
    7647           8 :   Entry.Ty = Exponent.getValueType().getTypeForEVT(*DAG.getContext());
    7648           4 :   Entry.IsZExt = true;
    7649           4 :   Args.push_back(Entry);
    7650             : 
    7651           8 :   Type *LCRTy = Val.getValueType().getTypeForEVT(*DAG.getContext());
    7652             : 
    7653             :   // In the in-chain to the call is the entry node  If we are emitting a
    7654             :   // tailcall, the chain will be mutated if the node has a non-entry input
    7655             :   // chain.
    7656           4 :   SDValue InChain = DAG.getEntryNode();
    7657           4 :   SDValue TCChain = InChain;
    7658             : 
    7659           4 :   const auto *F = DAG.getMachineFunction().getFunction();
    7660           6 :   bool IsTC = TLI.isInTailCallPosition(DAG, Op.getNode(), TCChain) &&
    7661           4 :               F->getReturnType() == LCRTy;
    7662             :   if (IsTC)
    7663           2 :     InChain = TCChain;
    7664             : 
    7665           8 :   TargetLowering::CallLoweringInfo CLI(DAG);
    7666           4 :   CLI.setDebugLoc(dl)
    7667           4 :       .setChain(InChain)
    7668           8 :       .setCallee(CallingConv::ARM_AAPCS_VFP, LCRTy, Callee, std::move(Args))
    7669           8 :       .setTailCall(IsTC);
    7670           4 :   std::pair<SDValue, SDValue> CI = TLI.LowerCallTo(CLI);
    7671             : 
    7672             :   // Return the chain (the DAG root) if it is a tail call
    7673          10 :   return !CI.second.getNode() ? DAG.getRoot() : CI.first;
    7674             : }
    7675             : 
    7676       19197 : SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
    7677       38394 :   switch (Op.getOpcode()) {
    7678           0 :   default: llvm_unreachable("Don't know how to custom lower this!");
    7679           2 :   case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
    7680         862 :   case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
    7681          37 :   case ISD::BlockAddress:  return LowerBlockAddress(Op, DAG);
    7682        1948 :   case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
    7683         187 :   case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
    7684         142 :   case ISD::SELECT:        return LowerSELECT(Op, DAG);
    7685        1090 :   case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG);
    7686        1737 :   case ISD::BR_CC:         return LowerBR_CC(Op, DAG);
    7687          37 :   case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
    7688          30 :   case ISD::VASTART:       return LowerVASTART(Op, DAG);
    7689          21 :   case ISD::ATOMIC_FENCE:  return LowerATOMIC_FENCE(Op, DAG, Subtarget);
    7690          32 :   case ISD::PREFETCH:      return LowerPREFETCH(Op, DAG, Subtarget);
    7691         165 :   case ISD::SINT_TO_FP:
    7692         165 :   case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
    7693          93 :   case ISD::FP_TO_SINT:
    7694          93 :   case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
    7695          22 :   case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
    7696          12 :   case ISD::RETURNADDR:    return LowerRETURNADDR(Op, DAG);
    7697          38 :   case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
    7698           4 :   case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
    7699           5 :   case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
    7700          28 :   case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
    7701        2099 :   case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
    7702        2099 :                                                                Subtarget);
    7703          53 :   case ISD::BITCAST:       return ExpandBITCAST(Op.getNode(), DAG);
    7704          43 :   case ISD::SHL:
    7705             :   case ISD::SRL:
    7706          43 :   case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
    7707           0 :   case ISD::SREM:          return LowerREM(Op.getNode(), DAG);
    7708           0 :   case ISD::UREM:          return LowerREM(Op.getNode(), DAG);
    7709           4 :   case ISD::SHL_PARTS:     return LowerShiftLeftParts(Op, DAG);
    7710           8 :   case ISD::SRL_PARTS:
    7711           8 :   case ISD::SRA_PARTS:     return LowerShiftRightParts(Op, DAG);
    7712          48 :   case ISD::CTTZ:
    7713          48 :   case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
    7714           4 :   case ISD::CTPOP:         return LowerCTPOP(Op.getNode(), DAG, Subtarget);
    7715         126 :   case ISD::SETCC:         return LowerVSETCC(Op, DAG);
    7716          81 :   case ISD::SETCCE:        return LowerSETCCE(Op, DAG);
    7717         976 :   case ISD::ConstantFP:    return LowerConstantFP(Op, DAG, Subtarget);
    7718         966 :   case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG, Subtarget);
    7719         358 :   case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
    7720         948 :   case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
    7721        5545 :   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
    7722           0 :   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
    7723           3 :   case ISD::FLT_ROUNDS_:   return LowerFLT_ROUNDS_(Op, DAG);
    7724         177 :   case ISD::MUL:           return LowerMUL(Op, DAG);
    7725          24 :   case ISD::SDIV:
    7726          95 :     if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
    7727          19 :       return LowerDIV_Windows(Op, DAG, /* Signed */ true);
    7728           5 :     return LowerSDIV(Op, DAG);
    7729           8 :   case ISD::UDIV:
    7730          32 :     if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
    7731           4 :       return LowerDIV_Windows(Op, DAG, /* Signed */ false);
    7732           4 :     return LowerUDIV(Op, DAG);
    7733         996 :   case ISD::ADDC:
    7734             :   case ISD::ADDE:
    7735             :   case ISD::SUBC:
    7736         996 :   case ISD::SUBE:          return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
    7737           4 :   case ISD::SADDO:
    7738             :   case ISD::UADDO:
    7739             :   case ISD::SSUBO:
    7740             :   case ISD::USUBO:
    7741           4 :     return LowerXALUO(Op, DAG);
    7742          24 :   case ISD::ATOMIC_LOAD:
    7743          24 :   case ISD::ATOMIC_STORE:  return LowerAtomicLoadStore(Op, DAG);
    7744           5 :   case ISD::FSINCOS:       return LowerFSINCOS(Op, DAG);
    7745         185 :   case ISD::SDIVREM:
    7746         185 :   case ISD::UDIVREM:       return LowerDivRem(Op, DAG);
    7747           4 :   case ISD::DYNAMIC_STACKALLOC:
    7748           8 :     if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
    7749           4 :       return LowerDYNAMIC_STACKALLOC(Op, DAG);
    7750           0 :     llvm_unreachable("Don't know how to custom lower this!");
    7751           5 :   case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
    7752           7 :   case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
    7753           4 :   case ISD::FPOWI: return LowerFPOWI(Op, *Subtarget, DAG);
    7754           0 :   case ARMISD::WIN__DBZCHK: return SDValue();
    7755             :   }
    7756             : }
    7757             : 
    7758          24 : static void ReplaceLongIntrinsic(SDNode *N, SmallVectorImpl<SDValue> &Results,
    7759             :                                  SelectionDAG &DAG) {
    7760          96 :   unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
    7761          24 :   unsigned Opc = 0;
    7762          24 :   if (IntNo == Intrinsic::arm_smlald)
    7763             :     Opc = ARMISD::SMLALD;
    7764          18 :   else if (IntNo == Intrinsic::arm_smlaldx)
    7765             :     Opc = ARMISD::SMLALDX;
    7766          12 :   else if (IntNo == Intrinsic::arm_smlsld)
    7767             :     Opc = ARMISD::SMLSLD;
    7768           6 :   else if (IntNo == Intrinsic::arm_smlsldx)
    7769             :     Opc = ARMISD::SMLSLDX;
    7770             :   else
    7771           0 :     return;
    7772             : 
    7773          48 :   SDLoc dl(N);
    7774             :   SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
    7775          48 :                            N->getOperand(3),
    7776          72 :                            DAG.getConstant(0, dl, MVT::i32));
    7777             :   SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
    7778          48 :                            N->getOperand(3),
    7779          72 :                            DAG.getConstant(1, dl, MVT::i32));
    7780             : 
    7781             :   SDValue LongMul = DAG.getNode(Opc, dl,
    7782          48 :                                 DAG.getVTList(MVT::i32, MVT::i32),
    7783          72 :                                 N->getOperand(1), N->getOperand(2),
    7784          24 :                                 Lo, Hi);
    7785          48 :   Results.push_back(LongMul.getValue(0));
    7786          48 :   Results.push_back(LongMul.getValue(1));
    7787             : }
    7788             : 
    7789             : /// ReplaceNodeResults - Replace the results of node with an illegal result
    7790             : /// type with new values built out of custom code.
    7791         779 : void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
    7792             :                                            SmallVectorImpl<SDValue> &Results,
    7793             :                                            SelectionDAG &DAG) const {
    7794         779 :   SDValue Res;
    7795        1558 :   switch (N->getOpcode()) {
    7796           0 :   default:
    7797           0 :     llvm_unreachable("Don't know how to custom expand this!");
    7798           2 :   case ISD::READ_REGISTER:
    7799           2 :     ExpandREAD_REGISTER(N, Results, DAG);
    7800           2 :     break;
    7801          27 :   case ISD::BITCAST:
    7802          27 :     Res = ExpandBITCAST(N, DAG);
    7803          27 :     break;
    7804         695 :   case ISD::SRL:
    7805             :   case ISD::SRA:
    7806         695 :     Res = Expand64BitShift(N, DAG, Subtarget);
    7807         695 :     break;
    7808           4 :   case ISD::SREM:
    7809             :   case ISD::UREM:
    7810           4 :     Res = LowerREM(N, DAG);
    7811           4 :     break;
    7812          14 :   case ISD::SDIVREM:
    7813             :   case ISD::UDIVREM:
    7814          14 :     Res = LowerDivRem(SDValue(N, 0), DAG);
    7815             :     assert(Res.getNumOperands() == 2 && "DivRem needs two values");
    7816          28 :     Results.push_back(Res.getValue(0));
    7817          28 :     Results.push_back(Res.getValue(1));
    7818          65 :     return;
    7819           2 :   case ISD::READCYCLECOUNTER:
    7820           2 :     ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
    7821           2 :     return;
    7822           4 :   case ISD::UDIV:
    7823             :   case ISD::SDIV:
    7824             :     assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows");
    7825           8 :     return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
    7826           4 :                              Results);
    7827           7 :   case ISD::ATOMIC_CMP_SWAP:
    7828           7 :     ReplaceCMP_SWAP_64Results(N, Results, DAG);
    7829           7 :     return;
    7830          24 :   case ISD::INTRINSIC_WO_CHAIN:
    7831          24 :     return ReplaceLongIntrinsic(N, Results, DAG);
    7832             :   }
    7833         728 :   if (Res.getNode())
    7834          38 :     Results.push_back(Res);
    7835             : }
    7836             : 
    7837             : //===----------------------------------------------------------------------===//
    7838             : //                           ARM Scheduler Hooks
    7839             : //===----------------------------------------------------------------------===//
    7840             : 
    7841             : /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
    7842             : /// registers the function context.
    7843          28 : void ARMTargetLowering::SetupEntryBlockForSjLj(MachineInstr &MI,
    7844             :                                                MachineBasicBlock *MBB,
    7845             :                                                MachineBasicBlock *DispatchBB,
    7846             :                                                int FI) const {
    7847             :   assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&
    7848             :          "ROPI/RWPI not currently supported with SjLj");
    7849          28 :   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    7850          84 :   DebugLoc dl = MI.getDebugLoc();
    7851          28 :   MachineFunction *MF = MBB->getParent();
    7852          28 :   MachineRegisterInfo *MRI = &MF->getRegInfo();
    7853          28 :   MachineConstantPool *MCP = MF->getConstantPool();
    7854          28 :   ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
    7855          28 :   const Function *F = MF->getFunction();
    7856             : 
    7857          28 :   bool isThumb = Subtarget->isThumb();
    7858          56 :   bool isThumb2 = Subtarget->isThumb2();
    7859             : 
    7860          56 :   unsigned PCLabelId = AFI->createPICLabelUId();
    7861          28 :   unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
    7862             :   ARMConstantPoolValue *CPV =
    7863          28 :     ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
    7864          28 :   unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
    7865             : 
    7866          28 :   const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
    7867             :                                            : &ARM::GPRRegClass;
    7868             : 
    7869             :   // Grab constant pool and fixed stack memory operands.
    7870             :   MachineMemOperand *CPMMO =
    7871          56 :       MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
    7872          28 :                                MachineMemOperand::MOLoad, 4, 4);
    7873             : 
    7874             :   MachineMemOperand *FIMMOSt =
    7875          56 :       MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
    7876          28 :                                MachineMemOperand::MOStore, 4, 4);
    7877             : 
    7878             :   // Load the address of the dispatch MBB into the jump buffer.
    7879          28 :   if (isThumb2) {
    7880             :     // Incoming value: jbuf
    7881             :     //   ldr.n  r5, LCPI1_1
    7882             :     //   orr    r5, r5, #1
    7883             :     //   add    r5, pc
    7884             :     //   str    r5, [$jbuf, #+4] ; &jbuf[1]
    7885           9 :     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
    7886          18 :     BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
    7887           9 :         .addConstantPoolIndex(CPI)
    7888           9 :         .addMemOperand(CPMMO)
    7889          27 :         .add(predOps(ARMCC::AL));
    7890             :     // Set the low bit because of thumb mode.
    7891           9 :     unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
    7892          27 :     BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
    7893           9 :         .addReg(NewVReg1, RegState::Kill)
    7894           9 :         .addImm(0x01)
    7895          36 :         .add(predOps(ARMCC::AL))
    7896          18 :         .add(condCodeOp());
    7897           9 :     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
    7898          27 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
    7899           9 :       .addReg(NewVReg2, RegState::Kill)
    7900          18 :       .addImm(PCLabelId);
    7901          27 :     BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
    7902           9 :         .addReg(NewVReg3, RegState::Kill)
    7903           9 :         .addFrameIndex(FI)
    7904           9 :         .addImm(36) // &jbuf[1] :: pc
    7905           9 :         .addMemOperand(FIMMOSt)
    7906          27 :         .add(predOps(ARMCC::AL));
    7907          19 :   } else if (isThumb) {
    7908             :     // Incoming value: jbuf
    7909             :     //   ldr.n  r1, LCPI1_4
    7910             :     //   add    r1, pc
    7911             :     //   mov    r2, #1
    7912             :     //   orrs   r1, r2
    7913             :     //   add    r2, $jbuf, #+4 ; &jbuf[1]
    7914             :     //   str    r1, [r2]
    7915           4 :     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
    7916           8 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
    7917           4 :         .addConstantPoolIndex(CPI)
    7918           4 :         .addMemOperand(CPMMO)
    7919          12 :         .add(predOps(ARMCC::AL));
    7920           4 :     unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
    7921          12 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
    7922           4 :       .addReg(NewVReg1, RegState::Kill)
    7923           8 :       .addImm(PCLabelId);
    7924             :     // Set the low bit because of thumb mode.
    7925           4 :     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
    7926          12 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
    7927           4 :         .addReg(ARM::CPSR, RegState::Define)
    7928           4 :         .addImm(1)
    7929          12 :         .add(predOps(ARMCC::AL));
    7930           4 :     unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
    7931          12 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
    7932           4 :         .addReg(ARM::CPSR, RegState::Define)
    7933           4 :         .addReg(NewVReg2, RegState::Kill)
    7934           4 :         .addReg(NewVReg3, RegState::Kill)
    7935          12 :         .add(predOps(ARMCC::AL));
    7936           4 :     unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
    7937           8 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
    7938           4 :             .addFrameIndex(FI)
    7939           4 :             .addImm(36); // &jbuf[1] :: pc
    7940          12 :     BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
    7941           4 :         .addReg(NewVReg4, RegState::Kill)
    7942           4 :         .addReg(NewVReg5, RegState::Kill)
    7943           4 :         .addImm(0)
    7944           4 :         .addMemOperand(FIMMOSt)
    7945          12 :         .add(predOps(ARMCC::AL));
    7946             :   } else {
    7947             :     // Incoming value: jbuf
    7948             :     //   ldr  r1, LCPI1_1
    7949             :     //   add  r1, pc, r1
    7950             :     //   str  r1, [$jbuf, #+4] ; &jbuf[1]
    7951          15 :     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
    7952          30 :     BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
    7953          15 :         .addConstantPoolIndex(CPI)
    7954          15 :         .addImm(0)
    7955          15 :         .addMemOperand(CPMMO)
    7956          45 :         .add(predOps(ARMCC::AL));
    7957          15 :     unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
    7958          45 :     BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
    7959          15 :         .addReg(NewVReg1, RegState::Kill)
    7960          30 :         .addImm(PCLabelId)
    7961          45 :         .add(predOps(ARMCC::AL));
    7962          45 :     BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
    7963          15 :         .addReg(NewVReg2, RegState::Kill)
    7964          15 :         .addFrameIndex(FI)
    7965          15 :         .addImm(36) // &jbuf[1] :: pc
    7966          15 :         .addMemOperand(FIMMOSt)
    7967          45 :         .add(predOps(ARMCC::AL));
    7968             :   }
    7969          28 : }
    7970             : 
    7971          28 : void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
    7972             :                                               MachineBasicBlock *MBB) const {
    7973          28 :   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    7974          84 :   DebugLoc dl = MI.getDebugLoc();
    7975          28 :   MachineFunction *MF = MBB->getParent();
    7976          28 :   MachineRegisterInfo *MRI = &MF->getRegInfo();
    7977          28 :   MachineFrameInfo &MFI = MF->getFrameInfo();
    7978          28 :   int FI = MFI.getFunctionContextIndex();
    7979             : 
    7980          28 :   const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
    7981          28 :                                                         : &ARM::GPRnopcRegClass;
    7982             : 
    7983             :   // Get a mapping of the call site numbers to all of the landing pads they're
    7984             :   // associated with.
    7985          56 :   DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2>> CallSiteNumToLPad;
    7986          28 :   unsigned MaxCSNum = 0;
    7987          56 :   for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
    7988             :        ++BB) {
    7989         327 :     if (!BB->isEHPad()) continue;
    7990             : 
    7991             :     // FIXME: We should assert that the EH_LABEL is the first MI in the landing
    7992             :     // pad.
    7993             :     for (MachineBasicBlock::iterator
    7994         600 :            II = BB->begin(), IE = BB->end(); II != IE; ++II) {
    7995         240 :       if (!II->isEHLabel()) continue;
    7996             : 
    7997         120 :       MCSymbol *Sym = II->getOperand(0).getMCSymbol();
    7998         120 :       if (!MF->hasCallSiteLandingPad(Sym)) continue;
    7999             : 
    8000         120 :       SmallVectorImpl<unsigned> &CallSiteIdxs = MF->getCallSiteLandingPad(Sym);
    8001         164 :       for (SmallVectorImpl<unsigned>::iterator
    8002         360 :              CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
    8003         284 :            CSI != CSE; ++CSI) {
    8004         328 :         CallSiteNumToLPad[*CSI].push_back(&*BB);
    8005         164 :         MaxCSNum = std::max(MaxCSNum, *CSI);
    8006             :       }
    8007             :       break;
    8008             :     }
    8009             :   }
    8010             : 
    8011             :   // Get an ordered list of the machine basic blocks for the jump table.
    8012          56 :   std::vector<MachineBasicBlock*> LPadList;
    8013          56 :   SmallPtrSet<MachineBasicBlock*, 32> InvokeBBs;
    8014          28 :   LPadList.reserve(CallSiteNumToLPad.size());
    8015         192 :   for (unsigned I = 1; I <= MaxCSNum; ++I) {
    8016         164 :     SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
    8017         164 :     for (SmallVectorImpl<MachineBasicBlock*>::iterator
    8018         492 :            II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
    8019         164 :       LPadList.push_back(*II);
    8020         656 :       InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
    8021             :     }
    8022             :   }
    8023             : 
    8024             :   assert(!LPadList.empty() &&
    8025             :          "No landing pad destinations for the dispatch jump table!");
    8026             : 
    8027             :   // Create the jump table and associated information.
    8028             :   MachineJumpTableInfo *JTI =
    8029          28 :     MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
    8030          28 :   unsigned MJTI = JTI->createJumpTableIndex(LPadList);
    8031             : 
    8032             :   // Create the MBBs for the dispatch code.
    8033             : 
    8034             :   // Shove the dispatch's address into the return slot in the function context.
    8035          28 :   MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
    8036          28 :   DispatchBB->setIsEHPad();
    8037             : 
    8038          28 :   MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
    8039             :   unsigned trap_opcode;
    8040          28 :   if (Subtarget->isThumb())
    8041             :     trap_opcode = ARM::tTRAP;
    8042             :   else
    8043          15 :     trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
    8044             : 
    8045          84 :   BuildMI(TrapBB, dl, TII->get(trap_opcode));
    8046          28 :   DispatchBB->addSuccessor(TrapBB);
    8047             : 
    8048          28 :   MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
    8049          28 :   DispatchBB->addSuccessor(DispContBB);
    8050             : 
    8051             :   // Insert and MBBs.
    8052          56 :   MF->insert(MF->end(), DispatchBB);
    8053          56 :   MF->insert(MF->end(), DispContBB);
    8054          56 :   MF->insert(MF->end(), TrapBB);
    8055             : 
    8056             :   // Insert code into the entry block that creates and registers the function
    8057             :   // context.
    8058          28 :   SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
    8059             : 
    8060          84 :   MachineMemOperand *FIMMOLd = MF->getMachineMemOperand(
    8061             :       MachinePointerInfo::getFixedStack(*MF, FI),
    8062          56 :       MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 4, 4);
    8063             : 
    8064          28 :   MachineInstrBuilder MIB;
    8065          84 :   MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
    8066             : 
    8067          28 :   const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
    8068          28 :   const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
    8069             : 
    8070             :   // Add a register mask with no preserved registers.  This results in all
    8071             :   // registers being marked as clobbered. This can't work if the dispatch block
    8072             :   // is in a Thumb1 function and is linked with ARM code which uses the FP
    8073             :   // registers, as there is no way to preserve the FP registers in Thumb1 mode.
    8074          56 :   MIB.addRegMask(RI.getSjLjDispatchPreservedMask(*MF));
    8075             : 
    8076          28 :   bool IsPositionIndependent = isPositionIndependent();
    8077          56 :   unsigned NumLPads = LPadList.size();
    8078          28 :   if (Subtarget->isThumb2()) {
    8079           9 :     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
    8080          27 :     BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
    8081           9 :         .addFrameIndex(FI)
    8082           9 :         .addImm(4)
    8083           9 :         .addMemOperand(FIMMOLd)
    8084          27 :         .add(predOps(ARMCC::AL));
    8085             : 
    8086           9 :     if (NumLPads < 256) {
    8087          36 :       BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
    8088           9 :           .addReg(NewVReg1)
    8089          27 :           .addImm(LPadList.size())
    8090          27 :           .add(predOps(ARMCC::AL));
    8091             :     } else {
    8092           0 :       unsigned VReg1 = MRI->createVirtualRegister(TRC);
    8093           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
    8094           0 :           .addImm(NumLPads & 0xFFFF)
    8095           0 :           .add(predOps(ARMCC::AL));
    8096             : 
    8097           0 :       unsigned VReg2 = VReg1;
    8098           0 :       if ((NumLPads & 0xFFFF0000) != 0) {
    8099           0 :         VReg2 = MRI->createVirtualRegister(TRC);
    8100           0 :         BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
    8101           0 :             .addReg(VReg1)
    8102           0 :             .addImm(NumLPads >> 16)
    8103           0 :             .add(predOps(ARMCC::AL));
    8104             :       }
    8105             : 
    8106           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
    8107           0 :           .addReg(NewVReg1)
    8108           0 :           .addReg(VReg2)
    8109           0 :           .add(predOps(ARMCC::AL));
    8110             :     }
    8111             : 
    8112          36 :     BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
    8113           9 :       .addMBB(TrapBB)
    8114           9 :       .addImm(ARMCC::HI)
    8115           9 :       .addReg(ARM::CPSR);
    8116             : 
    8117           9 :     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
    8118          27 :     BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg3)
    8119           9 :         .addJumpTableIndex(MJTI)
    8120          27 :         .add(predOps(ARMCC::AL));
    8121             : 
    8122           9 :     unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
    8123          36 :     BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
    8124           9 :         .addReg(NewVReg3, RegState::Kill)
    8125           9 :         .addReg(NewVReg1)
    8126          18 :         .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
    8127          36 :         .add(predOps(ARMCC::AL))
    8128          18 :         .add(condCodeOp());
    8129             : 
    8130          36 :     BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
    8131           9 :       .addReg(NewVReg4, RegState::Kill)
    8132           9 :       .addReg(NewVReg1)
    8133           9 :       .addJumpTableIndex(MJTI);
    8134          19 :   } else if (Subtarget->isThumb()) {
    8135           4 :     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
    8136          12 :     BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
    8137           4 :         .addFrameIndex(FI)
    8138           4 :         .addImm(1)
    8139           4 :         .addMemOperand(FIMMOLd)
    8140          12 :         .add(predOps(ARMCC::AL));
    8141             : 
    8142           4 :     if (NumLPads < 256) {
    8143          16 :       BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
    8144           4 :           .addReg(NewVReg1)
    8145           8 :           .addImm(NumLPads)
    8146          12 :           .add(predOps(ARMCC::AL));
    8147             :     } else {
    8148           0 :       MachineConstantPool *ConstantPool = MF->getConstantPool();
    8149           0 :       Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
    8150           0 :       const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
    8151             : 
    8152             :       // MachineConstantPool wants an explicit alignment.
    8153           0 :       unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
    8154           0 :       if (Align == 0)
    8155           0 :         Align = MF->getDataLayout().getTypeAllocSize(C->getType());
    8156           0 :       unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
    8157             : 
    8158           0 :       unsigned VReg1 = MRI->createVirtualRegister(TRC);
    8159           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
    8160           0 :           .addReg(VReg1, RegState::Define)
    8161           0 :           .addConstantPoolIndex(Idx)
    8162           0 :           .add(predOps(ARMCC::AL));
    8163           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
    8164           0 :           .addReg(NewVReg1)
    8165           0 :           .addReg(VReg1)
    8166           0 :           .add(predOps(ARMCC::AL));
    8167             :     }
    8168             : 
    8169          16 :     BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
    8170           4 :       .addMBB(TrapBB)
    8171           4 :       .addImm(ARMCC::HI)
    8172           4 :       .addReg(ARM::CPSR);
    8173             : 
    8174           4 :     unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
    8175          16 :     BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
    8176           4 :         .addReg(ARM::CPSR, RegState::Define)
    8177           4 :         .addReg(NewVReg1)
    8178           4 :         .addImm(2)
    8179          12 :         .add(predOps(ARMCC::AL));
    8180             : 
    8181           4 :     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
    8182          12 :     BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
    8183           4 :         .addJumpTableIndex(MJTI)
    8184          12 :         .add(predOps(ARMCC::AL));
    8185             : 
    8186           4 :     unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
    8187          16 :     BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
    8188           4 :         .addReg(ARM::CPSR, RegState::Define)
    8189           4 :         .addReg(NewVReg2, RegState::Kill)
    8190           4 :         .addReg(NewVReg3)
    8191          12 :         .add(predOps(ARMCC::AL));
    8192             : 
    8193           8 :     MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
    8194           4 :         MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
    8195             : 
    8196           4 :     unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
    8197          16 :     BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
    8198           4 :         .addReg(NewVReg4, RegState::Kill)
    8199           4 :         .addImm(0)
    8200           4 :         .addMemOperand(JTMMOLd)
    8201          12 :         .add(predOps(ARMCC::AL));
    8202             : 
    8203           4 :     unsigned NewVReg6 = NewVReg5;
    8204           4 :     if (IsPositionIndependent) {
    8205           2 :       NewVReg6 = MRI->createVirtualRegister(TRC);
    8206           8 :       BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
    8207           2 :           .addReg(ARM::CPSR, RegState::Define)
    8208           2 :           .addReg(NewVReg5, RegState::Kill)
    8209           2 :           .addReg(NewVReg3)
    8210           6 :           .add(predOps(ARMCC::AL));
    8211             :     }
    8212             : 
    8213          16 :     BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
    8214           4 :       .addReg(NewVReg6, RegState::Kill)
    8215           4 :       .addJumpTableIndex(MJTI);
    8216             :   } else {
    8217          15 :     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
    8218          45 :     BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
    8219          15 :         .addFrameIndex(FI)
    8220          15 :         .addImm(4)
    8221          15 :         .addMemOperand(FIMMOLd)
    8222          45 :         .add(predOps(ARMCC::AL));
    8223             : 
    8224          15 :     if (NumLPads < 256) {
    8225          60 :       BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
    8226          15 :           .addReg(NewVReg1)
    8227          30 :           .addImm(NumLPads)
    8228          45 :           .add(predOps(ARMCC::AL));
    8229           0 :     } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
    8230           0 :       unsigned VReg1 = MRI->createVirtualRegister(TRC);
    8231           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
    8232           0 :           .addImm(NumLPads & 0xFFFF)
    8233           0 :           .add(predOps(ARMCC::AL));
    8234             : 
    8235           0 :       unsigned VReg2 = VReg1;
    8236           0 :       if ((NumLPads & 0xFFFF0000) != 0) {
    8237           0 :         VReg2 = MRI->createVirtualRegister(TRC);
    8238           0 :         BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
    8239           0 :             .addReg(VReg1)
    8240           0 :             .addImm(NumLPads >> 16)
    8241           0 :             .add(predOps(ARMCC::AL));
    8242             :       }
    8243             : 
    8244           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
    8245           0 :           .addReg(NewVReg1)
    8246           0 :           .addReg(VReg2)
    8247           0 :           .add(predOps(ARMCC::AL));
    8248             :     } else {
    8249           0 :       MachineConstantPool *ConstantPool = MF->getConstantPool();
    8250           0 :       Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
    8251           0 :       const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
    8252             : 
    8253             :       // MachineConstantPool wants an explicit alignment.
    8254           0 :       unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
    8255           0 :       if (Align == 0)
    8256           0 :         Align = MF->getDataLayout().getTypeAllocSize(C->getType());
    8257           0 :       unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
    8258             : 
    8259           0 :       unsigned VReg1 = MRI->createVirtualRegister(TRC);
    8260           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
    8261           0 :           .addReg(VReg1, RegState::Define)
    8262           0 :           .addConstantPoolIndex(Idx)
    8263           0 :           .addImm(0)
    8264           0 :           .add(predOps(ARMCC::AL));
    8265           0 :       BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
    8266           0 :           .addReg(NewVReg1)
    8267           0 :           .addReg(VReg1, RegState::Kill)
    8268           0 :           .add(predOps(ARMCC::AL));
    8269             :     }
    8270             : 
    8271          60 :     BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
    8272          15 :       .addMBB(TrapBB)
    8273          15 :       .addImm(ARMCC::HI)
    8274          15 :       .addReg(ARM::CPSR);
    8275             : 
    8276          15 :     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
    8277          60 :     BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
    8278          15 :         .addReg(NewVReg1)
    8279          30 :         .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
    8280          60 :         .add(predOps(ARMCC::AL))
    8281          30 :         .add(condCodeOp());
    8282          15 :     unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
    8283          60 :     BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
    8284          15 :         .addJumpTableIndex(MJTI)
    8285          45 :         .add(predOps(ARMCC::AL));
    8286             : 
    8287          30 :     MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
    8288          15 :         MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
    8289          15 :     unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
    8290          60 :     BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
    8291          15 :         .addReg(NewVReg3, RegState::Kill)
    8292          15 :         .addReg(NewVReg4)
    8293          15 :         .addImm(0)
    8294          15 :         .addMemOperand(JTMMOLd)
    8295          45 :         .add(predOps(ARMCC::AL));
    8296             : 
    8297          15 :     if (IsPositionIndependent) {
    8298          52 :       BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
    8299          13 :         .addReg(NewVReg5, RegState::Kill)
    8300          13 :         .addReg(NewVReg4)
    8301          13 :         .addJumpTableIndex(MJTI);
    8302             :     } else {
    8303           8 :       BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
    8304           2 :         .addReg(NewVReg5, RegState::Kill)
    8305           2 :         .addJumpTableIndex(MJTI);
    8306             :     }
    8307             :   }
    8308             : 
    8309             :   // Add the jump table entries as successors to the MBB.
    8310          56 :   SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
    8311             :   for (std::vector<MachineBasicBlock*>::iterator
    8312         248 :          I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
    8313         164 :     MachineBasicBlock *CurMBB = *I;
    8314         164 :     if (SeenMBBs.insert(CurMBB).second)
    8315         120 :       DispContBB->addSuccessor(CurMBB);
    8316             :   }
    8317             : 
    8318             :   // N.B. the order the invoke BBs are processed in doesn't matter here.
    8319          28 :   const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
    8320          56 :   SmallVector<MachineBasicBlock*, 64> MBBLPads;
    8321         192 :   for (MachineBasicBlock *BB : InvokeBBs) {
    8322             : 
    8323             :     // Remove the landing pad successor from the invoke block and replace it
    8324             :     // with the new dispatch block.
    8325             :     SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
    8326         492 :                                                   BB->succ_end());
    8327         820 :     while (!Successors.empty()) {
    8328         328 :       MachineBasicBlock *SMBB = Successors.pop_back_val();
    8329         328 :       if (SMBB->isEHPad()) {
    8330         164 :         BB->removeSuccessor(SMBB);
    8331         164 :         MBBLPads.push_back(SMBB);
    8332             :       }
    8333             :     }
    8334             : 
    8335         164 :     BB->addSuccessor(DispatchBB, BranchProbability::getZero());
    8336         164 :     BB->normalizeSuccProbs();
    8337             : 
    8338             :     // Find the invoke call and mark all of the callee-saved registers as
    8339             :     // 'implicit defined' so that they're spilled. This prevents code from
    8340             :     // moving instructions to before the EH block, where they will never be
    8341             :     // executed.
    8342             :     for (MachineBasicBlock::reverse_iterator
    8343        1077 :            II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
    8344        1498 :       if (!II->isCall()) continue;
    8345             : 
    8346         328 :       DenseMap<unsigned, bool> DefRegs;
    8347        1451 :       for (MachineInstr::mop_iterator
    8348         492 :              OI = II->operands_begin(), OE = II->operands_end();
    8349        1615 :            OI != OE; ++OI) {
    8350        1451 :         if (!OI->isReg()) continue;
    8351        2078 :         DefRegs[OI->getReg()] = true;
    8352             :       }
    8353             : 
    8354         328 :       MachineInstrBuilder MIB(*MF, &*II);
    8355             : 
    8356        2788 :       for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
    8357        2624 :         unsigned Reg = SavedRegs[i];
    8358        4592 :         if (Subtarget->isThumb2() &&
    8359        3608 :             !ARM::tGPRRegClass.contains(Reg) &&
    8360        1968 :             !ARM::hGPRRegClass.contains(Reg))
    8361        1984 :           continue;
    8362        2144 :         if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
    8363          48 :           continue;
    8364        5040 :         if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
    8365         624 :           continue;
    8366        1296 :         if (!DefRegs[Reg])
    8367        1136 :           MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
    8368             :       }
    8369             : 
    8370             :       break;
    8371             :     }
    8372             :   }
    8373             : 
    8374             :   // Mark all former landing pads as non-landing pads. The dispatch is the only
    8375             :   // landing pad now.
    8376         164 :   for (SmallVectorImpl<MachineBasicBlock*>::iterator
    8377          56 :          I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
    8378         328 :     (*I)->setIsEHPad(false);
    8379             : 
    8380             :   // The instruction is gone now.
    8381          28 :   MI.eraseFromParent();
    8382          28 : }
    8383             : 
    8384             : static
    8385             : MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
    8386           1 :   for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
    8387           2 :        E = MBB->succ_end(); I != E; ++I)
    8388           1 :     if (*I != Succ)
    8389           1 :       return *I;
    8390           0 :   llvm_unreachable("Expecting a BB with two successors!");
    8391             : }
    8392             : 
    8393             : /// Return the load opcode for a given load size. If load size >= 8,
    8394             : /// neon opcode will be returned.
    8395        2526 : static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
    8396        2526 :   if (LdSize >= 8)
    8397          83 :     return LdSize == 16 ? ARM::VLD1q32wb_fixed
    8398             :                         : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
    8399        2443 :   if (IsThumb1)
    8400         915 :     return LdSize == 4 ? ARM::tLDRi
    8401             :                        : LdSize == 2 ? ARM::tLDRHi
    8402             :                                      : LdSize == 1 ? ARM::tLDRBi : 0;
    8403        1528 :   if (IsThumb2)
    8404         512 :     return LdSize == 4 ? ARM::t2LDR_POST
    8405             :                        : LdSize == 2 ? ARM::t2LDRH_POST
    8406             :                                      : LdSize == 1 ? ARM::t2LDRB_POST : 0;
    8407        1016 :   return LdSize == 4 ? ARM::LDR_POST_IMM
    8408             :                      : LdSize == 2 ? ARM::LDRH_POST
    8409             :                                    : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
    8410             : }
    8411             : 
    8412             : /// Return the store opcode for a given store size. If store size >= 8,
    8413             : /// neon opcode will be returned.
    8414        2526 : static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
    8415        2526 :   if (StSize >= 8)
    8416          83 :     return StSize == 16 ? ARM::VST1q32wb_fixed
    8417             :                         : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
    8418        2443 :   if (IsThumb1)
    8419         915 :     return StSize == 4 ? ARM::tSTRi
    8420             :                        : StSize == 2 ? ARM::tSTRHi
    8421             :                                      : StSize == 1 ? ARM::tSTRBi : 0;
    8422        1528 :   if (IsThumb2)
    8423         512 :     return StSize == 4 ? ARM::t2STR_POST
    8424             :                        : StSize == 2 ? ARM::t2STRH_POST
    8425             :                                      : StSize == 1 ? ARM::t2STRB_POST : 0;
    8426        1016 :   return StSize == 4 ? ARM::STR_POST_IMM
    8427             :                      : StSize == 2 ? ARM::STRH_POST
    8428             :                                    : StSize == 1 ? ARM::STRB_POST_IMM : 0;
    8429             : }
    8430             : 
    8431             : /// Emit a post-increment load operation with given size. The instructions
    8432             : /// will be added to BB at Pos.
    8433        2526 : static void emitPostLd(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos,
    8434             :                        const TargetInstrInfo *TII, const DebugLoc &dl,
    8435             :                        unsigned LdSize, unsigned Data, unsigned AddrIn,
    8436             :                        unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
    8437        2526 :   unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
    8438             :   assert(LdOpc != 0 && "Should have a load opcode");
    8439        2526 :   if (LdSize >= 8) {
    8440         249 :     BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
    8441          83 :         .addReg(AddrOut, RegState::Define)
    8442          83 :         .addReg(AddrIn)
    8443          83 :         .addImm(0)
    8444         249 :         .add(predOps(ARMCC::AL));
    8445        2443 :   } else if (IsThumb1) {
    8446             :     // load + update AddrIn
    8447        2745 :     BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
    8448         915 :         .addReg(AddrIn)
    8449         915 :         .addImm(0)
    8450        2745 :         .add(predOps(ARMCC::AL));
    8451        2745 :     BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
    8452        2745 :         .add(t1CondCodeOp())
    8453         915 :         .addReg(AddrIn)
    8454        1830 :         .addImm(LdSize)
    8455        2745 :         .add(predOps(ARMCC::AL));
    8456        1528 :   } else if (IsThumb2) {
    8457        1536 :     BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
    8458         512 :         .addReg(AddrOut, RegState::Define)
    8459         512 :         .addReg(AddrIn)
    8460        1024 :         .addImm(LdSize)
    8461        1536 :         .add(predOps(ARMCC::AL));
    8462             :   } else { // arm
    8463        3048 :     BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
    8464        1016 :         .addReg(AddrOut, RegState::Define)
    8465        1016 :         .addReg(AddrIn)
    8466        1016 :         .addReg(0)
    8467        2032 :         .addImm(LdSize)
    8468        3048 :         .add(predOps(ARMCC::AL));
    8469             :   }
    8470        2526 : }
    8471             : 
    8472             : /// Emit a post-increment store operation with given size. The instructions
    8473             : /// will be added to BB at Pos.
    8474        2526 : static void emitPostSt(MachineBasicBlock *BB, MachineBasicBlock::iterator Pos,
    8475             :                        const TargetInstrInfo *TII, const DebugLoc &dl,
    8476             :                        unsigned StSize, unsigned Data, unsigned AddrIn,
    8477             :                        unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
    8478        2526 :   unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
    8479             :   assert(StOpc != 0 && "Should have a store opcode");
    8480        2526 :   if (StSize >= 8) {
    8481         249 :     BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
    8482          83 :         .addReg(AddrIn)
    8483          83 :         .addImm(0)
    8484          83 :         .addReg(Data)
    8485         249 :         .add(predOps(ARMCC::AL));
    8486        2443 :   } else if (IsThumb1) {
    8487             :     // store + update AddrIn
    8488        2745 :     BuildMI(*BB, Pos, dl, TII->get(StOpc))
    8489         915 :         .addReg(Data)
    8490         915 :         .addReg(AddrIn)
    8491         915 :         .addImm(0)
    8492        2745 :         .add(predOps(ARMCC::AL));
    8493        2745 :     BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
    8494        2745 :         .add(t1CondCodeOp())
    8495         915 :         .addReg(AddrIn)
    8496        1830 :         .addImm(StSize)
    8497        2745 :         .add(predOps(ARMCC::AL));
    8498        1528 :   } else if (IsThumb2) {
    8499        1536 :     BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
    8500         512 :         .addReg(Data)
    8501         512 :         .addReg(AddrIn)
    8502        1024 :         .addImm(StSize)
    8503        1536 :         .add(predOps(ARMCC::AL));
    8504             :   } else { // arm
    8505        3048 :     BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
    8506        1016 :         .addReg(Data)
    8507        1016 :         .addReg(AddrIn)
    8508        1016 :         .addReg(0)
    8509        2032 :         .addImm(StSize)
    8510        3048 :         .add(predOps(ARMCC::AL));
    8511             :   }
    8512        2526 : }
    8513             : 
    8514             : MachineBasicBlock *
    8515         354 : ARMTargetLowering::EmitStructByval(MachineInstr &MI,
    8516             :                                    MachineBasicBlock *BB) const {
    8517             :   // This pseudo instruction has 3 operands: dst, src, size
    8518             :   // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
    8519             :   // Otherwise, we will generate unrolled scalar copies.
    8520         354 :   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    8521         354 :   const BasicBlock *LLVM_BB = BB->getBasicBlock();
    8522        1062 :   MachineFunction::iterator It = ++BB->getIterator();
    8523             : 
    8524         354 :   unsigned dest = MI.getOperand(0).getReg();
    8525         354 :   unsigned src = MI.getOperand(1).getReg();
    8526         354 :   unsigned SizeVal = MI.getOperand(2).getImm();
    8527         354 :   unsigned Align = MI.getOperand(3).getImm();
    8528        1062 :   DebugLoc dl = MI.getDebugLoc();
    8529             : 
    8530         354 :   MachineFunction *MF = BB->getParent();
    8531         354 :   MachineRegisterInfo &MRI = MF->getRegInfo();
    8532         354 :   unsigned UnitSize = 0;
    8533         354 :   const TargetRegisterClass *TRC = nullptr;
    8534         354 :   const TargetRegisterClass *VecTRC = nullptr;
    8535             : 
    8536         708 :   bool IsThumb1 = Subtarget->isThumb1Only();
    8537         708 :   bool IsThumb2 = Subtarget->isThumb2();
    8538         354 :   bool IsThumb = Subtarget->isThumb();
    8539             : 
    8540         354 :   if (Align & 1) {
    8541             :     UnitSize = 1;
    8542         281 :   } else if (Align & 2) {
    8543             :     UnitSize = 2;
    8544             :   } else {
    8545             :     // Check whether we can use NEON instructions.
    8546         657 :     if (!MF->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
    8547         219 :         Subtarget->hasNEON()) {
    8548         102 :       if ((Align % 16 == 0) && SizeVal >= 16)
    8549             :         UnitSize = 16;
    8550          71 :       else if ((Align % 8 == 0) && SizeVal >= 8)
    8551          26 :         UnitSize = 8;
    8552             :     }
    8553             :     // Can't use NEON instructions.
    8554             :     if (UnitSize == 0)
    8555             :       UnitSize = 4;
    8556             :   }
    8557             : 
    8558             :   // Select the correct opcode and register class for unit size load/store
    8559         354 :   bool IsNeon = UnitSize >= 8;
    8560         354 :   TRC = IsThumb ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
    8561         354 :   if (IsNeon)
    8562          57 :     VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
    8563          26 :                             : UnitSize == 8 ? &ARM::DPRRegClass
    8564             :                                             : nullptr;
    8565             : 
    8566         354 :   unsigned BytesLeft = SizeVal % UnitSize;
    8567         354 :   unsigned LoopSize = SizeVal - BytesLeft;
    8568             : 
    8569         354 :   if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
    8570             :     // Use LDR and STR to copy.
    8571             :     // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
    8572             :     // [destOut] = STR_POST(scratch, destIn, UnitSize)
    8573             :     unsigned srcIn = src;
    8574             :     unsigned destIn = dest;
    8575        4197 :     for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
    8576        2011 :       unsigned srcOut = MRI.createVirtualRegister(TRC);
    8577        2011 :       unsigned destOut = MRI.createVirtualRegister(TRC);
    8578        2011 :       unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
    8579        4022 :       emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
    8580             :                  IsThumb1, IsThumb2);
    8581        4022 :       emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
    8582             :                  IsThumb1, IsThumb2);
    8583        2011 :       srcIn = srcOut;
    8584        2011 :       destIn = destOut;
    8585             :     }
    8586             : 
    8587             :     // Handle the leftover bytes with LDRB and STRB.
    8588             :     // [scratch, srcOut] = LDRB_POST(srcIn, 1)
    8589             :     // [destOut] = STRB_POST(scratch, destIn, 1)
    8590         643 :     for (unsigned i = 0; i < BytesLeft; i++) {
    8591         234 :       unsigned srcOut = MRI.createVirtualRegister(TRC);
    8592         234 :       unsigned destOut = MRI.createVirtualRegister(TRC);
    8593         234 :       unsigned scratch = MRI.createVirtualRegister(TRC);
    8594         468 :       emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
    8595             :                  IsThumb1, IsThumb2);
    8596         468 :       emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
    8597             :                  IsThumb1, IsThumb2);
    8598         234 :       srcIn = srcOut;
    8599         234 :       destIn = destOut;
    8600             :     }
    8601         175 :     MI.eraseFromParent(); // The instruction is gone now.
    8602         175 :     return BB;
    8603             :   }
    8604             : 
    8605             :   // Expand the pseudo op to a loop.
    8606             :   // thisMBB:
    8607             :   //   ...
    8608             :   //   movw varEnd, # --> with thumb2
    8609             :   //   movt varEnd, #
    8610             :   //   ldrcp varEnd, idx --> without thumb2
    8611             :   //   fallthrough --> loopMBB
    8612             :   // loopMBB:
    8613             :   //   PHI varPhi, varEnd, varLoop
    8614             :   //   PHI srcPhi, src, srcLoop
    8615             :   //   PHI destPhi, dst, destLoop
    8616             :   //   [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
    8617             :   //   [destLoop] = STR_POST(scratch, destPhi, UnitSize)
    8618             :   //   subs varLoop, varPhi, #UnitSize
    8619             :   //   bne loopMBB
    8620             :   //   fallthrough --> exitMBB
    8621             :   // exitMBB:
    8622             :   //   epilogue to handle left-over bytes
    8623             :   //   [scratch, srcOut] = LDRB_POST(srcLoop, 1)
    8624             :   //   [destOut] = STRB_POST(scratch, destLoop, 1)
    8625         179 :   MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
    8626         179 :   MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
    8627         179 :   MF->insert(It, loopMBB);
    8628         179 :   MF->insert(It, exitMBB);
    8629             : 
    8630             :   // Transfer the remainder of BB and its successor edges to exitMBB.
    8631         895 :   exitMBB->splice(exitMBB->begin(), BB,
    8632             :                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
    8633         179 :   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
    8634             : 
    8635             :   // Load an immediate to varEnd.
    8636         179 :   unsigned varEnd = MRI.createVirtualRegister(TRC);
    8637         179 :   if (Subtarget->useMovt(*MF)) {
    8638         138 :     unsigned Vtmp = varEnd;
    8639         138 :     if ((LoopSize & 0xFFFF0000) != 0)
    8640           0 :       Vtmp = MRI.createVirtualRegister(TRC);
    8641         414 :     BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVi16 : ARM::MOVi16), Vtmp)
    8642         276 :         .addImm(LoopSize & 0xFFFF)
    8643         414 :         .add(predOps(ARMCC::AL));
    8644             : 
    8645         138 :     if ((LoopSize & 0xFFFF0000) != 0)
    8646           0 :       BuildMI(BB, dl, TII->get(IsThumb ? ARM::t2MOVTi16 : ARM::MOVTi16), varEnd)
    8647           0 :           .addReg(Vtmp)
    8648           0 :           .addImm(LoopSize >> 16)
    8649           0 :           .add(predOps(ARMCC::AL));
    8650             :   } else {
    8651          41 :     MachineConstantPool *ConstantPool = MF->getConstantPool();
    8652          41 :     Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
    8653          41 :     const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
    8654             : 
    8655             :     // MachineConstantPool wants an explicit alignment.
    8656          41 :     unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
    8657          41 :     if (Align == 0)
    8658           0 :       Align = MF->getDataLayout().getTypeAllocSize(C->getType());
    8659          41 :     unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
    8660             : 
    8661          41 :     if (IsThumb)
    8662         114 :       BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci))
    8663          38 :           .addReg(varEnd, RegState::Define)
    8664          38 :           .addConstantPoolIndex(Idx)
    8665         114 :           .add(predOps(ARMCC::AL));
    8666             :     else
    8667           9 :       BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp))
    8668           3 :           .addReg(varEnd, RegState::Define)
    8669           3 :           .addConstantPoolIndex(Idx)
    8670           3 :           .addImm(0)
    8671           9 :           .add(predOps(ARMCC::AL));
    8672             :   }
    8673         179 :   BB->addSuccessor(loopMBB);
    8674             : 
    8675             :   // Generate the loop body:
    8676             :   //   varPhi = PHI(varLoop, varEnd)
    8677             :   //   srcPhi = PHI(srcLoop, src)
    8678             :   //   destPhi = PHI(destLoop, dst)
    8679         179 :   MachineBasicBlock *entryBB = BB;
    8680         179 :   BB = loopMBB;
    8681         179 :   unsigned varLoop = MRI.createVirtualRegister(TRC);
    8682         179 :   unsigned varPhi = MRI.createVirtualRegister(TRC);
    8683         179 :   unsigned srcLoop = MRI.createVirtualRegister(TRC);
    8684         179 :   unsigned srcPhi = MRI.createVirtualRegister(TRC);
    8685         179 :   unsigned destLoop = MRI.createVirtualRegister(TRC);
    8686         179 :   unsigned destPhi = MRI.createVirtualRegister(TRC);
    8687             : 
    8688         537 :   BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
    8689         358 :     .addReg(varLoop).addMBB(loopMBB)
    8690         358 :     .addReg(varEnd).addMBB(entryBB);
    8691         537 :   BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
    8692         358 :     .addReg(srcLoop).addMBB(loopMBB)
    8693         358 :     .addReg(src).addMBB(entryBB);
    8694         537 :   BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
    8695         358 :     .addReg(destLoop).addMBB(loopMBB)
    8696         358 :     .addReg(dest).addMBB(entryBB);
    8697             : 
    8698             :   //   [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
    8699             :   //   [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
    8700         179 :   unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
    8701         358 :   emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
    8702             :              IsThumb1, IsThumb2);
    8703         358 :   emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
    8704             :              IsThumb1, IsThumb2);
    8705             : 
    8706             :   // Decrement loop variable by UnitSize.
    8707         179 :   if (IsThumb1) {
    8708         276 :     BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop)
    8709         207 :         .add(t1CondCodeOp())
    8710          69 :         .addReg(varPhi)
    8711         138 :         .addImm(UnitSize)
    8712         207 :         .add(predOps(ARMCC::AL));
    8713             :   } else {
    8714             :     MachineInstrBuilder MIB =
    8715             :         BuildMI(*BB, BB->end(), dl,
    8716         330 :                 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
    8717         110 :     MIB.addReg(varPhi)
    8718         220 :         .addImm(UnitSize)
    8719         440 :         .add(predOps(ARMCC::AL))
    8720         220 :         .add(condCodeOp());
    8721         220 :     MIB->getOperand(5).setReg(ARM::CPSR);
    8722         220 :     MIB->getOperand(5).setIsDef(true);
    8723             :   }
    8724         358 :   BuildMI(*BB, BB->end(), dl,
    8725         537 :           TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
    8726         358 :       .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
    8727             : 
    8728             :   // loopMBB can loop back to loopMBB or fall through to exitMBB.
    8729         179 :   BB->addSuccessor(loopMBB);
    8730         179 :   BB->addSuccessor(exitMBB);
    8731             : 
    8732             :   // Add epilogue to handle BytesLeft.
    8733         179 :   BB = exitMBB;
    8734         179 :   auto StartOfExit = exitMBB->begin();
    8735             : 
    8736             :   //   [scratch, srcOut] = LDRB_POST(srcLoop, 1)
    8737             :   //   [destOut] = STRB_POST(scratch, destLoop, 1)
    8738         179 :   unsigned srcIn = srcLoop;
    8739         179 :   unsigned destIn = destLoop;
    8740         281 :   for (unsigned i = 0; i < BytesLeft; i++) {
    8741         102 :     unsigned srcOut = MRI.createVirtualRegister(TRC);
    8742         102 :     unsigned destOut = MRI.createVirtualRegister(TRC);
    8743         102 :     unsigned scratch = MRI.createVirtualRegister(TRC);
    8744         102 :     emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
    8745             :                IsThumb1, IsThumb2);
    8746         102 :     emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
    8747             :                IsThumb1, IsThumb2);
    8748         102 :     srcIn = srcOut;
    8749         102 :     destIn = destOut;
    8750             :   }
    8751             : 
    8752         179 :   MI.eraseFromParent(); // The instruction is gone now.
    8753         179 :   return BB;
    8754             : }
    8755             : 
    8756             : MachineBasicBlock *
    8757           4 : ARMTargetLowering::EmitLowered__chkstk(MachineInstr &MI,
    8758             :                                        MachineBasicBlock *MBB) const {
    8759           4 :   const TargetMachine &TM = getTargetMachine();
    8760           4 :   const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
    8761          12 :   DebugLoc DL = MI.getDebugLoc();
    8762             : 
    8763             :   assert(Subtarget->isTargetWindows() &&
    8764             :          "__chkstk is only supported on Windows");
    8765             :   assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
    8766             : 
    8767             :   // __chkstk takes the number of words to allocate on the stack in R4, and
    8768             :   // returns the stack adjustment in number of bytes in R4.  This will not
    8769             :   // clober any other registers (other than the obvious lr).
    8770             :   //
    8771             :   // Although, technically, IP should be considered a register which may be
    8772             :   // clobbered, the call itself will not touch it.  Windows on ARM is a pure
    8773             :   // thumb-2 environment, so there is no interworking required.  As a result, we
    8774             :   // do not expect a veneer to be emitted by the linker, clobbering IP.
    8775             :   //
    8776             :   // Each module receives its own copy of __chkstk, so no import thunk is
    8777             :   // required, again, ensuring that IP is not clobbered.
    8778             :   //
    8779             :   // Finally, although some linkers may theoretically provide a trampoline for
    8780             :   // out of range calls (which is quite common due to a 32M range limitation of
    8781             :   // branches for Thumb), we can generate the long-call version via
    8782             :   // -mcmodel=large, alleviating the need for the trampoline which may clobber
    8783             :   // IP.
    8784             : 
    8785           4 :   switch (TM.getCodeModel()) {
    8786           3 :   case CodeModel::Small:
    8787             :   case CodeModel::Medium:
    8788             :   case CodeModel::Kernel:
    8789           9 :     BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
    8790          12 :         .add(predOps(ARMCC::AL))
    8791           3 :         .addExternalSymbol("__chkstk")
    8792           3 :         .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
    8793           3 :         .addReg(ARM::R4, RegState::Implicit | RegState::Define)
    8794             :         .addReg(ARM::R12,
    8795           3 :                 RegState::Implicit | RegState::Define | RegState::Dead)
    8796           3 :         .addReg(ARM::CPSR,
    8797             :                 RegState::Implicit | RegState::Define | RegState::Dead);
    8798           3 :     break;
    8799           1 :   case CodeModel::Large: {
    8800           1 :     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
    8801           1 :     unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
    8802             : 
    8803           3 :     BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
    8804           1 :       .addExternalSymbol("__chkstk");
    8805           3 :     BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
    8806           4 :         .add(predOps(ARMCC::AL))
    8807           1 :         .addReg(Reg, RegState::Kill)
    8808           1 :         .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
    8809           1 :         .addReg(ARM::R4, RegState::Implicit | RegState::Define)
    8810             :         .addReg(ARM::R12,
    8811           1 :                 RegState::Implicit | RegState::Define | RegState::Dead)
    8812           1 :         .addReg(ARM::CPSR,
    8813             :                 RegState::Implicit | RegState::Define | RegState::Dead);
    8814           1 :     break;
    8815             :   }
    8816             :   }
    8817             : 
    8818          12 :   BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
    8819           4 :       .addReg(ARM::SP, RegState::Kill)
    8820           4 :       .addReg(ARM::R4, RegState::Kill)
    8821           4 :       .setMIFlags(MachineInstr::FrameSetup)
    8822          16 :       .add(predOps(ARMCC::AL))
    8823           8 :       .add(condCodeOp());
    8824             : 
    8825           4 :   MI.eraseFromParent();
    8826           8 :   return MBB;
    8827             : }
    8828             : 
    8829             : MachineBasicBlock *
    8830          58 : ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
    8831             :                                        MachineBasicBlock *MBB) const {
    8832         174 :   DebugLoc DL = MI.getDebugLoc();
    8833          58 :   MachineFunction *MF = MBB->getParent();
    8834          58 :   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    8835             : 
    8836          58 :   MachineBasicBlock *ContBB = MF->CreateMachineBasicBlock();
    8837         232 :   MF->insert(++MBB->getIterator(), ContBB);
    8838         290 :   ContBB->splice(ContBB->begin(), MBB,
    8839             :                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
    8840          58 :   ContBB->transferSuccessorsAndUpdatePHIs(MBB);
    8841          58 :   MBB->addSuccessor(ContBB);
    8842             : 
    8843          58 :   MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
    8844         174 :   BuildMI(TrapBB, DL, TII->get(ARM::t__brkdiv0));
    8845          58 :   MF->push_back(TrapBB);
    8846          58 :   MBB->addSuccessor(TrapBB);
    8847             : 
    8848         174 :   BuildMI(*MBB, MI, DL, TII->get(ARM::tCMPi8))
    8849          58 :       .addReg(MI.getOperand(0).getReg())
    8850          58 :       .addImm(0)
    8851         174 :       .add(predOps(ARMCC::AL));
    8852         174 :   BuildMI(*MBB, MI, DL, TII->get(ARM::t2Bcc))
    8853          58 :       .addMBB(TrapBB)
    8854          58 :       .addImm(ARMCC::EQ)
    8855          58 :       .addReg(ARM::CPSR);
    8856             : 
    8857          58 :   MI.eraseFromParent();
    8858         116 :   return ContBB;
    8859             : }
    8860             : 
    8861             : MachineBasicBlock *
    8862         550 : ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
    8863             :                                                MachineBasicBlock *BB) const {
    8864         550 :   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
    8865        1650 :   DebugLoc dl = MI.getDebugLoc();
    8866        1100 :   bool isThumb2 = Subtarget->isThumb2();
    8867        1100 :   switch (MI.getOpcode()) {
    8868           0 :   default: {
    8869           0 :     MI.print(errs());
    8870           0 :     llvm_unreachable("Unexpected instr type to insert");
    8871             :   }
    8872             : 
    8873             :   // Thumb1 post-indexed loads are really just single-register LDMs.
    8874           2 :   case ARM::tLDR_postidx: {
    8875           4 :     BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
    8876           6 :         .add(MI.getOperand(1))  // Rn_wb
    8877           6 :         .add(MI.getOperand(2))  // Rn
    8878           6 :         .add(MI.getOperand(3))  // PredImm
    8879           6 :         .add(MI.getOperand(4))  // PredReg
    8880           4 :         .add(MI.getOperand(0)); // Rt
    8881           2 :     MI.eraseFromParent();
    8882           2 :     return BB;
    8883             :   }
    8884             : 
    8885             :   // The Thumb2 pre-indexed stores have the same MI operands, they just
    8886             :   // define them differently in the .td files from the isel patterns, so
    8887             :   // they need pseudos.
    8888           4 :   case ARM::t2STR_preidx:
    8889          12 :     MI.setDesc(TII->get(ARM::t2STR_PRE));
    8890           4 :     return BB;
    8891           0 :   case ARM::t2STRB_preidx:
    8892           0 :     MI.setDesc(TII->get(ARM::t2STRB_PRE));
    8893           0 :     return BB;
    8894           1 :   case ARM::t2STRH_preidx:
    8895           3 :     MI.setDesc(TII->get(ARM::t2STRH_PRE));
    8896           1 :     return BB;
    8897             : 
    8898          10 :   case ARM::STRi_preidx:
    8899             :   case ARM::STRBi_preidx: {
    8900          10 :     unsigned NewOpc = MI.getOpcode() == ARM::STRi_preidx ? ARM::STR_PRE_IMM
    8901          10 :                                                          : ARM::STRB_PRE_IMM;
    8902             :     // Decode the offset.
    8903          10 :     unsigned Offset = MI.getOperand(4).getImm();
    8904          10 :     bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
    8905          10 :     Offset = ARM_AM::getAM2Offset(Offset);
    8906             :     if (isSub)
    8907           0 :       Offset = -Offset;
    8908             : 
    8909          10 :     MachineMemOperand *MMO = *MI.memoperands_begin();
    8910          20 :     BuildMI(*BB, MI, dl, TII->get(NewOpc))
    8911          20 :         .add(MI.getOperand(0)) // Rn_wb
    8912          30 :         .add(MI.getOperand(1)) // Rt
    8913          30 :         .add(MI.getOperand(2)) // Rn
    8914          20 :         .addImm(Offset)        // offset (skip GPR==zero_reg)
    8915          30 :         .add(MI.getOperand(5)) // pred
    8916          30 :         .add(MI.getOperand(6))
    8917          10 :         .addMemOperand(MMO);
    8918          10 :     MI.eraseFromParent();
    8919          10 :     return BB;
    8920             :   }
    8921           3 :   case ARM::STRr_preidx:
    8922             :   case ARM::STRBr_preidx:
    8923             :   case ARM::STRH_preidx: {
    8924             :     unsigned NewOpc;
    8925           3 :     switch (MI.getOpcode()) {
    8926           0 :     default: llvm_unreachable("unexpected opcode!");
    8927             :     case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
    8928           0 :     case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
    8929           1 :     case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
    8930             :     }
    8931           6 :     MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
    8932          24 :     for (unsigned i = 0; i < MI.getNumOperands(); ++i)
    8933          63 :       MIB.add(MI.getOperand(i));
    8934           3 :     MI.eraseFromParent();
    8935             :     return BB;
    8936             :   }
    8937             : 
    8938          73 :   case ARM::tMOVCCr_pseudo: {
    8939             :     // To "insert" a SELECT_CC instruction, we actually have to insert the
    8940             :     // diamond control-flow pattern.  The incoming instruction knows the
    8941             :     // destination vreg to set, the condition code register to branch on, the
    8942             :     // true/false values to select between, and a branch opcode to use.
    8943          73 :     const BasicBlock *LLVM_BB = BB->getBasicBlock();
    8944         219 :     MachineFunction::iterator It = ++BB->getIterator();
    8945             : 
    8946             :     //  thisMBB:
    8947             :     //  ...
    8948             :     //   TrueVal = ...
    8949             :     //   cmpTY ccX, r1, r2
    8950             :     //   bCC copy1MBB
    8951             :     //   fallthrough --> copy0MBB
    8952          73 :     MachineBasicBlock *thisMBB  = BB;
    8953          73 :     MachineFunction *F = BB->getParent();
    8954          73 :     MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
    8955          73 :     MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
    8956          73 :     F->insert(It, copy0MBB);
    8957          73 :     F->insert(It, sinkMBB);
    8958             : 
    8959             :     // Transfer the remainder of BB and its successor edges to sinkMBB.
    8960         365 :     sinkMBB->splice(sinkMBB->begin(), BB,
    8961             :                     std::next(MachineBasicBlock::iterator(MI)), BB->end());
    8962          73 :     sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
    8963             : 
    8964          73 :     BB->addSuccessor(copy0MBB);
    8965          73 :     BB->addSuccessor(sinkMBB);
    8966             : 
    8967         292 :     BuildMI(BB, dl, TII->get(ARM::tBcc))
    8968          73 :         .addMBB(sinkMBB)
    8969         146 :         .addImm(MI.getOperand(3).getImm())
    8970          73 :         .addReg(MI.getOperand(4).getReg());
    8971             : 
    8972             :     //  copy0MBB:
    8973             :     //   %FalseValue = ...
    8974             :     //   # fallthrough to sinkMBB
    8975          73 :     BB = copy0MBB;
    8976             : 
    8977             :     // Update machine-CFG edges
    8978          73 :     BB->addSuccessor(sinkMBB);
    8979             : 
    8980             :     //  sinkMBB:
    8981             :     //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
    8982             :     //  ...
    8983          73 :     BB = sinkMBB;
    8984         219 :     BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg())
    8985          73 :         .addReg(MI.getOperand(1).getReg())
    8986          73 :         .addMBB(copy0MBB)
    8987          73 :         .addReg(MI.getOperand(2).getReg())
    8988          73 :         .addMBB(thisMBB);
    8989             : 
    8990          73 :     MI.eraseFromParent(); // The pseudo instruction is gone now.
    8991             :     return BB;
    8992             :   }
    8993             : 
    8994           1 :   case ARM::BCCi64:
    8995             :   case ARM::BCCZi64: {
    8996             :     // If there is an unconditional branch to the other successor, remove it.
    8997           4 :     BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
    8998             : 
    8999             :     // Compare both parts that make up the double comparison separately for
    9000             :     // equality.
    9001           2 :     bool RHSisZero = MI.getOpcode() == ARM::BCCZi64;
    9002             : 
    9003           1 :     unsigned LHS1 = MI.getOperand(1).getReg();
    9004           1 :     unsigned LHS2 = MI.getOperand(2).getReg();
    9005           1 :     if (RHSisZero) {
    9006           4 :       BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
    9007           1 :           .addReg(LHS1)
    9008           1 :           .addImm(0)
    9009           3 :           .add(predOps(ARMCC::AL));
    9010           4 :       BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
    9011           2 :         .addReg(LHS2).addImm(0)
    9012           1 :         .addImm(ARMCC::EQ).addReg(ARM::CPSR);
    9013             :     } else {
    9014           0 :       unsigned RHS1 = MI.getOperand(3).getReg();
    9015           0 :       unsigned RHS2 = MI.getOperand(4).getReg();
    9016           0 :       BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
    9017           0 :           .addReg(LHS1)
    9018           0 :           .addReg(RHS1)
    9019           0 :           .add(predOps(ARMCC::AL));
    9020           0 :       BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
    9021           0 :         .addReg(LHS2).addReg(RHS2)
    9022           0 :         .addImm(ARMCC::EQ).addReg(ARM::CPSR);
    9023             :     }
    9024             : 
    9025           2 :     MachineBasicBlock *destMBB = MI.getOperand(RHSisZero ? 3 : 5).getMBB();
    9026           2 :     MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
    9027           1 :     if (MI.getOperand(0).getImm() == ARMCC::NE)
    9028             :       std::swap(destMBB, exitMBB);
    9029             : 
    9030           4 :     BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
    9031           3 :       .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
    9032           1 :     if (isThumb2)
    9033           0 :       BuildMI(BB, dl, TII->get(ARM::t2B))
    9034           0 :           .addMBB(exitMBB)
    9035           0 :           .add(predOps(ARMCC::AL));
    9036             :     else
    9037           4 :       BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
    9038             : 
    9039           1 :     MI.eraseFromParent(); // The pseudo instruction is gone now.
    9040             :     return BB;
    9041             :   }
    9042             : 
    9043             :   case ARM::Int_eh_sjlj_setjmp:
    9044             :   case ARM::Int_eh_sjlj_setjmp_nofp:
    9045             :   case ARM::tInt_eh_sjlj_setjmp:
    9046             :   case ARM::t2Int_eh_sjlj_setjmp:
    9047             :   case ARM::t2Int_eh_sjlj_setjmp_nofp:
    9048             :     return BB;
    9049             : 
    9050          28 :   case ARM::Int_eh_sjlj_setup_dispatch:
    9051          28 :     EmitSjLjDispatchBlock(MI, BB);
    9052          28 :     return BB;
    9053             : 
    9054           8 :   case ARM::ABS:
    9055             :   case ARM::t2ABS: {
    9056             :     // To insert an ABS instruction, we have to insert the
    9057             :     // diamond control-flow pattern.  The incoming instruction knows the
    9058             :     // source vreg to test against 0, the destination vreg to set,
    9059             :     // the condition code register to branch on, the
    9060             :     // true/false values to select between, and a branch opcode to use.
    9061             :     // It transforms
    9062             :     //     V1 = ABS V0
    9063             :     // into
    9064             :     //     V2 = MOVS V0
    9065             :     //     BCC                      (branch to SinkBB if V0 >= 0)
    9066             :     //     RSBBB: V3 = RSBri V2, 0  (compute ABS if V2 < 0)
    9067             :     //     SinkBB: V1 = PHI(V2, V3)
    9068           8 :     const BasicBlock *LLVM_BB = BB->getBasicBlock();
    9069          24 :     MachineFunction::iterator BBI = ++BB->getIterator();
    9070           8 :     MachineFunction *Fn = BB->getParent();
    9071           8 :     MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
    9072           8 :     MachineBasicBlock *SinkBB  = Fn->CreateMachineBasicBlock(LLVM_BB);
    9073           8 :     Fn->insert(BBI, RSBBB);
    9074           8 :     Fn->insert(BBI, SinkBB);
    9075             : 
    9076           8 :     unsigned int ABSSrcReg = MI.getOperand(1).getReg();
    9077           8 :     unsigned int ABSDstReg = MI.getOperand(0).getReg();
    9078          16 :     bool ABSSrcKIll = MI.getOperand(1).isKill();
    9079          16 :     bool isThumb2 = Subtarget->isThumb2();
    9080           8 :     MachineRegisterInfo &MRI = Fn->getRegInfo();
    9081             :     // In Thumb mode S must not be specified if source register is the SP or
    9082             :     // PC and if destination register is the SP, so restrict register class
    9083             :     unsigned NewRsbDstReg =
    9084           8 :       MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
    9085             : 
    9086             :     // Transfer the remainder of BB and its successor edges to sinkMBB.
    9087          40 :     SinkBB->splice(SinkBB->begin(), BB,
    9088             :                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
    9089           8 :     SinkBB->transferSuccessorsAndUpdatePHIs(BB);
    9090             : 
    9091           8 :     BB->addSuccessor(RSBBB);
    9092           8 :     BB->addSuccessor(SinkBB);
    9093             : 
    9094             :     // fall through to SinkMBB
    9095           8 :     RSBBB->addSuccessor(SinkBB);
    9096             : 
    9097             :     // insert a cmp at the end of BB
    9098          32 :     BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
    9099           8 :         .addReg(ABSSrcReg)
    9100           8 :         .addImm(0)
    9101          24 :         .add(predOps(ARMCC::AL));
    9102             : 
    9103             :     // insert a bcc with opposite CC to ARMCC::MI at the end of BB
    9104          16 :     BuildMI(BB, dl,
    9105          24 :       TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
    9106          16 :       .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
    9107             : 
    9108             :     // insert rsbri in RSBBB
    9109             :     // Note: BCC and rsbri will be converted into predicated rsbmi
    9110             :     // by if-conversion pass
    9111          16 :     BuildMI(*RSBBB, RSBBB->begin(), dl,
    9112          24 :             TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
    9113           8 :         .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
    9114           8 :         .addImm(0)
    9115          32 :         .add(predOps(ARMCC::AL))
    9116          16 :         .add(condCodeOp());
    9117             : 
    9118             :     // insert PHI in SinkBB,
    9119             :     // reuse ABSDstReg to not change uses of ABS instruction
    9120          16 :     BuildMI(*SinkBB, SinkBB->begin(), dl,
    9121          16 :       TII->get(ARM::PHI), ABSDstReg)
    9122          16 :       .addReg(NewRsbDstReg).addMBB(RSBBB)
    9123          16 :       .addReg(ABSSrcReg).addMBB(BB);
    9124             : 
    9125             :     // remove ABS instruction
    9126           8 :     MI.eraseFromParent();
    9127             : 
    9128             :     // return last added BB
    9129             :     return SinkBB;
    9130             :   }
    9131         354 :   case ARM::COPY_STRUCT_BYVAL_I32:
    9132         354 :     ++NumLoopByVals;
    9133         354 :     return EmitStructByval(MI, BB);
    9134           4 :   case ARM::WIN__CHKSTK:
    9135           4 :     return EmitLowered__chkstk(MI, BB);
    9136          58 :   case ARM::WIN__DBZCHK:
    9137          58 :     return EmitLowered__dbzchk(MI, BB);
    9138             :   }
    9139             : }
    9140             : 
    9141             : /// \brief Attaches vregs to MEMCPY that it will use as scratch registers
    9142             : /// when it is expanded into LDM/STM. This is done as a post-isel lowering
    9143             : /// instead of as a custom inserter because we need the use list from the SDNode.
    9144          56 : static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget,
    9145             :                                     MachineInstr &MI, const SDNode *Node) {
    9146         112 :   bool isThumb1 = Subtarget->isThumb1Only();
    9147             : 
    9148         168 :   DebugLoc DL = MI.getDebugLoc();
    9149          56 :   MachineFunction *MF = MI.getParent()->getParent();
    9150          56 :   MachineRegisterInfo &MRI = MF->getRegInfo();
    9151         112 :   MachineInstrBuilder MIB(*MF, MI);
    9152             : 
    9153             :   // If the new dst/src is unused mark it as dead.
    9154          56 :   if (!Node->hasAnyUseOfValue(0)) {
    9155          26 :     MI.getOperand(0).setIsDead(true);
    9156             :   }
    9157          56 :   if (!Node->hasAnyUseOfValue(1)) {
    9158          26 :     MI.getOperand(1).setIsDead(true);
    9159             :   }
    9160             : 
    9161             :   // The MEMCPY both defines and kills the scratch registers.
    9162         514 :   for (unsigned I = 0; I != MI.getOperand(4).getImm(); ++I) {
    9163         229 :     unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass
    9164         229 :                                                          : &ARM::GPRRegClass);
    9165         229 :     MIB.addReg(TmpReg, RegState::Define|RegState::Dead);
    9166             :   }
    9167          56 : }
    9168             : 
    9169         853 : void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
    9170             :                                                       SDNode *Node) const {
    9171        1706 :   if (MI.getOpcode() == ARM::MEMCPY) {
    9172          56 :     attachMEMCPYScratchRegs(Subtarget, MI, Node);
    9173          56 :     return;
    9174             :   }
    9175             : 
    9176         797 :   const MCInstrDesc *MCID = &MI.getDesc();
    9177             :   // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
    9178             :   // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
    9179             :   // operand is still set to noreg. If needed, set the optional operand's
    9180             :   // register to CPSR, and remove the redundant implicit def.
    9181             :   //
    9182             :   // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
    9183             : 
    9184             :   // Rename pseudo opcodes.
    9185         797 :   unsigned NewOpc = convertAddSubFlagsOpcode(MI.getOpcode());
    9186             :   unsigned ccOutIdx;
    9187         797 :   if (NewOpc) {
    9188         454 :     const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
    9189         908 :     MCID = &TII->get(NewOpc);
    9190             : 
    9191             :     assert(MCID->getNumOperands() ==
    9192             :            MI.getDesc().getNumOperands() + 5 - MI.getDesc().getSize()
    9193             :         && "converted opcode should be the same except for cc_out"
    9194             :            " (and, on Thumb1, pred)");
    9195             : 
    9196         908 :     MI.setDesc(*MCID);
    9197             : 
    9198             :     // Add the optional cc_out operand
    9199         454 :     MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
    9200             : 
    9201             :     // On Thumb1, move all input operands to the end, then add the predicate
    9202         454 :     if (Subtarget->isThumb1Only()) {
    9203         426 :       for (unsigned c = MCID->getNumOperands() - 4; c--;) {
    9204         568 :         MI.addOperand(MI.getOperand(1));
    9205         284 :         MI.RemoveOperand(1);
    9206             :       }
    9207             : 
    9208             :       // Restore the ties
    9209         142 :       for (unsigned i = MI.getNumOperands(); i--;) {
    9210        1562 :         const MachineOperand& op = MI.getOperand(i);
    9211        1542 :         if (op.isReg() && op.isUse()) {
    9212         417 :           int DefIdx = MCID->getOperandConstraint(i, MCOI::TIED_TO);
    9213             :           if (DefIdx != -1)
    9214          82 :             MI.tieOperands(DefIdx, i);
    9215             :         }
    9216             :       }
    9217             : 
    9218         142 :       MI.addOperand(MachineOperand::CreateImm(ARMCC::AL));
    9219         142 :       MI.addOperand(MachineOperand::CreateReg(0, /*isDef=*/false));
    9220         142 :       ccOutIdx = 1;
    9221             :     } else
    9222         312 :       ccOutIdx = MCID->getNumOperands() - 1;
    9223             :   } else
    9224         343 :     ccOutIdx = MCID->getNumOperands() - 1;
    9225             : 
    9226             :   // Any ARM instruction that sets the 's' bit should specify an optional
    9227             :   // "cc_out" operand in the last operand position.
    9228         797 :   if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
    9229             :     assert(!NewOpc && "Optional cc_out operand required");
    9230             :     return;
    9231             :   }
    9232             :   // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
    9233             :   // since we already have an optional CPSR def.
    9234         797 :   bool definesCPSR = false;
    9235         797 :   bool deadCPSR = false;
    9236        1594 :   for (unsigned i = MCID->getNumOperands(), e = MI.getNumOperands(); i != e;
    9237             :        ++i) {
    9238        1594 :     const MachineOperand &MO = MI.getOperand(i);
    9239        1594 :     if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
    9240         797 :       definesCPSR = true;
    9241         797 :       if (MO.isDead())
    9242         307 :         deadCPSR = true;
    9243         797 :       MI.RemoveOperand(i);
    9244         797 :       break;
    9245             :     }
    9246             :   }
    9247         797 :   if (!definesCPSR) {
    9248             :     assert(!NewOpc && "Optional cc_out operand required");
    9249             :     return;
    9250             :   }
    9251             :   assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
    9252         797 :   if (deadCPSR) {
    9253             :     assert(!MI.getOperand(ccOutIdx).getReg() &&
    9254             :            "expect uninitialized optional cc_out operand");
    9255             :     // Thumb1 instructions must have the S bit even if the CPSR is dead.
    9256         307 :     if (!Subtarget->isThumb1Only())
    9257             :       return;
    9258             :   }
    9259             : 
    9260             :   // If this instruction was defined with an optional CPSR def and its dag node
    9261             :   // had a live implicit CPSR def, then activate the optional CPSR def.
    9262        1122 :   MachineOperand &MO = MI.getOperand(ccOutIdx);
    9263         561 :   MO.setReg(ARM::CPSR);
    9264         561 :   MO.setIsDef(true);
    9265             : }
    9266             : 
    9267             : //===----------------------------------------------------------------------===//
    9268             : //                           ARM Optimization Hooks
    9269             : //===----------------------------------------------------------------------===//
    9270             : 
    9271             : // Helper function that checks if N is a null or all ones constant.
    9272             : static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
    9273         211 :   return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
    9274             : }
    9275             : 
    9276             : // Return true if N is conditionally 0 or all ones.
    9277             : // Detects these expressions where cc is an i1 value:
    9278             : //
    9279             : //   (select cc 0, y)   [AllOnes=0]
    9280             : //   (select cc y, 0)   [AllOnes=0]
    9281             : //   (zext cc)          [AllOnes=0]
    9282             : //   (sext cc)          [AllOnes=0/1]
    9283             : //   (select cc -1, y)  [AllOnes=1]
    9284             : //   (select cc y, -1)  [AllOnes=1]
    9285             : //
    9286             : // Invert is set when N is the null/all ones constant when CC is false.
    9287             : // OtherOp is set to the alternative value of N.
    9288       26817 : static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
    9289             :                                        SDValue &CC, bool &Invert,
    9290             :                                        SDValue &OtherOp,
    9291             :                                        SelectionDAG &DAG) {
    9292       53634 :   switch (N->getOpcode()) {
    9293             :   default: return false;
    9294         113 :   case ISD::SELECT: {
    9295         226 :     CC = N->getOperand(0);
    9296         226 :     SDValue N1 = N->getOperand(1);
    9297         226 :     SDValue N2 = N->getOperand(2);
    9298         113 :     if (isZeroOrAllOnes(N1, AllOnes)) {
    9299          15 :       Invert = false;
    9300          15 :       OtherOp = N2;
    9301          15 :       return true;
    9302             :     }
    9303          98 :     if (isZeroOrAllOnes(N2, AllOnes)) {
    9304          25 :       Invert = true;
    9305          25 :       OtherOp = N1;
    9306          25 :       return true;
    9307             :     }
    9308             :     return false;
    9309             :   }
    9310         231 :   case ISD::ZERO_EXTEND:
    9311             :     // (zext cc) can never be the all ones value.
    9312         231 :     if (AllOnes)
    9313             :       return false;
    9314             :     LLVM_FALLTHROUGH;
    9315             :   case ISD::SIGN_EXTEND: {
    9316         830 :     SDLoc dl(N);
    9317         830 :     EVT VT = N->getValueType(0);
    9318         830 :     CC = N->getOperand(0);
    9319         864 :     if (CC.getValueType() != MVT::i1 || CC.getOpcode() != ISD::SETCC)
    9320             :       return false;
    9321          13 :     Invert = !AllOnes;
    9322          13 :     if (AllOnes)
    9323             :       // When looking for an AllOnes constant, N is an sext, and the 'other'
    9324             :       // value is 0.
    9325           0 :       OtherOp = DAG.getConstant(0, dl, VT);
    9326          13 :     else if (N->getOpcode() == ISD::ZERO_EXTEND)
    9327             :       // When looking for a 0 constant, N can be zext or sext.
    9328          13 :       OtherOp = DAG.getConstant(1, dl, VT);
    9329             :     else
    9330           0 :       OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
    9331             :                                 VT);
    9332             :     return true;
    9333             :   }
    9334             :   }
    9335             : }
    9336             : 
    9337             : // Combine a constant select operand into its use:
    9338             : //
    9339             : //   (add (select cc, 0, c), x)  -> (select cc, x, (add, x, c))
    9340             : //   (sub x, (select cc, 0, c))  -> (select cc, x, (sub, x, c))
    9341             : //   (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))  [AllOnes=1]
    9342             : //   (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
    9343             : //   (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))
    9344             : //
    9345             : // The transform is rejected if the select doesn't have a constant operand that
    9346             : // is null, or all ones when AllOnes is set.
    9347             : //
    9348             : // Also recognize sext/zext from i1:
    9349             : //
    9350             : //   (add (zext cc), x) -> (select cc (add x, 1), x)
    9351             : //   (add (sext cc), x) -> (select cc (add x, -1), x)
    9352             : //
    9353             : // These transformations eventually create predicated instructions.
    9354             : //
    9355             : // @param N       The node to transform.
    9356             : // @param Slct    The N operand that is a select.
    9357             : // @param OtherOp The other N operand (x above).
    9358             : // @param DCI     Context.
    9359             : // @param AllOnes Require the select constant to be all ones instead of null.
    9360             : // @returns The new node, or SDValue() on failure.
    9361             : static
    9362       26817 : SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
    9363             :                             TargetLowering::DAGCombinerInfo &DCI,
    9364             :                             bool AllOnes = false) {
    9365       26817 :   SelectionDAG &DAG = DCI.DAG;
    9366       53634 :   EVT VT = N->getValueType(0);
    9367       26817 :   SDValue NonConstantVal;
    9368       26817 :   SDValue CCOp;
    9369             :   bool SwapSelectOps;
    9370       26817 :   if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
    9371             :                                   NonConstantVal, DAG))
    9372       26764 :     return SDValue();
    9373             : 
    9374             :   // Slct is now know to be the desired identity constant when CC is true.
    9375          53 :   SDValue TrueVal = OtherOp;
    9376         106 :   SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
    9377         212 :                                  OtherOp, NonConstantVal);
    9378             :   // Unless SwapSelectOps says CC should be false.
    9379          53 :   if (SwapSelectOps)
    9380             :     std::swap(TrueVal, FalseVal);
    9381             : 
    9382         106 :   return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
    9383          53 :                      CCOp, TrueVal, FalseVal);
    9384             : }
    9385             : 
    9386             : // Attempt combineSelectAndUse on each operand of a commutative operator N.
    9387             : static
    9388        5167 : SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
    9389             :                                        TargetLowering::DAGCombinerInfo &DCI) {
    9390       10334 :   SDValue N0 = N->getOperand(0);
    9391       10334 :   SDValue N1 = N->getOperand(1);
    9392        8745 :   if (N0.getNode()->hasOneUse())
    9393        3578 :     if (SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes))
    9394          13 :       return Result;
    9395        9140 :   if (N1.getNode()->hasOneUse())
    9396        3986 :     if (SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes))
    9397           2 :       return Result;
    9398        5152 :   return SDValue();
    9399             : }
    9400             : 
    9401             : static bool IsVUZPShuffleNode(SDNode *N) {
    9402             :   // VUZP shuffle node.
    9403       37630 :   if (N->getOpcode() == ARMISD::VUZP)
    9404             :     return true;
    9405             : 
    9406             :   // "VUZP" on i32 is an alias for VTRN.
    9407       37647 :   if (N->getOpcode() == ARMISD::VTRN && N->getValueType(0) == MVT::v2i32)
    9408             :     return true;
    9409             : 
    9410             :   return false;
    9411             : }
    9412             : 
    9413       37548 : static SDValue AddCombineToVPADD(SDNode *N, SDValue N0, SDValue N1,
    9414             :                                  TargetLowering::DAGCombinerInfo &DCI,
    9415             :                                  const ARMSubtarget *Subtarget) {
    9416             :   // Look for ADD(VUZP.0, VUZP.1).
    9417       37562 :   if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() ||
    9418          14 :       N0 == N1)
    9419       37534 :    return SDValue();
    9420             : 
    9421             :   // Make sure the ADD is a 64-bit add; there is no 128-bit VPADD.
    9422          28 :   if (!N->getValueType(0).is64BitVector())
    9423          10 :     return SDValue();
    9424             : 
    9425             :   // Generate vpadd.
    9426           4 :   SelectionDAG &DAG = DCI.DAG;
    9427           4 :   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
    9428           4 :   SDLoc dl(N);
    9429           4 :   SDNode *Unzip = N0.getNode();
    9430           8 :   EVT VT = N->getValueType(0);
    9431             : 
    9432           8 :   SmallVector<SDValue, 8> Ops;
    9433           4 :   Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpadd, dl,
    9434          20 :                                 TLI.getPointerTy(DAG.getDataLayout())));
    9435           8 :   Ops.push_back(Unzip->getOperand(0));
    9436           8 :   Ops.push_back(Unzip->getOperand(1));
    9437             : 
    9438           8 :   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);
    9439             : }
    9440             : 
    9441       37544 : static SDValue AddCombineVUZPToVPADDL(SDNode *N, SDValue N0, SDValue N1,
    9442             :                                       TargetLowering::DAGCombinerInfo &DCI,
    9443             :                                       const ARMSubtarget *Subtarget) {
    9444             :   // Check for two extended operands.
    9445       37728 :   if (!(N0.getOpcode() == ISD::SIGN_EXTEND &&
    9446       75059 :         N1.getOpcode() == ISD::SIGN_EXTEND) &&
    9447       37707 :       !(N0.getOpcode() == ISD::ZERO_EXTEND &&
    9448         192 :         N1.getOpcode() == ISD::ZERO_EXTEND))
    9449       37462 :     return SDValue();
    9450             : 
    9451         164 :   SDValue N00 = N0.getOperand(0);
    9452         164 :   SDValue N10 = N1.getOperand(0);
    9453             : 
    9454             :   // Look for ADD(SEXT(VUZP.0), SEXT(VUZP.1))
    9455          88 :   if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() ||
    9456           6 :       N00 == N10)
    9457          76 :     return SDValue();
    9458             : 
    9459             :   // We only recognize Q register paddl here; this can't be reached until
    9460             :   // after type legalization.
    9461          24 :   if (!N00.getValueType().is64BitVector() ||
    9462          18 :       !N0.getValueType().is128BitVector())
    9463           0 :     return SDValue();
    9464             : 
    9465             :   // Generate vpaddl.
    9466           6 :   SelectionDAG &DAG = DCI.DAG;
    9467           6 :   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
    9468           6 :   SDLoc dl(N);
    9469          12 :   EVT VT = N->getValueType(0);
    9470             : 
    9471          12 :   SmallVector<SDValue, 8> Ops;
    9472             :   // Form vpaddl.sN or vpaddl.uN depending on the kind of extension.
    9473             :   unsigned Opcode;
    9474          12 :   if (N0.getOpcode() == ISD::SIGN_EXTEND)
    9475             :     Opcode = Intrinsic::arm_neon_vpaddls;
    9476             :   else
    9477           3 :     Opcode = Intrinsic::arm_neon_vpaddlu;
    9478           6 :   Ops.push_back(DAG.getConstant(Opcode, dl,
    9479          30 :                                 TLI.getPointerTy(DAG.getDataLayout())));
    9480          12 :   EVT ElemTy = N00.getValueType().getVectorElementType();
    9481           6 :   unsigned NumElts = VT.getVectorNumElements();
    9482           6 :   EVT ConcatVT = EVT::getVectorVT(*DAG.getContext(), ElemTy, NumElts * 2);
    9483          12 :   SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), ConcatVT,
    9484          30 :                                N00.getOperand(0), N00.getOperand(1));
    9485           6 :   Ops.push_back(Concat);
    9486             : 
    9487          12 :   return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, Ops);
    9488             : }
    9489             : 
    9490             : // FIXME: This function shouldn't be necessary; if we lower BUILD_VECTOR in
    9491             : // an appropriate manner, we end up with ADD(VUZP(ZEXT(N))), which is
    9492             : // much easier to match.
    9493             : static SDValue
    9494       37538 : AddCombineBUILD_VECTORToVPADDL(SDNode *N, SDValue N0, SDValue N1,
    9495             :                                TargetLowering::DAGCombinerInfo &DCI,
    9496             :                                const ARMSubtarget *Subtarget) {
    9497             :   // Only perform optimization if after legalize, and if NEON is available. We
    9498             :   // also expected both operands to be BUILD_VECTORs.
    9499       58622 :   if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
    9500       26264 :       || N0.getOpcode() != ISD::BUILD_VECTOR
    9501       37610 :       || N1.getOpcode() != ISD::BUILD_VECTOR)
    9502       37524 :     return SDValue();
    9503             : 
    9504             :   // Check output type since VPADDL operand elements can only be 8, 16, or 32.
    9505          28 :   EVT VT = N->getValueType(0);
    9506          42 :   if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
    9507           0 :     return SDValue();
    9508             : 
    9509             :   // Check that the vector operands are of the right form.
    9510             :   // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
    9511             :   // operands, where N is the size of the formed vector.
    9512             :   // Each EXTRACT_VECTOR should have the same input vector and odd or even
    9513             :   // index such that we have a pair wise add pattern.
    9514             : 
    9515             :   // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
    9516          28 :   if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
    9517           4 :     return SDValue();
    9518          30 :   SDValue Vec = N0->getOperand(0)->getOperand(0);
    9519          10 :   SDNode *V = Vec.getNode();
    9520          10 :   unsigned nextIndex = 0;
    9521             : 
    9522             :   // For each operands to the ADD which are BUILD_VECTORs,
    9523             :   // check to see if each of their operands are an EXTRACT_VECTOR with
    9524             :   // the same vector and appropriate index.
    9525          34 :   for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
    9526          38 :     if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
    9527          38 :         && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
    9528             : 
    9529          38 :       SDValue ExtVec0 = N0->getOperand(i);
    9530          38 :       SDValue ExtVec1 = N1->getOperand(i);
    9531             : 
    9532             :       // First operand is the vector, verify its the same.
    9533          57 :       if (V != ExtVec0->getOperand(0).getNode() ||
    9534          38 :           V != ExtVec1->getOperand(0).getNode())
    9535           0 :         return SDValue();
    9536             : 
    9537             :       // Second is the constant, verify its correct.
    9538          57 :       ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
    9539          57 :       ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
    9540             : 
    9541             :       // For the constant, we want to see all the even or all the odd.
    9542          38 :       if (!C0 || !C1 || C0->getZExtValue() != nextIndex
    9543          33 :           || C1->getZExtValue() != nextIndex+1)
    9544           5 :         return SDValue();
    9545             : 
    9546             :       // Increment index.
    9547          14 :       nextIndex+=2;
    9548             :     } else
    9549           0 :       return SDValue();
    9550             :   }
    9551             : 
    9552             :   // Don't generate vpaddl+vmovn; we'll match it to vpadd later. Also make sure
    9553             :   // we're using the entire input vector, otherwise there's a size/legality
    9554             :   // mismatch somewhere.
    9555          15 :   if (nextIndex != Vec.getValueType().getVectorNumElements() ||
    9556          11 :       Vec.getValueType().getVectorElementType() == VT.getVectorElementType())
    9557           3 :     return SDValue();
    9558             : 
    9559             :   // Create VPADDL node.