LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMISelLowering.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 24 34 70.6 %
Date: 2018-02-23 15:42:53 Functions: 10 12 83.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the interfaces that ARM uses to lower LLVM code into a
      11             : // selection DAG.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
      16             : #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
      17             : 
      18             : #include "MCTargetDesc/ARMBaseInfo.h"
      19             : #include "llvm/ADT/SmallVector.h"
      20             : #include "llvm/ADT/StringRef.h"
      21             : #include "llvm/CodeGen/CallingConvLower.h"
      22             : #include "llvm/CodeGen/ISDOpcodes.h"
      23             : #include "llvm/CodeGen/MachineFunction.h"
      24             : #include "llvm/CodeGen/MachineValueType.h"
      25             : #include "llvm/CodeGen/SelectionDAGNodes.h"
      26             : #include "llvm/CodeGen/TargetLowering.h"
      27             : #include "llvm/CodeGen/ValueTypes.h"
      28             : #include "llvm/IR/Attributes.h"
      29             : #include "llvm/IR/CallingConv.h"
      30             : #include "llvm/IR/Function.h"
      31             : #include "llvm/IR/IRBuilder.h"
      32             : #include "llvm/IR/InlineAsm.h"
      33             : #include "llvm/Support/CodeGen.h"
      34             : #include <utility>
      35             : 
      36             : namespace llvm {
      37             : 
      38             : class ARMSubtarget;
      39             : class DataLayout;
      40             : class FastISel;
      41             : class FunctionLoweringInfo;
      42             : class GlobalValue;
      43             : class InstrItineraryData;
      44             : class Instruction;
      45             : class MachineBasicBlock;
      46             : class MachineInstr;
      47             : class SelectionDAG;
      48             : class TargetLibraryInfo;
      49             : class TargetMachine;
      50             : class TargetRegisterInfo;
      51             : class VectorType;
      52             : 
      53             :   namespace ARMISD {
      54             : 
      55             :     // ARM Specific DAG Nodes
      56             :     enum NodeType : unsigned {
      57             :       // Start the numbering where the builtin ops and target ops leave off.
      58             :       FIRST_NUMBER = ISD::BUILTIN_OP_END,
      59             : 
      60             :       Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
      61             :                     // TargetExternalSymbol, and TargetGlobalAddress.
      62             :       WrapperPIC,   // WrapperPIC - A wrapper node for TargetGlobalAddress in
      63             :                     // PIC mode.
      64             :       WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
      65             : 
      66             :       // Add pseudo op to model memcpy for struct byval.
      67             :       COPY_STRUCT_BYVAL,
      68             : 
      69             :       CALL,         // Function call.
      70             :       CALL_PRED,    // Function call that's predicable.
      71             :       CALL_NOLINK,  // Function call with branch not branch-and-link.
      72             :       BRCOND,       // Conditional branch.
      73             :       BR_JT,        // Jumptable branch.
      74             :       BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
      75             :       RET_FLAG,     // Return with a flag operand.
      76             :       INTRET_FLAG,  // Interrupt return with an LR-offset and a flag operand.
      77             : 
      78             :       PIC_ADD,      // Add with a PC operand and a PIC label.
      79             : 
      80             :       CMP,          // ARM compare instructions.
      81             :       CMN,          // ARM CMN instructions.
      82             :       CMPZ,         // ARM compare that sets only Z flag.
      83             :       CMPFP,        // ARM VFP compare instruction, sets FPSCR.
      84             :       CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
      85             :       FMSTAT,       // ARM fmstat instruction.
      86             : 
      87             :       CMOV,         // ARM conditional move instructions.
      88             : 
      89             :       SSAT,         // Signed saturation
      90             :       USAT,         // Unsigned saturation
      91             : 
      92             :       BCC_i64,
      93             : 
      94             :       SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
      95             :       SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
      96             :       RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
      97             : 
      98             :       ADDC,         // Add with carry
      99             :       ADDE,         // Add using carry
     100             :       SUBC,         // Sub with carry
     101             :       SUBE,         // Sub using carry
     102             : 
     103             :       VMOVRRD,      // double to two gprs.
     104             :       VMOVDRR,      // Two gprs to double.
     105             : 
     106             :       EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
     107             :       EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
     108             :       EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
     109             : 
     110             :       TC_RETURN,    // Tail call return pseudo.
     111             : 
     112             :       THREAD_POINTER,
     113             : 
     114             :       DYN_ALLOC,    // Dynamic allocation on the stack.
     115             : 
     116             :       MEMBARRIER_MCR, // Memory barrier (MCR)
     117             : 
     118             :       PRELOAD,      // Preload
     119             : 
     120             :       WIN__CHKSTK,  // Windows' __chkstk call to do stack probing.
     121             :       WIN__DBZCHK,  // Windows' divide by zero check
     122             : 
     123             :       VCEQ,         // Vector compare equal.
     124             :       VCEQZ,        // Vector compare equal to zero.
     125             :       VCGE,         // Vector compare greater than or equal.
     126             :       VCGEZ,        // Vector compare greater than or equal to zero.
     127             :       VCLEZ,        // Vector compare less than or equal to zero.
     128             :       VCGEU,        // Vector compare unsigned greater than or equal.
     129             :       VCGT,         // Vector compare greater than.
     130             :       VCGTZ,        // Vector compare greater than zero.
     131             :       VCLTZ,        // Vector compare less than zero.
     132             :       VCGTU,        // Vector compare unsigned greater than.
     133             :       VTST,         // Vector test bits.
     134             : 
     135             :       // Vector shift by immediate:
     136             :       VSHL,         // ...left
     137             :       VSHRs,        // ...right (signed)
     138             :       VSHRu,        // ...right (unsigned)
     139             : 
     140             :       // Vector rounding shift by immediate:
     141             :       VRSHRs,       // ...right (signed)
     142             :       VRSHRu,       // ...right (unsigned)
     143             :       VRSHRN,       // ...right narrow
     144             : 
     145             :       // Vector saturating shift by immediate:
     146             :       VQSHLs,       // ...left (signed)
     147             :       VQSHLu,       // ...left (unsigned)
     148             :       VQSHLsu,      // ...left (signed to unsigned)
     149             :       VQSHRNs,      // ...right narrow (signed)
     150             :       VQSHRNu,      // ...right narrow (unsigned)
     151             :       VQSHRNsu,     // ...right narrow (signed to unsigned)
     152             : 
     153             :       // Vector saturating rounding shift by immediate:
     154             :       VQRSHRNs,     // ...right narrow (signed)
     155             :       VQRSHRNu,     // ...right narrow (unsigned)
     156             :       VQRSHRNsu,    // ...right narrow (signed to unsigned)
     157             : 
     158             :       // Vector shift and insert:
     159             :       VSLI,         // ...left
     160             :       VSRI,         // ...right
     161             : 
     162             :       // Vector get lane (VMOV scalar to ARM core register)
     163             :       // (These are used for 8- and 16-bit element types only.)
     164             :       VGETLANEu,    // zero-extend vector extract element
     165             :       VGETLANEs,    // sign-extend vector extract element
     166             : 
     167             :       // Vector move immediate and move negated immediate:
     168             :       VMOVIMM,
     169             :       VMVNIMM,
     170             : 
     171             :       // Vector move f32 immediate:
     172             :       VMOVFPIMM,
     173             : 
     174             :       // Move H <-> R, clearing top 16 bits
     175             :       VMOVrh,
     176             :       VMOVhr,
     177             : 
     178             :       // Vector duplicate:
     179             :       VDUP,
     180             :       VDUPLANE,
     181             : 
     182             :       // Vector shuffles:
     183             :       VEXT,         // extract
     184             :       VREV64,       // reverse elements within 64-bit doublewords
     185             :       VREV32,       // reverse elements within 32-bit words
     186             :       VREV16,       // reverse elements within 16-bit halfwords
     187             :       VZIP,         // zip (interleave)
     188             :       VUZP,         // unzip (deinterleave)
     189             :       VTRN,         // transpose
     190             :       VTBL1,        // 1-register shuffle with mask
     191             :       VTBL2,        // 2-register shuffle with mask
     192             : 
     193             :       // Vector multiply long:
     194             :       VMULLs,       // ...signed
     195             :       VMULLu,       // ...unsigned
     196             : 
     197             :       SMULWB,       // Signed multiply word by half word, bottom
     198             :       SMULWT,       // Signed multiply word by half word, top
     199             :       UMLAL,        // 64bit Unsigned Accumulate Multiply
     200             :       SMLAL,        // 64bit Signed Accumulate Multiply
     201             :       UMAAL,        // 64-bit Unsigned Accumulate Accumulate Multiply
     202             :       SMLALBB,      // 64-bit signed accumulate multiply bottom, bottom 16
     203             :       SMLALBT,      // 64-bit signed accumulate multiply bottom, top 16
     204             :       SMLALTB,      // 64-bit signed accumulate multiply top, bottom 16
     205             :       SMLALTT,      // 64-bit signed accumulate multiply top, top 16
     206             :       SMLALD,       // Signed multiply accumulate long dual
     207             :       SMLALDX,      // Signed multiply accumulate long dual exchange
     208             :       SMLSLD,       // Signed multiply subtract long dual
     209             :       SMLSLDX,      // Signed multiply subtract long dual exchange
     210             :       SMMLAR,       // Signed multiply long, round and add
     211             :       SMMLSR,       // Signed multiply long, subtract and round
     212             : 
     213             :       // Operands of the standard BUILD_VECTOR node are not legalized, which
     214             :       // is fine if BUILD_VECTORs are always lowered to shuffles or other
     215             :       // operations, but for ARM some BUILD_VECTORs are legal as-is and their
     216             :       // operands need to be legalized.  Define an ARM-specific version of
     217             :       // BUILD_VECTOR for this purpose.
     218             :       BUILD_VECTOR,
     219             : 
     220             :       // Bit-field insert
     221             :       BFI,
     222             : 
     223             :       // Vector OR with immediate
     224             :       VORRIMM,
     225             :       // Vector AND with NOT of immediate
     226             :       VBICIMM,
     227             : 
     228             :       // Vector bitwise select
     229             :       VBSL,
     230             : 
     231             :       // Pseudo-instruction representing a memory copy using ldm/stm
     232             :       // instructions.
     233             :       MEMCPY,
     234             : 
     235             :       // Vector load N-element structure to all lanes:
     236             :       VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
     237             :       VLD2DUP,
     238             :       VLD3DUP,
     239             :       VLD4DUP,
     240             : 
     241             :       // NEON loads with post-increment base updates:
     242             :       VLD1_UPD,
     243             :       VLD2_UPD,
     244             :       VLD3_UPD,
     245             :       VLD4_UPD,
     246             :       VLD2LN_UPD,
     247             :       VLD3LN_UPD,
     248             :       VLD4LN_UPD,
     249             :       VLD1DUP_UPD,
     250             :       VLD2DUP_UPD,
     251             :       VLD3DUP_UPD,
     252             :       VLD4DUP_UPD,
     253             : 
     254             :       // NEON stores with post-increment base updates:
     255             :       VST1_UPD,
     256             :       VST2_UPD,
     257             :       VST3_UPD,
     258             :       VST4_UPD,
     259             :       VST2LN_UPD,
     260             :       VST3LN_UPD,
     261             :       VST4LN_UPD
     262             :     };
     263             : 
     264             :   } // end namespace ARMISD
     265             : 
     266             :   /// Define some predicates that are used for node matching.
     267             :   namespace ARM {
     268             : 
     269             :     bool isBitFieldInvertedMask(unsigned v);
     270             : 
     271             :   } // end namespace ARM
     272             : 
     273             :   //===--------------------------------------------------------------------===//
     274             :   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
     275             : 
     276        4661 :   class ARMTargetLowering : public TargetLowering {
     277             :   public:
     278             :     explicit ARMTargetLowering(const TargetMachine &TM,
     279             :                                const ARMSubtarget &STI);
     280             : 
     281             :     unsigned getJumpTableEncoding() const override;
     282             :     bool useSoftFloat() const override;
     283             : 
     284             :     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     285             : 
     286             :     /// ReplaceNodeResults - Replace the results of node with an illegal result
     287             :     /// type with new values built out of custom code.
     288             :     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
     289             :                             SelectionDAG &DAG) const override;
     290             : 
     291             :     const char *getTargetNodeName(unsigned Opcode) const override;
     292             : 
     293        1031 :     bool isSelectSupported(SelectSupportKind Kind) const override {
     294             :       // ARM does not support scalar condition selects on vectors.
     295        1031 :       return (Kind != ScalarCondVectorVal);
     296             :     }
     297             : 
     298             :     bool isReadOnly(const GlobalValue *GV) const;
     299             : 
     300             :     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
     301             :     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
     302             :                            EVT VT) const override;
     303             : 
     304             :     MachineBasicBlock *
     305             :     EmitInstrWithCustomInserter(MachineInstr &MI,
     306             :                                 MachineBasicBlock *MBB) const override;
     307             : 
     308             :     void AdjustInstrPostInstrSelection(MachineInstr &MI,
     309             :                                        SDNode *Node) const override;
     310             : 
     311             :     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
     312             :     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
     313             :     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
     314             :     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
     315             : 
     316             :     bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
     317             : 
     318             :     /// allowsMisalignedMemoryAccesses - Returns true if the target allows
     319             :     /// unaligned memory accesses of the specified type. Returns whether it
     320             :     /// is "fast" by reference in the second argument.
     321             :     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
     322             :                                         unsigned Align,
     323             :                                         bool *Fast) const override;
     324             : 
     325             :     EVT getOptimalMemOpType(uint64_t Size,
     326             :                             unsigned DstAlign, unsigned SrcAlign,
     327             :                             bool IsMemset, bool ZeroMemset,
     328             :                             bool MemcpyStrSrc,
     329             :                             MachineFunction &MF) const override;
     330             : 
     331             :     bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
     332             :     bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
     333             :     bool isZExtFree(SDValue Val, EVT VT2) const override;
     334             :     bool isFNegFree(EVT VT) const override;
     335             : 
     336             :     bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
     337             : 
     338             :     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
     339             : 
     340             : 
     341             :     /// isLegalAddressingMode - Return true if the addressing mode represented
     342             :     /// by AM is legal for this target, for a load/store of the specified type.
     343             :     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
     344             :                                Type *Ty, unsigned AS,
     345             :                                Instruction *I = nullptr) const override;
     346             : 
     347             :     /// getScalingFactorCost - Return the cost of the scaling used in
     348             :     /// addressing mode represented by AM.
     349             :     /// If the AM is supported, the return value must be >= 0.
     350             :     /// If the AM is not supported, the return value must be negative.
     351             :     int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
     352             :                              unsigned AS) const override;
     353             : 
     354             :     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
     355             : 
     356             :     /// \brief Returns true if the addresing mode representing by AM is legal
     357             :     /// for the Thumb1 target, for a load/store of the specified type.
     358             :     bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
     359             : 
     360             :     /// isLegalICmpImmediate - Return true if the specified immediate is legal
     361             :     /// icmp immediate, that is the target has icmp instructions which can
     362             :     /// compare a register against the immediate without having to materialize
     363             :     /// the immediate into a register.
     364             :     bool isLegalICmpImmediate(int64_t Imm) const override;
     365             : 
     366             :     /// isLegalAddImmediate - Return true if the specified immediate is legal
     367             :     /// add immediate, that is the target has add instructions which can
     368             :     /// add a register and the immediate without having to materialize
     369             :     /// the immediate into a register.
     370             :     bool isLegalAddImmediate(int64_t Imm) const override;
     371             : 
     372             :     /// getPreIndexedAddressParts - returns true by value, base pointer and
     373             :     /// offset pointer and addressing mode by reference if the node's address
     374             :     /// can be legally represented as pre-indexed load / store address.
     375             :     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
     376             :                                    ISD::MemIndexedMode &AM,
     377             :                                    SelectionDAG &DAG) const override;
     378             : 
     379             :     /// getPostIndexedAddressParts - returns true by value, base pointer and
     380             :     /// offset pointer and addressing mode by reference if this node can be
     381             :     /// combined with a load / store to form a post-indexed load / store.
     382             :     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
     383             :                                     SDValue &Offset, ISD::MemIndexedMode &AM,
     384             :                                     SelectionDAG &DAG) const override;
     385             : 
     386             :     void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
     387             :                                        const APInt &DemandedElts,
     388             :                                        const SelectionDAG &DAG,
     389             :                                        unsigned Depth) const override;
     390             : 
     391             : 
     392             :     bool ExpandInlineAsm(CallInst *CI) const override;
     393             : 
     394             :     ConstraintType getConstraintType(StringRef Constraint) const override;
     395             : 
     396             :     /// Examine constraint string and operand type and determine a weight value.
     397             :     /// The operand object must already have been set up with the operand type.
     398             :     ConstraintWeight getSingleConstraintMatchWeight(
     399             :       AsmOperandInfo &info, const char *constraint) const override;
     400             : 
     401             :     std::pair<unsigned, const TargetRegisterClass *>
     402             :     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     403             :                                  StringRef Constraint, MVT VT) const override;
     404             : 
     405             :     const char *LowerXConstraint(EVT ConstraintVT) const override;
     406             : 
     407             :     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     408             :     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
     409             :     /// true it means one of the asm constraint of the inline asm instruction
     410             :     /// being processed is 'm'.
     411             :     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
     412             :                                       std::vector<SDValue> &Ops,
     413             :                                       SelectionDAG &DAG) const override;
     414             : 
     415             :     unsigned
     416          25 :     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
     417             :       if (ConstraintCode == "Q")
     418             :         return InlineAsm::Constraint_Q;
     419             :       else if (ConstraintCode == "o")
     420             :         return InlineAsm::Constraint_o;
     421          17 :       else if (ConstraintCode.size() == 2) {
     422           2 :         if (ConstraintCode[0] == 'U') {
     423           2 :           switch(ConstraintCode[1]) {
     424             :           default:
     425             :             break;
     426             :           case 'm':
     427             :             return InlineAsm::Constraint_Um;
     428           0 :           case 'n':
     429           0 :             return InlineAsm::Constraint_Un;
     430           0 :           case 'q':
     431           0 :             return InlineAsm::Constraint_Uq;
     432           0 :           case 's':
     433           0 :             return InlineAsm::Constraint_Us;
     434           0 :           case 't':
     435           0 :             return InlineAsm::Constraint_Ut;
     436           2 :           case 'v':
     437           2 :             return InlineAsm::Constraint_Uv;
     438           0 :           case 'y':
     439           0 :             return InlineAsm::Constraint_Uy;
     440             :           }
     441             :         }
     442             :       }
     443             :       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
     444             :     }
     445             : 
     446             :     const ARMSubtarget* getSubtarget() const {
     447             :       return Subtarget;
     448             :     }
     449             : 
     450             :     /// getRegClassFor - Return the register class that should be used for the
     451             :     /// specified value type.
     452             :     const TargetRegisterClass *getRegClassFor(MVT VT) const override;
     453             : 
     454             :     /// Returns true if a cast between SrcAS and DestAS is a noop.
     455           2 :     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
     456             :       // Addrspacecasts are always noops.
     457           2 :       return true;
     458             :     }
     459             : 
     460             :     bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
     461             :                                 unsigned &PrefAlign) const override;
     462             : 
     463             :     /// createFastISel - This method returns a target specific FastISel object,
     464             :     /// or null if the target does not support "fast" ISel.
     465             :     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
     466             :                              const TargetLibraryInfo *libInfo) const override;
     467             : 
     468             :     Sched::Preference getSchedulingPreference(SDNode *N) const override;
     469             : 
     470             :     bool
     471             :     isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
     472             :     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
     473             : 
     474             :     /// isFPImmLegal - Returns true if the target can instruction select the
     475             :     /// specified FP immediate natively. If false, the legalizer will
     476             :     /// materialize the FP immediate as a load from a constant pool.
     477             :     bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
     478             : 
     479             :     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
     480             :                             const CallInst &I,
     481             :                             MachineFunction &MF,
     482             :                             unsigned Intrinsic) const override;
     483             : 
     484             :     /// \brief Returns true if it is beneficial to convert a load of a constant
     485             :     /// to just the constant itself.
     486             :     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
     487             :                                            Type *Ty) const override;
     488             : 
     489             :     /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
     490             :     /// with this index.
     491             :     bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
     492             :                                  unsigned Index) const override;
     493             : 
     494             :     /// \brief Returns true if an argument of type Ty needs to be passed in a
     495             :     /// contiguous block of registers in calling convention CallConv.
     496             :     bool functionArgumentNeedsConsecutiveRegisters(
     497             :         Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
     498             : 
     499             :     /// If a physical register, this returns the register that receives the
     500             :     /// exception address on entry to an EH pad.
     501             :     unsigned
     502             :     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
     503             : 
     504             :     /// If a physical register, this returns the register that receives the
     505             :     /// exception typeid on entry to a landing pad.
     506             :     unsigned
     507             :     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
     508             : 
     509             :     Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
     510             :     Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
     511             :                           AtomicOrdering Ord) const override;
     512             :     Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
     513             :                                 Value *Addr, AtomicOrdering Ord) const override;
     514             : 
     515             :     void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
     516             : 
     517             :     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
     518             :                                   AtomicOrdering Ord) const override;
     519             :     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
     520             :                                    AtomicOrdering Ord) const override;
     521             : 
     522       12107 :     unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
     523             : 
     524             :     bool lowerInterleavedLoad(LoadInst *LI,
     525             :                               ArrayRef<ShuffleVectorInst *> Shuffles,
     526             :                               ArrayRef<unsigned> Indices,
     527             :                               unsigned Factor) const override;
     528             :     bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
     529             :                                unsigned Factor) const override;
     530             : 
     531             :     bool shouldInsertFencesForAtomic(const Instruction *I) const override;
     532             :     TargetLoweringBase::AtomicExpansionKind
     533             :     shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
     534             :     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
     535             :     TargetLoweringBase::AtomicExpansionKind
     536             :     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
     537             :     bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
     538             : 
     539             :     bool useLoadStackGuardNode() const override;
     540             : 
     541             :     bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
     542             :                                    unsigned &Cost) const override;
     543             : 
     544        2795 :     bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
     545             :                           const SelectionDAG &DAG) const override {
     546             :       // Do not merge to larger than i32.
     547        2795 :       return (MemVT.getSizeInBits() <= 32);
     548             :     }
     549             : 
     550             :     bool isCheapToSpeculateCttz() const override;
     551             :     bool isCheapToSpeculateCtlz() const override;
     552             : 
     553          41 :     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     554          41 :       return VT.isScalarInteger();
     555             :     }
     556             : 
     557      294466 :     bool supportSwiftError() const override {
     558      294466 :       return true;
     559             :     }
     560             : 
     561          32 :     bool hasStandaloneRem(EVT VT) const override {
     562          32 :       return HasStandaloneRem;
     563             :     }
     564             : 
     565             :     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
     566             :     CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
     567             : 
     568             :     /// Returns true if \p VecTy is a legal interleaved access type. This
     569             :     /// function checks the vector element type and the overall width of the
     570             :     /// vector.
     571             :     bool isLegalInterleavedAccessType(VectorType *VecTy,
     572             :                                       const DataLayout &DL) const;
     573             : 
     574             :     /// Returns the number of interleaved accesses that will be generated when
     575             :     /// lowering accesses of the given type.
     576             :     unsigned getNumInterleavedAccesses(VectorType *VecTy,
     577             :                                        const DataLayout &DL) const;
     578             : 
     579             :     void finalizeLowering(MachineFunction &MF) const override;
     580             : 
     581             :   protected:
     582             :     std::pair<const TargetRegisterClass *, uint8_t>
     583             :     findRepresentativeClass(const TargetRegisterInfo *TRI,
     584             :                             MVT VT) const override;
     585             : 
     586             :   private:
     587             :     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
     588             :     /// make the right decision when generating code for different targets.
     589             :     const ARMSubtarget *Subtarget;
     590             : 
     591             :     const TargetRegisterInfo *RegInfo;
     592             : 
     593             :     const InstrItineraryData *Itins;
     594             : 
     595             :     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
     596             :     unsigned ARMPCLabelIndex;
     597             : 
     598             :     // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
     599             :     // check.
     600             :     bool InsertFencesForAtomic;
     601             : 
     602             :     bool HasStandaloneRem = true;
     603             : 
     604             :     void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
     605             :     void addDRTypeForNEON(MVT VT);
     606             :     void addQRTypeForNEON(MVT VT);
     607             :     std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
     608             : 
     609             :     using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
     610             : 
     611             :     void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
     612             :                           SDValue &Arg, RegsToPassVector &RegsToPass,
     613             :                           CCValAssign &VA, CCValAssign &NextVA,
     614             :                           SDValue &StackPtr,
     615             :                           SmallVectorImpl<SDValue> &MemOpChains,
     616             :                           ISD::ArgFlagsTy Flags) const;
     617             :     SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
     618             :                                  SDValue &Root, SelectionDAG &DAG,
     619             :                                  const SDLoc &dl) const;
     620             : 
     621             :     CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
     622             :                                             bool isVarArg) const;
     623             :     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
     624             :                                   bool isVarArg) const;
     625             :     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
     626             :                              const SDLoc &dl, SelectionDAG &DAG,
     627             :                              const CCValAssign &VA,
     628             :                              ISD::ArgFlagsTy Flags) const;
     629             :     SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
     630             :     SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
     631             :     SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
     632             :     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
     633             :                                     const ARMSubtarget *Subtarget) const;
     634             :     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
     635             :     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
     636             :     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
     637             :     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
     638             :     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
     639             :     SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
     640             :     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
     641             :     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
     642             :                                             SelectionDAG &DAG) const;
     643             :     SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
     644             :                                  SelectionDAG &DAG,
     645             :                                  TLSModel::Model model) const;
     646             :     SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
     647             :     SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
     648             :     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
     649             :     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
     650             :     SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
     651             :     SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
     652             :     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
     653             :     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
     654             :     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
     655             :     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
     656             :     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
     657             :     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
     658             :     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     659             :     SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
     660             :     SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
     661             :     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
     662             :     SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
     663             :                             const ARMSubtarget *ST) const;
     664             :     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
     665             :                               const ARMSubtarget *ST) const;
     666             :     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
     667             :     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
     668             :     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
     669             :     void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
     670             :                            SmallVectorImpl<SDValue> &Results) const;
     671             :     SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
     672             :                                    SDValue &Chain) const;
     673             :     SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
     674             :     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     675             :     SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
     676             :     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
     677             :     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
     678             :     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
     679             : 
     680             :     unsigned getRegisterByName(const char* RegName, EVT VT,
     681             :                                SelectionDAG &DAG) const override;
     682             : 
     683             :     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
     684             :     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
     685             :     /// expanded to FMAs when this method returns true, otherwise fmuladd is
     686             :     /// expanded to fmul + fadd.
     687             :     ///
     688             :     /// ARM supports both fused and unfused multiply-add operations; we already
     689             :     /// lower a pair of fmul and fadd to the latter so it's not clear that there
     690             :     /// would be a gain or that the gain would be worthwhile enough to risk
     691             :     /// correctness bugs.
     692        4366 :     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
     693             : 
     694             :     SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
     695             : 
     696             :     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
     697             :                             CallingConv::ID CallConv, bool isVarArg,
     698             :                             const SmallVectorImpl<ISD::InputArg> &Ins,
     699             :                             const SDLoc &dl, SelectionDAG &DAG,
     700             :                             SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
     701             :                             SDValue ThisVal) const;
     702             : 
     703       12648 :     bool supportSplitCSR(MachineFunction *MF) const override {
     704       25331 :       return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
     705       12648 :           MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
     706             :     }
     707             : 
     708             :     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
     709             :     void insertCopiesSplitCSR(
     710             :       MachineBasicBlock *Entry,
     711             :       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
     712             : 
     713             :     SDValue
     714             :     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     715             :                          const SmallVectorImpl<ISD::InputArg> &Ins,
     716             :                          const SDLoc &dl, SelectionDAG &DAG,
     717             :                          SmallVectorImpl<SDValue> &InVals) const override;
     718             : 
     719             :     int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
     720             :                        SDValue &Chain, const Value *OrigArg,
     721             :                        unsigned InRegsParamRecordIdx, int ArgOffset,
     722             :                        unsigned ArgSize) const;
     723             : 
     724             :     void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
     725             :                               const SDLoc &dl, SDValue &Chain,
     726             :                               unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
     727             :                               bool ForceMutable = false) const;
     728             : 
     729             :     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
     730             :                       SmallVectorImpl<SDValue> &InVals) const override;
     731             : 
     732             :     /// HandleByVal - Target-specific cleanup for ByVal support.
     733             :     void HandleByVal(CCState *, unsigned &, unsigned) const override;
     734             : 
     735             :     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
     736             :     /// for tail call optimization. Targets which want to do tail call
     737             :     /// optimization should implement this function.
     738             :     bool IsEligibleForTailCallOptimization(SDValue Callee,
     739             :                                            CallingConv::ID CalleeCC,
     740             :                                            bool isVarArg,
     741             :                                            bool isCalleeStructRet,
     742             :                                            bool isCallerStructRet,
     743             :                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
     744             :                                     const SmallVectorImpl<SDValue> &OutVals,
     745             :                                     const SmallVectorImpl<ISD::InputArg> &Ins,
     746             :                                            SelectionDAG& DAG) const;
     747             : 
     748             :     bool CanLowerReturn(CallingConv::ID CallConv,
     749             :                         MachineFunction &MF, bool isVarArg,
     750             :                         const SmallVectorImpl<ISD::OutputArg> &Outs,
     751             :                         LLVMContext &Context) const override;
     752             : 
     753             :     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     754             :                         const SmallVectorImpl<ISD::OutputArg> &Outs,
     755             :                         const SmallVectorImpl<SDValue> &OutVals,
     756             :                         const SDLoc &dl, SelectionDAG &DAG) const override;
     757             : 
     758             :     bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
     759             : 
     760             :     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
     761             : 
     762             :     SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
     763             :                     SDValue ARMcc, SDValue CCR, SDValue Cmp,
     764             :                     SelectionDAG &DAG) const;
     765             :     SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
     766             :                       SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
     767             :     SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
     768             :                       const SDLoc &dl, bool InvalidOnQNaN) const;
     769             :     SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
     770             : 
     771             :     SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
     772             : 
     773             :     void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
     774             :                                 MachineBasicBlock *DispatchBB, int FI) const;
     775             : 
     776             :     void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
     777             : 
     778             :     bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
     779             : 
     780             :     MachineBasicBlock *EmitStructByval(MachineInstr &MI,
     781             :                                        MachineBasicBlock *MBB) const;
     782             : 
     783             :     MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
     784             :                                            MachineBasicBlock *MBB) const;
     785             :     MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
     786             :                                            MachineBasicBlock *MBB) const;
     787             :   };
     788             : 
     789             :   enum NEONModImmType {
     790             :     VMOVModImm,
     791             :     VMVNModImm,
     792             :     OtherModImm
     793             :   };
     794             : 
     795             :   namespace ARM {
     796             : 
     797             :     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
     798             :                              const TargetLibraryInfo *libInfo);
     799             : 
     800             :   } // end namespace ARM
     801             : 
     802             : } // end namespace llvm
     803             : 
     804             : #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H

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