Line data Source code
1 : //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file defines the interfaces that ARM uses to lower LLVM code into a
11 : // selection DAG.
12 : //
13 : //===----------------------------------------------------------------------===//
14 :
15 : #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 : #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
17 :
18 : #include "MCTargetDesc/ARMBaseInfo.h"
19 : #include "llvm/ADT/SmallVector.h"
20 : #include "llvm/ADT/StringRef.h"
21 : #include "llvm/CodeGen/CallingConvLower.h"
22 : #include "llvm/CodeGen/ISDOpcodes.h"
23 : #include "llvm/CodeGen/MachineFunction.h"
24 : #include "llvm/CodeGen/SelectionDAGNodes.h"
25 : #include "llvm/CodeGen/TargetLowering.h"
26 : #include "llvm/CodeGen/ValueTypes.h"
27 : #include "llvm/IR/Attributes.h"
28 : #include "llvm/IR/CallingConv.h"
29 : #include "llvm/IR/Function.h"
30 : #include "llvm/IR/IRBuilder.h"
31 : #include "llvm/IR/InlineAsm.h"
32 : #include "llvm/Support/CodeGen.h"
33 : #include "llvm/Support/MachineValueType.h"
34 : #include <utility>
35 :
36 : namespace llvm {
37 :
38 : class ARMSubtarget;
39 : class DataLayout;
40 : class FastISel;
41 : class FunctionLoweringInfo;
42 : class GlobalValue;
43 : class InstrItineraryData;
44 : class Instruction;
45 : class MachineBasicBlock;
46 : class MachineInstr;
47 : class SelectionDAG;
48 : class TargetLibraryInfo;
49 : class TargetMachine;
50 : class TargetRegisterInfo;
51 : class VectorType;
52 :
53 : namespace ARMISD {
54 :
55 : // ARM Specific DAG Nodes
56 : enum NodeType : unsigned {
57 : // Start the numbering where the builtin ops and target ops leave off.
58 : FIRST_NUMBER = ISD::BUILTIN_OP_END,
59 :
60 : Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
61 : // TargetExternalSymbol, and TargetGlobalAddress.
62 : WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
63 : // PIC mode.
64 : WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
65 :
66 : // Add pseudo op to model memcpy for struct byval.
67 : COPY_STRUCT_BYVAL,
68 :
69 : CALL, // Function call.
70 : CALL_PRED, // Function call that's predicable.
71 : CALL_NOLINK, // Function call with branch not branch-and-link.
72 : BRCOND, // Conditional branch.
73 : BR_JT, // Jumptable branch.
74 : BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
75 : RET_FLAG, // Return with a flag operand.
76 : INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
77 :
78 : PIC_ADD, // Add with a PC operand and a PIC label.
79 :
80 : CMP, // ARM compare instructions.
81 : CMN, // ARM CMN instructions.
82 : CMPZ, // ARM compare that sets only Z flag.
83 : CMPFP, // ARM VFP compare instruction, sets FPSCR.
84 : CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
85 : FMSTAT, // ARM fmstat instruction.
86 :
87 : CMOV, // ARM conditional move instructions.
88 :
89 : SSAT, // Signed saturation
90 : USAT, // Unsigned saturation
91 :
92 : BCC_i64,
93 :
94 : SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
95 : SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
96 : RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
97 :
98 : ADDC, // Add with carry
99 : ADDE, // Add using carry
100 : SUBC, // Sub with carry
101 : SUBE, // Sub using carry
102 :
103 : VMOVRRD, // double to two gprs.
104 : VMOVDRR, // Two gprs to double.
105 : VMOVSR, // move gpr to single, used for f32 literal constructed in a gpr
106 :
107 : EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
108 : EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
109 : EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
110 :
111 : TC_RETURN, // Tail call return pseudo.
112 :
113 : THREAD_POINTER,
114 :
115 : DYN_ALLOC, // Dynamic allocation on the stack.
116 :
117 : MEMBARRIER_MCR, // Memory barrier (MCR)
118 :
119 : PRELOAD, // Preload
120 :
121 : WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
122 : WIN__DBZCHK, // Windows' divide by zero check
123 :
124 : VCEQ, // Vector compare equal.
125 : VCEQZ, // Vector compare equal to zero.
126 : VCGE, // Vector compare greater than or equal.
127 : VCGEZ, // Vector compare greater than or equal to zero.
128 : VCLEZ, // Vector compare less than or equal to zero.
129 : VCGEU, // Vector compare unsigned greater than or equal.
130 : VCGT, // Vector compare greater than.
131 : VCGTZ, // Vector compare greater than zero.
132 : VCLTZ, // Vector compare less than zero.
133 : VCGTU, // Vector compare unsigned greater than.
134 : VTST, // Vector test bits.
135 :
136 : // Vector shift by immediate:
137 : VSHL, // ...left
138 : VSHRs, // ...right (signed)
139 : VSHRu, // ...right (unsigned)
140 :
141 : // Vector rounding shift by immediate:
142 : VRSHRs, // ...right (signed)
143 : VRSHRu, // ...right (unsigned)
144 : VRSHRN, // ...right narrow
145 :
146 : // Vector saturating shift by immediate:
147 : VQSHLs, // ...left (signed)
148 : VQSHLu, // ...left (unsigned)
149 : VQSHLsu, // ...left (signed to unsigned)
150 : VQSHRNs, // ...right narrow (signed)
151 : VQSHRNu, // ...right narrow (unsigned)
152 : VQSHRNsu, // ...right narrow (signed to unsigned)
153 :
154 : // Vector saturating rounding shift by immediate:
155 : VQRSHRNs, // ...right narrow (signed)
156 : VQRSHRNu, // ...right narrow (unsigned)
157 : VQRSHRNsu, // ...right narrow (signed to unsigned)
158 :
159 : // Vector shift and insert:
160 : VSLI, // ...left
161 : VSRI, // ...right
162 :
163 : // Vector get lane (VMOV scalar to ARM core register)
164 : // (These are used for 8- and 16-bit element types only.)
165 : VGETLANEu, // zero-extend vector extract element
166 : VGETLANEs, // sign-extend vector extract element
167 :
168 : // Vector move immediate and move negated immediate:
169 : VMOVIMM,
170 : VMVNIMM,
171 :
172 : // Vector move f32 immediate:
173 : VMOVFPIMM,
174 :
175 : // Move H <-> R, clearing top 16 bits
176 : VMOVrh,
177 : VMOVhr,
178 :
179 : // Vector duplicate:
180 : VDUP,
181 : VDUPLANE,
182 :
183 : // Vector shuffles:
184 : VEXT, // extract
185 : VREV64, // reverse elements within 64-bit doublewords
186 : VREV32, // reverse elements within 32-bit words
187 : VREV16, // reverse elements within 16-bit halfwords
188 : VZIP, // zip (interleave)
189 : VUZP, // unzip (deinterleave)
190 : VTRN, // transpose
191 : VTBL1, // 1-register shuffle with mask
192 : VTBL2, // 2-register shuffle with mask
193 :
194 : // Vector multiply long:
195 : VMULLs, // ...signed
196 : VMULLu, // ...unsigned
197 :
198 : SMULWB, // Signed multiply word by half word, bottom
199 : SMULWT, // Signed multiply word by half word, top
200 : UMLAL, // 64bit Unsigned Accumulate Multiply
201 : SMLAL, // 64bit Signed Accumulate Multiply
202 : UMAAL, // 64-bit Unsigned Accumulate Accumulate Multiply
203 : SMLALBB, // 64-bit signed accumulate multiply bottom, bottom 16
204 : SMLALBT, // 64-bit signed accumulate multiply bottom, top 16
205 : SMLALTB, // 64-bit signed accumulate multiply top, bottom 16
206 : SMLALTT, // 64-bit signed accumulate multiply top, top 16
207 : SMLALD, // Signed multiply accumulate long dual
208 : SMLALDX, // Signed multiply accumulate long dual exchange
209 : SMLSLD, // Signed multiply subtract long dual
210 : SMLSLDX, // Signed multiply subtract long dual exchange
211 : SMMLAR, // Signed multiply long, round and add
212 : SMMLSR, // Signed multiply long, subtract and round
213 :
214 : // Operands of the standard BUILD_VECTOR node are not legalized, which
215 : // is fine if BUILD_VECTORs are always lowered to shuffles or other
216 : // operations, but for ARM some BUILD_VECTORs are legal as-is and their
217 : // operands need to be legalized. Define an ARM-specific version of
218 : // BUILD_VECTOR for this purpose.
219 : BUILD_VECTOR,
220 :
221 : // Bit-field insert
222 : BFI,
223 :
224 : // Vector OR with immediate
225 : VORRIMM,
226 : // Vector AND with NOT of immediate
227 : VBICIMM,
228 :
229 : // Vector bitwise select
230 : VBSL,
231 :
232 : // Pseudo-instruction representing a memory copy using ldm/stm
233 : // instructions.
234 : MEMCPY,
235 :
236 : // Vector load N-element structure to all lanes:
237 : VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
238 : VLD2DUP,
239 : VLD3DUP,
240 : VLD4DUP,
241 :
242 : // NEON loads with post-increment base updates:
243 : VLD1_UPD,
244 : VLD2_UPD,
245 : VLD3_UPD,
246 : VLD4_UPD,
247 : VLD2LN_UPD,
248 : VLD3LN_UPD,
249 : VLD4LN_UPD,
250 : VLD1DUP_UPD,
251 : VLD2DUP_UPD,
252 : VLD3DUP_UPD,
253 : VLD4DUP_UPD,
254 :
255 : // NEON stores with post-increment base updates:
256 : VST1_UPD,
257 : VST2_UPD,
258 : VST3_UPD,
259 : VST4_UPD,
260 : VST2LN_UPD,
261 : VST3LN_UPD,
262 : VST4LN_UPD
263 : };
264 :
265 : } // end namespace ARMISD
266 :
267 : /// Define some predicates that are used for node matching.
268 : namespace ARM {
269 :
270 : bool isBitFieldInvertedMask(unsigned v);
271 :
272 : } // end namespace ARM
273 :
274 : //===--------------------------------------------------------------------===//
275 : // ARMTargetLowering - ARM Implementation of the TargetLowering interface
276 :
277 : class ARMTargetLowering : public TargetLowering {
278 : public:
279 : explicit ARMTargetLowering(const TargetMachine &TM,
280 : const ARMSubtarget &STI);
281 :
282 : unsigned getJumpTableEncoding() const override;
283 : bool useSoftFloat() const override;
284 :
285 : SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
286 :
287 : /// ReplaceNodeResults - Replace the results of node with an illegal result
288 : /// type with new values built out of custom code.
289 : void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
290 : SelectionDAG &DAG) const override;
291 :
292 : const char *getTargetNodeName(unsigned Opcode) const override;
293 :
294 1592 : bool isSelectSupported(SelectSupportKind Kind) const override {
295 : // ARM does not support scalar condition selects on vectors.
296 1592 : return (Kind != ScalarCondVectorVal);
297 : }
298 :
299 : bool isReadOnly(const GlobalValue *GV) const;
300 :
301 : /// getSetCCResultType - Return the value type to use for ISD::SETCC.
302 : EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
303 : EVT VT) const override;
304 :
305 : MachineBasicBlock *
306 : EmitInstrWithCustomInserter(MachineInstr &MI,
307 : MachineBasicBlock *MBB) const override;
308 :
309 : void AdjustInstrPostInstrSelection(MachineInstr &MI,
310 : SDNode *Node) const override;
311 :
312 : SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
313 : SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
314 : SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
315 : SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
316 :
317 : bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
318 :
319 : /// allowsMisalignedMemoryAccesses - Returns true if the target allows
320 : /// unaligned memory accesses of the specified type. Returns whether it
321 : /// is "fast" by reference in the second argument.
322 : bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
323 : unsigned Align,
324 : bool *Fast) const override;
325 :
326 : EVT getOptimalMemOpType(uint64_t Size,
327 : unsigned DstAlign, unsigned SrcAlign,
328 : bool IsMemset, bool ZeroMemset,
329 : bool MemcpyStrSrc,
330 : MachineFunction &MF) const override;
331 :
332 : bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
333 : bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
334 : bool isZExtFree(SDValue Val, EVT VT2) const override;
335 : bool isFNegFree(EVT VT) const override;
336 :
337 : bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
338 :
339 : bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
340 :
341 :
342 : /// isLegalAddressingMode - Return true if the addressing mode represented
343 : /// by AM is legal for this target, for a load/store of the specified type.
344 : bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
345 : Type *Ty, unsigned AS,
346 : Instruction *I = nullptr) const override;
347 :
348 : /// getScalingFactorCost - Return the cost of the scaling used in
349 : /// addressing mode represented by AM.
350 : /// If the AM is supported, the return value must be >= 0.
351 : /// If the AM is not supported, the return value must be negative.
352 : int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
353 : unsigned AS) const override;
354 :
355 : bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
356 :
357 : /// Returns true if the addresing mode representing by AM is legal
358 : /// for the Thumb1 target, for a load/store of the specified type.
359 : bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
360 :
361 : /// isLegalICmpImmediate - Return true if the specified immediate is legal
362 : /// icmp immediate, that is the target has icmp instructions which can
363 : /// compare a register against the immediate without having to materialize
364 : /// the immediate into a register.
365 : bool isLegalICmpImmediate(int64_t Imm) const override;
366 :
367 : /// isLegalAddImmediate - Return true if the specified immediate is legal
368 : /// add immediate, that is the target has add instructions which can
369 : /// add a register and the immediate without having to materialize
370 : /// the immediate into a register.
371 : bool isLegalAddImmediate(int64_t Imm) const override;
372 :
373 : /// getPreIndexedAddressParts - returns true by value, base pointer and
374 : /// offset pointer and addressing mode by reference if the node's address
375 : /// can be legally represented as pre-indexed load / store address.
376 : bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
377 : ISD::MemIndexedMode &AM,
378 : SelectionDAG &DAG) const override;
379 :
380 : /// getPostIndexedAddressParts - returns true by value, base pointer and
381 : /// offset pointer and addressing mode by reference if this node can be
382 : /// combined with a load / store to form a post-indexed load / store.
383 : bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
384 : SDValue &Offset, ISD::MemIndexedMode &AM,
385 : SelectionDAG &DAG) const override;
386 :
387 : void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
388 : const APInt &DemandedElts,
389 : const SelectionDAG &DAG,
390 : unsigned Depth) const override;
391 :
392 : bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
393 : TargetLoweringOpt &TLO) const override;
394 :
395 :
396 : bool ExpandInlineAsm(CallInst *CI) const override;
397 :
398 : ConstraintType getConstraintType(StringRef Constraint) const override;
399 :
400 : /// Examine constraint string and operand type and determine a weight value.
401 : /// The operand object must already have been set up with the operand type.
402 : ConstraintWeight getSingleConstraintMatchWeight(
403 : AsmOperandInfo &info, const char *constraint) const override;
404 :
405 : std::pair<unsigned, const TargetRegisterClass *>
406 : getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
407 : StringRef Constraint, MVT VT) const override;
408 :
409 : const char *LowerXConstraint(EVT ConstraintVT) const override;
410 :
411 : /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
412 : /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
413 : /// true it means one of the asm constraint of the inline asm instruction
414 : /// being processed is 'm'.
415 : void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
416 : std::vector<SDValue> &Ops,
417 : SelectionDAG &DAG) const override;
418 :
419 : unsigned
420 25 : getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
421 : if (ConstraintCode == "Q")
422 : return InlineAsm::Constraint_Q;
423 : else if (ConstraintCode == "o")
424 : return InlineAsm::Constraint_o;
425 17 : else if (ConstraintCode.size() == 2) {
426 2 : if (ConstraintCode[0] == 'U') {
427 2 : switch(ConstraintCode[1]) {
428 : default:
429 : break;
430 : case 'm':
431 : return InlineAsm::Constraint_Um;
432 0 : case 'n':
433 0 : return InlineAsm::Constraint_Un;
434 0 : case 'q':
435 0 : return InlineAsm::Constraint_Uq;
436 0 : case 's':
437 0 : return InlineAsm::Constraint_Us;
438 0 : case 't':
439 0 : return InlineAsm::Constraint_Ut;
440 2 : case 'v':
441 2 : return InlineAsm::Constraint_Uv;
442 0 : case 'y':
443 0 : return InlineAsm::Constraint_Uy;
444 : }
445 : }
446 : }
447 : return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
448 : }
449 :
450 0 : const ARMSubtarget* getSubtarget() const {
451 0 : return Subtarget;
452 : }
453 :
454 : /// getRegClassFor - Return the register class that should be used for the
455 : /// specified value type.
456 : const TargetRegisterClass *getRegClassFor(MVT VT) const override;
457 :
458 : /// Returns true if a cast between SrcAS and DestAS is a noop.
459 2 : bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
460 : // Addrspacecasts are always noops.
461 2 : return true;
462 : }
463 :
464 : bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
465 : unsigned &PrefAlign) const override;
466 :
467 : /// createFastISel - This method returns a target specific FastISel object,
468 : /// or null if the target does not support "fast" ISel.
469 : FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
470 : const TargetLibraryInfo *libInfo) const override;
471 :
472 : Sched::Preference getSchedulingPreference(SDNode *N) const override;
473 :
474 : bool
475 : isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
476 : bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
477 :
478 : /// isFPImmLegal - Returns true if the target can instruction select the
479 : /// specified FP immediate natively. If false, the legalizer will
480 : /// materialize the FP immediate as a load from a constant pool.
481 : bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
482 :
483 : bool getTgtMemIntrinsic(IntrinsicInfo &Info,
484 : const CallInst &I,
485 : MachineFunction &MF,
486 : unsigned Intrinsic) const override;
487 :
488 : /// Returns true if it is beneficial to convert a load of a constant
489 : /// to just the constant itself.
490 : bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
491 : Type *Ty) const override;
492 :
493 : /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
494 : /// with this index.
495 : bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
496 : unsigned Index) const override;
497 :
498 : /// Returns true if an argument of type Ty needs to be passed in a
499 : /// contiguous block of registers in calling convention CallConv.
500 : bool functionArgumentNeedsConsecutiveRegisters(
501 : Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
502 :
503 : /// If a physical register, this returns the register that receives the
504 : /// exception address on entry to an EH pad.
505 : unsigned
506 : getExceptionPointerRegister(const Constant *PersonalityFn) const override;
507 :
508 : /// If a physical register, this returns the register that receives the
509 : /// exception typeid on entry to a landing pad.
510 : unsigned
511 : getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
512 :
513 : Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
514 : Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
515 : AtomicOrdering Ord) const override;
516 : Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
517 : Value *Addr, AtomicOrdering Ord) const override;
518 :
519 : void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
520 :
521 : Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
522 : AtomicOrdering Ord) const override;
523 : Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
524 : AtomicOrdering Ord) const override;
525 :
526 13557 : unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
527 :
528 : bool lowerInterleavedLoad(LoadInst *LI,
529 : ArrayRef<ShuffleVectorInst *> Shuffles,
530 : ArrayRef<unsigned> Indices,
531 : unsigned Factor) const override;
532 : bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
533 : unsigned Factor) const override;
534 :
535 : bool shouldInsertFencesForAtomic(const Instruction *I) const override;
536 : TargetLoweringBase::AtomicExpansionKind
537 : shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
538 : bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
539 : TargetLoweringBase::AtomicExpansionKind
540 : shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
541 : TargetLoweringBase::AtomicExpansionKind
542 : shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
543 :
544 : bool useLoadStackGuardNode() const override;
545 :
546 : bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
547 : unsigned &Cost) const override;
548 :
549 2812 : bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
550 : const SelectionDAG &DAG) const override {
551 : // Do not merge to larger than i32.
552 2812 : return (MemVT.getSizeInBits() <= 32);
553 : }
554 :
555 : bool isCheapToSpeculateCttz() const override;
556 : bool isCheapToSpeculateCtlz() const override;
557 :
558 64 : bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
559 64 : return VT.isScalarInteger();
560 : }
561 :
562 321115 : bool supportSwiftError() const override {
563 321115 : return true;
564 : }
565 :
566 32 : bool hasStandaloneRem(EVT VT) const override {
567 32 : return HasStandaloneRem;
568 : }
569 :
570 : CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
571 : CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
572 :
573 : /// Returns true if \p VecTy is a legal interleaved access type. This
574 : /// function checks the vector element type and the overall width of the
575 : /// vector.
576 : bool isLegalInterleavedAccessType(VectorType *VecTy,
577 : const DataLayout &DL) const;
578 :
579 : bool alignLoopsWithOptSize() const override;
580 :
581 : /// Returns the number of interleaved accesses that will be generated when
582 : /// lowering accesses of the given type.
583 : unsigned getNumInterleavedAccesses(VectorType *VecTy,
584 : const DataLayout &DL) const;
585 :
586 : void finalizeLowering(MachineFunction &MF) const override;
587 :
588 : /// Return the correct alignment for the current calling convention.
589 : unsigned getABIAlignmentForCallingConv(Type *ArgTy,
590 : DataLayout DL) const override;
591 :
592 : bool isDesirableToCommuteWithShift(const SDNode *N,
593 : CombineLevel Level) const override;
594 :
595 : protected:
596 : std::pair<const TargetRegisterClass *, uint8_t>
597 : findRepresentativeClass(const TargetRegisterInfo *TRI,
598 : MVT VT) const override;
599 :
600 : private:
601 : /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
602 : /// make the right decision when generating code for different targets.
603 : const ARMSubtarget *Subtarget;
604 :
605 : const TargetRegisterInfo *RegInfo;
606 :
607 : const InstrItineraryData *Itins;
608 :
609 : /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
610 : unsigned ARMPCLabelIndex;
611 :
612 : // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
613 : // check.
614 : bool InsertFencesForAtomic;
615 :
616 : bool HasStandaloneRem = true;
617 :
618 : void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
619 : void addDRTypeForNEON(MVT VT);
620 : void addQRTypeForNEON(MVT VT);
621 : std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
622 :
623 : using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
624 :
625 : void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
626 : SDValue &Arg, RegsToPassVector &RegsToPass,
627 : CCValAssign &VA, CCValAssign &NextVA,
628 : SDValue &StackPtr,
629 : SmallVectorImpl<SDValue> &MemOpChains,
630 : ISD::ArgFlagsTy Flags) const;
631 : SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
632 : SDValue &Root, SelectionDAG &DAG,
633 : const SDLoc &dl) const;
634 :
635 : CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
636 : bool isVarArg) const;
637 : CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
638 : bool isVarArg) const;
639 : SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
640 : const SDLoc &dl, SelectionDAG &DAG,
641 : const CCValAssign &VA,
642 : ISD::ArgFlagsTy Flags) const;
643 : SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
644 : SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
645 : SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
646 : SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
647 : const ARMSubtarget *Subtarget) const;
648 : SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
649 : SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
650 : SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
651 : SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
652 : SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
653 : SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
654 : SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
655 : SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
656 : SelectionDAG &DAG) const;
657 : SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
658 : SelectionDAG &DAG,
659 : TLSModel::Model model) const;
660 : SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
661 : SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
662 : SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
663 : SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
664 : SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
665 : SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
666 : SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
667 : SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
668 : SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
669 : SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
670 : SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
671 : SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
672 : SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
673 : SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
674 : SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
675 : SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
676 : SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
677 : const ARMSubtarget *ST) const;
678 : SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
679 : const ARMSubtarget *ST) const;
680 : SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
681 : SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
682 : SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
683 : void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
684 : SmallVectorImpl<SDValue> &Results) const;
685 : SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
686 : SDValue &Chain) const;
687 : SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
688 : SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
689 : SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
690 : SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
691 : SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
692 : SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
693 :
694 : unsigned getRegisterByName(const char* RegName, EVT VT,
695 : SelectionDAG &DAG) const override;
696 :
697 : /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
698 : /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
699 : /// expanded to FMAs when this method returns true, otherwise fmuladd is
700 : /// expanded to fmul + fadd.
701 : ///
702 : /// ARM supports both fused and unfused multiply-add operations; we already
703 : /// lower a pair of fmul and fadd to the latter so it's not clear that there
704 : /// would be a gain or that the gain would be worthwhile enough to risk
705 : /// correctness bugs.
706 4128 : bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
707 :
708 : SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
709 :
710 : SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
711 : CallingConv::ID CallConv, bool isVarArg,
712 : const SmallVectorImpl<ISD::InputArg> &Ins,
713 : const SDLoc &dl, SelectionDAG &DAG,
714 : SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
715 : SDValue ThisVal) const;
716 :
717 14099 : bool supportSplitCSR(MachineFunction *MF) const override {
718 28233 : return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
719 14099 : MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
720 : }
721 :
722 : void initializeSplitCSR(MachineBasicBlock *Entry) const override;
723 : void insertCopiesSplitCSR(
724 : MachineBasicBlock *Entry,
725 : const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
726 :
727 : SDValue
728 : LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
729 : const SmallVectorImpl<ISD::InputArg> &Ins,
730 : const SDLoc &dl, SelectionDAG &DAG,
731 : SmallVectorImpl<SDValue> &InVals) const override;
732 :
733 : int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
734 : SDValue &Chain, const Value *OrigArg,
735 : unsigned InRegsParamRecordIdx, int ArgOffset,
736 : unsigned ArgSize) const;
737 :
738 : void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
739 : const SDLoc &dl, SDValue &Chain,
740 : unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
741 : bool ForceMutable = false) const;
742 :
743 : SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
744 : SmallVectorImpl<SDValue> &InVals) const override;
745 :
746 : /// HandleByVal - Target-specific cleanup for ByVal support.
747 : void HandleByVal(CCState *, unsigned &, unsigned) const override;
748 :
749 : /// IsEligibleForTailCallOptimization - Check whether the call is eligible
750 : /// for tail call optimization. Targets which want to do tail call
751 : /// optimization should implement this function.
752 : bool IsEligibleForTailCallOptimization(SDValue Callee,
753 : CallingConv::ID CalleeCC,
754 : bool isVarArg,
755 : bool isCalleeStructRet,
756 : bool isCallerStructRet,
757 : const SmallVectorImpl<ISD::OutputArg> &Outs,
758 : const SmallVectorImpl<SDValue> &OutVals,
759 : const SmallVectorImpl<ISD::InputArg> &Ins,
760 : SelectionDAG& DAG) const;
761 :
762 : bool CanLowerReturn(CallingConv::ID CallConv,
763 : MachineFunction &MF, bool isVarArg,
764 : const SmallVectorImpl<ISD::OutputArg> &Outs,
765 : LLVMContext &Context) const override;
766 :
767 : SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
768 : const SmallVectorImpl<ISD::OutputArg> &Outs,
769 : const SmallVectorImpl<SDValue> &OutVals,
770 : const SDLoc &dl, SelectionDAG &DAG) const override;
771 :
772 : bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
773 :
774 : bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
775 :
776 218 : bool shouldConsiderGEPOffsetSplit() const override { return true; }
777 :
778 : SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
779 : SDValue ARMcc, SDValue CCR, SDValue Cmp,
780 : SelectionDAG &DAG) const;
781 : SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
782 : SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
783 : SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
784 : const SDLoc &dl, bool InvalidOnQNaN) const;
785 : SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
786 :
787 : SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
788 :
789 : void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
790 : MachineBasicBlock *DispatchBB, int FI) const;
791 :
792 : void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
793 :
794 : bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
795 :
796 : MachineBasicBlock *EmitStructByval(MachineInstr &MI,
797 : MachineBasicBlock *MBB) const;
798 :
799 : MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
800 : MachineBasicBlock *MBB) const;
801 : MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
802 : MachineBasicBlock *MBB) const;
803 : };
804 :
805 : enum NEONModImmType {
806 : VMOVModImm,
807 : VMVNModImm,
808 : OtherModImm
809 : };
810 :
811 : namespace ARM {
812 :
813 : FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
814 : const TargetLibraryInfo *libInfo);
815 :
816 : } // end namespace ARM
817 :
818 : } // end namespace llvm
819 :
820 : #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
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