LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMISelLowering.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 27 37 73.0 %
Date: 2017-09-14 15:23:50 Functions: 10 12 83.3 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file defines the interfaces that ARM uses to lower LLVM code into a
      11             : // selection DAG.
      12             : //
      13             : //===----------------------------------------------------------------------===//
      14             : 
      15             : #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
      16             : #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
      17             : 
      18             : #include "MCTargetDesc/ARMBaseInfo.h"
      19             : #include "llvm/ADT/SmallVector.h"
      20             : #include "llvm/ADT/StringRef.h"
      21             : #include "llvm/CodeGen/CallingConvLower.h"
      22             : #include "llvm/CodeGen/MachineFunction.h"
      23             : #include "llvm/CodeGen/MachineValueType.h"
      24             : #include "llvm/CodeGen/SelectionDAG.h"
      25             : #include "llvm/CodeGen/SelectionDAGNodes.h"
      26             : #include "llvm/CodeGen/ValueTypes.h"
      27             : #include "llvm/IR/CallingConv.h"
      28             : #include "llvm/IR/IRBuilder.h"
      29             : #include "llvm/IR/InlineAsm.h"
      30             : #include "llvm/Support/CodeGen.h"
      31             : #include "llvm/Target/TargetLowering.h"
      32             : #include <utility>
      33             : 
      34             : namespace llvm {
      35             : 
      36             : class ARMSubtarget;
      37             : class InstrItineraryData;
      38             : 
      39             :   namespace ARMISD {
      40             : 
      41             :     // ARM Specific DAG Nodes
      42             :     enum NodeType : unsigned {
      43             :       // Start the numbering where the builtin ops and target ops leave off.
      44             :       FIRST_NUMBER = ISD::BUILTIN_OP_END,
      45             : 
      46             :       Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
      47             :                     // TargetExternalSymbol, and TargetGlobalAddress.
      48             :       WrapperPIC,   // WrapperPIC - A wrapper node for TargetGlobalAddress in
      49             :                     // PIC mode.
      50             :       WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
      51             : 
      52             :       // Add pseudo op to model memcpy for struct byval.
      53             :       COPY_STRUCT_BYVAL,
      54             : 
      55             :       CALL,         // Function call.
      56             :       CALL_PRED,    // Function call that's predicable.
      57             :       CALL_NOLINK,  // Function call with branch not branch-and-link.
      58             :       BRCOND,       // Conditional branch.
      59             :       BR_JT,        // Jumptable branch.
      60             :       BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
      61             :       RET_FLAG,     // Return with a flag operand.
      62             :       INTRET_FLAG,  // Interrupt return with an LR-offset and a flag operand.
      63             : 
      64             :       PIC_ADD,      // Add with a PC operand and a PIC label.
      65             : 
      66             :       CMP,          // ARM compare instructions.
      67             :       CMN,          // ARM CMN instructions.
      68             :       CMPZ,         // ARM compare that sets only Z flag.
      69             :       CMPFP,        // ARM VFP compare instruction, sets FPSCR.
      70             :       CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
      71             :       FMSTAT,       // ARM fmstat instruction.
      72             : 
      73             :       CMOV,         // ARM conditional move instructions.
      74             : 
      75             :       SSAT,         // Signed saturation
      76             : 
      77             :       BCC_i64,
      78             : 
      79             :       SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
      80             :       SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
      81             :       RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
      82             : 
      83             :       ADDC,         // Add with carry
      84             :       ADDE,         // Add using carry
      85             :       SUBC,         // Sub with carry
      86             :       SUBE,         // Sub using carry
      87             : 
      88             :       VMOVRRD,      // double to two gprs.
      89             :       VMOVDRR,      // Two gprs to double.
      90             : 
      91             :       EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
      92             :       EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
      93             :       EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
      94             : 
      95             :       TC_RETURN,    // Tail call return pseudo.
      96             : 
      97             :       THREAD_POINTER,
      98             : 
      99             :       DYN_ALLOC,    // Dynamic allocation on the stack.
     100             : 
     101             :       MEMBARRIER_MCR, // Memory barrier (MCR)
     102             : 
     103             :       PRELOAD,      // Preload
     104             : 
     105             :       WIN__CHKSTK,  // Windows' __chkstk call to do stack probing.
     106             :       WIN__DBZCHK,  // Windows' divide by zero check
     107             : 
     108             :       VCEQ,         // Vector compare equal.
     109             :       VCEQZ,        // Vector compare equal to zero.
     110             :       VCGE,         // Vector compare greater than or equal.
     111             :       VCGEZ,        // Vector compare greater than or equal to zero.
     112             :       VCLEZ,        // Vector compare less than or equal to zero.
     113             :       VCGEU,        // Vector compare unsigned greater than or equal.
     114             :       VCGT,         // Vector compare greater than.
     115             :       VCGTZ,        // Vector compare greater than zero.
     116             :       VCLTZ,        // Vector compare less than zero.
     117             :       VCGTU,        // Vector compare unsigned greater than.
     118             :       VTST,         // Vector test bits.
     119             : 
     120             :       // Vector shift by immediate:
     121             :       VSHL,         // ...left
     122             :       VSHRs,        // ...right (signed)
     123             :       VSHRu,        // ...right (unsigned)
     124             : 
     125             :       // Vector rounding shift by immediate:
     126             :       VRSHRs,       // ...right (signed)
     127             :       VRSHRu,       // ...right (unsigned)
     128             :       VRSHRN,       // ...right narrow
     129             : 
     130             :       // Vector saturating shift by immediate:
     131             :       VQSHLs,       // ...left (signed)
     132             :       VQSHLu,       // ...left (unsigned)
     133             :       VQSHLsu,      // ...left (signed to unsigned)
     134             :       VQSHRNs,      // ...right narrow (signed)
     135             :       VQSHRNu,      // ...right narrow (unsigned)
     136             :       VQSHRNsu,     // ...right narrow (signed to unsigned)
     137             : 
     138             :       // Vector saturating rounding shift by immediate:
     139             :       VQRSHRNs,     // ...right narrow (signed)
     140             :       VQRSHRNu,     // ...right narrow (unsigned)
     141             :       VQRSHRNsu,    // ...right narrow (signed to unsigned)
     142             : 
     143             :       // Vector shift and insert:
     144             :       VSLI,         // ...left
     145             :       VSRI,         // ...right
     146             : 
     147             :       // Vector get lane (VMOV scalar to ARM core register)
     148             :       // (These are used for 8- and 16-bit element types only.)
     149             :       VGETLANEu,    // zero-extend vector extract element
     150             :       VGETLANEs,    // sign-extend vector extract element
     151             : 
     152             :       // Vector move immediate and move negated immediate:
     153             :       VMOVIMM,
     154             :       VMVNIMM,
     155             : 
     156             :       // Vector move f32 immediate:
     157             :       VMOVFPIMM,
     158             : 
     159             :       // Vector duplicate:
     160             :       VDUP,
     161             :       VDUPLANE,
     162             : 
     163             :       // Vector shuffles:
     164             :       VEXT,         // extract
     165             :       VREV64,       // reverse elements within 64-bit doublewords
     166             :       VREV32,       // reverse elements within 32-bit words
     167             :       VREV16,       // reverse elements within 16-bit halfwords
     168             :       VZIP,         // zip (interleave)
     169             :       VUZP,         // unzip (deinterleave)
     170             :       VTRN,         // transpose
     171             :       VTBL1,        // 1-register shuffle with mask
     172             :       VTBL2,        // 2-register shuffle with mask
     173             : 
     174             :       // Vector multiply long:
     175             :       VMULLs,       // ...signed
     176             :       VMULLu,       // ...unsigned
     177             : 
     178             :       SMULWB,       // Signed multiply word by half word, bottom
     179             :       SMULWT,       // Signed multiply word by half word, top
     180             :       UMLAL,        // 64bit Unsigned Accumulate Multiply
     181             :       SMLAL,        // 64bit Signed Accumulate Multiply
     182             :       UMAAL,        // 64-bit Unsigned Accumulate Accumulate Multiply
     183             :       SMLALBB,      // 64-bit signed accumulate multiply bottom, bottom 16
     184             :       SMLALBT,      // 64-bit signed accumulate multiply bottom, top 16
     185             :       SMLALTB,      // 64-bit signed accumulate multiply top, bottom 16
     186             :       SMLALTT,      // 64-bit signed accumulate multiply top, top 16
     187             :       SMLALD,       // Signed multiply accumulate long dual
     188             :       SMLALDX,      // Signed multiply accumulate long dual exchange
     189             :       SMLSLD,       // Signed multiply subtract long dual
     190             :       SMLSLDX,      // Signed multiply subtract long dual exchange
     191             : 
     192             :       // Operands of the standard BUILD_VECTOR node are not legalized, which
     193             :       // is fine if BUILD_VECTORs are always lowered to shuffles or other
     194             :       // operations, but for ARM some BUILD_VECTORs are legal as-is and their
     195             :       // operands need to be legalized.  Define an ARM-specific version of
     196             :       // BUILD_VECTOR for this purpose.
     197             :       BUILD_VECTOR,
     198             : 
     199             :       // Bit-field insert
     200             :       BFI,
     201             : 
     202             :       // Vector OR with immediate
     203             :       VORRIMM,
     204             :       // Vector AND with NOT of immediate
     205             :       VBICIMM,
     206             : 
     207             :       // Vector bitwise select
     208             :       VBSL,
     209             : 
     210             :       // Pseudo-instruction representing a memory copy using ldm/stm
     211             :       // instructions.
     212             :       MEMCPY,
     213             : 
     214             :       // Vector load N-element structure to all lanes:
     215             :       VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
     216             :       VLD2DUP,
     217             :       VLD3DUP,
     218             :       VLD4DUP,
     219             : 
     220             :       // NEON loads with post-increment base updates:
     221             :       VLD1_UPD,
     222             :       VLD2_UPD,
     223             :       VLD3_UPD,
     224             :       VLD4_UPD,
     225             :       VLD2LN_UPD,
     226             :       VLD3LN_UPD,
     227             :       VLD4LN_UPD,
     228             :       VLD1DUP_UPD,
     229             :       VLD2DUP_UPD,
     230             :       VLD3DUP_UPD,
     231             :       VLD4DUP_UPD,
     232             : 
     233             :       // NEON stores with post-increment base updates:
     234             :       VST1_UPD,
     235             :       VST2_UPD,
     236             :       VST3_UPD,
     237             :       VST4_UPD,
     238             :       VST2LN_UPD,
     239             :       VST3LN_UPD,
     240             :       VST4LN_UPD
     241             :     };
     242             : 
     243             :   } // end namespace ARMISD
     244             : 
     245             :   /// Define some predicates that are used for node matching.
     246             :   namespace ARM {
     247             : 
     248             :     bool isBitFieldInvertedMask(unsigned v);
     249             : 
     250             :   } // end namespace ARM
     251             : 
     252             :   //===--------------------------------------------------------------------===//
     253             :   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
     254             : 
     255        8890 :   class ARMTargetLowering : public TargetLowering {
     256             :   public:
     257             :     explicit ARMTargetLowering(const TargetMachine &TM,
     258             :                                const ARMSubtarget &STI);
     259             : 
     260             :     unsigned getJumpTableEncoding() const override;
     261             :     bool useSoftFloat() const override;
     262             : 
     263             :     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     264             : 
     265             :     /// ReplaceNodeResults - Replace the results of node with an illegal result
     266             :     /// type with new values built out of custom code.
     267             :     ///
     268             :     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
     269             :                             SelectionDAG &DAG) const override;
     270             : 
     271             :     const char *getTargetNodeName(unsigned Opcode) const override;
     272             : 
     273         861 :     bool isSelectSupported(SelectSupportKind Kind) const override {
     274             :       // ARM does not support scalar condition selects on vectors.
     275         861 :       return (Kind != ScalarCondVectorVal);
     276             :     }
     277             : 
     278             :     bool isReadOnly(const GlobalValue *GV) const;
     279             : 
     280             :     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
     281             :     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
     282             :                            EVT VT) const override;
     283             : 
     284             :     MachineBasicBlock *
     285             :     EmitInstrWithCustomInserter(MachineInstr &MI,
     286             :                                 MachineBasicBlock *MBB) const override;
     287             : 
     288             :     void AdjustInstrPostInstrSelection(MachineInstr &MI,
     289             :                                        SDNode *Node) const override;
     290             : 
     291             :     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
     292             :     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
     293             :     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
     294             :     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
     295             : 
     296             :     bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
     297             : 
     298             :     /// allowsMisalignedMemoryAccesses - Returns true if the target allows
     299             :     /// unaligned memory accesses of the specified type. Returns whether it
     300             :     /// is "fast" by reference in the second argument.
     301             :     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
     302             :                                         unsigned Align,
     303             :                                         bool *Fast) const override;
     304             : 
     305             :     EVT getOptimalMemOpType(uint64_t Size,
     306             :                             unsigned DstAlign, unsigned SrcAlign,
     307             :                             bool IsMemset, bool ZeroMemset,
     308             :                             bool MemcpyStrSrc,
     309             :                             MachineFunction &MF) const override;
     310             : 
     311             :     using TargetLowering::isZExtFree;
     312             :     bool isZExtFree(SDValue Val, EVT VT2) const override;
     313             : 
     314             :     bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
     315             : 
     316             :     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
     317             : 
     318             : 
     319             :     /// isLegalAddressingMode - Return true if the addressing mode represented
     320             :     /// by AM is legal for this target, for a load/store of the specified type.
     321             :     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
     322             :                                Type *Ty, unsigned AS,
     323             :                                Instruction *I = nullptr) const override;
     324             : 
     325             :     /// getScalingFactorCost - Return the cost of the scaling used in
     326             :     /// addressing mode represented by AM.
     327             :     /// If the AM is supported, the return value must be >= 0.
     328             :     /// If the AM is not supported, the return value must be negative.
     329             :     int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
     330             :                              unsigned AS) const override;
     331             : 
     332             :     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
     333             : 
     334             :     /// \brief Returns true if the addresing mode representing by AM is legal
     335             :     /// for the Thumb1 target, for a load/store of the specified type.
     336             :     bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
     337             : 
     338             :     /// isLegalICmpImmediate - Return true if the specified immediate is legal
     339             :     /// icmp immediate, that is the target has icmp instructions which can
     340             :     /// compare a register against the immediate without having to materialize
     341             :     /// the immediate into a register.
     342             :     bool isLegalICmpImmediate(int64_t Imm) const override;
     343             : 
     344             :     /// isLegalAddImmediate - Return true if the specified immediate is legal
     345             :     /// add immediate, that is the target has add instructions which can
     346             :     /// add a register and the immediate without having to materialize
     347             :     /// the immediate into a register.
     348             :     bool isLegalAddImmediate(int64_t Imm) const override;
     349             : 
     350             :     /// getPreIndexedAddressParts - returns true by value, base pointer and
     351             :     /// offset pointer and addressing mode by reference if the node's address
     352             :     /// can be legally represented as pre-indexed load / store address.
     353             :     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
     354             :                                    ISD::MemIndexedMode &AM,
     355             :                                    SelectionDAG &DAG) const override;
     356             : 
     357             :     /// getPostIndexedAddressParts - returns true by value, base pointer and
     358             :     /// offset pointer and addressing mode by reference if this node can be
     359             :     /// combined with a load / store to form a post-indexed load / store.
     360             :     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
     361             :                                     SDValue &Offset, ISD::MemIndexedMode &AM,
     362             :                                     SelectionDAG &DAG) const override;
     363             : 
     364             :     void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
     365             :                                        const APInt &DemandedElts,
     366             :                                        const SelectionDAG &DAG,
     367             :                                        unsigned Depth) const override;
     368             : 
     369             : 
     370             :     bool ExpandInlineAsm(CallInst *CI) const override;
     371             : 
     372             :     ConstraintType getConstraintType(StringRef Constraint) const override;
     373             : 
     374             :     /// Examine constraint string and operand type and determine a weight value.
     375             :     /// The operand object must already have been set up with the operand type.
     376             :     ConstraintWeight getSingleConstraintMatchWeight(
     377             :       AsmOperandInfo &info, const char *constraint) const override;
     378             : 
     379             :     std::pair<unsigned, const TargetRegisterClass *>
     380             :     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
     381             :                                  StringRef Constraint, MVT VT) const override;
     382             : 
     383             :     const char *LowerXConstraint(EVT ConstraintVT) const override;
     384             : 
     385             :     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
     386             :     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
     387             :     /// true it means one of the asm constraint of the inline asm instruction
     388             :     /// being processed is 'm'.
     389             :     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
     390             :                                       std::vector<SDValue> &Ops,
     391             :                                       SelectionDAG &DAG) const override;
     392             : 
     393             :     unsigned
     394          25 :     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
     395          25 :       if (ConstraintCode == "Q")
     396             :         return InlineAsm::Constraint_Q;
     397          18 :       else if (ConstraintCode == "o")
     398             :         return InlineAsm::Constraint_o;
     399          17 :       else if (ConstraintCode.size() == 2) {
     400           4 :         if (ConstraintCode[0] == 'U') {
     401           4 :           switch(ConstraintCode[1]) {
     402             :           default:
     403             :             break;
     404             :           case 'm':
     405             :             return InlineAsm::Constraint_Um;
     406           0 :           case 'n':
     407           0 :             return InlineAsm::Constraint_Un;
     408           0 :           case 'q':
     409           0 :             return InlineAsm::Constraint_Uq;
     410           0 :           case 's':
     411           0 :             return InlineAsm::Constraint_Us;
     412           0 :           case 't':
     413           0 :             return InlineAsm::Constraint_Ut;
     414           2 :           case 'v':
     415           2 :             return InlineAsm::Constraint_Uv;
     416           0 :           case 'y':
     417           0 :             return InlineAsm::Constraint_Uy;
     418             :           }
     419             :         }
     420             :       }
     421          15 :       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
     422             :     }
     423             : 
     424             :     const ARMSubtarget* getSubtarget() const {
     425             :       return Subtarget;
     426             :     }
     427             : 
     428             :     /// getRegClassFor - Return the register class that should be used for the
     429             :     /// specified value type.
     430             :     const TargetRegisterClass *getRegClassFor(MVT VT) const override;
     431             : 
     432             :     /// Returns true if a cast between SrcAS and DestAS is a noop.
     433           2 :     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
     434             :       // Addrspacecasts are always noops.
     435           2 :       return true;
     436             :     }
     437             : 
     438             :     bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
     439             :                                 unsigned &PrefAlign) const override;
     440             : 
     441             :     /// createFastISel - This method returns a target specific FastISel object,
     442             :     /// or null if the target does not support "fast" ISel.
     443             :     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
     444             :                              const TargetLibraryInfo *libInfo) const override;
     445             : 
     446             :     Sched::Preference getSchedulingPreference(SDNode *N) const override;
     447             : 
     448             :     bool
     449             :     isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
     450             :     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
     451             : 
     452             :     /// isFPImmLegal - Returns true if the target can instruction select the
     453             :     /// specified FP immediate natively. If false, the legalizer will
     454             :     /// materialize the FP immediate as a load from a constant pool.
     455             :     bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
     456             : 
     457             :     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
     458             :                             const CallInst &I,
     459             :                             unsigned Intrinsic) const override;
     460             : 
     461             :     /// \brief Returns true if it is beneficial to convert a load of a constant
     462             :     /// to just the constant itself.
     463             :     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
     464             :                                            Type *Ty) const override;
     465             : 
     466             :     /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
     467             :     /// with this index.
     468             :     bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
     469             :                                  unsigned Index) const override;
     470             : 
     471             :     /// \brief Returns true if an argument of type Ty needs to be passed in a
     472             :     /// contiguous block of registers in calling convention CallConv.
     473             :     bool functionArgumentNeedsConsecutiveRegisters(
     474             :         Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
     475             : 
     476             :     /// If a physical register, this returns the register that receives the
     477             :     /// exception address on entry to an EH pad.
     478             :     unsigned
     479             :     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
     480             : 
     481             :     /// If a physical register, this returns the register that receives the
     482             :     /// exception typeid on entry to a landing pad.
     483             :     unsigned
     484             :     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
     485             : 
     486             :     Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
     487             :     Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
     488             :                           AtomicOrdering Ord) const override;
     489             :     Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
     490             :                                 Value *Addr, AtomicOrdering Ord) const override;
     491             : 
     492             :     void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
     493             : 
     494             :     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
     495             :                                   AtomicOrdering Ord) const override;
     496             :     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
     497             :                                    AtomicOrdering Ord) const override;
     498             : 
     499       11025 :     unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
     500             : 
     501             :     bool lowerInterleavedLoad(LoadInst *LI,
     502             :                               ArrayRef<ShuffleVectorInst *> Shuffles,
     503             :                               ArrayRef<unsigned> Indices,
     504             :                               unsigned Factor) const override;
     505             :     bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
     506             :                                unsigned Factor) const override;
     507             : 
     508             :     bool shouldInsertFencesForAtomic(const Instruction *I) const override;
     509             :     TargetLoweringBase::AtomicExpansionKind
     510             :     shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
     511             :     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
     512             :     TargetLoweringBase::AtomicExpansionKind
     513             :     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
     514             :     bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
     515             : 
     516             :     bool useLoadStackGuardNode() const override;
     517             : 
     518             :     bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
     519             :                                    unsigned &Cost) const override;
     520             : 
     521         250 :     bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
     522             :                           const SelectionDAG &DAG) const override {
     523             :       // Do not merge to larger than i32.
     524         250 :       return (MemVT.getSizeInBits() <= 32);
     525             :     }
     526             : 
     527             :     bool isCheapToSpeculateCttz() const override;
     528             :     bool isCheapToSpeculateCtlz() const override;
     529             : 
     530          40 :     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
     531          40 :       return VT.isScalarInteger();
     532             :     }
     533             : 
     534      270842 :     bool supportSwiftError() const override {
     535      270842 :       return true;
     536             :     }
     537             : 
     538          32 :     bool hasStandaloneRem(EVT VT) const override {
     539          32 :       return HasStandaloneRem;
     540             :     }
     541             : 
     542             :     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
     543             :     CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
     544             : 
     545             :     /// Returns true if \p VecTy is a legal interleaved access type. This
     546             :     /// function checks the vector element type and the overall width of the
     547             :     /// vector.
     548             :     bool isLegalInterleavedAccessType(VectorType *VecTy,
     549             :                                       const DataLayout &DL) const;
     550             : 
     551             :     /// Returns the number of interleaved accesses that will be generated when
     552             :     /// lowering accesses of the given type.
     553             :     unsigned getNumInterleavedAccesses(VectorType *VecTy,
     554             :                                        const DataLayout &DL) const;
     555             : 
     556             :     void finalizeLowering(MachineFunction &MF) const override;
     557             : 
     558             :   protected:
     559             :     std::pair<const TargetRegisterClass *, uint8_t>
     560             :     findRepresentativeClass(const TargetRegisterInfo *TRI,
     561             :                             MVT VT) const override;
     562             : 
     563             :   private:
     564             :     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
     565             :     /// make the right decision when generating code for different targets.
     566             :     const ARMSubtarget *Subtarget;
     567             : 
     568             :     const TargetRegisterInfo *RegInfo;
     569             : 
     570             :     const InstrItineraryData *Itins;
     571             : 
     572             :     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
     573             :     ///
     574             :     unsigned ARMPCLabelIndex;
     575             : 
     576             :     // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
     577             :     // check.
     578             :     bool InsertFencesForAtomic;
     579             : 
     580             :     bool HasStandaloneRem = true;
     581             : 
     582             :     void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
     583             :     void addDRTypeForNEON(MVT VT);
     584             :     void addQRTypeForNEON(MVT VT);
     585             :     std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
     586             : 
     587             :     typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
     588             : 
     589             :     void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
     590             :                           SDValue &Arg, RegsToPassVector &RegsToPass,
     591             :                           CCValAssign &VA, CCValAssign &NextVA,
     592             :                           SDValue &StackPtr,
     593             :                           SmallVectorImpl<SDValue> &MemOpChains,
     594             :                           ISD::ArgFlagsTy Flags) const;
     595             :     SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
     596             :                                  SDValue &Root, SelectionDAG &DAG,
     597             :                                  const SDLoc &dl) const;
     598             : 
     599             :     CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
     600             :                                             bool isVarArg) const;
     601             :     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
     602             :                                   bool isVarArg) const;
     603             :     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
     604             :                              const SDLoc &dl, SelectionDAG &DAG,
     605             :                              const CCValAssign &VA,
     606             :                              ISD::ArgFlagsTy Flags) const;
     607             :     SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
     608             :     SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
     609             :     SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
     610             :     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
     611             :                                     const ARMSubtarget *Subtarget) const;
     612             :     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
     613             :     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
     614             :     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
     615             :     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
     616             :     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
     617             :     SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
     618             :     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
     619             :     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
     620             :                                             SelectionDAG &DAG) const;
     621             :     SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
     622             :                                  SelectionDAG &DAG,
     623             :                                  TLSModel::Model model) const;
     624             :     SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
     625             :     SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
     626             :     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
     627             :     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
     628             :     SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
     629             :     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
     630             :     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
     631             :     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
     632             :     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
     633             :     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
     634             :     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     635             :     SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
     636             :     SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
     637             :     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
     638             :     SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
     639             :                             const ARMSubtarget *ST) const;
     640             :     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
     641             :                               const ARMSubtarget *ST) const;
     642             :     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
     643             :     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
     644             :     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
     645             :     void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
     646             :                            SmallVectorImpl<SDValue> &Results) const;
     647             :     SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
     648             :                                    SDValue &Chain) const;
     649             :     SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
     650             :     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
     651             :     SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
     652             :     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
     653             :     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
     654             :     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
     655             : 
     656             :     unsigned getRegisterByName(const char* RegName, EVT VT,
     657             :                                SelectionDAG &DAG) const override;
     658             : 
     659             :     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
     660             :     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
     661             :     /// expanded to FMAs when this method returns true, otherwise fmuladd is
     662             :     /// expanded to fmul + fadd.
     663             :     ///
     664             :     /// ARM supports both fused and unfused multiply-add operations; we already
     665             :     /// lower a pair of fmul and fadd to the latter so it's not clear that there
     666             :     /// would be a gain or that the gain would be worthwhile enough to risk
     667             :     /// correctness bugs.
     668        3603 :     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
     669             : 
     670             :     SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
     671             : 
     672             :     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
     673             :                             CallingConv::ID CallConv, bool isVarArg,
     674             :                             const SmallVectorImpl<ISD::InputArg> &Ins,
     675             :                             const SDLoc &dl, SelectionDAG &DAG,
     676             :                             SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
     677             :                             SDValue ThisVal) const;
     678             : 
     679       11578 :     bool supportSplitCSR(MachineFunction *MF) const override {
     680       23191 :       return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
     681       11648 :           MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
     682             :     }
     683             : 
     684             :     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
     685             :     void insertCopiesSplitCSR(
     686             :       MachineBasicBlock *Entry,
     687             :       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
     688             : 
     689             :     SDValue
     690             :     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     691             :                          const SmallVectorImpl<ISD::InputArg> &Ins,
     692             :                          const SDLoc &dl, SelectionDAG &DAG,
     693             :                          SmallVectorImpl<SDValue> &InVals) const override;
     694             : 
     695             :     int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
     696             :                        SDValue &Chain, const Value *OrigArg,
     697             :                        unsigned InRegsParamRecordIdx, int ArgOffset,
     698             :                        unsigned ArgSize) const;
     699             : 
     700             :     void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
     701             :                               const SDLoc &dl, SDValue &Chain,
     702             :                               unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
     703             :                               bool ForceMutable = false) const;
     704             : 
     705             :     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
     706             :                       SmallVectorImpl<SDValue> &InVals) const override;
     707             : 
     708             :     /// HandleByVal - Target-specific cleanup for ByVal support.
     709             :     void HandleByVal(CCState *, unsigned &, unsigned) const override;
     710             : 
     711             :     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
     712             :     /// for tail call optimization. Targets which want to do tail call
     713             :     /// optimization should implement this function.
     714             :     bool IsEligibleForTailCallOptimization(SDValue Callee,
     715             :                                            CallingConv::ID CalleeCC,
     716             :                                            bool isVarArg,
     717             :                                            bool isCalleeStructRet,
     718             :                                            bool isCallerStructRet,
     719             :                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
     720             :                                     const SmallVectorImpl<SDValue> &OutVals,
     721             :                                     const SmallVectorImpl<ISD::InputArg> &Ins,
     722             :                                            SelectionDAG& DAG) const;
     723             : 
     724             :     bool CanLowerReturn(CallingConv::ID CallConv,
     725             :                         MachineFunction &MF, bool isVarArg,
     726             :                         const SmallVectorImpl<ISD::OutputArg> &Outs,
     727             :                         LLVMContext &Context) const override;
     728             : 
     729             :     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     730             :                         const SmallVectorImpl<ISD::OutputArg> &Outs,
     731             :                         const SmallVectorImpl<SDValue> &OutVals,
     732             :                         const SDLoc &dl, SelectionDAG &DAG) const override;
     733             : 
     734             :     bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
     735             : 
     736             :     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
     737             : 
     738             :     SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
     739             :                     SDValue ARMcc, SDValue CCR, SDValue Cmp,
     740             :                     SelectionDAG &DAG) const;
     741             :     SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
     742             :                       SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
     743             :     SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
     744             :                       const SDLoc &dl, bool InvalidOnQNaN) const;
     745             :     SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
     746             : 
     747             :     SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
     748             : 
     749             :     void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
     750             :                                 MachineBasicBlock *DispatchBB, int FI) const;
     751             : 
     752             :     void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
     753             : 
     754             :     bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
     755             : 
     756             :     MachineBasicBlock *EmitStructByval(MachineInstr &MI,
     757             :                                        MachineBasicBlock *MBB) const;
     758             : 
     759             :     MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
     760             :                                            MachineBasicBlock *MBB) const;
     761             :     MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
     762             :                                            MachineBasicBlock *MBB) const;
     763             :   };
     764             : 
     765             :   enum NEONModImmType {
     766             :     VMOVModImm,
     767             :     VMVNModImm,
     768             :     OtherModImm
     769             :   };
     770             : 
     771             :   namespace ARM {
     772             : 
     773             :     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
     774             :                              const TargetLibraryInfo *libInfo);
     775             : 
     776             :   } // end namespace ARM
     777             : 
     778             : } // end namespace llvm
     779             : 
     780             : #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H

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