LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMLegalizerInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 197 199 99.0 %
Date: 2017-09-14 15:23:50 Functions: 6 6 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file implements the targeting of the Machinelegalizer class for ARM.
      11             : /// \todo This should be generated by TableGen.
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "ARMLegalizerInfo.h"
      15             : #include "ARMCallLowering.h"
      16             : #include "ARMSubtarget.h"
      17             : #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
      18             : #include "llvm/CodeGen/LowLevelType.h"
      19             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      20             : #include "llvm/CodeGen/ValueTypes.h"
      21             : #include "llvm/IR/DerivedTypes.h"
      22             : #include "llvm/IR/Type.h"
      23             : #include "llvm/Target/TargetOpcodes.h"
      24             : 
      25             : using namespace llvm;
      26             : 
      27        9610 : static bool AEABI(const ARMSubtarget &ST) {
      28        9610 :   return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI();
      29             : }
      30             : 
      31       13461 : ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
      32             :   using namespace TargetOpcode;
      33             : 
      34        4487 :   const LLT p0 = LLT::pointer(0, 32);
      35             : 
      36        4487 :   const LLT s1 = LLT::scalar(1);
      37        4487 :   const LLT s8 = LLT::scalar(8);
      38        4487 :   const LLT s16 = LLT::scalar(16);
      39        4487 :   const LLT s32 = LLT::scalar(32);
      40        4487 :   const LLT s64 = LLT::scalar(64);
      41             : 
      42        8974 :   setAction({G_GLOBAL_VALUE, p0}, Legal);
      43        8974 :   setAction({G_FRAME_INDEX, p0}, Legal);
      44             : 
      45       17948 :   for (unsigned Op : {G_LOAD, G_STORE}) {
      46       62818 :     for (auto Ty : {s1, s8, s16, s32, p0})
      47       89740 :       setAction({Op, Ty}, Legal);
      48       17948 :     setAction({Op, 1, p0}, Legal);
      49             :   }
      50             : 
      51       58331 :   for (unsigned Op : {G_ADD, G_SUB, G_MUL, G_AND, G_OR, G_XOR}) {
      52      134610 :     for (auto Ty : {s1, s8, s16})
      53      161532 :       setAction({Op, Ty}, WidenScalar);
      54       53844 :     setAction({Op, s32}, Legal);
      55             :   }
      56             : 
      57       22435 :   for (unsigned Op : {G_SDIV, G_UDIV}) {
      58       35896 :     for (auto Ty : {s8, s16})
      59       35896 :       setAction({Op, Ty}, WidenScalar);
      60        8974 :     if (ST.hasDivideInARMMode())
      61        2316 :       setAction({Op, s32}, Legal);
      62             :     else
      63       15632 :       setAction({Op, s32}, Libcall);
      64             :   }
      65             : 
      66       22435 :   for (unsigned Op : {G_SREM, G_UREM}) {
      67       35896 :     for (auto Ty : {s8, s16})
      68       35896 :       setAction({Op, Ty}, WidenScalar);
      69        8974 :     if (ST.hasDivideInARMMode())
      70        2316 :       setAction({Op, s32}, Lower);
      71        7816 :     else if (AEABI(ST))
      72       10208 :       setAction({Op, s32}, Custom);
      73             :     else
      74        5424 :       setAction({Op, s32}, Libcall);
      75             :   }
      76             : 
      77       22435 :   for (unsigned Op : {G_SEXT, G_ZEXT}) {
      78       17948 :     setAction({Op, s32}, Legal);
      79       35896 :     for (auto Ty : {s1, s8, s16})
      80       53844 :       setAction({Op, 1, Ty}, Legal);
      81             :   }
      82             : 
      83        8974 :   setAction({G_GEP, p0}, Legal);
      84        8974 :   setAction({G_GEP, 1, s32}, Legal);
      85             : 
      86        8974 :   setAction({G_SELECT, s32}, Legal);
      87        8974 :   setAction({G_SELECT, p0}, Legal);
      88        8974 :   setAction({G_SELECT, 1, s1}, Legal);
      89             : 
      90        8974 :   setAction({G_BRCOND, s1}, Legal);
      91             : 
      92        8974 :   setAction({G_CONSTANT, s32}, Legal);
      93       22435 :   for (auto Ty : {s1, s8, s16})
      94       26922 :     setAction({G_CONSTANT, Ty}, WidenScalar);
      95             : 
      96        8974 :   setAction({G_ICMP, s1}, Legal);
      97       17948 :   for (auto Ty : {s8, s16})
      98       17948 :     setAction({G_ICMP, 1, Ty}, WidenScalar);
      99       17948 :   for (auto Ty : {s32, p0})
     100       17948 :     setAction({G_ICMP, 1, Ty}, Legal);
     101             : 
     102        4487 :   if (!ST.useSoftFloat() && ST.hasVFP2()) {
     103        5386 :     setAction({G_FADD, s32}, Legal);
     104        5386 :     setAction({G_FADD, s64}, Legal);
     105             : 
     106        5386 :     setAction({G_LOAD, s64}, Legal);
     107        5386 :     setAction({G_STORE, s64}, Legal);
     108             : 
     109        5386 :     setAction({G_FCMP, s1}, Legal);
     110        5386 :     setAction({G_FCMP, 1, s32}, Legal);
     111        5386 :     setAction({G_FCMP, 1, s64}, Legal);
     112             :   } else {
     113        7176 :     for (auto Ty : {s32, s64})
     114        7176 :       setAction({G_FADD, Ty}, Libcall);
     115             : 
     116        3588 :     setAction({G_FCMP, s1}, Legal);
     117        3588 :     setAction({G_FCMP, 1, s32}, Custom);
     118        3588 :     setAction({G_FCMP, 1, s64}, Custom);
     119             : 
     120        1794 :     if (AEABI(ST))
     121        1304 :       setFCmpLibcallsAEABI();
     122             :     else
     123         490 :       setFCmpLibcallsGNU();
     124             :   }
     125             : 
     126       22435 :   for (unsigned Op : {G_FREM, G_FPOW})
     127       35896 :     for (auto Ty : {s32, s64})
     128       35896 :       setAction({Op, Ty}, Libcall);
     129             : 
     130        4487 :   computeTables();
     131        4487 : }
     132             : 
     133        1304 : void ARMLegalizerInfo::setFCmpLibcallsAEABI() {
     134             :   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
     135             :   // default-initialized.
     136        2608 :   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
     137        3912 :   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {
     138             :       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE}};
     139        3912 :   FCmp32Libcalls[CmpInst::FCMP_OGE] = {
     140             :       {RTLIB::OGE_F32, CmpInst::BAD_ICMP_PREDICATE}};
     141        3912 :   FCmp32Libcalls[CmpInst::FCMP_OGT] = {
     142             :       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE}};
     143        3912 :   FCmp32Libcalls[CmpInst::FCMP_OLE] = {
     144             :       {RTLIB::OLE_F32, CmpInst::BAD_ICMP_PREDICATE}};
     145        3912 :   FCmp32Libcalls[CmpInst::FCMP_OLT] = {
     146             :       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
     147        3912 :   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
     148        3912 :   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_EQ}};
     149        3912 :   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_EQ}};
     150        3912 :   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_EQ}};
     151        3912 :   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_EQ}};
     152        3912 :   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_EQ}};
     153        3912 :   FCmp32Libcalls[CmpInst::FCMP_UNO] = {
     154             :       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
     155        3912 :   FCmp32Libcalls[CmpInst::FCMP_ONE] = {
     156             :       {RTLIB::OGT_F32, CmpInst::BAD_ICMP_PREDICATE},
     157             :       {RTLIB::OLT_F32, CmpInst::BAD_ICMP_PREDICATE}};
     158        3912 :   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {
     159             :       {RTLIB::OEQ_F32, CmpInst::BAD_ICMP_PREDICATE},
     160             :       {RTLIB::UO_F32, CmpInst::BAD_ICMP_PREDICATE}};
     161             : 
     162        2608 :   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
     163        3912 :   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {
     164             :       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE}};
     165        3912 :   FCmp64Libcalls[CmpInst::FCMP_OGE] = {
     166             :       {RTLIB::OGE_F64, CmpInst::BAD_ICMP_PREDICATE}};
     167        3912 :   FCmp64Libcalls[CmpInst::FCMP_OGT] = {
     168             :       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE}};
     169        3912 :   FCmp64Libcalls[CmpInst::FCMP_OLE] = {
     170             :       {RTLIB::OLE_F64, CmpInst::BAD_ICMP_PREDICATE}};
     171        3912 :   FCmp64Libcalls[CmpInst::FCMP_OLT] = {
     172             :       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
     173        3912 :   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
     174        3912 :   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_EQ}};
     175        3912 :   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_EQ}};
     176        3912 :   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_EQ}};
     177        3912 :   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_EQ}};
     178        3912 :   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_EQ}};
     179        3912 :   FCmp64Libcalls[CmpInst::FCMP_UNO] = {
     180             :       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
     181        3912 :   FCmp64Libcalls[CmpInst::FCMP_ONE] = {
     182             :       {RTLIB::OGT_F64, CmpInst::BAD_ICMP_PREDICATE},
     183             :       {RTLIB::OLT_F64, CmpInst::BAD_ICMP_PREDICATE}};
     184        3912 :   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {
     185             :       {RTLIB::OEQ_F64, CmpInst::BAD_ICMP_PREDICATE},
     186             :       {RTLIB::UO_F64, CmpInst::BAD_ICMP_PREDICATE}};
     187        1304 : }
     188             : 
     189         490 : void ARMLegalizerInfo::setFCmpLibcallsGNU() {
     190             :   // FCMP_TRUE and FCMP_FALSE don't need libcalls, they should be
     191             :   // default-initialized.
     192         980 :   FCmp32Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
     193        1470 :   FCmp32Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ}};
     194        1470 :   FCmp32Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F32, CmpInst::ICMP_SGE}};
     195        1470 :   FCmp32Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT}};
     196        1470 :   FCmp32Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F32, CmpInst::ICMP_SLE}};
     197        1470 :   FCmp32Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
     198        1470 :   FCmp32Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F32, CmpInst::ICMP_EQ}};
     199        1470 :   FCmp32Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F32, CmpInst::ICMP_SGE}};
     200        1470 :   FCmp32Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F32, CmpInst::ICMP_SGT}};
     201        1470 :   FCmp32Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SLE}};
     202        1470 :   FCmp32Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F32, CmpInst::ICMP_SLT}};
     203        1470 :   FCmp32Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F32, CmpInst::ICMP_NE}};
     204        1470 :   FCmp32Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F32, CmpInst::ICMP_NE}};
     205        1470 :   FCmp32Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F32, CmpInst::ICMP_SGT},
     206             :                                        {RTLIB::OLT_F32, CmpInst::ICMP_SLT}};
     207        1470 :   FCmp32Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F32, CmpInst::ICMP_EQ},
     208             :                                        {RTLIB::UO_F32, CmpInst::ICMP_NE}};
     209             : 
     210         980 :   FCmp64Libcalls.resize(CmpInst::LAST_FCMP_PREDICATE + 1);
     211        1470 :   FCmp64Libcalls[CmpInst::FCMP_OEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ}};
     212        1470 :   FCmp64Libcalls[CmpInst::FCMP_OGE] = {{RTLIB::OGE_F64, CmpInst::ICMP_SGE}};
     213        1470 :   FCmp64Libcalls[CmpInst::FCMP_OGT] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT}};
     214        1470 :   FCmp64Libcalls[CmpInst::FCMP_OLE] = {{RTLIB::OLE_F64, CmpInst::ICMP_SLE}};
     215        1470 :   FCmp64Libcalls[CmpInst::FCMP_OLT] = {{RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
     216        1470 :   FCmp64Libcalls[CmpInst::FCMP_ORD] = {{RTLIB::O_F64, CmpInst::ICMP_EQ}};
     217        1470 :   FCmp64Libcalls[CmpInst::FCMP_UGE] = {{RTLIB::OLT_F64, CmpInst::ICMP_SGE}};
     218        1470 :   FCmp64Libcalls[CmpInst::FCMP_UGT] = {{RTLIB::OLE_F64, CmpInst::ICMP_SGT}};
     219        1470 :   FCmp64Libcalls[CmpInst::FCMP_ULE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SLE}};
     220        1470 :   FCmp64Libcalls[CmpInst::FCMP_ULT] = {{RTLIB::OGE_F64, CmpInst::ICMP_SLT}};
     221        1470 :   FCmp64Libcalls[CmpInst::FCMP_UNE] = {{RTLIB::UNE_F64, CmpInst::ICMP_NE}};
     222        1470 :   FCmp64Libcalls[CmpInst::FCMP_UNO] = {{RTLIB::UO_F64, CmpInst::ICMP_NE}};
     223        1470 :   FCmp64Libcalls[CmpInst::FCMP_ONE] = {{RTLIB::OGT_F64, CmpInst::ICMP_SGT},
     224             :                                        {RTLIB::OLT_F64, CmpInst::ICMP_SLT}};
     225        1470 :   FCmp64Libcalls[CmpInst::FCMP_UEQ] = {{RTLIB::OEQ_F64, CmpInst::ICMP_EQ},
     226             :                                        {RTLIB::UO_F64, CmpInst::ICMP_NE}};
     227         490 : }
     228             : 
     229             : ARMLegalizerInfo::FCmpLibcallsList
     230          68 : ARMLegalizerInfo::getFCmpLibcalls(CmpInst::Predicate Predicate,
     231             :                                   unsigned Size) const {
     232             :   assert(CmpInst::isFPPredicate(Predicate) && "Unsupported FCmp predicate");
     233          68 :   if (Size == 32)
     234          72 :     return FCmp32Libcalls[Predicate];
     235          32 :   if (Size == 64)
     236          64 :     return FCmp64Libcalls[Predicate];
     237           0 :   llvm_unreachable("Unsupported size for FCmp predicate");
     238             : }
     239             : 
     240          80 : bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
     241             :                                       MachineRegisterInfo &MRI,
     242             :                                       MachineIRBuilder &MIRBuilder) const {
     243             :   using namespace TargetOpcode;
     244             : 
     245          80 :   MIRBuilder.setInstr(MI);
     246             : 
     247         160 :   switch (MI.getOpcode()) {
     248             :   default:
     249             :     return false;
     250          12 :   case G_SREM:
     251             :   case G_UREM: {
     252          12 :     unsigned OriginalResult = MI.getOperand(0).getReg();
     253          12 :     auto Size = MRI.getType(OriginalResult).getSizeInBits();
     254          12 :     if (Size != 32)
     255             :       return false;
     256             : 
     257             :     auto Libcall =
     258          24 :         MI.getOpcode() == G_SREM ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32;
     259             : 
     260             :     // Our divmod libcalls return a struct containing the quotient and the
     261             :     // remainder. We need to create a virtual register for it.
     262          12 :     auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
     263          12 :     Type *ArgTy = Type::getInt32Ty(Ctx);
     264          24 :     StructType *RetTy = StructType::get(Ctx, {ArgTy, ArgTy}, /* Packed */ true);
     265          12 :     auto RetVal = MRI.createGenericVirtualRegister(
     266          24 :         getLLTForType(*RetTy, MIRBuilder.getMF().getDataLayout()));
     267             : 
     268          84 :     auto Status = createLibcall(MIRBuilder, Libcall, {RetVal, RetTy},
     269          12 :                                 {{MI.getOperand(1).getReg(), ArgTy},
     270          24 :                                  {MI.getOperand(2).getReg(), ArgTy}});
     271          12 :     if (Status != LegalizerHelper::Legalized)
     272             :       return false;
     273             : 
     274             :     // The remainder is the second result of divmod. Split the return value into
     275             :     // a new, unused register for the quotient and the destination of the
     276             :     // original instruction for the remainder.
     277          12 :     MIRBuilder.buildUnmerge(
     278          12 :         {MRI.createGenericVirtualRegister(LLT::scalar(32)), OriginalResult},
     279          36 :         RetVal);
     280          12 :     break;
     281             :   }
     282          68 :   case G_FCMP: {
     283             :     assert(MRI.getType(MI.getOperand(2).getReg()) ==
     284             :                MRI.getType(MI.getOperand(3).getReg()) &&
     285             :            "Mismatched operands for G_FCMP");
     286          68 :     auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
     287             : 
     288          68 :     auto OriginalResult = MI.getOperand(0).getReg();
     289             :     auto Predicate =
     290          68 :         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
     291          68 :     auto Libcalls = getFCmpLibcalls(Predicate, OpSize);
     292             : 
     293          68 :     if (Libcalls.empty()) {
     294             :       assert((Predicate == CmpInst::FCMP_TRUE ||
     295             :               Predicate == CmpInst::FCMP_FALSE) &&
     296             :              "Predicate needs libcalls, but none specified");
     297           8 :       MIRBuilder.buildConstant(OriginalResult,
     298           8 :                                Predicate == CmpInst::FCMP_TRUE ? 1 : 0);
     299           8 :       MI.eraseFromParent();
     300          16 :       return true;
     301             :     }
     302             : 
     303          60 :     auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
     304             :     assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size");
     305          60 :     auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx);
     306          60 :     auto *RetTy = Type::getInt32Ty(Ctx);
     307             : 
     308          60 :     SmallVector<unsigned, 2> Results;
     309         250 :     for (auto Libcall : Libcalls) {
     310          70 :       auto LibcallResult = MRI.createGenericVirtualRegister(LLT::scalar(32));
     311             :       auto Status =
     312         490 :           createLibcall(MIRBuilder, Libcall.LibcallID, {LibcallResult, RetTy},
     313          70 :                         {{MI.getOperand(2).getReg(), ArgTy},
     314         140 :                          {MI.getOperand(3).getReg(), ArgTy}});
     315             : 
     316          70 :       if (Status != LegalizerHelper::Legalized)
     317           0 :         return false;
     318             : 
     319             :       auto ProcessedResult =
     320          70 :           Libcalls.size() == 1
     321          90 :               ? OriginalResult
     322          90 :               : MRI.createGenericVirtualRegister(MRI.getType(OriginalResult));
     323             : 
     324             :       // We have a result, but we need to transform it into a proper 1-bit 0 or
     325             :       // 1, taking into account the different peculiarities of the values
     326             :       // returned by the comparison functions.
     327          70 :       CmpInst::Predicate ResultPred = Libcall.Predicate;
     328          70 :       if (ResultPred == CmpInst::BAD_ICMP_PREDICATE) {
     329             :         // We have a nice 0 or 1, and we just need to truncate it back to 1 bit
     330             :         // to keep the types consistent.
     331          23 :         MIRBuilder.buildTrunc(ProcessedResult, LibcallResult);
     332             :       } else {
     333             :         // We need to compare against 0.
     334             :         assert(CmpInst::isIntPredicate(ResultPred) && "Unsupported predicate");
     335          47 :         auto Zero = MRI.createGenericVirtualRegister(LLT::scalar(32));
     336          47 :         MIRBuilder.buildConstant(Zero, 0);
     337          47 :         MIRBuilder.buildICmp(ResultPred, ProcessedResult, LibcallResult, Zero);
     338             :       }
     339          70 :       Results.push_back(ProcessedResult);
     340             :     }
     341             : 
     342          60 :     if (Results.size() != 1) {
     343             :       assert(Results.size() == 2 && "Unexpected number of results");
     344          20 :       MIRBuilder.buildOr(OriginalResult, Results[0], Results[1]);
     345             :     }
     346          60 :     break;
     347             :   }
     348             :   }
     349             : 
     350          72 :   MI.eraseFromParent();
     351          72 :   return true;
     352             : }

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