LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMSubtarget.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 58 58 100.0 %
Date: 2017-09-14 15:23:50 Functions: 10 10 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file declares the ARM specific subclass of TargetSubtargetInfo.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
      15             : #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H
      16             : 
      17             : #include "ARMBaseInstrInfo.h"
      18             : #include "ARMBaseRegisterInfo.h"
      19             : #include "ARMConstantPoolValue.h"
      20             : #include "ARMFrameLowering.h"
      21             : #include "ARMISelLowering.h"
      22             : #include "ARMSelectionDAGInfo.h"
      23             : #include "llvm/ADT/Triple.h"
      24             : #include "llvm/CodeGen/GlobalISel/CallLowering.h"
      25             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      26             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      27             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/MC/MCInstrItineraries.h"
      30             : #include "llvm/MC/MCSchedule.h"
      31             : #include "llvm/Target/TargetOptions.h"
      32             : #include "llvm/Target/TargetSubtargetInfo.h"
      33             : #include <memory>
      34             : #include <string>
      35             : 
      36             : #define GET_SUBTARGETINFO_HEADER
      37             : #include "ARMGenSubtargetInfo.inc"
      38             : 
      39             : namespace llvm {
      40             : 
      41             : class ARMBaseTargetMachine;
      42             : class GlobalValue;
      43             : class StringRef;
      44             : 
      45       56030 : class ARMSubtarget : public ARMGenSubtargetInfo {
      46             : protected:
      47             :   enum ARMProcFamilyEnum {
      48             :     Others,
      49             : 
      50             :     CortexA12,
      51             :     CortexA15,
      52             :     CortexA17,
      53             :     CortexA32,
      54             :     CortexA35,
      55             :     CortexA5,
      56             :     CortexA53,
      57             :     CortexA55,
      58             :     CortexA57,
      59             :     CortexA7,
      60             :     CortexA72,
      61             :     CortexA73,
      62             :     CortexA75,
      63             :     CortexA8,
      64             :     CortexA9,
      65             :     CortexM3,
      66             :     CortexR4,
      67             :     CortexR4F,
      68             :     CortexR5,
      69             :     CortexR52,
      70             :     CortexR7,
      71             :     ExynosM1,
      72             :     Krait,
      73             :     Kryo,
      74             :     Swift
      75             :   };
      76             :   enum ARMProcClassEnum {
      77             :     None,
      78             : 
      79             :     AClass,
      80             :     MClass,
      81             :     RClass
      82             :   };
      83             :   enum ARMArchEnum {
      84             :     ARMv2,
      85             :     ARMv2a,
      86             :     ARMv3,
      87             :     ARMv3m,
      88             :     ARMv4,
      89             :     ARMv4t,
      90             :     ARMv5,
      91             :     ARMv5t,
      92             :     ARMv5te,
      93             :     ARMv5tej,
      94             :     ARMv6,
      95             :     ARMv6k,
      96             :     ARMv6kz,
      97             :     ARMv6m,
      98             :     ARMv6sm,
      99             :     ARMv6t2,
     100             :     ARMv7a,
     101             :     ARMv7em,
     102             :     ARMv7m,
     103             :     ARMv7r,
     104             :     ARMv7ve,
     105             :     ARMv81a,
     106             :     ARMv82a,
     107             :     ARMv83a,
     108             :     ARMv8a,
     109             :     ARMv8mBaseline,
     110             :     ARMv8mMainline,
     111             :     ARMv8r
     112             :   };
     113             : 
     114             : public:
     115             :   /// What kind of timing do load multiple/store multiple instructions have.
     116             :   enum ARMLdStMultipleTiming {
     117             :     /// Can load/store 2 registers/cycle.
     118             :     DoubleIssue,
     119             :     /// Can load/store 2 registers/cycle, but needs an extra cycle if the access
     120             :     /// is not 64-bit aligned.
     121             :     DoubleIssueCheckUnalignedAccess,
     122             :     /// Can load/store 1 register/cycle.
     123             :     SingleIssue,
     124             :     /// Can load/store 1 register/cycle, but needs an extra cycle for address
     125             :     /// computation and potentially also for register writeback.
     126             :     SingleIssuePlusExtras,
     127             :   };
     128             : 
     129             : protected:
     130             :   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
     131             :   ARMProcFamilyEnum ARMProcFamily = Others;
     132             : 
     133             :   /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass.
     134             :   ARMProcClassEnum ARMProcClass = None;
     135             : 
     136             :   /// ARMArch - ARM architecture
     137             :   ARMArchEnum ARMArch = ARMv4t;
     138             : 
     139             :   /// HasV4TOps, HasV5TOps, HasV5TEOps,
     140             :   /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops -
     141             :   /// Specify whether target support specific ARM ISA variants.
     142             :   bool HasV4TOps = false;
     143             :   bool HasV5TOps = false;
     144             :   bool HasV5TEOps = false;
     145             :   bool HasV6Ops = false;
     146             :   bool HasV6MOps = false;
     147             :   bool HasV6KOps = false;
     148             :   bool HasV6T2Ops = false;
     149             :   bool HasV7Ops = false;
     150             :   bool HasV8Ops = false;
     151             :   bool HasV8_1aOps = false;
     152             :   bool HasV8_2aOps = false;
     153             :   bool HasV8_3aOps = false;
     154             :   bool HasV8MBaselineOps = false;
     155             :   bool HasV8MMainlineOps = false;
     156             : 
     157             :   /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what
     158             :   /// floating point ISAs are supported.
     159             :   bool HasVFPv2 = false;
     160             :   bool HasVFPv3 = false;
     161             :   bool HasVFPv4 = false;
     162             :   bool HasFPARMv8 = false;
     163             :   bool HasNEON = false;
     164             : 
     165             :   /// HasDotProd - True if the ARMv8.2A dot product instructions are supported.
     166             :   bool HasDotProd = false;
     167             : 
     168             :   /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
     169             :   /// specified. Use the method useNEONForSinglePrecisionFP() to
     170             :   /// determine if NEON should actually be used.
     171             :   bool UseNEONForSinglePrecisionFP = false;
     172             : 
     173             :   /// UseMulOps - True if non-microcoded fused integer multiply-add and
     174             :   /// multiply-subtract instructions should be used.
     175             :   bool UseMulOps = false;
     176             : 
     177             :   /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
     178             :   /// whether the FP VML[AS] instructions are slow (if so, don't use them).
     179             :   bool SlowFPVMLx = false;
     180             : 
     181             :   /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
     182             :   /// forwarding to allow mul + mla being issued back to back.
     183             :   bool HasVMLxForwarding = false;
     184             : 
     185             :   /// SlowFPBrcc - True if floating point compare + branch is slow.
     186             :   bool SlowFPBrcc = false;
     187             : 
     188             :   /// InThumbMode - True if compiling for Thumb, false for ARM.
     189             :   bool InThumbMode = false;
     190             : 
     191             :   /// UseSoftFloat - True if we're using software floating point features.
     192             :   bool UseSoftFloat = false;
     193             : 
     194             :   /// UseMISched - True if MachineScheduler should be used for this subtarget.
     195             :   bool UseMISched = false;
     196             : 
     197             :   /// DisablePostRAScheduler - False if scheduling should happen again after
     198             :   /// register allocation.
     199             :   bool DisablePostRAScheduler = false;
     200             : 
     201             :   /// HasThumb2 - True if Thumb2 instructions are supported.
     202             :   bool HasThumb2 = false;
     203             : 
     204             :   /// NoARM - True if subtarget does not support ARM mode execution.
     205             :   bool NoARM = false;
     206             : 
     207             :   /// ReserveR9 - True if R9 is not available as a general purpose register.
     208             :   bool ReserveR9 = false;
     209             : 
     210             :   /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
     211             :   /// 32-bit imms (including global addresses).
     212             :   bool NoMovt = false;
     213             : 
     214             :   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
     215             :   /// must be able to synthesize call stubs for interworking between ARM and
     216             :   /// Thumb.
     217             :   bool SupportsTailCall = false;
     218             : 
     219             :   /// HasFP16 - True if subtarget supports half-precision FP conversions
     220             :   bool HasFP16 = false;
     221             : 
     222             :   /// HasFullFP16 - True if subtarget supports half-precision FP operations
     223             :   bool HasFullFP16 = false;
     224             : 
     225             :   /// HasD16 - True if subtarget is limited to 16 double precision
     226             :   /// FP registers for VFPv3.
     227             :   bool HasD16 = false;
     228             : 
     229             :   /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode
     230             :   bool HasHardwareDivideInThumb = false;
     231             : 
     232             :   /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode
     233             :   bool HasHardwareDivideInARM = false;
     234             : 
     235             :   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
     236             :   /// instructions.
     237             :   bool HasDataBarrier = false;
     238             : 
     239             :   /// HasV7Clrex - True if the subtarget supports CLREX instructions
     240             :   bool HasV7Clrex = false;
     241             : 
     242             :   /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
     243             :   /// instructions
     244             :   bool HasAcquireRelease = false;
     245             : 
     246             :   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
     247             :   /// over 16-bit ones.
     248             :   bool Pref32BitThumb = false;
     249             : 
     250             :   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
     251             :   /// that partially update CPSR and add false dependency on the previous
     252             :   /// CPSR setting instruction.
     253             :   bool AvoidCPSRPartialUpdate = false;
     254             : 
     255             :   /// CheapPredicableCPSRDef - If true, disable +1 predication cost
     256             :   /// for instructions updating CPSR. Enabled for Cortex-A57.
     257             :   bool CheapPredicableCPSRDef = false;
     258             : 
     259             :   /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting
     260             :   /// movs with shifter operand (i.e. asr, lsl, lsr).
     261             :   bool AvoidMOVsShifterOperand = false;
     262             : 
     263             :   /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should
     264             :   /// avoid issue "normal" call instructions to callees which do not return.
     265             :   bool HasRetAddrStack = false;
     266             : 
     267             :   /// HasBranchPredictor - True if the subtarget has a branch predictor. Having
     268             :   /// a branch predictor or not changes the expected cost of taking a branch
     269             :   /// which affects the choice of whether to use predicated instructions.
     270             :   bool HasBranchPredictor = true;
     271             : 
     272             :   /// HasMPExtension - True if the subtarget supports Multiprocessing
     273             :   /// extension (ARMv7 only).
     274             :   bool HasMPExtension = false;
     275             : 
     276             :   /// HasVirtualization - True if the subtarget supports the Virtualization
     277             :   /// extension.
     278             :   bool HasVirtualization = false;
     279             : 
     280             :   /// FPOnlySP - If true, the floating point unit only supports single
     281             :   /// precision.
     282             :   bool FPOnlySP = false;
     283             : 
     284             :   /// If true, the processor supports the Performance Monitor Extensions. These
     285             :   /// include a generic cycle-counter as well as more fine-grained (often
     286             :   /// implementation-specific) events.
     287             :   bool HasPerfMon = false;
     288             : 
     289             :   /// HasTrustZone - if true, processor supports TrustZone security extensions
     290             :   bool HasTrustZone = false;
     291             : 
     292             :   /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions
     293             :   bool Has8MSecExt = false;
     294             : 
     295             :   /// HasCrypto - if true, processor supports Cryptography extensions
     296             :   bool HasCrypto = false;
     297             : 
     298             :   /// HasCRC - if true, processor supports CRC instructions
     299             :   bool HasCRC = false;
     300             : 
     301             :   /// HasRAS - if true, the processor supports RAS extensions
     302             :   bool HasRAS = false;
     303             : 
     304             :   /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are
     305             :   /// particularly effective at zeroing a VFP register.
     306             :   bool HasZeroCycleZeroing = false;
     307             : 
     308             :   /// HasFPAO - if true, processor  does positive address offset computation faster
     309             :   bool HasFPAO = false;
     310             : 
     311             :   /// HasFuseAES - if true, processor executes back to back AES instruction
     312             :   /// pairs faster.
     313             :   bool HasFuseAES = false;
     314             : 
     315             :   /// If true, if conversion may decide to leave some instructions unpredicated.
     316             :   bool IsProfitableToUnpredicate = false;
     317             : 
     318             :   /// If true, VMOV will be favored over VGETLNi32.
     319             :   bool HasSlowVGETLNi32 = false;
     320             : 
     321             :   /// If true, VMOV will be favored over VDUP.
     322             :   bool HasSlowVDUP32 = false;
     323             : 
     324             :   /// If true, VMOVSR will be favored over VMOVDRR.
     325             :   bool PreferVMOVSR = false;
     326             : 
     327             :   /// If true, ISHST barriers will be used for Release semantics.
     328             :   bool PreferISHST = false;
     329             : 
     330             :   /// If true, a VLDM/VSTM starting with an odd register number is considered to
     331             :   /// take more microops than single VLDRS/VSTRS.
     332             :   bool SlowOddRegister = false;
     333             : 
     334             :   /// If true, loading into a D subregister will be penalized.
     335             :   bool SlowLoadDSubregister = false;
     336             : 
     337             :   /// If true, the AGU and NEON/FPU units are multiplexed.
     338             :   bool HasMuxedUnits = false;
     339             : 
     340             :   /// If true, VMOVS will never be widened to VMOVD
     341             :   bool DontWidenVMOVS = false;
     342             : 
     343             :   /// If true, run the MLx expansion pass.
     344             :   bool ExpandMLx = false;
     345             : 
     346             :   /// If true, VFP/NEON VMLA/VMLS have special RAW hazards.
     347             :   bool HasVMLxHazards = false;
     348             : 
     349             :   // If true, read thread pointer from coprocessor register.
     350             :   bool ReadTPHard = false;
     351             : 
     352             :   /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON.
     353             :   bool UseNEONForFPMovs = false;
     354             : 
     355             :   /// If true, VLDn instructions take an extra cycle for unaligned accesses.
     356             :   bool CheckVLDnAlign = false;
     357             : 
     358             :   /// If true, VFP instructions are not pipelined.
     359             :   bool NonpipelinedVFP = false;
     360             : 
     361             :   /// StrictAlign - If true, the subtarget disallows unaligned memory
     362             :   /// accesses for some types.  For details, see
     363             :   /// ARMTargetLowering::allowsMisalignedMemoryAccesses().
     364             :   bool StrictAlign = false;
     365             : 
     366             :   /// RestrictIT - If true, the subtarget disallows generation of deprecated IT
     367             :   ///  blocks to conform to ARMv8 rule.
     368             :   bool RestrictIT = false;
     369             : 
     370             :   /// HasDSP - If true, the subtarget supports the DSP (saturating arith
     371             :   /// and such) instructions.
     372             :   bool HasDSP = false;
     373             : 
     374             :   /// NaCl TRAP instruction is generated instead of the regular TRAP.
     375             :   bool UseNaClTrap = false;
     376             : 
     377             :   /// Generate calls via indirect call instructions.
     378             :   bool GenLongCalls = false;
     379             : 
     380             :   /// Generate code that does not contain data access to code sections.
     381             :   bool GenExecuteOnly = false;
     382             : 
     383             :   /// Target machine allowed unsafe FP math (such as use of NEON fp)
     384             :   bool UnsafeFPMath = false;
     385             : 
     386             :   /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS).
     387             :   bool UseSjLjEH = false;
     388             : 
     389             :   /// Implicitly convert an instruction to a different one if its immediates
     390             :   /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1.
     391             :   bool NegativeImmediates = true;
     392             : 
     393             :   /// stackAlignment - The minimum alignment known to hold of the stack frame on
     394             :   /// entry to the function and which must be maintained by every function.
     395             :   unsigned stackAlignment = 4;
     396             : 
     397             :   /// CPUString - String name of used CPU.
     398             :   std::string CPUString;
     399             : 
     400             :   unsigned MaxInterleaveFactor = 1;
     401             : 
     402             :   /// Clearance before partial register updates (in number of instructions)
     403             :   unsigned PartialUpdateClearance = 0;
     404             : 
     405             :   /// What kind of timing do load multiple/store multiple have (double issue,
     406             :   /// single issue etc).
     407             :   ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue;
     408             : 
     409             :   /// The adjustment that we need to apply to get the operand latency from the
     410             :   /// operand cycle returned by the itinerary data for pre-ISel operands.
     411             :   int PreISelOperandLatencyAdjustment = 2;
     412             : 
     413             :   /// IsLittle - The target is Little Endian
     414             :   bool IsLittle;
     415             : 
     416             :   /// TargetTriple - What processor and OS we're targeting.
     417             :   Triple TargetTriple;
     418             : 
     419             :   /// SchedModel - Processor specific instruction costs.
     420             :   MCSchedModel SchedModel;
     421             : 
     422             :   /// Selected instruction itineraries (one entry per itinerary class.)
     423             :   InstrItineraryData InstrItins;
     424             : 
     425             :   /// Options passed via command line that could influence the target
     426             :   const TargetOptions &Options;
     427             : 
     428             :   const ARMBaseTargetMachine &TM;
     429             : 
     430             : public:
     431             :   /// This constructor initializes the data members to match that
     432             :   /// of the specified triple.
     433             :   ///
     434             :   ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
     435             :                const ARMBaseTargetMachine &TM, bool IsLittle);
     436             : 
     437             :   /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
     438             :   /// that still makes it profitable to inline the call.
     439             :   unsigned getMaxInlineSizeThreshold() const {
     440             :     return 64;
     441             :   }
     442             : 
     443             :   /// ParseSubtargetFeatures - Parses features string setting specified
     444             :   /// subtarget options.  Definition of function is auto generated by tblgen.
     445             :   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
     446             : 
     447             :   /// initializeSubtargetDependencies - Initializes using a CPU and feature string
     448             :   /// so that we can use initializer lists for subtarget initialization.
     449             :   ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
     450             : 
     451       11835 :   const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
     452       11835 :     return &TSInfo;
     453             :   }
     454             : 
     455     1045158 :   const ARMBaseInstrInfo *getInstrInfo() const override {
     456     2090316 :     return InstrInfo.get();
     457             :   }
     458             : 
     459      462873 :   const ARMTargetLowering *getTargetLowering() const override {
     460      462873 :     return &TLInfo;
     461             :   }
     462             : 
     463     1783301 :   const ARMFrameLowering *getFrameLowering() const override {
     464     3566602 :     return FrameLowering.get();
     465             :   }
     466             : 
     467     2338752 :   const ARMBaseRegisterInfo *getRegisterInfo() const override {
     468     4686478 :     return &InstrInfo->getRegisterInfo();
     469             :   }
     470             : 
     471             :   const CallLowering *getCallLowering() const override;
     472             :   const InstructionSelector *getInstructionSelector() const override;
     473             :   const LegalizerInfo *getLegalizerInfo() const override;
     474             :   const RegisterBankInfo *getRegBankInfo() const override;
     475             : 
     476             : private:
     477             :   ARMSelectionDAGInfo TSInfo;
     478             :   // Either Thumb1FrameLowering or ARMFrameLowering.
     479             :   std::unique_ptr<ARMFrameLowering> FrameLowering;
     480             :   // Either Thumb1InstrInfo or Thumb2InstrInfo.
     481             :   std::unique_ptr<ARMBaseInstrInfo> InstrInfo;
     482             :   ARMTargetLowering   TLInfo;
     483             : 
     484             :   /// GlobalISel related APIs.
     485             :   std::unique_ptr<CallLowering> CallLoweringInfo;
     486             :   std::unique_ptr<InstructionSelector> InstSelector;
     487             :   std::unique_ptr<LegalizerInfo> Legalizer;
     488             :   std::unique_ptr<RegisterBankInfo> RegBankInfo;
     489             : 
     490             :   void initializeEnvironment();
     491             :   void initSubtargetFeatures(StringRef CPU, StringRef FS);
     492             :   ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS);
     493             : 
     494             : public:
     495             :   void computeIssueWidth();
     496             : 
     497             :   bool hasV4TOps()  const { return HasV4TOps;  }
     498             :   bool hasV5TOps()  const { return HasV5TOps;  }
     499             :   bool hasV5TEOps() const { return HasV5TEOps; }
     500             :   bool hasV6Ops()   const { return HasV6Ops;   }
     501             :   bool hasV6MOps()  const { return HasV6MOps;  }
     502             :   bool hasV6KOps()  const { return HasV6KOps; }
     503             :   bool hasV6T2Ops() const { return HasV6T2Ops; }
     504             :   bool hasV7Ops()   const { return HasV7Ops;  }
     505             :   bool hasV8Ops()   const { return HasV8Ops;  }
     506             :   bool hasV8_1aOps() const { return HasV8_1aOps; }
     507             :   bool hasV8_2aOps() const { return HasV8_2aOps; }
     508             :   bool hasV8_3aOps() const { return HasV8_3aOps; }
     509             :   bool hasV8MBaselineOps() const { return HasV8MBaselineOps; }
     510             :   bool hasV8MMainlineOps() const { return HasV8MMainlineOps; }
     511             : 
     512             :   /// @{
     513             :   /// These functions are obsolete, please consider adding subtarget features
     514             :   /// or properties instead of calling them.
     515             :   bool isCortexA5() const { return ARMProcFamily == CortexA5; }
     516             :   bool isCortexA7() const { return ARMProcFamily == CortexA7; }
     517             :   bool isCortexA8() const { return ARMProcFamily == CortexA8; }
     518             :   bool isCortexA9() const { return ARMProcFamily == CortexA9; }
     519             :   bool isCortexA15() const { return ARMProcFamily == CortexA15; }
     520         152 :   bool isSwift()    const { return ARMProcFamily == Swift; }
     521             :   bool isCortexM3() const { return ARMProcFamily == CortexM3; }
     522      135520 :   bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
     523             :   bool isCortexR5() const { return ARMProcFamily == CortexR5; }
     524             :   bool isKrait() const { return ARMProcFamily == Krait; }
     525             :   /// @}
     526             : 
     527             :   bool hasARMOps() const { return !NoARM; }
     528             : 
     529             :   bool hasVFP2() const { return HasVFPv2; }
     530             :   bool hasVFP3() const { return HasVFPv3; }
     531             :   bool hasVFP4() const { return HasVFPv4; }
     532             :   bool hasFPARMv8() const { return HasFPARMv8; }
     533             :   bool hasNEON() const { return HasNEON;  }
     534             :   bool hasCrypto() const { return HasCrypto; }
     535             :   bool hasDotProd() const { return HasDotProd; }
     536             :   bool hasCRC() const { return HasCRC; }
     537             :   bool hasRAS() const { return HasRAS; }
     538             :   bool hasVirtualization() const { return HasVirtualization; }
     539             : 
     540             :   bool useNEONForSinglePrecisionFP() const {
     541       52209 :     return hasNEON() && UseNEONForSinglePrecisionFP;
     542             :   }
     543             : 
     544             :   bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
     545             :   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
     546             :   bool hasDataBarrier() const { return HasDataBarrier; }
     547             :   bool hasV7Clrex() const { return HasV7Clrex; }
     548             :   bool hasAcquireRelease() const { return HasAcquireRelease; }
     549             : 
     550             :   bool hasAnyDataBarrier() const {
     551       29097 :     return HasDataBarrier || (hasV6Ops() && !isThumb());
     552             :   }
     553             : 
     554             :   bool useMulOps() const { return UseMulOps; }
     555             :   bool useFPVMLx() const { return !SlowFPVMLx; }
     556             :   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
     557             :   bool isFPBrccSlow() const { return SlowFPBrcc; }
     558             :   bool isFPOnlySP() const { return FPOnlySP; }
     559             :   bool hasPerfMon() const { return HasPerfMon; }
     560             :   bool hasTrustZone() const { return HasTrustZone; }
     561             :   bool has8MSecExt() const { return Has8MSecExt; }
     562             :   bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
     563             :   bool hasFPAO() const { return HasFPAO; }
     564             :   bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; }
     565             :   bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; }
     566             :   bool hasSlowVDUP32() const { return HasSlowVDUP32; }
     567             :   bool preferVMOVSR() const { return PreferVMOVSR; }
     568             :   bool preferISHSTBarriers() const { return PreferISHST; }
     569             :   bool expandMLx() const { return ExpandMLx; }
     570             :   bool hasVMLxHazards() const { return HasVMLxHazards; }
     571             :   bool hasSlowOddRegister() const { return SlowOddRegister; }
     572             :   bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; }
     573             :   bool hasMuxedUnits() const { return HasMuxedUnits; }
     574             :   bool dontWidenVMOVS() const { return DontWidenVMOVS; }
     575             :   bool useNEONForFPMovs() const { return UseNEONForFPMovs; }
     576             :   bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; }
     577             :   bool nonpipelinedVFP() const { return NonpipelinedVFP; }
     578             :   bool prefers32BitThumb() const { return Pref32BitThumb; }
     579             :   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
     580             :   bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; }
     581             :   bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; }
     582             :   bool hasRetAddrStack() const { return HasRetAddrStack; }
     583             :   bool hasBranchPredictor() const { return HasBranchPredictor; }
     584             :   bool hasMPExtension() const { return HasMPExtension; }
     585             :   bool hasDSP() const { return HasDSP; }
     586             :   bool useNaClTrap() const { return UseNaClTrap; }
     587             :   bool useSjLjEH() const { return UseSjLjEH; }
     588             :   bool genLongCalls() const { return GenLongCalls; }
     589             :   bool genExecuteOnly() const { return GenExecuteOnly; }
     590             : 
     591             :   bool hasFP16() const { return HasFP16; }
     592             :   bool hasD16() const { return HasD16; }
     593             :   bool hasFullFP16() const { return HasFullFP16; }
     594             : 
     595             :   bool hasFuseAES() const { return HasFuseAES; }
     596             :   /// \brief Return true if the CPU supports any kind of instruction fusion.
     597             :   bool hasFusion() const { return hasFuseAES(); }
     598             : 
     599         740 :   const Triple &getTargetTriple() const { return TargetTriple; }
     600             : 
     601     1301865 :   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
     602       13599 :   bool isTargetIOS() const { return TargetTriple.isiOS(); }
     603       16462 :   bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); }
     604       14238 :   bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); }
     605       16096 :   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
     606       18096 :   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
     607             :   bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); }
     608      811998 :   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
     609             : 
     610       39486 :   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
     611       15604 :   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
     612      196084 :   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
     613             : 
     614             :   // ARM EABI is the bare-metal EABI described in ARM ABI documents and
     615             :   // can be accessed via -target arm-none-eabi. This is NOT GNUEABI.
     616             :   // FIXME: Add a flag for bare-metal for that target and set Triple::EABI
     617             :   // even for GNUEABI, so we can make a distinction here and still conform to
     618             :   // the EABI on GNU (and Android) mode. This requires change in Clang, too.
     619             :   // FIXME: The Darwin exception is temporary, while we move users to
     620             :   // "*-*-*-macho" triples as quickly as possible.
     621             :   bool isTargetAEABI() const {
     622       40276 :     return (TargetTriple.getEnvironment() == Triple::EABI ||
     623       15498 :             TargetTriple.getEnvironment() == Triple::EABIHF) &&
     624       44114 :            !isTargetDarwin() && !isTargetWindows();
     625             :   }
     626             :   bool isTargetGNUAEABI() const {
     627       19937 :     return (TargetTriple.getEnvironment() == Triple::GNUEABI ||
     628        7714 :             TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
     629       23033 :            !isTargetDarwin() && !isTargetWindows();
     630             :   }
     631             :   bool isTargetMuslAEABI() const {
     632       13454 :     return (TargetTriple.getEnvironment() == Triple::MuslEABI ||
     633        6636 :             TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
     634        7400 :            !isTargetDarwin() && !isTargetWindows();
     635             :   }
     636             : 
     637             :   // ARM Targets that support EHABI exception handling standard
     638             :   // Darwin uses SjLj. Other targets might need more checks.
     639      124017 :   bool isTargetEHABICompatible() const {
     640      213996 :     return (TargetTriple.getEnvironment() == Triple::EABI ||
     641      163658 :             TargetTriple.getEnvironment() == Triple::GNUEABI ||
     642      146522 :             TargetTriple.getEnvironment() == Triple::MuslEABI ||
     643      142002 :             TargetTriple.getEnvironment() == Triple::EABIHF ||
     644      134438 :             TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     645      130181 :             TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
     646       64902 :             isTargetAndroid()) &&
     647      246239 :            !isTargetDarwin() && !isTargetWindows();
     648             :   }
     649             : 
     650             :   bool isTargetHardFloat() const {
     651             :     // FIXME: this is invalid for WindowsCE
     652             :     return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     653             :            TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
     654             :            TargetTriple.getEnvironment() == Triple::EABIHF ||
     655             :            isTargetWindows() || isAAPCS16_ABI();
     656             :   }
     657             : 
     658      137218 :   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
     659             : 
     660             :   bool isXRaySupported() const override;
     661             : 
     662             :   bool isAPCS_ABI() const;
     663             :   bool isAAPCS_ABI() const;
     664             :   bool isAAPCS16_ABI() const;
     665             : 
     666             :   bool isROPI() const;
     667             :   bool isRWPI() const;
     668             : 
     669             :   bool useMachineScheduler() const { return UseMISched; }
     670             :   bool disablePostRAScheduler() const { return DisablePostRAScheduler; }
     671             :   bool useSoftFloat() const { return UseSoftFloat; }
     672             :   bool isThumb() const { return InThumbMode; }
     673      708144 :   bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
     674      140434 :   bool isThumb2() const { return InThumbMode && HasThumb2; }
     675             :   bool hasThumb2() const { return HasThumb2; }
     676             :   bool isMClass() const { return ARMProcClass == MClass; }
     677             :   bool isRClass() const { return ARMProcClass == RClass; }
     678             :   bool isAClass() const { return ARMProcClass == AClass; }
     679             :   bool isReadTPHard() const { return ReadTPHard; }
     680             : 
     681             :   bool isR9Reserved() const {
     682       35966 :     return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9;
     683             :   }
     684             : 
     685             :   bool useR7AsFramePointer() const {
     686      546278 :     return isTargetDarwin() || (!isTargetWindows() && isThumb());
     687             :   }
     688             : 
     689             :   /// Returns true if the frame setup is split into two separate pushes (first
     690             :   /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent
     691             :   /// to lr. This is always required on Thumb1-only targets, as the push and
     692             :   /// pop instructions can't access the high registers.
     693      342121 :   bool splitFramePushPop(const MachineFunction &MF) const {
     694      169521 :     return (useR7AsFramePointer() &&
     695      169521 :             MF.getTarget().Options.DisableFramePointerElim(MF)) ||
     696      645007 :            isThumb1Only();
     697             :   }
     698             : 
     699             :   bool useStride4VFPs(const MachineFunction &MF) const;
     700             : 
     701             :   bool useMovt(const MachineFunction &MF) const;
     702             : 
     703             :   bool supportsTailCall() const { return SupportsTailCall; }
     704             : 
     705        1493 :   bool allowsUnalignedMem() const { return !StrictAlign; }
     706             : 
     707             :   bool restrictIT() const { return RestrictIT; }
     708             : 
     709             :   const std::string & getCPUString() const { return CPUString; }
     710             : 
     711             :   bool isLittle() const { return IsLittle; }
     712             : 
     713             :   unsigned getMispredictionPenalty() const;
     714             : 
     715             :   /// This function returns true if the target has sincos() routine in its
     716             :   /// compiler runtime or math libraries.
     717             :   bool hasSinCos() const;
     718             : 
     719             :   /// Returns true if machine scheduler should be enabled.
     720             :   bool enableMachineScheduler() const override;
     721             : 
     722             :   /// True for some subtargets at > -O0.
     723             :   bool enablePostRAScheduler() const override;
     724             : 
     725             :   // enableAtomicExpand- True if we need to expand our atomics.
     726             :   bool enableAtomicExpand() const override;
     727             : 
     728             :   /// getInstrItins - Return the instruction itineraries based on subtarget
     729             :   /// selection.
     730       50533 :   const InstrItineraryData *getInstrItineraryData() const override {
     731       50533 :     return &InstrItins;
     732             :   }
     733             : 
     734             :   /// getStackAlignment - Returns the minimum alignment known to hold of the
     735             :   /// stack frame on entry to the function and which must be maintained by every
     736             :   /// function for this subtarget.
     737             :   unsigned getStackAlignment() const { return stackAlignment; }
     738             : 
     739             :   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
     740             : 
     741             :   unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; }
     742             : 
     743             :   ARMLdStMultipleTiming getLdStMultipleTiming() const {
     744             :     return LdStMultipleTiming;
     745             :   }
     746             : 
     747             :   int getPreISelOperandLatencyAdjustment() const {
     748             :     return PreISelOperandLatencyAdjustment;
     749             :   }
     750             : 
     751             :   /// True if the GV will be accessed via an indirect symbol.
     752             :   bool isGVIndirectSymbol(const GlobalValue *GV) const;
     753             : 
     754             :   /// Returns the constant pool modifier needed to access the GV.
     755             :   ARMCP::ARMCPModifier getCPModifier(const GlobalValue *GV) const;
     756             : 
     757             :   /// True if fast-isel is used.
     758             :   bool useFastISel() const;
     759             : 
     760             :   /// Returns the correct return opcode for the current feature set.
     761             :   /// Use BX if available to allow mixing thumb/arm code, but fall back
     762             :   /// to plain mov pc,lr on ARMv4.
     763             :   unsigned getReturnOpcode() const {
     764        1148 :     if (isThumb())
     765             :       return ARM::tBX_RET;
     766         827 :     if (hasV4TOps())
     767             :       return ARM::BX_RET;
     768             :     return ARM::MOVPCLR;
     769             :   }
     770             : };
     771             : 
     772             : } // end namespace llvm
     773             : 
     774             : #endif  // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H

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