LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMTargetMachine.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 201 203 99.0 %
Date: 2018-07-13 00:08:38 Functions: 31 33 93.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : //
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "ARMTargetMachine.h"
      14             : #include "ARM.h"
      15             : #include "ARMMacroFusion.h"
      16             : #include "ARMSubtarget.h"
      17             : #include "ARMTargetObjectFile.h"
      18             : #include "ARMTargetTransformInfo.h"
      19             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      20             : #include "llvm/ADT/Optional.h"
      21             : #include "llvm/ADT/STLExtras.h"
      22             : #include "llvm/ADT/StringRef.h"
      23             : #include "llvm/ADT/Triple.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/CodeGen/ExecutionDomainFix.h"
      26             : #include "llvm/CodeGen/GlobalISel/CallLowering.h"
      27             : #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
      28             : #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
      29             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      30             : #include "llvm/CodeGen/GlobalISel/Legalizer.h"
      31             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      32             : #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
      33             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      34             : #include "llvm/CodeGen/MachineFunction.h"
      35             : #include "llvm/CodeGen/MachineScheduler.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/CodeGen/TargetPassConfig.h"
      38             : #include "llvm/IR/Attributes.h"
      39             : #include "llvm/IR/DataLayout.h"
      40             : #include "llvm/IR/Function.h"
      41             : #include "llvm/Pass.h"
      42             : #include "llvm/Support/CodeGen.h"
      43             : #include "llvm/Support/CommandLine.h"
      44             : #include "llvm/Support/ErrorHandling.h"
      45             : #include "llvm/Support/TargetParser.h"
      46             : #include "llvm/Support/TargetRegistry.h"
      47             : #include "llvm/Target/TargetLoweringObjectFile.h"
      48             : #include "llvm/Target/TargetOptions.h"
      49             : #include "llvm/Transforms/Scalar.h"
      50             : #include <cassert>
      51             : #include <memory>
      52             : #include <string>
      53             : 
      54             : using namespace llvm;
      55             : 
      56             : static cl::opt<bool>
      57       99743 : DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
      58       99743 :                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
      59      299229 :                    cl::init(false));
      60             : 
      61             : static cl::opt<bool>
      62       99743 : EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
      63       99743 :                  cl::desc("Run SimplifyCFG after expanding atomic operations"
      64             :                           " to make use of cmpxchg flow-based information"),
      65      299229 :                  cl::init(true));
      66             : 
      67             : static cl::opt<bool>
      68       99743 : EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
      69       99743 :                       cl::desc("Enable ARM load/store optimization pass"),
      70      299229 :                       cl::init(true));
      71             : 
      72             : // FIXME: Unify control over GlobalMerge.
      73             : static cl::opt<cl::boolOrDefault>
      74       99743 : EnableGlobalMerge("arm-global-merge", cl::Hidden,
      75       99743 :                   cl::desc("Enable the global merge pass"));
      76             : 
      77             : namespace llvm {
      78             :   void initializeARMExecutionDomainFixPass(PassRegistry&);
      79             : }
      80             : 
      81       98031 : extern "C" void LLVMInitializeARMTarget() {
      82             :   // Register the target.
      83       98031 :   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
      84       98031 :   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
      85       98031 :   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
      86       98031 :   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
      87             : 
      88       98031 :   PassRegistry &Registry = *PassRegistry::getPassRegistry();
      89       98031 :   initializeGlobalISel(Registry);
      90       98031 :   initializeARMLoadStoreOptPass(Registry);
      91       98031 :   initializeARMPreAllocLoadStoreOptPass(Registry);
      92       98031 :   initializeARMParallelDSPPass(Registry);
      93       98031 :   initializeARMConstantIslandsPass(Registry);
      94       98031 :   initializeARMExecutionDomainFixPass(Registry);
      95       98031 :   initializeARMExpandPseudoPass(Registry);
      96       98031 :   initializeThumb2SizeReducePass(Registry);
      97       98031 : }
      98             : 
      99        3317 : static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
     100        3317 :   if (TT.isOSBinFormatMachO())
     101             :     return llvm::make_unique<TargetLoweringObjectFileMachO>();
     102        2379 :   if (TT.isOSWindows())
     103         248 :     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
     104        4510 :   return llvm::make_unique<ARMElfTargetObjectFile>();
     105             : }
     106             : 
     107             : static ARMBaseTargetMachine::ARMABI
     108        6634 : computeTargetABI(const Triple &TT, StringRef CPU,
     109             :                  const TargetOptions &Options) {
     110        6634 :   StringRef ABIName = Options.MCOptions.getABIName();
     111             : 
     112        6634 :   if (ABIName.empty())
     113        6418 :     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
     114             : 
     115             :   if (ABIName == "aapcs16")
     116             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
     117             :   else if (ABIName.startswith("aapcs"))
     118             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
     119             :   else if (ABIName.startswith("apcs"))
     120             :     return ARMBaseTargetMachine::ARM_ABI_APCS;
     121             : 
     122           0 :   llvm_unreachable("Unhandled/unknown ABI Name!");
     123             :   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
     124             : }
     125             : 
     126        3317 : static std::string computeDataLayout(const Triple &TT, StringRef CPU,
     127             :                                      const TargetOptions &Options,
     128             :                                      bool isLittle) {
     129        3317 :   auto ABI = computeTargetABI(TT, CPU, Options);
     130             :   std::string Ret;
     131             : 
     132        3317 :   if (isLittle)
     133             :     // Little endian.
     134             :     Ret += "e";
     135             :   else
     136             :     // Big endian.
     137             :     Ret += "E";
     138             : 
     139        3317 :   Ret += DataLayout::getManglingComponent(TT);
     140             : 
     141             :   // Pointers are 32 bits and aligned to 32 bits.
     142             :   Ret += "-p:32:32";
     143             : 
     144             :   // ABIs other than APCS have 64 bit integers with natural alignment.
     145        3317 :   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
     146             :     Ret += "-i64:64";
     147             : 
     148             :   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
     149             :   // bits, others to 64 bits. We always try to align to 64 bits.
     150        3317 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     151             :     Ret += "-f64:32:64";
     152             : 
     153             :   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
     154             :   // to 64. We always ty to give them natural alignment.
     155        3317 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     156             :     Ret += "-v64:32:64-v128:32:128";
     157        2466 :   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     158             :     Ret += "-v128:64:128";
     159             : 
     160             :   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
     161             :   // particular hardware support on 32-bit ARM).
     162             :   Ret += "-a:0:32";
     163             : 
     164             :   // Integer registers are 32 bits.
     165             :   Ret += "-n32";
     166             : 
     167             :   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
     168             :   // aligned everywhere else.
     169        3317 :   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     170             :     Ret += "-S128";
     171        3279 :   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
     172             :     Ret += "-S64";
     173             :   else
     174             :     Ret += "-S32";
     175             : 
     176        3317 :   return Ret;
     177             : }
     178             : 
     179             : static Reloc::Model getEffectiveRelocModel(const Triple &TT,
     180             :                                            Optional<Reloc::Model> RM) {
     181        3317 :   if (!RM.hasValue())
     182             :     // Default relocation model on Darwin is PIC.
     183        2617 :     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
     184             : 
     185             :   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
     186             :     assert(TT.isOSBinFormatELF() &&
     187             :            "ROPI/RWPI currently only supported for ELF");
     188             : 
     189             :   // DynamicNoPIC is only used on darwin.
     190         700 :   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
     191             :     return Reloc::Static;
     192             : 
     193             :   return *RM;
     194             : }
     195             : 
     196             : static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
     197        3317 :   if (CM)
     198             :     return *CM;
     199             :   return CodeModel::Small;
     200             : }
     201             : 
     202             : /// Create an ARM architecture model.
     203             : ///
     204        3317 : ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
     205             :                                            StringRef CPU, StringRef FS,
     206             :                                            const TargetOptions &Options,
     207             :                                            Optional<Reloc::Model> RM,
     208             :                                            Optional<CodeModel::Model> CM,
     209        3317 :                                            CodeGenOpt::Level OL, bool isLittle)
     210        6634 :     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
     211             :                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
     212             :                         getEffectiveCodeModel(CM), OL),
     213        3317 :       TargetABI(computeTargetABI(TT, CPU, Options)),
     214       16585 :       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
     215             : 
     216             :   // Default to triple-appropriate float ABI
     217        3317 :   if (Options.FloatABIType == FloatABI::Default) {
     218        6189 :     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     219        3025 :         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
     220        2979 :         TargetTriple.getEnvironment() == Triple::EABIHF ||
     221        6014 :         TargetTriple.isOSWindows() ||
     222        2856 :         TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     223         333 :       this->Options.FloatABIType = FloatABI::Hard;
     224             :     else
     225        2825 :       this->Options.FloatABIType = FloatABI::Soft;
     226             :   }
     227             : 
     228             :   // Default to triple-appropriate EABI
     229        3317 :   if (Options.EABIVersion == EABI::Default ||
     230             :       Options.EABIVersion == EABI::Unknown) {
     231             :     // musl is compatible with glibc with regard to EABI version
     232        5948 :     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
     233        2527 :          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     234        2511 :          TargetTriple.getEnvironment() == Triple::MuslEABI ||
     235        4042 :          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
     236             :         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
     237         769 :       this->Options.EABIVersion = EABI::GNU;
     238             :     else
     239        2504 :       this->Options.EABIVersion = EABI::EABI5;
     240             :   }
     241             : 
     242        3317 :   if (TT.isOSBinFormatMachO()) {
     243         938 :     this->Options.TrapUnreachable = true;
     244         938 :     this->Options.NoTrapAfterNoreturn = true;
     245             :   }
     246             : 
     247        3317 :   initAsmInfo();
     248        3317 : }
     249             : 
     250             : ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
     251             : 
     252             : const ARMSubtarget *
     253      264807 : ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
     254      264807 :   Attribute CPUAttr = F.getFnAttribute("target-cpu");
     255      264807 :   Attribute FSAttr = F.getFnAttribute("target-features");
     256             : 
     257      264807 :   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
     258      320125 :                         ? CPUAttr.getValueAsString().str()
     259      264807 :                         : TargetCPU;
     260      264807 :   std::string FS = !FSAttr.hasAttribute(Attribute::None)
     261      378237 :                        ? FSAttr.getValueAsString().str()
     262      264807 :                        : TargetFS;
     263             : 
     264             :   // FIXME: This is related to the code below to reset the target options,
     265             :   // we need to know whether or not the soft float flag is set on the
     266             :   // function before we can generate a subtarget. We also need to use
     267             :   // it as a key for the subtarget since that can be the only difference
     268             :   // between two functions.
     269             :   bool SoftFloat =
     270      529380 :       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
     271             :   // If the soft float attribute is set on the function turn on the soft float
     272             :   // subtarget feature.
     273             :   if (SoftFloat)
     274         234 :     FS += FS.empty() ? "+soft-float" : ",+soft-float";
     275             : 
     276      794421 :   auto &I = SubtargetMap[CPU + FS];
     277      264807 :   if (!I) {
     278             :     // This needs to be done before we create a new subtarget since any
     279             :     // creation will depend on the TM and the code generation flags on the
     280             :     // function that reside in TargetOptions.
     281        2948 :     resetTargetOptions(F);
     282        2948 :     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
     283             : 
     284        2948 :     if (!I->isThumb() && !I->hasARMOps())
     285           9 :       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
     286           3 :           "instructions, but the target does not support ARM mode execution.");
     287             :   }
     288             : 
     289      264807 :   return I.get();
     290             : }
     291             : 
     292             : TargetTransformInfo
     293      123621 : ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
     294      123621 :   return TargetTransformInfo(ARMTTIImpl(this, F));
     295             : }
     296             : 
     297        3271 : ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
     298             :                                        StringRef CPU, StringRef FS,
     299             :                                        const TargetOptions &Options,
     300             :                                        Optional<Reloc::Model> RM,
     301             :                                        Optional<CodeModel::Model> CM,
     302        3271 :                                        CodeGenOpt::Level OL, bool JIT)
     303        6542 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
     304             : 
     305          46 : ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
     306             :                                        StringRef CPU, StringRef FS,
     307             :                                        const TargetOptions &Options,
     308             :                                        Optional<Reloc::Model> RM,
     309             :                                        Optional<CodeModel::Model> CM,
     310          46 :                                        CodeGenOpt::Level OL, bool JIT)
     311          92 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
     312             : 
     313             : namespace {
     314             : 
     315             : /// ARM Code Generator Pass Configuration Options.
     316        2939 : class ARMPassConfig : public TargetPassConfig {
     317             : public:
     318        2966 :   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
     319        2966 :       : TargetPassConfig(TM, PM) {
     320        2966 :     if (TM.getOptLevel() != CodeGenOpt::None) {
     321             :       ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
     322        2538 :                               TM.getTargetFeatureString());
     323        2538 :       if (STI.hasFeature(ARM::FeatureUseMISched))
     324          86 :         substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
     325             :     }
     326        2966 :   }
     327             : 
     328             :   ARMBaseTargetMachine &getARMTargetMachine() const {
     329        2709 :     return getTM<ARMBaseTargetMachine>();
     330             :   }
     331             : 
     332             :   ScheduleDAGInstrs *
     333         277 :   createMachineScheduler(MachineSchedContext *C) const override {
     334         277 :     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
     335             :     // add DAG Mutations here.
     336         277 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     337         277 :     if (ST.hasFusion())
     338           6 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     339         277 :     return DAG;
     340             :   }
     341             : 
     342             :   ScheduleDAGInstrs *
     343           7 :   createPostMachineScheduler(MachineSchedContext *C) const override {
     344           7 :     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
     345             :     // add DAG Mutations here.
     346           7 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     347           7 :     if (ST.hasFusion())
     348           0 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     349           7 :     return DAG;
     350             :   }
     351             : 
     352             :   void addIRPasses() override;
     353             :   bool addPreISel() override;
     354             :   bool addInstSelector() override;
     355             :   bool addIRTranslator() override;
     356             :   bool addLegalizeMachineIR() override;
     357             :   bool addRegBankSelect() override;
     358             :   bool addGlobalInstructionSelect() override;
     359             :   void addPreRegAlloc() override;
     360             :   void addPreSched2() override;
     361             :   void addPreEmitPass() override;
     362             : };
     363             : 
     364        2450 : class ARMExecutionDomainFix : public ExecutionDomainFix {
     365             : public:
     366             :   static char ID;
     367        2477 :   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
     368        2465 :   StringRef getPassName() const override {
     369        2465 :     return "ARM Execution Domain Fix";
     370             :   }
     371             : };
     372             : char ARMExecutionDomainFix::ID;
     373             : 
     374             : } // end anonymous namespace
     375             : 
     376       73254 : INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
     377             :   "ARM Execution Domain Fix", false, false)
     378       73254 : INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
     379      342570 : INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
     380             :   "ARM Execution Domain Fix", false, false)
     381             : 
     382        2966 : TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
     383        2966 :   return new ARMPassConfig(*this, PM);
     384             : }
     385             : 
     386        2737 : void ARMPassConfig::addIRPasses() {
     387        2737 :   if (TM->Options.ThreadModel == ThreadModel::Single)
     388           1 :     addPass(createLowerAtomicPass());
     389             :   else
     390        2736 :     addPass(createAtomicExpandPass());
     391             : 
     392             :   // Cmpxchg instructions are often used with a subsequent comparison to
     393             :   // determine whether it succeeded. We can exploit existing control-flow in
     394             :   // ldrex/strex loops to simplify this, but it needs tidying up.
     395        5214 :   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
     396        7266 :     addPass(createCFGSimplificationPass(
     397       12513 :         1, false, false, true, true, [this](const Function &F) {
     398       12513 :           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
     399       20424 :           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
     400             :         }));
     401             : 
     402        2737 :   TargetPassConfig::addIRPasses();
     403             : 
     404             :   // Match interleaved memory accesses to ldN/stN intrinsics.
     405        2737 :   if (TM->getOptLevel() != CodeGenOpt::None)
     406        2477 :     addPass(createInterleavedAccessPass());
     407        2737 : }
     408             : 
     409        2737 : bool ARMPassConfig::addPreISel() {
     410        2737 :   if (getOptLevel() != CodeGenOpt::None)
     411        2477 :     addPass(createARMParallelDSPPass());
     412             : 
     413        5214 :   if ((TM->getOptLevel() != CodeGenOpt::None &&
     414        3014 :        EnableGlobalMerge == cl::BOU_UNSET) ||
     415             :       EnableGlobalMerge == cl::BOU_TRUE) {
     416             :     // FIXME: This is using the thumb1 only constant value for
     417             :     // maximal global offset for merging globals. We may want
     418             :     // to look into using the old value for non-thumb1 code of
     419             :     // 4095 based on the TargetMachine, but this starts to become
     420             :     // tricky when doing code gen per function.
     421        4898 :     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
     422             :                                (EnableGlobalMerge == cl::BOU_UNSET);
     423             :     // Merging of extern globals is enabled by default on non-Mach-O as we
     424             :     // expect it to be generally either beneficial or harmless. On Mach-O it
     425             :     // is disabled as we emit the .subsections_via_symbols directive which
     426             :     // means that merging extern globals is not safe.
     427        4952 :     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
     428        2476 :     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
     429             :                                   MergeExternalByDefault));
     430             :   }
     431             : 
     432        2737 :   return false;
     433             : }
     434             : 
     435        2709 : bool ARMPassConfig::addInstSelector() {
     436        5418 :   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
     437        2709 :   return false;
     438             : }
     439             : 
     440          35 : bool ARMPassConfig::addIRTranslator() {
     441          35 :   addPass(new IRTranslator());
     442          35 :   return false;
     443             : }
     444             : 
     445          35 : bool ARMPassConfig::addLegalizeMachineIR() {
     446          35 :   addPass(new Legalizer());
     447          35 :   return false;
     448             : }
     449             : 
     450          35 : bool ARMPassConfig::addRegBankSelect() {
     451          35 :   addPass(new RegBankSelect());
     452          35 :   return false;
     453             : }
     454             : 
     455          35 : bool ARMPassConfig::addGlobalInstructionSelect() {
     456          35 :   addPass(new InstructionSelect());
     457          35 :   return false;
     458             : }
     459             : 
     460        2737 : void ARMPassConfig::addPreRegAlloc() {
     461        2737 :   if (getOptLevel() != CodeGenOpt::None) {
     462        2477 :     addPass(createMLxExpansionPass());
     463             : 
     464        2477 :     if (EnableARMLoadStoreOpt)
     465        2477 :       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
     466             : 
     467        2477 :     if (!DisableA15SDOptimization)
     468        2476 :       addPass(createA15SDOptimizerPass());
     469             :   }
     470        2737 : }
     471             : 
     472        2737 : void ARMPassConfig::addPreSched2() {
     473        2737 :   if (getOptLevel() != CodeGenOpt::None) {
     474        2477 :     if (EnableARMLoadStoreOpt)
     475        2477 :       addPass(createARMLoadStoreOptimizationPass());
     476             : 
     477        4954 :     addPass(new ARMExecutionDomainFix());
     478        2477 :     addPass(createBreakFalseDeps());
     479             :   }
     480             : 
     481             :   // Expand some pseudo instructions into multiple instructions to allow
     482             :   // proper scheduling.
     483        2737 :   addPass(createARMExpandPseudoPass());
     484             : 
     485        2737 :   if (getOptLevel() != CodeGenOpt::None) {
     486             :     // in v8, IfConversion depends on Thumb instruction widths
     487       17478 :     addPass(createThumb2SizeReductionPass([this](const Function &F) {
     488       12524 :       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
     489       12524 :     }));
     490             : 
     491        4954 :     addPass(createIfConverter([](const MachineFunction &MF) {
     492       12518 :       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
     493       12518 :     }));
     494             :   }
     495        2737 :   addPass(createThumb2ITBlockPass());
     496        2737 : }
     497             : 
     498        2737 : void ARMPassConfig::addPreEmitPass() {
     499        8211 :   addPass(createThumb2SizeReductionPass());
     500             : 
     501             :   // Constant island pass work on unbundled instructions.
     502        5474 :   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
     503       13735 :     return MF.getSubtarget<ARMSubtarget>().isThumb2();
     504       13735 :   }));
     505             : 
     506             :   // Don't optimize barriers at -O0.
     507        2737 :   if (getOptLevel() != CodeGenOpt::None)
     508        2477 :     addPass(createARMOptimizeBarriersPass());
     509             : 
     510        2737 :   addPass(createARMConstantIslandPass());
     511      301966 : }

Generated by: LCOV version 1.13