LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMTargetMachine.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 195 197 99.0 %
Date: 2017-09-14 15:23:50 Functions: 30 32 93.8 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : //
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "ARM.h"
      14             : #include "ARMSubtarget.h"
      15             : #include "ARMMacroFusion.h"
      16             : #include "ARMTargetMachine.h"
      17             : #include "ARMTargetObjectFile.h"
      18             : #include "ARMTargetTransformInfo.h"
      19             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      20             : #include "llvm/ADT/Optional.h"
      21             : #include "llvm/ADT/STLExtras.h"
      22             : #include "llvm/ADT/StringRef.h"
      23             : #include "llvm/ADT/Triple.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/CodeGen/ExecutionDepsFix.h"
      26             : #include "llvm/CodeGen/GlobalISel/CallLowering.h"
      27             : #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
      28             : #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
      29             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      30             : #include "llvm/CodeGen/GlobalISel/Legalizer.h"
      31             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      32             : #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
      33             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      34             : #include "llvm/CodeGen/MachineFunction.h"
      35             : #include "llvm/CodeGen/MachineScheduler.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/CodeGen/TargetPassConfig.h"
      38             : #include "llvm/IR/Attributes.h"
      39             : #include "llvm/IR/DataLayout.h"
      40             : #include "llvm/IR/Function.h"
      41             : #include "llvm/Pass.h"
      42             : #include "llvm/Support/CodeGen.h"
      43             : #include "llvm/Support/CommandLine.h"
      44             : #include "llvm/Support/ErrorHandling.h"
      45             : #include "llvm/Support/TargetParser.h"
      46             : #include "llvm/Support/TargetRegistry.h"
      47             : #include "llvm/Target/TargetLoweringObjectFile.h"
      48             : #include "llvm/Target/TargetOptions.h"
      49             : #include "llvm/Transforms/Scalar.h"
      50             : #include <cassert>
      51             : #include <memory>
      52             : #include <string>
      53             : 
      54             : using namespace llvm;
      55             : 
      56             : static cl::opt<bool>
      57       72306 : DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
      58      216918 :                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
      59      289224 :                    cl::init(false));
      60             : 
      61             : static cl::opt<bool>
      62       72306 : EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
      63      216918 :                  cl::desc("Run SimplifyCFG after expanding atomic operations"
      64             :                           " to make use of cmpxchg flow-based information"),
      65      289224 :                  cl::init(true));
      66             : 
      67             : static cl::opt<bool>
      68       72306 : EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
      69      216918 :                       cl::desc("Enable ARM load/store optimization pass"),
      70      289224 :                       cl::init(true));
      71             : 
      72             : // FIXME: Unify control over GlobalMerge.
      73             : static cl::opt<cl::boolOrDefault>
      74       72306 : EnableGlobalMerge("arm-global-merge", cl::Hidden,
      75      144612 :                   cl::desc("Enable the global merge pass"));
      76             : 
      77             : namespace llvm {
      78             :   void initializeARMExecutionDepsFixPass(PassRegistry&);
      79             : }
      80             : 
      81       68818 : extern "C" void LLVMInitializeARMTarget() {
      82             :   // Register the target.
      83      137636 :   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
      84      137636 :   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
      85      137636 :   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
      86      137636 :   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
      87             : 
      88       68818 :   PassRegistry &Registry = *PassRegistry::getPassRegistry();
      89       68818 :   initializeGlobalISel(Registry);
      90       68818 :   initializeARMLoadStoreOptPass(Registry);
      91       68818 :   initializeARMPreAllocLoadStoreOptPass(Registry);
      92       68818 :   initializeARMConstantIslandsPass(Registry);
      93       68818 :   initializeARMExecutionDepsFixPass(Registry);
      94       68818 :   initializeARMExpandPseudoPass(Registry);
      95       68818 : }
      96             : 
      97        3062 : static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
      98        3062 :   if (TT.isOSBinFormatMachO())
      99        2745 :     return llvm::make_unique<TargetLoweringObjectFileMachO>();
     100        2147 :   if (TT.isOSWindows())
     101         333 :     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
     102        6108 :   return llvm::make_unique<ARMElfTargetObjectFile>();
     103             : }
     104             : 
     105             : static ARMBaseTargetMachine::ARMABI
     106        6124 : computeTargetABI(const Triple &TT, StringRef CPU,
     107             :                  const TargetOptions &Options) {
     108        6124 :   StringRef ABIName = Options.MCOptions.getABIName();
     109             : 
     110        6124 :   if (ABIName.empty())
     111        5910 :     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
     112             : 
     113        6124 :   if (ABIName == "aapcs16")
     114             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
     115        6064 :   else if (ABIName.startswith("aapcs"))
     116             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
     117        1670 :   else if (ABIName.startswith("apcs"))
     118             :     return ARMBaseTargetMachine::ARM_ABI_APCS;
     119             : 
     120           0 :   llvm_unreachable("Unhandled/unknown ABI Name!");
     121             :   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
     122             : }
     123             : 
     124        3062 : static std::string computeDataLayout(const Triple &TT, StringRef CPU,
     125             :                                      const TargetOptions &Options,
     126             :                                      bool isLittle) {
     127        3062 :   auto ABI = computeTargetABI(TT, CPU, Options);
     128        3062 :   std::string Ret;
     129             : 
     130        3062 :   if (isLittle)
     131             :     // Little endian.
     132             :     Ret += "e";
     133             :   else
     134             :     // Big endian.
     135             :     Ret += "E";
     136             : 
     137        6124 :   Ret += DataLayout::getManglingComponent(TT);
     138             : 
     139             :   // Pointers are 32 bits and aligned to 32 bits.
     140        3062 :   Ret += "-p:32:32";
     141             : 
     142             :   // ABIs other than APCS have 64 bit integers with natural alignment.
     143        3062 :   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
     144             :     Ret += "-i64:64";
     145             : 
     146             :   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
     147             :   // bits, others to 64 bits. We always try to align to 64 bits.
     148        3062 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     149             :     Ret += "-f64:32:64";
     150             : 
     151             :   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
     152             :   // to 64. We always ty to give them natural alignment.
     153        3062 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     154             :     Ret += "-v64:32:64-v128:32:128";
     155        2227 :   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     156             :     Ret += "-v128:64:128";
     157             : 
     158             :   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
     159             :   // particular hardware support on 32-bit ARM).
     160        3062 :   Ret += "-a:0:32";
     161             : 
     162             :   // Integer registers are 32 bits.
     163        3062 :   Ret += "-n32";
     164             : 
     165             :   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
     166             :   // aligned everywhere else.
     167        3062 :   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     168             :     Ret += "-S128";
     169        3026 :   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
     170             :     Ret += "-S64";
     171             :   else
     172             :     Ret += "-S32";
     173             : 
     174        3062 :   return Ret;
     175             : }
     176             : 
     177             : static Reloc::Model getEffectiveRelocModel(const Triple &TT,
     178             :                                            Optional<Reloc::Model> RM) {
     179        3062 :   if (!RM.hasValue())
     180             :     // Default relocation model on Darwin is PIC.
     181        2394 :     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
     182             : 
     183         668 :   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
     184             :     assert(TT.isOSBinFormatELF() &&
     185             :            "ROPI/RWPI currently only supported for ELF");
     186             : 
     187             :   // DynamicNoPIC is only used on darwin.
     188         668 :   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
     189             :     return Reloc::Static;
     190             : 
     191             :   return *RM;
     192             : }
     193             : 
     194             : static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
     195        3062 :   if (CM)
     196           4 :     return *CM;
     197             :   return CodeModel::Small;
     198             : }
     199             : 
     200             : /// Create an ARM architecture model.
     201             : ///
     202        3062 : ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
     203             :                                            StringRef CPU, StringRef FS,
     204             :                                            const TargetOptions &Options,
     205             :                                            Optional<Reloc::Model> RM,
     206             :                                            Optional<CodeModel::Model> CM,
     207        3062 :                                            CodeGenOpt::Level OL, bool isLittle)
     208        6124 :     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
     209             :                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
     210             :                         getEffectiveCodeModel(CM), OL),
     211        3062 :       TargetABI(computeTargetABI(TT, CPU, Options)),
     212       33682 :       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
     213             : 
     214             :   // Default to triple-appropriate float ABI
     215        3062 :   if (Options.FloatABIType == FloatABI::Default) {
     216        5709 :     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     217        5586 :         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
     218        5545 :         TargetTriple.getEnvironment() == Triple::EABIHF ||
     219       11069 :         TargetTriple.isOSWindows() ||
     220        2646 :         TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     221         296 :       this->Options.FloatABIType = FloatABI::Hard;
     222             :     else
     223        2617 :       this->Options.FloatABIType = FloatABI::Soft;
     224             :   }
     225             : 
     226             :   // Default to triple-appropriate EABI
     227        3062 :   if (Options.EABIVersion == EABI::Default ||
     228             :       Options.EABIVersion == EABI::Unknown) {
     229             :     // musl is compatible with glibc with regard to EABI version
     230        5476 :     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
     231        4780 :          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     232        4628 :          TargetTriple.getEnvironment() == Triple::MuslEABI ||
     233        6043 :          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
     234        2876 :         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
     235         719 :       this->Options.EABIVersion = EABI::GNU;
     236             :     else
     237        2299 :       this->Options.EABIVersion = EABI::EABI5;
     238             :   }
     239             : 
     240        3062 :   initAsmInfo();
     241        3062 : }
     242             : 
     243             : ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
     244             : 
     245             : const ARMSubtarget *
     246      181795 : ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
     247      363590 :   Attribute CPUAttr = F.getFnAttribute("target-cpu");
     248      363590 :   Attribute FSAttr = F.getFnAttribute("target-features");
     249             : 
     250      181795 :   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
     251      223676 :                         ? CPUAttr.getValueAsString().str()
     252      545385 :                         : TargetCPU;
     253      181795 :   std::string FS = !FSAttr.hasAttribute(Attribute::None)
     254      259214 :                        ? FSAttr.getValueAsString().str()
     255      545385 :                        : TargetFS;
     256             : 
     257             :   // FIXME: This is related to the code below to reset the target options,
     258             :   // we need to know whether or not the soft float flag is set on the
     259             :   // function before we can generate a subtarget. We also need to use
     260             :   // it as a key for the subtarget since that can be the only difference
     261             :   // between two functions.
     262             :   bool SoftFloat =
     263      545385 :       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
     264             :   // If the soft float attribute is set on the function turn on the soft float
     265             :   // subtarget feature.
     266             :   if (SoftFloat)
     267         128 :     FS += FS.empty() ? "+soft-float" : ",+soft-float";
     268             : 
     269      727180 :   auto &I = SubtargetMap[CPU + FS];
     270      181795 :   if (!I) {
     271             :     // This needs to be done before we create a new subtarget since any
     272             :     // creation will depend on the TM and the code generation flags on the
     273             :     // function that reside in TargetOptions.
     274        2732 :     resetTargetOptions(F);
     275       10928 :     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
     276             : 
     277        4304 :     if (!I->isThumb() && !I->hasARMOps())
     278          12 :       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
     279           6 :           "instructions, but the target does not support ARM mode execution.");
     280             :   }
     281             : 
     282      363590 :   return I.get();
     283             : }
     284             : 
     285        3695 : TargetIRAnalysis ARMBaseTargetMachine::getTargetIRAnalysis() {
     286       70781 :   return TargetIRAnalysis([this](const Function &F) {
     287      141562 :     return TargetTransformInfo(ARMTTIImpl(this, F));
     288       81866 :   });
     289             : }
     290             : 
     291        3021 : ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
     292             :                                        StringRef CPU, StringRef FS,
     293             :                                        const TargetOptions &Options,
     294             :                                        Optional<Reloc::Model> RM,
     295             :                                        Optional<CodeModel::Model> CM,
     296        3021 :                                        CodeGenOpt::Level OL, bool JIT)
     297       15105 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
     298             : 
     299          41 : ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
     300             :                                        StringRef CPU, StringRef FS,
     301             :                                        const TargetOptions &Options,
     302             :                                        Optional<Reloc::Model> RM,
     303             :                                        Optional<CodeModel::Model> CM,
     304          41 :                                        CodeGenOpt::Level OL, bool JIT)
     305         205 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
     306             : 
     307             : namespace {
     308             : 
     309             : /// ARM Code Generator Pass Configuration Options.
     310        2712 : class ARMPassConfig : public TargetPassConfig {
     311             : public:
     312             :   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
     313        2739 :     : TargetPassConfig(TM, PM) {}
     314             : 
     315             :   ARMBaseTargetMachine &getARMTargetMachine() const {
     316        2551 :     return getTM<ARMBaseTargetMachine>();
     317             :   }
     318             : 
     319             :   ScheduleDAGInstrs *
     320         267 :   createMachineScheduler(MachineSchedContext *C) const override {
     321         267 :     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
     322             :     // add DAG Mutations here.
     323         267 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     324         267 :     if (ST.hasFusion())
     325           9 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     326         267 :     return DAG;
     327             :   }
     328             : 
     329             :   ScheduleDAGInstrs *
     330           2 :   createPostMachineScheduler(MachineSchedContext *C) const override {
     331           2 :     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
     332             :     // add DAG Mutations here.
     333           2 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     334           2 :     if (ST.hasFusion())
     335           0 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     336           2 :     return DAG;
     337             :   }
     338             : 
     339             :   void addIRPasses() override;
     340             :   bool addPreISel() override;
     341             :   bool addInstSelector() override;
     342             :   bool addIRTranslator() override;
     343             :   bool addLegalizeMachineIR() override;
     344             :   bool addRegBankSelect() override;
     345             :   bool addGlobalInstructionSelect() override;
     346             :   void addPreRegAlloc() override;
     347             :   void addPreSched2() override;
     348             :   void addPreEmitPass() override;
     349             : };
     350             : 
     351        2295 : class ARMExecutionDepsFix : public ExecutionDepsFix {
     352             : public:
     353             :   static char ID;
     354        2322 :   ARMExecutionDepsFix() : ExecutionDepsFix(ID, ARM::DPRRegClass) {}
     355        2315 :   StringRef getPassName() const override {
     356        2315 :     return "ARM Execution Dependency Fix";
     357             :   }
     358             : };
     359             : char ARMExecutionDepsFix::ID;
     360             : 
     361             : } // end anonymous namespace
     362             : 
     363      312538 : INITIALIZE_PASS(ARMExecutionDepsFix, "arm-execution-deps-fix",
     364             :                 "ARM Execution Dependency Fix", false, false)
     365             : 
     366        2739 : TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
     367        5478 :   return new ARMPassConfig(*this, PM);
     368             : }
     369             : 
     370        2575 : void ARMPassConfig::addIRPasses() {
     371        2575 :   if (TM->Options.ThreadModel == ThreadModel::Single)
     372           1 :     addPass(createLowerAtomicPass());
     373             :   else
     374        2574 :     addPass(createAtomicExpandPass());
     375             : 
     376             :   // Cmpxchg instructions are often used with a subsequent comparison to
     377             :   // determine whether it succeeded. We can exploit existing control-flow in
     378             :   // ldrex/strex loops to simplify this, but it needs tidying up.
     379        4897 :   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
     380       17637 :     addPass(createCFGSimplificationPass(-1, [this](const Function &F) {
     381       21672 :       const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
     382       10836 :       return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
     383             :     }));
     384             : 
     385        2575 :   TargetPassConfig::addIRPasses();
     386             : 
     387             :   // Match interleaved memory accesses to ldN/stN intrinsics.
     388        2575 :   if (TM->getOptLevel() != CodeGenOpt::None)
     389        2322 :     addPass(createInterleavedAccessPass());
     390        2575 : }
     391             : 
     392        2575 : bool ARMPassConfig::addPreISel() {
     393        4897 :   if ((TM->getOptLevel() != CodeGenOpt::None &&
     394        5164 :        EnableGlobalMerge == cl::BOU_UNSET) ||
     395         267 :       EnableGlobalMerge == cl::BOU_TRUE) {
     396             :     // FIXME: This is using the thumb1 only constant value for
     397             :     // maximal global offset for merging globals. We may want
     398             :     // to look into using the old value for non-thumb1 code of
     399             :     // 4095 based on the TargetMachine, but this starts to become
     400             :     // tricky when doing code gen per function.
     401        4593 :     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
     402        4593 :                                (EnableGlobalMerge == cl::BOU_UNSET);
     403             :     // Merging of extern globals is enabled by default on non-Mach-O as we
     404             :     // expect it to be generally either beneficial or harmless. On Mach-O it
     405             :     // is disabled as we emit the .subsections_via_symbols directive which
     406             :     // means that merging extern globals is not safe.
     407        2321 :     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
     408        2321 :     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
     409             :                                   MergeExternalByDefault));
     410             :   }
     411             : 
     412        2575 :   return false;
     413             : }
     414             : 
     415        2551 : bool ARMPassConfig::addInstSelector() {
     416        5102 :   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
     417        2551 :   return false;
     418             : }
     419             : 
     420          29 : bool ARMPassConfig::addIRTranslator() {
     421          29 :   addPass(new IRTranslator());
     422          29 :   return false;
     423             : }
     424             : 
     425          29 : bool ARMPassConfig::addLegalizeMachineIR() {
     426          29 :   addPass(new Legalizer());
     427          29 :   return false;
     428             : }
     429             : 
     430          29 : bool ARMPassConfig::addRegBankSelect() {
     431          29 :   addPass(new RegBankSelect());
     432          29 :   return false;
     433             : }
     434             : 
     435          29 : bool ARMPassConfig::addGlobalInstructionSelect() {
     436          29 :   addPass(new InstructionSelect());
     437          29 :   return false;
     438             : }
     439             : 
     440        2575 : void ARMPassConfig::addPreRegAlloc() {
     441        2575 :   if (getOptLevel() != CodeGenOpt::None) {
     442        2322 :     addPass(createMLxExpansionPass());
     443             : 
     444        2322 :     if (EnableARMLoadStoreOpt)
     445        2322 :       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
     446             : 
     447        2322 :     if (!DisableA15SDOptimization)
     448        2321 :       addPass(createA15SDOptimizerPass());
     449             :   }
     450        2575 : }
     451             : 
     452        2575 : void ARMPassConfig::addPreSched2() {
     453        2575 :   if (getOptLevel() != CodeGenOpt::None) {
     454        2322 :     if (EnableARMLoadStoreOpt)
     455        2322 :       addPass(createARMLoadStoreOptimizationPass());
     456             : 
     457        4644 :     addPass(new ARMExecutionDepsFix());
     458             :   }
     459             : 
     460             :   // Expand some pseudo instructions into multiple instructions to allow
     461             :   // proper scheduling.
     462        2575 :   addPass(createARMExpandPseudoPass());
     463             : 
     464        2575 :   if (getOptLevel() != CodeGenOpt::None) {
     465             :     // in v8, IfConversion depends on Thumb instruction widths
     466       17815 :     addPass(createThumb2SizeReductionPass([this](const Function &F) {
     467       21698 :       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
     468             :     }));
     469             : 
     470        6966 :     addPass(createIfConverter([](const MachineFunction &MF) {
     471             :       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
     472       10843 :     }));
     473             :   }
     474        2575 :   addPass(createThumb2ITBlockPass());
     475        2575 : }
     476             : 
     477        2575 : void ARMPassConfig::addPreEmitPass() {
     478        7725 :   addPass(createThumb2SizeReductionPass());
     479             : 
     480             :   // Constant island pass work on unbundled instructions.
     481        7725 :   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
     482             :     return MF.getSubtarget<ARMSubtarget>().isThumb2();
     483             :   }));
     484             : 
     485             :   // Don't optimize barriers at -O0.
     486        2575 :   if (getOptLevel() != CodeGenOpt::None)
     487        2322 :     addPass(createARMOptimizeBarriersPass());
     488             : 
     489        2575 :   addPass(createARMConstantIslandPass());
     490      219493 : }

Generated by: LCOV version 1.13