LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMTargetMachine.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 197 199 99.0 %
Date: 2018-06-17 00:07:59 Functions: 31 33 93.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : //
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "ARMTargetMachine.h"
      14             : #include "ARM.h"
      15             : #include "ARMMacroFusion.h"
      16             : #include "ARMSubtarget.h"
      17             : #include "ARMTargetObjectFile.h"
      18             : #include "ARMTargetTransformInfo.h"
      19             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      20             : #include "llvm/ADT/Optional.h"
      21             : #include "llvm/ADT/STLExtras.h"
      22             : #include "llvm/ADT/StringRef.h"
      23             : #include "llvm/ADT/Triple.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/CodeGen/ExecutionDomainFix.h"
      26             : #include "llvm/CodeGen/GlobalISel/CallLowering.h"
      27             : #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
      28             : #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
      29             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      30             : #include "llvm/CodeGen/GlobalISel/Legalizer.h"
      31             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      32             : #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
      33             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      34             : #include "llvm/CodeGen/MachineFunction.h"
      35             : #include "llvm/CodeGen/MachineScheduler.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/CodeGen/TargetPassConfig.h"
      38             : #include "llvm/IR/Attributes.h"
      39             : #include "llvm/IR/DataLayout.h"
      40             : #include "llvm/IR/Function.h"
      41             : #include "llvm/Pass.h"
      42             : #include "llvm/Support/CodeGen.h"
      43             : #include "llvm/Support/CommandLine.h"
      44             : #include "llvm/Support/ErrorHandling.h"
      45             : #include "llvm/Support/TargetParser.h"
      46             : #include "llvm/Support/TargetRegistry.h"
      47             : #include "llvm/Target/TargetLoweringObjectFile.h"
      48             : #include "llvm/Target/TargetOptions.h"
      49             : #include "llvm/Transforms/Scalar.h"
      50             : #include <cassert>
      51             : #include <memory>
      52             : #include <string>
      53             : 
      54             : using namespace llvm;
      55             : 
      56             : static cl::opt<bool>
      57      101169 : DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
      58      101169 :                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
      59      303507 :                    cl::init(false));
      60             : 
      61             : static cl::opt<bool>
      62      101169 : EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
      63      101169 :                  cl::desc("Run SimplifyCFG after expanding atomic operations"
      64             :                           " to make use of cmpxchg flow-based information"),
      65      303507 :                  cl::init(true));
      66             : 
      67             : static cl::opt<bool>
      68      101169 : EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
      69      101169 :                       cl::desc("Enable ARM load/store optimization pass"),
      70      303507 :                       cl::init(true));
      71             : 
      72             : // FIXME: Unify control over GlobalMerge.
      73             : static cl::opt<cl::boolOrDefault>
      74      101169 : EnableGlobalMerge("arm-global-merge", cl::Hidden,
      75      101169 :                   cl::desc("Enable the global merge pass"));
      76             : 
      77             : namespace llvm {
      78             :   void initializeARMExecutionDomainFixPass(PassRegistry&);
      79             : }
      80             : 
      81      102206 : extern "C" void LLVMInitializeARMTarget() {
      82             :   // Register the target.
      83      102206 :   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
      84      102206 :   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
      85      102206 :   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
      86      102206 :   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
      87             : 
      88      102206 :   PassRegistry &Registry = *PassRegistry::getPassRegistry();
      89      102206 :   initializeGlobalISel(Registry);
      90      102206 :   initializeARMLoadStoreOptPass(Registry);
      91      102206 :   initializeARMPreAllocLoadStoreOptPass(Registry);
      92      102206 :   initializeARMConstantIslandsPass(Registry);
      93      102206 :   initializeARMExecutionDomainFixPass(Registry);
      94      102206 :   initializeARMExpandPseudoPass(Registry);
      95      102206 :   initializeThumb2SizeReducePass(Registry);
      96      102206 : }
      97             : 
      98        3293 : static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
      99        3293 :   if (TT.isOSBinFormatMachO())
     100             :     return llvm::make_unique<TargetLoweringObjectFileMachO>();
     101        2356 :   if (TT.isOSWindows())
     102         248 :     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
     103        4464 :   return llvm::make_unique<ARMElfTargetObjectFile>();
     104             : }
     105             : 
     106             : static ARMBaseTargetMachine::ARMABI
     107        6586 : computeTargetABI(const Triple &TT, StringRef CPU,
     108             :                  const TargetOptions &Options) {
     109        6586 :   StringRef ABIName = Options.MCOptions.getABIName();
     110             : 
     111        6586 :   if (ABIName.empty())
     112        6370 :     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
     113             : 
     114             :   if (ABIName == "aapcs16")
     115             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
     116             :   else if (ABIName.startswith("aapcs"))
     117             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
     118             :   else if (ABIName.startswith("apcs"))
     119             :     return ARMBaseTargetMachine::ARM_ABI_APCS;
     120             : 
     121           0 :   llvm_unreachable("Unhandled/unknown ABI Name!");
     122             :   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
     123             : }
     124             : 
     125        3293 : static std::string computeDataLayout(const Triple &TT, StringRef CPU,
     126             :                                      const TargetOptions &Options,
     127             :                                      bool isLittle) {
     128        3293 :   auto ABI = computeTargetABI(TT, CPU, Options);
     129             :   std::string Ret;
     130             : 
     131        3293 :   if (isLittle)
     132             :     // Little endian.
     133             :     Ret += "e";
     134             :   else
     135             :     // Big endian.
     136             :     Ret += "E";
     137             : 
     138        3293 :   Ret += DataLayout::getManglingComponent(TT);
     139             : 
     140             :   // Pointers are 32 bits and aligned to 32 bits.
     141             :   Ret += "-p:32:32";
     142             : 
     143             :   // ABIs other than APCS have 64 bit integers with natural alignment.
     144        3293 :   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
     145             :     Ret += "-i64:64";
     146             : 
     147             :   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
     148             :   // bits, others to 64 bits. We always try to align to 64 bits.
     149        3293 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     150             :     Ret += "-f64:32:64";
     151             : 
     152             :   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
     153             :   // to 64. We always ty to give them natural alignment.
     154        3293 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     155             :     Ret += "-v64:32:64-v128:32:128";
     156        2441 :   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     157             :     Ret += "-v128:64:128";
     158             : 
     159             :   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
     160             :   // particular hardware support on 32-bit ARM).
     161             :   Ret += "-a:0:32";
     162             : 
     163             :   // Integer registers are 32 bits.
     164             :   Ret += "-n32";
     165             : 
     166             :   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
     167             :   // aligned everywhere else.
     168        3293 :   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     169             :     Ret += "-S128";
     170        3255 :   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
     171             :     Ret += "-S64";
     172             :   else
     173             :     Ret += "-S32";
     174             : 
     175        3293 :   return Ret;
     176             : }
     177             : 
     178             : static Reloc::Model getEffectiveRelocModel(const Triple &TT,
     179             :                                            Optional<Reloc::Model> RM) {
     180        3293 :   if (!RM.hasValue())
     181             :     // Default relocation model on Darwin is PIC.
     182        2592 :     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
     183             : 
     184             :   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
     185             :     assert(TT.isOSBinFormatELF() &&
     186             :            "ROPI/RWPI currently only supported for ELF");
     187             : 
     188             :   // DynamicNoPIC is only used on darwin.
     189         701 :   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
     190             :     return Reloc::Static;
     191             : 
     192             :   return *RM;
     193             : }
     194             : 
     195             : static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
     196        3293 :   if (CM)
     197             :     return *CM;
     198             :   return CodeModel::Small;
     199             : }
     200             : 
     201             : /// Create an ARM architecture model.
     202             : ///
     203        3293 : ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
     204             :                                            StringRef CPU, StringRef FS,
     205             :                                            const TargetOptions &Options,
     206             :                                            Optional<Reloc::Model> RM,
     207             :                                            Optional<CodeModel::Model> CM,
     208        3293 :                                            CodeGenOpt::Level OL, bool isLittle)
     209        6586 :     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
     210             :                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
     211             :                         getEffectiveCodeModel(CM), OL),
     212        3293 :       TargetABI(computeTargetABI(TT, CPU, Options)),
     213       16465 :       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
     214             : 
     215             :   // Default to triple-appropriate float ABI
     216        3293 :   if (Options.FloatABIType == FloatABI::Default) {
     217        6141 :     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     218        3001 :         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
     219        2955 :         TargetTriple.getEnvironment() == Triple::EABIHF ||
     220        5966 :         TargetTriple.isOSWindows() ||
     221        2832 :         TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     222         333 :       this->Options.FloatABIType = FloatABI::Hard;
     223             :     else
     224        2801 :       this->Options.FloatABIType = FloatABI::Soft;
     225             :   }
     226             : 
     227             :   // Default to triple-appropriate EABI
     228        3293 :   if (Options.EABIVersion == EABI::Default ||
     229             :       Options.EABIVersion == EABI::Unknown) {
     230             :     // musl is compatible with glibc with regard to EABI version
     231        5901 :     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
     232        2504 :          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     233        2488 :          TargetTriple.getEnvironment() == Triple::MuslEABI ||
     234        4017 :          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
     235             :         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
     236         768 :       this->Options.EABIVersion = EABI::GNU;
     237             :     else
     238        2481 :       this->Options.EABIVersion = EABI::EABI5;
     239             :   }
     240             : 
     241        3293 :   if (TT.isOSBinFormatMachO())
     242         937 :     this->Options.TrapUnreachable = true;
     243             : 
     244        3293 :   initAsmInfo();
     245        3293 : }
     246             : 
     247             : ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
     248             : 
     249             : const ARMSubtarget *
     250      262279 : ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
     251      262279 :   Attribute CPUAttr = F.getFnAttribute("target-cpu");
     252      262279 :   Attribute FSAttr = F.getFnAttribute("target-features");
     253             : 
     254      262279 :   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
     255      316706 :                         ? CPUAttr.getValueAsString().str()
     256      262279 :                         : TargetCPU;
     257      262279 :   std::string FS = !FSAttr.hasAttribute(Attribute::None)
     258      375439 :                        ? FSAttr.getValueAsString().str()
     259      262279 :                        : TargetFS;
     260             : 
     261             :   // FIXME: This is related to the code below to reset the target options,
     262             :   // we need to know whether or not the soft float flag is set on the
     263             :   // function before we can generate a subtarget. We also need to use
     264             :   // it as a key for the subtarget since that can be the only difference
     265             :   // between two functions.
     266             :   bool SoftFloat =
     267      524324 :       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
     268             :   // If the soft float attribute is set on the function turn on the soft float
     269             :   // subtarget feature.
     270             :   if (SoftFloat)
     271         234 :     FS += FS.empty() ? "+soft-float" : ",+soft-float";
     272             : 
     273      786837 :   auto &I = SubtargetMap[CPU + FS];
     274      262279 :   if (!I) {
     275             :     // This needs to be done before we create a new subtarget since any
     276             :     // creation will depend on the TM and the code generation flags on the
     277             :     // function that reside in TargetOptions.
     278        2925 :     resetTargetOptions(F);
     279        2925 :     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
     280             : 
     281        2925 :     if (!I->isThumb() && !I->hasARMOps())
     282           9 :       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
     283           3 :           "instructions, but the target does not support ARM mode execution.");
     284             :   }
     285             : 
     286      262279 :   return I.get();
     287             : }
     288             : 
     289             : TargetTransformInfo
     290      122662 : ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
     291      122662 :   return TargetTransformInfo(ARMTTIImpl(this, F));
     292             : }
     293             : 
     294        3247 : ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
     295             :                                        StringRef CPU, StringRef FS,
     296             :                                        const TargetOptions &Options,
     297             :                                        Optional<Reloc::Model> RM,
     298             :                                        Optional<CodeModel::Model> CM,
     299        3247 :                                        CodeGenOpt::Level OL, bool JIT)
     300        6494 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
     301             : 
     302          46 : ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
     303             :                                        StringRef CPU, StringRef FS,
     304             :                                        const TargetOptions &Options,
     305             :                                        Optional<Reloc::Model> RM,
     306             :                                        Optional<CodeModel::Model> CM,
     307          46 :                                        CodeGenOpt::Level OL, bool JIT)
     308          92 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
     309             : 
     310             : namespace {
     311             : 
     312             : /// ARM Code Generator Pass Configuration Options.
     313        2914 : class ARMPassConfig : public TargetPassConfig {
     314             : public:
     315        2941 :   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
     316        2941 :       : TargetPassConfig(TM, PM) {
     317        2941 :     if (TM.getOptLevel() != CodeGenOpt::None) {
     318             :       ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
     319        2529 :                               TM.getTargetFeatureString());
     320        2529 :       if (STI.hasFeature(ARM::FeatureUseMISched))
     321          84 :         substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
     322             :     }
     323        2941 :   }
     324             : 
     325             :   ARMBaseTargetMachine &getARMTargetMachine() const {
     326        2700 :     return getTM<ARMBaseTargetMachine>();
     327             :   }
     328             : 
     329             :   ScheduleDAGInstrs *
     330         272 :   createMachineScheduler(MachineSchedContext *C) const override {
     331         272 :     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
     332             :     // add DAG Mutations here.
     333         272 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     334         272 :     if (ST.hasFusion())
     335           6 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     336         272 :     return DAG;
     337             :   }
     338             : 
     339             :   ScheduleDAGInstrs *
     340           6 :   createPostMachineScheduler(MachineSchedContext *C) const override {
     341           6 :     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
     342             :     // add DAG Mutations here.
     343           6 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     344           6 :     if (ST.hasFusion())
     345           0 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     346           6 :     return DAG;
     347             :   }
     348             : 
     349             :   void addIRPasses() override;
     350             :   bool addPreISel() override;
     351             :   bool addInstSelector() override;
     352             :   bool addIRTranslator() override;
     353             :   bool addLegalizeMachineIR() override;
     354             :   bool addRegBankSelect() override;
     355             :   bool addGlobalInstructionSelect() override;
     356             :   void addPreRegAlloc() override;
     357             :   void addPreSched2() override;
     358             :   void addPreEmitPass() override;
     359             : };
     360             : 
     361        2441 : class ARMExecutionDomainFix : public ExecutionDomainFix {
     362             : public:
     363             :   static char ID;
     364        2468 :   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
     365        2456 :   StringRef getPassName() const override {
     366        2456 :     return "ARM Execution Domain Fix";
     367             :   }
     368             : };
     369             : char ARMExecutionDomainFix::ID;
     370             : 
     371             : } // end anonymous namespace
     372             : 
     373       76336 : INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
     374             :   "ARM Execution Domain Fix", false, false)
     375       76336 : INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
     376      357084 : INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
     377             :   "ARM Execution Domain Fix", false, false)
     378             : 
     379        2941 : TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
     380        2941 :   return new ARMPassConfig(*this, PM);
     381             : }
     382             : 
     383        2728 : void ARMPassConfig::addIRPasses() {
     384        2728 :   if (TM->Options.ThreadModel == ThreadModel::Single)
     385           1 :     addPass(createLowerAtomicPass());
     386             :   else
     387        2727 :     addPass(createAtomicExpandPass());
     388             : 
     389             :   // Cmpxchg instructions are often used with a subsequent comparison to
     390             :   // determine whether it succeeded. We can exploit existing control-flow in
     391             :   // ldrex/strex loops to simplify this, but it needs tidying up.
     392        5196 :   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
     393        7239 :     addPass(createCFGSimplificationPass(
     394       12412 :         1, false, false, true, true, [this](const Function &F) {
     395       12412 :           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
     396       20244 :           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
     397             :         }));
     398             : 
     399        2728 :   TargetPassConfig::addIRPasses();
     400             : 
     401             :   // Match interleaved memory accesses to ldN/stN intrinsics.
     402        2728 :   if (TM->getOptLevel() != CodeGenOpt::None)
     403        2468 :     addPass(createInterleavedAccessPass());
     404        2728 : }
     405             : 
     406        2728 : bool ARMPassConfig::addPreISel() {
     407        5196 :   if ((TM->getOptLevel() != CodeGenOpt::None &&
     408        3005 :        EnableGlobalMerge == cl::BOU_UNSET) ||
     409             :       EnableGlobalMerge == cl::BOU_TRUE) {
     410             :     // FIXME: This is using the thumb1 only constant value for
     411             :     // maximal global offset for merging globals. We may want
     412             :     // to look into using the old value for non-thumb1 code of
     413             :     // 4095 based on the TargetMachine, but this starts to become
     414             :     // tricky when doing code gen per function.
     415        4880 :     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
     416             :                                (EnableGlobalMerge == cl::BOU_UNSET);
     417             :     // Merging of extern globals is enabled by default on non-Mach-O as we
     418             :     // expect it to be generally either beneficial or harmless. On Mach-O it
     419             :     // is disabled as we emit the .subsections_via_symbols directive which
     420             :     // means that merging extern globals is not safe.
     421        4934 :     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
     422        2467 :     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
     423             :                                   MergeExternalByDefault));
     424             :   }
     425             : 
     426        2728 :   return false;
     427             : }
     428             : 
     429        2700 : bool ARMPassConfig::addInstSelector() {
     430        5400 :   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
     431        2700 :   return false;
     432             : }
     433             : 
     434          35 : bool ARMPassConfig::addIRTranslator() {
     435          35 :   addPass(new IRTranslator());
     436          35 :   return false;
     437             : }
     438             : 
     439          35 : bool ARMPassConfig::addLegalizeMachineIR() {
     440          35 :   addPass(new Legalizer());
     441          35 :   return false;
     442             : }
     443             : 
     444          35 : bool ARMPassConfig::addRegBankSelect() {
     445          35 :   addPass(new RegBankSelect());
     446          35 :   return false;
     447             : }
     448             : 
     449          35 : bool ARMPassConfig::addGlobalInstructionSelect() {
     450          35 :   addPass(new InstructionSelect());
     451          35 :   return false;
     452             : }
     453             : 
     454        2728 : void ARMPassConfig::addPreRegAlloc() {
     455        2728 :   if (getOptLevel() != CodeGenOpt::None) {
     456        2468 :     addPass(createMLxExpansionPass());
     457             : 
     458        2468 :     if (EnableARMLoadStoreOpt)
     459        2468 :       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
     460             : 
     461        2468 :     if (!DisableA15SDOptimization)
     462        2467 :       addPass(createA15SDOptimizerPass());
     463             :   }
     464        2728 : }
     465             : 
     466        2728 : void ARMPassConfig::addPreSched2() {
     467        2728 :   if (getOptLevel() != CodeGenOpt::None) {
     468        2468 :     if (EnableARMLoadStoreOpt)
     469        2468 :       addPass(createARMLoadStoreOptimizationPass());
     470             : 
     471        4936 :     addPass(new ARMExecutionDomainFix());
     472        2468 :     addPass(createBreakFalseDeps());
     473             :   }
     474             : 
     475             :   // Expand some pseudo instructions into multiple instructions to allow
     476             :   // proper scheduling.
     477        2728 :   addPass(createARMExpandPseudoPass());
     478             : 
     479        2728 :   if (getOptLevel() != CodeGenOpt::None) {
     480             :     // in v8, IfConversion depends on Thumb instruction widths
     481       17359 :     addPass(createThumb2SizeReductionPass([this](const Function &F) {
     482       12423 :       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
     483       12423 :     }));
     484             : 
     485        4936 :     addPass(createIfConverter([](const MachineFunction &MF) {
     486       12417 :       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
     487       12417 :     }));
     488             :   }
     489        2728 :   addPass(createThumb2ITBlockPass());
     490        2728 : }
     491             : 
     492        2728 : void ARMPassConfig::addPreEmitPass() {
     493        8184 :   addPass(createThumb2SizeReductionPass());
     494             : 
     495             :   // Constant island pass work on unbundled instructions.
     496        5456 :   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
     497       13634 :     return MF.getSubtarget<ARMSubtarget>().isThumb2();
     498       13634 :   }));
     499             : 
     500             :   // Don't optimize barriers at -O0.
     501        2728 :   if (getOptLevel() != CodeGenOpt::None)
     502        2468 :     addPass(createARMOptimizeBarriersPass());
     503             : 
     504        2728 :   addPass(createARMConstantIslandPass());
     505      306235 : }

Generated by: LCOV version 1.13