LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMTargetMachine.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 195 197 99.0 %
Date: 2018-02-23 15:42:53 Functions: 31 33 93.9 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMTargetMachine.cpp - Define TargetMachine for ARM ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : //
      11             : //===----------------------------------------------------------------------===//
      12             : 
      13             : #include "ARMTargetMachine.h"
      14             : #include "ARM.h"
      15             : #include "ARMMacroFusion.h"
      16             : #include "ARMSubtarget.h"
      17             : #include "ARMTargetObjectFile.h"
      18             : #include "ARMTargetTransformInfo.h"
      19             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      20             : #include "llvm/ADT/Optional.h"
      21             : #include "llvm/ADT/STLExtras.h"
      22             : #include "llvm/ADT/StringRef.h"
      23             : #include "llvm/ADT/Triple.h"
      24             : #include "llvm/Analysis/TargetTransformInfo.h"
      25             : #include "llvm/CodeGen/ExecutionDomainFix.h"
      26             : #include "llvm/CodeGen/GlobalISel/CallLowering.h"
      27             : #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
      28             : #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
      29             : #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
      30             : #include "llvm/CodeGen/GlobalISel/Legalizer.h"
      31             : #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
      32             : #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
      33             : #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
      34             : #include "llvm/CodeGen/MachineFunction.h"
      35             : #include "llvm/CodeGen/MachineScheduler.h"
      36             : #include "llvm/CodeGen/Passes.h"
      37             : #include "llvm/CodeGen/TargetLoweringObjectFile.h"
      38             : #include "llvm/CodeGen/TargetPassConfig.h"
      39             : #include "llvm/IR/Attributes.h"
      40             : #include "llvm/IR/DataLayout.h"
      41             : #include "llvm/IR/Function.h"
      42             : #include "llvm/Pass.h"
      43             : #include "llvm/Support/CodeGen.h"
      44             : #include "llvm/Support/CommandLine.h"
      45             : #include "llvm/Support/ErrorHandling.h"
      46             : #include "llvm/Support/TargetParser.h"
      47             : #include "llvm/Support/TargetRegistry.h"
      48             : #include "llvm/Target/TargetOptions.h"
      49             : #include "llvm/Transforms/Scalar.h"
      50             : #include <cassert>
      51             : #include <memory>
      52             : #include <string>
      53             : 
      54             : using namespace llvm;
      55             : 
      56             : static cl::opt<bool>
      57       81686 : DisableA15SDOptimization("disable-a15-sd-optimization", cl::Hidden,
      58       81686 :                    cl::desc("Inhibit optimization of S->D register accesses on A15"),
      59      245058 :                    cl::init(false));
      60             : 
      61             : static cl::opt<bool>
      62       81686 : EnableAtomicTidy("arm-atomic-cfg-tidy", cl::Hidden,
      63       81686 :                  cl::desc("Run SimplifyCFG after expanding atomic operations"
      64             :                           " to make use of cmpxchg flow-based information"),
      65      245058 :                  cl::init(true));
      66             : 
      67             : static cl::opt<bool>
      68       81686 : EnableARMLoadStoreOpt("arm-load-store-opt", cl::Hidden,
      69       81686 :                       cl::desc("Enable ARM load/store optimization pass"),
      70      245058 :                       cl::init(true));
      71             : 
      72             : // FIXME: Unify control over GlobalMerge.
      73             : static cl::opt<cl::boolOrDefault>
      74       81686 : EnableGlobalMerge("arm-global-merge", cl::Hidden,
      75       81686 :                   cl::desc("Enable the global merge pass"));
      76             : 
      77             : namespace llvm {
      78             :   void initializeARMExecutionDomainFixPass(PassRegistry&);
      79             : }
      80             : 
      81       80426 : extern "C" void LLVMInitializeARMTarget() {
      82             :   // Register the target.
      83       80426 :   RegisterTargetMachine<ARMLETargetMachine> X(getTheARMLETarget());
      84       80426 :   RegisterTargetMachine<ARMLETargetMachine> A(getTheThumbLETarget());
      85       80426 :   RegisterTargetMachine<ARMBETargetMachine> Y(getTheARMBETarget());
      86       80426 :   RegisterTargetMachine<ARMBETargetMachine> B(getTheThumbBETarget());
      87             : 
      88       80426 :   PassRegistry &Registry = *PassRegistry::getPassRegistry();
      89       80426 :   initializeGlobalISel(Registry);
      90       80426 :   initializeARMLoadStoreOptPass(Registry);
      91       80426 :   initializeARMPreAllocLoadStoreOptPass(Registry);
      92       80426 :   initializeARMConstantIslandsPass(Registry);
      93       80426 :   initializeARMExecutionDomainFixPass(Registry);
      94       80426 :   initializeARMExpandPseudoPass(Registry);
      95       80426 :   initializeThumb2SizeReducePass(Registry);
      96       80426 : }
      97             : 
      98        3202 : static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
      99        3202 :   if (TT.isOSBinFormatMachO())
     100             :     return llvm::make_unique<TargetLoweringObjectFileMachO>();
     101        2272 :   if (TT.isOSWindows())
     102         240 :     return llvm::make_unique<TargetLoweringObjectFileCOFF>();
     103        4304 :   return llvm::make_unique<ARMElfTargetObjectFile>();
     104             : }
     105             : 
     106             : static ARMBaseTargetMachine::ARMABI
     107        6404 : computeTargetABI(const Triple &TT, StringRef CPU,
     108             :                  const TargetOptions &Options) {
     109        6404 :   StringRef ABIName = Options.MCOptions.getABIName();
     110             : 
     111        6404 :   if (ABIName.empty())
     112        6190 :     ABIName = ARM::computeDefaultTargetABI(TT, CPU);
     113             : 
     114             :   if (ABIName == "aapcs16")
     115             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS16;
     116             :   else if (ABIName.startswith("aapcs"))
     117             :     return ARMBaseTargetMachine::ARM_ABI_AAPCS;
     118             :   else if (ABIName.startswith("apcs"))
     119             :     return ARMBaseTargetMachine::ARM_ABI_APCS;
     120             : 
     121           0 :   llvm_unreachable("Unhandled/unknown ABI Name!");
     122             :   return ARMBaseTargetMachine::ARM_ABI_UNKNOWN;
     123             : }
     124             : 
     125        3202 : static std::string computeDataLayout(const Triple &TT, StringRef CPU,
     126             :                                      const TargetOptions &Options,
     127             :                                      bool isLittle) {
     128        3202 :   auto ABI = computeTargetABI(TT, CPU, Options);
     129             :   std::string Ret;
     130             : 
     131        3202 :   if (isLittle)
     132             :     // Little endian.
     133             :     Ret += "e";
     134             :   else
     135             :     // Big endian.
     136             :     Ret += "E";
     137             : 
     138        3202 :   Ret += DataLayout::getManglingComponent(TT);
     139             : 
     140             :   // Pointers are 32 bits and aligned to 32 bits.
     141             :   Ret += "-p:32:32";
     142             : 
     143             :   // ABIs other than APCS have 64 bit integers with natural alignment.
     144        3202 :   if (ABI != ARMBaseTargetMachine::ARM_ABI_APCS)
     145             :     Ret += "-i64:64";
     146             : 
     147             :   // We have 64 bits floats. The APCS ABI requires them to be aligned to 32
     148             :   // bits, others to 64 bits. We always try to align to 64 bits.
     149        3202 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     150             :     Ret += "-f64:32:64";
     151             : 
     152             :   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
     153             :   // to 64. We always ty to give them natural alignment.
     154        3202 :   if (ABI == ARMBaseTargetMachine::ARM_ABI_APCS)
     155             :     Ret += "-v64:32:64-v128:32:128";
     156        2355 :   else if (ABI != ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     157             :     Ret += "-v128:64:128";
     158             : 
     159             :   // Try to align aggregates to 32 bits (the default is 64 bits, which has no
     160             :   // particular hardware support on 32-bit ARM).
     161             :   Ret += "-a:0:32";
     162             : 
     163             :   // Integer registers are 32 bits.
     164             :   Ret += "-n32";
     165             : 
     166             :   // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
     167             :   // aligned everywhere else.
     168        3202 :   if (TT.isOSNaCl() || ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     169             :     Ret += "-S128";
     170        3165 :   else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
     171             :     Ret += "-S64";
     172             :   else
     173             :     Ret += "-S32";
     174             : 
     175        3202 :   return Ret;
     176             : }
     177             : 
     178             : static Reloc::Model getEffectiveRelocModel(const Triple &TT,
     179             :                                            Optional<Reloc::Model> RM) {
     180        3202 :   if (!RM.hasValue())
     181             :     // Default relocation model on Darwin is PIC.
     182        2530 :     return TT.isOSBinFormatMachO() ? Reloc::PIC_ : Reloc::Static;
     183             : 
     184             :   if (*RM == Reloc::ROPI || *RM == Reloc::RWPI || *RM == Reloc::ROPI_RWPI)
     185             :     assert(TT.isOSBinFormatELF() &&
     186             :            "ROPI/RWPI currently only supported for ELF");
     187             : 
     188             :   // DynamicNoPIC is only used on darwin.
     189         672 :   if (*RM == Reloc::DynamicNoPIC && !TT.isOSDarwin())
     190             :     return Reloc::Static;
     191             : 
     192             :   return *RM;
     193             : }
     194             : 
     195             : static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
     196        3202 :   if (CM)
     197             :     return *CM;
     198             :   return CodeModel::Small;
     199             : }
     200             : 
     201             : /// Create an ARM architecture model.
     202             : ///
     203        3202 : ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
     204             :                                            StringRef CPU, StringRef FS,
     205             :                                            const TargetOptions &Options,
     206             :                                            Optional<Reloc::Model> RM,
     207             :                                            Optional<CodeModel::Model> CM,
     208        3202 :                                            CodeGenOpt::Level OL, bool isLittle)
     209        6404 :     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
     210             :                         CPU, FS, Options, getEffectiveRelocModel(TT, RM),
     211             :                         getEffectiveCodeModel(CM), OL),
     212        3202 :       TargetABI(computeTargetABI(TT, CPU, Options)),
     213       16010 :       TLOF(createTLOF(getTargetTriple())), isLittle(isLittle) {
     214             : 
     215             :   // Default to triple-appropriate float ABI
     216        3202 :   if (Options.FloatABIType == FloatABI::Default) {
     217        5972 :     if (TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     218        2919 :         TargetTriple.getEnvironment() == Triple::MuslEABIHF ||
     219        2873 :         TargetTriple.getEnvironment() == Triple::EABIHF ||
     220        5802 :         TargetTriple.isOSWindows() ||
     221        2755 :         TargetABI == ARMBaseTargetMachine::ARM_ABI_AAPCS16)
     222         322 :       this->Options.FloatABIType = FloatABI::Hard;
     223             :     else
     224        2725 :       this->Options.FloatABIType = FloatABI::Soft;
     225             :   }
     226             : 
     227             :   // Default to triple-appropriate EABI
     228        3202 :   if (Options.EABIVersion == EABI::Default ||
     229             :       Options.EABIVersion == EABI::Unknown) {
     230             :     // musl is compatible with glibc with regard to EABI version
     231        5748 :     if ((TargetTriple.getEnvironment() == Triple::GNUEABI ||
     232        2447 :          TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
     233        2431 :          TargetTriple.getEnvironment() == Triple::MuslEABI ||
     234        3892 :          TargetTriple.getEnvironment() == Triple::MuslEABIHF) &&
     235             :         !(TargetTriple.isOSWindows() || TargetTriple.isOSDarwin()))
     236         734 :       this->Options.EABIVersion = EABI::GNU;
     237             :     else
     238        2424 :       this->Options.EABIVersion = EABI::EABI5;
     239             :   }
     240             : 
     241        3202 :   initAsmInfo();
     242        3202 : }
     243             : 
     244             : ARMBaseTargetMachine::~ARMBaseTargetMachine() = default;
     245             : 
     246             : const ARMSubtarget *
     247      235487 : ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
     248      235487 :   Attribute CPUAttr = F.getFnAttribute("target-cpu");
     249      235487 :   Attribute FSAttr = F.getFnAttribute("target-features");
     250             : 
     251      235487 :   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
     252      286030 :                         ? CPUAttr.getValueAsString().str()
     253      235487 :                         : TargetCPU;
     254      235487 :   std::string FS = !FSAttr.hasAttribute(Attribute::None)
     255      337244 :                        ? FSAttr.getValueAsString().str()
     256      235487 :                        : TargetFS;
     257             : 
     258             :   // FIXME: This is related to the code below to reset the target options,
     259             :   // we need to know whether or not the soft float flag is set on the
     260             :   // function before we can generate a subtarget. We also need to use
     261             :   // it as a key for the subtarget since that can be the only difference
     262             :   // between two functions.
     263             :   bool SoftFloat =
     264      470810 :       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
     265             :   // If the soft float attribute is set on the function turn on the soft float
     266             :   // subtarget feature.
     267             :   if (SoftFloat)
     268         164 :     FS += FS.empty() ? "+soft-float" : ",+soft-float";
     269             : 
     270      706461 :   auto &I = SubtargetMap[CPU + FS];
     271      235487 :   if (!I) {
     272             :     // This needs to be done before we create a new subtarget since any
     273             :     // creation will depend on the TM and the code generation flags on the
     274             :     // function that reside in TargetOptions.
     275        2867 :     resetTargetOptions(F);
     276        2867 :     I = llvm::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle);
     277             : 
     278        2867 :     if (!I->isThumb() && !I->hasARMOps())
     279           9 :       F.getContext().emitError("Function '" + F.getName() + "' uses ARM "
     280           3 :           "instructions, but the target does not support ARM mode execution.");
     281             :   }
     282             : 
     283      235487 :   return I.get();
     284             : }
     285             : 
     286             : TargetTransformInfo
     287      101289 : ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) {
     288      101289 :   return TargetTransformInfo(ARMTTIImpl(this, F));
     289             : }
     290             : 
     291        3158 : ARMLETargetMachine::ARMLETargetMachine(const Target &T, const Triple &TT,
     292             :                                        StringRef CPU, StringRef FS,
     293             :                                        const TargetOptions &Options,
     294             :                                        Optional<Reloc::Model> RM,
     295             :                                        Optional<CodeModel::Model> CM,
     296        3158 :                                        CodeGenOpt::Level OL, bool JIT)
     297        6316 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
     298             : 
     299          44 : ARMBETargetMachine::ARMBETargetMachine(const Target &T, const Triple &TT,
     300             :                                        StringRef CPU, StringRef FS,
     301             :                                        const TargetOptions &Options,
     302             :                                        Optional<Reloc::Model> RM,
     303             :                                        Optional<CodeModel::Model> CM,
     304          44 :                                        CodeGenOpt::Level OL, bool JIT)
     305          88 :     : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
     306             : 
     307             : namespace {
     308             : 
     309             : /// ARM Code Generator Pass Configuration Options.
     310        2848 : class ARMPassConfig : public TargetPassConfig {
     311             : public:
     312        2875 :   ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
     313        2875 :       : TargetPassConfig(TM, PM) {
     314        2875 :     if (TM.getOptLevel() != CodeGenOpt::None) {
     315             :       ARMGenSubtargetInfo STI(TM.getTargetTriple(), TM.getTargetCPU(),
     316        2475 :                               TM.getTargetFeatureString());
     317        2475 :       if (STI.hasFeature(ARM::FeatureUseMISched))
     318          76 :         substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
     319             :     }
     320        2875 :   }
     321             : 
     322             :   ARMBaseTargetMachine &getARMTargetMachine() const {
     323        2647 :     return getTM<ARMBaseTargetMachine>();
     324             :   }
     325             : 
     326             :   ScheduleDAGInstrs *
     327         268 :   createMachineScheduler(MachineSchedContext *C) const override {
     328         268 :     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
     329             :     // add DAG Mutations here.
     330         268 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     331         268 :     if (ST.hasFusion())
     332           6 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     333         268 :     return DAG;
     334             :   }
     335             : 
     336             :   ScheduleDAGInstrs *
     337           2 :   createPostMachineScheduler(MachineSchedContext *C) const override {
     338           2 :     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
     339             :     // add DAG Mutations here.
     340           2 :     const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>();
     341           2 :     if (ST.hasFusion())
     342           0 :       DAG->addMutation(createARMMacroFusionDAGMutation());
     343           2 :     return DAG;
     344             :   }
     345             : 
     346             :   void addIRPasses() override;
     347             :   bool addPreISel() override;
     348             :   bool addInstSelector() override;
     349             :   bool addIRTranslator() override;
     350             :   bool addLegalizeMachineIR() override;
     351             :   bool addRegBankSelect() override;
     352             :   bool addGlobalInstructionSelect() override;
     353             :   void addPreRegAlloc() override;
     354             :   void addPreSched2() override;
     355             :   void addPreEmitPass() override;
     356             : };
     357             : 
     358        2389 : class ARMExecutionDomainFix : public ExecutionDomainFix {
     359             : public:
     360             :   static char ID;
     361        2416 :   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
     362        2404 :   StringRef getPassName() const override {
     363        2404 :     return "ARM Execution Domain Fix";
     364             :   }
     365             : };
     366             : char ARMExecutionDomainFix::ID;
     367             : 
     368             : } // end anonymous namespace
     369             : 
     370       59438 : INITIALIZE_PASS_BEGIN(ARMExecutionDomainFix, "arm-execution-domain-fix",
     371             :   "ARM Execution Domain Fix", false, false)
     372       59438 : INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
     373      279728 : INITIALIZE_PASS_END(ARMExecutionDomainFix, "arm-execution-domain-fix",
     374             :   "ARM Execution Domain Fix", false, false)
     375             : 
     376        2875 : TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
     377        2875 :   return new ARMPassConfig(*this, PM);
     378             : }
     379             : 
     380        2675 : void ARMPassConfig::addIRPasses() {
     381        2675 :   if (TM->Options.ThreadModel == ThreadModel::Single)
     382           1 :     addPass(createLowerAtomicPass());
     383             :   else
     384        2674 :     addPass(createAtomicExpandPass());
     385             : 
     386             :   // Cmpxchg instructions are often used with a subsequent comparison to
     387             :   // determine whether it succeeded. We can exploit existing control-flow in
     388             :   // ldrex/strex loops to simplify this, but it needs tidying up.
     389        5091 :   if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
     390        7083 :     addPass(createCFGSimplificationPass(
     391       11914 :         1, false, false, true, true, [this](const Function &F) {
     392       11914 :           const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F);
     393       19429 :           return ST.hasAnyDataBarrier() && !ST.isThumb1Only();
     394             :         }));
     395             : 
     396        2675 :   TargetPassConfig::addIRPasses();
     397             : 
     398             :   // Match interleaved memory accesses to ldN/stN intrinsics.
     399        2675 :   if (TM->getOptLevel() != CodeGenOpt::None)
     400        2416 :     addPass(createInterleavedAccessPass());
     401        2675 : }
     402             : 
     403        2675 : bool ARMPassConfig::addPreISel() {
     404        5091 :   if ((TM->getOptLevel() != CodeGenOpt::None &&
     405        2950 :        EnableGlobalMerge == cl::BOU_UNSET) ||
     406             :       EnableGlobalMerge == cl::BOU_TRUE) {
     407             :     // FIXME: This is using the thumb1 only constant value for
     408             :     // maximal global offset for merging globals. We may want
     409             :     // to look into using the old value for non-thumb1 code of
     410             :     // 4095 based on the TargetMachine, but this starts to become
     411             :     // tricky when doing code gen per function.
     412        4778 :     bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
     413             :                                (EnableGlobalMerge == cl::BOU_UNSET);
     414             :     // Merging of extern globals is enabled by default on non-Mach-O as we
     415             :     // expect it to be generally either beneficial or harmless. On Mach-O it
     416             :     // is disabled as we emit the .subsections_via_symbols directive which
     417             :     // means that merging extern globals is not safe.
     418        4830 :     bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
     419        2415 :     addPass(createGlobalMergePass(TM, 127, OnlyOptimizeForSize,
     420             :                                   MergeExternalByDefault));
     421             :   }
     422             : 
     423        2675 :   return false;
     424             : }
     425             : 
     426        2647 : bool ARMPassConfig::addInstSelector() {
     427        5294 :   addPass(createARMISelDag(getARMTargetMachine(), getOptLevel()));
     428        2647 :   return false;
     429             : }
     430             : 
     431          35 : bool ARMPassConfig::addIRTranslator() {
     432          35 :   addPass(new IRTranslator());
     433          35 :   return false;
     434             : }
     435             : 
     436          35 : bool ARMPassConfig::addLegalizeMachineIR() {
     437          35 :   addPass(new Legalizer());
     438          35 :   return false;
     439             : }
     440             : 
     441          35 : bool ARMPassConfig::addRegBankSelect() {
     442          35 :   addPass(new RegBankSelect());
     443          35 :   return false;
     444             : }
     445             : 
     446          35 : bool ARMPassConfig::addGlobalInstructionSelect() {
     447          35 :   addPass(new InstructionSelect());
     448          35 :   return false;
     449             : }
     450             : 
     451        2675 : void ARMPassConfig::addPreRegAlloc() {
     452        2675 :   if (getOptLevel() != CodeGenOpt::None) {
     453        2416 :     addPass(createMLxExpansionPass());
     454             : 
     455        2416 :     if (EnableARMLoadStoreOpt)
     456        2416 :       addPass(createARMLoadStoreOptimizationPass(/* pre-register alloc */ true));
     457             : 
     458        2416 :     if (!DisableA15SDOptimization)
     459        2415 :       addPass(createA15SDOptimizerPass());
     460             :   }
     461        2675 : }
     462             : 
     463        2675 : void ARMPassConfig::addPreSched2() {
     464        2675 :   if (getOptLevel() != CodeGenOpt::None) {
     465        2416 :     if (EnableARMLoadStoreOpt)
     466        2416 :       addPass(createARMLoadStoreOptimizationPass());
     467             : 
     468        4832 :     addPass(new ARMExecutionDomainFix());
     469        2416 :     addPass(createBreakFalseDeps());
     470             :   }
     471             : 
     472             :   // Expand some pseudo instructions into multiple instructions to allow
     473             :   // proper scheduling.
     474        2675 :   addPass(createARMExpandPseudoPass());
     475             : 
     476        2675 :   if (getOptLevel() != CodeGenOpt::None) {
     477             :     // in v8, IfConversion depends on Thumb instruction widths
     478       16757 :     addPass(createThumb2SizeReductionPass([this](const Function &F) {
     479       11925 :       return this->TM->getSubtarget<ARMSubtarget>(F).restrictIT();
     480       11925 :     }));
     481             : 
     482        4832 :     addPass(createIfConverter([](const MachineFunction &MF) {
     483       11919 :       return !MF.getSubtarget<ARMSubtarget>().isThumb1Only();
     484       11919 :     }));
     485             :   }
     486        2675 :   addPass(createThumb2ITBlockPass());
     487        2675 : }
     488             : 
     489        2675 : void ARMPassConfig::addPreEmitPass() {
     490        8025 :   addPass(createThumb2SizeReductionPass());
     491             : 
     492             :   // Constant island pass work on unbundled instructions.
     493        5350 :   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
     494       13114 :     return MF.getSubtarget<ARMSubtarget>().isThumb2();
     495       13114 :   }));
     496             : 
     497             :   // Don't optimize barriers at -O0.
     498        2675 :   if (getOptLevel() != CodeGenOpt::None)
     499        2416 :     addPass(createARMOptimizeBarriersPass());
     500             : 
     501        2675 :   addPass(createARMConstantIslandPass());
     502      247733 : }

Generated by: LCOV version 1.13