LCOV - code coverage report
Current view: top level - lib/Target/ARM - ARMTargetTransformInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 13 14 92.9 %
Date: 2017-09-14 15:23:50 Functions: 2 2 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : /// \file
      10             : /// This file a TargetTransformInfo::Concept conforming object specific to the
      11             : /// ARM target machine. It uses the target's detailed information to
      12             : /// provide more precise answers to certain TTI queries, while letting the
      13             : /// target independent and default TTI implementations handle the rest.
      14             : ///
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
      18             : #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
      19             : 
      20             : #include "ARM.h"
      21             : #include "ARMTargetMachine.h"
      22             : #include "llvm/Analysis/TargetTransformInfo.h"
      23             : #include "llvm/CodeGen/BasicTTIImpl.h"
      24             : #include "llvm/Target/TargetLowering.h"
      25             : 
      26             : namespace llvm {
      27             : 
      28      283124 : class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
      29             :   typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
      30             :   typedef TargetTransformInfo TTI;
      31             :   friend BaseT;
      32             : 
      33             :   const ARMSubtarget *ST;
      34             :   const ARMTargetLowering *TLI;
      35             : 
      36             :   // Currently the following features are excluded from InlineFeatureWhitelist.
      37             :   // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureVFPOnlySP, FeatureD16
      38             :   // Depending on whether they are set or unset, different
      39             :   // instructions/registers are available. For example, inlining a callee with
      40             :   // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
      41             :   // fail if the callee uses ARM only instructions, e.g. in inline asm.
      42             :   const FeatureBitset InlineFeatureWhitelist = {
      43             :       ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
      44             :       ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
      45             :       ARM::FeatureFullFP16, ARM::FeatureHWDivThumb,
      46             :       ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
      47             :       ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
      48             :       ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
      49             :       ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
      50             :       ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
      51             :       ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
      52             :       ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
      53             :       ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
      54             :       ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
      55             :       ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
      56             :       ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
      57             :       ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
      58             :       ARM::FeatureHasSlowFPVMLx, ARM::FeatureVMLxForwarding,
      59             :       ARM::FeaturePref32BitThumb, ARM::FeatureAvoidPartialCPSR,
      60             :       ARM::FeatureCheapPredicableCPSR, ARM::FeatureAvoidMOVsShOp,
      61             :       ARM::FeatureHasRetAddrStack, ARM::FeatureHasNoBranchPredictor,
      62             :       ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
      63             :       ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
      64             :       ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
      65             :       ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
      66             :       ARM::FeatureNoNegativeImmediates
      67             :   };
      68             : 
      69             :   const ARMSubtarget *getST() const { return ST; }
      70             :   const ARMTargetLowering *getTLI() const { return TLI; }
      71             : 
      72             : public:
      73       70781 :   explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
      74      141562 :       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
      75      212343 :         TLI(ST->getTargetLowering()) {}
      76             : 
      77             :   bool areInlineCompatible(const Function *Caller,
      78             :                            const Function *Callee) const;
      79             : 
      80             :   bool enableInterleavedAccessVectorization() { return true; }
      81             : 
      82             :   /// Floating-point computation using ARMv8 AArch32 Advanced
      83             :   /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
      84             :   /// is IEEE-754 compliant, but it's not covered in this target.
      85             :   bool isFPVectorizationPotentiallyUnsafe() {
      86           0 :     return !ST->isTargetDarwin();
      87             :   }
      88             : 
      89             :   /// \name Scalar TTI Implementations
      90             :   /// @{
      91             : 
      92             :   int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
      93             :                             Type *Ty);
      94             : 
      95             :   using BaseT::getIntImmCost;
      96             :   int getIntImmCost(const APInt &Imm, Type *Ty);
      97             : 
      98             :   int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
      99             : 
     100             :   /// @}
     101             : 
     102             :   /// \name Vector TTI Implementations
     103             :   /// @{
     104             : 
     105             :   unsigned getNumberOfRegisters(bool Vector) {
     106        6366 :     if (Vector) {
     107         391 :       if (ST->hasNEON())
     108             :         return 16;
     109             :       return 0;
     110             :     }
     111             : 
     112        5975 :     if (ST->isThumb1Only())
     113             :       return 8;
     114             :     return 13;
     115             :   }
     116             : 
     117             :   unsigned getRegisterBitWidth(bool Vector) const {
     118          28 :     if (Vector) {
     119          28 :       if (ST->hasNEON())
     120             :         return 128;
     121             :       return 0;
     122             :     }
     123             : 
     124             :     return 32;
     125             :   }
     126             : 
     127             :   unsigned getMaxInterleaveFactor(unsigned VF) {
     128          30 :     return ST->getMaxInterleaveFactor();
     129             :   }
     130             : 
     131             :   int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
     132             : 
     133             :   int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
     134             :                        const Instruction *I = nullptr);
     135             : 
     136             :   int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
     137             :                          const Instruction *I = nullptr);
     138             : 
     139             :   int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
     140             : 
     141             :   int getAddressComputationCost(Type *Val, ScalarEvolution *SE, 
     142             :                                 const SCEV *Ptr);
     143             : 
     144             :   int getFPOpCost(Type *Ty);
     145             : 
     146             :   int getArithmeticInstrCost(
     147             :       unsigned Opcode, Type *Ty,
     148             :       TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
     149             :       TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
     150             :       TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
     151             :       TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
     152             :       ArrayRef<const Value *> Args = ArrayRef<const Value *>());
     153             : 
     154             :   int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
     155             :                       unsigned AddressSpace, const Instruction *I = nullptr);
     156             : 
     157             :   int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
     158             :                                  ArrayRef<unsigned> Indices, unsigned Alignment,
     159             :                                  unsigned AddressSpace);
     160             : 
     161             :   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
     162             :                                TTI::UnrollingPreferences &UP);
     163             : 
     164         119 :   bool shouldBuildLookupTablesForConstant(Constant *C) const {
     165             :     // In the ROPI and RWPI relocation models we can't have pointers to global
     166             :     // variables or functions in constant data, so don't convert switches to
     167             :     // lookup tables if any of the values would need relocation.
     168         119 :     if (ST->isROPI() || ST->isRWPI())
     169          54 :       return !C->needsRelocation();
     170             : 
     171             :     return true;
     172             :   }
     173             :   /// @}
     174             : };
     175             : 
     176             : } // end namespace llvm
     177             : 
     178             : #endif

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