LCOV - code coverage report
Current view: top level - lib/Target/ARM/AsmParser - ARMAsmParser.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 4872 5324 91.5 %
Date: 2017-09-14 15:23:50 Functions: 224 231 97.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "ARMFeatures.h"
      11             : #include "Utils/ARMBaseInfo.h"
      12             : #include "MCTargetDesc/ARMAddressingModes.h"
      13             : #include "MCTargetDesc/ARMBaseInfo.h"
      14             : #include "MCTargetDesc/ARMMCExpr.h"
      15             : #include "llvm/ADT/STLExtras.h"
      16             : #include "llvm/ADT/SmallVector.h"
      17             : #include "llvm/ADT/StringExtras.h"
      18             : #include "llvm/ADT/StringSwitch.h"
      19             : #include "llvm/ADT/Triple.h"
      20             : #include "llvm/ADT/Twine.h"
      21             : #include "llvm/BinaryFormat/COFF.h"
      22             : #include "llvm/BinaryFormat/ELF.h"
      23             : #include "llvm/MC/MCAsmInfo.h"
      24             : #include "llvm/MC/MCAssembler.h"
      25             : #include "llvm/MC/MCContext.h"
      26             : #include "llvm/MC/MCDisassembler/MCDisassembler.h"
      27             : #include "llvm/MC/MCELFStreamer.h"
      28             : #include "llvm/MC/MCExpr.h"
      29             : #include "llvm/MC/MCInst.h"
      30             : #include "llvm/MC/MCInstrDesc.h"
      31             : #include "llvm/MC/MCInstrInfo.h"
      32             : #include "llvm/MC/MCObjectFileInfo.h"
      33             : #include "llvm/MC/MCParser/MCAsmLexer.h"
      34             : #include "llvm/MC/MCParser/MCAsmParser.h"
      35             : #include "llvm/MC/MCParser/MCAsmParserUtils.h"
      36             : #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
      37             : #include "llvm/MC/MCParser/MCTargetAsmParser.h"
      38             : #include "llvm/MC/MCRegisterInfo.h"
      39             : #include "llvm/MC/MCSection.h"
      40             : #include "llvm/MC/MCStreamer.h"
      41             : #include "llvm/MC/MCSubtargetInfo.h"
      42             : #include "llvm/MC/MCSymbol.h"
      43             : #include "llvm/Support/ARMBuildAttributes.h"
      44             : #include "llvm/Support/ARMEHABI.h"
      45             : #include "llvm/Support/CommandLine.h"
      46             : #include "llvm/Support/Debug.h"
      47             : #include "llvm/Support/MathExtras.h"
      48             : #include "llvm/Support/SourceMgr.h"
      49             : #include "llvm/Support/TargetParser.h"
      50             : #include "llvm/Support/TargetRegistry.h"
      51             : #include "llvm/Support/raw_ostream.h"
      52             : 
      53             : using namespace llvm;
      54             : 
      55             : namespace {
      56             : 
      57             : enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly };
      58             : 
      59       72306 : static cl::opt<ImplicitItModeTy> ImplicitItMode(
      60      216918 :     "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly),
      61      216918 :     cl::desc("Allow conditional instructions outdside of an IT block"),
      62      650754 :     cl::values(clEnumValN(ImplicitItModeTy::Always, "always",
      63             :                           "Accept in both ISAs, emit implicit ITs in Thumb"),
      64             :                clEnumValN(ImplicitItModeTy::Never, "never",
      65             :                           "Warn in ARM, reject in Thumb"),
      66             :                clEnumValN(ImplicitItModeTy::ARMOnly, "arm",
      67             :                           "Accept in ARM, reject in Thumb"),
      68             :                clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb",
      69       72306 :                           "Warn in ARM, emit implicit ITs in Thumb")));
      70             : 
      71       72306 : static cl::opt<bool> AddBuildAttributes("arm-add-build-attributes",
      72      144612 :                                         cl::init(false));
      73             : 
      74             : class ARMOperand;
      75             : 
      76             : enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
      77             : 
      78        6612 : class UnwindContext {
      79             :   MCAsmParser &Parser;
      80             : 
      81             :   typedef SmallVector<SMLoc, 4> Locs;
      82             : 
      83             :   Locs FnStartLocs;
      84             :   Locs CantUnwindLocs;
      85             :   Locs PersonalityLocs;
      86             :   Locs PersonalityIndexLocs;
      87             :   Locs HandlerDataLocs;
      88             :   int FPReg;
      89             : 
      90             : public:
      91        6648 :   UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
      92             : 
      93         839 :   bool hasFnStart() const { return !FnStartLocs.empty(); }
      94         165 :   bool cantUnwind() const { return !CantUnwindLocs.empty(); }
      95         255 :   bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
      96             :   bool hasPersonality() const {
      97         140 :     return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
      98             :   }
      99             : 
     100         213 :   void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
     101          45 :   void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
     102          76 :   void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
     103          75 :   void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
     104          16 :   void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
     105             : 
     106          37 :   void saveFPReg(int Reg) { FPReg = Reg; }
     107             :   int getFPReg() const { return FPReg; }
     108             : 
     109           1 :   void emitFnStartLocNotes() const {
     110           4 :     for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
     111           2 :          FI != FE; ++FI)
     112           3 :       Parser.Note(*FI, ".fnstart was specified here");
     113           1 :   }
     114           3 :   void emitCantUnwindLocNotes() const {
     115           9 :     for (Locs::const_iterator UI = CantUnwindLocs.begin(),
     116           6 :                               UE = CantUnwindLocs.end(); UI != UE; ++UI)
     117           9 :       Parser.Note(*UI, ".cantunwind was specified here");
     118           3 :   }
     119           3 :   void emitHandlerDataLocNotes() const {
     120           9 :     for (Locs::const_iterator HI = HandlerDataLocs.begin(),
     121           6 :                               HE = HandlerDataLocs.end(); HI != HE; ++HI)
     122           9 :       Parser.Note(*HI, ".handlerdata was specified here");
     123           3 :   }
     124           6 :   void emitPersonalityLocNotes() const {
     125          12 :     for (Locs::const_iterator PI = PersonalityLocs.begin(),
     126          12 :                               PE = PersonalityLocs.end(),
     127          12 :                               PII = PersonalityIndexLocs.begin(),
     128          12 :                               PIE = PersonalityIndexLocs.end();
     129          19 :          PI != PE || PII != PIE;) {
     130          15 :       if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
     131          30 :         Parser.Note(*PI++, ".personality was specified here");
     132           3 :       else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
     133           9 :         Parser.Note(*PII++, ".personalityindex was specified here");
     134             :       else
     135           0 :         llvm_unreachable(".personality and .personalityindex cannot be "
     136             :                          "at the same location");
     137             :     }
     138           6 :   }
     139             : 
     140         421 :   void reset() {
     141        1263 :     FnStartLocs = Locs();
     142        1263 :     CantUnwindLocs = Locs();
     143        1263 :     PersonalityLocs = Locs();
     144        1263 :     HandlerDataLocs = Locs();
     145        1263 :     PersonalityIndexLocs = Locs();
     146         421 :     FPReg = ARM::SP;
     147         421 :   }
     148             : };
     149             : 
     150        3306 : class ARMAsmParser : public MCTargetAsmParser {
     151             :   const MCInstrInfo &MII;
     152             :   const MCRegisterInfo *MRI;
     153             :   UnwindContext UC;
     154             : 
     155             :   ARMTargetStreamer &getTargetStreamer() {
     156             :     assert(getParser().getStreamer().getTargetStreamer() &&
     157             :            "do not have a target streamer");
     158        3846 :     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
     159             :     return static_cast<ARMTargetStreamer &>(TS);
     160             :   }
     161             : 
     162             :   // Map of register aliases registers via the .req directive.
     163             :   StringMap<unsigned> RegisterReqs;
     164             : 
     165             :   bool NextSymbolIsThumb;
     166             : 
     167             :   bool useImplicitITThumb() const {
     168       23174 :     return ImplicitItMode == ImplicitItModeTy::Always ||
     169       11533 :            ImplicitItMode == ImplicitItModeTy::ThumbOnly;
     170             :   }
     171             : 
     172             :   bool useImplicitITARM() const {
     173       14292 :     return ImplicitItMode == ImplicitItModeTy::Always ||
     174        7143 :            ImplicitItMode == ImplicitItModeTy::ARMOnly;
     175             :   }
     176             : 
     177             :   struct {
     178             :     ARMCC::CondCodes Cond;    // Condition for IT block.
     179             :     unsigned Mask:4;          // Condition mask for instructions.
     180             :                               // Starting at first 1 (from lsb).
     181             :                               //   '1'  condition as indicated in IT.
     182             :                               //   '0'  inverse of condition (else).
     183             :                               // Count of instructions in IT block is
     184             :                               // 4 - trailingzeroes(mask)
     185             :                               // Note that this does not have the same encoding
     186             :                               // as in the IT instruction, which also depends
     187             :                               // on the low bit of the condition code.
     188             : 
     189             :     unsigned CurPosition;     // Current position in parsing of IT
     190             :                               // block. In range [0,4], with 0 being the IT
     191             :                               // instruction itself. Initialized according to
     192             :                               // count of instructions in block.  ~0U if no
     193             :                               // active IT block.
     194             : 
     195             :     bool IsExplicit;          // true  - The IT instruction was present in the
     196             :                               //         input, we should not modify it.
     197             :                               // false - The IT instruction was added
     198             :                               //         implicitly, we can extend it if that
     199             :                               //         would be legal.
     200             :   } ITState;
     201             : 
     202             :   llvm::SmallVector<MCInst, 4> PendingConditionalInsts;
     203             : 
     204       10171 :   void flushPendingInstructions(MCStreamer &Out) override {
     205       10171 :     if (!inImplicitITBlock()) {
     206             :       assert(PendingConditionalInsts.size() == 0);
     207       10099 :       return;
     208             :     }
     209             : 
     210             :     // Emit the IT instruction
     211          72 :     unsigned Mask = getITMaskEncoding();
     212         144 :     MCInst ITInst;
     213         144 :     ITInst.setOpcode(ARM::t2IT);
     214         216 :     ITInst.addOperand(MCOperand::createImm(ITState.Cond));
     215         216 :     ITInst.addOperand(MCOperand::createImm(Mask));
     216          72 :     Out.EmitInstruction(ITInst, getSTI());
     217             : 
     218             :     // Emit the conditonal instructions
     219             :     assert(PendingConditionalInsts.size() <= 4);
     220         308 :     for (const MCInst &Inst : PendingConditionalInsts) {
     221          92 :       Out.EmitInstruction(Inst, getSTI());
     222             :     }
     223          72 :     PendingConditionalInsts.clear();
     224             : 
     225             :     // Clear the IT state
     226          72 :     ITState.Mask = 0;
     227          72 :     ITState.CurPosition = ~0U;
     228             :   }
     229             : 
     230          52 :   bool inITBlock() { return ITState.CurPosition != ~0U; }
     231       43970 :   bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; }
     232       10313 :   bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; }
     233             :   bool lastInITBlock() {
     234        5994 :     return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
     235             :   }
     236             :   void forwardITPosition() {
     237       20090 :     if (!inITBlock()) return;
     238             :     // Move to the next instruction in the IT block, if there is one. If not,
     239             :     // mark the block as done, except for implicit IT blocks, which we leave
     240             :     // open until we find an instruction that can't be added to it.
     241       11756 :     unsigned TZ = countTrailingZeros(ITState.Mask);
     242        5878 :     if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit)
     243        2753 :       ITState.CurPosition = ~0U; // Done with the IT block after this.
     244             :   }
     245             : 
     246             :   // Rewind the state of the current IT block, removing the last slot from it.
     247             :   void rewindImplicitITPosition() {
     248             :     assert(inImplicitITBlock());
     249             :     assert(ITState.CurPosition > 1);
     250           9 :     ITState.CurPosition--;
     251          18 :     unsigned TZ = countTrailingZeros(ITState.Mask);
     252           9 :     unsigned NewMask = 0;
     253           9 :     NewMask |= ITState.Mask & (0xC << TZ);
     254           9 :     NewMask |= 0x2 << TZ;
     255           9 :     ITState.Mask = NewMask;
     256             :   }
     257             : 
     258             :   // Rewind the state of the current IT block, removing the last slot from it.
     259             :   // If we were at the first slot, this closes the IT block.
     260             :   void discardImplicitITBlock() {
     261             :     assert(inImplicitITBlock());
     262             :     assert(ITState.CurPosition == 1);
     263           0 :     ITState.CurPosition = ~0U;
     264             :     return;
     265             :   }
     266             : 
     267             :   // Return the low-subreg of a given Q register.
     268             :   unsigned getDRegFromQReg(unsigned QReg) const {
     269          24 :     return MRI->getSubReg(QReg, ARM::dsub_0);
     270             :   }
     271             : 
     272             :   // Get the encoding of the IT mask, as it will appear in an IT instruction.
     273             :   unsigned getITMaskEncoding() {
     274             :     assert(inITBlock());
     275        2830 :     unsigned Mask = ITState.Mask;
     276        2830 :     unsigned TZ = countTrailingZeros(Mask);
     277        2830 :     if ((ITState.Cond & 1) == 0) {
     278             :       assert(Mask && TZ <= 3 && "illegal IT mask value!");
     279        2715 :       Mask ^= (0xE << TZ) & 0xF;
     280             :     }
     281             :     return Mask;
     282             :   }
     283             : 
     284             :   // Get the condition code corresponding to the current IT block slot.
     285        3159 :   ARMCC::CondCodes currentITCond() {
     286             :     unsigned MaskBit;
     287        3159 :     if (ITState.CurPosition == 1)
     288             :       MaskBit = 1;
     289             :     else
     290         327 :       MaskBit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
     291             : 
     292         327 :     return MaskBit ? ITState.Cond : ARMCC::getOppositeCondition(ITState.Cond);
     293             :   }
     294             : 
     295             :   // Invert the condition of the current IT block slot without changing any
     296             :   // other slots in the same block.
     297           5 :   void invertCurrentITCondition() {
     298           5 :     if (ITState.CurPosition == 1) {
     299           0 :       ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond);
     300             :     } else {
     301           5 :       ITState.Mask ^= 1 << (5 - ITState.CurPosition);
     302             :     }
     303           5 :   }
     304             : 
     305             :   // Returns true if the current IT block is full (all 4 slots used).
     306             :   bool isITBlockFull() {
     307          92 :     return inITBlock() && (ITState.Mask & 1);
     308             :   }
     309             : 
     310             :   // Extend the current implicit IT block to have one more slot with the given
     311             :   // condition code.
     312             :   void extendImplicitITBlock(ARMCC::CondCodes Cond) {
     313             :     assert(inImplicitITBlock());
     314             :     assert(!isITBlockFull());
     315             :     assert(Cond == ITState.Cond ||
     316             :            Cond == ARMCC::getOppositeCondition(ITState.Cond));
     317          58 :     unsigned TZ = countTrailingZeros(ITState.Mask);
     318          29 :     unsigned NewMask = 0;
     319             :     // Keep any existing condition bits.
     320          29 :     NewMask |= ITState.Mask & (0xE << TZ);
     321             :     // Insert the new condition bit.
     322          29 :     NewMask |= (Cond == ITState.Cond) << TZ;
     323             :     // Move the trailing 1 down one bit.
     324          29 :     NewMask |= 1 << (TZ - 1);
     325          29 :     ITState.Mask = NewMask;
     326             :   }
     327             : 
     328             :   // Create a new implicit IT block with a dummy condition code.
     329             :   void startImplicitITBlock() {
     330             :     assert(!inITBlock());
     331          72 :     ITState.Cond = ARMCC::AL;
     332          72 :     ITState.Mask = 8;
     333          72 :     ITState.CurPosition = 1;
     334          72 :     ITState.IsExplicit = false;
     335             :     return;
     336             :   }
     337             : 
     338             :   // Create a new explicit IT block with the given condition and mask. The mask
     339             :   // should be in the parsed format, with a 1 implying 't', regardless of the
     340             :   // low bit of the condition.
     341             :   void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) {
     342             :     assert(!inITBlock());
     343        2758 :     ITState.Cond = Cond;
     344        2758 :     ITState.Mask = Mask;
     345        2758 :     ITState.CurPosition = 0;
     346        2758 :     ITState.IsExplicit = true;
     347             :     return;
     348             :   }
     349             : 
     350             :   void Note(SMLoc L, const Twine &Msg, SMRange Range = None) {
     351             :     return getParser().Note(L, Msg, Range);
     352             :   }
     353             :   bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) {
     354        2166 :     return getParser().Warning(L, Msg, Range);
     355             :   }
     356             :   bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) {
     357        4579 :     return getParser().Error(L, Msg, Range);
     358             :   }
     359             : 
     360             :   bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
     361             :                            unsigned ListNo, bool IsARPop = false);
     362             :   bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
     363             :                            unsigned ListNo);
     364             : 
     365             :   int tryParseRegister();
     366             :   bool tryParseRegisterWithWriteBack(OperandVector &);
     367             :   int tryParseShiftRegister(OperandVector &);
     368             :   bool parseRegisterList(OperandVector &);
     369             :   bool parseMemory(OperandVector &);
     370             :   bool parseOperand(OperandVector &, StringRef Mnemonic);
     371             :   bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
     372             :   bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
     373             :                               unsigned &ShiftAmount);
     374             :   bool parseLiteralValues(unsigned Size, SMLoc L);
     375             :   bool parseDirectiveThumb(SMLoc L);
     376             :   bool parseDirectiveARM(SMLoc L);
     377             :   bool parseDirectiveThumbFunc(SMLoc L);
     378             :   bool parseDirectiveCode(SMLoc L);
     379             :   bool parseDirectiveSyntax(SMLoc L);
     380             :   bool parseDirectiveReq(StringRef Name, SMLoc L);
     381             :   bool parseDirectiveUnreq(SMLoc L);
     382             :   bool parseDirectiveArch(SMLoc L);
     383             :   bool parseDirectiveEabiAttr(SMLoc L);
     384             :   bool parseDirectiveCPU(SMLoc L);
     385             :   bool parseDirectiveFPU(SMLoc L);
     386             :   bool parseDirectiveFnStart(SMLoc L);
     387             :   bool parseDirectiveFnEnd(SMLoc L);
     388             :   bool parseDirectiveCantUnwind(SMLoc L);
     389             :   bool parseDirectivePersonality(SMLoc L);
     390             :   bool parseDirectiveHandlerData(SMLoc L);
     391             :   bool parseDirectiveSetFP(SMLoc L);
     392             :   bool parseDirectivePad(SMLoc L);
     393             :   bool parseDirectiveRegSave(SMLoc L, bool IsVector);
     394             :   bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
     395             :   bool parseDirectiveLtorg(SMLoc L);
     396             :   bool parseDirectiveEven(SMLoc L);
     397             :   bool parseDirectivePersonalityIndex(SMLoc L);
     398             :   bool parseDirectiveUnwindRaw(SMLoc L);
     399             :   bool parseDirectiveTLSDescSeq(SMLoc L);
     400             :   bool parseDirectiveMovSP(SMLoc L);
     401             :   bool parseDirectiveObjectArch(SMLoc L);
     402             :   bool parseDirectiveArchExtension(SMLoc L);
     403             :   bool parseDirectiveAlign(SMLoc L);
     404             :   bool parseDirectiveThumbSet(SMLoc L);
     405             : 
     406             :   StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
     407             :                           bool &CarrySetting, unsigned &ProcessorIMod,
     408             :                           StringRef &ITMask);
     409             :   void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
     410             :                              bool &CanAcceptCarrySet,
     411             :                              bool &CanAcceptPredicationCode);
     412             : 
     413             :   void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
     414             :                                      OperandVector &Operands);
     415             :   bool isThumb() const {
     416             :     // FIXME: Can tablegen auto-generate this?
     417      801960 :     return getSTI().getFeatureBits()[ARM::ModeThumb];
     418             :   }
     419       59183 :   bool isThumbOne() const {
     420      100297 :     return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
     421             :   }
     422      157226 :   bool isThumbTwo() const {
     423      256965 :     return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
     424             :   }
     425             :   bool hasThumb() const {
     426         404 :     return getSTI().getFeatureBits()[ARM::HasV4TOps];
     427             :   }
     428             :   bool hasThumb2() const {
     429         624 :     return getSTI().getFeatureBits()[ARM::FeatureThumb2];
     430             :   }
     431             :   bool hasV6Ops() const {
     432          78 :     return getSTI().getFeatureBits()[ARM::HasV6Ops];
     433             :   }
     434             :   bool hasV6T2Ops() const {
     435         158 :     return getSTI().getFeatureBits()[ARM::HasV6T2Ops];
     436             :   }
     437             :   bool hasV6MOps() const {
     438        1886 :     return getSTI().getFeatureBits()[ARM::HasV6MOps];
     439             :   }
     440             :   bool hasV7Ops() const {
     441        1992 :     return getSTI().getFeatureBits()[ARM::HasV7Ops];
     442             :   }
     443             :   bool hasV8Ops() const {
     444       19194 :     return getSTI().getFeatureBits()[ARM::HasV8Ops];
     445             :   }
     446             :   bool hasV8MBaseline() const {
     447         412 :     return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
     448             :   }
     449             :   bool hasV8MMainline() const {
     450             :     return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps];
     451             :   }
     452             :   bool has8MSecExt() const {
     453             :     return getSTI().getFeatureBits()[ARM::Feature8MSecExt];
     454             :   }
     455             :   bool hasARM() const {
     456         220 :     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
     457             :   }
     458             :   bool hasDSP() const {
     459             :     return getSTI().getFeatureBits()[ARM::FeatureDSP];
     460             :   }
     461             :   bool hasD16() const {
     462       96820 :     return getSTI().getFeatureBits()[ARM::FeatureD16];
     463             :   }
     464             :   bool hasV8_1aOps() const {
     465             :     return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
     466             :   }
     467             :   bool hasRAS() const {
     468         250 :     return getSTI().getFeatureBits()[ARM::FeatureRAS];
     469             :   }
     470             : 
     471         149 :   void SwitchMode() {
     472         149 :     MCSubtargetInfo &STI = copySTI();
     473         149 :     uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
     474         298 :     setAvailableFeatures(FB);
     475         149 :   }
     476             :   void FixModeAfterArchChange(bool WasThumb, SMLoc Loc);
     477             :   bool isMClass() const {
     478         592 :     return getSTI().getFeatureBits()[ARM::FeatureMClass];
     479             :   }
     480             : 
     481             :   /// @name Auto-generated Match Functions
     482             :   /// {
     483             : 
     484             : #define GET_ASSEMBLER_HEADER
     485             : #include "ARMGenAsmMatcher.inc"
     486             : 
     487             :   /// }
     488             : 
     489             :   OperandMatchResultTy parseITCondCode(OperandVector &);
     490             :   OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
     491             :   OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
     492             :   OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
     493             :   OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
     494             :   OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
     495             :   OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
     496             :   OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
     497             :   OperandMatchResultTy parseBankedRegOperand(OperandVector &);
     498             :   OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
     499             :                                    int High);
     500             :   OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
     501          22 :     return parsePKHImm(O, "lsl", 0, 31);
     502             :   }
     503             :   OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
     504          14 :     return parsePKHImm(O, "asr", 1, 32);
     505             :   }
     506             :   OperandMatchResultTy parseSetEndImm(OperandVector &);
     507             :   OperandMatchResultTy parseShifterImm(OperandVector &);
     508             :   OperandMatchResultTy parseRotImm(OperandVector &);
     509             :   OperandMatchResultTy parseModImm(OperandVector &);
     510             :   OperandMatchResultTy parseBitfield(OperandVector &);
     511             :   OperandMatchResultTy parsePostIdxReg(OperandVector &);
     512             :   OperandMatchResultTy parseAM3Offset(OperandVector &);
     513             :   OperandMatchResultTy parseFPImm(OperandVector &);
     514             :   OperandMatchResultTy parseVectorList(OperandVector &);
     515             :   OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
     516             :                                        SMLoc &EndLoc);
     517             : 
     518             :   // Asm Match Converter Methods
     519             :   void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
     520             :   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
     521             : 
     522             :   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
     523             :   bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
     524             :   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
     525             :   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
     526             :   bool isITBlockTerminator(MCInst &Inst) const;
     527             : 
     528             : public:
     529             :   enum ARMMatchResultTy {
     530             :     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
     531             :     Match_RequiresNotITBlock,
     532             :     Match_RequiresV6,
     533             :     Match_RequiresThumb2,
     534             :     Match_RequiresV8,
     535             :     Match_RequiresFlagSetting,
     536             : #define GET_OPERAND_DIAGNOSTIC_TYPES
     537             : #include "ARMGenAsmMatcher.inc"
     538             : 
     539             :   };
     540             : 
     541        1108 :   ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
     542             :                const MCInstrInfo &MII, const MCTargetOptions &Options)
     543        4432 :     : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
     544        1108 :     MCAsmParserExtension::Initialize(Parser);
     545             : 
     546             :     // Cache the MCRegisterInfo.
     547        2216 :     MRI = getContext().getRegisterInfo();
     548             : 
     549             :     // Initialize the set of available features.
     550        3324 :     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
     551             : 
     552             :     // Add build attributes based on the selected target.
     553        1108 :     if (AddBuildAttributes)
     554           5 :       getTargetStreamer().emitTargetAttributes(STI);
     555             : 
     556             :     // Not in an ITBlock to start with.
     557        1108 :     ITState.CurPosition = ~0U;
     558             : 
     559        1108 :     NextSymbolIsThumb = false;
     560        1108 :   }
     561             : 
     562             :   // Implementation of the MCTargetAsmParser interface:
     563             :   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
     564             :   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
     565             :                         SMLoc NameLoc, OperandVector &Operands) override;
     566             :   bool ParseDirective(AsmToken DirectiveID) override;
     567             : 
     568             :   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
     569             :                                       unsigned Kind) override;
     570             :   unsigned checkTargetMatchPredicate(MCInst &Inst) override;
     571             : 
     572             :   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     573             :                                OperandVector &Operands, MCStreamer &Out,
     574             :                                uint64_t &ErrorInfo,
     575             :                                bool MatchingInlineAsm) override;
     576             :   unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst,
     577             :                             uint64_t &ErrorInfo, bool MatchingInlineAsm,
     578             :                             bool &EmitInITBlock, MCStreamer &Out);
     579             :   void onLabelParsed(MCSymbol *Symbol) override;
     580             : };
     581             : } // end anonymous namespace
     582             : 
     583             : namespace {
     584             : 
     585             : /// ARMOperand - Instances of this class represent a parsed ARM machine
     586             : /// operand.
     587      470280 : class ARMOperand : public MCParsedAsmOperand {
     588             :   enum KindTy {
     589             :     k_CondCode,
     590             :     k_CCOut,
     591             :     k_ITCondMask,
     592             :     k_CoprocNum,
     593             :     k_CoprocReg,
     594             :     k_CoprocOption,
     595             :     k_Immediate,
     596             :     k_MemBarrierOpt,
     597             :     k_InstSyncBarrierOpt,
     598             :     k_Memory,
     599             :     k_PostIndexRegister,
     600             :     k_MSRMask,
     601             :     k_BankedReg,
     602             :     k_ProcIFlags,
     603             :     k_VectorIndex,
     604             :     k_Register,
     605             :     k_RegisterList,
     606             :     k_DPRRegisterList,
     607             :     k_SPRRegisterList,
     608             :     k_VectorList,
     609             :     k_VectorListAllLanes,
     610             :     k_VectorListIndexed,
     611             :     k_ShiftedRegister,
     612             :     k_ShiftedImmediate,
     613             :     k_ShifterImmediate,
     614             :     k_RotateImmediate,
     615             :     k_ModifiedImmediate,
     616             :     k_ConstantPoolImmediate,
     617             :     k_BitfieldDescriptor,
     618             :     k_Token,
     619             :   } Kind;
     620             : 
     621             :   SMLoc StartLoc, EndLoc, AlignmentLoc;
     622             :   SmallVector<unsigned, 8> Registers;
     623             : 
     624             :   struct CCOp {
     625             :     ARMCC::CondCodes Val;
     626             :   };
     627             : 
     628             :   struct CopOp {
     629             :     unsigned Val;
     630             :   };
     631             : 
     632             :   struct CoprocOptionOp {
     633             :     unsigned Val;
     634             :   };
     635             : 
     636             :   struct ITMaskOp {
     637             :     unsigned Mask:4;
     638             :   };
     639             : 
     640             :   struct MBOptOp {
     641             :     ARM_MB::MemBOpt Val;
     642             :   };
     643             : 
     644             :   struct ISBOptOp {
     645             :     ARM_ISB::InstSyncBOpt Val;
     646             :   };
     647             : 
     648             :   struct IFlagsOp {
     649             :     ARM_PROC::IFlags Val;
     650             :   };
     651             : 
     652             :   struct MMaskOp {
     653             :     unsigned Val;
     654             :   };
     655             : 
     656             :   struct BankedRegOp {
     657             :     unsigned Val;
     658             :   };
     659             : 
     660             :   struct TokOp {
     661             :     const char *Data;
     662             :     unsigned Length;
     663             :   };
     664             : 
     665             :   struct RegOp {
     666             :     unsigned RegNum;
     667             :   };
     668             : 
     669             :   // A vector register list is a sequential list of 1 to 4 registers.
     670             :   struct VectorListOp {
     671             :     unsigned RegNum;
     672             :     unsigned Count;
     673             :     unsigned LaneIndex;
     674             :     bool isDoubleSpaced;
     675             :   };
     676             : 
     677             :   struct VectorIndexOp {
     678             :     unsigned Val;
     679             :   };
     680             : 
     681             :   struct ImmOp {
     682             :     const MCExpr *Val;
     683             :   };
     684             : 
     685             :   /// Combined record for all forms of ARM address expressions.
     686             :   struct MemoryOp {
     687             :     unsigned BaseRegNum;
     688             :     // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
     689             :     // was specified.
     690             :     const MCConstantExpr *OffsetImm;  // Offset immediate value
     691             :     unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
     692             :     ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
     693             :     unsigned ShiftImm;        // shift for OffsetReg.
     694             :     unsigned Alignment;       // 0 = no alignment specified
     695             :     // n = alignment in bytes (2, 4, 8, 16, or 32)
     696             :     unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
     697             :   };
     698             : 
     699             :   struct PostIdxRegOp {
     700             :     unsigned RegNum;
     701             :     bool isAdd;
     702             :     ARM_AM::ShiftOpc ShiftTy;
     703             :     unsigned ShiftImm;
     704             :   };
     705             : 
     706             :   struct ShifterImmOp {
     707             :     bool isASR;
     708             :     unsigned Imm;
     709             :   };
     710             : 
     711             :   struct RegShiftedRegOp {
     712             :     ARM_AM::ShiftOpc ShiftTy;
     713             :     unsigned SrcReg;
     714             :     unsigned ShiftReg;
     715             :     unsigned ShiftImm;
     716             :   };
     717             : 
     718             :   struct RegShiftedImmOp {
     719             :     ARM_AM::ShiftOpc ShiftTy;
     720             :     unsigned SrcReg;
     721             :     unsigned ShiftImm;
     722             :   };
     723             : 
     724             :   struct RotImmOp {
     725             :     unsigned Imm;
     726             :   };
     727             : 
     728             :   struct ModImmOp {
     729             :     unsigned Bits;
     730             :     unsigned Rot;
     731             :   };
     732             : 
     733             :   struct BitfieldOp {
     734             :     unsigned LSB;
     735             :     unsigned Width;
     736             :   };
     737             : 
     738             :   union {
     739             :     struct CCOp CC;
     740             :     struct CopOp Cop;
     741             :     struct CoprocOptionOp CoprocOption;
     742             :     struct MBOptOp MBOpt;
     743             :     struct ISBOptOp ISBOpt;
     744             :     struct ITMaskOp ITMask;
     745             :     struct IFlagsOp IFlags;
     746             :     struct MMaskOp MMask;
     747             :     struct BankedRegOp BankedReg;
     748             :     struct TokOp Tok;
     749             :     struct RegOp Reg;
     750             :     struct VectorListOp VectorList;
     751             :     struct VectorIndexOp VectorIndex;
     752             :     struct ImmOp Imm;
     753             :     struct MemoryOp Memory;
     754             :     struct PostIdxRegOp PostIdxReg;
     755             :     struct ShifterImmOp ShifterImm;
     756             :     struct RegShiftedRegOp RegShiftedReg;
     757             :     struct RegShiftedImmOp RegShiftedImm;
     758             :     struct RotImmOp RotImm;
     759             :     struct ModImmOp ModImm;
     760             :     struct BitfieldOp Bitfield;
     761             :   };
     762             : 
     763             : public:
     764      705276 :   ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
     765             : 
     766             :   /// getStartLoc - Get the location of the first token of this operand.
     767       36629 :   SMLoc getStartLoc() const override { return StartLoc; }
     768             :   /// getEndLoc - Get the location of the last token of this operand.
     769          42 :   SMLoc getEndLoc() const override { return EndLoc; }
     770             :   /// getLocRange - Get the range between the first and last token of this
     771             :   /// operand.
     772          26 :   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
     773             : 
     774             :   /// getAlignmentLoc - Get the location of the Alignment token of this operand.
     775             :   SMLoc getAlignmentLoc() const {
     776             :     assert(Kind == k_Memory && "Invalid access!");
     777             :     return AlignmentLoc;
     778             :   }
     779             : 
     780             :   ARMCC::CondCodes getCondCode() const {
     781             :     assert(Kind == k_CondCode && "Invalid access!");
     782             :     return CC.Val;
     783             :   }
     784             : 
     785             :   unsigned getCoproc() const {
     786             :     assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
     787             :     return Cop.Val;
     788             :   }
     789             : 
     790             :   StringRef getToken() const {
     791             :     assert(Kind == k_Token && "Invalid access!");
     792      282839 :     return StringRef(Tok.Data, Tok.Length);
     793             :   }
     794             : 
     795           0 :   unsigned getReg() const override {
     796             :     assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
     797      185620 :     return Reg.RegNum;
     798             :   }
     799             : 
     800             :   const SmallVectorImpl<unsigned> &getRegList() const {
     801             :     assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
     802             :             Kind == k_SPRRegisterList) && "Invalid access!");
     803          52 :     return Registers;
     804             :   }
     805             : 
     806             :   const MCExpr *getImm() const {
     807             :     assert(isImm() && "Invalid access!");
     808             :     return Imm.Val;
     809             :   }
     810             : 
     811             :   const MCExpr *getConstantPoolImm() const {
     812             :     assert(isConstantPoolImm() && "Invalid access!");
     813             :     return Imm.Val;
     814             :   }
     815             : 
     816             :   unsigned getVectorIndex() const {
     817             :     assert(Kind == k_VectorIndex && "Invalid access!");
     818             :     return VectorIndex.Val;
     819             :   }
     820             : 
     821             :   ARM_MB::MemBOpt getMemBarrierOpt() const {
     822             :     assert(Kind == k_MemBarrierOpt && "Invalid access!");
     823             :     return MBOpt.Val;
     824             :   }
     825             : 
     826             :   ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
     827             :     assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
     828             :     return ISBOpt.Val;
     829             :   }
     830             : 
     831             :   ARM_PROC::IFlags getProcIFlags() const {
     832             :     assert(Kind == k_ProcIFlags && "Invalid access!");
     833             :     return IFlags.Val;
     834             :   }
     835             : 
     836             :   unsigned getMSRMask() const {
     837             :     assert(Kind == k_MSRMask && "Invalid access!");
     838             :     return MMask.Val;
     839             :   }
     840             : 
     841             :   unsigned getBankedReg() const {
     842             :     assert(Kind == k_BankedReg && "Invalid access!");
     843             :     return BankedReg.Val;
     844             :   }
     845             : 
     846             :   bool isCoprocNum() const { return Kind == k_CoprocNum; }
     847             :   bool isCoprocReg() const { return Kind == k_CoprocReg; }
     848             :   bool isCoprocOption() const { return Kind == k_CoprocOption; }
     849             :   bool isCondCode() const { return Kind == k_CondCode; }
     850             :   bool isCCOut() const { return Kind == k_CCOut; }
     851             :   bool isITMask() const { return Kind == k_ITCondMask; }
     852             :   bool isITCondCode() const { return Kind == k_CondCode; }
     853         451 :   bool isImm() const override {
     854       22985 :     return Kind == k_Immediate;
     855             :   }
     856             : 
     857             :   bool isARMBranchTarget() const {
     858         577 :     if (!isImm()) return false;
     859             : 
     860         597 :     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
     861         158 :       return CE->getValue() % 4 == 0;
     862             :     return true;
     863             :   }
     864             : 
     865             : 
     866             :   bool isThumbBranchTarget() const {
     867         194 :     if (!isImm()) return false;
     868             : 
     869         180 :     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()))
     870          40 :       return CE->getValue() % 2 == 0;
     871             :     return true;
     872             :   }
     873             : 
     874             :   // checks whether this operand is an unsigned offset which fits is a field
     875             :   // of specified width and scaled by a specific number of bits
     876             :   template<unsigned width, unsigned scale>
     877             :   bool isUnsignedOffset() const {
     878         142 :     if (!isImm()) return false;
     879         196 :     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
     880          89 :     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
     881          40 :       int64_t Val = CE->getValue();
     882          40 :       int64_t Align = 1LL << scale;
     883          40 :       int64_t Max = Align * ((1LL << width) - 1);
     884          40 :       return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
     885             :     }
     886             :     return false;
     887             :   }
     888             :   // checks whether this operand is an signed offset which fits is a field
     889             :   // of specified width and scaled by a specific number of bits
     890             :   template<unsigned width, unsigned scale>
     891             :   bool isSignedOffset() const {
     892        1022 :     if (!isImm()) return false;
     893        1022 :     if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
     894         659 :     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
     895         329 :       int64_t Val = CE->getValue();
     896         329 :       int64_t Align = 1LL << scale;
     897         329 :       int64_t Max = Align * ((1LL << (width-1)) - 1);
     898         329 :       int64_t Min = -Align * (1LL << (width-1));
     899         329 :       return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
     900             :     }
     901             :     return false;
     902             :   }
     903             : 
     904             :   // checks whether this operand is a memory operand computed as an offset
     905             :   // applied to PC. the offset may have 8 bits of magnitude and is represented
     906             :   // with two bits of shift. textually it may be either [pc, #imm], #imm or 
     907             :   // relocable expression...
     908         523 :   bool isThumbMemPC() const {
     909         523 :     int64_t Val = 0;
     910        1046 :     if (isImm()) {
     911          76 :       if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
     912          15 :       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
     913             :       if (!CE) return false;
     914           6 :       Val = CE->getValue();
     915             :     }
     916         485 :     else if (isMem()) {
     917         123 :       if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
     918          61 :       if(Memory.BaseRegNum != ARM::PC) return false;
     919          28 :       Val = Memory.OffsetImm->getValue();
     920             :     }
     921             :     else return false;
     922          34 :     return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
     923             :   }
     924          47 :   bool isFPImm() const {
     925          94 :     if (!isImm()) return false;
     926          82 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     927             :     if (!CE) return false;
     928         123 :     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
     929          41 :     return Val != -1;
     930             :   }
     931             : 
     932             :   template<int64_t N, int64_t M>
     933             :   bool isImmediate() const {
     934        6777 :     if (!isImm()) return false;
     935        6964 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     936             :     if (!CE) return false;
     937        3463 :     int64_t Value = CE->getValue();
     938        3463 :     return Value >= N && Value <= M;
     939             :   }
     940             :   template<int64_t N, int64_t M>
     941             :   bool isImmediateS4() const {
     942         222 :     if (!isImm()) return false;
     943         276 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     944             :     if (!CE) return false;
     945         138 :     int64_t Value = CE->getValue();
     946         138 :     return ((Value & 3) == 0) && Value >= N && Value <= M;
     947             :   }
     948             :   bool isFBits16() const {
     949          28 :     return isImmediate<0, 17>();
     950             :   }
     951             :   bool isFBits32() const {
     952          28 :     return isImmediate<1, 33>();
     953             :   }
     954             :   bool isImm8s4() const {
     955             :     return isImmediateS4<-1020, 1020>();
     956             :   }
     957             :   bool isImm0_1020s4() const {
     958             :     return isImmediateS4<0, 1020>();
     959             :   }
     960             :   bool isImm0_508s4() const {
     961             :     return isImmediateS4<0, 508>();
     962             :   }
     963             :   bool isImm0_508s4Neg() const {
     964          27 :     if (!isImm()) return false;
     965          38 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     966             :     if (!CE) return false;
     967          19 :     int64_t Value = -CE->getValue();
     968             :     // explicitly exclude zero. we want that to use the normal 0_508 version.
     969          19 :     return ((Value & 3) == 0) && Value > 0 && Value <= 508;
     970             :   }
     971             :   bool isImm0_4095Neg() const {
     972         198 :     if (!isImm()) return false;
     973          32 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     974             :     if (!CE) return false;
     975          16 :     int64_t Value = -CE->getValue();
     976          16 :     return Value > 0 && Value < 4096;
     977             :   }
     978             :   bool isImm0_7() const {
     979         280 :     return isImmediate<0, 7>();
     980             :   }
     981             :   bool isImm1_16() const {
     982             :     return isImmediate<1, 16>();
     983             :   }
     984             :   bool isImm1_32() const {
     985             :     return isImmediate<1, 32>();
     986             :   }
     987             :   bool isImm8_255() const {
     988             :     return isImmediate<8, 255>();
     989             :   }
     990             :   bool isImm256_65535Expr() const {
     991             :     if (!isImm()) return false;
     992             :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     993             :     // If it's not a constant expression, it'll generate a fixup and be
     994             :     // handled later.
     995             :     if (!CE) return true;
     996             :     int64_t Value = CE->getValue();
     997             :     return Value >= 256 && Value < 65536;
     998             :   }
     999             :   bool isImm0_65535Expr() const {
    1000         522 :     if (!isImm()) return false;
    1001         579 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1002             :     // If it's not a constant expression, it'll generate a fixup and be
    1003             :     // handled later.
    1004             :     if (!CE) return true;
    1005         131 :     int64_t Value = CE->getValue();
    1006         131 :     return Value >= 0 && Value < 65536;
    1007             :   }
    1008             :   bool isImm24bit() const {
    1009             :     return isImmediate<0, 0xffffff + 1>();
    1010             :   }
    1011             :   bool isImmThumbSR() const {
    1012             :     return isImmediate<1, 33>();
    1013             :   }
    1014             :   bool isPKHLSLImm() const {
    1015             :     return isImmediate<0, 32>();
    1016             :   }
    1017             :   bool isPKHASRImm() const {
    1018          12 :     return isImmediate<0, 33>();
    1019             :   }
    1020          26 :   bool isAdrLabel() const {
    1021             :     // If we have an immediate that's not a constant, treat it as a label
    1022             :     // reference needing a fixup.
    1023          78 :     if (isImm() && !isa<MCConstantExpr>(getImm()))
    1024             :       return true;
    1025             : 
    1026             :     // If it is a constant, it must fit into a modified immediate encoding.
    1027          14 :     if (!isImm()) return false;
    1028          28 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1029             :     if (!CE) return false;
    1030          14 :     int64_t Value = CE->getValue();
    1031          18 :     return (ARM_AM::getSOImmVal(Value) != -1 ||
    1032           4 :             ARM_AM::getSOImmVal(-Value) != -1);
    1033             :   }
    1034        4714 :   bool isT2SOImm() const {
    1035             :     // If we have an immediate that's not a constant, treat it as an expression
    1036             :     // needing a fixup.
    1037       10448 :     if (isImm() && !isa<MCConstantExpr>(getImm())) {
    1038             :       // We want to avoid matching :upper16: and :lower16: as we want these
    1039             :       // expressions to match in isImm0_65535Expr()
    1040          46 :       const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(getImm());
    1041           8 :       return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
    1042             :                              ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16));
    1043             :     }
    1044        4676 :     if (!isImm()) return false;
    1045        1964 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1046             :     if (!CE) return false;
    1047         982 :     int64_t Value = CE->getValue();
    1048         982 :     return ARM_AM::getT2SOImmVal(Value) != -1;
    1049             :   }
    1050        1253 :   bool isT2SOImmNot() const {
    1051        2506 :     if (!isImm()) return false;
    1052         142 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1053             :     if (!CE) return false;
    1054          66 :     int64_t Value = CE->getValue();
    1055         132 :     return ARM_AM::getT2SOImmVal(Value) == -1 &&
    1056          66 :       ARM_AM::getT2SOImmVal(~Value) != -1;
    1057             :   }
    1058        3076 :   bool isT2SOImmNeg() const {
    1059        6152 :     if (!isImm()) return false;
    1060         149 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1061             :     if (!CE) return false;
    1062          68 :     int64_t Value = CE->getValue();
    1063             :     // Only use this when not representable as a plain so_imm.
    1064         125 :     return ARM_AM::getT2SOImmVal(Value) == -1 &&
    1065          57 :       ARM_AM::getT2SOImmVal(-Value) != -1;
    1066             :   }
    1067             :   bool isSetEndImm() const {
    1068             :     if (!isImm()) return false;
    1069             :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1070             :     if (!CE) return false;
    1071             :     int64_t Value = CE->getValue();
    1072             :     return Value == 1 || Value == 0;
    1073             :   }
    1074      236904 :   bool isReg() const override { return Kind == k_Register; }
    1075             :   bool isRegList() const { return Kind == k_RegisterList; }
    1076             :   bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
    1077             :   bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
    1078      942363 :   bool isToken() const override { return Kind == k_Token; }
    1079             :   bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
    1080             :   bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
    1081        9259 :   bool isMem() const override { return Kind == k_Memory; }
    1082             :   bool isShifterImm() const { return Kind == k_ShifterImmediate; }
    1083             :   bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
    1084             :   bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
    1085             :   bool isRotImm() const { return Kind == k_RotateImmediate; }
    1086             :   bool isModImm() const { return Kind == k_ModifiedImmediate; }
    1087        1125 :   bool isModImmNot() const {
    1088        2250 :     if (!isImm()) return false;
    1089         150 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1090             :     if (!CE) return false;
    1091          75 :     int64_t Value = CE->getValue();
    1092          75 :     return ARM_AM::getSOImmVal(~Value) != -1;
    1093             :   }
    1094        1357 :   bool isModImmNeg() const {
    1095        2714 :     if (!isImm()) return false;
    1096          97 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1097             :     if (!CE) return false;
    1098          46 :     int64_t Value = CE->getValue();
    1099          83 :     return ARM_AM::getSOImmVal(Value) == -1 &&
    1100          37 :       ARM_AM::getSOImmVal(-Value) != -1;
    1101             :   }
    1102             :   bool isThumbModImmNeg1_7() const {
    1103         453 :     if (!isImm()) return false;
    1104          93 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1105             :     if (!CE) return false;
    1106          42 :     int32_t Value = -(int32_t)CE->getValue();
    1107          42 :     return 0 < Value && Value < 8;
    1108             :   }
    1109             :   bool isThumbModImmNeg8_255() const {
    1110        1162 :     if (!isImm()) return false;
    1111          98 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1112             :     if (!CE) return false;
    1113          49 :     int32_t Value = -(int32_t)CE->getValue();
    1114          49 :     return 7 < Value && Value < 256;
    1115             :   }
    1116             :   bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; }
    1117             :   bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
    1118             :   bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
    1119             :   bool isPostIdxReg() const {
    1120          25 :     return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
    1121             :   }
    1122             :   bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
    1123       21752 :     if (!isMem())
    1124             :       return false;
    1125             :     // No offset of any kind.
    1126       15957 :     return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
    1127       15756 :      (alignOK || Memory.Alignment == Alignment);
    1128             :   }
    1129         221 :   bool isMemPCRelImm12() const {
    1130         442 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1131             :       return false;
    1132             :     // Base register must be PC.
    1133         177 :     if (Memory.BaseRegNum != ARM::PC)
    1134             :       return false;
    1135             :     // Immediate offset in range [-4095, 4095].
    1136          53 :     if (!Memory.OffsetImm) return true;
    1137          53 :     int64_t Val = Memory.OffsetImm->getValue();
    1138          53 :     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
    1139             :   }
    1140             :   bool isAlignedMemory() const {
    1141             :     return isMemNoOffset(true);
    1142             :   }
    1143             :   bool isAlignedMemoryNone() const {
    1144         149 :     return isMemNoOffset(false, 0);
    1145             :   }
    1146             :   bool isDupAlignedMemoryNone() const {
    1147          96 :     return isMemNoOffset(false, 0);
    1148             :   }
    1149         215 :   bool isAlignedMemory16() const {
    1150             :     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
    1151             :       return true;
    1152             :     return isMemNoOffset(false, 0);
    1153             :   }
    1154         192 :   bool isDupAlignedMemory16() const {
    1155             :     if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
    1156             :       return true;
    1157             :     return isMemNoOffset(false, 0);
    1158             :   }
    1159         372 :   bool isAlignedMemory32() const {
    1160             :     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
    1161             :       return true;
    1162             :     return isMemNoOffset(false, 0);
    1163             :   }
    1164         300 :   bool isDupAlignedMemory32() const {
    1165             :     if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
    1166             :       return true;
    1167             :     return isMemNoOffset(false, 0);
    1168             :   }
    1169        1949 :   bool isAlignedMemory64() const {
    1170             :     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
    1171             :       return true;
    1172             :     return isMemNoOffset(false, 0);
    1173             :   }
    1174         216 :   bool isDupAlignedMemory64() const {
    1175             :     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
    1176             :       return true;
    1177             :     return isMemNoOffset(false, 0);
    1178             :   }
    1179        1180 :   bool isAlignedMemory64or128() const {
    1180             :     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
    1181             :       return true;
    1182             :     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
    1183             :       return true;
    1184             :     return isMemNoOffset(false, 0);
    1185             :   }
    1186         102 :   bool isDupAlignedMemory64or128() const {
    1187             :     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
    1188             :       return true;
    1189             :     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
    1190             :       return true;
    1191             :     return isMemNoOffset(false, 0);
    1192             :   }
    1193        1220 :   bool isAlignedMemory64or128or256() const {
    1194             :     if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
    1195             :       return true;
    1196             :     if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
    1197             :       return true;
    1198             :     if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
    1199             :       return true;
    1200             :     return isMemNoOffset(false, 0);
    1201             :   }
    1202             :   bool isAddrMode2() const {
    1203           0 :     if (!isMem() || Memory.Alignment != 0) return false;
    1204             :     // Check for register offset.
    1205           0 :     if (Memory.OffsetRegNum) return true;
    1206             :     // Immediate offset in range [-4095, 4095].
    1207           0 :     if (!Memory.OffsetImm) return true;
    1208           0 :     int64_t Val = Memory.OffsetImm->getValue();
    1209           0 :     return Val > -4096 && Val < 4096;
    1210             :   }
    1211             :   bool isAM2OffsetImm() const {
    1212          75 :     if (!isImm()) return false;
    1213             :     // Immediate offset in range [-4095, 4095].
    1214          78 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1215             :     if (!CE) return false;
    1216          39 :     int64_t Val = CE->getValue();
    1217          39 :     return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
    1218             :   }
    1219         469 :   bool isAddrMode3() const {
    1220             :     // If we have an immediate that's not a constant, treat it as a label
    1221             :     // reference needing a fixup. If it is a constant, it's something else
    1222             :     // and we reject it.
    1223         940 :     if (isImm() && !isa<MCConstantExpr>(getImm()))
    1224             :       return true;
    1225         467 :     if (!isMem() || Memory.Alignment != 0) return false;
    1226             :     // No shifts are legal for AM3.
    1227         467 :     if (Memory.ShiftType != ARM_AM::no_shift) return false;
    1228             :     // Check for register offset.
    1229         467 :     if (Memory.OffsetRegNum) return true;
    1230             :     // Immediate offset in range [-255, 255].
    1231         407 :     if (!Memory.OffsetImm) return true;
    1232         200 :     int64_t Val = Memory.OffsetImm->getValue();
    1233             :     // The #-0 offset is encoded as INT32_MIN, and we have to check 
    1234             :     // for this too.
    1235         200 :     return (Val > -256 && Val < 256) || Val == INT32_MIN;
    1236             :   }
    1237          71 :   bool isAM3Offset() const {
    1238          71 :     if (Kind != k_Immediate && Kind != k_PostIndexRegister)
    1239             :       return false;
    1240          71 :     if (Kind == k_PostIndexRegister)
    1241          23 :       return PostIdxReg.ShiftTy == ARM_AM::no_shift;
    1242             :     // Immediate offset in range [-255, 255].
    1243          96 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1244             :     if (!CE) return false;
    1245          48 :     int64_t Val = CE->getValue();
    1246             :     // Special case, #-0 is INT32_MIN.
    1247          48 :     return (Val > -256 && Val < 256) || Val == INT32_MIN;
    1248             :   }
    1249        2125 :   bool isAddrMode5() const {
    1250             :     // If we have an immediate that's not a constant, treat it as a label
    1251             :     // reference needing a fixup. If it is a constant, it's something else
    1252             :     // and we reject it.
    1253        4251 :     if (isImm() && !isa<MCConstantExpr>(getImm()))
    1254             :       return true;
    1255        2124 :     if (!isMem() || Memory.Alignment != 0) return false;
    1256             :     // Check for register offset.
    1257        2124 :     if (Memory.OffsetRegNum) return false;
    1258             :     // Immediate offset in range [-1020, 1020] and a multiple of 4.
    1259        2124 :     if (!Memory.OffsetImm) return true;
    1260         874 :     int64_t Val = Memory.OffsetImm->getValue();
    1261         874 :     return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
    1262             :       Val == INT32_MIN;
    1263             :   }
    1264          32 :   bool isAddrMode5FP16() const {
    1265             :     // If we have an immediate that's not a constant, treat it as a label
    1266             :     // reference needing a fixup. If it is a constant, it's something else
    1267             :     // and we reject it.
    1268          64 :     if (isImm() && !isa<MCConstantExpr>(getImm()))
    1269             :       return true;
    1270          32 :     if (!isMem() || Memory.Alignment != 0) return false;
    1271             :     // Check for register offset.
    1272          32 :     if (Memory.OffsetRegNum) return false;
    1273             :     // Immediate offset in range [-510, 510] and a multiple of 2.
    1274          32 :     if (!Memory.OffsetImm) return true;
    1275          32 :     int64_t Val = Memory.OffsetImm->getValue();
    1276          32 :     return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
    1277             :   }
    1278             :   bool isMemTBB() const {
    1279          21 :     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
    1280          21 :         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
    1281             :       return false;
    1282             :     return true;
    1283             :   }
    1284             :   bool isMemTBH() const {
    1285          21 :     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
    1286          21 :         Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
    1287             :         Memory.Alignment != 0 )
    1288             :       return false;
    1289             :     return true;
    1290             :   }
    1291             :   bool isMemRegOffset() const {
    1292         540 :     if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
    1293             :       return false;
    1294             :     return true;
    1295             :   }
    1296         611 :   bool isT2MemRegOffset() const {
    1297        2115 :     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
    1298        1199 :         Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
    1299             :       return false;
    1300             :     // Only lsl #{0, 1, 2, 3} allowed.
    1301         284 :     if (Memory.ShiftType == ARM_AM::no_shift)
    1302             :       return true;
    1303          84 :     if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
    1304             :       return false;
    1305          81 :     return true;
    1306             :   }
    1307         641 :   bool isMemThumbRR() const {
    1308             :     // Thumb reg+reg addressing is simple. Just two registers, a base and
    1309             :     // an offset. No shifts, negations or any other complicating factors.
    1310        1912 :     if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
    1311         894 :         Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
    1312             :       return false;
    1313         155 :     return isARMLowRegister(Memory.BaseRegNum) &&
    1314          62 :       (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
    1315             :   }
    1316         380 :   bool isMemThumbRIs4() const {
    1317         975 :     if (!isMem() || Memory.OffsetRegNum != 0 ||
    1318         637 :         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
    1319             :       return false;
    1320             :     // Immediate offset, multiple of 4 in range [0, 124].
    1321         104 :     if (!Memory.OffsetImm) return true;
    1322          65 :     int64_t Val = Memory.OffsetImm->getValue();
    1323          65 :     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
    1324             :   }
    1325         120 :   bool isMemThumbRIs2() const {
    1326         358 :     if (!isMem() || Memory.OffsetRegNum != 0 ||
    1327         272 :         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
    1328             :       return false;
    1329             :     // Immediate offset, multiple of 4 in range [0, 62].
    1330          71 :     if (!Memory.OffsetImm) return true;
    1331          51 :     int64_t Val = Memory.OffsetImm->getValue();
    1332          51 :     return Val >= 0 && Val <= 62 && (Val % 2) == 0;
    1333             :   }
    1334             :   bool isMemThumbRIs1() const {
    1335         250 :     if (!isMem() || Memory.OffsetRegNum != 0 ||
    1336         279 :         !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
    1337             :       return false;
    1338             :     // Immediate offset in range [0, 31].
    1339          70 :     if (!Memory.OffsetImm) return true;
    1340          46 :     int64_t Val = Memory.OffsetImm->getValue();
    1341          46 :     return Val >= 0 && Val <= 31;
    1342             :   }
    1343         340 :   bool isMemThumbSPI() const {
    1344         977 :     if (!isMem() || Memory.OffsetRegNum != 0 ||
    1345         487 :         Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
    1346             :       return false;
    1347             :     // Immediate offset, multiple of 4 in range [0, 1020].
    1348          25 :     if (!Memory.OffsetImm) return true;
    1349          17 :     int64_t Val = Memory.OffsetImm->getValue();
    1350          17 :     return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
    1351             :   }
    1352         339 :   bool isMemImm8s4Offset() const {
    1353             :     // If we have an immediate that's not a constant, treat it as a label
    1354             :     // reference needing a fixup. If it is a constant, it's something else
    1355             :     // and we reject it.
    1356         680 :     if (isImm() && !isa<MCConstantExpr>(getImm()))
    1357             :       return true;
    1358         337 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1359             :       return false;
    1360             :     // Immediate offset a multiple of 4 in range [-1020, 1020].
    1361         324 :     if (!Memory.OffsetImm) return true;
    1362         156 :     int64_t Val = Memory.OffsetImm->getValue();
    1363             :     // Special case, #-0 is INT32_MIN.
    1364         156 :     return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
    1365             :   }
    1366             :   bool isMemImm0_1020s4Offset() const {
    1367          44 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1368             :       return false;
    1369             :     // Immediate offset a multiple of 4 in range [0, 1020].
    1370          44 :     if (!Memory.OffsetImm) return true;
    1371          14 :     int64_t Val = Memory.OffsetImm->getValue();
    1372          14 :     return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
    1373             :   }
    1374         297 :   bool isMemImm8Offset() const {
    1375         594 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1376             :       return false;
    1377             :     // Base reg of PC isn't allowed for these encodings.
    1378         260 :     if (Memory.BaseRegNum == ARM::PC) return false;
    1379             :     // Immediate offset in range [-255, 255].
    1380         250 :     if (!Memory.OffsetImm) return true;
    1381         104 :     int64_t Val = Memory.OffsetImm->getValue();
    1382         104 :     return (Val == INT32_MIN) || (Val > -256 && Val < 256);
    1383             :   }
    1384             :   bool isMemPosImm8Offset() const {
    1385          74 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1386             :       return false;
    1387             :     // Immediate offset in range [0, 255].
    1388          74 :     if (!Memory.OffsetImm) return true;
    1389          30 :     int64_t Val = Memory.OffsetImm->getValue();
    1390          30 :     return Val >= 0 && Val < 256;
    1391             :   }
    1392         682 :   bool isMemNegImm8Offset() const {
    1393        1364 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1394             :       return false;
    1395             :     // Base reg of PC isn't allowed for these encodings.
    1396         364 :     if (Memory.BaseRegNum == ARM::PC) return false;
    1397             :     // Immediate offset in range [-255, -1].
    1398         312 :     if (!Memory.OffsetImm) return false;
    1399         179 :     int64_t Val = Memory.OffsetImm->getValue();
    1400         179 :     return (Val == INT32_MIN) || (Val > -256 && Val < 0);
    1401             :   }
    1402             :   bool isMemUImm12Offset() const {
    1403         861 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1404             :       return false;
    1405             :     // Immediate offset in range [0, 4095].
    1406         543 :     if (!Memory.OffsetImm) return true;
    1407         289 :     int64_t Val = Memory.OffsetImm->getValue();
    1408         289 :     return (Val >= 0 && Val < 4096);
    1409             :   }
    1410         670 :   bool isMemImm12Offset() const {
    1411             :     // If we have an immediate that's not a constant, treat it as a label
    1412             :     // reference needing a fixup. If it is a constant, it's something else
    1413             :     // and we reject it.
    1414             : 
    1415        1351 :     if (isImm() && !isa<MCConstantExpr>(getImm()))
    1416             :       return true;
    1417             : 
    1418         659 :     if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
    1419             :       return false;
    1420             :     // Immediate offset in range [-4095, 4095].
    1421         306 :     if (!Memory.OffsetImm) return true;
    1422         168 :     int64_t Val = Memory.OffsetImm->getValue();
    1423         168 :     return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
    1424             :   }
    1425             :   bool isConstPoolAsmImm() const {
    1426             :     // Delay processing of Constant Pool Immediate, this will turn into
    1427             :     // a constant. Match no other operand
    1428         892 :     return (isConstantPoolImm());
    1429             :   }
    1430             :   bool isPostIdxImm8() const {
    1431          19 :     if (!isImm()) return false;
    1432          32 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1433             :     if (!CE) return false;
    1434          16 :     int64_t Val = CE->getValue();
    1435          16 :     return (Val > -256 && Val < 256) || (Val == INT32_MIN);
    1436             :   }
    1437             :   bool isPostIdxImm8s4() const {
    1438         352 :     if (!isImm()) return false;
    1439         704 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1440             :     if (!CE) return false;
    1441         352 :     int64_t Val = CE->getValue();
    1442         352 :     return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
    1443             :       (Val == INT32_MIN);
    1444             :   }
    1445             : 
    1446             :   bool isMSRMask() const { return Kind == k_MSRMask; }
    1447             :   bool isBankedReg() const { return Kind == k_BankedReg; }
    1448             :   bool isProcIFlags() const { return Kind == k_ProcIFlags; }
    1449             : 
    1450             :   // NEON operands.
    1451             :   bool isSingleSpacedVectorList() const {
    1452       15063 :     return Kind == k_VectorList && !VectorList.isDoubleSpaced;
    1453             :   }
    1454             :   bool isDoubleSpacedVectorList() const {
    1455        2684 :     return Kind == k_VectorList && VectorList.isDoubleSpaced;
    1456             :   }
    1457             :   bool isVecListOneD() const {
    1458        2001 :     if (!isSingleSpacedVectorList()) return false;
    1459        1364 :     return VectorList.Count == 1;
    1460             :   }
    1461             : 
    1462             :   bool isVecListDPair() const {
    1463        3886 :     if (!isSingleSpacedVectorList()) return false;
    1464             :     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
    1465        2247 :               .contains(VectorList.RegNum));
    1466             :   }
    1467             : 
    1468             :   bool isVecListThreeD() const {
    1469        3431 :     if (!isSingleSpacedVectorList()) return false;
    1470        1571 :     return VectorList.Count == 3;
    1471             :   }
    1472             : 
    1473             :   bool isVecListFourD() const {
    1474        5075 :     if (!isSingleSpacedVectorList()) return false;
    1475        2250 :     return VectorList.Count == 4;
    1476             :   }
    1477             : 
    1478             :   bool isVecListDPairSpaced() const {
    1479        1365 :     if (Kind != k_VectorList) return false;
    1480         670 :     if (isSingleSpacedVectorList()) return false;
    1481             :     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
    1482         227 :               .contains(VectorList.RegNum));
    1483             :   }
    1484             : 
    1485             :   bool isVecListThreeQ() const {
    1486        1428 :     if (!isDoubleSpacedVectorList()) return false;
    1487         348 :     return VectorList.Count == 3;
    1488             :   }
    1489             : 
    1490             :   bool isVecListFourQ() const {
    1491        1256 :     if (!isDoubleSpacedVectorList()) return false;
    1492         312 :     return VectorList.Count == 4;
    1493             :   }
    1494             : 
    1495             :   bool isSingleSpacedVectorAllLanes() const {
    1496        5273 :     return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
    1497             :   }
    1498             :   bool isDoubleSpacedVectorAllLanes() const {
    1499        2625 :     return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
    1500             :   }
    1501             :   bool isVecListOneDAllLanes() const {
    1502        1041 :     if (!isSingleSpacedVectorAllLanes()) return false;
    1503         282 :     return VectorList.Count == 1;
    1504             :   }
    1505             : 
    1506             :   bool isVecListDPairAllLanes() const {
    1507        2268 :     if (!isSingleSpacedVectorAllLanes()) return false;
    1508             :     return (ARMMCRegisterClasses[ARM::DPairRegClassID]
    1509         462 :               .contains(VectorList.RegNum));
    1510             :   }
    1511             : 
    1512             :   bool isVecListDPairSpacedAllLanes() const {
    1513         953 :     if (!isDoubleSpacedVectorAllLanes()) return false;
    1514         150 :     return VectorList.Count == 2;
    1515             :   }
    1516             : 
    1517             :   bool isVecListThreeDAllLanes() const {
    1518        1011 :     if (!isSingleSpacedVectorAllLanes()) return false;
    1519         171 :     return VectorList.Count == 3;
    1520             :   }
    1521             : 
    1522             :   bool isVecListThreeQAllLanes() const {
    1523         900 :     if (!isDoubleSpacedVectorAllLanes()) return false;
    1524         171 :     return VectorList.Count == 3;
    1525             :   }
    1526             : 
    1527             :   bool isVecListFourDAllLanes() const {
    1528         953 :     if (!isSingleSpacedVectorAllLanes()) return false;
    1529         159 :     return VectorList.Count == 4;
    1530             :   }
    1531             : 
    1532             :   bool isVecListFourQAllLanes() const {
    1533         772 :     if (!isDoubleSpacedVectorAllLanes()) return false;
    1534         159 :     return VectorList.Count == 4;
    1535             :   }
    1536             : 
    1537             :   bool isSingleSpacedVectorIndexed() const {
    1538        5711 :     return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
    1539             :   }
    1540             :   bool isDoubleSpacedVectorIndexed() const {
    1541        2529 :     return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
    1542             :   }
    1543             :   bool isVecListOneDByteIndexed() const {
    1544         526 :     if (!isSingleSpacedVectorIndexed()) return false;
    1545         109 :     return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
    1546             :   }
    1547             : 
    1548             :   bool isVecListOneDHWordIndexed() const {
    1549         495 :     if (!isSingleSpacedVectorIndexed()) return false;
    1550         103 :     return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
    1551             :   }
    1552             : 
    1553             :   bool isVecListOneDWordIndexed() const {
    1554         544 :     if (!isSingleSpacedVectorIndexed()) return false;
    1555         152 :     return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
    1556             :   }
    1557             : 
    1558             :   bool isVecListTwoDByteIndexed() const {
    1559         382 :     if (!isSingleSpacedVectorIndexed()) return false;
    1560         112 :     return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
    1561             :   }
    1562             : 
    1563             :   bool isVecListTwoDHWordIndexed() const {
    1564         291 :     if (!isSingleSpacedVectorIndexed()) return false;
    1565          52 :     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
    1566             :   }
    1567             : 
    1568             :   bool isVecListTwoQWordIndexed() const {
    1569         462 :     if (!isDoubleSpacedVectorIndexed()) return false;
    1570         108 :     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
    1571             :   }
    1572             : 
    1573             :   bool isVecListTwoQHWordIndexed() const {
    1574         276 :     if (!isDoubleSpacedVectorIndexed()) return false;
    1575          58 :     return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
    1576             :   }
    1577             : 
    1578             :   bool isVecListTwoDWordIndexed() const {
    1579         488 :     if (!isSingleSpacedVectorIndexed()) return false;
    1580         100 :     return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
    1581             :   }
    1582             : 
    1583             :   bool isVecListThreeDByteIndexed() const {
    1584         434 :     if (!isSingleSpacedVectorIndexed()) return false;
    1585         116 :     return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
    1586             :   }
    1587             : 
    1588             :   bool isVecListThreeDHWordIndexed() const {
    1589         554 :     if (!isSingleSpacedVectorIndexed()) return false;
    1590         116 :     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
    1591             :   }
    1592             : 
    1593             :   bool isVecListThreeQWordIndexed() const {
    1594         484 :     if (!isDoubleSpacedVectorIndexed()) return false;
    1595         116 :     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
    1596             :   }
    1597             : 
    1598             :   bool isVecListThreeQHWordIndexed() const {
    1599         484 :     if (!isDoubleSpacedVectorIndexed()) return false;
    1600         116 :     return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
    1601             :   }
    1602             : 
    1603             :   bool isVecListThreeDWordIndexed() const {
    1604         554 :     if (!isSingleSpacedVectorIndexed()) return false;
    1605         116 :     return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
    1606             :   }
    1607             : 
    1608             :   bool isVecListFourDByteIndexed() const {
    1609         383 :     if (!isSingleSpacedVectorIndexed()) return false;
    1610         110 :     return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
    1611             :   }
    1612             : 
    1613             :   bool isVecListFourDHWordIndexed() const {
    1614         499 :     if (!isSingleSpacedVectorIndexed()) return false;
    1615         110 :     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
    1616             :   }
    1617             : 
    1618             :   bool isVecListFourQWordIndexed() const {
    1619         429 :     if (!isDoubleSpacedVectorIndexed()) return false;
    1620         149 :     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
    1621             :   }
    1622             : 
    1623             :   bool isVecListFourQHWordIndexed() const {
    1624         394 :     if (!isDoubleSpacedVectorIndexed()) return false;
    1625         110 :     return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
    1626             :   }
    1627             : 
    1628             :   bool isVecListFourDWordIndexed() const {
    1629         561 :     if (!isSingleSpacedVectorIndexed()) return false;
    1630         137 :     return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
    1631             :   }
    1632             : 
    1633             :   bool isVectorIndex8() const {
    1634          22 :     if (Kind != k_VectorIndex) return false;
    1635          22 :     return VectorIndex.Val < 8;
    1636             :   }
    1637             :   bool isVectorIndex16() const {
    1638         117 :     if (Kind != k_VectorIndex) return false;
    1639         102 :     return VectorIndex.Val < 4;
    1640             :   }
    1641             :   bool isVectorIndex32() const {
    1642         132 :     if (Kind != k_VectorIndex) return false;
    1643         127 :     return VectorIndex.Val < 2;
    1644             :   }
    1645             : 
    1646             :   bool isNEONi8splat() const {
    1647           4 :     if (!isImm()) return false;
    1648           8 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1649             :     // Must be a constant.
    1650             :     if (!CE) return false;
    1651           4 :     int64_t Value = CE->getValue();
    1652             :     // i8 value splatted across 8 bytes. The immediate is just the 8 byte
    1653             :     // value.
    1654           4 :     return Value >= 0 && Value < 256;
    1655             :   }
    1656             : 
    1657          37 :   bool isNEONi16splat() const {
    1658          31 :     if (isNEONByteReplicate(2))
    1659             :       return false; // Leave that for bytes replication and forbid by default.
    1660          27 :     if (!isImm())
    1661             :       return false;
    1662          42 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1663             :     // Must be a constant.
    1664             :     if (!CE) return false;
    1665          21 :     unsigned Value = CE->getValue();
    1666             :     return ARM_AM::isNEONi16splat(Value);
    1667             :   }
    1668             : 
    1669           8 :   bool isNEONi16splatNot() const {
    1670          16 :     if (!isImm())
    1671             :       return false;
    1672           8 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1673             :     // Must be a constant.
    1674             :     if (!CE) return false;
    1675           4 :     unsigned Value = CE->getValue();
    1676           4 :     return ARM_AM::isNEONi16splat(~Value & 0xffff);
    1677             :   }
    1678             : 
    1679          26 :   bool isNEONi32splat() const {
    1680          22 :     if (isNEONByteReplicate(4))
    1681             :       return false; // Leave that for bytes replication and forbid by default.
    1682          18 :     if (!isImm())
    1683             :       return false;
    1684          30 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1685             :     // Must be a constant.
    1686             :     if (!CE) return false;
    1687          15 :     unsigned Value = CE->getValue();
    1688             :     return ARM_AM::isNEONi32splat(Value);
    1689             :   }
    1690             : 
    1691          12 :   bool isNEONi32splatNot() const {
    1692          24 :     if (!isImm())
    1693             :       return false;
    1694          16 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1695             :     // Must be a constant.
    1696             :     if (!CE) return false;
    1697           8 :     unsigned Value = CE->getValue();
    1698           8 :     return ARM_AM::isNEONi32splat(~Value);
    1699             :   }
    1700             : 
    1701             :   bool isNEONByteReplicate(unsigned NumBytes) const {
    1702         258 :     if (!isImm())
    1703             :       return false;
    1704         248 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1705             :     // Must be a constant.
    1706             :     if (!CE)
    1707             :       return false;
    1708         124 :     int64_t Value = CE->getValue();
    1709         124 :     if (!Value)
    1710             :       return false; // Don't bother with zero.
    1711             : 
    1712             :     unsigned char B = Value & 0xff;
    1713         346 :     for (unsigned i = 1; i < NumBytes; ++i) {
    1714         209 :       Value >>= 8;
    1715         209 :       if ((Value & 0xff) != B)
    1716             :         return false;
    1717             :     }
    1718             :     return true;
    1719             :   }
    1720           8 :   bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
    1721          12 :   bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
    1722          53 :   bool isNEONi32vmov() const {
    1723          49 :     if (isNEONByteReplicate(4))
    1724             :       return false; // Let it to be classified as byte-replicate case.
    1725          45 :     if (!isImm())
    1726             :       return false;
    1727          84 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1728             :     // Must be a constant.
    1729             :     if (!CE)
    1730             :       return false;
    1731          42 :     int64_t Value = CE->getValue();
    1732             :     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
    1733             :     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
    1734             :     // FIXME: This is probably wrong and a copy and paste from previous example
    1735          42 :     return (Value >= 0 && Value < 256) ||
    1736          42 :       (Value >= 0x0100 && Value <= 0xff00) ||
    1737          53 :       (Value >= 0x010000 && Value <= 0xff0000) ||
    1738          15 :       (Value >= 0x01000000 && Value <= 0xff000000) ||
    1739          50 :       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
    1740           4 :       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
    1741             :   }
    1742          11 :   bool isNEONi32vmovNeg() const {
    1743          22 :     if (!isImm()) return false;
    1744          16 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1745             :     // Must be a constant.
    1746             :     if (!CE) return false;
    1747           8 :     int64_t Value = ~CE->getValue();
    1748             :     // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
    1749             :     // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
    1750             :     // FIXME: This is probably wrong and a copy and paste from previous example
    1751           8 :     return (Value >= 0 && Value < 256) ||
    1752           8 :       (Value >= 0x0100 && Value <= 0xff00) ||
    1753          16 :       (Value >= 0x010000 && Value <= 0xff0000) ||
    1754          16 :       (Value >= 0x01000000 && Value <= 0xff000000) ||
    1755          24 :       (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
    1756           8 :       (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
    1757             :   }
    1758             : 
    1759             :   bool isNEONi64splat() const {
    1760           5 :     if (!isImm()) return false;
    1761          10 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1762             :     // Must be a constant.
    1763             :     if (!CE) return false;
    1764           5 :     uint64_t Value = CE->getValue();
    1765             :     // i64 value with each byte being either 0 or 0xff.
    1766          44 :     for (unsigned i = 0; i < 8; ++i, Value >>= 8)
    1767          40 :       if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
    1768             :     return true;
    1769             :   }
    1770             : 
    1771        4417 :   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
    1772             :     // Add as immediates when possible.  Null MCExpr = 0.
    1773        4417 :     if (!Expr)
    1774           0 :       Inst.addOperand(MCOperand::createImm(0));
    1775        4417 :     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
    1776       11172 :       Inst.addOperand(MCOperand::createImm(CE->getValue()));
    1777             :     else
    1778        1386 :       Inst.addOperand(MCOperand::createExpr(Expr));
    1779        4417 :   }
    1780             : 
    1781             :   void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
    1782             :     assert(N == 1 && "Invalid number of operands!");
    1783         167 :     addExpr(Inst, getImm());
    1784             :   }
    1785             : 
    1786             :   void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
    1787             :     assert(N == 1 && "Invalid number of operands!");
    1788         122 :     addExpr(Inst, getImm());
    1789             :   }
    1790             : 
    1791       16401 :   void addCondCodeOperands(MCInst &Inst, unsigned N) const {
    1792             :     assert(N == 2 && "Invalid number of operands!");
    1793       49203 :     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
    1794       16401 :     unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
    1795       32802 :     Inst.addOperand(MCOperand::createReg(RegNum));
    1796       16401 :   }
    1797             : 
    1798             :   void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
    1799             :     assert(N == 1 && "Invalid number of operands!");
    1800        2541 :     Inst.addOperand(MCOperand::createImm(getCoproc()));
    1801             :   }
    1802             : 
    1803             :   void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
    1804             :     assert(N == 1 && "Invalid number of operands!");
    1805        2832 :     Inst.addOperand(MCOperand::createImm(getCoproc()));
    1806             :   }
    1807             : 
    1808             :   void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
    1809             :     assert(N == 1 && "Invalid number of operands!");
    1810         234 :     Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
    1811             :   }
    1812             : 
    1813             :   void addITMaskOperands(MCInst &Inst, unsigned N) const {
    1814             :     assert(N == 1 && "Invalid number of operands!");
    1815        8298 :     Inst.addOperand(MCOperand::createImm(ITMask.Mask));
    1816             :   }
    1817             : 
    1818             :   void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
    1819             :     assert(N == 1 && "Invalid number of operands!");
    1820        8298 :     Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
    1821             :   }
    1822             : 
    1823        4369 :   void addCCOutOperands(MCInst &Inst, unsigned N) const {
    1824             :     assert(N == 1 && "Invalid number of operands!");
    1825       17476 :     Inst.addOperand(MCOperand::createReg(getReg()));
    1826        4369 :   }
    1827             : 
    1828       26875 :   void addRegOperands(MCInst &Inst, unsigned N) const {
    1829             :     assert(N == 1 && "Invalid number of operands!");
    1830      107500 :     Inst.addOperand(MCOperand::createReg(getReg()));
    1831       26875 :   }
    1832             : 
    1833         241 :   void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
    1834             :     assert(N == 3 && "Invalid number of operands!");
    1835             :     assert(isRegShiftedReg() &&
    1836             :            "addRegShiftedRegOperands() on non-RegShiftedReg!");
    1837         723 :     Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
    1838         723 :     Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
    1839         482 :     Inst.addOperand(MCOperand::createImm(
    1840         482 :       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
    1841         241 :   }
    1842             : 
    1843         618 :   void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
    1844             :     assert(N == 2 && "Invalid number of operands!");
    1845             :     assert(isRegShiftedImm() &&
    1846             :            "addRegShiftedImmOperands() on non-RegShiftedImm!");
    1847        1854 :     Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
    1848             :     // Shift of #32 is encoded as 0 where permitted
    1849         618 :     unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
    1850        1236 :     Inst.addOperand(MCOperand::createImm(
    1851        1236 :       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
    1852         618 :   }
    1853             : 
    1854             :   void addShifterImmOperands(MCInst &Inst, unsigned N) const {
    1855             :     assert(N == 1 && "Invalid number of operands!");
    1856          84 :     Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
    1857          28 :                                          ShifterImm.Imm));
    1858             :   }
    1859             : 
    1860         679 :   void addRegListOperands(MCInst &Inst, unsigned N) const {
    1861             :     assert(N == 1 && "Invalid number of operands!");
    1862         679 :     const SmallVectorImpl<unsigned> &RegList = getRegList();
    1863        2014 :     for (SmallVectorImpl<unsigned>::const_iterator
    1864        2037 :            I = RegList.begin(), E = RegList.end(); I != E; ++I)
    1865        6042 :       Inst.addOperand(MCOperand::createReg(*I));
    1866         679 :   }
    1867             : 
    1868             :   void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
    1869          72 :     addRegListOperands(Inst, N);
    1870             :   }
    1871             : 
    1872             :   void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
    1873          18 :     addRegListOperands(Inst, N);
    1874             :   }
    1875             : 
    1876             :   void addRotImmOperands(MCInst &Inst, unsigned N) const {
    1877             :     assert(N == 1 && "Invalid number of operands!");
    1878             :     // Encoded as val>>3. The printer handles display as 8, 16, 24.
    1879         654 :     Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
    1880             :   }
    1881             : 
    1882        1066 :   void addModImmOperands(MCInst &Inst, unsigned N) const {
    1883             :     assert(N == 1 && "Invalid number of operands!");
    1884             : 
    1885             :     // Support for fixups (MCFixup)
    1886        2132 :     if (isImm())
    1887          11 :       return addImmOperands(Inst, N);
    1888             : 
    1889        3165 :     Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
    1890             :   }
    1891             : 
    1892          33 :   void addModImmNotOperands(MCInst &Inst, unsigned N) const {
    1893             :     assert(N == 1 && "Invalid number of operands!");
    1894          66 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1895          33 :     uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
    1896          99 :     Inst.addOperand(MCOperand::createImm(Enc));
    1897          33 :   }
    1898             : 
    1899          18 :   void addModImmNegOperands(MCInst &Inst, unsigned N) const {
    1900             :     assert(N == 1 && "Invalid number of operands!");
    1901          36 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1902          18 :     uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
    1903          54 :     Inst.addOperand(MCOperand::createImm(Enc));
    1904          18 :   }
    1905             : 
    1906           2 :   void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const {
    1907             :     assert(N == 1 && "Invalid number of operands!");
    1908           4 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1909           2 :     uint32_t Val = -CE->getValue();
    1910           6 :     Inst.addOperand(MCOperand::createImm(Val));
    1911           2 :   }
    1912             : 
    1913           2 :   void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const {
    1914             :     assert(N == 1 && "Invalid number of operands!");
    1915           4 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1916           2 :     uint32_t Val = -CE->getValue();
    1917           6 :     Inst.addOperand(MCOperand::createImm(Val));
    1918           2 :   }
    1919             : 
    1920          34 :   void addBitfieldOperands(MCInst &Inst, unsigned N) const {
    1921             :     assert(N == 1 && "Invalid number of operands!");
    1922             :     // Munge the lsb/width into a bitfield mask.
    1923          34 :     unsigned lsb = Bitfield.LSB;
    1924          34 :     unsigned width = Bitfield.Width;
    1925             :     // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
    1926          68 :     uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
    1927          34 :                       (32 - (lsb + width)));
    1928         102 :     Inst.addOperand(MCOperand::createImm(Mask));
    1929          34 :   }
    1930             : 
    1931             :   void addImmOperands(MCInst &Inst, unsigned N) const {
    1932             :     assert(N == 1 && "Invalid number of operands!");
    1933        3741 :     addExpr(Inst, getImm());
    1934             :   }
    1935             : 
    1936          16 :   void addFBits16Operands(MCInst &Inst, unsigned N) const {
    1937             :     assert(N == 1 && "Invalid number of operands!");
    1938          32 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1939          48 :     Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
    1940          16 :   }
    1941             : 
    1942          16 :   void addFBits32Operands(MCInst &Inst, unsigned N) const {
    1943             :     assert(N == 1 && "Invalid number of operands!");
    1944          32 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1945          48 :     Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
    1946          16 :   }
    1947             : 
    1948          35 :   void addFPImmOperands(MCInst &Inst, unsigned N) const {
    1949             :     assert(N == 1 && "Invalid number of operands!");
    1950          70 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1951         105 :     int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
    1952         105 :     Inst.addOperand(MCOperand::createImm(Val));
    1953          35 :   }
    1954             : 
    1955             :   void addImm8s4Operands(MCInst &Inst, unsigned N) const {
    1956             :     assert(N == 1 && "Invalid number of operands!");
    1957             :     // FIXME: We really want to scale the value here, but the LDRD/STRD
    1958             :     // instruction don't encode operands that way yet.
    1959             :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1960             :     Inst.addOperand(MCOperand::createImm(CE->getValue()));
    1961             :   }
    1962             : 
    1963          14 :   void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
    1964             :     assert(N == 1 && "Invalid number of operands!");
    1965             :     // The immediate is scaled by four in the encoding and is stored
    1966             :     // in the MCInst as such. Lop off the low two bits here.
    1967          28 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1968          42 :     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
    1969          14 :   }
    1970             : 
    1971           6 :   void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
    1972             :     assert(N == 1 && "Invalid number of operands!");
    1973             :     // The immediate is scaled by four in the encoding and is stored
    1974             :     // in the MCInst as such. Lop off the low two bits here.
    1975          12 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1976          18 :     Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
    1977           6 :   }
    1978             : 
    1979          35 :   void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
    1980             :     assert(N == 1 && "Invalid number of operands!");
    1981             :     // The immediate is scaled by four in the encoding and is stored
    1982             :     // in the MCInst as such. Lop off the low two bits here.
    1983          70 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1984         105 :     Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
    1985          35 :   }
    1986             : 
    1987          11 :   void addImm1_16Operands(MCInst &Inst, unsigned N) const {
    1988             :     assert(N == 1 && "Invalid number of operands!");
    1989             :     // The constant encodes as the immediate-1, and we store in the instruction
    1990             :     // the bits as encoded, so subtract off one here.
    1991          22 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    1992          33 :     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
    1993          11 :   }
    1994             : 
    1995         122 :   void addImm1_32Operands(MCInst &Inst, unsigned N) const {
    1996             :     assert(N == 1 && "Invalid number of operands!");
    1997             :     // The constant encodes as the immediate-1, and we store in the instruction
    1998             :     // the bits as encoded, so subtract off one here.
    1999         244 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2000         366 :     Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
    2001         122 :   }
    2002             : 
    2003             :   void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
    2004             :     assert(N == 1 && "Invalid number of operands!");
    2005             :     // The constant encodes as the immediate, except for 32, which encodes as
    2006             :     // zero.
    2007             :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2008             :     unsigned Imm = CE->getValue();
    2009             :     Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
    2010             :   }
    2011             : 
    2012           8 :   void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
    2013             :     assert(N == 1 && "Invalid number of operands!");
    2014             :     // An ASR value of 32 encodes as 0, so that's how we want to add it to
    2015             :     // the instruction as well.
    2016          16 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2017           8 :     int Val = CE->getValue();
    2018          24 :     Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
    2019           8 :   }
    2020             : 
    2021          17 :   void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
    2022             :     assert(N == 1 && "Invalid number of operands!");
    2023             :     // The operand is actually a t2_so_imm, but we have its bitwise
    2024             :     // negation in the assembly source, so twiddle it here.
    2025          34 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2026          51 :     Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue()));
    2027          17 :   }
    2028             : 
    2029          14 :   void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
    2030             :     assert(N == 1 && "Invalid number of operands!");
    2031             :     // The operand is actually a t2_so_imm, but we have its
    2032             :     // negation in the assembly source, so twiddle it here.
    2033          28 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2034          42 :     Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
    2035          14 :   }
    2036             : 
    2037           8 :   void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
    2038             :     assert(N == 1 && "Invalid number of operands!");
    2039             :     // The operand is actually an imm0_4095, but we have its
    2040             :     // negation in the assembly source, so twiddle it here.
    2041          16 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2042          24 :     Inst.addOperand(MCOperand::createImm(-CE->getValue()));
    2043           8 :   }
    2044             : 
    2045          25 :   void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
    2046          35 :     if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
    2047          30 :       Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
    2048             :       return;
    2049             :     }
    2050             : 
    2051          30 :     const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
    2052             :     assert(SR && "Unknown value type!");
    2053          30 :     Inst.addOperand(MCOperand::createExpr(SR));
    2054             :   }
    2055             : 
    2056          35 :   void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
    2057             :     assert(N == 1 && "Invalid number of operands!");
    2058          70 :     if (isImm()) {
    2059          32 :       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2060             :       if (CE) {
    2061          18 :         Inst.addOperand(MCOperand::createImm(CE->getValue()));
    2062             :         return;
    2063             :       }
    2064             : 
    2065          40 :       const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
    2066             :  
    2067             :       assert(SR && "Unknown value type!");
    2068          40 :       Inst.addOperand(MCOperand::createExpr(SR));
    2069             :       return;
    2070             :     }
    2071             : 
    2072             :     assert(isMem()  && "Unknown value type!");
    2073             :     assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
    2074          27 :     Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
    2075             :   }
    2076             : 
    2077             :   void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
    2078             :     assert(N == 1 && "Invalid number of operands!");
    2079         762 :     Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
    2080             :   }
    2081             : 
    2082             :   void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
    2083             :     assert(N == 1 && "Invalid number of operands!");
    2084          54 :     Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
    2085             :   }
    2086             : 
    2087         674 :   void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
    2088             :     assert(N == 1 && "Invalid number of operands!");
    2089        2022 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2090         674 :   }
    2091             : 
    2092             :   void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
    2093             :     assert(N == 1 && "Invalid number of operands!");
    2094          51 :     int32_t Imm = Memory.OffsetImm->getValue();
    2095         153 :     Inst.addOperand(MCOperand::createImm(Imm));
    2096             :   }
    2097             : 
    2098          26 :   void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
    2099             :     assert(N == 1 && "Invalid number of operands!");
    2100             :     assert(isImm() && "Not an immediate!");
    2101             : 
    2102             :     // If we have an immediate that's not a constant, treat it as a label
    2103             :     // reference needing a fixup. 
    2104          52 :     if (!isa<MCConstantExpr>(getImm())) {
    2105          36 :       Inst.addOperand(MCOperand::createExpr(getImm()));
    2106             :       return;
    2107             :     }
    2108             : 
    2109          28 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2110          14 :     int Val = CE->getValue();
    2111          42 :     Inst.addOperand(MCOperand::createImm(Val));
    2112             :   }
    2113             : 
    2114        1386 :   void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
    2115             :     assert(N == 2 && "Invalid number of operands!");
    2116        4158 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2117        4158 :     Inst.addOperand(MCOperand::createImm(Memory.Alignment));
    2118        1386 :   }
    2119             : 
    2120             :   void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
    2121          48 :     addAlignedMemoryOperands(Inst, N);
    2122             :   }
    2123             : 
    2124             :   void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
    2125          80 :     addAlignedMemoryOperands(Inst, N);
    2126             :   }
    2127             : 
    2128             :   void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
    2129          38 :     addAlignedMemoryOperands(Inst, N);
    2130             :   }
    2131             : 
    2132             :   void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
    2133          24 :     addAlignedMemoryOperands(Inst, N);
    2134             :   }
    2135             : 
    2136             :   void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
    2137          66 :     addAlignedMemoryOperands(Inst, N);
    2138             :   }
    2139             : 
    2140             :   void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
    2141          42 :     addAlignedMemoryOperands(Inst, N);
    2142             :   }
    2143             : 
    2144             :   void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
    2145         346 :     addAlignedMemoryOperands(Inst, N);
    2146             :   }
    2147             : 
    2148             :   void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
    2149          36 :     addAlignedMemoryOperands(Inst, N);
    2150             :   }
    2151             : 
    2152             :   void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
    2153         289 :     addAlignedMemoryOperands(Inst, N);
    2154             :   }
    2155             : 
    2156             :   void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
    2157          24 :     addAlignedMemoryOperands(Inst, N);
    2158             :   }
    2159             : 
    2160             :   void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
    2161         393 :     addAlignedMemoryOperands(Inst, N);
    2162             :   }
    2163             : 
    2164             :   void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
    2165             :     assert(N == 3 && "Invalid number of operands!");
    2166             :     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
    2167             :     if (!Memory.OffsetRegNum) {
    2168             :       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
    2169             :       // Special case for #-0
    2170             :       if (Val == INT32_MIN) Val = 0;
    2171             :       if (Val < 0) Val = -Val;
    2172             :       Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
    2173             :     } else {
    2174             :       // For register offset, we encode the shift type and negation flag
    2175             :       // here.
    2176             :       Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
    2177             :                               Memory.ShiftImm, Memory.ShiftType);
    2178             :     }
    2179             :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2180             :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2181             :     Inst.addOperand(MCOperand::createImm(Val));
    2182             :   }
    2183             : 
    2184          27 :   void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
    2185             :     assert(N == 2 && "Invalid number of operands!");
    2186          54 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2187             :     assert(CE && "non-constant AM2OffsetImm operand!");
    2188          27 :     int32_t Val = CE->getValue();
    2189          27 :     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
    2190             :     // Special case for #-0
    2191          27 :     if (Val == INT32_MIN) Val = 0;
    2192          25 :     if (Val < 0) Val = -Val;
    2193          54 :     Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
    2194          54 :     Inst.addOperand(MCOperand::createReg(0));
    2195          81 :     Inst.addOperand(MCOperand::createImm(Val));
    2196          27 :   }
    2197             : 
    2198          85 :   void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
    2199             :     assert(N == 3 && "Invalid number of operands!");
    2200             :     // If we have an immediate that's not a constant, treat it as a label
    2201             :     // reference needing a fixup. If it is a constant, it's something else
    2202             :     // and we reject it.
    2203         170 :     if (isImm()) {
    2204           6 :       Inst.addOperand(MCOperand::createExpr(getImm()));
    2205           4 :       Inst.addOperand(MCOperand::createReg(0));
    2206           4 :       Inst.addOperand(MCOperand::createImm(0));
    2207             :       return;
    2208             :     }
    2209             : 
    2210          83 :     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
    2211          83 :     if (!Memory.OffsetRegNum) {
    2212          52 :       ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
    2213             :       // Special case for #-0
    2214          52 :       if (Val == INT32_MIN) Val = 0;
    2215          49 :       if (Val < 0) Val = -Val;
    2216         104 :       Val = ARM_AM::getAM3Opc(AddSub, Val);
    2217             :     } else {
    2218             :       // For register offset, we encode the shift type and negation flag
    2219             :       // here.
    2220          62 :       Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
    2221             :     }
    2222         249 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2223         249 :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2224         249 :     Inst.addOperand(MCOperand::createImm(Val));
    2225             :   }
    2226             : 
    2227          52 :   void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
    2228             :     assert(N == 2 && "Invalid number of operands!");
    2229          52 :     if (Kind == k_PostIndexRegister) {
    2230             :       int32_t Val =
    2231          46 :         ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
    2232          69 :       Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
    2233          69 :       Inst.addOperand(MCOperand::createImm(Val));
    2234             :       return;
    2235             :     }
    2236             : 
    2237             :     // Constant offset.
    2238          29 :     const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
    2239          29 :     int32_t Val = CE->getValue();
    2240          29 :     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
    2241             :     // Special case for #-0
    2242          29 :     if (Val == INT32_MIN) Val = 0;
    2243          27 :     if (Val < 0) Val = -Val;
    2244          58 :     Val = ARM_AM::getAM3Opc(AddSub, Val);
    2245          58 :     Inst.addOperand(MCOperand::createReg(0));
    2246          87 :     Inst.addOperand(MCOperand::createImm(Val));
    2247             :   }
    2248             : 
    2249         457 :   void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
    2250             :     assert(N == 2 && "Invalid number of operands!");
    2251             :     // If we have an immediate that's not a constant, treat it as a label
    2252             :     // reference needing a fixup. If it is a constant, it's something else
    2253             :     // and we reject it.
    2254         914 :     if (isImm()) {
    2255           3 :       Inst.addOperand(MCOperand::createExpr(getImm()));
    2256           2 :       Inst.addOperand(MCOperand::createImm(0));
    2257             :       return;
    2258             :     }
    2259             : 
    2260             :     // The lower two bits are always zero and as such are not encoded.
    2261         456 :     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
    2262         338 :     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
    2263             :     // Special case for #-0
    2264         456 :     if (Val == INT32_MIN) Val = 0;
    2265         456 :     if (Val < 0) Val = -Val;
    2266         912 :     Val = ARM_AM::getAM5Opc(AddSub, Val);
    2267        1368 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2268        1368 :     Inst.addOperand(MCOperand::createImm(Val));
    2269             :   }
    2270             : 
    2271          16 :   void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
    2272             :     assert(N == 2 && "Invalid number of operands!");
    2273             :     // If we have an immediate that's not a constant, treat it as a label
    2274             :     // reference needing a fixup. If it is a constant, it's something else
    2275             :     // and we reject it.
    2276          32 :     if (isImm()) {
    2277           0 :       Inst.addOperand(MCOperand::createExpr(getImm()));
    2278           0 :       Inst.addOperand(MCOperand::createImm(0));
    2279             :       return;
    2280             :     }
    2281             : 
    2282             :     // The lower bit is always zero and as such is not encoded.
    2283          16 :     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
    2284          16 :     ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
    2285             :     // Special case for #-0
    2286          16 :     if (Val == INT32_MIN) Val = 0;
    2287          16 :     if (Val < 0) Val = -Val;
    2288          32 :     Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
    2289          48 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2290          48 :     Inst.addOperand(MCOperand::createImm(Val));
    2291             :   }
    2292             : 
    2293          99 :   void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
    2294             :     assert(N == 2 && "Invalid number of operands!");
    2295             :     // If we have an immediate that's not a constant, treat it as a label
    2296             :     // reference needing a fixup. If it is a constant, it's something else
    2297             :     // and we reject it.
    2298         198 :     if (isImm()) {
    2299           0 :       Inst.addOperand(MCOperand::createExpr(getImm()));
    2300           0 :       Inst.addOperand(MCOperand::createImm(0));
    2301             :       return;
    2302             :     }
    2303             : 
    2304          99 :     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
    2305         297 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2306         198 :     Inst.addOperand(MCOperand::createImm(Val));
    2307             :   }
    2308             : 
    2309          40 :   void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
    2310             :     assert(N == 2 && "Invalid number of operands!");
    2311             :     // The lower two bits are always zero and as such are not encoded.
    2312          40 :     int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
    2313         120 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2314         120 :     Inst.addOperand(MCOperand::createImm(Val));
    2315          40 :   }
    2316             : 
    2317         147 :   void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
    2318             :     assert(N == 2 && "Invalid number of operands!");
    2319         147 :     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
    2320         441 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2321         294 :     Inst.addOperand(MCOperand::createImm(Val));
    2322         147 :   }
    2323             : 
    2324             :   void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
    2325          40 :     addMemImm8OffsetOperands(Inst, N);
    2326             :   }
    2327             : 
    2328             :   void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
    2329          33 :     addMemImm8OffsetOperands(Inst, N);
    2330             :   }
    2331             : 
    2332         250 :   void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
    2333             :     assert(N == 2 && "Invalid number of operands!");
    2334             :     // If this is an immediate, it's a label reference.
    2335         500 :     if (isImm()) {
    2336           0 :       addExpr(Inst, getImm());
    2337           0 :       Inst.addOperand(MCOperand::createImm(0));
    2338             :       return;
    2339             :     }
    2340             : 
    2341             :     // Otherwise, it's a normal memory reg+offset.
    2342         250 :     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
    2343         750 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2344         500 :     Inst.addOperand(MCOperand::createImm(Val));
    2345             :   }
    2346             : 
    2347          49 :   void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
    2348             :     assert(N == 2 && "Invalid number of operands!");
    2349             :     // If this is an immediate, it's a label reference.
    2350          98 :     if (isImm()) {
    2351          11 :       addExpr(Inst, getImm());
    2352          22 :       Inst.addOperand(MCOperand::createImm(0));
    2353             :       return;
    2354             :     }
    2355             : 
    2356             :     // Otherwise, it's a normal memory reg+offset.
    2357          38 :     int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
    2358         114 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2359          76 :     Inst.addOperand(MCOperand::createImm(Val));
    2360             :   }
    2361             : 
    2362             :   void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
    2363             :     assert(N == 1 && "Invalid number of operands!");
    2364             :     // This is container for the immediate that we will create the constant
    2365             :     // pool from
    2366         376 :     addExpr(Inst, getConstantPoolImm());
    2367             :     return;
    2368             :   }
    2369             : 
    2370           7 :   void addMemTBBOperands(MCInst &Inst, unsigned N) const {
    2371             :     assert(N == 2 && "Invalid number of operands!");
    2372          21 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2373          21 :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2374           7 :   }
    2375             : 
    2376           7 :   void addMemTBHOperands(MCInst &Inst, unsigned N) const {
    2377             :     assert(N == 2 && "Invalid number of operands!");
    2378          21 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2379          21 :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2380           7 :   }
    2381             : 
    2382          59 :   void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
    2383             :     assert(N == 3 && "Invalid number of operands!");
    2384             :     unsigned Val =
    2385          59 :       ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
    2386         118 :                         Memory.ShiftImm, Memory.ShiftType);
    2387         177 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2388         177 :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2389         177 :     Inst.addOperand(MCOperand::createImm(Val));
    2390          59 :   }
    2391             : 
    2392         251 :   void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
    2393             :     assert(N == 3 && "Invalid number of operands!");
    2394         753 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2395         753 :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2396         753 :     Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
    2397         251 :   }
    2398             : 
    2399          33 :   void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
    2400             :     assert(N == 2 && "Invalid number of operands!");
    2401          99 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2402          99 :     Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
    2403          33 :   }
    2404             : 
    2405          31 :   void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
    2406             :     assert(N == 2 && "Invalid number of operands!");
    2407          31 :     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
    2408          93 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2409          62 :     Inst.addOperand(MCOperand::createImm(Val));
    2410          31 :   }
    2411             : 
    2412          26 :   void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
    2413             :     assert(N == 2 && "Invalid number of operands!");
    2414          26 :     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
    2415          78 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2416          52 :     Inst.addOperand(MCOperand::createImm(Val));
    2417          26 :   }
    2418             : 
    2419          22 :   void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
    2420             :     assert(N == 2 && "Invalid number of operands!");
    2421          22 :     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
    2422          66 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2423          44 :     Inst.addOperand(MCOperand::createImm(Val));
    2424          22 :   }
    2425             : 
    2426          25 :   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
    2427             :     assert(N == 2 && "Invalid number of operands!");
    2428          25 :     int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
    2429          75 :     Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
    2430          50 :     Inst.addOperand(MCOperand::createImm(Val));
    2431          25 :   }
    2432             : 
    2433          16 :   void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
    2434             :     assert(N == 1 && "Invalid number of operands!");
    2435          32 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2436             :     assert(CE && "non-constant post-idx-imm8 operand!");
    2437          16 :     int Imm = CE->getValue();
    2438          16 :     bool isAdd = Imm >= 0;
    2439          16 :     if (Imm == INT32_MIN) Imm = 0;
    2440          16 :     Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
    2441          48 :     Inst.addOperand(MCOperand::createImm(Imm));
    2442          16 :   }
    2443             : 
    2444         208 :   void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
    2445             :     assert(N == 1 && "Invalid number of operands!");
    2446         416 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2447             :     assert(CE && "non-constant post-idx-imm8s4 operand!");
    2448         208 :     int Imm = CE->getValue();
    2449         208 :     bool isAdd = Imm >= 0;
    2450         208 :     if (Imm == INT32_MIN) Imm = 0;
    2451             :     // Immediate is scaled by 4.
    2452         208 :     Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
    2453         624 :     Inst.addOperand(MCOperand::createImm(Imm));
    2454         208 :   }
    2455             : 
    2456          12 :   void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
    2457             :     assert(N == 2 && "Invalid number of operands!");
    2458          36 :     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
    2459          36 :     Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
    2460          12 :   }
    2461             : 
    2462          36 :   void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
    2463             :     assert(N == 2 && "Invalid number of operands!");
    2464         108 :     Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
    2465             :     // The sign, shift type, and shift amount are encoded in a single operand
    2466             :     // using the AM2 encoding helpers.
    2467          36 :     ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
    2468          36 :     unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
    2469          72 :                                      PostIdxReg.ShiftTy);
    2470         108 :     Inst.addOperand(MCOperand::createImm(Imm));
    2471          36 :   }
    2472             : 
    2473             :   void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
    2474             :     assert(N == 1 && "Invalid number of operands!");
    2475         627 :     Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
    2476             :   }
    2477             : 
    2478             :   void addBankedRegOperands(MCInst &Inst, unsigned N) const {
    2479             :     assert(N == 1 && "Invalid number of operands!");
    2480         396 :     Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
    2481             :   }
    2482             : 
    2483             :   void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
    2484             :     assert(N == 1 && "Invalid number of operands!");
    2485         117 :     Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
    2486             :   }
    2487             : 
    2488        1075 :   void addVecListOperands(MCInst &Inst, unsigned N) const {
    2489             :     assert(N == 1 && "Invalid number of operands!");
    2490        3225 :     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
    2491        1075 :   }
    2492             : 
    2493         327 :   void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
    2494             :     assert(N == 2 && "Invalid number of operands!");
    2495         981 :     Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
    2496         981 :     Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
    2497         327 :   }
    2498             : 
    2499             :   void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
    2500             :     assert(N == 1 && "Invalid number of operands!");
    2501          54 :     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
    2502             :   }
    2503             : 
    2504             :   void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
    2505             :     assert(N == 1 && "Invalid number of operands!");
    2506         198 :     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
    2507             :   }
    2508             : 
    2509             :   void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
    2510             :     assert(N == 1 && "Invalid number of operands!");
    2511         237 :     Inst.addOperand(MCOperand::createImm(getVectorIndex()));
    2512             :   }
    2513             : 
    2514           4 :   void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
    2515             :     assert(N == 1 && "Invalid number of operands!");
    2516             :     // The immediate encodes the type of constant as well as the value.
    2517             :     // Mask in that this is an i8 splat.
    2518           8 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2519          12 :     Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
    2520           4 :   }
    2521             : 
    2522          16 :   void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
    2523             :     assert(N == 1 && "Invalid number of operands!");
    2524             :     // The immediate encodes the type of constant as well as the value.
    2525          32 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2526          16 :     unsigned Value = CE->getValue();
    2527          16 :     Value = ARM_AM::encodeNEONi16splat(Value);
    2528          48 :     Inst.addOperand(MCOperand::createImm(Value));
    2529          16 :   }
    2530             : 
    2531           4 :   void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
    2532             :     assert(N == 1 && "Invalid number of operands!");
    2533             :     // The immediate encodes the type of constant as well as the value.
    2534           8 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2535           4 :     unsigned Value = CE->getValue();
    2536           8 :     Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
    2537          12 :     Inst.addOperand(MCOperand::createImm(Value));
    2538           4 :   }
    2539             : 
    2540          11 :   void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
    2541             :     assert(N == 1 && "Invalid number of operands!");
    2542             :     // The immediate encodes the type of constant as well as the value.
    2543          22 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2544          11 :     unsigned Value = CE->getValue();
    2545          11 :     Value = ARM_AM::encodeNEONi32splat(Value);
    2546          33 :     Inst.addOperand(MCOperand::createImm(Value));
    2547          11 :   }
    2548             : 
    2549           8 :   void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
    2550             :     assert(N == 1 && "Invalid number of operands!");
    2551             :     // The immediate encodes the type of constant as well as the value.
    2552          16 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2553           8 :     unsigned Value = CE->getValue();
    2554          16 :     Value = ARM_AM::encodeNEONi32splat(~Value);
    2555          24 :     Inst.addOperand(MCOperand::createImm(Value));
    2556           8 :   }
    2557             : 
    2558           6 :   void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
    2559             :     assert(N == 1 && "Invalid number of operands!");
    2560             :     // The immediate encodes the type of constant as well as the value.
    2561          12 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2562           6 :     unsigned Value = CE->getValue();
    2563             :     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
    2564             :             Inst.getOpcode() == ARM::VMOVv16i8) &&
    2565             :            "All vmvn instructions that wants to replicate non-zero byte "
    2566             :            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
    2567           6 :     unsigned B = ((~Value) & 0xff);
    2568           6 :     B |= 0xe00; // cmode = 0b1110
    2569          18 :     Inst.addOperand(MCOperand::createImm(B));
    2570           6 :   }
    2571          38 :   void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
    2572             :     assert(N == 1 && "Invalid number of operands!");
    2573             :     // The immediate encodes the type of constant as well as the value.
    2574          76 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2575          38 :     unsigned Value = CE->getValue();
    2576          38 :     if (Value >= 256 && Value <= 0xffff)
    2577          12 :       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
    2578          26 :     else if (Value > 0xffff && Value <= 0xffffff)
    2579          12 :       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
    2580          14 :     else if (Value > 0xffffff)
    2581           7 :       Value = (Value >> 24) | 0x600;
    2582         114 :     Inst.addOperand(MCOperand::createImm(Value));
    2583          38 :   }
    2584             : 
    2585           6 :   void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
    2586             :     assert(N == 1 && "Invalid number of operands!");
    2587             :     // The immediate encodes the type of constant as well as the value.
    2588          12 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2589           6 :     unsigned Value = CE->getValue();
    2590             :     assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
    2591             :             Inst.getOpcode() == ARM::VMOVv16i8) &&
    2592             :            "All instructions that wants to replicate non-zero byte "
    2593             :            "always must be replaced with VMOVv8i8 or VMOVv16i8.");
    2594           6 :     unsigned B = Value & 0xff;
    2595           6 :     B |= 0xe00; // cmode = 0b1110
    2596          18 :     Inst.addOperand(MCOperand::createImm(B));
    2597           6 :   }
    2598           0 :   void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
    2599             :     assert(N == 1 && "Invalid number of operands!");
    2600             :     // The immediate encodes the type of constant as well as the value.
    2601           0 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2602           0 :     unsigned Value = ~CE->getValue();
    2603           0 :     if (Value >= 256 && Value <= 0xffff)
    2604           0 :       Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
    2605           0 :     else if (Value > 0xffff && Value <= 0xffffff)
    2606           0 :       Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
    2607           0 :     else if (Value > 0xffffff)
    2608           0 :       Value = (Value >> 24) | 0x600;
    2609           0 :     Inst.addOperand(MCOperand::createImm(Value));
    2610           0 :   }
    2611             : 
    2612           4 :   void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
    2613             :     assert(N == 1 && "Invalid number of operands!");
    2614             :     // The immediate encodes the type of constant as well as the value.
    2615           8 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
    2616           4 :     uint64_t Value = CE->getValue();
    2617           4 :     unsigned Imm = 0;
    2618          36 :     for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
    2619          32 :       Imm |= (Value & 1) << i;
    2620             :     }
    2621          12 :     Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
    2622           4 :   }
    2623             : 
    2624             :   void print(raw_ostream &OS) const override;
    2625             : 
    2626             :   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
    2627        2768 :     auto Op = make_unique<ARMOperand>(k_ITCondMask);
    2628        2768 :     Op->ITMask.Mask = Mask;
    2629        2768 :     Op->StartLoc = S;
    2630        2768 :     Op->EndLoc = S;
    2631             :     return Op;
    2632             :   }
    2633             : 
    2634             :   static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
    2635             :                                                     SMLoc S) {
    2636       22011 :     auto Op = make_unique<ARMOperand>(k_CondCode);
    2637       22011 :     Op->CC.Val = CC;
    2638       22011 :     Op->StartLoc = S;
    2639       22011 :     Op->EndLoc = S;
    2640             :     return Op;
    2641             :   }
    2642             : 
    2643             :   static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
    2644         886 :     auto Op = make_unique<ARMOperand>(k_CoprocNum);
    2645         886 :     Op->Cop.Val = CopVal;
    2646         886 :     Op->StartLoc = S;
    2647         886 :     Op->EndLoc = S;
    2648             :     return Op;
    2649             :   }
    2650             : 
    2651             :   static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
    2652        1021 :     auto Op = make_unique<ARMOperand>(k_CoprocReg);
    2653        1021 :     Op->Cop.Val = CopVal;
    2654        1021 :     Op->StartLoc = S;
    2655        1021 :     Op->EndLoc = S;
    2656             :     return Op;
    2657             :   }
    2658             : 
    2659             :   static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
    2660             :                                                         SMLoc E) {
    2661          78 :     auto Op = make_unique<ARMOperand>(k_CoprocOption);
    2662          78 :     Op->Cop.Val = Val;
    2663          78 :     Op->StartLoc = S;
    2664          78 :     Op->EndLoc = E;
    2665             :     return Op;
    2666             :   }
    2667             : 
    2668             :   static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
    2669        4584 :     auto Op = make_unique<ARMOperand>(k_CCOut);
    2670        4584 :     Op->Reg.RegNum = RegNum;
    2671        4584 :     Op->StartLoc = S;
    2672        4584 :     Op->EndLoc = S;
    2673             :     return Op;
    2674             :   }
    2675             : 
    2676       35867 :   static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
    2677       35867 :     auto Op = make_unique<ARMOperand>(k_Token);
    2678       71734 :     Op->Tok.Data = Str.data();
    2679       71734 :     Op->Tok.Length = Str.size();
    2680       35867 :     Op->StartLoc = S;
    2681       35867 :     Op->EndLoc = S;
    2682       35867 :     return Op;
    2683             :   }
    2684             : 
    2685             :   static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
    2686             :                                                SMLoc E) {
    2687       32409 :     auto Op = make_unique<ARMOperand>(k_Register);
    2688       32409 :     Op->Reg.RegNum = RegNum;
    2689       32409 :     Op->StartLoc = S;
    2690       32409 :     Op->EndLoc = E;
    2691             :     return Op;
    2692             :   }
    2693             : 
    2694             :   static std::unique_ptr<ARMOperand>
    2695         241 :   CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
    2696             :                         unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
    2697             :                         SMLoc E) {
    2698         241 :     auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
    2699         241 :     Op->RegShiftedReg.ShiftTy = ShTy;
    2700         241 :     Op->RegShiftedReg.SrcReg = SrcReg;
    2701         241 :     Op->RegShiftedReg.ShiftReg = ShiftReg;
    2702         241 :     Op->RegShiftedReg.ShiftImm = ShiftImm;
    2703         241 :     Op->StartLoc = S;
    2704         241 :     Op->EndLoc = E;
    2705         241 :     return Op;
    2706             :   }
    2707             : 
    2708             :   static std::unique_ptr<ARMOperand>
    2709         637 :   CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
    2710             :                          unsigned ShiftImm, SMLoc S, SMLoc E) {
    2711         637 :     auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
    2712         637 :     Op->RegShiftedImm.ShiftTy = ShTy;
    2713         637 :     Op->RegShiftedImm.SrcReg = SrcReg;
    2714         637 :     Op->RegShiftedImm.ShiftImm = ShiftImm;
    2715         637 :     Op->StartLoc = S;
    2716         637 :     Op->EndLoc = E;
    2717         637 :     return Op;
    2718             :   }
    2719             : 
    2720             :   static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
    2721             :                                                       SMLoc S, SMLoc E) {
    2722          32 :     auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
    2723          32 :     Op->ShifterImm.isASR = isASR;
    2724          32 :     Op->ShifterImm.Imm = Imm;
    2725          32 :     Op->StartLoc = S;
    2726          32 :     Op->EndLoc = E;
    2727             :     return Op;
    2728             :   }
    2729             : 
    2730             :   static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
    2731             :                                                   SMLoc E) {
    2732         218 :     auto Op = make_unique<ARMOperand>(k_RotateImmediate);
    2733         218 :     Op->RotImm.Imm = Imm;
    2734         218 :     Op->StartLoc = S;
    2735         218 :     Op->EndLoc = E;
    2736             :     return Op;
    2737             :   }
    2738             : 
    2739             :   static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
    2740             :                                                   SMLoc S, SMLoc E) {
    2741        1059 :     auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
    2742        1059 :     Op->ModImm.Bits = Bits;
    2743        1059 :     Op->ModImm.Rot = Rot;
    2744        1059 :     Op->StartLoc = S;
    2745        1059 :     Op->EndLoc = E;
    2746             :     return Op;
    2747             :   }
    2748             : 
    2749             :   static std::unique_ptr<ARMOperand>
    2750             :   CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) {
    2751         386 :     auto Op = make_unique<ARMOperand>(k_ConstantPoolImmediate);
    2752         386 :     Op->Imm.Val = Val;
    2753         386 :     Op->StartLoc = S;
    2754         386 :     Op->EndLoc = E;
    2755             :     return Op;
    2756             :   }
    2757             : 
    2758             :   static std::unique_ptr<ARMOperand>
    2759             :   CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
    2760          34 :     auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
    2761          34 :     Op->Bitfield.LSB = LSB;
    2762          34 :     Op->Bitfield.Width = Width;
    2763          34 :     Op->StartLoc = S;
    2764          34 :     Op->EndLoc = E;
    2765             :     return Op;
    2766             :   }
    2767             : 
    2768             :   static std::unique_ptr<ARMOperand>
    2769         768 :   CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
    2770             :                 SMLoc StartLoc, SMLoc EndLoc) {
    2771             :     assert (Regs.size() > 0 && "RegList contains no registers?");
    2772         768 :     KindTy Kind = k_RegisterList;
    2773             : 
    2774        1720 :     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
    2775             :       Kind = k_DPRRegisterList;
    2776         673 :     else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
    2777        2019 :              contains(Regs.front().second))
    2778          34 :       Kind = k_SPRRegisterList;
    2779             : 
    2780             :     // Sort based on the register encoding values.
    2781        2304 :     array_pod_sort(Regs.begin(), Regs.end());
    2782             : 
    2783         768 :     auto Op = make_unique<ARMOperand>(Kind);
    2784        2288 :     for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
    2785        2304 :            I = Regs.begin(), E = Regs.end(); I != E; ++I)
    2786        2288 :       Op->Registers.push_back(I->second);
    2787         768 :     Op->StartLoc = StartLoc;
    2788         768 :     Op->EndLoc = EndLoc;
    2789         768 :     return Op;
    2790             :   }
    2791             : 
    2792        1549 :   static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
    2793             :                                                       unsigned Count,
    2794             :                                                       bool isDoubleSpaced,
    2795             :                                                       SMLoc S, SMLoc E) {
    2796        1549 :     auto Op = make_unique<ARMOperand>(k_VectorList);
    2797        1549 :     Op->VectorList.RegNum = RegNum;
    2798        1549 :     Op->VectorList.Count = Count;
    2799        1549 :     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
    2800        1549 :     Op->StartLoc = S;
    2801        1549 :     Op->EndLoc = E;
    2802        1549 :     return Op;
    2803             :   }
    2804             : 
    2805             :   static std::unique_ptr<ARMOperand>
    2806         480 :   CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
    2807             :                            SMLoc S, SMLoc E) {
    2808         480 :     auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
    2809         480 :     Op->VectorList.RegNum = RegNum;
    2810         480 :     Op->VectorList.Count = Count;
    2811         480 :     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
    2812         480 :     Op->StartLoc = S;
    2813         480 :     Op->EndLoc = E;
    2814         480 :     return Op;
    2815             :   }
    2816             : 
    2817             :   static std::unique_ptr<ARMOperand>
    2818         786 :   CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
    2819             :                           bool isDoubleSpaced, SMLoc S, SMLoc E) {
    2820         786 :     auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
    2821         786 :     Op->VectorList.RegNum = RegNum;
    2822         786 :     Op->VectorList.Count = Count;
    2823         786 :     Op->VectorList.LaneIndex = Index;
    2824         786 :     Op->VectorList.isDoubleSpaced = isDoubleSpaced;
    2825         786 :     Op->StartLoc = S;
    2826         786 :     Op->EndLoc = E;
    2827         786 :     return Op;
    2828             :   }
    2829             : 
    2830             :   static std::unique_ptr<ARMOperand>
    2831             :   CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
    2832         267 :     auto Op = make_unique<ARMOperand>(k_VectorIndex);
    2833         267 :     Op->VectorIndex.Val = Idx;
    2834         267 :     Op->StartLoc = S;
    2835         267 :     Op->EndLoc = E;
    2836             :     return Op;
    2837             :   }
    2838             : 
    2839             :   static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
    2840             :                                                SMLoc E) {
    2841        5449 :     auto Op = make_unique<ARMOperand>(k_Immediate);
    2842        5449 :     Op->Imm.Val = Val;
    2843        5449 :     Op->StartLoc = S;
    2844        5449 :     Op->EndLoc = E;
    2845             :     return Op;
    2846             :   }
    2847             : 
    2848             :   static std::unique_ptr<ARMOperand>
    2849        5288 :   CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
    2850             :             unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
    2851             :             unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
    2852             :             SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
    2853        5288 :     auto Op = make_unique<ARMOperand>(k_Memory);
    2854        5288 :     Op->Memory.BaseRegNum = BaseRegNum;
    2855        5288 :     Op->Memory.OffsetImm = OffsetImm;
    2856        5288 :     Op->Memory.OffsetRegNum = OffsetRegNum;
    2857        5288 :     Op->Memory.ShiftType = ShiftType;
    2858        5288 :     Op->Memory.ShiftImm = ShiftImm;
    2859        5288 :     Op->Memory.Alignment = Alignment;
    2860        5288 :     Op->Memory.isNegative = isNegative;
    2861        5288 :     Op->StartLoc = S;
    2862        5288 :     Op->EndLoc = E;
    2863        5288 :     Op->AlignmentLoc = AlignmentLoc;
    2864        5288 :     return Op;
    2865             :   }
    2866             : 
    2867             :   static std::unique_ptr<ARMOperand>
    2868          71 :   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
    2869             :                    unsigned ShiftImm, SMLoc S, SMLoc E) {
    2870          71 :     auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
    2871          71 :     Op->PostIdxReg.RegNum = RegNum;
    2872          71 :     Op->PostIdxReg.isAdd = isAdd;
    2873          71 :     Op->PostIdxReg.ShiftTy = ShiftTy;
    2874          71 :     Op->PostIdxReg.ShiftImm = ShiftImm;
    2875          71 :     Op->StartLoc = S;
    2876          71 :     Op->EndLoc = E;
    2877          71 :     return Op;
    2878             :   }
    2879             : 
    2880             :   static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
    2881             :                                                          SMLoc S) {
    2882         254 :     auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
    2883         254 :     Op->MBOpt.Val = Opt;
    2884         254 :     Op->StartLoc = S;
    2885         254 :     Op->EndLoc = S;
    2886             :     return Op;
    2887             :   }
    2888             : 
    2889             :   static std::unique_ptr<ARMOperand>
    2890             :   CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
    2891          18 :     auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
    2892          18 :     Op->ISBOpt.Val = Opt;
    2893          18 :     Op->StartLoc = S;
    2894          18 :     Op->EndLoc = S;
    2895             :     return Op;
    2896             :   }
    2897             : 
    2898             :   static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
    2899             :                                                       SMLoc S) {
    2900          40 :     auto Op = make_unique<ARMOperand>(k_ProcIFlags);
    2901          40 :     Op->IFlags.Val = IFlags;
    2902          40 :     Op->StartLoc = S;
    2903          40 :     Op->EndLoc = S;
    2904             :     return Op;
    2905             :   }
    2906             : 
    2907             :   static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
    2908         213 :     auto Op = make_unique<ARMOperand>(k_MSRMask);
    2909         213 :     Op->MMask.Val = MMask;
    2910         213 :     Op->StartLoc = S;
    2911         213 :     Op->EndLoc = S;
    2912             :     return Op;
    2913             :   }
    2914             : 
    2915             :   static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
    2916         132 :     auto Op = make_unique<ARMOperand>(k_BankedReg);
    2917         132 :     Op->BankedReg.Val = Reg;
    2918         132 :     Op->StartLoc = S;
    2919         132 :     Op->EndLoc = S;
    2920             :     return Op;
    2921             :   }
    2922             : };
    2923             : 
    2924             : } // end anonymous namespace.
    2925             : 
    2926           0 : void ARMOperand::print(raw_ostream &OS) const {
    2927           0 :   switch (Kind) {
    2928           0 :   case k_CondCode:
    2929           0 :     OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
    2930           0 :     break;
    2931           0 :   case k_CCOut:
    2932           0 :     OS << "<ccout " << getReg() << ">";
    2933           0 :     break;
    2934           0 :   case k_ITCondMask: {
    2935             :     static const char *const MaskStr[] = {
    2936             :       "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
    2937             :       "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
    2938             :     };
    2939             :     assert((ITMask.Mask & 0xf) == ITMask.Mask);
    2940           0 :     OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
    2941           0 :     break;
    2942             :   }
    2943           0 :   case k_CoprocNum:
    2944           0 :     OS << "<coprocessor number: " << getCoproc() << ">";
    2945           0 :     break;
    2946           0 :   case k_CoprocReg:
    2947           0 :     OS << "<coprocessor register: " << getCoproc() << ">";
    2948           0 :     break;
    2949           0 :   case k_CoprocOption:
    2950           0 :     OS << "<coprocessor option: " << CoprocOption.Val << ">";
    2951           0 :     break;
    2952           0 :   case k_MSRMask:
    2953           0 :     OS << "<mask: " << getMSRMask() << ">";
    2954           0 :     break;
    2955           0 :   case k_BankedReg:
    2956           0 :     OS << "<banked reg: " << getBankedReg() << ">";
    2957           0 :     break;
    2958           0 :   case k_Immediate:
    2959           0 :     OS << *getImm();
    2960             :     break;
    2961           0 :   case k_MemBarrierOpt:
    2962           0 :     OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
    2963           0 :     break;
    2964           0 :   case k_InstSyncBarrierOpt:
    2965           0 :     OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
    2966           0 :     break;
    2967           0 :   case k_Memory:
    2968           0 :     OS << "<memory "
    2969           0 :        << " base:" << Memory.BaseRegNum;
    2970           0 :     OS << ">";
    2971           0 :     break;
    2972           0 :   case k_PostIndexRegister:
    2973           0 :     OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
    2974           0 :        << PostIdxReg.RegNum;
    2975           0 :     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
    2976           0 :       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
    2977           0 :          << PostIdxReg.ShiftImm;
    2978           0 :     OS << ">";
    2979           0 :     break;
    2980           0 :   case k_ProcIFlags: {
    2981           0 :     OS << "<ARM_PROC::";
    2982           0 :     unsigned IFlags = getProcIFlags();
    2983           0 :     for (int i=2; i >= 0; --i)
    2984           0 :       if (IFlags & (1 << i))
    2985           0 :         OS << ARM_PROC::IFlagsToString(1 << i);
    2986           0 :     OS << ">";
    2987           0 :     break;
    2988             :   }
    2989           0 :   case k_Register:
    2990           0 :     OS << "<register " << getReg() << ">";
    2991           0 :     break;
    2992           0 :   case k_ShifterImmediate:
    2993           0 :     OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
    2994           0 :        << " #" << ShifterImm.Imm << ">";
    2995           0 :     break;
    2996           0 :   case k_ShiftedRegister:
    2997           0 :     OS << "<so_reg_reg "
    2998           0 :        << RegShiftedReg.SrcReg << " "
    2999           0 :        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
    3000           0 :        << " " << RegShiftedReg.ShiftReg << ">";
    3001           0 :     break;
    3002           0 :   case k_ShiftedImmediate:
    3003           0 :     OS << "<so_reg_imm "
    3004           0 :        << RegShiftedImm.SrcReg << " "
    3005           0 :        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
    3006           0 :        << " #" << RegShiftedImm.ShiftImm << ">";
    3007           0 :     break;
    3008           0 :   case k_RotateImmediate:
    3009           0 :     OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
    3010           0 :     break;
    3011           0 :   case k_ModifiedImmediate:
    3012           0 :     OS << "<mod_imm #" << ModImm.Bits << ", #"
    3013           0 :        <<  ModImm.Rot << ")>";
    3014           0 :     break;
    3015           0 :   case k_ConstantPoolImmediate:
    3016           0 :     OS << "<constant_pool_imm #" << *getConstantPoolImm();
    3017             :     break;
    3018           0 :   case k_BitfieldDescriptor:
    3019           0 :     OS << "<bitfield " << "lsb: " << Bitfield.LSB
    3020           0 :        << ", width: " << Bitfield.Width << ">";
    3021           0 :     break;
    3022           0 :   case k_RegisterList:
    3023             :   case k_DPRRegisterList:
    3024             :   case k_SPRRegisterList: {
    3025           0 :     OS << "<register_list ";
    3026             : 
    3027           0 :     const SmallVectorImpl<unsigned> &RegList = getRegList();
    3028             :     for (SmallVectorImpl<unsigned>::const_iterator
    3029           0 :            I = RegList.begin(), E = RegList.end(); I != E; ) {
    3030           0 :       OS << *I;
    3031           0 :       if (++I < E) OS << ", ";
    3032             :     }
    3033             : 
    3034           0 :     OS << ">";
    3035           0 :     break;
    3036             :   }
    3037           0 :   case k_VectorList:
    3038           0 :     OS << "<vector_list " << VectorList.Count << " * "
    3039           0 :        << VectorList.RegNum << ">";
    3040           0 :     break;
    3041           0 :   case k_VectorListAllLanes:
    3042           0 :     OS << "<vector_list(all lanes) " << VectorList.Count << " * "
    3043           0 :        << VectorList.RegNum << ">";
    3044           0 :     break;
    3045           0 :   case k_VectorListIndexed:
    3046           0 :     OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
    3047           0 :        << VectorList.Count << " * " << VectorList.RegNum << ">";
    3048           0 :     break;
    3049           0 :   case k_Token:
    3050           0 :     OS << "'" << getToken() << "'";
    3051           0 :     break;
    3052           0 :   case k_VectorIndex:
    3053           0 :     OS << "<vectorindex " << getVectorIndex() << ">";
    3054           0 :     break;
    3055             :   }
    3056           0 : }
    3057             : 
    3058             : /// @name Auto-generated Match Functions
    3059             : /// {
    3060             : 
    3061             : static unsigned MatchRegisterName(StringRef Name);
    3062             : 
    3063             : /// }
    3064             : 
    3065          42 : bool ARMAsmParser::ParseRegister(unsigned &RegNo,
    3066             :                                  SMLoc &StartLoc, SMLoc &EndLoc) {
    3067          42 :   const AsmToken &Tok = getParser().getTok();
    3068          42 :   StartLoc = Tok.getLoc();
    3069          42 :   EndLoc = Tok.getEndLoc();
    3070          42 :   RegNo = tryParseRegister();
    3071             : 
    3072          42 :   return (RegNo == (unsigned)-1);
    3073             : }
    3074             : 
    3075             : /// Try to parse a register name.  The token must be an Identifier when called,
    3076             : /// and if it is a register name the token is eaten and the register number is
    3077             : /// returned.  Otherwise return -1.
    3078             : ///
    3079       49648 : int ARMAsmParser::tryParseRegister() {
    3080       49648 :   MCAsmParser &Parser = getParser();
    3081       49648 :   const AsmToken &Tok = Parser.getTok();
    3082       49648 :   if (Tok.isNot(AsmToken::Identifier)) return -1;
    3083             : 
    3084       49600 :   std::string lowerCase = Tok.getString().lower();
    3085       49600 :   unsigned RegNum = MatchRegisterName(lowerCase);
    3086       49600 :   if (!RegNum) {
    3087        2664 :     RegNum = StringSwitch<unsigned>(lowerCase)
    3088        3996 :       .Case("r13", ARM::SP)
    3089        3996 :       .Case("r14", ARM::LR)
    3090        3996 :       .Case("r15", ARM::PC)
    3091        3996 :       .Case("ip", ARM::R12)
    3092             :       // Additional register name aliases for 'gas' compatibility.
    3093        3996 :       .Case("a1", ARM::R0)
    3094        3996 :       .Case("a2", ARM::R1)
    3095        3996 :       .Case("a3", ARM::R2)
    3096        3996 :       .Case("a4", ARM::R3)
    3097        3996 :       .Case("v1", ARM::R4)
    3098        3996 :       .Case("v2", ARM::R5)
    3099        3996 :       .Case("v3", ARM::R6)
    3100        3996 :       .Case("v4", ARM::R7)
    3101        3996 :       .Case("v5", ARM::R8)
    3102        3996 :       .Case("v6", ARM::R9)
    3103        3996 :       .Case("v7", ARM::R10)
    3104        3996 :       .Case("v8", ARM::R11)
    3105        3996 :       .Case("sb", ARM::R9)
    3106        3996 :       .Case("sl", ARM::R10)
    3107        3996 :       .Case("fp", ARM::R11)
    3108        1332 :       .Default(0);
    3109             :   }
    3110       48410 :   if (!RegNum) {
    3111             :     // Check for aliases registered via .req. Canonicalize to lower case.
    3112             :     // That's more consistent since register names are case insensitive, and
    3113             :     // it's how the original entry was passed in from MC/MCParser/AsmParser.
    3114        3570 :     StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
    3115             :     // If no match, return failure.
    3116        3570 :     if (Entry == RegisterReqs.end())
    3117             :       return -1;
    3118           5 :     Parser.Lex(); // Eat identifier token.
    3119           5 :     return Entry->getValue();
    3120             :   }
    3121             : 
    3122             :   // Some FPUs only have 16 D registers, so D16-D31 are invalid
    3123       48410 :   if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
    3124             :     return -1;
    3125             : 
    3126       48387 :   Parser.Lex(); // Eat identifier token.
    3127             : 
    3128       48387 :   return RegNum;
    3129             : }
    3130             : 
    3131             : // Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
    3132             : // If a recoverable error occurs, return 1. If an irrecoverable error
    3133             : // occurs, return -1. An irrecoverable error is one where tokens have been
    3134             : // consumed in the process of trying to parse the shifter (i.e., when it is
    3135             : // indeed a shifter operand, but malformed).
    3136        1211 : int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
    3137        1211 :   MCAsmParser &Parser = getParser();
    3138        1211 :   SMLoc S = Parser.getTok().getLoc();
    3139        1211 :   const AsmToken &Tok = Parser.getTok();
    3140        1211 :   if (Tok.isNot(AsmToken::Identifier))
    3141             :     return -1; 
    3142             : 
    3143        1208 :   std::string lowerCase = Tok.getString().lower();
    3144        1208 :   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
    3145        3624 :       .Case("asl", ARM_AM::lsl)
    3146        3624 :       .Case("lsl", ARM_AM::lsl)
    3147        3624 :       .Case("lsr", ARM_AM::lsr)
    3148        3624 :       .Case("asr", ARM_AM::asr)
    3149        3624 :       .Case("ror", ARM_AM::ror)
    3150        3624 :       .Case("rrx", ARM_AM::rrx)
    3151        2416 :       .Default(ARM_AM::no_shift);
    3152             : 
    3153         896 :   if (ShiftTy == ARM_AM::no_shift)
    3154             :     return 1;
    3155             : 
    3156         896 :   Parser.Lex(); // Eat the operator.
    3157             : 
    3158             :   // The source register for the shift has already been added to the
    3159             :   // operand list, so we need to pop it off and combine it into the shifted
    3160             :   // register operand instead.
    3161             :   std::unique_ptr<ARMOperand> PrevOp(
    3162        4480 :       (ARMOperand *)Operands.pop_back_val().release());
    3163        1792 :   if (!PrevOp->isReg())
    3164           0 :     return Error(PrevOp->getStartLoc(), "shift must be of a register");
    3165        1792 :   int SrcReg = PrevOp->getReg();
    3166             : 
    3167         896 :   SMLoc EndLoc;
    3168         896 :   int64_t Imm = 0;
    3169         896 :   int ShiftReg = 0;
    3170         896 :   if (ShiftTy == ARM_AM::rrx) {
    3171             :     // RRX Doesn't have an explicit shift amount. The encoder expects
    3172             :     // the shift register to be the same as the source register. Seems odd,
    3173             :     // but OK.
    3174             :     ShiftReg = SrcReg;
    3175             :   } else {
    3176             :     // Figure out if this is shifted by a constant or a register (for non-RRX).
    3177        1087 :     if (Parser.getTok().is(AsmToken::Hash) ||
    3178         241 :         Parser.getTok().is(AsmToken::Dollar)) {
    3179         605 :       Parser.Lex(); // Eat hash.
    3180         605 :       SMLoc ImmLoc = Parser.getTok().getLoc();
    3181         605 :       const MCExpr *ShiftExpr = nullptr;
    3182         605 :       if (getParser().parseExpression(ShiftExpr, EndLoc)) {
    3183           0 :         Error(ImmLoc, "invalid immediate shift value");
    3184          18 :         return -1;
    3185             :       }
    3186             :       // The expression must be evaluatable as an immediate.
    3187        1208 :       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
    3188             :       if (!CE) {
    3189           6 :         Error(ImmLoc, "invalid immediate shift value");
    3190           2 :         return -1;
    3191             :       }
    3192             :       // Range check the immediate.
    3193             :       // lsl, ror: 0 <= imm <= 31
    3194             :       // lsr, asr: 0 <= imm <= 32
    3195         603 :       Imm = CE->getValue();
    3196        1198 :       if (Imm < 0 ||
    3197        1456 :           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
    3198         916 :           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
    3199          48 :         Error(ImmLoc, "immediate shift value out of range");
    3200          16 :         return -1;
    3201             :       }
    3202             :       // shift by zero is a nop. Always send it through as lsl.
    3203             :       // ('as' compatibility)
    3204         587 :       if (Imm == 0)
    3205          60 :         ShiftTy = ARM_AM::lsl;
    3206         241 :     } else if (Parser.getTok().is(AsmToken::Identifier)) {
    3207         241 :       SMLoc L = Parser.getTok().getLoc();
    3208         241 :       EndLoc = Parser.getTok().getEndLoc();
    3209         241 :       ShiftReg = tryParseRegister();
    3210         241 :       if (ShiftReg == -1) {
    3211           0 :         Error(L, "expected immediate or register in shift operand");
    3212           0 :         return -1;
    3213             :       }
    3214             :     } else {
    3215           0 :       Error(Parser.getTok().getLoc(),
    3216             :             "expected immediate or register in shift operand");
    3217           0 :       return -1;
    3218             :     }
    3219             :   }
    3220             : 
    3221         878 :   if (ShiftReg && ShiftTy != ARM_AM::rrx)
    3222         723 :     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
    3223             :                                                          ShiftReg, Imm,
    3224             :                                                          S, EndLoc));
    3225             :   else
    3226        1911 :     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
    3227             :                                                           S, EndLoc));
    3228             : 
    3229             :   return 0;
    3230             : }
    3231             : 
    3232             : 
    3233             : /// Try to parse a register name.  The token must be an Identifier when called.
    3234             : /// If it's a register, an AsmOperand is created. Another AsmOperand is created
    3235             : /// if there is a "writeback". 'true' if it's not a register.
    3236             : ///
    3237             : /// TODO this is likely to change to allow different register types and or to
    3238             : /// parse for a specific register type.
    3239       33575 : bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
    3240       33575 :   MCAsmParser &Parser = getParser();
    3241       33575 :   const AsmToken &RegTok = Parser.getTok();
    3242       33575 :   int RegNo = tryParseRegister();
    3243       33575 :   if (RegNo == -1)
    3244             :     return true;
    3245             : 
    3246      129468 :   Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
    3247             :                                            RegTok.getEndLoc()));
    3248             : 
    3249       32367 :   const AsmToken &ExclaimTok = Parser.getTok();
    3250       32367 :   if (ExclaimTok.is(AsmToken::Exclaim)) {
    3251        1056 :     Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
    3252             :                                                ExclaimTok.getLoc()));
    3253         352 :     Parser.Lex(); // Eat exclaim token
    3254         352 :     return false;
    3255             :   }
    3256             : 
    3257             :   // Also check for an index operand. This is only legal for vector registers,
    3258             :   // but that'll get caught OK in operand matching, so we don't need to
    3259             :   // explicitly filter everything else out here.
    3260       32015 :   if (Parser.getTok().is(AsmToken::LBrac)) {
    3261         270 :     SMLoc SIdx = Parser.getTok().getLoc();
    3262         270 :     Parser.Lex(); // Eat left bracket token.
    3263             : 
    3264             :     const MCExpr *ImmVal;
    3265         270 :     if (getParser().parseExpression(ImmVal))
    3266           3 :       return true;
    3267         537 :     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
    3268             :     if (!MCE)
    3269           9 :       return TokError("immediate value expected for vector index");
    3270             : 
    3271         267 :     if (Parser.getTok().isNot(AsmToken::RBrac))
    3272           0 :       return Error(Parser.getTok().getLoc(), "']' expected");
    3273             : 
    3274         267 :     SMLoc E = Parser.getTok().getEndLoc();
    3275         267 :     Parser.Lex(); // Eat right bracket token.
    3276             : 
    3277        1335 :     Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
    3278             :                                                      SIdx, E,
    3279             :                                                      getContext()));
    3280             :   }
    3281             : 
    3282             :   return false;
    3283             : }
    3284             : 
    3285             : /// MatchCoprocessorOperandName - Try to parse an coprocessor related
    3286             : /// instruction with a symbolic operand name.
    3287             : /// We accept "crN" syntax for GAS compatibility.
    3288             : /// <operand-name> ::= <prefix><number>
    3289             : /// If CoprocOp is 'c', then:
    3290             : ///   <prefix> ::= c | cr
    3291             : /// If CoprocOp is 'p', then :
    3292             : ///   <prefix> ::= p
    3293             : /// <number> ::= integer in range [0, 15]
    3294        1913 : static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
    3295             :   // Use the same layout as the tablegen'erated register name matcher. Ugly,
    3296             :   // but efficient.
    3297        3826 :   if (Name.size() < 2 || Name[0] != CoprocOp)
    3298             :     return -1;
    3299        5739 :   Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
    3300             : 
    3301        1913 :   switch (Name.size()) {
    3302             :   default: return -1;
    3303        1679 :   case 1:
    3304        3358 :     switch (Name[0]) {
    3305             :     default:  return -1;
    3306        1002 :     case '0': return 0;
    3307         211 :     case '1': return 1;
    3308          78 :     case '2': return 2;
    3309          41 :     case '3': return 3;
    3310          49 :     case '4': return 4;
    3311          47 :     case '5': return 5;
    3312          54 :     case '6': return 6;
    3313         130 :     case '7': return 7;
    3314          42 :     case '8': return 8;
    3315          25 :     case '9': return 9;
    3316             :     }
    3317         234 :   case 2:
    3318         468 :     if (Name[0] != '1')
    3319             :       return -1;
    3320         468 :     switch (Name[1]) {
    3321             :     default:  return -1;
    3322             :     // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
    3323             :     // However, old cores (v5/v6) did use them in that way.
    3324          29 :     case '0': return 10;
    3325          18 :     case '1': return 11;
    3326          35 :     case '2': return 12;
    3327          24 :     case '3': return 13;
    3328          71 :     case '4': return 14;
    3329          57 :     case '5': return 15;
    3330             :     }
    3331             :   }
    3332             : }
    3333             : 
    3334             : /// parseITCondCode - Try to parse a condition code for an IT instruction.
    3335             : OperandMatchResultTy
    3336        2765 : ARMAsmParser::parseITCondCode(OperandVector &Operands) {
    3337        2765 :   MCAsmParser &Parser = getParser();
    3338        2765 :   SMLoc S = Parser.getTok().getLoc();
    3339        2765 :   const AsmToken &Tok = Parser.getTok();
    3340        2765 :   if (!Tok.is(AsmToken::Identifier))
    3341             :     return MatchOperand_NoMatch;
    3342        2765 :   unsigned CC = ARMCondCodeFromString(Tok.getString());
    3343        2765 :   if (CC == ~0U)
    3344             :     return MatchOperand_NoMatch;
    3345        2765 :   Parser.Lex(); // Eat the token.
    3346             : 
    3347       11060 :   Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
    3348             : 
    3349        2765 :   return MatchOperand_Success;
    3350             : }
    3351             : 
    3352             : /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
    3353             : /// token must be an Identifier when called, and if it is a coprocessor
    3354             : /// number, the token is eaten and the operand is added to the operand list.
    3355             : OperandMatchResultTy
    3356         892 : ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
    3357         892 :   MCAsmParser &Parser = getParser();
    3358         892 :   SMLoc S = Parser.getTok().getLoc();
    3359         892 :   const AsmToken &Tok = Parser.getTok();
    3360         892 :   if (Tok.isNot(AsmToken::Identifier))
    3361             :     return MatchOperand_NoMatch;
    3362             : 
    3363         892 :   int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
    3364         892 :   if (Num == -1)
    3365             :     return MatchOperand_NoMatch;
    3366             :   // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
    3367         903 :   if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
    3368             :     return MatchOperand_NoMatch;
    3369             : 
    3370         886 :   Parser.Lex(); // Eat identifier token.
    3371        3544 :   Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
    3372         886 :   return MatchOperand_Success;
    3373             : }
    3374             : 
    3375             : /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
    3376             : /// token must be an Identifier when called, and if it is a coprocessor
    3377             : /// number, the token is eaten and the operand is added to the operand list.
    3378             : OperandMatchResultTy
    3379        1021 : ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
    3380        1021 :   MCAsmParser &Parser = getParser();
    3381        1021 :   SMLoc S = Parser.getTok().getLoc();
    3382        1021 :   const AsmToken &Tok = Parser.getTok();
    3383        1021 :   if (Tok.isNot(AsmToken::Identifier))
    3384             :     return MatchOperand_NoMatch;
    3385             : 
    3386        1021 :   int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
    3387        1021 :   if (Reg == -1)
    3388             :     return MatchOperand_NoMatch;
    3389             : 
    3390        1021 :   Parser.Lex(); // Eat identifier token.
    3391        4084 :   Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
    3392        1021 :   return MatchOperand_Success;
    3393             : }
    3394             : 
    3395             : /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
    3396             : /// coproc_option : '{' imm0_255 '}'
    3397             : OperandMatchResultTy
    3398         288 : ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
    3399         288 :   MCAsmParser &Parser = getParser();
    3400         288 :   SMLoc S = Parser.getTok().getLoc();
    3401             : 
    3402             :   // If this isn't a '{', this isn't a coprocessor immediate operand.
    3403         288 :   if (Parser.getTok().isNot(AsmToken::LCurly))
    3404             :     return MatchOperand_NoMatch;
    3405          80 :   Parser.Lex(); // Eat the '{'
    3406             : 
    3407             :   const MCExpr *Expr;
    3408          80 :   SMLoc Loc = Parser.getTok().getLoc();
    3409          80 :   if (getParser().parseExpression(Expr)) {
    3410           0 :     Error(Loc, "illegal expression");
    3411           0 :     return MatchOperand_ParseFail;
    3412             :   }
    3413         160 :   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
    3414          80 :   if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
    3415           6 :     Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
    3416           2 :     return MatchOperand_ParseFail;
    3417             :   }
    3418          78 :   int Val = CE->getValue();
    3419             : 
    3420             :   // Check for and consume the closing '}'
    3421          78 :   if (Parser.getTok().isNot(AsmToken::RCurly))
    3422             :     return MatchOperand_ParseFail;
    3423          78 :   SMLoc E = Parser.getTok().getEndLoc();
    3424          78 :   Parser.Lex(); // Eat the '}'
    3425             : 
    3426         312 :   Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
    3427          78 :   return MatchOperand_Success;
    3428             : }
    3429             : 
    3430             : // For register list parsing, we need to map from raw GPR register numbering
    3431             : // to the enumeration values. The enumeration values aren't sorted by
    3432             : // register number due to our using "sp", "lr" and "pc" as canonical names.
    3433         357 : static unsigned getNextRegister(unsigned Reg) {
    3434             :   // If this is a GPR, we need to do it manually, otherwise we can rely
    3435             :   // on the sort ordering of the enumeration since the other reg-classes
    3436             :   // are sane.
    3437         708 :   if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
    3438         146 :     return Reg + 1;
    3439         211 :   switch(Reg) {
    3440           0 :   default: llvm_unreachable("Invalid GPR number!");
    3441           9 :   case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
    3442          17 :   case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
    3443          51 :   case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
    3444           5 :   case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
    3445           5 :   case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
    3446           5 :   case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
    3447           0 :   case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
    3448           0 :   case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
    3449             :   }
    3450             : }
    3451             : 
    3452             : /// Parse a register list.
    3453         772 : bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
    3454         772 :   MCAsmParser &Parser = getParser();
    3455         772 :   if (Parser.getTok().isNot(AsmToken::LCurly))
    3456           0 :     return TokError("Token is not a Left Curly Brace");
    3457         772 :   SMLoc S = Parser.getTok().getLoc();
    3458         772 :   Parser.Lex(); // Eat '{' token.
    3459         772 :   SMLoc RegLoc = Parser.getTok().getLoc();
    3460             : 
    3461             :   // Check the first register in the list to see what register class
    3462             :   // this is a list of.
    3463         772 :   int Reg = tryParseRegister();
    3464         772 :   if (Reg == -1)
    3465           6 :     return Error(RegLoc, "register expected");
    3466             : 
    3467             :   // The reglist instructions have at most 16 registers, so reserve
    3468             :   // space for that many.
    3469         770 :   int EReg = 0;
    3470         770 :   SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
    3471             : 
    3472             :   // Allow Q regs and just interpret them as the two D sub-registers.
    3473        1404 :   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
    3474           2 :     Reg = getDRegFromQReg(Reg);
    3475           2 :     EReg = MRI->getEncodingValue(Reg);
    3476           1 :     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
    3477           1 :     ++Reg;
    3478             :   }
    3479             :   const MCRegisterClass *RC;
    3480        1530 :   if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
    3481             :     RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
    3482         226 :   else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
    3483             :     RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
    3484          72 :   else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
    3485             :     RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
    3486             :   else
    3487           0 :     return Error(RegLoc, "invalid register in register list");
    3488             : 
    3489             :   // Store the register.
    3490        1540 :   EReg = MRI->getEncodingValue(Reg);
    3491         770 :   Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
    3492             : 
    3493             :   // This starts immediately after the first register token in the list,
    3494             :   // so we can see either a comma or a minus (range separator) as a legal
    3495             :   // next token.
    3496        2866 :   while (Parser.getTok().is(AsmToken::Comma) ||
    3497         851 :          Parser.getTok().is(AsmToken::Minus)) {
    3498        1247 :     if (Parser.getTok().is(AsmToken::Minus)) {
    3499          83 :       Parser.Lex(); // Eat the minus.
    3500          83 :       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
    3501          83 :       int EndReg = tryParseRegister();
    3502          83 :       if (EndReg == -1)
    3503           0 :         return Error(AfterMinusLoc, "register expected");
    3504             :       // Allow Q regs and just interpret them as the two D sub-registers.
    3505         113 :       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
    3506           2 :         EndReg = getDRegFromQReg(EndReg) + 1;
    3507             :       // If the register is the same as the start reg, there's nothing
    3508             :       // more to do.
    3509          83 :       if (Reg == EndReg)
    3510          83 :         continue;
    3511             :       // The register must be in the same register class as the first.
    3512         166 :       if (!RC->contains(EndReg))
    3513           0 :         return Error(AfterMinusLoc, "invalid register in register list");
    3514             :       // Ranges must go from low to high.
    3515         249 :       if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
    3516           0 :         return Error(AfterMinusLoc, "bad range in register list");
    3517             : 
    3518             :       // Add all the registers in the range to the register list.
    3519         797 :       while (Reg != EndReg) {
    3520         357 :         Reg = getNextRegister(Reg);
    3521         714 :         EReg = MRI->getEncodingValue(Reg);
    3522         357 :         Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
    3523             :       }
    3524          83 :       continue;
    3525             :     }
    3526        1164 :     Parser.Lex(); // Eat the comma.
    3527        1164 :     RegLoc = Parser.getTok().getLoc();
    3528        1164 :     int OldReg = Reg;
    3529        3490 :     const AsmToken RegTok = Parser.getTok();
    3530        1164 :     Reg = tryParseRegister();
    3531        1164 :     if (Reg == -1)
    3532           0 :       return Error(RegLoc, "register expected");
    3533             :     // Allow Q regs and just interpret them as the two D sub-registers.
    3534        1164 :     bool isQReg = false;
    3535        1953 :     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
    3536           0 :       Reg = getDRegFromQReg(Reg);
    3537           0 :       isQReg = true;
    3538             :     }
    3539             :     // The register must be in the same register class as the first.
    3540        2328 :     if (!RC->contains(Reg))
    3541           0 :       return Error(RegLoc, "invalid register in register list");
    3542             :     // List must be monotonically increasing.
    3543        3492 :     if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
    3544           6 :       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
    3545           9 :         Warning(RegLoc, "register list not in ascending order");
    3546             :       else
    3547           0 :         return Error(RegLoc, "register list not in ascending order");
    3548             :     }
    3549        3492 :     if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
    3550           0 :       Warning(RegLoc, "duplicated register (" + RegTok.getString() +
    3551           0 :               ") in register list");
    3552             :       continue;
    3553             :     }
    3554             :     // VFP register lists must also be contiguous.
    3555        1388 :     if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
    3556         224 :         Reg != OldReg + 1)
    3557           6 :       return Error(RegLoc, "non-contiguous register range");
    3558        1162 :     EReg = MRI->getEncodingValue(Reg);
    3559        1162 :     Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
    3560        1162 :     if (isQReg) {
    3561           0 :       EReg = MRI->getEncodingValue(++Reg);
    3562           0 :       Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
    3563             :     }
    3564             :   }
    3565             : 
    3566         768 :   if (Parser.getTok().isNot(AsmToken::RCurly))
    3567           0 :     return Error(Parser.getTok().getLoc(), "'}' expected");
    3568         768 :   SMLoc E = Parser.getTok().getEndLoc();
    3569         768 :   Parser.Lex(); // Eat '}' token.
    3570             : 
    3571             :   // Push the register list operand.
    3572        2304 :   Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
    3573             : 
    3574             :   // The ARM system instruction variants for LDM/STM have a '^' token here.
    3575         768 :   if (Parser.getTok().is(AsmToken::Caret)) {
    3576          32 :     Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
    3577           8 :     Parser.Lex(); // Eat '^' token.
    3578             :   }
    3579             : 
    3580             :   return false;
    3581             : }
    3582             : 
    3583             : // Helper function to parse the lane index for vector lists.
    3584        7854 : OperandMatchResultTy ARMAsmParser::
    3585             : parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
    3586        7854 :   MCAsmParser &Parser = getParser();
    3587        7854 :   Index = 0; // Always return a defined index value.
    3588        7854 :   if (Parser.getTok().is(AsmToken::LBrac)) {
    3589        3434 :     Parser.Lex(); // Eat the '['.
    3590        3434 :     if (Parser.getTok().is(AsmToken::RBrac)) {
    3591             :       // "Dn[]" is the 'all lanes' syntax.
    3592        1281 :       LaneKind = AllLanes;
    3593        1281 :       EndLoc = Parser.getTok().getEndLoc();
    3594        1281 :       Parser.Lex(); // Eat the ']'.
    3595        1281 :       return MatchOperand_Success;
    3596             :     }
    3597             : 
    3598             :     // There's an optional '#' token here. Normally there wouldn't be, but
    3599             :     // inline assemble puts one in, and it's friendly to accept that.
    3600        2153 :     if (Parser.getTok().is(AsmToken::Hash))
    3601           0 :       Parser.Lex(); // Eat '#' or '$'.
    3602             : 
    3603             :     const MCExpr *LaneIndex;
    3604        2153 :     SMLoc Loc = Parser.getTok().getLoc();
    3605        2153 :     if (getParser().parseExpression(LaneIndex)) {
    3606           0 :       Error(Loc, "illegal expression");
    3607           0 :       return MatchOperand_ParseFail;
    3608             :     }
    3609        4306 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
    3610             :     if (!CE) {
    3611           0 :       Error(Loc, "lane index must be empty or an integer");
    3612           0 :       return MatchOperand_ParseFail;
    3613             :     }
    3614        2153 :     if (Parser.getTok().isNot(AsmToken::RBrac)) {
    3615           0 :       Error(Parser.getTok().getLoc(), "']' expected");
    3616           0 :       return MatchOperand_ParseFail;
    3617             :     }
    3618        2153 :     EndLoc = Parser.getTok().getEndLoc();
    3619        2153 :     Parser.Lex(); // Eat the ']'.
    3620        2153 :     int64_t Val = CE->getValue();
    3621             : 
    3622             :     // FIXME: Make this range check context sensitive for .8, .16, .32.
    3623        2153 :     if (Val < 0 || Val > 7) {
    3624           0 :       Error(Parser.getTok().getLoc(), "lane index out of range");
    3625           0 :       return MatchOperand_ParseFail;
    3626             :     }
    3627        2153 :     Index = Val;
    3628        2153 :     LaneKind = IndexedLane;
    3629        2153 :     return MatchOperand_Success;
    3630             :   }
    3631        4420 :   LaneKind = NoLanes;
    3632        4420 :   return MatchOperand_Success;
    3633             : }
    3634             : 
    3635             : // parse a vector register list
    3636             : OperandMatchResultTy
    3637        2815 : ARMAsmParser::parseVectorList(OperandVector &Operands) {
    3638        2815 :   MCAsmParser &Parser = getParser();
    3639             :   VectorLaneTy LaneKind;
    3640             :   unsigned LaneIndex;
    3641        2815 :   SMLoc S = Parser.getTok().getLoc();
    3642             :   // As an extension (to match gas), support a plain D register or Q register
    3643             :   // (without encosing curly braces) as a single or double entry list,
    3644             :   // respectively.
    3645        2815 :   if (Parser.getTok().is(AsmToken::Identifier)) {
    3646           4 :     SMLoc E = Parser.getTok().getEndLoc();
    3647           4 :     int Reg = tryParseRegister();
    3648           4 :     if (Reg == -1)
    3649             :       return MatchOperand_NoMatch;
    3650           8 :     if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
    3651           4 :       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
    3652           4 :       if (Res != MatchOperand_Success)
    3653             :         return Res;
    3654           4 :       switch (LaneKind) {
    3655           0 :       case NoLanes:
    3656           0 :         Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
    3657           0 :         break;
    3658           0 :       case AllLanes:
    3659           0 :         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
    3660             :                                                                 S, E));
    3661           0 :         break;
    3662           4 :       case IndexedLane:
    3663          12 :         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
    3664             :                                                                LaneIndex,
    3665             :                                                                false, S, E));
    3666           4 :         break;
    3667             :       }
    3668             :       return MatchOperand_Success;
    3669             :     }
    3670           0 :     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
    3671           0 :       Reg = getDRegFromQReg(Reg);
    3672           0 :       OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
    3673           0 :       if (Res != MatchOperand_Success)
    3674             :         return Res;
    3675           0 :       switch (LaneKind) {
    3676           0 :       case NoLanes:
    3677           0 :         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
    3678             :                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
    3679           0 :         Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
    3680           0 :         break;
    3681           0 :       case AllLanes:
    3682           0 :         Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
    3683             :                                    &ARMMCRegisterClasses[ARM::DPairRegClassID]);
    3684           0 :         Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
    3685             :                                                                 S, E));
    3686           0 :         break;
    3687           0 :       case IndexedLane:
    3688           0 :         Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
    3689             :                                                                LaneIndex,
    3690             :                                                                false, S, E));
    3691           0 :         break;
    3692             :       }
    3693             :       return MatchOperand_Success;
    3694             :     }
    3695           0 :     Error(S, "vector register expected");
    3696           0 :     return MatchOperand_ParseFail;
    3697             :   }
    3698             : 
    3699        2811 :   if (Parser.getTok().isNot(AsmToken::LCurly))
    3700             :     return MatchOperand_NoMatch;
    3701             : 
    3702        2811 :   Parser.Lex(); // Eat '{' token.
    3703        2811 :   SMLoc RegLoc = Parser.getTok().getLoc();
    3704             : 
    3705        2811 :   int Reg = tryParseRegister();
    3706        2811 :   if (Reg == -1) {
    3707           0 :     Error(RegLoc, "register expected");
    3708           0 :     return MatchOperand_ParseFail;
    3709             :   }
    3710        2811 :   unsigned Count = 1;
    3711        2811 :   int Spacing = 0;
    3712        2811 :   unsigned FirstReg = Reg;
    3713             :   // The list is of D registers, but we also allow Q regs and just interpret
    3714             :   // them as the two D sub-registers.
    3715        5622 :   if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
    3716          34 :     FirstReg = Reg = getDRegFromQReg(Reg);
    3717          17 :     Spacing = 1; // double-spacing requires explicit D registers, otherwise
    3718             :                  // it's ambiguous with four-register single spaced.
    3719          17 :     ++Reg;
    3720          17 :     ++Count;
    3721             :   }
    3722             : 
    3723        2811 :   SMLoc E;
    3724        2811 :   if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
    3725             :     return MatchOperand_ParseFail;
    3726             : 
    3727       10665 :   while (Parser.getTok().is(AsmToken::Comma) ||
    3728        2815 :          Parser.getTok().is(AsmToken::Minus)) {
    3729        5039 :     if (Parser.getTok().is(AsmToken::Minus)) {
    3730           4 :       if (!Spacing)
    3731             :         Spacing = 1; // Register range implies a single spaced list.
    3732           0 :       else if (Spacing == 2) {
    3733           0 :         Error(Parser.getTok().getLoc(),
    3734             :               "sequential registers in double spaced list");
    3735           0 :         return MatchOperand_ParseFail;
    3736             :       }
    3737           4 :       Parser.Lex(); // Eat the minus.
    3738           4 :       SMLoc AfterMinusLoc = Parser.getTok().getLoc();
    3739           4 :       int EndReg = tryParseRegister();
    3740           4 :       if (EndReg == -1) {
    3741           0 :         Error(AfterMinusLoc, "register expected");
    3742           0 :         return MatchOperand_ParseFail;
    3743             :       }
    3744             :       // Allow Q regs and just interpret them as the two D sub-registers.
    3745           8 :       if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
    3746           0 :         EndReg = getDRegFromQReg(EndReg) + 1;
    3747             :       // If the register is the same as the start reg, there's nothing
    3748             :       // more to do.
    3749           4 :       if (Reg == EndReg)
    3750           4 :         continue;
    3751             :       // The register must be in the same register class as the first.
    3752           8 :       if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
    3753           0 :         Error(AfterMinusLoc, "invalid register in register list");
    3754           0 :         return MatchOperand_ParseFail;
    3755             :       }
    3756             :       // Ranges must go from low to high.
    3757           4 :       if (Reg > EndReg) {
    3758           0 :         Error(AfterMinusLoc, "bad range in register list");
    3759           0 :         return MatchOperand_ParseFail;
    3760             :       }
    3761             :       // Parse the lane specifier if present.
    3762             :       VectorLaneTy NextLaneKind;
    3763             :       unsigned NextLaneIndex;
    3764           4 :       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
    3765             :           MatchOperand_Success)
    3766             :         return MatchOperand_ParseFail;
    3767           4 :       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
    3768           0 :         Error(AfterMinusLoc, "mismatched lane index in register list");
    3769           0 :         return MatchOperand_ParseFail;
    3770             :       }
    3771             : 
    3772             :       // Add all the registers in the range to the register list.
    3773           4 :       Count += EndReg - Reg;
    3774           4 :       Reg = EndReg;
    3775           4 :       continue;
    3776             :     }
    3777        5035 :     Parser.Lex(); // Eat the comma.
    3778        5035 :     RegLoc = Parser.getTok().getLoc();
    3779        5035 :     int OldReg = Reg;
    3780        5035 :     Reg = tryParseRegister();
    3781        5035 :     if (Reg == -1) {
    3782           0 :       Error(RegLoc, "register expected");
    3783           0 :       return MatchOperand_ParseFail;
    3784             :     }
    3785             :     // vector register lists must be contiguous.
    3786             :     // It's OK to use the enumeration values directly here rather, as the
    3787             :     // VFP register classes have the enum sorted properly.
    3788             :     //
    3789             :     // The list is of D registers, but we also allow Q regs and just interpret
    3790             :     // them as the two D sub-registers.
    3791       10070 :     if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
    3792           5 :       if (!Spacing)
    3793             :         Spacing = 1; // Register range implies a single spaced list.
    3794           5 :       else if (Spacing == 2) {
    3795           0 :         Error(RegLoc,
    3796             :               "invalid register in double-spaced list (must be 'D' register')");
    3797           0 :         return MatchOperand_ParseFail;
    3798             :       }
    3799          10 :       Reg = getDRegFromQReg(Reg);
    3800           5 :       if (Reg != OldReg + 1) {
    3801           0 :         Error(RegLoc, "non-contiguous register range");
    3802           0 :         return MatchOperand_ParseFail;
    3803             :       }
    3804           5 :       ++Reg;
    3805           5 :       Count += 2;
    3806             :       // Parse the lane specifier if present.
    3807             :       VectorLaneTy NextLaneKind;
    3808             :       unsigned NextLaneIndex;
    3809           5 :       SMLoc LaneLoc = Parser.getTok().getLoc();
    3810           5 :       if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
    3811             :           MatchOperand_Success)
    3812             :         return MatchOperand_ParseFail;
    3813           5 :       if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
    3814           0 :         Error(LaneLoc, "mismatched lane index in register list");
    3815           0 :         return MatchOperand_ParseFail;
    3816             :       }
    3817           5 :       continue;
    3818             :     }
    3819             :     // Normal D register.
    3820             :     // Figure out the register spacing (single or double) of the list if
    3821             :     // we don't know it already.
    3822        5030 :     if (!Spacing)
    3823        2420 :       Spacing = 1 + (Reg == OldReg + 2);
    3824             : 
    3825             :     // Just check that it's contiguous and keep going.
    3826        5030 :     if (Reg != OldReg + Spacing) {
    3827           0 :       Error(RegLoc, "non-contiguous register range");
    3828           0 :       return MatchOperand_ParseFail;
    3829             :     }
    3830        5030 :     ++Count;
    3831             :     // Parse the lane specifier if present.
    3832             :     VectorLaneTy NextLaneKind;
    3833             :     unsigned NextLaneIndex;
    3834        5030 :     SMLoc EndLoc = Parser.getTok().getLoc();
    3835        5030 :     if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
    3836             :       return MatchOperand_ParseFail;
    3837        5030 :     if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
    3838           0 :       Error(EndLoc, "mismatched lane index in register list");
    3839           0 :       return MatchOperand_ParseFail;
    3840             :     }
    3841             :   }
    3842             : 
    3843        2811 :   if (Parser.getTok().isNot(AsmToken::RCurly)) {
    3844           0 :     Error(Parser.getTok().getLoc(), "'}' expected");
    3845           0 :     return MatchOperand_ParseFail;
    3846             :   }
    3847        2811 :   E = Parser.getTok().getEndLoc();
    3848        2811 :   Parser.Lex(); // Eat '}' token.
    3849             : 
    3850        2811 :   switch (LaneKind) {
    3851        1549 :   case NoLanes:
    3852             :     // Two-register operands have been converted to the
    3853             :     // composite register classes.
    3854        1549 :     if (Count == 2) {
    3855         388 :       const MCRegisterClass *RC = (Spacing == 1) ?
    3856             :         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
    3857             :         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
    3858         388 :       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
    3859             :     }
    3860             : 
    3861        4647 :     Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
    3862             :                                                     (Spacing == 2), S, E));
    3863        1549 :     break;
    3864         480 :   case AllLanes:
    3865             :     // Two-register operands have been converted to the
    3866             :     // composite register classes.
    3867         480 :     if (Count == 2) {
    3868         171 :       const MCRegisterClass *RC = (Spacing == 1) ?
    3869             :         &ARMMCRegisterClasses[ARM::DPairRegClassID] :
    3870             :         &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
    3871         171 :       FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
    3872             :     }
    3873        1440 :     Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
    3874             :                                                             (Spacing == 2),
    3875             :                                                             S, E));
    3876         480 :     break;
    3877         782 :   case IndexedLane:
    3878        2346 :     Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
    3879             :                                                            LaneIndex,
    3880             :                                                            (Spacing == 2),
    3881             :                                                            S, E));
    3882         782 :     break;
    3883             :   }
    3884             :   return MatchOperand_Success;
    3885             : }
    3886             : 
    3887             : /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
    3888             : OperandMatchResultTy
    3889         278 : ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
    3890         278 :   MCAsmParser &Parser = getParser();
    3891         278 :   SMLoc S = Parser.getTok().getLoc();
    3892         278 :   const AsmToken &Tok = Parser.getTok();
    3893             :   unsigned Opt;
    3894             : 
    3895         278 :   if (Tok.is(AsmToken::Identifier)) {
    3896         140 :     StringRef OptStr = Tok.getString();
    3897             : 
    3898         840 :     Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
    3899         420 :       .Case("sy",    ARM_MB::SY)
    3900         420 :       .Case("st",    ARM_MB::ST)
    3901         420 :       .Case("ld",    ARM_MB::LD)
    3902         420 :       .Case("sh",    ARM_MB::ISH)
    3903         420 :       .Case("ish",   ARM_MB::ISH)
    3904         420 :       .Case("shst",  ARM_MB::ISHST)
    3905         420 :       .Case("ishst", ARM_MB::ISHST)
    3906         420 :       .Case("ishld", ARM_MB::ISHLD)
    3907         420 :       .Case("nsh",   ARM_MB::NSH)
    3908         420 :       .Case("un",    ARM_MB::NSH)
    3909         420 :       .Case("nshst", ARM_MB::NSHST)
    3910         420 :       .Case("nshld", ARM_MB::NSHLD)
    3911         420 :       .Case("unst",  ARM_MB::NSHST)
    3912         420 :       .Case("osh",   ARM_MB::OSH)
    3913         420 :       .Case("oshst", ARM_MB::OSHST)
    3914         420 :       .Case("oshld", ARM_MB::OSHLD)
    3915         140 :       .Default(~0U);
    3916             : 
    3917             :     // ishld, oshld, nshld and ld are only available from ARMv8.
    3918         140 :     if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
    3919         116 :                         Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
    3920             :       Opt = ~0U;
    3921             : 
    3922         124 :     if (Opt == ~0U)
    3923          20 :       return MatchOperand_NoMatch;
    3924             : 
    3925         120 :     Parser.Lex(); // Eat identifier token.
    3926         142 :   } else if (Tok.is(AsmToken::Hash) ||
    3927         142 :              Tok.is(AsmToken::Dollar) ||
    3928           4 :              Tok.is(AsmToken::Integer)) {
    3929         138 :     if (Parser.getTok().isNot(AsmToken::Integer))
    3930         134 :       Parser.Lex(); // Eat '#' or '$'.
    3931         138 :     SMLoc Loc = Parser.getTok().getLoc();
    3932             : 
    3933             :     const MCExpr *MemBarrierID;
    3934         138 :     if (getParser().parseExpression(MemBarrierID)) {
    3935           0 :       Error(Loc, "illegal expression");
    3936           4 :       return MatchOperand_ParseFail;
    3937             :     }
    3938             : 
    3939         276 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
    3940             :     if (!CE) {
    3941           0 :       Error(Loc, "constant expression expected");
    3942           0 :       return MatchOperand_ParseFail;
    3943             :     }
    3944             : 
    3945         138 :     int Val = CE->getValue();
    3946         138 :     if (Val & ~0xf) {
    3947          12 :       Error(Loc, "immediate value out of range");
    3948           4 :       return MatchOperand_ParseFail;
    3949             :     }
    3950             : 
    3951         134 :     Opt = ARM_MB::RESERVED_0 + Val;
    3952             :   } else
    3953             :     return MatchOperand_ParseFail;
    3954             : 
    3955        1016 :   Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
    3956         254 :   return MatchOperand_Success;
    3957             : }
    3958             : 
    3959             : /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
    3960             : OperandMatchResultTy
    3961          30 : ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
    3962          30 :   MCAsmParser &Parser = getParser();
    3963          30 :   SMLoc S = Parser.getTok().getLoc();
    3964          30 :   const AsmToken &Tok = Parser.getTok();
    3965             :   unsigned Opt;
    3966             : 
    3967          30 :   if (Tok.is(AsmToken::Identifier)) {
    3968          11 :     StringRef OptStr = Tok.getString();
    3969             : 
    3970          20 :     if (OptStr.equals_lower("sy"))
    3971           9 :       Opt = ARM_ISB::SY;
    3972             :     else
    3973           2 :       return MatchOperand_NoMatch;
    3974             : 
    3975           9 :     Parser.Lex(); // Eat identifier token.
    3976          19 :   } else if (Tok.is(AsmToken::Hash) ||
    3977          19 :              Tok.is(AsmToken::Dollar) ||
    3978           0 :              Tok.is(AsmToken::Integer)) {
    3979          19 :     if (Parser.getTok().isNot(AsmToken::Integer))
    3980          19 :       Parser.Lex(); // Eat '#' or '$'.
    3981          19 :     SMLoc Loc = Parser.getTok().getLoc();
    3982             : 
    3983             :     const MCExpr *ISBarrierID;
    3984          19 :     if (getParser().parseExpression(ISBarrierID)) {
    3985           0 :       Error(Loc, "illegal expression");
    3986          10 :       return MatchOperand_ParseFail;
    3987             :     }
    3988             : 
    3989          38 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
    3990             :     if (!CE) {
    3991           0 :       Error(Loc, "constant expression expected");
    3992           0 :       return MatchOperand_ParseFail;
    3993             :     }
    3994             : 
    3995          19 :     int Val = CE->getValue();
    3996          19 :     if (Val & ~0xf) {
    3997          30 :       Error(Loc, "immediate value out of range");
    3998          10 :       return MatchOperand_ParseFail;
    3999             :     }
    4000             : 
    4001           9 :     Opt = ARM_ISB::RESERVED_0 + Val;
    4002             :   } else
    4003             :     return MatchOperand_ParseFail;
    4004             : 
    4005          72 :   Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
    4006             :           (ARM_ISB::InstSyncBOpt)Opt, S));
    4007          18 :   return MatchOperand_Success;
    4008             : }
    4009             : 
    4010             : 
    4011             : /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
    4012             : OperandMatchResultTy
    4013          65 : ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
    4014          65 :   MCAsmParser &Parser = getParser();
    4015          65 :   SMLoc S = Parser.getTok().getLoc();
    4016          65 :   const AsmToken &Tok = Parser.getTok();
    4017          65 :   if (!Tok.is(AsmToken::Identifier)) 
    4018             :     return MatchOperand_NoMatch;
    4019          40 :   StringRef IFlagsStr = Tok.getString();
    4020             : 
    4021             :   // An iflags string of "none" is interpreted to mean that none of the AIF
    4022             :   // bits are set.  Not a terribly useful instruction, but a valid encoding.
    4023          40 :   unsigned IFlags = 0;
    4024          40 :   if (IFlagsStr != "none") {
    4025          82 :         for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
    4026          90 :       unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
    4027         135 :         .Case("a", ARM_PROC::A)
    4028         135 :         .Case("i", ARM_PROC::I)
    4029         135 :         .Case("f", ARM_PROC::F)
    4030          90 :         .Default(~0U);
    4031             : 
    4032             :       // If some specific iflag is already set, it means that some letter is
    4033             :       // present more than once, this is not acceptable.
    4034          45 :       if (Flag == ~0U || (IFlags & Flag))
    4035             :         return MatchOperand_NoMatch;
    4036             : 
    4037          45 :       IFlags |= Flag;
    4038             :     }
    4039             :   }
    4040             : 
    4041          40 :   Parser.Lex(); // Eat identifier token.
    4042         160 :   Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
    4043          40 :   return MatchOperand_Success;
    4044             : }
    4045             : 
    4046             : /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
    4047             : OperandMatchResultTy
    4048         243 : ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
    4049         243 :   MCAsmParser &Parser = getParser();
    4050         243 :   SMLoc S = Parser.getTok().getLoc();
    4051         243 :   const AsmToken &Tok = Parser.getTok();
    4052         243 :   if (!Tok.is(AsmToken::Identifier))
    4053             :     return MatchOperand_NoMatch;
    4054         239 :   StringRef Mask = Tok.getString();
    4055             : 
    4056         239 :   if (isMClass()) {
    4057         345 :     auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
    4058         230 :     if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
    4059             :       return MatchOperand_NoMatch;
    4060             : 
    4061         105 :     unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
    4062             : 
    4063         105 :     Parser.Lex(); // Eat identifier token.
    4064         420 :     Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
    4065         105 :     return MatchOperand_Success;
    4066             :   }
    4067             : 
    4068             :   // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
    4069         248 :   size_t Start = 0, Next = Mask.find('_');
    4070         124 :   StringRef Flags = "";
    4071         124 :   std::string SpecReg = Mask.slice(Start, Next).lower();
    4072         124 :   if (Next != StringRef::npos)
    4073         216 :     Flags = Mask.slice(Next+1, Mask.size());
    4074             : 
    4075             :   // FlagsVal contains the complete mask:
    4076             :   // 3-0: Mask
    4077             :   // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
    4078         124 :   unsigned FlagsVal = 0;
    4079             : 
    4080         124 :   if (SpecReg == "apsr") {
    4081          94 :     FlagsVal = StringSwitch<unsigned>(Flags)
    4082         141 :     .Case("nzcvq",  0x8) // same as CPSR_f
    4083         141 :     .Case("g",      0x4) // same as CPSR_s
    4084         141 :     .Case("nzcvqg", 0xc) // same as CPSR_fs
    4085          47 :     .Default(~0U);
    4086             : 
    4087          34 :     if (FlagsVal == ~0U) {
    4088          13 :       if (!Flags.empty())
    4089             :         return MatchOperand_NoMatch;
    4090             :       else
    4091             :         FlagsVal = 8; // No flag
    4092             :     }
    4093         104 :   } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
    4094             :     // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
    4095         134 :     if (Flags == "all" || Flags == "")
    4096           8 :       Flags = "fc";
    4097         305 :     for (int i = 0, e = Flags.size(); i != e; ++i) {
    4098         342 :       unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
    4099         513 :       .Case("c", 1)
    4100         513 :       .Case("x", 2)
    4101         513 :       .Case("s", 4)
    4102         513 :       .Case("f", 8)
    4103         342 :       .Default(~0U);
    4104             : 
    4105             :       // If some specific flag is already set, it means that some letter is
    4106             :       // present more than once, this is not acceptable.
    4107         168 :       if (Flag == ~0U || (FlagsVal & Flag))
    4108             :         return MatchOperand_NoMatch;
    4109         165 :       FlagsVal |= Flag;
    4110             :     }
    4111             :   } else // No match for special register.
    4112             :     return MatchOperand_NoMatch;
    4113             : 
    4114             :   // Special register without flags is NOT equivalent to "fc" flags.
    4115             :   // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
    4116             :   // two lines would enable gas compatibility at the expense of breaking
    4117             :   // round-tripping.
    4118             :   //
    4119             :   // if (!FlagsVal)
    4120             :   //  FlagsVal = 0x9;
    4121             : 
    4122             :   // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
    4123         108 :   if (SpecReg == "spsr")
    4124          20 :     FlagsVal |= 16;
    4125             : 
    4126         108 :   Parser.Lex(); // Eat identifier token.
    4127         432 :   Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
    4128         108 :   return MatchOperand_Success;
    4129             : }
    4130             : 
    4131             : /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
    4132             : /// use in the MRS/MSR instructions added to support virtualization.
    4133             : OperandMatchResultTy
    4134         136 : ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
    4135         136 :   MCAsmParser &Parser = getParser();
    4136         136 :   SMLoc S = Parser.getTok().getLoc();
    4137         136 :   const AsmToken &Tok = Parser.getTok();
    4138         136 :   if (!Tok.is(AsmToken::Identifier))
    4139             :     return MatchOperand_NoMatch;
    4140         135 :   StringRef RegName = Tok.getString();
    4141             : 
    4142         405 :   auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
    4143         135 :   if (!TheReg)
    4144             :     return MatchOperand_NoMatch;
    4145         132 :   unsigned Encoding = TheReg->Encoding;
    4146             : 
    4147         132 :   Parser.Lex(); // Eat identifier token.
    4148         528 :   Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
    4149         132 :   return MatchOperand_Success;
    4150             : }
    4151             : 
    4152             : OperandMatchResultTy
    4153          36 : ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
    4154             :                           int High) {
    4155          36 :   MCAsmParser &Parser = getParser();
    4156          36 :   const AsmToken &Tok = Parser.getTok();
    4157          36 :   if (Tok.isNot(AsmToken::Identifier)) {
    4158           0 :     Error(Parser.getTok().getLoc(), Op + " operand expected.");
    4159           0 :     return MatchOperand_ParseFail;
    4160             :   }
    4161          36 :   StringRef ShiftName = Tok.getString();
    4162          36 :   std::string LowerOp = Op.lower();
    4163          72 :   std::string UpperOp = Op.upper();
    4164          40 :   if (ShiftName != LowerOp && ShiftName != UpperOp) {
    4165          12 :     Error(Parser.getTok().getLoc(), Op + " operand expected.");
    4166           4 :     return MatchOperand_ParseFail;
    4167             :   }
    4168          32 :   Parser.Lex(); // Eat shift type token.
    4169             : 
    4170             :   // There must be a '#' and a shift amount.
    4171          32 :   if (Parser.getTok().isNot(AsmToken::Hash) &&
    4172           0 :       Parser.getTok().isNot(AsmToken::Dollar)) {
    4173           0 :     Error(Parser.getTok().getLoc(), "'#' expected");
    4174           0 :     return MatchOperand_ParseFail;
    4175             :   }
    4176          32 :   Parser.Lex(); // Eat hash token.
    4177             : 
    4178             :   const MCExpr *ShiftAmount;
    4179          32 :   SMLoc Loc = Parser.getTok().getLoc();
    4180          32 :   SMLoc EndLoc;
    4181          32 :   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
    4182           0 :     Error(Loc, "illegal expression");
    4183           0 :     return MatchOperand_ParseFail;
    4184             :   }
    4185          64 :   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
    4186             :   if (!CE) {
    4187           0 :     Error(Loc, "constant expression expected");
    4188           0 :     return MatchOperand_ParseFail;
    4189             :   }
    4190          32 :   int Val = CE->getValue();
    4191          32 :   if (Val < Low || Val > High) {
    4192          24 :     Error(Loc, "immediate value out of range");
    4193           8 :     return MatchOperand_ParseFail;
    4194             :   }
    4195             : 
    4196          96 :   Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
    4197             : 
    4198          24 :   return MatchOperand_Success;
    4199             : }
    4200             : 
    4201             : OperandMatchResultTy
    4202          26 : ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
    4203          26 :   MCAsmParser &Parser = getParser();
    4204          26 :   const AsmToken &Tok = Parser.getTok();
    4205          26 :   SMLoc S = Tok.getLoc();
    4206          26 :   if (Tok.isNot(AsmToken::Identifier)) {
    4207           6 :     Error(S, "'be' or 'le' operand expected");
    4208           2 :     return MatchOperand_ParseFail;
    4209             :   }
    4210          96 :   int Val = StringSwitch<int>(Tok.getString().lower())
    4211          72 :     .Case("be", 1)
    4212          72 :     .Case("le", 0)
    4213          48 :     .Default(-1);
    4214          24 :   Parser.Lex(); // Eat the token.
    4215             : 
    4216          24 :   if (Val == -1) {
    4217           6 :     Error(S, "'be' or 'le' operand expected");
    4218           2 :     return MatchOperand_ParseFail;
    4219             :   }
    4220         110 :   Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
    4221             :                                                                   getContext()),
    4222             :                                            S, Tok.getEndLoc()));
    4223          22 :   return MatchOperand_Success;
    4224             : }
    4225             : 
    4226             : /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
    4227             : /// instructions. Legal values are:
    4228             : ///     lsl #n  'n' in [0,31]
    4229             : ///     asr #n  'n' in [1,32]
    4230             : ///             n == 32 encoded as n == 0.
    4231             : OperandMatchResultTy
    4232          50 : ARMAsmParser::parseShifterImm(OperandVector &Operands) {
    4233          50 :   MCAsmParser &Parser = getParser();
    4234          50 :   const AsmToken &Tok = Parser.getTok();
    4235          50 :   SMLoc S = Tok.getLoc();
    4236          50 :   if (Tok.isNot(AsmToken::Identifier)) {
    4237           0 :     Error(S, "shift operator 'asr' or 'lsl' expected");
    4238           0 :     return MatchOperand_ParseFail;
    4239             :   }
    4240          50 :   StringRef ShiftName = Tok.getString();
    4241             :   bool isASR;
    4242          72 :   if (ShiftName == "lsl" || ShiftName == "LSL")
    4243             :     isASR = false;
    4244          24 :   else if (ShiftName == "asr" || ShiftName == "ASR")
    4245             :     isASR = true;
    4246             :   else {
    4247           6 :     Error(S, "shift operator 'asr' or 'lsl' expected");
    4248           2 :     return MatchOperand_ParseFail;
    4249             :   }
    4250          48 :   Parser.Lex(); // Eat the operator.
    4251             : 
    4252             :   // A '#' and a shift amount.
    4253          50 :   if (Parser.getTok().isNot(AsmToken::Hash) &&
    4254           2 :       Parser.getTok().isNot(AsmToken::Dollar)) {
    4255           6 :     Error(Parser.getTok().getLoc(), "'#' expected");
    4256           2 :     return MatchOperand_ParseFail;
    4257             :   }
    4258          46 :   Parser.Lex(); // Eat hash token.
    4259          46 :   SMLoc ExLoc = Parser.getTok().getLoc();
    4260             : 
    4261             :   const MCExpr *ShiftAmount;
    4262          46 :   SMLoc EndLoc;
    4263          46 :   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
    4264           0 :     Error(ExLoc, "malformed shift expression");
    4265           0 :     return MatchOperand_ParseFail;
    4266             :   }
    4267          90 :   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
    4268             :   if (!CE) {
    4269           6 :     Error(ExLoc, "shift amount must be an immediate");
    4270           2 :     return MatchOperand_ParseFail;
    4271             :   }
    4272             : 
    4273          44 :   int64_t Val = CE->getValue();
    4274          44 :   if (isASR) {
    4275             :     // Shift amount must be in [1,32]
    4276          20 :     if (Val < 1 || Val > 32) {
    4277          12 :       Error(ExLoc, "'asr' shift amount must be in range [1,32]");
    4278           4 :       return MatchOperand_ParseFail;
    4279             :     }
    4280             :     // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
    4281          16 :     if (isThumb() && Val == 32) {
    4282          12 :       Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
    4283           4 :       return MatchOperand_ParseFail;
    4284             :     }
    4285          16 :     if (Val == 32) Val = 0;
    4286             :   } else {
    4287             :     // Shift amount must be in [1,32]
    4288          24 :     if (Val < 0 || Val > 31) {
    4289          12 :       Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
    4290           4 :       return MatchOperand_ParseFail;
    4291             :     }
    4292             :   }
    4293             : 
    4294         128 :   Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
    4295             : 
    4296          32 :   return MatchOperand_Success;
    4297             : }
    4298             : 
    4299             : /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
    4300             : /// of instructions. Legal values are:
    4301             : ///     ror #n  'n' in {0, 8, 16, 24}
    4302             : OperandMatchResultTy
    4303         244 : ARMAsmParser::parseRotImm(OperandVector &Operands) {
    4304         244 :   MCAsmParser &Parser = getParser();
    4305         244 :   const AsmToken &Tok = Parser.getTok();
    4306         244 :   SMLoc S = Tok.getLoc();
    4307         244 :   if (Tok.isNot(AsmToken::Identifier))
    4308             :     return MatchOperand_NoMatch;
    4309         242 :   StringRef ShiftName = Tok.getString();
    4310         256 :   if (ShiftName != "ror" && ShiftName != "ROR")
    4311             :     return MatchOperand_NoMatch;
    4312         228 :   Parser.Lex(); // Eat the operator.
    4313             : 
    4314             :   // A '#' and a rotate amount.
    4315         230 :   if (Parser.getTok().isNot(AsmToken::Hash) &&
    4316           2 :       Parser.getTok().isNot(AsmToken::Dollar)) {
    4317           6 :     Error(Parser.getTok().getLoc(), "'#' expected");
    4318           2 :     return MatchOperand_ParseFail;
    4319             :   }
    4320         226 :   Parser.Lex(); // Eat hash token.
    4321         226 :   SMLoc ExLoc = Parser.getTok().getLoc();
    4322             : 
    4323             :   const MCExpr *ShiftAmount;
    4324         226 :   SMLoc EndLoc;
    4325         226 :   if (getParser().parseExpression(ShiftAmount, EndLoc)) {
    4326           6 :     Error(ExLoc, "malformed rotate expression");
    4327           2 :     return MatchOperand_ParseFail;
    4328             :   }
    4329         446 :   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
    4330             :   if (!CE) {
    4331           6 :     Error(ExLoc, "rotate amount must be an immediate");
    4332           2 :     return MatchOperand_ParseFail;
    4333             :   }
    4334             : 
    4335         222 :   int64_t Val = CE->getValue();
    4336             :   // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
    4337             :   // normally, zero is represented in asm by omitting the rotate operand
    4338             :   // entirely.
    4339         222 :   if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
    4340          12 :     Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
    4341           4 :     return MatchOperand_ParseFail;
    4342             :   }
    4343             : 
    4344         872 :   Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
    4345             : 
    4346         218 :   return MatchOperand_Success;
    4347             : }
    4348             : 
    4349             : OperandMatchResultTy
    4350        3448 : ARMAsmParser::parseModImm(OperandVector &Operands) {
    4351        3448 :   MCAsmParser &Parser = getParser();
    4352        6896 :   MCAsmLexer &Lexer = getLexer();
    4353             :   int64_t Imm1, Imm2;
    4354             : 
    4355        3448 :   SMLoc S = Parser.getTok().getLoc();
    4356             : 
    4357             :   // 1) A mod_imm operand can appear in the place of a register name:
    4358             :   //   add r0, #mod_imm
    4359             :   //   add r0, r0, #mod_imm
    4360             :   // to correctly handle the latter, we bail out as soon as we see an
    4361             :   // identifier.
    4362             :   //
    4363             :   // 2) Similarly, we do not want to parse into complex operands:
    4364             :   //   mov r0, #mod_imm
    4365             :   //   mov r0, :lower16:(_foo)
    4366        4678 :   if (Parser.getTok().is(AsmToken::Identifier) ||
    4367        1230 :       Parser.getTok().is(AsmToken::Colon))
    4368             :     return MatchOperand_NoMatch;
    4369             : 
    4370             :   // Hash (dollar) is optional as per the ARMARM
    4371        1538 :   if (Parser.getTok().is(AsmToken::Hash) ||
    4372         312 :       Parser.getTok().is(AsmToken::Dollar)) {
    4373             :     // Avoid parsing into complex operands (#:)
    4374        2060 :     if (Lexer.peekTok().is(AsmToken::Colon))
    4375             :       return MatchOperand_NoMatch;
    4376             : 
    4377             :     // Eat the hash (dollar)
    4378        1028 :     Parser.Lex();
    4379             :   }
    4380             : 
    4381        1224 :   SMLoc Sx1, Ex1;
    4382        1224 :   Sx1 = Parser.getTok().getLoc();
    4383             :   const MCExpr *Imm1Exp;
    4384        1224 :   if (getParser().parseExpression(Imm1Exp, Ex1)) {
    4385           6 :     Error(Sx1, "malformed expression");
    4386           2 :     return MatchOperand_ParseFail;
    4387             :   }
    4388             : 
    4389        2433 :   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
    4390             : 
    4391             :   if (CE) {
    4392             :     // Immediate must fit within 32-bits
    4393        1211 :     Imm1 = CE->getValue();
    4394        1211 :     int Enc = ARM_AM::getSOImmVal(Imm1);
    4395        1211 :     if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
    4396             :       // We have a match!
    4397        3785 :       Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
    4398         757 :                                                   (Enc & 0xF00) >> 7,
    4399             :                                                   Sx1, Ex1));
    4400         757 :       return MatchOperand_Success;
    4401             :     }
    4402             : 
    4403             :     // We have parsed an immediate which is not for us, fallback to a plain
    4404             :     // immediate. This can happen for instruction aliases. For an example,
    4405             :     // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
    4406             :     // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
    4407             :     // instruction with a mod_imm operand. The alias is defined such that the
    4408             :     // parser method is shared, that's why we have to do this here.
    4409         454 :     if (Parser.getTok().is(AsmToken::EndOfStatement)) {
    4410         288 :       Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
    4411          72 :       return MatchOperand_Success;
    4412             :     }
    4413             :   } else {
    4414             :     // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
    4415             :     // MCFixup). Fallback to a plain immediate.
    4416          44 :     Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
    4417          11 :     return MatchOperand_Success;
    4418             :   }
    4419             : 
    4420             :   // From this point onward, we expect the input to be a (#bits, #rot) pair
    4421         382 :   if (Parser.getTok().isNot(AsmToken::Comma)) {
    4422           0 :     Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
    4423           0 :     return MatchOperand_ParseFail;
    4424             :   }
    4425             : 
    4426         382 :   if (Imm1 & ~0xFF) {
    4427         120 :     Error(Sx1, "immediate operand must a number in the range [0, 255]");
    4428          40 :     return MatchOperand_ParseFail;
    4429             :   }
    4430             : 
    4431             :   // Eat the comma
    4432         342 :   Parser.Lex();
    4433             : 
    4434             :   // Repeat for #rot
    4435         342 :   SMLoc Sx2, Ex2;
    4436         342 :   Sx2 = Parser.getTok().getLoc();
    4437             : 
    4438             :   // Eat the optional hash (dollar)
    4439         516 :   if (Parser.getTok().is(AsmToken::Hash) ||
    4440         174 :       Parser.getTok().is(AsmToken::Dollar))
    4441         226 :     Parser.Lex();
    4442             : 
    4443             :   const MCExpr *Imm2Exp;
    4444         342 :   if (getParser().parseExpression(Imm2Exp, Ex2)) {
    4445           0 :     Error(Sx2, "malformed expression");
    4446           0 :     return MatchOperand_ParseFail;
    4447             :   }
    4448             : 
    4449         684 :   CE = dyn_cast<MCConstantExpr>(Imm2Exp);
    4450             : 
    4451             :   if (CE) {
    4452         342 :     Imm2 = CE->getValue();
    4453         342 :     if (!(Imm2 & ~0x1E)) {
    4454             :       // We have a match!
    4455        1208 :       Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
    4456         302 :       return MatchOperand_Success;
    4457             :     }
    4458         120 :     Error(Sx2, "immediate operand must an even number in the range [0, 30]");
    4459          40 :     return MatchOperand_ParseFail;
    4460             :   } else {
    4461           0 :     Error(Sx2, "constant expression expected");
    4462           0 :     return MatchOperand_ParseFail;
    4463             :   }
    4464             : }
    4465             : 
    4466             : OperandMatchResultTy
    4467          34 : ARMAsmParser::parseBitfield(OperandVector &Operands) {
    4468          34 :   MCAsmParser &Parser = getParser();
    4469          34 :   SMLoc S = Parser.getTok().getLoc();
    4470             :   // The bitfield descriptor is really two operands, the LSB and the width.
    4471          34 :   if (Parser.getTok().isNot(AsmToken::Hash) &&
    4472           0 :       Parser.getTok().isNot(AsmToken::Dollar)) {
    4473           0 :     Error(Parser.getTok().getLoc(), "'#' expected");
    4474           0 :     return MatchOperand_ParseFail;
    4475             :   }
    4476          34 :   Parser.Lex(); // Eat hash token.
    4477             : 
    4478             :   const MCExpr *LSBExpr;
    4479          34 :   SMLoc E = Parser.getTok().getLoc();
    4480          34 :   if (getParser().parseExpression(LSBExpr)) {
    4481           0 :     Error(E, "malformed immediate expression");
    4482           0 :     return MatchOperand_ParseFail;
    4483             :   }
    4484          68 :   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
    4485             :   if (!CE) {
    4486           0 :     Error(E, "'lsb' operand must be an immediate");
    4487           0 :     return MatchOperand_ParseFail;
    4488             :   }
    4489             : 
    4490          34 :   int64_t LSB = CE->getValue();
    4491             :   // The LSB must be in the range [0,31]
    4492          34 :   if (LSB < 0 || LSB > 31) {
    4493           0 :     Error(E, "'lsb' operand must be in the range [0,31]");
    4494           0 :     return MatchOperand_ParseFail;
    4495             :   }
    4496          34 :   E = Parser.getTok().getLoc();
    4497             : 
    4498             :   // Expect another immediate operand.
    4499          34 :   if (Parser.getTok().isNot(AsmToken::Comma)) {
    4500           0 :     Error(Parser.getTok().getLoc(), "too few operands");
    4501           0 :     return MatchOperand_ParseFail;
    4502             :   }
    4503          34 :   Parser.Lex(); // Eat hash token.
    4504          34 :   if (Parser.getTok().isNot(AsmToken::Hash) &&
    4505           0 :       Parser.getTok().isNot(AsmToken::Dollar)) {
    4506           0 :     Error(Parser.getTok().getLoc(), "'#' expected");
    4507           0 :     return MatchOperand_ParseFail;
    4508             :   }
    4509          34 :   Parser.Lex(); // Eat hash token.
    4510             : 
    4511             :   const MCExpr *WidthExpr;
    4512          34 :   SMLoc EndLoc;
    4513          34 :   if (getParser().parseExpression(WidthExpr, EndLoc)) {
    4514           0 :     Error(E, "malformed immediate expression");
    4515           0 :     return MatchOperand_ParseFail;
    4516             :   }
    4517          68 :   CE = dyn_cast<MCConstantExpr>(WidthExpr);
    4518             :   if (!CE) {
    4519           0 :     Error(E, "'width' operand must be an immediate");
    4520           0 :     return MatchOperand_ParseFail;
    4521             :   }
    4522             : 
    4523          34 :   int64_t Width = CE->getValue();
    4524             :   // The LSB must be in the range [1,32-lsb]
    4525          34 :   if (Width < 1 || Width > 32 - LSB) {
    4526           0 :     Error(E, "'width' operand must be in the range [1,32-lsb]");
    4527           0 :     return MatchOperand_ParseFail;
    4528             :   }
    4529             : 
    4530         136 :   Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
    4531             : 
    4532          34 :   return MatchOperand_Success;
    4533             : }
    4534             : 
    4535             : OperandMatchResultTy
    4536          95 : ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
    4537             :   // Check for a post-index addressing register operand. Specifically:
    4538             :   // postidx_reg := '+' register {, shift}
    4539             :   //              | '-' register {, shift}
    4540             :   //              | register {, shift}
    4541             : 
    4542             :   // This method must return MatchOperand_NoMatch without consuming any tokens
    4543             :   // in the case where there is no match, as other alternatives take other
    4544             :   // parse methods.
    4545          95 :   MCAsmParser &Parser = getParser();
    4546         285 :   AsmToken Tok = Parser.getTok();
    4547          95 :   SMLoc S = Tok.getLoc();
    4548          95 :   bool haveEaten = false;
    4549          95 :   bool isAdd = true;
    4550          95 :   if (Tok.is(AsmToken::Plus)) {
    4551           0 :     Parser.Lex(); // Eat the '+' token.
    4552           0 :     haveEaten = true;
    4553          95 :   } else if (Tok.is(AsmToken::Minus)) {
    4554          10 :     Parser.Lex(); // Eat the '-' token.
    4555          10 :     isAdd = false;
    4556          10 :     haveEaten = true;
    4557             :   }
    4558             : 
    4559          95 :   SMLoc E = Parser.getTok().getEndLoc();
    4560          95 :   int Reg = tryParseRegister();
    4561          95 :   if (Reg == -1) {
    4562          43 :     if (!haveEaten)
    4563             :       return MatchOperand_NoMatch;
    4564           0 :     Error(Parser.getTok().getLoc(), "register expected");
    4565           0 :     return MatchOperand_ParseFail;
    4566             :   }
    4567             : 
    4568          52 :   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
    4569          52 :   unsigned ShiftImm = 0;
    4570          52 :   if (Parser.getTok().is(AsmToken::Comma)) {
    4571          17 :     Parser.Lex(); // Eat the ','.
    4572          17 :     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
    4573             :       return MatchOperand_ParseFail;
    4574             : 
    4575             :     // FIXME: Only approximates end...may include intervening whitespace.
    4576          13 :     E = Parser.getTok().getLoc();
    4577             :   }
    4578             : 
    4579         144 :   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
    4580             :                                                   ShiftImm, S, E));
    4581             : 
    4582          48 :   return MatchOperand_Success;
    4583             : }
    4584             : 
    4585             : OperandMatchResultTy
    4586          50 : ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
    4587             :   // Check for a post-index addressing register operand. Specifically:
    4588             :   // am3offset := '+' register
    4589             :   //              | '-' register
    4590             :   //              | register
    4591             :   //              | # imm
    4592             :   //              | # + imm
    4593             :   //              | # - imm
    4594             : 
    4595             :   // This method must return MatchOperand_NoMatch without consuming any tokens
    4596             :   // in the case where there is no match, as other alternatives take other
    4597             :   // parse methods.
    4598          50 :   MCAsmParser &Parser = getParser();
    4599         150 :   AsmToken Tok = Parser.getTok();
    4600          50 :   SMLoc S = Tok.getLoc();
    4601             : 
    4602             :   // Do immediates first, as we always parse those if we have a '#'.
    4603          73 :   if (Parser.getTok().is(AsmToken::Hash) ||
    4604          23 :       Parser.getTok().is(AsmToken::Dollar)) {
    4605          27 :     Parser.Lex(); // Eat '#' or '$'.
    4606             :     // Explicitly look for a '-', as we need to encode negative zero
    4607             :     // differently.
    4608          54 :     bool isNegative = Parser.getTok().is(AsmToken::Minus);
    4609             :     const MCExpr *Offset;
    4610          27 :     SMLoc E;
    4611          27 :     if (getParser().parseExpression(Offset, E))
    4612             :       return MatchOperand_ParseFail;
    4613          54 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
    4614             :     if (!CE) {
    4615           0 :       Error(S, "constant expression expected");
    4616           0 :       return MatchOperand_ParseFail;
    4617             :     }
    4618             :     // Negative zero is encoded as the flag value INT32_MIN.
    4619          27 :     int32_t Val = CE->getValue();
    4620          27 :     if (isNegative && Val == 0)
    4621           2 :       Val = INT32_MIN;
    4622             : 
    4623          81 :     Operands.push_back(
    4624         108 :       ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
    4625             : 
    4626          27 :     return MatchOperand_Success;
    4627             :   }
    4628             : 
    4629             : 
    4630          23 :   bool haveEaten = false;
    4631          23 :   bool isAdd = true;
    4632          23 :   if (Tok.is(AsmToken::Plus)) {
    4633           0 :     Parser.Lex(); // Eat the '+' token.
    4634           0 :     haveEaten = true;
    4635          23 :   } else if (Tok.is(AsmToken::Minus)) {
    4636           6 :     Parser.Lex(); // Eat the '-' token.
    4637           6 :     isAdd = false;
    4638           6 :     haveEaten = true;
    4639             :   }
    4640             : 
    4641          46 :   Tok = Parser.getTok();
    4642          23 :   int Reg = tryParseRegister();
    4643          23 :   if (Reg == -1) {
    4644           0 :     if (!haveEaten)
    4645             :       return MatchOperand_NoMatch;
    4646           0 :     Error(Tok.getLoc(), "register expected");
    4647           0 :     return MatchOperand_ParseFail;
    4648             :   }
    4649             : 
    4650          69 :   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
    4651             :                                                   0, S, Tok.getEndLoc()));
    4652             : 
    4653          23 :   return MatchOperand_Success;
    4654             : }
    4655             : 
    4656             : /// Convert parsed operands to MCInst.  Needed here because this instruction
    4657             : /// only has two register operands, but multiplication is commutative so
    4658             : /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
    4659          16 : void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
    4660             :                                     const OperandVector &Operands) {
    4661          48 :   ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
    4662          48 :   ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
    4663             :   // If we have a three-operand form, make sure to set Rn to be the operand
    4664             :   // that isn't the same as Rd.
    4665          16 :   unsigned RegOp = 4;
    4666          45 :   if (Operands.size() == 6 &&
    4667          52 :       ((ARMOperand &)*Operands[4]).getReg() ==
    4668          52 :           ((ARMOperand &)*Operands[3]).getReg())
    4669             :     RegOp = 5;
    4670          48 :   ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
    4671          32 :   Inst.addOperand(Inst.getOperand(0));
    4672          48 :   ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
    4673          16 : }
    4674             : 
    4675         307 : void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
    4676             :                                     const OperandVector &Operands) {
    4677         307 :   int CondOp = -1, ImmOp = -1;
    4678         307 :   switch(Inst.getOpcode()) {
    4679             :     case ARM::tB:
    4680             :     case ARM::tBcc:  CondOp = 1; ImmOp = 2; break;
    4681             : 
    4682          99 :     case ARM::t2B:
    4683          99 :     case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
    4684             : 
    4685           0 :     default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
    4686             :   }
    4687             :   // first decide whether or not the branch should be conditional
    4688             :   // by looking at it's location relative to an IT block
    4689         307 :   if(inITBlock()) {
    4690             :     // inside an IT block we cannot have any conditional branches. any 
    4691             :     // such instructions needs to be converted to unconditional form
    4692          38 :     switch(Inst.getOpcode()) {
    4693           0 :       case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
    4694          19 :       case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
    4695             :     }
    4696             :   } else {
    4697             :     // outside IT blocks we can only have unconditional branches with AL
    4698             :     // condition code or conditional branches with non-AL condition code
    4699         807 :     unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
    4700         269 :     switch(Inst.getOpcode()) {
    4701         189 :       case ARM::tB:
    4702             :       case ARM::tBcc: 
    4703         189 :         Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); 
    4704             :         break;
    4705          80 :       case ARM::t2B:
    4706             :       case ARM::t2Bcc: 
    4707          80 :         Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
    4708             :         break;
    4709             :     }
    4710             :   }
    4711             : 
    4712             :   // now decide on encoding size based on branch target range
    4713         307 :   switch(Inst.getOpcode()) {
    4714             :     // classify tB as either t2B or t1B based on range of immediate operand
    4715         127 :     case ARM::tB: {
    4716         381 :       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
    4717          64 :       if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
    4718          26 :         Inst.setOpcode(ARM::t2B);
    4719             :       break;
    4720             :     }
    4721             :     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
    4722          81 :     case ARM::tBcc: {
    4723         243 :       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
    4724          62 :       if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
    4725          25 :         Inst.setOpcode(ARM::t2Bcc);
    4726             :       break;
    4727             :     }
    4728             :   }
    4729        1228 :   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
    4730         921 :   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
    4731         307 : }
    4732             : 
    4733             : /// Parse an ARM memory expression, return false if successful else return true
    4734             : /// or an error.  The first token must be a '[' when called.
    4735        5304 : bool ARMAsmParser::parseMemory(OperandVector &Operands) {
    4736        5304 :   MCAsmParser &Parser = getParser();
    4737        5304 :   SMLoc S, E;
    4738        5304 :   if (Parser.getTok().isNot(AsmToken::LBrac))
    4739           0 :     return TokError("Token is not a Left Bracket");
    4740        5304 :   S = Parser.getTok().getLoc();
    4741        5304 :   Parser.Lex(); // Eat left bracket token.
    4742             : 
    4743        5304 :   const AsmToken &BaseRegTok = Parser.getTok();
    4744        5304 :   int BaseRegNum = tryParseRegister();
    4745        5304 :   if (BaseRegNum == -1)
    4746           0 :     return Error(BaseRegTok.getLoc(), "register expected");
    4747             : 
    4748             :   // The next token must either be a comma, a colon or a closing bracket.
    4749        5304 :   const AsmToken &Tok = Parser.getTok();
    4750        7077 :   if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
    4751        1773 :       !Tok.is(AsmToken::RBrac))
    4752           0 :     return Error(Tok.getLoc(), "malformed memory operand");
    4753             : 
    4754        5304 :   if (Tok.is(AsmToken::RBrac)) {
    4755        1773 :     E = Tok.getEndLoc();
    4756        1773 :     Parser.Lex(); // Eat right bracket token.
    4757             : 
    4758        7092 :     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
    4759             :                                              ARM_AM::no_shift, 0, 0, false,
    4760        1773 :                                              S, E));
    4761             : 
    4762             :     // If there's a pre-indexing writeback marker, '!', just add it as a token
    4763             :     // operand. It's rather odd, but syntactically valid.
    4764        1773 :     if (Parser.getTok().is(AsmToken::Exclaim)) {
    4765         832 :       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
    4766         208 :       Parser.Lex(); // Eat the '!'.
    4767             :     }
    4768             : 
    4769             :     return false;
    4770             :   }
    4771             : 
    4772             :   assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
    4773             :          "Lost colon or comma in memory operand?!");
    4774        3531 :   if (Tok.is(AsmToken::Comma)) {
    4775        1405 :     Parser.Lex(); // Eat the comma.
    4776             :   }
    4777             : 
    4778             :   // If we have a ':', it's an alignment specifier.
    4779        3531 :   if (Parser.getTok().is(AsmToken::Colon)) {
    4780        2130 :     Parser.Lex(); // Eat the ':'.
    4781        2130 :     E = Parser.getTok().getLoc();
    4782        2130 :     SMLoc AlignmentLoc = Tok.getLoc();
    4783             : 
    4784             :     const MCExpr *Expr;
    4785        2130 :     if (getParser().parseExpression(Expr))
    4786             :      return true;
    4787             : 
    4788             :     // The expression has to be a constant. Memory references with relocations
    4789             :     // don't come through here, as they use the <label> forms of the relevant
    4790             :     // instructions.
    4791        4260 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
    4792             :     if (!CE)
    4793           0 :       return Error (E, "constant expression expected");
    4794             : 
    4795        2130 :     unsigned Align = 0;
    4796        2130 :     switch (CE->getValue()) {
    4797           0 :     default:
    4798           0 :       return Error(E,
    4799           0 :                    "alignment specifier must be 16, 32, 64, 128, or 256 bits");
    4800             :     case 16:  Align = 2; break;
    4801         410 :     case 32:  Align = 4; break;
    4802         473 :     case 64:  Align = 8; break;
    4803         429 :     case 128: Align = 16; break;
    4804         417 :     case 256: Align = 32; break;
    4805             :     }
    4806             : 
    4807             :     // Now we should have the closing ']'
    4808        2130 :     if (Parser.getTok().isNot(AsmToken::RBrac))
    4809           0 :       return Error(Parser.getTok().getLoc(), "']' expected");
    4810        2130 :     E = Parser.getTok().getEndLoc();
    4811        2130 :     Parser.Lex(); // Eat right bracket token.
    4812             : 
    4813             :     // Don't worry about range checking the value here. That's handled by
    4814             :     // the is*() predicates.
    4815        6390 :     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
    4816             :                                              ARM_AM::no_shift, 0, Align,
    4817             :                                              false, S, E, AlignmentLoc));
    4818             : 
    4819             :     // If there's a pre-indexing writeback marker, '!', just add it as a token
    4820             :     // operand.
    4821        2130 :     if (Parser.getTok().is(AsmToken::Exclaim)) {
    4822        2832 :       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
    4823         708 :       Parser.Lex(); // Eat the '!'.
    4824             :     }
    4825             : 
    4826             :     return false;
    4827             :   }
    4828             : 
    4829             :   // If we have a '#', it's an immediate offset, else assume it's a register
    4830             :   // offset. Be friendly and also accept a plain integer (without a leading
    4831             :   // hash) for gas compatibility.
    4832        1814 :   if (Parser.getTok().is(AsmToken::Hash) ||
    4833        1814 :       Parser.getTok().is(AsmToken::Dollar) ||
    4834         413 :       Parser.getTok().is(AsmToken::Integer)) {
    4835         988 :     if (Parser.getTok().isNot(AsmToken::Integer))
    4836         988 :       Parser.Lex(); // Eat '#' or '$'.
    4837         988 :     E = Parser.getTok().getLoc();
    4838             : 
    4839        1976 :     bool isNegative = getParser().getTok().is(AsmToken::Minus);
    4840             :     const MCExpr *Offset;
    4841         988 :     if (getParser().parseExpression(Offset))
    4842             :      return true;
    4843             : 
    4844             :     // The expression has to be a constant. Memory references with relocations
    4845             :     // don't come through here, as they use the <label> forms of the relevant
    4846             :     // instructions.
    4847        1976 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
    4848             :     if (!CE)
    4849           0 :       return Error (E, "constant expression expected");
    4850             : 
    4851             :     // If the constant was #-0, represent it as INT32_MIN.
    4852         988 :     int32_t Val = CE->getValue();
    4853         988 :     if (isNegative && Val == 0)
    4854         390 :       CE = MCConstantExpr::create(INT32_MIN, getContext());
    4855             : 
    4856             :     // Now we should have the closing ']'
    4857         988 :     if (Parser.getTok().isNot(AsmToken::RBrac))
    4858           0 :       return Error(Parser.getTok().getLoc(), "']' expected");
    4859         988 :     E = Parser.getTok().getEndLoc();
    4860         988 :     Parser.Lex(); // Eat right bracket token.
    4861             : 
    4862             :     // Don't worry about range checking the value here. That's handled by
    4863             :     // the is*() predicates.
    4864        3952 :     Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
    4865             :                                              ARM_AM::no_shift, 0, 0,
    4866         988 :                                              false, S, E));
    4867             : 
    4868             :     // If there's a pre-indexing writeback marker, '!', just add it as a token
    4869             :     // operand.
    4870         988 :     if (Parser.getTok().is(AsmToken::Exclaim)) {
    4871        1216 :       Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
    4872         304 :       Parser.Lex(); // Eat the '!'.
    4873             :     }
    4874             : 
    4875             :     return false;
    4876             :   }
    4877             : 
    4878             :   // The register offset is optionally preceded by a '+' or '-'
    4879         413 :   bool isNegative = false;
    4880         413 :   if (Parser.getTok().is(AsmToken::Minus)) {
    4881          19 :     isNegative = true;
    4882          19 :     Parser.Lex(); // Eat the '-'.
    4883         394 :   } else if (Parser.getTok().is(AsmToken::Plus)) {
    4884             :     // Nothing to do.
    4885           1 :     Parser.Lex(); // Eat the '+'.
    4886             :   }
    4887             : 
    4888         413 :   E = Parser.getTok().getLoc();
    4889         413 :   int OffsetRegNum = tryParseRegister();
    4890         413 :   if (OffsetRegNum == -1)
    4891           0 :     return Error(E, "register expected");
    4892             : 
    4893             :   // If there's a shift operator, handle it.
    4894         413 :   ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
    4895         413 :   unsigned ShiftImm = 0;
    4896         413 :   if (Parser.getTok().is(AsmToken::Comma)) {
    4897         134 :     Parser.Lex(); // Eat the ','.
    4898         134 :     if (parseMemRegOffsetShift(ShiftType, ShiftImm))
    4899             :       return true;
    4900             :   }
    4901             : 
    4902             :   // Now we should have the closing ']'
    4903         399 :   if (Parser.getTok().isNot(AsmToken::RBrac))
    4904           6 :     return Error(Parser.getTok().getLoc(), "']' expected");
    4905         397 :   E = Parser.getTok().getEndLoc();
    4906         397 :   Parser.Lex(); // Eat right bracket token.
    4907             : 
    4908        1588 :   Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
    4909             :                                            ShiftType, ShiftImm, 0, isNegative,
    4910         397 :                                            S, E));
    4911             : 
    4912             :   // If there's a pre-indexing writeback marker, '!', just add it as a token
    4913             :   // operand.
    4914         397 :   if (Parser.getTok().is(AsmToken::Exclaim)) {
    4915         160 :     Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
    4916          40 :     Parser.Lex(); // Eat the '!'.
    4917             :   }
    4918             : 
    4919             :   return false;
    4920             : }
    4921             : 
    4922             : /// parseMemRegOffsetShift - one of these two:
    4923             : ///   ( lsl | lsr | asr | ror ) , # shift_amount
    4924             : ///   rrx
    4925             : /// return true if it parses a shift otherwise it returns false.
    4926         151 : bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
    4927             :                                           unsigned &Amount) {
    4928         151 :   MCAsmParser &Parser = getParser();
    4929         151 :   SMLoc Loc = Parser.getTok().getLoc();
    4930         151 :   const AsmToken &Tok = Parser.getTok();
    4931         151 :   if (Tok.isNot(AsmToken::Identifier))
    4932             :     return true;
    4933         151 :   StringRef ShiftName = Tok.getString();
    4934         198 :   if (ShiftName == "lsl" || ShiftName == "LSL" ||
    4935          90 :       ShiftName == "asl" || ShiftName == "ASL")
    4936         106 :     St = ARM_AM::lsl;
    4937          73 :   else if (ShiftName == "lsr" || ShiftName == "LSR")
    4938          17 :     St = ARM_AM::lsr;
    4939          42 :   else if (ShiftName == "asr" || ShiftName == "ASR")
    4940          14 :     St = ARM_AM::asr;
    4941          20 :   else if (ShiftName == "ror" || ShiftName == "ROR")
    4942           8 :     St = ARM_AM::ror;
    4943           6 :   else if (ShiftName == "rrx" || ShiftName == "RRX")
    4944           6 :     St = ARM_AM::rrx;
    4945             :   else
    4946           0 :     return Error(Loc, "illegal shift operator");
    4947         151 :   Parser.Lex(); // Eat shift type token.
    4948             : 
    4949             :   // rrx stands alone.
    4950         151 :   Amount = 0;
    4951         151 :   if (St != ARM_AM::rrx) {
    4952         145 :     Loc = Parser.getTok().getLoc();
    4953             :     // A '#' and a shift amount.
    4954         145 :     const AsmToken &HashTok = Parser.getTok();
    4955         145 :     if (HashTok.isNot(AsmToken::Hash) &&
    4956           0 :         HashTok.isNot(AsmToken::Dollar))
    4957           0 :       return Error(HashTok.getLoc(), "'#' expected");
    4958         145 :     Parser.Lex(); // Eat hash token.
    4959             : 
    4960             :     const MCExpr *Expr;
    4961         145 :     if (getParser().parseExpression(Expr))
    4962             :       return true;
    4963             :     // Range check the immediate.
    4964             :     // lsl, ror: 0 <= imm <= 31
    4965             :     // lsr, asr: 0 <= imm <= 32
    4966         288 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
    4967             :     if (!CE)
    4968           6 :       return Error(Loc, "shift amount must be an immediate");
    4969         143 :     int64_t Imm = CE->getValue();
    4970         278 :     if (Imm < 0 ||
    4971         374 :         ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
    4972         158 :         ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
    4973          48 :       return Error(Loc, "immediate shift value out of range");
    4974             :     // If <ShiftTy> #0, turn it into a no_shift.
    4975         127 :     if (Imm == 0)
    4976          25 :       St = ARM_AM::lsl;
    4977             :     // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
    4978         127 :     if (Imm == 32)
    4979           6 :       Imm = 0;
    4980         127 :     Amount = Imm;
    4981             :   }
    4982             : 
    4983             :   return false;
    4984             : }
    4985             : 
    4986             : /// parseFPImm - A floating point immediate expression operand.
    4987             : OperandMatchResultTy
    4988         482 : ARMAsmParser::parseFPImm(OperandVector &Operands) {
    4989         482 :   MCAsmParser &Parser = getParser();
    4990             :   // Anything that can accept a floating point constant as an operand
    4991             :   // needs to go through here, as the regular parseExpression is
    4992             :   // integer only.
    4993             :   //
    4994             :   // This routine still creates a generic Immediate operand, containing
    4995             :   // a bitcast of the 64-bit floating point value. The various operands
    4996             :   // that accept floats can check whether the value is valid for them
    4997             :   // via the standard is*() predicates.
    4998             : 
    4999         482 :   SMLoc S = Parser.getTok().getLoc();
    5000             : 
    5001         719 :   if (Parser.getTok().isNot(AsmToken::Hash) &&
    5002         237 :       Parser.getTok().isNot(AsmToken::Dollar))
    5003             :     return MatchOperand_NoMatch;
    5004             : 
    5005             :   // Disambiguate the VMOV forms that can accept an FP immediate.
    5006             :   // vmov.f32 <sreg>, #imm
    5007             :   // vmov.f64 <dreg>, #imm
    5008             :   // vmov.f32 <dreg>, #imm  @ vector f32x2
    5009             :   // vmov.f32 <qreg>, #imm  @ vector f32x4
    5010             :   //
    5011             :   // There are also the NEON VMOV instructions which expect an
    5012             :   // integer constant. Make sure we don't try to parse an FPImm
    5013             :   // for these:
    5014             :   // vmov.i{8|16|32|64} <dreg|qreg>, #imm
    5015         735 :   ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
    5016         490 :   bool isVmovf = TyOp.isToken() &&
    5017         447 :                  (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
    5018         449 :                   TyOp.getToken() == ".f16");
    5019         735 :   ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
    5020         490 :   bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
    5021         485 :                                          Mnemonic.getToken() == "fconsts");
    5022         245 :   if (!(isVmovf || isFconst))
    5023             :     return MatchOperand_NoMatch;
    5024             : 
    5025          45 :   Parser.Lex(); // Eat '#' or '$'.
    5026             : 
    5027             :   // Handle negation, as that still comes through as a separate token.
    5028          45 :   bool isNegative = false;
    5029          45 :   if (Parser.getTok().is(AsmToken::Minus)) {
    5030          10 :     isNegative = true;
    5031          10 :     Parser.Lex();
    5032             :   }
    5033          45 :   const AsmToken &Tok = Parser.getTok();
    5034          45 :   SMLoc Loc = Tok.getLoc();
    5035          45 :   if (Tok.is(AsmToken::Real) && isVmovf) {
    5036          66 :     APFloat RealVal(APFloat::IEEEsingle(), Tok.getString());
    5037          99 :     uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
    5038             :     // If we had a '-' in front, toggle the sign bit.
    5039          33 :     IntVal ^= (uint64_t)isNegative << 31;
    5040          33 :     Parser.Lex(); // Eat the token.
    5041         165 :     Operands.push_back(ARMOperand::CreateImm(
    5042          66 :           MCConstantExpr::create(IntVal, getContext()),
    5043          33 :           S, Parser.getTok().getLoc()));
    5044          33 :     return MatchOperand_Success;
    5045             :   }
    5046             :   // Also handle plain integers. Instructions which allow floating point
    5047             :   // immediates also allow a raw encoded 8-bit value.
    5048          22 :   if (Tok.is(AsmToken::Integer) && isFconst) {
    5049           8 :     int64_t Val = Tok.getIntVal();
    5050           8 :     Parser.Lex(); // Eat the token.
    5051           8 :     if (Val > 255 || Val < 0) {
    5052           0 :       Error(Loc, "encoded floating point value out of range");
    5053           0 :       return MatchOperand_ParseFail;
    5054             :     }
    5055           8 :     float RealVal = ARM_AM::getFPImmFloat(Val);
    5056          32 :     Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
    5057             : 
    5058          40 :     Operands.push_back(ARMOperand::CreateImm(
    5059          16 :         MCConstantExpr::create(Val, getContext()), S,
    5060           8 :         Parser.getTok().getLoc()));
    5061           8 :     return MatchOperand_Success;
    5062             :   }
    5063             : 
    5064          12 :   Error(Loc, "invalid floating point immediate");
    5065           4 :   return MatchOperand_ParseFail;
    5066             : }
    5067             : 
    5068             : /// Parse a arm instruction operand.  For now this parses the operand regardless
    5069             : /// of the mnemonic.
    5070       54869 : bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
    5071       54869 :   MCAsmParser &Parser = getParser();
    5072       54869 :   SMLoc S, E;
    5073             : 
    5074             :   // Check if the current operand has a custom associated parser, if so, try to
    5075             :   // custom parse the operand, or fallback to the general approach.
    5076       54869 :   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
    5077       54869 :   if (ResTy == MatchOperand_Success)
    5078             :     return false;
    5079             :   // If there wasn't a custom match, try the generic matcher below. Otherwise,
    5080             :   // there was a match, but an error occurred, in which case, just return that
    5081             :   // the operand parsing failed.
    5082       45036 :   if (ResTy == MatchOperand_ParseFail)
    5083             :     return true;
    5084             : 
    5085      134658 :   switch (getLexer().getKind()) {
    5086           2 :   default:
    5087           6 :     Error(Parser.getTok().getLoc(), "unexpected token in operand");
    5088           2 :     return true;
    5089       33859 :   case AsmToken::Identifier: {
    5090             :     // If we've seen a branch mnemonic, the next operand must be a label.  This
    5091             :     // is true even if the label is a register name.  So "br r1" means branch to
    5092             :     // label "r1".
    5093      101139 :     bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
    5094             :     if (!ExpectLabel) {
    5095       33575 :       if (!tryParseRegisterWithWriteBack(Operands))
    5096             :         return false;
    5097        1211 :       int Res = tryParseShiftRegister(Operands);
    5098        1211 :       if (Res == 0) // success
    5099             :         return false;
    5100         333 :       else if (Res == -1) // irrecoverable error
    5101             :         return true;
    5102             :       // If this is VMRS, check for the apsr_nzcv operand.
    5103         312 :       if (Mnemonic == "vmrs" &&
    5104         312 :           Parser.getTok().getString().equals_lower("apsr_nzcv")) {
    5105           0 :         S = Parser.getTok().getLoc();
    5106           0 :         Parser.Lex();
    5107           0 :         Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
    5108           0 :         return false;
    5109             :       }
    5110             :     }
    5111             : 
    5112             :     // Fall though for the Identifier case that is not a register or a
    5113             :     // special name.
    5114             :     LLVM_FALLTHROUGH;
    5115             :   }
    5116             :   case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
    5117             :   case AsmToken::Integer: // things like 1f and 2b as a branch targets
    5118             :   case AsmToken::String:  // quoted label names.
    5119             :   case AsmToken::Dot: {   // . as a branch target
    5120             :     // This was not a register so parse other operands that start with an
    5121             :     // identifier (like labels) as expressions and create them as immediates.
    5122             :     const MCExpr *IdVal;
    5123         639 :     S = Parser.getTok().getLoc();
    5124         639 :     if (getParser().parseExpression(IdVal))
    5125             :       return true;
    5126        1908 :     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    5127        2544 :     Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
    5128         636 :     return false;
    5129             :   }
    5130        5304 :   case AsmToken::LBrac:
    5131        5304 :     return parseMemory(Operands);
    5132         716 :   case AsmToken::LCurly:
    5133         716 :     return parseRegisterList(Operands);
    5134        4409 :   case AsmToken::Dollar:
    5135             :   case AsmToken::Hash: {
    5136             :     // #42 -> immediate.
    5137        4409 :     S = Parser.getTok().getLoc();
    5138        4409 :     Parser.Lex();
    5139             : 
    5140        4409 :     if (Parser.getTok().isNot(AsmToken::Colon)) {
    5141        8772 :       bool isNegative = Parser.getTok().is(AsmToken::Minus);
    5142             :       const MCExpr *ImmVal;
    5143        4386 :       if (getParser().parseExpression(ImmVal))
    5144             :         return true;
    5145        8768 :       const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
    5146             :       if (CE) {
    5147        4382 :         int32_t Val = CE->getValue();
    5148        4382 :         if (isNegative && Val == 0)
    5149         188 :           ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
    5150             :       }
    5151       13158 :       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    5152       17544 :       Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
    5153             : 
    5154             :       // There can be a trailing '!' on operands that we want as a separate
    5155             :       // '!' Token operand. Handle that here. For example, the compatibility
    5156             :       // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
    5157        4386 :       if (Parser.getTok().is(AsmToken::Exclaim)) {
    5158          84 :         Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
    5159          28 :                                                    Parser.getTok().getLoc()));
    5160          28 :         Parser.Lex(); // Eat exclaim token
    5161             :       }
    5162             :       return false;
    5163             :     }
    5164             :     // w/ a ':' after the '#', it's just like a plain ':'.
    5165             :     LLVM_FALLTHROUGH;
    5166             :   }
    5167             :   case AsmToken::Colon: {
    5168         190 :     S = Parser.getTok().getLoc();
    5169             :     // ":lower16:" and ":upper16:" expression prefixes
    5170             :     // FIXME: Check it's an expression prefix,
    5171             :     // e.g. (FOO - :lower16:BAR) isn't legal.
    5172             :     ARMMCExpr::VariantKind RefKind;
    5173         190 :     if (parsePrefix(RefKind))
    5174             :       return true;
    5175             : 
    5176             :     const MCExpr *SubExprVal;
    5177         190 :     if (getParser().parseExpression(SubExprVal))
    5178             :       return true;
    5179             : 
    5180         380 :     const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
    5181         190 :                                               getContext());
    5182         570 :     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    5183         760 :     Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
    5184         190 :     return false;
    5185             :   }
    5186         386 :   case AsmToken::Equal: {
    5187         386 :     S = Parser.getTok().getLoc();
    5188         772 :     if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
    5189           0 :       return Error(S, "unexpected token in operand");
    5190         386 :     Parser.Lex(); // Eat '='
    5191             :     const MCExpr *SubExprVal;
    5192         386 :     if (getParser().parseExpression(SubExprVal))
    5193             :       return true;
    5194        1158 :     E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
    5195             : 
    5196             :     // execute-only: we assume that assembly programmers know what they are
    5197             :     // doing and allow literal pool creation here
    5198        1544 :     Operands.push_back(ARMOperand::CreateConstantPoolImm(SubExprVal, S, E));
    5199         386 :     return false;
    5200             :   }
    5201             :   }
    5202             : }
    5203             : 
    5204             : // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
    5205             : //  :lower16: and :upper16:.
    5206         190 : bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
    5207         190 :   MCAsmParser &Parser = getParser();
    5208         190 :   RefKind = ARMMCExpr::VK_ARM_None;
    5209             : 
    5210             :   // consume an optional '#' (GNU compatibility)
    5211         570 :   if (getLexer().is(AsmToken::Hash))
    5212           0 :     Parser.Lex();
    5213             : 
    5214             :   // :lower16: and :upper16: modifiers
    5215             :   assert(getLexer().is(AsmToken::Colon) && "expected a :");
    5216         190 :   Parser.Lex(); // Eat ':'
    5217             : 
    5218         570 :   if (getLexer().isNot(AsmToken::Identifier)) {
    5219           0 :     Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
    5220           0 :     return true;
    5221             :   }
    5222             : 
    5223             :   enum {
    5224             :     COFF = (1 << MCObjectFileInfo::IsCOFF),
    5225             :     ELF = (1 << MCObjectFileInfo::IsELF),
    5226             :     MACHO = (1 << MCObjectFileInfo::IsMachO),
    5227             :     WASM = (1 << MCObjectFileInfo::IsWasm),
    5228             :   };
    5229             :   static const struct PrefixEntry {
    5230             :     const char *Spelling;
    5231             :     ARMMCExpr::VariantKind VariantKind;
    5232             :     uint8_t SupportedFormats;
    5233             :   } PrefixEntries[] = {
    5234             :     { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
    5235             :     { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
    5236             :   };
    5237             : 
    5238         380 :   StringRef IDVal = Parser.getTok().getIdentifier();
    5239             : 
    5240             :   const auto &Prefix =
    5241         190 :       std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
    5242         281 :                    [&IDVal](const PrefixEntry &PE) {
    5243         562 :                       return PE.Spelling == IDVal;
    5244         471 :                    });
    5245         190 :   if (Prefix == std::end(PrefixEntries)) {
    5246           0 :     Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
    5247           0 :     return true;
    5248             :   }
    5249             : 
    5250             :   uint8_t CurrentFormat;
    5251         380 :   switch (getContext().getObjectFileInfo()->getObjectFileType()) {
    5252          31 :   case MCObjectFileInfo::IsMachO:
    5253          31 :     CurrentFormat = MACHO;
    5254          31 :     break;
    5255         139 :   case MCObjectFileInfo::IsELF:
    5256         139 :     CurrentFormat = ELF;
    5257         139 :     break;
    5258          20 :   case MCObjectFileInfo::IsCOFF:
    5259          20 :     CurrentFormat = COFF;
    5260          20 :     break;
    5261           0 :   case MCObjectFileInfo::IsWasm:
    5262           0 :     CurrentFormat = WASM;
    5263           0 :     break;
    5264             :   }
    5265             : 
    5266         190 :   if (~Prefix->SupportedFormats & CurrentFormat) {
    5267           0 :     Error(Parser.getTok().getLoc(),
    5268             :           "cannot represent relocation in the current file format");
    5269           0 :     return true;
    5270             :   }
    5271             : 
    5272         190 :   RefKind = Prefix->VariantKind;
    5273         190 :   Parser.Lex();
    5274             : 
    5275         570 :   if (getLexer().isNot(AsmToken::Colon)) {
    5276           0 :     Error(Parser.getTok().getLoc(), "unexpected token after prefix");
    5277           0 :     return true;
    5278             :   }
    5279         190 :   Parser.Lex(); // Eat the last ':'
    5280             : 
    5281         190 :   return false;
    5282             : }
    5283             : 
    5284             : /// \brief Given a mnemonic, split out possible predication code and carry
    5285             : /// setting letters to form a canonical mnemonic and flags.
    5286             : //
    5287             : // FIXME: Would be nice to autogen this.
    5288             : // FIXME: This is a bit of a maze of special cases.
    5289       24250 : StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
    5290             :                                       unsigned &PredicationCode,
    5291             :                                       bool &CarrySetting,
    5292             :                                       unsigned &ProcessorIMod,
    5293             :                                       StringRef &ITMask) {
    5294       24250 :   PredicationCode = ARMCC::AL;
    5295       24250 :   CarrySetting = false;
    5296       24250 :   ProcessorIMod = 0;
    5297             : 
    5298             :   // Ignore some mnemonics we know aren't predicated forms.
    5299             :   //
    5300             :   // FIXME: Would be nice to autogen this.
    5301       24532 :   if ((Mnemonic == "movs" && isThumb()) ||
    5302       72223 :       Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
    5303       71976 :       Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
    5304       71823 :       Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
    5305       71585 :       Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
    5306       71364 :       Mnemonic == "vaclt" || Mnemonic == "vacle"  || Mnemonic == "hlt" ||
    5307       71123 :       Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
    5308       70957 :       Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
    5309       70849 :       Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
    5310       70690 :       Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
    5311       70054 :       Mnemonic == "vcvta" || Mnemonic == "vcvtn"  || Mnemonic == "vcvtp" ||
    5312       69048 :       Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
    5313       68181 :       Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
    5314       67628 :       Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx" ||
    5315       44985 :       Mnemonic == "bxns"  || Mnemonic == "blxns" ||
    5316       44892 :       Mnemonic == "vudot" || Mnemonic == "vsdot")
    5317        1894 :     return Mnemonic;
    5318             : 
    5319             :   // First, split out any predication code. Ignore mnemonics we know aren't
    5320             :   // predicated but do have a carry-set and so weren't caught above.
    5321       66978 :   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
    5322       66810 :       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
    5323       66772 :       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
    5324       44343 :       Mnemonic != "sbcs" && Mnemonic != "rscs") {
    5325       44312 :     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
    5326       22156 :     if (CC != ~0U) {
    5327        7646 :       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
    5328        3823 :       PredicationCode = CC;
    5329             :     }
    5330             :   }
    5331             : 
    5332             :   // Next, determine if we have a carry setting bit. We explicitly ignore all
    5333             :   // the instructions we know end in 's'.
    5334       24151 :   if (Mnemonic.endswith("s") &&
    5335        3577 :       !(Mnemonic == "cps" || Mnemonic == "mls" ||
    5336        5082 :         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
    5337        4842 :         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
    5338        4770 :         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
    5339        4666 :         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
    5340        4650 :         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
    5341        4650 :         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
    5342        4650 :         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
    5343        4581 :         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
    5344        3006 :         Mnemonic == "bxns" || Mnemonic == "blxns" ||
    5345        1561 :         (Mnemonic == "movs" && isThumb()))) {
    5346        2976 :     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
    5347        1488 :     CarrySetting = true;
    5348             :   }
    5349             : 
    5350             :   // The "cps" instruction can have a interrupt mode operand which is glued into
    5351             :   // the mnemonic. Check if this is the case, split it and parse the imod op
    5352       22409 :   if (Mnemonic.startswith("cps")) {
    5353             :     // Split out any imod code.
    5354             :     unsigned IMod =
    5355         106 :       StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
    5356         159 :       .Case("ie", ARM_PROC::IE)
    5357         159 :       .Case("id", ARM_PROC::ID)
    5358         106 :       .Default(~0U);
    5359          40 :     if (IMod != ~0U) {
    5360          80 :       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
    5361          40 :       ProcessorIMod = IMod;
    5362             :     }
    5363             :   }
    5364             : 
    5365             :   // The "it" instruction has the condition mask on the end of the mnemonic.
    5366       25128 :   if (Mnemonic.startswith("it")) {
    5367        5544 :     ITMask = Mnemonic.slice(2, Mnemonic.size());
    5368        2772 :     Mnemonic = Mnemonic.slice(0, 2);
    5369             :   }
    5370             : 
    5371       22356 :   return Mnemonic;
    5372             : }
    5373             : 
    5374             : /// \brief Given a canonical mnemonic, determine if the instruction ever allows
    5375             : /// inclusion of carry set or predication code operands.
    5376             : //
    5377             : // FIXME: It would be nice to autogen this.
    5378       24242 : void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
    5379             :                                          bool &CanAcceptCarrySet,
    5380             :                                          bool &CanAcceptPredicationCode) {
    5381       24242 :   CanAcceptCarrySet =
    5382       96248 :       Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
    5383       71064 :       Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
    5384       66778 :       Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
    5385       64027 :       Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
    5386       62318 :       Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
    5387       61032 :       Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
    5388       79565 :       Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
    5389       19889 :       (!isThumb() &&
    5390       20331 :        (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
    5391       19899 :         Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
    5392             : 
    5393       72607 :   if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
    5394       69537 :       Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
    5395       63804 :       Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
    5396       42396 :       Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
    5397       42207 :       Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
    5398       62715 :       Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
    5399       61743 :       Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
    5400       60832 :       Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
    5401       60151 :       Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
    5402       39921 :       Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
    5403       19898 :       (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
    5404       39700 :       Mnemonic == "vmovx" || Mnemonic == "vins" ||
    5405       39628 :       Mnemonic == "vudot" || Mnemonic == "vsdot") {
    5406             :     // These mnemonics are never predicable
    5407        4518 :     CanAcceptPredicationCode = false;
    5408       19724 :   } else if (!isThumb()) {
    5409             :     // Some instructions are only predicable in Thumb mode
    5410        7677 :     CanAcceptPredicationCode =
    5411       22999 :         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
    5412       22928 :         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
    5413       22656 :         Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
    5414       22326 :         Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
    5415       22244 :         Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
    5416       14760 :         Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
    5417        7338 :         !Mnemonic.startswith("srs");
    5418       12047 :   } else if (isThumbOne()) {
    5419         933 :     if (hasV6MOps())
    5420         656 :       CanAcceptPredicationCode = Mnemonic != "movs";
    5421             :     else
    5422        1781 :       CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
    5423             :   } else
    5424       11114 :     CanAcceptPredicationCode = true;
    5425       24242 : }
    5426             : 
    5427             : // \brief Some Thumb instructions have two operand forms that are not
    5428             : // available as three operand, convert to two operand form if possible.
    5429             : //
    5430             : // FIXME: We would really like to be able to tablegen'erate this.
    5431       23922 : void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
    5432             :                                                  bool CarrySetting,
    5433             :                                                  OperandVector &Operands) {
    5434       47844 :   if (Operands.size() != 6)
    5435             :     return;
    5436             : 
    5437       23688 :   const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
    5438       23688 :         auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
    5439       21053 :   if (!Op3.isReg() || !Op4.isReg())
    5440             :     return;
    5441             : 
    5442        9980 :   auto Op3Reg = Op3.getReg();
    5443        9980 :   auto Op4Reg = Op4.getReg();
    5444             : 
    5445             :   // For most Thumb2 cases we just generate the 3 operand form and reduce
    5446             :   // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
    5447             :   // won't accept SP or PC so we do the transformation here taking care
    5448             :   // with immediate range in the 'add sp, sp #imm' case.
    5449       14970 :   auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
    5450        4990 :   if (isThumbTwo()) {
    5451        2765 :     if (Mnemonic != "add")
    5452             :       return;
    5453         695 :     bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
    5454         850 :                         (Op5.isReg() && Op5.getReg() == ARM::PC);
    5455             :     if (!TryTransform) {
    5456         625 :       TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
    5457         531 :                       (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
    5458          81 :                      !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
    5459          20 :                        Op5.isImm() && !Op5.isImm0_508s4());
    5460             :     }
    5461         351 :     if (!TryTransform)
    5462             :       return;
    5463        2576 :   } else if (!isThumbOne())
    5464             :     return;
    5465             : 
    5466         525 :   if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
    5467         185 :         Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
    5468         132 :         Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
    5469         112 :         Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
    5470             :     return;
    5471             : 
    5472             :   // If first 2 operands of a 3 operand instruction are the same
    5473             :   // then transform to 2 operand version of the same instruction
    5474             :   // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
    5475         344 :   bool Transform = Op3Reg == Op4Reg;
    5476             : 
    5477             :   // For communtative operations, we might be able to transform if we swap
    5478             :   // Op4 and Op5.  The 'ADD Rdm, SP, Rdm' form is already handled specially
    5479             :   // as tADDrsp.
    5480         344 :   const ARMOperand *LastOp = &Op5;
    5481         344 :   bool Swap = false;
    5482         466 :   if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
    5483          34 :       ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
    5484          29 :        Mnemonic == "and" || Mnemonic == "eor" ||
    5485          25 :        Mnemonic == "adc" || Mnemonic == "orr")) {
    5486             :     Swap = true;
    5487             :     LastOp = &Op4;
    5488             :     Transform = true;
    5489             :   }
    5490             : 
    5491             :   // If both registers are the same then remove one of them from
    5492             :   // the operand list, with certain exceptions.
    5493         344 :   if (Transform) {
    5494             :     // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
    5495             :     // 2 operand forms don't exist.
    5496         715 :     if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
    5497         424 :         LastOp->isReg())
    5498             :       Transform = false;
    5499             : 
    5500             :     // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
    5501             :     // 3-bits because the ARMARM says not to.
    5502         510 :     if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
    5503             :       Transform = false;
    5504             :   }
    5505             : 
    5506         137 :   if (Transform) {
    5507          52 :     if (Swap)
    5508           8 :       std::swap(Op4, Op5);
    5509         104 :     Operands.erase(Operands.begin() + 3);
    5510             :   }
    5511             : }
    5512             : 
    5513       22450 : bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
    5514             :                                           OperandVector &Operands) {
    5515             :   // FIXME: This is all horribly hacky. We really need a better way to deal
    5516             :   // with optional operands like this in the matcher table.
    5517             : 
    5518             :   // The 'mov' mnemonic is special. One variant has a cc_out operand, while
    5519             :   // another does not. Specifically, the MOVW instruction does not. So we
    5520             :   // special case it here and remove the defaulted (non-setting) cc_out
    5521             :   // operand if that's the instruction we're trying to match.
    5522             :   //
    5523             :   // We do this as post-processing of the explicit operands rather than just
    5524             :   // conditionally adding the cc_out in the first place because we need
    5525             :   // to check the type of the parsed immediate operand.
    5526       23338 :   if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
    5527         429 :       !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
    5528         269 :       static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
    5529          44 :       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
    5530             :     return true;
    5531             : 
    5532             :   // Register-register 'add' for thumb does not have a cc_out operand
    5533             :   // when there are only two register operands.
    5534       37919 :   if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
    5535         785 :       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5536       23144 :       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
    5537         308 :       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
    5538             :     return true;
    5539             :   // Register-register 'add' for thumb does not have a cc_out operand
    5540             :   // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
    5541             :   // have to check the immediate range here since Thumb2 has a variant
    5542             :   // that can handle a different range and has a cc_out operand.
    5543       58892 :   if (((isThumb() && Mnemonic == "add") ||
    5544       35977 :        (isThumbTwo() && Mnemonic == "sub")) &&
    5545        1977 :       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5546        1105 :       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
    5547         956 :       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
    5548       22650 :       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
    5549         304 :       ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
    5550         159 :        static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
    5551             :     return true;
    5552             :   // For Thumb2, add/sub immediate does not have a cc_out operand for the
    5553             :   // imm0_4095 variant. That's the least-preferred variant when
    5554             :   // selecting via the generic "add" mnemonic, so to know that we
    5555             :   // should remove the cc_out operand, we have to explicitly check that
    5556             :   // it's not one of the other variants. Ugh.
    5557       49904 :   if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
    5558        1591 :       Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5559       23159 :       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
    5560         676 :       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
    5561             :     // Nest conditions rather than one big 'if' statement for readability.
    5562             :     //
    5563             :     // If both registers are low, we're in an IT block, and the immediate is
    5564             :     // in range, we should use encoding T1 instead, which has a cc_out.
    5565         107 :     if (inITBlock() &&
    5566         316 :         isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
    5567         459 :         isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
    5568         224 :         static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
    5569             :       return false;
    5570             :     // Check against T3. If the second register is the PC, this is an
    5571             :     // alternate form of ADR, which uses encoding T4, so check for that too.
    5572         280 :     if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
    5573         168 :         static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
    5574             :       return false;
    5575             : 
    5576             :     // Otherwise, we use encoding T4, which does not have a cc_out
    5577             :     // operand.
    5578             :     return true;
    5579             :   }
    5580             : 
    5581             :   // The thumb2 multiply instruction doesn't have a CCOut register, so
    5582             :   // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
    5583             :   // use the 16-bit encoding or not.
    5584       35870 :   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
    5585          50 :       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
    5586          50 :       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5587          50 :       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
    5588       22247 :       static_cast<ARMOperand &>(*Operands[5]).isReg() &&
    5589             :       // If the registers aren't low regs, the destination reg isn't the
    5590             :       // same as one of the source regs, or the cc_out operand is zero
    5591             :       // outside of an IT block, we have to use the 32-bit encoding, so
    5592             :       // remove the cc_out operand.
    5593          50 :       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
    5594          50 :        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
    5595          56 :        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
    5596          24 :        !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
    5597          15 :                             static_cast<ARMOperand &>(*Operands[5]).getReg() &&
    5598           9 :                         static_cast<ARMOperand &>(*Operands[3]).getReg() !=
    5599           9 :                             static_cast<ARMOperand &>(*Operands[4]).getReg())))
    5600             :     return true;
    5601             : 
    5602             :   // Also check the 'mul' syntax variant that doesn't specify an explicit
    5603             :   // destination register.
    5604       35826 :   if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
    5605          10 :       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
    5606          10 :       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5607       22206 :       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
    5608             :       // If the registers aren't low regs  or the cc_out operand is zero
    5609             :       // outside of an IT block, we have to use the 32-bit encoding, so
    5610             :       // remove the cc_out operand.
    5611          10 :       (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
    5612          12 :        !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
    5613           2 :        !inITBlock()))
    5614             :     return true;
    5615             : 
    5616             : 
    5617             : 
    5618             :   // Register-register 'add/sub' for thumb does not have a cc_out operand
    5619             :   // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
    5620             :   // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
    5621             :   // right, this will result in better diagnostics (which operand is off)
    5622             :   // anyway.
    5623       50916 :   if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
    5624        1089 :       (Operands.size() == 5 || Operands.size() == 6) &&
    5625         833 :       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5626         704 :       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
    5627       22416 :       static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
    5628         180 :       (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
    5629          10 :        (Operands.size() == 6 &&
    5630           8 :         static_cast<ARMOperand &>(*Operands[5]).isImm())))
    5631             :     return true;
    5632             : 
    5633             :   return false;
    5634             : }
    5635             : 
    5636       23922 : bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
    5637             :                                               OperandVector &Operands) {
    5638             :   // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
    5639       23922 :   unsigned RegIdx = 3;
    5640       71480 :   if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
    5641         798 :       (static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32" ||
    5642         435 :        static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f16")) {
    5643         628 :     if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
    5644         240 :         (static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32" ||
    5645          72 :          static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f16"))
    5646             :       RegIdx = 4;
    5647             : 
    5648         647 :     if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
    5649         176 :         (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
    5650         491 :              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
    5651         158 :          ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
    5652         414 :              static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
    5653             :       return true;
    5654             :   }
    5655             :   return false;
    5656             : }
    5657             : 
    5658       10009 : static bool isDataTypeToken(StringRef Tok) {
    5659       34230 :   return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
    5660       26635 :     Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
    5661       24028 :     Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
    5662       19560 :     Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
    5663       15559 :     Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
    5664       14641 :     Tok == ".f" || Tok == ".d";
    5665             : }
    5666             : 
    5667             : // FIXME: This bit should probably be handled via an explicit match class
    5668             : // in the .td files that matches the suffix instead of having it be
    5669             : // a literal string token the way it is now.
    5670        7701 : static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
    5671       23103 :   return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
    5672             : }
    5673             : static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
    5674             :                                  unsigned VariantID);
    5675             : 
    5676       24257 : static bool RequiresVFPRegListValidation(StringRef Inst,
    5677             :                                          bool &AcceptSinglePrecisionOnly,
    5678             :                                          bool &AcceptDoublePrecisionOnly) {
    5679       24257 :   if (Inst.size() < 7)
    5680             :     return false;
    5681             : 
    5682       16503 :   if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
    5683          55 :     StringRef AddressingMode = Inst.substr(4, 2);
    5684          90 :     if (AddressingMode == "ia" || AddressingMode == "db" ||
    5685          38 :         AddressingMode == "ea" || AddressingMode == "fd") {
    5686         110 :       AcceptSinglePrecisionOnly = Inst[6] == 's';
    5687         110 :       AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
    5688          55 :       return true;
    5689             :     }
    5690             :   }
    5691             : 
    5692             :   return false;
    5693             : }
    5694             : 
    5695             : /// Parse an arm instruction mnemonic followed by its operands.
    5696       24257 : bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
    5697             :                                     SMLoc NameLoc, OperandVector &Operands) {
    5698       24257 :   MCAsmParser &Parser = getParser();
    5699             :   // FIXME: Can this be done via tablegen in some fashion?
    5700             :   bool RequireVFPRegisterListCheck;
    5701             :   bool AcceptSinglePrecisionOnly;
    5702             :   bool AcceptDoublePrecisionOnly;
    5703       24257 :   RequireVFPRegisterListCheck =
    5704             :     RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
    5705             :                                  AcceptDoublePrecisionOnly);
    5706             : 
    5707             :   // Apply mnemonic aliases before doing anything else, as the destination
    5708             :   // mnemonic may include suffices and we want to handle them normally.
    5709             :   // The generic tblgen'erated code does this later, at the start of
    5710             :   // MatchInstructionImpl(), but that's too late for aliases that include
    5711             :   // any sort of suffix.
    5712       24257 :   uint64_t AvailableFeatures = getAvailableFeatures();
    5713       24257 :   unsigned AssemblerDialect = getParser().getAssemblerDialect();
    5714       24257 :   applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
    5715             : 
    5716             :   // First check for the ARM-specific .req directive.
    5717       24257 :   if (Parser.getTok().is(AsmToken::Identifier) &&
    5718       39989 :       Parser.getTok().getIdentifier() == ".req") {
    5719           7 :     parseDirectiveReq(Name, NameLoc);
    5720             :     // We always return 'error' for this, as we're done with this
    5721             :     // statement and don't need to match the 'instruction."
    5722           7 :     return true;
    5723             :   }
    5724             : 
    5725             :   // Create the leading tokens for the mnemonic, split by '.' characters.
    5726       48500 :   size_t Start = 0, Next = Name.find('.');
    5727       24250 :   StringRef Mnemonic = Name.slice(Start, Next);
    5728             : 
    5729             :   // Split out the predication code and carry setting flag from the mnemonic.
    5730             :   unsigned PredicationCode;
    5731             :   unsigned ProcessorIMod;
    5732             :   bool CarrySetting;
    5733       24250 :   StringRef ITMask;
    5734       24250 :   Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
    5735             :                            ProcessorIMod, ITMask);
    5736             : 
    5737             :   // In Thumb1, only the branch (B) instruction can be predicated.
    5738       24250 :   if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
    5739          12 :     return Error(NameLoc, "conditional execution not supported in Thumb1");
    5740             :   }
    5741             : 
    5742       72738 :   Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
    5743             : 
    5744             :   // Handle the IT instruction ITMask. Convert it to a bitmask. This
    5745             :   // is the mask as it will be for the IT encoding if the conditional
    5746             :   // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
    5747             :   // where the conditional bit0 is zero, the instruction post-processing
    5748             :   // will adjust the mask accordingly.
    5749       27018 :   if (Mnemonic == "it") {
    5750        5544 :     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
    5751        2772 :     if (ITMask.size() > 3) {
    5752           6 :       return Error(Loc, "too many conditions on IT instruction");
    5753             :     }
    5754        2770 :     unsigned Mask = 8;
    5755        2770 :     for (unsigned i = ITMask.size(); i != 0; --i) {
    5756         574 :       char pos = ITMask[i - 1];
    5757         287 :       if (pos != 't' && pos != 'e') {
    5758          10 :         return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
    5759             :       }
    5760         285 :       Mask >>= 1;
    5761         285 :       if (ITMask[i - 1] == 't')
    5762         141 :         Mask |= 8;
    5763             :     }
    5764       11072 :     Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
    5765             :   }
    5766             : 
    5767             :   // FIXME: This is all a pretty gross hack. We should automatically handle
    5768             :   // optional operands like this via tblgen.
    5769             : 
    5770             :   // Next, add the CCOut and ConditionCode operands, if needed.
    5771             :   //
    5772             :   // For mnemonics which can ever incorporate a carry setting bit or predication
    5773             :   // code, our matching model involves us always generating CCOut and
    5774             :   // ConditionCode operands to match the mnemonic "as written" and then we let
    5775             :   // the matcher deal with finding the right instruction or generating an
    5776             :   // appropriate error.
    5777             :   bool CanAcceptCarrySet, CanAcceptPredicationCode;
    5778       24242 :   getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
    5779             : 
    5780             :   // If we had a carry-set on an instruction that can't do that, issue an
    5781             :   // error.
    5782       24242 :   if (!CanAcceptCarrySet && CarrySetting) {
    5783          16 :     return Error(NameLoc, "instruction '" + Mnemonic +
    5784          12 :                  "' can not set flags, but 's' suffix specified");
    5785             :   }
    5786             :   // If we had a predication code on an instruction that can't do that, issue an
    5787             :   // error.
    5788       24238 :   if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
    5789         304 :     return Error(NameLoc, "instruction '" + Mnemonic +
    5790         228 :                  "' is not predicable, but condition code specified");
    5791             :   }
    5792             : 
    5793             :   // Add the carry setting operand, if necessary.
    5794       24162 :   if (CanAcceptCarrySet) {
    5795       13752 :     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
    5796       18336 :     Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
    5797             :                                                Loc));
    5798             :   }
    5799             : 
    5800             :   // Add the predication code operand, if necessary.
    5801       24162 :   if (CanAcceptPredicationCode) {
    5802       38492 :     SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
    5803       38492 :                                       CarrySetting);
    5804       76984 :     Operands.push_back(ARMOperand::CreateCondCode(
    5805             :                          ARMCC::CondCodes(PredicationCode), Loc));
    5806             :   }
    5807             : 
    5808             :   // Add the processor imod operand, if necessary.
    5809       24162 :   if (ProcessorIMod) {
    5810         120 :     Operands.push_back(ARMOperand::CreateImm(
    5811          80 :           MCConstantExpr::create(ProcessorIMod, getContext()),
    5812             :                                  NameLoc, NameLoc));
    5813       24148 :   } else if (Mnemonic == "cps" && isMClass()) {
    5814           3 :     return Error(NameLoc, "instruction 'cps' requires effect for M-class");
    5815             :   }
    5816             : 
    5817             :   // Add the remaining tokens in the mnemonic.
    5818       34167 :   while (Next != StringRef::npos) {
    5819       10009 :     Start = Next;
    5820       20018 :     Next = Name.find('.', Start + 1);
    5821       10009 :     StringRef ExtraToken = Name.slice(Start, Next);
    5822             : 
    5823             :     // Some NEON instructions have an optional datatype suffix that is
    5824             :     // completely ignored. Check for that.
    5825       17710 :     if (isDataTypeToken(ExtraToken) &&
    5826        7701 :         doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
    5827           0 :       continue;
    5828             : 
    5829             :     // For for ARM mode generate an error if the .n qualifier is used.
    5830       10069 :     if (ExtraToken == ".n" && !isThumb()) {
    5831           6 :       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
    5832           9 :       return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
    5833           3 :                    "arm mode");
    5834             :     }
    5835             : 
    5836             :     // The .n qualifier is always discarded as that is what the tables
    5837             :     // and matcher expect.  In ARM mode the .w qualifier has no effect,
    5838             :     // so discard it to avoid errors that can be caused by the matcher.
    5839       19985 :     if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
    5840       19938 :       SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
    5841       29907 :       Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
    5842             :     }
    5843             :   }
    5844             : 
    5845             :   // Read the remaining operands.
    5846       72474 :   if (getLexer().isNot(AsmToken::EndOfStatement)) {
    5847             :     // Read the first operand.
    5848       23768 :     if (parseOperand(Operands, Mnemonic)) {
    5849             :       return true;
    5850             :     }
    5851             : 
    5852      109346 :     while (parseOptionalToken(AsmToken::Comma)) {
    5853             :       // Parse and remember the operand.
    5854       31101 :       if (parseOperand(Operands, Mnemonic)) {
    5855             :         return true;
    5856             :       }
    5857             :     }
    5858             :   }
    5859             : 
    5860       71886 :   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
    5861             :     return true;
    5862             : 
    5863       23946 :   if (RequireVFPRegisterListCheck) {
    5864         165 :     ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
    5865          55 :     if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
    5866          32 :       return Error(Op.getStartLoc(),
    5867           8 :                    "VFP/Neon single precision register expected");
    5868          86 :     if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
    5869          64 :       return Error(Op.getStartLoc(),
    5870          16 :                    "VFP/Neon double precision register expected");
    5871             :   }
    5872             : 
    5873       23922 :   tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
    5874             : 
    5875             :   // Some instructions, mostly Thumb, have forms for the same mnemonic that
    5876             :   // do and don't have a cc_out optional-def operand. With some spot-checks
    5877             :   // of the operand list, we can figure out which variant we're trying to
    5878             :   // parse and adjust accordingly before actually matching. We shouldn't ever
    5879             :   // try to remove a cc_out operand that was explicitly set on the
    5880             :   // mnemonic, of course (CarrySetting == true). Reason number #317 the
    5881             :   // table driven matcher doesn't fit well with the ARM instruction set.
    5882       23922 :   if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
    5883         406 :     Operands.erase(Operands.begin() + 1);
    5884             : 
    5885             :   // Some instructions have the same mnemonic, but don't always
    5886             :   // have a predicate. Distinguish them here and delete the
    5887             :   // predicate if needed.
    5888       23922 :   if (shouldOmitPredicateOperand(Mnemonic, Operands))
    5889          78 :     Operands.erase(Operands.begin() + 1);
    5890             : 
    5891             :   // ARM mode 'blx' need special handling, as the register operand version
    5892             :   // is predicable, but the label operand version is not. So, we can't rely
    5893             :   // on the Mnemonic based checking to correctly figure out when to put
    5894             :   // a k_CondCode operand in the list. If we're trying to match the label
    5895             :   // version, remove the k_CondCode operand here.
    5896       24003 :   if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
    5897         108 :       static_cast<ARMOperand &>(*Operands[2]).isImm())
    5898          21 :     Operands.erase(Operands.begin() + 1);
    5899             : 
    5900             :   // Adjust operands of ldrexd/strexd to MCK_GPRPair.
    5901             :   // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
    5902             :   // a single GPRPair reg operand is used in the .td file to replace the two
    5903             :   // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
    5904             :   // expressed as a GPRPair, so we have to manually merge them.
    5905             :   // FIXME: We would really like to be able to tablegen'erate this.
    5906       32232 :   if (!isThumb() && Operands.size() > 4 &&
    5907       18224 :       (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
    5908        6064 :        Mnemonic == "stlexd")) {
    5909          34 :     bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
    5910          26 :     unsigned Idx = isLoad ? 2 : 3;
    5911          78 :     ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
    5912          78 :     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
    5913             : 
    5914          26 :     const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
    5915             :     // Adjust only if Op1 and Op2 are GPRs.
    5916         156 :     if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
    5917          78 :         MRC.contains(Op2.getReg())) {
    5918          26 :       unsigned Reg1 = Op1.getReg();
    5919          26 :       unsigned Reg2 = Op2.getReg();
    5920          52 :       unsigned Rt = MRI->getEncodingValue(Reg1);
    5921          52 :       unsigned Rt2 = MRI->getEncodingValue(Reg2);
    5922             : 
    5923             :       // Rt2 must be Rt + 1 and Rt must be even.
    5924          26 :       if (Rt + 1 != Rt2 || (Rt & 1)) {
    5925          16 :         return Error(Op2.getStartLoc(),
    5926             :                      isLoad ? "destination operands must be sequential"
    5927           4 :                             : "source operands must be sequential");
    5928             :       }
    5929             :       unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
    5930          44 :           &(MRI->getRegClass(ARM::GPRPairRegClassID)));
    5931          66 :       Operands[Idx] =
    5932         110 :           ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
    5933          44 :       Operands.erase(Operands.begin() + Idx + 1);
    5934             :     }
    5935             :   }
    5936             : 
    5937             :   // GNU Assembler extension (compatibility)
    5938       47760 :   if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
    5939         663 :     ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
    5940         663 :     ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
    5941         442 :     if (Op3.isMem()) {
    5942             :       assert(Op2.isReg() && "expected register argument");
    5943             : 
    5944          40 :       unsigned SuperReg = MRI->getMatchingSuperReg(
    5945          60 :           Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
    5946             : 
    5947             :       assert(SuperReg && "expected register pair");
    5948             : 
    5949          20 :       unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
    5950             : 
    5951          60 :       Operands.insert(
    5952          40 :           Operands.begin() + 3,
    5953         100 :           ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
    5954             :     }
    5955             :   }
    5956             : 
    5957             :   // FIXME: As said above, this is all a pretty gross hack.  This instruction
    5958             :   // does not fit with other "subs" and tblgen.
    5959             :   // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
    5960             :   // so the Mnemonic is the original name "subs" and delete the predicate
    5961             :   // operand so it will match the table entry.
    5962       38975 :   if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
    5963         288 :       static_cast<ARMOperand &>(*Operands[3]).isReg() &&
    5964         228 :       static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
    5965          20 :       static_cast<ARMOperand &>(*Operands[4]).isReg() &&
    5966       23938 :       static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
    5967          16 :       static_cast<ARMOperand &>(*Operands[5]).isImm()) {
    5968          12 :     Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
    5969           8 :     Operands.erase(Operands.begin() + 1);
    5970             :   }
    5971             :   return false;
    5972             : }
    5973             : 
    5974             : // Validate context-sensitive operand constraints.
    5975             : 
    5976             : // return 'true' if register list contains non-low GPR registers,
    5977             : // 'false' otherwise. If Reg is in the register list or is HiReg, set
    5978             : // 'containsReg' to true.
    5979             : static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
    5980             :                                  unsigned Reg, unsigned HiReg,
    5981             :                                  bool &containsReg) {
    5982         171 :   containsReg = false;
    5983        1663 :   for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
    5984         757 :     unsigned OpReg = Inst.getOperand(i).getReg();
    5985         424 :     if (OpReg == Reg)
    5986          35 :       containsReg = true;
    5987             :     // Anything other than a low register isn't legal here.
    5988         208 :     if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
    5989             :       return true;
    5990             :   }
    5991             :   return false;
    5992             : }
    5993             : 
    5994             : // Check if the specified regisgter is in the register list of the inst,
    5995             : // starting at the indicated operand number.
    5996             : static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
    5997        3920 :   for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
    5998        2361 :     unsigned OpReg = Inst.getOperand(i).getReg();
    5999        2361 :     if (OpReg == Reg)
    6000             :       return true;
    6001             :   }
    6002             :   return false;
    6003             : }
    6004             : 
    6005             : // Return true if instruction has the interesting property of being
    6006             : // allowed in IT blocks, but not being predicable.
    6007             : static bool instIsBreakpoint(const MCInst &Inst) {
    6008        6238 :     return Inst.getOpcode() == ARM::tBKPT ||
    6009        6236 :            Inst.getOpcode() == ARM::BKPT ||
    6010        9355 :            Inst.getOpcode() == ARM::tHLT ||
    6011        3117 :            Inst.getOpcode() == ARM::HLT;
    6012             : 
    6013             : }
    6014             : 
    6015         146 : bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
    6016             :                                        const OperandVector &Operands,
    6017             :                                        unsigned ListNo, bool IsARPop) {
    6018         438 :   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
    6019         438 :   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
    6020             : 
    6021         146 :   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
    6022         146 :   bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
    6023         146 :   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
    6024             : 
    6025         146 :   if (!IsARPop && ListContainsSP)
    6026         115 :     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
    6027          23 :                  "SP may not be in the register list");
    6028         123 :   else if (ListContainsPC && ListContainsLR)
    6029          45 :     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
    6030           9 :                  "PC and LR may not be in the register list simultaneously");
    6031             :   return false;
    6032             : }
    6033             : 
    6034         128 : bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
    6035             :                                        const OperandVector &Operands,
    6036             :                                        unsigned ListNo) {
    6037         384 :   const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
    6038         384 :   bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
    6039             : 
    6040         128 :   bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
    6041         128 :   bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
    6042             : 
    6043         128 :   if (ListContainsSP && ListContainsPC)
    6044          45 :     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
    6045           9 :                  "SP and PC may not be in the register list");
    6046         119 :   else if (ListContainsSP)
    6047          85 :     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
    6048          17 :                  "SP may not be in the register list");
    6049         102 :   else if (ListContainsPC)
    6050          45 :     return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
    6051           9 :                  "PC may not be in the register list");
    6052             :   return false;
    6053             : }
    6054             : 
    6055             : // FIXME: We would really like to be able to tablegen'erate this.
    6056       20090 : bool ARMAsmParser::validateInstruction(MCInst &Inst,
    6057             :                                        const OperandVector &Operands) {
    6058       40180 :   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
    6059       60270 :   SMLoc Loc = Operands[0]->getStartLoc();
    6060             : 
    6061             :   // Check the IT block state first.
    6062             :   // NOTE: BKPT and HLT instructions have the interesting property of being
    6063             :   // allowed in IT blocks, but not being predicable. They just always execute.
    6064       23207 :   if (inITBlock() && !instIsBreakpoint(Inst)) {
    6065             :     // The instruction must be predicable.
    6066        3117 :     if (!MCID.isPredicable())
    6067          21 :       return Error(Loc, "instructions in IT block must be predicable");
    6068        6220 :     unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
    6069        3110 :     if (Cond != currentITCond()) {
    6070             :       // Find the condition code Operand to get its SMLoc information.
    6071             :       SMLoc CondLoc;
    6072         384 :       for (unsigned I = 1; I < Operands.size(); ++I)
    6073         336 :         if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
    6074          72 :           CondLoc = Operands[I]->getStartLoc();
    6075          72 :       return Error(CondLoc, "incorrect condition in IT block; got '" +
    6076         120 :                    StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
    6077          96 :                    "', but expected '" +
    6078         120 :                    ARMCondCodeToString(ARMCC::CondCodes(currentITCond())) + "'");
    6079             :     }
    6080             :   // Check for non-'al' condition codes outside of the IT block.
    6081       31920 :   } else if (isThumbTwo() && MCID.isPredicable() &&
    6082       11868 :              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
    6083       17152 :              ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
    6084          68 :              Inst.getOpcode() != ARM::t2Bcc) {
    6085          15 :     return Error(Loc, "predicated instructions must be in IT block");
    6086       24129 :   } else if (!isThumb() && !useImplicitITARM() && MCID.isPredicable() &&
    6087           4 :              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
    6088             :                  ARMCC::AL) {
    6089           6 :     return Warning(Loc, "predicated instructions should be in IT block");
    6090             :   }
    6091             : 
    6092             :   // PC-setting instructions in an IT block, but not the last instruction of
    6093             :   // the block, are UNPREDICTABLE.
    6094        5994 :   if (inExplicitITBlock() && !lastInITBlock() && isITBlockTerminator(Inst)) {
    6095          84 :     return Error(Loc, "instruction must be outside of IT block or the last instruction in an IT block");
    6096             :   }
    6097             : 
    6098       20024 :   const unsigned Opcode = Inst.getOpcode();
    6099       20024 :   switch (Opcode) {
    6100          49 :   case ARM::LDRD:
    6101             :   case ARM::LDRD_PRE:
    6102             :   case ARM::LDRD_POST: {
    6103          49 :     const unsigned RtReg = Inst.getOperand(0).getReg();
    6104             : 
    6105             :     // Rt can't be R14.
    6106          49 :     if (RtReg == ARM::LR)
    6107          35 :       return Error(Operands[3]->getStartLoc(),
    6108           7 :                    "Rt can't be R14");
    6109             : 
    6110          84 :     const unsigned Rt = MRI->getEncodingValue(RtReg);
    6111             :     // Rt must be even-numbered.
    6112          42 :     if ((Rt & 1) == 1)
    6113          35 :       return Error(Operands[3]->getStartLoc(),
    6114           7 :                    "Rt must be even-numbered");
    6115             : 
    6116             :     // Rt2 must be Rt + 1.
    6117         105 :     const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
    6118          35 :     if (Rt2 != Rt + 1)
    6119          65 :       return Error(Operands[3]->getStartLoc(),
    6120          13 :                    "destination operands must be sequential");
    6121             : 
    6122          22 :     if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
    6123          42 :       const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
    6124             :       // For addressing modes with writeback, the base register needs to be
    6125             :       // different from the destination registers.
    6126          14 :       if (Rn == Rt || Rn == Rt2)
    6127          20 :         return Error(Operands[3]->getStartLoc(),
    6128             :                      "base register needs to be different from destination "
    6129           4 :                      "registers");
    6130             :     }
    6131             : 
    6132             :     return false;
    6133             :   }
    6134          25 :   case ARM::t2LDRDi8:
    6135             :   case ARM::t2LDRD_PRE:
    6136             :   case ARM::t2LDRD_POST: {
    6137             :     // Rt2 must be different from Rt.
    6138          75 :     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
    6139          75 :     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
    6140          25 :     if (Rt2 == Rt)
    6141          20 :       return Error(Operands[3]->getStartLoc(),
    6142           4 :                    "destination operands can't be identical");
    6143             :     return false;
    6144             :   }
    6145          13 :   case ARM::t2BXJ: {
    6146          13 :     const unsigned RmReg = Inst.getOperand(0).getReg();
    6147             :     // Rm = SP is no longer unpredictable in v8-A
    6148          17 :     if (RmReg == ARM::SP && !hasV8Ops())
    6149          15 :       return Error(Operands[2]->getStartLoc(),
    6150           3 :                    "r13 (SP) is an unpredictable operand to BXJ");
    6151             :     return false;
    6152             :   }
    6153           7 :   case ARM::STRD: {
    6154             :     // Rt2 must be Rt + 1.
    6155          21 :     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
    6156          21 :     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
    6157           7 :     if (Rt2 != Rt + 1)
    6158           0 :       return Error(Operands[3]->getStartLoc(),
    6159           0 :                    "source operands must be sequential");
    6160             :     return false;
    6161             :   }
    6162          10 :   case ARM::STRD_PRE:
    6163             :   case ARM::STRD_POST: {
    6164             :     // Rt2 must be Rt + 1.
    6165          30 :     unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
    6166          30 :     unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
    6167          10 :     if (Rt2 != Rt + 1)
    6168           0 :       return Error(Operands[3]->getStartLoc(),
    6169           0 :                    "source operands must be sequential");
    6170             :     return false;
    6171             :   }
    6172          54 :   case ARM::STR_PRE_IMM:
    6173             :   case ARM::STR_PRE_REG:
    6174             :   case ARM::STR_POST_IMM:
    6175             :   case ARM::STR_POST_REG:
    6176             :   case ARM::STRH_PRE:
    6177             :   case ARM::STRH_POST:
    6178             :   case ARM::STRB_PRE_IMM:
    6179             :   case ARM::STRB_PRE_REG:
    6180             :   case ARM::STRB_POST_IMM:
    6181             :   case ARM::STRB_POST_REG: {
    6182             :     // Rt must be different from Rn.
    6183         162 :     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
    6184         162 :     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
    6185             : 
    6186          54 :     if (Rt == Rn)
    6187         120 :       return Error(Operands[3]->getStartLoc(),
    6188          24 :                    "source register and base register can't be identical");
    6189             :     return false;
    6190             :   }
    6191          81 :   case ARM::LDR_PRE_IMM:
    6192             :   case ARM::LDR_PRE_REG:
    6193             :   case ARM::LDR_POST_IMM:
    6194             :   case ARM::LDR_POST_REG:
    6195             :   case ARM::LDRH_PRE:
    6196             :   case ARM::LDRH_POST:
    6197             :   case ARM::LDRSH_PRE:
    6198             :   case ARM::LDRSH_POST:
    6199             :   case ARM::LDRB_PRE_IMM:
    6200             :   case ARM::LDRB_PRE_REG:
    6201             :   case ARM::LDRB_POST_IMM:
    6202             :   case ARM::LDRB_POST_REG:
    6203             :   case ARM::LDRSB_PRE:
    6204             :   case ARM::LDRSB_POST: {
    6205             :     // Rt must be different from Rn.
    6206         243 :     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
    6207         243 :     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
    6208             : 
    6209          81 :     if (Rt == Rn)
    6210         200 :       return Error(Operands[3]->getStartLoc(),
    6211          40 :                    "destination register and base register can't be identical");
    6212             :     return false;
    6213             :   }
    6214          12 :   case ARM::SBFX:
    6215             :   case ARM::UBFX: {
    6216             :     // Width must be in range [1, 32-lsb].
    6217          12 :     unsigned LSB = Inst.getOperand(2).getImm();
    6218          12 :     unsigned Widthm1 = Inst.getOperand(3).getImm();
    6219          12 :     if (Widthm1 >= 32 - LSB)
    6220          20 :       return Error(Operands[5]->getStartLoc(),
    6221           4 :                    "bitfield width must be in range [1,32-lsb]");
    6222             :     return false;
    6223             :   }
    6224             :   // Notionally handles ARM::tLDMIA_UPD too.
    6225          75 :   case ARM::tLDMIA: {
    6226             :     // If we're parsing Thumb2, the .w variant is available and handles
    6227             :     // most cases that are normally illegal for a Thumb1 LDM instruction.
    6228             :     // We'll make the transformation in processInstruction() if necessary.
    6229             :     //
    6230             :     // Thumb LDM instructions are writeback iff the base register is not
    6231             :     // in the register list.
    6232          75 :     unsigned Rn = Inst.getOperand(0).getReg();
    6233             :     bool HasWritebackToken =
    6234         300 :         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
    6235         204 :          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
    6236             :     bool ListContainsBase;
    6237          52 :     if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
    6238          70 :       return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
    6239          14 :                    "registers must be in range r0-r7");
    6240             :     // If we should have writeback, then there should be a '!' token.
    6241         106 :     if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
    6242          10 :       return Error(Operands[2]->getStartLoc(),
    6243           2 :                    "writeback operator '!' expected");
    6244             :     // If we should not have writeback, there must not be a '!'. This is
    6245             :     // true even for the 32-bit wide encodings.
    6246          75 :     if (ListContainsBase && HasWritebackToken)
    6247          30 :       return Error(Operands[3]->getStartLoc(),
    6248             :                    "writeback operator '!' not allowed when base register "
    6249           6 :                    "in register list");
    6250             : 
    6251          53 :     if (validatetLDMRegList(Inst, Operands, 3))
    6252             :       return true;
    6253             :     break;
    6254             :   }
    6255         104 :   case ARM::LDMIA_UPD:
    6256             :   case ARM::LDMDB_UPD:
    6257             :   case ARM::LDMIB_UPD:
    6258             :   case ARM::LDMDA_UPD:
    6259             :     // ARM variants loading and updating the same register are only officially
    6260             :     // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
    6261         104 :     if (!hasV7Ops())
    6262             :       break;
    6263         164 :     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
    6264          50 :       return Error(Operands.back()->getStartLoc(),
    6265          10 :                    "writeback register not allowed in register list");
    6266             :     break;
    6267          20 :   case ARM::t2LDMIA:
    6268             :   case ARM::t2LDMDB:
    6269          20 :     if (validatetLDMRegList(Inst, Operands, 3))
    6270             :       return true;
    6271             :     break;
    6272          30 :   case ARM::t2STMIA:
    6273             :   case ARM::t2STMDB:
    6274          30 :     if (validatetSTMRegList(Inst, Operands, 3))
    6275             :       return true;
    6276             :     break;
    6277          59 :   case ARM::t2LDMIA_UPD:
    6278             :   case ARM::t2LDMDB_UPD:
    6279             :   case ARM::t2STMIA_UPD:
    6280             :   case ARM::t2STMDB_UPD: {
    6281         118 :     if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
    6282          20 :       return Error(Operands.back()->getStartLoc(),
    6283           4 :                    "writeback register not allowed in register list");
    6284             : 
    6285          55 :     if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
    6286          29 :       if (validatetLDMRegList(Inst, Operands, 3))
    6287             :         return true;
    6288             :     } else {
    6289          26 :       if (validatetSTMRegList(Inst, Operands, 3))
    6290             :         return true;
    6291             :     }
    6292             :     break;
    6293             :   }
    6294           4 :   case ARM::sysLDMIA_UPD:
    6295             :   case ARM::sysLDMDA_UPD:
    6296             :   case ARM::sysLDMDB_UPD:
    6297             :   case ARM::sysLDMIB_UPD:
    6298           4 :     if (!listContainsReg(Inst, 3, ARM::PC))
    6299          10 :       return Error(Operands[4]->getStartLoc(),
    6300             :                    "writeback register only allowed on system LDM "
    6301           2 :                    "if PC in register-list");
    6302             :     break;
    6303           2 :   case ARM::sysSTMIA_UPD:
    6304             :   case ARM::sysSTMDA_UPD:
    6305             :   case ARM::sysSTMDB_UPD:
    6306             :   case ARM::sysSTMIB_UPD:
    6307          10 :     return Error(Operands[2]->getStartLoc(),
    6308           2 :                  "system STM cannot have writeback register");
    6309          16 :   case ARM::tMUL: {
    6310             :     // The second source operand must be the same register as the destination
    6311             :     // operand.
    6312             :     //
    6313             :     // In this case, we must directly check the parsed operands because the
    6314             :     // cvtThumbMultiply() function is written in such a way that it guarantees
    6315             :     // this first statement is always true for the new Inst.  Essentially, the
    6316             :     // destination is unconditionally copied into the second source operand
    6317             :     // without checking to see if it matches what we actually parsed.
    6318          97 :     if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
    6319          75 :                                  ((ARMOperand &)*Operands[5]).getReg()) &&
    6320          21 :         (((ARMOperand &)*Operands[3]).getReg() !=
    6321          28 :          ((ARMOperand &)*Operands[4]).getReg())) {
    6322          20 :       return Error(Operands[3]->getStartLoc(),
    6323           4 :                    "destination register must match source register");
    6324             :     }
    6325             :     break;
    6326             :   }
    6327             :   // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
    6328             :   // so only issue a diagnostic for thumb1. The instructions will be
    6329             :   // switched to the t2 encodings in processInstruction() if necessary.
    6330             :   case ARM::tPOP: {
    6331             :     bool ListContainsBase;
    6332          70 :     if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
    6333          24 :         !isThumbTwo())
    6334          10 :       return Error(Operands[2]->getStartLoc(),
    6335           2 :                    "registers must be in range r0-r7 or pc");
    6336          44 :     if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
    6337             :       return true;
    6338             :     break;
    6339             :   }
    6340             :   case ARM::tPUSH: {
    6341             :     bool ListContainsBase;
    6342          59 :     if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
    6343          16 :         !isThumbTwo())
    6344          10 :       return Error(Operands[2]->getStartLoc(),
    6345           2 :                    "registers must be in range r0-r7 or lr");
    6346          41 :     if (validatetSTMRegList(Inst, Operands, 2))
    6347             :       return true;
    6348             :     break;
    6349             :   }
    6350          41 :   case ARM::tSTMIA_UPD: {
    6351             :     bool ListContainsBase, InvalidLowList;
    6352          74 :     InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
    6353             :                                           0, ListContainsBase);
    6354          33 :     if (InvalidLowList && !isThumbTwo())
    6355          40 :       return Error(Operands[4]->getStartLoc(),
    6356           8 :                    "registers must be in range r0-r7");
    6357             : 
    6358             :     // This would be converted to a 32-bit stm, but that's not valid if the
    6359             :     // writeback register is in the list.
    6360          58 :     if (InvalidLowList && ListContainsBase)
    6361          10 :       return Error(Operands[4]->getStartLoc(),
    6362             :                    "writeback operator '!' not allowed when base register "
    6363           2 :                    "in register list");
    6364             : 
    6365          31 :     if (validatetSTMRegList(Inst, Operands, 4))
    6366             :       return true;
    6367             :     break;
    6368             :   }
    6369          18 :   case ARM::tADDrSP: {
    6370             :     // If the non-SP source operand and the destination operand are not the
    6371             :     // same, we need thumb2 (for the wide encoding), or we have an error.
    6372          22 :     if (!isThumbTwo() &&
    6373           8 :         Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
    6374          10 :       return Error(Operands[4]->getStartLoc(),
    6375           2 :                    "source register must be the same as destination");
    6376             :     }
    6377             :     break;
    6378             :   }
    6379             :   // Final range checking for Thumb unconditional branch instructions.
    6380          99 :   case ARM::tB:
    6381         297 :     if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
    6382          30 :       return Error(Operands[2]->getStartLoc(), "branch target out of range");
    6383             :     break;
    6384          85 :   case ARM::t2B: {
    6385         255 :     int op = (Operands[2]->isImm()) ? 2 : 3;
    6386         255 :     if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
    6387          45 :       return Error(Operands[op]->getStartLoc(), "branch target out of range");
    6388             :     break;
    6389             :   }
    6390             :   // Final range checking for Thumb conditional branch instructions.
    6391          56 :   case ARM::tBcc:
    6392         168 :     if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
    6393          30 :       return Error(Operands[2]->getStartLoc(), "branch target out of range");
    6394             :     break;
    6395          63 :   case ARM::t2Bcc: {
    6396         189 :     int Op = (Operands[2]->isImm()) ? 2 : 3;
    6397         189 :     if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
    6398          45 :       return Error(Operands[Op]->getStartLoc(), "branch target out of range");
    6399             :     break;
    6400             :   }
    6401          44 :   case ARM::tCBZ:
    6402             :   case ARM::tCBNZ: {
    6403         132 :     if (!static_cast<ARMOperand &>(*Operands[2]).isUnsignedOffset<6, 1>())
    6404          20 :       return Error(Operands[2]->getStartLoc(), "branch target out of range");
    6405             :     break;
    6406             :   }
    6407         303 :   case ARM::MOVi16:
    6408             :   case ARM::MOVTi16:
    6409             :   case ARM::t2MOVi16:
    6410             :   case ARM::t2MOVTi16:
    6411             :     {
    6412             :     // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
    6413             :     // especially when we turn it into a movw and the expression <symbol> does
    6414             :     // not have a :lower16: or :upper16 as part of the expression.  We don't
    6415             :     // want the behavior of silently truncating, which can be unexpected and
    6416             :     // lead to bugs that are difficult to find since this is an easy mistake
    6417             :     // to make.
    6418         909 :     int i = (Operands[3]->isImm()) ? 3 : 4;
    6419         909 :     ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
    6420         303 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
    6421             :     if (CE) break;
    6422         394 :     const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
    6423             :     if (!E) break;
    6424         187 :     const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
    6425         187 :     if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
    6426             :                        ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
    6427          40 :       return Error(
    6428          10 :           Op.getStartLoc(),
    6429          10 :           "immediate expression for mov requires :lower16: or :upper16");
    6430             :     break;
    6431             :   }
    6432         125 :   case ARM::HINT:
    6433             :   case ARM::t2HINT: {
    6434         125 :     if (hasRAS()) {
    6435             :       // ESB is not predicable (pred must be AL)
    6436           2 :       unsigned Imm8 = Inst.getOperand(0).getImm();
    6437           2 :       unsigned Pred = Inst.getOperand(1).getImm();
    6438           2 :       if (Imm8 == 0x10 && Pred != ARMCC::AL)
    6439           0 :         return Error(Operands[1]->getStartLoc(), "instruction 'esb' is not "
    6440             :                                                  "predicable, but condition "
    6441           0 :                                                  "code specified");
    6442             :     }
    6443             :     // Without the RAS extension, this behaves as any other unallocated hint.
    6444             :     break;
    6445             :   }
    6446             :   }
    6447             : 
    6448             :   return false;
    6449             : }
    6450             : 
    6451         322 : static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
    6452         322 :   switch(Opc) {
    6453           0 :   default: llvm_unreachable("unexpected opcode!");
    6454             :   // VST1LN
    6455           1 :   case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
    6456           2 :   case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
    6457           3 :   case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
    6458           1 :   case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
    6459           2 :   case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
    6460           3 :   case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
    6461           1 :   case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
    6462           2 :   case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
    6463           3 :   case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
    6464             : 
    6465             :   // VST2LN
    6466           3 :   case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
    6467           0 :   case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
    6468           2 :   case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
    6469           1 :   case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
    6470           3 :   case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
    6471             : 
    6472           3 :   case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
    6473           0 :   case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
    6474           2 :   case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
    6475           1 :   case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
    6476           3 :   case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
    6477             : 
    6478           5 :   case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
    6479           2 :   case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
    6480           4 :   case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
    6481           3 :   case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
    6482           5 :   case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
    6483             : 
    6484             :   // VST3LN
    6485           2 :   case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
    6486           2 :   case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
    6487           2 :   case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
    6488           2 :   case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
    6489           2 :   case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
    6490           2 :   case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
    6491           2 :   case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
    6492           2 :   case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
    6493           2 :   case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
    6494           2 :   case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
    6495           3 :   case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
    6496           3 :   case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
    6497           3 :   case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
    6498           3 :   case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
    6499           3 :   case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
    6500             : 
    6501             :   // VST3
    6502           3 :   case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
    6503           3 :   case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
    6504           3 :   case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
    6505           5 :   case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
    6506           5 :   case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
    6507           5 :   case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
    6508           3 :   case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
    6509           3 :   case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
    6510           3 :   case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
    6511           3 :   case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
    6512           3 :   case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
    6513           3 :   case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
    6514           4 :   case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
    6515           4 :   case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
    6516           4 :   case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
    6517           3 :   case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
    6518           3 :   case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
    6519           3 :   case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
    6520             : 
    6521             :   // VST4LN
    6522           3 :   case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
    6523           3 :   case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
    6524           7 :   case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
    6525           3 :   case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
    6526           7 :   case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
    6527           3 :   case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
    6528           3 :   case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
    6529           7 :   case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
    6530           3 :   case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
    6531           7 :   case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
    6532           4 :   case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
    6533           4 :   case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
    6534           5 :   case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
    6535           4 :   case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
    6536           8 :   case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
    6537             : 
    6538             :   // VST4
    6539           5 :   case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
    6540           5 :   case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
    6541           5 :   case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
    6542           7 :   case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
    6543           7 :   case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
    6544           7 :   case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
    6545           5 :   case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
    6546           5 :   case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
    6547           5 :   case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
    6548           5 :   case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
    6549           5 :   case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
    6550           5 :   case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
    6551           6 :   case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
    6552           6 :   case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
    6553           5 :   case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
    6554           5 :   case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
    6555           5 :   case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
    6556           5 :   case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
    6557             :   }
    6558             : }
    6559             : 
    6560         424 : static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
    6561         424 :   switch(Opc) {
    6562           0 :   default: llvm_unreachable("unexpected opcode!");
    6563             :   // VLD1LN
    6564           2 :   case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
    6565           3 :   case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
    6566           4 :   case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
    6567           2 :   case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
    6568           3 :   case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
    6569           4 :   case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
    6570           3 :   case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
    6571           4 :   case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
    6572           6 :   case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
    6573             : 
    6574             :   // VLD2LN
    6575           3 :   case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
    6576           2 :   case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
    6577           2 :   case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
    6578           2 :   case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
    6579           3 :   case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
    6580           3 :   case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
    6581           2 :   case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
    6582           2 :   case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
    6583           2 :   case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
    6584           2 :   case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
    6585           5 :   case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
    6586           4 :   case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
    6587           4 :   case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
    6588           4 :   case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
    6589           4 :   case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
    6590             : 
    6591             :   // VLD3DUP
    6592           2 :   case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
    6593           2 :   case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
    6594           2 :   case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
    6595           2 :   case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
    6596           2 :   case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
    6597           2 :   case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
    6598           2 :   case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
    6599           2 :   case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
    6600           2 :   case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
    6601           2 :   case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
    6602           2 :   case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
    6603           2 :   case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
    6604           2 :   case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
    6605           2 :   case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
    6606           2 :   case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
    6607           2 :   case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
    6608           2 :   case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
    6609           2 :   case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
    6610             : 
    6611             :   // VLD3LN
    6612           2 :   case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
    6613           2 :   case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
    6614           2 :   case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
    6615           2 :   case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
    6616           2 :   case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
    6617           2 :   case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
    6618           2 :   case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
    6619           2 :   case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
    6620           2 :   case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
    6621           2 :   case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
    6622           3 :   case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
    6623           3 :   case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
    6624           3 :   case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
    6625           3 :   case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
    6626           3 :   case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
    6627             : 
    6628             :   // VLD3
    6629           3 :   case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
    6630           3 :   case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
    6631           3 :   case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
    6632           5 :   case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
    6633           5 :   case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
    6634           5 :   case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
    6635           3 :   case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
    6636           3 :   case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
    6637           3 :   case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
    6638           3 :   case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
    6639           3 :   case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
    6640           3 :   case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
    6641           4 :   case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
    6642           4 :   case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
    6643           4 :   case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
    6644           3 :   case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
    6645           3 :   case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
    6646           3 :   case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
    6647             : 
    6648             :   // VLD4LN
    6649           3 :   case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
    6650           3 :   case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
    6651           4 :   case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
    6652           3 :   case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
    6653           4 :   case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
    6654           3 :   case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
    6655           3 :   case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
    6656           4 :   case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
    6657           3 :   case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
    6658           4 :   case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
    6659           4 :   case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
    6660           4 :   case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
    6661           5 :   case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
    6662           4 :   case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
    6663           5 :   case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
    6664             : 
    6665             :   // VLD4DUP
    6666           3 :   case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
    6667           3 :   case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
    6668           4 :   case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
    6669           3 :   case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
    6670           3 :   case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
    6671           4 :   case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
    6672           3 :   case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
    6673           3 :   case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
    6674           4 :   case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
    6675           3 :   case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
    6676           3 :   case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
    6677           4 :   case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
    6678           3 :   case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
    6679           3 :   case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
    6680           4 :   case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
    6681           3 :   case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
    6682           3 :   case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
    6683           4 :   case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
    6684             : 
    6685             :   // VLD4
    6686           5 :   case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
    6687           5 :   case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
    6688           5 :   case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
    6689           7 :   case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
    6690           7 :   case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
    6691           7 :   case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
    6692           5 :   case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
    6693           5 :   case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
    6694           5 :   case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
    6695           5 :   case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
    6696           5 :   case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
    6697           5 :   case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
    6698           6 :   case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
    6699           6 :   case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
    6700           6 :   case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
    6701           5 :   case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
    6702           5 :   case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
    6703           5 :   case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
    6704             :   }
    6705             : }
    6706             : 
    6707       21313 : bool ARMAsmParser::processInstruction(MCInst &Inst,
    6708             :                                       const OperandVector &Operands,
    6709             :                                       MCStreamer &Out) {
    6710             :   // Check if we have the wide qualifier, because if it's present we
    6711             :   // must avoid selecting a 16-bit thumb instruction.
    6712       21313 :   bool HasWideQualifier = false;
    6713      161451 :   for (auto &Op : Operands) {
    6714       98658 :     ARMOperand &ARMOp = static_cast<ARMOperand&>(*Op);
    6715      197316 :     if (ARMOp.isToken() && ARMOp.getToken() == ".w") {
    6716             :       HasWideQualifier = true;
    6717             :       break;
    6718             :     }
    6719             :   }
    6720             : 
    6721       21313 :   switch (Inst.getOpcode()) {
    6722             :   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
    6723           2 :   case ARM::LDRT_POST:
    6724             :   case ARM::LDRBT_POST: {
    6725             :     const unsigned Opcode =
    6726           2 :       (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
    6727           2 :                                            : ARM::LDRBT_POST_IMM;
    6728           4 :     MCInst TmpInst;
    6729           4 :     TmpInst.setOpcode(Opcode);
    6730           4 :     TmpInst.addOperand(Inst.getOperand(0));
    6731           4 :     TmpInst.addOperand(Inst.getOperand(1));
    6732           4 :     TmpInst.addOperand(Inst.getOperand(1));
    6733           4 :     TmpInst.addOperand(MCOperand::createReg(0));
    6734           4 :     TmpInst.addOperand(MCOperand::createImm(0));
    6735           4 :     TmpInst.addOperand(Inst.getOperand(2));
    6736           4 :     TmpInst.addOperand(Inst.getOperand(3));
    6737           2 :     Inst = TmpInst;
    6738           2 :     return true;
    6739             :   }
    6740             :   // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
    6741           4 :   case ARM::STRT_POST:
    6742             :   case ARM::STRBT_POST: {
    6743             :     const unsigned Opcode =
    6744           4 :       (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
    6745           4 :                                            : ARM::STRBT_POST_IMM;
    6746           8 :     MCInst TmpInst;
    6747           8 :     TmpInst.setOpcode(Opcode);
    6748           8 :     TmpInst.addOperand(Inst.getOperand(1));
    6749           8 :     TmpInst.addOperand(Inst.getOperand(0));
    6750           8 :     TmpInst.addOperand(Inst.getOperand(1));
    6751           8 :     TmpInst.addOperand(MCOperand::createReg(0));
    6752           8 :     TmpInst.addOperand(MCOperand::createImm(0));
    6753           8 :     TmpInst.addOperand(Inst.getOperand(2));
    6754           8 :     TmpInst.addOperand(Inst.getOperand(3));
    6755           4 :     Inst = TmpInst;
    6756           4 :     return true;
    6757             :   }
    6758             :   // Alias for alternate form of 'ADR Rd, #imm' instruction.
    6759         363 :   case ARM::ADDri: {
    6760         370 :     if (Inst.getOperand(1).getReg() != ARM::PC ||
    6761         375 :         Inst.getOperand(5).getReg() != 0 ||
    6762           8 :         !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
    6763             :       return false;
    6764           5 :     MCInst TmpInst;
    6765          10 :     TmpInst.setOpcode(ARM::ADR);
    6766          10 :     TmpInst.addOperand(Inst.getOperand(0));
    6767           5 :     if (Inst.getOperand(2).isImm()) {
    6768             :       // Immediate (mod_imm) will be in its encoded form, we must unencode it
    6769             :       // before passing it to the ADR instruction.
    6770           3 :       unsigned Enc = Inst.getOperand(2).getImm();
    6771           6 :       TmpInst.addOperand(MCOperand::createImm(
    6772           6 :         ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
    6773             :     } else {
    6774             :       // Turn PC-relative expression into absolute expression.
    6775             :       // Reading PC provides the start of the current instruction + 8 and
    6776             :       // the transform to adr is biased by that.
    6777           4 :       MCSymbol *Dot = getContext().createTempSymbol();
    6778           2 :       Out.EmitLabel(Dot);
    6779           2 :       const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
    6780           6 :       const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
    6781             :                                                      MCSymbolRefExpr::VK_None,
    6782           4 :                                                      getContext());
    6783           4 :       const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
    6784           4 :       const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
    6785           2 :                                                      getContext());
    6786           4 :       const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
    6787           2 :                                                         getContext());
    6788           4 :       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
    6789             :     }
    6790          10 :     TmpInst.addOperand(Inst.getOperand(3));
    6791          10 :     TmpInst.addOperand(Inst.getOperand(4));
    6792           5 :     Inst = TmpInst;
    6793           5 :     return true;
    6794             :   }
    6795             :   // Aliases for alternate PC+imm syntax of LDR instructions.
    6796          18 :   case ARM::t2LDRpcrel:
    6797             :     // Select the narrow version if the immediate will fit.
    6798          18 :     if (Inst.getOperand(1).getImm() > 0 &&
    6799          18 :         Inst.getOperand(1).getImm() <= 0xff &&
    6800             :         !HasWideQualifier)
    6801           0 :       Inst.setOpcode(ARM::tLDRpci);
    6802             :     else
    6803          18 :       Inst.setOpcode(ARM::t2LDRpci);
    6804             :     return true;
    6805             :   case ARM::t2LDRBpcrel:
    6806          14 :     Inst.setOpcode(ARM::t2LDRBpci);
    6807           7 :     return true;
    6808             :   case ARM::t2LDRHpcrel:
    6809          14 :     Inst.setOpcode(ARM::t2LDRHpci);
    6810           7 :     return true;
    6811             :   case ARM::t2LDRSBpcrel:
    6812          14 :     Inst.setOpcode(ARM::t2LDRSBpci);
    6813           7 :     return true;
    6814             :   case ARM::t2LDRSHpcrel:
    6815          14 :     Inst.setOpcode(ARM::t2LDRSHpci);
    6816           7 :     return true;
    6817         376 :   case ARM::LDRConstPool:
    6818             :   case ARM::tLDRConstPool:
    6819             :   case ARM::t2LDRConstPool: {
    6820             :     // Pseudo instruction ldr rt, =immediate is converted to a
    6821             :     // MOV rt, immediate if immediate is known and representable
    6822             :     // otherwise we create a constant pool entry that we load from.
    6823         752 :     MCInst TmpInst;
    6824         376 :     if (Inst.getOpcode() == ARM::LDRConstPool)
    6825         157 :       TmpInst.setOpcode(ARM::LDRi12);
    6826         219 :     else if (Inst.getOpcode() == ARM::tLDRConstPool)
    6827         209 :       TmpInst.setOpcode(ARM::tLDRpci);
    6828          10 :     else if (Inst.getOpcode() == ARM::t2LDRConstPool)
    6829          10 :       TmpInst.setOpcode(ARM::t2LDRpci);
    6830             :     const ARMOperand &PoolOperand =
    6831             :       (HasWideQualifier ?
    6832          12 :        static_cast<ARMOperand &>(*Operands[4]) :
    6833        1122 :        static_cast<ARMOperand &>(*Operands[3]));
    6834         376 :     const MCExpr *SubExprVal = PoolOperand.getConstantPoolImm();
    6835             :     // If SubExprVal is a constant we may be able to use a MOV
    6836         672 :     if (isa<MCConstantExpr>(SubExprVal) &&
    6837         964 :         Inst.getOperand(0).getReg() != ARM::PC &&
    6838         292 :         Inst.getOperand(0).getReg() != ARM::SP) {
    6839             :       int64_t Value =
    6840         576 :         (int64_t) (cast<MCConstantExpr>(SubExprVal))->getValue();
    6841         288 :       bool UseMov  = true;
    6842         288 :       bool MovHasS = true;
    6843         288 :       if (Inst.getOpcode() == ARM::LDRConstPool) {
    6844             :         // ARM Constant
    6845         121 :         if (ARM_AM::getSOImmVal(Value) != -1) {
    6846          34 :           Value = ARM_AM::getSOImmVal(Value);
    6847          34 :           TmpInst.setOpcode(ARM::MOVi);
    6848             :         }
    6849          87 :         else if (ARM_AM::getSOImmVal(~Value) != -1) {
    6850           8 :           Value = ARM_AM::getSOImmVal(~Value);
    6851           8 :           TmpInst.setOpcode(ARM::MVNi);
    6852             :         }
    6853          79 :         else if (hasV6T2Ops() &&
    6854          79 :                  Value >=0 && Value < 65536) {
    6855           8 :           TmpInst.setOpcode(ARM::MOVi16);
    6856           4 :           MovHasS = false;
    6857             :         }
    6858             :         else
    6859             :           UseMov = false;
    6860             :       }
    6861             :       else {
    6862             :         // Thumb/Thumb2 Constant
    6863         238 :         if (hasThumb2() &&
    6864          71 :             ARM_AM::getT2SOImmVal(Value) != -1)
    6865          22 :           TmpInst.setOpcode(ARM::t2MOVi);
    6866         194 :         else if (hasThumb2() &&
    6867          49 :                  ARM_AM::getT2SOImmVal(~Value) != -1) {
    6868           4 :           TmpInst.setOpcode(ARM::t2MVNi);
    6869           2 :           Value = ~Value;
    6870             :         }
    6871         143 :         else if (hasV8MBaseline() &&
    6872         232 :                  Value >=0 && Value < 65536) {
    6873          32 :           TmpInst.setOpcode(ARM::t2MOVi16);
    6874          16 :           MovHasS = false;
    6875             :         }
    6876             :         else
    6877             :           UseMov = false;
    6878             :       }
    6879         288 :       if (UseMov) {
    6880         172 :         TmpInst.addOperand(Inst.getOperand(0));           // Rt
    6881         172 :         TmpInst.addOperand(MCOperand::createImm(Value));  // Immediate
    6882         172 :         TmpInst.addOperand(Inst.getOperand(2));           // CondCode
    6883         172 :         TmpInst.addOperand(Inst.getOperand(3));           // CondCode
    6884          86 :         if (MovHasS)
    6885         132 :           TmpInst.addOperand(MCOperand::createReg(0));    // S
    6886          86 :         Inst = TmpInst;
    6887          86 :         return true;
    6888             :       }
    6889             :     }
    6890             :     // No opportunity to use MOV/MVN create constant pool
    6891             :     const MCExpr *CPLoc =
    6892         580 :       getTargetStreamer().addConstantPoolEntry(SubExprVal,
    6893         580 :                                                PoolOperand.getStartLoc());
    6894         580 :     TmpInst.addOperand(Inst.getOperand(0));           // Rt
    6895         580 :     TmpInst.addOperand(MCOperand::createExpr(CPLoc)); // offset to constpool
    6896         290 :     if (TmpInst.getOpcode() == ARM::LDRi12)
    6897         222 :       TmpInst.addOperand(MCOperand::createImm(0));    // unused offset
    6898         580 :     TmpInst.addOperand(Inst.getOperand(2));           // CondCode
    6899         580 :     TmpInst.addOperand(Inst.getOperand(3));           // CondCode
    6900         290 :     Inst = TmpInst;
    6901         290 :     return true;
    6902             :   }
    6903             :   // Handle NEON VST complex aliases.
    6904           6 :   case ARM::VST1LNdWB_register_Asm_8:
    6905             :   case ARM::VST1LNdWB_register_Asm_16:
    6906             :   case ARM::VST1LNdWB_register_Asm_32: {
    6907          12 :     MCInst TmpInst;
    6908             :     // Shuffle the operands around so the lane index operand is in the
    6909             :     // right place.
    6910             :     unsigned Spacing;
    6911          12 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    6912          12 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    6913          12 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    6914          12 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    6915          12 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    6916          12 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    6917          12 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    6918          12 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    6919          12 :     TmpInst.addOperand(Inst.getOperand(6));
    6920           6 :     Inst = TmpInst;
    6921           6 :     return true;
    6922             :   }
    6923             : 
    6924           9 :   case ARM::VST2LNdWB_register_Asm_8:
    6925             :   case ARM::VST2LNdWB_register_Asm_16:
    6926             :   case ARM::VST2LNdWB_register_Asm_32:
    6927             :   case ARM::VST2LNqWB_register_Asm_16:
    6928             :   case ARM::VST2LNqWB_register_Asm_32: {
    6929          18 :     MCInst TmpInst;
    6930             :     // Shuffle the operands around so the lane index operand is in the
    6931             :     // right place.
    6932             :     unsigned Spacing;
    6933          18 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    6934          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    6935          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    6936          18 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    6937          18 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    6938          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    6939          27 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    6940           9 :                                             Spacing));
    6941          18 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    6942          18 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    6943          18 :     TmpInst.addOperand(Inst.getOperand(6));
    6944           9 :     Inst = TmpInst;
    6945           9 :     return true;
    6946             :   }
    6947             : 
    6948          10 :   case ARM::VST3LNdWB_register_Asm_8:
    6949             :   case ARM::VST3LNdWB_register_Asm_16:
    6950             :   case ARM::VST3LNdWB_register_Asm_32:
    6951             :   case ARM::VST3LNqWB_register_Asm_16:
    6952             :   case ARM::VST3LNqWB_register_Asm_32: {
    6953          20 :     MCInst TmpInst;
    6954             :     // Shuffle the operands around so the lane index operand is in the
    6955             :     // right place.
    6956             :     unsigned Spacing;
    6957          20 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    6958          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    6959          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    6960          20 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    6961          20 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    6962          20 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    6963          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    6964          10 :                                             Spacing));
    6965          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    6966          10 :                                             Spacing * 2));
    6967          20 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    6968          20 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    6969          20 :     TmpInst.addOperand(Inst.getOperand(6));
    6970          10 :     Inst = TmpInst;
    6971          10 :     return true;
    6972             :   }
    6973             : 
    6974          23 :   case ARM::VST4LNdWB_register_Asm_8:
    6975             :   case ARM::VST4LNdWB_register_Asm_16:
    6976             :   case ARM::VST4LNdWB_register_Asm_32:
    6977             :   case ARM::VST4LNqWB_register_Asm_16:
    6978             :   case ARM::VST4LNqWB_register_Asm_32: {
    6979          46 :     MCInst TmpInst;
    6980             :     // Shuffle the operands around so the lane index operand is in the
    6981             :     // right place.
    6982             :     unsigned Spacing;
    6983          46 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    6984          46 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    6985          46 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    6986          46 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    6987          46 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    6988          46 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    6989          69 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    6990          23 :                                             Spacing));
    6991          69 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    6992          23 :                                             Spacing * 2));
    6993          69 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    6994          23 :                                             Spacing * 3));
    6995          46 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    6996          46 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    6997          46 :     TmpInst.addOperand(Inst.getOperand(6));
    6998          23 :     Inst = TmpInst;
    6999          23 :     return true;
    7000             :   }
    7001             : 
    7002           6 :   case ARM::VST1LNdWB_fixed_Asm_8:
    7003             :   case ARM::VST1LNdWB_fixed_Asm_16:
    7004             :   case ARM::VST1LNdWB_fixed_Asm_32: {
    7005          12 :     MCInst TmpInst;
    7006             :     // Shuffle the operands around so the lane index operand is in the
    7007             :     // right place.
    7008             :     unsigned Spacing;
    7009          12 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7010          12 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7011          12 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7012          12 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7013          12 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7014          12 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7015          12 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7016          12 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7017          12 :     TmpInst.addOperand(Inst.getOperand(5));
    7018           6 :     Inst = TmpInst;
    7019           6 :     return true;
    7020             :   }
    7021             : 
    7022           9 :   case ARM::VST2LNdWB_fixed_Asm_8:
    7023             :   case ARM::VST2LNdWB_fixed_Asm_16:
    7024             :   case ARM::VST2LNdWB_fixed_Asm_32:
    7025             :   case ARM::VST2LNqWB_fixed_Asm_16:
    7026             :   case ARM::VST2LNqWB_fixed_Asm_32: {
    7027          18 :     MCInst TmpInst;
    7028             :     // Shuffle the operands around so the lane index operand is in the
    7029             :     // right place.
    7030             :     unsigned Spacing;
    7031          18 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7032          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7033          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7034          18 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7035          18 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7036          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7037          27 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7038           9 :                                             Spacing));
    7039          18 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7040          18 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7041          18 :     TmpInst.addOperand(Inst.getOperand(5));
    7042           9 :     Inst = TmpInst;
    7043           9 :     return true;
    7044             :   }
    7045             : 
    7046          10 :   case ARM::VST3LNdWB_fixed_Asm_8:
    7047             :   case ARM::VST3LNdWB_fixed_Asm_16:
    7048             :   case ARM::VST3LNdWB_fixed_Asm_32:
    7049             :   case ARM::VST3LNqWB_fixed_Asm_16:
    7050             :   case ARM::VST3LNqWB_fixed_Asm_32: {
    7051          20 :     MCInst TmpInst;
    7052             :     // Shuffle the operands around so the lane index operand is in the
    7053             :     // right place.
    7054             :     unsigned Spacing;
    7055          20 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7056          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7057          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7058          20 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7059          20 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7060          20 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7061          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7062          10 :                                             Spacing));
    7063          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7064          10 :                                             Spacing * 2));
    7065          20 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7066          20 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7067          20 :     TmpInst.addOperand(Inst.getOperand(5));
    7068          10 :     Inst = TmpInst;
    7069          10 :     return true;
    7070             :   }
    7071             : 
    7072          23 :   case ARM::VST4LNdWB_fixed_Asm_8:
    7073             :   case ARM::VST4LNdWB_fixed_Asm_16:
    7074             :   case ARM::VST4LNdWB_fixed_Asm_32:
    7075             :   case ARM::VST4LNqWB_fixed_Asm_16:
    7076             :   case ARM::VST4LNqWB_fixed_Asm_32: {
    7077          46 :     MCInst TmpInst;
    7078             :     // Shuffle the operands around so the lane index operand is in the
    7079             :     // right place.
    7080             :     unsigned Spacing;
    7081          46 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7082          46 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7083          46 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7084          46 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7085          46 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7086          46 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7087          69 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7088          23 :                                             Spacing));
    7089          69 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7090          23 :                                             Spacing * 2));
    7091          69 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7092          23 :                                             Spacing * 3));
    7093          46 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7094          46 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7095          46 :     TmpInst.addOperand(Inst.getOperand(5));
    7096          23 :     Inst = TmpInst;
    7097          23 :     return true;
    7098             :   }
    7099             : 
    7100           6 :   case ARM::VST1LNdAsm_8:
    7101             :   case ARM::VST1LNdAsm_16:
    7102             :   case ARM::VST1LNdAsm_32: {
    7103          12 :     MCInst TmpInst;
    7104             :     // Shuffle the operands around so the lane index operand is in the
    7105             :     // right place.
    7106             :     unsigned Spacing;
    7107          12 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7108          12 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7109          12 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7110          12 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7111          12 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7112          12 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7113          12 :     TmpInst.addOperand(Inst.getOperand(5));
    7114           6 :     Inst = TmpInst;
    7115           6 :     return true;
    7116             :   }
    7117             : 
    7118          19 :   case ARM::VST2LNdAsm_8:
    7119             :   case ARM::VST2LNdAsm_16:
    7120             :   case ARM::VST2LNdAsm_32:
    7121             :   case ARM::VST2LNqAsm_16:
    7122             :   case ARM::VST2LNqAsm_32: {
    7123          38 :     MCInst TmpInst;
    7124             :     // Shuffle the operands around so the lane index operand is in the
    7125             :     // right place.
    7126             :     unsigned Spacing;
    7127          38 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7128          38 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7129          38 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7130          38 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7131          57 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7132          19 :                                             Spacing));
    7133          38 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7134          38 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7135          38 :     TmpInst.addOperand(Inst.getOperand(5));
    7136          19 :     Inst = TmpInst;
    7137          19 :     return true;
    7138             :   }
    7139             : 
    7140          15 :   case ARM::VST3LNdAsm_8:
    7141             :   case ARM::VST3LNdAsm_16:
    7142             :   case ARM::VST3LNdAsm_32:
    7143             :   case ARM::VST3LNqAsm_16:
    7144             :   case ARM::VST3LNqAsm_32: {
    7145          30 :     MCInst TmpInst;
    7146             :     // Shuffle the operands around so the lane index operand is in the
    7147             :     // right place.
    7148             :     unsigned Spacing;
    7149          30 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7150          30 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7151          30 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7152          30 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7153          45 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7154          15 :                                             Spacing));
    7155          45 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7156          15 :                                             Spacing * 2));
    7157          30 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7158          30 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7159          30 :     TmpInst.addOperand(Inst.getOperand(5));
    7160          15 :     Inst = TmpInst;
    7161          15 :     return true;
    7162             :   }
    7163             : 
    7164          25 :   case ARM::VST4LNdAsm_8:
    7165             :   case ARM::VST4LNdAsm_16:
    7166             :   case ARM::VST4LNdAsm_32:
    7167             :   case ARM::VST4LNqAsm_16:
    7168             :   case ARM::VST4LNqAsm_32: {
    7169          50 :     MCInst TmpInst;
    7170             :     // Shuffle the operands around so the lane index operand is in the
    7171             :     // right place.
    7172             :     unsigned Spacing;
    7173          50 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7174          50 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7175          50 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7176          50 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7177          75 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7178          25 :                                             Spacing));
    7179          75 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7180          25 :                                             Spacing * 2));
    7181          75 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7182          25 :                                             Spacing * 3));
    7183          50 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7184          50 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7185          50 :     TmpInst.addOperand(Inst.getOperand(5));
    7186          25 :     Inst = TmpInst;
    7187          25 :     return true;
    7188             :   }
    7189             : 
    7190             :   // Handle NEON VLD complex aliases.
    7191           9 :   case ARM::VLD1LNdWB_register_Asm_8:
    7192             :   case ARM::VLD1LNdWB_register_Asm_16:
    7193             :   case ARM::VLD1LNdWB_register_Asm_32: {
    7194          18 :     MCInst TmpInst;
    7195             :     // Shuffle the operands around so the lane index operand is in the
    7196             :     // right place.
    7197             :     unsigned Spacing;
    7198          18 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7199          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7200          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7201          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7202          18 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7203          18 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    7204          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7205          18 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7206          18 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    7207          18 :     TmpInst.addOperand(Inst.getOperand(6));
    7208           9 :     Inst = TmpInst;
    7209           9 :     return true;
    7210             :   }
    7211             : 
    7212          11 :   case ARM::VLD2LNdWB_register_Asm_8:
    7213             :   case ARM::VLD2LNdWB_register_Asm_16:
    7214             :   case ARM::VLD2LNdWB_register_Asm_32:
    7215             :   case ARM::VLD2LNqWB_register_Asm_16:
    7216             :   case ARM::VLD2LNqWB_register_Asm_32: {
    7217          22 :     MCInst TmpInst;
    7218             :     // Shuffle the operands around so the lane index operand is in the
    7219             :     // right place.
    7220             :     unsigned Spacing;
    7221          22 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7222          22 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7223          33 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7224          11 :                                             Spacing));
    7225          22 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7226          22 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7227          22 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7228          22 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    7229          22 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7230          33 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7231          11 :                                             Spacing));
    7232          22 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7233          22 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    7234          22 :     TmpInst.addOperand(Inst.getOperand(6));
    7235          11 :     Inst = TmpInst;
    7236          11 :     return true;
    7237             :   }
    7238             : 
    7239          10 :   case ARM::VLD3LNdWB_register_Asm_8:
    7240             :   case ARM::VLD3LNdWB_register_Asm_16:
    7241             :   case ARM::VLD3LNdWB_register_Asm_32:
    7242             :   case ARM::VLD3LNqWB_register_Asm_16:
    7243             :   case ARM::VLD3LNqWB_register_Asm_32: {
    7244          20 :     MCInst TmpInst;
    7245             :     // Shuffle the operands around so the lane index operand is in the
    7246             :     // right place.
    7247             :     unsigned Spacing;
    7248          20 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7249          20 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7250          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7251          10 :                                             Spacing));
    7252          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7253          10 :                                             Spacing * 2));
    7254          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7255          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7256          20 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7257          20 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    7258          20 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7259          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7260          10 :                                             Spacing));
    7261          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7262          10 :                                             Spacing * 2));
    7263          20 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7264          20 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    7265          20 :     TmpInst.addOperand(Inst.getOperand(6));
    7266          10 :     Inst = TmpInst;
    7267          10 :     return true;
    7268             :   }
    7269             : 
    7270          17 :   case ARM::VLD4LNdWB_register_Asm_8:
    7271             :   case ARM::VLD4LNdWB_register_Asm_16:
    7272             :   case ARM::VLD4LNdWB_register_Asm_32:
    7273             :   case ARM::VLD4LNqWB_register_Asm_16:
    7274             :   case ARM::VLD4LNqWB_register_Asm_32: {
    7275          34 :     MCInst TmpInst;
    7276             :     // Shuffle the operands around so the lane index operand is in the
    7277             :     // right place.
    7278             :     unsigned Spacing;
    7279          34 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7280          34 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7281          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7282          17 :                                             Spacing));
    7283          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7284          17 :                                             Spacing * 2));
    7285          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7286          17 :                                             Spacing * 3));
    7287          34 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7288          34 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7289          34 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7290          34 :     TmpInst.addOperand(Inst.getOperand(4)); // Rm
    7291          34 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7292          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7293          17 :                                             Spacing));
    7294          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7295          17 :                                             Spacing * 2));
    7296          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7297          17 :                                             Spacing * 3));
    7298          34 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7299          34 :     TmpInst.addOperand(Inst.getOperand(5)); // CondCode
    7300          34 :     TmpInst.addOperand(Inst.getOperand(6));
    7301          17 :     Inst = TmpInst;
    7302          17 :     return true;
    7303             :   }
    7304             : 
    7305           9 :   case ARM::VLD1LNdWB_fixed_Asm_8:
    7306             :   case ARM::VLD1LNdWB_fixed_Asm_16:
    7307             :   case ARM::VLD1LNdWB_fixed_Asm_32: {
    7308          18 :     MCInst TmpInst;
    7309             :     // Shuffle the operands around so the lane index operand is in the
    7310             :     // right place.
    7311             :     unsigned Spacing;
    7312          18 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7313          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7314          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7315          18 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7316          18 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7317          18 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7318          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7319          18 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7320          18 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7321          18 :     TmpInst.addOperand(Inst.getOperand(5));
    7322           9 :     Inst = TmpInst;
    7323           9 :     return true;
    7324             :   }
    7325             : 
    7326          12 :   case ARM::VLD2LNdWB_fixed_Asm_8:
    7327             :   case ARM::VLD2LNdWB_fixed_Asm_16:
    7328             :   case ARM::VLD2LNdWB_fixed_Asm_32:
    7329             :   case ARM::VLD2LNqWB_fixed_Asm_16:
    7330             :   case ARM::VLD2LNqWB_fixed_Asm_32: {
    7331          24 :     MCInst TmpInst;
    7332             :     // Shuffle the operands around so the lane index operand is in the
    7333             :     // right place.
    7334             :     unsigned Spacing;
    7335          24 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7336          24 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7337          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7338          12 :                                             Spacing));
    7339          24 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7340          24 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7341          24 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7342          24 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7343          24 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7344          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7345          12 :                                             Spacing));
    7346          24 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7347          24 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7348          24 :     TmpInst.addOperand(Inst.getOperand(5));
    7349          12 :     Inst = TmpInst;
    7350          12 :     return true;
    7351             :   }
    7352             : 
    7353          10 :   case ARM::VLD3LNdWB_fixed_Asm_8:
    7354             :   case ARM::VLD3LNdWB_fixed_Asm_16:
    7355             :   case ARM::VLD3LNdWB_fixed_Asm_32:
    7356             :   case ARM::VLD3LNqWB_fixed_Asm_16:
    7357             :   case ARM::VLD3LNqWB_fixed_Asm_32: {
    7358          20 :     MCInst TmpInst;
    7359             :     // Shuffle the operands around so the lane index operand is in the
    7360             :     // right place.
    7361             :     unsigned Spacing;
    7362          20 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7363          20 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7364          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7365          10 :                                             Spacing));
    7366          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7367          10 :                                             Spacing * 2));
    7368          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7369          20 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7370          20 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7371          20 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7372          20 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7373          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7374          10 :                                             Spacing));
    7375          30 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7376          10 :                                             Spacing * 2));
    7377          20 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7378          20 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7379          20 :     TmpInst.addOperand(Inst.getOperand(5));
    7380          10 :     Inst = TmpInst;
    7381          10 :     return true;
    7382             :   }
    7383             : 
    7384          17 :   case ARM::VLD4LNdWB_fixed_Asm_8:
    7385             :   case ARM::VLD4LNdWB_fixed_Asm_16:
    7386             :   case ARM::VLD4LNdWB_fixed_Asm_32:
    7387             :   case ARM::VLD4LNqWB_fixed_Asm_16:
    7388             :   case ARM::VLD4LNqWB_fixed_Asm_32: {
    7389          34 :     MCInst TmpInst;
    7390             :     // Shuffle the operands around so the lane index operand is in the
    7391             :     // right place.
    7392             :     unsigned Spacing;
    7393          34 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7394          34 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7395          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7396          17 :                                             Spacing));
    7397          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7398          17 :                                             Spacing * 2));
    7399          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7400          17 :                                             Spacing * 3));
    7401          34 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
    7402          34 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7403          34 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7404          34 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7405          34 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7406          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7407          17 :                                             Spacing));
    7408          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7409          17 :                                             Spacing * 2));
    7410          51 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7411          17 :                                             Spacing * 3));
    7412          34 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7413          34 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7414          34 :     TmpInst.addOperand(Inst.getOperand(5));
    7415          17 :     Inst = TmpInst;
    7416          17 :     return true;
    7417             :   }
    7418             : 
    7419          13 :   case ARM::VLD1LNdAsm_8:
    7420             :   case ARM::VLD1LNdAsm_16:
    7421             :   case ARM::VLD1LNdAsm_32: {
    7422          26 :     MCInst TmpInst;
    7423             :     // Shuffle the operands around so the lane index operand is in the
    7424             :     // right place.
    7425             :     unsigned Spacing;
    7426          26 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7427          26 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7428          26 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7429          26 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7430          26 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7431          26 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7432          26 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7433          26 :     TmpInst.addOperand(Inst.getOperand(5));
    7434          13 :     Inst = TmpInst;
    7435          13 :     return true;
    7436             :   }
    7437             : 
    7438          21 :   case ARM::VLD2LNdAsm_8:
    7439             :   case ARM::VLD2LNdAsm_16:
    7440             :   case ARM::VLD2LNdAsm_32:
    7441             :   case ARM::VLD2LNqAsm_16:
    7442             :   case ARM::VLD2LNqAsm_32: {
    7443          42 :     MCInst TmpInst;
    7444             :     // Shuffle the operands around so the lane index operand is in the
    7445             :     // right place.
    7446             :     unsigned Spacing;
    7447          42 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7448          42 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7449          63 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7450          21 :                                             Spacing));
    7451          42 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7452          42 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7453          42 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7454          63 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7455          21 :                                             Spacing));
    7456          42 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7457          42 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7458          42 :     TmpInst.addOperand(Inst.getOperand(5));
    7459          21 :     Inst = TmpInst;
    7460          21 :     return true;
    7461             :   }
    7462             : 
    7463          15 :   case ARM::VLD3LNdAsm_8:
    7464             :   case ARM::VLD3LNdAsm_16:
    7465             :   case ARM::VLD3LNdAsm_32:
    7466             :   case ARM::VLD3LNqAsm_16:
    7467             :   case ARM::VLD3LNqAsm_32: {
    7468          30 :     MCInst TmpInst;
    7469             :     // Shuffle the operands around so the lane index operand is in the
    7470             :     // right place.
    7471             :     unsigned Spacing;
    7472          30 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7473          30 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7474          45 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7475          15 :                                             Spacing));
    7476          45 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7477          15 :                                             Spacing * 2));
    7478          30 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7479          30 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7480          30 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7481          45 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7482          15 :                                             Spacing));
    7483          45 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7484          15 :                                             Spacing * 2));
    7485          30 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7486          30 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7487          30 :     TmpInst.addOperand(Inst.getOperand(5));
    7488          15 :     Inst = TmpInst;
    7489          15 :     return true;
    7490             :   }
    7491             : 
    7492          22 :   case ARM::VLD4LNdAsm_8:
    7493             :   case ARM::VLD4LNdAsm_16:
    7494             :   case ARM::VLD4LNdAsm_32:
    7495             :   case ARM::VLD4LNqAsm_16:
    7496             :   case ARM::VLD4LNqAsm_32: {
    7497          44 :     MCInst TmpInst;
    7498             :     // Shuffle the operands around so the lane index operand is in the
    7499             :     // right place.
    7500             :     unsigned Spacing;
    7501          44 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7502          44 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7503          66 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7504          22 :                                             Spacing));
    7505          66 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7506          22 :                                             Spacing * 2));
    7507          66 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7508          22 :                                             Spacing * 3));
    7509          44 :     TmpInst.addOperand(Inst.getOperand(2)); // Rn
    7510          44 :     TmpInst.addOperand(Inst.getOperand(3)); // alignment
    7511          44 :     TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
    7512          66 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7513          22 :                                             Spacing));
    7514          66 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7515          22 :                                             Spacing * 2));
    7516          66 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7517          22 :                                             Spacing * 3));
    7518          44 :     TmpInst.addOperand(Inst.getOperand(1)); // lane
    7519          44 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7520          44 :     TmpInst.addOperand(Inst.getOperand(5));
    7521          22 :     Inst = TmpInst;
    7522          22 :     return true;
    7523             :   }
    7524             : 
    7525             :   // VLD3DUP single 3-element structure to all lanes instructions.
    7526          12 :   case ARM::VLD3DUPdAsm_8:
    7527             :   case ARM::VLD3DUPdAsm_16:
    7528             :   case ARM::VLD3DUPdAsm_32:
    7529             :   case ARM::VLD3DUPqAsm_8:
    7530             :   case ARM::VLD3DUPqAsm_16:
    7531             :   case ARM::VLD3DUPqAsm_32: {
    7532          24 :     MCInst TmpInst;
    7533             :     unsigned Spacing;
    7534          24 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7535          24 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7536          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7537          12 :                                             Spacing));
    7538          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7539          12 :                                             Spacing * 2));
    7540          24 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7541          24 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7542          24 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7543          24 :     TmpInst.addOperand(Inst.getOperand(4));
    7544          12 :     Inst = TmpInst;
    7545          12 :     return true;
    7546             :   }
    7547             : 
    7548          12 :   case ARM::VLD3DUPdWB_fixed_Asm_8:
    7549             :   case ARM::VLD3DUPdWB_fixed_Asm_16:
    7550             :   case ARM::VLD3DUPdWB_fixed_Asm_32:
    7551             :   case ARM::VLD3DUPqWB_fixed_Asm_8:
    7552             :   case ARM::VLD3DUPqWB_fixed_Asm_16:
    7553             :   case ARM::VLD3DUPqWB_fixed_Asm_32: {
    7554          24 :     MCInst TmpInst;
    7555             :     unsigned Spacing;
    7556          24 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7557          24 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7558          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7559          12 :                                             Spacing));
    7560          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7561          12 :                                             Spacing * 2));
    7562          24 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7563          24 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7564          24 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7565          24 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7566          24 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7567          24 :     TmpInst.addOperand(Inst.getOperand(4));
    7568          12 :     Inst = TmpInst;
    7569          12 :     return true;
    7570             :   }
    7571             : 
    7572          12 :   case ARM::VLD3DUPdWB_register_Asm_8:
    7573             :   case ARM::VLD3DUPdWB_register_Asm_16:
    7574             :   case ARM::VLD3DUPdWB_register_Asm_32:
    7575             :   case ARM::VLD3DUPqWB_register_Asm_8:
    7576             :   case ARM::VLD3DUPqWB_register_Asm_16:
    7577             :   case ARM::VLD3DUPqWB_register_Asm_32: {
    7578          24 :     MCInst TmpInst;
    7579             :     unsigned Spacing;
    7580          24 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7581          24 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7582          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7583          12 :                                             Spacing));
    7584          36 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7585          12 :                                             Spacing * 2));
    7586          24 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7587          24 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7588          24 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7589          24 :     TmpInst.addOperand(Inst.getOperand(3)); // Rm
    7590          24 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7591          24 :     TmpInst.addOperand(Inst.getOperand(5));
    7592          12 :     Inst = TmpInst;
    7593          12 :     return true;
    7594             :   }
    7595             : 
    7596             :   // VLD3 multiple 3-element structure instructions.
    7597          21 :   case ARM::VLD3dAsm_8:
    7598             :   case ARM::VLD3dAsm_16:
    7599             :   case ARM::VLD3dAsm_32:
    7600             :   case ARM::VLD3qAsm_8:
    7601             :   case ARM::VLD3qAsm_16:
    7602             :   case ARM::VLD3qAsm_32: {
    7603          42 :     MCInst TmpInst;
    7604             :     unsigned Spacing;
    7605          42 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7606          42 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7607          63 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7608          21 :                                             Spacing));
    7609          63 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7610          21 :                                             Spacing * 2));
    7611          42 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7612          42 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7613          42 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7614          42 :     TmpInst.addOperand(Inst.getOperand(4));
    7615          21 :     Inst = TmpInst;
    7616          21 :     return true;
    7617             :   }
    7618             : 
    7619          24 :   case ARM::VLD3dWB_fixed_Asm_8:
    7620             :   case ARM::VLD3dWB_fixed_Asm_16:
    7621             :   case ARM::VLD3dWB_fixed_Asm_32:
    7622             :   case ARM::VLD3qWB_fixed_Asm_8:
    7623             :   case ARM::VLD3qWB_fixed_Asm_16:
    7624             :   case ARM::VLD3qWB_fixed_Asm_32: {
    7625          48 :     MCInst TmpInst;
    7626             :     unsigned Spacing;
    7627          48 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7628          48 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7629          72 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7630          24 :                                             Spacing));
    7631          72 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7632          24 :                                             Spacing * 2));
    7633          48 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7634          48 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7635          48 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7636          48 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7637          48 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7638          48 :     TmpInst.addOperand(Inst.getOperand(4));
    7639          24 :     Inst = TmpInst;
    7640          24 :     return true;
    7641             :   }
    7642             : 
    7643          18 :   case ARM::VLD3dWB_register_Asm_8:
    7644             :   case ARM::VLD3dWB_register_Asm_16:
    7645             :   case ARM::VLD3dWB_register_Asm_32:
    7646             :   case ARM::VLD3qWB_register_Asm_8:
    7647             :   case ARM::VLD3qWB_register_Asm_16:
    7648             :   case ARM::VLD3qWB_register_Asm_32: {
    7649          36 :     MCInst TmpInst;
    7650             :     unsigned Spacing;
    7651          36 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7652          36 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7653          54 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7654          18 :                                             Spacing));
    7655          54 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7656          18 :                                             Spacing * 2));
    7657          36 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7658          36 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7659          36 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7660          36 :     TmpInst.addOperand(Inst.getOperand(3)); // Rm
    7661          36 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7662          36 :     TmpInst.addOperand(Inst.getOperand(5));
    7663          18 :     Inst = TmpInst;
    7664          18 :     return true;
    7665             :   }
    7666             : 
    7667             :   // VLD4DUP single 3-element structure to all lanes instructions.
    7668          20 :   case ARM::VLD4DUPdAsm_8:
    7669             :   case ARM::VLD4DUPdAsm_16:
    7670             :   case ARM::VLD4DUPdAsm_32:
    7671             :   case ARM::VLD4DUPqAsm_8:
    7672             :   case ARM::VLD4DUPqAsm_16:
    7673             :   case ARM::VLD4DUPqAsm_32: {
    7674          40 :     MCInst TmpInst;
    7675             :     unsigned Spacing;
    7676          40 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7677          40 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7678          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7679          20 :                                             Spacing));
    7680          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7681          20 :                                             Spacing * 2));
    7682          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7683          20 :                                             Spacing * 3));
    7684          40 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7685          40 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7686          40 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7687          40 :     TmpInst.addOperand(Inst.getOperand(4));
    7688          20 :     Inst = TmpInst;
    7689          20 :     return true;
    7690             :   }
    7691             : 
    7692          20 :   case ARM::VLD4DUPdWB_fixed_Asm_8:
    7693             :   case ARM::VLD4DUPdWB_fixed_Asm_16:
    7694             :   case ARM::VLD4DUPdWB_fixed_Asm_32:
    7695             :   case ARM::VLD4DUPqWB_fixed_Asm_8:
    7696             :   case ARM::VLD4DUPqWB_fixed_Asm_16:
    7697             :   case ARM::VLD4DUPqWB_fixed_Asm_32: {
    7698          40 :     MCInst TmpInst;
    7699             :     unsigned Spacing;
    7700          40 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7701          40 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7702          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7703          20 :                                             Spacing));
    7704          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7705          20 :                                             Spacing * 2));
    7706          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7707          20 :                                             Spacing * 3));
    7708          40 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7709          40 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7710          40 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7711          40 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7712          40 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7713          40 :     TmpInst.addOperand(Inst.getOperand(4));
    7714          20 :     Inst = TmpInst;
    7715          20 :     return true;
    7716             :   }
    7717             : 
    7718          20 :   case ARM::VLD4DUPdWB_register_Asm_8:
    7719             :   case ARM::VLD4DUPdWB_register_Asm_16:
    7720             :   case ARM::VLD4DUPdWB_register_Asm_32:
    7721             :   case ARM::VLD4DUPqWB_register_Asm_8:
    7722             :   case ARM::VLD4DUPqWB_register_Asm_16:
    7723             :   case ARM::VLD4DUPqWB_register_Asm_32: {
    7724          40 :     MCInst TmpInst;
    7725             :     unsigned Spacing;
    7726          40 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7727          40 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7728          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7729          20 :                                             Spacing));
    7730          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7731          20 :                                             Spacing * 2));
    7732          60 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7733          20 :                                             Spacing * 3));
    7734          40 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7735          40 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7736          40 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7737          40 :     TmpInst.addOperand(Inst.getOperand(3)); // Rm
    7738          40 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7739          40 :     TmpInst.addOperand(Inst.getOperand(5));
    7740          20 :     Inst = TmpInst;
    7741          20 :     return true;
    7742             :   }
    7743             : 
    7744             :   // VLD4 multiple 4-element structure instructions.
    7745          33 :   case ARM::VLD4dAsm_8:
    7746             :   case ARM::VLD4dAsm_16:
    7747             :   case ARM::VLD4dAsm_32:
    7748             :   case ARM::VLD4qAsm_8:
    7749             :   case ARM::VLD4qAsm_16:
    7750             :   case ARM::VLD4qAsm_32: {
    7751          66 :     MCInst TmpInst;
    7752             :     unsigned Spacing;
    7753          66 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7754          66 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7755          99 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7756          33 :                                             Spacing));
    7757          99 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7758          33 :                                             Spacing * 2));
    7759          99 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7760          33 :                                             Spacing * 3));
    7761          66 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7762          66 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7763          66 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7764          66 :     TmpInst.addOperand(Inst.getOperand(4));
    7765          33 :     Inst = TmpInst;
    7766          33 :     return true;
    7767             :   }
    7768             : 
    7769          36 :   case ARM::VLD4dWB_fixed_Asm_8:
    7770             :   case ARM::VLD4dWB_fixed_Asm_16:
    7771             :   case ARM::VLD4dWB_fixed_Asm_32:
    7772             :   case ARM::VLD4qWB_fixed_Asm_8:
    7773             :   case ARM::VLD4qWB_fixed_Asm_16:
    7774             :   case ARM::VLD4qWB_fixed_Asm_32: {
    7775          72 :     MCInst TmpInst;
    7776             :     unsigned Spacing;
    7777          72 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7778          72 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7779         108 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7780          36 :                                             Spacing));
    7781         108 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7782          36 :                                             Spacing * 2));
    7783         108 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7784          36 :                                             Spacing * 3));
    7785          72 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7786          72 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7787          72 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7788          72 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7789          72 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7790          72 :     TmpInst.addOperand(Inst.getOperand(4));
    7791          36 :     Inst = TmpInst;
    7792          36 :     return true;
    7793             :   }
    7794             : 
    7795          30 :   case ARM::VLD4dWB_register_Asm_8:
    7796             :   case ARM::VLD4dWB_register_Asm_16:
    7797             :   case ARM::VLD4dWB_register_Asm_32:
    7798             :   case ARM::VLD4qWB_register_Asm_8:
    7799             :   case ARM::VLD4qWB_register_Asm_16:
    7800             :   case ARM::VLD4qWB_register_Asm_32: {
    7801          60 :     MCInst TmpInst;
    7802             :     unsigned Spacing;
    7803          60 :     TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
    7804          60 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7805          90 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7806          30 :                                             Spacing));
    7807          90 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7808          30 :                                             Spacing * 2));
    7809          90 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7810          30 :                                             Spacing * 3));
    7811          60 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7812          60 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7813          60 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7814          60 :     TmpInst.addOperand(Inst.getOperand(3)); // Rm
    7815          60 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7816          60 :     TmpInst.addOperand(Inst.getOperand(5));
    7817          30 :     Inst = TmpInst;
    7818          30 :     return true;
    7819             :   }
    7820             : 
    7821             :   // VST3 multiple 3-element structure instructions.
    7822          21 :   case ARM::VST3dAsm_8:
    7823             :   case ARM::VST3dAsm_16:
    7824             :   case ARM::VST3dAsm_32:
    7825             :   case ARM::VST3qAsm_8:
    7826             :   case ARM::VST3qAsm_16:
    7827             :   case ARM::VST3qAsm_32: {
    7828          42 :     MCInst TmpInst;
    7829             :     unsigned Spacing;
    7830          42 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7831          42 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7832          42 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7833          42 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7834          63 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7835          21 :                                             Spacing));
    7836          63 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7837          21 :                                             Spacing * 2));
    7838          42 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7839          42 :     TmpInst.addOperand(Inst.getOperand(4));
    7840          21 :     Inst = TmpInst;
    7841          21 :     return true;
    7842             :   }
    7843             : 
    7844          24 :   case ARM::VST3dWB_fixed_Asm_8:
    7845             :   case ARM::VST3dWB_fixed_Asm_16:
    7846             :   case ARM::VST3dWB_fixed_Asm_32:
    7847             :   case ARM::VST3qWB_fixed_Asm_8:
    7848             :   case ARM::VST3qWB_fixed_Asm_16:
    7849             :   case ARM::VST3qWB_fixed_Asm_32: {
    7850          48 :     MCInst TmpInst;
    7851             :     unsigned Spacing;
    7852          48 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7853          48 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7854          48 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7855          48 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7856          48 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7857          48 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7858          72 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7859          24 :                                             Spacing));
    7860          72 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7861          24 :                                             Spacing * 2));
    7862          48 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7863          48 :     TmpInst.addOperand(Inst.getOperand(4));
    7864          24 :     Inst = TmpInst;
    7865          24 :     return true;
    7866             :   }
    7867             : 
    7868          18 :   case ARM::VST3dWB_register_Asm_8:
    7869             :   case ARM::VST3dWB_register_Asm_16:
    7870             :   case ARM::VST3dWB_register_Asm_32:
    7871             :   case ARM::VST3qWB_register_Asm_8:
    7872             :   case ARM::VST3qWB_register_Asm_16:
    7873             :   case ARM::VST3qWB_register_Asm_32: {
    7874          36 :     MCInst TmpInst;
    7875             :     unsigned Spacing;
    7876          36 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7877          36 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7878          36 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7879          36 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7880          36 :     TmpInst.addOperand(Inst.getOperand(3)); // Rm
    7881          36 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7882          54 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7883          18 :                                             Spacing));
    7884          54 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7885          18 :                                             Spacing * 2));
    7886          36 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7887          36 :     TmpInst.addOperand(Inst.getOperand(5));
    7888          18 :     Inst = TmpInst;
    7889          18 :     return true;
    7890             :   }
    7891             : 
    7892             :   // VST4 multiple 3-element structure instructions.
    7893          32 :   case ARM::VST4dAsm_8:
    7894             :   case ARM::VST4dAsm_16:
    7895             :   case ARM::VST4dAsm_32:
    7896             :   case ARM::VST4qAsm_8:
    7897             :   case ARM::VST4qAsm_16:
    7898             :   case ARM::VST4qAsm_32: {
    7899          64 :     MCInst TmpInst;
    7900             :     unsigned Spacing;
    7901          64 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7902          64 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7903          64 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7904          64 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7905          96 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7906          32 :                                             Spacing));
    7907          96 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7908          32 :                                             Spacing * 2));
    7909          96 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7910          32 :                                             Spacing * 3));
    7911          64 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7912          64 :     TmpInst.addOperand(Inst.getOperand(4));
    7913          32 :     Inst = TmpInst;
    7914          32 :     return true;
    7915             :   }
    7916             : 
    7917          36 :   case ARM::VST4dWB_fixed_Asm_8:
    7918             :   case ARM::VST4dWB_fixed_Asm_16:
    7919             :   case ARM::VST4dWB_fixed_Asm_32:
    7920             :   case ARM::VST4qWB_fixed_Asm_8:
    7921             :   case ARM::VST4qWB_fixed_Asm_16:
    7922             :   case ARM::VST4qWB_fixed_Asm_32: {
    7923          72 :     MCInst TmpInst;
    7924             :     unsigned Spacing;
    7925          72 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7926          72 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7927          72 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7928          72 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7929          72 :     TmpInst.addOperand(MCOperand::createReg(0)); // Rm
    7930          72 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7931         108 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7932          36 :                                             Spacing));
    7933         108 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7934          36 :                                             Spacing * 2));
    7935         108 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7936          36 :                                             Spacing * 3));
    7937          72 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    7938          72 :     TmpInst.addOperand(Inst.getOperand(4));
    7939          36 :     Inst = TmpInst;
    7940          36 :     return true;
    7941             :   }
    7942             : 
    7943          30 :   case ARM::VST4dWB_register_Asm_8:
    7944             :   case ARM::VST4dWB_register_Asm_16:
    7945             :   case ARM::VST4dWB_register_Asm_32:
    7946             :   case ARM::VST4qWB_register_Asm_8:
    7947             :   case ARM::VST4qWB_register_Asm_16:
    7948             :   case ARM::VST4qWB_register_Asm_32: {
    7949          60 :     MCInst TmpInst;
    7950             :     unsigned Spacing;
    7951          60 :     TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
    7952          60 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    7953          60 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
    7954          60 :     TmpInst.addOperand(Inst.getOperand(2)); // alignment
    7955          60 :     TmpInst.addOperand(Inst.getOperand(3)); // Rm
    7956          60 :     TmpInst.addOperand(Inst.getOperand(0)); // Vd
    7957          90 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7958          30 :                                             Spacing));
    7959          90 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7960          30 :                                             Spacing * 2));
    7961          90 :     TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
    7962          30 :                                             Spacing * 3));
    7963          60 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    7964          60 :     TmpInst.addOperand(Inst.getOperand(5));
    7965          30 :     Inst = TmpInst;
    7966          30 :     return true;
    7967             :   }
    7968             : 
    7969             :   // Handle encoding choice for the shift-immediate instructions.
    7970          73 :   case ARM::t2LSLri:
    7971             :   case ARM::t2LSRri:
    7972             :   case ARM::t2ASRri: {
    7973         127 :     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
    7974         146 :         isARMLowRegister(Inst.getOperand(1).getReg()) &&
    7975          60 :         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
    7976             :         !HasWideQualifier) {
    7977             :       unsigned NewOpc;
    7978           0 :       switch (Inst.getOpcode()) {
    7979           0 :       default: llvm_unreachable("unexpected opcode");
    7980             :       case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
    7981           0 :       case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
    7982           0 :       case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
    7983             :       }
    7984             :       // The Thumb1 operands aren't in the same order. Awesome, eh?
    7985           0 :       MCInst TmpInst;
    7986           0 :       TmpInst.setOpcode(NewOpc);
    7987           0 :       TmpInst.addOperand(Inst.getOperand(0));
    7988           0 :       TmpInst.addOperand(Inst.getOperand(5));
    7989           0 :       TmpInst.addOperand(Inst.getOperand(1));
    7990           0 :       TmpInst.addOperand(Inst.getOperand(2));
    7991           0 :       TmpInst.addOperand(Inst.getOperand(3));
    7992           0 :       TmpInst.addOperand(Inst.getOperand(4));
    7993           0 :       Inst = TmpInst;
    7994           0 :       return true;
    7995             :     }
    7996             :     return false;
    7997             :   }
    7998             : 
    7999             :   // Handle the Thumb2 mode MOV complex aliases.
    8000          30 :   case ARM::t2MOVsr:
    8001             :   case ARM::t2MOVSsr: {
    8002             :     // Which instruction to expand to depends on the CCOut operand and
    8003             :     // whether we're in an IT block if the register operands are low
    8004             :     // registers.
    8005          30 :     bool isNarrow = false;
    8006          60 :     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
    8007          60 :         isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8008          86 :         isARMLowRegister(Inst.getOperand(2).getReg()) &&
    8009          82 :         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
    8010          76 :         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
    8011             :         !HasWideQualifier)
    8012             :       isNarrow = true;
    8013          60 :     MCInst TmpInst;
    8014             :     unsigned newOpc;
    8015          60 :     switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
    8016           0 :     default: llvm_unreachable("unexpected opcode!");
    8017           6 :     case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
    8018           8 :     case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
    8019           8 :     case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
    8020           8 :     case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
    8021             :     }
    8022          60 :     TmpInst.setOpcode(newOpc);
    8023          60 :     TmpInst.addOperand(Inst.getOperand(0)); // Rd
    8024          30 :     if (isNarrow)
    8025          32 :       TmpInst.addOperand(MCOperand::createReg(
    8026          16 :           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
    8027          60 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8028          60 :     TmpInst.addOperand(Inst.getOperand(2)); // Rm
    8029          60 :     TmpInst.addOperand(Inst.getOperand(4)); // CondCode
    8030          60 :     TmpInst.addOperand(Inst.getOperand(5));
    8031          30 :     if (!isNarrow)
    8032          28 :       TmpInst.addOperand(MCOperand::createReg(
    8033          14 :           Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
    8034          30 :     Inst = TmpInst;
    8035          30 :     return true;
    8036             :   }
    8037          30 :   case ARM::t2MOVsi:
    8038             :   case ARM::t2MOVSsi: {
    8039             :     // Which instruction to expand to depends on the CCOut operand and
    8040             :     // whether we're in an IT block if the register operands are low
    8041             :     // registers.
    8042          30 :     bool isNarrow = false;
    8043          57 :     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
    8044          79 :         isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8045          64 :         inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
    8046             :         !HasWideQualifier)
    8047             :       isNarrow = true;
    8048          60 :     MCInst TmpInst;
    8049             :     unsigned newOpc;
    8050          60 :     unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
    8051          60 :     unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
    8052          30 :     bool isMov = false;
    8053             :     // MOV rd, rm, LSL #0 is actually a MOV instruction
    8054          30 :     if (Shift == ARM_AM::lsl && Amount == 0) {
    8055          12 :       isMov = true;
    8056             :       // The 16-bit encoding of MOV rd, rm, LSL #N is explicitly encoding T2 of
    8057             :       // MOV (register) in the ARMv8-A and ARMv8-M manuals, and immediate 0 is
    8058             :       // unpredictable in an IT block so the 32-bit encoding T3 has to be used
    8059             :       // instead.
    8060          12 :       if (inITBlock()) {
    8061             :         isNarrow = false;
    8062             :       }
    8063           4 :       newOpc = isNarrow ? ARM::tMOVSr : ARM::t2MOVr;
    8064             :     } else {
    8065          18 :       switch(Shift) {
    8066           0 :       default: llvm_unreachable("unexpected opcode!");
    8067           4 :       case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
    8068           4 :       case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
    8069           4 :       case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
    8070             :       case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
    8071           2 :       case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
    8072             :       }
    8073             :     }
    8074          30 :     if (Amount == 32) Amount = 0;
    8075          60 :     TmpInst.setOpcode(newOpc);
    8076          60 :     TmpInst.addOperand(Inst.getOperand(0)); // Rd
    8077          30 :     if (isNarrow && !isMov)
    8078           4 :       TmpInst.addOperand(MCOperand::createReg(
    8079           2 :           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
    8080          60 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8081          30 :     if (newOpc != ARM::t2RRX && !isMov)
    8082          48 :       TmpInst.addOperand(MCOperand::createImm(Amount));
    8083          60 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    8084          60 :     TmpInst.addOperand(Inst.getOperand(4));
    8085          30 :     if (!isNarrow)
    8086          56 :       TmpInst.addOperand(MCOperand::createReg(
    8087          28 :           Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
    8088          30 :     Inst = TmpInst;
    8089          30 :     return true;
    8090             :   }
    8091             :   // Handle the ARM mode MOV complex aliases.
    8092           0 :   case ARM::ASRr:
    8093             :   case ARM::LSRr:
    8094             :   case ARM::LSLr:
    8095             :   case ARM::RORr: {
    8096             :     ARM_AM::ShiftOpc ShiftTy;
    8097           0 :     switch(Inst.getOpcode()) {
    8098           0 :     default: llvm_unreachable("unexpected opcode!");
    8099             :     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
    8100           0 :     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
    8101           0 :     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
    8102           0 :     case ARM::RORr: ShiftTy = ARM_AM::ror; break;
    8103             :     }
    8104           0 :     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
    8105           0 :     MCInst TmpInst;
    8106           0 :     TmpInst.setOpcode(ARM::MOVsr);
    8107           0 :     TmpInst.addOperand(Inst.getOperand(0)); // Rd
    8108           0 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8109           0 :     TmpInst.addOperand(Inst.getOperand(2)); // Rm
    8110           0 :     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
    8111           0 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    8112           0 :     TmpInst.addOperand(Inst.getOperand(4));
    8113           0 :     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
    8114           0 :     Inst = TmpInst;
    8115           0 :     return true;
    8116             :   }
    8117          56 :   case ARM::ASRi:
    8118             :   case ARM::LSRi:
    8119             :   case ARM::LSLi:
    8120             :   case ARM::RORi: {
    8121             :     ARM_AM::ShiftOpc ShiftTy;
    8122          56 :     switch(Inst.getOpcode()) {
    8123           0 :     default: llvm_unreachable("unexpected opcode!");
    8124             :     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
    8125          10 :     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
    8126          26 :     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
    8127          10 :     case ARM::RORi: ShiftTy = ARM_AM::ror; break;
    8128             :     }
    8129             :     // A shift by zero is a plain MOVr, not a MOVsi.
    8130          56 :     unsigned Amt = Inst.getOperand(2).getImm();
    8131          56 :     unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
    8132             :     // A shift by 32 should be encoded as 0 when permitted
    8133          56 :     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
    8134           4 :       Amt = 0;
    8135          56 :     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
    8136         112 :     MCInst TmpInst;
    8137         112 :     TmpInst.setOpcode(Opc);
    8138         112 :     TmpInst.addOperand(Inst.getOperand(0)); // Rd
    8139         112 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8140          56 :     if (Opc == ARM::MOVsi)
    8141          72 :       TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
    8142         112 :     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
    8143         112 :     TmpInst.addOperand(Inst.getOperand(4));
    8144         112 :     TmpInst.addOperand(Inst.getOperand(5)); // cc_out
    8145          56 :     Inst = TmpInst;
    8146          56 :     return true;
    8147             :   }
    8148          16 :   case ARM::RRXi: {
    8149          16 :     unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
    8150          32 :     MCInst TmpInst;
    8151          32 :     TmpInst.setOpcode(ARM::MOVsi);
    8152          32 :     TmpInst.addOperand(Inst.getOperand(0)); // Rd
    8153          32 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8154          48 :     TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
    8155          32 :     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
    8156          32 :     TmpInst.addOperand(Inst.getOperand(3));
    8157          32 :     TmpInst.addOperand(Inst.getOperand(4)); // cc_out
    8158          16 :     Inst = TmpInst;
    8159          16 :     return true;
    8160             :   }
    8161          45 :   case ARM::t2LDMIA_UPD: {
    8162             :     // If this is a load of a single register, then we should use
    8163             :     // a post-indexed LDR instruction instead, per the ARM ARM.
    8164          45 :     if (Inst.getNumOperands() != 5)
    8165             :       return false;
    8166           9 :     MCInst TmpInst;
    8167          18 :     TmpInst.setOpcode(ARM::t2LDR_POST);
    8168          18 :     TmpInst.addOperand(Inst.getOperand(4)); // Rt
    8169          18 :     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
    8170          18 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8171          18 :     TmpInst.addOperand(MCOperand::createImm(4));
    8172          18 :     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
    8173          18 :     TmpInst.addOperand(Inst.getOperand(3));
    8174           9 :     Inst = TmpInst;
    8175           9 :     return true;
    8176             :   }
    8177          14 :   case ARM::t2STMDB_UPD: {
    8178             :     // If this is a store of a single register, then we should use
    8179             :     // a pre-indexed STR instruction instead, per the ARM ARM.
    8180          14 :     if (Inst.getNumOperands() != 5)
    8181             :       return false;
    8182           4 :     MCInst TmpInst;
    8183           8 :     TmpInst.setOpcode(ARM::t2STR_PRE);
    8184           8 :     TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
    8185           8 :     TmpInst.addOperand(Inst.getOperand(4)); // Rt
    8186           8 :     TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8187           8 :     TmpInst.addOperand(MCOperand::createImm(-4));
    8188           8 :     TmpInst.addOperand(Inst.getOperand(2)); // CondCode
    8189           8 :     TmpInst.addOperand(Inst.getOperand(3));
    8190           4 :     Inst = TmpInst;
    8191           4 :     return true;
    8192             :   }
    8193          64 :   case ARM::LDMIA_UPD:
    8194             :     // If this is a load of a single register via a 'pop', then we should use
    8195             :     // a post-indexed LDR instruction instead, per the ARM ARM.
    8196         298 :     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
    8197          53 :         Inst.getNumOperands() == 5) {
    8198          24 :       MCInst TmpInst;
    8199          24 :       TmpInst.setOpcode(ARM::LDR_POST_IMM);
    8200          24 :       TmpInst.addOperand(Inst.getOperand(4)); // Rt
    8201          24 :       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
    8202          24 :       TmpInst.addOperand(Inst.getOperand(1)); // Rn
    8203          24 :       TmpInst.addOperand(MCOperand::createReg(0));  // am2offset
    8204          24 :       TmpInst.addOperand(MCOperand::createImm(4));
    8205          24 :       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
    8206          24 :       TmpInst.addOperand(Inst.getOperand(3));
    8207          12 :       Inst = TmpInst;
    8208          12 :       return true;
    8209             :     }
    8210             :     break;
    8211          72 :   case ARM::STMDB_UPD:
    8212             :     // If this is a store of a single register via a 'push', then we should use
    8213             :     // a pre-indexed STR instruction instead, per the ARM ARM.
    8214         330 :     if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
    8215          57 :         Inst.getNumOperands() == 5) {
    8216          30 :       MCInst TmpInst;
    8217          30 :       TmpInst.setOpcode(ARM::STR_PRE_IMM);
    8218          30 :       TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
    8219          30 :       TmpInst.addOperand(Inst.getOperand(4)); // Rt
    8220          30 :       TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
    8221          30 :       TmpInst.addOperand(MCOperand::createImm(-4));
    8222          30 :       TmpInst.addOperand(Inst.getOperand(2)); // CondCode
    8223          30 :       TmpInst.addOperand(Inst.getOperand(3));
    8224          15 :       Inst = TmpInst;
    8225             :     }
    8226             :     break;
    8227          57 :   case ARM::t2ADDri12:
    8228             :     // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
    8229             :     // mnemonic was used (not "addw"), encoding T3 is preferred.
    8230         203 :     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
    8231          16 :         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
    8232             :       break;
    8233          16 :     Inst.setOpcode(ARM::t2ADDri);
    8234          16 :     Inst.addOperand(MCOperand::createReg(0)); // cc_out
    8235           8 :     break;
    8236          55 :   case ARM::t2SUBri12:
    8237             :     // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
    8238             :     // mnemonic was used (not "subw"), encoding T3 is preferred.
    8239         177 :     if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
    8240           6 :         ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
    8241             :       break;
    8242           0 :     Inst.setOpcode(ARM::t2SUBri);
    8243           0 :     Inst.addOperand(MCOperand::createReg(0)); // cc_out
    8244           0 :     break;
    8245          62 :   case ARM::tADDi8:
    8246             :     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
    8247             :     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
    8248             :     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
    8249             :     // to encoding T1 if <Rd> is omitted."
    8250         112 :     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
    8251           0 :       Inst.setOpcode(ARM::tADDi3);
    8252           0 :       return true;
    8253             :     }
    8254             :     break;
    8255          16 :   case ARM::tSUBi8:
    8256             :     // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
    8257             :     // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
    8258             :     // to encoding T2 if <Rd> is specified and encoding T2 is preferred
    8259             :     // to encoding T1 if <Rd> is omitted."
    8260          22 :     if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
    8261           0 :       Inst.setOpcode(ARM::tSUBi3);
    8262           0 :       return true;
    8263             :     }
    8264             :     break;
    8265         191 :   case ARM::t2ADDri:
    8266             :   case ARM::t2SUBri: {
    8267             :     // If the destination and first source operand are the same, and
    8268             :     // the flags are compatible with the current IT status, use encoding T2
    8269             :     // instead of T3. For compatibility with the system 'as'. Make sure the
    8270             :     // wide encoding wasn't explicit.
    8271         382 :     if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
    8272         123 :         !isARMLowRegister(Inst.getOperand(0).getReg()) ||
    8273          77 :         (Inst.getOperand(2).isImm() &&
    8274          72 :          (unsigned)Inst.getOperand(2).getImm() > 255) ||
    8275         241 :         Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) ||
    8276             :         HasWideQualifier)
    8277             :       break;
    8278          16 :     MCInst TmpInst;
    8279          16 :     TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
    8280             :                       ARM::tADDi8 : ARM::tSUBi8);
    8281          16 :     TmpInst.addOperand(Inst.getOperand(0));
    8282          16 :     TmpInst.addOperand(Inst.getOperand(5));
    8283          16 :     TmpInst.addOperand(Inst.getOperand(0));
    8284          16 :     TmpInst.addOperand(Inst.getOperand(2));
    8285          16 :     TmpInst.addOperand(Inst.getOperand(3));
    8286          16 :     TmpInst.addOperand(Inst.getOperand(4));
    8287           8 :     Inst = TmpInst;
    8288           8 :     return true;
    8289             :   }
    8290          72 :   case ARM::t2ADDrr: {
    8291             :     // If the destination and first source operand are the same, and
    8292             :     // there's no setting of the flags, use encoding T2 instead of T3.
    8293             :     // Note that this is only for ADD, not SUB. This mirrors the system
    8294             :     // 'as' behaviour.  Also take advantage of ADD being commutative.
    8295             :     // Make sure the wide encoding wasn't explicit.
    8296          72 :     bool Swap = false;
    8297          72 :     auto DestReg = Inst.getOperand(0).getReg();
    8298          72 :     bool Transform = DestReg == Inst.getOperand(1).getReg();
    8299         121 :     if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
    8300             :       Transform = true;
    8301             :       Swap = true;
    8302             :     }
    8303          53 :     if (!Transform ||
    8304         156 :         Inst.getOperand(5).getReg() != 0 ||
    8305             :         HasWideQualifier)
    8306             :       break;
    8307          24 :     MCInst TmpInst;
    8308          24 :     TmpInst.setOpcode(ARM::tADDhirr);
    8309          24 :     TmpInst.addOperand(Inst.getOperand(0));
    8310          24 :     TmpInst.addOperand(Inst.getOperand(0));
    8311          36 :     TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
    8312          24 :     TmpInst.addOperand(Inst.getOperand(3));
    8313          24 :     TmpInst.addOperand(Inst.getOperand(4));
    8314          12 :     Inst = TmpInst;
    8315          12 :     return true;
    8316             :   }
    8317          16 :   case ARM::tADDrSP: {
    8318             :     // If the non-SP source operand and the destination operand are not the
    8319             :     // same, we need to use the 32-bit encoding if it's available.
    8320          32 :     if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
    8321          12 :       Inst.setOpcode(ARM::t2ADDrr);
    8322          12 :       Inst.addOperand(MCOperand::createReg(0)); // cc_out
    8323           6 :       return true;
    8324             :     }
    8325             :     break;
    8326             :   }
    8327          93 :   case ARM::tB:
    8328             :     // A Thumb conditional branch outside of an IT block is a tBcc.
    8329          93 :     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
    8330           0 :       Inst.setOpcode(ARM::tBcc);
    8331           0 :       return true;
    8332             :     }
    8333             :     break;
    8334          76 :   case ARM::t2B:
    8335             :     // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
    8336          76 :     if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
    8337           0 :       Inst.setOpcode(ARM::t2Bcc);
    8338           0 :       return true;
    8339             :     }
    8340             :     break;
    8341          54 :   case ARM::t2Bcc:
    8342             :     // If the conditional is AL or we're in an IT block, we really want t2B.
    8343          54 :     if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
    8344           0 :       Inst.setOpcode(ARM::t2B);
    8345           0 :       return true;
    8346             :     }
    8347             :     break;
    8348          50 :   case ARM::tBcc:
    8349             :     // If the conditional is AL, we really want tB.
    8350          50 :     if (Inst.getOperand(1).getImm() == ARMCC::AL) {
    8351           0 :       Inst.setOpcode(ARM::tB);
    8352           0 :       return true;
    8353             :     }
    8354             :     break;
    8355          37 :   case ARM::tLDMIA: {
    8356             :     // If the register list contains any high registers, or if the writeback
    8357             :     // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
    8358             :     // instead if we're in Thumb2. Otherwise, this should have generated
    8359             :     // an error in validateInstruction().
    8360          37 :     unsigned Rn = Inst.getOperand(0).getReg();
    8361             :     bool hasWritebackToken =
    8362         148 :         (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
    8363          94 :          static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
    8364             :     bool listContainsBase;
    8365          17 :     if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
    8366          11 :         (!listContainsBase && !hasWritebackToken) ||
    8367           6 :         (listContainsBase && hasWritebackToken)) {
    8368             :       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
    8369             :       assert (isThumbTwo());
    8370          54 :       Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
    8371             :       // If we're switching to the updating version, we need to insert
    8372             :       // the writeback tied operand.
    8373          27 :       if (hasWritebackToken)
    8374          30 :         Inst.insert(Inst.begin(),
    8375          45 :                     MCOperand::createReg(Inst.getOperand(0).getReg()));
    8376             :       return true;
    8377             :     }
    8378             :     break;
    8379             :   }
    8380          18 :   case ARM::tSTMIA_UPD: {
    8381             :     // If the register list contains any high registers, we need to use
    8382             :     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
    8383             :     // should have generated an error in validateInstruction().
    8384          18 :     unsigned Rn = Inst.getOperand(0).getReg();
    8385             :     bool listContainsBase;
    8386          10 :     if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
    8387             :       // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
    8388             :       assert (isThumbTwo());
    8389          20 :       Inst.setOpcode(ARM::t2STMIA_UPD);
    8390          10 :       return true;
    8391             :     }
    8392             :     break;
    8393             :   }
    8394             :   case ARM::tPOP: {
    8395             :     bool listContainsBase;
    8396             :     // If the register list contains any high registers, we need to use
    8397             :     // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
    8398             :     // should have generated an error in validateInstruction().
    8399          38 :     if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
    8400             :       return false;
    8401             :     assert (isThumbTwo());
    8402          32 :     Inst.setOpcode(ARM::t2LDMIA_UPD);
    8403             :     // Add the base register and writeback operands.
    8404          48 :     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
    8405          48 :     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
    8406          16 :     return true;
    8407             :   }
    8408             :   case ARM::tPUSH: {
    8409             :     bool listContainsBase;
    8410          32 :     if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
    8411             :       return false;
    8412             :     assert (isThumbTwo());
    8413          10 :     Inst.setOpcode(ARM::t2STMDB_UPD);
    8414             :     // Add the base register and writeback operands.
    8415          15 :     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
    8416          15 :     Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
    8417           5 :     return true;
    8418             :   }
    8419          86 :   case ARM::t2MOVi: {
    8420             :     // If we can use the 16-bit encoding and the user didn't explicitly
    8421             :     // request the 32-bit variant, transform it here.
    8422         252 :     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
    8423         164 :         (Inst.getOperand(1).isImm() &&
    8424         142 :          (unsigned)Inst.getOperand(1).getImm() <= 255) &&
    8425          91 :         Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
    8426             :         !HasWideQualifier) {
    8427             :       // The operands aren't in the same order for tMOVi8...
    8428          50 :       MCInst TmpInst;
    8429          50 :       TmpInst.setOpcode(ARM::tMOVi8);
    8430          50 :       TmpInst.addOperand(Inst.getOperand(0));
    8431          50 :       TmpInst.addOperand(Inst.getOperand(4));
    8432          50 :       TmpInst.addOperand(Inst.getOperand(1));
    8433          50 :       TmpInst.addOperand(Inst.getOperand(2));
    8434          50 :       TmpInst.addOperand(Inst.getOperand(3));
    8435          25 :       Inst = TmpInst;
    8436          25 :       return true;
    8437             :     }
    8438             :     break;
    8439             :   }
    8440          52 :   case ARM::t2MOVr: {
    8441             :     // If we can use the 16-bit encoding and the user didn't explicitly
    8442             :     // request the 32-bit variant, transform it here.
    8443          89 :     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
    8444          95 :         isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8445          40 :         Inst.getOperand(2).getImm() == ARMCC::AL &&
    8446          20 :         Inst.getOperand(4).getReg() == ARM::CPSR &&
    8447             :         !HasWideQualifier) {
    8448             :       // The operands aren't the same for tMOV[S]r... (no cc_out)
    8449          18 :       MCInst TmpInst;
    8450          18 :       TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
    8451          18 :       TmpInst.addOperand(Inst.getOperand(0));
    8452          18 :       TmpInst.addOperand(Inst.getOperand(1));
    8453          18 :       TmpInst.addOperand(Inst.getOperand(2));
    8454          18 :       TmpInst.addOperand(Inst.getOperand(3));
    8455           9 :       Inst = TmpInst;
    8456           9 :       return true;
    8457             :     }
    8458             :     break;
    8459             :   }
    8460          66 :   case ARM::t2SXTH:
    8461             :   case ARM::t2SXTB:
    8462             :   case ARM::t2UXTH:
    8463             :   case ARM::t2UXTB: {
    8464             :     // If we can use the 16-bit encoding and the user didn't explicitly
    8465             :     // request the 32-bit variant, transform it here.
    8466         118 :     if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
    8467         100 :         isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8468          36 :         Inst.getOperand(2).getImm() == 0 &&
    8469             :         !HasWideQualifier) {
    8470             :       unsigned NewOpc;
    8471          12 :       switch (Inst.getOpcode()) {
    8472           0 :       default: llvm_unreachable("Illegal opcode!");
    8473             :       case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
    8474           4 :       case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
    8475           2 :       case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
    8476           2 :       case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
    8477             :       }
    8478             :       // The operands aren't the same for thumb1 (no rotate operand).
    8479          24 :       MCInst TmpInst;
    8480          24 :       TmpInst.setOpcode(NewOpc);
    8481          24 :       TmpInst.addOperand(Inst.getOperand(0));
    8482          24 :       TmpInst.addOperand(Inst.getOperand(1));
    8483          24 :       TmpInst.addOperand(Inst.getOperand(3));
    8484          24 :       TmpInst.addOperand(Inst.getOperand(4));
    8485          12 :       Inst = TmpInst;
    8486          12 :       return true;
    8487             :     }
    8488             :     break;
    8489             :   }
    8490          64 :   case ARM::MOVsi: {
    8491         128 :     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
    8492             :     // rrx shifts and asr/lsr of #32 is encoded as 0
    8493          64 :     if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 
    8494             :       return false;
    8495          68 :     if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
    8496             :       // Shifting by zero is accepted as a vanilla 'MOVr'
    8497          44 :       MCInst TmpInst;
    8498          44 :       TmpInst.setOpcode(ARM::MOVr);
    8499          44 :       TmpInst.addOperand(Inst.getOperand(0));
    8500          44 :       TmpInst.addOperand(Inst.getOperand(1));
    8501          44 :       TmpInst.addOperand(Inst.getOperand(3));
    8502          44 :       TmpInst.addOperand(Inst.getOperand(4));
    8503          44 :       TmpInst.addOperand(Inst.getOperand(5));
    8504          22 :       Inst = TmpInst;
    8505          22 :       return true;
    8506             :     }
    8507             :     return false;
    8508             :   }
    8509         179 :   case ARM::ANDrsi:
    8510             :   case ARM::ORRrsi:
    8511             :   case ARM::EORrsi:
    8512             :   case ARM::BICrsi:
    8513             :   case ARM::SUBrsi:
    8514             :   case ARM::ADDrsi: {
    8515             :     unsigned newOpc;
    8516         358 :     ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
    8517         179 :     if (SOpc == ARM_AM::rrx) return false;
    8518         155 :     switch (Inst.getOpcode()) {
    8519           0 :     default: llvm_unreachable("unexpected opcode!");
    8520             :     case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
    8521          27 :     case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
    8522          25 :     case ARM::EORrsi: newOpc = ARM::EORrr; break;
    8523          27 :     case ARM::BICrsi: newOpc = ARM::BICrr; break;
    8524          25 :     case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
    8525          26 :     case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
    8526             :     }
    8527             :     // If the shift is by zero, use the non-shifted instruction definition.
    8528             :     // The exception is for right shifts, where 0 == 32
    8529         340 :     if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
    8530          30 :         !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
    8531          12 :       MCInst TmpInst;
    8532          12 :       TmpInst.setOpcode(newOpc);
    8533          12 :       TmpInst.addOperand(Inst.getOperand(0));
    8534          12 :       TmpInst.addOperand(Inst.getOperand(1));
    8535          12 :       TmpInst.addOperand(Inst.getOperand(2));
    8536          12 :       TmpInst.addOperand(Inst.getOperand(4));
    8537          12 :       TmpInst.addOperand(Inst.getOperand(5));
    8538          12 :       TmpInst.addOperand(Inst.getOperand(6));
    8539           6 :       Inst = TmpInst;
    8540           6 :       return true;
    8541             :     }
    8542             :     return false;
    8543             :   }
    8544        2758 :   case ARM::ITasm:
    8545             :   case ARM::t2IT: {
    8546        2758 :     MCOperand &MO = Inst.getOperand(1);
    8547        2758 :     unsigned Mask = MO.getImm();
    8548        2758 :     ARMCC::CondCodes Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
    8549             : 
    8550             :     // Set up the IT block state according to the IT instruction we just
    8551             :     // matched.
    8552             :     assert(!inITBlock() && "nested IT blocks?!");
    8553        2758 :     startExplicitITBlock(Cond, Mask);
    8554        2758 :     MO.setImm(getITMaskEncoding());
    8555             :     break;
    8556             :   }
    8557         251 :   case ARM::t2LSLrr:
    8558             :   case ARM::t2LSRrr:
    8559             :   case ARM::t2ASRrr:
    8560             :   case ARM::t2SBCrr:
    8561             :   case ARM::t2RORrr:
    8562             :   case ARM::t2BICrr:
    8563             :   {
    8564             :     // Assemblers should use the narrow encodings of these instructions when permissible.
    8565         451 :     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8566         524 :          isARMLowRegister(Inst.getOperand(2).getReg())) &&
    8567         391 :         Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
    8568         120 :         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
    8569             :         !HasWideQualifier) {
    8570             :       unsigned NewOpc;
    8571          30 :       switch (Inst.getOpcode()) {
    8572           0 :         default: llvm_unreachable("unexpected opcode");
    8573             :         case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
    8574           5 :         case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
    8575           5 :         case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
    8576           5 :         case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
    8577           5 :         case ARM::t2RORrr: NewOpc = ARM::tROR; break;
    8578           5 :         case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
    8579             :       }
    8580          60 :       MCInst TmpInst;
    8581          60 :       TmpInst.setOpcode(NewOpc);
    8582          60 :       TmpInst.addOperand(Inst.getOperand(0));
    8583          60 :       TmpInst.addOperand(Inst.getOperand(5));
    8584          60 :       TmpInst.addOperand(Inst.getOperand(1));
    8585          60 :       TmpInst.addOperand(Inst.getOperand(2));
    8586          60 :       TmpInst.addOperand(Inst.getOperand(3));
    8587          60 :       TmpInst.addOperand(Inst.getOperand(4));
    8588          30 :       Inst = TmpInst;
    8589          30 :       return true;
    8590             :     }
    8591             :     return false;
    8592             :   }
    8593         238 :   case ARM::t2ANDrr:
    8594             :   case ARM::t2EORrr:
    8595             :   case ARM::t2ADCrr:
    8596             :   case ARM::t2ORRrr:
    8597             :   {
    8598             :     // Assemblers should use the narrow encodings of these instructions when permissible.
    8599             :     // These instructions are special in that they are commutable, so shorter encodings
    8600             :     // are available more often.
    8601         408 :     if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8602         472 :          isARMLowRegister(Inst.getOperand(2).getReg())) &&
    8603         412 :         (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
    8604         351 :          Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
    8605         219 :         Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
    8606             :         !HasWideQualifier) {
    8607             :       unsigned NewOpc;
    8608          40 :       switch (Inst.getOpcode()) {
    8609           0 :         default: llvm_unreachable("unexpected opcode");
    8610             :         case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
    8611          10 :         case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
    8612          10 :         case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
    8613          10 :         case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
    8614             :       }
    8615          80 :       MCInst TmpInst;
    8616          80 :       TmpInst.setOpcode(NewOpc);
    8617          80 :       TmpInst.addOperand(Inst.getOperand(0));
    8618          80 :       TmpInst.addOperand(Inst.getOperand(5));
    8619          80 :       if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
    8620          40 :         TmpInst.addOperand(Inst.getOperand(1));
    8621          20 :         TmpInst.addOperand(Inst.getOperand(2));
    8622             :       } else {
    8623          40 :         TmpInst.addOperand(Inst.getOperand(2));
    8624          20 :         TmpInst.addOperand(Inst.getOperand(1));
    8625             :       }
    8626          80 :       TmpInst.addOperand(Inst.getOperand(3));
    8627          80 :       TmpInst.addOperand(Inst.getOperand(4));
    8628          40 :       Inst = TmpInst;
    8629          40 :       return true;
    8630             :     }
    8631             :     return false;
    8632             :   }
    8633             :   }
    8634             :   return false;
    8635             : }
    8636             : 
    8637       20310 : unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
    8638             :   // 16-bit thumb arithmetic instructions either require or preclude the 'S'
    8639             :   // suffix depending on whether they're in an IT block or not.
    8640       20310 :   unsigned Opc = Inst.getOpcode();
    8641       40620 :   const MCInstrDesc &MCID = MII.get(Opc);
    8642       20310 :   if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
    8643             :     assert(MCID.hasOptionalDef() &&
    8644             :            "optionally flag setting instruction missing optional def operand");
    8645             :     assert(MCID.NumOperands == Inst.getNumOperands() &&
    8646             :            "operand count mismatch!");
    8647             :     // Find the optional-def operand (cc_out).
    8648             :     unsigned OpNo;
    8649         816 :     for (OpNo = 0;
    8650        1632 :          !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
    8651             :          ++OpNo)
    8652             :       ;
    8653             :     // If we're parsing Thumb1, reject it completely.
    8654        1120 :     if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
    8655             :       return Match_RequiresFlagSetting;
    8656             :     // If we're parsing Thumb2, which form is legal depends on whether we're
    8657             :     // in an IT block.
    8658        1565 :     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
    8659         239 :         !inITBlock())
    8660             :       return Match_RequiresITBlock;
    8661        1427 :     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
    8662         273 :         inITBlock())
    8663             :       return Match_RequiresNotITBlock;
    8664             :     // LSL with zero immediate is not allowed in an IT block
    8665         730 :     if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock())
    8666             :       return Match_RequiresNotITBlock;
    8667       19494 :   } else if (isThumbOne()) {
    8668             :     // Some high-register supporting Thumb1 encodings only allow both registers
    8669             :     // to be from r0-r7 when in Thumb2.
    8670          10 :     if (Opc == ARM::tADDhirr && !hasV6MOps() &&
    8671         518 :         isARMLowRegister(Inst.getOperand(1).getReg()) &&
    8672           3 :         isARMLowRegister(Inst.getOperand(2).getReg()))
    8673             :       return Match_RequiresThumb2;
    8674             :     // Others only require ARMv6 or later.
    8675          39 :     else if (Opc == ARM::tMOVr && !hasV6Ops() &&
    8676         546 :              isARMLowRegister(Inst.getOperand(0).getReg()) &&
    8677           2 :              isARMLowRegister(Inst.getOperand(1).getReg()))
    8678             :       return Match_RequiresV6;
    8679             :   }
    8680             : 
    8681             :   // Before ARMv8 the rules for when SP is allowed in t2MOVr are more complex
    8682             :   // than the loop below can handle, so it uses the GPRnopc register class and
    8683             :   // we do SP handling here.
    8684       20244 :   if (Opc == ARM::t2MOVr && !hasV8Ops())
    8685             :   {
    8686             :     // SP as both source and destination is not allowed
    8687          40 :     if (Inst.getOperand(0).getReg() == ARM::SP &&
    8688          10 :         Inst.getOperand(1).getReg() == ARM::SP)
    8689             :       return Match_RequiresV8;
    8690             :     // When flags-setting SP as either source or destination is not allowed
    8691          42 :     if (Inst.getOperand(4).getReg() == ARM::CPSR &&
    8692          31 :         (Inst.getOperand(0).getReg() == ARM::SP ||
    8693          14 :          Inst.getOperand(1).getReg() == ARM::SP))
    8694             :       return Match_RequiresV8;
    8695             :   }
    8696             : 
    8697      206980 :   for (unsigned I = 0; I < MCID.NumOperands; ++I)
    8698       93410 :     if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
    8699             :       // rGPRRegClass excludes PC, and also excluded SP before ARMv8
    8700        8211 :       if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
    8701             :         return Match_RequiresV8;
    8702        8196 :       else if (Inst.getOperand(I).getReg() == ARM::PC)
    8703             :         return Match_InvalidOperand;
    8704             :     }
    8705             : 
    8706             :   return Match_Success;
    8707             : }
    8708             : 
    8709             : namespace llvm {
    8710             : template <> inline bool IsCPSRDead<MCInst>(const MCInst *Instr) {
    8711             :   return true; // In an assembly source, no need to second-guess
    8712             : }
    8713             : }
    8714             : 
    8715             : // Returns true if Inst is unpredictable if it is in and IT block, but is not
    8716             : // the last instruction in the block.
    8717         356 : bool ARMAsmParser::isITBlockTerminator(MCInst &Inst) const {
    8718         712 :   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
    8719             : 
    8720             :   // All branch & call instructions terminate IT blocks with the exception of
    8721             :   // SVC.
    8722         669 :   if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
    8723        1018 :       MCID.isReturn() || MCID.isBranch() || MCID.isIndirectBranch())
    8724             :     return true;
    8725             : 
    8726             :   // Any arithmetic instruction which writes to the PC also terminates the IT
    8727             :   // block.
    8728        1029 :   for (unsigned OpIdx = 0; OpIdx < MCID.getNumDefs(); ++OpIdx) {
    8729         363 :     MCOperand &Op = Inst.getOperand(OpIdx);
    8730         363 :     if (Op.isReg() && Op.getReg() == ARM::PC)
    8731             :       return true;
    8732             :   }
    8733             : 
    8734         317 :   if (MCID.hasImplicitDefOfPhysReg(ARM::PC, MRI))
    8735             :     return true;
    8736             : 
    8737             :   // Instructions with variable operand lists, which write to the variable
    8738             :   // operands. We only care about Thumb instructions here, as ARM instructions
    8739             :   // obviously can't be in an IT block.
    8740         317 :   switch (Inst.getOpcode()) {
    8741          12 :   case ARM::tLDMIA:
    8742             :   case ARM::t2LDMIA:
    8743             :   case ARM::t2LDMIA_UPD:
    8744             :   case ARM::t2LDMDB:
    8745             :   case ARM::t2LDMDB_UPD:
    8746          12 :     if (listContainsReg(Inst, 3, ARM::PC))
    8747             :       return true;
    8748             :     break;
    8749           7 :   case ARM::tPOP:
    8750           7 :     if (listContainsReg(Inst, 2, ARM::PC))
    8751             :       return true;
    8752             :     break;
    8753             :   }
    8754             : 
    8755             :   return false;
    8756             : }
    8757             : 
    8758       23918 : unsigned ARMAsmParser::MatchInstruction(OperandVector &Operands, MCInst &Inst,
    8759             :                                           uint64_t &ErrorInfo,
    8760             :                                           bool MatchingInlineAsm,
    8761             :                                           bool &EmitInITBlock,
    8762             :                                           MCStreamer &Out) {
    8763             :   // If we can't use an implicit IT block here, just match as normal.
    8764       20871 :   if (inExplicitITBlock() || !isThumbTwo() || !useImplicitITThumb())
    8765       23805 :     return MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
    8766             : 
    8767             :   // Try to match the instruction in an extension of the current IT block (if
    8768             :   // there is one).
    8769          29 :   if (inImplicitITBlock()) {
    8770          58 :     extendImplicitITBlock(ITState.Cond);
    8771          29 :     if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
    8772             :             Match_Success) {
    8773             :       // The match succeded, but we still have to check that the instruction is
    8774             :       // valid in this implicit IT block.
    8775          58 :       const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
    8776          29 :       if (MCID.isPredicable()) {
    8777             :         ARMCC::CondCodes InstCond =
    8778          50 :             (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
    8779          25 :                 .getImm();
    8780          25 :         ARMCC::CondCodes ITCond = currentITCond();
    8781          25 :         if (InstCond == ITCond) {
    8782          15 :           EmitInITBlock = true;
    8783          15 :           return Match_Success;
    8784          10 :         } else if (InstCond == ARMCC::getOppositeCondition(ITCond)) {
    8785           5 :           invertCurrentITCondition();
    8786           5 :           EmitInITBlock = true;
    8787           5 :           return Match_Success;
    8788             :         }
    8789             :       }
    8790             :     }
    8791             :     rewindImplicitITPosition();
    8792             :   }
    8793             : 
    8794             :   // Finish the current IT block, and try to match outside any IT block.
    8795          93 :   flushPendingInstructions(Out);
    8796             :   unsigned PlainMatchResult =
    8797          93 :       MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
    8798          93 :   if (PlainMatchResult == Match_Success) {
    8799         186 :     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
    8800          93 :     if (MCID.isPredicable()) {
    8801             :       ARMCC::CondCodes InstCond =
    8802         160 :           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
    8803          80 :               .getImm();
    8804             :       // Some forms of the branch instruction have their own condition code
    8805             :       // fields, so can be conditionally executed without an IT block.
    8806          80 :       if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
    8807           4 :         EmitInITBlock = false;
    8808           4 :         return Match_Success;
    8809             :       }
    8810          76 :       if (InstCond == ARMCC::AL) {
    8811           4 :         EmitInITBlock = false;
    8812           4 :         return Match_Success;
    8813             :       }
    8814             :     } else {
    8815          13 :       EmitInITBlock = false;
    8816          13 :       return Match_Success;
    8817             :     }
    8818             :   }
    8819             : 
    8820             :   // Try to match in a new IT block. The matcher doesn't check the actual
    8821             :   // condition, so we create an IT block with a dummy condition, and fix it up
    8822             :   // once we know the actual condition.
    8823          72 :   startImplicitITBlock();
    8824          72 :   if (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm) ==
    8825             :       Match_Success) {
    8826         144 :     const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
    8827          72 :     if (MCID.isPredicable()) {
    8828          72 :       ITState.Cond =
    8829         144 :           (ARMCC::CondCodes)Inst.getOperand(MCID.findFirstPredOperandIdx())
    8830             :               .getImm();
    8831          72 :       EmitInITBlock = true;
    8832          72 :       return Match_Success;
    8833             :     }
    8834             :   }
    8835           0 :   discardImplicitITBlock();
    8836             : 
    8837             :   // If none of these succeed, return the error we got when trying to match
    8838             :   // outside any IT blocks.
    8839           0 :   EmitInITBlock = false;
    8840           0 :   return PlainMatchResult;
    8841             : }
    8842             : 
    8843             : std::string ARMMnemonicSpellCheck(StringRef S, uint64_t FBS);
    8844             : 
    8845             : static const char *getSubtargetFeatureName(uint64_t Val);
    8846       23918 : bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
    8847             :                                            OperandVector &Operands,
    8848             :                                            MCStreamer &Out, uint64_t &ErrorInfo,
    8849             :                                            bool MatchingInlineAsm) {
    8850       47836 :   MCInst Inst;
    8851             :   unsigned MatchResult;
    8852       23918 :   bool PendConditionalInstruction = false;
    8853             : 
    8854       23918 :   MatchResult = MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
    8855             :                                  PendConditionalInstruction, Out);
    8856             : 
    8857       23918 :   SMLoc ErrorLoc;
    8858       47836 :   if (ErrorInfo < Operands.size()) {
    8859       61480 :     ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
    8860       15370 :     if (ErrorLoc == SMLoc())
    8861           0 :       ErrorLoc = IDLoc;
    8862             :   }
    8863             : 
    8864       23918 :   switch (MatchResult) {
    8865       20090 :   case Match_Success:
    8866             :     // Context sensitive operand constraints aren't handled by the matcher,
    8867             :     // so check them here.
    8868       20090 :     if (validateInstruction(Inst, Operands)) {
    8869             :       // Still progress the IT block, otherwise one wrong condition causes
    8870             :       // nasty cascading errors.
    8871             :       forwardITPosition();
    8872             :       return true;
    8873             :     }
    8874             : 
    8875             :     { // processInstruction() updates inITBlock state, we need to save it away
    8876       19749 :       bool wasInITBlock = inITBlock();
    8877             : 
    8878             :       // Some instructions need post-processing to, for example, tweak which
    8879             :       // encoding is selected. Loop on it while changes happen so the
    8880             :       // individual transformations can chain off each other. E.g.,
    8881             :       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
    8882       21313 :       while (processInstruction(Inst, Operands, Out))
    8883             :         ;
    8884             : 
    8885             :       // Only after the instruction is fully processed, we can validate it
    8886       27238 :       if (wasInITBlock && hasV8Ops() && isThumb() &&
    8887        2211 :           !isV8EligibleForIT(&Inst)) {
    8888        6456 :         Warning(IDLoc, "deprecated instruction in IT block");
    8889             :       }
    8890             :     }
    8891             : 
    8892             :     // Only move forward at the very end so that everything in validate
    8893             :     // and process gets a consistent answer about whether we're in an IT
    8894             :     // block.
    8895       19749 :     forwardITPosition();
    8896             : 
    8897             :     // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
    8898             :     // doesn't actually encode.
    8899       19749 :     if (Inst.getOpcode() == ARM::ITasm)
    8900             :       return false;
    8901             : 
    8902       19699 :     Inst.setLoc(IDLoc);
    8903       19699 :     if (PendConditionalInstruction) {
    8904          92 :       PendingConditionalInsts.push_back(Inst);
    8905          88 :       if (isITBlockFull() || isITBlockTerminator(Inst))
    8906          34 :         flushPendingInstructions(Out);
    8907             :     } else {
    8908       19607 :       Out.EmitInstruction(Inst, getSTI());
    8909             :     }
    8910             :     return false;
    8911             :   case Match_MissingFeature: {
    8912             :     assert(ErrorInfo && "Unknown missing feature!");
    8913             :     // Special case the error message for the very common case where only
    8914             :     // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
    8915        5721 :     std::string Msg = "instruction requires:";
    8916        1907 :     uint64_t Mask = 1;
    8917      122048 :     for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
    8918      120141 :       if (ErrorInfo & Mask) {
    8919        2029 :         Msg += " ";
    8920        2029 :         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
    8921             :       }
    8922      120141 :       Mask <<= 1;
    8923             :     }
    8924        5721 :     return Error(IDLoc, Msg);
    8925             :   }
    8926         353 :   case Match_InvalidOperand: {
    8927         353 :     SMLoc ErrorLoc = IDLoc;
    8928         353 :     if (ErrorInfo != ~0ULL) {
    8929         706 :       if (ErrorInfo >= Operands.size())
    8930          30 :         return Error(IDLoc, "too few operands for instruction");
    8931             : 
    8932        1372 :       ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
    8933         343 :       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
    8934             :     }
    8935             : 
    8936        1029 :     return Error(ErrorLoc, "invalid operand for instruction");
    8937             :   }
    8938          26 :   case Match_MnemonicFail: {
    8939          52 :     uint64_t FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
    8940             :     std::string Suggestion = ARMMnemonicSpellCheck(
    8941         130 :       ((ARMOperand &)*Operands[0]).getToken(), FBS);
    8942         104 :     return Error(IDLoc, "invalid instruction" + Suggestion,
    8943         104 :                  ((ARMOperand &)*Operands[0]).getLocRange());
    8944             :   }
    8945           0 :   case Match_RequiresNotITBlock:
    8946           0 :     return Error(IDLoc, "flag setting instruction only valid outside IT block");
    8947           0 :   case Match_RequiresITBlock:
    8948           0 :     return Error(IDLoc, "instruction only valid inside IT block");
    8949           1 :   case Match_RequiresV6:
    8950           3 :     return Error(IDLoc, "instruction variant requires ARMv6 or later");
    8951           2 :   case Match_RequiresThumb2:
    8952           6 :     return Error(IDLoc, "instruction variant requires Thumb2");
    8953          14 :   case Match_RequiresV8:
    8954          42 :     return Error(IDLoc, "instruction variant requires ARMv8 or later");
    8955           2 :   case Match_RequiresFlagSetting:
    8956           6 :     return Error(IDLoc, "no flag-preserving variant of this instruction available");
    8957          12 :   case Match_ImmRange0_1:
    8958          36 :     return Error(ErrorLoc, "immediate operand must be in the range [0,1]");
    8959           0 :   case Match_ImmRange0_3:
    8960           0 :     return Error(ErrorLoc, "immediate operand must be in the range [0,3]");
    8961          29 :   case Match_ImmRange0_7:
    8962          87 :     return Error(ErrorLoc, "immediate operand must be in the range [0,7]");
    8963          13 :   case Match_ImmRange0_15:
    8964          39 :     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
    8965          10 :   case Match_ImmRange0_31:
    8966          30 :     return Error(ErrorLoc, "immediate operand must be in the range [0,31]");
    8967           4 :   case Match_ImmRange0_32:
    8968          12 :     return Error(ErrorLoc, "immediate operand must be in the range [0,32]");
    8969           0 :   case Match_ImmRange0_63:
    8970           0 :     return Error(ErrorLoc, "immediate operand must be in the range [0,63]");
    8971           4 :   case Match_ImmRange0_239:
    8972          12 :     return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
    8973           4 :   case Match_ImmRange0_255:
    8974          12 :     return Error(ErrorLoc, "immediate operand must be in the range [0,255]");
    8975           0 :   case Match_ImmRange0_4095:
    8976           0 :     return Error(ErrorLoc, "immediate operand must be in the range [0,4095]");
    8977          20 :   case Match_ImmRange0_65535:
    8978          60 :     return Error(ErrorLoc, "immediate operand must be in the range [0,65535]");
    8979           0 :   case Match_ImmRange1_7:
    8980           0 :     return Error(ErrorLoc, "immediate operand must be in the range [1,7]");
    8981           0 :   case Match_ImmRange1_8:
    8982           0 :     return Error(ErrorLoc, "immediate operand must be in the range [1,8]");
    8983           0 :   case Match_ImmRange1_15:
    8984           0 :     return Error(ErrorLoc, "immediate operand must be in the range [1,15]");
    8985           4 :   case Match_ImmRange1_16:
    8986          12 :     return Error(ErrorLoc, "immediate operand must be in the range [1,16]");
    8987           0 :   case Match_ImmRange1_31:
    8988           0 :     return Error(ErrorLoc, "immediate operand must be in the range [1,31]");
    8989           4 :   case Match_ImmRange1_32:
    8990          12 :     return Error(ErrorLoc, "immediate operand must be in the range [1,32]");
    8991           0 :   case Match_ImmRange1_64:
    8992           0 :     return Error(ErrorLoc, "immediate operand must be in the range [1,64]");
    8993           0 :   case Match_ImmRange8_8:
    8994           0 :     return Error(ErrorLoc, "immediate operand must be 8.");
    8995           0 :   case Match_ImmRange16_16:
    8996           0 :     return Error(ErrorLoc, "immediate operand must be 16.");
    8997           0 :   case Match_ImmRange32_32:
    8998           0 :     return Error(ErrorLoc, "immediate operand must be 32.");
    8999           0 :   case Match_ImmRange256_65535:
    9000           0 :     return Error(ErrorLoc, "immediate operand must be in the range [255,65535]");
    9001           6 :   case Match_ImmRange0_16777215:
    9002          18 :     return Error(ErrorLoc, "immediate operand must be in the range [0,0xffffff]");
    9003        1413 :   case Match_AlignedMemoryRequiresNone:
    9004             :   case Match_DupAlignedMemoryRequiresNone:
    9005             :   case Match_AlignedMemoryRequires16:
    9006             :   case Match_DupAlignedMemoryRequires16:
    9007             :   case Match_AlignedMemoryRequires32:
    9008             :   case Match_DupAlignedMemoryRequires32:
    9009             :   case Match_AlignedMemoryRequires64:
    9010             :   case Match_DupAlignedMemoryRequires64:
    9011             :   case Match_AlignedMemoryRequires64or128:
    9012             :   case Match_DupAlignedMemoryRequires64or128:
    9013             :   case Match_AlignedMemoryRequires64or128or256:
    9014             :   {
    9015        4239 :     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
    9016        1413 :     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
    9017        1413 :     switch (MatchResult) {
    9018           0 :       default:
    9019           0 :         llvm_unreachable("Missing Match_Aligned type");
    9020         300 :       case Match_AlignedMemoryRequiresNone:
    9021             :       case Match_DupAlignedMemoryRequiresNone:
    9022         900 :         return Error(ErrorLoc, "alignment must be omitted");
    9023          96 :       case Match_AlignedMemoryRequires16:
    9024             :       case Match_DupAlignedMemoryRequires16:
    9025         288 :         return Error(ErrorLoc, "alignment must be 16 or omitted");
    9026         156 :       case Match_AlignedMemoryRequires32:
    9027             :       case Match_DupAlignedMemoryRequires32:
    9028         468 :         return Error(ErrorLoc, "alignment must be 32 or omitted");
    9029         480 :       case Match_AlignedMemoryRequires64:
    9030             :       case Match_DupAlignedMemoryRequires64:
    9031        1440 :         return Error(ErrorLoc, "alignment must be 64 or omitted");
    9032         231 :       case Match_AlignedMemoryRequires64or128:
    9033             :       case Match_DupAlignedMemoryRequires64or128:
    9034         693 :         return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
    9035         150 :       case Match_AlignedMemoryRequires64or128or256:
    9036         450 :         return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
    9037             :     }
    9038             :   }
    9039             :   }
    9040             : 
    9041           0 :   llvm_unreachable("Implement any new match types added!");
    9042             : }
    9043             : 
    9044             : /// parseDirective parses the arm specific directives
    9045        7578 : bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
    9046             :   const MCObjectFileInfo::Environment Format =
    9047       15156 :     getContext().getObjectFileInfo()->getObjectFileType();
    9048        7578 :   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
    9049        7578 :   bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
    9050             : 
    9051        7578 :   StringRef IDVal = DirectiveID.getIdentifier();
    9052        9841 :   if (IDVal == ".word")
    9053        2263 :     parseLiteralValues(4, DirectiveID.getLoc());
    9054       10606 :   else if (IDVal == ".short" || IDVal == ".hword")
    9055          32 :     parseLiteralValues(2, DirectiveID.getLoc());
    9056        5404 :   else if (IDVal == ".thumb")
    9057         121 :     parseDirectiveThumb(DirectiveID.getLoc());
    9058        5229 :   else if (IDVal == ".arm")
    9059          67 :     parseDirectiveARM(DirectiveID.getLoc());
    9060        5218 :   else if (IDVal == ".thumb_func")
    9061         123 :     parseDirectiveThumbFunc(DirectiveID.getLoc());
    9062        5088 :   else if (IDVal == ".code")
    9063         116 :     parseDirectiveCode(DirectiveID.getLoc());
    9064        5176 :   else if (IDVal == ".syntax")
    9065         320 :     parseDirectiveSyntax(DirectiveID.getLoc());
    9066        4543 :   else if (IDVal == ".unreq")
    9067           7 :     parseDirectiveUnreq(DirectiveID.getLoc());
    9068        4740 :   else if (IDVal == ".fnend")
    9069         211 :     parseDirectiveFnEnd(DirectiveID.getLoc());
    9070        4365 :   else if (IDVal == ".cantunwind")
    9071          47 :     parseDirectiveCantUnwind(DirectiveID.getLoc());
    9072        4349 :   else if (IDVal == ".personality")
    9073          78 :     parseDirectivePersonality(DirectiveID.getLoc());
    9074        4270 :   else if (IDVal == ".handlerdata")
    9075          77 :     parseDirectiveHandlerData(DirectiveID.getLoc());
    9076        4154 :   else if (IDVal == ".setfp")
    9077          38 :     parseDirectiveSetFP(DirectiveID.getLoc());
    9078        4107 :   else if (IDVal == ".pad")
    9079          29 :     parseDirectivePad(DirectiveID.getLoc());
    9080        4092 :   else if (IDVal == ".save")
    9081          43 :     parseDirectiveRegSave(DirectiveID.getLoc(), false);
    9082        4023 :   else if (IDVal == ".vsave")
    9083          17 :     parseDirectiveRegSave(DirectiveID.getLoc(), true);
    9084        7935 :   else if (IDVal == ".ltorg" || IDVal == ".pool")
    9085          48 :     parseDirectiveLtorg(DirectiveID.getLoc());
    9086        3949 :   else if (IDVal == ".even")
    9087           8 :     parseDirectiveEven(DirectiveID.getLoc());
    9088        3952 :   else if (IDVal == ".personalityindex")
    9089          19 :     parseDirectivePersonalityIndex(DirectiveID.getLoc());
    9090        3978 :   else if (IDVal == ".unwind_raw")
    9091          64 :     parseDirectiveUnwindRaw(DirectiveID.getLoc());
    9092        3863 :   else if (IDVal == ".movsp")
    9093          13 :     parseDirectiveMovSP(DirectiveID.getLoc());
    9094        3917 :   else if (IDVal == ".arch_extension")
    9095          80 :     parseDirectiveArchExtension(DirectiveID.getLoc());
    9096        3943 :   else if (IDVal == ".align")
    9097         186 :     return parseDirectiveAlign(DirectiveID.getLoc()); // Use Generic on failure.
    9098        3601 :   else if (IDVal == ".thumb_set")
    9099          30 :     parseDirectiveThumbSet(DirectiveID.getLoc());
    9100        3541 :   else if (!IsMachO && !IsCOFF) {
    9101        3109 :     if (IDVal == ".arch")
    9102          77 :       parseDirectiveArch(DirectiveID.getLoc());
    9103        2973 :     else if (IDVal == ".cpu")
    9104          18 :       parseDirectiveCPU(DirectiveID.getLoc());
    9105        3544 :     else if (IDVal == ".eabi_attribute")
    9106         607 :       parseDirectiveEabiAttr(DirectiveID.getLoc());
    9107        2388 :     else if (IDVal == ".fpu")
    9108          58 :       parseDirectiveFPU(DirectiveID.getLoc());
    9109        2488 :     else if (IDVal == ".fnstart")
    9110         216 :       parseDirectiveFnStart(DirectiveID.getLoc());
    9111        2065 :     else if (IDVal == ".inst")
    9112           9 :       parseDirectiveInst(DirectiveID.getLoc());
    9113        2054 :     else if (IDVal == ".inst.n")
    9114           7 :       parseDirectiveInst(DirectiveID.getLoc(), 'n');
    9115        2049 :     else if (IDVal == ".inst.w")
    9116           9 :       parseDirectiveInst(DirectiveID.getLoc(), 'w');
    9117        2041 :     else if (IDVal == ".object_arch")
    9118          10 :       parseDirectiveObjectArch(DirectiveID.getLoc());
    9119        2034 :     else if (IDVal == ".tlsdescseq")
    9120          13 :       parseDirectiveTLSDescSeq(DirectiveID.getLoc());
    9121             :     else
    9122             :       return true;
    9123             :   } else
    9124             :     return true;
    9125             :   return false;
    9126             : }
    9127             : 
    9128             : /// parseLiteralValues
    9129             : ///  ::= .hword expression [, expression]*
    9130             : ///  ::= .short expression [, expression]*
    9131             : ///  ::= .word expression [, expression]*
    9132             : bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
    9133        2350 :   auto parseOne = [&]() -> bool {
    9134             :     const MCExpr *Value;
    9135        2350 :     if (getParser().parseExpression(Value))
    9136             :       return true;
    9137        2347 :     getParser().getStreamer().EmitValue(Value, Size, L);
    9138        2347 :     return false;
    9139        2295 :   };
    9140        6885 :   return (parseMany(parseOne));
    9141             : }
    9142             : 
    9143             : /// parseDirectiveThumb
    9144             : ///  ::= .thumb
    9145         121 : bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
    9146         603 :   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
    9147         597 :       check(!hasThumb(), L, "target does not support Thumb mode"))
    9148             :     return true;
    9149             : 
    9150         118 :   if (!isThumb())
    9151          63 :     SwitchMode();
    9152             : 
    9153         118 :   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
    9154         118 :   return false;
    9155             : }
    9156             : 
    9157             : /// parseDirectiveARM
    9158             : ///  ::= .arm
    9159          67 : bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
    9160         333 :   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive") ||
    9161         327 :       check(!hasARM(), L, "target does not support ARM mode"))
    9162             :     return true;
    9163             : 
    9164          58 :   if (isThumb())
    9165          30 :     SwitchMode();
    9166          58 :   getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
    9167          58 :   return false;
    9168             : }
    9169             : 
    9170        1358 : void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
    9171             :   // We need to flush the current implicit IT block on a label, because it is
    9172             :   // not legal to branch into an IT block.
    9173        2716 :   flushPendingInstructions(getStreamer());
    9174        1358 :   if (NextSymbolIsThumb) {
    9175          79 :     getParser().getStreamer().EmitThumbFunc(Symbol);
    9176          79 :     NextSymbolIsThumb = false;
    9177             :   }
    9178        1358 : }
    9179             : 
    9180             : /// parseDirectiveThumbFunc
    9181             : ///  ::= .thumbfunc symbol_name
    9182         123 : bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
    9183         123 :   MCAsmParser &Parser = getParser();
    9184         246 :   const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
    9185         123 :   bool IsMachO = Format == MCObjectFileInfo::IsMachO;
    9186             : 
    9187             :   // Darwin asm has (optionally) function name after .thumb_func direction
    9188             :   // ELF doesn't
    9189             : 
    9190         123 :   if (IsMachO) {
    9191          45 :     if (Parser.getTok().is(AsmToken::Identifier) ||
    9192           2 :         Parser.getTok().is(AsmToken::String)) {
    9193         123 :       MCSymbol *Func = getParser().getContext().getOrCreateSymbol(
    9194         164 :           Parser.getTok().getIdentifier());
    9195          41 :       getParser().getStreamer().EmitThumbFunc(Func);
    9196          41 :       Parser.Lex();
    9197         123 :       if (parseToken(AsmToken::EndOfStatement,
    9198             :                      "unexpected token in '.thumb_func' directive"))
    9199             :         return true;
    9200             :       return false;
    9201             :     }
    9202             :   }
    9203             : 
    9204         246 :   if (parseToken(AsmToken::EndOfStatement,
    9205             :                  "unexpected token in '.thumb_func' directive"))
    9206             :     return true;
    9207             : 
    9208          79 :   NextSymbolIsThumb = true;
    9209             :   return false;
    9210             : }
    9211             : 
    9212             : /// parseDirectiveSyntax
    9213             : ///  ::= .syntax unified | divided
    9214         320 : bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
    9215         320 :   MCAsmParser &Parser = getParser();
    9216         320 :   const AsmToken &Tok = Parser.getTok();
    9217         320 :   if (Tok.isNot(AsmToken::Identifier)) {
    9218           0 :     Error(L, "unexpected token in .syntax directive");
    9219           0 :     return false;
    9220             :   }
    9221             : 
    9222         320 :   StringRef Mode = Tok.getString();
    9223         320 :   Parser.Lex();
    9224        1920 :   if (check(Mode == "divided" || Mode == "DIVIDED", L,
    9225         320 :             "'.syntax divided' arm assembly not supported") ||
    9226        1600 :       check(Mode != "unified" && Mode != "UNIFIED", L,
    9227         640 :             "unrecognized syntax mode in .syntax directive") ||
    9228        1280 :       parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
    9229             :     return true;
    9230             : 
    9231             :   // TODO tell the MC streamer the mode
    9232             :   // getParser().getStreamer().Emit???();
    9233             :   return false;
    9234             : }
    9235             : 
    9236             : /// parseDirectiveCode
    9237             : ///  ::= .code 16 | 32
    9238         116 : bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
    9239         116 :   MCAsmParser &Parser = getParser();
    9240         116 :   const AsmToken &Tok = Parser.getTok();
    9241         116 :   if (Tok.isNot(AsmToken::Integer))
    9242           0 :     return Error(L, "unexpected token in .code directive");
    9243         232 :   int64_t Val = Parser.getTok().getIntVal();
    9244         116 :   if (Val != 16 && Val != 32) {
    9245           0 :     Error(L, "invalid operand to .code directive");
    9246           0 :     return false;
    9247             :   }
    9248         116 :   Parser.Lex();
    9249             : 
    9250         348 :   if (parseToken(AsmToken::EndOfStatement, "unexpected token in directive"))
    9251             :     return true;
    9252             : 
    9253         114 :   if (Val == 16) {
    9254          78 :     if (!hasThumb())
    9255           3 :       return Error(L, "target does not support Thumb mode");
    9256             : 
    9257          77 :     if (!isThumb())
    9258          30 :       SwitchMode();
    9259          77 :     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
    9260             :   } else {
    9261          36 :     if (!hasARM())
    9262          12 :       return Error(L, "target does not support ARM mode");
    9263             : 
    9264          32 :     if (isThumb())
    9265          21 :       SwitchMode();
    9266          32 :     getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
    9267             :   }
    9268             : 
    9269             :   return false;
    9270             : }
    9271             : 
    9272             : /// parseDirectiveReq
    9273             : ///  ::= name .req registername
    9274           7 : bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
    9275           7 :   MCAsmParser &Parser = getParser();
    9276           7 :   Parser.Lex(); // Eat the '.req' token.
    9277             :   unsigned Reg;
    9278           7 :   SMLoc SRegLoc, ERegLoc;
    9279          28 :   if (check(ParseRegister(Reg, SRegLoc, ERegLoc), SRegLoc,
    9280          14 :             "register name expected") ||
    9281          28 :       parseToken(AsmToken::EndOfStatement,
    9282             :                  "unexpected input in .req directive."))
    9283             :     return true;
    9284             : 
    9285          28 :   if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg)
    9286           0 :     return Error(SRegLoc,
    9287           0 :                  "redefinition of '" + Name + "' does not match original.");
    9288             : 
    9289             :   return false;
    9290             : }
    9291             : 
    9292             : /// parseDirectiveUneq
    9293             : ///  ::= .unreq registername
    9294           7 : bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
    9295           7 :   MCAsmParser &Parser = getParser();
    9296           7 :   if (Parser.getTok().isNot(AsmToken::Identifier))
    9297           0 :     return Error(L, "unexpected input in .unreq directive.");
    9298          28 :   RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
    9299           7 :   Parser.Lex(); // Eat the identifier.
    9300          21 :   if (parseToken(AsmToken::EndOfStatement,
    9301             :                  "unexpected input in '.unreq' directive"))
    9302             :     return true;
    9303           5 :   return false;
    9304             : }
    9305             : 
    9306             : // After changing arch/CPU, try to put the ARM/Thumb mode back to what it was
    9307             : // before, if supported by the new target, or emit mapping symbols for the mode
    9308             : // switch.
    9309          92 : void ARMAsmParser::FixModeAfterArchChange(bool WasThumb, SMLoc Loc) {
    9310          92 :   if (WasThumb != isThumb()) {
    9311          19 :     if (WasThumb && hasThumb()) {
    9312             :       // Stay in Thumb mode
    9313           5 :       SwitchMode();
    9314          18 :     } else if (!WasThumb && hasARM()) {
    9315             :       // Stay in ARM mode
    9316           0 :       SwitchMode();
    9317             :     } else {
    9318             :       // Mode switch forced, because the new arch doesn't support the old mode.
    9319          27 :       getParser().getStreamer().EmitAssemblerFlag(isThumb() ? MCAF_Code16
    9320           9 :                                                             : MCAF_Code32);
    9321             :       // Warn about the implcit mode switch. GAS does not switch modes here,
    9322             :       // but instead stays in the old mode, reporting an error on any following
    9323             :       // instructions as the mode does not exist on the target.
    9324          45 :       Warning(Loc, Twine("new target does not support ") +
    9325          54 :                        (WasThumb ? "thumb" : "arm") + " mode, switching to " +
    9326          45 :                        (!WasThumb ? "thumb" : "arm") + " mode");
    9327             :     }
    9328             :   }
    9329          92 : }
    9330             : 
    9331             : /// parseDirectiveArch
    9332             : ///  ::= .arch token
    9333          77 : bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
    9334         154 :   StringRef Arch = getParser().parseStringToEndOfStatement().trim();
    9335          77 :   ARM::ArchKind ID = ARM::parseArch(Arch);
    9336             : 
    9337          77 :   if (ID == ARM::ArchKind::INVALID)
    9338           3 :     return Error(L, "Unknown arch name");
    9339             : 
    9340          76 :   bool WasThumb = isThumb();
    9341          76 :   Triple T;
    9342          76 :   MCSubtargetInfo &STI = copySTI();
    9343         380 :   STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
    9344         228 :   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
    9345          76 :   FixModeAfterArchChange(WasThumb, L);
    9346             : 
    9347          76 :   getTargetStreamer().emitArch(ID);
    9348          76 :   return false;
    9349             : }
    9350             : 
    9351             : /// parseDirectiveEabiAttr
    9352             : ///  ::= .eabi_attribute int, int [, "str"]
    9353             : ///  ::= .eabi_attribute Tag_name, int [, "str"]
    9354         607 : bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
    9355         607 :   MCAsmParser &Parser = getParser();
    9356             :   int64_t Tag;
    9357         607 :   SMLoc TagLoc;
    9358         607 :   TagLoc = Parser.getTok().getLoc();
    9359         607 :   if (Parser.getTok().is(AsmToken::Identifier)) {
    9360         844 :     StringRef Name = Parser.getTok().getIdentifier();
    9361         422 :     Tag = ARMBuildAttrs::AttrTypeFromString(Name);
    9362         422 :     if (Tag == -1) {
    9363           6 :       Error(TagLoc, "attribute name not recognised: " + Name);
    9364           2 :       return false;
    9365             :     }
    9366         420 :     Parser.Lex();
    9367             :   } else {
    9368             :     const MCExpr *AttrExpr;
    9369             : 
    9370         185 :     TagLoc = Parser.getTok().getLoc();
    9371         185 :     if (Parser.parseExpression(AttrExpr))
    9372           1 :       return true;
    9373             : 
    9374         370 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
    9375         555 :     if (check(!CE, TagLoc, "expected numeric constant"))
    9376             :       return true;
    9377             : 
    9378         184 :     Tag = CE->getValue();
    9379             :   }
    9380             : 
    9381         604 :   if (Parser.parseToken(AsmToken::Comma, "comma expected"))
    9382             :     return true;
    9383             : 
    9384         603 :   StringRef StringValue = "";
    9385         603 :   bool IsStringValue = false;
    9386             : 
    9387         603 :   int64_t IntegerValue = 0;
    9388         603 :   bool IsIntegerValue = false;
    9389             : 
    9390         603 :   if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
    9391             :     IsStringValue = true;
    9392         597 :   else if (Tag == ARMBuildAttrs::compatibility) {
    9393             :     IsStringValue = true;
    9394             :     IsIntegerValue = true;
    9395         583 :   } else if (Tag < 32 || Tag % 2 == 0)
    9396             :     IsIntegerValue = true;
    9397          21 :   else if (Tag % 2 == 1)
    9398             :     IsStringValue = true;
    9399             :   else
    9400           0 :     llvm_unreachable("invalid tag type");
    9401             : 
    9402             :   if (IsIntegerValue) {
    9403             :     const MCExpr *ValueExpr;
    9404         576 :     SMLoc ValueExprLoc = Parser.getTok().getLoc();
    9405         576 :     if (Parser.parseExpression(ValueExpr))
    9406           1 :       return true;
    9407             : 
    9408        1151 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
    9409             :     if (!CE)
    9410           3 :       return Error(ValueExprLoc, "expected numeric constant");
    9411         575 :     IntegerValue = CE->getValue();
    9412             :   }
    9413             : 
    9414         602 :   if (Tag == ARMBuildAttrs::compatibility) {
    9415          14 :     if (Parser.parseToken(AsmToken::Comma, "comma expected"))
    9416             :       return true;
    9417             :   }
    9418             : 
    9419         601 :   if (IsStringValue) {
    9420          40 :     if (Parser.getTok().isNot(AsmToken::String))
    9421           3 :       return Error(Parser.getTok().getLoc(), "bad string constant");
    9422             : 
    9423          39 :     StringValue = Parser.getTok().getStringContents();
    9424          39 :     Parser.Lex();
    9425             :   }
    9426             : 
    9427         600 :   if (Parser.parseToken(AsmToken::EndOfStatement,
    9428             :                         "unexpected token in '.eabi_attribute' directive"))
    9429             :     return true;
    9430             : 
    9431         598 :   if (IsIntegerValue && IsStringValue) {
    9432             :     assert(Tag == ARMBuildAttrs::compatibility);
    9433          13 :     getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
    9434         585 :   } else if (IsIntegerValue)
    9435         559 :     getTargetStreamer().emitAttribute(Tag, IntegerValue);
    9436          26 :   else if (IsStringValue)
    9437          26 :     getTargetStreamer().emitTextAttribute(Tag, StringValue);
    9438             :   return false;
    9439             : }
    9440             : 
    9441             : /// parseDirectiveCPU
    9442             : ///  ::= .cpu str
    9443          18 : bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
    9444          36 :   StringRef CPU = getParser().parseStringToEndOfStatement().trim();
    9445          18 :   getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
    9446             : 
    9447             :   // FIXME: This is using table-gen data, but should be moved to
    9448             :   // ARMTargetParser once that is table-gen'd.
    9449          18 :   if (!getSTI().isCPUStringValid(CPU))
    9450           6 :     return Error(L, "Unknown CPU name");
    9451             : 
    9452          16 :   bool WasThumb = isThumb();
    9453          16 :   MCSubtargetInfo &STI = copySTI();
    9454          16 :   STI.setDefaultFeatures(CPU, "");
    9455          48 :   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
    9456          16 :   FixModeAfterArchChange(WasThumb, L);
    9457             : 
    9458          16 :   return false;
    9459             : }
    9460             : /// parseDirectiveFPU
    9461             : ///  ::= .fpu str
    9462          58 : bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
    9463         116 :   SMLoc FPUNameLoc = getTok().getLoc();
    9464         116 :   StringRef FPU = getParser().parseStringToEndOfStatement().trim();
    9465             : 
    9466          58 :   unsigned ID = ARM::parseFPU(FPU);
    9467         116 :   std::vector<StringRef> Features;
    9468          58 :   if (!ARM::getFPUFeatures(ID, Features))
    9469           3 :     return Error(FPUNameLoc, "Unknown FPU name");
    9470             : 
    9471          57 :   MCSubtargetInfo &STI = copySTI();
    9472         638 :   for (auto Feature : Features)
    9473         410 :     STI.ApplyFeatureFlag(Feature);
    9474         171 :   setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
    9475             : 
    9476          57 :   getTargetStreamer().emitFPU(ID);
    9477             :   return false;
    9478             : }
    9479             : 
    9480             : /// parseDirectiveFnStart
    9481             : ///  ::= .fnstart
    9482         216 : bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
    9483         648 :   if (parseToken(AsmToken::EndOfStatement,
    9484             :                  "unexpected token in '.fnstart' directive"))
    9485             :     return true;
    9486             : 
    9487         428 :   if (UC.hasFnStart()) {
    9488           3 :     Error(L, ".fnstart starts before the end of previous one");
    9489           1 :     UC.emitFnStartLocNotes();
    9490           1 :     return true;
    9491             :   }
    9492             : 
    9493             :   // Reset the unwind directives parser state
    9494         213 :   UC.reset();
    9495             : 
    9496         213 :   getTargetStreamer().emitFnStart();
    9497             : 
    9498         426 :   UC.recordFnStart(L);
    9499         213 :   return false;
    9500             : }
    9501             : 
    9502             : /// parseDirectiveFnEnd
    9503             : ///  ::= .fnend
    9504         211 : bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
    9505         633 :   if (parseToken(AsmToken::EndOfStatement,
    9506             :                  "unexpected token in '.fnend' directive"))
    9507             :     return true;
    9508             :   // Check the ordering of unwind directives
    9509         418 :   if (!UC.hasFnStart())
    9510           3 :     return Error(L, ".fnstart must precede .fnend directive");
    9511             : 
    9512             :   // Reset the unwind directives parser state
    9513         208 :   getTargetStreamer().emitFnEnd();
    9514             : 
    9515         208 :   UC.reset();
    9516         208 :   return false;
    9517             : }
    9518             : 
    9519             : /// parseDirectiveCantUnwind
    9520             : ///  ::= .cantunwind
    9521          47 : bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
    9522         141 :   if (parseToken(AsmToken::EndOfStatement,
    9523             :                  "unexpected token in '.cantunwind' directive"))
    9524             :     return true;
    9525             : 
    9526          90 :   UC.recordCantUnwind(L);
    9527             :   // Check the ordering of unwind directives
    9528         180 :   if (check(!UC.hasFnStart(), L, ".fnstart must precede .cantunwind directive"))
    9529             :     return true;
    9530             : 
    9531          88 :   if (UC.hasHandlerData()) {
    9532           3 :     Error(L, ".cantunwind can't be used with .handlerdata directive");
    9533           1 :     UC.emitHandlerDataLocNotes();
    9534           1 :     return true;
    9535             :   }
    9536          84 :   if (UC.hasPersonality()) {
    9537           6 :     Error(L, ".cantunwind can't be used with .personality directive");
    9538           2 :     UC.emitPersonalityLocNotes();
    9539           2 :     return true;
    9540             :   }
    9541             : 
    9542          41 :   getTargetStreamer().emitCantUnwind();
    9543          41 :   return false;
    9544             : }
    9545             : 
    9546             : /// parseDirectivePersonality
    9547             : ///  ::= .personality name
    9548          78 : bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
    9549          78 :   MCAsmParser &Parser = getParser();
    9550         156 :   bool HasExistingPersonality = UC.hasPersonality();
    9551             : 
    9552             :   // Parse the name of the personality routine
    9553          78 :   if (Parser.getTok().isNot(AsmToken::Identifier))
    9554           0 :     return Error(L, "unexpected input in .personality directive.");
    9555         156 :   StringRef Name(Parser.getTok().getIdentifier());
    9556          78 :   Parser.Lex();
    9557             : 
    9558         234 :   if (parseToken(AsmToken::EndOfStatement,
    9559             :                  "unexpected token in '.personality' directive"))
    9560             :     return true;
    9561             : 
    9562         152 :   UC.recordPersonality(L);
    9563             : 
    9564             :   // Check the ordering of unwind directives
    9565         152 :   if (!UC.hasFnStart())
    9566           3 :     return Error(L, ".fnstart must precede .personality directive");
    9567         150 :   if (UC.cantUnwind()) {
    9568           3 :     Error(L, ".personality can't be used with .cantunwind directive");
    9569           1 :     UC.emitCantUnwindLocNotes();
    9570           1 :     return true;
    9571             :   }
    9572         148 :   if (UC.hasHandlerData()) {
    9573           3 :     Error(L, ".personality must precede .handlerdata directive");
    9574           1 :     UC.emitHandlerDataLocNotes();
    9575           1 :     return true;
    9576             :   }
    9577          73 :   if (HasExistingPersonality) {
    9578           6 :     Error(L, "multiple personality directives");
    9579           2 :     UC.emitPersonalityLocNotes();
    9580           2 :     return true;
    9581             :   }
    9582             : 
    9583         142 :   MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
    9584          71 :   getTargetStreamer().emitPersonality(PR);
    9585          71 :   return false;
    9586             : }
    9587             : 
    9588             : /// parseDirectiveHandlerData
    9589             : ///  ::= .handlerdata
    9590          77 : bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
    9591         231 :   if (parseToken(AsmToken::EndOfStatement,
    9592             :                  "unexpected token in '.handlerdata' directive"))
    9593             :     return true;
    9594             : 
    9595         150 :   UC.recordHandlerData(L);
    9596             :   // Check the ordering of unwind directives
    9597         150 :   if (!UC.hasFnStart())
    9598           0 :     return Error(L, ".fnstart must precede .personality directive");
    9599         150 :   if (UC.cantUnwind()) {
    9600           3 :     Error(L, ".handlerdata can't be used with .cantunwind directive");
    9601           1 :     UC.emitCantUnwindLocNotes();
    9602           1 :     return true;
    9603             :   }
    9604             : 
    9605          74 :   getTargetStreamer().emitHandlerData();
    9606          74 :   return false;
    9607             : }
    9608             : 
    9609             : /// parseDirectiveSetFP
    9610             : ///  ::= .setfp fpreg, spreg [, offset]
    9611          38 : bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
    9612          38 :   MCAsmParser &Parser = getParser();
    9613             :   // Check the ordering of unwind directives
    9614         227 :   if (check(!UC.hasFnStart(), L, ".fnstart must precede .setfp directive") ||
    9615         186 :       check(UC.hasHandlerData(), L,
    9616             :             ".setfp must precede .handlerdata directive"))
    9617             :     return true;
    9618             : 
    9619             :   // Parse fpreg
    9620          36 :   SMLoc FPRegLoc = Parser.getTok().getLoc();
    9621          36 :   int FPReg = tryParseRegister();
    9622             : 
    9623         179 :   if (check(FPReg == -1, FPRegLoc, "frame pointer register expected") ||
    9624          71 :       Parser.parseToken(AsmToken::Comma, "comma expected"))
    9625             :     return true;
    9626             : 
    9627             :   // Parse spreg
    9628          35 :   SMLoc SPRegLoc = Parser.getTok().getLoc();
    9629          35 :   int SPReg = tryParseRegister();
    9630         174 :   if (check(SPReg == -1, SPRegLoc, "stack pointer register expected") ||
    9631         137 :       check(SPReg != ARM::SP && SPReg != UC.getFPReg(), SPRegLoc,
    9632             :             "register should be either $sp or the latest fp register"))
    9633             :     return true;
    9634             : 
    9635             :   // Update the frame pointer register
    9636          66 :   UC.saveFPReg(FPReg);
    9637             : 
    9638             :   // Parse offset
    9639          33 :   int64_t Offset = 0;
    9640          33 :   if (Parser.parseOptionalToken(AsmToken::Comma)) {
    9641          29 :     if (Parser.getTok().isNot(AsmToken::Hash) &&
    9642           0 :         Parser.getTok().isNot(AsmToken::Dollar))
    9643           0 :       return Error(Parser.getTok().getLoc(), "'#' expected");
    9644          29 :     Parser.Lex(); // skip hash token.
    9645             : 
    9646             :     const MCExpr *OffsetExpr;
    9647          29 :     SMLoc ExLoc = Parser.getTok().getLoc();
    9648          29 :     SMLoc EndLoc;
    9649          29 :     if (getParser().parseExpression(OffsetExpr, EndLoc))
    9650           0 :       return Error(ExLoc, "malformed setfp offset");
    9651          58 :     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
    9652          87 :     if (check(!CE, ExLoc, "setfp offset must be an immediate"))
    9653             :       return true;
    9654          29 :     Offset = CE->getValue();
    9655             :   }
    9656             : 
    9657          33 :   if (Parser.parseToken(AsmToken::EndOfStatement))
    9658             :     return true;
    9659             : 
    9660          62 :   getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
    9661          31 :                                 static_cast<unsigned>(SPReg), Offset);
    9662          31 :   return false;
    9663             : }
    9664             : 
    9665             : /// parseDirective
    9666             : ///  ::= .pad offset
    9667          29 : bool ARMAsmParser::parseDirectivePad(SMLoc L) {
    9668          29 :   MCAsmParser &Parser = getParser();
    9669             :   // Check the ordering of unwind directives
    9670          58 :   if (!UC.hasFnStart())
    9671           3 :     return Error(L, ".fnstart must prece