LCOV - code coverage report
Current view: top level - lib/Target/ARM/Disassembler - ARMDisassembler.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1902 2042 93.1 %
Date: 2017-09-14 15:23:50 Functions: 123 125 98.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "MCTargetDesc/ARMAddressingModes.h"
      11             : #include "MCTargetDesc/ARMBaseInfo.h"
      12             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      13             : #include "llvm/MC/MCContext.h"
      14             : #include "llvm/MC/MCDisassembler/MCDisassembler.h"
      15             : #include "llvm/MC/MCFixedLenDisassembler.h"
      16             : #include "llvm/MC/MCInst.h"
      17             : #include "llvm/MC/MCInstrDesc.h"
      18             : #include "llvm/MC/MCSubtargetInfo.h"
      19             : #include "llvm/MC/SubtargetFeature.h"
      20             : #include "llvm/Support/Compiler.h"
      21             : #include "llvm/Support/ErrorHandling.h"
      22             : #include "llvm/Support/MathExtras.h"
      23             : #include "llvm/Support/TargetRegistry.h"
      24             : #include "llvm/Support/raw_ostream.h"
      25             : #include <algorithm>
      26             : #include <cassert>
      27             : #include <cstdint>
      28             : #include <vector>
      29             : 
      30             : using namespace llvm;
      31             : 
      32             : #define DEBUG_TYPE "arm-disassembler"
      33             : 
      34             : typedef MCDisassembler::DecodeStatus DecodeStatus;
      35             : 
      36             : namespace {
      37             : 
      38             :   // Handles the condition code status of instructions in IT blocks
      39         556 :   class ITStatus
      40             :   {
      41             :     public:
      42             :       // Returns the condition code for instruction in IT block
      43             :       unsigned getITCC() {
      44       10492 :         unsigned CC = ARMCC::AL;
      45       10492 :         if (instrInITBlock())
      46         400 :           CC = ITStates.back();
      47             :         return CC;
      48             :       }
      49             : 
      50             :       // Advances the IT block state to the next T or E
      51             :       void advanceITState() {
      52         200 :         ITStates.pop_back();
      53             :       }
      54             : 
      55             :       // Returns true if the current instruction is in an IT block
      56             :       bool instrInITBlock() {
      57       47458 :         return !ITStates.empty();
      58             :       }
      59             : 
      60             :       // Returns true if current instruction is the last instruction in an IT block
      61             :       bool instrLastInITBlock() {
      62           2 :         return ITStates.size() == 1;
      63             :       }
      64             : 
      65             :       // Called when decoding an IT instruction. Sets the IT state for the following
      66             :       // instructions that for the IT block. Firstcond and Mask correspond to the
      67             :       // fields in the IT instruction encoding.
      68         126 :       void setITState(char Firstcond, char Mask) {
      69             :         // (3 - the number of trailing zeros) is the number of then / else.
      70         126 :         unsigned CondBit0 = Firstcond & 1;
      71         252 :         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
      72         126 :         unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
      73             :         assert(NumTZ <= 3 && "Invalid IT mask!");
      74             :         // push condition codes onto the stack the correct order for the pops
      75         201 :         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
      76          75 :           bool T = ((Mask >> Pos) & 1) == CondBit0;
      77          75 :           if (T)
      78          29 :             ITStates.push_back(CCBits);
      79             :           else
      80          92 :             ITStates.push_back(CCBits ^ 1);
      81             :         }
      82         126 :         ITStates.push_back(CCBits);
      83         126 :       }
      84             : 
      85             :     private:
      86             :       std::vector<unsigned char> ITStates;
      87             :   };
      88             : 
      89             : /// ARM disassembler for all ARM platforms.
      90             : class ARMDisassembler : public MCDisassembler {
      91             : public:
      92             :   ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
      93         290 :     MCDisassembler(STI, Ctx) {
      94             :   }
      95             : 
      96         145 :   ~ARMDisassembler() override = default;
      97             : 
      98             :   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
      99             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
     100             :                               raw_ostream &VStream,
     101             :                               raw_ostream &CStream) const override;
     102             : };
     103             : 
     104             : /// Thumb disassembler for all Thumb platforms.
     105             : class ThumbDisassembler : public MCDisassembler {
     106             : public:
     107         139 :   ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
     108         417 :     MCDisassembler(STI, Ctx) {
     109             :   }
     110             : 
     111         417 :   ~ThumbDisassembler() override = default;
     112             : 
     113             :   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
     114             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
     115             :                               raw_ostream &VStream,
     116             :                               raw_ostream &CStream) const override;
     117             : 
     118             : private:
     119             :   mutable ITStatus ITBlock;
     120             :   DecodeStatus AddThumbPredicate(MCInst&) const;
     121             :   void UpdateThumbVFPPredicate(MCInst&) const;
     122             : };
     123             : 
     124             : } // end anonymous namespace
     125             : 
     126             : static bool Check(DecodeStatus &Out, DecodeStatus In) {
     127       80296 :   switch (In) {
     128             :     case MCDisassembler::Success:
     129             :       // Out stays the same.
     130             :       return true;
     131         119 :     case MCDisassembler::SoftFail:
     132         119 :       Out = In;
     133             :       return true;
     134        1911 :     case MCDisassembler::Fail:
     135        1911 :       Out = In;
     136             :       return false;
     137             :   }
     138           0 :   llvm_unreachable("Invalid DecodeStatus!");
     139             : }
     140             : 
     141             : // Forward declare these because the autogenerated code will reference them.
     142             : // Definitions are further down.
     143             : static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     144             :                                    uint64_t Address, const void *Decoder);
     145             : static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
     146             :                                                unsigned RegNo, uint64_t Address,
     147             :                                                const void *Decoder);
     148             : static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
     149             :                                                unsigned RegNo, uint64_t Address,
     150             :                                                const void *Decoder);
     151             : static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     152             :                                    uint64_t Address, const void *Decoder);
     153             : static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     154             :                                    uint64_t Address, const void *Decoder);
     155             : static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     156             :                                    uint64_t Address, const void *Decoder);
     157             : static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
     158             :                                    uint64_t Address, const void *Decoder);
     159             : static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
     160             :                                    uint64_t Address, const void *Decoder);
     161             : static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
     162             :                                    uint64_t Address, const void *Decoder);
     163             : static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
     164             :                                    uint64_t Address, const void *Decoder);
     165             : static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
     166             :                                                 unsigned RegNo,
     167             :                                                 uint64_t Address,
     168             :                                                 const void *Decoder);
     169             : static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
     170             :                                    uint64_t Address, const void *Decoder);
     171             : static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
     172             :                                    uint64_t Address, const void *Decoder);
     173             : static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
     174             :                                unsigned RegNo, uint64_t Address,
     175             :                                const void *Decoder);
     176             : 
     177             : static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
     178             :                                uint64_t Address, const void *Decoder);
     179             : static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
     180             :                                uint64_t Address, const void *Decoder);
     181             : static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
     182             :                                uint64_t Address, const void *Decoder);
     183             : static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
     184             :                                uint64_t Address, const void *Decoder);
     185             : static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
     186             :                                uint64_t Address, const void *Decoder);
     187             : 
     188             : static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
     189             :                                uint64_t Address, const void *Decoder);
     190             : static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
     191             :                                uint64_t Address, const void *Decoder);
     192             : static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
     193             :                                                   unsigned Insn,
     194             :                                                   uint64_t Address,
     195             :                                                   const void *Decoder);
     196             : static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
     197             :                                uint64_t Address, const void *Decoder);
     198             : static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
     199             :                                uint64_t Address, const void *Decoder);
     200             : static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
     201             :                                uint64_t Address, const void *Decoder);
     202             : static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
     203             :                                uint64_t Address, const void *Decoder);
     204             : 
     205             : static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
     206             :                                                   unsigned Insn,
     207             :                                                   uint64_t Adddress,
     208             :                                                   const void *Decoder);
     209             : static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
     210             :                                uint64_t Address, const void *Decoder);
     211             : static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
     212             :                                uint64_t Address, const void *Decoder);
     213             : static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
     214             :                                uint64_t Address, const void *Decoder);
     215             : static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
     216             :                                uint64_t Address, const void *Decoder);
     217             : static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
     218             :                                uint64_t Address, const void *Decoder);
     219             : static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
     220             :                                uint64_t Address, const void *Decoder);
     221             : static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
     222             :                                uint64_t Address, const void *Decoder);
     223             : static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
     224             :                                uint64_t Address, const void *Decoder);
     225             : static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
     226             :                                uint64_t Address, const void *Decoder);
     227             : static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
     228             :                                uint64_t Address, const void *Decoder);
     229             : static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
     230             :                                uint64_t Address, const void *Decoder);
     231             : static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
     232             :                                uint64_t Address, const void *Decoder);
     233             : static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
     234             :                                uint64_t Address, const void *Decoder);
     235             : static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
     236             :                                uint64_t Address, const void *Decoder);
     237             : static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
     238             :                                uint64_t Address, const void *Decoder);
     239             : static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
     240             :                                uint64_t Address, const void *Decoder);
     241             : static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
     242             :                                uint64_t Address, const void *Decoder);
     243             : static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
     244             :                                uint64_t Address, const void *Decoder);
     245             : static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
     246             :                                uint64_t Address, const void *Decoder);
     247             : static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
     248             :                                uint64_t Address, const void *Decoder);
     249             : static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
     250             :                                uint64_t Address, const void *Decoder);
     251             : static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
     252             :                                uint64_t Address, const void *Decoder);
     253             : static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
     254             :                                uint64_t Address, const void *Decoder);
     255             : static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
     256             :                                uint64_t Address, const void *Decoder);
     257             : static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
     258             :                                uint64_t Address, const void *Decoder);
     259             : static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
     260             :                                uint64_t Address, const void *Decoder);
     261             : static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
     262             :                                uint64_t Address, const void *Decoder);
     263             : static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
     264             :                                uint64_t Address, const void *Decoder);
     265             : static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
     266             :                                uint64_t Address, const void *Decoder);
     267             : static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
     268             :                                uint64_t Address, const void *Decoder);
     269             : static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
     270             :                                uint64_t Address, const void *Decoder);
     271             : static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
     272             :                                uint64_t Address, const void *Decoder);
     273             : static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
     274             :                                uint64_t Address, const void *Decoder);
     275             : static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
     276             :                                uint64_t Address, const void *Decoder);
     277             : static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
     278             :                                uint64_t Address, const void *Decoder);
     279             : static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
     280             :                                uint64_t Address, const void *Decoder);
     281             : static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
     282             :                                uint64_t Address, const void *Decoder);
     283             : static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
     284             :                                uint64_t Address, const void *Decoder);
     285             : static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
     286             :                                uint64_t Address, const void *Decoder);
     287             : static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
     288             :                                uint64_t Address, const void *Decoder);
     289             : static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
     290             :                                uint64_t Address, const void *Decoder);
     291             : static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
     292             :                                uint64_t Address, const void *Decoder);
     293             : static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
     294             :                                uint64_t Address, const void *Decoder);
     295             : static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
     296             :                                uint64_t Address, const void *Decoder);
     297             : static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
     298             :                                uint64_t Address, const void *Decoder);
     299             : static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
     300             :                                uint64_t Address, const void *Decoder);
     301             : static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
     302             :                                uint64_t Address, const void *Decoder);
     303             : static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
     304             :                                uint64_t Address, const void *Decoder);
     305             : static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
     306             :                                uint64_t Address, const void *Decoder);
     307             : static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
     308             :                                uint64_t Address, const void *Decoder);
     309             : static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
     310             :                                uint64_t Address, const void *Decoder);
     311             : static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
     312             :                                uint64_t Address, const void *Decoder);
     313             : static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
     314             :                                uint64_t Address, const void *Decoder);
     315             : static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
     316             :                                uint64_t Address, const void *Decoder);
     317             : static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
     318             :                                uint64_t Address, const void *Decoder);
     319             : static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
     320             :                                 uint64_t Address, const void *Decoder);
     321             : static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
     322             :                                 uint64_t Address, const void *Decoder);
     323             : 
     324             : static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
     325             :                                uint64_t Address, const void *Decoder);
     326             : static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
     327             :                                uint64_t Address, const void *Decoder);
     328             : static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
     329             :                                uint64_t Address, const void *Decoder);
     330             : static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
     331             :                                uint64_t Address, const void *Decoder);
     332             : static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
     333             :                                uint64_t Address, const void *Decoder);
     334             : static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
     335             :                                uint64_t Address, const void *Decoder);
     336             : static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
     337             :                                uint64_t Address, const void *Decoder);
     338             : static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
     339             :                                uint64_t Address, const void *Decoder);
     340             : static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
     341             :                                uint64_t Address, const void *Decoder);
     342             : static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
     343             :                                uint64_t Address, const void *Decoder);
     344             : static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
     345             :                                uint64_t Address, const void* Decoder);
     346             : static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
     347             :                                uint64_t Address, const void* Decoder);
     348             : static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
     349             :                                uint64_t Address, const void* Decoder);
     350             : static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
     351             :                                uint64_t Address, const void* Decoder);
     352             : static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
     353             :                                uint64_t Address, const void *Decoder);
     354             : static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
     355             :                                uint64_t Address, const void *Decoder);
     356             : static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
     357             :                                uint64_t Address, const void *Decoder);
     358             : static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
     359             :                                uint64_t Address, const void *Decoder);
     360             : static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
     361             :                                uint64_t Address, const void *Decoder);
     362             : static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
     363             :                                uint64_t Address, const void *Decoder);
     364             : static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
     365             :                                 uint64_t Address, const void *Decoder);
     366             : static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
     367             :                                 uint64_t Address, const void *Decoder);
     368             : static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
     369             :                                 uint64_t Address, const void *Decoder);
     370             : static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
     371             :                                 uint64_t Address, const void *Decoder);
     372             : static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
     373             :                                 uint64_t Address, const void *Decoder);
     374             : static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
     375             :                                 uint64_t Address, const void *Decoder);
     376             : static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
     377             :                                 uint64_t Address, const void *Decoder);
     378             : static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
     379             :                                 uint64_t Address, const void *Decoder);
     380             : static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
     381             :                                 uint64_t Address, const void *Decoder);
     382             : static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
     383             :                                 uint64_t Address, const void *Decoder);
     384             : static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
     385             :                                 uint64_t Address, const void *Decoder);
     386             : static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
     387             :                                uint64_t Address, const void *Decoder);
     388             : static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
     389             :                                uint64_t Address, const void *Decoder);
     390             : static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
     391             :                                 uint64_t Address, const void *Decoder);
     392             : static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
     393             :                                 uint64_t Address, const void *Decoder);
     394             : static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
     395             :                                 uint64_t Address, const void *Decoder);
     396             : 
     397             : static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
     398             :                                 uint64_t Address, const void *Decoder);
     399             : static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
     400             :                                             uint64_t Address, const void *Decoder);
     401             : 
     402             : #include "ARMGenDisassemblerTables.inc"
     403             : 
     404         145 : static MCDisassembler *createARMDisassembler(const Target &T,
     405             :                                              const MCSubtargetInfo &STI,
     406             :                                              MCContext &Ctx) {
     407         290 :   return new ARMDisassembler(STI, Ctx);
     408             : }
     409             : 
     410         139 : static MCDisassembler *createThumbDisassembler(const Target &T,
     411             :                                                const MCSubtargetInfo &STI,
     412             :                                                MCContext &Ctx) {
     413         278 :   return new ThumbDisassembler(STI, Ctx);
     414             : }
     415             : 
     416             : // Post-decoding checks
     417             : static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
     418             :                                             uint64_t Address, raw_ostream &OS,
     419             :                                             raw_ostream &CS,
     420             :                                             uint32_t Insn,
     421             :                                             DecodeStatus Result) {
     422        5198 :   switch (MI.getOpcode()) {
     423           7 :     case ARM::HVC: {
     424             :       // HVC is undefined if condition = 0xf otherwise upredictable
     425             :       // if condition != 0xe
     426           7 :       uint32_t Cond = (Insn >> 28) & 0xF;
     427           7 :       if (Cond == 0xF)
     428             :         return MCDisassembler::Fail;
     429           6 :       if (Cond != 0xE)
     430             :         return MCDisassembler::SoftFail;
     431             :       return Result;
     432             :     }
     433             :     default: return Result;
     434             :   }
     435             : }
     436             : 
     437        7201 : DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     438             :                                              ArrayRef<uint8_t> Bytes,
     439             :                                              uint64_t Address, raw_ostream &OS,
     440             :                                              raw_ostream &CS) const {
     441        7201 :   CommentStream = &CS;
     442             : 
     443             :   assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
     444             :          "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
     445             :          "mode!");
     446             : 
     447             :   // We want to read exactly 4 bytes of data.
     448        7201 :   if (Bytes.size() < 4) {
     449          27 :     Size = 0;
     450          27 :     return MCDisassembler::Fail;
     451             :   }
     452             : 
     453             :   // Encoded as a small-endian 32-bit word in the stream.
     454             :   uint32_t Insn =
     455        7174 :       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
     456             : 
     457             :   // Calling the auto-generated decoder function.
     458             :   DecodeStatus Result =
     459        7174 :       decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
     460        7174 :   if (Result != MCDisassembler::Fail) {
     461        5127 :     Size = 4;
     462        5127 :     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
     463             :   }
     464             : 
     465             :   struct DecodeTable {
     466             :     const uint8_t *P;
     467             :     bool DecodePred;
     468             :   };
     469             : 
     470        2047 :   const DecodeTable Tables[] = {
     471             :       {DecoderTableVFP32, false},      {DecoderTableVFPV832, false},
     472             :       {DecoderTableNEONData32, true},  {DecoderTableNEONLoadStore32, true},
     473             :       {DecoderTableNEONDup32, true},   {DecoderTablev8NEON32, false},
     474             :       {DecoderTablev8Crypto32, false},
     475             :   };
     476             : 
     477        8503 :   for (auto Table : Tables) {
     478        8078 :     Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
     479        8078 :     if (Result != MCDisassembler::Fail) {
     480        1622 :       Size = 4;
     481             :       // Add a fake predicate operand, because we share these instruction
     482             :       // definitions with Thumb2 where these instructions are predicable.
     483        1622 :       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
     484        1622 :         return MCDisassembler::Fail;
     485             :       return Result;
     486             :     }
     487             :   }
     488             : 
     489         425 :   Result =
     490         425 :       decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
     491         425 :   if (Result != MCDisassembler::Fail) {
     492          71 :     Size = 4;
     493          71 :     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
     494             :   }
     495             : 
     496         354 :   Size = 4;
     497         354 :   return MCDisassembler::Fail;
     498             : }
     499             : 
     500             : namespace llvm {
     501             : 
     502             : extern const MCInstrDesc ARMInsts[];
     503             : 
     504             : } // end namespace llvm
     505             : 
     506             : /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
     507             : /// immediate Value in the MCInst.  The immediate Value has had any PC
     508             : /// adjustment made by the caller.  If the instruction is a branch instruction
     509             : /// then isBranch is true, else false.  If the getOpInfo() function was set as
     510             : /// part of the setupForSymbolicDisassembly() call then that function is called
     511             : /// to get any symbolic information at the Address for this instruction.  If
     512             : /// that returns non-zero then the symbolic information it returns is used to
     513             : /// create an MCExpr and that is added as an operand to the MCInst.  If
     514             : /// getOpInfo() returns zero and isBranch is true then a symbol look up for
     515             : /// Value is done and if a symbol is found an MCExpr is created with that, else
     516             : /// an MCExpr with Value is created.  This function returns true if it adds an
     517             : /// operand to the MCInst and false otherwise.
     518             : static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
     519             :                                      bool isBranch, uint64_t InstSize,
     520             :                                      MCInst &MI, const void *Decoder) {
     521        1138 :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
     522             :   // FIXME: Does it make sense for value to be negative?
     523        1138 :   return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
     524        1138 :                                        /* Offset */ 0, InstSize);
     525             : }
     526             : 
     527             : /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
     528             : /// referenced by a load instruction with the base register that is the Pc.
     529             : /// These can often be values in a literal pool near the Address of the
     530             : /// instruction.  The Address of the instruction and its immediate Value are
     531             : /// used as a possible literal pool entry.  The SymbolLookUp call back will
     532             : /// return the name of a symbol referenced by the literal pool's entry if
     533             : /// the referenced address is that of a symbol.  Or it will return a pointer to
     534             : /// a literal 'C' string if the referenced address of the literal pool's entry
     535             : /// is an address into a section with 'C' string literals.
     536             : static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
     537             :                                             const void *Decoder) {
     538         105 :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
     539         105 :   Dis->tryAddingPcLoadReferenceComment(Value, Address);
     540             : }
     541             : 
     542             : // Thumb1 instructions don't have explicit S bits.  Rather, they
     543             : // implicitly set CPSR.  Since it's not represented in the encoding, the
     544             : // auto-generated decoder won't inject the CPSR operand.  We need to fix
     545             : // that as a post-pass.
     546        2279 : static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
     547        2279 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     548        2279 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     549        2279 :   MCInst::iterator I = MI.begin();
     550        5078 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     551        4818 :     if (I == MI.end()) break;
     552        4818 :     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
     553        2019 :       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
     554        6057 :       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
     555        2019 :       return;
     556             :     }
     557             :   }
     558             : 
     559         780 :   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
     560             : }
     561             : 
     562             : // Most Thumb instructions don't have explicit predicates in the
     563             : // encoding, but rather get their predicates from IT context.  We need
     564             : // to fix up the predicate operands using this context information as a
     565             : // post-pass.
     566             : MCDisassembler::DecodeStatus
     567       10637 : ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
     568       10637 :   MCDisassembler::DecodeStatus S = Success;
     569             : 
     570       10637 :   const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
     571             : 
     572             :   // A few instructions actually have predicates encoded in them.  Don't
     573             :   // try to overwrite it if we're seeing one of those.
     574       10637 :   switch (MI.getOpcode()) {
     575         240 :     case ARM::tBcc:
     576             :     case ARM::t2Bcc:
     577             :     case ARM::tCBZ:
     578             :     case ARM::tCBNZ:
     579             :     case ARM::tCPS:
     580             :     case ARM::t2CPS3p:
     581             :     case ARM::t2CPS2p:
     582             :     case ARM::t2CPS1p:
     583             :     case ARM::tMOVSr:
     584             :     case ARM::tSETEND:
     585             :       // Some instructions (mostly conditional branches) are not
     586             :       // allowed in IT blocks.
     587         480 :       if (ITBlock.instrInITBlock())
     588             :         S = SoftFail;
     589             :       else
     590             :         return Success;
     591             :       break;
     592           9 :     case ARM::t2HINT:
     593          11 :       if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
     594             :         S = SoftFail;
     595             :       break;
     596         100 :     case ARM::tB:
     597             :     case ARM::t2B:
     598             :     case ARM::t2TBB:
     599             :     case ARM::t2TBH:
     600             :       // Some instructions (mostly unconditional branches) can
     601             :       // only appears at the end of, or outside of, an IT.
     602         202 :       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
     603             :         S = SoftFail;
     604             :       break;
     605             :     default:
     606             :       break;
     607             :   }
     608             : 
     609             :   // If we're in an IT block, base the predicate on that.  Otherwise,
     610             :   // assume a predicate of AL.
     611             :   unsigned CC;
     612       10587 :   CC = ITBlock.getITCC();
     613         188 :   if (CC == 0xF) 
     614           6 :     CC = ARMCC::AL;
     615       20798 :   if (ITBlock.instrInITBlock())
     616         188 :     ITBlock.advanceITState();
     617             : 
     618       10399 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     619       10399 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     620       10399 :   MCInst::iterator I = MI.begin();
     621       39867 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     622       39714 :     if (I == MI.end()) break;
     623       30786 :     if (OpInfo[i].isPredicate()) {
     624        3954 :       I = MI.insert(I, MCOperand::createImm(CC));
     625        1318 :       ++I;
     626        1318 :       if (CC == ARMCC::AL)
     627        2620 :         MI.insert(I, MCOperand::createReg(0));
     628             :       else
     629          16 :         MI.insert(I, MCOperand::createReg(ARM::CPSR));
     630             :       return S;
     631             :     }
     632             :   }
     633             : 
     634       27243 :   I = MI.insert(I, MCOperand::createImm(CC));
     635        9081 :   ++I;
     636        9081 :   if (CC == ARMCC::AL)
     637       17818 :     MI.insert(I, MCOperand::createReg(0));
     638             :   else
     639         344 :     MI.insert(I, MCOperand::createReg(ARM::CPSR));
     640             : 
     641             :   return S;
     642             : }
     643             : 
     644             : // Thumb VFP instructions are a special case.  Because we share their
     645             : // encodings between ARM and Thumb modes, and they are predicable in ARM
     646             : // mode, the auto-generated decoder will give them an (incorrect)
     647             : // predicate operand.  We need to rewrite these operands based on the IT
     648             : // context as a post-pass.
     649          93 : void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
     650             :   unsigned CC;
     651         186 :   CC = ITBlock.getITCC();
     652         186 :   if (ITBlock.instrInITBlock())
     653          12 :     ITBlock.advanceITState();
     654             : 
     655          93 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     656          93 :   MCInst::iterator I = MI.begin();
     657          93 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     658         342 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     659         342 :     if (OpInfo[i].isPredicate() ) {
     660         186 :       I->setImm(CC);
     661          93 :       ++I;
     662          93 :       if (CC == ARMCC::AL)
     663          84 :         I->setReg(0);
     664             :       else
     665           9 :         I->setReg(ARM::CPSR);
     666             :       return;
     667             :     }
     668             :   }
     669             : }
     670             : 
     671       11315 : DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     672             :                                                ArrayRef<uint8_t> Bytes,
     673             :                                                uint64_t Address,
     674             :                                                raw_ostream &OS,
     675             :                                                raw_ostream &CS) const {
     676       11315 :   CommentStream = &CS;
     677             : 
     678             :   assert(STI.getFeatureBits()[ARM::ModeThumb] &&
     679             :          "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
     680             : 
     681             :   // We want to read exactly 2 bytes of data.
     682       11315 :   if (Bytes.size() < 2) {
     683          10 :     Size = 0;
     684          10 :     return MCDisassembler::Fail;
     685             :   }
     686             : 
     687       11305 :   uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
     688             :   DecodeStatus Result =
     689       11305 :       decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
     690       11305 :   if (Result != MCDisassembler::Fail) {
     691        4450 :     Size = 2;
     692        4450 :     Check(Result, AddThumbPredicate(MI));
     693             :     return Result;
     694             :   }
     695             : 
     696        6855 :   Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
     697             :                              STI);
     698        6855 :   if (Result) {
     699        2019 :     Size = 2;
     700        4038 :     bool InITBlock = ITBlock.instrInITBlock();
     701        4038 :     Check(Result, AddThumbPredicate(MI));
     702        2019 :     AddThumb1SBit(MI, InITBlock);
     703        2019 :     return Result;
     704             :   }
     705             : 
     706        4836 :   Result =
     707        4836 :       decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
     708        4836 :   if (Result != MCDisassembler::Fail) {
     709         126 :     Size = 2;
     710             : 
     711             :     // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
     712             :     // the Thumb predicate.
     713         252 :     if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
     714             :       Result = MCDisassembler::SoftFail;
     715             : 
     716         252 :     Check(Result, AddThumbPredicate(MI));
     717             : 
     718             :     // If we find an IT instruction, we need to parse its condition
     719             :     // code and mask operands so that we can apply them correctly
     720             :     // to the subsequent instructions.
     721         126 :     if (MI.getOpcode() == ARM::t2IT) {
     722             : 
     723         126 :       unsigned Firstcond = MI.getOperand(0).getImm();
     724         126 :       unsigned Mask = MI.getOperand(1).getImm();
     725         126 :       ITBlock.setITState(Firstcond, Mask);
     726             :     }
     727             : 
     728             :     return Result;
     729             :   }
     730             : 
     731             :   // We want to read exactly 4 bytes of data.
     732        4710 :   if (Bytes.size() < 4) {
     733           6 :     Size = 0;
     734           6 :     return MCDisassembler::Fail;
     735             :   }
     736             : 
     737             :   uint32_t Insn32 =
     738        4704 :       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
     739        4704 :   Result =
     740        4704 :       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
     741        4704 :   if (Result != MCDisassembler::Fail) {
     742         260 :     Size = 4;
     743         520 :     bool InITBlock = ITBlock.instrInITBlock();
     744         520 :     Check(Result, AddThumbPredicate(MI));
     745         260 :     AddThumb1SBit(MI, InITBlock);
     746         260 :     return Result;
     747             :   }
     748             : 
     749        4444 :   Result =
     750        4444 :       decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
     751        4444 :   if (Result != MCDisassembler::Fail) {
     752        2465 :     Size = 4;
     753        2465 :     Check(Result, AddThumbPredicate(MI));
     754             :     return Result;
     755             :   }
     756             : 
     757        1979 :   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
     758         575 :     Result =
     759         575 :         decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
     760         575 :     if (Result != MCDisassembler::Fail) {
     761          93 :       Size = 4;
     762          93 :       UpdateThumbVFPPredicate(MI);
     763          93 :       return Result;
     764             :     }
     765             :   }
     766             : 
     767        1886 :   Result =
     768        1886 :       decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
     769        1886 :   if (Result != MCDisassembler::Fail) {
     770          64 :     Size = 4;
     771          64 :     return Result;
     772             :   }
     773             : 
     774        1822 :   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
     775         482 :     Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
     776             :                                STI);
     777         482 :     if (Result != MCDisassembler::Fail) {
     778          17 :       Size = 4;
     779          17 :       Check(Result, AddThumbPredicate(MI));
     780             :       return Result;
     781             :     }
     782             :   }
     783             : 
     784        1805 :   if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
     785         499 :     uint32_t NEONLdStInsn = Insn32;
     786         499 :     NEONLdStInsn &= 0xF0FFFFFF;
     787         499 :     NEONLdStInsn |= 0x04000000;
     788         499 :     Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
     789             :                                Address, this, STI);
     790         499 :     if (Result != MCDisassembler::Fail) {
     791         449 :       Size = 4;
     792         449 :       Check(Result, AddThumbPredicate(MI));
     793             :       return Result;
     794             :     }
     795             :   }
     796             : 
     797        1356 :   if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
     798        1039 :     uint32_t NEONDataInsn = Insn32;
     799        1039 :     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
     800        1039 :     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     801        1039 :     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
     802        1039 :     Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
     803             :                                Address, this, STI);
     804        1039 :     if (Result != MCDisassembler::Fail) {
     805         789 :       Size = 4;
     806         789 :       Check(Result, AddThumbPredicate(MI));
     807             :       return Result;
     808             :     }
     809             : 
     810         250 :     uint32_t NEONCryptoInsn = Insn32;
     811         250 :     NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
     812         250 :     NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     813         250 :     NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
     814         250 :     Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
     815             :                                Address, this, STI);
     816         250 :     if (Result != MCDisassembler::Fail) {
     817          14 :       Size = 4;
     818          14 :       return Result;
     819             :     }
     820             : 
     821         236 :     uint32_t NEONv8Insn = Insn32;
     822         236 :     NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
     823         236 :     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
     824             :                                this, STI);
     825         236 :     if (Result != MCDisassembler::Fail) {
     826          64 :       Size = 4;
     827          64 :       return Result;
     828             :     }
     829             :   }
     830             : 
     831         489 :   Result =
     832         489 :       decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
     833         489 :   if (Result != MCDisassembler::Fail) {
     834          62 :     Size = 4;
     835          62 :     Check(Result, AddThumbPredicate(MI));
     836             :     return Result;
     837             :   }
     838             : 
     839         427 :   Size = 0;
     840         427 :   return MCDisassembler::Fail;
     841             : }
     842             : 
     843       10550 : extern "C" void LLVMInitializeARMDisassembler() {
     844       21100 :   TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
     845             :                                          createARMDisassembler);
     846       21100 :   TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
     847             :                                          createARMDisassembler);
     848       21100 :   TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
     849             :                                          createThumbDisassembler);
     850       21100 :   TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
     851             :                                          createThumbDisassembler);
     852       10550 : }
     853             : 
     854             : static const uint16_t GPRDecoderTable[] = {
     855             :   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
     856             :   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
     857             :   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
     858             :   ARM::R12, ARM::SP, ARM::LR, ARM::PC
     859             : };
     860             : 
     861       34662 : static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     862             :                                    uint64_t Address, const void *Decoder) {
     863       34662 :   if (RegNo > 15)
     864             :     return MCDisassembler::Fail;
     865             : 
     866       34662 :   unsigned Register = GPRDecoderTable[RegNo];
     867       69324 :   Inst.addOperand(MCOperand::createReg(Register));
     868             :   return MCDisassembler::Success;
     869             : }
     870             : 
     871             : static DecodeStatus
     872        2097 : DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
     873             :                            uint64_t Address, const void *Decoder) {
     874        2097 :   DecodeStatus S = MCDisassembler::Success;
     875             : 
     876        2097 :   if (RegNo == 15) 
     877          34 :     S = MCDisassembler::SoftFail;
     878             : 
     879        4194 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     880             : 
     881        2097 :   return S;
     882             : }
     883             : 
     884             : static DecodeStatus
     885          31 : DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
     886             :                                uint64_t Address, const void *Decoder) {
     887          31 :   DecodeStatus S = MCDisassembler::Success;
     888             : 
     889          31 :   if (RegNo == 15)
     890             :   {
     891          12 :     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
     892             :     return MCDisassembler::Success;
     893             :   }
     894             : 
     895          25 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     896             :   return S;
     897             : }
     898             : 
     899             : static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     900             :                                    uint64_t Address, const void *Decoder) {
     901             :   if (RegNo > 7)
     902             :     return MCDisassembler::Fail;
     903        8950 :   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
     904             : }
     905             : 
     906             : static const uint16_t GPRPairDecoderTable[] = {
     907             :   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
     908             :   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
     909             : };
     910             : 
     911          15 : static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
     912             :                                    uint64_t Address, const void *Decoder) {
     913          15 :   DecodeStatus S = MCDisassembler::Success;
     914             : 
     915          15 :   if (RegNo > 13)
     916             :     return MCDisassembler::Fail;
     917             : 
     918          15 :   if ((RegNo & 1) || RegNo == 0xe)
     919           0 :      S = MCDisassembler::SoftFail;
     920             : 
     921          15 :   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
     922          30 :   Inst.addOperand(MCOperand::createReg(RegisterPair));
     923             :   return S;
     924             : }
     925             : 
     926           1 : static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     927             :                                    uint64_t Address, const void *Decoder) {
     928           1 :   unsigned Register = 0;
     929           1 :   switch (RegNo) {
     930             :     case 0:
     931             :       Register = ARM::R0;
     932             :       break;
     933           0 :     case 1:
     934           0 :       Register = ARM::R1;
     935             :       break;
     936           0 :     case 2:
     937           0 :       Register = ARM::R2;
     938             :       break;
     939           0 :     case 3:
     940           0 :       Register = ARM::R3;
     941             :       break;
     942           0 :     case 9:
     943           0 :       Register = ARM::R9;
     944             :       break;
     945           0 :     case 12:
     946           0 :       Register = ARM::R12;
     947             :       break;
     948             :     default:
     949             :       return MCDisassembler::Fail;
     950             :     }
     951             : 
     952           0 :   Inst.addOperand(MCOperand::createReg(Register));
     953             :   return MCDisassembler::Success;
     954             : }
     955             : 
     956        2145 : static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     957             :                                    uint64_t Address, const void *Decoder) {
     958        2145 :   DecodeStatus S = MCDisassembler::Success;
     959             : 
     960             :   const FeatureBitset &featureBits =
     961        2145 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
     962             : 
     963        2156 :   if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
     964             :     S = MCDisassembler::SoftFail;
     965             : 
     966        4290 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     967        2145 :   return S;
     968             : }
     969             : 
     970             : static const uint16_t SPRDecoderTable[] = {
     971             :      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
     972             :      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
     973             :      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
     974             :     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
     975             :     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
     976             :     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
     977             :     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
     978             :     ARM::S28, ARM::S29, ARM::S30, ARM::S31
     979             : };
     980             : 
     981         704 : static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
     982             :                                    uint64_t Address, const void *Decoder) {
     983         704 :   if (RegNo > 31)
     984             :     return MCDisassembler::Fail;
     985             : 
     986         704 :   unsigned Register = SPRDecoderTable[RegNo];
     987        1408 :   Inst.addOperand(MCOperand::createReg(Register));
     988             :   return MCDisassembler::Success;
     989             : }
     990             : 
     991             : static const uint16_t DPRDecoderTable[] = {
     992             :      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
     993             :      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
     994             :      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
     995             :     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
     996             :     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
     997             :     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
     998             :     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
     999             :     ARM::D28, ARM::D29, ARM::D30, ARM::D31
    1000             : };
    1001             : 
    1002        4337 : static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1003             :                                    uint64_t Address, const void *Decoder) {
    1004             :   const FeatureBitset &featureBits =
    1005        4337 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    1006             : 
    1007        8674 :   bool hasD16 = featureBits[ARM::FeatureD16];
    1008             : 
    1009        4337 :   if (RegNo > 31 || (hasD16 && RegNo > 15))
    1010             :     return MCDisassembler::Fail;
    1011             : 
    1012        4337 :   unsigned Register = DPRDecoderTable[RegNo];
    1013        8674 :   Inst.addOperand(MCOperand::createReg(Register));
    1014             :   return MCDisassembler::Success;
    1015             : }
    1016             : 
    1017             : static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
    1018             :                                    uint64_t Address, const void *Decoder) {
    1019             :   if (RegNo > 7)
    1020             :     return MCDisassembler::Fail;
    1021          18 :   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
    1022             : }
    1023             : 
    1024             : static DecodeStatus
    1025             : DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
    1026             :                             uint64_t Address, const void *Decoder) {
    1027             :   if (RegNo > 15)
    1028             :     return MCDisassembler::Fail;
    1029           7 :   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
    1030             : }
    1031             : 
    1032             : static const uint16_t QPRDecoderTable[] = {
    1033             :      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
    1034             :      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
    1035             :      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
    1036             :     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
    1037             : };
    1038             : 
    1039        2370 : static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1040             :                                    uint64_t Address, const void *Decoder) {
    1041        2370 :   if (RegNo > 31 || (RegNo & 1) != 0)
    1042             :     return MCDisassembler::Fail;
    1043        2362 :   RegNo >>= 1;
    1044             : 
    1045        2362 :   unsigned Register = QPRDecoderTable[RegNo];
    1046        4724 :   Inst.addOperand(MCOperand::createReg(Register));
    1047             :   return MCDisassembler::Success;
    1048             : }
    1049             : 
    1050             : static const uint16_t DPairDecoderTable[] = {
    1051             :   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
    1052             :   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
    1053             :   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
    1054             :   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
    1055             :   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
    1056             :   ARM::Q15
    1057             : };
    1058             : 
    1059         209 : static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
    1060             :                                    uint64_t Address, const void *Decoder) {
    1061         209 :   if (RegNo > 30)
    1062             :     return MCDisassembler::Fail;
    1063             : 
    1064         209 :   unsigned Register = DPairDecoderTable[RegNo];
    1065         418 :   Inst.addOperand(MCOperand::createReg(Register));
    1066             :   return MCDisassembler::Success;
    1067             : }
    1068             : 
    1069             : static const uint16_t DPairSpacedDecoderTable[] = {
    1070             :   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
    1071             :   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
    1072             :   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
    1073             :   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
    1074             :   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
    1075             :   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
    1076             :   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
    1077             :   ARM::D28_D30, ARM::D29_D31
    1078             : };
    1079             : 
    1080          61 : static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
    1081             :                                                    unsigned RegNo,
    1082             :                                                    uint64_t Address,
    1083             :                                                    const void *Decoder) {
    1084          61 :   if (RegNo > 29)
    1085             :     return MCDisassembler::Fail;
    1086             : 
    1087          61 :   unsigned Register = DPairSpacedDecoderTable[RegNo];
    1088         122 :   Inst.addOperand(MCOperand::createReg(Register));
    1089             :   return MCDisassembler::Success;
    1090             : }
    1091             : 
    1092        7949 : static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
    1093             :                                uint64_t Address, const void *Decoder) {
    1094        7949 :   if (Val == 0xF) return MCDisassembler::Fail;
    1095             :   // AL predicate is not allowed on Thumb1 branches.
    1096        6716 :   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
    1097             :     return MCDisassembler::Fail;
    1098       20148 :   Inst.addOperand(MCOperand::createImm(Val));
    1099        6716 :   if (Val == ARMCC::AL) {
    1100       12286 :     Inst.addOperand(MCOperand::createReg(0));
    1101             :   } else
    1102        1146 :     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    1103             :   return MCDisassembler::Success;
    1104             : }
    1105             : 
    1106        1736 : static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
    1107             :                                uint64_t Address, const void *Decoder) {
    1108        1736 :   if (Val)
    1109         412 :     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    1110             :   else
    1111        3060 :     Inst.addOperand(MCOperand::createReg(0));
    1112        1736 :   return MCDisassembler::Success;
    1113             : }
    1114             : 
    1115         274 : static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
    1116             :                                uint64_t Address, const void *Decoder) {
    1117         274 :   DecodeStatus S = MCDisassembler::Success;
    1118             : 
    1119         274 :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    1120         274 :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1121         274 :   unsigned imm = fieldFromInstruction(Val, 7, 5);
    1122             : 
    1123             :   // Register-immediate
    1124         548 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1125             :     return MCDisassembler::Fail;
    1126             : 
    1127         274 :   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
    1128             :   switch (type) {
    1129             :     case 0:
    1130             :       Shift = ARM_AM::lsl;
    1131             :       break;
    1132             :     case 1:
    1133             :       Shift = ARM_AM::lsr;
    1134             :       break;
    1135             :     case 2:
    1136             :       Shift = ARM_AM::asr;
    1137             :       break;
    1138             :     case 3:
    1139             :       Shift = ARM_AM::ror;
    1140             :       break;
    1141             :   }
    1142             : 
    1143         274 :   if (Shift == ARM_AM::ror && imm == 0)
    1144          37 :     Shift = ARM_AM::rrx;
    1145             : 
    1146         274 :   unsigned Op = Shift | (imm << 3);
    1147         822 :   Inst.addOperand(MCOperand::createImm(Op));
    1148             : 
    1149             :   return S;
    1150             : }
    1151             : 
    1152         122 : static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
    1153             :                                uint64_t Address, const void *Decoder) {
    1154         122 :   DecodeStatus S = MCDisassembler::Success;
    1155             : 
    1156         122 :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    1157         122 :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1158         122 :   unsigned Rs = fieldFromInstruction(Val, 8, 4);
    1159             : 
    1160             :   // Register-register
    1161         244 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1162             :     return MCDisassembler::Fail;
    1163         244 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
    1164             :     return MCDisassembler::Fail;
    1165             : 
    1166         122 :   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
    1167             :   switch (type) {
    1168             :     case 0:
    1169             :       Shift = ARM_AM::lsl;
    1170             :       break;
    1171             :     case 1:
    1172             :       Shift = ARM_AM::lsr;
    1173             :       break;
    1174             :     case 2:
    1175             :       Shift = ARM_AM::asr;
    1176             :       break;
    1177             :     case 3:
    1178             :       Shift = ARM_AM::ror;
    1179             :       break;
    1180             :   }
    1181             : 
    1182         366 :   Inst.addOperand(MCOperand::createImm(Shift));
    1183             : 
    1184             :   return S;
    1185             : }
    1186             : 
    1187        1063 : static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
    1188             :                                  uint64_t Address, const void *Decoder) {
    1189        1063 :   DecodeStatus S = MCDisassembler::Success;
    1190             : 
    1191        1063 :   bool NeedDisjointWriteback = false;
    1192        1063 :   unsigned WritebackReg = 0;
    1193        1063 :   switch (Inst.getOpcode()) {
    1194             :   default:
    1195             :     break;
    1196         157 :   case ARM::LDMIA_UPD:
    1197             :   case ARM::LDMDB_UPD:
    1198             :   case ARM::LDMIB_UPD:
    1199             :   case ARM::LDMDA_UPD:
    1200             :   case ARM::t2LDMIA_UPD:
    1201             :   case ARM::t2LDMDB_UPD:
    1202             :   case ARM::t2STMIA_UPD:
    1203             :   case ARM::t2STMDB_UPD:
    1204         157 :     NeedDisjointWriteback = true;
    1205         157 :     WritebackReg = Inst.getOperand(0).getReg();
    1206             :     break;
    1207             :   }
    1208             : 
    1209             :   // Empty register lists are not allowed.
    1210        1063 :   if (Val == 0) return MCDisassembler::Fail;
    1211       34848 :   for (unsigned i = 0; i < 16; ++i) {
    1212       16896 :     if (Val & (1 << i)) {
    1213        6824 :       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
    1214             :         return MCDisassembler::Fail;
    1215             :       // Writeback not allowed if Rn is in the target list.
    1216        3968 :       if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
    1217             :         Check(S, MCDisassembler::SoftFail);
    1218             :     }
    1219             :   }
    1220             : 
    1221             :   return S;
    1222             : }
    1223             : 
    1224          10 : static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
    1225             :                                  uint64_t Address, const void *Decoder) {
    1226          10 :   DecodeStatus S = MCDisassembler::Success;
    1227             : 
    1228          10 :   unsigned Vd = fieldFromInstruction(Val, 8, 5);
    1229          10 :   unsigned regs = fieldFromInstruction(Val, 0, 8);
    1230             : 
    1231             :   // In case of unpredictable encoding, tweak the operands.
    1232          10 :   if (regs == 0 || (Vd + regs) > 32) {
    1233           1 :     regs = Vd + regs > 32 ? 32 - Vd : regs;
    1234           2 :     regs = std::max( 1u, regs);
    1235           1 :     S = MCDisassembler::SoftFail;
    1236             :   }
    1237             : 
    1238          20 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
    1239             :     return MCDisassembler::Fail;
    1240          92 :   for (unsigned i = 0; i < (regs - 1); ++i) {
    1241          82 :     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
    1242             :       return MCDisassembler::Fail;
    1243             :   }
    1244             : 
    1245             :   return S;
    1246             : }
    1247             : 
    1248          20 : static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
    1249             :                                  uint64_t Address, const void *Decoder) {
    1250          20 :   DecodeStatus S = MCDisassembler::Success;
    1251             : 
    1252          20 :   unsigned Vd = fieldFromInstruction(Val, 8, 5);
    1253          20 :   unsigned regs = fieldFromInstruction(Val, 1, 7);
    1254             : 
    1255             :   // In case of unpredictable encoding, tweak the operands.
    1256          20 :   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
    1257           2 :     regs = Vd + regs > 32 ? 32 - Vd : regs;
    1258           4 :     regs = std::max( 1u, regs);
    1259           4 :     regs = std::min(16u, regs);
    1260           2 :     S = MCDisassembler::SoftFail;
    1261             :   }
    1262             : 
    1263          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
    1264             :       return MCDisassembler::Fail;
    1265         164 :   for (unsigned i = 0; i < (regs - 1); ++i) {
    1266         144 :     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
    1267             :       return MCDisassembler::Fail;
    1268             :   }
    1269             : 
    1270             :   return S;
    1271             : }
    1272             : 
    1273          54 : static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
    1274             :                                       uint64_t Address, const void *Decoder) {
    1275             :   // This operand encodes a mask of contiguous zeros between a specified MSB
    1276             :   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
    1277             :   // the mask of all bits LSB-and-lower, and then xor them to create
    1278             :   // the mask of that's all ones on [msb, lsb].  Finally we not it to
    1279             :   // create the final mask.
    1280          54 :   unsigned msb = fieldFromInstruction(Val, 5, 5);
    1281          54 :   unsigned lsb = fieldFromInstruction(Val, 0, 5);
    1282             : 
    1283          54 :   DecodeStatus S = MCDisassembler::Success;
    1284          54 :   if (lsb > msb) {
    1285           0 :     Check(S, MCDisassembler::SoftFail);
    1286             :     // The check above will cause the warning for the "potentially undefined
    1287             :     // instruction encoding" but we can't build a bad MCOperand value here
    1288             :     // with a lsb > msb or else printing the MCInst will cause a crash.
    1289           0 :     lsb = msb;
    1290             :   }
    1291             : 
    1292          54 :   uint32_t msb_mask = 0xFFFFFFFF;
    1293          54 :   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
    1294          54 :   uint32_t lsb_mask = (1U << lsb) - 1;
    1295             : 
    1296         162 :   Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
    1297          54 :   return S;
    1298             : }
    1299             : 
    1300          82 : static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
    1301             :                                   uint64_t Address, const void *Decoder) {
    1302          82 :   DecodeStatus S = MCDisassembler::Success;
    1303             : 
    1304          82 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1305          82 :   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
    1306          82 :   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
    1307          82 :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    1308          82 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1309          82 :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    1310             : 
    1311          82 :   switch (Inst.getOpcode()) {
    1312          58 :     case ARM::LDC_OFFSET:
    1313             :     case ARM::LDC_PRE:
    1314             :     case ARM::LDC_POST:
    1315             :     case ARM::LDC_OPTION:
    1316             :     case ARM::LDCL_OFFSET:
    1317             :     case ARM::LDCL_PRE:
    1318             :     case ARM::LDCL_POST:
    1319             :     case ARM::LDCL_OPTION:
    1320             :     case ARM::STC_OFFSET:
    1321             :     case ARM::STC_PRE:
    1322             :     case ARM::STC_POST:
    1323             :     case ARM::STC_OPTION:
    1324             :     case ARM::STCL_OFFSET:
    1325             :     case ARM::STCL_PRE:
    1326             :     case ARM::STCL_POST:
    1327             :     case ARM::STCL_OPTION:
    1328             :     case ARM::t2LDC_OFFSET:
    1329             :     case ARM::t2LDC_PRE:
    1330             :     case ARM::t2LDC_POST:
    1331             :     case ARM::t2LDC_OPTION:
    1332             :     case ARM::t2LDCL_OFFSET:
    1333             :     case ARM::t2LDCL_PRE:
    1334             :     case ARM::t2LDCL_POST:
    1335             :     case ARM::t2LDCL_OPTION:
    1336             :     case ARM::t2STC_OFFSET:
    1337             :     case ARM::t2STC_PRE:
    1338             :     case ARM::t2STC_POST:
    1339             :     case ARM::t2STC_OPTION:
    1340             :     case ARM::t2STCL_OFFSET:
    1341             :     case ARM::t2STCL_PRE:
    1342             :     case ARM::t2STCL_POST:
    1343             :     case ARM::t2STCL_OPTION:
    1344          58 :       if (coproc == 0xA || coproc == 0xB)
    1345             :         return MCDisassembler::Fail;
    1346             :       break;
    1347             :     default:
    1348             :       break;
    1349             :   }
    1350             : 
    1351             :   const FeatureBitset &featureBits =
    1352          82 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    1353         164 :   if (featureBits[ARM::HasV8Ops] && (coproc != 14))
    1354             :     return MCDisassembler::Fail;
    1355             : 
    1356         162 :   Inst.addOperand(MCOperand::createImm(coproc));
    1357         162 :   Inst.addOperand(MCOperand::createImm(CRd));
    1358         108 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1359             :     return MCDisassembler::Fail;
    1360             : 
    1361          54 :   switch (Inst.getOpcode()) {
    1362           6 :     case ARM::t2LDC2_OFFSET:
    1363             :     case ARM::t2LDC2L_OFFSET:
    1364             :     case ARM::t2LDC2_PRE:
    1365             :     case ARM::t2LDC2L_PRE:
    1366             :     case ARM::t2STC2_OFFSET:
    1367             :     case ARM::t2STC2L_OFFSET:
    1368             :     case ARM::t2STC2_PRE:
    1369             :     case ARM::t2STC2L_PRE:
    1370             :     case ARM::LDC2_OFFSET:
    1371             :     case ARM::LDC2L_OFFSET:
    1372             :     case ARM::LDC2_PRE:
    1373             :     case ARM::LDC2L_PRE:
    1374             :     case ARM::STC2_OFFSET:
    1375             :     case ARM::STC2L_OFFSET:
    1376             :     case ARM::STC2_PRE:
    1377             :     case ARM::STC2L_PRE:
    1378             :     case ARM::t2LDC_OFFSET:
    1379             :     case ARM::t2LDCL_OFFSET:
    1380             :     case ARM::t2LDC_PRE:
    1381             :     case ARM::t2LDCL_PRE:
    1382             :     case ARM::t2STC_OFFSET:
    1383             :     case ARM::t2STCL_OFFSET:
    1384             :     case ARM::t2STC_PRE:
    1385             :     case ARM::t2STCL_PRE:
    1386             :     case ARM::LDC_OFFSET:
    1387             :     case ARM::LDCL_OFFSET:
    1388             :     case ARM::LDC_PRE:
    1389             :     case ARM::LDCL_PRE:
    1390             :     case ARM::STC_OFFSET:
    1391             :     case ARM::STCL_OFFSET:
    1392             :     case ARM::STC_PRE:
    1393             :     case ARM::STCL_PRE:
    1394          12 :       imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
    1395          18 :       Inst.addOperand(MCOperand::createImm(imm));
    1396             :       break;
    1397          15 :     case ARM::t2LDC2_POST:
    1398             :     case ARM::t2LDC2L_POST:
    1399             :     case ARM::t2STC2_POST:
    1400             :     case ARM::t2STC2L_POST:
    1401             :     case ARM::LDC2_POST:
    1402             :     case ARM::LDC2L_POST:
    1403             :     case ARM::STC2_POST:
    1404             :     case ARM::STC2L_POST:
    1405             :     case ARM::t2LDC_POST:
    1406             :     case ARM::t2LDCL_POST:
    1407             :     case ARM::t2STC_POST:
    1408             :     case ARM::t2STCL_POST:
    1409             :     case ARM::LDC_POST:
    1410             :     case ARM::LDCL_POST:
    1411             :     case ARM::STC_POST:
    1412             :     case ARM::STCL_POST:
    1413          15 :       imm |= U << 8;
    1414             :       LLVM_FALLTHROUGH;
    1415          48 :     default:
    1416             :       // The 'option' variant doesn't encode 'U' in the immediate since
    1417             :       // the immediate is unsigned [0,255].
    1418         144 :       Inst.addOperand(MCOperand::createImm(imm));
    1419             :       break;
    1420             :   }
    1421             : 
    1422          54 :   switch (Inst.getOpcode()) {
    1423          24 :     case ARM::LDC_OFFSET:
    1424             :     case ARM::LDC_PRE:
    1425             :     case ARM::LDC_POST:
    1426             :     case ARM::LDC_OPTION:
    1427             :     case ARM::LDCL_OFFSET:
    1428             :     case ARM::LDCL_PRE:
    1429             :     case ARM::LDCL_POST:
    1430             :     case ARM::LDCL_OPTION:
    1431             :     case ARM::STC_OFFSET:
    1432             :     case ARM::STC_PRE:
    1433             :     case ARM::STC_POST:
    1434             :     case ARM::STC_OPTION:
    1435             :     case ARM::STCL_OFFSET:
    1436             :     case ARM::STCL_PRE:
    1437             :     case ARM::STCL_POST:
    1438             :     case ARM::STCL_OPTION:
    1439          48 :       if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1440             :         return MCDisassembler::Fail;
    1441             :       break;
    1442             :     default:
    1443             :       break;
    1444             :   }
    1445             : 
    1446             :   return S;
    1447             : }
    1448             : 
    1449             : static DecodeStatus
    1450        1919 : DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
    1451             :                               uint64_t Address, const void *Decoder) {
    1452        1919 :   DecodeStatus S = MCDisassembler::Success;
    1453             : 
    1454        1919 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1455        1919 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    1456        1919 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1457        1919 :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    1458        1919 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1459        1919 :   unsigned reg = fieldFromInstruction(Insn, 25, 1);
    1460        1919 :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    1461        1919 :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    1462             : 
    1463             :   // On stores, the writeback operand precedes Rt.
    1464        1919 :   switch (Inst.getOpcode()) {
    1465        1161 :     case ARM::STR_POST_IMM:
    1466             :     case ARM::STR_POST_REG:
    1467             :     case ARM::STRB_POST_IMM:
    1468             :     case ARM::STRB_POST_REG:
    1469             :     case ARM::STRT_POST_REG:
    1470             :     case ARM::STRT_POST_IMM:
    1471             :     case ARM::STRBT_POST_REG:
    1472             :     case ARM::STRBT_POST_IMM:
    1473        2322 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1474             :         return MCDisassembler::Fail;
    1475             :       break;
    1476             :     default:
    1477             :       break;
    1478             :   }
    1479             : 
    1480        3838 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    1481             :     return MCDisassembler::Fail;
    1482             : 
    1483             :   // On loads, the writeback operand comes after Rt.
    1484        1919 :   switch (Inst.getOpcode()) {
    1485         758 :     case ARM::LDR_POST_IMM:
    1486             :     case ARM::LDR_POST_REG:
    1487             :     case ARM::LDRB_POST_IMM:
    1488             :     case ARM::LDRB_POST_REG:
    1489             :     case ARM::LDRBT_POST_REG:
    1490             :     case ARM::LDRBT_POST_IMM:
    1491             :     case ARM::LDRT_POST_REG:
    1492             :     case ARM::LDRT_POST_IMM:
    1493        1516 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1494             :         return MCDisassembler::Fail;
    1495             :       break;
    1496             :     default:
    1497             :       break;
    1498             :   }
    1499             : 
    1500        3838 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1501             :     return MCDisassembler::Fail;
    1502             : 
    1503        1919 :   ARM_AM::AddrOpc Op = ARM_AM::add;
    1504        1919 :   if (!fieldFromInstruction(Insn, 23, 1))
    1505         346 :     Op = ARM_AM::sub;
    1506             : 
    1507        1919 :   bool writeback = (P == 0) || (W == 1);
    1508        1919 :   unsigned idx_mode = 0;
    1509        1919 :   if (P && writeback)
    1510             :     idx_mode = ARMII::IndexModePre;
    1511        1919 :   else if (!P && writeback)
    1512        1919 :     idx_mode = ARMII::IndexModePost;
    1513             : 
    1514        1919 :   if (writeback && (Rn == 15 || Rn == Rt))
    1515          80 :     S = MCDisassembler::SoftFail; // UNPREDICTABLE
    1516             : 
    1517        1919 :   if (reg) {
    1518          42 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1519             :       return MCDisassembler::Fail;
    1520          21 :     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
    1521          21 :     switch( fieldFromInstruction(Insn, 5, 2)) {
    1522             :       case 0:
    1523             :         Opc = ARM_AM::lsl;
    1524             :         break;
    1525           2 :       case 1:
    1526           2 :         Opc = ARM_AM::lsr;
    1527             :         break;
    1528           4 :       case 2:
    1529           4 :         Opc = ARM_AM::asr;
    1530             :         break;
    1531           0 :       case 3:
    1532           0 :         Opc = ARM_AM::ror;
    1533             :         break;
    1534             :       default:
    1535             :         return MCDisassembler::Fail;
    1536             :     }
    1537          21 :     unsigned amt = fieldFromInstruction(Insn, 7, 5);
    1538          21 :     if (Opc == ARM_AM::ror && amt == 0)
    1539           0 :       Opc = ARM_AM::rrx;
    1540          21 :     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
    1541             : 
    1542          63 :     Inst.addOperand(MCOperand::createImm(imm));
    1543             :   } else {
    1544        3796 :     Inst.addOperand(MCOperand::createReg(0));
    1545        1898 :     unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
    1546        5694 :     Inst.addOperand(MCOperand::createImm(tmp));
    1547             :   }
    1548             : 
    1549        3838 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1550             :     return MCDisassembler::Fail;
    1551             : 
    1552             :   return S;
    1553             : }
    1554             : 
    1555          33 : static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
    1556             :                                   uint64_t Address, const void *Decoder) {
    1557          33 :   DecodeStatus S = MCDisassembler::Success;
    1558             : 
    1559          33 :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    1560          33 :   unsigned Rm = fieldFromInstruction(Val,  0, 4);
    1561          33 :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1562          33 :   unsigned imm = fieldFromInstruction(Val, 7, 5);
    1563          33 :   unsigned U = fieldFromInstruction(Val, 12, 1);
    1564             : 
    1565          33 :   ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
    1566             :   switch (type) {
    1567             :     case 0:
    1568             :       ShOp = ARM_AM::lsl;
    1569             :       break;
    1570             :     case 1:
    1571             :       ShOp = ARM_AM::lsr;
    1572             :       break;
    1573             :     case 2:
    1574             :       ShOp = ARM_AM::asr;
    1575             :       break;
    1576             :     case 3:
    1577             :       ShOp = ARM_AM::ror;
    1578             :       break;
    1579             :   }
    1580             : 
    1581          33 :   if (ShOp == ARM_AM::ror && imm == 0)
    1582           0 :     ShOp = ARM_AM::rrx;
    1583             : 
    1584          66 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1585             :     return MCDisassembler::Fail;
    1586          66 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1587             :     return MCDisassembler::Fail;
    1588             :   unsigned shift;
    1589          33 :   if (U)
    1590          15 :     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
    1591             :   else
    1592          18 :     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
    1593          99 :   Inst.addOperand(MCOperand::createImm(shift));
    1594             : 
    1595             :   return S;
    1596             : }
    1597             : 
    1598             : static DecodeStatus
    1599         409 : DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
    1600             :                            uint64_t Address, const void *Decoder) {
    1601         409 :   DecodeStatus S = MCDisassembler::Success;
    1602             : 
    1603         409 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    1604         409 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1605         409 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1606         409 :   unsigned type = fieldFromInstruction(Insn, 22, 1);
    1607         409 :   unsigned imm = fieldFromInstruction(Insn, 8, 4);
    1608         409 :   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
    1609         409 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1610         409 :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    1611         409 :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    1612         409 :   unsigned Rt2 = Rt + 1;
    1613             : 
    1614         409 :   bool writeback = (W == 1) | (P == 0);
    1615             : 
    1616             :   // For {LD,ST}RD, Rt must be even, else undefined.
    1617         409 :   switch (Inst.getOpcode()) {
    1618          31 :     case ARM::STRD:
    1619             :     case ARM::STRD_PRE:
    1620             :     case ARM::STRD_POST:
    1621             :     case ARM::LDRD:
    1622             :     case ARM::LDRD_PRE:
    1623             :     case ARM::LDRD_POST:
    1624          31 :       if (Rt & 0x1) S = MCDisassembler::SoftFail;
    1625             :       break;
    1626             :     default:
    1627             :       break;
    1628             :   }
    1629         409 :   switch (Inst.getOpcode()) {
    1630          14 :     case ARM::STRD:
    1631             :     case ARM::STRD_PRE:
    1632             :     case ARM::STRD_POST:
    1633          14 :       if (P == 0 && W == 1)
    1634           0 :         S = MCDisassembler::SoftFail;
    1635             : 
    1636          14 :       if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
    1637           0 :         S = MCDisassembler::SoftFail;
    1638          14 :       if (type && Rm == 15)
    1639           0 :         S = MCDisassembler::SoftFail;
    1640          14 :       if (Rt2 == 15)
    1641           0 :         S = MCDisassembler::SoftFail;
    1642          20 :       if (!type && fieldFromInstruction(Insn, 8, 4))
    1643             :         S = MCDisassembler::SoftFail;
    1644             :       break;
    1645         177 :     case ARM::STRH:
    1646             :     case ARM::STRH_PRE:
    1647             :     case ARM::STRH_POST:
    1648         177 :       if (Rt == 15)
    1649           0 :         S = MCDisassembler::SoftFail;
    1650         177 :       if (writeback && (Rn == 15 || Rn == Rt))
    1651           0 :         S = MCDisassembler::SoftFail;
    1652         177 :       if (!type && Rm == 15)
    1653           0 :         S = MCDisassembler::SoftFail;
    1654             :       break;
    1655          17 :     case ARM::LDRD:
    1656             :     case ARM::LDRD_PRE:
    1657             :     case ARM::LDRD_POST:
    1658          17 :       if (type && Rn == 15) {
    1659           1 :         if (Rt2 == 15)
    1660           1 :           S = MCDisassembler::SoftFail;
    1661             :         break;
    1662             :       }
    1663          16 :       if (P == 0 && W == 1)
    1664           0 :         S = MCDisassembler::SoftFail;
    1665          16 :       if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
    1666           0 :         S = MCDisassembler::SoftFail;
    1667          16 :       if (!type && writeback && Rn == 15)
    1668           0 :         S = MCDisassembler::SoftFail;
    1669          16 :       if (writeback && (Rn == Rt || Rn == Rt2))
    1670           1 :         S = MCDisassembler::SoftFail;
    1671             :       break;
    1672         178 :     case ARM::LDRH:
    1673             :     case ARM::LDRH_PRE:
    1674             :     case ARM::LDRH_POST:
    1675         178 :       if (type && Rn == 15) {
    1676           0 :         if (Rt == 15)
    1677           0 :           S = MCDisassembler::SoftFail;
    1678             :         break;
    1679             :       }
    1680         178 :       if (Rt == 15)
    1681           0 :         S = MCDisassembler::SoftFail;
    1682         178 :       if (!type && Rm == 15)
    1683           0 :         S = MCDisassembler::SoftFail;
    1684         178 :       if (!type && writeback && (Rn == 15 || Rn == Rt))
    1685           0 :         S = MCDisassembler::SoftFail;
    1686             :       break;
    1687          23 :     case ARM::LDRSH:
    1688             :     case ARM::LDRSH_PRE:
    1689             :     case ARM::LDRSH_POST:
    1690             :     case ARM::LDRSB:
    1691             :     case ARM::LDRSB_PRE:
    1692             :     case ARM::LDRSB_POST:
    1693          23 :       if (type && Rn == 15) {
    1694           3 :         if (Rt == 15)
    1695           3 :           S = MCDisassembler::SoftFail;
    1696             :         break;
    1697             :       }
    1698          20 :       if (type && (Rt == 15 || (writeback && Rn == Rt)))
    1699           0 :         S = MCDisassembler::SoftFail;
    1700          20 :       if (!type && (Rt == 15 || Rm == 15))
    1701           0 :         S = MCDisassembler::SoftFail;
    1702          20 :       if (!type && writeback && (Rn == 15 || Rn == Rt))
    1703           0 :         S = MCDisassembler::SoftFail;
    1704             :       break;
    1705             :     default:
    1706             :       break;
    1707             :   }
    1708             : 
    1709         409 :   if (writeback) { // Writeback
    1710         383 :     if (P)
    1711          22 :       U |= ARMII::IndexModePre << 9;
    1712             :     else
    1713         361 :       U |= ARMII::IndexModePost << 9;
    1714             : 
    1715             :     // On stores, the writeback operand precedes Rt.
    1716         383 :     switch (Inst.getOpcode()) {
    1717         183 :     case ARM::STRD:
    1718             :     case ARM::STRD_PRE:
    1719             :     case ARM::STRD_POST:
    1720             :     case ARM::STRH:
    1721             :     case ARM::STRH_PRE:
    1722             :     case ARM::STRH_POST:
    1723         366 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1724             :         return MCDisassembler::Fail;
    1725             :       break;
    1726             :     default:
    1727             :       break;
    1728             :     }
    1729             :   }
    1730             : 
    1731         818 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    1732             :     return MCDisassembler::Fail;
    1733         409 :   switch (Inst.getOpcode()) {
    1734          31 :     case ARM::STRD:
    1735             :     case ARM::STRD_PRE:
    1736             :     case ARM::STRD_POST:
    1737             :     case ARM::LDRD:
    1738             :     case ARM::LDRD_PRE:
    1739             :     case ARM::LDRD_POST:
    1740          62 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
    1741             :         return MCDisassembler::Fail;
    1742             :       break;
    1743             :     default:
    1744             :       break;
    1745             :   }
    1746             : 
    1747         409 :   if (writeback) {
    1748             :     // On loads, the writeback operand comes after Rt.
    1749         383 :     switch (Inst.getOpcode()) {
    1750         200 :     case ARM::LDRD:
    1751             :     case ARM::LDRD_PRE:
    1752             :     case ARM::LDRD_POST:
    1753             :     case ARM::LDRH:
    1754             :     case ARM::LDRH_PRE:
    1755             :     case ARM::LDRH_POST:
    1756             :     case ARM::LDRSH:
    1757             :     case ARM::LDRSH_PRE:
    1758             :     case ARM::LDRSH_POST:
    1759             :     case ARM::LDRSB:
    1760             :     case ARM::LDRSB_PRE:
    1761             :     case ARM::LDRSB_POST:
    1762             :     case ARM::LDRHTr:
    1763             :     case ARM::LDRSBTr:
    1764         400 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1765             :         return MCDisassembler::Fail;
    1766             :       break;
    1767             :     default:
    1768             :       break;
    1769             :     }
    1770             :   }
    1771             : 
    1772         818 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1773             :     return MCDisassembler::Fail;
    1774             : 
    1775         409 :   if (type) {
    1776         748 :     Inst.addOperand(MCOperand::createReg(0));
    1777        1122 :     Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
    1778             :   } else {
    1779          70 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1780             :     return MCDisassembler::Fail;
    1781         105 :     Inst.addOperand(MCOperand::createImm(U));
    1782             :   }
    1783             : 
    1784         818 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1785             :     return MCDisassembler::Fail;
    1786             : 
    1787             :   return S;
    1788             : }
    1789             : 
    1790           1 : static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
    1791             :                                  uint64_t Address, const void *Decoder) {
    1792           1 :   DecodeStatus S = MCDisassembler::Success;
    1793             : 
    1794           1 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1795           1 :   unsigned mode = fieldFromInstruction(Insn, 23, 2);
    1796             : 
    1797           1 :   switch (mode) {
    1798           0 :     case 0:
    1799           0 :       mode = ARM_AM::da;
    1800             :       break;
    1801           0 :     case 1:
    1802           0 :       mode = ARM_AM::ia;
    1803             :       break;
    1804           1 :     case 2:
    1805           1 :       mode = ARM_AM::db;
    1806             :       break;
    1807           0 :     case 3:
    1808           0 :       mode = ARM_AM::ib;
    1809             :       break;
    1810             :   }
    1811             : 
    1812           3 :   Inst.addOperand(MCOperand::createImm(mode));
    1813           2 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1814             :     return MCDisassembler::Fail;
    1815             : 
    1816             :   return S;
    1817             : }
    1818             : 
    1819           2 : static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
    1820             :                                uint64_t Address, const void *Decoder) {
    1821           2 :   DecodeStatus S = MCDisassembler::Success;
    1822             : 
    1823           2 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    1824           2 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1825           2 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1826           2 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1827             : 
    1828           2 :   if (pred == 0xF)
    1829           0 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    1830             : 
    1831           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    1832             :     return MCDisassembler::Fail;
    1833           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1834             :     return MCDisassembler::Fail;
    1835           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    1836             :     return MCDisassembler::Fail;
    1837           4 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1838             :     return MCDisassembler::Fail;
    1839             :   return S;
    1840             : }
    1841             : 
    1842         274 : static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
    1843             :                                   unsigned Insn,
    1844             :                                   uint64_t Address, const void *Decoder) {
    1845         274 :   DecodeStatus S = MCDisassembler::Success;
    1846             : 
    1847         274 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1848         274 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1849         274 :   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
    1850             : 
    1851         274 :   if (pred == 0xF) {
    1852             :     // Ambiguous with RFE and SRS
    1853           7 :     switch (Inst.getOpcode()) {
    1854             :       case ARM::LDMDA:
    1855           0 :         Inst.setOpcode(ARM::RFEDA);
    1856             :         break;
    1857             :       case ARM::LDMDA_UPD:
    1858           0 :         Inst.setOpcode(ARM::RFEDA_UPD);
    1859             :         break;
    1860             :       case ARM::LDMDB:
    1861           0 :         Inst.setOpcode(ARM::RFEDB);
    1862             :         break;
    1863             :       case ARM::LDMDB_UPD:
    1864           1 :         Inst.setOpcode(ARM::RFEDB_UPD);
    1865             :         break;
    1866             :       case ARM::LDMIA:
    1867           0 :         Inst.setOpcode(ARM::RFEIA);
    1868             :         break;
    1869             :       case ARM::LDMIA_UPD:
    1870           0 :         Inst.setOpcode(ARM::RFEIA_UPD);
    1871             :         break;
    1872             :       case ARM::LDMIB:
    1873           0 :         Inst.setOpcode(ARM::RFEIB);
    1874             :         break;
    1875             :       case ARM::LDMIB_UPD:
    1876           0 :         Inst.setOpcode(ARM::RFEIB_UPD);
    1877             :         break;
    1878             :       case ARM::STMDA:
    1879           0 :         Inst.setOpcode(ARM::SRSDA);
    1880             :         break;
    1881             :       case ARM::STMDA_UPD:
    1882           1 :         Inst.setOpcode(ARM::SRSDA_UPD);
    1883             :         break;
    1884             :       case ARM::STMDB:
    1885           0 :         Inst.setOpcode(ARM::SRSDB);
    1886             :         break;
    1887             :       case ARM::STMDB_UPD:
    1888           0 :         Inst.setOpcode(ARM::SRSDB_UPD);
    1889             :         break;
    1890             :       case ARM::STMIA:
    1891           0 :         Inst.setOpcode(ARM::SRSIA);
    1892             :         break;
    1893             :       case ARM::STMIA_UPD:
    1894           2 :         Inst.setOpcode(ARM::SRSIA_UPD);
    1895             :         break;
    1896             :       case ARM::STMIB:
    1897           0 :         Inst.setOpcode(ARM::SRSIB);
    1898             :         break;
    1899             :       case ARM::STMIB_UPD:
    1900           0 :         Inst.setOpcode(ARM::SRSIB_UPD);
    1901             :         break;
    1902             :       default:
    1903             :         return MCDisassembler::Fail;
    1904             :     }
    1905             : 
    1906             :     // For stores (which become SRS's, the only operand is the mode.
    1907           4 :     if (fieldFromInstruction(Insn, 20, 1) == 0) {
    1908             :       // Check SRS encoding constraints
    1909           3 :       if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
    1910           0 :             fieldFromInstruction(Insn, 20, 1) == 0))
    1911             :         return MCDisassembler::Fail;
    1912             : 
    1913           0 :       Inst.addOperand(
    1914           0 :           MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
    1915             :       return S;
    1916             :     }
    1917             : 
    1918           1 :     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
    1919             :   }
    1920             : 
    1921         534 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1922             :     return MCDisassembler::Fail;
    1923         534 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1924             :     return MCDisassembler::Fail; // Tied
    1925         534 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1926             :     return MCDisassembler::Fail;
    1927         534 :   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
    1928             :     return MCDisassembler::Fail;
    1929             : 
    1930             :   return S;
    1931             : }
    1932             : 
    1933             : // Check for UNPREDICTABLE predicated ESB instruction
    1934          39 : static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
    1935             :                                  uint64_t Address, const void *Decoder) {
    1936          39 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1937          39 :   unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
    1938          39 :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
    1939          39 :   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
    1940             : 
    1941          39 :   DecodeStatus S = MCDisassembler::Success;
    1942             : 
    1943         117 :   Inst.addOperand(MCOperand::createImm(imm8));
    1944             : 
    1945          78 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1946             :     return MCDisassembler::Fail;
    1947             : 
    1948             :   // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
    1949             :   // so all predicates should be allowed.
    1950          39 :   if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
    1951             :     S = MCDisassembler::SoftFail;
    1952             : 
    1953             :   return S;
    1954             : }
    1955             : 
    1956          15 : static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
    1957             :                                  uint64_t Address, const void *Decoder) {
    1958          15 :   unsigned imod = fieldFromInstruction(Insn, 18, 2);
    1959          15 :   unsigned M = fieldFromInstruction(Insn, 17, 1);
    1960          15 :   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
    1961          15 :   unsigned mode = fieldFromInstruction(Insn, 0, 5);
    1962             : 
    1963          15 :   DecodeStatus S = MCDisassembler::Success;
    1964             : 
    1965             :   // This decoder is called from multiple location that do not check
    1966             :   // the full encoding is valid before they do.
    1967          29 :   if (fieldFromInstruction(Insn, 5, 1) != 0 ||
    1968          43 :       fieldFromInstruction(Insn, 16, 1) != 0 ||
    1969          14 :       fieldFromInstruction(Insn, 20, 8) != 0x10)
    1970             :     return MCDisassembler::Fail;
    1971             : 
    1972             :   // imod == '01' --> UNPREDICTABLE
    1973             :   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
    1974             :   // return failure here.  The '01' imod value is unprintable, so there's
    1975             :   // nothing useful we could do even if we returned UNPREDICTABLE.
    1976             : 
    1977          10 :   if (imod == 1) return MCDisassembler::Fail;
    1978             : 
    1979           9 :   if (imod && M) {
    1980           8 :     Inst.setOpcode(ARM::CPS3p);
    1981          12 :     Inst.addOperand(MCOperand::createImm(imod));
    1982          12 :     Inst.addOperand(MCOperand::createImm(iflags));
    1983          12 :     Inst.addOperand(MCOperand::createImm(mode));
    1984           5 :   } else if (imod && !M) {
    1985           4 :     Inst.setOpcode(ARM::CPS2p);
    1986           6 :     Inst.addOperand(MCOperand::createImm(imod));
    1987           6 :     Inst.addOperand(MCOperand::createImm(iflags));
    1988           2 :     if (mode) S = MCDisassembler::SoftFail;
    1989           3 :   } else if (!imod && M) {
    1990           6 :     Inst.setOpcode(ARM::CPS1p);
    1991           9 :     Inst.addOperand(MCOperand::createImm(mode));
    1992           3 :     if (iflags) S = MCDisassembler::SoftFail;
    1993             :   } else {
    1994             :     // imod == '00' && M == '0' --> UNPREDICTABLE
    1995           0 :     Inst.setOpcode(ARM::CPS1p);
    1996           0 :     Inst.addOperand(MCOperand::createImm(mode));
    1997           0 :     S = MCDisassembler::SoftFail;
    1998             :   }
    1999             : 
    2000             :   return S;
    2001             : }
    2002             : 
    2003           3 : static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
    2004             :                                  uint64_t Address, const void *Decoder) {
    2005           3 :   unsigned imod = fieldFromInstruction(Insn, 9, 2);
    2006           3 :   unsigned M = fieldFromInstruction(Insn, 8, 1);
    2007           3 :   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
    2008           3 :   unsigned mode = fieldFromInstruction(Insn, 0, 5);
    2009             : 
    2010           3 :   DecodeStatus S = MCDisassembler::Success;
    2011             : 
    2012             :   // imod == '01' --> UNPREDICTABLE
    2013             :   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
    2014             :   // return failure here.  The '01' imod value is unprintable, so there's
    2015             :   // nothing useful we could do even if we returned UNPREDICTABLE.
    2016             : 
    2017           3 :   if (imod == 1) return MCDisassembler::Fail;
    2018             : 
    2019           3 :   if (imod && M) {
    2020           2 :     Inst.setOpcode(ARM::t2CPS3p);
    2021           3 :     Inst.addOperand(MCOperand::createImm(imod));
    2022           3 :     Inst.addOperand(MCOperand::createImm(iflags));
    2023           3 :     Inst.addOperand(MCOperand::createImm(mode));
    2024           2 :   } else if (imod && !M) {
    2025           2 :     Inst.setOpcode(ARM::t2CPS2p);
    2026           3 :     Inst.addOperand(MCOperand::createImm(imod));
    2027           3 :     Inst.addOperand(MCOperand::createImm(iflags));
    2028           1 :     if (mode) S = MCDisassembler::SoftFail;
    2029           1 :   } else if (!imod && M) {
    2030           2 :     Inst.setOpcode(ARM::t2CPS1p);
    2031           3 :     Inst.addOperand(MCOperand::createImm(mode));
    2032           1 :     if (iflags) S = MCDisassembler::SoftFail;
    2033             :   } else {
    2034             :     // imod == '00' && M == '0' --> this is a HINT instruction
    2035           0 :     int imm = fieldFromInstruction(Insn, 0, 8);
    2036             :     // HINT are defined only for immediate in [0..4]
    2037           0 :     if(imm > 4) return MCDisassembler::Fail;
    2038           0 :     Inst.setOpcode(ARM::t2HINT);
    2039           0 :     Inst.addOperand(MCOperand::createImm(imm));
    2040             :   }
    2041             : 
    2042             :   return S;
    2043             : }
    2044             : 
    2045         184 : static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
    2046             :                                  uint64_t Address, const void *Decoder) {
    2047         184 :   DecodeStatus S = MCDisassembler::Success;
    2048             : 
    2049         184 :   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
    2050         184 :   unsigned imm = 0;
    2051             : 
    2052         184 :   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
    2053         184 :   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
    2054         184 :   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
    2055         184 :   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
    2056             : 
    2057         184 :   if (Inst.getOpcode() == ARM::t2MOVTi16)
    2058         118 :     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
    2059             :       return MCDisassembler::Fail;
    2060         368 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
    2061             :     return MCDisassembler::Fail;
    2062             : 
    2063         368 :   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
    2064         507 :     Inst.addOperand(MCOperand::createImm(imm));
    2065             : 
    2066             :   return S;
    2067             : }
    2068             : 
    2069         195 : static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
    2070             :                                  uint64_t Address, const void *Decoder) {
    2071         195 :   DecodeStatus S = MCDisassembler::Success;
    2072             : 
    2073         195 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2074         195 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2075         195 :   unsigned imm = 0;
    2076             : 
    2077         195 :   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
    2078         195 :   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
    2079             : 
    2080         195 :   if (Inst.getOpcode() == ARM::MOVTi16)
    2081         176 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2082             :       return MCDisassembler::Fail;
    2083             : 
    2084         390 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2085             :     return MCDisassembler::Fail;
    2086             : 
    2087         390 :   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
    2088         570 :     Inst.addOperand(MCOperand::createImm(imm));
    2089             : 
    2090         390 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2091             :     return MCDisassembler::Fail;
    2092             : 
    2093         138 :   return S;
    2094             : }
    2095             : 
    2096          17 : static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
    2097             :                                  uint64_t Address, const void *Decoder) {
    2098          17 :   DecodeStatus S = MCDisassembler::Success;
    2099             : 
    2100          17 :   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
    2101          17 :   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
    2102          17 :   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
    2103          17 :   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
    2104          17 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2105             : 
    2106          17 :   if (pred == 0xF)
    2107           5 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    2108             : 
    2109          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2110             :     return MCDisassembler::Fail;
    2111          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    2112             :     return MCDisassembler::Fail;
    2113          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    2114             :     return MCDisassembler::Fail;
    2115          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
    2116             :     return MCDisassembler::Fail;
    2117             : 
    2118          24 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2119             :     return MCDisassembler::Fail;
    2120             : 
    2121             :   return S;
    2122             : }
    2123             : 
    2124           5 : static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
    2125             :                                   uint64_t Address, const void *Decoder) {
    2126           5 :   DecodeStatus S = MCDisassembler::Success;
    2127             : 
    2128           5 :   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
    2129           5 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2130           5 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2131             : 
    2132           5 :   if (Pred == 0xF)
    2133           2 :     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
    2134             : 
    2135           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2136             :     return MCDisassembler::Fail;
    2137           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2138             :     return MCDisassembler::Fail;
    2139           6 :   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
    2140             :     return MCDisassembler::Fail;
    2141             : 
    2142             :   return S;
    2143             : }
    2144             : 
    2145           2 : static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
    2146             :                                   uint64_t Address, const void *Decoder) {
    2147           2 :   DecodeStatus S = MCDisassembler::Success;
    2148             : 
    2149           2 :   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
    2150             : 
    2151           2 :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
    2152           2 :   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
    2153             : 
    2154           5 :   if (!FeatureBits[ARM::HasV8_1aOps] || 
    2155           2 :       !FeatureBits[ARM::HasV8Ops])
    2156             :     return MCDisassembler::Fail;
    2157             : 
    2158             :   // Decoder can be called from DecodeTST, which does not check the full
    2159             :   // encoding is valid.
    2160           2 :   if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
    2161           1 :       fieldFromInstruction(Insn, 4,4) != 0)
    2162             :     return MCDisassembler::Fail;
    2163           2 :   if (fieldFromInstruction(Insn, 10,10) != 0 ||
    2164           1 :       fieldFromInstruction(Insn, 0,4) != 0)
    2165             :     S = MCDisassembler::SoftFail;
    2166             : 
    2167           2 :   Inst.setOpcode(ARM::SETPAN);
    2168           3 :   Inst.addOperand(MCOperand::createImm(Imm));
    2169             : 
    2170             :   return S;
    2171             : }
    2172             : 
    2173         108 : static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
    2174             :                            uint64_t Address, const void *Decoder) {
    2175         108 :   DecodeStatus S = MCDisassembler::Success;
    2176             : 
    2177         108 :   unsigned add = fieldFromInstruction(Val, 12, 1);
    2178         108 :   unsigned imm = fieldFromInstruction(Val, 0, 12);
    2179         108 :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    2180             : 
    2181         216 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2182             :     return MCDisassembler::Fail;
    2183             : 
    2184         108 :   if (!add) imm *= -1;
    2185         108 :   if (imm == 0 && !add) imm = INT32_MIN;
    2186         324 :   Inst.addOperand(MCOperand::createImm(imm));
    2187         108 :   if (Rn == 15)
    2188          43 :     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
    2189             : 
    2190             :   return S;
    2191             : }
    2192             : 
    2193          19 : static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
    2194             :                                    uint64_t Address, const void *Decoder) {
    2195          19 :   DecodeStatus S = MCDisassembler::Success;
    2196             : 
    2197          19 :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    2198             :   // U == 1 to add imm, 0 to subtract it.
    2199          19 :   unsigned U = fieldFromInstruction(Val, 8, 1);
    2200          19 :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    2201             : 
    2202          38 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2203             :     return MCDisassembler::Fail;
    2204             : 
    2205          19 :   if (U)
    2206          60 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
    2207             :   else
    2208          16 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
    2209             : 
    2210             :   return S;
    2211             : }
    2212             : 
    2213          16 : static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
    2214             :                                    uint64_t Address, const void *Decoder) {
    2215          16 :   DecodeStatus S = MCDisassembler::Success;
    2216             : 
    2217          16 :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    2218             :   // U == 1 to add imm, 0 to subtract it.
    2219          16 :   unsigned U = fieldFromInstruction(Val, 8, 1);
    2220          16 :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    2221             : 
    2222          32 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2223             :     return MCDisassembler::Fail;
    2224             : 
    2225          16 :   if (U)
    2226          32 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
    2227             :   else
    2228          32 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
    2229             : 
    2230             :   return S;
    2231             : }
    2232             : 
    2233             : static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
    2234             :                                    uint64_t Address, const void *Decoder) {
    2235          74 :   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
    2236             : }
    2237             : 
    2238             : static DecodeStatus
    2239          26 : DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
    2240             :                      uint64_t Address, const void *Decoder) {
    2241          26 :   DecodeStatus Status = MCDisassembler::Success;
    2242             : 
    2243             :   // Note the J1 and J2 values are from the encoded instruction.  So here
    2244             :   // change them to I1 and I2 values via as documented:
    2245             :   // I1 = NOT(J1 EOR S);
    2246             :   // I2 = NOT(J2 EOR S);
    2247             :   // and build the imm32 with one trailing zero as documented:
    2248             :   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
    2249          26 :   unsigned S = fieldFromInstruction(Insn, 26, 1);
    2250          26 :   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
    2251          26 :   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
    2252          26 :   unsigned I1 = !(J1 ^ S);
    2253          26 :   unsigned I2 = !(J2 ^ S);
    2254          26 :   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
    2255          26 :   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
    2256          26 :   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
    2257          52 :   int imm32 = SignExtend32<25>(tmp << 1);
    2258          52 :   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
    2259             :                                 true, 4, Inst, Decoder))
    2260          78 :     Inst.addOperand(MCOperand::createImm(imm32));
    2261             : 
    2262          26 :   return Status;
    2263             : }
    2264             : 
    2265             : static DecodeStatus
    2266         276 : DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
    2267             :                            uint64_t Address, const void *Decoder) {
    2268         276 :   DecodeStatus S = MCDisassembler::Success;
    2269             : 
    2270         276 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2271         276 :   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
    2272             : 
    2273         276 :   if (pred == 0xF) {
    2274          38 :     Inst.setOpcode(ARM::BLXi);
    2275          19 :     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
    2276          38 :     if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
    2277             :                                   true, 4, Inst, Decoder))
    2278          57 :     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
    2279             :     return S;
    2280             :   }
    2281             : 
    2282         514 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
    2283             :                                 true, 4, Inst, Decoder))
    2284         771 :     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
    2285         514 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2286             :     return MCDisassembler::Fail;
    2287             : 
    2288         257 :   return S;
    2289             : }
    2290             : 
    2291         626 : static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
    2292             :                                    uint64_t Address, const void *Decoder) {
    2293         626 :   DecodeStatus S = MCDisassembler::Success;
    2294             : 
    2295         626 :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    2296         626 :   unsigned align = fieldFromInstruction(Val, 4, 2);
    2297             : 
    2298        1252 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2299             :     return MCDisassembler::Fail;
    2300         626 :   if (!align)
    2301        1120 :     Inst.addOperand(MCOperand::createImm(0));
    2302             :   else
    2303         198 :     Inst.addOperand(MCOperand::createImm(4 << align));
    2304             : 
    2305             :   return S;
    2306             : }
    2307             : 
    2308         322 : static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
    2309             :                                    uint64_t Address, const void *Decoder) {
    2310         322 :   DecodeStatus S = MCDisassembler::Success;
    2311             : 
    2312         322 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2313         322 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2314         322 :   unsigned wb = fieldFromInstruction(Insn, 16, 4);
    2315         322 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2316         322 :   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
    2317         322 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2318             : 
    2319             :   // First output register
    2320         322 :   switch (Inst.getOpcode()) {
    2321          93 :   case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
    2322             :   case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
    2323             :   case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
    2324             :   case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
    2325             :   case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
    2326             :   case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
    2327             :   case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
    2328             :   case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
    2329             :   case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
    2330         186 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2331             :       return MCDisassembler::Fail;
    2332             :     break;
    2333          18 :   case ARM::VLD2b16:
    2334             :   case ARM::VLD2b32:
    2335             :   case ARM::VLD2b8:
    2336             :   case ARM::VLD2b16wb_fixed:
    2337             :   case ARM::VLD2b16wb_register:
    2338             :   case ARM::VLD2b32wb_fixed:
    2339             :   case ARM::VLD2b32wb_register:
    2340             :   case ARM::VLD2b8wb_fixed:
    2341             :   case ARM::VLD2b8wb_register:
    2342          36 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2343             :       return MCDisassembler::Fail;
    2344             :     break;
    2345         211 :   default:
    2346         422 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2347             :       return MCDisassembler::Fail;
    2348             :   }
    2349             : 
    2350             :   // Second output register
    2351         322 :   switch (Inst.getOpcode()) {
    2352          37 :     case ARM::VLD3d8:
    2353             :     case ARM::VLD3d16:
    2354             :     case ARM::VLD3d32:
    2355             :     case ARM::VLD3d8_UPD:
    2356             :     case ARM::VLD3d16_UPD:
    2357             :     case ARM::VLD3d32_UPD:
    2358             :     case ARM::VLD4d8:
    2359             :     case ARM::VLD4d16:
    2360             :     case ARM::VLD4d32:
    2361             :     case ARM::VLD4d8_UPD:
    2362             :     case ARM::VLD4d16_UPD:
    2363             :     case ARM::VLD4d32_UPD:
    2364          74 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
    2365             :         return MCDisassembler::Fail;
    2366             :       break;
    2367          49 :     case ARM::VLD3q8:
    2368             :     case ARM::VLD3q16:
    2369             :     case ARM::VLD3q32:
    2370             :     case ARM::VLD3q8_UPD:
    2371             :     case ARM::VLD3q16_UPD:
    2372             :     case ARM::VLD3q32_UPD:
    2373             :     case ARM::VLD4q8:
    2374             :     case ARM::VLD4q16:
    2375             :     case ARM::VLD4q32:
    2376             :     case ARM::VLD4q8_UPD:
    2377             :     case ARM::VLD4q16_UPD:
    2378             :     case ARM::VLD4q32_UPD:
    2379          98 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2380             :         return MCDisassembler::Fail;
    2381             :     default:
    2382             :       break;
    2383             :   }
    2384             : 
    2385             :   // Third output register
    2386         322 :   switch(Inst.getOpcode()) {
    2387          37 :     case ARM::VLD3d8:
    2388             :     case ARM::VLD3d16:
    2389             :     case ARM::VLD3d32:
    2390             :     case ARM::VLD3d8_UPD:
    2391             :     case ARM::VLD3d16_UPD:
    2392             :     case ARM::VLD3d32_UPD:
    2393             :     case ARM::VLD4d8:
    2394             :     case ARM::VLD4d16:
    2395             :     case ARM::VLD4d32:
    2396             :     case ARM::VLD4d8_UPD:
    2397             :     case ARM::VLD4d16_UPD:
    2398             :     case ARM::VLD4d32_UPD:
    2399          74 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2400             :         return MCDisassembler::Fail;
    2401             :       break;
    2402          49 :     case ARM::VLD3q8:
    2403             :     case ARM::VLD3q16:
    2404             :     case ARM::VLD3q32:
    2405             :     case ARM::VLD3q8_UPD:
    2406             :     case ARM::VLD3q16_UPD:
    2407             :     case ARM::VLD3q32_UPD:
    2408             :     case ARM::VLD4q8:
    2409             :     case ARM::VLD4q16:
    2410             :     case ARM::VLD4q32:
    2411             :     case ARM::VLD4q8_UPD:
    2412             :     case ARM::VLD4q16_UPD:
    2413             :     case ARM::VLD4q32_UPD:
    2414          98 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
    2415             :         return MCDisassembler::Fail;
    2416             :       break;
    2417             :     default:
    2418             :       break;
    2419             :   }
    2420             : 
    2421             :   // Fourth output register
    2422         322 :   switch (Inst.getOpcode()) {
    2423          19 :     case ARM::VLD4d8:
    2424             :     case ARM::VLD4d16:
    2425             :     case ARM::VLD4d32:
    2426             :     case ARM::VLD4d8_UPD:
    2427             :     case ARM::VLD4d16_UPD:
    2428             :     case ARM::VLD4d32_UPD:
    2429          38 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
    2430             :         return MCDisassembler::Fail;
    2431             :       break;
    2432          25 :     case ARM::VLD4q8:
    2433             :     case ARM::VLD4q16:
    2434             :     case ARM::VLD4q32:
    2435             :     case ARM::VLD4q8_UPD:
    2436             :     case ARM::VLD4q16_UPD:
    2437             :     case ARM::VLD4q32_UPD:
    2438          50 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
    2439             :         return MCDisassembler::Fail;
    2440             :       break;
    2441             :     default:
    2442             :       break;
    2443             :   }
    2444             : 
    2445             :   // Writeback operand
    2446         322 :   switch (Inst.getOpcode()) {
    2447         188 :     case ARM::VLD1d8wb_fixed:
    2448             :     case ARM::VLD1d16wb_fixed:
    2449             :     case ARM::VLD1d32wb_fixed:
    2450             :     case ARM::VLD1d64wb_fixed:
    2451             :     case ARM::VLD1d8wb_register:
    2452             :     case ARM::VLD1d16wb_register:
    2453             :     case ARM::VLD1d32wb_register:
    2454             :     case ARM::VLD1d64wb_register:
    2455             :     case ARM::VLD1q8wb_fixed:
    2456             :     case ARM::VLD1q16wb_fixed:
    2457             :     case ARM::VLD1q32wb_fixed:
    2458             :     case ARM::VLD1q64wb_fixed:
    2459             :     case ARM::VLD1q8wb_register:
    2460             :     case ARM::VLD1q16wb_register:
    2461             :     case ARM::VLD1q32wb_register:
    2462             :     case ARM::VLD1q64wb_register:
    2463             :     case ARM::VLD1d8Twb_fixed:
    2464             :     case ARM::VLD1d8Twb_register:
    2465             :     case ARM::VLD1d16Twb_fixed:
    2466             :     case ARM::VLD1d16Twb_register:
    2467             :     case ARM::VLD1d32Twb_fixed:
    2468             :     case ARM::VLD1d32Twb_register:
    2469             :     case ARM::VLD1d64Twb_fixed:
    2470             :     case ARM::VLD1d64Twb_register:
    2471             :     case ARM::VLD1d8Qwb_fixed:
    2472             :     case ARM::VLD1d8Qwb_register:
    2473             :     case ARM::VLD1d16Qwb_fixed:
    2474             :     case ARM::VLD1d16Qwb_register:
    2475             :     case ARM::VLD1d32Qwb_fixed:
    2476             :     case ARM::VLD1d32Qwb_register:
    2477             :     case ARM::VLD1d64Qwb_fixed:
    2478             :     case ARM::VLD1d64Qwb_register:
    2479             :     case ARM::VLD2d8wb_fixed:
    2480             :     case ARM::VLD2d16wb_fixed:
    2481             :     case ARM::VLD2d32wb_fixed:
    2482             :     case ARM::VLD2q8wb_fixed:
    2483             :     case ARM::VLD2q16wb_fixed:
    2484             :     case ARM::VLD2q32wb_fixed:
    2485             :     case ARM::VLD2d8wb_register:
    2486             :     case ARM::VLD2d16wb_register:
    2487             :     case ARM::VLD2d32wb_register:
    2488             :     case ARM::VLD2q8wb_register:
    2489             :     case ARM::VLD2q16wb_register:
    2490             :     case ARM::VLD2q32wb_register:
    2491             :     case ARM::VLD2b8wb_fixed:
    2492             :     case ARM::VLD2b16wb_fixed:
    2493             :     case ARM::VLD2b32wb_fixed:
    2494             :     case ARM::VLD2b8wb_register:
    2495             :     case ARM::VLD2b16wb_register:
    2496             :     case ARM::VLD2b32wb_register:
    2497         376 :       Inst.addOperand(MCOperand::createImm(0));
    2498             :       break;
    2499          49 :     case ARM::VLD3d8_UPD:
    2500             :     case ARM::VLD3d16_UPD:
    2501             :     case ARM::VLD3d32_UPD:
    2502             :     case ARM::VLD3q8_UPD:
    2503             :     case ARM::VLD3q16_UPD:
    2504             :     case ARM::VLD3q32_UPD:
    2505             :     case ARM::VLD4d8_UPD:
    2506             :     case ARM::VLD4d16_UPD:
    2507             :     case ARM::VLD4d32_UPD:
    2508             :     case ARM::VLD4q8_UPD:
    2509             :     case ARM::VLD4q16_UPD:
    2510             :     case ARM::VLD4q32_UPD:
    2511          98 :       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
    2512             :         return MCDisassembler::Fail;
    2513             :       break;
    2514             :     default:
    2515             :       break;
    2516             :   }
    2517             : 
    2518             :   // AddrMode6 Base (register+alignment)
    2519         644 :   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
    2520             :     return MCDisassembler::Fail;
    2521             : 
    2522             :   // AddrMode6 Offset (register)
    2523         322 :   switch (Inst.getOpcode()) {
    2524         175 :   default:
    2525             :     // The below have been updated to have explicit am6offset split
    2526             :     // between fixed and register offset. For those instructions not
    2527             :     // yet updated, we need to add an additional reg0 operand for the
    2528             :     // fixed variant.
    2529             :     //
    2530             :     // The fixed offset encodes as Rm == 0xd, so we check for that.
    2531         175 :     if (Rm == 0xd) {
    2532          72 :       Inst.addOperand(MCOperand::createReg(0));
    2533             :       break;
    2534             :     }
    2535             :     // Fall through to handle the register offset variant.
    2536             :     LLVM_FALLTHROUGH;
    2537             :   case ARM::VLD1d8wb_fixed:
    2538             :   case ARM::VLD1d16wb_fixed:
    2539             :   case ARM::VLD1d32wb_fixed:
    2540             :   case ARM::VLD1d64wb_fixed:
    2541             :   case ARM::VLD1d8Twb_fixed:
    2542             :   case ARM::VLD1d16Twb_fixed:
    2543             :   case ARM::VLD1d32Twb_fixed:
    2544             :   case ARM::VLD1d64Twb_fixed:
    2545             :   case ARM::VLD1d8Qwb_fixed:
    2546             :   case ARM::VLD1d16Qwb_fixed:
    2547             :   case ARM::VLD1d32Qwb_fixed:
    2548             :   case ARM::VLD1d64Qwb_fixed:
    2549             :   case ARM::VLD1d8wb_register:
    2550             :   case ARM::VLD1d16wb_register:
    2551             :   case ARM::VLD1d32wb_register:
    2552             :   case ARM::VLD1d64wb_register:
    2553             :   case ARM::VLD1q8wb_fixed:
    2554             :   case ARM::VLD1q16wb_fixed:
    2555             :   case ARM::VLD1q32wb_fixed:
    2556             :   case ARM::VLD1q64wb_fixed:
    2557             :   case ARM::VLD1q8wb_register:
    2558             :   case ARM::VLD1q16wb_register:
    2559             :   case ARM::VLD1q32wb_register:
    2560             :   case ARM::VLD1q64wb_register:
    2561             :     // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
    2562             :     // variant encodes Rm == 0xf. Anything else is a register offset post-
    2563             :     // increment and we need to add the register operand to the instruction.
    2564         333 :     if (Rm != 0xD && Rm != 0xF &&
    2565         142 :         !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2566             :       return MCDisassembler::Fail;
    2567             :     break;
    2568             :   case ARM::VLD2d8wb_fixed:
    2569             :   case ARM::VLD2d16wb_fixed:
    2570             :   case ARM::VLD2d32wb_fixed:
    2571             :   case ARM::VLD2b8wb_fixed:
    2572             :   case ARM::VLD2b16wb_fixed:
    2573             :   case ARM::VLD2b32wb_fixed:
    2574             :   case ARM::VLD2q8wb_fixed:
    2575             :   case ARM::VLD2q16wb_fixed:
    2576             :   case ARM::VLD2q32wb_fixed:
    2577             :     break;
    2578             :   }
    2579             : 
    2580             :   return S;
    2581             : }
    2582             : 
    2583         332 : static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
    2584             :                                    uint64_t Address, const void *Decoder) {
    2585         332 :   unsigned type = fieldFromInstruction(Insn, 8, 4);
    2586         332 :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2587         332 :   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
    2588         328 :   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
    2589         328 :   if (type == 10 && align == 3) return MCDisassembler::Fail;
    2590             : 
    2591         325 :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2592         325 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2593             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2594             : }
    2595             : 
    2596         139 : static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
    2597             :                                    uint64_t Address, const void *Decoder) {
    2598         139 :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2599         139 :   if (size == 3) return MCDisassembler::Fail;
    2600             : 
    2601         139 :   unsigned type = fieldFromInstruction(Insn, 8, 4);
    2602         139 :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2603         139 :   if (type == 8 && align == 3) return MCDisassembler::Fail;
    2604         136 :   if (type == 9 && align == 3) return MCDisassembler::Fail;
    2605             : 
    2606         133 :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2607         133 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2608             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2609             : }
    2610             : 
    2611          84 : static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
    2612             :                                    uint64_t Address, const void *Decoder) {
    2613          84 :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2614          84 :   if (size == 3) return MCDisassembler::Fail;
    2615             : 
    2616          84 :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2617          84 :   if (align & 2) return MCDisassembler::Fail;
    2618             : 
    2619          84 :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2620          84 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2621             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2622             : }
    2623             : 
    2624          84 : static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
    2625             :                                    uint64_t Address, const void *Decoder) {
    2626          84 :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2627          84 :   if (size == 3) return MCDisassembler::Fail;
    2628             : 
    2629          84 :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2630          84 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2631             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2632             : }
    2633             : 
    2634         304 : static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
    2635             :                                  uint64_t Address, const void *Decoder) {
    2636         304 :   DecodeStatus S = MCDisassembler::Success;
    2637             : 
    2638         304 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2639         304 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2640         304 :   unsigned wb = fieldFromInstruction(Insn, 16, 4);
    2641         304 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2642         304 :   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
    2643         304 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2644             : 
    2645             :   // Writeback Operand
    2646         304 :   switch (Inst.getOpcode()) {
    2647         174 :     case ARM::VST1d8wb_fixed:
    2648             :     case ARM::VST1d16wb_fixed:
    2649             :     case ARM::VST1d32wb_fixed:
    2650             :     case ARM::VST1d64wb_fixed:
    2651             :     case ARM::VST1d8wb_register:
    2652             :     case ARM::VST1d16wb_register:
    2653             :     case ARM::VST1d32wb_register:
    2654             :     case ARM::VST1d64wb_register:
    2655             :     case ARM::VST1q8wb_fixed:
    2656             :     case ARM::VST1q16wb_fixed:
    2657             :     case ARM::VST1q32wb_fixed:
    2658             :     case ARM::VST1q64wb_fixed:
    2659             :     case ARM::VST1q8wb_register:
    2660             :     case ARM::VST1q16wb_register:
    2661             :     case ARM::VST1q32wb_register:
    2662             :     case ARM::VST1q64wb_register:
    2663             :     case ARM::VST1d8Twb_fixed:
    2664             :     case ARM::VST1d16Twb_fixed:
    2665             :     case ARM::VST1d32Twb_fixed:
    2666             :     case ARM::VST1d64Twb_fixed:
    2667             :     case ARM::VST1d8Twb_register:
    2668             :     case ARM::VST1d16Twb_register:
    2669             :     case ARM::VST1d32Twb_register:
    2670             :     case ARM::VST1d64Twb_register:
    2671             :     case ARM::VST1d8Qwb_fixed:
    2672             :     case ARM::VST1d16Qwb_fixed:
    2673             :     case ARM::VST1d32Qwb_fixed:
    2674             :     case ARM::VST1d64Qwb_fixed:
    2675             :     case ARM::VST1d8Qwb_register:
    2676             :     case ARM::VST1d16Qwb_register:
    2677             :     case ARM::VST1d32Qwb_register:
    2678             :     case ARM::VST1d64Qwb_register:
    2679             :     case ARM::VST2d8wb_fixed:
    2680             :     case ARM::VST2d16wb_fixed:
    2681             :     case ARM::VST2d32wb_fixed:
    2682             :     case ARM::VST2d8wb_register:
    2683             :     case ARM::VST2d16wb_register:
    2684             :     case ARM::VST2d32wb_register:
    2685             :     case ARM::VST2q8wb_fixed:
    2686             :     case ARM::VST2q16wb_fixed:
    2687             :     case ARM::VST2q32wb_fixed:
    2688             :     case ARM::VST2q8wb_register:
    2689             :     case ARM::VST2q16wb_register:
    2690             :     case ARM::VST2q32wb_register:
    2691             :     case ARM::VST2b8wb_fixed:
    2692             :     case ARM::VST2b16wb_fixed:
    2693             :     case ARM::VST2b32wb_fixed:
    2694             :     case ARM::VST2b8wb_register:
    2695             :     case ARM::VST2b16wb_register:
    2696             :     case ARM::VST2b32wb_register:
    2697         174 :       if (Rm == 0xF)
    2698             :         return MCDisassembler::Fail;
    2699         348 :       Inst.addOperand(MCOperand::createImm(0));
    2700             :       break;
    2701          48 :     case ARM::VST3d8_UPD:
    2702             :     case ARM::VST3d16_UPD:
    2703             :     case ARM::VST3d32_UPD:
    2704             :     case ARM::VST3q8_UPD:
    2705             :     case ARM::VST3q16_UPD:
    2706             :     case ARM::VST3q32_UPD:
    2707             :     case ARM::VST4d8_UPD:
    2708             :     case ARM::VST4d16_UPD:
    2709             :     case ARM::VST4d32_UPD:
    2710             :     case ARM::VST4q8_UPD:
    2711             :     case ARM::VST4q16_UPD:
    2712             :     case ARM::VST4q32_UPD:
    2713          96 :       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
    2714             :         return MCDisassembler::Fail;
    2715             :       break;
    2716             :     default:
    2717             :       break;
    2718             :   }
    2719             : 
    2720             :   // AddrMode6 Base (register+alignment)
    2721         608 :   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
    2722             :     return MCDisassembler::Fail;
    2723             : 
    2724             :   // AddrMode6 Offset (register)
    2725         304 :   switch (Inst.getOpcode()) {
    2726         181 :     default:
    2727         181 :       if (Rm == 0xD)
    2728          72 :         Inst.addOperand(MCOperand::createReg(0));
    2729         145 :       else if (Rm != 0xF) {
    2730         126 :         if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2731             :           return MCDisassembler::Fail;
    2732             :       }
    2733             :       break;
    2734             :     case ARM::VST1d8wb_fixed:
    2735             :     case ARM::VST1d16wb_fixed:
    2736             :     case ARM::VST1d32wb_fixed:
    2737             :     case ARM::VST1d64wb_fixed:
    2738             :     case ARM::VST1q8wb_fixed:
    2739             :     case ARM::VST1q16wb_fixed:
    2740             :     case ARM::VST1q32wb_fixed:
    2741             :     case ARM::VST1q64wb_fixed:
    2742             :     case ARM::VST1d8Twb_fixed:
    2743             :     case ARM::VST1d16Twb_fixed:
    2744             :     case ARM::VST1d32Twb_fixed:
    2745             :     case ARM::VST1d64Twb_fixed:
    2746             :     case ARM::VST1d8Qwb_fixed:
    2747             :     case ARM::VST1d16Qwb_fixed:
    2748             :     case ARM::VST1d32Qwb_fixed:
    2749             :     case ARM::VST1d64Qwb_fixed:
    2750             :     case ARM::VST2d8wb_fixed:
    2751             :     case ARM::VST2d16wb_fixed:
    2752             :     case ARM::VST2d32wb_fixed:
    2753             :     case ARM::VST2q8wb_fixed:
    2754             :     case ARM::VST2q16wb_fixed:
    2755             :     case ARM::VST2q32wb_fixed:
    2756             :     case ARM::VST2b8wb_fixed:
    2757             :     case ARM::VST2b16wb_fixed:
    2758             :     case ARM::VST2b32wb_fixed:
    2759             :       break;
    2760             :   }
    2761             : 
    2762             : 
    2763             :   // First input register
    2764         304 :   switch (Inst.getOpcode()) {
    2765          93 :   case ARM::VST1q16:
    2766             :   case ARM::VST1q32:
    2767             :   case ARM::VST1q64:
    2768             :   case ARM::VST1q8:
    2769             :   case ARM::VST1q16wb_fixed:
    2770             :   case ARM::VST1q16wb_register:
    2771             :   case ARM::VST1q32wb_fixed:
    2772             :   case ARM::VST1q32wb_register:
    2773             :   case ARM::VST1q64wb_fixed:
    2774             :   case ARM::VST1q64wb_register:
    2775             :   case ARM::VST1q8wb_fixed:
    2776             :   case ARM::VST1q8wb_register:
    2777             :   case ARM::VST2d16:
    2778             :   case ARM::VST2d32:
    2779             :   case ARM::VST2d8:
    2780             :   case ARM::VST2d16wb_fixed:
    2781             :   case ARM::VST2d16wb_register:
    2782             :   case ARM::VST2d32wb_fixed:
    2783             :   case ARM::VST2d32wb_register:
    2784             :   case ARM::VST2d8wb_fixed:
    2785             :   case ARM::VST2d8wb_register:
    2786         186 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2787             :       return MCDisassembler::Fail;
    2788             :     break;
    2789          19 :   case ARM::VST2b16:
    2790             :   case ARM::VST2b32:
    2791             :   case ARM::VST2b8:
    2792             :   case ARM::VST2b16wb_fixed:
    2793             :   case ARM::VST2b16wb_register:
    2794             :   case ARM::VST2b32wb_fixed:
    2795             :   case ARM::VST2b32wb_register:
    2796             :   case ARM::VST2b8wb_fixed:
    2797             :   case ARM::VST2b8wb_register:
    2798          38 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2799             :       return MCDisassembler::Fail;
    2800             :     break;
    2801         192 :   default:
    2802         384 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2803             :       return MCDisassembler::Fail;
    2804             :   }
    2805             : 
    2806             :   // Second input register
    2807         304 :   switch (Inst.getOpcode()) {
    2808          34 :     case ARM::VST3d8:
    2809             :     case ARM::VST3d16:
    2810             :     case ARM::VST3d32:
    2811             :     case ARM::VST3d8_UPD:
    2812             :     case ARM::VST3d16_UPD:
    2813             :     case ARM::VST3d32_UPD:
    2814             :     case ARM::VST4d8:
    2815             :     case ARM::VST4d16:
    2816             :     case ARM::VST4d32:
    2817             :     case ARM::VST4d8_UPD:
    2818             :     case ARM::VST4d16_UPD:
    2819             :     case ARM::VST4d32_UPD:
    2820          68 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
    2821             :         return MCDisassembler::Fail;
    2822             :       break;
    2823          48 :     case ARM::VST3q8:
    2824             :     case ARM::VST3q16:
    2825             :     case ARM::VST3q32:
    2826             :     case ARM::VST3q8_UPD:
    2827             :     case ARM::VST3q16_UPD:
    2828             :     case ARM::VST3q32_UPD:
    2829             :     case ARM::VST4q8:
    2830             :     case ARM::VST4q16:
    2831             :     case ARM::VST4q32:
    2832             :     case ARM::VST4q8_UPD:
    2833             :     case ARM::VST4q16_UPD:
    2834             :     case ARM::VST4q32_UPD:
    2835          96 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2836             :         return MCDisassembler::Fail;
    2837             :       break;
    2838             :     default:
    2839             :       break;
    2840             :   }
    2841             : 
    2842             :   // Third input register
    2843         304 :   switch (Inst.getOpcode()) {
    2844          34 :     case ARM::VST3d8:
    2845             :     case ARM::VST3d16:
    2846             :     case ARM::VST3d32:
    2847             :     case ARM::VST3d8_UPD:
    2848             :     case ARM::VST3d16_UPD:
    2849             :     case ARM::VST3d32_UPD:
    2850             :     case ARM::VST4d8:
    2851             :     case ARM::VST4d16:
    2852             :     case ARM::VST4d32:
    2853             :     case ARM::VST4d8_UPD:
    2854             :     case ARM::VST4d16_UPD:
    2855             :     case ARM::VST4d32_UPD:
    2856          68 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2857             :         return MCDisassembler::Fail;
    2858             :       break;
    2859          48 :     case ARM::VST3q8:
    2860             :     case ARM::VST3q16:
    2861             :     case ARM::VST3q32:
    2862             :     case ARM::VST3q8_UPD:
    2863             :     case ARM::VST3q16_UPD:
    2864             :     case ARM::VST3q32_UPD:
    2865             :     case ARM::VST4q8:
    2866             :     case ARM::VST4q16:
    2867             :     case ARM::VST4q32:
    2868             :     case ARM::VST4q8_UPD:
    2869             :     case ARM::VST4q16_UPD:
    2870             :     case ARM::VST4q32_UPD:
    2871          96 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
    2872             :         return MCDisassembler::Fail;
    2873             :       break;
    2874             :     default:
    2875             :       break;
    2876             :   }
    2877             : 
    2878             :   // Fourth input register
    2879         304 :   switch (Inst.getOpcode()) {
    2880          16 :     case ARM::VST4d8:
    2881             :     case ARM::VST4d16:
    2882             :     case ARM::VST4d32:
    2883             :     case ARM::VST4d8_UPD:
    2884             :     case ARM::VST4d16_UPD:
    2885             :     case ARM::VST4d32_UPD:
    2886          32 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
    2887             :         return MCDisassembler::Fail;
    2888             :       break;
    2889          24 :     case ARM::VST4q8:
    2890             :     case ARM::VST4q16:
    2891             :     case ARM::VST4q32:
    2892             :     case ARM::VST4q8_UPD:
    2893             :     case ARM::VST4q16_UPD:
    2894             :     case ARM::VST4q32_UPD:
    2895          48 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
    2896             :         return MCDisassembler::Fail;
    2897             :       break;
    2898             :     default:
    2899             :       break;
    2900             :   }
    2901             : 
    2902             :   return S;
    2903             : }
    2904             : 
    2905           3 : static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
    2906             :                                     uint64_t Address, const void *Decoder) {
    2907           3 :   DecodeStatus S = MCDisassembler::Success;
    2908             : 
    2909           3 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2910           3 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2911           3 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2912           3 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2913           3 :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    2914           3 :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2915             : 
    2916           3 :   if (size == 0 && align == 1)
    2917             :     return MCDisassembler::Fail;
    2918           2 :   align *= (1 << size);
    2919             : 
    2920           2 :   switch (Inst.getOpcode()) {
    2921           1 :   case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
    2922             :   case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
    2923             :   case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
    2924             :   case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
    2925           2 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2926             :       return MCDisassembler::Fail;
    2927             :     break;
    2928           1 :   default:
    2929           2 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2930             :       return MCDisassembler::Fail;
    2931             :     break;
    2932             :   }
    2933           2 :   if (Rm != 0xF) {
    2934           4 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2935             :       return MCDisassembler::Fail;
    2936             :   }
    2937             : 
    2938           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2939             :     return MCDisassembler::Fail;
    2940           6 :   Inst.addOperand(MCOperand::createImm(align));
    2941             : 
    2942             :   // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
    2943             :   // variant encodes Rm == 0xf. Anything else is a register offset post-
    2944             :   // increment and we need to add the register operand to the instruction.
    2945           3 :   if (Rm != 0xD && Rm != 0xF &&
    2946           2 :       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2947             :     return MCDisassembler::Fail;
    2948             : 
    2949             :   return S;
    2950             : }
    2951             : 
    2952          42 : static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
    2953             :                                     uint64_t Address, const void *Decoder) {
    2954          42 :   DecodeStatus S = MCDisassembler::Success;
    2955             : 
    2956          42 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2957          42 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2958          42 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2959          42 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2960          42 :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    2961          42 :   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
    2962          42 :   align *= 2*size;
    2963             : 
    2964          42 :   switch (Inst.getOpcode()) {
    2965          18 :   case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
    2966             :   case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
    2967             :   case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
    2968             :   case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
    2969          36 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2970             :       return MCDisassembler::Fail;
    2971             :     break;
    2972          24 :   case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
    2973             :   case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
    2974             :   case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
    2975             :   case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
    2976          48 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2977             :       return MCDisassembler::Fail;
    2978             :     break;
    2979           0 :   default:
    2980           0 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2981             :       return MCDisassembler::Fail;
    2982             :     break;
    2983             :   }
    2984             : 
    2985          42 :   if (Rm != 0xF)
    2986          56 :     Inst.addOperand(MCOperand::createImm(0));
    2987             : 
    2988          84 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2989             :     return MCDisassembler::Fail;
    2990         126 :   Inst.addOperand(MCOperand::createImm(align));
    2991             : 
    2992          42 :   if (Rm != 0xD && Rm != 0xF) {
    2993          28 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2994             :       return MCDisassembler::Fail;
    2995             :   }
    2996             : 
    2997             :   return S;
    2998             : }
    2999             : 
    3000          18 : static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
    3001             :                                     uint64_t Address, const void *Decoder) {
    3002          18 :   DecodeStatus S = MCDisassembler::Success;
    3003             : 
    3004          18 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3005          18 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3006          18 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3007          18 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3008          18 :   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
    3009             : 
    3010          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3011             :     return MCDisassembler::Fail;
    3012          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
    3013             :     return MCDisassembler::Fail;
    3014          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
    3015             :     return MCDisassembler::Fail;
    3016          18 :   if (Rm != 0xF) {
    3017          24 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3018             :       return MCDisassembler::Fail;
    3019             :   }
    3020             : 
    3021          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3022             :     return MCDisassembler::Fail;
    3023          36 :   Inst.addOperand(MCOperand::createImm(0));
    3024             : 
    3025          18 :   if (Rm == 0xD)
    3026          12 :     Inst.addOperand(MCOperand::createReg(0));
    3027          12 :   else if (Rm != 0xF) {
    3028          12 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3029             :       return MCDisassembler::Fail;
    3030             :   }
    3031             : 
    3032             :   return S;
    3033             : }
    3034             : 
    3035          27 : static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
    3036             :                                     uint64_t Address, const void *Decoder) {
    3037          27 :   DecodeStatus S = MCDisassembler::Success;
    3038             : 
    3039          27 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3040          27 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3041          27 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3042          27 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3043          27 :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    3044          27 :   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
    3045          27 :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    3046             : 
    3047          27 :   if (size == 0x3) {
    3048           6 :     if (align == 0)
    3049             :       return MCDisassembler::Fail;
    3050             :     align = 16;
    3051             :   } else {
    3052          21 :     if (size == 2) {
    3053           4 :       align *= 8;
    3054             :     } else {
    3055          17 :       size = 1 << size;
    3056          17 :       align *= 4*size;
    3057             :     }
    3058             :   }
    3059             : 
    3060          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3061             :     return MCDisassembler::Fail;
    3062          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
    3063             :     return MCDisassembler::Fail;
    3064          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
    3065             :     return MCDisassembler::Fail;
    3066          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
    3067             :     return MCDisassembler::Fail;
    3068          25 :   if (Rm != 0xF) {
    3069          26 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3070             :       return MCDisassembler::Fail;
    3071             :   }
    3072             : 
    3073          50 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3074             :     return MCDisassembler::Fail;
    3075          75 :   Inst.addOperand(MCOperand::createImm(align));
    3076             : 
    3077          25 :   if (Rm == 0xD)
    3078          14 :     Inst.addOperand(MCOperand::createReg(0));
    3079          18 :   else if (Rm != 0xF) {
    3080          12 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3081             :       return MCDisassembler::Fail;
    3082             :   }
    3083             : 
    3084             :   return S;
    3085             : }
    3086             : 
    3087             : static DecodeStatus
    3088          94 : DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
    3089             :                             uint64_t Address, const void *Decoder) {
    3090          94 :   DecodeStatus S = MCDisassembler::Success;
    3091             : 
    3092          94 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3093          94 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3094          94 :   unsigned imm = fieldFromInstruction(Insn, 0, 4);
    3095          94 :   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
    3096          94 :   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
    3097          94 :   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
    3098          94 :   imm |= fieldFromInstruction(Insn, 5, 1) << 12;
    3099          94 :   unsigned Q = fieldFromInstruction(Insn, 6, 1);
    3100             : 
    3101          94 :   if (Q) {
    3102          88 :     if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3103             :     return MCDisassembler::Fail;
    3104             :   } else {
    3105         100 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3106             :     return MCDisassembler::Fail;
    3107             :   }
    3108             : 
    3109         282 :   Inst.addOperand(MCOperand::createImm(imm));
    3110             : 
    3111          94 :   switch (Inst.getOpcode()) {
    3112           4 :     case ARM::VORRiv4i16:
    3113             :     case ARM::VORRiv2i32:
    3114             :     case ARM::VBICiv4i16:
    3115             :     case ARM::VBICiv2i32:
    3116           8 :       if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3117             :         return MCDisassembler::Fail;
    3118             :       break;
    3119           8 :     case ARM::VORRiv8i16:
    3120             :     case ARM::VORRiv4i32:
    3121             :     case ARM::VBICiv8i16:
    3122             :     case ARM::VBICiv4i32:
    3123          16 :       if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3124             :         return MCDisassembler::Fail;
    3125             :       break;
    3126             :     default:
    3127             :       break;
    3128             :   }
    3129             : 
    3130             :   return S;
    3131             : }
    3132             : 
    3133           7 : static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
    3134             :                                         uint64_t Address, const void *Decoder) {
    3135           7 :   DecodeStatus S = MCDisassembler::Success;
    3136             : 
    3137           7 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3138           7 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3139           7 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3140           7 :   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
    3141           7 :   unsigned size = fieldFromInstruction(Insn, 18, 2);
    3142             : 
    3143          14 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3144             :     return MCDisassembler::Fail;
    3145          14 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
    3146             :     return MCDisassembler::Fail;
    3147          21 :   Inst.addOperand(MCOperand::createImm(8 << size));
    3148             : 
    3149             :   return S;
    3150             : }
    3151             : 
    3152             : static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
    3153             :                                uint64_t Address, const void *Decoder) {
    3154         180 :   Inst.addOperand(MCOperand::createImm(8 - Val));
    3155             :   return MCDisassembler::Success;
    3156             : }
    3157             : 
    3158             : static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
    3159             :                                uint64_t Address, const void *Decoder) {
    3160         180 :   Inst.addOperand(MCOperand::createImm(16 - Val));
    3161             :   return MCDisassembler::Success;
    3162             : }
    3163             : 
    3164             : static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
    3165             :                                uint64_t Address, const void *Decoder) {
    3166         186 :   Inst.addOperand(MCOperand::createImm(32 - Val));
    3167             :   return MCDisassembler::Success;
    3168             : }
    3169             : 
    3170             : static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
    3171             :                                uint64_t Address, const void *Decoder) {
    3172         126 :   Inst.addOperand(MCOperand::createImm(64 - Val));
    3173             :   return MCDisassembler::Success;
    3174             : }
    3175             : 
    3176          17 : static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
    3177             :                                uint64_t Address, const void *Decoder) {
    3178          17 :   DecodeStatus S = MCDisassembler::Success;
    3179             : 
    3180          17 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3181          17 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3182          17 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3183          17 :   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
    3184          17 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3185          17 :   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
    3186          17 :   unsigned op = fieldFromInstruction(Insn, 6, 1);
    3187             : 
    3188          34 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3189             :     return MCDisassembler::Fail;
    3190          17 :   if (op) {
    3191          18 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3192             :     return MCDisassembler::Fail; // Writeback
    3193             :   }
    3194             : 
    3195          17 :   switch (Inst.getOpcode()) {
    3196           4 :   case ARM::VTBL2:
    3197             :   case ARM::VTBX2:
    3198           8 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
    3199             :       return MCDisassembler::Fail;
    3200             :     break;
    3201          13 :   default:
    3202          26 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
    3203             :       return MCDisassembler::Fail;
    3204             :   }
    3205             : 
    3206          34 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
    3207             :     return MCDisassembler::Fail;
    3208             : 
    3209             :   return S;
    3210             : }
    3211             : 
    3212         317 : static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
    3213             :                                      uint64_t Address, const void *Decoder) {
    3214         317 :   DecodeStatus S = MCDisassembler::Success;
    3215             : 
    3216         317 :   unsigned dst = fieldFromInstruction(Insn, 8, 3);
    3217         317 :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3218             : 
    3219         951 :   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
    3220             :     return MCDisassembler::Fail;
    3221             : 
    3222         317 :   switch(Inst.getOpcode()) {
    3223             :     default:
    3224             :       return MCDisassembler::Fail;
    3225             :     case ARM::tADR:
    3226             :       break; // tADR does not explicitly represent the PC as an operand.
    3227         312 :     case ARM::tADDrSPi:
    3228         624 :       Inst.addOperand(MCOperand::createReg(ARM::SP));
    3229         312 :       break;
    3230             :   }
    3231             : 
    3232         951 :   Inst.addOperand(MCOperand::createImm(imm));
    3233         317 :   return S;
    3234             : }
    3235             : 
    3236          68 : static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
    3237             :                                  uint64_t Address, const void *Decoder) {
    3238         204 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
    3239             :                                 true, 2, Inst, Decoder))
    3240         198 :     Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
    3241          68 :   return MCDisassembler::Success;
    3242             : }
    3243             : 
    3244          17 : static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
    3245             :                                  uint64_t Address, const void *Decoder) {
    3246          34 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
    3247             :                                 true, 4, Inst, Decoder))
    3248          51 :     Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
    3249          17 :   return MCDisassembler::Success;
    3250             : }
    3251             : 
    3252          10 : static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
    3253             :                                  uint64_t Address, const void *Decoder) {
    3254          20 :   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
    3255             :                                 true, 2, Inst, Decoder))
    3256          30 :     Inst.addOperand(MCOperand::createImm(Val << 1));
    3257          10 :   return MCDisassembler::Success;
    3258             : }
    3259             : 
    3260          12 : static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
    3261             :                                  uint64_t Address, const void *Decoder) {
    3262          12 :   DecodeStatus S = MCDisassembler::Success;
    3263             : 
    3264          12 :   unsigned Rn = fieldFromInstruction(Val, 0, 3);
    3265          12 :   unsigned Rm = fieldFromInstruction(Val, 3, 3);
    3266             : 
    3267          36 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3268             :     return MCDisassembler::Fail;
    3269          36 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3270             :     return MCDisassembler::Fail;
    3271             : 
    3272             :   return S;
    3273             : }
    3274             : 
    3275        1875 : static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
    3276             :                                   uint64_t Address, const void *Decoder) {
    3277        1875 :   DecodeStatus S = MCDisassembler::Success;
    3278             : 
    3279        1875 :   unsigned Rn = fieldFromInstruction(Val, 0, 3);
    3280        1875 :   unsigned imm = fieldFromInstruction(Val, 3, 5);
    3281             : 
    3282        5625 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3283             :     return MCDisassembler::Fail;
    3284        5625 :   Inst.addOperand(MCOperand::createImm(imm));
    3285             : 
    3286             :   return S;
    3287             : }
    3288             : 
    3289          62 : static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
    3290             :                                   uint64_t Address, const void *Decoder) {
    3291          62 :   unsigned imm = Val << 2;
    3292             : 
    3293         186 :   Inst.addOperand(MCOperand::createImm(imm));
    3294         124 :   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
    3295             : 
    3296          62 :   return MCDisassembler::Success;
    3297             : }
    3298             : 
    3299         278 : static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
    3300             :                                   uint64_t Address, const void *Decoder) {
    3301         556 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3302         834 :   Inst.addOperand(MCOperand::createImm(Val));
    3303             : 
    3304         278 :   return MCDisassembler::Success;
    3305             : }
    3306             : 
    3307          79 : static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
    3308             :                                   uint64_t Address, const void *Decoder) {
    3309          79 :   DecodeStatus S = MCDisassembler::Success;
    3310             : 
    3311          79 :   unsigned Rn = fieldFromInstruction(Val, 6, 4);
    3312          79 :   unsigned Rm = fieldFromInstruction(Val, 2, 4);
    3313          79 :   unsigned imm = fieldFromInstruction(Val, 0, 2);
    3314             : 
    3315             :   // Thumb stores cannot use PC as dest register.
    3316          79 :   switch (Inst.getOpcode()) {
    3317          14 :   case ARM::t2STRHs:
    3318             :   case ARM::t2STRBs:
    3319             :   case ARM::t2STRs:
    3320          14 :     if (Rn == 15)
    3321             :       return MCDisassembler::Fail;
    3322             :   default:
    3323             :     break;
    3324             :   }
    3325             : 
    3326         142 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3327             :     return MCDisassembler::Fail;
    3328         142 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3329             :     return MCDisassembler::Fail;
    3330         213 :   Inst.addOperand(MCOperand::createImm(imm));
    3331             : 
    3332             :   return S;
    3333             : }
    3334             : 
    3335         105 : static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
    3336             :                               uint64_t Address, const void *Decoder) {
    3337         105 :   DecodeStatus S = MCDisassembler::Success;
    3338             : 
    3339         105 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3340         105 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3341             : 
    3342             :   const FeatureBitset &featureBits =
    3343         105 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3344             : 
    3345         210 :   bool hasMP = featureBits[ARM::FeatureMP];
    3346         210 :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3347             : 
    3348         105 :   if (Rn == 15) {
    3349          26 :     switch (Inst.getOpcode()) {
    3350             :     case ARM::t2LDRBs:
    3351           2 :       Inst.setOpcode(ARM::t2LDRBpci);
    3352             :       break;
    3353             :     case ARM::t2LDRHs:
    3354           1 :       Inst.setOpcode(ARM::t2LDRHpci);
    3355             :       break;
    3356             :     case ARM::t2LDRSHs:
    3357           1 :       Inst.setOpcode(ARM::t2LDRSHpci);
    3358             :       break;
    3359             :     case ARM::t2LDRSBs:
    3360           3 :       Inst.setOpcode(ARM::t2LDRSBpci);
    3361             :       break;
    3362             :     case ARM::t2LDRs:
    3363           2 :       Inst.setOpcode(ARM::t2LDRpci);
    3364             :       break;
    3365             :     case ARM::t2PLDs:
    3366          10 :       Inst.setOpcode(ARM::t2PLDpci);
    3367             :       break;
    3368             :     case ARM::t2PLIs:
    3369           7 :       Inst.setOpcode(ARM::t2PLIpci);
    3370             :       break;
    3371             :     default:
    3372             :       return MCDisassembler::Fail;
    3373             :     }
    3374             : 
    3375          26 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3376             :   }
    3377             : 
    3378          79 :   if (Rt == 15) {
    3379          48 :     switch (Inst.getOpcode()) {
    3380             :     case ARM::t2LDRSHs:
    3381             :       return MCDisassembler::Fail;
    3382             :     case ARM::t2LDRHs:
    3383          12 :       Inst.setOpcode(ARM::t2PLDWs);
    3384             :       break;
    3385             :     case ARM::t2LDRSBs:
    3386           0 :       Inst.setOpcode(ARM::t2PLIs);
    3387             :     default:
    3388             :       break;
    3389             :     }
    3390             :   }
    3391             : 
    3392          77 :   switch (Inst.getOpcode()) {
    3393             :     case ARM::t2PLDs:
    3394             :       break;
    3395           6 :     case ARM::t2PLIs:
    3396           6 :       if (!hasV7Ops)
    3397             :         return MCDisassembler::Fail;
    3398             :       break;
    3399          17 :     case ARM::t2PLDWs:
    3400          17 :       if (!hasV7Ops || !hasMP)
    3401             :         return MCDisassembler::Fail;
    3402             :       break;
    3403          31 :     default:
    3404          62 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3405             :         return MCDisassembler::Fail;
    3406             :   }
    3407             : 
    3408          65 :   unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
    3409          65 :   addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
    3410          65 :   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
    3411         130 :   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
    3412             :     return MCDisassembler::Fail;
    3413             : 
    3414             :   return S;
    3415             : }
    3416             : 
    3417          37 : static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
    3418             :                                 uint64_t Address, const void* Decoder) {
    3419          37 :   DecodeStatus S = MCDisassembler::Success;
    3420             : 
    3421          37 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3422          37 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3423          37 :   unsigned U = fieldFromInstruction(Insn, 9, 1);
    3424          37 :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3425          37 :   imm |= (U << 8);
    3426          37 :   imm |= (Rn << 9);
    3427          37 :   unsigned add = fieldFromInstruction(Insn, 9, 1);
    3428             : 
    3429             :   const FeatureBitset &featureBits =
    3430          37 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3431             : 
    3432          74 :   bool hasMP = featureBits[ARM::FeatureMP];
    3433          74 :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3434             : 
    3435          37 :   if (Rn == 15) {
    3436           0 :     switch (Inst.getOpcode()) {
    3437             :     case ARM::t2LDRi8:
    3438           0 :       Inst.setOpcode(ARM::t2LDRpci);
    3439             :       break;
    3440             :     case ARM::t2LDRBi8:
    3441           0 :       Inst.setOpcode(ARM::t2LDRBpci);
    3442             :       break;
    3443             :     case ARM::t2LDRSBi8:
    3444           0 :       Inst.setOpcode(ARM::t2LDRSBpci);
    3445             :       break;
    3446             :     case ARM::t2LDRHi8:
    3447           0 :       Inst.setOpcode(ARM::t2LDRHpci);
    3448             :       break;
    3449             :     case ARM::t2LDRSHi8:
    3450           0 :       Inst.setOpcode(ARM::t2LDRSHpci);
    3451             :       break;
    3452             :     case ARM::t2PLDi8:
    3453           0 :       Inst.setOpcode(ARM::t2PLDpci);
    3454             :       break;
    3455             :     case ARM::t2PLIi8:
    3456           0 :       Inst.setOpcode(ARM::t2PLIpci);
    3457             :       break;
    3458             :     default:
    3459             :       return MCDisassembler::Fail;
    3460             :     }
    3461           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3462             :   }
    3463             : 
    3464          37 :   if (Rt == 15) {
    3465          30 :     switch (Inst.getOpcode()) {
    3466             :     case ARM::t2LDRSHi8:
    3467             :       return MCDisassembler::Fail;
    3468           6 :     case ARM::t2LDRHi8:
    3469           6 :       if (!add)
    3470           6 :         Inst.setOpcode(ARM::t2PLDWi8);
    3471             :       break;
    3472             :     case ARM::t2LDRSBi8:
    3473           2 :       Inst.setOpcode(ARM::t2PLIi8);
    3474             :       break;
    3475             :     default:
    3476             :       break;
    3477             :     }
    3478             :   }
    3479             : 
    3480          33 :   switch (Inst.getOpcode()) {
    3481             :   case ARM::t2PLDi8:
    3482             :     break;
    3483           9 :   case ARM::t2PLIi8:
    3484           9 :     if (!hasV7Ops)
    3485             :       return MCDisassembler::Fail;
    3486             :     break;
    3487           8 :   case ARM::t2PLDWi8:
    3488           8 :       if (!hasV7Ops || !hasMP)
    3489             :         return MCDisassembler::Fail;
    3490             :       break;
    3491           7 :   default:
    3492          14 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3493             :       return MCDisassembler::Fail;
    3494             :   }
    3495             : 
    3496          50 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
    3497             :     return MCDisassembler::Fail;
    3498             :   return S;
    3499             : }
    3500             : 
    3501          89 : static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
    3502             :                                 uint64_t Address, const void* Decoder) {
    3503          89 :   DecodeStatus S = MCDisassembler::Success;
    3504             : 
    3505          89 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3506          89 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3507          89 :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    3508          89 :   imm |= (Rn << 13);
    3509             : 
    3510             :   const FeatureBitset &featureBits =
    3511          89 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3512             : 
    3513         178 :   bool hasMP = featureBits[ARM::FeatureMP];
    3514         178 :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3515             : 
    3516          89 :   if (Rn == 15) {
    3517          30 :     switch (Inst.getOpcode()) {
    3518             :     case ARM::t2LDRi12:
    3519           4 :       Inst.setOpcode(ARM::t2LDRpci);
    3520             :       break;
    3521             :     case ARM::t2LDRHi12:
    3522           2 :       Inst.setOpcode(ARM::t2LDRHpci);
    3523             :       break;
    3524             :     case ARM::t2LDRSHi12:
    3525           1 :       Inst.setOpcode(ARM::t2LDRSHpci);
    3526             :       break;
    3527             :     case ARM::t2LDRBi12:
    3528           2 :       Inst.setOpcode(ARM::t2LDRBpci);
    3529             :       break;
    3530             :     case ARM::t2LDRSBi12:
    3531           4 :       Inst.setOpcode(ARM::t2LDRSBpci);
    3532             :       break;
    3533             :     case ARM::t2PLDi12:
    3534          10 :       Inst.setOpcode(ARM::t2PLDpci);
    3535             :       break;
    3536             :     case ARM::t2PLIi12:
    3537           7 :       Inst.setOpcode(ARM::t2PLIpci);
    3538             :       break;
    3539             :     default:
    3540             :       return MCDisassembler::Fail;
    3541             :     }
    3542          30 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3543             :   }
    3544             : 
    3545          59 :   if (Rt == 15) {
    3546          39 :     switch (Inst.getOpcode()) {
    3547             :     case ARM::t2LDRSHi12:
    3548             :       return MCDisassembler::Fail;
    3549             :     case ARM::t2LDRHi12:
    3550           6 :       Inst.setOpcode(ARM::t2PLDWi12);
    3551             :       break;
    3552             :     case ARM::t2LDRSBi12:
    3553           2 :       Inst.setOpcode(ARM::t2PLIi12);
    3554             :       break;
    3555             :     default:
    3556             :       break;
    3557             :     }
    3558             :   }
    3559             : 
    3560          55 :   switch (Inst.getOpcode()) {
    3561             :   case ARM::t2PLDi12:
    3562             :     break;
    3563          12 :   case ARM::t2PLIi12:
    3564          12 :     if (!hasV7Ops)
    3565             :       return MCDisassembler::Fail;
    3566             :     break;
    3567           8 :   case ARM::t2PLDWi12:
    3568           8 :       if (!hasV7Ops || !hasMP)
    3569             :         return MCDisassembler::Fail;
    3570             :       break;
    3571          22 :   default:
    3572          44 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3573             :       return MCDisassembler::Fail;
    3574             :   }
    3575             : 
    3576          94 :   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
    3577             :     return MCDisassembler::Fail;
    3578             :   return S;
    3579             : }
    3580             : 
    3581          19 : static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
    3582             :                                 uint64_t Address, const void* Decoder) {
    3583          19 :   DecodeStatus S = MCDisassembler::Success;
    3584             : 
    3585          19 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3586          19 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3587          19 :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3588          19 :   imm |= (Rn << 9);
    3589             : 
    3590          19 :   if (Rn == 15) {
    3591           0 :     switch (Inst.getOpcode()) {
    3592             :     case ARM::t2LDRT:
    3593           0 :       Inst.setOpcode(ARM::t2LDRpci);
    3594             :       break;
    3595             :     case ARM::t2LDRBT:
    3596           0 :       Inst.setOpcode(ARM::t2LDRBpci);
    3597             :       break;
    3598             :     case ARM::t2LDRHT:
    3599           0 :       Inst.setOpcode(ARM::t2LDRHpci);
    3600             :       break;
    3601             :     case ARM::t2LDRSBT:
    3602           0 :       Inst.setOpcode(ARM::t2LDRSBpci);
    3603             :       break;
    3604             :     case ARM::t2LDRSHT:
    3605           0 :       Inst.setOpcode(ARM::t2LDRSHpci);
    3606             :       break;
    3607             :     default:
    3608             :       return MCDisassembler::Fail;
    3609             :     }
    3610           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3611             :   }
    3612             : 
    3613          38 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3614             :     return MCDisassembler::Fail;
    3615          38 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
    3616             :     return MCDisassembler::Fail;
    3617             :   return S;
    3618             : }
    3619             : 
    3620          58 : static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
    3621             :                                 uint64_t Address, const void* Decoder) {
    3622          58 :   DecodeStatus S = MCDisassembler::Success;
    3623             : 
    3624          58 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3625          58 :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    3626          58 :   int imm = fieldFromInstruction(Insn, 0, 12);
    3627             : 
    3628             :   const FeatureBitset &featureBits =
    3629          58 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3630             : 
    3631         116 :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3632             : 
    3633          58 :   if (Rt == 15) {
    3634          39 :     switch (Inst.getOpcode()) {
    3635             :       case ARM::t2LDRBpci:
    3636             :       case ARM::t2LDRHpci:
    3637           0 :         Inst.setOpcode(ARM::t2PLDpci);
    3638             :         break;
    3639             :       case ARM::t2LDRSBpci:
    3640           4 :         Inst.setOpcode(ARM::t2PLIpci);
    3641             :         break;
    3642             :       case ARM::t2LDRSHpci:
    3643             :         return MCDisassembler::Fail;
    3644             :       default:
    3645             :         break;
    3646             :     }
    3647             :   }
    3648             : 
    3649          58 :   switch(Inst.getOpcode()) {
    3650             :   case ARM::t2PLDpci:
    3651             :     break;
    3652          19 :   case ARM::t2PLIpci:
    3653          19 :     if (!hasV7Ops)
    3654             :       return MCDisassembler::Fail;
    3655             :     break;
    3656          19 :   default:
    3657          38 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3658             :       return MCDisassembler::Fail;
    3659             :   }
    3660             : 
    3661          54 :   if (!U) {
    3662             :     // Special case for #-0.
    3663          26 :     if (imm == 0)
    3664             :       imm = INT32_MIN;
    3665             :     else
    3666          19 :       imm = -imm;
    3667             :   }
    3668         162 :   Inst.addOperand(MCOperand::createImm(imm));
    3669             : 
    3670             :   return S;
    3671             : }
    3672             : 
    3673          25 : static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
    3674             :                            uint64_t Address, const void *Decoder) {
    3675          25 :   if (Val == 0)
    3676          12 :     Inst.addOperand(MCOperand::createImm(INT32_MIN));
    3677             :   else {
    3678          19 :     int imm = Val & 0xFF;
    3679             : 
    3680          19 :     if (!(Val & 0x100)) imm *= -1;
    3681          57 :     Inst.addOperand(MCOperand::createImm(imm * 4));
    3682             :   }
    3683             : 
    3684          25 :   return MCDisassembler::Success;
    3685             : }
    3686             : 
    3687          17 : static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
    3688             :                                    uint64_t Address, const void *Decoder) {
    3689          17 :   DecodeStatus S = MCDisassembler::Success;
    3690             : 
    3691          17 :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    3692          17 :   unsigned imm = fieldFromInstruction(Val, 0, 9);
    3693             : 
    3694          34 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3695             :     return MCDisassembler::Fail;
    3696          34 :   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
    3697             :     return MCDisassembler::Fail;
    3698             : 
    3699             :   return S;
    3700             : }
    3701             : 
    3702           7 : static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
    3703             :                                    uint64_t Address, const void *Decoder) {
    3704           7 :   DecodeStatus S = MCDisassembler::Success;
    3705             : 
    3706           7 :   unsigned Rn = fieldFromInstruction(Val, 8, 4);
    3707           7 :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    3708             : 
    3709          14 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    3710             :     return MCDisassembler::Fail;
    3711             : 
    3712          21 :   Inst.addOperand(MCOperand::createImm(imm));
    3713             : 
    3714             :   return S;
    3715             : }
    3716             : 
    3717         993 : static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
    3718             :                          uint64_t Address, const void *Decoder) {
    3719         993 :   int imm = Val & 0xFF;
    3720         993 :   if (Val == 0)
    3721             :     imm = INT32_MIN;
    3722         992 :   else if (!(Val & 0x100))
    3723          38 :     imm *= -1;
    3724        2979 :   Inst.addOperand(MCOperand::createImm(imm));
    3725             : 
    3726         993 :   return MCDisassembler::Success;
    3727             : }
    3728             : 
    3729        1005 : static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
    3730             :                                  uint64_t Address, const void *Decoder) {
    3731        1005 :   DecodeStatus S = MCDisassembler::Success;
    3732             : 
    3733        1005 :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    3734        1005 :   unsigned imm = fieldFromInstruction(Val, 0, 9);
    3735             : 
    3736             :   // Thumb stores cannot use PC as dest register.
    3737        1005 :   switch (Inst.getOpcode()) {
    3738          21 :   case ARM::t2STRT:
    3739             :   case ARM::t2STRBT:
    3740             :   case ARM::t2STRHT:
    3741             :   case ARM::t2STRi8:
    3742             :   case ARM::t2STRHi8:
    3743             :   case ARM::t2STRBi8:
    3744          21 :     if (Rn == 15)
    3745             :       return MCDisassembler::Fail;
    3746             :     break;
    3747             :   default:
    3748             :     break;
    3749             :   }
    3750             : 
    3751             :   // Some instructions always use an additive offset.
    3752         993 :   switch (Inst.getOpcode()) {
    3753          27 :     case ARM::t2LDRT:
    3754             :     case ARM::t2LDRBT:
    3755             :     case ARM::t2LDRHT:
    3756             :     case ARM::t2LDRSBT:
    3757             :     case ARM::t2LDRSHT:
    3758             :     case ARM::t2STRT:
    3759             :     case ARM::t2STRBT:
    3760             :     case ARM::t2STRHT:
    3761          27 :       imm |= 0x100;
    3762             :       break;
    3763             :     default:
    3764             :       break;
    3765             :   }
    3766             : 
    3767        1986 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3768             :     return MCDisassembler::Fail;
    3769        1986 :   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
    3770             :     return MCDisassembler::Fail;
    3771             : 
    3772             :   return S;
    3773             : }
    3774             : 
    3775         942 : static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
    3776             :                                     uint64_t Address, const void *Decoder) {
    3777         942 :   DecodeStatus S = MCDisassembler::Success;
    3778             : 
    3779         942 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3780         942 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3781         942 :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    3782         942 :   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
    3783         942 :   addr |= Rn << 9;
    3784         942 :   unsigned load = fieldFromInstruction(Insn, 20, 1);
    3785             : 
    3786         942 :   if (Rn == 15) {
    3787           2 :     switch (Inst.getOpcode()) {
    3788             :     case ARM::t2LDR_PRE:
    3789             :     case ARM::t2LDR_POST:
    3790           0 :       Inst.setOpcode(ARM::t2LDRpci);
    3791             :       break;
    3792             :     case ARM::t2LDRB_PRE:
    3793             :     case ARM::t2LDRB_POST:
    3794           0 :       Inst.setOpcode(ARM::t2LDRBpci);
    3795             :       break;
    3796             :     case ARM::t2LDRH_PRE:
    3797             :     case ARM::t2LDRH_POST:
    3798           0 :       Inst.setOpcode(ARM::t2LDRHpci);
    3799             :       break;
    3800           0 :     case ARM::t2LDRSB_PRE:
    3801             :     case ARM::t2LDRSB_POST:
    3802           0 :       if (Rt == 15)
    3803           0 :         Inst.setOpcode(ARM::t2PLIpci);
    3804             :       else
    3805           0 :         Inst.setOpcode(ARM::t2LDRSBpci);
    3806             :       break;
    3807             :     case ARM::t2LDRSH_PRE:
    3808             :     case ARM::t2LDRSH_POST:
    3809           0 :       Inst.setOpcode(ARM::t2LDRSHpci);
    3810             :       break;
    3811             :     default:
    3812             :       return MCDisassembler::Fail;
    3813             :     }
    3814           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3815             :   }
    3816             : 
    3817         940 :   if (!load) {
    3818         910 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3819             :       return MCDisassembler::Fail;
    3820             :   }
    3821             : 
    3822        1880 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3823             :     return MCDisassembler::Fail;
    3824             : 
    3825         940 :   if (load) {
    3826         970 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3827             :       return MCDisassembler::Fail;
    3828             :   }
    3829             : 
    3830        1880 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
    3831             :     return MCDisassembler::Fail;
    3832             : 
    3833             :   return S;
    3834             : }
    3835             : 
    3836          57 : static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
    3837             :                                   uint64_t Address, const void *Decoder) {
    3838          57 :   DecodeStatus S = MCDisassembler::Success;
    3839             : 
    3840          57 :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    3841          57 :   unsigned imm = fieldFromInstruction(Val, 0, 12);
    3842             : 
    3843             :   // Thumb stores cannot use PC as dest register.
    3844          57 :   switch (Inst.getOpcode()) {
    3845          10 :   case ARM::t2STRi12:
    3846             :   case ARM::t2STRBi12:
    3847             :   case ARM::t2STRHi12:
    3848          10 :     if (Rn == 15)
    3849             :       return MCDisassembler::Fail;
    3850             :   default:
    3851             :     break;
    3852             :   }
    3853             : 
    3854         106 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3855             :     return MCDisassembler::Fail;
    3856         159 :   Inst.addOperand(MCOperand::createImm(imm));
    3857             : 
    3858             :   return S;
    3859             : }
    3860             : 
    3861             : 
    3862         501 : static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
    3863             :                                 uint64_t Address, const void *Decoder) {
    3864         501 :   unsigned imm = fieldFromInstruction(Insn, 0, 7);
    3865             : 
    3866        1002 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3867        1002 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3868        1503 :   Inst.addOperand(MCOperand::createImm(imm));
    3869             : 
    3870         501 :   return MCDisassembler::Success;
    3871             : }
    3872             : 
    3873          20 : static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
    3874             :                                 uint64_t Address, const void *Decoder) {
    3875          20 :   DecodeStatus S = MCDisassembler::Success;
    3876             : 
    3877          20 :   if (Inst.getOpcode() == ARM::tADDrSP) {
    3878           5 :     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
    3879           5 :     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
    3880             : 
    3881          10 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
    3882             :     return MCDisassembler::Fail;
    3883          10 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3884          10 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
    3885             :     return MCDisassembler::Fail;
    3886          15 :   } else if (Inst.getOpcode() == ARM::tADDspr) {
    3887          15 :     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
    3888             : 
    3889          30 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3890          30 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3891          30 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3892             :     return MCDisassembler::Fail;
    3893             :   }
    3894             : 
    3895             :   return S;
    3896             : }
    3897             : 
    3898           1 : static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
    3899             :                            uint64_t Address, const void *Decoder) {
    3900           1 :   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
    3901           1 :   unsigned flags = fieldFromInstruction(Insn, 0, 3);
    3902             : 
    3903           3 :   Inst.addOperand(MCOperand::createImm(imod));
    3904           3 :   Inst.addOperand(MCOperand::createImm(flags));
    3905             : 
    3906           1 :   return MCDisassembler::Success;
    3907             : }
    3908             : 
    3909          15 : static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
    3910             :                              uint64_t Address, const void *Decoder) {
    3911          15 :   DecodeStatus S = MCDisassembler::Success;
    3912          15 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3913          15 :   unsigned add = fieldFromInstruction(Insn, 4, 1);
    3914             : 
    3915          30 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    3916             :     return MCDisassembler::Fail;
    3917          45 :   Inst.addOperand(MCOperand::createImm(add));
    3918             : 
    3919             :   return S;
    3920             : }
    3921             : 
    3922          41 : static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
    3923             :                                  uint64_t Address, const void *Decoder) {
    3924             :   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
    3925             :   // Note only one trailing zero not two.  Also the J1 and J2 values are from
    3926             :   // the encoded instruction.  So here change to I1 and I2 values via:
    3927             :   // I1 = NOT(J1 EOR S);
    3928             :   // I2 = NOT(J2 EOR S);
    3929             :   // and build the imm32 with two trailing zeros as documented:
    3930             :   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
    3931          41 :   unsigned S = (Val >> 23) & 1;
    3932          41 :   unsigned J1 = (Val >> 22) & 1;
    3933          41 :   unsigned J2 = (Val >> 21) & 1;
    3934          41 :   unsigned I1 = !(J1 ^ S);
    3935          41 :   unsigned I2 = !(J2 ^ S);
    3936          41 :   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
    3937          82 :   int imm32 = SignExtend32<25>(tmp << 1);
    3938             : 
    3939          82 :   if (!tryAddingSymbolicOperand(Address,
    3940          41 :                                 (Address & ~2u) + imm32 + 4,
    3941             :                                 true, 4, Inst, Decoder))
    3942         105 :     Inst.addOperand(MCOperand::createImm(imm32));
    3943          41 :   return MCDisassembler::Success;
    3944             : }
    3945             : 
    3946         137 : static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
    3947             :                               uint64_t Address, const void *Decoder) {
    3948         137 :   if (Val == 0xA || Val == 0xB)
    3949             :     return MCDisassembler::Fail;
    3950             : 
    3951             :   const FeatureBitset &featureBits =
    3952         115 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3953             : 
    3954         230 :   if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
    3955             :     return MCDisassembler::Fail;
    3956             : 
    3957         297 :   Inst.addOperand(MCOperand::createImm(Val));
    3958             :   return MCDisassembler::Success;
    3959             : }
    3960             : 
    3961             : static DecodeStatus
    3962           6 : DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
    3963             :                        uint64_t Address, const void *Decoder) {
    3964           6 :   DecodeStatus S = MCDisassembler::Success;
    3965             : 
    3966           6 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3967           6 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3968             : 
    3969           6 :   if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
    3970          12 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3971             :     return MCDisassembler::Fail;
    3972          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3973             :     return MCDisassembler::Fail;
    3974             :   return S;
    3975             : }
    3976             : 
    3977             : static DecodeStatus
    3978          25 : DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
    3979             :                            uint64_t Address, const void *Decoder) {
    3980          25 :   DecodeStatus S = MCDisassembler::Success;
    3981             : 
    3982          25 :   unsigned pred = fieldFromInstruction(Insn, 22, 4);
    3983          25 :   if (pred == 0xE || pred == 0xF) {
    3984           8 :     unsigned opc = fieldFromInstruction(Insn, 4, 28);
    3985           8 :     switch (opc) {
    3986             :       default:
    3987             :         return MCDisassembler::Fail;
    3988             :       case 0xf3bf8f4:
    3989           0 :         Inst.setOpcode(ARM::t2DSB);
    3990             :         break;
    3991             :       case 0xf3bf8f5:
    3992           0 :         Inst.setOpcode(ARM::t2DMB);
    3993             :         break;
    3994             :       case 0xf3bf8f6:
    3995           0 :         Inst.setOpcode(ARM::t2ISB);
    3996             :         break;
    3997             :     }
    3998             : 
    3999           0 :     unsigned imm = fieldFromInstruction(Insn, 0, 4);
    4000           0 :     return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
    4001             :   }
    4002             : 
    4003          17 :   unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
    4004          17 :   brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
    4005          17 :   brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
    4006          17 :   brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
    4007          17 :   brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
    4008             : 
    4009          34 :   if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
    4010             :     return MCDisassembler::Fail;
    4011          34 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4012             :     return MCDisassembler::Fail;
    4013             : 
    4014          17 :   return S;
    4015             : }
    4016             : 
    4017             : // Decode a shifted immediate operand.  These basically consist
    4018             : // of an 8-bit value, and a 4-bit directive that specifies either
    4019             : // a splat operation or a rotation.
    4020         251 : static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
    4021             :                           uint64_t Address, const void *Decoder) {
    4022         251 :   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
    4023         251 :   if (ctrl == 0) {
    4024         163 :     unsigned byte = fieldFromInstruction(Val, 8, 2);
    4025         163 :     unsigned imm = fieldFromInstruction(Val, 0, 8);
    4026         163 :     switch (byte) {
    4027         152 :       case 0:
    4028         456 :         Inst.addOperand(MCOperand::createImm(imm));
    4029             :         break;
    4030           3 :       case 1:
    4031           9 :         Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
    4032             :         break;
    4033           3 :       case 2:
    4034           9 :         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
    4035             :         break;
    4036           5 :       case 3:
    4037          20 :         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
    4038          10 :                                              (imm << 8)  |  imm));
    4039             :         break;
    4040             :     }
    4041             :   } else {
    4042          88 :     unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
    4043          88 :     unsigned rot = fieldFromInstruction(Val, 7, 5);
    4044          88 :     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
    4045         264 :     Inst.addOperand(MCOperand::createImm(imm));
    4046             :   }
    4047             : 
    4048         251 :   return MCDisassembler::Success;
    4049             : }
    4050             : 
    4051             : static DecodeStatus
    4052         102 : DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
    4053             :                             uint64_t Address, const void *Decoder) {
    4054         306 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
    4055             :                                 true, 2, Inst, Decoder))
    4056         306 :     Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
    4057         102 :   return MCDisassembler::Success;
    4058             : }
    4059             : 
    4060         219 : static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
    4061             :                                                uint64_t Address,
    4062             :                                                const void *Decoder) {
    4063             :   // Val is passed in as S:J1:J2:imm10:imm11
    4064             :   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
    4065             :   // the encoded instruction.  So here change to I1 and I2 values via:
    4066             :   // I1 = NOT(J1 EOR S);
    4067             :   // I2 = NOT(J2 EOR S);
    4068             :   // and build the imm32 with one trailing zero as documented:
    4069             :   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
    4070         219 :   unsigned S = (Val >> 23) & 1;
    4071         219 :   unsigned J1 = (Val >> 22) & 1;
    4072         219 :   unsigned J2 = (Val >> 21) & 1;
    4073         219 :   unsigned I1 = !(J1 ^ S);
    4074         219 :   unsigned I2 = !(J2 ^ S);
    4075         219 :   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
    4076         438 :   int imm32 = SignExtend32<25>(tmp << 1);
    4077             : 
    4078         438 :   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
    4079             :                                 true, 4, Inst, Decoder))
    4080         648 :     Inst.addOperand(MCOperand::createImm(imm32));
    4081         219 :   return MCDisassembler::Success;
    4082             : }
    4083             : 
    4084             : static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
    4085             :                                    uint64_t Address, const void *Decoder) {
    4086             :   if (Val & ~0xf)
    4087             :     return MCDisassembler::Fail;
    4088             : 
    4089         234 :   Inst.addOperand(MCOperand::createImm(Val));
    4090             :   return MCDisassembler::Success;
    4091             : }
    4092             : 
    4093             : static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
    4094             :                                         uint64_t Address, const void *Decoder) {
    4095             :   if (Val & ~0xf)
    4096             :     return MCDisassembler::Fail;
    4097             : 
    4098          18 :   Inst.addOperand(MCOperand::createImm(Val));
    4099             :   return MCDisassembler::Success;
    4100             : }
    4101             : 
    4102         114 : static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
    4103             :                           uint64_t Address, const void *Decoder) {
    4104         114 :   DecodeStatus S = MCDisassembler::Success;
    4105             :   const FeatureBitset &FeatureBits =
    4106         114 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    4107             : 
    4108         228 :   if (FeatureBits[ARM::FeatureMClass]) {
    4109          63 :     unsigned ValLow = Val & 0xff;
    4110             : 
    4111             :     // Validate the SYSm value first.
    4112          63 :     switch (ValLow) {
    4113             :     case  0: // apsr
    4114             :     case  1: // iapsr
    4115             :     case  2: // eapsr
    4116             :     case  3: // xpsr
    4117             :     case  5: // ipsr
    4118             :     case  6: // epsr
    4119             :     case  7: // iepsr
    4120             :     case  8: // msp
    4121             :     case  9: // psp
    4122             :     case 16: // primask
    4123             :     case 20: // control
    4124             :       break;
    4125           6 :     case 17: // basepri
    4126             :     case 18: // basepri_max
    4127             :     case 19: // faultmask
    4128          12 :       if (!(FeatureBits[ARM::HasV7Ops]))
    4129             :         // Values basepri, basepri_max and faultmask are only valid for v7m.
    4130             :         return MCDisassembler::Fail;
    4131             :       break;
    4132           3 :     case 0x8a: // msplim_ns
    4133             :     case 0x8b: // psplim_ns
    4134             :     case 0x91: // basepri_ns
    4135             :     case 0x92: // basepri_max_ns
    4136             :     case 0x93: // faultmask_ns
    4137           6 :       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
    4138             :         return MCDisassembler::Fail;
    4139             :       LLVM_FALLTHROUGH;
    4140             :     case 10:   // msplim
    4141             :     case 11:   // psplim
    4142             :     case 0x88: // msp_ns
    4143             :     case 0x89: // psp_ns
    4144             :     case 0x90: // primask_ns
    4145             :     case 0x94: // control_ns
    4146             :     case 0x98: // sp_ns
    4147          28 :       if (!(FeatureBits[ARM::Feature8MSecExt]))
    4148             :         return MCDisassembler::Fail;
    4149             :       break;
    4150             :     default:
    4151             :       return MCDisassembler::Fail;
    4152             :     }
    4153             : 
    4154          58 :     if (Inst.getOpcode() == ARM::t2MSR_M) {
    4155          37 :       unsigned Mask = fieldFromInstruction(Val, 10, 2);
    4156          74 :       if (!(FeatureBits[ARM::HasV7Ops])) {
    4157             :         // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
    4158             :         // unpredictable.
    4159           3 :         if (Mask != 2)
    4160           0 :           S = MCDisassembler::SoftFail;
    4161             :       }
    4162             :       else {
    4163             :         // The ARMv7-M architecture stores an additional 2-bit mask value in
    4164             :         // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
    4165             :         // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
    4166             :         // the NZCVQ bits should be moved by the instruction. Bit mask{0}
    4167             :         // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
    4168             :         // only if the processor includes the DSP extension.
    4169          64 :         if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
    4170          66 :             (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
    4171             :           S = MCDisassembler::SoftFail;
    4172             :       }
    4173             :     }
    4174             :   } else {
    4175             :     // A/R class
    4176          51 :     if (Val == 0)
    4177             :       return MCDisassembler::Fail;
    4178             :   }
    4179         318 :   Inst.addOperand(MCOperand::createImm(Val));
    4180             :   return S;
    4181             : }
    4182             : 
    4183         132 : static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
    4184             :                                     uint64_t Address, const void *Decoder) {
    4185             : 
    4186         132 :   unsigned R = fieldFromInstruction(Val, 5, 1);
    4187         132 :   unsigned SysM = fieldFromInstruction(Val, 0, 5);
    4188             : 
    4189             :   // The table of encodings for these banked registers comes from B9.2.3 of the
    4190             :   // ARM ARM. There are patterns, but nothing regular enough to make this logic
    4191             :   // neater. So by fiat, these values are UNPREDICTABLE:
    4192         132 :   if (!R) {
    4193         104 :     if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
    4194         104 :         SysM == 0x1a || SysM == 0x1b)
    4195             :       return MCDisassembler::SoftFail;
    4196             :   } else {
    4197          28 :     if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
    4198          12 :         SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
    4199             :       return MCDisassembler::SoftFail;
    4200             :   }
    4201             : 
    4202         396 :   Inst.addOperand(MCOperand::createImm(Val));
    4203             :   return MCDisassembler::Success;
    4204             : }
    4205             : 
    4206           7 : static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
    4207             :                                         uint64_t Address, const void *Decoder) {
    4208           7 :   DecodeStatus S = MCDisassembler::Success;
    4209             : 
    4210           7 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4211           7 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4212           7 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4213             : 
    4214           7 :   if (Rn == 0xF)
    4215           0 :     S = MCDisassembler::SoftFail;
    4216             : 
    4217          14 :   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
    4218             :     return MCDisassembler::Fail;
    4219          14 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4220             :     return MCDisassembler::Fail;
    4221          14 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4222             :     return MCDisassembler::Fail;
    4223             : 
    4224             :   return S;
    4225             : }
    4226             : 
    4227           8 : static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
    4228             :                                          uint64_t Address,
    4229             :                                          const void *Decoder) {
    4230           8 :   DecodeStatus S = MCDisassembler::Success;
    4231             : 
    4232           8 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4233           8 :   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
    4234           8 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4235           8 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4236             : 
    4237          16 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    4238             :     return MCDisassembler::Fail;
    4239             : 
    4240           8 :   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
    4241           0 :     S = MCDisassembler::SoftFail;
    4242             : 
    4243          16 :   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
    4244             :     return MCDisassembler::Fail;
    4245          16 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4246             :     return MCDisassembler::Fail;
    4247          16 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4248             :     return MCDisassembler::Fail;
    4249             : 
    4250             :   return S;
    4251             : }
    4252             : 
    4253          10 : static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
    4254             :                             uint64_t Address, const void *Decoder) {
    4255          10 :   DecodeStatus S = MCDisassembler::Success;
    4256             : 
    4257          10 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4258          10 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4259          10 :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4260          10 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4261          10 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4262          10 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4263             : 
    4264          10 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4265             : 
    4266          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4267             :     return MCDisassembler::Fail;
    4268          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4269             :     return MCDisassembler::Fail;
    4270          20 :   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
    4271             :     return MCDisassembler::Fail;
    4272          20 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4273             :     return MCDisassembler::Fail;
    4274             : 
    4275          10 :   return S;
    4276             : }
    4277             : 
    4278           9 : static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
    4279             :                             uint64_t Address, const void *Decoder) {
    4280           9 :   DecodeStatus S = MCDisassembler::Success;
    4281             : 
    4282           9 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4283           9 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4284           9 :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4285           9 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4286           9 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4287           9 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4288           9 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4289             : 
    4290           9 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4291           9 :   if (Rm == 0xF) S = MCDisassembler::SoftFail;
    4292             : 
    4293          18 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4294             :     return MCDisassembler::Fail;
    4295          18 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4296             :     return MCDisassembler::Fail;
    4297          18 :   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
    4298             :     return MCDisassembler::Fail;
    4299          18 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4300             :     return MCDisassembler::Fail;
    4301             : 
    4302             :   return S;
    4303             : }
    4304             : 
    4305          13 : static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
    4306             :                             uint64_t Address, const void *Decoder) {
    4307          13 :   DecodeStatus S = MCDisassembler::Success;
    4308             : 
    4309          13 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4310          13 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4311          13 :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4312          13 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4313          13 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4314          13 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4315             : 
    4316          13 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4317             : 
    4318          26 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4319             :     return MCDisassembler::Fail;
    4320          26 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4321             :     return MCDisassembler::Fail;
    4322          26 :   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
    4323             :     return MCDisassembler::Fail;
    4324          26 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4325             :     return MCDisassembler::Fail;
    4326             : 
    4327          13 :   return S;
    4328             : }
    4329             : 
    4330           5 : static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
    4331             :                             uint64_t Address, const void *Decoder) {
    4332           5 :   DecodeStatus S = MCDisassembler::Success;
    4333             : 
    4334           5 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4335           5 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4336           5 :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4337           5 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4338           5 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4339           5 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4340             : 
    4341           5 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4342             : 
    4343          10 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4344             :     return MCDisassembler::Fail;
    4345          10 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4346             :     return MCDisassembler::Fail;
    4347          10 :   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
    4348             :     return MCDisassembler::Fail;
    4349          10 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4350             :     return MCDisassembler::Fail;
    4351             : 
    4352             :   return S;
    4353             : }
    4354             : 
    4355          36 : static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
    4356             :                          uint64_t Address, const void *Decoder) {
    4357          36 :   DecodeStatus S = MCDisassembler::Success;
    4358             : 
    4359          36 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4360          36 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4361          36 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4362          36 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4363          36 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4364             : 
    4365          36 :   unsigned align = 0;
    4366          36 :   unsigned index = 0;
    4367          36 :   switch (size) {
    4368             :     default:
    4369             :       return MCDisassembler::Fail;
    4370          12 :     case 0:
    4371          12 :       if (fieldFromInstruction(Insn, 4, 1))
    4372             :         return MCDisassembler::Fail; // UNDEFINED
    4373          12 :       index = fieldFromInstruction(Insn, 5, 3);
    4374             :       break;
    4375          16 :     case 1:
    4376          16 :       if (fieldFromInstruction(Insn, 5, 1))
    4377             :         return MCDisassembler::Fail; // UNDEFINED
    4378          16 :       index = fieldFromInstruction(Insn, 6, 2);
    4379          16 :       if (fieldFromInstruction(Insn, 4, 1))
    4380          12 :         align = 2;
    4381             :       break;
    4382           8 :     case 2:
    4383           8 :       if (fieldFromInstruction(Insn, 6, 1))
    4384             :         return MCDisassembler::Fail; // UNDEFINED
    4385           8 :       index = fieldFromInstruction(Insn, 7, 1);
    4386             : 
    4387           8 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4388             :         case 0 :
    4389             :           align = 0; break;
    4390           4 :         case 3:
    4391           4 :           align = 4; break;
    4392             :         default:
    4393             :           return MCDisassembler::Fail;
    4394             :       }
    4395             :       break;
    4396             :   }
    4397             : 
    4398          68 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4399             :     return MCDisassembler::Fail;
    4400          34 :   if (Rm != 0xF) { // Writeback
    4401          52 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4402             :       return MCDisassembler::Fail;
    4403             :   }
    4404          68 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4405             :     return MCDisassembler::Fail;
    4406         102 :   Inst.addOperand(MCOperand::createImm(align));
    4407          34 :   if (Rm != 0xF) {
    4408          26 :     if (Rm != 0xD) {
    4409          48 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4410             :         return MCDisassembler::Fail;
    4411             :     } else
    4412           4 :       Inst.addOperand(MCOperand::createReg(0));
    4413             :   }
    4414             : 
    4415          68 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4416             :     return MCDisassembler::Fail;
    4417         102 :   Inst.addOperand(MCOperand::createImm(index));
    4418             : 
    4419             :   return S;
    4420             : }
    4421             : 
    4422          30 : static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
    4423             :                          uint64_t Address, const void *Decoder) {
    4424          30 :   DecodeStatus S = MCDisassembler::Success;
    4425             : 
    4426          30 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4427          30 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4428          30 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4429          30 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4430          30 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4431             : 
    4432          30 :   unsigned align = 0;
    4433          30 :   unsigned index = 0;
    4434          30 :   switch (size) {
    4435             :     default:
    4436             :       return MCDisassembler::Fail;
    4437          10 :     case 0:
    4438          10 :       if (fieldFromInstruction(Insn, 4, 1))
    4439             :         return MCDisassembler::Fail; // UNDEFINED
    4440          10 :       index = fieldFromInstruction(Insn, 5, 3);
    4441             :       break;
    4442          14 :     case 1:
    4443          14 :       if (fieldFromInstruction(Insn, 5, 1))
    4444             :         return MCDisassembler::Fail; // UNDEFINED
    4445          14 :       index = fieldFromInstruction(Insn, 6, 2);
    4446          14 :       if (fieldFromInstruction(Insn, 4, 1))
    4447          10 :         align = 2;
    4448             :       break;
    4449           6 :     case 2:
    4450           6 :       if (fieldFromInstruction(Insn, 6, 1))
    4451             :         return MCDisassembler::Fail; // UNDEFINED
    4452           6 :       index = fieldFromInstruction(Insn, 7, 1);
    4453             : 
    4454           6 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4455             :         case 0: 
    4456             :           align = 0; break;
    4457           2 :         case 3:
    4458           2 :           align = 4; break;
    4459             :         default:
    4460             :           return MCDisassembler::Fail;
    4461             :       }
    4462             :       break;
    4463             :   }
    4464             : 
    4465          28 :   if (Rm != 0xF) { // Writeback
    4466          52 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4467             :     return MCDisassembler::Fail;
    4468             :   }
    4469          56 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4470             :     return MCDisassembler::Fail;
    4471          84 :   Inst.addOperand(MCOperand::createImm(align));
    4472          28 :   if (Rm != 0xF) {
    4473          26 :     if (Rm != 0xD) {
    4474          48 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4475             :     return MCDisassembler::Fail;
    4476             :     } else
    4477           4 :       Inst.addOperand(MCOperand::createReg(0));
    4478             :   }
    4479             : 
    4480          56 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4481             :     return MCDisassembler::Fail;
    4482          84 :   Inst.addOperand(MCOperand::createImm(index));
    4483             : 
    4484             :   return S;
    4485             : }
    4486             : 
    4487          10 : static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
    4488             :                          uint64_t Address, const void *Decoder) {
    4489          10 :   DecodeStatus S = MCDisassembler::Success;
    4490             : 
    4491          10 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4492          10 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4493          10 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4494          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4495          10 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4496             : 
    4497          10 :   unsigned align = 0;
    4498          10 :   unsigned index = 0;
    4499          10 :   unsigned inc = 1;
    4500          10 :   switch (size) {
    4501             :     default:
    4502             :       return MCDisassembler::Fail;
    4503           2 :     case 0:
    4504           2 :       index = fieldFromInstruction(Insn, 5, 3);
    4505           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4506           2 :         align = 2;
    4507             :       break;
    4508           4 :     case 1:
    4509           4 :       index = fieldFromInstruction(Insn, 6, 2);
    4510           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4511           2 :         align = 4;
    4512           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4513           2 :         inc = 2;
    4514             :       break;
    4515           4 :     case 2:
    4516           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4517             :         return MCDisassembler::Fail; // UNDEFINED
    4518           4 :       index = fieldFromInstruction(Insn, 7, 1);
    4519           4 :       if (fieldFromInstruction(Insn, 4, 1) != 0)
    4520           2 :         align = 8;
    4521           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4522           2 :         inc = 2;
    4523             :       break;
    4524             :   }
    4525             : 
    4526          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4527             :     return MCDisassembler::Fail;
    4528          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4529             :     return MCDisassembler::Fail;
    4530          10 :   if (Rm != 0xF) { // Writeback
    4531           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4532             :       return MCDisassembler::Fail;
    4533             :   }
    4534          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4535             :     return MCDisassembler::Fail;
    4536          30 :   Inst.addOperand(MCOperand::createImm(align));
    4537          10 :   if (Rm != 0xF) {
    4538           0 :     if (Rm != 0xD) {
    4539           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4540             :         return MCDisassembler::Fail;
    4541             :     } else
    4542           0 :       Inst.addOperand(MCOperand::createReg(0));
    4543             :   }
    4544             : 
    4545          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4546             :     return MCDisassembler::Fail;
    4547          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4548             :     return MCDisassembler::Fail;
    4549          30 :   Inst.addOperand(MCOperand::createImm(index));
    4550             : 
    4551             :   return S;
    4552             : }
    4553             : 
    4554          10 : static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
    4555             :                          uint64_t Address, const void *Decoder) {
    4556          10 :   DecodeStatus S = MCDisassembler::Success;
    4557             : 
    4558          10 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4559          10 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4560          10 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4561          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4562          10 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4563             : 
    4564          10 :   unsigned align = 0;
    4565          10 :   unsigned index = 0;
    4566          10 :   unsigned inc = 1;
    4567          10 :   switch (size) {
    4568             :     default:
    4569             :       return MCDisassembler::Fail;
    4570           2 :     case 0:
    4571           2 :       index = fieldFromInstruction(Insn, 5, 3);
    4572           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4573           2 :         align = 2;
    4574             :       break;
    4575           4 :     case 1:
    4576           4 :       index = fieldFromInstruction(Insn, 6, 2);
    4577           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4578           2 :         align = 4;
    4579           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4580           2 :         inc = 2;
    4581             :       break;
    4582           4 :     case 2:
    4583           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4584             :         return MCDisassembler::Fail; // UNDEFINED
    4585           4 :       index = fieldFromInstruction(Insn, 7, 1);
    4586           4 :       if (fieldFromInstruction(Insn, 4, 1) != 0)
    4587           2 :         align = 8;
    4588           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4589           2 :         inc = 2;
    4590             :       break;
    4591             :   }
    4592             : 
    4593          10 :   if (Rm != 0xF) { // Writeback
    4594           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4595             :       return MCDisassembler::Fail;
    4596             :   }
    4597          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4598             :     return MCDisassembler::Fail;
    4599          30 :   Inst.addOperand(MCOperand::createImm(align));
    4600          10 :   if (Rm != 0xF) {
    4601           0 :     if (Rm != 0xD) {
    4602           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4603             :         return MCDisassembler::Fail;
    4604             :     } else
    4605           0 :       Inst.addOperand(MCOperand::createReg(0));
    4606             :   }
    4607             : 
    4608          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4609             :     return MCDisassembler::Fail;
    4610          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4611             :     return MCDisassembler::Fail;
    4612          30 :   Inst.addOperand(MCOperand::createImm(index));
    4613             : 
    4614             :   return S;
    4615             : }
    4616             : 
    4617          10 : static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
    4618             :                          uint64_t Address, const void *Decoder) {
    4619          10 :   DecodeStatus S = MCDisassembler::Success;
    4620             : 
    4621          10 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4622          10 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4623          10 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4624          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4625          10 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4626             : 
    4627          10 :   unsigned align = 0;
    4628          10 :   unsigned index = 0;
    4629          10 :   unsigned inc = 1;
    4630          10 :   switch (size) {
    4631             :     default:
    4632             :       return MCDisassembler::Fail;
    4633           2 :     case 0:
    4634           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4635             :         return MCDisassembler::Fail; // UNDEFINED
    4636           2 :       index = fieldFromInstruction(Insn, 5, 3);
    4637             :       break;
    4638           4 :     case 1:
    4639           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4640             :         return MCDisassembler::Fail; // UNDEFINED
    4641           4 :       index = fieldFromInstruction(Insn, 6, 2);
    4642           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4643           2 :         inc = 2;
    4644             :       break;
    4645           4 :     case 2:
    4646           4 :       if (fieldFromInstruction(Insn, 4, 2))
    4647             :         return MCDisassembler::Fail; // UNDEFINED
    4648           4 :       index = fieldFromInstruction(Insn, 7, 1);
    4649           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4650           2 :         inc = 2;
    4651             :       break;
    4652             :   }
    4653             : 
    4654          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4655             :     return MCDisassembler::Fail;
    4656          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4657             :     return MCDisassembler::Fail;
    4658          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4659             :     return MCDisassembler::Fail;
    4660             : 
    4661          10 :   if (Rm != 0xF) { // Writeback
    4662           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4663             :     return MCDisassembler::Fail;
    4664             :   }
    4665          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4666             :     return MCDisassembler::Fail;
    4667          30 :   Inst.addOperand(MCOperand::createImm(align));
    4668          10 :   if (Rm != 0xF) {
    4669           0 :     if (Rm != 0xD) {
    4670           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4671             :     return MCDisassembler::Fail;
    4672             :     } else
    4673           0 :       Inst.addOperand(MCOperand::createReg(0));
    4674             :   }
    4675             : 
    4676          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4677             :     return MCDisassembler::Fail;
    4678          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4679             :     return MCDisassembler::Fail;
    4680          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4681             :     return MCDisassembler::Fail;
    4682          30 :   Inst.addOperand(MCOperand::createImm(index));
    4683             : 
    4684             :   return S;
    4685             : }
    4686             : 
    4687          10 : static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
    4688             :                          uint64_t Address, const void *Decoder) {
    4689          10 :   DecodeStatus S = MCDisassembler::Success;
    4690             : 
    4691          10 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4692          10 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4693          10 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4694          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4695          10 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4696             : 
    4697          10 :   unsigned align = 0;
    4698          10 :   unsigned index = 0;
    4699          10 :   unsigned inc = 1;
    4700          10 :   switch (size) {
    4701             :     default:
    4702             :       return MCDisassembler::Fail;
    4703           2 :     case 0:
    4704           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4705             :         return MCDisassembler::Fail; // UNDEFINED
    4706           2 :       index = fieldFromInstruction(Insn, 5, 3);
    4707             :       break;
    4708           4 :     case 1:
    4709           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4710             :         return MCDisassembler::Fail; // UNDEFINED
    4711           4 :       index = fieldFromInstruction(Insn, 6, 2);
    4712           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4713           2 :         inc = 2;
    4714             :       break;
    4715           4 :     case 2:
    4716           4 :       if (fieldFromInstruction(Insn, 4, 2))
    4717             :         return MCDisassembler::Fail; // UNDEFINED
    4718           4 :       index = fieldFromInstruction(Insn, 7, 1);
    4719           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4720           2 :         inc = 2;
    4721             :       break;
    4722             :   }
    4723             : 
    4724          10 :   if (Rm != 0xF) { // Writeback
    4725           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4726             :     return MCDisassembler::Fail;
    4727             :   }
    4728          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4729             :     return MCDisassembler::Fail;
    4730          30 :   Inst.addOperand(MCOperand::createImm(align));
    4731          10 :   if (Rm != 0xF) {
    4732           0 :     if (Rm != 0xD) {
    4733           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4734             :     return MCDisassembler::Fail;
    4735             :     } else
    4736           0 :       Inst.addOperand(MCOperand::createReg(0));
    4737             :   }
    4738             : 
    4739          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4740             :     return MCDisassembler::Fail;
    4741          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4742             :     return MCDisassembler::Fail;
    4743          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4744             :     return MCDisassembler::Fail;
    4745          30 :   Inst.addOperand(MCOperand::createImm(index));
    4746             : 
    4747             :   return S;
    4748             : }
    4749             : 
    4750          15 : static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
    4751             :                          uint64_t Address, const void *Decoder) {
    4752          15 :   DecodeStatus S = MCDisassembler::Success;
    4753             : 
    4754          15 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4755          15 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4756          15 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4757          15 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4758          15 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4759             : 
    4760          15 :   unsigned align = 0;
    4761          15 :   unsigned index = 0;
    4762          15 :   unsigned inc = 1;
    4763          15 :   switch (size) {
    4764             :     default:
    4765             :       return MCDisassembler::Fail;
    4766           3 :     case 0:
    4767           3 :       if (fieldFromInstruction(Insn, 4, 1))
    4768           2 :         align = 4;
    4769           3 :       index = fieldFromInstruction(Insn, 5, 3);
    4770             :       break;
    4771           5 :     case 1:
    4772           5 :       if (fieldFromInstruction(Insn, 4, 1))
    4773           2 :         align = 8;
    4774           5 :       index = fieldFromInstruction(Insn, 6, 2);
    4775           5 :       if (fieldFromInstruction(Insn, 5, 1))
    4776           3 :         inc = 2;
    4777             :       break;
    4778           7 :     case 2:
    4779           7 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4780             :         case 0:
    4781             :           align = 0; break;
    4782             :         case 3:
    4783             :           return MCDisassembler::Fail;
    4784           3 :         default:
    4785           3 :           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
    4786             :       }
    4787             : 
    4788           5 :       index = fieldFromInstruction(Insn, 7, 1);
    4789           5 :       if (fieldFromInstruction(Insn, 6, 1))
    4790           2 :         inc = 2;
    4791             :       break;
    4792             :   }
    4793             : 
    4794          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4795             :     return MCDisassembler::Fail;
    4796          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4797             :     return MCDisassembler::Fail;
    4798          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4799             :     return MCDisassembler::Fail;
    4800          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4801             :     return MCDisassembler::Fail;
    4802             : 
    4803          13 :   if (Rm != 0xF) { // Writeback
    4804           6 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4805             :       return MCDisassembler::Fail;
    4806             :   }
    4807          26 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4808             :     return MCDisassembler::Fail;
    4809          39 :   Inst.addOperand(MCOperand::createImm(align));
    4810          13 :   if (Rm != 0xF) {
    4811           3 :     if (Rm != 0xD) {
    4812           6 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4813             :         return MCDisassembler::Fail;
    4814             :     } else
    4815           0 :       Inst.addOperand(MCOperand::createReg(0));
    4816             :   }
    4817             : 
    4818          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4819             :     return MCDisassembler::Fail;
    4820          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4821             :     return MCDisassembler::Fail;
    4822          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4823             :     return MCDisassembler::Fail;
    4824          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4825             :     return MCDisassembler::Fail;
    4826          39 :   Inst.addOperand(MCOperand::createImm(index));
    4827             : 
    4828             :   return S;
    4829             : }
    4830             : 
    4831          16 : static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
    4832             :                          uint64_t Address, const void *Decoder) {
    4833          16 :   DecodeStatus S = MCDisassembler::Success;
    4834             : 
    4835          16 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4836          16 :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4837          16 :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4838          16 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4839          16 :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4840             : 
    4841          16 :   unsigned align = 0;
    4842          16 :   unsigned index = 0;
    4843          16 :   unsigned inc = 1;
    4844          16 :   switch (size) {
    4845             :     default:
    4846             :       return MCDisassembler::Fail;
    4847           4 :     case 0:
    4848           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4849           2 :         align = 4;
    4850           4 :       index = fieldFromInstruction(Insn, 5, 3);
    4851             :       break;
    4852           5 :     case 1:
    4853           5 :       if (fieldFromInstruction(Insn, 4, 1))
    4854           2 :         align = 8;
    4855           5 :       index = fieldFromInstruction(Insn, 6, 2);
    4856           5 :       if (fieldFromInstruction(Insn, 5, 1))
    4857           3 :         inc = 2;
    4858             :       break;
    4859           7 :     case 2:
    4860           7 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4861             :         case 0:
    4862             :           align = 0; break;
    4863             :         case 3:
    4864             :           return MCDisassembler::Fail;
    4865           3 :         default:
    4866           3 :           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
    4867             :       }
    4868             : 
    4869           5 :       index = fieldFromInstruction(Insn, 7, 1);
    4870           5 :       if (fieldFromInstruction(Insn, 6, 1))
    4871           2 :         inc = 2;
    4872             :       break;
    4873             :   }
    4874             : 
    4875          14 :   if (Rm != 0xF) { // Writeback
    4876           8 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4877             :     return MCDisassembler::Fail;
    4878             :   }
    4879          28 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4880             :     return MCDisassembler::Fail;
    4881          42 :   Inst.addOperand(MCOperand::createImm(align));
    4882          14 :   if (Rm != 0xF) {
    4883           4 :     if (Rm != 0xD) {
    4884           6 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4885             :     return MCDisassembler::Fail;
    4886             :     } else
    4887           2 :       Inst.addOperand(MCOperand::createReg(0));
    4888             :   }
    4889             : 
    4890          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4891             :     return MCDisassembler::Fail;
    4892          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4893             :     return MCDisassembler::Fail;
    4894          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4895             :     return MCDisassembler::Fail;
    4896          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4897             :     return MCDisassembler::Fail;
    4898          42 :   Inst.addOperand(MCOperand::createImm(index));
    4899             : 
    4900             :   return S;
    4901             : }
    4902             : 
    4903           2 : static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
    4904             :                                   uint64_t Address, const void *Decoder) {
    4905           2 :   DecodeStatus S = MCDisassembler::Success;
    4906           2 :   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
    4907           2 :   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
    4908           2 :   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
    4909           2 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4910           2 :   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
    4911             : 
    4912           2 :   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
    4913           0 :     S = MCDisassembler::SoftFail;
    4914             : 
    4915           4 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
    4916             :     return MCDisassembler::Fail;
    4917           4 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
    4918             :     return MCDisassembler::Fail;
    4919           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
    4920             :     return MCDisassembler::Fail;
    4921           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
    4922             :     return MCDisassembler::Fail;
    4923           4 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4924             :     return MCDisassembler::Fail;
    4925             : 
    4926             :   return S;
    4927             : }
    4928             : 
    4929           3 : static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
    4930             :                                   uint64_t Address, const void *Decoder) {
    4931           3 :   DecodeStatus S = MCDisassembler::Success;
    4932           3 :   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
    4933           3 :   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
    4934           3 :   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
    4935           3 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4936           3 :   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
    4937             : 
    4938           3 :   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
    4939           0 :     S = MCDisassembler::SoftFail;
    4940             : 
    4941           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
    4942             :     return MCDisassembler::Fail;
    4943           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
    4944             :     return MCDisassembler::Fail;
    4945           6 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
    4946             :     return MCDisassembler::Fail;
    4947           6 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
    4948             :     return MCDisassembler::Fail;
    4949           6 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4950             :     return MCDisassembler::Fail;
    4951             : 
    4952             :   return S;
    4953             : }
    4954             : 
    4955         126 : static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
    4956             :                              uint64_t Address, const void *Decoder) {
    4957         126 :   DecodeStatus S = MCDisassembler::Success;
    4958         126 :   unsigned pred = fieldFromInstruction(Insn, 4, 4);
    4959         126 :   unsigned mask = fieldFromInstruction(Insn, 0, 4);
    4960             : 
    4961         126 :   if (pred == 0xF) {
    4962           2 :     pred = 0xE;
    4963           2 :     S = MCDisassembler::SoftFail;
    4964             :   }
    4965             : 
    4966         126 :   if (mask == 0x0)
    4967             :     return MCDisassembler::Fail;
    4968             : 
    4969         378 :   Inst.addOperand(MCOperand::createImm(pred));
    4970         378 :   Inst.addOperand(MCOperand::createImm(mask));
    4971             :   return S;
    4972             : }
    4973             : 
    4974             : static DecodeStatus
    4975           6 : DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
    4976             :                            uint64_t Address, const void *Decoder) {
    4977           6 :   DecodeStatus S = MCDisassembler::Success;
    4978             : 
    4979           6 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4980           6 :   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
    4981           6 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4982           6 :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    4983           6 :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    4984           6 :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    4985           6 :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    4986           6 :   bool writeback = (W == 1) | (P == 0);
    4987             : 
    4988           6 :   addr |= (U << 8) | (Rn << 9);
    4989             : 
    4990           6 :   if (writeback && (Rn == Rt || Rn == Rt2))
    4991             :     Check(S, MCDisassembler::SoftFail);
    4992           6 :   if (Rt == Rt2)
    4993             :     Check(S, MCDisassembler::SoftFail);
    4994             : 
    4995             :   // Rt
    4996          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4997             :     return MCDisassembler::Fail;
    4998             :   // Rt2
    4999          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
    5000             :     return MCDisassembler::Fail;
    5001             :   // Writeback operand
    5002          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
    5003             :     return MCDisassembler::Fail;
    5004             :   // addr
    5005          12 :   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
    5006             :     return MCDisassembler::Fail;
    5007             : 
    5008             :   return S;
    5009             : }
    5010             : 
    5011             : static DecodeStatus
    5012           4 : DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
    5013             :                            uint64_t Address, const void *Decoder) {
    5014           4 :   DecodeStatus S = MCDisassembler::Success;
    5015             : 
    5016           4 :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    5017           4 :   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
    5018           4 :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    5019           4 :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    5020           4 :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    5021           4 :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    5022           4 :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    5023           4 :   bool writeback = (W == 1) | (P == 0);
    5024             : 
    5025           4 :   addr |= (U << 8) | (Rn << 9);
    5026             : 
    5027           4 :   if (writeback && (Rn == Rt || Rn == Rt2))
    5028             :     Check(S, MCDisassembler::SoftFail);
    5029             : 
    5030             :   // Writeback operand
    5031           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
    5032             :     return MCDisassembler::Fail;
    5033             :   // Rt
    5034           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    5035             :     return MCDisassembler::Fail;
    5036             :   // Rt2
    5037           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
    5038             :     return MCDisassembler::Fail;
    5039             :   // addr
    5040           8 :   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
    5041             :     return MCDisassembler::Fail;
    5042             : 
    5043             :   return S;
    5044             : }
    5045             : 
    5046           0 : static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
    5047             :                                 uint64_t Address, const void *Decoder) {
    5048           0 :   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
    5049           0 :   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
    5050           0 :   if (sign1 != sign2) return MCDisassembler::Fail;
    5051             : 
    5052           0 :   unsigned Val = fieldFromInstruction(Insn, 0, 8);
    5053           0 :   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
    5054           0 :   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
    5055           0 :   Val |= sign1 << 12;
    5056           0 :   Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
    5057             : 
    5058             :   return MCDisassembler::Success;
    5059             : }
    5060             : 
    5061             : static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
    5062             :                                               uint64_t Address,
    5063             :                                               const void *Decoder) {
    5064           6 :   DecodeStatus S = MCDisassembler::Success;
    5065             : 
    5066             :   // Shift of "asr #32" is not allowed in Thumb2 mode.
    5067           6 :   if (Val == 0x20) S = MCDisassembler::Fail;
    5068          18 :   Inst.addOperand(MCOperand::createImm(Val));
    5069             :   return S;
    5070             : }
    5071             : 
    5072          11 : static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
    5073             :                                uint64_t Address, const void *Decoder) {
    5074          11 :   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
    5075          11 :   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
    5076          11 :   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
    5077          11 :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    5078             : 
    5079          11 :   if (pred == 0xF)
    5080           1 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    5081             : 
    5082          10 :   DecodeStatus S = MCDisassembler::Success;
    5083             : 
    5084          10 :   if (Rt == Rn || Rn == Rt2)
    5085           2 :     S = MCDisassembler::SoftFail;
    5086             : 
    5087          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5088             :     return MCDisassembler::Fail;
    5089          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5090             :     return MCDisassembler::Fail;
    5091          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    5092             :     return MCDisassembler::Fail;
    5093          20 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    5094             :     return MCDisassembler::Fail;
    5095             : 
    5096             :   return S;
    5097             : }
    5098             : 
    5099          30 : static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
    5100             :                                 uint64_t Address, const void *Decoder) {
    5101             :   const FeatureBitset &featureBits =
    5102          30 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5103          60 :   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
    5104             : 
    5105          30 :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5106          30 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5107          30 :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5108          30 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5109          30 :   unsigned imm = fieldFromInstruction(Insn, 16, 6);
    5110          30 :   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
    5111          30 :   unsigned op = fieldFromInstruction(Insn, 5, 1);
    5112             : 
    5113          30 :   DecodeStatus S = MCDisassembler::Success;
    5114             : 
    5115             :   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
    5116          30 :   if (!(imm & 0x38)) {
    5117           8 :     if (cmode == 0xF) {
    5118           4 :       if (op == 1) return MCDisassembler::Fail;
    5119           3 :       Inst.setOpcode(ARM::VMOVv2f32);
    5120             :     }
    5121           7 :     if (hasFullFP16) {
    5122           6 :       if (cmode == 0xE) {
    5123           0 :         if (op == 1) {
    5124           0 :           Inst.setOpcode(ARM::VMOVv1i64);
    5125             :         } else {
    5126           0 :           Inst.setOpcode(ARM::VMOVv8i8);
    5127             :         }
    5128             :       }
    5129           6 :       if (cmode == 0xD) {
    5130           2 :         if (op == 1) {
    5131           0 :           Inst.setOpcode(ARM::VMVNv2i32);
    5132             :         } else {
    5133           2 :           Inst.setOpcode(ARM::VMOVv2i32);
    5134             :         }
    5135             :       }
    5136           6 :       if (cmode == 0xC) {
    5137           2 :         if (op == 1) {
    5138           0 :           Inst.setOpcode(ARM::VMVNv2i32);
    5139             :         } else {
    5140           2 :           Inst.setOpcode(ARM::VMOVv2i32);
    5141             :         }
    5142             :       }
    5143             :     }
    5144           7 :     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
    5145             :   }
    5146             : 
    5147          22 :   if (!(imm & 0x20)) return MCDisassembler::Fail;
    5148             : 
    5149          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
    5150             :     return MCDisassembler::Fail;
    5151          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
    5152             :     return MCDisassembler::Fail;
    5153          60 :   Inst.addOperand(MCOperand::createImm(64 - imm));
    5154             : 
    5155             :   return S;
    5156             : }
    5157             : 
    5158          37 : static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
    5159             :                                 uint64_t Address, const void *Decoder) {
    5160             :   const FeatureBitset &featureBits =
    5161          37 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5162          74 :   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
    5163             : 
    5164          37 :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5165          37 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5166          37 :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5167          37 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5168          37 :   unsigned imm = fieldFromInstruction(Insn, 16, 6);
    5169          37 :   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
    5170          37 :   unsigned op = fieldFromInstruction(Insn, 5, 1);
    5171             : 
    5172          37 :   DecodeStatus S = MCDisassembler::Success;
    5173             : 
    5174             :   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
    5175          37 :   if (!(imm & 0x38)) {
    5176          16 :     if (cmode == 0xF) {
    5177           8 :       if (op == 1) return MCDisassembler::Fail;
    5178           3 :       Inst.setOpcode(ARM::VMOVv4f32);
    5179             :     }
    5180          11 :     if (hasFullFP16) {
    5181          10 :       if (cmode == 0xE) {
    5182           0 :         if (op == 1) {
    5183           0 :           Inst.setOpcode(ARM::VMOVv2i64);
    5184             :         } else {
    5185           0 :           Inst.setOpcode(ARM::VMOVv16i8);
    5186             :         }
    5187             :       }
    5188          10 :       if (cmode == 0xD) {
    5189           4 :         if (op == 1) {
    5190           2 :           Inst.setOpcode(ARM::VMVNv4i32);
    5191             :         } else {
    5192           2 :           Inst.setOpcode(ARM::VMOVv4i32);
    5193             :         }
    5194             :       }
    5195          10 :       if (cmode == 0xC) {
    5196           4 :         if (op == 1) {
    5197           2 :           Inst.setOpcode(ARM::VMVNv4i32);
    5198             :         } else {
    5199           2 :           Inst.setOpcode(ARM::VMOVv4i32);
    5200             :         }
    5201             :       }
    5202             :     }
    5203          11 :     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
    5204             :   }
    5205             : 
    5206          21 :   if (!(imm & 0x20)) return MCDisassembler::Fail;
    5207             : 
    5208          42 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
    5209             :     return MCDisassembler::Fail;
    5210          42 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
    5211             :     return MCDisassembler::Fail;
    5212          63 :   Inst.addOperand(MCOperand::createImm(64 - imm));
    5213             : 
    5214             :   return S;
    5215             : }
    5216             : 
    5217          13 : static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
    5218             :                                 uint64_t Address, const void *Decoder) {
    5219          13 :   DecodeStatus S = MCDisassembler::Success;
    5220             : 
    5221          13 :   unsigned Rn = fieldFromInstruction(Val, 16, 4);
    5222          13 :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5223          13 :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    5224          13 :   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
    5225          13 :   unsigned Cond = fieldFromInstruction(Val, 28, 4);
    5226             : 
    5227          13 :   if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
    5228             :     S = MCDisassembler::SoftFail;
    5229             : 
    5230          26 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5231             :     return MCDisassembler::Fail;
    5232          26 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    5233             :     return MCDisassembler::Fail;
    5234          39 :   if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 
    5235             :     return MCDisassembler::Fail;
    5236          26 :   if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
    5237             :     return MCDisassembler::Fail;
    5238          26 :   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
    5239             :     return MCDisassembler::Fail;
    5240             : 
    5241             :   return S;
    5242             : }
    5243             : 
    5244          10 : static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
    5245             :                                             uint64_t Address, const void *Decoder) {
    5246          10 :   DecodeStatus S = MCDisassembler::Success;
    5247             : 
    5248          10 :   unsigned CRm = fieldFromInstruction(Val, 0, 4);
    5249          10 :   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
    5250          10 :   unsigned cop = fieldFromInstruction(Val, 8, 4);
    5251          10 :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5252          10 :   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
    5253             : 
    5254          10 :   if ((cop & ~0x1) == 0xa)
    5255             :     return MCDisassembler::Fail;
    5256             : 
    5257           9 :   if (Rt == Rt2)
    5258           7 :     S = MCDisassembler::SoftFail;
    5259             : 
    5260             :   // We have to check if the instruction is MRRC2
    5261             :   // or MCRR2 when constructing the operands for
    5262             :   // Inst. Reason is because MRRC2 stores to two
    5263             :   // registers so it's tablegen desc has has two
    5264             :   // outputs whereas MCRR doesn't store to any
    5265             :   // registers so all of it's operands are listed
    5266             :   // as inputs, therefore the operand order for
    5267             :   // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
    5268             :   // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
    5269             : 
    5270           9 :   if (Inst.getOpcode() == ARM::MRRC2) {
    5271          10 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5272             :       return MCDisassembler::Fail;
    5273          10 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5274             :       return MCDisassembler::Fail;
    5275             :   }
    5276          27 :   Inst.addOperand(MCOperand::createImm(cop));
    5277          27 :   Inst.addOperand(MCOperand::createImm(opc1));
    5278           9 :   if (Inst.getOpcode() == ARM::MCRR2) {
    5279           8 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5280             :       return MCDisassembler::Fail;
    5281           8 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5282             :       return MCDisassembler::Fail;
    5283             :   }
    5284          27 :   Inst.addOperand(MCOperand::createImm(CRm));
    5285             : 
    5286             :   return S;
    5287             : }

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