LCOV - code coverage report
Current view: top level - lib/Target/ARM/Disassembler - ARMDisassembler.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1344 1397 96.2 %
Date: 2018-07-13 00:08:38 Functions: 125 127 98.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "MCTargetDesc/ARMAddressingModes.h"
      11             : #include "MCTargetDesc/ARMBaseInfo.h"
      12             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      13             : #include "Utils/ARMBaseInfo.h"
      14             : #include "llvm/MC/MCContext.h"
      15             : #include "llvm/MC/MCDisassembler/MCDisassembler.h"
      16             : #include "llvm/MC/MCFixedLenDisassembler.h"
      17             : #include "llvm/MC/MCInst.h"
      18             : #include "llvm/MC/MCInstrDesc.h"
      19             : #include "llvm/MC/MCSubtargetInfo.h"
      20             : #include "llvm/MC/SubtargetFeature.h"
      21             : #include "llvm/Support/Compiler.h"
      22             : #include "llvm/Support/ErrorHandling.h"
      23             : #include "llvm/Support/MathExtras.h"
      24             : #include "llvm/Support/TargetRegistry.h"
      25             : #include "llvm/Support/raw_ostream.h"
      26             : #include <algorithm>
      27             : #include <cassert>
      28             : #include <cstdint>
      29             : #include <vector>
      30             : 
      31             : using namespace llvm;
      32             : 
      33             : #define DEBUG_TYPE "arm-disassembler"
      34             : 
      35             : using DecodeStatus = MCDisassembler::DecodeStatus;
      36             : 
      37             : namespace {
      38             : 
      39             :   // Handles the condition code status of instructions in IT blocks
      40         207 :   class ITStatus
      41             :   {
      42             :     public:
      43             :       // Returns the condition code for instruction in IT block
      44             :       unsigned getITCC() {
      45             :         unsigned CC = ARMCC::AL;
      46       10971 :         if (instrInITBlock())
      47         223 :           CC = ITStates.back();
      48             :         return CC;
      49             :       }
      50             : 
      51             :       // Advances the IT block state to the next T or E
      52             :       void advanceITState() {
      53             :         ITStates.pop_back();
      54             :       }
      55             : 
      56             :       // Returns true if the current instruction is in an IT block
      57             :       bool instrInITBlock() {
      58        2441 :         return !ITStates.empty();
      59             :       }
      60             : 
      61             :       // Returns true if current instruction is the last instruction in an IT block
      62             :       bool instrLastInITBlock() {
      63             :         return ITStates.size() == 1;
      64             :       }
      65             : 
      66             :       // Called when decoding an IT instruction. Sets the IT state for the following
      67             :       // instructions that for the IT block. Firstcond and Mask correspond to the
      68             :       // fields in the IT instruction encoding.
      69         139 :       void setITState(char Firstcond, char Mask) {
      70             :         // (3 - the number of trailing zeros) is the number of then / else.
      71         139 :         unsigned CondBit0 = Firstcond & 1;
      72         278 :         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
      73         139 :         unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
      74             :         assert(NumTZ <= 3 && "Invalid IT mask!");
      75             :         // push condition codes onto the stack the correct order for the pops
      76         241 :         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
      77         102 :           bool T = ((Mask >> Pos) & 1) == CondBit0;
      78         102 :           if (T)
      79          42 :             ITStates.push_back(CCBits);
      80             :           else
      81         120 :             ITStates.push_back(CCBits ^ 1);
      82             :         }
      83         139 :         ITStates.push_back(CCBits);
      84         139 :       }
      85             : 
      86             :     private:
      87             :       std::vector<unsigned char> ITStates;
      88             :   };
      89             : 
      90             : /// ARM disassembler for all ARM platforms.
      91             : class ARMDisassembler : public MCDisassembler {
      92             : public:
      93             :   ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
      94         175 :     MCDisassembler(STI, Ctx) {
      95             :   }
      96             : 
      97         175 :   ~ARMDisassembler() override = default;
      98             : 
      99             :   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
     100             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
     101             :                               raw_ostream &VStream,
     102             :                               raw_ostream &CStream) const override;
     103             : };
     104             : 
     105             : /// Thumb disassembler for all Thumb platforms.
     106             : class ThumbDisassembler : public MCDisassembler {
     107             : public:
     108         207 :   ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
     109         207 :     MCDisassembler(STI, Ctx) {
     110             :   }
     111             : 
     112         621 :   ~ThumbDisassembler() override = default;
     113             : 
     114             :   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
     115             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
     116             :                               raw_ostream &VStream,
     117             :                               raw_ostream &CStream) const override;
     118             : 
     119             : private:
     120             :   mutable ITStatus ITBlock;
     121             : 
     122             :   DecodeStatus AddThumbPredicate(MCInst&) const;
     123             :   void UpdateThumbVFPPredicate(MCInst&) const;
     124             : };
     125             : 
     126             : } // end anonymous namespace
     127             : 
     128             : static bool Check(DecodeStatus &Out, DecodeStatus In) {
     129       83278 :   switch (In) {
     130             :     case MCDisassembler::Success:
     131             :       // Out stays the same.
     132             :       return true;
     133         151 :     case MCDisassembler::SoftFail:
     134             :       Out = In;
     135             :       return true;
     136        1979 :     case MCDisassembler::Fail:
     137             :       Out = In;
     138             :       return false;
     139             :   }
     140           0 :   llvm_unreachable("Invalid DecodeStatus!");
     141             : }
     142             : 
     143             : // Forward declare these because the autogenerated code will reference them.
     144             : // Definitions are further down.
     145             : static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     146             :                                    uint64_t Address, const void *Decoder);
     147             : static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
     148             :                                                unsigned RegNo, uint64_t Address,
     149             :                                                const void *Decoder);
     150             : static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
     151             :                                                unsigned RegNo, uint64_t Address,
     152             :                                                const void *Decoder);
     153             : static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     154             :                                    uint64_t Address, const void *Decoder);
     155             : static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     156             :                                    uint64_t Address, const void *Decoder);
     157             : static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     158             :                                    uint64_t Address, const void *Decoder);
     159             : static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
     160             :                                    uint64_t Address, const void *Decoder);
     161             : static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
     162             :                                    uint64_t Address, const void *Decoder);
     163             : static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
     164             :                                    uint64_t Address, const void *Decoder);
     165             : static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
     166             :                                    uint64_t Address, const void *Decoder);
     167             : static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
     168             :                                    uint64_t Address, const void *Decoder);
     169             : static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
     170             :                                                 unsigned RegNo,
     171             :                                                 uint64_t Address,
     172             :                                                 const void *Decoder);
     173             : static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
     174             :                                    uint64_t Address, const void *Decoder);
     175             : static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
     176             :                                    uint64_t Address, const void *Decoder);
     177             : static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
     178             :                                unsigned RegNo, uint64_t Address,
     179             :                                const void *Decoder);
     180             : 
     181             : static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
     182             :                                uint64_t Address, const void *Decoder);
     183             : static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
     184             :                                uint64_t Address, const void *Decoder);
     185             : static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
     186             :                                uint64_t Address, const void *Decoder);
     187             : static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
     188             :                                uint64_t Address, const void *Decoder);
     189             : static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
     190             :                                uint64_t Address, const void *Decoder);
     191             : 
     192             : static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
     193             :                                uint64_t Address, const void *Decoder);
     194             : static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
     195             :                                uint64_t Address, const void *Decoder);
     196             : static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
     197             :                                                   unsigned Insn,
     198             :                                                   uint64_t Address,
     199             :                                                   const void *Decoder);
     200             : static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
     201             :                                uint64_t Address, const void *Decoder);
     202             : static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
     203             :                                uint64_t Address, const void *Decoder);
     204             : static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
     205             :                                uint64_t Address, const void *Decoder);
     206             : static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
     207             :                                uint64_t Address, const void *Decoder);
     208             : 
     209             : static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
     210             :                                                   unsigned Insn,
     211             :                                                   uint64_t Adddress,
     212             :                                                   const void *Decoder);
     213             : static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
     214             :                                uint64_t Address, const void *Decoder);
     215             : static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
     216             :                                uint64_t Address, const void *Decoder);
     217             : static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
     218             :                                uint64_t Address, const void *Decoder);
     219             : static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
     220             :                                uint64_t Address, const void *Decoder);
     221             : static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
     222             :                                uint64_t Address, const void *Decoder);
     223             : static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
     224             :                                uint64_t Address, const void *Decoder);
     225             : static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
     226             :                                uint64_t Address, const void *Decoder);
     227             : static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
     228             :                                uint64_t Address, const void *Decoder);
     229             : static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
     230             :                                uint64_t Address, const void *Decoder);
     231             : static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
     232             :                                uint64_t Address, const void *Decoder);
     233             : static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
     234             :                                uint64_t Address, const void *Decoder);
     235             : static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
     236             :                                uint64_t Address, const void *Decoder);
     237             : static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
     238             :                                uint64_t Address, const void *Decoder);
     239             : static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
     240             :                                uint64_t Address, const void *Decoder);
     241             : static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
     242             :                                uint64_t Address, const void *Decoder);
     243             : static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
     244             :                                uint64_t Address, const void *Decoder);
     245             : static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
     246             :                                uint64_t Address, const void *Decoder);
     247             : static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
     248             :                                uint64_t Address, const void *Decoder);
     249             : static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
     250             :                                uint64_t Address, const void *Decoder);
     251             : static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
     252             :                                uint64_t Address, const void *Decoder);
     253             : static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
     254             :                                uint64_t Address, const void *Decoder);
     255             : static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
     256             :                                uint64_t Address, const void *Decoder);
     257             : static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
     258             :                                uint64_t Address, const void *Decoder);
     259             : static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
     260             :                                uint64_t Address, const void *Decoder);
     261             : static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
     262             :                                uint64_t Address, const void *Decoder);
     263             : static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
     264             :                                uint64_t Address, const void *Decoder);
     265             : static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
     266             :                                uint64_t Address, const void *Decoder);
     267             : static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
     268             :                                uint64_t Address, const void *Decoder);
     269             : static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
     270             :                                uint64_t Address, const void *Decoder);
     271             : static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
     272             :                                uint64_t Address, const void *Decoder);
     273             : static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
     274             :                                uint64_t Address, const void *Decoder);
     275             : static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
     276             :                                uint64_t Address, const void *Decoder);
     277             : static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
     278             :                                uint64_t Address, const void *Decoder);
     279             : static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
     280             :                                uint64_t Address, const void *Decoder);
     281             : static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
     282             :                                uint64_t Address, const void *Decoder);
     283             : static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
     284             :                                uint64_t Address, const void *Decoder);
     285             : static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
     286             :                                uint64_t Address, const void *Decoder);
     287             : static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
     288             :                                uint64_t Address, const void *Decoder);
     289             : static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
     290             :                                uint64_t Address, const void *Decoder);
     291             : static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
     292             :                                uint64_t Address, const void *Decoder);
     293             : static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
     294             :                                uint64_t Address, const void *Decoder);
     295             : static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
     296             :                                uint64_t Address, const void *Decoder);
     297             : static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
     298             :                                uint64_t Address, const void *Decoder);
     299             : static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
     300             :                                uint64_t Address, const void *Decoder);
     301             : static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
     302             :                                uint64_t Address, const void *Decoder);
     303             : static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
     304             :                                uint64_t Address, const void *Decoder);
     305             : static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
     306             :                                uint64_t Address, const void *Decoder);
     307             : static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
     308             :                                uint64_t Address, const void *Decoder);
     309             : static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
     310             :                                uint64_t Address, const void *Decoder);
     311             : static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
     312             :                                uint64_t Address, const void *Decoder);
     313             : static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
     314             :                                uint64_t Address, const void *Decoder);
     315             : static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
     316             :                                uint64_t Address, const void *Decoder);
     317             : static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
     318             :                                uint64_t Address, const void *Decoder);
     319             : static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
     320             :                                uint64_t Address, const void *Decoder);
     321             : static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
     322             :                                uint64_t Address, const void *Decoder);
     323             : static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
     324             :                                 uint64_t Address, const void *Decoder);
     325             : static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
     326             :                                 uint64_t Address, const void *Decoder);
     327             : static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
     328             :                                                        unsigned Val,
     329             :                                                        uint64_t Address,
     330             :                                                        const void *Decoder);
     331             : 
     332             : static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
     333             :                                uint64_t Address, const void *Decoder);
     334             : static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
     335             :                                uint64_t Address, const void *Decoder);
     336             : static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
     337             :                                uint64_t Address, const void *Decoder);
     338             : static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
     339             :                                uint64_t Address, const void *Decoder);
     340             : static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
     341             :                                uint64_t Address, const void *Decoder);
     342             : static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
     343             :                                uint64_t Address, const void *Decoder);
     344             : static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
     345             :                                uint64_t Address, const void *Decoder);
     346             : static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
     347             :                                uint64_t Address, const void *Decoder);
     348             : static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
     349             :                                uint64_t Address, const void *Decoder);
     350             : static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
     351             :                                uint64_t Address, const void *Decoder);
     352             : static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
     353             :                                uint64_t Address, const void* Decoder);
     354             : static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
     355             :                                uint64_t Address, const void* Decoder);
     356             : static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
     357             :                                uint64_t Address, const void* Decoder);
     358             : static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
     359             :                                uint64_t Address, const void* Decoder);
     360             : static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
     361             :                                uint64_t Address, const void *Decoder);
     362             : static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
     363             :                                uint64_t Address, const void *Decoder);
     364             : static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
     365             :                                uint64_t Address, const void *Decoder);
     366             : static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
     367             :                                uint64_t Address, const void *Decoder);
     368             : static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
     369             :                                uint64_t Address, const void *Decoder);
     370             : static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
     371             :                                uint64_t Address, const void *Decoder);
     372             : static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
     373             :                                 uint64_t Address, const void *Decoder);
     374             : static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
     375             :                                 uint64_t Address, const void *Decoder);
     376             : static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
     377             :                                 uint64_t Address, const void *Decoder);
     378             : static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
     379             :                                 uint64_t Address, const void *Decoder);
     380             : static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
     381             :                                 uint64_t Address, const void *Decoder);
     382             : static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
     383             :                                 uint64_t Address, const void *Decoder);
     384             : static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
     385             :                                 uint64_t Address, const void *Decoder);
     386             : static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
     387             :                                 uint64_t Address, const void *Decoder);
     388             : static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
     389             :                                 uint64_t Address, const void *Decoder);
     390             : static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
     391             :                                 uint64_t Address, const void *Decoder);
     392             : static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
     393             :                                 uint64_t Address, const void *Decoder);
     394             : static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
     395             :                                uint64_t Address, const void *Decoder);
     396             : static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
     397             :                                uint64_t Address, const void *Decoder);
     398             : static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
     399             :                                 uint64_t Address, const void *Decoder);
     400             : static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
     401             :                                 uint64_t Address, const void *Decoder);
     402             : static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
     403             :                                 uint64_t Address, const void *Decoder);
     404             : 
     405             : static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
     406             :                                 uint64_t Address, const void *Decoder);
     407             : static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
     408             :                                             uint64_t Address, const void *Decoder);
     409             : static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
     410             :                                          uint64_t Address, const void *Decoder);
     411             : 
     412             : #include "ARMGenDisassemblerTables.inc"
     413             : 
     414         175 : static MCDisassembler *createARMDisassembler(const Target &T,
     415             :                                              const MCSubtargetInfo &STI,
     416             :                                              MCContext &Ctx) {
     417         350 :   return new ARMDisassembler(STI, Ctx);
     418             : }
     419             : 
     420         207 : static MCDisassembler *createThumbDisassembler(const Target &T,
     421             :                                                const MCSubtargetInfo &STI,
     422             :                                                MCContext &Ctx) {
     423         414 :   return new ThumbDisassembler(STI, Ctx);
     424             : }
     425             : 
     426             : // Post-decoding checks
     427             : static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
     428             :                                             uint64_t Address, raw_ostream &OS,
     429             :                                             raw_ostream &CS,
     430             :                                             uint32_t Insn,
     431             :                                             DecodeStatus Result) {
     432        5355 :   switch (MI.getOpcode()) {
     433           7 :     case ARM::HVC: {
     434             :       // HVC is undefined if condition = 0xf otherwise upredictable
     435             :       // if condition != 0xe
     436           7 :       uint32_t Cond = (Insn >> 28) & 0xF;
     437           7 :       if (Cond == 0xF)
     438             :         return MCDisassembler::Fail;
     439           6 :       if (Cond != 0xE)
     440             :         return MCDisassembler::SoftFail;
     441             :       return Result;
     442             :     }
     443             :     default: return Result;
     444             :   }
     445             : }
     446             : 
     447        7504 : DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     448             :                                              ArrayRef<uint8_t> Bytes,
     449             :                                              uint64_t Address, raw_ostream &OS,
     450             :                                              raw_ostream &CS) const {
     451        7504 :   CommentStream = &CS;
     452             : 
     453             :   assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
     454             :          "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
     455             :          "mode!");
     456             : 
     457             :   // We want to read exactly 4 bytes of data.
     458        7504 :   if (Bytes.size() < 4) {
     459          27 :     Size = 0;
     460          27 :     return MCDisassembler::Fail;
     461             :   }
     462             : 
     463             :   // Encoded as a small-endian 32-bit word in the stream.
     464             :   uint32_t Insn =
     465        7477 :       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
     466             : 
     467             :   // Calling the auto-generated decoder function.
     468             :   DecodeStatus Result =
     469        7477 :       decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
     470        7477 :   if (Result != MCDisassembler::Fail) {
     471        5285 :     Size = 4;
     472             :     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
     473             :   }
     474             : 
     475             :   struct DecodeTable {
     476             :     const uint8_t *P;
     477             :     bool DecodePred;
     478             :   };
     479             : 
     480        2192 :   const DecodeTable Tables[] = {
     481             :       {DecoderTableVFP32, false},      {DecoderTableVFPV832, false},
     482             :       {DecoderTableNEONData32, true},  {DecoderTableNEONLoadStore32, true},
     483             :       {DecoderTableNEONDup32, true},   {DecoderTablev8NEON32, false},
     484             :       {DecoderTablev8Crypto32, false},
     485             :   };
     486             : 
     487       15898 :   for (auto Table : Tables) {
     488        8568 :     Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
     489        8568 :     if (Result != MCDisassembler::Fail) {
     490        1715 :       Size = 4;
     491             :       // Add a fake predicate operand, because we share these instruction
     492             :       // definitions with Thumb2 where these instructions are predicable.
     493        1715 :       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
     494             :         return MCDisassembler::Fail;
     495             :       return Result;
     496             :     }
     497             :   }
     498             : 
     499         477 :   Result =
     500         477 :       decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
     501         477 :   if (Result != MCDisassembler::Fail) {
     502          70 :     Size = 4;
     503             :     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
     504             :   }
     505             : 
     506         407 :   Size = 4;
     507         407 :   return MCDisassembler::Fail;
     508             : }
     509             : 
     510             : namespace llvm {
     511             : 
     512             : extern const MCInstrDesc ARMInsts[];
     513             : 
     514             : } // end namespace llvm
     515             : 
     516             : /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
     517             : /// immediate Value in the MCInst.  The immediate Value has had any PC
     518             : /// adjustment made by the caller.  If the instruction is a branch instruction
     519             : /// then isBranch is true, else false.  If the getOpInfo() function was set as
     520             : /// part of the setupForSymbolicDisassembly() call then that function is called
     521             : /// to get any symbolic information at the Address for this instruction.  If
     522             : /// that returns non-zero then the symbolic information it returns is used to
     523             : /// create an MCExpr and that is added as an operand to the MCInst.  If
     524             : /// getOpInfo() returns zero and isBranch is true then a symbol look up for
     525             : /// Value is done and if a symbol is found an MCExpr is created with that, else
     526             : /// an MCExpr with Value is created.  This function returns true if it adds an
     527             : /// operand to the MCInst and false otherwise.
     528             : static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
     529             :                                      bool isBranch, uint64_t InstSize,
     530             :                                      MCInst &MI, const void *Decoder) {
     531             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
     532             :   // FIXME: Does it make sense for value to be negative?
     533        1354 :   return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
     534        1354 :                                        /* Offset */ 0, InstSize);
     535             : }
     536             : 
     537             : /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
     538             : /// referenced by a load instruction with the base register that is the Pc.
     539             : /// These can often be values in a literal pool near the Address of the
     540             : /// instruction.  The Address of the instruction and its immediate Value are
     541             : /// used as a possible literal pool entry.  The SymbolLookUp call back will
     542             : /// return the name of a symbol referenced by the literal pool's entry if
     543             : /// the referenced address is that of a symbol.  Or it will return a pointer to
     544             : /// a literal 'C' string if the referenced address of the literal pool's entry
     545             : /// is an address into a section with 'C' string literals.
     546             : static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
     547             :                                             const void *Decoder) {
     548             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
     549          85 :   Dis->tryAddingPcLoadReferenceComment(Value, Address);
     550             : }
     551             : 
     552             : // Thumb1 instructions don't have explicit S bits.  Rather, they
     553             : // implicitly set CPSR.  Since it's not represented in the encoding, the
     554             : // auto-generated decoder won't inject the CPSR operand.  We need to fix
     555             : // that as a post-pass.
     556        2441 : static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
     557        2441 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     558        2441 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     559             :   MCInst::iterator I = MI.begin();
     560        8559 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     561        5191 :     if (I == MI.end()) break;
     562        5191 :     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
     563        2132 :       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
     564        6396 :       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
     565        2132 :       return;
     566             :     }
     567             :   }
     568             : 
     569         927 :   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
     570             : }
     571             : 
     572             : // Most Thumb instructions don't have explicit predicates in the
     573             : // encoding, but rather get their predicates from IT context.  We need
     574             : // to fix up the predicate operands using this context information as a
     575             : // post-pass.
     576             : MCDisassembler::DecodeStatus
     577       11106 : ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
     578             :   MCDisassembler::DecodeStatus S = Success;
     579             : 
     580       11106 :   const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
     581             : 
     582             :   // A few instructions actually have predicates encoded in them.  Don't
     583             :   // try to overwrite it if we're seeing one of those.
     584       11106 :   switch (MI.getOpcode()) {
     585         308 :     case ARM::tBcc:
     586             :     case ARM::t2Bcc:
     587             :     case ARM::tCBZ:
     588             :     case ARM::tCBNZ:
     589             :     case ARM::tCPS:
     590             :     case ARM::t2CPS3p:
     591             :     case ARM::t2CPS2p:
     592             :     case ARM::t2CPS1p:
     593             :     case ARM::tMOVSr:
     594             :     case ARM::tSETEND:
     595             :       // Some instructions (mostly conditional branches) are not
     596             :       // allowed in IT blocks.
     597         308 :       if (ITBlock.instrInITBlock())
     598             :         S = SoftFail;
     599             :       else
     600             :         return Success;
     601             :       break;
     602             :     case ARM::t2HINT:
     603          12 :       if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
     604             :         S = SoftFail;
     605             :       break;
     606         102 :     case ARM::tB:
     607             :     case ARM::t2B:
     608             :     case ARM::t2TBB:
     609             :     case ARM::t2TBH:
     610             :       // Some instructions (mostly unconditional branches) can
     611             :       // only appears at the end of, or outside of, an IT.
     612         104 :       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
     613             :         S = SoftFail;
     614             :       break;
     615             :     default:
     616             :       break;
     617             :   }
     618             : 
     619             :   // If we're in an IT block, base the predicate on that.  Otherwise,
     620             :   // assume a predicate of AL.
     621             :   unsigned CC;
     622             :   CC = ITBlock.getITCC();
     623         195 :   if (CC == 0xF) 
     624             :     CC = ARMCC::AL;
     625       10800 :   if (ITBlock.instrInITBlock())
     626             :     ITBlock.advanceITState();
     627             : 
     628       10800 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     629       10800 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     630             :   MCInst::iterator I = MI.begin();
     631       71328 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     632       40898 :     if (I == MI.end()) break;
     633       31624 :     if (OpInfo[i].isPredicate()) {
     634        4080 :       I = MI.insert(I, MCOperand::createImm(CC));
     635        1360 :       ++I;
     636        1360 :       if (CC == ARMCC::AL)
     637        2704 :         MI.insert(I, MCOperand::createReg(0));
     638             :       else
     639          16 :         MI.insert(I, MCOperand::createReg(ARM::CPSR));
     640             :       return S;
     641             :     }
     642             :   }
     643             : 
     644       28320 :   I = MI.insert(I, MCOperand::createImm(CC));
     645        9440 :   ++I;
     646        9440 :   if (CC == ARMCC::AL)
     647       18534 :     MI.insert(I, MCOperand::createReg(0));
     648             :   else
     649         346 :     MI.insert(I, MCOperand::createReg(ARM::CPSR));
     650             : 
     651             :   return S;
     652             : }
     653             : 
     654             : // Thumb VFP instructions are a special case.  Because we share their
     655             : // encodings between ARM and Thumb modes, and they are predicable in ARM
     656             : // mode, the auto-generated decoder will give them an (incorrect)
     657             : // predicate operand.  We need to rewrite these operands based on the IT
     658             : // context as a post-pass.
     659         171 : void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
     660             :   unsigned CC;
     661             :   CC = ITBlock.getITCC();
     662          28 :   if (CC == 0xF)
     663             :     CC = ARMCC::AL;
     664         171 :   if (ITBlock.instrInITBlock())
     665             :     ITBlock.advanceITState();
     666             : 
     667         171 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     668             :   MCInst::iterator I = MI.begin();
     669         171 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     670         801 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     671         486 :     if (OpInfo[i].isPredicate() ) {
     672         171 :       I->setImm(CC);
     673             :       ++I;
     674         171 :       if (CC == ARMCC::AL)
     675             :         I->setReg(0);
     676             :       else
     677             :         I->setReg(ARM::CPSR);
     678             :       return;
     679             :     }
     680             :   }
     681             : }
     682             : 
     683       11983 : DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     684             :                                                ArrayRef<uint8_t> Bytes,
     685             :                                                uint64_t Address,
     686             :                                                raw_ostream &OS,
     687             :                                                raw_ostream &CS) const {
     688       11983 :   CommentStream = &CS;
     689             : 
     690             :   assert(STI.getFeatureBits()[ARM::ModeThumb] &&
     691             :          "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
     692             : 
     693             :   // We want to read exactly 2 bytes of data.
     694       11983 :   if (Bytes.size() < 2) {
     695          10 :     Size = 0;
     696          10 :     return MCDisassembler::Fail;
     697             :   }
     698             : 
     699       11973 :   uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
     700             :   DecodeStatus Result =
     701       11973 :       decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
     702       11973 :   if (Result != MCDisassembler::Fail) {
     703        4635 :     Size = 2;
     704        4635 :     Check(Result, AddThumbPredicate(MI));
     705             :     return Result;
     706             :   }
     707             : 
     708        7338 :   Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
     709             :                              STI);
     710        7338 :   if (Result) {
     711        2132 :     Size = 2;
     712             :     bool InITBlock = ITBlock.instrInITBlock();
     713        2132 :     Check(Result, AddThumbPredicate(MI));
     714        2132 :     AddThumb1SBit(MI, InITBlock);
     715        2132 :     return Result;
     716             :   }
     717             : 
     718             :   Result =
     719        5206 :       decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
     720        5206 :   if (Result != MCDisassembler::Fail) {
     721         139 :     Size = 2;
     722             : 
     723             :     // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
     724             :     // the Thumb predicate.
     725         278 :     if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
     726             :       Result = MCDisassembler::SoftFail;
     727             : 
     728         139 :     Check(Result, AddThumbPredicate(MI));
     729             : 
     730             :     // If we find an IT instruction, we need to parse its condition
     731             :     // code and mask operands so that we can apply them correctly
     732             :     // to the subsequent instructions.
     733         139 :     if (MI.getOpcode() == ARM::t2IT) {
     734         139 :       unsigned Firstcond = MI.getOperand(0).getImm();
     735         139 :       unsigned Mask = MI.getOperand(1).getImm();
     736         139 :       ITBlock.setITState(Firstcond, Mask);
     737             : 
     738             :       // An IT instruction that would give a 'NV' predicate is unpredictable.
     739         139 :       if (Firstcond == ARMCC::AL && !isPowerOf2_32(Mask))
     740           6 :         CS << "unpredictable IT predicate sequence";
     741             :     }
     742             : 
     743             :     return Result;
     744             :   }
     745             : 
     746             :   // We want to read exactly 4 bytes of data.
     747        5067 :   if (Bytes.size() < 4) {
     748           6 :     Size = 0;
     749           6 :     return MCDisassembler::Fail;
     750             :   }
     751             : 
     752             :   uint32_t Insn32 =
     753        5061 :       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
     754             :   Result =
     755        5061 :       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
     756        5061 :   if (Result != MCDisassembler::Fail) {
     757         309 :     Size = 4;
     758             :     bool InITBlock = ITBlock.instrInITBlock();
     759         309 :     Check(Result, AddThumbPredicate(MI));
     760         309 :     AddThumb1SBit(MI, InITBlock);
     761         309 :     return Result;
     762             :   }
     763             : 
     764             :   Result =
     765        4752 :       decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
     766        4752 :   if (Result != MCDisassembler::Fail) {
     767        2569 :     Size = 4;
     768        2569 :     Check(Result, AddThumbPredicate(MI));
     769             :     return Result;
     770             :   }
     771             : 
     772        2183 :   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
     773             :     Result =
     774         676 :         decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
     775         676 :     if (Result != MCDisassembler::Fail) {
     776         171 :       Size = 4;
     777         171 :       UpdateThumbVFPPredicate(MI);
     778         171 :       return Result;
     779             :     }
     780             :   }
     781             : 
     782             :   Result =
     783        2012 :       decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
     784        2012 :   if (Result != MCDisassembler::Fail) {
     785          97 :     Size = 4;
     786          97 :     return Result;
     787             :   }
     788             : 
     789        1915 :   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
     790         505 :     Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
     791             :                                STI);
     792         505 :     if (Result != MCDisassembler::Fail) {
     793          17 :       Size = 4;
     794          17 :       Check(Result, AddThumbPredicate(MI));
     795             :       return Result;
     796             :     }
     797             :   }
     798             : 
     799        1898 :   if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
     800             :     uint32_t NEONLdStInsn = Insn32;
     801         499 :     NEONLdStInsn &= 0xF0FFFFFF;
     802         499 :     NEONLdStInsn |= 0x04000000;
     803         499 :     Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
     804             :                                Address, this, STI);
     805         499 :     if (Result != MCDisassembler::Fail) {
     806         449 :       Size = 4;
     807         449 :       Check(Result, AddThumbPredicate(MI));
     808             :       return Result;
     809             :     }
     810             :   }
     811             : 
     812        1449 :   if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
     813             :     uint32_t NEONDataInsn = Insn32;
     814        1046 :     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
     815        1046 :     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     816        1046 :     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
     817        1046 :     Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
     818             :                                Address, this, STI);
     819        1046 :     if (Result != MCDisassembler::Fail) {
     820         794 :       Size = 4;
     821         794 :       Check(Result, AddThumbPredicate(MI));
     822             :       return Result;
     823             :     }
     824             : 
     825             :     uint32_t NEONCryptoInsn = Insn32;
     826             :     NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
     827             :     NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     828             :     NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
     829         252 :     Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
     830             :                                Address, this, STI);
     831         252 :     if (Result != MCDisassembler::Fail) {
     832          14 :       Size = 4;
     833          14 :       return Result;
     834             :     }
     835             : 
     836             :     uint32_t NEONv8Insn = Insn32;
     837         238 :     NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
     838         238 :     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
     839             :                                this, STI);
     840         238 :     if (Result != MCDisassembler::Fail) {
     841          64 :       Size = 4;
     842          64 :       return Result;
     843             :     }
     844             :   }
     845             : 
     846             :   Result =
     847         577 :       decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
     848         577 :   if (Result != MCDisassembler::Fail) {
     849          62 :     Size = 4;
     850          62 :     Check(Result, AddThumbPredicate(MI));
     851             :     return Result;
     852             :   }
     853             : 
     854         515 :   Size = 0;
     855         515 :   return MCDisassembler::Fail;
     856             : }
     857             : 
     858       13834 : extern "C" void LLVMInitializeARMDisassembler() {
     859       13834 :   TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
     860             :                                          createARMDisassembler);
     861       13834 :   TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
     862             :                                          createARMDisassembler);
     863       13834 :   TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
     864             :                                          createThumbDisassembler);
     865       13834 :   TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
     866             :                                          createThumbDisassembler);
     867       13834 : }
     868             : 
     869             : static const uint16_t GPRDecoderTable[] = {
     870             :   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
     871             :   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
     872             :   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
     873             :   ARM::R12, ARM::SP, ARM::LR, ARM::PC
     874             : };
     875             : 
     876       35791 : static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     877             :                                    uint64_t Address, const void *Decoder) {
     878       35791 :   if (RegNo > 15)
     879             :     return MCDisassembler::Fail;
     880             : 
     881       35791 :   unsigned Register = GPRDecoderTable[RegNo];
     882       71582 :   Inst.addOperand(MCOperand::createReg(Register));
     883             :   return MCDisassembler::Success;
     884             : }
     885             : 
     886             : static DecodeStatus
     887        2226 : DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
     888             :                            uint64_t Address, const void *Decoder) {
     889             :   DecodeStatus S = MCDisassembler::Success;
     890             : 
     891        2226 :   if (RegNo == 15) 
     892             :     S = MCDisassembler::SoftFail;
     893             : 
     894        2226 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     895             : 
     896        2226 :   return S;
     897             : }
     898             : 
     899             : static DecodeStatus
     900          47 : DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
     901             :                                uint64_t Address, const void *Decoder) {
     902             :   DecodeStatus S = MCDisassembler::Success;
     903             : 
     904          47 :   if (RegNo == 15)
     905             :   {
     906          18 :     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
     907             :     return MCDisassembler::Success;
     908             :   }
     909             : 
     910          38 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     911             :   return S;
     912             : }
     913             : 
     914             : static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     915             :                                    uint64_t Address, const void *Decoder) {
     916             :   if (RegNo > 7)
     917             :     return MCDisassembler::Fail;
     918        9284 :   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
     919             : }
     920             : 
     921             : static const uint16_t GPRPairDecoderTable[] = {
     922             :   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
     923             :   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
     924             : };
     925             : 
     926          15 : static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
     927             :                                    uint64_t Address, const void *Decoder) {
     928             :   DecodeStatus S = MCDisassembler::Success;
     929             : 
     930          15 :   if (RegNo > 13)
     931             :     return MCDisassembler::Fail;
     932             : 
     933          15 :   if ((RegNo & 1) || RegNo == 0xe)
     934             :      S = MCDisassembler::SoftFail;
     935             : 
     936          15 :   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
     937          30 :   Inst.addOperand(MCOperand::createReg(RegisterPair));
     938             :   return S;
     939             : }
     940             : 
     941           1 : static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     942             :                                    uint64_t Address, const void *Decoder) {
     943             :   unsigned Register = 0;
     944           1 :   switch (RegNo) {
     945             :     case 0:
     946             :       Register = ARM::R0;
     947             :       break;
     948           0 :     case 1:
     949             :       Register = ARM::R1;
     950             :       break;
     951           0 :     case 2:
     952             :       Register = ARM::R2;
     953             :       break;
     954           0 :     case 3:
     955             :       Register = ARM::R3;
     956             :       break;
     957           0 :     case 9:
     958             :       Register = ARM::R9;
     959             :       break;
     960           0 :     case 12:
     961             :       Register = ARM::R12;
     962             :       break;
     963             :     default:
     964             :       return MCDisassembler::Fail;
     965             :     }
     966             : 
     967           0 :   Inst.addOperand(MCOperand::createReg(Register));
     968             :   return MCDisassembler::Success;
     969             : }
     970             : 
     971        2245 : static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     972             :                                    uint64_t Address, const void *Decoder) {
     973             :   DecodeStatus S = MCDisassembler::Success;
     974             : 
     975             :   const FeatureBitset &featureBits =
     976        2245 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
     977             : 
     978        2256 :   if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
     979             :     S = MCDisassembler::SoftFail;
     980             : 
     981        2245 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     982        2245 :   return S;
     983             : }
     984             : 
     985             : static const uint16_t SPRDecoderTable[] = {
     986             :      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
     987             :      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
     988             :      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
     989             :     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
     990             :     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
     991             :     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
     992             :     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
     993             :     ARM::S28, ARM::S29, ARM::S30, ARM::S31
     994             : };
     995             : 
     996         704 : static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
     997             :                                    uint64_t Address, const void *Decoder) {
     998         704 :   if (RegNo > 31)
     999             :     return MCDisassembler::Fail;
    1000             : 
    1001         704 :   unsigned Register = SPRDecoderTable[RegNo];
    1002        1408 :   Inst.addOperand(MCOperand::createReg(Register));
    1003             :   return MCDisassembler::Success;
    1004             : }
    1005             : 
    1006             : static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1007             :                                    uint64_t Address, const void *Decoder) {
    1008         212 :   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
    1009             : }
    1010             : 
    1011             : static const uint16_t DPRDecoderTable[] = {
    1012             :      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
    1013             :      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
    1014             :      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
    1015             :     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
    1016             :     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
    1017             :     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
    1018             :     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
    1019             :     ARM::D28, ARM::D29, ARM::D30, ARM::D31
    1020             : };
    1021             : 
    1022        4548 : static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1023             :                                    uint64_t Address, const void *Decoder) {
    1024             :   const FeatureBitset &featureBits =
    1025        4548 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    1026             : 
    1027             :   bool hasD16 = featureBits[ARM::FeatureD16];
    1028             : 
    1029        4548 :   if (RegNo > 31 || (hasD16 && RegNo > 15))
    1030             :     return MCDisassembler::Fail;
    1031             : 
    1032        4548 :   unsigned Register = DPRDecoderTable[RegNo];
    1033        9096 :   Inst.addOperand(MCOperand::createReg(Register));
    1034        4548 :   return MCDisassembler::Success;
    1035             : }
    1036             : 
    1037             : static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
    1038             :                                    uint64_t Address, const void *Decoder) {
    1039             :   if (RegNo > 7)
    1040             :     return MCDisassembler::Fail;
    1041          18 :   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
    1042             : }
    1043             : 
    1044             : static DecodeStatus
    1045             : DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
    1046             :                             uint64_t Address, const void *Decoder) {
    1047             :   if (RegNo > 15)
    1048             :     return MCDisassembler::Fail;
    1049          21 :   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
    1050             : }
    1051             : 
    1052             : static const uint16_t QPRDecoderTable[] = {
    1053             :      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
    1054             :      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
    1055             :      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
    1056             :     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
    1057             : };
    1058             : 
    1059        2438 : static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1060             :                                    uint64_t Address, const void *Decoder) {
    1061        2438 :   if (RegNo > 31 || (RegNo & 1) != 0)
    1062             :     return MCDisassembler::Fail;
    1063        2430 :   RegNo >>= 1;
    1064             : 
    1065        2430 :   unsigned Register = QPRDecoderTable[RegNo];
    1066        4860 :   Inst.addOperand(MCOperand::createReg(Register));
    1067        2430 :   return MCDisassembler::Success;
    1068             : }
    1069             : 
    1070             : static const uint16_t DPairDecoderTable[] = {
    1071             :   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
    1072             :   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
    1073             :   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
    1074             :   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
    1075             :   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
    1076             :   ARM::Q15
    1077             : };
    1078             : 
    1079         209 : static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
    1080             :                                    uint64_t Address, const void *Decoder) {
    1081         209 :   if (RegNo > 30)
    1082             :     return MCDisassembler::Fail;
    1083             : 
    1084         209 :   unsigned Register = DPairDecoderTable[RegNo];
    1085         418 :   Inst.addOperand(MCOperand::createReg(Register));
    1086             :   return MCDisassembler::Success;
    1087             : }
    1088             : 
    1089             : static const uint16_t DPairSpacedDecoderTable[] = {
    1090             :   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
    1091             :   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
    1092             :   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
    1093             :   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
    1094             :   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
    1095             :   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
    1096             :   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
    1097             :   ARM::D28_D30, ARM::D29_D31
    1098             : };
    1099             : 
    1100          61 : static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
    1101             :                                                    unsigned RegNo,
    1102             :                                                    uint64_t Address,
    1103             :                                                    const void *Decoder) {
    1104          61 :   if (RegNo > 29)
    1105             :     return MCDisassembler::Fail;
    1106             : 
    1107          61 :   unsigned Register = DPairSpacedDecoderTable[RegNo];
    1108         122 :   Inst.addOperand(MCOperand::createReg(Register));
    1109             :   return MCDisassembler::Success;
    1110             : }
    1111             : 
    1112        8218 : static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
    1113             :                                uint64_t Address, const void *Decoder) {
    1114        8218 :   if (Val == 0xF) return MCDisassembler::Fail;
    1115             :   // AL predicate is not allowed on Thumb1 branches.
    1116        6985 :   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
    1117             :     return MCDisassembler::Fail;
    1118       20955 :   Inst.addOperand(MCOperand::createImm(Val));
    1119        6985 :   if (Val == ARMCC::AL) {
    1120       12636 :     Inst.addOperand(MCOperand::createReg(0));
    1121             :   } else
    1122        1334 :     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    1123             :   return MCDisassembler::Success;
    1124             : }
    1125             : 
    1126        1805 : static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
    1127             :                                uint64_t Address, const void *Decoder) {
    1128        1805 :   if (Val)
    1129         412 :     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    1130             :   else
    1131        3198 :     Inst.addOperand(MCOperand::createReg(0));
    1132        1805 :   return MCDisassembler::Success;
    1133             : }
    1134             : 
    1135         276 : static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
    1136             :                                uint64_t Address, const void *Decoder) {
    1137             :   DecodeStatus S = MCDisassembler::Success;
    1138             : 
    1139             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    1140             :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1141             :   unsigned imm = fieldFromInstruction(Val, 7, 5);
    1142             : 
    1143             :   // Register-immediate
    1144         552 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1145             :     return MCDisassembler::Fail;
    1146             : 
    1147             :   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
    1148             :   switch (type) {
    1149             :     case 0:
    1150             :       Shift = ARM_AM::lsl;
    1151             :       break;
    1152             :     case 1:
    1153             :       Shift = ARM_AM::lsr;
    1154             :       break;
    1155             :     case 2:
    1156             :       Shift = ARM_AM::asr;
    1157             :       break;
    1158             :     case 3:
    1159             :       Shift = ARM_AM::ror;
    1160             :       break;
    1161             :   }
    1162             : 
    1163         276 :   if (Shift == ARM_AM::ror && imm == 0)
    1164             :     Shift = ARM_AM::rrx;
    1165             : 
    1166         276 :   unsigned Op = Shift | (imm << 3);
    1167         828 :   Inst.addOperand(MCOperand::createImm(Op));
    1168             : 
    1169             :   return S;
    1170             : }
    1171             : 
    1172         125 : static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
    1173             :                                uint64_t Address, const void *Decoder) {
    1174             :   DecodeStatus S = MCDisassembler::Success;
    1175             : 
    1176             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    1177             :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1178             :   unsigned Rs = fieldFromInstruction(Val, 8, 4);
    1179             : 
    1180             :   // Register-register
    1181         250 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1182             :     return MCDisassembler::Fail;
    1183         250 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
    1184             :     return MCDisassembler::Fail;
    1185             : 
    1186             :   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
    1187             :   switch (type) {
    1188             :     case 0:
    1189             :       Shift = ARM_AM::lsl;
    1190             :       break;
    1191             :     case 1:
    1192             :       Shift = ARM_AM::lsr;
    1193             :       break;
    1194             :     case 2:
    1195             :       Shift = ARM_AM::asr;
    1196             :       break;
    1197             :     case 3:
    1198             :       Shift = ARM_AM::ror;
    1199             :       break;
    1200             :   }
    1201             : 
    1202         375 :   Inst.addOperand(MCOperand::createImm(Shift));
    1203             : 
    1204             :   return S;
    1205             : }
    1206             : 
    1207        1069 : static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
    1208             :                                  uint64_t Address, const void *Decoder) {
    1209             :   DecodeStatus S = MCDisassembler::Success;
    1210             : 
    1211             :   bool NeedDisjointWriteback = false;
    1212             :   unsigned WritebackReg = 0;
    1213        1069 :   switch (Inst.getOpcode()) {
    1214             :   default:
    1215             :     break;
    1216         159 :   case ARM::LDMIA_UPD:
    1217             :   case ARM::LDMDB_UPD:
    1218             :   case ARM::LDMIB_UPD:
    1219             :   case ARM::LDMDA_UPD:
    1220             :   case ARM::t2LDMIA_UPD:
    1221             :   case ARM::t2LDMDB_UPD:
    1222             :   case ARM::t2STMIA_UPD:
    1223             :   case ARM::t2STMDB_UPD:
    1224             :     NeedDisjointWriteback = true;
    1225         159 :     WritebackReg = Inst.getOperand(0).getReg();
    1226             :     break;
    1227             :   }
    1228             : 
    1229             :   // Empty register lists are not allowed.
    1230        1069 :   if (Val == 0) return MCDisassembler::Fail;
    1231       34617 :   for (unsigned i = 0; i < 16; ++i) {
    1232       16784 :     if (Val & (1 << i)) {
    1233        7092 :       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
    1234             :         return MCDisassembler::Fail;
    1235             :       // Writeback not allowed if Rn is in the target list.
    1236        4110 :       if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
    1237             :         Check(S, MCDisassembler::SoftFail);
    1238             :     }
    1239             :   }
    1240             : 
    1241             :   return S;
    1242             : }
    1243             : 
    1244          10 : static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
    1245             :                                  uint64_t Address, const void *Decoder) {
    1246             :   DecodeStatus S = MCDisassembler::Success;
    1247             : 
    1248             :   unsigned Vd = fieldFromInstruction(Val, 8, 5);
    1249          10 :   unsigned regs = fieldFromInstruction(Val, 0, 8);
    1250             : 
    1251             :   // In case of unpredictable encoding, tweak the operands.
    1252          10 :   if (regs == 0 || (Vd + regs) > 32) {
    1253           1 :     regs = Vd + regs > 32 ? 32 - Vd : regs;
    1254           2 :     regs = std::max( 1u, regs);
    1255             :     S = MCDisassembler::SoftFail;
    1256             :   }
    1257             : 
    1258          20 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
    1259             :     return MCDisassembler::Fail;
    1260          92 :   for (unsigned i = 0; i < (regs - 1); ++i) {
    1261          82 :     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
    1262             :       return MCDisassembler::Fail;
    1263             :   }
    1264             : 
    1265             :   return S;
    1266             : }
    1267             : 
    1268          20 : static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
    1269             :                                  uint64_t Address, const void *Decoder) {
    1270             :   DecodeStatus S = MCDisassembler::Success;
    1271             : 
    1272             :   unsigned Vd = fieldFromInstruction(Val, 8, 5);
    1273          20 :   unsigned regs = fieldFromInstruction(Val, 1, 7);
    1274             : 
    1275             :   // In case of unpredictable encoding, tweak the operands.
    1276          20 :   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
    1277           2 :     regs = Vd + regs > 32 ? 32 - Vd : regs;
    1278           4 :     regs = std::max( 1u, regs);
    1279           4 :     regs = std::min(16u, regs);
    1280             :     S = MCDisassembler::SoftFail;
    1281             :   }
    1282             : 
    1283          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
    1284             :       return MCDisassembler::Fail;
    1285         164 :   for (unsigned i = 0; i < (regs - 1); ++i) {
    1286         144 :     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
    1287             :       return MCDisassembler::Fail;
    1288             :   }
    1289             : 
    1290             :   return S;
    1291             : }
    1292             : 
    1293          54 : static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
    1294             :                                       uint64_t Address, const void *Decoder) {
    1295             :   // This operand encodes a mask of contiguous zeros between a specified MSB
    1296             :   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
    1297             :   // the mask of all bits LSB-and-lower, and then xor them to create
    1298             :   // the mask of that's all ones on [msb, lsb].  Finally we not it to
    1299             :   // create the final mask.
    1300             :   unsigned msb = fieldFromInstruction(Val, 5, 5);
    1301             :   unsigned lsb = fieldFromInstruction(Val, 0, 5);
    1302             : 
    1303             :   DecodeStatus S = MCDisassembler::Success;
    1304          54 :   if (lsb > msb) {
    1305             :     Check(S, MCDisassembler::SoftFail);
    1306             :     // The check above will cause the warning for the "potentially undefined
    1307             :     // instruction encoding" but we can't build a bad MCOperand value here
    1308             :     // with a lsb > msb or else printing the MCInst will cause a crash.
    1309             :     lsb = msb;
    1310             :   }
    1311             : 
    1312             :   uint32_t msb_mask = 0xFFFFFFFF;
    1313          54 :   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
    1314          54 :   uint32_t lsb_mask = (1U << lsb) - 1;
    1315             : 
    1316         162 :   Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
    1317          54 :   return S;
    1318             : }
    1319             : 
    1320         109 : static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
    1321             :                                   uint64_t Address, const void *Decoder) {
    1322             :   DecodeStatus S = MCDisassembler::Success;
    1323             : 
    1324             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1325             :   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
    1326             :   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
    1327             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    1328             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1329             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    1330             : 
    1331         109 :   switch (Inst.getOpcode()) {
    1332          85 :     case ARM::LDC_OFFSET:
    1333             :     case ARM::LDC_PRE:
    1334             :     case ARM::LDC_POST:
    1335             :     case ARM::LDC_OPTION:
    1336             :     case ARM::LDCL_OFFSET:
    1337             :     case ARM::LDCL_PRE:
    1338             :     case ARM::LDCL_POST:
    1339             :     case ARM::LDCL_OPTION:
    1340             :     case ARM::STC_OFFSET:
    1341             :     case ARM::STC_PRE:
    1342             :     case ARM::STC_POST:
    1343             :     case ARM::STC_OPTION:
    1344             :     case ARM::STCL_OFFSET:
    1345             :     case ARM::STCL_PRE:
    1346             :     case ARM::STCL_POST:
    1347             :     case ARM::STCL_OPTION:
    1348             :     case ARM::t2LDC_OFFSET:
    1349             :     case ARM::t2LDC_PRE:
    1350             :     case ARM::t2LDC_POST:
    1351             :     case ARM::t2LDC_OPTION:
    1352             :     case ARM::t2LDCL_OFFSET:
    1353             :     case ARM::t2LDCL_PRE:
    1354             :     case ARM::t2LDCL_POST:
    1355             :     case ARM::t2LDCL_OPTION:
    1356             :     case ARM::t2STC_OFFSET:
    1357             :     case ARM::t2STC_PRE:
    1358             :     case ARM::t2STC_POST:
    1359             :     case ARM::t2STC_OPTION:
    1360             :     case ARM::t2STCL_OFFSET:
    1361             :     case ARM::t2STCL_PRE:
    1362             :     case ARM::t2STCL_POST:
    1363             :     case ARM::t2STCL_OPTION:
    1364          85 :       if (coproc == 0xA || coproc == 0xB)
    1365             :         return MCDisassembler::Fail;
    1366             :       break;
    1367             :     default:
    1368             :       break;
    1369             :   }
    1370             : 
    1371             :   const FeatureBitset &featureBits =
    1372         109 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    1373         109 :   if (featureBits[ARM::HasV8Ops] && (coproc != 14))
    1374             :     return MCDisassembler::Fail;
    1375             : 
    1376         159 :   Inst.addOperand(MCOperand::createImm(coproc));
    1377         159 :   Inst.addOperand(MCOperand::createImm(CRd));
    1378         106 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1379             :     return MCDisassembler::Fail;
    1380             : 
    1381          53 :   switch (Inst.getOpcode()) {
    1382           6 :     case ARM::t2LDC2_OFFSET:
    1383             :     case ARM::t2LDC2L_OFFSET:
    1384             :     case ARM::t2LDC2_PRE:
    1385             :     case ARM::t2LDC2L_PRE:
    1386             :     case ARM::t2STC2_OFFSET:
    1387             :     case ARM::t2STC2L_OFFSET:
    1388             :     case ARM::t2STC2_PRE:
    1389             :     case ARM::t2STC2L_PRE:
    1390             :     case ARM::LDC2_OFFSET:
    1391             :     case ARM::LDC2L_OFFSET:
    1392             :     case ARM::LDC2_PRE:
    1393             :     case ARM::LDC2L_PRE:
    1394             :     case ARM::STC2_OFFSET:
    1395             :     case ARM::STC2L_OFFSET:
    1396             :     case ARM::STC2_PRE:
    1397             :     case ARM::STC2L_PRE:
    1398             :     case ARM::t2LDC_OFFSET:
    1399             :     case ARM::t2LDCL_OFFSET:
    1400             :     case ARM::t2LDC_PRE:
    1401             :     case ARM::t2LDCL_PRE:
    1402             :     case ARM::t2STC_OFFSET:
    1403             :     case ARM::t2STCL_OFFSET:
    1404             :     case ARM::t2STC_PRE:
    1405             :     case ARM::t2STCL_PRE:
    1406             :     case ARM::LDC_OFFSET:
    1407             :     case ARM::LDCL_OFFSET:
    1408             :     case ARM::LDC_PRE:
    1409             :     case ARM::LDCL_PRE:
    1410             :     case ARM::STC_OFFSET:
    1411             :     case ARM::STCL_OFFSET:
    1412             :     case ARM::STC_PRE:
    1413             :     case ARM::STCL_PRE:
    1414           6 :       imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
    1415          18 :       Inst.addOperand(MCOperand::createImm(imm));
    1416             :       break;
    1417          14 :     case ARM::t2LDC2_POST:
    1418             :     case ARM::t2LDC2L_POST:
    1419             :     case ARM::t2STC2_POST:
    1420             :     case ARM::t2STC2L_POST:
    1421             :     case ARM::LDC2_POST:
    1422             :     case ARM::LDC2L_POST:
    1423             :     case ARM::STC2_POST:
    1424             :     case ARM::STC2L_POST:
    1425             :     case ARM::t2LDC_POST:
    1426             :     case ARM::t2LDCL_POST:
    1427             :     case ARM::t2STC_POST:
    1428             :     case ARM::t2STCL_POST:
    1429             :     case ARM::LDC_POST:
    1430             :     case ARM::LDCL_POST:
    1431             :     case ARM::STC_POST:
    1432             :     case ARM::STCL_POST:
    1433          14 :       imm |= U << 8;
    1434             :       LLVM_FALLTHROUGH;
    1435          47 :     default:
    1436             :       // The 'option' variant doesn't encode 'U' in the immediate since
    1437             :       // the immediate is unsigned [0,255].
    1438         141 :       Inst.addOperand(MCOperand::createImm(imm));
    1439             :       break;
    1440             :   }
    1441             : 
    1442          53 :   switch (Inst.getOpcode()) {
    1443          23 :     case ARM::LDC_OFFSET:
    1444             :     case ARM::LDC_PRE:
    1445             :     case ARM::LDC_POST:
    1446             :     case ARM::LDC_OPTION:
    1447             :     case ARM::LDCL_OFFSET:
    1448             :     case ARM::LDCL_PRE:
    1449             :     case ARM::LDCL_POST:
    1450             :     case ARM::LDCL_OPTION:
    1451             :     case ARM::STC_OFFSET:
    1452             :     case ARM::STC_PRE:
    1453             :     case ARM::STC_POST:
    1454             :     case ARM::STC_OPTION:
    1455             :     case ARM::STCL_OFFSET:
    1456             :     case ARM::STCL_PRE:
    1457             :     case ARM::STCL_POST:
    1458             :     case ARM::STCL_OPTION:
    1459          46 :       if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1460             :         return MCDisassembler::Fail;
    1461             :       break;
    1462             :     default:
    1463             :       break;
    1464             :   }
    1465             : 
    1466             :   return S;
    1467             : }
    1468             : 
    1469             : static DecodeStatus
    1470        1919 : DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
    1471             :                               uint64_t Address, const void *Decoder) {
    1472             :   DecodeStatus S = MCDisassembler::Success;
    1473             : 
    1474             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1475             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    1476             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1477             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    1478             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1479             :   unsigned reg = fieldFromInstruction(Insn, 25, 1);
    1480             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    1481             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    1482             : 
    1483             :   // On stores, the writeback operand precedes Rt.
    1484        1919 :   switch (Inst.getOpcode()) {
    1485        1161 :     case ARM::STR_POST_IMM:
    1486             :     case ARM::STR_POST_REG:
    1487             :     case ARM::STRB_POST_IMM:
    1488             :     case ARM::STRB_POST_REG:
    1489             :     case ARM::STRT_POST_REG:
    1490             :     case ARM::STRT_POST_IMM:
    1491             :     case ARM::STRBT_POST_REG:
    1492             :     case ARM::STRBT_POST_IMM:
    1493        2322 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1494             :         return MCDisassembler::Fail;
    1495             :       break;
    1496             :     default:
    1497             :       break;
    1498             :   }
    1499             : 
    1500        3838 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    1501             :     return MCDisassembler::Fail;
    1502             : 
    1503             :   // On loads, the writeback operand comes after Rt.
    1504        1919 :   switch (Inst.getOpcode()) {
    1505         758 :     case ARM::LDR_POST_IMM:
    1506             :     case ARM::LDR_POST_REG:
    1507             :     case ARM::LDRB_POST_IMM:
    1508             :     case ARM::LDRB_POST_REG:
    1509             :     case ARM::LDRBT_POST_REG:
    1510             :     case ARM::LDRBT_POST_IMM:
    1511             :     case ARM::LDRT_POST_REG:
    1512             :     case ARM::LDRT_POST_IMM:
    1513        1516 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1514             :         return MCDisassembler::Fail;
    1515             :       break;
    1516             :     default:
    1517             :       break;
    1518             :   }
    1519             : 
    1520        3838 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1521             :     return MCDisassembler::Fail;
    1522             : 
    1523             :   ARM_AM::AddrOpc Op = ARM_AM::add;
    1524        1919 :   if (!fieldFromInstruction(Insn, 23, 1))
    1525             :     Op = ARM_AM::sub;
    1526             : 
    1527        1919 :   bool writeback = (P == 0) || (W == 1);
    1528             :   unsigned idx_mode = 0;
    1529        1919 :   if (P && writeback)
    1530             :     idx_mode = ARMII::IndexModePre;
    1531        1919 :   else if (!P && writeback)
    1532             :     idx_mode = ARMII::IndexModePost;
    1533             : 
    1534        1919 :   if (writeback && (Rn == 15 || Rn == Rt))
    1535             :     S = MCDisassembler::SoftFail; // UNPREDICTABLE
    1536             : 
    1537        1919 :   if (reg) {
    1538          42 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1539             :       return MCDisassembler::Fail;
    1540             :     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
    1541          21 :     switch( fieldFromInstruction(Insn, 5, 2)) {
    1542             :       case 0:
    1543             :         Opc = ARM_AM::lsl;
    1544             :         break;
    1545           2 :       case 1:
    1546             :         Opc = ARM_AM::lsr;
    1547             :         break;
    1548           4 :       case 2:
    1549             :         Opc = ARM_AM::asr;
    1550             :         break;
    1551           0 :       case 3:
    1552             :         Opc = ARM_AM::ror;
    1553             :         break;
    1554             :       default:
    1555             :         return MCDisassembler::Fail;
    1556             :     }
    1557             :     unsigned amt = fieldFromInstruction(Insn, 7, 5);
    1558          21 :     if (Opc == ARM_AM::ror && amt == 0)
    1559             :       Opc = ARM_AM::rrx;
    1560             :     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
    1561             : 
    1562          63 :     Inst.addOperand(MCOperand::createImm(imm));
    1563             :   } else {
    1564        3796 :     Inst.addOperand(MCOperand::createReg(0));
    1565             :     unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
    1566        5694 :     Inst.addOperand(MCOperand::createImm(tmp));
    1567             :   }
    1568             : 
    1569        3838 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1570             :     return MCDisassembler::Fail;
    1571             : 
    1572             :   return S;
    1573             : }
    1574             : 
    1575          33 : static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
    1576             :                                   uint64_t Address, const void *Decoder) {
    1577             :   DecodeStatus S = MCDisassembler::Success;
    1578             : 
    1579             :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    1580             :   unsigned Rm = fieldFromInstruction(Val,  0, 4);
    1581             :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1582             :   unsigned imm = fieldFromInstruction(Val, 7, 5);
    1583             :   unsigned U = fieldFromInstruction(Val, 12, 1);
    1584             : 
    1585             :   ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
    1586             :   switch (type) {
    1587             :     case 0:
    1588             :       ShOp = ARM_AM::lsl;
    1589             :       break;
    1590             :     case 1:
    1591             :       ShOp = ARM_AM::lsr;
    1592             :       break;
    1593             :     case 2:
    1594             :       ShOp = ARM_AM::asr;
    1595             :       break;
    1596             :     case 3:
    1597             :       ShOp = ARM_AM::ror;
    1598             :       break;
    1599             :   }
    1600             : 
    1601          33 :   if (ShOp == ARM_AM::ror && imm == 0)
    1602             :     ShOp = ARM_AM::rrx;
    1603             : 
    1604          66 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1605             :     return MCDisassembler::Fail;
    1606          66 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1607             :     return MCDisassembler::Fail;
    1608             :   unsigned shift;
    1609          33 :   if (U)
    1610             :     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
    1611             :   else
    1612             :     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
    1613          99 :   Inst.addOperand(MCOperand::createImm(shift));
    1614             : 
    1615             :   return S;
    1616             : }
    1617             : 
    1618             : static DecodeStatus
    1619         409 : DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
    1620             :                            uint64_t Address, const void *Decoder) {
    1621             :   DecodeStatus S = MCDisassembler::Success;
    1622             : 
    1623             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    1624             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1625             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1626             :   unsigned type = fieldFromInstruction(Insn, 22, 1);
    1627             :   unsigned imm = fieldFromInstruction(Insn, 8, 4);
    1628         409 :   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
    1629             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1630             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    1631             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    1632         409 :   unsigned Rt2 = Rt + 1;
    1633             : 
    1634         409 :   bool writeback = (W == 1) | (P == 0);
    1635             : 
    1636             :   // For {LD,ST}RD, Rt must be even, else undefined.
    1637         409 :   switch (Inst.getOpcode()) {
    1638          31 :     case ARM::STRD:
    1639             :     case ARM::STRD_PRE:
    1640             :     case ARM::STRD_POST:
    1641             :     case ARM::LDRD:
    1642             :     case ARM::LDRD_PRE:
    1643             :     case ARM::LDRD_POST:
    1644          31 :       if (Rt & 0x1) S = MCDisassembler::SoftFail;
    1645             :       break;
    1646             :     default:
    1647             :       break;
    1648             :   }
    1649         409 :   switch (Inst.getOpcode()) {
    1650          14 :     case ARM::STRD:
    1651             :     case ARM::STRD_PRE:
    1652             :     case ARM::STRD_POST:
    1653          14 :       if (P == 0 && W == 1)
    1654             :         S = MCDisassembler::SoftFail;
    1655             : 
    1656          14 :       if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
    1657             :         S = MCDisassembler::SoftFail;
    1658          14 :       if (type && Rm == 15)
    1659             :         S = MCDisassembler::SoftFail;
    1660          14 :       if (Rt2 == 15)
    1661             :         S = MCDisassembler::SoftFail;
    1662          14 :       if (!type && fieldFromInstruction(Insn, 8, 4))
    1663             :         S = MCDisassembler::SoftFail;
    1664             :       break;
    1665         177 :     case ARM::STRH:
    1666             :     case ARM::STRH_PRE:
    1667             :     case ARM::STRH_POST:
    1668         177 :       if (Rt == 15)
    1669             :         S = MCDisassembler::SoftFail;
    1670         177 :       if (writeback && (Rn == 15 || Rn == Rt))
    1671             :         S = MCDisassembler::SoftFail;
    1672         177 :       if (!type && Rm == 15)
    1673             :         S = MCDisassembler::SoftFail;
    1674             :       break;
    1675          17 :     case ARM::LDRD:
    1676             :     case ARM::LDRD_PRE:
    1677             :     case ARM::LDRD_POST:
    1678          17 :       if (type && Rn == 15) {
    1679           1 :         if (Rt2 == 15)
    1680             :           S = MCDisassembler::SoftFail;
    1681             :         break;
    1682             :       }
    1683          16 :       if (P == 0 && W == 1)
    1684             :         S = MCDisassembler::SoftFail;
    1685          16 :       if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
    1686             :         S = MCDisassembler::SoftFail;
    1687          16 :       if (!type && writeback && Rn == 15)
    1688             :         S = MCDisassembler::SoftFail;
    1689          16 :       if (writeback && (Rn == Rt || Rn == Rt2))
    1690             :         S = MCDisassembler::SoftFail;
    1691             :       break;
    1692         178 :     case ARM::LDRH:
    1693             :     case ARM::LDRH_PRE:
    1694             :     case ARM::LDRH_POST:
    1695         178 :       if (type && Rn == 15) {
    1696           0 :         if (Rt == 15)
    1697             :           S = MCDisassembler::SoftFail;
    1698             :         break;
    1699             :       }
    1700         178 :       if (Rt == 15)
    1701             :         S = MCDisassembler::SoftFail;
    1702         178 :       if (!type && Rm == 15)
    1703             :         S = MCDisassembler::SoftFail;
    1704         178 :       if (!type && writeback && (Rn == 15 || Rn == Rt))
    1705             :         S = MCDisassembler::SoftFail;
    1706             :       break;
    1707          23 :     case ARM::LDRSH:
    1708             :     case ARM::LDRSH_PRE:
    1709             :     case ARM::LDRSH_POST:
    1710             :     case ARM::LDRSB:
    1711             :     case ARM::LDRSB_PRE:
    1712             :     case ARM::LDRSB_POST:
    1713          23 :       if (type && Rn == 15) {
    1714           3 :         if (Rt == 15)
    1715             :           S = MCDisassembler::SoftFail;
    1716             :         break;
    1717             :       }
    1718          20 :       if (type && (Rt == 15 || (writeback && Rn == Rt)))
    1719             :         S = MCDisassembler::SoftFail;
    1720          20 :       if (!type && (Rt == 15 || Rm == 15))
    1721             :         S = MCDisassembler::SoftFail;
    1722          20 :       if (!type && writeback && (Rn == 15 || Rn == Rt))
    1723             :         S = MCDisassembler::SoftFail;
    1724             :       break;
    1725             :     default:
    1726             :       break;
    1727             :   }
    1728             : 
    1729         409 :   if (writeback) { // Writeback
    1730         383 :     if (P)
    1731          22 :       U |= ARMII::IndexModePre << 9;
    1732             :     else
    1733         361 :       U |= ARMII::IndexModePost << 9;
    1734             : 
    1735             :     // On stores, the writeback operand precedes Rt.
    1736             :     switch (Inst.getOpcode()) {
    1737         183 :     case ARM::STRD:
    1738             :     case ARM::STRD_PRE:
    1739             :     case ARM::STRD_POST:
    1740             :     case ARM::STRH:
    1741             :     case ARM::STRH_PRE:
    1742             :     case ARM::STRH_POST:
    1743         366 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1744             :         return MCDisassembler::Fail;
    1745             :       break;
    1746             :     default:
    1747             :       break;
    1748             :     }
    1749             :   }
    1750             : 
    1751         818 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    1752             :     return MCDisassembler::Fail;
    1753         409 :   switch (Inst.getOpcode()) {
    1754          31 :     case ARM::STRD:
    1755             :     case ARM::STRD_PRE:
    1756             :     case ARM::STRD_POST:
    1757             :     case ARM::LDRD:
    1758             :     case ARM::LDRD_PRE:
    1759             :     case ARM::LDRD_POST:
    1760          62 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
    1761             :         return MCDisassembler::Fail;
    1762             :       break;
    1763             :     default:
    1764             :       break;
    1765             :   }
    1766             : 
    1767         409 :   if (writeback) {
    1768             :     // On loads, the writeback operand comes after Rt.
    1769         383 :     switch (Inst.getOpcode()) {
    1770         200 :     case ARM::LDRD:
    1771             :     case ARM::LDRD_PRE:
    1772             :     case ARM::LDRD_POST:
    1773             :     case ARM::LDRH:
    1774             :     case ARM::LDRH_PRE:
    1775             :     case ARM::LDRH_POST:
    1776             :     case ARM::LDRSH:
    1777             :     case ARM::LDRSH_PRE:
    1778             :     case ARM::LDRSH_POST:
    1779             :     case ARM::LDRSB:
    1780             :     case ARM::LDRSB_PRE:
    1781             :     case ARM::LDRSB_POST:
    1782             :     case ARM::LDRHTr:
    1783             :     case ARM::LDRSBTr:
    1784         400 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1785             :         return MCDisassembler::Fail;
    1786             :       break;
    1787             :     default:
    1788             :       break;
    1789             :     }
    1790             :   }
    1791             : 
    1792         818 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1793             :     return MCDisassembler::Fail;
    1794             : 
    1795         409 :   if (type) {
    1796         748 :     Inst.addOperand(MCOperand::createReg(0));
    1797        1122 :     Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
    1798             :   } else {
    1799          70 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1800             :     return MCDisassembler::Fail;
    1801         105 :     Inst.addOperand(MCOperand::createImm(U));
    1802             :   }
    1803             : 
    1804         818 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1805             :     return MCDisassembler::Fail;
    1806             : 
    1807             :   return S;
    1808             : }
    1809             : 
    1810           1 : static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
    1811             :                                  uint64_t Address, const void *Decoder) {
    1812             :   DecodeStatus S = MCDisassembler::Success;
    1813             : 
    1814             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1815             :   unsigned mode = fieldFromInstruction(Insn, 23, 2);
    1816             : 
    1817           1 :   switch (mode) {
    1818           0 :     case 0:
    1819             :       mode = ARM_AM::da;
    1820             :       break;
    1821           0 :     case 1:
    1822             :       mode = ARM_AM::ia;
    1823             :       break;
    1824           1 :     case 2:
    1825             :       mode = ARM_AM::db;
    1826             :       break;
    1827           0 :     case 3:
    1828             :       mode = ARM_AM::ib;
    1829             :       break;
    1830             :   }
    1831             : 
    1832           3 :   Inst.addOperand(MCOperand::createImm(mode));
    1833           2 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1834             :     return MCDisassembler::Fail;
    1835             : 
    1836             :   return S;
    1837             : }
    1838             : 
    1839           2 : static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
    1840             :                                uint64_t Address, const void *Decoder) {
    1841             :   DecodeStatus S = MCDisassembler::Success;
    1842             : 
    1843             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    1844             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1845             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1846             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1847             : 
    1848           2 :   if (pred == 0xF)
    1849           0 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    1850             : 
    1851           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    1852             :     return MCDisassembler::Fail;
    1853           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1854             :     return MCDisassembler::Fail;
    1855           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    1856             :     return MCDisassembler::Fail;
    1857           4 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1858             :     return MCDisassembler::Fail;
    1859             :   return S;
    1860             : }
    1861             : 
    1862         277 : static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
    1863             :                                   unsigned Insn,
    1864             :                                   uint64_t Address, const void *Decoder) {
    1865             :   DecodeStatus S = MCDisassembler::Success;
    1866             : 
    1867             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1868             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1869             :   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
    1870             : 
    1871         277 :   if (pred == 0xF) {
    1872             :     // Ambiguous with RFE and SRS
    1873           7 :     switch (Inst.getOpcode()) {
    1874             :       case ARM::LDMDA:
    1875             :         Inst.setOpcode(ARM::RFEDA);
    1876             :         break;
    1877             :       case ARM::LDMDA_UPD:
    1878             :         Inst.setOpcode(ARM::RFEDA_UPD);
    1879             :         break;
    1880             :       case ARM::LDMDB:
    1881             :         Inst.setOpcode(ARM::RFEDB);
    1882             :         break;
    1883             :       case ARM::LDMDB_UPD:
    1884             :         Inst.setOpcode(ARM::RFEDB_UPD);
    1885             :         break;
    1886             :       case ARM::LDMIA:
    1887             :         Inst.setOpcode(ARM::RFEIA);
    1888             :         break;
    1889             :       case ARM::LDMIA_UPD:
    1890             :         Inst.setOpcode(ARM::RFEIA_UPD);
    1891             :         break;
    1892             :       case ARM::LDMIB:
    1893             :         Inst.setOpcode(ARM::RFEIB);
    1894             :         break;
    1895             :       case ARM::LDMIB_UPD:
    1896             :         Inst.setOpcode(ARM::RFEIB_UPD);
    1897             :         break;
    1898             :       case ARM::STMDA:
    1899             :         Inst.setOpcode(ARM::SRSDA);
    1900             :         break;
    1901             :       case ARM::STMDA_UPD:
    1902             :         Inst.setOpcode(ARM::SRSDA_UPD);
    1903             :         break;
    1904             :       case ARM::STMDB:
    1905             :         Inst.setOpcode(ARM::SRSDB);
    1906             :         break;
    1907             :       case ARM::STMDB_UPD:
    1908             :         Inst.setOpcode(ARM::SRSDB_UPD);
    1909             :         break;
    1910             :       case ARM::STMIA:
    1911             :         Inst.setOpcode(ARM::SRSIA);
    1912             :         break;
    1913             :       case ARM::STMIA_UPD:
    1914             :         Inst.setOpcode(ARM::SRSIA_UPD);
    1915             :         break;
    1916             :       case ARM::STMIB:
    1917             :         Inst.setOpcode(ARM::SRSIB);
    1918             :         break;
    1919             :       case ARM::STMIB_UPD:
    1920             :         Inst.setOpcode(ARM::SRSIB_UPD);
    1921             :         break;
    1922             :       default:
    1923             :         return MCDisassembler::Fail;
    1924             :     }
    1925             : 
    1926             :     // For stores (which become SRS's, the only operand is the mode.
    1927           4 :     if (fieldFromInstruction(Insn, 20, 1) == 0) {
    1928             :       // Check SRS encoding constraints
    1929           3 :       if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
    1930             :             fieldFromInstruction(Insn, 20, 1) == 0))
    1931             :         return MCDisassembler::Fail;
    1932             : 
    1933             :       Inst.addOperand(
    1934           0 :           MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
    1935             :       return S;
    1936             :     }
    1937             : 
    1938           1 :     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
    1939             :   }
    1940             : 
    1941         540 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1942             :     return MCDisassembler::Fail;
    1943         540 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1944             :     return MCDisassembler::Fail; // Tied
    1945         540 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1946             :     return MCDisassembler::Fail;
    1947         540 :   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
    1948             :     return MCDisassembler::Fail;
    1949             : 
    1950             :   return S;
    1951             : }
    1952             : 
    1953             : // Check for UNPREDICTABLE predicated ESB instruction
    1954          41 : static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
    1955             :                                  uint64_t Address, const void *Decoder) {
    1956             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1957             :   unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
    1958             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
    1959          41 :   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
    1960             : 
    1961             :   DecodeStatus S = MCDisassembler::Success;
    1962             : 
    1963         123 :   Inst.addOperand(MCOperand::createImm(imm8));
    1964             : 
    1965          82 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1966             :     return MCDisassembler::Fail;
    1967             : 
    1968             :   // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
    1969             :   // so all predicates should be allowed.
    1970          41 :   if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
    1971             :     S = MCDisassembler::SoftFail;
    1972             : 
    1973             :   return S;
    1974             : }
    1975             : 
    1976          15 : static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
    1977             :                                  uint64_t Address, const void *Decoder) {
    1978             :   unsigned imod = fieldFromInstruction(Insn, 18, 2);
    1979             :   unsigned M = fieldFromInstruction(Insn, 17, 1);
    1980             :   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
    1981             :   unsigned mode = fieldFromInstruction(Insn, 0, 5);
    1982             : 
    1983             :   DecodeStatus S = MCDisassembler::Success;
    1984             : 
    1985             :   // This decoder is called from multiple location that do not check
    1986             :   // the full encoding is valid before they do.
    1987          14 :   if (fieldFromInstruction(Insn, 5, 1) != 0 ||
    1988          29 :       fieldFromInstruction(Insn, 16, 1) != 0 ||
    1989             :       fieldFromInstruction(Insn, 20, 8) != 0x10)
    1990             :     return MCDisassembler::Fail;
    1991             : 
    1992             :   // imod == '01' --> UNPREDICTABLE
    1993             :   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
    1994             :   // return failure here.  The '01' imod value is unprintable, so there's
    1995             :   // nothing useful we could do even if we returned UNPREDICTABLE.
    1996             : 
    1997          10 :   if (imod == 1) return MCDisassembler::Fail;
    1998             : 
    1999           9 :   if (imod && M) {
    2000             :     Inst.setOpcode(ARM::CPS3p);
    2001          12 :     Inst.addOperand(MCOperand::createImm(imod));
    2002          12 :     Inst.addOperand(MCOperand::createImm(iflags));
    2003          12 :     Inst.addOperand(MCOperand::createImm(mode));
    2004           5 :   } else if (imod && !M) {
    2005             :     Inst.setOpcode(ARM::CPS2p);
    2006           6 :     Inst.addOperand(MCOperand::createImm(imod));
    2007           6 :     Inst.addOperand(MCOperand::createImm(iflags));
    2008           2 :     if (mode) S = MCDisassembler::SoftFail;
    2009           3 :   } else if (!imod && M) {
    2010             :     Inst.setOpcode(ARM::CPS1p);
    2011           9 :     Inst.addOperand(MCOperand::createImm(mode));
    2012           3 :     if (iflags) S = MCDisassembler::SoftFail;
    2013             :   } else {
    2014             :     // imod == '00' && M == '0' --> UNPREDICTABLE
    2015             :     Inst.setOpcode(ARM::CPS1p);
    2016           0 :     Inst.addOperand(MCOperand::createImm(mode));
    2017             :     S = MCDisassembler::SoftFail;
    2018             :   }
    2019             : 
    2020             :   return S;
    2021             : }
    2022             : 
    2023           3 : static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
    2024             :                                  uint64_t Address, const void *Decoder) {
    2025             :   unsigned imod = fieldFromInstruction(Insn, 9, 2);
    2026             :   unsigned M = fieldFromInstruction(Insn, 8, 1);
    2027             :   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
    2028             :   unsigned mode = fieldFromInstruction(Insn, 0, 5);
    2029             : 
    2030             :   DecodeStatus S = MCDisassembler::Success;
    2031             : 
    2032             :   // imod == '01' --> UNPREDICTABLE
    2033             :   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
    2034             :   // return failure here.  The '01' imod value is unprintable, so there's
    2035             :   // nothing useful we could do even if we returned UNPREDICTABLE.
    2036             : 
    2037           3 :   if (imod == 1) return MCDisassembler::Fail;
    2038             : 
    2039           3 :   if (imod && M) {
    2040             :     Inst.setOpcode(ARM::t2CPS3p);
    2041           3 :     Inst.addOperand(MCOperand::createImm(imod));
    2042           3 :     Inst.addOperand(MCOperand::createImm(iflags));
    2043           3 :     Inst.addOperand(MCOperand::createImm(mode));
    2044           2 :   } else if (imod && !M) {
    2045             :     Inst.setOpcode(ARM::t2CPS2p);
    2046           3 :     Inst.addOperand(MCOperand::createImm(imod));
    2047           3 :     Inst.addOperand(MCOperand::createImm(iflags));
    2048           1 :     if (mode) S = MCDisassembler::SoftFail;
    2049           1 :   } else if (!imod && M) {
    2050             :     Inst.setOpcode(ARM::t2CPS1p);
    2051           3 :     Inst.addOperand(MCOperand::createImm(mode));
    2052           1 :     if (iflags) S = MCDisassembler::SoftFail;
    2053             :   } else {
    2054             :     // imod == '00' && M == '0' --> this is a HINT instruction
    2055           0 :     int imm = fieldFromInstruction(Insn, 0, 8);
    2056             :     // HINT are defined only for immediate in [0..4]
    2057           0 :     if(imm > 4) return MCDisassembler::Fail;
    2058             :     Inst.setOpcode(ARM::t2HINT);
    2059           0 :     Inst.addOperand(MCOperand::createImm(imm));
    2060             :   }
    2061             : 
    2062             :   return S;
    2063             : }
    2064             : 
    2065         242 : static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
    2066             :                                  uint64_t Address, const void *Decoder) {
    2067             :   DecodeStatus S = MCDisassembler::Success;
    2068             : 
    2069             :   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
    2070             :   unsigned imm = 0;
    2071             : 
    2072             :   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
    2073         242 :   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
    2074         242 :   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
    2075         242 :   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
    2076             : 
    2077         242 :   if (Inst.getOpcode() == ARM::t2MOVTi16)
    2078         176 :     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
    2079             :       return MCDisassembler::Fail;
    2080         484 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
    2081             :     return MCDisassembler::Fail;
    2082             : 
    2083         242 :   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
    2084         454 :     Inst.addOperand(MCOperand::createImm(imm));
    2085             : 
    2086             :   return S;
    2087             : }
    2088             : 
    2089         217 : static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
    2090             :                                  uint64_t Address, const void *Decoder) {
    2091             :   DecodeStatus S = MCDisassembler::Success;
    2092             : 
    2093             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2094             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2095             :   unsigned imm = 0;
    2096             : 
    2097             :   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
    2098         217 :   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
    2099             : 
    2100         217 :   if (Inst.getOpcode() == ARM::MOVTi16)
    2101         198 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2102             :       return MCDisassembler::Fail;
    2103             : 
    2104         434 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2105             :     return MCDisassembler::Fail;
    2106             : 
    2107         217 :   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
    2108         424 :     Inst.addOperand(MCOperand::createImm(imm));
    2109             : 
    2110         434 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2111             :     return MCDisassembler::Fail;
    2112             : 
    2113         160 :   return S;
    2114             : }
    2115             : 
    2116          17 : static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
    2117             :                                  uint64_t Address, const void *Decoder) {
    2118             :   DecodeStatus S = MCDisassembler::Success;
    2119             : 
    2120             :   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
    2121             :   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
    2122             :   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
    2123             :   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
    2124             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2125             : 
    2126          17 :   if (pred == 0xF)
    2127           5 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    2128             : 
    2129          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2130             :     return MCDisassembler::Fail;
    2131          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    2132             :     return MCDisassembler::Fail;
    2133          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    2134             :     return MCDisassembler::Fail;
    2135          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
    2136             :     return MCDisassembler::Fail;
    2137             : 
    2138          24 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2139             :     return MCDisassembler::Fail;
    2140             : 
    2141             :   return S;
    2142             : }
    2143             : 
    2144           5 : static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
    2145             :                                   uint64_t Address, const void *Decoder) {
    2146             :   DecodeStatus S = MCDisassembler::Success;
    2147             : 
    2148             :   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
    2149             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2150             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2151             : 
    2152           5 :   if (Pred == 0xF)
    2153           2 :     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
    2154             : 
    2155           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2156             :     return MCDisassembler::Fail;
    2157           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2158             :     return MCDisassembler::Fail;
    2159           6 :   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
    2160             :     return MCDisassembler::Fail;
    2161             : 
    2162             :   return S;
    2163             : }
    2164             : 
    2165           2 : static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
    2166             :                                   uint64_t Address, const void *Decoder) {
    2167             :   DecodeStatus S = MCDisassembler::Success;
    2168             : 
    2169             :   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
    2170             : 
    2171             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
    2172           2 :   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
    2173             : 
    2174           3 :   if (!FeatureBits[ARM::HasV8_1aOps] || 
    2175             :       !FeatureBits[ARM::HasV8Ops])
    2176             :     return MCDisassembler::Fail;
    2177             : 
    2178             :   // Decoder can be called from DecodeTST, which does not check the full
    2179             :   // encoding is valid.
    2180           2 :   if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
    2181             :       fieldFromInstruction(Insn, 4,4) != 0)
    2182             :     return MCDisassembler::Fail;
    2183           2 :   if (fieldFromInstruction(Insn, 10,10) != 0 ||
    2184             :       fieldFromInstruction(Insn, 0,4) != 0)
    2185             :     S = MCDisassembler::SoftFail;
    2186             : 
    2187             :   Inst.setOpcode(ARM::SETPAN);
    2188           3 :   Inst.addOperand(MCOperand::createImm(Imm));
    2189             : 
    2190             :   return S;
    2191             : }
    2192             : 
    2193         111 : static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
    2194             :                            uint64_t Address, const void *Decoder) {
    2195             :   DecodeStatus S = MCDisassembler::Success;
    2196             : 
    2197             :   unsigned add = fieldFromInstruction(Val, 12, 1);
    2198             :   unsigned imm = fieldFromInstruction(Val, 0, 12);
    2199             :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    2200             : 
    2201         222 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2202             :     return MCDisassembler::Fail;
    2203             : 
    2204         111 :   if (!add) imm *= -1;
    2205         111 :   if (imm == 0 && !add) imm = INT32_MIN;
    2206         333 :   Inst.addOperand(MCOperand::createImm(imm));
    2207         111 :   if (Rn == 15)
    2208          22 :     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
    2209             : 
    2210             :   return S;
    2211             : }
    2212             : 
    2213          19 : static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
    2214             :                                    uint64_t Address, const void *Decoder) {
    2215             :   DecodeStatus S = MCDisassembler::Success;
    2216             : 
    2217             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    2218             :   // U == 1 to add imm, 0 to subtract it.
    2219             :   unsigned U = fieldFromInstruction(Val, 8, 1);
    2220             :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    2221             : 
    2222          38 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2223             :     return MCDisassembler::Fail;
    2224             : 
    2225          19 :   if (U)
    2226          45 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
    2227             :   else
    2228          16 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
    2229             : 
    2230             :   return S;
    2231             : }
    2232             : 
    2233          16 : static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
    2234             :                                    uint64_t Address, const void *Decoder) {
    2235             :   DecodeStatus S = MCDisassembler::Success;
    2236             : 
    2237             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    2238             :   // U == 1 to add imm, 0 to subtract it.
    2239             :   unsigned U = fieldFromInstruction(Val, 8, 1);
    2240             :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    2241             : 
    2242          32 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2243             :     return MCDisassembler::Fail;
    2244             : 
    2245          16 :   if (U)
    2246          24 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
    2247             :   else
    2248          32 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
    2249             : 
    2250             :   return S;
    2251             : }
    2252             : 
    2253             : static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
    2254             :                                    uint64_t Address, const void *Decoder) {
    2255          74 :   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
    2256             : }
    2257             : 
    2258             : static DecodeStatus
    2259          55 : DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
    2260             :                      uint64_t Address, const void *Decoder) {
    2261             :   DecodeStatus Status = MCDisassembler::Success;
    2262             : 
    2263             :   // Note the J1 and J2 values are from the encoded instruction.  So here
    2264             :   // change them to I1 and I2 values via as documented:
    2265             :   // I1 = NOT(J1 EOR S);
    2266             :   // I2 = NOT(J2 EOR S);
    2267             :   // and build the imm32 with one trailing zero as documented:
    2268             :   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
    2269             :   unsigned S = fieldFromInstruction(Insn, 26, 1);
    2270             :   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
    2271             :   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
    2272          55 :   unsigned I1 = !(J1 ^ S);
    2273          55 :   unsigned I2 = !(J2 ^ S);
    2274             :   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
    2275             :   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
    2276          55 :   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
    2277             :   int imm32 = SignExtend32<25>(tmp << 1);
    2278         110 :   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
    2279             :                                 true, 4, Inst, Decoder))
    2280         165 :     Inst.addOperand(MCOperand::createImm(imm32));
    2281             : 
    2282          55 :   return Status;
    2283             : }
    2284             : 
    2285             : static DecodeStatus
    2286         306 : DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
    2287             :                            uint64_t Address, const void *Decoder) {
    2288             :   DecodeStatus S = MCDisassembler::Success;
    2289             : 
    2290             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2291         306 :   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
    2292             : 
    2293         306 :   if (pred == 0xF) {
    2294             :     Inst.setOpcode(ARM::BLXi);
    2295          21 :     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
    2296          42 :     if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
    2297             :                                   true, 4, Inst, Decoder))
    2298          63 :     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
    2299             :     return S;
    2300             :   }
    2301             : 
    2302         570 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
    2303             :                                 true, 4, Inst, Decoder))
    2304         855 :     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
    2305         570 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2306             :     return MCDisassembler::Fail;
    2307             : 
    2308         285 :   return S;
    2309             : }
    2310             : 
    2311         626 : static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
    2312             :                                    uint64_t Address, const void *Decoder) {
    2313             :   DecodeStatus S = MCDisassembler::Success;
    2314             : 
    2315             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    2316             :   unsigned align = fieldFromInstruction(Val, 4, 2);
    2317             : 
    2318        1252 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2319             :     return MCDisassembler::Fail;
    2320         626 :   if (!align)
    2321        1120 :     Inst.addOperand(MCOperand::createImm(0));
    2322             :   else
    2323         198 :     Inst.addOperand(MCOperand::createImm(4 << align));
    2324             : 
    2325             :   return S;
    2326             : }
    2327             : 
    2328         322 : static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
    2329             :                                    uint64_t Address, const void *Decoder) {
    2330             :   DecodeStatus S = MCDisassembler::Success;
    2331             : 
    2332             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2333         322 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2334             :   unsigned wb = fieldFromInstruction(Insn, 16, 4);
    2335             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2336         322 :   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
    2337             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2338             : 
    2339             :   // First output register
    2340         322 :   switch (Inst.getOpcode()) {
    2341          93 :   case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
    2342             :   case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
    2343             :   case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
    2344             :   case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
    2345             :   case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
    2346             :   case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
    2347             :   case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
    2348             :   case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
    2349             :   case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
    2350         186 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2351             :       return MCDisassembler::Fail;
    2352             :     break;
    2353          18 :   case ARM::VLD2b16:
    2354             :   case ARM::VLD2b32:
    2355             :   case ARM::VLD2b8:
    2356             :   case ARM::VLD2b16wb_fixed:
    2357             :   case ARM::VLD2b16wb_register:
    2358             :   case ARM::VLD2b32wb_fixed:
    2359             :   case ARM::VLD2b32wb_register:
    2360             :   case ARM::VLD2b8wb_fixed:
    2361             :   case ARM::VLD2b8wb_register:
    2362          36 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2363             :       return MCDisassembler::Fail;
    2364             :     break;
    2365         211 :   default:
    2366         422 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2367             :       return MCDisassembler::Fail;
    2368             :   }
    2369             : 
    2370             :   // Second output register
    2371         322 :   switch (Inst.getOpcode()) {
    2372          37 :     case ARM::VLD3d8:
    2373             :     case ARM::VLD3d16:
    2374             :     case ARM::VLD3d32:
    2375             :     case ARM::VLD3d8_UPD:
    2376             :     case ARM::VLD3d16_UPD:
    2377             :     case ARM::VLD3d32_UPD:
    2378             :     case ARM::VLD4d8:
    2379             :     case ARM::VLD4d16:
    2380             :     case ARM::VLD4d32:
    2381             :     case ARM::VLD4d8_UPD:
    2382             :     case ARM::VLD4d16_UPD:
    2383             :     case ARM::VLD4d32_UPD:
    2384          74 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
    2385             :         return MCDisassembler::Fail;
    2386             :       break;
    2387          49 :     case ARM::VLD3q8:
    2388             :     case ARM::VLD3q16:
    2389             :     case ARM::VLD3q32:
    2390             :     case ARM::VLD3q8_UPD:
    2391             :     case ARM::VLD3q16_UPD:
    2392             :     case ARM::VLD3q32_UPD:
    2393             :     case ARM::VLD4q8:
    2394             :     case ARM::VLD4q16:
    2395             :     case ARM::VLD4q32:
    2396             :     case ARM::VLD4q8_UPD:
    2397             :     case ARM::VLD4q16_UPD:
    2398             :     case ARM::VLD4q32_UPD:
    2399          98 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2400             :         return MCDisassembler::Fail;
    2401             :       break;
    2402             :     default:
    2403             :       break;
    2404             :   }
    2405             : 
    2406             :   // Third output register
    2407         322 :   switch(Inst.getOpcode()) {
    2408          37 :     case ARM::VLD3d8:
    2409             :     case ARM::VLD3d16:
    2410             :     case ARM::VLD3d32:
    2411             :     case ARM::VLD3d8_UPD:
    2412             :     case ARM::VLD3d16_UPD:
    2413             :     case ARM::VLD3d32_UPD:
    2414             :     case ARM::VLD4d8:
    2415             :     case ARM::VLD4d16:
    2416             :     case ARM::VLD4d32:
    2417             :     case ARM::VLD4d8_UPD:
    2418             :     case ARM::VLD4d16_UPD:
    2419             :     case ARM::VLD4d32_UPD:
    2420          74 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2421             :         return MCDisassembler::Fail;
    2422             :       break;
    2423          49 :     case ARM::VLD3q8:
    2424             :     case ARM::VLD3q16:
    2425             :     case ARM::VLD3q32:
    2426             :     case ARM::VLD3q8_UPD:
    2427             :     case ARM::VLD3q16_UPD:
    2428             :     case ARM::VLD3q32_UPD:
    2429             :     case ARM::VLD4q8:
    2430             :     case ARM::VLD4q16:
    2431             :     case ARM::VLD4q32:
    2432             :     case ARM::VLD4q8_UPD:
    2433             :     case ARM::VLD4q16_UPD:
    2434             :     case ARM::VLD4q32_UPD:
    2435          98 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
    2436             :         return MCDisassembler::Fail;
    2437             :       break;
    2438             :     default:
    2439             :       break;
    2440             :   }
    2441             : 
    2442             :   // Fourth output register
    2443         322 :   switch (Inst.getOpcode()) {
    2444          19 :     case ARM::VLD4d8:
    2445             :     case ARM::VLD4d16:
    2446             :     case ARM::VLD4d32:
    2447             :     case ARM::VLD4d8_UPD:
    2448             :     case ARM::VLD4d16_UPD:
    2449             :     case ARM::VLD4d32_UPD:
    2450          38 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
    2451             :         return MCDisassembler::Fail;
    2452             :       break;
    2453          25 :     case ARM::VLD4q8:
    2454             :     case ARM::VLD4q16:
    2455             :     case ARM::VLD4q32:
    2456             :     case ARM::VLD4q8_UPD:
    2457             :     case ARM::VLD4q16_UPD:
    2458             :     case ARM::VLD4q32_UPD:
    2459          50 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
    2460             :         return MCDisassembler::Fail;
    2461             :       break;
    2462             :     default:
    2463             :       break;
    2464             :   }
    2465             : 
    2466             :   // Writeback operand
    2467         322 :   switch (Inst.getOpcode()) {
    2468             :     case ARM::VLD1d8wb_fixed:
    2469             :     case ARM::VLD1d16wb_fixed:
    2470             :     case ARM::VLD1d32wb_fixed:
    2471             :     case ARM::VLD1d64wb_fixed:
    2472             :     case ARM::VLD1d8wb_register:
    2473             :     case ARM::VLD1d16wb_register:
    2474             :     case ARM::VLD1d32wb_register:
    2475             :     case ARM::VLD1d64wb_register:
    2476             :     case ARM::VLD1q8wb_fixed:
    2477             :     case ARM::VLD1q16wb_fixed:
    2478             :     case ARM::VLD1q32wb_fixed:
    2479             :     case ARM::VLD1q64wb_fixed:
    2480             :     case ARM::VLD1q8wb_register:
    2481             :     case ARM::VLD1q16wb_register:
    2482             :     case ARM::VLD1q32wb_register:
    2483             :     case ARM::VLD1q64wb_register:
    2484             :     case ARM::VLD1d8Twb_fixed:
    2485             :     case ARM::VLD1d8Twb_register:
    2486             :     case ARM::VLD1d16Twb_fixed:
    2487             :     case ARM::VLD1d16Twb_register:
    2488             :     case ARM::VLD1d32Twb_fixed:
    2489             :     case ARM::VLD1d32Twb_register:
    2490             :     case ARM::VLD1d64Twb_fixed:
    2491             :     case ARM::VLD1d64Twb_register:
    2492             :     case ARM::VLD1d8Qwb_fixed:
    2493             :     case ARM::VLD1d8Qwb_register:
    2494             :     case ARM::VLD1d16Qwb_fixed:
    2495             :     case ARM::VLD1d16Qwb_register:
    2496             :     case ARM::VLD1d32Qwb_fixed:
    2497             :     case ARM::VLD1d32Qwb_register:
    2498             :     case ARM::VLD1d64Qwb_fixed:
    2499             :     case ARM::VLD1d64Qwb_register:
    2500             :     case ARM::VLD2d8wb_fixed:
    2501             :     case ARM::VLD2d16wb_fixed:
    2502             :     case ARM::VLD2d32wb_fixed:
    2503             :     case ARM::VLD2q8wb_fixed:
    2504             :     case ARM::VLD2q16wb_fixed:
    2505             :     case ARM::VLD2q32wb_fixed:
    2506             :     case ARM::VLD2d8wb_register:
    2507             :     case ARM::VLD2d16wb_register:
    2508             :     case ARM::VLD2d32wb_register:
    2509             :     case ARM::VLD2q8wb_register:
    2510             :     case ARM::VLD2q16wb_register:
    2511             :     case ARM::VLD2q32wb_register:
    2512             :     case ARM::VLD2b8wb_fixed:
    2513             :     case ARM::VLD2b16wb_fixed:
    2514             :     case ARM::VLD2b32wb_fixed:
    2515             :     case ARM::VLD2b8wb_register:
    2516             :     case ARM::VLD2b16wb_register:
    2517             :     case ARM::VLD2b32wb_register:
    2518         376 :       Inst.addOperand(MCOperand::createImm(0));
    2519         188 :       break;
    2520          49 :     case ARM::VLD3d8_UPD:
    2521             :     case ARM::VLD3d16_UPD:
    2522             :     case ARM::VLD3d32_UPD:
    2523             :     case ARM::VLD3q8_UPD:
    2524             :     case ARM::VLD3q16_UPD:
    2525             :     case ARM::VLD3q32_UPD:
    2526             :     case ARM::VLD4d8_UPD:
    2527             :     case ARM::VLD4d16_UPD:
    2528             :     case ARM::VLD4d32_UPD:
    2529             :     case ARM::VLD4q8_UPD:
    2530             :     case ARM::VLD4q16_UPD:
    2531             :     case ARM::VLD4q32_UPD:
    2532          98 :       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
    2533             :         return MCDisassembler::Fail;
    2534             :       break;
    2535             :     default:
    2536             :       break;
    2537             :   }
    2538             : 
    2539             :   // AddrMode6 Base (register+alignment)
    2540         644 :   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
    2541             :     return MCDisassembler::Fail;
    2542             : 
    2543             :   // AddrMode6 Offset (register)
    2544         322 :   switch (Inst.getOpcode()) {
    2545         175 :   default:
    2546             :     // The below have been updated to have explicit am6offset split
    2547             :     // between fixed and register offset. For those instructions not
    2548             :     // yet updated, we need to add an additional reg0 operand for the
    2549             :     // fixed variant.
    2550             :     //
    2551             :     // The fixed offset encodes as Rm == 0xd, so we check for that.
    2552         175 :     if (Rm == 0xd) {
    2553          72 :       Inst.addOperand(MCOperand::createReg(0));
    2554          36 :       break;
    2555             :     }
    2556             :     // Fall through to handle the register offset variant.
    2557             :     LLVM_FALLTHROUGH;
    2558             :   case ARM::VLD1d8wb_fixed:
    2559             :   case ARM::VLD1d16wb_fixed:
    2560             :   case ARM::VLD1d32wb_fixed:
    2561             :   case ARM::VLD1d64wb_fixed:
    2562             :   case ARM::VLD1d8Twb_fixed:
    2563             :   case ARM::VLD1d16Twb_fixed:
    2564             :   case ARM::VLD1d32Twb_fixed:
    2565             :   case ARM::VLD1d64Twb_fixed:
    2566             :   case ARM::VLD1d8Qwb_fixed:
    2567             :   case ARM::VLD1d16Qwb_fixed:
    2568             :   case ARM::VLD1d32Qwb_fixed:
    2569             :   case ARM::VLD1d64Qwb_fixed:
    2570             :   case ARM::VLD1d8wb_register:
    2571             :   case ARM::VLD1d16wb_register:
    2572             :   case ARM::VLD1d32wb_register:
    2573             :   case ARM::VLD1d64wb_register:
    2574             :   case ARM::VLD1q8wb_fixed:
    2575             :   case ARM::VLD1q16wb_fixed:
    2576             :   case ARM::VLD1q32wb_fixed:
    2577             :   case ARM::VLD1q64wb_fixed:
    2578             :   case ARM::VLD1q8wb_register:
    2579             :   case ARM::VLD1q16wb_register:
    2580             :   case ARM::VLD1q32wb_register:
    2581             :   case ARM::VLD1q64wb_register:
    2582             :     // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
    2583             :     // variant encodes Rm == 0xf. Anything else is a register offset post-
    2584             :     // increment and we need to add the register operand to the instruction.
    2585         333 :     if (Rm != 0xD && Rm != 0xF &&
    2586          71 :         !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2587             :       return MCDisassembler::Fail;
    2588             :     break;
    2589             :   case ARM::VLD2d8wb_fixed:
    2590             :   case ARM::VLD2d16wb_fixed:
    2591             :   case ARM::VLD2d32wb_fixed:
    2592             :   case ARM::VLD2b8wb_fixed:
    2593             :   case ARM::VLD2b16wb_fixed:
    2594             :   case ARM::VLD2b32wb_fixed:
    2595             :   case ARM::VLD2q8wb_fixed:
    2596             :   case ARM::VLD2q16wb_fixed:
    2597             :   case ARM::VLD2q32wb_fixed:
    2598             :     break;
    2599             :   }
    2600             : 
    2601             :   return S;
    2602             : }
    2603             : 
    2604         332 : static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
    2605             :                                    uint64_t Address, const void *Decoder) {
    2606             :   unsigned type = fieldFromInstruction(Insn, 8, 4);
    2607             :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2608         332 :   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
    2609         328 :   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
    2610         328 :   if (type == 10 && align == 3) return MCDisassembler::Fail;
    2611             : 
    2612             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2613         325 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2614             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2615             : }
    2616             : 
    2617         139 : static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
    2618             :                                    uint64_t Address, const void *Decoder) {
    2619             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2620         139 :   if (size == 3) return MCDisassembler::Fail;
    2621             : 
    2622             :   unsigned type = fieldFromInstruction(Insn, 8, 4);
    2623             :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2624         139 :   if (type == 8 && align == 3) return MCDisassembler::Fail;
    2625         136 :   if (type == 9 && align == 3) return MCDisassembler::Fail;
    2626             : 
    2627             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2628         133 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2629             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2630             : }
    2631             : 
    2632          84 : static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
    2633             :                                    uint64_t Address, const void *Decoder) {
    2634             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2635          84 :   if (size == 3) return MCDisassembler::Fail;
    2636             : 
    2637             :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2638          84 :   if (align & 2) return MCDisassembler::Fail;
    2639             : 
    2640             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2641          84 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2642             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2643             : }
    2644             : 
    2645          84 : static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
    2646             :                                    uint64_t Address, const void *Decoder) {
    2647             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2648          84 :   if (size == 3) return MCDisassembler::Fail;
    2649             : 
    2650             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2651          84 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2652             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2653             : }
    2654             : 
    2655         304 : static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
    2656             :                                  uint64_t Address, const void *Decoder) {
    2657             :   DecodeStatus S = MCDisassembler::Success;
    2658             : 
    2659             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2660         304 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2661             :   unsigned wb = fieldFromInstruction(Insn, 16, 4);
    2662             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2663         304 :   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
    2664             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2665             : 
    2666             :   // Writeback Operand
    2667         304 :   switch (Inst.getOpcode()) {
    2668         174 :     case ARM::VST1d8wb_fixed:
    2669             :     case ARM::VST1d16wb_fixed:
    2670             :     case ARM::VST1d32wb_fixed:
    2671             :     case ARM::VST1d64wb_fixed:
    2672             :     case ARM::VST1d8wb_register:
    2673             :     case ARM::VST1d16wb_register:
    2674             :     case ARM::VST1d32wb_register:
    2675             :     case ARM::VST1d64wb_register:
    2676             :     case ARM::VST1q8wb_fixed:
    2677             :     case ARM::VST1q16wb_fixed:
    2678             :     case ARM::VST1q32wb_fixed:
    2679             :     case ARM::VST1q64wb_fixed:
    2680             :     case ARM::VST1q8wb_register:
    2681             :     case ARM::VST1q16wb_register:
    2682             :     case ARM::VST1q32wb_register:
    2683             :     case ARM::VST1q64wb_register:
    2684             :     case ARM::VST1d8Twb_fixed:
    2685             :     case ARM::VST1d16Twb_fixed:
    2686             :     case ARM::VST1d32Twb_fixed:
    2687             :     case ARM::VST1d64Twb_fixed:
    2688             :     case ARM::VST1d8Twb_register:
    2689             :     case ARM::VST1d16Twb_register:
    2690             :     case ARM::VST1d32Twb_register:
    2691             :     case ARM::VST1d64Twb_register:
    2692             :     case ARM::VST1d8Qwb_fixed:
    2693             :     case ARM::VST1d16Qwb_fixed:
    2694             :     case ARM::VST1d32Qwb_fixed:
    2695             :     case ARM::VST1d64Qwb_fixed:
    2696             :     case ARM::VST1d8Qwb_register:
    2697             :     case ARM::VST1d16Qwb_register:
    2698             :     case ARM::VST1d32Qwb_register:
    2699             :     case ARM::VST1d64Qwb_register:
    2700             :     case ARM::VST2d8wb_fixed:
    2701             :     case ARM::VST2d16wb_fixed:
    2702             :     case ARM::VST2d32wb_fixed:
    2703             :     case ARM::VST2d8wb_register:
    2704             :     case ARM::VST2d16wb_register:
    2705             :     case ARM::VST2d32wb_register:
    2706             :     case ARM::VST2q8wb_fixed:
    2707             :     case ARM::VST2q16wb_fixed:
    2708             :     case ARM::VST2q32wb_fixed:
    2709             :     case ARM::VST2q8wb_register:
    2710             :     case ARM::VST2q16wb_register:
    2711             :     case ARM::VST2q32wb_register:
    2712             :     case ARM::VST2b8wb_fixed:
    2713             :     case ARM::VST2b16wb_fixed:
    2714             :     case ARM::VST2b32wb_fixed:
    2715             :     case ARM::VST2b8wb_register:
    2716             :     case ARM::VST2b16wb_register:
    2717             :     case ARM::VST2b32wb_register:
    2718         174 :       if (Rm == 0xF)
    2719             :         return MCDisassembler::Fail;
    2720         348 :       Inst.addOperand(MCOperand::createImm(0));
    2721         174 :       break;
    2722          48 :     case ARM::VST3d8_UPD:
    2723             :     case ARM::VST3d16_UPD:
    2724             :     case ARM::VST3d32_UPD:
    2725             :     case ARM::VST3q8_UPD:
    2726             :     case ARM::VST3q16_UPD:
    2727             :     case ARM::VST3q32_UPD:
    2728             :     case ARM::VST4d8_UPD:
    2729             :     case ARM::VST4d16_UPD:
    2730             :     case ARM::VST4d32_UPD:
    2731             :     case ARM::VST4q8_UPD:
    2732             :     case ARM::VST4q16_UPD:
    2733             :     case ARM::VST4q32_UPD:
    2734          96 :       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
    2735             :         return MCDisassembler::Fail;
    2736             :       break;
    2737             :     default:
    2738             :       break;
    2739             :   }
    2740             : 
    2741             :   // AddrMode6 Base (register+alignment)
    2742         608 :   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
    2743             :     return MCDisassembler::Fail;
    2744             : 
    2745             :   // AddrMode6 Offset (register)
    2746         304 :   switch (Inst.getOpcode()) {
    2747         181 :     default:
    2748         181 :       if (Rm == 0xD)
    2749          72 :         Inst.addOperand(MCOperand::createReg(0));
    2750         145 :       else if (Rm != 0xF) {
    2751         126 :         if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2752             :           return MCDisassembler::Fail;
    2753             :       }
    2754             :       break;
    2755             :     case ARM::VST1d8wb_fixed:
    2756             :     case ARM::VST1d16wb_fixed:
    2757             :     case ARM::VST1d32wb_fixed:
    2758             :     case ARM::VST1d64wb_fixed:
    2759             :     case ARM::VST1q8wb_fixed:
    2760             :     case ARM::VST1q16wb_fixed:
    2761             :     case ARM::VST1q32wb_fixed:
    2762             :     case ARM::VST1q64wb_fixed:
    2763             :     case ARM::VST1d8Twb_fixed:
    2764             :     case ARM::VST1d16Twb_fixed:
    2765             :     case ARM::VST1d32Twb_fixed:
    2766             :     case ARM::VST1d64Twb_fixed:
    2767             :     case ARM::VST1d8Qwb_fixed:
    2768             :     case ARM::VST1d16Qwb_fixed:
    2769             :     case ARM::VST1d32Qwb_fixed:
    2770             :     case ARM::VST1d64Qwb_fixed:
    2771             :     case ARM::VST2d8wb_fixed:
    2772             :     case ARM::VST2d16wb_fixed:
    2773             :     case ARM::VST2d32wb_fixed:
    2774             :     case ARM::VST2q8wb_fixed:
    2775             :     case ARM::VST2q16wb_fixed:
    2776             :     case ARM::VST2q32wb_fixed:
    2777             :     case ARM::VST2b8wb_fixed:
    2778             :     case ARM::VST2b16wb_fixed:
    2779             :     case ARM::VST2b32wb_fixed:
    2780             :       break;
    2781             :   }
    2782             : 
    2783             :   // First input register
    2784         304 :   switch (Inst.getOpcode()) {
    2785          93 :   case ARM::VST1q16:
    2786             :   case ARM::VST1q32:
    2787             :   case ARM::VST1q64:
    2788             :   case ARM::VST1q8:
    2789             :   case ARM::VST1q16wb_fixed:
    2790             :   case ARM::VST1q16wb_register:
    2791             :   case ARM::VST1q32wb_fixed:
    2792             :   case ARM::VST1q32wb_register:
    2793             :   case ARM::VST1q64wb_fixed:
    2794             :   case ARM::VST1q64wb_register:
    2795             :   case ARM::VST1q8wb_fixed:
    2796             :   case ARM::VST1q8wb_register:
    2797             :   case ARM::VST2d16:
    2798             :   case ARM::VST2d32:
    2799             :   case ARM::VST2d8:
    2800             :   case ARM::VST2d16wb_fixed:
    2801             :   case ARM::VST2d16wb_register:
    2802             :   case ARM::VST2d32wb_fixed:
    2803             :   case ARM::VST2d32wb_register:
    2804             :   case ARM::VST2d8wb_fixed:
    2805             :   case ARM::VST2d8wb_register:
    2806         186 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2807             :       return MCDisassembler::Fail;
    2808             :     break;
    2809          19 :   case ARM::VST2b16:
    2810             :   case ARM::VST2b32:
    2811             :   case ARM::VST2b8:
    2812             :   case ARM::VST2b16wb_fixed:
    2813             :   case ARM::VST2b16wb_register:
    2814             :   case ARM::VST2b32wb_fixed:
    2815             :   case ARM::VST2b32wb_register:
    2816             :   case ARM::VST2b8wb_fixed:
    2817             :   case ARM::VST2b8wb_register:
    2818          38 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2819             :       return MCDisassembler::Fail;
    2820             :     break;
    2821         192 :   default:
    2822         384 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2823             :       return MCDisassembler::Fail;
    2824             :   }
    2825             : 
    2826             :   // Second input register
    2827         304 :   switch (Inst.getOpcode()) {
    2828          34 :     case ARM::VST3d8:
    2829             :     case ARM::VST3d16:
    2830             :     case ARM::VST3d32:
    2831             :     case ARM::VST3d8_UPD:
    2832             :     case ARM::VST3d16_UPD:
    2833             :     case ARM::VST3d32_UPD:
    2834             :     case ARM::VST4d8:
    2835             :     case ARM::VST4d16:
    2836             :     case ARM::VST4d32:
    2837             :     case ARM::VST4d8_UPD:
    2838             :     case ARM::VST4d16_UPD:
    2839             :     case ARM::VST4d32_UPD:
    2840          68 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
    2841             :         return MCDisassembler::Fail;
    2842             :       break;
    2843          48 :     case ARM::VST3q8:
    2844             :     case ARM::VST3q16:
    2845             :     case ARM::VST3q32:
    2846             :     case ARM::VST3q8_UPD:
    2847             :     case ARM::VST3q16_UPD:
    2848             :     case ARM::VST3q32_UPD:
    2849             :     case ARM::VST4q8:
    2850             :     case ARM::VST4q16:
    2851             :     case ARM::VST4q32:
    2852             :     case ARM::VST4q8_UPD:
    2853             :     case ARM::VST4q16_UPD:
    2854             :     case ARM::VST4q32_UPD:
    2855          96 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2856             :         return MCDisassembler::Fail;
    2857             :       break;
    2858             :     default:
    2859             :       break;
    2860             :   }
    2861             : 
    2862             :   // Third input register
    2863         304 :   switch (Inst.getOpcode()) {
    2864          34 :     case ARM::VST3d8:
    2865             :     case ARM::VST3d16:
    2866             :     case ARM::VST3d32:
    2867             :     case ARM::VST3d8_UPD:
    2868             :     case ARM::VST3d16_UPD:
    2869             :     case ARM::VST3d32_UPD:
    2870             :     case ARM::VST4d8:
    2871             :     case ARM::VST4d16:
    2872             :     case ARM::VST4d32:
    2873             :     case ARM::VST4d8_UPD:
    2874             :     case ARM::VST4d16_UPD:
    2875             :     case ARM::VST4d32_UPD:
    2876          68 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2877             :         return MCDisassembler::Fail;
    2878             :       break;
    2879          48 :     case ARM::VST3q8:
    2880             :     case ARM::VST3q16:
    2881             :     case ARM::VST3q32:
    2882             :     case ARM::VST3q8_UPD:
    2883             :     case ARM::VST3q16_UPD:
    2884             :     case ARM::VST3q32_UPD:
    2885             :     case ARM::VST4q8:
    2886             :     case ARM::VST4q16:
    2887             :     case ARM::VST4q32:
    2888             :     case ARM::VST4q8_UPD:
    2889             :     case ARM::VST4q16_UPD:
    2890             :     case ARM::VST4q32_UPD:
    2891          96 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
    2892             :         return MCDisassembler::Fail;
    2893             :       break;
    2894             :     default:
    2895             :       break;
    2896             :   }
    2897             : 
    2898             :   // Fourth input register
    2899         304 :   switch (Inst.getOpcode()) {
    2900          16 :     case ARM::VST4d8:
    2901             :     case ARM::VST4d16:
    2902             :     case ARM::VST4d32:
    2903             :     case ARM::VST4d8_UPD:
    2904             :     case ARM::VST4d16_UPD:
    2905             :     case ARM::VST4d32_UPD:
    2906          32 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
    2907             :         return MCDisassembler::Fail;
    2908             :       break;
    2909          24 :     case ARM::VST4q8:
    2910             :     case ARM::VST4q16:
    2911             :     case ARM::VST4q32:
    2912             :     case ARM::VST4q8_UPD:
    2913             :     case ARM::VST4q16_UPD:
    2914             :     case ARM::VST4q32_UPD:
    2915          48 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
    2916             :         return MCDisassembler::Fail;
    2917             :       break;
    2918             :     default:
    2919             :       break;
    2920             :   }
    2921             : 
    2922             :   return S;
    2923             : }
    2924             : 
    2925           3 : static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
    2926             :                                     uint64_t Address, const void *Decoder) {
    2927             :   DecodeStatus S = MCDisassembler::Success;
    2928             : 
    2929             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2930           3 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2931             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2932             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2933             :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    2934             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2935             : 
    2936           3 :   if (size == 0 && align == 1)
    2937             :     return MCDisassembler::Fail;
    2938           2 :   align *= (1 << size);
    2939             : 
    2940           2 :   switch (Inst.getOpcode()) {
    2941           1 :   case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
    2942             :   case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
    2943             :   case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
    2944             :   case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
    2945           2 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2946             :       return MCDisassembler::Fail;
    2947             :     break;
    2948           1 :   default:
    2949           2 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2950             :       return MCDisassembler::Fail;
    2951             :     break;
    2952             :   }
    2953           2 :   if (Rm != 0xF) {
    2954           4 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2955             :       return MCDisassembler::Fail;
    2956             :   }
    2957             : 
    2958           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2959             :     return MCDisassembler::Fail;
    2960           6 :   Inst.addOperand(MCOperand::createImm(align));
    2961             : 
    2962             :   // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
    2963             :   // variant encodes Rm == 0xf. Anything else is a register offset post-
    2964             :   // increment and we need to add the register operand to the instruction.
    2965           3 :   if (Rm != 0xD && Rm != 0xF &&
    2966           1 :       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2967             :     return MCDisassembler::Fail;
    2968             : 
    2969             :   return S;
    2970             : }
    2971             : 
    2972          42 : static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
    2973             :                                     uint64_t Address, const void *Decoder) {
    2974             :   DecodeStatus S = MCDisassembler::Success;
    2975             : 
    2976             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2977          42 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2978             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2979             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2980             :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    2981             :   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
    2982          42 :   align *= 2*size;
    2983             : 
    2984          42 :   switch (Inst.getOpcode()) {
    2985          18 :   case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
    2986             :   case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
    2987             :   case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
    2988             :   case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
    2989          36 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2990             :       return MCDisassembler::Fail;
    2991             :     break;
    2992          24 :   case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
    2993             :   case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
    2994             :   case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
    2995             :   case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
    2996          48 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2997             :       return MCDisassembler::Fail;
    2998             :     break;
    2999           0 :   default:
    3000           0 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3001             :       return MCDisassembler::Fail;
    3002             :     break;
    3003             :   }
    3004             : 
    3005          42 :   if (Rm != 0xF)
    3006          56 :     Inst.addOperand(MCOperand::createImm(0));
    3007             : 
    3008          84 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3009             :     return MCDisassembler::Fail;
    3010         126 :   Inst.addOperand(MCOperand::createImm(align));
    3011             : 
    3012          42 :   if (Rm != 0xD && Rm != 0xF) {
    3013          28 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3014             :       return MCDisassembler::Fail;
    3015             :   }
    3016             : 
    3017             :   return S;
    3018             : }
    3019             : 
    3020          18 : static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
    3021             :                                     uint64_t Address, const void *Decoder) {
    3022             :   DecodeStatus S = MCDisassembler::Success;
    3023             : 
    3024             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3025          18 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3026             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3027             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3028          18 :   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
    3029             : 
    3030          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3031             :     return MCDisassembler::Fail;
    3032          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
    3033             :     return MCDisassembler::Fail;
    3034          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
    3035             :     return MCDisassembler::Fail;
    3036          18 :   if (Rm != 0xF) {
    3037          24 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3038             :       return MCDisassembler::Fail;
    3039             :   }
    3040             : 
    3041          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3042             :     return MCDisassembler::Fail;
    3043          36 :   Inst.addOperand(MCOperand::createImm(0));
    3044             : 
    3045          18 :   if (Rm == 0xD)
    3046          12 :     Inst.addOperand(MCOperand::createReg(0));
    3047          12 :   else if (Rm != 0xF) {
    3048          12 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3049             :       return MCDisassembler::Fail;
    3050             :   }
    3051             : 
    3052             :   return S;
    3053             : }
    3054             : 
    3055          27 : static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
    3056             :                                     uint64_t Address, const void *Decoder) {
    3057             :   DecodeStatus S = MCDisassembler::Success;
    3058             : 
    3059             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3060          27 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3061             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3062             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3063             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    3064          27 :   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
    3065             :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    3066             : 
    3067          27 :   if (size == 0x3) {
    3068           6 :     if (align == 0)
    3069             :       return MCDisassembler::Fail;
    3070             :     align = 16;
    3071             :   } else {
    3072          21 :     if (size == 2) {
    3073           4 :       align *= 8;
    3074             :     } else {
    3075             :       size = 1 << size;
    3076          17 :       align *= 4*size;
    3077             :     }
    3078             :   }
    3079             : 
    3080          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3081             :     return MCDisassembler::Fail;
    3082          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
    3083             :     return MCDisassembler::Fail;
    3084          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
    3085             :     return MCDisassembler::Fail;
    3086          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
    3087             :     return MCDisassembler::Fail;
    3088          25 :   if (Rm != 0xF) {
    3089          26 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3090             :       return MCDisassembler::Fail;
    3091             :   }
    3092             : 
    3093          50 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3094             :     return MCDisassembler::Fail;
    3095          75 :   Inst.addOperand(MCOperand::createImm(align));
    3096             : 
    3097          25 :   if (Rm == 0xD)
    3098          14 :     Inst.addOperand(MCOperand::createReg(0));
    3099          18 :   else if (Rm != 0xF) {
    3100          12 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3101             :       return MCDisassembler::Fail;
    3102             :   }
    3103             : 
    3104             :   return S;
    3105             : }
    3106             : 
    3107             : static DecodeStatus
    3108          94 : DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
    3109             :                             uint64_t Address, const void *Decoder) {
    3110             :   DecodeStatus S = MCDisassembler::Success;
    3111             : 
    3112             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3113          94 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3114             :   unsigned imm = fieldFromInstruction(Insn, 0, 4);
    3115          94 :   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
    3116          94 :   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
    3117          94 :   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
    3118          94 :   imm |= fieldFromInstruction(Insn, 5, 1) << 12;
    3119             :   unsigned Q = fieldFromInstruction(Insn, 6, 1);
    3120             : 
    3121          94 :   if (Q) {
    3122          88 :     if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3123             :     return MCDisassembler::Fail;
    3124             :   } else {
    3125         100 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3126             :     return MCDisassembler::Fail;
    3127             :   }
    3128             : 
    3129         282 :   Inst.addOperand(MCOperand::createImm(imm));
    3130             : 
    3131          94 :   switch (Inst.getOpcode()) {
    3132           4 :     case ARM::VORRiv4i16:
    3133             :     case ARM::VORRiv2i32:
    3134             :     case ARM::VBICiv4i16:
    3135             :     case ARM::VBICiv2i32:
    3136           8 :       if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3137             :         return MCDisassembler::Fail;
    3138             :       break;
    3139           8 :     case ARM::VORRiv8i16:
    3140             :     case ARM::VORRiv4i32:
    3141             :     case ARM::VBICiv8i16:
    3142             :     case ARM::VBICiv4i32:
    3143          16 :       if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3144             :         return MCDisassembler::Fail;
    3145             :       break;
    3146             :     default:
    3147             :       break;
    3148             :   }
    3149             : 
    3150             :   return S;
    3151             : }
    3152             : 
    3153           7 : static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
    3154             :                                         uint64_t Address, const void *Decoder) {
    3155             :   DecodeStatus S = MCDisassembler::Success;
    3156             : 
    3157             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3158           7 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3159             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3160           7 :   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
    3161             :   unsigned size = fieldFromInstruction(Insn, 18, 2);
    3162             : 
    3163          14 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3164             :     return MCDisassembler::Fail;
    3165          14 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
    3166             :     return MCDisassembler::Fail;
    3167          21 :   Inst.addOperand(MCOperand::createImm(8 << size));
    3168             : 
    3169           7 :   return S;
    3170             : }
    3171             : 
    3172             : static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
    3173             :                                uint64_t Address, const void *Decoder) {
    3174         180 :   Inst.addOperand(MCOperand::createImm(8 - Val));
    3175             :   return MCDisassembler::Success;
    3176             : }
    3177             : 
    3178             : static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
    3179             :                                uint64_t Address, const void *Decoder) {
    3180         180 :   Inst.addOperand(MCOperand::createImm(16 - Val));
    3181             :   return MCDisassembler::Success;
    3182             : }
    3183             : 
    3184             : static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
    3185             :                                uint64_t Address, const void *Decoder) {
    3186         186 :   Inst.addOperand(MCOperand::createImm(32 - Val));
    3187             :   return MCDisassembler::Success;
    3188             : }
    3189             : 
    3190             : static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
    3191             :                                uint64_t Address, const void *Decoder) {
    3192         126 :   Inst.addOperand(MCOperand::createImm(64 - Val));
    3193             :   return MCDisassembler::Success;
    3194             : }
    3195             : 
    3196          17 : static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
    3197             :                                uint64_t Address, const void *Decoder) {
    3198             :   DecodeStatus S = MCDisassembler::Success;
    3199             : 
    3200             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3201          17 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3202             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3203          17 :   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
    3204             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3205          17 :   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
    3206             :   unsigned op = fieldFromInstruction(Insn, 6, 1);
    3207             : 
    3208          34 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3209             :     return MCDisassembler::Fail;
    3210          17 :   if (op) {
    3211          18 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3212             :     return MCDisassembler::Fail; // Writeback
    3213             :   }
    3214             : 
    3215          17 :   switch (Inst.getOpcode()) {
    3216           4 :   case ARM::VTBL2:
    3217             :   case ARM::VTBX2:
    3218           8 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
    3219             :       return MCDisassembler::Fail;
    3220             :     break;
    3221          13 :   default:
    3222          26 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
    3223             :       return MCDisassembler::Fail;
    3224             :   }
    3225             : 
    3226          34 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
    3227             :     return MCDisassembler::Fail;
    3228             : 
    3229          17 :   return S;
    3230             : }
    3231             : 
    3232         342 : static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
    3233             :                                      uint64_t Address, const void *Decoder) {
    3234             :   DecodeStatus S = MCDisassembler::Success;
    3235             : 
    3236         342 :   unsigned dst = fieldFromInstruction(Insn, 8, 3);
    3237             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3238             : 
    3239         342 :   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
    3240             :     return MCDisassembler::Fail;
    3241             : 
    3242         342 :   switch(Inst.getOpcode()) {
    3243             :     default:
    3244             :       return MCDisassembler::Fail;
    3245             :     case ARM::tADR:
    3246             :       break; // tADR does not explicitly represent the PC as an operand.
    3247             :     case ARM::tADDrSPi:
    3248         674 :       Inst.addOperand(MCOperand::createReg(ARM::SP));
    3249         337 :       break;
    3250             :   }
    3251             : 
    3252        1026 :   Inst.addOperand(MCOperand::createImm(imm));
    3253         342 :   return S;
    3254             : }
    3255             : 
    3256          41 : static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
    3257             :                                  uint64_t Address, const void *Decoder) {
    3258          82 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
    3259             :                                 true, 2, Inst, Decoder))
    3260         117 :     Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
    3261          41 :   return MCDisassembler::Success;
    3262             : }
    3263             : 
    3264          24 : static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
    3265             :                                  uint64_t Address, const void *Decoder) {
    3266          48 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
    3267             :                                 true, 4, Inst, Decoder))
    3268          72 :     Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
    3269          24 :   return MCDisassembler::Success;
    3270             : }
    3271             : 
    3272          10 : static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
    3273             :                                  uint64_t Address, const void *Decoder) {
    3274          20 :   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
    3275             :                                 true, 2, Inst, Decoder))
    3276          30 :     Inst.addOperand(MCOperand::createImm(Val << 1));
    3277          10 :   return MCDisassembler::Success;
    3278             : }
    3279             : 
    3280          13 : static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
    3281             :                                  uint64_t Address, const void *Decoder) {
    3282             :   DecodeStatus S = MCDisassembler::Success;
    3283             : 
    3284             :   unsigned Rn = fieldFromInstruction(Val, 0, 3);
    3285             :   unsigned Rm = fieldFromInstruction(Val, 3, 3);
    3286             : 
    3287          13 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3288             :     return MCDisassembler::Fail;
    3289          13 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3290             :     return MCDisassembler::Fail;
    3291             : 
    3292             :   return S;
    3293             : }
    3294             : 
    3295        1905 : static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
    3296             :                                   uint64_t Address, const void *Decoder) {
    3297             :   DecodeStatus S = MCDisassembler::Success;
    3298             : 
    3299             :   unsigned Rn = fieldFromInstruction(Val, 0, 3);
    3300             :   unsigned imm = fieldFromInstruction(Val, 3, 5);
    3301             : 
    3302        1905 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3303             :     return MCDisassembler::Fail;
    3304        5715 :   Inst.addOperand(MCOperand::createImm(imm));
    3305             : 
    3306             :   return S;
    3307             : }
    3308             : 
    3309          63 : static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
    3310             :                                   uint64_t Address, const void *Decoder) {
    3311          63 :   unsigned imm = Val << 2;
    3312             : 
    3313         189 :   Inst.addOperand(MCOperand::createImm(imm));
    3314          63 :   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
    3315             : 
    3316          63 :   return MCDisassembler::Success;
    3317             : }
    3318             : 
    3319         278 : static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
    3320             :                                   uint64_t Address, const void *Decoder) {
    3321         556 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3322         834 :   Inst.addOperand(MCOperand::createImm(Val));
    3323             : 
    3324         278 :   return MCDisassembler::Success;
    3325             : }
    3326             : 
    3327          79 : static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
    3328             :                                   uint64_t Address, const void *Decoder) {
    3329             :   DecodeStatus S = MCDisassembler::Success;
    3330             : 
    3331             :   unsigned Rn = fieldFromInstruction(Val, 6, 4);
    3332             :   unsigned Rm = fieldFromInstruction(Val, 2, 4);
    3333             :   unsigned imm = fieldFromInstruction(Val, 0, 2);
    3334             : 
    3335             :   // Thumb stores cannot use PC as dest register.
    3336          79 :   switch (Inst.getOpcode()) {
    3337          14 :   case ARM::t2STRHs:
    3338             :   case ARM::t2STRBs:
    3339             :   case ARM::t2STRs:
    3340          14 :     if (Rn == 15)
    3341             :       return MCDisassembler::Fail;
    3342             :     break;
    3343             :   default:
    3344             :     break;
    3345             :   }
    3346             : 
    3347         142 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3348             :     return MCDisassembler::Fail;
    3349         142 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3350             :     return MCDisassembler::Fail;
    3351         213 :   Inst.addOperand(MCOperand::createImm(imm));
    3352             : 
    3353             :   return S;
    3354             : }
    3355             : 
    3356         105 : static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
    3357             :                               uint64_t Address, const void *Decoder) {
    3358             :   DecodeStatus S = MCDisassembler::Success;
    3359             : 
    3360             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3361             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3362             : 
    3363             :   const FeatureBitset &featureBits =
    3364         105 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3365             : 
    3366             :   bool hasMP = featureBits[ARM::FeatureMP];
    3367             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3368             : 
    3369         105 :   if (Rn == 15) {
    3370          26 :     switch (Inst.getOpcode()) {
    3371             :     case ARM::t2LDRBs:
    3372             :       Inst.setOpcode(ARM::t2LDRBpci);
    3373             :       break;
    3374             :     case ARM::t2LDRHs:
    3375             :       Inst.setOpcode(ARM::t2LDRHpci);
    3376             :       break;
    3377             :     case ARM::t2LDRSHs:
    3378             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3379             :       break;
    3380             :     case ARM::t2LDRSBs:
    3381             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3382             :       break;
    3383             :     case ARM::t2LDRs:
    3384             :       Inst.setOpcode(ARM::t2LDRpci);
    3385             :       break;
    3386             :     case ARM::t2PLDs:
    3387             :       Inst.setOpcode(ARM::t2PLDpci);
    3388             :       break;
    3389             :     case ARM::t2PLIs:
    3390             :       Inst.setOpcode(ARM::t2PLIpci);
    3391             :       break;
    3392             :     default:
    3393             :       return MCDisassembler::Fail;
    3394             :     }
    3395             : 
    3396          26 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3397             :   }
    3398             : 
    3399          79 :   if (Rt == 15) {
    3400          48 :     switch (Inst.getOpcode()) {
    3401             :     case ARM::t2LDRSHs:
    3402             :       return MCDisassembler::Fail;
    3403             :     case ARM::t2LDRHs:
    3404             :       Inst.setOpcode(ARM::t2PLDWs);
    3405             :       break;
    3406             :     case ARM::t2LDRSBs:
    3407             :       Inst.setOpcode(ARM::t2PLIs);
    3408             :       break;
    3409             :     default:
    3410             :       break;
    3411             :     }
    3412             :   }
    3413             : 
    3414          77 :   switch (Inst.getOpcode()) {
    3415             :     case ARM::t2PLDs:
    3416             :       break;
    3417           6 :     case ARM::t2PLIs:
    3418           6 :       if (!hasV7Ops)
    3419             :         return MCDisassembler::Fail;
    3420             :       break;
    3421          17 :     case ARM::t2PLDWs:
    3422          17 :       if (!hasV7Ops || !hasMP)
    3423             :         return MCDisassembler::Fail;
    3424             :       break;
    3425          31 :     default:
    3426          62 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3427             :         return MCDisassembler::Fail;
    3428             :   }
    3429             : 
    3430             :   unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
    3431          65 :   addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
    3432          65 :   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
    3433         130 :   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
    3434             :     return MCDisassembler::Fail;
    3435             : 
    3436             :   return S;
    3437             : }
    3438             : 
    3439          37 : static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
    3440             :                                 uint64_t Address, const void* Decoder) {
    3441             :   DecodeStatus S = MCDisassembler::Success;
    3442             : 
    3443             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3444             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3445             :   unsigned U = fieldFromInstruction(Insn, 9, 1);
    3446             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3447          37 :   imm |= (U << 8);
    3448          37 :   imm |= (Rn << 9);
    3449             :   unsigned add = fieldFromInstruction(Insn, 9, 1);
    3450             : 
    3451             :   const FeatureBitset &featureBits =
    3452          37 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3453             : 
    3454             :   bool hasMP = featureBits[ARM::FeatureMP];
    3455             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3456             : 
    3457          37 :   if (Rn == 15) {
    3458           0 :     switch (Inst.getOpcode()) {
    3459             :     case ARM::t2LDRi8:
    3460             :       Inst.setOpcode(ARM::t2LDRpci);
    3461             :       break;
    3462             :     case ARM::t2LDRBi8:
    3463             :       Inst.setOpcode(ARM::t2LDRBpci);
    3464             :       break;
    3465             :     case ARM::t2LDRSBi8:
    3466             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3467             :       break;
    3468             :     case ARM::t2LDRHi8:
    3469             :       Inst.setOpcode(ARM::t2LDRHpci);
    3470             :       break;
    3471             :     case ARM::t2LDRSHi8:
    3472             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3473             :       break;
    3474             :     case ARM::t2PLDi8:
    3475             :       Inst.setOpcode(ARM::t2PLDpci);
    3476             :       break;
    3477             :     case ARM::t2PLIi8:
    3478             :       Inst.setOpcode(ARM::t2PLIpci);
    3479             :       break;
    3480             :     default:
    3481             :       return MCDisassembler::Fail;
    3482             :     }
    3483           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3484             :   }
    3485             : 
    3486          37 :   if (Rt == 15) {
    3487          30 :     switch (Inst.getOpcode()) {
    3488             :     case ARM::t2LDRSHi8:
    3489             :       return MCDisassembler::Fail;
    3490           6 :     case ARM::t2LDRHi8:
    3491           6 :       if (!add)
    3492             :         Inst.setOpcode(ARM::t2PLDWi8);
    3493             :       break;
    3494             :     case ARM::t2LDRSBi8:
    3495             :       Inst.setOpcode(ARM::t2PLIi8);
    3496             :       break;
    3497             :     default:
    3498             :       break;
    3499             :     }
    3500             :   }
    3501             : 
    3502          33 :   switch (Inst.getOpcode()) {
    3503             :   case ARM::t2PLDi8:
    3504             :     break;
    3505           9 :   case ARM::t2PLIi8:
    3506           9 :     if (!hasV7Ops)
    3507             :       return MCDisassembler::Fail;
    3508             :     break;
    3509           8 :   case ARM::t2PLDWi8:
    3510           8 :       if (!hasV7Ops || !hasMP)
    3511             :         return MCDisassembler::Fail;
    3512             :       break;
    3513           7 :   default:
    3514          14 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3515             :       return MCDisassembler::Fail;
    3516             :   }
    3517             : 
    3518          50 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
    3519             :     return MCDisassembler::Fail;
    3520             :   return S;
    3521             : }
    3522             : 
    3523          88 : static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
    3524             :                                 uint64_t Address, const void* Decoder) {
    3525             :   DecodeStatus S = MCDisassembler::Success;
    3526             : 
    3527             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3528             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3529             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    3530          88 :   imm |= (Rn << 13);
    3531             : 
    3532             :   const FeatureBitset &featureBits =
    3533          88 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3534             : 
    3535             :   bool hasMP = featureBits[ARM::FeatureMP];
    3536             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3537             : 
    3538          88 :   if (Rn == 15) {
    3539          30 :     switch (Inst.getOpcode()) {
    3540             :     case ARM::t2LDRi12:
    3541             :       Inst.setOpcode(ARM::t2LDRpci);
    3542             :       break;
    3543             :     case ARM::t2LDRHi12:
    3544             :       Inst.setOpcode(ARM::t2LDRHpci);
    3545             :       break;
    3546             :     case ARM::t2LDRSHi12:
    3547             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3548             :       break;
    3549             :     case ARM::t2LDRBi12:
    3550             :       Inst.setOpcode(ARM::t2LDRBpci);
    3551             :       break;
    3552             :     case ARM::t2LDRSBi12:
    3553             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3554             :       break;
    3555             :     case ARM::t2PLDi12:
    3556             :       Inst.setOpcode(ARM::t2PLDpci);
    3557             :       break;
    3558             :     case ARM::t2PLIi12:
    3559             :       Inst.setOpcode(ARM::t2PLIpci);
    3560             :       break;
    3561             :     default:
    3562             :       return MCDisassembler::Fail;
    3563             :     }
    3564          30 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3565             :   }
    3566             : 
    3567          58 :   if (Rt == 15) {
    3568          38 :     switch (Inst.getOpcode()) {
    3569             :     case ARM::t2LDRSHi12:
    3570             :       return MCDisassembler::Fail;
    3571             :     case ARM::t2LDRHi12:
    3572             :       Inst.setOpcode(ARM::t2PLDWi12);
    3573             :       break;
    3574             :     case ARM::t2LDRSBi12:
    3575             :       Inst.setOpcode(ARM::t2PLIi12);
    3576             :       break;
    3577             :     default:
    3578             :       break;
    3579             :     }
    3580             :   }
    3581             : 
    3582          54 :   switch (Inst.getOpcode()) {
    3583             :   case ARM::t2PLDi12:
    3584             :     break;
    3585          12 :   case ARM::t2PLIi12:
    3586          12 :     if (!hasV7Ops)
    3587             :       return MCDisassembler::Fail;
    3588             :     break;
    3589           8 :   case ARM::t2PLDWi12:
    3590           8 :       if (!hasV7Ops || !hasMP)
    3591             :         return MCDisassembler::Fail;
    3592             :       break;
    3593          21 :   default:
    3594          42 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3595             :       return MCDisassembler::Fail;
    3596             :   }
    3597             : 
    3598          92 :   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
    3599             :     return MCDisassembler::Fail;
    3600             :   return S;
    3601             : }
    3602             : 
    3603          19 : static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
    3604             :                                 uint64_t Address, const void* Decoder) {
    3605             :   DecodeStatus S = MCDisassembler::Success;
    3606             : 
    3607             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3608             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3609             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3610          19 :   imm |= (Rn << 9);
    3611             : 
    3612          19 :   if (Rn == 15) {
    3613           0 :     switch (Inst.getOpcode()) {
    3614             :     case ARM::t2LDRT:
    3615             :       Inst.setOpcode(ARM::t2LDRpci);
    3616             :       break;
    3617             :     case ARM::t2LDRBT:
    3618             :       Inst.setOpcode(ARM::t2LDRBpci);
    3619             :       break;
    3620             :     case ARM::t2LDRHT:
    3621             :       Inst.setOpcode(ARM::t2LDRHpci);
    3622             :       break;
    3623             :     case ARM::t2LDRSBT:
    3624             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3625             :       break;
    3626             :     case ARM::t2LDRSHT:
    3627             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3628             :       break;
    3629             :     default:
    3630             :       return MCDisassembler::Fail;
    3631             :     }
    3632           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3633             :   }
    3634             : 
    3635          38 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3636             :     return MCDisassembler::Fail;
    3637          38 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
    3638             :     return MCDisassembler::Fail;
    3639             :   return S;
    3640             : }
    3641             : 
    3642          58 : static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
    3643             :                                 uint64_t Address, const void* Decoder) {
    3644             :   DecodeStatus S = MCDisassembler::Success;
    3645             : 
    3646             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3647             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    3648          58 :   int imm = fieldFromInstruction(Insn, 0, 12);
    3649             : 
    3650             :   const FeatureBitset &featureBits =
    3651          58 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3652             : 
    3653             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3654             : 
    3655          58 :   if (Rt == 15) {
    3656          39 :     switch (Inst.getOpcode()) {
    3657             :       case ARM::t2LDRBpci:
    3658             :       case ARM::t2LDRHpci:
    3659             :         Inst.setOpcode(ARM::t2PLDpci);
    3660             :         break;
    3661             :       case ARM::t2LDRSBpci:
    3662             :         Inst.setOpcode(ARM::t2PLIpci);
    3663             :         break;
    3664             :       case ARM::t2LDRSHpci:
    3665             :         return MCDisassembler::Fail;
    3666             :       default:
    3667             :         break;
    3668             :     }
    3669             :   }
    3670             : 
    3671          58 :   switch(Inst.getOpcode()) {
    3672             :   case ARM::t2PLDpci:
    3673             :     break;
    3674          19 :   case ARM::t2PLIpci:
    3675          19 :     if (!hasV7Ops)
    3676             :       return MCDisassembler::Fail;
    3677             :     break;
    3678          19 :   default:
    3679          38 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3680             :       return MCDisassembler::Fail;
    3681             :   }
    3682             : 
    3683          54 :   if (!U) {
    3684             :     // Special case for #-0.
    3685          26 :     if (imm == 0)
    3686             :       imm = INT32_MIN;
    3687             :     else
    3688          19 :       imm = -imm;
    3689             :   }
    3690         162 :   Inst.addOperand(MCOperand::createImm(imm));
    3691             : 
    3692             :   return S;
    3693             : }
    3694             : 
    3695          25 : static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
    3696             :                            uint64_t Address, const void *Decoder) {
    3697          25 :   if (Val == 0)
    3698          12 :     Inst.addOperand(MCOperand::createImm(INT32_MIN));
    3699             :   else {
    3700          19 :     int imm = Val & 0xFF;
    3701             : 
    3702          19 :     if (!(Val & 0x100)) imm *= -1;
    3703          57 :     Inst.addOperand(MCOperand::createImm(imm * 4));
    3704             :   }
    3705             : 
    3706          25 :   return MCDisassembler::Success;
    3707             : }
    3708             : 
    3709          17 : static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
    3710             :                                    uint64_t Address, const void *Decoder) {
    3711             :   DecodeStatus S = MCDisassembler::Success;
    3712             : 
    3713             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    3714             :   unsigned imm = fieldFromInstruction(Val, 0, 9);
    3715             : 
    3716          34 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3717             :     return MCDisassembler::Fail;
    3718          34 :   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
    3719             :     return MCDisassembler::Fail;
    3720             : 
    3721             :   return S;
    3722             : }
    3723             : 
    3724           7 : static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
    3725             :                                    uint64_t Address, const void *Decoder) {
    3726             :   DecodeStatus S = MCDisassembler::Success;
    3727             : 
    3728             :   unsigned Rn = fieldFromInstruction(Val, 8, 4);
    3729             :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    3730             : 
    3731          14 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    3732             :     return MCDisassembler::Fail;
    3733             : 
    3734          21 :   Inst.addOperand(MCOperand::createImm(imm));
    3735             : 
    3736             :   return S;
    3737             : }
    3738             : 
    3739         993 : static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
    3740             :                          uint64_t Address, const void *Decoder) {
    3741         993 :   int imm = Val & 0xFF;
    3742         993 :   if (Val == 0)
    3743             :     imm = INT32_MIN;
    3744         992 :   else if (!(Val & 0x100))
    3745          38 :     imm *= -1;
    3746        2979 :   Inst.addOperand(MCOperand::createImm(imm));
    3747             : 
    3748         993 :   return MCDisassembler::Success;
    3749             : }
    3750             : 
    3751        1005 : static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
    3752             :                                  uint64_t Address, const void *Decoder) {
    3753             :   DecodeStatus S = MCDisassembler::Success;
    3754             : 
    3755             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    3756             :   unsigned imm = fieldFromInstruction(Val, 0, 9);
    3757             : 
    3758             :   // Thumb stores cannot use PC as dest register.
    3759        1005 :   switch (Inst.getOpcode()) {
    3760          21 :   case ARM::t2STRT:
    3761             :   case ARM::t2STRBT:
    3762             :   case ARM::t2STRHT:
    3763             :   case ARM::t2STRi8:
    3764             :   case ARM::t2STRHi8:
    3765             :   case ARM::t2STRBi8:
    3766          21 :     if (Rn == 15)
    3767             :       return MCDisassembler::Fail;
    3768             :     break;
    3769             :   default:
    3770             :     break;
    3771             :   }
    3772             : 
    3773             :   // Some instructions always use an additive offset.
    3774         993 :   switch (Inst.getOpcode()) {
    3775          27 :     case ARM::t2LDRT:
    3776             :     case ARM::t2LDRBT:
    3777             :     case ARM::t2LDRHT:
    3778             :     case ARM::t2LDRSBT:
    3779             :     case ARM::t2LDRSHT:
    3780             :     case ARM::t2STRT:
    3781             :     case ARM::t2STRBT:
    3782             :     case ARM::t2STRHT:
    3783          27 :       imm |= 0x100;
    3784             :       break;
    3785             :     default:
    3786             :       break;
    3787             :   }
    3788             : 
    3789        1986 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3790             :     return MCDisassembler::Fail;
    3791        1986 :   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
    3792             :     return MCDisassembler::Fail;
    3793             : 
    3794             :   return S;
    3795             : }
    3796             : 
    3797         942 : static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
    3798             :                                     uint64_t Address, const void *Decoder) {
    3799             :   DecodeStatus S = MCDisassembler::Success;
    3800             : 
    3801             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3802             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3803             :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    3804         942 :   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
    3805         942 :   addr |= Rn << 9;
    3806             :   unsigned load = fieldFromInstruction(Insn, 20, 1);
    3807             : 
    3808         942 :   if (Rn == 15) {
    3809           2 :     switch (Inst.getOpcode()) {
    3810             :     case ARM::t2LDR_PRE:
    3811             :     case ARM::t2LDR_POST:
    3812             :       Inst.setOpcode(ARM::t2LDRpci);
    3813             :       break;
    3814             :     case ARM::t2LDRB_PRE:
    3815             :     case ARM::t2LDRB_POST:
    3816             :       Inst.setOpcode(ARM::t2LDRBpci);
    3817             :       break;
    3818             :     case ARM::t2LDRH_PRE:
    3819             :     case ARM::t2LDRH_POST:
    3820             :       Inst.setOpcode(ARM::t2LDRHpci);
    3821             :       break;
    3822           0 :     case ARM::t2LDRSB_PRE:
    3823             :     case ARM::t2LDRSB_POST:
    3824           0 :       if (Rt == 15)
    3825             :         Inst.setOpcode(ARM::t2PLIpci);
    3826             :       else
    3827             :         Inst.setOpcode(ARM::t2LDRSBpci);
    3828             :       break;
    3829             :     case ARM::t2LDRSH_PRE:
    3830             :     case ARM::t2LDRSH_POST:
    3831             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3832             :       break;
    3833             :     default:
    3834             :       return MCDisassembler::Fail;
    3835             :     }
    3836           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3837             :   }
    3838             : 
    3839         940 :   if (!load) {
    3840         910 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3841             :       return MCDisassembler::Fail;
    3842             :   }
    3843             : 
    3844        1880 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3845             :     return MCDisassembler::Fail;
    3846             : 
    3847         940 :   if (load) {
    3848         970 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3849             :       return MCDisassembler::Fail;
    3850             :   }
    3851             : 
    3852        1880 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
    3853             :     return MCDisassembler::Fail;
    3854             : 
    3855             :   return S;
    3856             : }
    3857             : 
    3858          56 : static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
    3859             :                                   uint64_t Address, const void *Decoder) {
    3860             :   DecodeStatus S = MCDisassembler::Success;
    3861             : 
    3862             :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    3863             :   unsigned imm = fieldFromInstruction(Val, 0, 12);
    3864             : 
    3865             :   // Thumb stores cannot use PC as dest register.
    3866          56 :   switch (Inst.getOpcode()) {
    3867          10 :   case ARM::t2STRi12:
    3868             :   case ARM::t2STRBi12:
    3869             :   case ARM::t2STRHi12:
    3870          10 :     if (Rn == 15)
    3871             :       return MCDisassembler::Fail;
    3872             :     break;
    3873             :   default:
    3874             :     break;
    3875             :   }
    3876             : 
    3877         104 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3878             :     return MCDisassembler::Fail;
    3879         156 :   Inst.addOperand(MCOperand::createImm(imm));
    3880             : 
    3881             :   return S;
    3882             : }
    3883             : 
    3884         465 : static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
    3885             :                                 uint64_t Address, const void *Decoder) {
    3886             :   unsigned imm = fieldFromInstruction(Insn, 0, 7);
    3887             : 
    3888         930 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3889         930 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3890        1395 :   Inst.addOperand(MCOperand::createImm(imm));
    3891             : 
    3892         465 :   return MCDisassembler::Success;
    3893             : }
    3894             : 
    3895          20 : static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
    3896             :                                 uint64_t Address, const void *Decoder) {
    3897             :   DecodeStatus S = MCDisassembler::Success;
    3898             : 
    3899          20 :   if (Inst.getOpcode() == ARM::tADDrSP) {
    3900           5 :     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
    3901           5 :     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
    3902             : 
    3903          10 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
    3904             :     return MCDisassembler::Fail;
    3905          10 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3906          10 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
    3907             :     return MCDisassembler::Fail;
    3908          15 :   } else if (Inst.getOpcode() == ARM::tADDspr) {
    3909          15 :     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
    3910             : 
    3911          30 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3912          30 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3913          30 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3914             :     return MCDisassembler::Fail;
    3915             :   }
    3916             : 
    3917             :   return S;
    3918             : }
    3919             : 
    3920           1 : static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
    3921             :                            uint64_t Address, const void *Decoder) {
    3922           1 :   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
    3923             :   unsigned flags = fieldFromInstruction(Insn, 0, 3);
    3924             : 
    3925           3 :   Inst.addOperand(MCOperand::createImm(imod));
    3926           3 :   Inst.addOperand(MCOperand::createImm(flags));
    3927             : 
    3928           1 :   return MCDisassembler::Success;
    3929             : }
    3930             : 
    3931          15 : static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
    3932             :                              uint64_t Address, const void *Decoder) {
    3933             :   DecodeStatus S = MCDisassembler::Success;
    3934             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3935             :   unsigned add = fieldFromInstruction(Insn, 4, 1);
    3936             : 
    3937          30 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    3938             :     return MCDisassembler::Fail;
    3939          45 :   Inst.addOperand(MCOperand::createImm(add));
    3940             : 
    3941             :   return S;
    3942             : }
    3943             : 
    3944          28 : static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
    3945             :                                  uint64_t Address, const void *Decoder) {
    3946             :   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
    3947             :   // Note only one trailing zero not two.  Also the J1 and J2 values are from
    3948             :   // the encoded instruction.  So here change to I1 and I2 values via:
    3949             :   // I1 = NOT(J1 EOR S);
    3950             :   // I2 = NOT(J2 EOR S);
    3951             :   // and build the imm32 with two trailing zeros as documented:
    3952             :   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
    3953          28 :   unsigned S = (Val >> 23) & 1;
    3954          28 :   unsigned J1 = (Val >> 22) & 1;
    3955          28 :   unsigned J2 = (Val >> 21) & 1;
    3956          28 :   unsigned I1 = !(J1 ^ S);
    3957          28 :   unsigned I2 = !(J2 ^ S);
    3958          28 :   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
    3959             :   int imm32 = SignExtend32<25>(tmp << 1);
    3960             : 
    3961          28 :   if (!tryAddingSymbolicOperand(Address,
    3962          28 :                                 (Address & ~2u) + imm32 + 4,
    3963             :                                 true, 4, Inst, Decoder))
    3964          66 :     Inst.addOperand(MCOperand::createImm(imm32));
    3965          28 :   return MCDisassembler::Success;
    3966             : }
    3967             : 
    3968         164 : static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
    3969             :                               uint64_t Address, const void *Decoder) {
    3970         164 :   if (Val == 0xA || Val == 0xB)
    3971             :     return MCDisassembler::Fail;
    3972             : 
    3973             :   const FeatureBitset &featureBits =
    3974         118 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3975             : 
    3976         118 :   if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
    3977             :     return MCDisassembler::Fail;
    3978             : 
    3979         306 :   Inst.addOperand(MCOperand::createImm(Val));
    3980             :   return MCDisassembler::Success;
    3981             : }
    3982             : 
    3983             : static DecodeStatus
    3984           6 : DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
    3985             :                        uint64_t Address, const void *Decoder) {
    3986             :   DecodeStatus S = MCDisassembler::Success;
    3987             : 
    3988             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3989             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3990             : 
    3991           6 :   if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
    3992          12 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3993             :     return MCDisassembler::Fail;
    3994          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3995             :     return MCDisassembler::Fail;
    3996             :   return S;
    3997             : }
    3998             : 
    3999             : static DecodeStatus
    4000          32 : DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
    4001             :                            uint64_t Address, const void *Decoder) {
    4002             :   DecodeStatus S = MCDisassembler::Success;
    4003             : 
    4004             :   unsigned pred = fieldFromInstruction(Insn, 22, 4);
    4005          32 :   if (pred == 0xE || pred == 0xF) {
    4006             :     unsigned opc = fieldFromInstruction(Insn, 4, 28);
    4007           8 :     switch (opc) {
    4008             :       default:
    4009             :         return MCDisassembler::Fail;
    4010             :       case 0xf3bf8f4:
    4011             :         Inst.setOpcode(ARM::t2DSB);
    4012             :         break;
    4013             :       case 0xf3bf8f5:
    4014             :         Inst.setOpcode(ARM::t2DMB);
    4015             :         break;
    4016             :       case 0xf3bf8f6:
    4017             :         Inst.setOpcode(ARM::t2ISB);
    4018             :         break;
    4019             :     }
    4020             : 
    4021             :     unsigned imm = fieldFromInstruction(Insn, 0, 4);
    4022           0 :     return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
    4023             :   }
    4024             : 
    4025          24 :   unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
    4026          24 :   brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
    4027          24 :   brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
    4028          24 :   brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
    4029          24 :   brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
    4030             : 
    4031          48 :   if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
    4032             :     return MCDisassembler::Fail;
    4033          48 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4034             :     return MCDisassembler::Fail;
    4035             : 
    4036          24 :   return S;
    4037             : }
    4038             : 
    4039             : // Decode a shifted immediate operand.  These basically consist
    4040             : // of an 8-bit value, and a 4-bit directive that specifies either
    4041             : // a splat operation or a rotation.
    4042         251 : static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
    4043             :                           uint64_t Address, const void *Decoder) {
    4044             :   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
    4045         251 :   if (ctrl == 0) {
    4046             :     unsigned byte = fieldFromInstruction(Val, 8, 2);
    4047             :     unsigned imm = fieldFromInstruction(Val, 0, 8);
    4048         163 :     switch (byte) {
    4049         152 :       case 0:
    4050         456 :         Inst.addOperand(MCOperand::createImm(imm));
    4051             :         break;
    4052           3 :       case 1:
    4053           9 :         Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
    4054             :         break;
    4055           3 :       case 2:
    4056           9 :         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
    4057             :         break;
    4058           5 :       case 3:
    4059          20 :         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
    4060          10 :                                              (imm << 8)  |  imm));
    4061             :         break;
    4062             :     }
    4063             :   } else {
    4064          88 :     unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
    4065             :     unsigned rot = fieldFromInstruction(Val, 7, 5);
    4066          88 :     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
    4067         264 :     Inst.addOperand(MCOperand::createImm(imm));
    4068             :   }
    4069             : 
    4070         251 :   return MCDisassembler::Success;
    4071             : }
    4072             : 
    4073             : static DecodeStatus
    4074         150 : DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
    4075             :                             uint64_t Address, const void *Decoder) {
    4076         300 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
    4077             :                                 true, 2, Inst, Decoder))
    4078         450 :     Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
    4079         150 :   return MCDisassembler::Success;
    4080             : }
    4081             : 
    4082         281 : static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
    4083             :                                                uint64_t Address,
    4084             :                                                const void *Decoder) {
    4085             :   // Val is passed in as S:J1:J2:imm10:imm11
    4086             :   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
    4087             :   // the encoded instruction.  So here change to I1 and I2 values via:
    4088             :   // I1 = NOT(J1 EOR S);
    4089             :   // I2 = NOT(J2 EOR S);
    4090             :   // and build the imm32 with one trailing zero as documented:
    4091             :   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
    4092         281 :   unsigned S = (Val >> 23) & 1;
    4093         281 :   unsigned J1 = (Val >> 22) & 1;
    4094         281 :   unsigned J2 = (Val >> 21) & 1;
    4095         281 :   unsigned I1 = !(J1 ^ S);
    4096         281 :   unsigned I2 = !(J2 ^ S);
    4097         281 :   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
    4098             :   int imm32 = SignExtend32<25>(tmp << 1);
    4099             : 
    4100         562 :   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
    4101             :                                 true, 4, Inst, Decoder))
    4102         834 :     Inst.addOperand(MCOperand::createImm(imm32));
    4103         281 :   return MCDisassembler::Success;
    4104             : }
    4105             : 
    4106             : static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
    4107             :                                    uint64_t Address, const void *Decoder) {
    4108             :   if (Val & ~0xf)
    4109             :     return MCDisassembler::Fail;
    4110             : 
    4111         246 :   Inst.addOperand(MCOperand::createImm(Val));
    4112             :   return MCDisassembler::Success;
    4113             : }
    4114             : 
    4115             : static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
    4116             :                                         uint64_t Address, const void *Decoder) {
    4117             :   if (Val & ~0xf)
    4118             :     return MCDisassembler::Fail;
    4119             : 
    4120          18 :   Inst.addOperand(MCOperand::createImm(Val));
    4121             :   return MCDisassembler::Success;
    4122             : }
    4123             : 
    4124         115 : static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
    4125             :                           uint64_t Address, const void *Decoder) {
    4126             :   DecodeStatus S = MCDisassembler::Success;
    4127             :   const FeatureBitset &FeatureBits =
    4128         115 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    4129             : 
    4130         115 :   if (FeatureBits[ARM::FeatureMClass]) {
    4131          63 :     unsigned ValLow = Val & 0xff;
    4132             : 
    4133             :     // Validate the SYSm value first.
    4134          63 :     switch (ValLow) {
    4135             :     case  0: // apsr
    4136             :     case  1: // iapsr
    4137             :     case  2: // eapsr
    4138             :     case  3: // xpsr
    4139             :     case  5: // ipsr
    4140             :     case  6: // epsr
    4141             :     case  7: // iepsr
    4142             :     case  8: // msp
    4143             :     case  9: // psp
    4144             :     case 16: // primask
    4145             :     case 20: // control
    4146             :       break;
    4147           6 :     case 17: // basepri
    4148             :     case 18: // basepri_max
    4149             :     case 19: // faultmask
    4150           6 :       if (!(FeatureBits[ARM::HasV7Ops]))
    4151             :         // Values basepri, basepri_max and faultmask are only valid for v7m.
    4152             :         return MCDisassembler::Fail;
    4153             :       break;
    4154           3 :     case 0x8a: // msplim_ns
    4155             :     case 0x8b: // psplim_ns
    4156             :     case 0x91: // basepri_ns
    4157             :     case 0x93: // faultmask_ns
    4158           3 :       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
    4159             :         return MCDisassembler::Fail;
    4160             :       LLVM_FALLTHROUGH;
    4161             :     case 10:   // msplim
    4162             :     case 11:   // psplim
    4163             :     case 0x88: // msp_ns
    4164             :     case 0x89: // psp_ns
    4165             :     case 0x90: // primask_ns
    4166             :     case 0x94: // control_ns
    4167             :     case 0x98: // sp_ns
    4168          14 :       if (!(FeatureBits[ARM::Feature8MSecExt]))
    4169             :         return MCDisassembler::Fail;
    4170             :       break;
    4171           4 :     default:
    4172             :       // Architecturally defined as unpredictable
    4173             :       S = MCDisassembler::SoftFail;
    4174             :       break;
    4175             :     }
    4176             : 
    4177          62 :     if (Inst.getOpcode() == ARM::t2MSR_M) {
    4178             :       unsigned Mask = fieldFromInstruction(Val, 10, 2);
    4179          39 :       if (!(FeatureBits[ARM::HasV7Ops])) {
    4180             :         // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
    4181             :         // unpredictable.
    4182           3 :         if (Mask != 2)
    4183             :           S = MCDisassembler::SoftFail;
    4184             :       }
    4185             :       else {
    4186             :         // The ARMv7-M architecture stores an additional 2-bit mask value in
    4187             :         // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
    4188             :         // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
    4189             :         // the NZCVQ bits should be moved by the instruction. Bit mask{0}
    4190             :         // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
    4191             :         // only if the processor includes the DSP extension.
    4192          68 :         if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
    4193           7 :             (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
    4194             :           S = MCDisassembler::SoftFail;
    4195             :       }
    4196             :     }
    4197             :   } else {
    4198             :     // A/R class
    4199          52 :     if (Val == 0)
    4200             :       return MCDisassembler::Fail;
    4201             :   }
    4202         330 :   Inst.addOperand(MCOperand::createImm(Val));
    4203             :   return S;
    4204             : }
    4205             : 
    4206         138 : static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
    4207             :                                     uint64_t Address, const void *Decoder) {
    4208             :   unsigned R = fieldFromInstruction(Val, 5, 1);
    4209             :   unsigned SysM = fieldFromInstruction(Val, 0, 5);
    4210             : 
    4211             :   // The table of encodings for these banked registers comes from B9.2.3 of the
    4212             :   // ARM ARM. There are patterns, but nothing regular enough to make this logic
    4213             :   // neater. So by fiat, these values are UNPREDICTABLE:
    4214         138 :   if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
    4215             :     return MCDisassembler::Fail;
    4216             : 
    4217         396 :   Inst.addOperand(MCOperand::createImm(Val));
    4218             :   return MCDisassembler::Success;
    4219             : }
    4220             : 
    4221           7 : static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
    4222             :                                         uint64_t Address, const void *Decoder) {
    4223             :   DecodeStatus S = MCDisassembler::Success;
    4224             : 
    4225             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4226             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4227             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4228             : 
    4229           7 :   if (Rn == 0xF)
    4230             :     S = MCDisassembler::SoftFail;
    4231             : 
    4232          14 :   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
    4233             :     return MCDisassembler::Fail;
    4234          14 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4235             :     return MCDisassembler::Fail;
    4236          14 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4237             :     return MCDisassembler::Fail;
    4238             : 
    4239             :   return S;
    4240             : }
    4241             : 
    4242           8 : static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
    4243             :                                          uint64_t Address,
    4244             :                                          const void *Decoder) {
    4245             :   DecodeStatus S = MCDisassembler::Success;
    4246             : 
    4247             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4248             :   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
    4249             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4250             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4251             : 
    4252          16 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    4253             :     return MCDisassembler::Fail;
    4254             : 
    4255           8 :   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
    4256             :     S = MCDisassembler::SoftFail;
    4257             : 
    4258          16 :   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
    4259             :     return MCDisassembler::Fail;
    4260          16 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4261             :     return MCDisassembler::Fail;
    4262          16 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4263             :     return MCDisassembler::Fail;
    4264             : 
    4265             :   return S;
    4266             : }
    4267             : 
    4268          47 : static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
    4269             :                             uint64_t Address, const void *Decoder) {
    4270             :   DecodeStatus S = MCDisassembler::Success;
    4271             : 
    4272             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4273             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4274             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4275          47 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4276          47 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4277             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4278             : 
    4279          47 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4280             : 
    4281          94 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4282             :     return MCDisassembler::Fail;
    4283          94 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4284             :     return MCDisassembler::Fail;
    4285          94 :   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
    4286             :     return MCDisassembler::Fail;
    4287          94 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4288             :     return MCDisassembler::Fail;
    4289             : 
    4290          47 :   return S;
    4291             : }
    4292             : 
    4293           9 : static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
    4294             :                             uint64_t Address, const void *Decoder) {
    4295             :   DecodeStatus S = MCDisassembler::Success;
    4296             : 
    4297             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4298             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4299             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4300           9 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4301           9 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4302             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4303             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4304             : 
    4305           9 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4306           9 :   if (Rm == 0xF) S = MCDisassembler::SoftFail;
    4307             : 
    4308          18 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4309             :     return MCDisassembler::Fail;
    4310          18 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4311             :     return MCDisassembler::Fail;
    4312          18 :   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
    4313             :     return MCDisassembler::Fail;
    4314          18 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4315             :     return MCDisassembler::Fail;
    4316             : 
    4317             :   return S;
    4318             : }
    4319             : 
    4320          18 : static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
    4321             :                             uint64_t Address, const void *Decoder) {
    4322             :   DecodeStatus S = MCDisassembler::Success;
    4323             : 
    4324             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4325             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4326             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4327          18 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4328          18 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4329             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4330             : 
    4331          18 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4332             : 
    4333          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4334             :     return MCDisassembler::Fail;
    4335          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4336             :     return MCDisassembler::Fail;
    4337          36 :   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
    4338             :     return MCDisassembler::Fail;
    4339          36 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4340             :     return MCDisassembler::Fail;
    4341             : 
    4342          18 :   return S;
    4343             : }
    4344             : 
    4345           5 : static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
    4346             :                             uint64_t Address, const void *Decoder) {
    4347             :   DecodeStatus S = MCDisassembler::Success;
    4348             : 
    4349             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4350             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4351             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4352           5 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4353           5 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4354             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4355             : 
    4356           5 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4357             : 
    4358          10 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4359             :     return MCDisassembler::Fail;
    4360          10 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4361             :     return MCDisassembler::Fail;
    4362          10 :   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
    4363             :     return MCDisassembler::Fail;
    4364          10 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4365             :     return MCDisassembler::Fail;
    4366             : 
    4367             :   return S;
    4368             : }
    4369             : 
    4370          36 : static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
    4371             :                          uint64_t Address, const void *Decoder) {
    4372             :   DecodeStatus S = MCDisassembler::Success;
    4373             : 
    4374             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4375             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4376             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4377          36 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4378             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4379             : 
    4380             :   unsigned align = 0;
    4381             :   unsigned index = 0;
    4382          36 :   switch (size) {
    4383             :     default:
    4384             :       return MCDisassembler::Fail;
    4385             :     case 0:
    4386          12 :       if (fieldFromInstruction(Insn, 4, 1))
    4387             :         return MCDisassembler::Fail; // UNDEFINED
    4388             :       index = fieldFromInstruction(Insn, 5, 3);
    4389          12 :       break;
    4390             :     case 1:
    4391          16 :       if (fieldFromInstruction(Insn, 5, 1))
    4392             :         return MCDisassembler::Fail; // UNDEFINED
    4393             :       index = fieldFromInstruction(Insn, 6, 2);
    4394          16 :       if (fieldFromInstruction(Insn, 4, 1))
    4395             :         align = 2;
    4396             :       break;
    4397             :     case 2:
    4398           8 :       if (fieldFromInstruction(Insn, 6, 1))
    4399             :         return MCDisassembler::Fail; // UNDEFINED
    4400             :       index = fieldFromInstruction(Insn, 7, 1);
    4401             : 
    4402           8 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4403             :         case 0 :
    4404             :           align = 0; break;
    4405           4 :         case 3:
    4406           4 :           align = 4; break;
    4407             :         default:
    4408             :           return MCDisassembler::Fail;
    4409             :       }
    4410             :       break;
    4411             :   }
    4412             : 
    4413          68 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4414             :     return MCDisassembler::Fail;
    4415          34 :   if (Rm != 0xF) { // Writeback
    4416          52 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4417             :       return MCDisassembler::Fail;
    4418             :   }
    4419          68 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4420             :     return MCDisassembler::Fail;
    4421         102 :   Inst.addOperand(MCOperand::createImm(align));
    4422          34 :   if (Rm != 0xF) {
    4423          26 :     if (Rm != 0xD) {
    4424          48 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4425             :         return MCDisassembler::Fail;
    4426             :     } else
    4427           4 :       Inst.addOperand(MCOperand::createReg(0));
    4428             :   }
    4429             : 
    4430          68 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4431             :     return MCDisassembler::Fail;
    4432         102 :   Inst.addOperand(MCOperand::createImm(index));
    4433             : 
    4434          34 :   return S;
    4435             : }
    4436             : 
    4437          30 : static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
    4438             :                          uint64_t Address, const void *Decoder) {
    4439             :   DecodeStatus S = MCDisassembler::Success;
    4440             : 
    4441             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4442             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4443             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4444          30 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4445             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4446             : 
    4447             :   unsigned align = 0;
    4448             :   unsigned index = 0;
    4449          30 :   switch (size) {
    4450             :     default:
    4451             :       return MCDisassembler::Fail;
    4452             :     case 0:
    4453          10 :       if (fieldFromInstruction(Insn, 4, 1))
    4454             :         return MCDisassembler::Fail; // UNDEFINED
    4455             :       index = fieldFromInstruction(Insn, 5, 3);
    4456          10 :       break;
    4457             :     case 1:
    4458          14 :       if (fieldFromInstruction(Insn, 5, 1))
    4459             :         return MCDisassembler::Fail; // UNDEFINED
    4460             :       index = fieldFromInstruction(Insn, 6, 2);
    4461          14 :       if (fieldFromInstruction(Insn, 4, 1))
    4462             :         align = 2;
    4463             :       break;
    4464             :     case 2:
    4465           6 :       if (fieldFromInstruction(Insn, 6, 1))
    4466             :         return MCDisassembler::Fail; // UNDEFINED
    4467             :       index = fieldFromInstruction(Insn, 7, 1);
    4468             : 
    4469           6 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4470             :         case 0: 
    4471             :           align = 0; break;
    4472           2 :         case 3:
    4473           2 :           align = 4; break;
    4474             :         default:
    4475             :           return MCDisassembler::Fail;
    4476             :       }
    4477             :       break;
    4478             :   }
    4479             : 
    4480          28 :   if (Rm != 0xF) { // Writeback
    4481          52 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4482             :     return MCDisassembler::Fail;
    4483             :   }
    4484          56 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4485             :     return MCDisassembler::Fail;
    4486          84 :   Inst.addOperand(MCOperand::createImm(align));
    4487          28 :   if (Rm != 0xF) {
    4488          26 :     if (Rm != 0xD) {
    4489          48 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4490             :     return MCDisassembler::Fail;
    4491             :     } else
    4492           4 :       Inst.addOperand(MCOperand::createReg(0));
    4493             :   }
    4494             : 
    4495          56 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4496             :     return MCDisassembler::Fail;
    4497          84 :   Inst.addOperand(MCOperand::createImm(index));
    4498             : 
    4499          28 :   return S;
    4500             : }
    4501             : 
    4502          10 : static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
    4503             :                          uint64_t Address, const void *Decoder) {
    4504             :   DecodeStatus S = MCDisassembler::Success;
    4505             : 
    4506             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4507             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4508             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4509          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4510             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4511             : 
    4512             :   unsigned align = 0;
    4513             :   unsigned index = 0;
    4514             :   unsigned inc = 1;
    4515          10 :   switch (size) {
    4516             :     default:
    4517             :       return MCDisassembler::Fail;
    4518             :     case 0:
    4519             :       index = fieldFromInstruction(Insn, 5, 3);
    4520           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4521             :         align = 2;
    4522             :       break;
    4523             :     case 1:
    4524             :       index = fieldFromInstruction(Insn, 6, 2);
    4525           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4526             :         align = 4;
    4527           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4528             :         inc = 2;
    4529             :       break;
    4530             :     case 2:
    4531           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4532             :         return MCDisassembler::Fail; // UNDEFINED
    4533             :       index = fieldFromInstruction(Insn, 7, 1);
    4534           4 :       if (fieldFromInstruction(Insn, 4, 1) != 0)
    4535             :         align = 8;
    4536           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4537             :         inc = 2;
    4538             :       break;
    4539             :   }
    4540             : 
    4541          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4542             :     return MCDisassembler::Fail;
    4543          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4544             :     return MCDisassembler::Fail;
    4545          10 :   if (Rm != 0xF) { // Writeback
    4546           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4547             :       return MCDisassembler::Fail;
    4548             :   }
    4549          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4550             :     return MCDisassembler::Fail;
    4551          30 :   Inst.addOperand(MCOperand::createImm(align));
    4552          10 :   if (Rm != 0xF) {
    4553           0 :     if (Rm != 0xD) {
    4554           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4555             :         return MCDisassembler::Fail;
    4556             :     } else
    4557           0 :       Inst.addOperand(MCOperand::createReg(0));
    4558             :   }
    4559             : 
    4560          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4561             :     return MCDisassembler::Fail;
    4562          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4563             :     return MCDisassembler::Fail;
    4564          30 :   Inst.addOperand(MCOperand::createImm(index));
    4565             : 
    4566          10 :   return S;
    4567             : }
    4568             : 
    4569          10 : static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
    4570             :                          uint64_t Address, const void *Decoder) {
    4571             :   DecodeStatus S = MCDisassembler::Success;
    4572             : 
    4573             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4574             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4575             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4576          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4577             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4578             : 
    4579             :   unsigned align = 0;
    4580             :   unsigned index = 0;
    4581             :   unsigned inc = 1;
    4582          10 :   switch (size) {
    4583             :     default:
    4584             :       return MCDisassembler::Fail;
    4585             :     case 0:
    4586             :       index = fieldFromInstruction(Insn, 5, 3);
    4587           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4588             :         align = 2;
    4589             :       break;
    4590             :     case 1:
    4591             :       index = fieldFromInstruction(Insn, 6, 2);
    4592           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4593             :         align = 4;
    4594           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4595             :         inc = 2;
    4596             :       break;
    4597             :     case 2:
    4598           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4599             :         return MCDisassembler::Fail; // UNDEFINED
    4600             :       index = fieldFromInstruction(Insn, 7, 1);
    4601           4 :       if (fieldFromInstruction(Insn, 4, 1) != 0)
    4602             :         align = 8;
    4603           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4604             :         inc = 2;
    4605             :       break;
    4606             :   }
    4607             : 
    4608          10 :   if (Rm != 0xF) { // Writeback
    4609           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4610             :       return MCDisassembler::Fail;
    4611             :   }
    4612          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4613             :     return MCDisassembler::Fail;
    4614          30 :   Inst.addOperand(MCOperand::createImm(align));
    4615          10 :   if (Rm != 0xF) {
    4616           0 :     if (Rm != 0xD) {
    4617           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4618             :         return MCDisassembler::Fail;
    4619             :     } else
    4620           0 :       Inst.addOperand(MCOperand::createReg(0));
    4621             :   }
    4622             : 
    4623          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4624             :     return MCDisassembler::Fail;
    4625          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4626             :     return MCDisassembler::Fail;
    4627          30 :   Inst.addOperand(MCOperand::createImm(index));
    4628             : 
    4629          10 :   return S;
    4630             : }
    4631             : 
    4632          10 : static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
    4633             :                          uint64_t Address, const void *Decoder) {
    4634             :   DecodeStatus S = MCDisassembler::Success;
    4635             : 
    4636             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4637             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4638             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4639          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4640             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4641             : 
    4642             :   unsigned align = 0;
    4643             :   unsigned index = 0;
    4644             :   unsigned inc = 1;
    4645          10 :   switch (size) {
    4646             :     default:
    4647             :       return MCDisassembler::Fail;
    4648             :     case 0:
    4649           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4650             :         return MCDisassembler::Fail; // UNDEFINED
    4651             :       index = fieldFromInstruction(Insn, 5, 3);
    4652           2 :       break;
    4653             :     case 1:
    4654           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4655             :         return MCDisassembler::Fail; // UNDEFINED
    4656             :       index = fieldFromInstruction(Insn, 6, 2);
    4657           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4658             :         inc = 2;
    4659             :       break;
    4660             :     case 2:
    4661           4 :       if (fieldFromInstruction(Insn, 4, 2))
    4662             :         return MCDisassembler::Fail; // UNDEFINED
    4663             :       index = fieldFromInstruction(Insn, 7, 1);
    4664           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4665             :         inc = 2;
    4666             :       break;
    4667             :   }
    4668             : 
    4669          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4670             :     return MCDisassembler::Fail;
    4671          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4672             :     return MCDisassembler::Fail;
    4673          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4674             :     return MCDisassembler::Fail;
    4675             : 
    4676          10 :   if (Rm != 0xF) { // Writeback
    4677           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4678             :     return MCDisassembler::Fail;
    4679             :   }
    4680          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4681             :     return MCDisassembler::Fail;
    4682          20 :   Inst.addOperand(MCOperand::createImm(align));
    4683          10 :   if (Rm != 0xF) {
    4684           0 :     if (Rm != 0xD) {
    4685           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4686             :     return MCDisassembler::Fail;
    4687             :     } else
    4688           0 :       Inst.addOperand(MCOperand::createReg(0));
    4689             :   }
    4690             : 
    4691          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4692             :     return MCDisassembler::Fail;
    4693          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4694             :     return MCDisassembler::Fail;
    4695          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4696             :     return MCDisassembler::Fail;
    4697          30 :   Inst.addOperand(MCOperand::createImm(index));
    4698             : 
    4699          10 :   return S;
    4700             : }
    4701             : 
    4702          10 : static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
    4703             :                          uint64_t Address, const void *Decoder) {
    4704             :   DecodeStatus S = MCDisassembler::Success;
    4705             : 
    4706             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4707             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4708             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4709          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4710             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4711             : 
    4712             :   unsigned align = 0;
    4713             :   unsigned index = 0;
    4714             :   unsigned inc = 1;
    4715          10 :   switch (size) {
    4716             :     default:
    4717             :       return MCDisassembler::Fail;
    4718             :     case 0:
    4719           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4720             :         return MCDisassembler::Fail; // UNDEFINED
    4721             :       index = fieldFromInstruction(Insn, 5, 3);
    4722           2 :       break;
    4723             :     case 1:
    4724           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4725             :         return MCDisassembler::Fail; // UNDEFINED
    4726             :       index = fieldFromInstruction(Insn, 6, 2);
    4727           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4728             :         inc = 2;
    4729             :       break;
    4730             :     case 2:
    4731           4 :       if (fieldFromInstruction(Insn, 4, 2))
    4732             :         return MCDisassembler::Fail; // UNDEFINED
    4733             :       index = fieldFromInstruction(Insn, 7, 1);
    4734           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4735             :         inc = 2;
    4736             :       break;
    4737             :   }
    4738             : 
    4739          10 :   if (Rm != 0xF) { // Writeback
    4740           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4741             :     return MCDisassembler::Fail;
    4742             :   }
    4743          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4744             :     return MCDisassembler::Fail;
    4745          20 :   Inst.addOperand(MCOperand::createImm(align));
    4746          10 :   if (Rm != 0xF) {
    4747           0 :     if (Rm != 0xD) {
    4748           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4749             :     return MCDisassembler::Fail;
    4750             :     } else
    4751           0 :       Inst.addOperand(MCOperand::createReg(0));
    4752             :   }
    4753             : 
    4754          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4755             :     return MCDisassembler::Fail;
    4756          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4757             :     return MCDisassembler::Fail;
    4758          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4759             :     return MCDisassembler::Fail;
    4760          30 :   Inst.addOperand(MCOperand::createImm(index));
    4761             : 
    4762          10 :   return S;
    4763             : }
    4764             : 
    4765          15 : static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
    4766             :                          uint64_t Address, const void *Decoder) {
    4767             :   DecodeStatus S = MCDisassembler::Success;
    4768             : 
    4769             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4770             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4771             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4772          15 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4773             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4774             : 
    4775             :   unsigned align = 0;
    4776             :   unsigned index = 0;
    4777             :   unsigned inc = 1;
    4778          15 :   switch (size) {
    4779             :     default:
    4780             :       return MCDisassembler::Fail;
    4781             :     case 0:
    4782           3 :       if (fieldFromInstruction(Insn, 4, 1))
    4783             :         align = 4;
    4784             :       index = fieldFromInstruction(Insn, 5, 3);
    4785           3 :       break;
    4786             :     case 1:
    4787           5 :       if (fieldFromInstruction(Insn, 4, 1))
    4788             :         align = 8;
    4789             :       index = fieldFromInstruction(Insn, 6, 2);
    4790           5 :       if (fieldFromInstruction(Insn, 5, 1))
    4791             :         inc = 2;
    4792             :       break;
    4793             :     case 2:
    4794           7 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4795             :         case 0:
    4796             :           align = 0; break;
    4797             :         case 3:
    4798             :           return MCDisassembler::Fail;
    4799             :         default:
    4800           3 :           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
    4801             :       }
    4802             : 
    4803             :       index = fieldFromInstruction(Insn, 7, 1);
    4804           5 :       if (fieldFromInstruction(Insn, 6, 1))
    4805             :         inc = 2;
    4806             :       break;
    4807             :   }
    4808             : 
    4809          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4810             :     return MCDisassembler::Fail;
    4811          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4812             :     return MCDisassembler::Fail;
    4813          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4814             :     return MCDisassembler::Fail;
    4815          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4816             :     return MCDisassembler::Fail;
    4817             : 
    4818          13 :   if (Rm != 0xF) { // Writeback
    4819           6 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4820             :       return MCDisassembler::Fail;
    4821             :   }
    4822          26 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4823             :     return MCDisassembler::Fail;
    4824          39 :   Inst.addOperand(MCOperand::createImm(align));
    4825          13 :   if (Rm != 0xF) {
    4826           3 :     if (Rm != 0xD) {
    4827           6 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4828             :         return MCDisassembler::Fail;
    4829             :     } else
    4830           0 :       Inst.addOperand(MCOperand::createReg(0));
    4831             :   }
    4832             : 
    4833          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4834             :     return MCDisassembler::Fail;
    4835          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4836             :     return MCDisassembler::Fail;
    4837          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4838             :     return MCDisassembler::Fail;
    4839          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4840             :     return MCDisassembler::Fail;
    4841          39 :   Inst.addOperand(MCOperand::createImm(index));
    4842             : 
    4843          13 :   return S;
    4844             : }
    4845             : 
    4846          16 : static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
    4847             :                          uint64_t Address, const void *Decoder) {
    4848             :   DecodeStatus S = MCDisassembler::Success;
    4849             : 
    4850             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4851             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4852             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4853          16 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4854             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4855             : 
    4856             :   unsigned align = 0;
    4857             :   unsigned index = 0;
    4858             :   unsigned inc = 1;
    4859          16 :   switch (size) {
    4860             :     default:
    4861             :       return MCDisassembler::Fail;
    4862             :     case 0:
    4863           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4864             :         align = 4;
    4865             :       index = fieldFromInstruction(Insn, 5, 3);
    4866           4 :       break;
    4867             :     case 1:
    4868           5 :       if (fieldFromInstruction(Insn, 4, 1))
    4869             :         align = 8;
    4870             :       index = fieldFromInstruction(Insn, 6, 2);
    4871           5 :       if (fieldFromInstruction(Insn, 5, 1))
    4872             :         inc = 2;
    4873             :       break;
    4874             :     case 2:
    4875           7 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4876             :         case 0:
    4877             :           align = 0; break;
    4878             :         case 3:
    4879             :           return MCDisassembler::Fail;
    4880             :         default:
    4881           3 :           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
    4882             :       }
    4883             : 
    4884             :       index = fieldFromInstruction(Insn, 7, 1);
    4885           5 :       if (fieldFromInstruction(Insn, 6, 1))
    4886             :         inc = 2;
    4887             :       break;
    4888             :   }
    4889             : 
    4890          14 :   if (Rm != 0xF) { // Writeback
    4891           8 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4892             :     return MCDisassembler::Fail;
    4893             :   }
    4894          28 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4895             :     return MCDisassembler::Fail;
    4896          42 :   Inst.addOperand(MCOperand::createImm(align));
    4897          14 :   if (Rm != 0xF) {
    4898           4 :     if (Rm != 0xD) {
    4899           6 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4900             :     return MCDisassembler::Fail;
    4901             :     } else
    4902           2 :       Inst.addOperand(MCOperand::createReg(0));
    4903             :   }
    4904             : 
    4905          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4906             :     return MCDisassembler::Fail;
    4907          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4908             :     return MCDisassembler::Fail;
    4909          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4910             :     return MCDisassembler::Fail;
    4911          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4912             :     return MCDisassembler::Fail;
    4913          42 :   Inst.addOperand(MCOperand::createImm(index));
    4914             : 
    4915          14 :   return S;
    4916             : }
    4917             : 
    4918           2 : static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
    4919             :                                   uint64_t Address, const void *Decoder) {
    4920             :   DecodeStatus S = MCDisassembler::Success;
    4921             :   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
    4922             :   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
    4923             :   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
    4924             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4925           2 :   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
    4926             : 
    4927           2 :   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
    4928             :     S = MCDisassembler::SoftFail;
    4929             : 
    4930           4 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
    4931             :     return MCDisassembler::Fail;
    4932           4 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
    4933             :     return MCDisassembler::Fail;
    4934           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
    4935             :     return MCDisassembler::Fail;
    4936           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
    4937             :     return MCDisassembler::Fail;
    4938           4 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4939             :     return MCDisassembler::Fail;
    4940             : 
    4941             :   return S;
    4942             : }
    4943             : 
    4944           3 : static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
    4945             :                                   uint64_t Address, const void *Decoder) {
    4946             :   DecodeStatus S = MCDisassembler::Success;
    4947             :   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
    4948             :   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
    4949             :   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
    4950             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4951           3 :   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
    4952             : 
    4953           3 :   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
    4954             :     S = MCDisassembler::SoftFail;
    4955             : 
    4956           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
    4957             :     return MCDisassembler::Fail;
    4958           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
    4959             :     return MCDisassembler::Fail;
    4960           6 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
    4961             :     return MCDisassembler::Fail;
    4962           6 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
    4963             :     return MCDisassembler::Fail;
    4964           6 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4965             :     return MCDisassembler::Fail;
    4966             : 
    4967             :   return S;
    4968             : }
    4969             : 
    4970         139 : static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
    4971             :                              uint64_t Address, const void *Decoder) {
    4972             :   DecodeStatus S = MCDisassembler::Success;
    4973             :   unsigned pred = fieldFromInstruction(Insn, 4, 4);
    4974             :   unsigned mask = fieldFromInstruction(Insn, 0, 4);
    4975             : 
    4976         139 :   if (pred == 0xF) {
    4977             :     pred = 0xE;
    4978             :     S = MCDisassembler::SoftFail;
    4979             :   }
    4980             : 
    4981         139 :   if (mask == 0x0)
    4982             :     return MCDisassembler::Fail;
    4983             : 
    4984         417 :   Inst.addOperand(MCOperand::createImm(pred));
    4985         417 :   Inst.addOperand(MCOperand::createImm(mask));
    4986             :   return S;
    4987             : }
    4988             : 
    4989             : static DecodeStatus
    4990           6 : DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
    4991             :                            uint64_t Address, const void *Decoder) {
    4992             :   DecodeStatus S = MCDisassembler::Success;
    4993             : 
    4994             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4995             :   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
    4996             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4997             :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    4998             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    4999             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    5000             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    5001           6 :   bool writeback = (W == 1) | (P == 0);
    5002             : 
    5003           6 :   addr |= (U << 8) | (Rn << 9);
    5004             : 
    5005           6 :   if (writeback && (Rn == Rt || Rn == Rt2))
    5006             :     Check(S, MCDisassembler::SoftFail);
    5007           6 :   if (Rt == Rt2)
    5008             :     Check(S, MCDisassembler::SoftFail);
    5009             : 
    5010             :   // Rt
    5011          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    5012             :     return MCDisassembler::Fail;
    5013             :   // Rt2
    5014          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
    5015             :     return MCDisassembler::Fail;
    5016             :   // Writeback operand
    5017          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
    5018             :     return MCDisassembler::Fail;
    5019             :   // addr
    5020          12 :   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
    5021             :     return MCDisassembler::Fail;
    5022             : 
    5023             :   return S;
    5024             : }
    5025             : 
    5026             : static DecodeStatus
    5027           4 : DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
    5028             :                            uint64_t Address, const void *Decoder) {
    5029             :   DecodeStatus S = MCDisassembler::Success;
    5030             : 
    5031             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    5032             :   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
    5033             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    5034             :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    5035             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    5036             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    5037             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    5038           4 :   bool writeback = (W == 1) | (P == 0);
    5039             : 
    5040           4 :   addr |= (U << 8) | (Rn << 9);
    5041             : 
    5042           4 :   if (writeback && (Rn == Rt || Rn == Rt2))
    5043             :     Check(S, MCDisassembler::SoftFail);
    5044             : 
    5045             :   // Writeback operand
    5046           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
    5047             :     return MCDisassembler::Fail;
    5048             :   // Rt
    5049           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    5050             :     return MCDisassembler::Fail;
    5051             :   // Rt2
    5052           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
    5053             :     return MCDisassembler::Fail;
    5054             :   // addr
    5055           8 :   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
    5056             :     return MCDisassembler::Fail;
    5057             : 
    5058             :   return S;
    5059             : }
    5060             : 
    5061           0 : static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
    5062             :                                 uint64_t Address, const void *Decoder) {
    5063             :   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
    5064             :   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
    5065           0 :   if (sign1 != sign2) return MCDisassembler::Fail;
    5066             : 
    5067             :   unsigned Val = fieldFromInstruction(Insn, 0, 8);
    5068           0 :   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
    5069           0 :   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
    5070           0 :   Val |= sign1 << 12;
    5071           0 :   Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
    5072             : 
    5073             :   return MCDisassembler::Success;
    5074             : }
    5075             : 
    5076             : static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
    5077             :                                               uint64_t Address,
    5078             :                                               const void *Decoder) {
    5079             :   DecodeStatus S = MCDisassembler::Success;
    5080             : 
    5081             :   // Shift of "asr #32" is not allowed in Thumb2 mode.
    5082           6 :   if (Val == 0x20) S = MCDisassembler::Fail;
    5083          18 :   Inst.addOperand(MCOperand::createImm(Val));
    5084             :   return S;
    5085             : }
    5086             : 
    5087          11 : static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
    5088             :                                uint64_t Address, const void *Decoder) {
    5089             :   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
    5090             :   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
    5091             :   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
    5092             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    5093             : 
    5094          11 :   if (pred == 0xF)
    5095           1 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    5096             : 
    5097             :   DecodeStatus S = MCDisassembler::Success;
    5098             : 
    5099          10 :   if (Rt == Rn || Rn == Rt2)
    5100             :     S = MCDisassembler::SoftFail;
    5101             : 
    5102          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5103             :     return MCDisassembler::Fail;
    5104          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5105             :     return MCDisassembler::Fail;
    5106          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    5107             :     return MCDisassembler::Fail;
    5108          20 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    5109             :     return MCDisassembler::Fail;
    5110             : 
    5111             :   return S;
    5112             : }
    5113             : 
    5114          30 : static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
    5115             :                                 uint64_t Address, const void *Decoder) {
    5116             :   const FeatureBitset &featureBits =
    5117          30 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5118             :   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
    5119             : 
    5120             :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5121          30 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5122             :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5123          30 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5124             :   unsigned imm = fieldFromInstruction(Insn, 16, 6);
    5125             :   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
    5126             :   unsigned op = fieldFromInstruction(Insn, 5, 1);
    5127             : 
    5128             :   DecodeStatus S = MCDisassembler::Success;
    5129             : 
    5130             :   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
    5131          30 :   if (!(imm & 0x38)) {
    5132           8 :     if (cmode == 0xF) {
    5133           4 :       if (op == 1) return MCDisassembler::Fail;
    5134             :       Inst.setOpcode(ARM::VMOVv2f32);
    5135             :     }
    5136           7 :     if (hasFullFP16) {
    5137           6 :       if (cmode == 0xE) {
    5138           0 :         if (op == 1) {
    5139             :           Inst.setOpcode(ARM::VMOVv1i64);
    5140             :         } else {
    5141             :           Inst.setOpcode(ARM::VMOVv8i8);
    5142             :         }
    5143             :       }
    5144           6 :       if (cmode == 0xD) {
    5145           2 :         if (op == 1) {
    5146             :           Inst.setOpcode(ARM::VMVNv2i32);
    5147             :         } else {
    5148             :           Inst.setOpcode(ARM::VMOVv2i32);
    5149             :         }
    5150             :       }
    5151           6 :       if (cmode == 0xC) {
    5152           2 :         if (op == 1) {
    5153             :           Inst.setOpcode(ARM::VMVNv2i32);
    5154             :         } else {
    5155             :           Inst.setOpcode(ARM::VMOVv2i32);
    5156             :         }
    5157             :       }
    5158             :     }
    5159           7 :     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
    5160             :   }
    5161             : 
    5162          22 :   if (!(imm & 0x20)) return MCDisassembler::Fail;
    5163             : 
    5164          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
    5165             :     return MCDisassembler::Fail;
    5166          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
    5167             :     return MCDisassembler::Fail;
    5168          60 :   Inst.addOperand(MCOperand::createImm(64 - imm));
    5169             : 
    5170          20 :   return S;
    5171             : }
    5172             : 
    5173          37 : static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
    5174             :                                 uint64_t Address, const void *Decoder) {
    5175             :   const FeatureBitset &featureBits =
    5176          37 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5177             :   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
    5178             : 
    5179             :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5180          37 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5181             :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5182          37 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5183             :   unsigned imm = fieldFromInstruction(Insn, 16, 6);
    5184             :   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
    5185             :   unsigned op = fieldFromInstruction(Insn, 5, 1);
    5186             : 
    5187             :   DecodeStatus S = MCDisassembler::Success;
    5188             : 
    5189             :   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
    5190          37 :   if (!(imm & 0x38)) {
    5191          16 :     if (cmode == 0xF) {
    5192           8 :       if (op == 1) return MCDisassembler::Fail;
    5193             :       Inst.setOpcode(ARM::VMOVv4f32);
    5194             :     }
    5195          11 :     if (hasFullFP16) {
    5196          10 :       if (cmode == 0xE) {
    5197           0 :         if (op == 1) {
    5198             :           Inst.setOpcode(ARM::VMOVv2i64);
    5199             :         } else {
    5200             :           Inst.setOpcode(ARM::VMOVv16i8);
    5201             :         }
    5202             :       }
    5203          10 :       if (cmode == 0xD) {
    5204           4 :         if (op == 1) {
    5205             :           Inst.setOpcode(ARM::VMVNv4i32);
    5206             :         } else {
    5207             :           Inst.setOpcode(ARM::VMOVv4i32);
    5208             :         }
    5209             :       }
    5210          10 :       if (cmode == 0xC) {
    5211           4 :         if (op == 1) {
    5212             :           Inst.setOpcode(ARM::VMVNv4i32);
    5213             :         } else {
    5214             :           Inst.setOpcode(ARM::VMOVv4i32);
    5215             :         }
    5216             :       }
    5217             :     }
    5218          11 :     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
    5219             :   }
    5220             : 
    5221          21 :   if (!(imm & 0x20)) return MCDisassembler::Fail;
    5222             : 
    5223          42 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
    5224             :     return MCDisassembler::Fail;
    5225          42 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
    5226             :     return MCDisassembler::Fail;
    5227          63 :   Inst.addOperand(MCOperand::createImm(64 - imm));
    5228             : 
    5229          21 :   return S;
    5230             : }
    5231             : 
    5232          20 : static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
    5233             :                                                        unsigned Insn,
    5234             :                                                        uint64_t Address,
    5235             :                                                        const void *Decoder) {
    5236             :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5237          20 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5238             :   unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
    5239          20 :   Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
    5240             :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5241          20 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5242             :   unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
    5243             :   unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
    5244             : 
    5245             :   DecodeStatus S = MCDisassembler::Success;
    5246             : 
    5247          20 :   auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
    5248             : 
    5249          40 :   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
    5250             :     return MCDisassembler::Fail;
    5251          40 :   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
    5252             :     return MCDisassembler::Fail;
    5253          40 :   if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
    5254             :     return MCDisassembler::Fail;
    5255          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
    5256             :     return MCDisassembler::Fail;
    5257             :   // The lane index does not have any bits in the encoding, because it can only
    5258             :   // be 0.
    5259          40 :   Inst.addOperand(MCOperand::createImm(0));
    5260          60 :   Inst.addOperand(MCOperand::createImm(rotate));
    5261             : 
    5262          20 :   return S;
    5263             : }
    5264             : 
    5265          13 : static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
    5266             :                                 uint64_t Address, const void *Decoder) {
    5267             :   DecodeStatus S = MCDisassembler::Success;
    5268             : 
    5269             :   unsigned Rn = fieldFromInstruction(Val, 16, 4);
    5270             :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5271             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    5272          13 :   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
    5273             :   unsigned Cond = fieldFromInstruction(Val, 28, 4);
    5274             : 
    5275          13 :   if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
    5276             :     S = MCDisassembler::SoftFail;
    5277             : 
    5278          26 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5279             :     return MCDisassembler::Fail;
    5280          26 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    5281             :     return MCDisassembler::Fail;
    5282          13 :   if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 
    5283             :     return MCDisassembler::Fail;
    5284          26 :   if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
    5285             :     return MCDisassembler::Fail;
    5286          26 :   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
    5287             :     return MCDisassembler::Fail;
    5288             : 
    5289             :   return S;
    5290             : }
    5291             : 
    5292          10 : static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
    5293             :                                             uint64_t Address, const void *Decoder) {
    5294             :   DecodeStatus S = MCDisassembler::Success;
    5295             : 
    5296             :   unsigned CRm = fieldFromInstruction(Val, 0, 4);
    5297             :   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
    5298             :   unsigned cop = fieldFromInstruction(Val, 8, 4);
    5299             :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5300             :   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
    5301             : 
    5302          10 :   if ((cop & ~0x1) == 0xa)
    5303             :     return MCDisassembler::Fail;
    5304             : 
    5305           9 :   if (Rt == Rt2)
    5306             :     S = MCDisassembler::SoftFail;
    5307             : 
    5308             :   // We have to check if the instruction is MRRC2
    5309             :   // or MCRR2 when constructing the operands for
    5310             :   // Inst. Reason is because MRRC2 stores to two
    5311             :   // registers so it's tablegen desc has has two
    5312             :   // outputs whereas MCRR doesn't store to any
    5313             :   // registers so all of it's operands are listed
    5314             :   // as inputs, therefore the operand order for
    5315             :   // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
    5316             :   // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
    5317             : 
    5318           9 :   if (Inst.getOpcode() == ARM::MRRC2) {
    5319          10 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5320             :       return MCDisassembler::Fail;
    5321          10 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5322             :       return MCDisassembler::Fail;
    5323             :   }
    5324          27 :   Inst.addOperand(MCOperand::createImm(cop));
    5325          27 :   Inst.addOperand(MCOperand::createImm(opc1));
    5326           9 :   if (Inst.getOpcode() == ARM::MCRR2) {
    5327           8 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5328             :       return MCDisassembler::Fail;
    5329           8 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5330             :       return MCDisassembler::Fail;
    5331             :   }
    5332          27 :   Inst.addOperand(MCOperand::createImm(CRm));
    5333             : 
    5334             :   return S;
    5335             : }
    5336             : 
    5337         125 : static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
    5338             :                                          uint64_t Address,
    5339             :                                          const void *Decoder) {
    5340             :   const FeatureBitset &featureBits =
    5341         125 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5342             :   DecodeStatus S = MCDisassembler::Success;
    5343             : 
    5344             :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5345             : 
    5346         191 :   if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
    5347          49 :     if (Rt == 13 || Rt == 15)
    5348             :       S = MCDisassembler::SoftFail;
    5349          49 :     Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
    5350             :   } else
    5351          76 :     Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
    5352             : 
    5353         125 :   if (featureBits[ARM::ModeThumb]) {
    5354         132 :     Inst.addOperand(MCOperand::createImm(ARMCC::AL));
    5355         132 :     Inst.addOperand(MCOperand::createReg(0));
    5356             :   } else {
    5357             :     unsigned pred = fieldFromInstruction(Val, 28, 4);
    5358         118 :     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    5359             :       return MCDisassembler::Fail;
    5360             :   }
    5361             : 
    5362             :   return S;
    5363             : }

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