LCOV - code coverage report
Current view: top level - lib/Target/ARM/Disassembler - ARMDisassembler.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 1340 1393 96.2 %
Date: 2018-02-19 03:08:00 Functions: 125 127 98.4 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA ---------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "MCTargetDesc/ARMAddressingModes.h"
      11             : #include "MCTargetDesc/ARMBaseInfo.h"
      12             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      13             : #include "Utils/ARMBaseInfo.h"
      14             : #include "llvm/MC/MCContext.h"
      15             : #include "llvm/MC/MCDisassembler/MCDisassembler.h"
      16             : #include "llvm/MC/MCFixedLenDisassembler.h"
      17             : #include "llvm/MC/MCInst.h"
      18             : #include "llvm/MC/MCInstrDesc.h"
      19             : #include "llvm/MC/MCSubtargetInfo.h"
      20             : #include "llvm/MC/SubtargetFeature.h"
      21             : #include "llvm/Support/Compiler.h"
      22             : #include "llvm/Support/ErrorHandling.h"
      23             : #include "llvm/Support/MathExtras.h"
      24             : #include "llvm/Support/TargetRegistry.h"
      25             : #include "llvm/Support/raw_ostream.h"
      26             : #include <algorithm>
      27             : #include <cassert>
      28             : #include <cstdint>
      29             : #include <vector>
      30             : 
      31             : using namespace llvm;
      32             : 
      33             : #define DEBUG_TYPE "arm-disassembler"
      34             : 
      35             : using DecodeStatus = MCDisassembler::DecodeStatus;
      36             : 
      37             : namespace {
      38             : 
      39             :   // Handles the condition code status of instructions in IT blocks
      40         204 :   class ITStatus
      41             :   {
      42             :     public:
      43             :       // Returns the condition code for instruction in IT block
      44             :       unsigned getITCC() {
      45             :         unsigned CC = ARMCC::AL;
      46       11000 :         if (instrInITBlock())
      47         216 :           CC = ITStates.back();
      48             :         return CC;
      49             :       }
      50             : 
      51             :       // Advances the IT block state to the next T or E
      52             :       void advanceITState() {
      53             :         ITStates.pop_back();
      54             :       }
      55             : 
      56             :       // Returns true if the current instruction is in an IT block
      57             :       bool instrInITBlock() {
      58        2438 :         return !ITStates.empty();
      59             :       }
      60             : 
      61             :       // Returns true if current instruction is the last instruction in an IT block
      62             :       bool instrLastInITBlock() {
      63             :         return ITStates.size() == 1;
      64             :       }
      65             : 
      66             :       // Called when decoding an IT instruction. Sets the IT state for the following
      67             :       // instructions that for the IT block. Firstcond and Mask correspond to the
      68             :       // fields in the IT instruction encoding.
      69         131 :       void setITState(char Firstcond, char Mask) {
      70             :         // (3 - the number of trailing zeros) is the number of then / else.
      71         131 :         unsigned CondBit0 = Firstcond & 1;
      72         262 :         unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
      73         131 :         unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
      74             :         assert(NumTZ <= 3 && "Invalid IT mask!");
      75             :         // push condition codes onto the stack the correct order for the pops
      76         221 :         for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
      77          90 :           bool T = ((Mask >> Pos) & 1) == CondBit0;
      78          90 :           if (T)
      79          34 :             ITStates.push_back(CCBits);
      80             :           else
      81         112 :             ITStates.push_back(CCBits ^ 1);
      82             :         }
      83         131 :         ITStates.push_back(CCBits);
      84         131 :       }
      85             : 
      86             :     private:
      87             :       std::vector<unsigned char> ITStates;
      88             :   };
      89             : 
      90             : /// ARM disassembler for all ARM platforms.
      91             : class ARMDisassembler : public MCDisassembler {
      92             : public:
      93             :   ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
      94         169 :     MCDisassembler(STI, Ctx) {
      95             :   }
      96             : 
      97         169 :   ~ARMDisassembler() override = default;
      98             : 
      99             :   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
     100             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
     101             :                               raw_ostream &VStream,
     102             :                               raw_ostream &CStream) const override;
     103             : };
     104             : 
     105             : /// Thumb disassembler for all Thumb platforms.
     106             : class ThumbDisassembler : public MCDisassembler {
     107             : public:
     108         204 :   ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
     109         204 :     MCDisassembler(STI, Ctx) {
     110             :   }
     111             : 
     112         612 :   ~ThumbDisassembler() override = default;
     113             : 
     114             :   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
     115             :                               ArrayRef<uint8_t> Bytes, uint64_t Address,
     116             :                               raw_ostream &VStream,
     117             :                               raw_ostream &CStream) const override;
     118             : 
     119             : private:
     120             :   mutable ITStatus ITBlock;
     121             : 
     122             :   DecodeStatus AddThumbPredicate(MCInst&) const;
     123             :   void UpdateThumbVFPPredicate(MCInst&) const;
     124             : };
     125             : 
     126             : } // end anonymous namespace
     127             : 
     128             : static bool Check(DecodeStatus &Out, DecodeStatus In) {
     129       83240 :   switch (In) {
     130             :     case MCDisassembler::Success:
     131             :       // Out stays the same.
     132             :       return true;
     133         142 :     case MCDisassembler::SoftFail:
     134             :       Out = In;
     135             :       return true;
     136        1982 :     case MCDisassembler::Fail:
     137             :       Out = In;
     138             :       return false;
     139             :   }
     140           0 :   llvm_unreachable("Invalid DecodeStatus!");
     141             : }
     142             : 
     143             : // Forward declare these because the autogenerated code will reference them.
     144             : // Definitions are further down.
     145             : static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     146             :                                    uint64_t Address, const void *Decoder);
     147             : static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
     148             :                                                unsigned RegNo, uint64_t Address,
     149             :                                                const void *Decoder);
     150             : static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
     151             :                                                unsigned RegNo, uint64_t Address,
     152             :                                                const void *Decoder);
     153             : static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     154             :                                    uint64_t Address, const void *Decoder);
     155             : static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     156             :                                    uint64_t Address, const void *Decoder);
     157             : static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     158             :                                    uint64_t Address, const void *Decoder);
     159             : static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
     160             :                                    uint64_t Address, const void *Decoder);
     161             : static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
     162             :                                    uint64_t Address, const void *Decoder);
     163             : static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
     164             :                                    uint64_t Address, const void *Decoder);
     165             : static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
     166             :                                    uint64_t Address, const void *Decoder);
     167             : static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
     168             :                                    uint64_t Address, const void *Decoder);
     169             : static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
     170             :                                                 unsigned RegNo,
     171             :                                                 uint64_t Address,
     172             :                                                 const void *Decoder);
     173             : static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
     174             :                                    uint64_t Address, const void *Decoder);
     175             : static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
     176             :                                    uint64_t Address, const void *Decoder);
     177             : static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
     178             :                                unsigned RegNo, uint64_t Address,
     179             :                                const void *Decoder);
     180             : 
     181             : static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
     182             :                                uint64_t Address, const void *Decoder);
     183             : static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
     184             :                                uint64_t Address, const void *Decoder);
     185             : static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
     186             :                                uint64_t Address, const void *Decoder);
     187             : static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
     188             :                                uint64_t Address, const void *Decoder);
     189             : static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
     190             :                                uint64_t Address, const void *Decoder);
     191             : 
     192             : static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
     193             :                                uint64_t Address, const void *Decoder);
     194             : static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
     195             :                                uint64_t Address, const void *Decoder);
     196             : static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
     197             :                                                   unsigned Insn,
     198             :                                                   uint64_t Address,
     199             :                                                   const void *Decoder);
     200             : static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
     201             :                                uint64_t Address, const void *Decoder);
     202             : static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
     203             :                                uint64_t Address, const void *Decoder);
     204             : static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
     205             :                                uint64_t Address, const void *Decoder);
     206             : static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
     207             :                                uint64_t Address, const void *Decoder);
     208             : 
     209             : static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
     210             :                                                   unsigned Insn,
     211             :                                                   uint64_t Adddress,
     212             :                                                   const void *Decoder);
     213             : static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
     214             :                                uint64_t Address, const void *Decoder);
     215             : static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
     216             :                                uint64_t Address, const void *Decoder);
     217             : static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
     218             :                                uint64_t Address, const void *Decoder);
     219             : static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
     220             :                                uint64_t Address, const void *Decoder);
     221             : static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
     222             :                                uint64_t Address, const void *Decoder);
     223             : static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
     224             :                                uint64_t Address, const void *Decoder);
     225             : static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
     226             :                                uint64_t Address, const void *Decoder);
     227             : static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
     228             :                                uint64_t Address, const void *Decoder);
     229             : static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
     230             :                                uint64_t Address, const void *Decoder);
     231             : static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
     232             :                                uint64_t Address, const void *Decoder);
     233             : static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
     234             :                                uint64_t Address, const void *Decoder);
     235             : static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
     236             :                                uint64_t Address, const void *Decoder);
     237             : static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
     238             :                                uint64_t Address, const void *Decoder);
     239             : static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
     240             :                                uint64_t Address, const void *Decoder);
     241             : static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
     242             :                                uint64_t Address, const void *Decoder);
     243             : static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
     244             :                                uint64_t Address, const void *Decoder);
     245             : static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
     246             :                                uint64_t Address, const void *Decoder);
     247             : static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
     248             :                                uint64_t Address, const void *Decoder);
     249             : static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
     250             :                                uint64_t Address, const void *Decoder);
     251             : static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
     252             :                                uint64_t Address, const void *Decoder);
     253             : static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
     254             :                                uint64_t Address, const void *Decoder);
     255             : static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
     256             :                                uint64_t Address, const void *Decoder);
     257             : static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
     258             :                                uint64_t Address, const void *Decoder);
     259             : static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
     260             :                                uint64_t Address, const void *Decoder);
     261             : static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
     262             :                                uint64_t Address, const void *Decoder);
     263             : static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
     264             :                                uint64_t Address, const void *Decoder);
     265             : static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
     266             :                                uint64_t Address, const void *Decoder);
     267             : static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
     268             :                                uint64_t Address, const void *Decoder);
     269             : static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
     270             :                                uint64_t Address, const void *Decoder);
     271             : static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
     272             :                                uint64_t Address, const void *Decoder);
     273             : static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
     274             :                                uint64_t Address, const void *Decoder);
     275             : static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
     276             :                                uint64_t Address, const void *Decoder);
     277             : static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
     278             :                                uint64_t Address, const void *Decoder);
     279             : static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
     280             :                                uint64_t Address, const void *Decoder);
     281             : static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
     282             :                                uint64_t Address, const void *Decoder);
     283             : static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
     284             :                                uint64_t Address, const void *Decoder);
     285             : static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
     286             :                                uint64_t Address, const void *Decoder);
     287             : static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
     288             :                                uint64_t Address, const void *Decoder);
     289             : static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
     290             :                                uint64_t Address, const void *Decoder);
     291             : static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
     292             :                                uint64_t Address, const void *Decoder);
     293             : static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
     294             :                                uint64_t Address, const void *Decoder);
     295             : static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
     296             :                                uint64_t Address, const void *Decoder);
     297             : static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
     298             :                                uint64_t Address, const void *Decoder);
     299             : static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
     300             :                                uint64_t Address, const void *Decoder);
     301             : static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
     302             :                                uint64_t Address, const void *Decoder);
     303             : static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
     304             :                                uint64_t Address, const void *Decoder);
     305             : static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
     306             :                                uint64_t Address, const void *Decoder);
     307             : static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
     308             :                                uint64_t Address, const void *Decoder);
     309             : static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
     310             :                                uint64_t Address, const void *Decoder);
     311             : static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
     312             :                                uint64_t Address, const void *Decoder);
     313             : static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
     314             :                                uint64_t Address, const void *Decoder);
     315             : static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
     316             :                                uint64_t Address, const void *Decoder);
     317             : static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
     318             :                                uint64_t Address, const void *Decoder);
     319             : static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
     320             :                                uint64_t Address, const void *Decoder);
     321             : static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
     322             :                                uint64_t Address, const void *Decoder);
     323             : static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
     324             :                                 uint64_t Address, const void *Decoder);
     325             : static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
     326             :                                 uint64_t Address, const void *Decoder);
     327             : static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
     328             :                                                        unsigned Val,
     329             :                                                        uint64_t Address,
     330             :                                                        const void *Decoder);
     331             : 
     332             : static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
     333             :                                uint64_t Address, const void *Decoder);
     334             : static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
     335             :                                uint64_t Address, const void *Decoder);
     336             : static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
     337             :                                uint64_t Address, const void *Decoder);
     338             : static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
     339             :                                uint64_t Address, const void *Decoder);
     340             : static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
     341             :                                uint64_t Address, const void *Decoder);
     342             : static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
     343             :                                uint64_t Address, const void *Decoder);
     344             : static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
     345             :                                uint64_t Address, const void *Decoder);
     346             : static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
     347             :                                uint64_t Address, const void *Decoder);
     348             : static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
     349             :                                uint64_t Address, const void *Decoder);
     350             : static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
     351             :                                uint64_t Address, const void *Decoder);
     352             : static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
     353             :                                uint64_t Address, const void* Decoder);
     354             : static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
     355             :                                uint64_t Address, const void* Decoder);
     356             : static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
     357             :                                uint64_t Address, const void* Decoder);
     358             : static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
     359             :                                uint64_t Address, const void* Decoder);
     360             : static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
     361             :                                uint64_t Address, const void *Decoder);
     362             : static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
     363             :                                uint64_t Address, const void *Decoder);
     364             : static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
     365             :                                uint64_t Address, const void *Decoder);
     366             : static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
     367             :                                uint64_t Address, const void *Decoder);
     368             : static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
     369             :                                uint64_t Address, const void *Decoder);
     370             : static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
     371             :                                uint64_t Address, const void *Decoder);
     372             : static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
     373             :                                 uint64_t Address, const void *Decoder);
     374             : static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
     375             :                                 uint64_t Address, const void *Decoder);
     376             : static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
     377             :                                 uint64_t Address, const void *Decoder);
     378             : static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
     379             :                                 uint64_t Address, const void *Decoder);
     380             : static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
     381             :                                 uint64_t Address, const void *Decoder);
     382             : static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
     383             :                                 uint64_t Address, const void *Decoder);
     384             : static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
     385             :                                 uint64_t Address, const void *Decoder);
     386             : static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
     387             :                                 uint64_t Address, const void *Decoder);
     388             : static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
     389             :                                 uint64_t Address, const void *Decoder);
     390             : static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
     391             :                                 uint64_t Address, const void *Decoder);
     392             : static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
     393             :                                 uint64_t Address, const void *Decoder);
     394             : static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
     395             :                                uint64_t Address, const void *Decoder);
     396             : static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
     397             :                                uint64_t Address, const void *Decoder);
     398             : static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
     399             :                                 uint64_t Address, const void *Decoder);
     400             : static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
     401             :                                 uint64_t Address, const void *Decoder);
     402             : static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
     403             :                                 uint64_t Address, const void *Decoder);
     404             : 
     405             : static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
     406             :                                 uint64_t Address, const void *Decoder);
     407             : static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
     408             :                                             uint64_t Address, const void *Decoder);
     409             : static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
     410             :                                          uint64_t Address, const void *Decoder);
     411             : 
     412             : #include "ARMGenDisassemblerTables.inc"
     413             : 
     414         169 : static MCDisassembler *createARMDisassembler(const Target &T,
     415             :                                              const MCSubtargetInfo &STI,
     416             :                                              MCContext &Ctx) {
     417         338 :   return new ARMDisassembler(STI, Ctx);
     418             : }
     419             : 
     420         204 : static MCDisassembler *createThumbDisassembler(const Target &T,
     421             :                                                const MCSubtargetInfo &STI,
     422             :                                                MCContext &Ctx) {
     423         408 :   return new ThumbDisassembler(STI, Ctx);
     424             : }
     425             : 
     426             : // Post-decoding checks
     427             : static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
     428             :                                             uint64_t Address, raw_ostream &OS,
     429             :                                             raw_ostream &CS,
     430             :                                             uint32_t Insn,
     431             :                                             DecodeStatus Result) {
     432        5331 :   switch (MI.getOpcode()) {
     433           7 :     case ARM::HVC: {
     434             :       // HVC is undefined if condition = 0xf otherwise upredictable
     435             :       // if condition != 0xe
     436           7 :       uint32_t Cond = (Insn >> 28) & 0xF;
     437           7 :       if (Cond == 0xF)
     438             :         return MCDisassembler::Fail;
     439           6 :       if (Cond != 0xE)
     440             :         return MCDisassembler::SoftFail;
     441             :       return Result;
     442             :     }
     443             :     default: return Result;
     444             :   }
     445             : }
     446             : 
     447        7479 : DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     448             :                                              ArrayRef<uint8_t> Bytes,
     449             :                                              uint64_t Address, raw_ostream &OS,
     450             :                                              raw_ostream &CS) const {
     451        7479 :   CommentStream = &CS;
     452             : 
     453             :   assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
     454             :          "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
     455             :          "mode!");
     456             : 
     457             :   // We want to read exactly 4 bytes of data.
     458        7479 :   if (Bytes.size() < 4) {
     459          27 :     Size = 0;
     460          27 :     return MCDisassembler::Fail;
     461             :   }
     462             : 
     463             :   // Encoded as a small-endian 32-bit word in the stream.
     464             :   uint32_t Insn =
     465        7452 :       (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
     466             : 
     467             :   // Calling the auto-generated decoder function.
     468             :   DecodeStatus Result =
     469        7452 :       decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
     470        7452 :   if (Result != MCDisassembler::Fail) {
     471        5261 :     Size = 4;
     472             :     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
     473             :   }
     474             : 
     475             :   struct DecodeTable {
     476             :     const uint8_t *P;
     477             :     bool DecodePred;
     478             :   };
     479             : 
     480        2191 :   const DecodeTable Tables[] = {
     481             :       {DecoderTableVFP32, false},      {DecoderTableVFPV832, false},
     482             :       {DecoderTableNEONData32, true},  {DecoderTableNEONLoadStore32, true},
     483             :       {DecoderTableNEONDup32, true},   {DecoderTablev8NEON32, false},
     484             :       {DecoderTablev8Crypto32, false},
     485             :   };
     486             : 
     487       15883 :   for (auto Table : Tables) {
     488        8561 :     Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
     489        8561 :     if (Result != MCDisassembler::Fail) {
     490        1715 :       Size = 4;
     491             :       // Add a fake predicate operand, because we share these instruction
     492             :       // definitions with Thumb2 where these instructions are predicable.
     493        1715 :       if (Table.DecodePred && !DecodePredicateOperand(MI, 0xE, Address, this))
     494             :         return MCDisassembler::Fail;
     495             :       return Result;
     496             :     }
     497             :   }
     498             : 
     499         476 :   Result =
     500         476 :       decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
     501         476 :   if (Result != MCDisassembler::Fail) {
     502          70 :     Size = 4;
     503             :     return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
     504             :   }
     505             : 
     506         406 :   Size = 4;
     507         406 :   return MCDisassembler::Fail;
     508             : }
     509             : 
     510             : namespace llvm {
     511             : 
     512             : extern const MCInstrDesc ARMInsts[];
     513             : 
     514             : } // end namespace llvm
     515             : 
     516             : /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
     517             : /// immediate Value in the MCInst.  The immediate Value has had any PC
     518             : /// adjustment made by the caller.  If the instruction is a branch instruction
     519             : /// then isBranch is true, else false.  If the getOpInfo() function was set as
     520             : /// part of the setupForSymbolicDisassembly() call then that function is called
     521             : /// to get any symbolic information at the Address for this instruction.  If
     522             : /// that returns non-zero then the symbolic information it returns is used to
     523             : /// create an MCExpr and that is added as an operand to the MCInst.  If
     524             : /// getOpInfo() returns zero and isBranch is true then a symbol look up for
     525             : /// Value is done and if a symbol is found an MCExpr is created with that, else
     526             : /// an MCExpr with Value is created.  This function returns true if it adds an
     527             : /// operand to the MCInst and false otherwise.
     528             : static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
     529             :                                      bool isBranch, uint64_t InstSize,
     530             :                                      MCInst &MI, const void *Decoder) {
     531             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
     532             :   // FIXME: Does it make sense for value to be negative?
     533        1335 :   return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
     534        1335 :                                        /* Offset */ 0, InstSize);
     535             : }
     536             : 
     537             : /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
     538             : /// referenced by a load instruction with the base register that is the Pc.
     539             : /// These can often be values in a literal pool near the Address of the
     540             : /// instruction.  The Address of the instruction and its immediate Value are
     541             : /// used as a possible literal pool entry.  The SymbolLookUp call back will
     542             : /// return the name of a symbol referenced by the literal pool's entry if
     543             : /// the referenced address is that of a symbol.  Or it will return a pointer to
     544             : /// a literal 'C' string if the referenced address of the literal pool's entry
     545             : /// is an address into a section with 'C' string literals.
     546             : static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
     547             :                                             const void *Decoder) {
     548             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
     549          84 :   Dis->tryAddingPcLoadReferenceComment(Value, Address);
     550             : }
     551             : 
     552             : // Thumb1 instructions don't have explicit S bits.  Rather, they
     553             : // implicitly set CPSR.  Since it's not represented in the encoding, the
     554             : // auto-generated decoder won't inject the CPSR operand.  We need to fix
     555             : // that as a post-pass.
     556        2438 : static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
     557        2438 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     558        2438 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     559             :   MCInst::iterator I = MI.begin();
     560        8546 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     561        5184 :     if (I == MI.end()) break;
     562        5184 :     if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
     563        2130 :       if (i > 0 && OpInfo[i-1].isPredicate()) continue;
     564        6390 :       MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
     565        2130 :       return;
     566             :     }
     567             :   }
     568             : 
     569         924 :   MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
     570             : }
     571             : 
     572             : // Most Thumb instructions don't have explicit predicates in the
     573             : // encoding, but rather get their predicates from IT context.  We need
     574             : // to fix up the predicate operands using this context information as a
     575             : // post-pass.
     576             : MCDisassembler::DecodeStatus
     577       11095 : ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
     578             :   MCDisassembler::DecodeStatus S = Success;
     579             : 
     580       11095 :   const FeatureBitset &FeatureBits = getSubtargetInfo().getFeatureBits();
     581             : 
     582             :   // A few instructions actually have predicates encoded in them.  Don't
     583             :   // try to overwrite it if we're seeing one of those.
     584       11095 :   switch (MI.getOpcode()) {
     585         268 :     case ARM::tBcc:
     586             :     case ARM::t2Bcc:
     587             :     case ARM::tCBZ:
     588             :     case ARM::tCBNZ:
     589             :     case ARM::tCPS:
     590             :     case ARM::t2CPS3p:
     591             :     case ARM::t2CPS2p:
     592             :     case ARM::t2CPS1p:
     593             :     case ARM::tMOVSr:
     594             :     case ARM::tSETEND:
     595             :       // Some instructions (mostly conditional branches) are not
     596             :       // allowed in IT blocks.
     597         268 :       if (ITBlock.instrInITBlock())
     598             :         S = SoftFail;
     599             :       else
     600             :         return Success;
     601             :       break;
     602             :     case ARM::t2HINT:
     603          12 :       if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
     604             :         S = SoftFail;
     605             :       break;
     606          82 :     case ARM::tB:
     607             :     case ARM::t2B:
     608             :     case ARM::t2TBB:
     609             :     case ARM::t2TBH:
     610             :       // Some instructions (mostly unconditional branches) can
     611             :       // only appears at the end of, or outside of, an IT.
     612          84 :       if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
     613             :         S = SoftFail;
     614             :       break;
     615             :     default:
     616             :       break;
     617             :   }
     618             : 
     619             :   // If we're in an IT block, base the predicate on that.  Otherwise,
     620             :   // assume a predicate of AL.
     621             :   unsigned CC;
     622             :   CC = ITBlock.getITCC();
     623         188 :   if (CC == 0xF) 
     624             :     CC = ARMCC::AL;
     625       10829 :   if (ITBlock.instrInITBlock())
     626             :     ITBlock.advanceITState();
     627             : 
     628       10829 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     629       10829 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     630             :   MCInst::iterator I = MI.begin();
     631       71525 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     632       41019 :     if (I == MI.end()) break;
     633       31707 :     if (OpInfo[i].isPredicate()) {
     634        4077 :       I = MI.insert(I, MCOperand::createImm(CC));
     635        1359 :       ++I;
     636        1359 :       if (CC == ARMCC::AL)
     637        2702 :         MI.insert(I, MCOperand::createReg(0));
     638             :       else
     639          16 :         MI.insert(I, MCOperand::createReg(ARM::CPSR));
     640             :       return S;
     641             :     }
     642             :   }
     643             : 
     644       28410 :   I = MI.insert(I, MCOperand::createImm(CC));
     645        9470 :   ++I;
     646        9470 :   if (CC == ARMCC::AL)
     647       18596 :     MI.insert(I, MCOperand::createReg(0));
     648             :   else
     649         344 :     MI.insert(I, MCOperand::createReg(ARM::CPSR));
     650             : 
     651             :   return S;
     652             : }
     653             : 
     654             : // Thumb VFP instructions are a special case.  Because we share their
     655             : // encodings between ARM and Thumb modes, and they are predicable in ARM
     656             : // mode, the auto-generated decoder will give them an (incorrect)
     657             : // predicate operand.  We need to rewrite these operands based on the IT
     658             : // context as a post-pass.
     659         171 : void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
     660             :   unsigned CC;
     661             :   CC = ITBlock.getITCC();
     662         171 :   if (ITBlock.instrInITBlock())
     663             :     ITBlock.advanceITState();
     664             : 
     665         171 :   const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
     666             :   MCInst::iterator I = MI.begin();
     667         171 :   unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
     668         801 :   for (unsigned i = 0; i < NumOps; ++i, ++I) {
     669         486 :     if (OpInfo[i].isPredicate() ) {
     670         171 :       I->setImm(CC);
     671             :       ++I;
     672         171 :       if (CC == ARMCC::AL)
     673             :         I->setReg(0);
     674             :       else
     675             :         I->setReg(ARM::CPSR);
     676             :       return;
     677             :     }
     678             :   }
     679             : }
     680             : 
     681       11975 : DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
     682             :                                                ArrayRef<uint8_t> Bytes,
     683             :                                                uint64_t Address,
     684             :                                                raw_ostream &OS,
     685             :                                                raw_ostream &CS) const {
     686       11975 :   CommentStream = &CS;
     687             : 
     688             :   assert(STI.getFeatureBits()[ARM::ModeThumb] &&
     689             :          "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
     690             : 
     691             :   // We want to read exactly 2 bytes of data.
     692       11975 :   if (Bytes.size() < 2) {
     693          10 :     Size = 0;
     694          10 :     return MCDisassembler::Fail;
     695             :   }
     696             : 
     697       11965 :   uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
     698             :   DecodeStatus Result =
     699       11965 :       decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
     700       11965 :   if (Result != MCDisassembler::Fail) {
     701        4617 :     Size = 2;
     702        4617 :     Check(Result, AddThumbPredicate(MI));
     703             :     return Result;
     704             :   }
     705             : 
     706        7348 :   Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
     707             :                              STI);
     708        7348 :   if (Result) {
     709        2130 :     Size = 2;
     710             :     bool InITBlock = ITBlock.instrInITBlock();
     711        2130 :     Check(Result, AddThumbPredicate(MI));
     712        2130 :     AddThumb1SBit(MI, InITBlock);
     713        2130 :     return Result;
     714             :   }
     715             : 
     716             :   Result =
     717        5218 :       decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
     718        5218 :   if (Result != MCDisassembler::Fail) {
     719         131 :     Size = 2;
     720             : 
     721             :     // Nested IT blocks are UNPREDICTABLE.  Must be checked before we add
     722             :     // the Thumb predicate.
     723         262 :     if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
     724             :       Result = MCDisassembler::SoftFail;
     725             : 
     726         131 :     Check(Result, AddThumbPredicate(MI));
     727             : 
     728             :     // If we find an IT instruction, we need to parse its condition
     729             :     // code and mask operands so that we can apply them correctly
     730             :     // to the subsequent instructions.
     731         131 :     if (MI.getOpcode() == ARM::t2IT) {
     732             : 
     733         131 :       unsigned Firstcond = MI.getOperand(0).getImm();
     734         131 :       unsigned Mask = MI.getOperand(1).getImm();
     735         131 :       ITBlock.setITState(Firstcond, Mask);
     736             :     }
     737             : 
     738             :     return Result;
     739             :   }
     740             : 
     741             :   // We want to read exactly 4 bytes of data.
     742        5087 :   if (Bytes.size() < 4) {
     743           6 :     Size = 0;
     744           6 :     return MCDisassembler::Fail;
     745             :   }
     746             : 
     747             :   uint32_t Insn32 =
     748        5081 :       (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
     749             :   Result =
     750        5081 :       decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
     751        5081 :   if (Result != MCDisassembler::Fail) {
     752         308 :     Size = 4;
     753             :     bool InITBlock = ITBlock.instrInITBlock();
     754         308 :     Check(Result, AddThumbPredicate(MI));
     755         308 :     AddThumb1SBit(MI, InITBlock);
     756         308 :     return Result;
     757             :   }
     758             : 
     759             :   Result =
     760        4773 :       decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
     761        4773 :   if (Result != MCDisassembler::Fail) {
     762        2587 :     Size = 4;
     763        2587 :     Check(Result, AddThumbPredicate(MI));
     764             :     return Result;
     765             :   }
     766             : 
     767        2186 :   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
     768             :     Result =
     769         676 :         decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
     770         676 :     if (Result != MCDisassembler::Fail) {
     771         171 :       Size = 4;
     772         171 :       UpdateThumbVFPPredicate(MI);
     773         171 :       return Result;
     774             :     }
     775             :   }
     776             : 
     777             :   Result =
     778        2015 :       decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
     779        2015 :   if (Result != MCDisassembler::Fail) {
     780          97 :     Size = 4;
     781          97 :     return Result;
     782             :   }
     783             : 
     784        1918 :   if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
     785         505 :     Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
     786             :                                STI);
     787         505 :     if (Result != MCDisassembler::Fail) {
     788          17 :       Size = 4;
     789          17 :       Check(Result, AddThumbPredicate(MI));
     790             :       return Result;
     791             :     }
     792             :   }
     793             : 
     794        1901 :   if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
     795             :     uint32_t NEONLdStInsn = Insn32;
     796         499 :     NEONLdStInsn &= 0xF0FFFFFF;
     797         499 :     NEONLdStInsn |= 0x04000000;
     798         499 :     Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
     799             :                                Address, this, STI);
     800         499 :     if (Result != MCDisassembler::Fail) {
     801         449 :       Size = 4;
     802         449 :       Check(Result, AddThumbPredicate(MI));
     803             :       return Result;
     804             :     }
     805             :   }
     806             : 
     807        1452 :   if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
     808             :     uint32_t NEONDataInsn = Insn32;
     809        1046 :     NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
     810        1046 :     NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     811        1046 :     NEONDataInsn |= 0x12000000; // Set bits 28 and 25
     812        1046 :     Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
     813             :                                Address, this, STI);
     814        1046 :     if (Result != MCDisassembler::Fail) {
     815         794 :       Size = 4;
     816         794 :       Check(Result, AddThumbPredicate(MI));
     817             :       return Result;
     818             :     }
     819             : 
     820             :     uint32_t NEONCryptoInsn = Insn32;
     821             :     NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
     822             :     NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
     823             :     NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
     824         252 :     Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
     825             :                                Address, this, STI);
     826         252 :     if (Result != MCDisassembler::Fail) {
     827          14 :       Size = 4;
     828          14 :       return Result;
     829             :     }
     830             : 
     831             :     uint32_t NEONv8Insn = Insn32;
     832         238 :     NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
     833         238 :     Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
     834             :                                this, STI);
     835         238 :     if (Result != MCDisassembler::Fail) {
     836          64 :       Size = 4;
     837          64 :       return Result;
     838             :     }
     839             :   }
     840             : 
     841             :   Result =
     842         580 :       decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
     843         580 :   if (Result != MCDisassembler::Fail) {
     844          62 :     Size = 4;
     845          62 :     Check(Result, AddThumbPredicate(MI));
     846             :     return Result;
     847             :   }
     848             : 
     849         518 :   Size = 0;
     850         518 :   return MCDisassembler::Fail;
     851             : }
     852             : 
     853       11199 : extern "C" void LLVMInitializeARMDisassembler() {
     854       11199 :   TargetRegistry::RegisterMCDisassembler(getTheARMLETarget(),
     855             :                                          createARMDisassembler);
     856       11199 :   TargetRegistry::RegisterMCDisassembler(getTheARMBETarget(),
     857             :                                          createARMDisassembler);
     858       11199 :   TargetRegistry::RegisterMCDisassembler(getTheThumbLETarget(),
     859             :                                          createThumbDisassembler);
     860       11199 :   TargetRegistry::RegisterMCDisassembler(getTheThumbBETarget(),
     861             :                                          createThumbDisassembler);
     862       11199 : }
     863             : 
     864             : static const uint16_t GPRDecoderTable[] = {
     865             :   ARM::R0, ARM::R1, ARM::R2, ARM::R3,
     866             :   ARM::R4, ARM::R5, ARM::R6, ARM::R7,
     867             :   ARM::R8, ARM::R9, ARM::R10, ARM::R11,
     868             :   ARM::R12, ARM::SP, ARM::LR, ARM::PC
     869             : };
     870             : 
     871       35808 : static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     872             :                                    uint64_t Address, const void *Decoder) {
     873       35808 :   if (RegNo > 15)
     874             :     return MCDisassembler::Fail;
     875             : 
     876       35808 :   unsigned Register = GPRDecoderTable[RegNo];
     877       71616 :   Inst.addOperand(MCOperand::createReg(Register));
     878             :   return MCDisassembler::Success;
     879             : }
     880             : 
     881             : static DecodeStatus
     882        2217 : DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
     883             :                            uint64_t Address, const void *Decoder) {
     884             :   DecodeStatus S = MCDisassembler::Success;
     885             : 
     886        2217 :   if (RegNo == 15) 
     887             :     S = MCDisassembler::SoftFail;
     888             : 
     889        2217 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     890             : 
     891        2217 :   return S;
     892             : }
     893             : 
     894             : static DecodeStatus
     895          47 : DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
     896             :                                uint64_t Address, const void *Decoder) {
     897             :   DecodeStatus S = MCDisassembler::Success;
     898             : 
     899          47 :   if (RegNo == 15)
     900             :   {
     901          18 :     Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
     902             :     return MCDisassembler::Success;
     903             :   }
     904             : 
     905          38 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     906             :   return S;
     907             : }
     908             : 
     909             : static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     910             :                                    uint64_t Address, const void *Decoder) {
     911             :   if (RegNo > 7)
     912             :     return MCDisassembler::Fail;
     913        9258 :   return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
     914             : }
     915             : 
     916             : static const uint16_t GPRPairDecoderTable[] = {
     917             :   ARM::R0_R1, ARM::R2_R3,   ARM::R4_R5,  ARM::R6_R7,
     918             :   ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
     919             : };
     920             : 
     921          15 : static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
     922             :                                    uint64_t Address, const void *Decoder) {
     923             :   DecodeStatus S = MCDisassembler::Success;
     924             : 
     925          15 :   if (RegNo > 13)
     926             :     return MCDisassembler::Fail;
     927             : 
     928          15 :   if ((RegNo & 1) || RegNo == 0xe)
     929             :      S = MCDisassembler::SoftFail;
     930             : 
     931          15 :   unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
     932          30 :   Inst.addOperand(MCOperand::createReg(RegisterPair));
     933             :   return S;
     934             : }
     935             : 
     936           1 : static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     937             :                                    uint64_t Address, const void *Decoder) {
     938             :   unsigned Register = 0;
     939           1 :   switch (RegNo) {
     940             :     case 0:
     941             :       Register = ARM::R0;
     942             :       break;
     943           0 :     case 1:
     944             :       Register = ARM::R1;
     945             :       break;
     946           0 :     case 2:
     947             :       Register = ARM::R2;
     948             :       break;
     949           0 :     case 3:
     950             :       Register = ARM::R3;
     951             :       break;
     952           0 :     case 9:
     953             :       Register = ARM::R9;
     954             :       break;
     955           0 :     case 12:
     956             :       Register = ARM::R12;
     957             :       break;
     958             :     default:
     959             :       return MCDisassembler::Fail;
     960             :     }
     961             : 
     962           0 :   Inst.addOperand(MCOperand::createReg(Register));
     963             :   return MCDisassembler::Success;
     964             : }
     965             : 
     966        2306 : static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
     967             :                                    uint64_t Address, const void *Decoder) {
     968             :   DecodeStatus S = MCDisassembler::Success;
     969             : 
     970             :   const FeatureBitset &featureBits =
     971        2306 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
     972             : 
     973        2317 :   if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
     974             :     S = MCDisassembler::SoftFail;
     975             : 
     976        2306 :   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
     977        2306 :   return S;
     978             : }
     979             : 
     980             : static const uint16_t SPRDecoderTable[] = {
     981             :      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
     982             :      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
     983             :      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
     984             :     ARM::S12, ARM::S13, ARM::S14, ARM::S15,
     985             :     ARM::S16, ARM::S17, ARM::S18, ARM::S19,
     986             :     ARM::S20, ARM::S21, ARM::S22, ARM::S23,
     987             :     ARM::S24, ARM::S25, ARM::S26, ARM::S27,
     988             :     ARM::S28, ARM::S29, ARM::S30, ARM::S31
     989             : };
     990             : 
     991         704 : static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
     992             :                                    uint64_t Address, const void *Decoder) {
     993         704 :   if (RegNo > 31)
     994             :     return MCDisassembler::Fail;
     995             : 
     996         704 :   unsigned Register = SPRDecoderTable[RegNo];
     997        1408 :   Inst.addOperand(MCOperand::createReg(Register));
     998             :   return MCDisassembler::Success;
     999             : }
    1000             : 
    1001             : static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1002             :                                    uint64_t Address, const void *Decoder) {
    1003         176 :   return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
    1004             : }
    1005             : 
    1006             : static const uint16_t DPRDecoderTable[] = {
    1007             :      ARM::D0,  ARM::D1,  ARM::D2,  ARM::D3,
    1008             :      ARM::D4,  ARM::D5,  ARM::D6,  ARM::D7,
    1009             :      ARM::D8,  ARM::D9, ARM::D10, ARM::D11,
    1010             :     ARM::D12, ARM::D13, ARM::D14, ARM::D15,
    1011             :     ARM::D16, ARM::D17, ARM::D18, ARM::D19,
    1012             :     ARM::D20, ARM::D21, ARM::D22, ARM::D23,
    1013             :     ARM::D24, ARM::D25, ARM::D26, ARM::D27,
    1014             :     ARM::D28, ARM::D29, ARM::D30, ARM::D31
    1015             : };
    1016             : 
    1017        4540 : static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1018             :                                    uint64_t Address, const void *Decoder) {
    1019             :   const FeatureBitset &featureBits =
    1020        4540 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    1021             : 
    1022             :   bool hasD16 = featureBits[ARM::FeatureD16];
    1023             : 
    1024        4540 :   if (RegNo > 31 || (hasD16 && RegNo > 15))
    1025             :     return MCDisassembler::Fail;
    1026             : 
    1027        4540 :   unsigned Register = DPRDecoderTable[RegNo];
    1028        9080 :   Inst.addOperand(MCOperand::createReg(Register));
    1029        4540 :   return MCDisassembler::Success;
    1030             : }
    1031             : 
    1032             : static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
    1033             :                                    uint64_t Address, const void *Decoder) {
    1034             :   if (RegNo > 7)
    1035             :     return MCDisassembler::Fail;
    1036          18 :   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
    1037             : }
    1038             : 
    1039             : static DecodeStatus
    1040             : DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
    1041             :                             uint64_t Address, const void *Decoder) {
    1042             :   if (RegNo > 15)
    1043             :     return MCDisassembler::Fail;
    1044          21 :   return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
    1045             : }
    1046             : 
    1047             : static const uint16_t QPRDecoderTable[] = {
    1048             :      ARM::Q0,  ARM::Q1,  ARM::Q2,  ARM::Q3,
    1049             :      ARM::Q4,  ARM::Q5,  ARM::Q6,  ARM::Q7,
    1050             :      ARM::Q8,  ARM::Q9, ARM::Q10, ARM::Q11,
    1051             :     ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
    1052             : };
    1053             : 
    1054        2430 : static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
    1055             :                                    uint64_t Address, const void *Decoder) {
    1056        2430 :   if (RegNo > 31 || (RegNo & 1) != 0)
    1057             :     return MCDisassembler::Fail;
    1058        2422 :   RegNo >>= 1;
    1059             : 
    1060        2422 :   unsigned Register = QPRDecoderTable[RegNo];
    1061        4844 :   Inst.addOperand(MCOperand::createReg(Register));
    1062        2422 :   return MCDisassembler::Success;
    1063             : }
    1064             : 
    1065             : static const uint16_t DPairDecoderTable[] = {
    1066             :   ARM::Q0,  ARM::D1_D2,   ARM::Q1,  ARM::D3_D4,   ARM::Q2,  ARM::D5_D6,
    1067             :   ARM::Q3,  ARM::D7_D8,   ARM::Q4,  ARM::D9_D10,  ARM::Q5,  ARM::D11_D12,
    1068             :   ARM::Q6,  ARM::D13_D14, ARM::Q7,  ARM::D15_D16, ARM::Q8,  ARM::D17_D18,
    1069             :   ARM::Q9,  ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
    1070             :   ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
    1071             :   ARM::Q15
    1072             : };
    1073             : 
    1074         209 : static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
    1075             :                                    uint64_t Address, const void *Decoder) {
    1076         209 :   if (RegNo > 30)
    1077             :     return MCDisassembler::Fail;
    1078             : 
    1079         209 :   unsigned Register = DPairDecoderTable[RegNo];
    1080         418 :   Inst.addOperand(MCOperand::createReg(Register));
    1081             :   return MCDisassembler::Success;
    1082             : }
    1083             : 
    1084             : static const uint16_t DPairSpacedDecoderTable[] = {
    1085             :   ARM::D0_D2,   ARM::D1_D3,   ARM::D2_D4,   ARM::D3_D5,
    1086             :   ARM::D4_D6,   ARM::D5_D7,   ARM::D6_D8,   ARM::D7_D9,
    1087             :   ARM::D8_D10,  ARM::D9_D11,  ARM::D10_D12, ARM::D11_D13,
    1088             :   ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
    1089             :   ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
    1090             :   ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
    1091             :   ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
    1092             :   ARM::D28_D30, ARM::D29_D31
    1093             : };
    1094             : 
    1095          61 : static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
    1096             :                                                    unsigned RegNo,
    1097             :                                                    uint64_t Address,
    1098             :                                                    const void *Decoder) {
    1099          61 :   if (RegNo > 29)
    1100             :     return MCDisassembler::Fail;
    1101             : 
    1102          61 :   unsigned Register = DPairSpacedDecoderTable[RegNo];
    1103         122 :   Inst.addOperand(MCOperand::createReg(Register));
    1104             :   return MCDisassembler::Success;
    1105             : }
    1106             : 
    1107        8169 : static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
    1108             :                                uint64_t Address, const void *Decoder) {
    1109        8169 :   if (Val == 0xF) return MCDisassembler::Fail;
    1110             :   // AL predicate is not allowed on Thumb1 branches.
    1111        6936 :   if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
    1112             :     return MCDisassembler::Fail;
    1113       20808 :   Inst.addOperand(MCOperand::createImm(Val));
    1114        6936 :   if (Val == ARMCC::AL) {
    1115       12596 :     Inst.addOperand(MCOperand::createReg(0));
    1116             :   } else
    1117        1276 :     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    1118             :   return MCDisassembler::Success;
    1119             : }
    1120             : 
    1121        1803 : static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
    1122             :                                uint64_t Address, const void *Decoder) {
    1123        1803 :   if (Val)
    1124         412 :     Inst.addOperand(MCOperand::createReg(ARM::CPSR));
    1125             :   else
    1126        3194 :     Inst.addOperand(MCOperand::createReg(0));
    1127        1803 :   return MCDisassembler::Success;
    1128             : }
    1129             : 
    1130         277 : static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
    1131             :                                uint64_t Address, const void *Decoder) {
    1132             :   DecodeStatus S = MCDisassembler::Success;
    1133             : 
    1134             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    1135             :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1136             :   unsigned imm = fieldFromInstruction(Val, 7, 5);
    1137             : 
    1138             :   // Register-immediate
    1139         554 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1140             :     return MCDisassembler::Fail;
    1141             : 
    1142             :   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
    1143             :   switch (type) {
    1144             :     case 0:
    1145             :       Shift = ARM_AM::lsl;
    1146             :       break;
    1147             :     case 1:
    1148             :       Shift = ARM_AM::lsr;
    1149             :       break;
    1150             :     case 2:
    1151             :       Shift = ARM_AM::asr;
    1152             :       break;
    1153             :     case 3:
    1154             :       Shift = ARM_AM::ror;
    1155             :       break;
    1156             :   }
    1157             : 
    1158         277 :   if (Shift == ARM_AM::ror && imm == 0)
    1159             :     Shift = ARM_AM::rrx;
    1160             : 
    1161         277 :   unsigned Op = Shift | (imm << 3);
    1162         831 :   Inst.addOperand(MCOperand::createImm(Op));
    1163             : 
    1164             :   return S;
    1165             : }
    1166             : 
    1167         125 : static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
    1168             :                                uint64_t Address, const void *Decoder) {
    1169             :   DecodeStatus S = MCDisassembler::Success;
    1170             : 
    1171             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    1172             :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1173             :   unsigned Rs = fieldFromInstruction(Val, 8, 4);
    1174             : 
    1175             :   // Register-register
    1176         250 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1177             :     return MCDisassembler::Fail;
    1178         250 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
    1179             :     return MCDisassembler::Fail;
    1180             : 
    1181             :   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
    1182             :   switch (type) {
    1183             :     case 0:
    1184             :       Shift = ARM_AM::lsl;
    1185             :       break;
    1186             :     case 1:
    1187             :       Shift = ARM_AM::lsr;
    1188             :       break;
    1189             :     case 2:
    1190             :       Shift = ARM_AM::asr;
    1191             :       break;
    1192             :     case 3:
    1193             :       Shift = ARM_AM::ror;
    1194             :       break;
    1195             :   }
    1196             : 
    1197         375 :   Inst.addOperand(MCOperand::createImm(Shift));
    1198             : 
    1199             :   return S;
    1200             : }
    1201             : 
    1202        1067 : static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
    1203             :                                  uint64_t Address, const void *Decoder) {
    1204             :   DecodeStatus S = MCDisassembler::Success;
    1205             : 
    1206             :   bool NeedDisjointWriteback = false;
    1207             :   unsigned WritebackReg = 0;
    1208        1067 :   switch (Inst.getOpcode()) {
    1209             :   default:
    1210             :     break;
    1211         157 :   case ARM::LDMIA_UPD:
    1212             :   case ARM::LDMDB_UPD:
    1213             :   case ARM::LDMIB_UPD:
    1214             :   case ARM::LDMDA_UPD:
    1215             :   case ARM::t2LDMIA_UPD:
    1216             :   case ARM::t2LDMDB_UPD:
    1217             :   case ARM::t2STMIA_UPD:
    1218             :   case ARM::t2STMDB_UPD:
    1219             :     NeedDisjointWriteback = true;
    1220         157 :     WritebackReg = Inst.getOperand(0).getReg();
    1221             :     break;
    1222             :   }
    1223             : 
    1224             :   // Empty register lists are not allowed.
    1225        1067 :   if (Val == 0) return MCDisassembler::Fail;
    1226       34551 :   for (unsigned i = 0; i < 16; ++i) {
    1227       16752 :     if (Val & (1 << i)) {
    1228        7052 :       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
    1229             :         return MCDisassembler::Fail;
    1230             :       // Writeback not allowed if Rn is in the target list.
    1231        4082 :       if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
    1232             :         Check(S, MCDisassembler::SoftFail);
    1233             :     }
    1234             :   }
    1235             : 
    1236             :   return S;
    1237             : }
    1238             : 
    1239          10 : static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
    1240             :                                  uint64_t Address, const void *Decoder) {
    1241             :   DecodeStatus S = MCDisassembler::Success;
    1242             : 
    1243             :   unsigned Vd = fieldFromInstruction(Val, 8, 5);
    1244          10 :   unsigned regs = fieldFromInstruction(Val, 0, 8);
    1245             : 
    1246             :   // In case of unpredictable encoding, tweak the operands.
    1247          10 :   if (regs == 0 || (Vd + regs) > 32) {
    1248           1 :     regs = Vd + regs > 32 ? 32 - Vd : regs;
    1249           2 :     regs = std::max( 1u, regs);
    1250             :     S = MCDisassembler::SoftFail;
    1251             :   }
    1252             : 
    1253          20 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
    1254             :     return MCDisassembler::Fail;
    1255          92 :   for (unsigned i = 0; i < (regs - 1); ++i) {
    1256          82 :     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
    1257             :       return MCDisassembler::Fail;
    1258             :   }
    1259             : 
    1260             :   return S;
    1261             : }
    1262             : 
    1263          20 : static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
    1264             :                                  uint64_t Address, const void *Decoder) {
    1265             :   DecodeStatus S = MCDisassembler::Success;
    1266             : 
    1267             :   unsigned Vd = fieldFromInstruction(Val, 8, 5);
    1268          20 :   unsigned regs = fieldFromInstruction(Val, 1, 7);
    1269             : 
    1270             :   // In case of unpredictable encoding, tweak the operands.
    1271          20 :   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
    1272           2 :     regs = Vd + regs > 32 ? 32 - Vd : regs;
    1273           4 :     regs = std::max( 1u, regs);
    1274           4 :     regs = std::min(16u, regs);
    1275             :     S = MCDisassembler::SoftFail;
    1276             :   }
    1277             : 
    1278          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
    1279             :       return MCDisassembler::Fail;
    1280         164 :   for (unsigned i = 0; i < (regs - 1); ++i) {
    1281         144 :     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
    1282             :       return MCDisassembler::Fail;
    1283             :   }
    1284             : 
    1285             :   return S;
    1286             : }
    1287             : 
    1288          54 : static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
    1289             :                                       uint64_t Address, const void *Decoder) {
    1290             :   // This operand encodes a mask of contiguous zeros between a specified MSB
    1291             :   // and LSB.  To decode it, we create the mask of all bits MSB-and-lower,
    1292             :   // the mask of all bits LSB-and-lower, and then xor them to create
    1293             :   // the mask of that's all ones on [msb, lsb].  Finally we not it to
    1294             :   // create the final mask.
    1295             :   unsigned msb = fieldFromInstruction(Val, 5, 5);
    1296             :   unsigned lsb = fieldFromInstruction(Val, 0, 5);
    1297             : 
    1298             :   DecodeStatus S = MCDisassembler::Success;
    1299          54 :   if (lsb > msb) {
    1300             :     Check(S, MCDisassembler::SoftFail);
    1301             :     // The check above will cause the warning for the "potentially undefined
    1302             :     // instruction encoding" but we can't build a bad MCOperand value here
    1303             :     // with a lsb > msb or else printing the MCInst will cause a crash.
    1304             :     lsb = msb;
    1305             :   }
    1306             : 
    1307             :   uint32_t msb_mask = 0xFFFFFFFF;
    1308          54 :   if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
    1309          54 :   uint32_t lsb_mask = (1U << lsb) - 1;
    1310             : 
    1311         162 :   Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
    1312          54 :   return S;
    1313             : }
    1314             : 
    1315         109 : static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
    1316             :                                   uint64_t Address, const void *Decoder) {
    1317             :   DecodeStatus S = MCDisassembler::Success;
    1318             : 
    1319             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1320             :   unsigned CRd = fieldFromInstruction(Insn, 12, 4);
    1321             :   unsigned coproc = fieldFromInstruction(Insn, 8, 4);
    1322             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    1323             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1324             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    1325             : 
    1326         109 :   switch (Inst.getOpcode()) {
    1327          85 :     case ARM::LDC_OFFSET:
    1328             :     case ARM::LDC_PRE:
    1329             :     case ARM::LDC_POST:
    1330             :     case ARM::LDC_OPTION:
    1331             :     case ARM::LDCL_OFFSET:
    1332             :     case ARM::LDCL_PRE:
    1333             :     case ARM::LDCL_POST:
    1334             :     case ARM::LDCL_OPTION:
    1335             :     case ARM::STC_OFFSET:
    1336             :     case ARM::STC_PRE:
    1337             :     case ARM::STC_POST:
    1338             :     case ARM::STC_OPTION:
    1339             :     case ARM::STCL_OFFSET:
    1340             :     case ARM::STCL_PRE:
    1341             :     case ARM::STCL_POST:
    1342             :     case ARM::STCL_OPTION:
    1343             :     case ARM::t2LDC_OFFSET:
    1344             :     case ARM::t2LDC_PRE:
    1345             :     case ARM::t2LDC_POST:
    1346             :     case ARM::t2LDC_OPTION:
    1347             :     case ARM::t2LDCL_OFFSET:
    1348             :     case ARM::t2LDCL_PRE:
    1349             :     case ARM::t2LDCL_POST:
    1350             :     case ARM::t2LDCL_OPTION:
    1351             :     case ARM::t2STC_OFFSET:
    1352             :     case ARM::t2STC_PRE:
    1353             :     case ARM::t2STC_POST:
    1354             :     case ARM::t2STC_OPTION:
    1355             :     case ARM::t2STCL_OFFSET:
    1356             :     case ARM::t2STCL_PRE:
    1357             :     case ARM::t2STCL_POST:
    1358             :     case ARM::t2STCL_OPTION:
    1359          85 :       if (coproc == 0xA || coproc == 0xB)
    1360             :         return MCDisassembler::Fail;
    1361             :       break;
    1362             :     default:
    1363             :       break;
    1364             :   }
    1365             : 
    1366             :   const FeatureBitset &featureBits =
    1367         109 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    1368         109 :   if (featureBits[ARM::HasV8Ops] && (coproc != 14))
    1369             :     return MCDisassembler::Fail;
    1370             : 
    1371         159 :   Inst.addOperand(MCOperand::createImm(coproc));
    1372         159 :   Inst.addOperand(MCOperand::createImm(CRd));
    1373         106 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1374             :     return MCDisassembler::Fail;
    1375             : 
    1376          53 :   switch (Inst.getOpcode()) {
    1377           6 :     case ARM::t2LDC2_OFFSET:
    1378             :     case ARM::t2LDC2L_OFFSET:
    1379             :     case ARM::t2LDC2_PRE:
    1380             :     case ARM::t2LDC2L_PRE:
    1381             :     case ARM::t2STC2_OFFSET:
    1382             :     case ARM::t2STC2L_OFFSET:
    1383             :     case ARM::t2STC2_PRE:
    1384             :     case ARM::t2STC2L_PRE:
    1385             :     case ARM::LDC2_OFFSET:
    1386             :     case ARM::LDC2L_OFFSET:
    1387             :     case ARM::LDC2_PRE:
    1388             :     case ARM::LDC2L_PRE:
    1389             :     case ARM::STC2_OFFSET:
    1390             :     case ARM::STC2L_OFFSET:
    1391             :     case ARM::STC2_PRE:
    1392             :     case ARM::STC2L_PRE:
    1393             :     case ARM::t2LDC_OFFSET:
    1394             :     case ARM::t2LDCL_OFFSET:
    1395             :     case ARM::t2LDC_PRE:
    1396             :     case ARM::t2LDCL_PRE:
    1397             :     case ARM::t2STC_OFFSET:
    1398             :     case ARM::t2STCL_OFFSET:
    1399             :     case ARM::t2STC_PRE:
    1400             :     case ARM::t2STCL_PRE:
    1401             :     case ARM::LDC_OFFSET:
    1402             :     case ARM::LDCL_OFFSET:
    1403             :     case ARM::LDC_PRE:
    1404             :     case ARM::LDCL_PRE:
    1405             :     case ARM::STC_OFFSET:
    1406             :     case ARM::STCL_OFFSET:
    1407             :     case ARM::STC_PRE:
    1408             :     case ARM::STCL_PRE:
    1409           6 :       imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
    1410          18 :       Inst.addOperand(MCOperand::createImm(imm));
    1411             :       break;
    1412          14 :     case ARM::t2LDC2_POST:
    1413             :     case ARM::t2LDC2L_POST:
    1414             :     case ARM::t2STC2_POST:
    1415             :     case ARM::t2STC2L_POST:
    1416             :     case ARM::LDC2_POST:
    1417             :     case ARM::LDC2L_POST:
    1418             :     case ARM::STC2_POST:
    1419             :     case ARM::STC2L_POST:
    1420             :     case ARM::t2LDC_POST:
    1421             :     case ARM::t2LDCL_POST:
    1422             :     case ARM::t2STC_POST:
    1423             :     case ARM::t2STCL_POST:
    1424             :     case ARM::LDC_POST:
    1425             :     case ARM::LDCL_POST:
    1426             :     case ARM::STC_POST:
    1427             :     case ARM::STCL_POST:
    1428          14 :       imm |= U << 8;
    1429             :       LLVM_FALLTHROUGH;
    1430          47 :     default:
    1431             :       // The 'option' variant doesn't encode 'U' in the immediate since
    1432             :       // the immediate is unsigned [0,255].
    1433         141 :       Inst.addOperand(MCOperand::createImm(imm));
    1434             :       break;
    1435             :   }
    1436             : 
    1437          53 :   switch (Inst.getOpcode()) {
    1438          23 :     case ARM::LDC_OFFSET:
    1439             :     case ARM::LDC_PRE:
    1440             :     case ARM::LDC_POST:
    1441             :     case ARM::LDC_OPTION:
    1442             :     case ARM::LDCL_OFFSET:
    1443             :     case ARM::LDCL_PRE:
    1444             :     case ARM::LDCL_POST:
    1445             :     case ARM::LDCL_OPTION:
    1446             :     case ARM::STC_OFFSET:
    1447             :     case ARM::STC_PRE:
    1448             :     case ARM::STC_POST:
    1449             :     case ARM::STC_OPTION:
    1450             :     case ARM::STCL_OFFSET:
    1451             :     case ARM::STCL_PRE:
    1452             :     case ARM::STCL_POST:
    1453             :     case ARM::STCL_OPTION:
    1454          46 :       if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1455             :         return MCDisassembler::Fail;
    1456             :       break;
    1457             :     default:
    1458             :       break;
    1459             :   }
    1460             : 
    1461             :   return S;
    1462             : }
    1463             : 
    1464             : static DecodeStatus
    1465        1919 : DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
    1466             :                               uint64_t Address, const void *Decoder) {
    1467             :   DecodeStatus S = MCDisassembler::Success;
    1468             : 
    1469             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1470             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    1471             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1472             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    1473             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1474             :   unsigned reg = fieldFromInstruction(Insn, 25, 1);
    1475             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    1476             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    1477             : 
    1478             :   // On stores, the writeback operand precedes Rt.
    1479        1919 :   switch (Inst.getOpcode()) {
    1480        1161 :     case ARM::STR_POST_IMM:
    1481             :     case ARM::STR_POST_REG:
    1482             :     case ARM::STRB_POST_IMM:
    1483             :     case ARM::STRB_POST_REG:
    1484             :     case ARM::STRT_POST_REG:
    1485             :     case ARM::STRT_POST_IMM:
    1486             :     case ARM::STRBT_POST_REG:
    1487             :     case ARM::STRBT_POST_IMM:
    1488        2322 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1489             :         return MCDisassembler::Fail;
    1490             :       break;
    1491             :     default:
    1492             :       break;
    1493             :   }
    1494             : 
    1495        3838 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    1496             :     return MCDisassembler::Fail;
    1497             : 
    1498             :   // On loads, the writeback operand comes after Rt.
    1499        1919 :   switch (Inst.getOpcode()) {
    1500         758 :     case ARM::LDR_POST_IMM:
    1501             :     case ARM::LDR_POST_REG:
    1502             :     case ARM::LDRB_POST_IMM:
    1503             :     case ARM::LDRB_POST_REG:
    1504             :     case ARM::LDRBT_POST_REG:
    1505             :     case ARM::LDRBT_POST_IMM:
    1506             :     case ARM::LDRT_POST_REG:
    1507             :     case ARM::LDRT_POST_IMM:
    1508        1516 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1509             :         return MCDisassembler::Fail;
    1510             :       break;
    1511             :     default:
    1512             :       break;
    1513             :   }
    1514             : 
    1515        3838 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1516             :     return MCDisassembler::Fail;
    1517             : 
    1518             :   ARM_AM::AddrOpc Op = ARM_AM::add;
    1519        1919 :   if (!fieldFromInstruction(Insn, 23, 1))
    1520             :     Op = ARM_AM::sub;
    1521             : 
    1522        1919 :   bool writeback = (P == 0) || (W == 1);
    1523             :   unsigned idx_mode = 0;
    1524        1919 :   if (P && writeback)
    1525             :     idx_mode = ARMII::IndexModePre;
    1526        1919 :   else if (!P && writeback)
    1527             :     idx_mode = ARMII::IndexModePost;
    1528             : 
    1529        1919 :   if (writeback && (Rn == 15 || Rn == Rt))
    1530             :     S = MCDisassembler::SoftFail; // UNPREDICTABLE
    1531             : 
    1532        1919 :   if (reg) {
    1533          42 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1534             :       return MCDisassembler::Fail;
    1535             :     ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
    1536          21 :     switch( fieldFromInstruction(Insn, 5, 2)) {
    1537             :       case 0:
    1538             :         Opc = ARM_AM::lsl;
    1539             :         break;
    1540           2 :       case 1:
    1541             :         Opc = ARM_AM::lsr;
    1542             :         break;
    1543           4 :       case 2:
    1544             :         Opc = ARM_AM::asr;
    1545             :         break;
    1546           0 :       case 3:
    1547             :         Opc = ARM_AM::ror;
    1548             :         break;
    1549             :       default:
    1550             :         return MCDisassembler::Fail;
    1551             :     }
    1552             :     unsigned amt = fieldFromInstruction(Insn, 7, 5);
    1553          21 :     if (Opc == ARM_AM::ror && amt == 0)
    1554             :       Opc = ARM_AM::rrx;
    1555             :     unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
    1556             : 
    1557          63 :     Inst.addOperand(MCOperand::createImm(imm));
    1558             :   } else {
    1559        3796 :     Inst.addOperand(MCOperand::createReg(0));
    1560             :     unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
    1561        5694 :     Inst.addOperand(MCOperand::createImm(tmp));
    1562             :   }
    1563             : 
    1564        3838 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1565             :     return MCDisassembler::Fail;
    1566             : 
    1567             :   return S;
    1568             : }
    1569             : 
    1570          33 : static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
    1571             :                                   uint64_t Address, const void *Decoder) {
    1572             :   DecodeStatus S = MCDisassembler::Success;
    1573             : 
    1574             :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    1575             :   unsigned Rm = fieldFromInstruction(Val,  0, 4);
    1576             :   unsigned type = fieldFromInstruction(Val, 5, 2);
    1577             :   unsigned imm = fieldFromInstruction(Val, 7, 5);
    1578             :   unsigned U = fieldFromInstruction(Val, 12, 1);
    1579             : 
    1580             :   ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
    1581             :   switch (type) {
    1582             :     case 0:
    1583             :       ShOp = ARM_AM::lsl;
    1584             :       break;
    1585             :     case 1:
    1586             :       ShOp = ARM_AM::lsr;
    1587             :       break;
    1588             :     case 2:
    1589             :       ShOp = ARM_AM::asr;
    1590             :       break;
    1591             :     case 3:
    1592             :       ShOp = ARM_AM::ror;
    1593             :       break;
    1594             :   }
    1595             : 
    1596          33 :   if (ShOp == ARM_AM::ror && imm == 0)
    1597             :     ShOp = ARM_AM::rrx;
    1598             : 
    1599          66 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1600             :     return MCDisassembler::Fail;
    1601          66 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1602             :     return MCDisassembler::Fail;
    1603             :   unsigned shift;
    1604          33 :   if (U)
    1605             :     shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
    1606             :   else
    1607             :     shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
    1608          99 :   Inst.addOperand(MCOperand::createImm(shift));
    1609             : 
    1610             :   return S;
    1611             : }
    1612             : 
    1613             : static DecodeStatus
    1614         409 : DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
    1615             :                            uint64_t Address, const void *Decoder) {
    1616             :   DecodeStatus S = MCDisassembler::Success;
    1617             : 
    1618             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    1619             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1620             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1621             :   unsigned type = fieldFromInstruction(Insn, 22, 1);
    1622             :   unsigned imm = fieldFromInstruction(Insn, 8, 4);
    1623         409 :   unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
    1624             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1625             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    1626             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    1627         409 :   unsigned Rt2 = Rt + 1;
    1628             : 
    1629         409 :   bool writeback = (W == 1) | (P == 0);
    1630             : 
    1631             :   // For {LD,ST}RD, Rt must be even, else undefined.
    1632         409 :   switch (Inst.getOpcode()) {
    1633          31 :     case ARM::STRD:
    1634             :     case ARM::STRD_PRE:
    1635             :     case ARM::STRD_POST:
    1636             :     case ARM::LDRD:
    1637             :     case ARM::LDRD_PRE:
    1638             :     case ARM::LDRD_POST:
    1639          31 :       if (Rt & 0x1) S = MCDisassembler::SoftFail;
    1640             :       break;
    1641             :     default:
    1642             :       break;
    1643             :   }
    1644         409 :   switch (Inst.getOpcode()) {
    1645          14 :     case ARM::STRD:
    1646             :     case ARM::STRD_PRE:
    1647             :     case ARM::STRD_POST:
    1648          14 :       if (P == 0 && W == 1)
    1649             :         S = MCDisassembler::SoftFail;
    1650             : 
    1651          14 :       if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
    1652             :         S = MCDisassembler::SoftFail;
    1653          14 :       if (type && Rm == 15)
    1654             :         S = MCDisassembler::SoftFail;
    1655          14 :       if (Rt2 == 15)
    1656             :         S = MCDisassembler::SoftFail;
    1657          14 :       if (!type && fieldFromInstruction(Insn, 8, 4))
    1658             :         S = MCDisassembler::SoftFail;
    1659             :       break;
    1660         177 :     case ARM::STRH:
    1661             :     case ARM::STRH_PRE:
    1662             :     case ARM::STRH_POST:
    1663         177 :       if (Rt == 15)
    1664             :         S = MCDisassembler::SoftFail;
    1665         177 :       if (writeback && (Rn == 15 || Rn == Rt))
    1666             :         S = MCDisassembler::SoftFail;
    1667         177 :       if (!type && Rm == 15)
    1668             :         S = MCDisassembler::SoftFail;
    1669             :       break;
    1670          17 :     case ARM::LDRD:
    1671             :     case ARM::LDRD_PRE:
    1672             :     case ARM::LDRD_POST:
    1673          17 :       if (type && Rn == 15) {
    1674           1 :         if (Rt2 == 15)
    1675             :           S = MCDisassembler::SoftFail;
    1676             :         break;
    1677             :       }
    1678          16 :       if (P == 0 && W == 1)
    1679             :         S = MCDisassembler::SoftFail;
    1680          16 :       if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
    1681             :         S = MCDisassembler::SoftFail;
    1682          16 :       if (!type && writeback && Rn == 15)
    1683             :         S = MCDisassembler::SoftFail;
    1684          16 :       if (writeback && (Rn == Rt || Rn == Rt2))
    1685             :         S = MCDisassembler::SoftFail;
    1686             :       break;
    1687         178 :     case ARM::LDRH:
    1688             :     case ARM::LDRH_PRE:
    1689             :     case ARM::LDRH_POST:
    1690         178 :       if (type && Rn == 15) {
    1691           0 :         if (Rt == 15)
    1692             :           S = MCDisassembler::SoftFail;
    1693             :         break;
    1694             :       }
    1695         178 :       if (Rt == 15)
    1696             :         S = MCDisassembler::SoftFail;
    1697         178 :       if (!type && Rm == 15)
    1698             :         S = MCDisassembler::SoftFail;
    1699         178 :       if (!type && writeback && (Rn == 15 || Rn == Rt))
    1700             :         S = MCDisassembler::SoftFail;
    1701             :       break;
    1702          23 :     case ARM::LDRSH:
    1703             :     case ARM::LDRSH_PRE:
    1704             :     case ARM::LDRSH_POST:
    1705             :     case ARM::LDRSB:
    1706             :     case ARM::LDRSB_PRE:
    1707             :     case ARM::LDRSB_POST:
    1708          23 :       if (type && Rn == 15) {
    1709           3 :         if (Rt == 15)
    1710             :           S = MCDisassembler::SoftFail;
    1711             :         break;
    1712             :       }
    1713          20 :       if (type && (Rt == 15 || (writeback && Rn == Rt)))
    1714             :         S = MCDisassembler::SoftFail;
    1715          20 :       if (!type && (Rt == 15 || Rm == 15))
    1716             :         S = MCDisassembler::SoftFail;
    1717          20 :       if (!type && writeback && (Rn == 15 || Rn == Rt))
    1718             :         S = MCDisassembler::SoftFail;
    1719             :       break;
    1720             :     default:
    1721             :       break;
    1722             :   }
    1723             : 
    1724         409 :   if (writeback) { // Writeback
    1725         383 :     if (P)
    1726          22 :       U |= ARMII::IndexModePre << 9;
    1727             :     else
    1728         361 :       U |= ARMII::IndexModePost << 9;
    1729             : 
    1730             :     // On stores, the writeback operand precedes Rt.
    1731             :     switch (Inst.getOpcode()) {
    1732         183 :     case ARM::STRD:
    1733             :     case ARM::STRD_PRE:
    1734             :     case ARM::STRD_POST:
    1735             :     case ARM::STRH:
    1736             :     case ARM::STRH_PRE:
    1737             :     case ARM::STRH_POST:
    1738         366 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1739             :         return MCDisassembler::Fail;
    1740             :       break;
    1741             :     default:
    1742             :       break;
    1743             :     }
    1744             :   }
    1745             : 
    1746         818 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    1747             :     return MCDisassembler::Fail;
    1748         409 :   switch (Inst.getOpcode()) {
    1749          31 :     case ARM::STRD:
    1750             :     case ARM::STRD_PRE:
    1751             :     case ARM::STRD_POST:
    1752             :     case ARM::LDRD:
    1753             :     case ARM::LDRD_PRE:
    1754             :     case ARM::LDRD_POST:
    1755          62 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
    1756             :         return MCDisassembler::Fail;
    1757             :       break;
    1758             :     default:
    1759             :       break;
    1760             :   }
    1761             : 
    1762         409 :   if (writeback) {
    1763             :     // On loads, the writeback operand comes after Rt.
    1764         383 :     switch (Inst.getOpcode()) {
    1765         200 :     case ARM::LDRD:
    1766             :     case ARM::LDRD_PRE:
    1767             :     case ARM::LDRD_POST:
    1768             :     case ARM::LDRH:
    1769             :     case ARM::LDRH_PRE:
    1770             :     case ARM::LDRH_POST:
    1771             :     case ARM::LDRSH:
    1772             :     case ARM::LDRSH_PRE:
    1773             :     case ARM::LDRSH_POST:
    1774             :     case ARM::LDRSB:
    1775             :     case ARM::LDRSB_PRE:
    1776             :     case ARM::LDRSB_POST:
    1777             :     case ARM::LDRHTr:
    1778             :     case ARM::LDRSBTr:
    1779         400 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1780             :         return MCDisassembler::Fail;
    1781             :       break;
    1782             :     default:
    1783             :       break;
    1784             :     }
    1785             :   }
    1786             : 
    1787         818 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1788             :     return MCDisassembler::Fail;
    1789             : 
    1790         409 :   if (type) {
    1791         748 :     Inst.addOperand(MCOperand::createReg(0));
    1792        1122 :     Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
    1793             :   } else {
    1794          70 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    1795             :     return MCDisassembler::Fail;
    1796         105 :     Inst.addOperand(MCOperand::createImm(U));
    1797             :   }
    1798             : 
    1799         818 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1800             :     return MCDisassembler::Fail;
    1801             : 
    1802             :   return S;
    1803             : }
    1804             : 
    1805           1 : static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
    1806             :                                  uint64_t Address, const void *Decoder) {
    1807             :   DecodeStatus S = MCDisassembler::Success;
    1808             : 
    1809             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1810             :   unsigned mode = fieldFromInstruction(Insn, 23, 2);
    1811             : 
    1812           1 :   switch (mode) {
    1813           0 :     case 0:
    1814             :       mode = ARM_AM::da;
    1815             :       break;
    1816           0 :     case 1:
    1817             :       mode = ARM_AM::ia;
    1818             :       break;
    1819           1 :     case 2:
    1820             :       mode = ARM_AM::db;
    1821             :       break;
    1822           0 :     case 3:
    1823             :       mode = ARM_AM::ib;
    1824             :       break;
    1825             :   }
    1826             : 
    1827           3 :   Inst.addOperand(MCOperand::createImm(mode));
    1828           2 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1829             :     return MCDisassembler::Fail;
    1830             : 
    1831             :   return S;
    1832             : }
    1833             : 
    1834           2 : static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
    1835             :                                uint64_t Address, const void *Decoder) {
    1836             :   DecodeStatus S = MCDisassembler::Success;
    1837             : 
    1838             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    1839             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    1840             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1841             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1842             : 
    1843           2 :   if (pred == 0xF)
    1844           0 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    1845             : 
    1846           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    1847             :     return MCDisassembler::Fail;
    1848           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    1849             :     return MCDisassembler::Fail;
    1850           4 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    1851             :     return MCDisassembler::Fail;
    1852           4 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1853             :     return MCDisassembler::Fail;
    1854             :   return S;
    1855             : }
    1856             : 
    1857         275 : static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
    1858             :                                   unsigned Insn,
    1859             :                                   uint64_t Address, const void *Decoder) {
    1860             :   DecodeStatus S = MCDisassembler::Success;
    1861             : 
    1862             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    1863             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1864             :   unsigned reglist = fieldFromInstruction(Insn, 0, 16);
    1865             : 
    1866         275 :   if (pred == 0xF) {
    1867             :     // Ambiguous with RFE and SRS
    1868           7 :     switch (Inst.getOpcode()) {
    1869             :       case ARM::LDMDA:
    1870             :         Inst.setOpcode(ARM::RFEDA);
    1871             :         break;
    1872             :       case ARM::LDMDA_UPD:
    1873             :         Inst.setOpcode(ARM::RFEDA_UPD);
    1874             :         break;
    1875             :       case ARM::LDMDB:
    1876             :         Inst.setOpcode(ARM::RFEDB);
    1877             :         break;
    1878             :       case ARM::LDMDB_UPD:
    1879             :         Inst.setOpcode(ARM::RFEDB_UPD);
    1880             :         break;
    1881             :       case ARM::LDMIA:
    1882             :         Inst.setOpcode(ARM::RFEIA);
    1883             :         break;
    1884             :       case ARM::LDMIA_UPD:
    1885             :         Inst.setOpcode(ARM::RFEIA_UPD);
    1886             :         break;
    1887             :       case ARM::LDMIB:
    1888             :         Inst.setOpcode(ARM::RFEIB);
    1889             :         break;
    1890             :       case ARM::LDMIB_UPD:
    1891             :         Inst.setOpcode(ARM::RFEIB_UPD);
    1892             :         break;
    1893             :       case ARM::STMDA:
    1894             :         Inst.setOpcode(ARM::SRSDA);
    1895             :         break;
    1896             :       case ARM::STMDA_UPD:
    1897             :         Inst.setOpcode(ARM::SRSDA_UPD);
    1898             :         break;
    1899             :       case ARM::STMDB:
    1900             :         Inst.setOpcode(ARM::SRSDB);
    1901             :         break;
    1902             :       case ARM::STMDB_UPD:
    1903             :         Inst.setOpcode(ARM::SRSDB_UPD);
    1904             :         break;
    1905             :       case ARM::STMIA:
    1906             :         Inst.setOpcode(ARM::SRSIA);
    1907             :         break;
    1908             :       case ARM::STMIA_UPD:
    1909             :         Inst.setOpcode(ARM::SRSIA_UPD);
    1910             :         break;
    1911             :       case ARM::STMIB:
    1912             :         Inst.setOpcode(ARM::SRSIB);
    1913             :         break;
    1914             :       case ARM::STMIB_UPD:
    1915             :         Inst.setOpcode(ARM::SRSIB_UPD);
    1916             :         break;
    1917             :       default:
    1918             :         return MCDisassembler::Fail;
    1919             :     }
    1920             : 
    1921             :     // For stores (which become SRS's, the only operand is the mode.
    1922           4 :     if (fieldFromInstruction(Insn, 20, 1) == 0) {
    1923             :       // Check SRS encoding constraints
    1924           3 :       if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
    1925             :             fieldFromInstruction(Insn, 20, 1) == 0))
    1926             :         return MCDisassembler::Fail;
    1927             : 
    1928             :       Inst.addOperand(
    1929           0 :           MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
    1930             :       return S;
    1931             :     }
    1932             : 
    1933           1 :     return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
    1934             :   }
    1935             : 
    1936         536 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1937             :     return MCDisassembler::Fail;
    1938         536 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    1939             :     return MCDisassembler::Fail; // Tied
    1940         536 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1941             :     return MCDisassembler::Fail;
    1942         536 :   if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
    1943             :     return MCDisassembler::Fail;
    1944             : 
    1945             :   return S;
    1946             : }
    1947             : 
    1948             : // Check for UNPREDICTABLE predicated ESB instruction
    1949          40 : static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
    1950             :                                  uint64_t Address, const void *Decoder) {
    1951             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    1952             :   unsigned imm8 = fieldFromInstruction(Insn, 0, 8);
    1953             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
    1954          40 :   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
    1955             : 
    1956             :   DecodeStatus S = MCDisassembler::Success;
    1957             : 
    1958         120 :   Inst.addOperand(MCOperand::createImm(imm8));
    1959             : 
    1960          80 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    1961             :     return MCDisassembler::Fail;
    1962             : 
    1963             :   // ESB is unpredictable if pred != AL. Without the RAS extension, it is a NOP,
    1964             :   // so all predicates should be allowed.
    1965          40 :   if (imm8 == 0x10 && pred != 0xe && ((FeatureBits[ARM::FeatureRAS]) != 0))
    1966             :     S = MCDisassembler::SoftFail;
    1967             : 
    1968             :   return S;
    1969             : }
    1970             : 
    1971          15 : static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
    1972             :                                  uint64_t Address, const void *Decoder) {
    1973             :   unsigned imod = fieldFromInstruction(Insn, 18, 2);
    1974             :   unsigned M = fieldFromInstruction(Insn, 17, 1);
    1975             :   unsigned iflags = fieldFromInstruction(Insn, 6, 3);
    1976             :   unsigned mode = fieldFromInstruction(Insn, 0, 5);
    1977             : 
    1978             :   DecodeStatus S = MCDisassembler::Success;
    1979             : 
    1980             :   // This decoder is called from multiple location that do not check
    1981             :   // the full encoding is valid before they do.
    1982          14 :   if (fieldFromInstruction(Insn, 5, 1) != 0 ||
    1983          29 :       fieldFromInstruction(Insn, 16, 1) != 0 ||
    1984             :       fieldFromInstruction(Insn, 20, 8) != 0x10)
    1985             :     return MCDisassembler::Fail;
    1986             : 
    1987             :   // imod == '01' --> UNPREDICTABLE
    1988             :   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
    1989             :   // return failure here.  The '01' imod value is unprintable, so there's
    1990             :   // nothing useful we could do even if we returned UNPREDICTABLE.
    1991             : 
    1992          10 :   if (imod == 1) return MCDisassembler::Fail;
    1993             : 
    1994           9 :   if (imod && M) {
    1995             :     Inst.setOpcode(ARM::CPS3p);
    1996          12 :     Inst.addOperand(MCOperand::createImm(imod));
    1997          12 :     Inst.addOperand(MCOperand::createImm(iflags));
    1998          12 :     Inst.addOperand(MCOperand::createImm(mode));
    1999           5 :   } else if (imod && !M) {
    2000             :     Inst.setOpcode(ARM::CPS2p);
    2001           6 :     Inst.addOperand(MCOperand::createImm(imod));
    2002           6 :     Inst.addOperand(MCOperand::createImm(iflags));
    2003           2 :     if (mode) S = MCDisassembler::SoftFail;
    2004           3 :   } else if (!imod && M) {
    2005             :     Inst.setOpcode(ARM::CPS1p);
    2006           9 :     Inst.addOperand(MCOperand::createImm(mode));
    2007           3 :     if (iflags) S = MCDisassembler::SoftFail;
    2008             :   } else {
    2009             :     // imod == '00' && M == '0' --> UNPREDICTABLE
    2010             :     Inst.setOpcode(ARM::CPS1p);
    2011           0 :     Inst.addOperand(MCOperand::createImm(mode));
    2012             :     S = MCDisassembler::SoftFail;
    2013             :   }
    2014             : 
    2015             :   return S;
    2016             : }
    2017             : 
    2018           3 : static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
    2019             :                                  uint64_t Address, const void *Decoder) {
    2020             :   unsigned imod = fieldFromInstruction(Insn, 9, 2);
    2021             :   unsigned M = fieldFromInstruction(Insn, 8, 1);
    2022             :   unsigned iflags = fieldFromInstruction(Insn, 5, 3);
    2023             :   unsigned mode = fieldFromInstruction(Insn, 0, 5);
    2024             : 
    2025             :   DecodeStatus S = MCDisassembler::Success;
    2026             : 
    2027             :   // imod == '01' --> UNPREDICTABLE
    2028             :   // NOTE: Even though this is technically UNPREDICTABLE, we choose to
    2029             :   // return failure here.  The '01' imod value is unprintable, so there's
    2030             :   // nothing useful we could do even if we returned UNPREDICTABLE.
    2031             : 
    2032           3 :   if (imod == 1) return MCDisassembler::Fail;
    2033             : 
    2034           3 :   if (imod && M) {
    2035             :     Inst.setOpcode(ARM::t2CPS3p);
    2036           3 :     Inst.addOperand(MCOperand::createImm(imod));
    2037           3 :     Inst.addOperand(MCOperand::createImm(iflags));
    2038           3 :     Inst.addOperand(MCOperand::createImm(mode));
    2039           2 :   } else if (imod && !M) {
    2040             :     Inst.setOpcode(ARM::t2CPS2p);
    2041           3 :     Inst.addOperand(MCOperand::createImm(imod));
    2042           3 :     Inst.addOperand(MCOperand::createImm(iflags));
    2043           1 :     if (mode) S = MCDisassembler::SoftFail;
    2044           1 :   } else if (!imod && M) {
    2045             :     Inst.setOpcode(ARM::t2CPS1p);
    2046           3 :     Inst.addOperand(MCOperand::createImm(mode));
    2047           1 :     if (iflags) S = MCDisassembler::SoftFail;
    2048             :   } else {
    2049             :     // imod == '00' && M == '0' --> this is a HINT instruction
    2050           0 :     int imm = fieldFromInstruction(Insn, 0, 8);
    2051             :     // HINT are defined only for immediate in [0..4]
    2052           0 :     if(imm > 4) return MCDisassembler::Fail;
    2053             :     Inst.setOpcode(ARM::t2HINT);
    2054           0 :     Inst.addOperand(MCOperand::createImm(imm));
    2055             :   }
    2056             : 
    2057             :   return S;
    2058             : }
    2059             : 
    2060         284 : static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
    2061             :                                  uint64_t Address, const void *Decoder) {
    2062             :   DecodeStatus S = MCDisassembler::Success;
    2063             : 
    2064             :   unsigned Rd = fieldFromInstruction(Insn, 8, 4);
    2065             :   unsigned imm = 0;
    2066             : 
    2067             :   imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
    2068         284 :   imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
    2069         284 :   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
    2070         284 :   imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
    2071             : 
    2072         284 :   if (Inst.getOpcode() == ARM::t2MOVTi16)
    2073         218 :     if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
    2074             :       return MCDisassembler::Fail;
    2075         568 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
    2076             :     return MCDisassembler::Fail;
    2077             : 
    2078         284 :   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
    2079         538 :     Inst.addOperand(MCOperand::createImm(imm));
    2080             : 
    2081             :   return S;
    2082             : }
    2083             : 
    2084         211 : static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
    2085             :                                  uint64_t Address, const void *Decoder) {
    2086             :   DecodeStatus S = MCDisassembler::Success;
    2087             : 
    2088             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2089             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2090             :   unsigned imm = 0;
    2091             : 
    2092             :   imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
    2093         211 :   imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
    2094             : 
    2095         211 :   if (Inst.getOpcode() == ARM::MOVTi16)
    2096         192 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2097             :       return MCDisassembler::Fail;
    2098             : 
    2099         422 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2100             :     return MCDisassembler::Fail;
    2101             : 
    2102         211 :   if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
    2103         412 :     Inst.addOperand(MCOperand::createImm(imm));
    2104             : 
    2105         422 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2106             :     return MCDisassembler::Fail;
    2107             : 
    2108         154 :   return S;
    2109             : }
    2110             : 
    2111          17 : static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
    2112             :                                  uint64_t Address, const void *Decoder) {
    2113             :   DecodeStatus S = MCDisassembler::Success;
    2114             : 
    2115             :   unsigned Rd = fieldFromInstruction(Insn, 16, 4);
    2116             :   unsigned Rn = fieldFromInstruction(Insn, 0, 4);
    2117             :   unsigned Rm = fieldFromInstruction(Insn, 8, 4);
    2118             :   unsigned Ra = fieldFromInstruction(Insn, 12, 4);
    2119             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2120             : 
    2121          17 :   if (pred == 0xF)
    2122           5 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    2123             : 
    2124          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    2125             :     return MCDisassembler::Fail;
    2126          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    2127             :     return MCDisassembler::Fail;
    2128          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    2129             :     return MCDisassembler::Fail;
    2130          24 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
    2131             :     return MCDisassembler::Fail;
    2132             : 
    2133          24 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2134             :     return MCDisassembler::Fail;
    2135             : 
    2136             :   return S;
    2137             : }
    2138             : 
    2139           5 : static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
    2140             :                                   uint64_t Address, const void *Decoder) {
    2141             :   DecodeStatus S = MCDisassembler::Success;
    2142             : 
    2143             :   unsigned Pred = fieldFromInstruction(Insn, 28, 4);
    2144             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2145             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2146             : 
    2147           5 :   if (Pred == 0xF)
    2148           2 :     return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
    2149             : 
    2150           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2151             :     return MCDisassembler::Fail;
    2152           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2153             :     return MCDisassembler::Fail;
    2154           6 :   if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
    2155             :     return MCDisassembler::Fail;
    2156             : 
    2157             :   return S;
    2158             : }
    2159             : 
    2160           2 : static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
    2161             :                                   uint64_t Address, const void *Decoder) {
    2162             :   DecodeStatus S = MCDisassembler::Success;
    2163             : 
    2164             :   unsigned Imm = fieldFromInstruction(Insn, 9, 1);
    2165             : 
    2166             :   const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
    2167           2 :   const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
    2168             : 
    2169           3 :   if (!FeatureBits[ARM::HasV8_1aOps] || 
    2170             :       !FeatureBits[ARM::HasV8Ops])
    2171             :     return MCDisassembler::Fail;
    2172             : 
    2173             :   // Decoder can be called from DecodeTST, which does not check the full
    2174             :   // encoding is valid.
    2175           2 :   if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
    2176             :       fieldFromInstruction(Insn, 4,4) != 0)
    2177             :     return MCDisassembler::Fail;
    2178           2 :   if (fieldFromInstruction(Insn, 10,10) != 0 ||
    2179             :       fieldFromInstruction(Insn, 0,4) != 0)
    2180             :     S = MCDisassembler::SoftFail;
    2181             : 
    2182             :   Inst.setOpcode(ARM::SETPAN);
    2183           3 :   Inst.addOperand(MCOperand::createImm(Imm));
    2184             : 
    2185             :   return S;
    2186             : }
    2187             : 
    2188         111 : static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
    2189             :                            uint64_t Address, const void *Decoder) {
    2190             :   DecodeStatus S = MCDisassembler::Success;
    2191             : 
    2192             :   unsigned add = fieldFromInstruction(Val, 12, 1);
    2193             :   unsigned imm = fieldFromInstruction(Val, 0, 12);
    2194             :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    2195             : 
    2196         222 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2197             :     return MCDisassembler::Fail;
    2198             : 
    2199         111 :   if (!add) imm *= -1;
    2200         111 :   if (imm == 0 && !add) imm = INT32_MIN;
    2201         333 :   Inst.addOperand(MCOperand::createImm(imm));
    2202         111 :   if (Rn == 15)
    2203          22 :     tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
    2204             : 
    2205             :   return S;
    2206             : }
    2207             : 
    2208          19 : static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
    2209             :                                    uint64_t Address, const void *Decoder) {
    2210             :   DecodeStatus S = MCDisassembler::Success;
    2211             : 
    2212             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    2213             :   // U == 1 to add imm, 0 to subtract it.
    2214             :   unsigned U = fieldFromInstruction(Val, 8, 1);
    2215             :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    2216             : 
    2217          38 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2218             :     return MCDisassembler::Fail;
    2219             : 
    2220          19 :   if (U)
    2221          45 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
    2222             :   else
    2223          16 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
    2224             : 
    2225             :   return S;
    2226             : }
    2227             : 
    2228          16 : static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
    2229             :                                    uint64_t Address, const void *Decoder) {
    2230             :   DecodeStatus S = MCDisassembler::Success;
    2231             : 
    2232             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    2233             :   // U == 1 to add imm, 0 to subtract it.
    2234             :   unsigned U = fieldFromInstruction(Val, 8, 1);
    2235             :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    2236             : 
    2237          32 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2238             :     return MCDisassembler::Fail;
    2239             : 
    2240          16 :   if (U)
    2241          24 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
    2242             :   else
    2243          32 :     Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
    2244             : 
    2245             :   return S;
    2246             : }
    2247             : 
    2248             : static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
    2249             :                                    uint64_t Address, const void *Decoder) {
    2250          74 :   return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
    2251             : }
    2252             : 
    2253             : static DecodeStatus
    2254          35 : DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
    2255             :                      uint64_t Address, const void *Decoder) {
    2256             :   DecodeStatus Status = MCDisassembler::Success;
    2257             : 
    2258             :   // Note the J1 and J2 values are from the encoded instruction.  So here
    2259             :   // change them to I1 and I2 values via as documented:
    2260             :   // I1 = NOT(J1 EOR S);
    2261             :   // I2 = NOT(J2 EOR S);
    2262             :   // and build the imm32 with one trailing zero as documented:
    2263             :   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
    2264             :   unsigned S = fieldFromInstruction(Insn, 26, 1);
    2265             :   unsigned J1 = fieldFromInstruction(Insn, 13, 1);
    2266             :   unsigned J2 = fieldFromInstruction(Insn, 11, 1);
    2267          35 :   unsigned I1 = !(J1 ^ S);
    2268          35 :   unsigned I2 = !(J2 ^ S);
    2269             :   unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
    2270             :   unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
    2271          35 :   unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
    2272             :   int imm32 = SignExtend32<25>(tmp << 1);
    2273          70 :   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
    2274             :                                 true, 4, Inst, Decoder))
    2275         105 :     Inst.addOperand(MCOperand::createImm(imm32));
    2276             : 
    2277          35 :   return Status;
    2278             : }
    2279             : 
    2280             : static DecodeStatus
    2281         300 : DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
    2282             :                            uint64_t Address, const void *Decoder) {
    2283             :   DecodeStatus S = MCDisassembler::Success;
    2284             : 
    2285             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    2286         300 :   unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
    2287             : 
    2288         300 :   if (pred == 0xF) {
    2289             :     Inst.setOpcode(ARM::BLXi);
    2290          21 :     imm |= fieldFromInstruction(Insn, 24, 1) << 1;
    2291          42 :     if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
    2292             :                                   true, 4, Inst, Decoder))
    2293          63 :     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
    2294             :     return S;
    2295             :   }
    2296             : 
    2297         558 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
    2298             :                                 true, 4, Inst, Decoder))
    2299         837 :     Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
    2300         558 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    2301             :     return MCDisassembler::Fail;
    2302             : 
    2303         279 :   return S;
    2304             : }
    2305             : 
    2306         626 : static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
    2307             :                                    uint64_t Address, const void *Decoder) {
    2308             :   DecodeStatus S = MCDisassembler::Success;
    2309             : 
    2310             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    2311             :   unsigned align = fieldFromInstruction(Val, 4, 2);
    2312             : 
    2313        1252 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2314             :     return MCDisassembler::Fail;
    2315         626 :   if (!align)
    2316        1120 :     Inst.addOperand(MCOperand::createImm(0));
    2317             :   else
    2318         198 :     Inst.addOperand(MCOperand::createImm(4 << align));
    2319             : 
    2320             :   return S;
    2321             : }
    2322             : 
    2323         322 : static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
    2324             :                                    uint64_t Address, const void *Decoder) {
    2325             :   DecodeStatus S = MCDisassembler::Success;
    2326             : 
    2327             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2328         322 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2329             :   unsigned wb = fieldFromInstruction(Insn, 16, 4);
    2330             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2331         322 :   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
    2332             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2333             : 
    2334             :   // First output register
    2335         322 :   switch (Inst.getOpcode()) {
    2336          93 :   case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
    2337             :   case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
    2338             :   case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
    2339             :   case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
    2340             :   case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
    2341             :   case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
    2342             :   case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
    2343             :   case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
    2344             :   case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
    2345         186 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2346             :       return MCDisassembler::Fail;
    2347             :     break;
    2348          18 :   case ARM::VLD2b16:
    2349             :   case ARM::VLD2b32:
    2350             :   case ARM::VLD2b8:
    2351             :   case ARM::VLD2b16wb_fixed:
    2352             :   case ARM::VLD2b16wb_register:
    2353             :   case ARM::VLD2b32wb_fixed:
    2354             :   case ARM::VLD2b32wb_register:
    2355             :   case ARM::VLD2b8wb_fixed:
    2356             :   case ARM::VLD2b8wb_register:
    2357          36 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2358             :       return MCDisassembler::Fail;
    2359             :     break;
    2360         211 :   default:
    2361         422 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2362             :       return MCDisassembler::Fail;
    2363             :   }
    2364             : 
    2365             :   // Second output register
    2366         322 :   switch (Inst.getOpcode()) {
    2367          37 :     case ARM::VLD3d8:
    2368             :     case ARM::VLD3d16:
    2369             :     case ARM::VLD3d32:
    2370             :     case ARM::VLD3d8_UPD:
    2371             :     case ARM::VLD3d16_UPD:
    2372             :     case ARM::VLD3d32_UPD:
    2373             :     case ARM::VLD4d8:
    2374             :     case ARM::VLD4d16:
    2375             :     case ARM::VLD4d32:
    2376             :     case ARM::VLD4d8_UPD:
    2377             :     case ARM::VLD4d16_UPD:
    2378             :     case ARM::VLD4d32_UPD:
    2379          74 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
    2380             :         return MCDisassembler::Fail;
    2381             :       break;
    2382          49 :     case ARM::VLD3q8:
    2383             :     case ARM::VLD3q16:
    2384             :     case ARM::VLD3q32:
    2385             :     case ARM::VLD3q8_UPD:
    2386             :     case ARM::VLD3q16_UPD:
    2387             :     case ARM::VLD3q32_UPD:
    2388             :     case ARM::VLD4q8:
    2389             :     case ARM::VLD4q16:
    2390             :     case ARM::VLD4q32:
    2391             :     case ARM::VLD4q8_UPD:
    2392             :     case ARM::VLD4q16_UPD:
    2393             :     case ARM::VLD4q32_UPD:
    2394          98 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2395             :         return MCDisassembler::Fail;
    2396             :       break;
    2397             :     default:
    2398             :       break;
    2399             :   }
    2400             : 
    2401             :   // Third output register
    2402         322 :   switch(Inst.getOpcode()) {
    2403          37 :     case ARM::VLD3d8:
    2404             :     case ARM::VLD3d16:
    2405             :     case ARM::VLD3d32:
    2406             :     case ARM::VLD3d8_UPD:
    2407             :     case ARM::VLD3d16_UPD:
    2408             :     case ARM::VLD3d32_UPD:
    2409             :     case ARM::VLD4d8:
    2410             :     case ARM::VLD4d16:
    2411             :     case ARM::VLD4d32:
    2412             :     case ARM::VLD4d8_UPD:
    2413             :     case ARM::VLD4d16_UPD:
    2414             :     case ARM::VLD4d32_UPD:
    2415          74 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2416             :         return MCDisassembler::Fail;
    2417             :       break;
    2418          49 :     case ARM::VLD3q8:
    2419             :     case ARM::VLD3q16:
    2420             :     case ARM::VLD3q32:
    2421             :     case ARM::VLD3q8_UPD:
    2422             :     case ARM::VLD3q16_UPD:
    2423             :     case ARM::VLD3q32_UPD:
    2424             :     case ARM::VLD4q8:
    2425             :     case ARM::VLD4q16:
    2426             :     case ARM::VLD4q32:
    2427             :     case ARM::VLD4q8_UPD:
    2428             :     case ARM::VLD4q16_UPD:
    2429             :     case ARM::VLD4q32_UPD:
    2430          98 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
    2431             :         return MCDisassembler::Fail;
    2432             :       break;
    2433             :     default:
    2434             :       break;
    2435             :   }
    2436             : 
    2437             :   // Fourth output register
    2438         322 :   switch (Inst.getOpcode()) {
    2439          19 :     case ARM::VLD4d8:
    2440             :     case ARM::VLD4d16:
    2441             :     case ARM::VLD4d32:
    2442             :     case ARM::VLD4d8_UPD:
    2443             :     case ARM::VLD4d16_UPD:
    2444             :     case ARM::VLD4d32_UPD:
    2445          38 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
    2446             :         return MCDisassembler::Fail;
    2447             :       break;
    2448          25 :     case ARM::VLD4q8:
    2449             :     case ARM::VLD4q16:
    2450             :     case ARM::VLD4q32:
    2451             :     case ARM::VLD4q8_UPD:
    2452             :     case ARM::VLD4q16_UPD:
    2453             :     case ARM::VLD4q32_UPD:
    2454          50 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
    2455             :         return MCDisassembler::Fail;
    2456             :       break;
    2457             :     default:
    2458             :       break;
    2459             :   }
    2460             : 
    2461             :   // Writeback operand
    2462         322 :   switch (Inst.getOpcode()) {
    2463             :     case ARM::VLD1d8wb_fixed:
    2464             :     case ARM::VLD1d16wb_fixed:
    2465             :     case ARM::VLD1d32wb_fixed:
    2466             :     case ARM::VLD1d64wb_fixed:
    2467             :     case ARM::VLD1d8wb_register:
    2468             :     case ARM::VLD1d16wb_register:
    2469             :     case ARM::VLD1d32wb_register:
    2470             :     case ARM::VLD1d64wb_register:
    2471             :     case ARM::VLD1q8wb_fixed:
    2472             :     case ARM::VLD1q16wb_fixed:
    2473             :     case ARM::VLD1q32wb_fixed:
    2474             :     case ARM::VLD1q64wb_fixed:
    2475             :     case ARM::VLD1q8wb_register:
    2476             :     case ARM::VLD1q16wb_register:
    2477             :     case ARM::VLD1q32wb_register:
    2478             :     case ARM::VLD1q64wb_register:
    2479             :     case ARM::VLD1d8Twb_fixed:
    2480             :     case ARM::VLD1d8Twb_register:
    2481             :     case ARM::VLD1d16Twb_fixed:
    2482             :     case ARM::VLD1d16Twb_register:
    2483             :     case ARM::VLD1d32Twb_fixed:
    2484             :     case ARM::VLD1d32Twb_register:
    2485             :     case ARM::VLD1d64Twb_fixed:
    2486             :     case ARM::VLD1d64Twb_register:
    2487             :     case ARM::VLD1d8Qwb_fixed:
    2488             :     case ARM::VLD1d8Qwb_register:
    2489             :     case ARM::VLD1d16Qwb_fixed:
    2490             :     case ARM::VLD1d16Qwb_register:
    2491             :     case ARM::VLD1d32Qwb_fixed:
    2492             :     case ARM::VLD1d32Qwb_register:
    2493             :     case ARM::VLD1d64Qwb_fixed:
    2494             :     case ARM::VLD1d64Qwb_register:
    2495             :     case ARM::VLD2d8wb_fixed:
    2496             :     case ARM::VLD2d16wb_fixed:
    2497             :     case ARM::VLD2d32wb_fixed:
    2498             :     case ARM::VLD2q8wb_fixed:
    2499             :     case ARM::VLD2q16wb_fixed:
    2500             :     case ARM::VLD2q32wb_fixed:
    2501             :     case ARM::VLD2d8wb_register:
    2502             :     case ARM::VLD2d16wb_register:
    2503             :     case ARM::VLD2d32wb_register:
    2504             :     case ARM::VLD2q8wb_register:
    2505             :     case ARM::VLD2q16wb_register:
    2506             :     case ARM::VLD2q32wb_register:
    2507             :     case ARM::VLD2b8wb_fixed:
    2508             :     case ARM::VLD2b16wb_fixed:
    2509             :     case ARM::VLD2b32wb_fixed:
    2510             :     case ARM::VLD2b8wb_register:
    2511             :     case ARM::VLD2b16wb_register:
    2512             :     case ARM::VLD2b32wb_register:
    2513         376 :       Inst.addOperand(MCOperand::createImm(0));
    2514         188 :       break;
    2515          49 :     case ARM::VLD3d8_UPD:
    2516             :     case ARM::VLD3d16_UPD:
    2517             :     case ARM::VLD3d32_UPD:
    2518             :     case ARM::VLD3q8_UPD:
    2519             :     case ARM::VLD3q16_UPD:
    2520             :     case ARM::VLD3q32_UPD:
    2521             :     case ARM::VLD4d8_UPD:
    2522             :     case ARM::VLD4d16_UPD:
    2523             :     case ARM::VLD4d32_UPD:
    2524             :     case ARM::VLD4q8_UPD:
    2525             :     case ARM::VLD4q16_UPD:
    2526             :     case ARM::VLD4q32_UPD:
    2527          98 :       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
    2528             :         return MCDisassembler::Fail;
    2529             :       break;
    2530             :     default:
    2531             :       break;
    2532             :   }
    2533             : 
    2534             :   // AddrMode6 Base (register+alignment)
    2535         644 :   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
    2536             :     return MCDisassembler::Fail;
    2537             : 
    2538             :   // AddrMode6 Offset (register)
    2539         322 :   switch (Inst.getOpcode()) {
    2540         175 :   default:
    2541             :     // The below have been updated to have explicit am6offset split
    2542             :     // between fixed and register offset. For those instructions not
    2543             :     // yet updated, we need to add an additional reg0 operand for the
    2544             :     // fixed variant.
    2545             :     //
    2546             :     // The fixed offset encodes as Rm == 0xd, so we check for that.
    2547         175 :     if (Rm == 0xd) {
    2548          72 :       Inst.addOperand(MCOperand::createReg(0));
    2549          36 :       break;
    2550             :     }
    2551             :     // Fall through to handle the register offset variant.
    2552             :     LLVM_FALLTHROUGH;
    2553             :   case ARM::VLD1d8wb_fixed:
    2554             :   case ARM::VLD1d16wb_fixed:
    2555             :   case ARM::VLD1d32wb_fixed:
    2556             :   case ARM::VLD1d64wb_fixed:
    2557             :   case ARM::VLD1d8Twb_fixed:
    2558             :   case ARM::VLD1d16Twb_fixed:
    2559             :   case ARM::VLD1d32Twb_fixed:
    2560             :   case ARM::VLD1d64Twb_fixed:
    2561             :   case ARM::VLD1d8Qwb_fixed:
    2562             :   case ARM::VLD1d16Qwb_fixed:
    2563             :   case ARM::VLD1d32Qwb_fixed:
    2564             :   case ARM::VLD1d64Qwb_fixed:
    2565             :   case ARM::VLD1d8wb_register:
    2566             :   case ARM::VLD1d16wb_register:
    2567             :   case ARM::VLD1d32wb_register:
    2568             :   case ARM::VLD1d64wb_register:
    2569             :   case ARM::VLD1q8wb_fixed:
    2570             :   case ARM::VLD1q16wb_fixed:
    2571             :   case ARM::VLD1q32wb_fixed:
    2572             :   case ARM::VLD1q64wb_fixed:
    2573             :   case ARM::VLD1q8wb_register:
    2574             :   case ARM::VLD1q16wb_register:
    2575             :   case ARM::VLD1q32wb_register:
    2576             :   case ARM::VLD1q64wb_register:
    2577             :     // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
    2578             :     // variant encodes Rm == 0xf. Anything else is a register offset post-
    2579             :     // increment and we need to add the register operand to the instruction.
    2580         333 :     if (Rm != 0xD && Rm != 0xF &&
    2581          71 :         !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2582             :       return MCDisassembler::Fail;
    2583             :     break;
    2584             :   case ARM::VLD2d8wb_fixed:
    2585             :   case ARM::VLD2d16wb_fixed:
    2586             :   case ARM::VLD2d32wb_fixed:
    2587             :   case ARM::VLD2b8wb_fixed:
    2588             :   case ARM::VLD2b16wb_fixed:
    2589             :   case ARM::VLD2b32wb_fixed:
    2590             :   case ARM::VLD2q8wb_fixed:
    2591             :   case ARM::VLD2q16wb_fixed:
    2592             :   case ARM::VLD2q32wb_fixed:
    2593             :     break;
    2594             :   }
    2595             : 
    2596             :   return S;
    2597             : }
    2598             : 
    2599         332 : static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
    2600             :                                    uint64_t Address, const void *Decoder) {
    2601             :   unsigned type = fieldFromInstruction(Insn, 8, 4);
    2602             :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2603         332 :   if (type == 6 && (align & 2)) return MCDisassembler::Fail;
    2604         328 :   if (type == 7 && (align & 2)) return MCDisassembler::Fail;
    2605         328 :   if (type == 10 && align == 3) return MCDisassembler::Fail;
    2606             : 
    2607             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2608         325 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2609             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2610             : }
    2611             : 
    2612         139 : static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
    2613             :                                    uint64_t Address, const void *Decoder) {
    2614             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2615         139 :   if (size == 3) return MCDisassembler::Fail;
    2616             : 
    2617             :   unsigned type = fieldFromInstruction(Insn, 8, 4);
    2618             :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2619         139 :   if (type == 8 && align == 3) return MCDisassembler::Fail;
    2620         136 :   if (type == 9 && align == 3) return MCDisassembler::Fail;
    2621             : 
    2622             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2623         133 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2624             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2625             : }
    2626             : 
    2627          84 : static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
    2628             :                                    uint64_t Address, const void *Decoder) {
    2629             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2630          84 :   if (size == 3) return MCDisassembler::Fail;
    2631             : 
    2632             :   unsigned align = fieldFromInstruction(Insn, 4, 2);
    2633          84 :   if (align & 2) return MCDisassembler::Fail;
    2634             : 
    2635             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2636          84 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2637             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2638             : }
    2639             : 
    2640          84 : static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
    2641             :                                    uint64_t Address, const void *Decoder) {
    2642             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2643          84 :   if (size == 3) return MCDisassembler::Fail;
    2644             : 
    2645             :   unsigned load = fieldFromInstruction(Insn, 21, 1);
    2646          84 :   return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
    2647             :               : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
    2648             : }
    2649             : 
    2650         304 : static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
    2651             :                                  uint64_t Address, const void *Decoder) {
    2652             :   DecodeStatus S = MCDisassembler::Success;
    2653             : 
    2654             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2655         304 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2656             :   unsigned wb = fieldFromInstruction(Insn, 16, 4);
    2657             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2658         304 :   Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
    2659             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2660             : 
    2661             :   // Writeback Operand
    2662         304 :   switch (Inst.getOpcode()) {
    2663         174 :     case ARM::VST1d8wb_fixed:
    2664             :     case ARM::VST1d16wb_fixed:
    2665             :     case ARM::VST1d32wb_fixed:
    2666             :     case ARM::VST1d64wb_fixed:
    2667             :     case ARM::VST1d8wb_register:
    2668             :     case ARM::VST1d16wb_register:
    2669             :     case ARM::VST1d32wb_register:
    2670             :     case ARM::VST1d64wb_register:
    2671             :     case ARM::VST1q8wb_fixed:
    2672             :     case ARM::VST1q16wb_fixed:
    2673             :     case ARM::VST1q32wb_fixed:
    2674             :     case ARM::VST1q64wb_fixed:
    2675             :     case ARM::VST1q8wb_register:
    2676             :     case ARM::VST1q16wb_register:
    2677             :     case ARM::VST1q32wb_register:
    2678             :     case ARM::VST1q64wb_register:
    2679             :     case ARM::VST1d8Twb_fixed:
    2680             :     case ARM::VST1d16Twb_fixed:
    2681             :     case ARM::VST1d32Twb_fixed:
    2682             :     case ARM::VST1d64Twb_fixed:
    2683             :     case ARM::VST1d8Twb_register:
    2684             :     case ARM::VST1d16Twb_register:
    2685             :     case ARM::VST1d32Twb_register:
    2686             :     case ARM::VST1d64Twb_register:
    2687             :     case ARM::VST1d8Qwb_fixed:
    2688             :     case ARM::VST1d16Qwb_fixed:
    2689             :     case ARM::VST1d32Qwb_fixed:
    2690             :     case ARM::VST1d64Qwb_fixed:
    2691             :     case ARM::VST1d8Qwb_register:
    2692             :     case ARM::VST1d16Qwb_register:
    2693             :     case ARM::VST1d32Qwb_register:
    2694             :     case ARM::VST1d64Qwb_register:
    2695             :     case ARM::VST2d8wb_fixed:
    2696             :     case ARM::VST2d16wb_fixed:
    2697             :     case ARM::VST2d32wb_fixed:
    2698             :     case ARM::VST2d8wb_register:
    2699             :     case ARM::VST2d16wb_register:
    2700             :     case ARM::VST2d32wb_register:
    2701             :     case ARM::VST2q8wb_fixed:
    2702             :     case ARM::VST2q16wb_fixed:
    2703             :     case ARM::VST2q32wb_fixed:
    2704             :     case ARM::VST2q8wb_register:
    2705             :     case ARM::VST2q16wb_register:
    2706             :     case ARM::VST2q32wb_register:
    2707             :     case ARM::VST2b8wb_fixed:
    2708             :     case ARM::VST2b16wb_fixed:
    2709             :     case ARM::VST2b32wb_fixed:
    2710             :     case ARM::VST2b8wb_register:
    2711             :     case ARM::VST2b16wb_register:
    2712             :     case ARM::VST2b32wb_register:
    2713         174 :       if (Rm == 0xF)
    2714             :         return MCDisassembler::Fail;
    2715         348 :       Inst.addOperand(MCOperand::createImm(0));
    2716         174 :       break;
    2717          48 :     case ARM::VST3d8_UPD:
    2718             :     case ARM::VST3d16_UPD:
    2719             :     case ARM::VST3d32_UPD:
    2720             :     case ARM::VST3q8_UPD:
    2721             :     case ARM::VST3q16_UPD:
    2722             :     case ARM::VST3q32_UPD:
    2723             :     case ARM::VST4d8_UPD:
    2724             :     case ARM::VST4d16_UPD:
    2725             :     case ARM::VST4d32_UPD:
    2726             :     case ARM::VST4q8_UPD:
    2727             :     case ARM::VST4q16_UPD:
    2728             :     case ARM::VST4q32_UPD:
    2729          96 :       if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
    2730             :         return MCDisassembler::Fail;
    2731             :       break;
    2732             :     default:
    2733             :       break;
    2734             :   }
    2735             : 
    2736             :   // AddrMode6 Base (register+alignment)
    2737         608 :   if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
    2738             :     return MCDisassembler::Fail;
    2739             : 
    2740             :   // AddrMode6 Offset (register)
    2741         304 :   switch (Inst.getOpcode()) {
    2742         181 :     default:
    2743         181 :       if (Rm == 0xD)
    2744          72 :         Inst.addOperand(MCOperand::createReg(0));
    2745         145 :       else if (Rm != 0xF) {
    2746         126 :         if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2747             :           return MCDisassembler::Fail;
    2748             :       }
    2749             :       break;
    2750             :     case ARM::VST1d8wb_fixed:
    2751             :     case ARM::VST1d16wb_fixed:
    2752             :     case ARM::VST1d32wb_fixed:
    2753             :     case ARM::VST1d64wb_fixed:
    2754             :     case ARM::VST1q8wb_fixed:
    2755             :     case ARM::VST1q16wb_fixed:
    2756             :     case ARM::VST1q32wb_fixed:
    2757             :     case ARM::VST1q64wb_fixed:
    2758             :     case ARM::VST1d8Twb_fixed:
    2759             :     case ARM::VST1d16Twb_fixed:
    2760             :     case ARM::VST1d32Twb_fixed:
    2761             :     case ARM::VST1d64Twb_fixed:
    2762             :     case ARM::VST1d8Qwb_fixed:
    2763             :     case ARM::VST1d16Qwb_fixed:
    2764             :     case ARM::VST1d32Qwb_fixed:
    2765             :     case ARM::VST1d64Qwb_fixed:
    2766             :     case ARM::VST2d8wb_fixed:
    2767             :     case ARM::VST2d16wb_fixed:
    2768             :     case ARM::VST2d32wb_fixed:
    2769             :     case ARM::VST2q8wb_fixed:
    2770             :     case ARM::VST2q16wb_fixed:
    2771             :     case ARM::VST2q32wb_fixed:
    2772             :     case ARM::VST2b8wb_fixed:
    2773             :     case ARM::VST2b16wb_fixed:
    2774             :     case ARM::VST2b32wb_fixed:
    2775             :       break;
    2776             :   }
    2777             : 
    2778             :   // First input register
    2779         304 :   switch (Inst.getOpcode()) {
    2780          93 :   case ARM::VST1q16:
    2781             :   case ARM::VST1q32:
    2782             :   case ARM::VST1q64:
    2783             :   case ARM::VST1q8:
    2784             :   case ARM::VST1q16wb_fixed:
    2785             :   case ARM::VST1q16wb_register:
    2786             :   case ARM::VST1q32wb_fixed:
    2787             :   case ARM::VST1q32wb_register:
    2788             :   case ARM::VST1q64wb_fixed:
    2789             :   case ARM::VST1q64wb_register:
    2790             :   case ARM::VST1q8wb_fixed:
    2791             :   case ARM::VST1q8wb_register:
    2792             :   case ARM::VST2d16:
    2793             :   case ARM::VST2d32:
    2794             :   case ARM::VST2d8:
    2795             :   case ARM::VST2d16wb_fixed:
    2796             :   case ARM::VST2d16wb_register:
    2797             :   case ARM::VST2d32wb_fixed:
    2798             :   case ARM::VST2d32wb_register:
    2799             :   case ARM::VST2d8wb_fixed:
    2800             :   case ARM::VST2d8wb_register:
    2801         186 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2802             :       return MCDisassembler::Fail;
    2803             :     break;
    2804          19 :   case ARM::VST2b16:
    2805             :   case ARM::VST2b32:
    2806             :   case ARM::VST2b8:
    2807             :   case ARM::VST2b16wb_fixed:
    2808             :   case ARM::VST2b16wb_register:
    2809             :   case ARM::VST2b32wb_fixed:
    2810             :   case ARM::VST2b32wb_register:
    2811             :   case ARM::VST2b8wb_fixed:
    2812             :   case ARM::VST2b8wb_register:
    2813          38 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2814             :       return MCDisassembler::Fail;
    2815             :     break;
    2816         192 :   default:
    2817         384 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2818             :       return MCDisassembler::Fail;
    2819             :   }
    2820             : 
    2821             :   // Second input register
    2822         304 :   switch (Inst.getOpcode()) {
    2823          34 :     case ARM::VST3d8:
    2824             :     case ARM::VST3d16:
    2825             :     case ARM::VST3d32:
    2826             :     case ARM::VST3d8_UPD:
    2827             :     case ARM::VST3d16_UPD:
    2828             :     case ARM::VST3d32_UPD:
    2829             :     case ARM::VST4d8:
    2830             :     case ARM::VST4d16:
    2831             :     case ARM::VST4d32:
    2832             :     case ARM::VST4d8_UPD:
    2833             :     case ARM::VST4d16_UPD:
    2834             :     case ARM::VST4d32_UPD:
    2835          68 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
    2836             :         return MCDisassembler::Fail;
    2837             :       break;
    2838          48 :     case ARM::VST3q8:
    2839             :     case ARM::VST3q16:
    2840             :     case ARM::VST3q32:
    2841             :     case ARM::VST3q8_UPD:
    2842             :     case ARM::VST3q16_UPD:
    2843             :     case ARM::VST3q32_UPD:
    2844             :     case ARM::VST4q8:
    2845             :     case ARM::VST4q16:
    2846             :     case ARM::VST4q32:
    2847             :     case ARM::VST4q8_UPD:
    2848             :     case ARM::VST4q16_UPD:
    2849             :     case ARM::VST4q32_UPD:
    2850          96 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2851             :         return MCDisassembler::Fail;
    2852             :       break;
    2853             :     default:
    2854             :       break;
    2855             :   }
    2856             : 
    2857             :   // Third input register
    2858         304 :   switch (Inst.getOpcode()) {
    2859          34 :     case ARM::VST3d8:
    2860             :     case ARM::VST3d16:
    2861             :     case ARM::VST3d32:
    2862             :     case ARM::VST3d8_UPD:
    2863             :     case ARM::VST3d16_UPD:
    2864             :     case ARM::VST3d32_UPD:
    2865             :     case ARM::VST4d8:
    2866             :     case ARM::VST4d16:
    2867             :     case ARM::VST4d32:
    2868             :     case ARM::VST4d8_UPD:
    2869             :     case ARM::VST4d16_UPD:
    2870             :     case ARM::VST4d32_UPD:
    2871          68 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
    2872             :         return MCDisassembler::Fail;
    2873             :       break;
    2874          48 :     case ARM::VST3q8:
    2875             :     case ARM::VST3q16:
    2876             :     case ARM::VST3q32:
    2877             :     case ARM::VST3q8_UPD:
    2878             :     case ARM::VST3q16_UPD:
    2879             :     case ARM::VST3q32_UPD:
    2880             :     case ARM::VST4q8:
    2881             :     case ARM::VST4q16:
    2882             :     case ARM::VST4q32:
    2883             :     case ARM::VST4q8_UPD:
    2884             :     case ARM::VST4q16_UPD:
    2885             :     case ARM::VST4q32_UPD:
    2886          96 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
    2887             :         return MCDisassembler::Fail;
    2888             :       break;
    2889             :     default:
    2890             :       break;
    2891             :   }
    2892             : 
    2893             :   // Fourth input register
    2894         304 :   switch (Inst.getOpcode()) {
    2895          16 :     case ARM::VST4d8:
    2896             :     case ARM::VST4d16:
    2897             :     case ARM::VST4d32:
    2898             :     case ARM::VST4d8_UPD:
    2899             :     case ARM::VST4d16_UPD:
    2900             :     case ARM::VST4d32_UPD:
    2901          32 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
    2902             :         return MCDisassembler::Fail;
    2903             :       break;
    2904          24 :     case ARM::VST4q8:
    2905             :     case ARM::VST4q16:
    2906             :     case ARM::VST4q32:
    2907             :     case ARM::VST4q8_UPD:
    2908             :     case ARM::VST4q16_UPD:
    2909             :     case ARM::VST4q32_UPD:
    2910          48 :       if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
    2911             :         return MCDisassembler::Fail;
    2912             :       break;
    2913             :     default:
    2914             :       break;
    2915             :   }
    2916             : 
    2917             :   return S;
    2918             : }
    2919             : 
    2920           3 : static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
    2921             :                                     uint64_t Address, const void *Decoder) {
    2922             :   DecodeStatus S = MCDisassembler::Success;
    2923             : 
    2924             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2925           3 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2926             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2927             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2928             :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    2929             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    2930             : 
    2931           3 :   if (size == 0 && align == 1)
    2932             :     return MCDisassembler::Fail;
    2933           2 :   align *= (1 << size);
    2934             : 
    2935           2 :   switch (Inst.getOpcode()) {
    2936           1 :   case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
    2937             :   case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
    2938             :   case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
    2939             :   case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
    2940           2 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2941             :       return MCDisassembler::Fail;
    2942             :     break;
    2943           1 :   default:
    2944           2 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2945             :       return MCDisassembler::Fail;
    2946             :     break;
    2947             :   }
    2948           2 :   if (Rm != 0xF) {
    2949           4 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2950             :       return MCDisassembler::Fail;
    2951             :   }
    2952             : 
    2953           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    2954             :     return MCDisassembler::Fail;
    2955           6 :   Inst.addOperand(MCOperand::createImm(align));
    2956             : 
    2957             :   // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
    2958             :   // variant encodes Rm == 0xf. Anything else is a register offset post-
    2959             :   // increment and we need to add the register operand to the instruction.
    2960           3 :   if (Rm != 0xD && Rm != 0xF &&
    2961           1 :       !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    2962             :     return MCDisassembler::Fail;
    2963             : 
    2964             :   return S;
    2965             : }
    2966             : 
    2967          42 : static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
    2968             :                                     uint64_t Address, const void *Decoder) {
    2969             :   DecodeStatus S = MCDisassembler::Success;
    2970             : 
    2971             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    2972          42 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    2973             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    2974             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    2975             :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    2976             :   unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
    2977          42 :   align *= 2*size;
    2978             : 
    2979          42 :   switch (Inst.getOpcode()) {
    2980          18 :   case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
    2981             :   case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
    2982             :   case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
    2983             :   case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
    2984          36 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
    2985             :       return MCDisassembler::Fail;
    2986             :     break;
    2987          24 :   case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
    2988             :   case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
    2989             :   case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
    2990             :   case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
    2991          48 :     if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
    2992             :       return MCDisassembler::Fail;
    2993             :     break;
    2994           0 :   default:
    2995           0 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    2996             :       return MCDisassembler::Fail;
    2997             :     break;
    2998             :   }
    2999             : 
    3000          42 :   if (Rm != 0xF)
    3001          56 :     Inst.addOperand(MCOperand::createImm(0));
    3002             : 
    3003          84 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3004             :     return MCDisassembler::Fail;
    3005         126 :   Inst.addOperand(MCOperand::createImm(align));
    3006             : 
    3007          42 :   if (Rm != 0xD && Rm != 0xF) {
    3008          28 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3009             :       return MCDisassembler::Fail;
    3010             :   }
    3011             : 
    3012             :   return S;
    3013             : }
    3014             : 
    3015          18 : static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
    3016             :                                     uint64_t Address, const void *Decoder) {
    3017             :   DecodeStatus S = MCDisassembler::Success;
    3018             : 
    3019             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3020          18 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3021             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3022             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3023          18 :   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
    3024             : 
    3025          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3026             :     return MCDisassembler::Fail;
    3027          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
    3028             :     return MCDisassembler::Fail;
    3029          36 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
    3030             :     return MCDisassembler::Fail;
    3031          18 :   if (Rm != 0xF) {
    3032          24 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3033             :       return MCDisassembler::Fail;
    3034             :   }
    3035             : 
    3036          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3037             :     return MCDisassembler::Fail;
    3038          36 :   Inst.addOperand(MCOperand::createImm(0));
    3039             : 
    3040          18 :   if (Rm == 0xD)
    3041          12 :     Inst.addOperand(MCOperand::createReg(0));
    3042          12 :   else if (Rm != 0xF) {
    3043          12 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3044             :       return MCDisassembler::Fail;
    3045             :   }
    3046             : 
    3047             :   return S;
    3048             : }
    3049             : 
    3050          27 : static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
    3051             :                                     uint64_t Address, const void *Decoder) {
    3052             :   DecodeStatus S = MCDisassembler::Success;
    3053             : 
    3054             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3055          27 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3056             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3057             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3058             :   unsigned size = fieldFromInstruction(Insn, 6, 2);
    3059          27 :   unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
    3060             :   unsigned align = fieldFromInstruction(Insn, 4, 1);
    3061             : 
    3062          27 :   if (size == 0x3) {
    3063           6 :     if (align == 0)
    3064             :       return MCDisassembler::Fail;
    3065             :     align = 16;
    3066             :   } else {
    3067          21 :     if (size == 2) {
    3068           4 :       align *= 8;
    3069             :     } else {
    3070             :       size = 1 << size;
    3071          17 :       align *= 4*size;
    3072             :     }
    3073             :   }
    3074             : 
    3075          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3076             :     return MCDisassembler::Fail;
    3077          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
    3078             :     return MCDisassembler::Fail;
    3079          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
    3080             :     return MCDisassembler::Fail;
    3081          50 :   if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
    3082             :     return MCDisassembler::Fail;
    3083          25 :   if (Rm != 0xF) {
    3084          26 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3085             :       return MCDisassembler::Fail;
    3086             :   }
    3087             : 
    3088          50 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3089             :     return MCDisassembler::Fail;
    3090          75 :   Inst.addOperand(MCOperand::createImm(align));
    3091             : 
    3092          25 :   if (Rm == 0xD)
    3093          14 :     Inst.addOperand(MCOperand::createReg(0));
    3094          18 :   else if (Rm != 0xF) {
    3095          12 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3096             :       return MCDisassembler::Fail;
    3097             :   }
    3098             : 
    3099             :   return S;
    3100             : }
    3101             : 
    3102             : static DecodeStatus
    3103          94 : DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
    3104             :                             uint64_t Address, const void *Decoder) {
    3105             :   DecodeStatus S = MCDisassembler::Success;
    3106             : 
    3107             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3108          94 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3109             :   unsigned imm = fieldFromInstruction(Insn, 0, 4);
    3110          94 :   imm |= fieldFromInstruction(Insn, 16, 3) << 4;
    3111          94 :   imm |= fieldFromInstruction(Insn, 24, 1) << 7;
    3112          94 :   imm |= fieldFromInstruction(Insn, 8, 4) << 8;
    3113          94 :   imm |= fieldFromInstruction(Insn, 5, 1) << 12;
    3114             :   unsigned Q = fieldFromInstruction(Insn, 6, 1);
    3115             : 
    3116          94 :   if (Q) {
    3117          88 :     if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3118             :     return MCDisassembler::Fail;
    3119             :   } else {
    3120         100 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3121             :     return MCDisassembler::Fail;
    3122             :   }
    3123             : 
    3124         282 :   Inst.addOperand(MCOperand::createImm(imm));
    3125             : 
    3126          94 :   switch (Inst.getOpcode()) {
    3127           4 :     case ARM::VORRiv4i16:
    3128             :     case ARM::VORRiv2i32:
    3129             :     case ARM::VBICiv4i16:
    3130             :     case ARM::VBICiv2i32:
    3131           8 :       if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3132             :         return MCDisassembler::Fail;
    3133             :       break;
    3134           8 :     case ARM::VORRiv8i16:
    3135             :     case ARM::VORRiv4i32:
    3136             :     case ARM::VBICiv8i16:
    3137             :     case ARM::VBICiv4i32:
    3138          16 :       if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3139             :         return MCDisassembler::Fail;
    3140             :       break;
    3141             :     default:
    3142             :       break;
    3143             :   }
    3144             : 
    3145             :   return S;
    3146             : }
    3147             : 
    3148           7 : static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
    3149             :                                         uint64_t Address, const void *Decoder) {
    3150             :   DecodeStatus S = MCDisassembler::Success;
    3151             : 
    3152             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3153           7 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3154             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3155           7 :   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
    3156             :   unsigned size = fieldFromInstruction(Insn, 18, 2);
    3157             : 
    3158          14 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
    3159             :     return MCDisassembler::Fail;
    3160          14 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
    3161             :     return MCDisassembler::Fail;
    3162          21 :   Inst.addOperand(MCOperand::createImm(8 << size));
    3163             : 
    3164           7 :   return S;
    3165             : }
    3166             : 
    3167             : static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
    3168             :                                uint64_t Address, const void *Decoder) {
    3169         180 :   Inst.addOperand(MCOperand::createImm(8 - Val));
    3170             :   return MCDisassembler::Success;
    3171             : }
    3172             : 
    3173             : static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
    3174             :                                uint64_t Address, const void *Decoder) {
    3175         180 :   Inst.addOperand(MCOperand::createImm(16 - Val));
    3176             :   return MCDisassembler::Success;
    3177             : }
    3178             : 
    3179             : static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
    3180             :                                uint64_t Address, const void *Decoder) {
    3181         186 :   Inst.addOperand(MCOperand::createImm(32 - Val));
    3182             :   return MCDisassembler::Success;
    3183             : }
    3184             : 
    3185             : static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
    3186             :                                uint64_t Address, const void *Decoder) {
    3187         126 :   Inst.addOperand(MCOperand::createImm(64 - Val));
    3188             :   return MCDisassembler::Success;
    3189             : }
    3190             : 
    3191          17 : static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
    3192             :                                uint64_t Address, const void *Decoder) {
    3193             :   DecodeStatus S = MCDisassembler::Success;
    3194             : 
    3195             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    3196          17 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    3197             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3198          17 :   Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
    3199             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3200          17 :   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
    3201             :   unsigned op = fieldFromInstruction(Insn, 6, 1);
    3202             : 
    3203          34 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3204             :     return MCDisassembler::Fail;
    3205          17 :   if (op) {
    3206          18 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    3207             :     return MCDisassembler::Fail; // Writeback
    3208             :   }
    3209             : 
    3210          17 :   switch (Inst.getOpcode()) {
    3211           4 :   case ARM::VTBL2:
    3212             :   case ARM::VTBX2:
    3213           8 :     if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
    3214             :       return MCDisassembler::Fail;
    3215             :     break;
    3216          13 :   default:
    3217          26 :     if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
    3218             :       return MCDisassembler::Fail;
    3219             :   }
    3220             : 
    3221          34 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
    3222             :     return MCDisassembler::Fail;
    3223             : 
    3224          17 :   return S;
    3225             : }
    3226             : 
    3227         342 : static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
    3228             :                                      uint64_t Address, const void *Decoder) {
    3229             :   DecodeStatus S = MCDisassembler::Success;
    3230             : 
    3231         342 :   unsigned dst = fieldFromInstruction(Insn, 8, 3);
    3232             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3233             : 
    3234         342 :   if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
    3235             :     return MCDisassembler::Fail;
    3236             : 
    3237         342 :   switch(Inst.getOpcode()) {
    3238             :     default:
    3239             :       return MCDisassembler::Fail;
    3240             :     case ARM::tADR:
    3241             :       break; // tADR does not explicitly represent the PC as an operand.
    3242             :     case ARM::tADDrSPi:
    3243         674 :       Inst.addOperand(MCOperand::createReg(ARM::SP));
    3244         337 :       break;
    3245             :   }
    3246             : 
    3247        1026 :   Inst.addOperand(MCOperand::createImm(imm));
    3248         342 :   return S;
    3249             : }
    3250             : 
    3251          41 : static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
    3252             :                                  uint64_t Address, const void *Decoder) {
    3253          82 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
    3254             :                                 true, 2, Inst, Decoder))
    3255         117 :     Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
    3256          41 :   return MCDisassembler::Success;
    3257             : }
    3258             : 
    3259          24 : static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
    3260             :                                  uint64_t Address, const void *Decoder) {
    3261          48 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
    3262             :                                 true, 4, Inst, Decoder))
    3263          72 :     Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
    3264          24 :   return MCDisassembler::Success;
    3265             : }
    3266             : 
    3267          10 : static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
    3268             :                                  uint64_t Address, const void *Decoder) {
    3269          20 :   if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
    3270             :                                 true, 2, Inst, Decoder))
    3271          30 :     Inst.addOperand(MCOperand::createImm(Val << 1));
    3272          10 :   return MCDisassembler::Success;
    3273             : }
    3274             : 
    3275          14 : static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
    3276             :                                  uint64_t Address, const void *Decoder) {
    3277             :   DecodeStatus S = MCDisassembler::Success;
    3278             : 
    3279             :   unsigned Rn = fieldFromInstruction(Val, 0, 3);
    3280             :   unsigned Rm = fieldFromInstruction(Val, 3, 3);
    3281             : 
    3282          14 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3283             :     return MCDisassembler::Fail;
    3284          14 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3285             :     return MCDisassembler::Fail;
    3286             : 
    3287             :   return S;
    3288             : }
    3289             : 
    3290        1905 : static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
    3291             :                                   uint64_t Address, const void *Decoder) {
    3292             :   DecodeStatus S = MCDisassembler::Success;
    3293             : 
    3294             :   unsigned Rn = fieldFromInstruction(Val, 0, 3);
    3295             :   unsigned imm = fieldFromInstruction(Val, 3, 5);
    3296             : 
    3297        1905 :   if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3298             :     return MCDisassembler::Fail;
    3299        5715 :   Inst.addOperand(MCOperand::createImm(imm));
    3300             : 
    3301             :   return S;
    3302             : }
    3303             : 
    3304          62 : static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
    3305             :                                   uint64_t Address, const void *Decoder) {
    3306          62 :   unsigned imm = Val << 2;
    3307             : 
    3308         186 :   Inst.addOperand(MCOperand::createImm(imm));
    3309          62 :   tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
    3310             : 
    3311          62 :   return MCDisassembler::Success;
    3312             : }
    3313             : 
    3314         279 : static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
    3315             :                                   uint64_t Address, const void *Decoder) {
    3316         558 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3317         837 :   Inst.addOperand(MCOperand::createImm(Val));
    3318             : 
    3319         279 :   return MCDisassembler::Success;
    3320             : }
    3321             : 
    3322          79 : static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
    3323             :                                   uint64_t Address, const void *Decoder) {
    3324             :   DecodeStatus S = MCDisassembler::Success;
    3325             : 
    3326             :   unsigned Rn = fieldFromInstruction(Val, 6, 4);
    3327             :   unsigned Rm = fieldFromInstruction(Val, 2, 4);
    3328             :   unsigned imm = fieldFromInstruction(Val, 0, 2);
    3329             : 
    3330             :   // Thumb stores cannot use PC as dest register.
    3331          79 :   switch (Inst.getOpcode()) {
    3332          14 :   case ARM::t2STRHs:
    3333             :   case ARM::t2STRBs:
    3334             :   case ARM::t2STRs:
    3335          14 :     if (Rn == 15)
    3336             :       return MCDisassembler::Fail;
    3337             :     break;
    3338             :   default:
    3339             :     break;
    3340             :   }
    3341             : 
    3342         142 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3343             :     return MCDisassembler::Fail;
    3344         142 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3345             :     return MCDisassembler::Fail;
    3346         213 :   Inst.addOperand(MCOperand::createImm(imm));
    3347             : 
    3348             :   return S;
    3349             : }
    3350             : 
    3351         105 : static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
    3352             :                               uint64_t Address, const void *Decoder) {
    3353             :   DecodeStatus S = MCDisassembler::Success;
    3354             : 
    3355             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3356             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3357             : 
    3358             :   const FeatureBitset &featureBits =
    3359         105 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3360             : 
    3361             :   bool hasMP = featureBits[ARM::FeatureMP];
    3362             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3363             : 
    3364         105 :   if (Rn == 15) {
    3365          26 :     switch (Inst.getOpcode()) {
    3366             :     case ARM::t2LDRBs:
    3367             :       Inst.setOpcode(ARM::t2LDRBpci);
    3368             :       break;
    3369             :     case ARM::t2LDRHs:
    3370             :       Inst.setOpcode(ARM::t2LDRHpci);
    3371             :       break;
    3372             :     case ARM::t2LDRSHs:
    3373             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3374             :       break;
    3375             :     case ARM::t2LDRSBs:
    3376             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3377             :       break;
    3378             :     case ARM::t2LDRs:
    3379             :       Inst.setOpcode(ARM::t2LDRpci);
    3380             :       break;
    3381             :     case ARM::t2PLDs:
    3382             :       Inst.setOpcode(ARM::t2PLDpci);
    3383             :       break;
    3384             :     case ARM::t2PLIs:
    3385             :       Inst.setOpcode(ARM::t2PLIpci);
    3386             :       break;
    3387             :     default:
    3388             :       return MCDisassembler::Fail;
    3389             :     }
    3390             : 
    3391          26 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3392             :   }
    3393             : 
    3394          79 :   if (Rt == 15) {
    3395          48 :     switch (Inst.getOpcode()) {
    3396             :     case ARM::t2LDRSHs:
    3397             :       return MCDisassembler::Fail;
    3398             :     case ARM::t2LDRHs:
    3399             :       Inst.setOpcode(ARM::t2PLDWs);
    3400             :       break;
    3401             :     case ARM::t2LDRSBs:
    3402             :       Inst.setOpcode(ARM::t2PLIs);
    3403             :       break;
    3404             :     default:
    3405             :       break;
    3406             :     }
    3407             :   }
    3408             : 
    3409          77 :   switch (Inst.getOpcode()) {
    3410             :     case ARM::t2PLDs:
    3411             :       break;
    3412           6 :     case ARM::t2PLIs:
    3413           6 :       if (!hasV7Ops)
    3414             :         return MCDisassembler::Fail;
    3415             :       break;
    3416          17 :     case ARM::t2PLDWs:
    3417          17 :       if (!hasV7Ops || !hasMP)
    3418             :         return MCDisassembler::Fail;
    3419             :       break;
    3420          31 :     default:
    3421          62 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3422             :         return MCDisassembler::Fail;
    3423             :   }
    3424             : 
    3425             :   unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
    3426          65 :   addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
    3427          65 :   addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
    3428         130 :   if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
    3429             :     return MCDisassembler::Fail;
    3430             : 
    3431             :   return S;
    3432             : }
    3433             : 
    3434          37 : static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
    3435             :                                 uint64_t Address, const void* Decoder) {
    3436             :   DecodeStatus S = MCDisassembler::Success;
    3437             : 
    3438             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3439             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3440             :   unsigned U = fieldFromInstruction(Insn, 9, 1);
    3441             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3442          37 :   imm |= (U << 8);
    3443          37 :   imm |= (Rn << 9);
    3444             :   unsigned add = fieldFromInstruction(Insn, 9, 1);
    3445             : 
    3446             :   const FeatureBitset &featureBits =
    3447          37 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3448             : 
    3449             :   bool hasMP = featureBits[ARM::FeatureMP];
    3450             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3451             : 
    3452          37 :   if (Rn == 15) {
    3453           0 :     switch (Inst.getOpcode()) {
    3454             :     case ARM::t2LDRi8:
    3455             :       Inst.setOpcode(ARM::t2LDRpci);
    3456             :       break;
    3457             :     case ARM::t2LDRBi8:
    3458             :       Inst.setOpcode(ARM::t2LDRBpci);
    3459             :       break;
    3460             :     case ARM::t2LDRSBi8:
    3461             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3462             :       break;
    3463             :     case ARM::t2LDRHi8:
    3464             :       Inst.setOpcode(ARM::t2LDRHpci);
    3465             :       break;
    3466             :     case ARM::t2LDRSHi8:
    3467             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3468             :       break;
    3469             :     case ARM::t2PLDi8:
    3470             :       Inst.setOpcode(ARM::t2PLDpci);
    3471             :       break;
    3472             :     case ARM::t2PLIi8:
    3473             :       Inst.setOpcode(ARM::t2PLIpci);
    3474             :       break;
    3475             :     default:
    3476             :       return MCDisassembler::Fail;
    3477             :     }
    3478           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3479             :   }
    3480             : 
    3481          37 :   if (Rt == 15) {
    3482          30 :     switch (Inst.getOpcode()) {
    3483             :     case ARM::t2LDRSHi8:
    3484             :       return MCDisassembler::Fail;
    3485           6 :     case ARM::t2LDRHi8:
    3486           6 :       if (!add)
    3487             :         Inst.setOpcode(ARM::t2PLDWi8);
    3488             :       break;
    3489             :     case ARM::t2LDRSBi8:
    3490             :       Inst.setOpcode(ARM::t2PLIi8);
    3491             :       break;
    3492             :     default:
    3493             :       break;
    3494             :     }
    3495             :   }
    3496             : 
    3497          33 :   switch (Inst.getOpcode()) {
    3498             :   case ARM::t2PLDi8:
    3499             :     break;
    3500           9 :   case ARM::t2PLIi8:
    3501           9 :     if (!hasV7Ops)
    3502             :       return MCDisassembler::Fail;
    3503             :     break;
    3504           8 :   case ARM::t2PLDWi8:
    3505           8 :       if (!hasV7Ops || !hasMP)
    3506             :         return MCDisassembler::Fail;
    3507             :       break;
    3508           7 :   default:
    3509          14 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3510             :       return MCDisassembler::Fail;
    3511             :   }
    3512             : 
    3513          50 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
    3514             :     return MCDisassembler::Fail;
    3515             :   return S;
    3516             : }
    3517             : 
    3518          89 : static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
    3519             :                                 uint64_t Address, const void* Decoder) {
    3520             :   DecodeStatus S = MCDisassembler::Success;
    3521             : 
    3522             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3523             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3524             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    3525          89 :   imm |= (Rn << 13);
    3526             : 
    3527             :   const FeatureBitset &featureBits =
    3528          89 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3529             : 
    3530             :   bool hasMP = featureBits[ARM::FeatureMP];
    3531             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3532             : 
    3533          89 :   if (Rn == 15) {
    3534          30 :     switch (Inst.getOpcode()) {
    3535             :     case ARM::t2LDRi12:
    3536             :       Inst.setOpcode(ARM::t2LDRpci);
    3537             :       break;
    3538             :     case ARM::t2LDRHi12:
    3539             :       Inst.setOpcode(ARM::t2LDRHpci);
    3540             :       break;
    3541             :     case ARM::t2LDRSHi12:
    3542             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3543             :       break;
    3544             :     case ARM::t2LDRBi12:
    3545             :       Inst.setOpcode(ARM::t2LDRBpci);
    3546             :       break;
    3547             :     case ARM::t2LDRSBi12:
    3548             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3549             :       break;
    3550             :     case ARM::t2PLDi12:
    3551             :       Inst.setOpcode(ARM::t2PLDpci);
    3552             :       break;
    3553             :     case ARM::t2PLIi12:
    3554             :       Inst.setOpcode(ARM::t2PLIpci);
    3555             :       break;
    3556             :     default:
    3557             :       return MCDisassembler::Fail;
    3558             :     }
    3559          30 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3560             :   }
    3561             : 
    3562          59 :   if (Rt == 15) {
    3563          39 :     switch (Inst.getOpcode()) {
    3564             :     case ARM::t2LDRSHi12:
    3565             :       return MCDisassembler::Fail;
    3566             :     case ARM::t2LDRHi12:
    3567             :       Inst.setOpcode(ARM::t2PLDWi12);
    3568             :       break;
    3569             :     case ARM::t2LDRSBi12:
    3570             :       Inst.setOpcode(ARM::t2PLIi12);
    3571             :       break;
    3572             :     default:
    3573             :       break;
    3574             :     }
    3575             :   }
    3576             : 
    3577          55 :   switch (Inst.getOpcode()) {
    3578             :   case ARM::t2PLDi12:
    3579             :     break;
    3580          12 :   case ARM::t2PLIi12:
    3581          12 :     if (!hasV7Ops)
    3582             :       return MCDisassembler::Fail;
    3583             :     break;
    3584           8 :   case ARM::t2PLDWi12:
    3585           8 :       if (!hasV7Ops || !hasMP)
    3586             :         return MCDisassembler::Fail;
    3587             :       break;
    3588          22 :   default:
    3589          44 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3590             :       return MCDisassembler::Fail;
    3591             :   }
    3592             : 
    3593          94 :   if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
    3594             :     return MCDisassembler::Fail;
    3595             :   return S;
    3596             : }
    3597             : 
    3598          19 : static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
    3599             :                                 uint64_t Address, const void* Decoder) {
    3600             :   DecodeStatus S = MCDisassembler::Success;
    3601             : 
    3602             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3603             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3604             :   unsigned imm = fieldFromInstruction(Insn, 0, 8);
    3605          19 :   imm |= (Rn << 9);
    3606             : 
    3607          19 :   if (Rn == 15) {
    3608           0 :     switch (Inst.getOpcode()) {
    3609             :     case ARM::t2LDRT:
    3610             :       Inst.setOpcode(ARM::t2LDRpci);
    3611             :       break;
    3612             :     case ARM::t2LDRBT:
    3613             :       Inst.setOpcode(ARM::t2LDRBpci);
    3614             :       break;
    3615             :     case ARM::t2LDRHT:
    3616             :       Inst.setOpcode(ARM::t2LDRHpci);
    3617             :       break;
    3618             :     case ARM::t2LDRSBT:
    3619             :       Inst.setOpcode(ARM::t2LDRSBpci);
    3620             :       break;
    3621             :     case ARM::t2LDRSHT:
    3622             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3623             :       break;
    3624             :     default:
    3625             :       return MCDisassembler::Fail;
    3626             :     }
    3627           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3628             :   }
    3629             : 
    3630          38 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3631             :     return MCDisassembler::Fail;
    3632          38 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
    3633             :     return MCDisassembler::Fail;
    3634             :   return S;
    3635             : }
    3636             : 
    3637          58 : static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
    3638             :                                 uint64_t Address, const void* Decoder) {
    3639             :   DecodeStatus S = MCDisassembler::Success;
    3640             : 
    3641             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3642             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    3643          58 :   int imm = fieldFromInstruction(Insn, 0, 12);
    3644             : 
    3645             :   const FeatureBitset &featureBits =
    3646          58 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3647             : 
    3648             :   bool hasV7Ops = featureBits[ARM::HasV7Ops];
    3649             : 
    3650          58 :   if (Rt == 15) {
    3651          39 :     switch (Inst.getOpcode()) {
    3652             :       case ARM::t2LDRBpci:
    3653             :       case ARM::t2LDRHpci:
    3654             :         Inst.setOpcode(ARM::t2PLDpci);
    3655             :         break;
    3656             :       case ARM::t2LDRSBpci:
    3657             :         Inst.setOpcode(ARM::t2PLIpci);
    3658             :         break;
    3659             :       case ARM::t2LDRSHpci:
    3660             :         return MCDisassembler::Fail;
    3661             :       default:
    3662             :         break;
    3663             :     }
    3664             :   }
    3665             : 
    3666          58 :   switch(Inst.getOpcode()) {
    3667             :   case ARM::t2PLDpci:
    3668             :     break;
    3669          19 :   case ARM::t2PLIpci:
    3670          19 :     if (!hasV7Ops)
    3671             :       return MCDisassembler::Fail;
    3672             :     break;
    3673          19 :   default:
    3674          38 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3675             :       return MCDisassembler::Fail;
    3676             :   }
    3677             : 
    3678          54 :   if (!U) {
    3679             :     // Special case for #-0.
    3680          26 :     if (imm == 0)
    3681             :       imm = INT32_MIN;
    3682             :     else
    3683          19 :       imm = -imm;
    3684             :   }
    3685         162 :   Inst.addOperand(MCOperand::createImm(imm));
    3686             : 
    3687             :   return S;
    3688             : }
    3689             : 
    3690          25 : static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
    3691             :                            uint64_t Address, const void *Decoder) {
    3692          25 :   if (Val == 0)
    3693          12 :     Inst.addOperand(MCOperand::createImm(INT32_MIN));
    3694             :   else {
    3695          19 :     int imm = Val & 0xFF;
    3696             : 
    3697          19 :     if (!(Val & 0x100)) imm *= -1;
    3698          57 :     Inst.addOperand(MCOperand::createImm(imm * 4));
    3699             :   }
    3700             : 
    3701          25 :   return MCDisassembler::Success;
    3702             : }
    3703             : 
    3704          17 : static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
    3705             :                                    uint64_t Address, const void *Decoder) {
    3706             :   DecodeStatus S = MCDisassembler::Success;
    3707             : 
    3708             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    3709             :   unsigned imm = fieldFromInstruction(Val, 0, 9);
    3710             : 
    3711          34 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3712             :     return MCDisassembler::Fail;
    3713          34 :   if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
    3714             :     return MCDisassembler::Fail;
    3715             : 
    3716             :   return S;
    3717             : }
    3718             : 
    3719           7 : static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
    3720             :                                    uint64_t Address, const void *Decoder) {
    3721             :   DecodeStatus S = MCDisassembler::Success;
    3722             : 
    3723             :   unsigned Rn = fieldFromInstruction(Val, 8, 4);
    3724             :   unsigned imm = fieldFromInstruction(Val, 0, 8);
    3725             : 
    3726          14 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    3727             :     return MCDisassembler::Fail;
    3728             : 
    3729          21 :   Inst.addOperand(MCOperand::createImm(imm));
    3730             : 
    3731             :   return S;
    3732             : }
    3733             : 
    3734         993 : static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
    3735             :                          uint64_t Address, const void *Decoder) {
    3736         993 :   int imm = Val & 0xFF;
    3737         993 :   if (Val == 0)
    3738             :     imm = INT32_MIN;
    3739         992 :   else if (!(Val & 0x100))
    3740          38 :     imm *= -1;
    3741        2979 :   Inst.addOperand(MCOperand::createImm(imm));
    3742             : 
    3743         993 :   return MCDisassembler::Success;
    3744             : }
    3745             : 
    3746        1005 : static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
    3747             :                                  uint64_t Address, const void *Decoder) {
    3748             :   DecodeStatus S = MCDisassembler::Success;
    3749             : 
    3750             :   unsigned Rn = fieldFromInstruction(Val, 9, 4);
    3751             :   unsigned imm = fieldFromInstruction(Val, 0, 9);
    3752             : 
    3753             :   // Thumb stores cannot use PC as dest register.
    3754        1005 :   switch (Inst.getOpcode()) {
    3755          21 :   case ARM::t2STRT:
    3756             :   case ARM::t2STRBT:
    3757             :   case ARM::t2STRHT:
    3758             :   case ARM::t2STRi8:
    3759             :   case ARM::t2STRHi8:
    3760             :   case ARM::t2STRBi8:
    3761          21 :     if (Rn == 15)
    3762             :       return MCDisassembler::Fail;
    3763             :     break;
    3764             :   default:
    3765             :     break;
    3766             :   }
    3767             : 
    3768             :   // Some instructions always use an additive offset.
    3769         993 :   switch (Inst.getOpcode()) {
    3770          27 :     case ARM::t2LDRT:
    3771             :     case ARM::t2LDRBT:
    3772             :     case ARM::t2LDRHT:
    3773             :     case ARM::t2LDRSBT:
    3774             :     case ARM::t2LDRSHT:
    3775             :     case ARM::t2STRT:
    3776             :     case ARM::t2STRBT:
    3777             :     case ARM::t2STRHT:
    3778          27 :       imm |= 0x100;
    3779             :       break;
    3780             :     default:
    3781             :       break;
    3782             :   }
    3783             : 
    3784        1986 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3785             :     return MCDisassembler::Fail;
    3786        1986 :   if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
    3787             :     return MCDisassembler::Fail;
    3788             : 
    3789             :   return S;
    3790             : }
    3791             : 
    3792         942 : static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
    3793             :                                     uint64_t Address, const void *Decoder) {
    3794             :   DecodeStatus S = MCDisassembler::Success;
    3795             : 
    3796             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    3797             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3798             :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    3799         942 :   addr |= fieldFromInstruction(Insn, 9, 1) << 8;
    3800         942 :   addr |= Rn << 9;
    3801             :   unsigned load = fieldFromInstruction(Insn, 20, 1);
    3802             : 
    3803         942 :   if (Rn == 15) {
    3804           2 :     switch (Inst.getOpcode()) {
    3805             :     case ARM::t2LDR_PRE:
    3806             :     case ARM::t2LDR_POST:
    3807             :       Inst.setOpcode(ARM::t2LDRpci);
    3808             :       break;
    3809             :     case ARM::t2LDRB_PRE:
    3810             :     case ARM::t2LDRB_POST:
    3811             :       Inst.setOpcode(ARM::t2LDRBpci);
    3812             :       break;
    3813             :     case ARM::t2LDRH_PRE:
    3814             :     case ARM::t2LDRH_POST:
    3815             :       Inst.setOpcode(ARM::t2LDRHpci);
    3816             :       break;
    3817           0 :     case ARM::t2LDRSB_PRE:
    3818             :     case ARM::t2LDRSB_POST:
    3819           0 :       if (Rt == 15)
    3820             :         Inst.setOpcode(ARM::t2PLIpci);
    3821             :       else
    3822             :         Inst.setOpcode(ARM::t2LDRSBpci);
    3823             :       break;
    3824             :     case ARM::t2LDRSH_PRE:
    3825             :     case ARM::t2LDRSH_POST:
    3826             :       Inst.setOpcode(ARM::t2LDRSHpci);
    3827             :       break;
    3828             :     default:
    3829             :       return MCDisassembler::Fail;
    3830             :     }
    3831           0 :     return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
    3832             :   }
    3833             : 
    3834         940 :   if (!load) {
    3835         910 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3836             :       return MCDisassembler::Fail;
    3837             :   }
    3838             : 
    3839        1880 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    3840             :     return MCDisassembler::Fail;
    3841             : 
    3842         940 :   if (load) {
    3843         970 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3844             :       return MCDisassembler::Fail;
    3845             :   }
    3846             : 
    3847        1880 :   if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
    3848             :     return MCDisassembler::Fail;
    3849             : 
    3850             :   return S;
    3851             : }
    3852             : 
    3853          57 : static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
    3854             :                                   uint64_t Address, const void *Decoder) {
    3855             :   DecodeStatus S = MCDisassembler::Success;
    3856             : 
    3857             :   unsigned Rn = fieldFromInstruction(Val, 13, 4);
    3858             :   unsigned imm = fieldFromInstruction(Val, 0, 12);
    3859             : 
    3860             :   // Thumb stores cannot use PC as dest register.
    3861          57 :   switch (Inst.getOpcode()) {
    3862          10 :   case ARM::t2STRi12:
    3863             :   case ARM::t2STRBi12:
    3864             :   case ARM::t2STRHi12:
    3865          10 :     if (Rn == 15)
    3866             :       return MCDisassembler::Fail;
    3867             :     break;
    3868             :   default:
    3869             :     break;
    3870             :   }
    3871             : 
    3872         106 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3873             :     return MCDisassembler::Fail;
    3874         159 :   Inst.addOperand(MCOperand::createImm(imm));
    3875             : 
    3876             :   return S;
    3877             : }
    3878             : 
    3879         465 : static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
    3880             :                                 uint64_t Address, const void *Decoder) {
    3881             :   unsigned imm = fieldFromInstruction(Insn, 0, 7);
    3882             : 
    3883         930 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3884         930 :   Inst.addOperand(MCOperand::createReg(ARM::SP));
    3885        1395 :   Inst.addOperand(MCOperand::createImm(imm));
    3886             : 
    3887         465 :   return MCDisassembler::Success;
    3888             : }
    3889             : 
    3890          20 : static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
    3891             :                                 uint64_t Address, const void *Decoder) {
    3892             :   DecodeStatus S = MCDisassembler::Success;
    3893             : 
    3894          20 :   if (Inst.getOpcode() == ARM::tADDrSP) {
    3895           5 :     unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
    3896           5 :     Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
    3897             : 
    3898          10 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
    3899             :     return MCDisassembler::Fail;
    3900          10 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3901          10 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
    3902             :     return MCDisassembler::Fail;
    3903          15 :   } else if (Inst.getOpcode() == ARM::tADDspr) {
    3904          15 :     unsigned Rm = fieldFromInstruction(Insn, 3, 4);
    3905             : 
    3906          30 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3907          30 :     Inst.addOperand(MCOperand::createReg(ARM::SP));
    3908          30 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3909             :     return MCDisassembler::Fail;
    3910             :   }
    3911             : 
    3912             :   return S;
    3913             : }
    3914             : 
    3915           1 : static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
    3916             :                            uint64_t Address, const void *Decoder) {
    3917           1 :   unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
    3918             :   unsigned flags = fieldFromInstruction(Insn, 0, 3);
    3919             : 
    3920           3 :   Inst.addOperand(MCOperand::createImm(imod));
    3921           3 :   Inst.addOperand(MCOperand::createImm(flags));
    3922             : 
    3923           1 :   return MCDisassembler::Success;
    3924             : }
    3925             : 
    3926          15 : static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
    3927             :                              uint64_t Address, const void *Decoder) {
    3928             :   DecodeStatus S = MCDisassembler::Success;
    3929             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3930             :   unsigned add = fieldFromInstruction(Insn, 4, 1);
    3931             : 
    3932          30 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
    3933             :     return MCDisassembler::Fail;
    3934          45 :   Inst.addOperand(MCOperand::createImm(add));
    3935             : 
    3936             :   return S;
    3937             : }
    3938             : 
    3939          28 : static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
    3940             :                                  uint64_t Address, const void *Decoder) {
    3941             :   // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
    3942             :   // Note only one trailing zero not two.  Also the J1 and J2 values are from
    3943             :   // the encoded instruction.  So here change to I1 and I2 values via:
    3944             :   // I1 = NOT(J1 EOR S);
    3945             :   // I2 = NOT(J2 EOR S);
    3946             :   // and build the imm32 with two trailing zeros as documented:
    3947             :   // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
    3948          28 :   unsigned S = (Val >> 23) & 1;
    3949          28 :   unsigned J1 = (Val >> 22) & 1;
    3950          28 :   unsigned J2 = (Val >> 21) & 1;
    3951          28 :   unsigned I1 = !(J1 ^ S);
    3952          28 :   unsigned I2 = !(J2 ^ S);
    3953          28 :   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
    3954             :   int imm32 = SignExtend32<25>(tmp << 1);
    3955             : 
    3956          28 :   if (!tryAddingSymbolicOperand(Address,
    3957          28 :                                 (Address & ~2u) + imm32 + 4,
    3958             :                                 true, 4, Inst, Decoder))
    3959          66 :     Inst.addOperand(MCOperand::createImm(imm32));
    3960          28 :   return MCDisassembler::Success;
    3961             : }
    3962             : 
    3963         164 : static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
    3964             :                               uint64_t Address, const void *Decoder) {
    3965         164 :   if (Val == 0xA || Val == 0xB)
    3966             :     return MCDisassembler::Fail;
    3967             : 
    3968             :   const FeatureBitset &featureBits =
    3969         118 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    3970             : 
    3971         118 :   if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
    3972             :     return MCDisassembler::Fail;
    3973             : 
    3974         306 :   Inst.addOperand(MCOperand::createImm(Val));
    3975             :   return MCDisassembler::Success;
    3976             : }
    3977             : 
    3978             : static DecodeStatus
    3979           6 : DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
    3980             :                        uint64_t Address, const void *Decoder) {
    3981             :   DecodeStatus S = MCDisassembler::Success;
    3982             : 
    3983             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    3984             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    3985             : 
    3986           6 :   if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
    3987          12 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    3988             :     return MCDisassembler::Fail;
    3989          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
    3990             :     return MCDisassembler::Fail;
    3991             :   return S;
    3992             : }
    3993             : 
    3994             : static DecodeStatus
    3995          32 : DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
    3996             :                            uint64_t Address, const void *Decoder) {
    3997             :   DecodeStatus S = MCDisassembler::Success;
    3998             : 
    3999             :   unsigned pred = fieldFromInstruction(Insn, 22, 4);
    4000          32 :   if (pred == 0xE || pred == 0xF) {
    4001             :     unsigned opc = fieldFromInstruction(Insn, 4, 28);
    4002           8 :     switch (opc) {
    4003             :       default:
    4004             :         return MCDisassembler::Fail;
    4005             :       case 0xf3bf8f4:
    4006             :         Inst.setOpcode(ARM::t2DSB);
    4007             :         break;
    4008             :       case 0xf3bf8f5:
    4009             :         Inst.setOpcode(ARM::t2DMB);
    4010             :         break;
    4011             :       case 0xf3bf8f6:
    4012             :         Inst.setOpcode(ARM::t2ISB);
    4013             :         break;
    4014             :     }
    4015             : 
    4016             :     unsigned imm = fieldFromInstruction(Insn, 0, 4);
    4017           0 :     return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
    4018             :   }
    4019             : 
    4020          24 :   unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
    4021          24 :   brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
    4022          24 :   brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
    4023          24 :   brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
    4024          24 :   brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
    4025             : 
    4026          48 :   if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
    4027             :     return MCDisassembler::Fail;
    4028          48 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4029             :     return MCDisassembler::Fail;
    4030             : 
    4031          24 :   return S;
    4032             : }
    4033             : 
    4034             : // Decode a shifted immediate operand.  These basically consist
    4035             : // of an 8-bit value, and a 4-bit directive that specifies either
    4036             : // a splat operation or a rotation.
    4037         251 : static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
    4038             :                           uint64_t Address, const void *Decoder) {
    4039             :   unsigned ctrl = fieldFromInstruction(Val, 10, 2);
    4040         251 :   if (ctrl == 0) {
    4041             :     unsigned byte = fieldFromInstruction(Val, 8, 2);
    4042             :     unsigned imm = fieldFromInstruction(Val, 0, 8);
    4043         163 :     switch (byte) {
    4044         152 :       case 0:
    4045         456 :         Inst.addOperand(MCOperand::createImm(imm));
    4046             :         break;
    4047           3 :       case 1:
    4048           9 :         Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
    4049             :         break;
    4050           3 :       case 2:
    4051           9 :         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
    4052             :         break;
    4053           5 :       case 3:
    4054          20 :         Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
    4055          10 :                                              (imm << 8)  |  imm));
    4056             :         break;
    4057             :     }
    4058             :   } else {
    4059          88 :     unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
    4060             :     unsigned rot = fieldFromInstruction(Val, 7, 5);
    4061          88 :     unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
    4062         264 :     Inst.addOperand(MCOperand::createImm(imm));
    4063             :   }
    4064             : 
    4065         251 :   return MCDisassembler::Success;
    4066             : }
    4067             : 
    4068             : static DecodeStatus
    4069         122 : DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
    4070             :                             uint64_t Address, const void *Decoder) {
    4071         244 :   if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
    4072             :                                 true, 2, Inst, Decoder))
    4073         366 :     Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
    4074         122 :   return MCDisassembler::Success;
    4075             : }
    4076             : 
    4077         280 : static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
    4078             :                                                uint64_t Address,
    4079             :                                                const void *Decoder) {
    4080             :   // Val is passed in as S:J1:J2:imm10:imm11
    4081             :   // Note no trailing zero after imm11.  Also the J1 and J2 values are from
    4082             :   // the encoded instruction.  So here change to I1 and I2 values via:
    4083             :   // I1 = NOT(J1 EOR S);
    4084             :   // I2 = NOT(J2 EOR S);
    4085             :   // and build the imm32 with one trailing zero as documented:
    4086             :   // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
    4087         280 :   unsigned S = (Val >> 23) & 1;
    4088         280 :   unsigned J1 = (Val >> 22) & 1;
    4089         280 :   unsigned J2 = (Val >> 21) & 1;
    4090         280 :   unsigned I1 = !(J1 ^ S);
    4091         280 :   unsigned I2 = !(J2 ^ S);
    4092         280 :   unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
    4093             :   int imm32 = SignExtend32<25>(tmp << 1);
    4094             : 
    4095         560 :   if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
    4096             :                                 true, 4, Inst, Decoder))
    4097         831 :     Inst.addOperand(MCOperand::createImm(imm32));
    4098         280 :   return MCDisassembler::Success;
    4099             : }
    4100             : 
    4101             : static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
    4102             :                                    uint64_t Address, const void *Decoder) {
    4103             :   if (Val & ~0xf)
    4104             :     return MCDisassembler::Fail;
    4105             : 
    4106         246 :   Inst.addOperand(MCOperand::createImm(Val));
    4107             :   return MCDisassembler::Success;
    4108             : }
    4109             : 
    4110             : static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
    4111             :                                         uint64_t Address, const void *Decoder) {
    4112             :   if (Val & ~0xf)
    4113             :     return MCDisassembler::Fail;
    4114             : 
    4115          18 :   Inst.addOperand(MCOperand::createImm(Val));
    4116             :   return MCDisassembler::Success;
    4117             : }
    4118             : 
    4119         114 : static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
    4120             :                           uint64_t Address, const void *Decoder) {
    4121             :   DecodeStatus S = MCDisassembler::Success;
    4122             :   const FeatureBitset &FeatureBits =
    4123         114 :     ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
    4124             : 
    4125         114 :   if (FeatureBits[ARM::FeatureMClass]) {
    4126          63 :     unsigned ValLow = Val & 0xff;
    4127             : 
    4128             :     // Validate the SYSm value first.
    4129          63 :     switch (ValLow) {
    4130             :     case  0: // apsr
    4131             :     case  1: // iapsr
    4132             :     case  2: // eapsr
    4133             :     case  3: // xpsr
    4134             :     case  5: // ipsr
    4135             :     case  6: // epsr
    4136             :     case  7: // iepsr
    4137             :     case  8: // msp
    4138             :     case  9: // psp
    4139             :     case 16: // primask
    4140             :     case 20: // control
    4141             :       break;
    4142           6 :     case 17: // basepri
    4143             :     case 18: // basepri_max
    4144             :     case 19: // faultmask
    4145           6 :       if (!(FeatureBits[ARM::HasV7Ops]))
    4146             :         // Values basepri, basepri_max and faultmask are only valid for v7m.
    4147             :         return MCDisassembler::Fail;
    4148             :       break;
    4149           3 :     case 0x8a: // msplim_ns
    4150             :     case 0x8b: // psplim_ns
    4151             :     case 0x91: // basepri_ns
    4152             :     case 0x92: // basepri_max_ns
    4153             :     case 0x93: // faultmask_ns
    4154           3 :       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
    4155             :         return MCDisassembler::Fail;
    4156             :       LLVM_FALLTHROUGH;
    4157             :     case 10:   // msplim
    4158             :     case 11:   // psplim
    4159             :     case 0x88: // msp_ns
    4160             :     case 0x89: // psp_ns
    4161             :     case 0x90: // primask_ns
    4162             :     case 0x94: // control_ns
    4163             :     case 0x98: // sp_ns
    4164          14 :       if (!(FeatureBits[ARM::Feature8MSecExt]))
    4165             :         return MCDisassembler::Fail;
    4166             :       break;
    4167             :     default:
    4168             :       return MCDisassembler::Fail;
    4169             :     }
    4170             : 
    4171          58 :     if (Inst.getOpcode() == ARM::t2MSR_M) {
    4172             :       unsigned Mask = fieldFromInstruction(Val, 10, 2);
    4173          37 :       if (!(FeatureBits[ARM::HasV7Ops])) {
    4174             :         // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
    4175             :         // unpredictable.
    4176           3 :         if (Mask != 2)
    4177             :           S = MCDisassembler::SoftFail;
    4178             :       }
    4179             :       else {
    4180             :         // The ARMv7-M architecture stores an additional 2-bit mask value in
    4181             :         // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
    4182             :         // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
    4183             :         // the NZCVQ bits should be moved by the instruction. Bit mask{0}
    4184             :         // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
    4185             :         // only if the processor includes the DSP extension.
    4186          64 :         if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
    4187           6 :             (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
    4188             :           S = MCDisassembler::SoftFail;
    4189             :       }
    4190             :     }
    4191             :   } else {
    4192             :     // A/R class
    4193          51 :     if (Val == 0)
    4194             :       return MCDisassembler::Fail;
    4195             :   }
    4196         318 :   Inst.addOperand(MCOperand::createImm(Val));
    4197             :   return S;
    4198             : }
    4199             : 
    4200         138 : static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
    4201             :                                     uint64_t Address, const void *Decoder) {
    4202             :   unsigned R = fieldFromInstruction(Val, 5, 1);
    4203             :   unsigned SysM = fieldFromInstruction(Val, 0, 5);
    4204             : 
    4205             :   // The table of encodings for these banked registers comes from B9.2.3 of the
    4206             :   // ARM ARM. There are patterns, but nothing regular enough to make this logic
    4207             :   // neater. So by fiat, these values are UNPREDICTABLE:
    4208         138 :   if (!ARMBankedReg::lookupBankedRegByEncoding((R << 5) | SysM))
    4209             :     return MCDisassembler::Fail;
    4210             : 
    4211         396 :   Inst.addOperand(MCOperand::createImm(Val));
    4212             :   return MCDisassembler::Success;
    4213             : }
    4214             : 
    4215           7 : static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
    4216             :                                         uint64_t Address, const void *Decoder) {
    4217             :   DecodeStatus S = MCDisassembler::Success;
    4218             : 
    4219             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4220             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4221             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4222             : 
    4223           7 :   if (Rn == 0xF)
    4224             :     S = MCDisassembler::SoftFail;
    4225             : 
    4226          14 :   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
    4227             :     return MCDisassembler::Fail;
    4228          14 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4229             :     return MCDisassembler::Fail;
    4230          14 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4231             :     return MCDisassembler::Fail;
    4232             : 
    4233             :   return S;
    4234             : }
    4235             : 
    4236           8 : static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
    4237             :                                          uint64_t Address,
    4238             :                                          const void *Decoder) {
    4239             :   DecodeStatus S = MCDisassembler::Success;
    4240             : 
    4241             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4242             :   unsigned Rt = fieldFromInstruction(Insn, 0, 4);
    4243             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4244             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4245             : 
    4246          16 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
    4247             :     return MCDisassembler::Fail;
    4248             : 
    4249           8 :   if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
    4250             :     S = MCDisassembler::SoftFail;
    4251             : 
    4252          16 :   if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
    4253             :     return MCDisassembler::Fail;
    4254          16 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4255             :     return MCDisassembler::Fail;
    4256          16 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4257             :     return MCDisassembler::Fail;
    4258             : 
    4259             :   return S;
    4260             : }
    4261             : 
    4262          47 : static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
    4263             :                             uint64_t Address, const void *Decoder) {
    4264             :   DecodeStatus S = MCDisassembler::Success;
    4265             : 
    4266             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4267             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4268             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4269          47 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4270          47 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4271             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4272             : 
    4273          47 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4274             : 
    4275          94 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4276             :     return MCDisassembler::Fail;
    4277          94 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4278             :     return MCDisassembler::Fail;
    4279          94 :   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
    4280             :     return MCDisassembler::Fail;
    4281          94 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4282             :     return MCDisassembler::Fail;
    4283             : 
    4284          47 :   return S;
    4285             : }
    4286             : 
    4287           9 : static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
    4288             :                             uint64_t Address, const void *Decoder) {
    4289             :   DecodeStatus S = MCDisassembler::Success;
    4290             : 
    4291             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4292             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4293             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4294           9 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4295           9 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4296             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4297             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4298             : 
    4299           9 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4300           9 :   if (Rm == 0xF) S = MCDisassembler::SoftFail;
    4301             : 
    4302          18 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4303             :     return MCDisassembler::Fail;
    4304          18 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4305             :     return MCDisassembler::Fail;
    4306          18 :   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
    4307             :     return MCDisassembler::Fail;
    4308          18 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4309             :     return MCDisassembler::Fail;
    4310             : 
    4311             :   return S;
    4312             : }
    4313             : 
    4314          18 : static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
    4315             :                             uint64_t Address, const void *Decoder) {
    4316             :   DecodeStatus S = MCDisassembler::Success;
    4317             : 
    4318             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4319             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4320             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4321          18 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4322          18 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4323             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4324             : 
    4325          18 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4326             : 
    4327          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4328             :     return MCDisassembler::Fail;
    4329          36 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4330             :     return MCDisassembler::Fail;
    4331          36 :   if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
    4332             :     return MCDisassembler::Fail;
    4333          36 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4334             :     return MCDisassembler::Fail;
    4335             : 
    4336          18 :   return S;
    4337             : }
    4338             : 
    4339           5 : static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
    4340             :                             uint64_t Address, const void *Decoder) {
    4341             :   DecodeStatus S = MCDisassembler::Success;
    4342             : 
    4343             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4344             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4345             :   unsigned imm = fieldFromInstruction(Insn, 0, 12);
    4346           5 :   imm |= fieldFromInstruction(Insn, 16, 4) << 13;
    4347           5 :   imm |= fieldFromInstruction(Insn, 23, 1) << 12;
    4348             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4349             : 
    4350           5 :   if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
    4351             : 
    4352          10 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4353             :     return MCDisassembler::Fail;
    4354          10 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
    4355             :     return MCDisassembler::Fail;
    4356          10 :   if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
    4357             :     return MCDisassembler::Fail;
    4358          10 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4359             :     return MCDisassembler::Fail;
    4360             : 
    4361             :   return S;
    4362             : }
    4363             : 
    4364          36 : static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
    4365             :                          uint64_t Address, const void *Decoder) {
    4366             :   DecodeStatus S = MCDisassembler::Success;
    4367             : 
    4368             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4369             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4370             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4371          36 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4372             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4373             : 
    4374             :   unsigned align = 0;
    4375             :   unsigned index = 0;
    4376          36 :   switch (size) {
    4377             :     default:
    4378             :       return MCDisassembler::Fail;
    4379             :     case 0:
    4380          12 :       if (fieldFromInstruction(Insn, 4, 1))
    4381             :         return MCDisassembler::Fail; // UNDEFINED
    4382             :       index = fieldFromInstruction(Insn, 5, 3);
    4383          12 :       break;
    4384             :     case 1:
    4385          16 :       if (fieldFromInstruction(Insn, 5, 1))
    4386             :         return MCDisassembler::Fail; // UNDEFINED
    4387             :       index = fieldFromInstruction(Insn, 6, 2);
    4388          16 :       if (fieldFromInstruction(Insn, 4, 1))
    4389             :         align = 2;
    4390             :       break;
    4391             :     case 2:
    4392           8 :       if (fieldFromInstruction(Insn, 6, 1))
    4393             :         return MCDisassembler::Fail; // UNDEFINED
    4394             :       index = fieldFromInstruction(Insn, 7, 1);
    4395             : 
    4396           8 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4397             :         case 0 :
    4398             :           align = 0; break;
    4399           4 :         case 3:
    4400           4 :           align = 4; break;
    4401             :         default:
    4402             :           return MCDisassembler::Fail;
    4403             :       }
    4404             :       break;
    4405             :   }
    4406             : 
    4407          68 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4408             :     return MCDisassembler::Fail;
    4409          34 :   if (Rm != 0xF) { // Writeback
    4410          52 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4411             :       return MCDisassembler::Fail;
    4412             :   }
    4413          68 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4414             :     return MCDisassembler::Fail;
    4415         102 :   Inst.addOperand(MCOperand::createImm(align));
    4416          34 :   if (Rm != 0xF) {
    4417          26 :     if (Rm != 0xD) {
    4418          48 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4419             :         return MCDisassembler::Fail;
    4420             :     } else
    4421           4 :       Inst.addOperand(MCOperand::createReg(0));
    4422             :   }
    4423             : 
    4424          68 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4425             :     return MCDisassembler::Fail;
    4426         102 :   Inst.addOperand(MCOperand::createImm(index));
    4427             : 
    4428          34 :   return S;
    4429             : }
    4430             : 
    4431          30 : static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
    4432             :                          uint64_t Address, const void *Decoder) {
    4433             :   DecodeStatus S = MCDisassembler::Success;
    4434             : 
    4435             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4436             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4437             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4438          30 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4439             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4440             : 
    4441             :   unsigned align = 0;
    4442             :   unsigned index = 0;
    4443          30 :   switch (size) {
    4444             :     default:
    4445             :       return MCDisassembler::Fail;
    4446             :     case 0:
    4447          10 :       if (fieldFromInstruction(Insn, 4, 1))
    4448             :         return MCDisassembler::Fail; // UNDEFINED
    4449             :       index = fieldFromInstruction(Insn, 5, 3);
    4450          10 :       break;
    4451             :     case 1:
    4452          14 :       if (fieldFromInstruction(Insn, 5, 1))
    4453             :         return MCDisassembler::Fail; // UNDEFINED
    4454             :       index = fieldFromInstruction(Insn, 6, 2);
    4455          14 :       if (fieldFromInstruction(Insn, 4, 1))
    4456             :         align = 2;
    4457             :       break;
    4458             :     case 2:
    4459           6 :       if (fieldFromInstruction(Insn, 6, 1))
    4460             :         return MCDisassembler::Fail; // UNDEFINED
    4461             :       index = fieldFromInstruction(Insn, 7, 1);
    4462             : 
    4463           6 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4464             :         case 0: 
    4465             :           align = 0; break;
    4466           2 :         case 3:
    4467           2 :           align = 4; break;
    4468             :         default:
    4469             :           return MCDisassembler::Fail;
    4470             :       }
    4471             :       break;
    4472             :   }
    4473             : 
    4474          28 :   if (Rm != 0xF) { // Writeback
    4475          52 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4476             :     return MCDisassembler::Fail;
    4477             :   }
    4478          56 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4479             :     return MCDisassembler::Fail;
    4480          84 :   Inst.addOperand(MCOperand::createImm(align));
    4481          28 :   if (Rm != 0xF) {
    4482          26 :     if (Rm != 0xD) {
    4483          48 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4484             :     return MCDisassembler::Fail;
    4485             :     } else
    4486           4 :       Inst.addOperand(MCOperand::createReg(0));
    4487             :   }
    4488             : 
    4489          56 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4490             :     return MCDisassembler::Fail;
    4491          84 :   Inst.addOperand(MCOperand::createImm(index));
    4492             : 
    4493          28 :   return S;
    4494             : }
    4495             : 
    4496          10 : static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
    4497             :                          uint64_t Address, const void *Decoder) {
    4498             :   DecodeStatus S = MCDisassembler::Success;
    4499             : 
    4500             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4501             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4502             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4503          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4504             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4505             : 
    4506             :   unsigned align = 0;
    4507             :   unsigned index = 0;
    4508             :   unsigned inc = 1;
    4509          10 :   switch (size) {
    4510             :     default:
    4511             :       return MCDisassembler::Fail;
    4512             :     case 0:
    4513             :       index = fieldFromInstruction(Insn, 5, 3);
    4514           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4515             :         align = 2;
    4516             :       break;
    4517             :     case 1:
    4518             :       index = fieldFromInstruction(Insn, 6, 2);
    4519           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4520             :         align = 4;
    4521           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4522             :         inc = 2;
    4523             :       break;
    4524             :     case 2:
    4525           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4526             :         return MCDisassembler::Fail; // UNDEFINED
    4527             :       index = fieldFromInstruction(Insn, 7, 1);
    4528           4 :       if (fieldFromInstruction(Insn, 4, 1) != 0)
    4529             :         align = 8;
    4530           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4531             :         inc = 2;
    4532             :       break;
    4533             :   }
    4534             : 
    4535          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4536             :     return MCDisassembler::Fail;
    4537          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4538             :     return MCDisassembler::Fail;
    4539          10 :   if (Rm != 0xF) { // Writeback
    4540           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4541             :       return MCDisassembler::Fail;
    4542             :   }
    4543          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4544             :     return MCDisassembler::Fail;
    4545          30 :   Inst.addOperand(MCOperand::createImm(align));
    4546          10 :   if (Rm != 0xF) {
    4547           0 :     if (Rm != 0xD) {
    4548           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4549             :         return MCDisassembler::Fail;
    4550             :     } else
    4551           0 :       Inst.addOperand(MCOperand::createReg(0));
    4552             :   }
    4553             : 
    4554          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4555             :     return MCDisassembler::Fail;
    4556          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4557             :     return MCDisassembler::Fail;
    4558          30 :   Inst.addOperand(MCOperand::createImm(index));
    4559             : 
    4560          10 :   return S;
    4561             : }
    4562             : 
    4563          10 : static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
    4564             :                          uint64_t Address, const void *Decoder) {
    4565             :   DecodeStatus S = MCDisassembler::Success;
    4566             : 
    4567             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4568             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4569             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4570          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4571             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4572             : 
    4573             :   unsigned align = 0;
    4574             :   unsigned index = 0;
    4575             :   unsigned inc = 1;
    4576          10 :   switch (size) {
    4577             :     default:
    4578             :       return MCDisassembler::Fail;
    4579             :     case 0:
    4580             :       index = fieldFromInstruction(Insn, 5, 3);
    4581           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4582             :         align = 2;
    4583             :       break;
    4584             :     case 1:
    4585             :       index = fieldFromInstruction(Insn, 6, 2);
    4586           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4587             :         align = 4;
    4588           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4589             :         inc = 2;
    4590             :       break;
    4591             :     case 2:
    4592           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4593             :         return MCDisassembler::Fail; // UNDEFINED
    4594             :       index = fieldFromInstruction(Insn, 7, 1);
    4595           4 :       if (fieldFromInstruction(Insn, 4, 1) != 0)
    4596             :         align = 8;
    4597           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4598             :         inc = 2;
    4599             :       break;
    4600             :   }
    4601             : 
    4602          10 :   if (Rm != 0xF) { // Writeback
    4603           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4604             :       return MCDisassembler::Fail;
    4605             :   }
    4606          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4607             :     return MCDisassembler::Fail;
    4608          30 :   Inst.addOperand(MCOperand::createImm(align));
    4609          10 :   if (Rm != 0xF) {
    4610           0 :     if (Rm != 0xD) {
    4611           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4612             :         return MCDisassembler::Fail;
    4613             :     } else
    4614           0 :       Inst.addOperand(MCOperand::createReg(0));
    4615             :   }
    4616             : 
    4617          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4618             :     return MCDisassembler::Fail;
    4619          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4620             :     return MCDisassembler::Fail;
    4621          30 :   Inst.addOperand(MCOperand::createImm(index));
    4622             : 
    4623          10 :   return S;
    4624             : }
    4625             : 
    4626          10 : static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
    4627             :                          uint64_t Address, const void *Decoder) {
    4628             :   DecodeStatus S = MCDisassembler::Success;
    4629             : 
    4630             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4631             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4632             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4633          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4634             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4635             : 
    4636             :   unsigned align = 0;
    4637             :   unsigned index = 0;
    4638             :   unsigned inc = 1;
    4639          10 :   switch (size) {
    4640             :     default:
    4641             :       return MCDisassembler::Fail;
    4642             :     case 0:
    4643           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4644             :         return MCDisassembler::Fail; // UNDEFINED
    4645             :       index = fieldFromInstruction(Insn, 5, 3);
    4646           2 :       break;
    4647             :     case 1:
    4648           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4649             :         return MCDisassembler::Fail; // UNDEFINED
    4650             :       index = fieldFromInstruction(Insn, 6, 2);
    4651           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4652             :         inc = 2;
    4653             :       break;
    4654             :     case 2:
    4655           4 :       if (fieldFromInstruction(Insn, 4, 2))
    4656             :         return MCDisassembler::Fail; // UNDEFINED
    4657             :       index = fieldFromInstruction(Insn, 7, 1);
    4658           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4659             :         inc = 2;
    4660             :       break;
    4661             :   }
    4662             : 
    4663          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4664             :     return MCDisassembler::Fail;
    4665          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4666             :     return MCDisassembler::Fail;
    4667          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4668             :     return MCDisassembler::Fail;
    4669             : 
    4670          10 :   if (Rm != 0xF) { // Writeback
    4671           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4672             :     return MCDisassembler::Fail;
    4673             :   }
    4674          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4675             :     return MCDisassembler::Fail;
    4676          20 :   Inst.addOperand(MCOperand::createImm(align));
    4677          10 :   if (Rm != 0xF) {
    4678           0 :     if (Rm != 0xD) {
    4679           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4680             :     return MCDisassembler::Fail;
    4681             :     } else
    4682           0 :       Inst.addOperand(MCOperand::createReg(0));
    4683             :   }
    4684             : 
    4685          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4686             :     return MCDisassembler::Fail;
    4687          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4688             :     return MCDisassembler::Fail;
    4689          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4690             :     return MCDisassembler::Fail;
    4691          30 :   Inst.addOperand(MCOperand::createImm(index));
    4692             : 
    4693          10 :   return S;
    4694             : }
    4695             : 
    4696          10 : static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
    4697             :                          uint64_t Address, const void *Decoder) {
    4698             :   DecodeStatus S = MCDisassembler::Success;
    4699             : 
    4700             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4701             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4702             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4703          10 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4704             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4705             : 
    4706             :   unsigned align = 0;
    4707             :   unsigned index = 0;
    4708             :   unsigned inc = 1;
    4709          10 :   switch (size) {
    4710             :     default:
    4711             :       return MCDisassembler::Fail;
    4712             :     case 0:
    4713           2 :       if (fieldFromInstruction(Insn, 4, 1))
    4714             :         return MCDisassembler::Fail; // UNDEFINED
    4715             :       index = fieldFromInstruction(Insn, 5, 3);
    4716           2 :       break;
    4717             :     case 1:
    4718           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4719             :         return MCDisassembler::Fail; // UNDEFINED
    4720             :       index = fieldFromInstruction(Insn, 6, 2);
    4721           4 :       if (fieldFromInstruction(Insn, 5, 1))
    4722             :         inc = 2;
    4723             :       break;
    4724             :     case 2:
    4725           4 :       if (fieldFromInstruction(Insn, 4, 2))
    4726             :         return MCDisassembler::Fail; // UNDEFINED
    4727             :       index = fieldFromInstruction(Insn, 7, 1);
    4728           4 :       if (fieldFromInstruction(Insn, 6, 1))
    4729             :         inc = 2;
    4730             :       break;
    4731             :   }
    4732             : 
    4733          10 :   if (Rm != 0xF) { // Writeback
    4734           0 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4735             :     return MCDisassembler::Fail;
    4736             :   }
    4737          20 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4738             :     return MCDisassembler::Fail;
    4739          20 :   Inst.addOperand(MCOperand::createImm(align));
    4740          10 :   if (Rm != 0xF) {
    4741           0 :     if (Rm != 0xD) {
    4742           0 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4743             :     return MCDisassembler::Fail;
    4744             :     } else
    4745           0 :       Inst.addOperand(MCOperand::createReg(0));
    4746             :   }
    4747             : 
    4748          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4749             :     return MCDisassembler::Fail;
    4750          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4751             :     return MCDisassembler::Fail;
    4752          20 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4753             :     return MCDisassembler::Fail;
    4754          30 :   Inst.addOperand(MCOperand::createImm(index));
    4755             : 
    4756          10 :   return S;
    4757             : }
    4758             : 
    4759          15 : static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
    4760             :                          uint64_t Address, const void *Decoder) {
    4761             :   DecodeStatus S = MCDisassembler::Success;
    4762             : 
    4763             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4764             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4765             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4766          15 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4767             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4768             : 
    4769             :   unsigned align = 0;
    4770             :   unsigned index = 0;
    4771             :   unsigned inc = 1;
    4772          15 :   switch (size) {
    4773             :     default:
    4774             :       return MCDisassembler::Fail;
    4775             :     case 0:
    4776           3 :       if (fieldFromInstruction(Insn, 4, 1))
    4777             :         align = 4;
    4778             :       index = fieldFromInstruction(Insn, 5, 3);
    4779           3 :       break;
    4780             :     case 1:
    4781           5 :       if (fieldFromInstruction(Insn, 4, 1))
    4782             :         align = 8;
    4783             :       index = fieldFromInstruction(Insn, 6, 2);
    4784           5 :       if (fieldFromInstruction(Insn, 5, 1))
    4785             :         inc = 2;
    4786             :       break;
    4787             :     case 2:
    4788           7 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4789             :         case 0:
    4790             :           align = 0; break;
    4791             :         case 3:
    4792             :           return MCDisassembler::Fail;
    4793             :         default:
    4794           3 :           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
    4795             :       }
    4796             : 
    4797             :       index = fieldFromInstruction(Insn, 7, 1);
    4798           5 :       if (fieldFromInstruction(Insn, 6, 1))
    4799             :         inc = 2;
    4800             :       break;
    4801             :   }
    4802             : 
    4803          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4804             :     return MCDisassembler::Fail;
    4805          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4806             :     return MCDisassembler::Fail;
    4807          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4808             :     return MCDisassembler::Fail;
    4809          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4810             :     return MCDisassembler::Fail;
    4811             : 
    4812          13 :   if (Rm != 0xF) { // Writeback
    4813           6 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4814             :       return MCDisassembler::Fail;
    4815             :   }
    4816          26 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4817             :     return MCDisassembler::Fail;
    4818          39 :   Inst.addOperand(MCOperand::createImm(align));
    4819          13 :   if (Rm != 0xF) {
    4820           3 :     if (Rm != 0xD) {
    4821           6 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4822             :         return MCDisassembler::Fail;
    4823             :     } else
    4824           0 :       Inst.addOperand(MCOperand::createReg(0));
    4825             :   }
    4826             : 
    4827          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4828             :     return MCDisassembler::Fail;
    4829          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4830             :     return MCDisassembler::Fail;
    4831          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4832             :     return MCDisassembler::Fail;
    4833          26 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4834             :     return MCDisassembler::Fail;
    4835          39 :   Inst.addOperand(MCOperand::createImm(index));
    4836             : 
    4837          13 :   return S;
    4838             : }
    4839             : 
    4840          16 : static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
    4841             :                          uint64_t Address, const void *Decoder) {
    4842             :   DecodeStatus S = MCDisassembler::Success;
    4843             : 
    4844             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4845             :   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
    4846             :   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
    4847          16 :   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
    4848             :   unsigned size = fieldFromInstruction(Insn, 10, 2);
    4849             : 
    4850             :   unsigned align = 0;
    4851             :   unsigned index = 0;
    4852             :   unsigned inc = 1;
    4853          16 :   switch (size) {
    4854             :     default:
    4855             :       return MCDisassembler::Fail;
    4856             :     case 0:
    4857           4 :       if (fieldFromInstruction(Insn, 4, 1))
    4858             :         align = 4;
    4859             :       index = fieldFromInstruction(Insn, 5, 3);
    4860           4 :       break;
    4861             :     case 1:
    4862           5 :       if (fieldFromInstruction(Insn, 4, 1))
    4863             :         align = 8;
    4864             :       index = fieldFromInstruction(Insn, 6, 2);
    4865           5 :       if (fieldFromInstruction(Insn, 5, 1))
    4866             :         inc = 2;
    4867             :       break;
    4868             :     case 2:
    4869           7 :       switch (fieldFromInstruction(Insn, 4, 2)) {
    4870             :         case 0:
    4871             :           align = 0; break;
    4872             :         case 3:
    4873             :           return MCDisassembler::Fail;
    4874             :         default:
    4875           3 :           align = 4 << fieldFromInstruction(Insn, 4, 2); break;
    4876             :       }
    4877             : 
    4878             :       index = fieldFromInstruction(Insn, 7, 1);
    4879           5 :       if (fieldFromInstruction(Insn, 6, 1))
    4880             :         inc = 2;
    4881             :       break;
    4882             :   }
    4883             : 
    4884          14 :   if (Rm != 0xF) { // Writeback
    4885           8 :     if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4886             :     return MCDisassembler::Fail;
    4887             :   }
    4888          28 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
    4889             :     return MCDisassembler::Fail;
    4890          42 :   Inst.addOperand(MCOperand::createImm(align));
    4891          14 :   if (Rm != 0xF) {
    4892           4 :     if (Rm != 0xD) {
    4893           6 :       if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
    4894             :     return MCDisassembler::Fail;
    4895             :     } else
    4896           2 :       Inst.addOperand(MCOperand::createReg(0));
    4897             :   }
    4898             : 
    4899          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
    4900             :     return MCDisassembler::Fail;
    4901          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
    4902             :     return MCDisassembler::Fail;
    4903          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
    4904             :     return MCDisassembler::Fail;
    4905          28 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
    4906             :     return MCDisassembler::Fail;
    4907          42 :   Inst.addOperand(MCOperand::createImm(index));
    4908             : 
    4909          14 :   return S;
    4910             : }
    4911             : 
    4912           2 : static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
    4913             :                                   uint64_t Address, const void *Decoder) {
    4914             :   DecodeStatus S = MCDisassembler::Success;
    4915             :   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
    4916             :   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
    4917             :   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
    4918             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4919           2 :   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
    4920             : 
    4921           2 :   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
    4922             :     S = MCDisassembler::SoftFail;
    4923             : 
    4924           4 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
    4925             :     return MCDisassembler::Fail;
    4926           4 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
    4927             :     return MCDisassembler::Fail;
    4928           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
    4929             :     return MCDisassembler::Fail;
    4930           4 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
    4931             :     return MCDisassembler::Fail;
    4932           4 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4933             :     return MCDisassembler::Fail;
    4934             : 
    4935             :   return S;
    4936             : }
    4937             : 
    4938           3 : static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
    4939             :                                   uint64_t Address, const void *Decoder) {
    4940             :   DecodeStatus S = MCDisassembler::Success;
    4941             :   unsigned Rt  = fieldFromInstruction(Insn, 12, 4);
    4942             :   unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
    4943             :   unsigned Rm  = fieldFromInstruction(Insn,  5, 1);
    4944             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    4945           3 :   Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
    4946             : 
    4947           3 :   if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
    4948             :     S = MCDisassembler::SoftFail;
    4949             : 
    4950           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt  , Address, Decoder)))
    4951             :     return MCDisassembler::Fail;
    4952           6 :   if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
    4953             :     return MCDisassembler::Fail;
    4954           6 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm  , Address, Decoder)))
    4955             :     return MCDisassembler::Fail;
    4956           6 :   if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
    4957             :     return MCDisassembler::Fail;
    4958           6 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    4959             :     return MCDisassembler::Fail;
    4960             : 
    4961             :   return S;
    4962             : }
    4963             : 
    4964         131 : static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
    4965             :                              uint64_t Address, const void *Decoder) {
    4966             :   DecodeStatus S = MCDisassembler::Success;
    4967             :   unsigned pred = fieldFromInstruction(Insn, 4, 4);
    4968             :   unsigned mask = fieldFromInstruction(Insn, 0, 4);
    4969             : 
    4970         131 :   if (pred == 0xF) {
    4971             :     pred = 0xE;
    4972             :     S = MCDisassembler::SoftFail;
    4973             :   }
    4974             : 
    4975         131 :   if (mask == 0x0)
    4976             :     return MCDisassembler::Fail;
    4977             : 
    4978         393 :   Inst.addOperand(MCOperand::createImm(pred));
    4979         393 :   Inst.addOperand(MCOperand::createImm(mask));
    4980             :   return S;
    4981             : }
    4982             : 
    4983             : static DecodeStatus
    4984           6 : DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
    4985             :                            uint64_t Address, const void *Decoder) {
    4986             :   DecodeStatus S = MCDisassembler::Success;
    4987             : 
    4988             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    4989             :   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
    4990             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    4991             :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    4992             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    4993             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    4994             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    4995           6 :   bool writeback = (W == 1) | (P == 0);
    4996             : 
    4997           6 :   addr |= (U << 8) | (Rn << 9);
    4998             : 
    4999           6 :   if (writeback && (Rn == Rt || Rn == Rt2))
    5000             :     Check(S, MCDisassembler::SoftFail);
    5001           6 :   if (Rt == Rt2)
    5002             :     Check(S, MCDisassembler::SoftFail);
    5003             : 
    5004             :   // Rt
    5005          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    5006             :     return MCDisassembler::Fail;
    5007             :   // Rt2
    5008          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
    5009             :     return MCDisassembler::Fail;
    5010             :   // Writeback operand
    5011          12 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
    5012             :     return MCDisassembler::Fail;
    5013             :   // addr
    5014          12 :   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
    5015             :     return MCDisassembler::Fail;
    5016             : 
    5017             :   return S;
    5018             : }
    5019             : 
    5020             : static DecodeStatus
    5021           4 : DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
    5022             :                            uint64_t Address, const void *Decoder) {
    5023             :   DecodeStatus S = MCDisassembler::Success;
    5024             : 
    5025             :   unsigned Rt = fieldFromInstruction(Insn, 12, 4);
    5026             :   unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
    5027             :   unsigned Rn = fieldFromInstruction(Insn, 16, 4);
    5028             :   unsigned addr = fieldFromInstruction(Insn, 0, 8);
    5029             :   unsigned W = fieldFromInstruction(Insn, 21, 1);
    5030             :   unsigned U = fieldFromInstruction(Insn, 23, 1);
    5031             :   unsigned P = fieldFromInstruction(Insn, 24, 1);
    5032           4 :   bool writeback = (W == 1) | (P == 0);
    5033             : 
    5034           4 :   addr |= (U << 8) | (Rn << 9);
    5035             : 
    5036           4 :   if (writeback && (Rn == Rt || Rn == Rt2))
    5037             :     Check(S, MCDisassembler::SoftFail);
    5038             : 
    5039             :   // Writeback operand
    5040           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
    5041             :     return MCDisassembler::Fail;
    5042             :   // Rt
    5043           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
    5044             :     return MCDisassembler::Fail;
    5045             :   // Rt2
    5046           8 :   if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
    5047             :     return MCDisassembler::Fail;
    5048             :   // addr
    5049           8 :   if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
    5050             :     return MCDisassembler::Fail;
    5051             : 
    5052             :   return S;
    5053             : }
    5054             : 
    5055           0 : static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
    5056             :                                 uint64_t Address, const void *Decoder) {
    5057             :   unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
    5058             :   unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
    5059           0 :   if (sign1 != sign2) return MCDisassembler::Fail;
    5060             : 
    5061             :   unsigned Val = fieldFromInstruction(Insn, 0, 8);
    5062           0 :   Val |= fieldFromInstruction(Insn, 12, 3) << 8;
    5063           0 :   Val |= fieldFromInstruction(Insn, 26, 1) << 11;
    5064           0 :   Val |= sign1 << 12;
    5065           0 :   Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
    5066             : 
    5067             :   return MCDisassembler::Success;
    5068             : }
    5069             : 
    5070             : static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
    5071             :                                               uint64_t Address,
    5072             :                                               const void *Decoder) {
    5073             :   DecodeStatus S = MCDisassembler::Success;
    5074             : 
    5075             :   // Shift of "asr #32" is not allowed in Thumb2 mode.
    5076           6 :   if (Val == 0x20) S = MCDisassembler::Fail;
    5077          18 :   Inst.addOperand(MCOperand::createImm(Val));
    5078             :   return S;
    5079             : }
    5080             : 
    5081          11 : static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
    5082             :                                uint64_t Address, const void *Decoder) {
    5083             :   unsigned Rt   = fieldFromInstruction(Insn, 12, 4);
    5084             :   unsigned Rt2  = fieldFromInstruction(Insn, 0,  4);
    5085             :   unsigned Rn   = fieldFromInstruction(Insn, 16, 4);
    5086             :   unsigned pred = fieldFromInstruction(Insn, 28, 4);
    5087             : 
    5088          11 :   if (pred == 0xF)
    5089           1 :     return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
    5090             : 
    5091             :   DecodeStatus S = MCDisassembler::Success;
    5092             : 
    5093          10 :   if (Rt == Rn || Rn == Rt2)
    5094             :     S = MCDisassembler::SoftFail;
    5095             : 
    5096          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5097             :     return MCDisassembler::Fail;
    5098          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5099             :     return MCDisassembler::Fail;
    5100          20 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    5101             :     return MCDisassembler::Fail;
    5102          20 :   if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    5103             :     return MCDisassembler::Fail;
    5104             : 
    5105             :   return S;
    5106             : }
    5107             : 
    5108          30 : static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
    5109             :                                 uint64_t Address, const void *Decoder) {
    5110             :   const FeatureBitset &featureBits =
    5111          30 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5112             :   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
    5113             : 
    5114             :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5115          30 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5116             :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5117          30 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5118             :   unsigned imm = fieldFromInstruction(Insn, 16, 6);
    5119             :   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
    5120             :   unsigned op = fieldFromInstruction(Insn, 5, 1);
    5121             : 
    5122             :   DecodeStatus S = MCDisassembler::Success;
    5123             : 
    5124             :   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
    5125          30 :   if (!(imm & 0x38)) {
    5126           8 :     if (cmode == 0xF) {
    5127           4 :       if (op == 1) return MCDisassembler::Fail;
    5128             :       Inst.setOpcode(ARM::VMOVv2f32);
    5129             :     }
    5130           7 :     if (hasFullFP16) {
    5131           6 :       if (cmode == 0xE) {
    5132           0 :         if (op == 1) {
    5133             :           Inst.setOpcode(ARM::VMOVv1i64);
    5134             :         } else {
    5135             :           Inst.setOpcode(ARM::VMOVv8i8);
    5136             :         }
    5137             :       }
    5138           6 :       if (cmode == 0xD) {
    5139           2 :         if (op == 1) {
    5140             :           Inst.setOpcode(ARM::VMVNv2i32);
    5141             :         } else {
    5142             :           Inst.setOpcode(ARM::VMOVv2i32);
    5143             :         }
    5144             :       }
    5145           6 :       if (cmode == 0xC) {
    5146           2 :         if (op == 1) {
    5147             :           Inst.setOpcode(ARM::VMVNv2i32);
    5148             :         } else {
    5149             :           Inst.setOpcode(ARM::VMOVv2i32);
    5150             :         }
    5151             :       }
    5152             :     }
    5153           7 :     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
    5154             :   }
    5155             : 
    5156          22 :   if (!(imm & 0x20)) return MCDisassembler::Fail;
    5157             : 
    5158          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
    5159             :     return MCDisassembler::Fail;
    5160          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
    5161             :     return MCDisassembler::Fail;
    5162          60 :   Inst.addOperand(MCOperand::createImm(64 - imm));
    5163             : 
    5164          20 :   return S;
    5165             : }
    5166             : 
    5167          37 : static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
    5168             :                                 uint64_t Address, const void *Decoder) {
    5169             :   const FeatureBitset &featureBits =
    5170          37 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5171             :   bool hasFullFP16 = featureBits[ARM::FeatureFullFP16];
    5172             : 
    5173             :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5174          37 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5175             :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5176          37 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5177             :   unsigned imm = fieldFromInstruction(Insn, 16, 6);
    5178             :   unsigned cmode = fieldFromInstruction(Insn, 8, 4);
    5179             :   unsigned op = fieldFromInstruction(Insn, 5, 1);
    5180             : 
    5181             :   DecodeStatus S = MCDisassembler::Success;
    5182             : 
    5183             :   // If the top 3 bits of imm are clear, this is a VMOV (immediate)
    5184          37 :   if (!(imm & 0x38)) {
    5185          16 :     if (cmode == 0xF) {
    5186           8 :       if (op == 1) return MCDisassembler::Fail;
    5187             :       Inst.setOpcode(ARM::VMOVv4f32);
    5188             :     }
    5189          11 :     if (hasFullFP16) {
    5190          10 :       if (cmode == 0xE) {
    5191           0 :         if (op == 1) {
    5192             :           Inst.setOpcode(ARM::VMOVv2i64);
    5193             :         } else {
    5194             :           Inst.setOpcode(ARM::VMOVv16i8);
    5195             :         }
    5196             :       }
    5197          10 :       if (cmode == 0xD) {
    5198           4 :         if (op == 1) {
    5199             :           Inst.setOpcode(ARM::VMVNv4i32);
    5200             :         } else {
    5201             :           Inst.setOpcode(ARM::VMOVv4i32);
    5202             :         }
    5203             :       }
    5204          10 :       if (cmode == 0xC) {
    5205           4 :         if (op == 1) {
    5206             :           Inst.setOpcode(ARM::VMVNv4i32);
    5207             :         } else {
    5208             :           Inst.setOpcode(ARM::VMOVv4i32);
    5209             :         }
    5210             :       }
    5211             :     }
    5212          11 :     return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
    5213             :   }
    5214             : 
    5215          21 :   if (!(imm & 0x20)) return MCDisassembler::Fail;
    5216             : 
    5217          42 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
    5218             :     return MCDisassembler::Fail;
    5219          42 :   if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
    5220             :     return MCDisassembler::Fail;
    5221          63 :   Inst.addOperand(MCOperand::createImm(64 - imm));
    5222             : 
    5223          21 :   return S;
    5224             : }
    5225             : 
    5226          20 : static DecodeStatus DecodeNEONComplexLane64Instruction(MCInst &Inst,
    5227             :                                                        unsigned Insn,
    5228             :                                                        uint64_t Address,
    5229             :                                                        const void *Decoder) {
    5230             :   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
    5231          20 :   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
    5232             :   unsigned Vn = (fieldFromInstruction(Insn, 16, 4) << 0);
    5233          20 :   Vn |= (fieldFromInstruction(Insn, 7, 1) << 4);
    5234             :   unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
    5235          20 :   Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
    5236             :   unsigned q = (fieldFromInstruction(Insn, 6, 1) << 0);
    5237             :   unsigned rotate = (fieldFromInstruction(Insn, 20, 2) << 0);
    5238             : 
    5239             :   DecodeStatus S = MCDisassembler::Success;
    5240             : 
    5241          20 :   auto DestRegDecoder = q ? DecodeQPRRegisterClass : DecodeDPRRegisterClass;
    5242             : 
    5243          40 :   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
    5244             :     return MCDisassembler::Fail;
    5245          40 :   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
    5246             :     return MCDisassembler::Fail;
    5247          40 :   if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
    5248             :     return MCDisassembler::Fail;
    5249          40 :   if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
    5250             :     return MCDisassembler::Fail;
    5251             :   // The lane index does not have any bits in the encoding, because it can only
    5252             :   // be 0.
    5253          40 :   Inst.addOperand(MCOperand::createImm(0));
    5254          60 :   Inst.addOperand(MCOperand::createImm(rotate));
    5255             : 
    5256          20 :   return S;
    5257             : }
    5258             : 
    5259          13 : static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
    5260             :                                 uint64_t Address, const void *Decoder) {
    5261             :   DecodeStatus S = MCDisassembler::Success;
    5262             : 
    5263             :   unsigned Rn = fieldFromInstruction(Val, 16, 4);
    5264             :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5265             :   unsigned Rm = fieldFromInstruction(Val, 0, 4);
    5266          13 :   Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
    5267             :   unsigned Cond = fieldFromInstruction(Val, 28, 4);
    5268             : 
    5269          13 :   if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
    5270             :     S = MCDisassembler::SoftFail;
    5271             : 
    5272          26 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5273             :     return MCDisassembler::Fail;
    5274          26 :   if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
    5275             :     return MCDisassembler::Fail;
    5276          13 :   if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 
    5277             :     return MCDisassembler::Fail;
    5278          26 :   if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
    5279             :     return MCDisassembler::Fail;
    5280          26 :   if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
    5281             :     return MCDisassembler::Fail;
    5282             : 
    5283             :   return S;
    5284             : }
    5285             : 
    5286          10 : static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
    5287             :                                             uint64_t Address, const void *Decoder) {
    5288             :   DecodeStatus S = MCDisassembler::Success;
    5289             : 
    5290             :   unsigned CRm = fieldFromInstruction(Val, 0, 4);
    5291             :   unsigned opc1 = fieldFromInstruction(Val, 4, 4);
    5292             :   unsigned cop = fieldFromInstruction(Val, 8, 4);
    5293             :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5294             :   unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
    5295             : 
    5296          10 :   if ((cop & ~0x1) == 0xa)
    5297             :     return MCDisassembler::Fail;
    5298             : 
    5299           9 :   if (Rt == Rt2)
    5300             :     S = MCDisassembler::SoftFail;
    5301             : 
    5302             :   // We have to check if the instruction is MRRC2
    5303             :   // or MCRR2 when constructing the operands for
    5304             :   // Inst. Reason is because MRRC2 stores to two
    5305             :   // registers so it's tablegen desc has has two
    5306             :   // outputs whereas MCRR doesn't store to any
    5307             :   // registers so all of it's operands are listed
    5308             :   // as inputs, therefore the operand order for
    5309             :   // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm]
    5310             :   // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm]
    5311             : 
    5312           9 :   if (Inst.getOpcode() == ARM::MRRC2) {
    5313          10 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5314             :       return MCDisassembler::Fail;
    5315          10 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5316             :       return MCDisassembler::Fail;
    5317             :   }
    5318          27 :   Inst.addOperand(MCOperand::createImm(cop));
    5319          27 :   Inst.addOperand(MCOperand::createImm(opc1));
    5320           9 :   if (Inst.getOpcode() == ARM::MCRR2) {
    5321           8 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
    5322             :       return MCDisassembler::Fail;
    5323           8 :     if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
    5324             :       return MCDisassembler::Fail;
    5325             :   }
    5326          27 :   Inst.addOperand(MCOperand::createImm(CRm));
    5327             : 
    5328             :   return S;
    5329             : }
    5330             : 
    5331         125 : static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
    5332             :                                          uint64_t Address,
    5333             :                                          const void *Decoder) {
    5334             :   const FeatureBitset &featureBits =
    5335         125 :       ((const MCDisassembler *)Decoder)->getSubtargetInfo().getFeatureBits();
    5336             :   DecodeStatus S = MCDisassembler::Success;
    5337             : 
    5338             :   unsigned Rt = fieldFromInstruction(Val, 12, 4);
    5339             : 
    5340         191 :   if (featureBits[ARM::ModeThumb] && !featureBits[ARM::HasV8Ops]) {
    5341          49 :     if (Rt == 13 || Rt == 15)
    5342             :       S = MCDisassembler::SoftFail;
    5343          49 :     Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
    5344             :   } else
    5345          76 :     Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
    5346             : 
    5347         125 :   if (featureBits[ARM::ModeThumb]) {
    5348         132 :     Inst.addOperand(MCOperand::createImm(ARMCC::AL));
    5349         132 :     Inst.addOperand(MCOperand::createReg(0));
    5350             :   } else {
    5351             :     unsigned pred = fieldFromInstruction(Val, 28, 4);
    5352         118 :     if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
    5353             :       return MCDisassembler::Fail;
    5354             :   }
    5355             : 
    5356             :   return S;
    5357             : }

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