LCOV - code coverage report
Current view: top level - lib/Target/ARM/MCTargetDesc - ARMAsmBackend.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 361 413 87.4 %
Date: 2018-02-21 17:27:13 Functions: 19 19 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "MCTargetDesc/ARMAsmBackend.h"
      11             : #include "MCTargetDesc/ARMAddressingModes.h"
      12             : #include "MCTargetDesc/ARMAsmBackendDarwin.h"
      13             : #include "MCTargetDesc/ARMAsmBackendELF.h"
      14             : #include "MCTargetDesc/ARMAsmBackendWinCOFF.h"
      15             : #include "MCTargetDesc/ARMFixupKinds.h"
      16             : #include "MCTargetDesc/ARMMCTargetDesc.h"
      17             : #include "llvm/ADT/StringSwitch.h"
      18             : #include "llvm/BinaryFormat/ELF.h"
      19             : #include "llvm/BinaryFormat/MachO.h"
      20             : #include "llvm/MC/MCAsmBackend.h"
      21             : #include "llvm/MC/MCAssembler.h"
      22             : #include "llvm/MC/MCContext.h"
      23             : #include "llvm/MC/MCDirectives.h"
      24             : #include "llvm/MC/MCELFObjectWriter.h"
      25             : #include "llvm/MC/MCExpr.h"
      26             : #include "llvm/MC/MCFixupKindInfo.h"
      27             : #include "llvm/MC/MCObjectWriter.h"
      28             : #include "llvm/MC/MCRegisterInfo.h"
      29             : #include "llvm/MC/MCSectionELF.h"
      30             : #include "llvm/MC/MCSectionMachO.h"
      31             : #include "llvm/MC/MCSubtargetInfo.h"
      32             : #include "llvm/MC/MCValue.h"
      33             : #include "llvm/Support/Debug.h"
      34             : #include "llvm/Support/ErrorHandling.h"
      35             : #include "llvm/Support/Format.h"
      36             : #include "llvm/Support/TargetParser.h"
      37             : #include "llvm/Support/raw_ostream.h"
      38             : using namespace llvm;
      39             : 
      40             : namespace {
      41             : class ARMELFObjectWriter : public MCELFObjectTargetWriter {
      42             : public:
      43             :   ARMELFObjectWriter(uint8_t OSABI)
      44             :       : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM,
      45             :                                 /*HasRelocationAddend*/ false) {}
      46             : };
      47             : } // end anonymous namespace
      48             : 
      49       14571 : const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
      50             :   const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = {
      51             :       // This table *must* be in the order that the fixup_* kinds are defined in
      52             :       // ARMFixupKinds.h.
      53             :       //
      54             :       // Name                      Offset (bits) Size (bits)     Flags
      55             :       {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      56             :       {"fixup_t2_ldst_pcrel_12", 0, 32,
      57             :        MCFixupKindInfo::FKF_IsPCRel |
      58             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      59             :       {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      60             :       {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      61             :       {"fixup_t2_pcrel_10", 0, 32,
      62             :        MCFixupKindInfo::FKF_IsPCRel |
      63             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      64             :       {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      65             :       {"fixup_t2_pcrel_9", 0, 32,
      66             :        MCFixupKindInfo::FKF_IsPCRel |
      67             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      68             :       {"fixup_thumb_adr_pcrel_10", 0, 8,
      69             :        MCFixupKindInfo::FKF_IsPCRel |
      70             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      71             :       {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      72             :       {"fixup_t2_adr_pcrel_12", 0, 32,
      73             :        MCFixupKindInfo::FKF_IsPCRel |
      74             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      75             :       {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
      76             :       {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
      77             :       {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      78             :       {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      79             :       {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
      80             :       {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
      81             :       {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
      82             :       {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel},
      83             :       {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
      84             :       {"fixup_arm_thumb_blx", 0, 32,
      85             :        MCFixupKindInfo::FKF_IsPCRel |
      86             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      87             :       {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
      88             :       {"fixup_arm_thumb_cp", 0, 8,
      89             :        MCFixupKindInfo::FKF_IsPCRel |
      90             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
      91             :       {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel},
      92             :       // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
      93             :       // - 19.
      94             :       {"fixup_arm_movt_hi16", 0, 20, 0},
      95             :       {"fixup_arm_movw_lo16", 0, 20, 0},
      96             :       {"fixup_t2_movt_hi16", 0, 20, 0},
      97             :       {"fixup_t2_movw_lo16", 0, 20, 0},
      98             :       {"fixup_arm_mod_imm", 0, 12, 0},
      99             :       {"fixup_t2_so_imm", 0, 26, 0},
     100             :   };
     101             :   const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = {
     102             :       // This table *must* be in the order that the fixup_* kinds are defined in
     103             :       // ARMFixupKinds.h.
     104             :       //
     105             :       // Name                      Offset (bits) Size (bits)     Flags
     106             :       {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     107             :       {"fixup_t2_ldst_pcrel_12", 0, 32,
     108             :        MCFixupKindInfo::FKF_IsPCRel |
     109             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     110             :       {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     111             :       {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     112             :       {"fixup_t2_pcrel_10", 0, 32,
     113             :        MCFixupKindInfo::FKF_IsPCRel |
     114             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     115             :       {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     116             :       {"fixup_t2_pcrel_9", 0, 32,
     117             :        MCFixupKindInfo::FKF_IsPCRel |
     118             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     119             :       {"fixup_thumb_adr_pcrel_10", 8, 8,
     120             :        MCFixupKindInfo::FKF_IsPCRel |
     121             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     122             :       {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     123             :       {"fixup_t2_adr_pcrel_12", 0, 32,
     124             :        MCFixupKindInfo::FKF_IsPCRel |
     125             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     126             :       {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
     127             :       {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
     128             :       {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     129             :       {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     130             :       {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
     131             :       {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
     132             :       {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
     133             :       {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel},
     134             :       {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
     135             :       {"fixup_arm_thumb_blx", 0, 32,
     136             :        MCFixupKindInfo::FKF_IsPCRel |
     137             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     138             :       {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel},
     139             :       {"fixup_arm_thumb_cp", 8, 8,
     140             :        MCFixupKindInfo::FKF_IsPCRel |
     141             :            MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
     142             :       {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel},
     143             :       // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16
     144             :       // - 19.
     145             :       {"fixup_arm_movt_hi16", 12, 20, 0},
     146             :       {"fixup_arm_movw_lo16", 12, 20, 0},
     147             :       {"fixup_t2_movt_hi16", 12, 20, 0},
     148             :       {"fixup_t2_movw_lo16", 12, 20, 0},
     149             :       {"fixup_arm_mod_imm", 20, 12, 0},
     150             :       {"fixup_t2_so_imm", 26, 6, 0},
     151             :   };
     152             : 
     153       14571 :   if (Kind < FirstTargetFixupKind)
     154        6304 :     return MCAsmBackend::getFixupKindInfo(Kind);
     155             : 
     156             :   assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
     157             :          "Invalid kind!");
     158        8267 :   return (IsLittleEndian ? InfosLE : InfosBE)[Kind - FirstTargetFixupKind];
     159             : }
     160             : 
     161        1133 : void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) {
     162        1133 :   switch (Flag) {
     163             :   default:
     164             :     break;
     165             :   case MCAF_Code16:
     166             :     setIsThumb(true);
     167             :     break;
     168             :   case MCAF_Code32:
     169             :     setIsThumb(false);
     170             :     break;
     171             :   }
     172        1133 : }
     173             : 
     174       23711 : unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
     175       23711 :   bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2];
     176             :   bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps];
     177             : 
     178       23711 :   switch (Op) {
     179             :   default:
     180             :     return Op;
     181         209 :   case ARM::tBcc:
     182         209 :     return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
     183         135 :   case ARM::tLDRpci:
     184         135 :     return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
     185          17 :   case ARM::tADR:
     186          17 :     return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
     187         210 :   case ARM::tB:
     188         210 :     return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
     189          25 :   case ARM::tCBZ:
     190          25 :     return ARM::tHINT;
     191          25 :   case ARM::tCBNZ:
     192          25 :     return ARM::tHINT;
     193             :   }
     194             : }
     195             : 
     196       23673 : bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
     197       23673 :   if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode())
     198             :     return true;
     199       23267 :   return false;
     200             : }
     201             : 
     202         363 : const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup,
     203             :                                                     uint64_t Value) const {
     204         363 :   switch ((unsigned)Fixup.getKind()) {
     205          84 :   case ARM::fixup_arm_thumb_br: {
     206             :     // Relaxing tB to t2B. tB has a signed 12-bit displacement with the
     207             :     // low bit being an implied zero. There's an implied +4 offset for the
     208             :     // branch, so we adjust the other way here to determine what's
     209             :     // encodable.
     210             :     //
     211             :     // Relax if the value is too big for a (signed) i8.
     212          84 :     int64_t Offset = int64_t(Value) - 4;
     213          84 :     if (Offset > 2046 || Offset < -2048)
     214             :       return "out of range pc-relative fixup value";
     215             :     break;
     216             :   }
     217         139 :   case ARM::fixup_arm_thumb_bcc: {
     218             :     // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the
     219             :     // low bit being an implied zero. There's an implied +4 offset for the
     220             :     // branch, so we adjust the other way here to determine what's
     221             :     // encodable.
     222             :     //
     223             :     // Relax if the value is too big for a (signed) i8.
     224         139 :     int64_t Offset = int64_t(Value) - 4;
     225         139 :     if (Offset > 254 || Offset < -256)
     226             :       return "out of range pc-relative fixup value";
     227             :     break;
     228             :   }
     229         114 :   case ARM::fixup_thumb_adr_pcrel_10:
     230             :   case ARM::fixup_arm_thumb_cp: {
     231             :     // If the immediate is negative, greater than 1020, or not a multiple
     232             :     // of four, the wide version of the instruction must be used.
     233         114 :     int64_t Offset = int64_t(Value) - 4;
     234         114 :     if (Offset & 3)
     235             :       return "misaligned pc-relative fixup value";
     236         104 :     else if (Offset > 1020 || Offset < 0)
     237             :       return "out of range pc-relative fixup value";
     238             :     break;
     239             :   }
     240          26 :   case ARM::fixup_arm_thumb_cb: {
     241             :     // If we have a Thumb CBZ or CBNZ instruction and its target is the next
     242             :     // instruction it is is actually out of range for the instruction.
     243             :     // It will be changed to a NOP.
     244          26 :     int64_t Offset = (Value & ~1);
     245          26 :     if (Offset == 2)
     246             :       return "will be converted to nop";
     247             :     break;
     248             :   }
     249           0 :   default:
     250           0 :     llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!");
     251             :   }
     252         340 :   return nullptr;
     253             : }
     254             : 
     255         188 : bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
     256             :                                          const MCRelaxableFragment *DF,
     257             :                                          const MCAsmLayout &Layout) const {
     258         188 :   return reasonForFixupRelaxation(Fixup, Value);
     259             : }
     260             : 
     261          38 : void ARMAsmBackend::relaxInstruction(const MCInst &Inst,
     262             :                                      const MCSubtargetInfo &STI,
     263             :                                      MCInst &Res) const {
     264          38 :   unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
     265             : 
     266             :   // Sanity check w/ diagnostic if we get here w/ a bogus instruction.
     267          38 :   if (RelaxedOp == Inst.getOpcode()) {
     268             :     SmallString<256> Tmp;
     269             :     raw_svector_ostream OS(Tmp);
     270           0 :     Inst.dump_pretty(OS);
     271           0 :     OS << "\n";
     272           0 :     report_fatal_error("unexpected instruction to relax: " + OS.str());
     273             :   }
     274             : 
     275             :   // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we
     276             :   // have to change the operands too.
     277          38 :   if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
     278             :       RelaxedOp == ARM::tHINT) {
     279             :     Res.setOpcode(RelaxedOp);
     280           4 :     Res.addOperand(MCOperand::createImm(0));
     281           4 :     Res.addOperand(MCOperand::createImm(14));
     282           4 :     Res.addOperand(MCOperand::createReg(0));
     283           2 :     return;
     284             :   }
     285             : 
     286             :   // The rest of instructions we're relaxing have the same operands.
     287             :   // We just need to update to the proper opcode.
     288             :   Res = Inst;
     289             :   Res.setOpcode(RelaxedOp);
     290             : }
     291             : 
     292        2333 : bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
     293             :   const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8
     294             :   const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP
     295             :   const uint32_t ARMv4_NopEncoding = 0xe1a00000;   // using MOV r0,r0
     296             :   const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP
     297        2333 :   if (isThumb()) {
     298             :     const uint16_t nopEncoding =
     299        2436 :         hasNOP() ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding;
     300        1218 :     uint64_t NumNops = Count / 2;
     301        1304 :     for (uint64_t i = 0; i != NumNops; ++i)
     302          43 :       OW->write16(nopEncoding);
     303        1218 :     if (Count & 1)
     304           2 :       OW->write8(0);
     305             :     return true;
     306             :   }
     307             :   // ARM mode
     308             :   const uint32_t nopEncoding =
     309        2230 :       hasNOP() ? ARMv6T2_NopEncoding : ARMv4_NopEncoding;
     310        1115 :   uint64_t NumNops = Count / 4;
     311        1151 :   for (uint64_t i = 0; i != NumNops; ++i)
     312          18 :     OW->write32(nopEncoding);
     313             :   // FIXME: should this function return false when unable to write exactly
     314             :   // 'Count' bytes with NOP encodings?
     315        1115 :   switch (Count % 4) {
     316             :   default:
     317             :     break; // No leftover bytes to write
     318           1 :   case 1:
     319           1 :     OW->write8(0);
     320           1 :     break;
     321           4 :   case 2:
     322           4 :     OW->write16(0);
     323           4 :     break;
     324           0 :   case 3:
     325           0 :     OW->write16(0);
     326           0 :     OW->write8(0xa0);
     327           0 :     break;
     328             :   }
     329             : 
     330             :   return true;
     331             : }
     332             : 
     333             : static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) {
     334         328 :   if (IsLittleEndian) {
     335             :     // Note that the halfwords are stored high first and low second in thumb;
     336             :     // so we need to swap the fixup value here to map properly.
     337             :     uint32_t Swapped = (Value & 0xFFFF0000) >> 16;
     338         315 :     Swapped |= (Value & 0x0000FFFF) << 16;
     339             :     return Swapped;
     340             :   } else
     341             :     return Value;
     342             : }
     343             : 
     344             : static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf,
     345             :                               bool IsLittleEndian) {
     346             :   uint32_t Value;
     347             : 
     348         924 :   if (IsLittleEndian) {
     349         921 :     Value = (SecondHalf & 0xFFFF) << 16;
     350         921 :     Value |= (FirstHalf & 0xFFFF);
     351             :   } else {
     352             :     Value = (SecondHalf & 0xFFFF);
     353           3 :     Value |= (FirstHalf & 0xFFFF) << 16;
     354             :   }
     355             : 
     356             :   return Value;
     357             : }
     358             : 
     359        5036 : unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm,
     360             :                                          const MCFixup &Fixup,
     361             :                                          const MCValue &Target, uint64_t Value,
     362             :                                          bool IsResolved, MCContext &Ctx,
     363             :                                          bool IsLittleEndian) const {
     364        5036 :   unsigned Kind = Fixup.getKind();
     365             : 
     366             :   // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT
     367             :   // and .word relocations they put the Thumb bit into the addend if possible.
     368             :   // Other relocation types don't want this bit though (branches couldn't encode
     369             :   // it if it *was* present, and no other relocations exist) and it can
     370             :   // interfere with checking valid expressions.
     371        5036 :   if (const MCSymbolRefExpr *A = Target.getSymA()) {
     372        4587 :     if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) &&
     373          21 :         (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 ||
     374          20 :          Kind == ARM::fixup_arm_movt_hi16 || Kind == ARM::fixup_t2_movw_lo16 ||
     375             :          Kind == ARM::fixup_t2_movt_hi16))
     376           3 :       Value |= 1;
     377             :   }
     378             : 
     379        5036 :   switch (Kind) {
     380             :   default:
     381           0 :     Ctx.reportError(Fixup.getLoc(), "bad relocation fixup type");
     382           0 :     return 0;
     383        2243 :   case FK_Data_1:
     384             :   case FK_Data_2:
     385             :   case FK_Data_4:
     386        2243 :     return Value;
     387           3 :   case FK_SecRel_2:
     388           3 :     return Value;
     389          11 :   case FK_SecRel_4:
     390          11 :     return Value;
     391          36 :   case ARM::fixup_arm_movt_hi16:
     392          71 :     if (IsResolved || !STI.getTargetTriple().isOSBinFormatELF())
     393           9 :       Value >>= 16;
     394             :     LLVM_FALLTHROUGH;
     395             :   case ARM::fixup_arm_movw_lo16: {
     396          74 :     unsigned Hi4 = (Value & 0xF000) >> 12;
     397          74 :     unsigned Lo12 = Value & 0x0FFF;
     398             :     // inst{19-16} = Hi4;
     399             :     // inst{11-0} = Lo12;
     400          74 :     Value = (Hi4 << 16) | (Lo12);
     401          74 :     return Value;
     402             :   }
     403          64 :   case ARM::fixup_t2_movt_hi16:
     404         127 :     if (IsResolved || !STI.getTargetTriple().isOSBinFormatELF())
     405          44 :       Value >>= 16;
     406             :     LLVM_FALLTHROUGH;
     407             :   case ARM::fixup_t2_movw_lo16: {
     408         127 :     unsigned Hi4 = (Value & 0xF000) >> 12;
     409         127 :     unsigned i = (Value & 0x800) >> 11;
     410         127 :     unsigned Mid3 = (Value & 0x700) >> 8;
     411         127 :     unsigned Lo8 = Value & 0x0FF;
     412             :     // inst{19-16} = Hi4;
     413             :     // inst{26} = i;
     414             :     // inst{14-12} = Mid3;
     415             :     // inst{7-0} = Lo8;
     416         127 :     Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
     417             :     return swapHalfWords(Value, IsLittleEndian);
     418             :   }
     419          27 :   case ARM::fixup_arm_ldst_pcrel_12:
     420             :     // ARM PC-relative values are offset by 8.
     421          27 :     Value -= 4;
     422             :     LLVM_FALLTHROUGH;
     423          39 :   case ARM::fixup_t2_ldst_pcrel_12: {
     424             :     // Offset by 4, adjusted by two due to the half-word ordering of thumb.
     425          39 :     Value -= 4;
     426             :     bool isAdd = true;
     427          39 :     if ((int64_t)Value < 0) {
     428           9 :       Value = -Value;
     429             :       isAdd = false;
     430             :     }
     431          39 :     if (Value >= 4096) {
     432           2 :       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
     433           2 :       return 0;
     434             :     }
     435          37 :     Value |= isAdd << 23;
     436             : 
     437             :     // Same addressing mode as fixup_arm_pcrel_10,
     438             :     // but with 16-bit halfwords swapped.
     439          37 :     if (Kind == ARM::fixup_t2_ldst_pcrel_12)
     440          12 :       return swapHalfWords(Value, IsLittleEndian);
     441             : 
     442          25 :     return Value;
     443             :   }
     444           7 :   case ARM::fixup_arm_adr_pcrel_12: {
     445             :     // ARM PC-relative values are offset by 8.
     446           7 :     Value -= 8;
     447             :     unsigned opc = 4; // bits {24-21}. Default to add: 0b0100
     448           7 :     if ((int64_t)Value < 0) {
     449           1 :       Value = -Value;
     450             :       opc = 2; // 0b0010
     451             :     }
     452           7 :     if (ARM_AM::getSOImmVal(Value) == -1) {
     453           0 :       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
     454           0 :       return 0;
     455             :     }
     456             :     // Encode the immediate and shift the opcode into place.
     457           7 :     return ARM_AM::getSOImmVal(Value) | (opc << 21);
     458             :   }
     459             : 
     460           2 :   case ARM::fixup_t2_adr_pcrel_12: {
     461           2 :     Value -= 4;
     462             :     unsigned opc = 0;
     463           2 :     if ((int64_t)Value < 0) {
     464           1 :       Value = -Value;
     465             :       opc = 5;
     466             :     }
     467             : 
     468           2 :     uint32_t out = (opc << 21);
     469           2 :     out |= (Value & 0x800) << 15;
     470           2 :     out |= (Value & 0x700) << 4;
     471           2 :     out |= (Value & 0x0FF);
     472             : 
     473             :     return swapHalfWords(out, IsLittleEndian);
     474             :   }
     475             : 
     476        1004 :   case ARM::fixup_arm_condbranch:
     477             :   case ARM::fixup_arm_uncondbranch:
     478             :   case ARM::fixup_arm_uncondbl:
     479             :   case ARM::fixup_arm_condbl:
     480             :   case ARM::fixup_arm_blx:
     481             :     // These values don't encode the low two bits since they're always zero.
     482             :     // Offset by 8 just as above.
     483             :     if (const MCSymbolRefExpr *SRE =
     484        1004 :             dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
     485         995 :       if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
     486             :         return 0;
     487        1004 :     return 0xffffff & ((Value - 8) >> 2);
     488          73 :   case ARM::fixup_t2_uncondbranch: {
     489          73 :     Value = Value - 4;
     490          73 :     Value >>= 1; // Low bit is not encoded.
     491             : 
     492             :     uint32_t out = 0;
     493          73 :     bool I = Value & 0x800000;
     494          73 :     bool J1 = Value & 0x400000;
     495          73 :     bool J2 = Value & 0x200000;
     496             :     J1 ^= I;
     497             :     J2 ^= I;
     498             : 
     499          73 :     out |= I << 26;                 // S bit
     500          73 :     out |= !J1 << 13;               // J1 bit
     501          73 :     out |= !J2 << 11;               // J2 bit
     502          73 :     out |= (Value & 0x1FF800) << 5; // imm6 field
     503          73 :     out |= (Value & 0x0007FF);      // imm11 field
     504             : 
     505             :     return swapHalfWords(out, IsLittleEndian);
     506             :   }
     507          27 :   case ARM::fixup_t2_condbranch: {
     508          27 :     Value = Value - 4;
     509          27 :     Value >>= 1; // Low bit is not encoded.
     510             : 
     511             :     uint64_t out = 0;
     512          27 :     out |= (Value & 0x80000) << 7; // S bit
     513          27 :     out |= (Value & 0x40000) >> 7; // J2 bit
     514          27 :     out |= (Value & 0x20000) >> 4; // J1 bit
     515          27 :     out |= (Value & 0x1F800) << 5; // imm6 field
     516          27 :     out |= (Value & 0x007FF);      // imm11 field
     517             : 
     518          27 :     return swapHalfWords(out, IsLittleEndian);
     519             :   }
     520         909 :   case ARM::fixup_arm_thumb_bl: {
     521             :     // FIXME: We get both thumb1 and thumb2 in here, so we can only check for
     522             :     // the less strict thumb2 value.
     523        1818 :     if (!isInt<26>(Value - 4)) {
     524           2 :       Ctx.reportError(Fixup.getLoc(), "Relocation out of range");
     525           2 :       return 0;
     526             :     }
     527             : 
     528             :     // The value doesn't encode the low bit (always zero) and is offset by
     529             :     // four. The 32-bit immediate value is encoded as
     530             :     //   imm32 = SignExtend(S:I1:I2:imm10:imm11:0)
     531             :     // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
     532             :     // The value is encoded into disjoint bit positions in the destination
     533             :     // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
     534             :     // J = either J1 or J2 bit
     535             :     //
     536             :     //   BL:  xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII
     537             :     //
     538             :     // Note that the halfwords are stored high first, low second; so we need
     539             :     // to transpose the fixup value here to map properly.
     540         907 :     uint32_t offset = (Value - 4) >> 1;
     541         907 :     uint32_t signBit = (offset & 0x800000) >> 23;
     542         907 :     uint32_t I1Bit = (offset & 0x400000) >> 22;
     543         907 :     uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
     544         907 :     uint32_t I2Bit = (offset & 0x200000) >> 21;
     545         907 :     uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
     546         907 :     uint32_t imm10Bits = (offset & 0x1FF800) >> 11;
     547         907 :     uint32_t imm11Bits = (offset & 0x000007FF);
     548             : 
     549         907 :     uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits);
     550        1814 :     uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
     551         907 :                            (uint16_t)imm11Bits);
     552             :     return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
     553             :   }
     554          19 :   case ARM::fixup_arm_thumb_blx: {
     555             :     // The value doesn't encode the low two bits (always zero) and is offset by
     556             :     // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as
     557             :     //   imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00)
     558             :     // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S).
     559             :     // The value is encoded into disjoint bit positions in the destination
     560             :     // opcode. x = unchanged, I = immediate value bit, S = sign extension bit,
     561             :     // J = either J1 or J2 bit, 0 = zero.
     562             :     //
     563             :     //   BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0
     564             :     //
     565             :     // Note that the halfwords are stored high first, low second; so we need
     566             :     // to transpose the fixup value here to map properly.
     567          19 :     if (Value % 4 != 0) {
     568           2 :       Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination");
     569           2 :       return 0;
     570             :     }
     571             : 
     572          17 :     uint32_t offset = (Value - 4) >> 2;
     573             :     if (const MCSymbolRefExpr *SRE =
     574          17 :             dyn_cast<MCSymbolRefExpr>(Fixup.getValue()))
     575          15 :       if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL)
     576             :         offset = 0;
     577          17 :     uint32_t signBit = (offset & 0x400000) >> 22;
     578          17 :     uint32_t I1Bit = (offset & 0x200000) >> 21;
     579          17 :     uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit;
     580          17 :     uint32_t I2Bit = (offset & 0x100000) >> 20;
     581          17 :     uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit;
     582          17 :     uint32_t imm10HBits = (offset & 0xFFC00) >> 10;
     583          17 :     uint32_t imm10LBits = (offset & 0x3FF);
     584             : 
     585          17 :     uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits);
     586          34 :     uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) |
     587          17 :                            ((uint16_t)imm10LBits) << 1);
     588             :     return joinHalfWords(FirstHalf, SecondHalf, IsLittleEndian);
     589             :   }
     590          98 :   case ARM::fixup_thumb_adr_pcrel_10:
     591             :   case ARM::fixup_arm_thumb_cp:
     592             :     // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we
     593             :     // could have an error on our hands.
     594         196 :     if (!STI.getFeatureBits()[ARM::FeatureThumb2] && IsResolved) {
     595          84 :       const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
     596          84 :       if (FixupDiagnostic) {
     597           8 :         Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
     598           8 :         return 0;
     599             :       }
     600             :     }
     601             :     // Offset by 4, and don't encode the low two bits.
     602          90 :     return ((Value - 4) >> 2) & 0xff;
     603          20 :   case ARM::fixup_arm_thumb_cb: {
     604             :     // CB instructions can only branch to offsets in [4, 126] in multiples of 2
     605             :     // so ensure that the raw value LSB is zero and it lies in [2, 130].
     606             :     // An offset of 2 will be relaxed to a NOP.
     607          20 :     if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) {
     608          12 :       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
     609          12 :       return 0;
     610             :     }
     611             :     // Offset by 4 and don't encode the lower bit, which is always 0.
     612             :     // FIXME: diagnose if no Thumb2
     613           8 :     uint32_t Binary = (Value - 4) >> 1;
     614           8 :     return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
     615             :   }
     616          83 :   case ARM::fixup_arm_thumb_br:
     617             :     // Offset by 4 and don't encode the lower bit, which is always 0.
     618         174 :     if (!STI.getFeatureBits()[ARM::FeatureThumb2] &&
     619             :         !STI.getFeatureBits()[ARM::HasV8MBaselineOps]) {
     620           7 :       const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
     621           7 :       if (FixupDiagnostic) {
     622           3 :         Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
     623           3 :         return 0;
     624             :       }
     625             :     }
     626          80 :     return ((Value - 4) >> 1) & 0x7ff;
     627         128 :   case ARM::fixup_arm_thumb_bcc:
     628             :     // Offset by 4 and don't encode the lower bit, which is always 0.
     629         256 :     if (!STI.getFeatureBits()[ARM::FeatureThumb2]) {
     630          84 :       const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
     631          84 :       if (FixupDiagnostic) {
     632           2 :         Ctx.reportError(Fixup.getLoc(), FixupDiagnostic);
     633           2 :         return 0;
     634             :       }
     635             :     }
     636         126 :     return ((Value - 4) >> 1) & 0xff;
     637           1 :   case ARM::fixup_arm_pcrel_10_unscaled: {
     638           1 :     Value = Value - 8; // ARM fixups offset by an additional word and don't
     639             :                        // need to adjust for the half-word ordering.
     640             :     bool isAdd = true;
     641           1 :     if ((int64_t)Value < 0) {
     642           0 :       Value = -Value;
     643             :       isAdd = false;
     644             :     }
     645             :     // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8].
     646           1 :     if (Value >= 256) {
     647           0 :       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
     648           0 :       return 0;
     649             :     }
     650           1 :     Value = (Value & 0xf) | ((Value & 0xf0) << 4);
     651           1 :     return Value | (isAdd << 23);
     652             :   }
     653          73 :   case ARM::fixup_arm_pcrel_10:
     654          73 :     Value = Value - 4; // ARM fixups offset by an additional word and don't
     655             :                        // need to adjust for the half-word ordering.
     656             :     LLVM_FALLTHROUGH;
     657         148 :   case ARM::fixup_t2_pcrel_10: {
     658             :     // Offset by 4, adjusted by two due to the half-word ordering of thumb.
     659         148 :     Value = Value - 4;
     660             :     bool isAdd = true;
     661         148 :     if ((int64_t)Value < 0) {
     662          86 :       Value = -Value;
     663             :       isAdd = false;
     664             :     }
     665             :     // These values don't encode the low two bits since they're always zero.
     666         148 :     Value >>= 2;
     667         148 :     if (Value >= 256) {
     668           0 :       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
     669           0 :       return 0;
     670             :     }
     671         148 :     Value |= isAdd << 23;
     672             : 
     673             :     // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords
     674             :     // swapped.
     675         148 :     if (Kind == ARM::fixup_t2_pcrel_10)
     676          75 :       return swapHalfWords(Value, IsLittleEndian);
     677             : 
     678          73 :     return Value;
     679             :   }
     680           0 :   case ARM::fixup_arm_pcrel_9:
     681           0 :     Value = Value - 4; // ARM fixups offset by an additional word and don't
     682             :                        // need to adjust for the half-word ordering.
     683             :     LLVM_FALLTHROUGH;
     684           0 :   case ARM::fixup_t2_pcrel_9: {
     685             :     // Offset by 4, adjusted by two due to the half-word ordering of thumb.
     686           0 :     Value = Value - 4;
     687             :     bool isAdd = true;
     688           0 :     if ((int64_t)Value < 0) {
     689           0 :       Value = -Value;
     690             :       isAdd = false;
     691             :     }
     692             :     // These values don't encode the low bit since it's always zero.
     693           0 :     if (Value & 1) {
     694           0 :       Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup");
     695           0 :       return 0;
     696             :     }
     697           0 :     Value >>= 1;
     698           0 :     if (Value >= 256) {
     699           0 :       Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value");
     700           0 :       return 0;
     701             :     }
     702           0 :     Value |= isAdd << 23;
     703             : 
     704             :     // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords
     705             :     // swapped.
     706           0 :     if (Kind == ARM::fixup_t2_pcrel_9)
     707           0 :       return swapHalfWords(Value, IsLittleEndian);
     708             : 
     709           0 :     return Value;
     710             :   }
     711           7 :   case ARM::fixup_arm_mod_imm:
     712           7 :     Value = ARM_AM::getSOImmVal(Value);
     713           7 :     if (Value >> 12) {
     714           1 :       Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
     715           1 :       return 0;
     716             :     }
     717           6 :     return Value;
     718          13 :   case ARM::fixup_t2_so_imm: {
     719          13 :     Value = ARM_AM::getT2SOImmVal(Value);
     720          13 :     if ((int64_t)Value < 0) {
     721           1 :       Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value");
     722           1 :       return 0;
     723             :     }
     724             :     // Value will contain a 12-bit value broken up into a 4-bit shift in bits
     725             :     // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate
     726             :     // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit
     727             :     // 10 of the upper half-word and imm3 is placed at 14:12 of the lower
     728             :     // half-word.
     729             :     uint64_t EncValue = 0;
     730          12 :     EncValue |= (Value & 0x800) << 15;
     731          12 :     EncValue |= (Value & 0x700) << 4;
     732          12 :     EncValue |= (Value & 0xff);
     733          12 :     return swapHalfWords(EncValue, IsLittleEndian);
     734             :   }
     735             :   }
     736             : }
     737             : 
     738        1440 : bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
     739             :                                           const MCFixup &Fixup,
     740             :                                           const MCValue &Target) {
     741        1440 :   const MCSymbolRefExpr *A = Target.getSymA();
     742        1440 :   const MCSymbol *Sym = A ? &A->getSymbol() : nullptr;
     743        1440 :   const unsigned FixupKind = Fixup.getKind() ;
     744        1440 :   if ((unsigned)Fixup.getKind() == ARM::fixup_arm_thumb_bl) {
     745             :     assert(Sym && "How did we resolve this?");
     746             : 
     747             :     // If the symbol is external the linker will handle it.
     748             :     // FIXME: Should we handle it as an optimization?
     749             : 
     750             :     // If the symbol is out of range, produce a relocation and hope the
     751             :     // linker can handle it. GNU AS produces an error in this case.
     752          25 :     if (Sym->isExternal())
     753             :       return true;
     754             :   }
     755             :   // Create relocations for unconditional branches to function symbols with
     756             :   // different execution mode in ELF binaries.
     757        2392 :   if (Sym && Sym->isELF()) {
     758         450 :     unsigned Type = dyn_cast<MCSymbolELF>(Sym)->getType();
     759         450 :     if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) {
     760          23 :       if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch))
     761             :         return true;
     762          35 :       if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br ||
     763          13 :                                     FixupKind == ARM::fixup_arm_thumb_bl ||
     764          10 :                                     FixupKind == ARM::fixup_t2_condbranch ||
     765             :                                     FixupKind == ARM::fixup_t2_uncondbranch))
     766             :         return true;
     767             :     }
     768             :   }
     769             :   // We must always generate a relocation for BL/BLX instructions if we have
     770             :   // a symbol to reference, as the linker relies on knowing the destination
     771             :   // symbol's thumb-ness to get interworking right.
     772        2378 :   if (A && (FixupKind == ARM::fixup_arm_thumb_blx ||
     773         958 :             FixupKind == ARM::fixup_arm_blx ||
     774         948 :             FixupKind == ARM::fixup_arm_uncondbl ||
     775             :             FixupKind == ARM::fixup_arm_condbl))
     776             :     return true;
     777        1395 :   return false;
     778             : }
     779             : 
     780             : /// getFixupKindNumBytes - The number of bytes the fixup may change.
     781        5036 : static unsigned getFixupKindNumBytes(unsigned Kind) {
     782        5036 :   switch (Kind) {
     783           0 :   default:
     784           0 :     llvm_unreachable("Unknown fixup kind!");
     785             : 
     786             :   case FK_Data_1:
     787             :   case ARM::fixup_arm_thumb_bcc:
     788             :   case ARM::fixup_arm_thumb_cp:
     789             :   case ARM::fixup_thumb_adr_pcrel_10:
     790             :     return 1;
     791             : 
     792         181 :   case FK_Data_2:
     793             :   case ARM::fixup_arm_thumb_br:
     794             :   case ARM::fixup_arm_thumb_cb:
     795             :   case ARM::fixup_arm_mod_imm:
     796         181 :     return 2;
     797             : 
     798        1112 :   case ARM::fixup_arm_pcrel_10_unscaled:
     799             :   case ARM::fixup_arm_ldst_pcrel_12:
     800             :   case ARM::fixup_arm_pcrel_10:
     801             :   case ARM::fixup_arm_pcrel_9:
     802             :   case ARM::fixup_arm_adr_pcrel_12:
     803             :   case ARM::fixup_arm_uncondbl:
     804             :   case ARM::fixup_arm_condbl:
     805             :   case ARM::fixup_arm_blx:
     806             :   case ARM::fixup_arm_condbranch:
     807             :   case ARM::fixup_arm_uncondbranch:
     808        1112 :     return 3;
     809             : 
     810        3494 :   case FK_Data_4:
     811             :   case ARM::fixup_t2_ldst_pcrel_12:
     812             :   case ARM::fixup_t2_condbranch:
     813             :   case ARM::fixup_t2_uncondbranch:
     814             :   case ARM::fixup_t2_pcrel_10:
     815             :   case ARM::fixup_t2_pcrel_9:
     816             :   case ARM::fixup_t2_adr_pcrel_12:
     817             :   case ARM::fixup_arm_thumb_bl:
     818             :   case ARM::fixup_arm_thumb_blx:
     819             :   case ARM::fixup_arm_movt_hi16:
     820             :   case ARM::fixup_arm_movw_lo16:
     821             :   case ARM::fixup_t2_movt_hi16:
     822             :   case ARM::fixup_t2_movw_lo16:
     823             :   case ARM::fixup_t2_so_imm:
     824        3494 :     return 4;
     825             : 
     826           3 :   case FK_SecRel_2:
     827           3 :     return 2;
     828          11 :   case FK_SecRel_4:
     829          11 :     return 4;
     830             :   }
     831             : }
     832             : 
     833             : /// getFixupKindContainerSizeBytes - The number of bytes of the
     834             : /// container involved in big endian.
     835          43 : static unsigned getFixupKindContainerSizeBytes(unsigned Kind) {
     836          43 :   switch (Kind) {
     837           0 :   default:
     838           0 :     llvm_unreachable("Unknown fixup kind!");
     839             : 
     840             :   case FK_Data_1:
     841             :     return 1;
     842           1 :   case FK_Data_2:
     843           1 :     return 2;
     844           6 :   case FK_Data_4:
     845           6 :     return 4;
     846             : 
     847           3 :   case ARM::fixup_arm_thumb_bcc:
     848             :   case ARM::fixup_arm_thumb_cp:
     849             :   case ARM::fixup_thumb_adr_pcrel_10:
     850             :   case ARM::fixup_arm_thumb_br:
     851             :   case ARM::fixup_arm_thumb_cb:
     852             :     // Instruction size is 2 bytes.
     853           3 :     return 2;
     854             : 
     855          32 :   case ARM::fixup_arm_pcrel_10_unscaled:
     856             :   case ARM::fixup_arm_ldst_pcrel_12:
     857             :   case ARM::fixup_arm_pcrel_10:
     858             :   case ARM::fixup_arm_adr_pcrel_12:
     859             :   case ARM::fixup_arm_uncondbl:
     860             :   case ARM::fixup_arm_condbl:
     861             :   case ARM::fixup_arm_blx:
     862             :   case ARM::fixup_arm_condbranch:
     863             :   case ARM::fixup_arm_uncondbranch:
     864             :   case ARM::fixup_t2_ldst_pcrel_12:
     865             :   case ARM::fixup_t2_condbranch:
     866             :   case ARM::fixup_t2_uncondbranch:
     867             :   case ARM::fixup_t2_pcrel_10:
     868             :   case ARM::fixup_t2_adr_pcrel_12:
     869             :   case ARM::fixup_arm_thumb_bl:
     870             :   case ARM::fixup_arm_thumb_blx:
     871             :   case ARM::fixup_arm_movt_hi16:
     872             :   case ARM::fixup_arm_movw_lo16:
     873             :   case ARM::fixup_t2_movt_hi16:
     874             :   case ARM::fixup_t2_movw_lo16:
     875             :   case ARM::fixup_arm_mod_imm:
     876             :   case ARM::fixup_t2_so_imm:
     877             :     // Instruction size is 4 bytes.
     878          32 :     return 4;
     879             :   }
     880             : }
     881             : 
     882        5036 : void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
     883             :                                const MCValue &Target,
     884             :                                MutableArrayRef<char> Data, uint64_t Value,
     885             :                                bool IsResolved) const {
     886        5036 :   unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
     887        5036 :   MCContext &Ctx = Asm.getContext();
     888        5036 :   Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx,
     889        5036 :                            IsLittleEndian);
     890        5036 :   if (!Value)
     891             :     return; // Doesn't change encoding.
     892             : 
     893        3715 :   unsigned Offset = Fixup.getOffset();
     894             :   assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
     895             : 
     896             :   // Used to point to big endian bytes.
     897             :   unsigned FullSizeBytes;
     898        3715 :   if (!IsLittleEndian) {
     899          43 :     FullSizeBytes = getFixupKindContainerSizeBytes(Fixup.getKind());
     900             :     assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!");
     901             :     assert(NumBytes <= FullSizeBytes && "Invalid fixup size!");
     902             :   }
     903             : 
     904             :   // For each byte of the fragment that the fixup touches, mask in the bits from
     905             :   // the fixup value. The Value has been "split up" into the appropriate
     906             :   // bitfields above.
     907       29271 :   for (unsigned i = 0; i != NumBytes; ++i) {
     908       12778 :     unsigned Idx = IsLittleEndian ? i : (FullSizeBytes - 1 - i);
     909       25556 :     Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
     910             :   }
     911             : }
     912             : 
     913             : namespace CU {
     914             : 
     915             : /// \brief Compact unwind encoding values.
     916             : enum CompactUnwindEncodings {
     917             :   UNWIND_ARM_MODE_MASK                         = 0x0F000000,
     918             :   UNWIND_ARM_MODE_FRAME                        = 0x01000000,
     919             :   UNWIND_ARM_MODE_FRAME_D                      = 0x02000000,
     920             :   UNWIND_ARM_MODE_DWARF                        = 0x04000000,
     921             : 
     922             :   UNWIND_ARM_FRAME_STACK_ADJUST_MASK           = 0x00C00000,
     923             : 
     924             :   UNWIND_ARM_FRAME_FIRST_PUSH_R4               = 0x00000001,
     925             :   UNWIND_ARM_FRAME_FIRST_PUSH_R5               = 0x00000002,
     926             :   UNWIND_ARM_FRAME_FIRST_PUSH_R6               = 0x00000004,
     927             : 
     928             :   UNWIND_ARM_FRAME_SECOND_PUSH_R8              = 0x00000008,
     929             :   UNWIND_ARM_FRAME_SECOND_PUSH_R9              = 0x00000010,
     930             :   UNWIND_ARM_FRAME_SECOND_PUSH_R10             = 0x00000020,
     931             :   UNWIND_ARM_FRAME_SECOND_PUSH_R11             = 0x00000040,
     932             :   UNWIND_ARM_FRAME_SECOND_PUSH_R12             = 0x00000080,
     933             : 
     934             :   UNWIND_ARM_FRAME_D_REG_COUNT_MASK            = 0x00000F00,
     935             : 
     936             :   UNWIND_ARM_DWARF_SECTION_OFFSET              = 0x00FFFFFF
     937             : };
     938             : 
     939             : } // end CU namespace
     940             : 
     941             : /// Generate compact unwind encoding for the function based on the CFI
     942             : /// instructions. If the CFI instructions describe a frame that cannot be
     943             : /// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which
     944             : /// tells the runtime to fallback and unwind using dwarf.
     945          18 : uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
     946             :     ArrayRef<MCCFIInstruction> Instrs) const {
     947             :   DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n");
     948             :   // Only armv7k uses CFI based unwinding.
     949          18 :   if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K)
     950             :     return 0;
     951             :   // No .cfi directives means no frame.
     952           9 :   if (Instrs.empty())
     953             :     return 0;
     954             :   // Start off assuming CFA is at SP+0.
     955             :   int CFARegister = ARM::SP;
     956             :   int CFARegisterOffset = 0;
     957             :   // Mark savable registers as initially unsaved
     958             :   DenseMap<unsigned, int> RegOffsets;
     959             :   int FloatRegCount = 0;
     960             :   // Process each .cfi directive and build up compact unwind info.
     961          77 :   for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
     962             :     int Reg;
     963          35 :     const MCCFIInstruction &Inst = Instrs[i];
     964          35 :     switch (Inst.getOperation()) {
     965           7 :     case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
     966           7 :       CFARegisterOffset = -Inst.getOffset();
     967           7 :       CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
     968           7 :       break;
     969           0 :     case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset
     970           0 :       CFARegisterOffset = -Inst.getOffset();
     971           0 :       break;
     972           0 :     case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register
     973           0 :       CFARegister = MRI.getLLVMRegNum(Inst.getRegister(), true);
     974           0 :       break;
     975          28 :     case MCCFIInstruction::OpOffset: // DW_CFA_offset
     976          28 :       Reg = MRI.getLLVMRegNum(Inst.getRegister(), true);
     977          56 :       if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
     978          46 :         RegOffsets[Reg] = Inst.getOffset();
     979          10 :       else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
     980          10 :         RegOffsets[Reg] = Inst.getOffset();
     981           5 :         ++FloatRegCount;
     982             :       } else {
     983             :         DEBUG_WITH_TYPE("compact-unwind",
     984             :                         llvm::dbgs() << ".cfi_offset on unknown register="
     985             :                                      << Inst.getRegister() << "\n");
     986             :         return CU::UNWIND_ARM_MODE_DWARF;
     987             :       }
     988             :       break;
     989             :     case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc
     990             :       // Ignore
     991             :       break;
     992             :     default:
     993             :       // Directive not convertable to compact unwind, bail out.
     994             :       DEBUG_WITH_TYPE("compact-unwind",
     995             :                       llvm::dbgs()
     996             :                           << "CFI directive not compatiable with comact "
     997             :                              "unwind encoding, opcode=" << Inst.getOperation()
     998             :                           << "\n");
     999             :       return CU::UNWIND_ARM_MODE_DWARF;
    1000             :       break;
    1001             :     }
    1002             :   }
    1003             : 
    1004             :   // If no frame set up, return no unwind info.
    1005           7 :   if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0))
    1006             :     return 0;
    1007             : 
    1008             :   // Verify standard frame (lr/r7) was used.
    1009           7 :   if (CFARegister != ARM::R7) {
    1010             :     DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is "
    1011             :                                                    << CFARegister
    1012             :                                                    << " instead of r7\n");
    1013             :     return CU::UNWIND_ARM_MODE_DWARF;
    1014             :   }
    1015           7 :   int StackAdjust = CFARegisterOffset - 8;
    1016          14 :   if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) {
    1017             :     DEBUG_WITH_TYPE("compact-unwind",
    1018             :                     llvm::dbgs()
    1019             :                         << "LR not saved as standard frame, StackAdjust="
    1020             :                         << StackAdjust
    1021             :                         << ", CFARegisterOffset=" << CFARegisterOffset
    1022             :                         << ", lr save at offset=" << RegOffsets[14] << "\n");
    1023             :     return CU::UNWIND_ARM_MODE_DWARF;
    1024             :   }
    1025          14 :   if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) {
    1026             :     DEBUG_WITH_TYPE("compact-unwind",
    1027             :                     llvm::dbgs() << "r7 not saved as standard frame\n");
    1028             :     return CU::UNWIND_ARM_MODE_DWARF;
    1029             :   }
    1030             :   uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME;
    1031             : 
    1032             :   // If var-args are used, there may be a stack adjust required.
    1033           7 :   switch (StackAdjust) {
    1034             :   case 0:
    1035             :     break;
    1036           0 :   case 4:
    1037             :     CompactUnwindEncoding |= 0x00400000;
    1038           0 :     break;
    1039           0 :   case 8:
    1040             :     CompactUnwindEncoding |= 0x00800000;
    1041           0 :     break;
    1042           1 :   case 12:
    1043             :     CompactUnwindEncoding |= 0x00C00000;
    1044           1 :     break;
    1045             :   default:
    1046             :     DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs()
    1047             :                                           << ".cfi_def_cfa stack adjust ("
    1048             :                                           << StackAdjust << ") out of range\n");
    1049             :     return CU::UNWIND_ARM_MODE_DWARF;
    1050             :   }
    1051             : 
    1052             :   // If r6 is saved, it must be right below r7.
    1053             :   static struct {
    1054             :     unsigned Reg;
    1055             :     unsigned Encoding;
    1056             :   } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6},
    1057             :                    {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5},
    1058             :                    {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4},
    1059             :                    {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12},
    1060             :                    {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11},
    1061             :                    {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10},
    1062             :                    {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9},
    1063             :                    {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}};
    1064             : 
    1065             :   int CurOffset = -8 - StackAdjust;
    1066          90 :   for (auto CSReg : GPRCSRegs) {
    1067          43 :     auto Offset = RegOffsets.find(CSReg.Reg);
    1068          43 :     if (Offset == RegOffsets.end())
    1069          34 :       continue;
    1070             : 
    1071           9 :     int RegOffset = Offset->second;
    1072           9 :     if (RegOffset != CurOffset - 4) {
    1073             :       DEBUG_WITH_TYPE("compact-unwind",
    1074             :                       llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at "
    1075             :                                    << RegOffset << " but only supported at "
    1076             :                                    << CurOffset << "\n");
    1077           1 :       return CU::UNWIND_ARM_MODE_DWARF;
    1078             :     }
    1079           8 :     CompactUnwindEncoding |= CSReg.Encoding;
    1080             :     CurOffset -= 4;
    1081             :   }
    1082             : 
    1083             :   // If no floats saved, we are done.
    1084           5 :   if (FloatRegCount == 0)
    1085             :     return CompactUnwindEncoding;
    1086             : 
    1087             :   // Switch mode to include D register saving.
    1088           2 :   CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK;
    1089           2 :   CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D;
    1090             : 
    1091             :   // FIXME: supporting more than 4 saved D-registers compactly would be trivial,
    1092             :   // but needs coordination with the linker and libunwind.
    1093           2 :   if (FloatRegCount > 4) {
    1094             :     DEBUG_WITH_TYPE("compact-unwind",
    1095             :                     llvm::dbgs() << "unsupported number of D registers saved ("
    1096             :                                  << FloatRegCount << ")\n");
    1097             :       return CU::UNWIND_ARM_MODE_DWARF;
    1098             :   }
    1099             : 
    1100             :   // Floating point registers must either be saved sequentially, or we defer to
    1101             :   // DWARF. No gaps allowed here so check that each saved d-register is
    1102             :   // precisely where it should be.
    1103             :   static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 };
    1104           7 :   for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) {
    1105           5 :     auto Offset = RegOffsets.find(FPRCSRegs[Idx]);
    1106           5 :     if (Offset == RegOffsets.end()) {
    1107             :       DEBUG_WITH_TYPE("compact-unwind",
    1108             :                       llvm::dbgs() << FloatRegCount << " D-regs saved, but "
    1109             :                                    << MRI.getName(FPRCSRegs[Idx])
    1110             :                                    << " not saved\n");
    1111           0 :       return CU::UNWIND_ARM_MODE_DWARF;
    1112           5 :     } else if (Offset->second != CurOffset - 8) {
    1113             :       DEBUG_WITH_TYPE("compact-unwind",
    1114             :                       llvm::dbgs() << FloatRegCount << " D-regs saved, but "
    1115             :                                    << MRI.getName(FPRCSRegs[Idx])
    1116             :                                    << " saved at " << Offset->second
    1117             :                                    << ", expected at " << CurOffset - 8
    1118             :                                    << "\n");
    1119             :       return CU::UNWIND_ARM_MODE_DWARF;
    1120             :     }
    1121             :     CurOffset -= 8;
    1122             :   }
    1123             : 
    1124           2 :   return CompactUnwindEncoding | ((FloatRegCount - 1) << 8);
    1125             : }
    1126             : 
    1127             : static MachO::CPUSubTypeARM getMachOSubTypeFromArch(StringRef Arch) {
    1128         852 :   ARM::ArchKind AK = ARM::parseArch(Arch);
    1129         852 :   switch (AK) {
    1130             :   default:
    1131             :     return MachO::CPU_SUBTYPE_ARM_V7;
    1132             :   case ARM::ArchKind::ARMV4T:
    1133             :     return MachO::CPU_SUBTYPE_ARM_V4T;
    1134             :   case ARM::ArchKind::ARMV5T:
    1135             :   case ARM::ArchKind::ARMV5TE:
    1136             :   case ARM::ArchKind::ARMV5TEJ:
    1137             :     return MachO::CPU_SUBTYPE_ARM_V5;
    1138             :   case ARM::ArchKind::ARMV6:
    1139             :   case ARM::ArchKind::ARMV6K:
    1140             :     return MachO::CPU_SUBTYPE_ARM_V6;
    1141             :   case ARM::ArchKind::ARMV7A:
    1142             :     return MachO::CPU_SUBTYPE_ARM_V7;
    1143             :   case ARM::ArchKind::ARMV7S:
    1144             :     return MachO::CPU_SUBTYPE_ARM_V7S;
    1145             :   case ARM::ArchKind::ARMV7K:
    1146             :     return MachO::CPU_SUBTYPE_ARM_V7K;
    1147             :   case ARM::ArchKind::ARMV6M:
    1148             :     return MachO::CPU_SUBTYPE_ARM_V6M;
    1149             :   case ARM::ArchKind::ARMV7M:
    1150             :     return MachO::CPU_SUBTYPE_ARM_V7M;
    1151             :   case ARM::ArchKind::ARMV7EM:
    1152             :     return MachO::CPU_SUBTYPE_ARM_V7EM;
    1153             :   }
    1154             : }
    1155             : 
    1156        3395 : MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
    1157             :                                         const MCSubtargetInfo &STI,
    1158             :                                         const MCRegisterInfo &MRI,
    1159             :                                         const MCTargetOptions &Options,
    1160             :                                         bool isLittle) {
    1161             :   const Triple &TheTriple = STI.getTargetTriple();
    1162        3395 :   switch (TheTriple.getObjectFormat()) {
    1163           0 :   default:
    1164           0 :     llvm_unreachable("unsupported object format");
    1165         852 :   case Triple::MachO: {
    1166         852 :     MachO::CPUSubTypeARM CS = getMachOSubTypeFromArch(TheTriple.getArchName());
    1167        1704 :     return new ARMAsmBackendDarwin(T, STI, MRI, CS);
    1168             :   }
    1169          84 :   case Triple::COFF:
    1170             :     assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
    1171         168 :     return new ARMAsmBackendWinCOFF(T, STI);
    1172        2459 :   case Triple::ELF:
    1173             :     assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
    1174        2459 :     uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
    1175        4918 :     return new ARMAsmBackendELF(T, STI, OSABI, isLittle);
    1176             :   }
    1177             : }
    1178             : 
    1179        1917 : MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
    1180             :                                           const MCSubtargetInfo &STI,
    1181             :                                           const MCRegisterInfo &MRI,
    1182             :                                           const MCTargetOptions &Options) {
    1183        1917 :   return createARMAsmBackend(T, STI, MRI, Options, true);
    1184             : }
    1185             : 
    1186          36 : MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
    1187             :                                           const MCSubtargetInfo &STI,
    1188             :                                           const MCRegisterInfo &MRI,
    1189             :                                           const MCTargetOptions &Options) {
    1190          36 :   return createARMAsmBackend(T, STI, MRI, Options, false);
    1191             : }
    1192             : 
    1193        1426 : MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
    1194             :                                             const MCSubtargetInfo &STI,
    1195             :                                             const MCRegisterInfo &MRI,
    1196             :                                             const MCTargetOptions &Options) {
    1197        1426 :   return createARMAsmBackend(T, STI, MRI, Options, true);
    1198             : }
    1199             : 
    1200          16 : MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
    1201             :                                             const MCSubtargetInfo &STI,
    1202             :                                             const MCRegisterInfo &MRI,
    1203             :                                             const MCTargetOptions &Options) {
    1204          16 :   return createARMAsmBackend(T, STI, MRI, Options, false);
    1205             : }

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