LCOV - code coverage report
Current view: top level - lib/Target/ARM/MCTargetDesc - ARMBaseInfo.h (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 28 45 62.2 %
Date: 2017-09-14 15:23:50 Functions: 2 2 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains small standalone helper functions and enum definitions for
      11             : // the ARM target useful for the compiler back-end and the MC libraries.
      12             : // As such, it deliberately does not include references to LLVM core
      13             : // code gen types, passes, etc..
      14             : //
      15             : //===----------------------------------------------------------------------===//
      16             : 
      17             : #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
      18             : #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMBASEINFO_H
      19             : 
      20             : #include "ARMMCTargetDesc.h"
      21             : #include "llvm/Support/ErrorHandling.h"
      22             : #include "Utils/ARMBaseInfo.h"
      23             : 
      24             : namespace llvm {
      25             : 
      26             : namespace ARM_PROC {
      27             :   enum IMod {
      28             :     IE = 2,
      29             :     ID = 3
      30             :   };
      31             : 
      32             :   enum IFlags {
      33             :     F = 1,
      34             :     I = 2,
      35             :     A = 4
      36             :   };
      37             : 
      38             :   inline static const char *IFlagsToString(unsigned val) {
      39          63 :     switch (val) {
      40           0 :     default: llvm_unreachable("Unknown iflags operand");
      41             :     case F: return "f";
      42          19 :     case I: return "i";
      43          14 :     case A: return "a";
      44             :     }
      45             :   }
      46             : 
      47             :   inline static const char *IModToString(unsigned val) {
      48          48 :     switch (val) {
      49           0 :     default: llvm_unreachable("Unknown imod operand");
      50             :     case IE: return "ie";
      51          16 :     case ID: return "id";
      52             :     }
      53             :   }
      54             : }
      55             : 
      56             : namespace ARM_MB {
      57             :   // The Memory Barrier Option constants map directly to the 4-bit encoding of
      58             :   // the option field for memory barrier operations.
      59             :   enum MemBOpt {
      60             :     RESERVED_0 = 0,
      61             :     OSHLD = 1,
      62             :     OSHST = 2,
      63             :     OSH   = 3,
      64             :     RESERVED_4 = 4,
      65             :     NSHLD = 5,
      66             :     NSHST = 6,
      67             :     NSH   = 7,
      68             :     RESERVED_8 = 8,
      69             :     ISHLD = 9,
      70             :     ISHST = 10,
      71             :     ISH   = 11,
      72             :     RESERVED_12 = 12,
      73             :     LD = 13,
      74             :     ST    = 14,
      75             :     SY    = 15
      76             :   };
      77             : 
      78         644 :   inline static const char *MemBOptToString(unsigned val, bool HasV8) {
      79         644 :     switch (val) {
      80           0 :     default: llvm_unreachable("Unknown memory operation");
      81             :     case SY:    return "sy";
      82          21 :     case ST:    return "st";
      83          19 :     case LD: return HasV8 ? "ld" : "#0xd";
      84          12 :     case RESERVED_12: return "#0xc";
      85         243 :     case ISH:   return "ish";
      86          33 :     case ISHST: return "ishst";
      87          20 :     case ISHLD: return HasV8 ?  "ishld" : "#0x9";
      88          14 :     case RESERVED_8: return "#0x8";
      89          34 :     case NSH:   return "nsh";
      90          29 :     case NSHST: return "nshst";
      91          18 :     case NSHLD: return HasV8 ? "nshld" : "#0x5";
      92          12 :     case RESERVED_4: return "#0x4";
      93          23 :     case OSH:   return "osh";
      94          22 :     case OSHST: return "oshst";
      95          18 :     case OSHLD: return HasV8 ? "oshld" : "#0x1";
      96          12 :     case RESERVED_0: return "#0x0";
      97             :     }
      98             :   }
      99             : } // namespace ARM_MB
     100             : 
     101             : namespace ARM_ISB {
     102             :   enum InstSyncBOpt {
     103             :     RESERVED_0 = 0,
     104             :     RESERVED_1 = 1,
     105             :     RESERVED_2 = 2,
     106             :     RESERVED_3 = 3,
     107             :     RESERVED_4 = 4,
     108             :     RESERVED_5 = 5,
     109             :     RESERVED_6 = 6,
     110             :     RESERVED_7 = 7,
     111             :     RESERVED_8 = 8,
     112             :     RESERVED_9 = 9,
     113             :     RESERVED_10 = 10,
     114             :     RESERVED_11 = 11,
     115             :     RESERVED_12 = 12,
     116             :     RESERVED_13 = 13,
     117             :     RESERVED_14 = 14,
     118             :     SY = 15
     119             :   };
     120             : 
     121          35 :   inline static const char *InstSyncBOptToString(unsigned val) {
     122          35 :     switch (val) {
     123           0 :     default:
     124           0 :       llvm_unreachable("Unknown memory operation");
     125             :       case RESERVED_0:  return "#0x0";
     126           4 :       case RESERVED_1:  return "#0x1";
     127           0 :       case RESERVED_2:  return "#0x2";
     128           0 :       case RESERVED_3:  return "#0x3";
     129           0 :       case RESERVED_4:  return "#0x4";
     130           0 :       case RESERVED_5:  return "#0x5";
     131           0 :       case RESERVED_6:  return "#0x6";
     132           0 :       case RESERVED_7:  return "#0x7";
     133           0 :       case RESERVED_8:  return "#0x8";
     134           0 :       case RESERVED_9:  return "#0x9";
     135           2 :       case RESERVED_10: return "#0xa";
     136           0 :       case RESERVED_11: return "#0xb";
     137           0 :       case RESERVED_12: return "#0xc";
     138           0 :       case RESERVED_13: return "#0xd";
     139           0 :       case RESERVED_14: return "#0xe";
     140          29 :       case SY:          return "sy";
     141             :     }
     142             :   }
     143             : } // namespace ARM_ISB
     144             : 
     145             : /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
     146             : ///
     147             : static inline bool isARMLowRegister(unsigned Reg) {
     148             :   using namespace ARM;
     149       27248 :   switch (Reg) {
     150             :   case R0:  case R1:  case R2:  case R3:
     151             :   case R4:  case R5:  case R6:  case R7:
     152             :     return true;
     153             :   default:
     154             :     return false;
     155             :   }
     156             : }
     157             : 
     158             : /// ARMII - This namespace holds all of the target specific flags that
     159             : /// instruction info tracks.
     160             : ///
     161             : namespace ARMII {
     162             : 
     163             :   /// ARM Index Modes
     164             :   enum IndexMode {
     165             :     IndexModeNone  = 0,
     166             :     IndexModePre   = 1,
     167             :     IndexModePost  = 2,
     168             :     IndexModeUpd   = 3
     169             :   };
     170             : 
     171             :   /// ARM Addressing Modes
     172             :   enum AddrMode {
     173             :     AddrModeNone    = 0,
     174             :     AddrMode1       = 1,
     175             :     AddrMode2       = 2,
     176             :     AddrMode3       = 3,
     177             :     AddrMode4       = 4,
     178             :     AddrMode5       = 5,
     179             :     AddrMode6       = 6,
     180             :     AddrModeT1_1    = 7,
     181             :     AddrModeT1_2    = 8,
     182             :     AddrModeT1_4    = 9,
     183             :     AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
     184             :     AddrModeT2_i12  = 11,
     185             :     AddrModeT2_i8   = 12,
     186             :     AddrModeT2_so   = 13,
     187             :     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
     188             :     AddrModeT2_i8s4 = 15, // i8 * 4
     189             :     AddrMode_i12    = 16
     190             :   };
     191             : 
     192             :   inline static const char *AddrModeToString(AddrMode addrmode) {
     193             :     switch (addrmode) {
     194             :     case AddrModeNone:    return "AddrModeNone";
     195             :     case AddrMode1:       return "AddrMode1";
     196             :     case AddrMode2:       return "AddrMode2";
     197             :     case AddrMode3:       return "AddrMode3";
     198             :     case AddrMode4:       return "AddrMode4";
     199             :     case AddrMode5:       return "AddrMode5";
     200             :     case AddrMode6:       return "AddrMode6";
     201             :     case AddrModeT1_1:    return "AddrModeT1_1";
     202             :     case AddrModeT1_2:    return "AddrModeT1_2";
     203             :     case AddrModeT1_4:    return "AddrModeT1_4";
     204             :     case AddrModeT1_s:    return "AddrModeT1_s";
     205             :     case AddrModeT2_i12:  return "AddrModeT2_i12";
     206             :     case AddrModeT2_i8:   return "AddrModeT2_i8";
     207             :     case AddrModeT2_so:   return "AddrModeT2_so";
     208             :     case AddrModeT2_pc:   return "AddrModeT2_pc";
     209             :     case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
     210             :     case AddrMode_i12:    return "AddrMode_i12";
     211             :     }
     212             :   }
     213             : 
     214             :   /// Target Operand Flag enum.
     215             :   enum TOF {
     216             :     //===------------------------------------------------------------------===//
     217             :     // ARM Specific MachineOperand flags.
     218             : 
     219             :     MO_NO_FLAG = 0,
     220             : 
     221             :     /// MO_LO16 - On a symbol operand, this represents a relocation containing
     222             :     /// lower 16 bit of the address. Used only via movw instruction.
     223             :     MO_LO16 = 0x1,
     224             : 
     225             :     /// MO_HI16 - On a symbol operand, this represents a relocation containing
     226             :     /// higher 16 bit of the address. Used only via movt instruction.
     227             :     MO_HI16 = 0x2,
     228             : 
     229             :     /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
     230             :     /// just that part of the flag set.
     231             :     MO_OPTION_MASK = 0x0f,
     232             : 
     233             :     /// MO_SBREL - On a symbol operand, this represents a static base relative
     234             :     /// relocation. Used in movw and movt instructions.
     235             :     MO_SBREL = 0x10,
     236             : 
     237             :     /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
     238             :     /// to the symbol is for an import stub.  This is used for DLL import
     239             :     /// storage class indication on Windows.
     240             :     MO_DLLIMPORT = 0x20,
     241             : 
     242             :     /// MO_SECREL - On a symbol operand this indicates that the immediate is
     243             :     /// the offset from beginning of section.
     244             :     ///
     245             :     /// This is the TLS offset for the COFF/Windows TLS mechanism.
     246             :     MO_SECREL = 0x40,
     247             : 
     248             :     /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
     249             :     /// represents a symbol which, if indirect, will get special Darwin mangling
     250             :     /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
     251             :     /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
     252             :     /// example).
     253             :     MO_NONLAZY = 0x80,
     254             : 
     255             :     // It's undefined behaviour if an enum overflows the range between its
     256             :     // smallest and largest values, but since these are |ed together, it can
     257             :     // happen. Put a sentinel in (values of this enum are stored as "unsigned
     258             :     // char").
     259             :     MO_UNUSED_MAXIMUM = 0xff
     260             :   };
     261             : 
     262             :   enum {
     263             :     //===------------------------------------------------------------------===//
     264             :     // Instruction Flags.
     265             : 
     266             :     //===------------------------------------------------------------------===//
     267             :     // This four-bit field describes the addressing mode used.
     268             :     AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
     269             : 
     270             :     // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
     271             :     // and store ops only.  Generic "updating" flag is used for ld/st multiple.
     272             :     // The index mode enums are declared in ARMBaseInfo.h
     273             :     IndexModeShift = 5,
     274             :     IndexModeMask  = 3 << IndexModeShift,
     275             : 
     276             :     //===------------------------------------------------------------------===//
     277             :     // Instruction encoding formats.
     278             :     //
     279             :     FormShift     = 7,
     280             :     FormMask      = 0x3f << FormShift,
     281             : 
     282             :     // Pseudo instructions
     283             :     Pseudo        = 0  << FormShift,
     284             : 
     285             :     // Multiply instructions
     286             :     MulFrm        = 1  << FormShift,
     287             : 
     288             :     // Branch instructions
     289             :     BrFrm         = 2  << FormShift,
     290             :     BrMiscFrm     = 3  << FormShift,
     291             : 
     292             :     // Data Processing instructions
     293             :     DPFrm         = 4  << FormShift,
     294             :     DPSoRegFrm    = 5  << FormShift,
     295             : 
     296             :     // Load and Store
     297             :     LdFrm         = 6  << FormShift,
     298             :     StFrm         = 7  << FormShift,
     299             :     LdMiscFrm     = 8  << FormShift,
     300             :     StMiscFrm     = 9  << FormShift,
     301             :     LdStMulFrm    = 10 << FormShift,
     302             : 
     303             :     LdStExFrm     = 11 << FormShift,
     304             : 
     305             :     // Miscellaneous arithmetic instructions
     306             :     ArithMiscFrm  = 12 << FormShift,
     307             :     SatFrm        = 13 << FormShift,
     308             : 
     309             :     // Extend instructions
     310             :     ExtFrm        = 14 << FormShift,
     311             : 
     312             :     // VFP formats
     313             :     VFPUnaryFrm   = 15 << FormShift,
     314             :     VFPBinaryFrm  = 16 << FormShift,
     315             :     VFPConv1Frm   = 17 << FormShift,
     316             :     VFPConv2Frm   = 18 << FormShift,
     317             :     VFPConv3Frm   = 19 << FormShift,
     318             :     VFPConv4Frm   = 20 << FormShift,
     319             :     VFPConv5Frm   = 21 << FormShift,
     320             :     VFPLdStFrm    = 22 << FormShift,
     321             :     VFPLdStMulFrm = 23 << FormShift,
     322             :     VFPMiscFrm    = 24 << FormShift,
     323             : 
     324             :     // Thumb format
     325             :     ThumbFrm      = 25 << FormShift,
     326             : 
     327             :     // Miscelleaneous format
     328             :     MiscFrm       = 26 << FormShift,
     329             : 
     330             :     // NEON formats
     331             :     NGetLnFrm     = 27 << FormShift,
     332             :     NSetLnFrm     = 28 << FormShift,
     333             :     NDupFrm       = 29 << FormShift,
     334             :     NLdStFrm      = 30 << FormShift,
     335             :     N1RegModImmFrm= 31 << FormShift,
     336             :     N2RegFrm      = 32 << FormShift,
     337             :     NVCVTFrm      = 33 << FormShift,
     338             :     NVDupLnFrm    = 34 << FormShift,
     339             :     N2RegVShLFrm  = 35 << FormShift,
     340             :     N2RegVShRFrm  = 36 << FormShift,
     341             :     N3RegFrm      = 37 << FormShift,
     342             :     N3RegVShFrm   = 38 << FormShift,
     343             :     NVExtFrm      = 39 << FormShift,
     344             :     NVMulSLFrm    = 40 << FormShift,
     345             :     NVTBLFrm      = 41 << FormShift,
     346             : 
     347             :     //===------------------------------------------------------------------===//
     348             :     // Misc flags.
     349             : 
     350             :     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
     351             :     // it doesn't have a Rn operand.
     352             :     UnaryDP       = 1 << 13,
     353             : 
     354             :     // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
     355             :     // a 16-bit Thumb instruction if certain conditions are met.
     356             :     Xform16Bit    = 1 << 14,
     357             : 
     358             :     // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
     359             :     // instruction. Used by the parser to determine whether to require the 'S'
     360             :     // suffix on the mnemonic (when not in an IT block) or preclude it (when
     361             :     // in an IT block).
     362             :     ThumbArithFlagSetting = 1 << 18,
     363             : 
     364             :     //===------------------------------------------------------------------===//
     365             :     // Code domain.
     366             :     DomainShift   = 15,
     367             :     DomainMask    = 7 << DomainShift,
     368             :     DomainGeneral = 0 << DomainShift,
     369             :     DomainVFP     = 1 << DomainShift,
     370             :     DomainNEON    = 2 << DomainShift,
     371             :     DomainNEONA8  = 4 << DomainShift,
     372             : 
     373             :     //===------------------------------------------------------------------===//
     374             :     // Field shifts - such shifts are used to set field while generating
     375             :     // machine instructions.
     376             :     //
     377             :     // FIXME: This list will need adjusting/fixing as the MC code emitter
     378             :     // takes shape and the ARMCodeEmitter.cpp bits go away.
     379             :     ShiftTypeShift = 4,
     380             : 
     381             :     M_BitShift     = 5,
     382             :     ShiftImmShift  = 5,
     383             :     ShiftShift     = 7,
     384             :     N_BitShift     = 7,
     385             :     ImmHiShift     = 8,
     386             :     SoRotImmShift  = 8,
     387             :     RegRsShift     = 8,
     388             :     ExtRotImmShift = 10,
     389             :     RegRdLoShift   = 12,
     390             :     RegRdShift     = 12,
     391             :     RegRdHiShift   = 16,
     392             :     RegRnShift     = 16,
     393             :     S_BitShift     = 20,
     394             :     W_BitShift     = 21,
     395             :     AM3_I_BitShift = 22,
     396             :     D_BitShift     = 22,
     397             :     U_BitShift     = 23,
     398             :     P_BitShift     = 24,
     399             :     I_BitShift     = 25,
     400             :     CondShift      = 28
     401             :   };
     402             : 
     403             : } // end namespace ARMII
     404             : 
     405             : } // end namespace llvm;
     406             : 
     407             : #endif

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