LCOV - code coverage report
Current view: top level - lib/Target/ARM/MCTargetDesc - ARMWinCOFFObjectWriter.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 29 29 100.0 %
Date: 2017-09-14 15:23:50 Functions: 4 5 80.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- ARMWinCOFFObjectWriter.cpp - ARM Windows COFF Object Writer -- C++ -==//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : 
      10             : #include "MCTargetDesc/ARMFixupKinds.h"
      11             : #include "llvm/ADT/Twine.h"
      12             : #include "llvm/BinaryFormat/COFF.h"
      13             : #include "llvm/MC/MCAsmBackend.h"
      14             : #include "llvm/MC/MCExpr.h"
      15             : #include "llvm/MC/MCFixup.h"
      16             : #include "llvm/MC/MCFixupKindInfo.h"
      17             : #include "llvm/MC/MCValue.h"
      18             : #include "llvm/MC/MCWinCOFFObjectWriter.h"
      19             : #include "llvm/Support/ErrorHandling.h"
      20             : #include "llvm/Support/raw_ostream.h"
      21             : #include <cassert>
      22             : 
      23             : using namespace llvm;
      24             : 
      25             : namespace {
      26             : 
      27             : class ARMWinCOFFObjectWriter : public MCWinCOFFObjectTargetWriter {
      28             : public:
      29             :   ARMWinCOFFObjectWriter(bool Is64Bit)
      30          21 :     : MCWinCOFFObjectTargetWriter(COFF::IMAGE_FILE_MACHINE_ARMNT) {
      31             :     assert(!Is64Bit && "AArch64 support not yet implemented");
      32             :   }
      33             : 
      34          20 :   ~ARMWinCOFFObjectWriter() override = default;
      35             : 
      36             :   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
      37             :                         const MCFixup &Fixup, bool IsCrossSection,
      38             :                         const MCAsmBackend &MAB) const override;
      39             : 
      40             :   bool recordRelocation(const MCFixup &) const override;
      41             : };
      42             : 
      43             : } // end anonymous namespace
      44             : 
      45          59 : unsigned ARMWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
      46             :                                               const MCValue &Target,
      47             :                                               const MCFixup &Fixup,
      48             :                                               bool IsCrossSection,
      49             :                                               const MCAsmBackend &MAB) const {
      50             :   assert(getMachine() == COFF::IMAGE_FILE_MACHINE_ARMNT &&
      51             :          "AArch64 support not yet implemented");
      52             : 
      53             :   MCSymbolRefExpr::VariantKind Modifier =
      54         118 :     Target.isAbsolute() ? MCSymbolRefExpr::VK_None : Target.getSymA()->getKind();
      55             : 
      56          59 :   switch (static_cast<unsigned>(Fixup.getKind())) {
      57           1 :   default: {
      58           1 :     const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind());
      59           4 :     report_fatal_error(Twine("unsupported relocation type: ") + Info.Name);
      60             :   }
      61          14 :   case FK_Data_4:
      62          14 :     switch (Modifier) {
      63             :     case MCSymbolRefExpr::VK_COFF_IMGREL32:
      64             :       return COFF::IMAGE_REL_ARM_ADDR32NB;
      65           3 :     case MCSymbolRefExpr::VK_SECREL:
      66           3 :       return COFF::IMAGE_REL_ARM_SECREL;
      67           8 :     default:
      68           8 :       return COFF::IMAGE_REL_ARM_ADDR32;
      69             :     }
      70             :   case FK_SecRel_2:
      71             :     return COFF::IMAGE_REL_ARM_SECTION;
      72          11 :   case FK_SecRel_4:
      73          11 :     return COFF::IMAGE_REL_ARM_SECREL;
      74           2 :   case ARM::fixup_t2_condbranch:
      75           2 :     return COFF::IMAGE_REL_ARM_BRANCH20T;
      76           2 :   case ARM::fixup_t2_uncondbranch:
      77           2 :     return COFF::IMAGE_REL_ARM_BRANCH24T;
      78           4 :   case ARM::fixup_arm_thumb_bl:
      79             :   case ARM::fixup_arm_thumb_blx:
      80           4 :     return COFF::IMAGE_REL_ARM_BLX23T;
      81          22 :   case ARM::fixup_t2_movw_lo16:
      82             :   case ARM::fixup_t2_movt_hi16:
      83          22 :     return COFF::IMAGE_REL_ARM_MOV32T;
      84             :   }
      85             : }
      86             : 
      87          58 : bool ARMWinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {
      88          58 :   return static_cast<unsigned>(Fixup.getKind()) != ARM::fixup_t2_movt_hi16;
      89             : }
      90             : 
      91             : namespace llvm {
      92             : 
      93          21 : MCObjectWriter *createARMWinCOFFObjectWriter(raw_pwrite_stream &OS,
      94             :                                              bool Is64Bit) {
      95          42 :   MCWinCOFFObjectTargetWriter *MOTW = new ARMWinCOFFObjectWriter(Is64Bit);
      96          21 :   return createWinCOFFObjectWriter(MOTW, OS);
      97             : }
      98             : 
      99             : } // end namespace llvm

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