LCOV - code coverage report
Current view: top level - lib/Target/ARM - Thumb1FrameLowering.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 373 403 92.6 %
Date: 2018-07-13 00:08:38 Functions: 12 12 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===- Thumb1FrameLowering.cpp - Thumb1 Frame Information -----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the Thumb1 implementation of TargetFrameLowering class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "Thumb1FrameLowering.h"
      15             : #include "ARMBaseInstrInfo.h"
      16             : #include "ARMBaseRegisterInfo.h"
      17             : #include "ARMMachineFunctionInfo.h"
      18             : #include "ARMSubtarget.h"
      19             : #include "Thumb1InstrInfo.h"
      20             : #include "ThumbRegisterInfo.h"
      21             : #include "Utils/ARMBaseInfo.h"
      22             : #include "llvm/ADT/BitVector.h"
      23             : #include "llvm/ADT/STLExtras.h"
      24             : #include "llvm/ADT/SmallVector.h"
      25             : #include "llvm/CodeGen/LivePhysRegs.h"
      26             : #include "llvm/CodeGen/MachineBasicBlock.h"
      27             : #include "llvm/CodeGen/MachineFrameInfo.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineInstr.h"
      30             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      31             : #include "llvm/CodeGen/MachineModuleInfo.h"
      32             : #include "llvm/CodeGen/MachineOperand.h"
      33             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      34             : #include "llvm/CodeGen/TargetInstrInfo.h"
      35             : #include "llvm/CodeGen/TargetOpcodes.h"
      36             : #include "llvm/CodeGen/TargetSubtargetInfo.h"
      37             : #include "llvm/IR/DebugLoc.h"
      38             : #include "llvm/MC/MCContext.h"
      39             : #include "llvm/MC/MCDwarf.h"
      40             : #include "llvm/MC/MCRegisterInfo.h"
      41             : #include "llvm/Support/Compiler.h"
      42             : #include "llvm/Support/ErrorHandling.h"
      43             : #include "llvm/Support/MathExtras.h"
      44             : #include <bitset>
      45             : #include <cassert>
      46             : #include <iterator>
      47             : #include <vector>
      48             : 
      49             : using namespace llvm;
      50             : 
      51         473 : Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
      52         473 :     : ARMFrameLowering(sti) {}
      53             : 
      54        8844 : bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
      55        8844 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
      56             :   unsigned CFSize = MFI.getMaxCallFrameSize();
      57             :   // It's not always a good idea to include the call frame as part of the
      58             :   // stack frame. ARM (especially Thumb) has small immediate offset to
      59             :   // address the stack frame. So a large call frame can cause poor codegen
      60             :   // and may even makes it impossible to scavenge a register.
      61        8844 :   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
      62             :     return false;
      63             : 
      64        8643 :   return !MFI.hasVarSizedObjects();
      65             : }
      66             : 
      67             : static void emitSPUpdate(MachineBasicBlock &MBB,
      68             :                          MachineBasicBlock::iterator &MBBI,
      69             :                          const TargetInstrInfo &TII, const DebugLoc &dl,
      70             :                          const ThumbRegisterInfo &MRI, int NumBytes,
      71             :                          unsigned MIFlags = MachineInstr::NoFlags) {
      72        1197 :   emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
      73             :                             MRI, MIFlags);
      74             : }
      75             : 
      76        1702 : MachineBasicBlock::iterator Thumb1FrameLowering::
      77             : eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
      78             :                               MachineBasicBlock::iterator I) const {
      79             :   const Thumb1InstrInfo &TII =
      80        1702 :       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
      81             :   const ThumbRegisterInfo *RegInfo =
      82        1702 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
      83        1702 :   if (!hasReservedCallFrame(MF)) {
      84             :     // If we have alloca, convert as follows:
      85             :     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
      86             :     // ADJCALLSTACKUP   -> add, sp, sp, amount
      87             :     MachineInstr &Old = *I;
      88             :     DebugLoc dl = Old.getDebugLoc();
      89         268 :     unsigned Amount = TII.getFrameSize(Old);
      90         134 :     if (Amount != 0) {
      91             :       // We need to keep the stack aligned properly.  To do this, we round the
      92             :       // amount of space needed for the outgoing arguments up to the next
      93             :       // alignment boundary.
      94          44 :       Amount = alignTo(Amount, getStackAlignment());
      95             : 
      96             :       // Replace the pseudo instruction with a new instruction...
      97          22 :       unsigned Opc = Old.getOpcode();
      98          22 :       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
      99          11 :         emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
     100             :       } else {
     101             :         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
     102          11 :         emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
     103             :       }
     104             :     }
     105             :   }
     106        1702 :   return MBB.erase(I);
     107             : }
     108             : 
     109        1115 : void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
     110             :                                        MachineBasicBlock &MBB) const {
     111        1115 :   MachineBasicBlock::iterator MBBI = MBB.begin();
     112        1115 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     113        1115 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     114        1115 :   MachineModuleInfo &MMI = MF.getMMI();
     115        1115 :   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
     116             :   const ThumbRegisterInfo *RegInfo =
     117        1115 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
     118             :   const Thumb1InstrInfo &TII =
     119        1115 :       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
     120             : 
     121        1115 :   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
     122        1115 :   unsigned NumBytes = MFI.getStackSize();
     123             :   assert(NumBytes >= ArgRegsSaveSize &&
     124             :          "ArgRegsSaveSize is included in NumBytes");
     125             :   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
     126             : 
     127             :   // Debug location must be unknown since the first debug location is used
     128             :   // to determine the end of the prologue.
     129        1115 :   DebugLoc dl;
     130             :   
     131        1115 :   unsigned FramePtr = RegInfo->getFrameRegister(MF);
     132        1115 :   unsigned BasePtr = RegInfo->getBaseRegister();
     133             :   int CFAOffset = 0;
     134             : 
     135             :   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
     136        1115 :   NumBytes = (NumBytes + 3) & ~3;
     137        1115 :   MFI.setStackSize(NumBytes);
     138             : 
     139             :   // Determine the sizes of each callee-save spill areas and record which frame
     140             :   // belongs to which callee-save spill areas.
     141             :   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
     142             :   int FramePtrSpillFI = 0;
     143             : 
     144        1115 :   if (ArgRegsSaveSize) {
     145          17 :     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
     146             :                  MachineInstr::FrameSetup);
     147             :     CFAOffset -= ArgRegsSaveSize;
     148             :     unsigned CFIIndex = MF.addFrameInst(
     149          17 :         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     150          51 :     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     151             :         .addCFIIndex(CFIIndex)
     152             :         .setMIFlags(MachineInstr::FrameSetup);
     153             :   }
     154             : 
     155        1115 :   if (!AFI->hasStackFrame()) {
     156         490 :     if (NumBytes - ArgRegsSaveSize != 0) {
     157          28 :       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
     158             :                    MachineInstr::FrameSetup);
     159          28 :       CFAOffset -= NumBytes - ArgRegsSaveSize;
     160             :       unsigned CFIIndex = MF.addFrameInst(
     161          28 :           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     162          84 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     163             :           .addCFIIndex(CFIIndex)
     164             :           .setMIFlags(MachineInstr::FrameSetup);
     165             :     }
     166             :     return;
     167             :   }
     168             : 
     169        3010 :   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     170        3520 :     unsigned Reg = CSI[i].getReg();
     171        1760 :     int FI = CSI[i].getFrameIdx();
     172        1760 :     switch (Reg) {
     173          54 :     case ARM::R8:
     174             :     case ARM::R9:
     175             :     case ARM::R10:
     176             :     case ARM::R11:
     177          54 :       if (STI.splitFramePushPop(MF)) {
     178          54 :         GPRCS2Size += 4;
     179          54 :         break;
     180             :       }
     181             :       LLVM_FALLTHROUGH;
     182             :     case ARM::R4:
     183             :     case ARM::R5:
     184             :     case ARM::R6:
     185             :     case ARM::R7:
     186             :     case ARM::LR:
     187        1706 :       if (Reg == FramePtr)
     188             :         FramePtrSpillFI = FI;
     189        1706 :       GPRCS1Size += 4;
     190        1706 :       break;
     191           0 :     default:
     192           0 :       DPRCSSize += 8;
     193             :     }
     194             :   }
     195             : 
     196        1250 :   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
     197             :     ++MBBI;
     198             :   }
     199             : 
     200             :   // Determine starting offsets of spill areas.
     201         625 :   unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
     202         625 :   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
     203         625 :   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
     204         625 :   bool HasFP = hasFP(MF);
     205         625 :   if (HasFP)
     206         157 :     AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
     207             :                                 NumBytes);
     208             :   AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
     209             :   AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
     210             :   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
     211             :   NumBytes = DPRCSOffset;
     212             : 
     213             :   int FramePtrOffsetInBlock = 0;
     214             :   unsigned adjustedGPRCS1Size = GPRCS1Size;
     215        1232 :   if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
     216         607 :       tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
     217           8 :     FramePtrOffsetInBlock = NumBytes;
     218           8 :     adjustedGPRCS1Size += NumBytes;
     219             :     NumBytes = 0;
     220             :   }
     221             : 
     222         625 :   if (adjustedGPRCS1Size) {
     223         623 :     CFAOffset -= adjustedGPRCS1Size;
     224             :     unsigned CFIIndex = MF.addFrameInst(
     225         623 :         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     226        1869 :     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     227             :         .addCFIIndex(CFIIndex)
     228             :         .setMIFlags(MachineInstr::FrameSetup);
     229             :   }
     230         625 :   for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
     231         625 :          E = CSI.end(); I != E; ++I) {
     232        1760 :     unsigned Reg = I->getReg();
     233        1760 :     int FI = I->getFrameIdx();
     234        1760 :     switch (Reg) {
     235          54 :     case ARM::R8:
     236             :     case ARM::R9:
     237             :     case ARM::R10:
     238             :     case ARM::R11:
     239             :     case ARM::R12:
     240          54 :       if (STI.splitFramePushPop(MF))
     241             :         break;
     242             :       LLVM_FALLTHROUGH;
     243             :     case ARM::R0:
     244             :     case ARM::R1:
     245             :     case ARM::R2:
     246             :     case ARM::R3:
     247             :     case ARM::R4:
     248             :     case ARM::R5:
     249             :     case ARM::R6:
     250             :     case ARM::R7:
     251             :     case ARM::LR:
     252        5118 :       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
     253        1706 :           nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
     254        5118 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     255             :           .addCFIIndex(CFIIndex)
     256             :           .setMIFlags(MachineInstr::FrameSetup);
     257        1706 :       break;
     258             :     }
     259             :   }
     260             : 
     261             :   // Adjust FP so it point to the stack slot that contains the previous FP.
     262         625 :   if (HasFP) {
     263         157 :     FramePtrOffsetInBlock +=
     264         157 :         MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
     265         471 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
     266         157 :         .addReg(ARM::SP)
     267         157 :         .addImm(FramePtrOffsetInBlock / 4)
     268             :         .setMIFlags(MachineInstr::FrameSetup)
     269         157 :         .add(predOps(ARMCC::AL));
     270         157 :     if(FramePtrOffsetInBlock) {
     271         100 :       CFAOffset += FramePtrOffsetInBlock;
     272         200 :       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
     273         100 :           nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
     274         300 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     275             :           .addCFIIndex(CFIIndex)
     276             :           .setMIFlags(MachineInstr::FrameSetup);
     277             :     } else {
     278             :       unsigned CFIIndex =
     279         114 :           MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
     280          57 :               nullptr, MRI->getDwarfRegNum(FramePtr, true)));
     281         171 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     282             :           .addCFIIndex(CFIIndex)
     283             :           .setMIFlags(MachineInstr::FrameSetup);
     284             :     }
     285         157 :     if (NumBytes > 508)
     286             :       // If offset is > 508 then sp cannot be adjusted in a single instruction,
     287             :       // try restoring from fp instead.
     288             :       AFI->setShouldRestoreSPFromFP(true);
     289             :   }
     290             : 
     291             :   // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
     292             :   // and tMOVr instructions. We don't need to add any call frame information
     293             :   // in-between these instructions, because they do not modify the high
     294             :   // registers.
     295             :   while (true) {
     296         644 :     MachineBasicBlock::iterator OldMBBI = MBBI;
     297             :     // Skip a run of tMOVr instructions
     298        1392 :     while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
     299             :       MBBI++;
     300        1924 :     if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
     301             :       MBBI++;
     302             :     } else {
     303             :       // We have reached an instruction which is not a push, so the previous
     304             :       // run of tMOVr instructions (which may have been empty) was not part of
     305             :       // the prologue. Reset MBBI back to the last PUSH of the prologue.
     306         625 :       MBBI = OldMBBI;
     307             :       break;
     308             :     }
     309             :   }
     310             : 
     311             :   // Emit call frame information for the callee-saved high registers.
     312        3010 :   for (auto &I : CSI) {
     313        1760 :     unsigned Reg = I.getReg();
     314        1760 :     int FI = I.getFrameIdx();
     315        1760 :     switch (Reg) {
     316             :     case ARM::R8:
     317             :     case ARM::R9:
     318             :     case ARM::R10:
     319             :     case ARM::R11:
     320             :     case ARM::R12: {
     321         162 :       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
     322          54 :           nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
     323         162 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     324             :           .addCFIIndex(CFIIndex)
     325             :           .setMIFlags(MachineInstr::FrameSetup);
     326          54 :       break;
     327             :     }
     328             :     default:
     329             :       break;
     330             :     }
     331             :   }
     332             : 
     333         625 :   if (NumBytes) {
     334             :     // Insert it after all the callee-save spills.
     335         311 :     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
     336             :                  MachineInstr::FrameSetup);
     337         311 :     if (!HasFP) {
     338         231 :       CFAOffset -= NumBytes;
     339             :       unsigned CFIIndex = MF.addFrameInst(
     340         231 :           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     341         693 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     342             :           .addCFIIndex(CFIIndex)
     343             :           .setMIFlags(MachineInstr::FrameSetup);
     344             :     }
     345             :   }
     346             : 
     347        1250 :   if (STI.isTargetELF() && HasFP)
     348         234 :     MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
     349         117 :                             AFI->getFramePtrSpillOffset());
     350             : 
     351             :   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
     352             :   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
     353             :   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
     354             : 
     355         625 :   if (RegInfo->needsStackRealignment(MF)) {
     356          36 :     const unsigned NrBitsToZero = countTrailingZeros(MFI.getMaxAlignment());
     357             :     // Emit the following sequence, using R4 as a temporary, since we cannot use
     358             :     // SP as a source or destination register for the shifts:
     359             :     // mov  r4, sp
     360             :     // lsrs r4, r4, #NrBitsToZero
     361             :     // lsls r4, r4, #NrBitsToZero
     362             :     // mov  sp, r4
     363         108 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
     364          36 :       .addReg(ARM::SP, RegState::Kill)
     365          36 :       .add(predOps(ARMCC::AL));
     366             : 
     367         108 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
     368             :       .addDef(ARM::CPSR)
     369          36 :       .addReg(ARM::R4, RegState::Kill)
     370          36 :       .addImm(NrBitsToZero)
     371          36 :       .add(predOps(ARMCC::AL));
     372             : 
     373         108 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
     374             :       .addDef(ARM::CPSR)
     375          36 :       .addReg(ARM::R4, RegState::Kill)
     376             :       .addImm(NrBitsToZero)
     377          36 :       .add(predOps(ARMCC::AL));
     378             : 
     379         108 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
     380          36 :       .addReg(ARM::R4, RegState::Kill)
     381          36 :       .add(predOps(ARMCC::AL));
     382             : 
     383             :     AFI->setShouldRestoreSPFromFP(true);
     384             :   }
     385             : 
     386             :   // If we need a base pointer, set it up here. It's whatever the value
     387             :   // of the stack pointer is at this point. Any variable size objects
     388             :   // will be allocated after this, so we can still use the base pointer
     389             :   // to reference locals.
     390         625 :   if (RegInfo->hasBasePointer(MF))
     391          54 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
     392          18 :         .addReg(ARM::SP)
     393          18 :         .add(predOps(ARMCC::AL));
     394             : 
     395             :   // If the frame has variable sized objects then the epilogue must restore
     396             :   // the sp from fp. We can assume there's an FP here since hasFP already
     397             :   // checks for hasVarSizedObjects.
     398         625 :   if (MFI.hasVarSizedObjects())
     399             :     AFI->setShouldRestoreSPFromFP(true);
     400             : 
     401             :   // In some cases, virtual registers have been introduced, e.g. by uses of
     402             :   // emitThumbRegPlusImmInReg.
     403             :   MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs);
     404             : }
     405             : 
     406        1425 : static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
     407        2866 :   if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
     408           8 :       isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
     409             :     return true;
     410        1425 :   else if (MI.getOpcode() == ARM::tPOP) {
     411             :     return true;
     412        1206 :   } else if (MI.getOpcode() == ARM::tMOVr) {
     413          54 :     unsigned Dst = MI.getOperand(0).getReg();
     414          54 :     unsigned Src = MI.getOperand(1).getReg();
     415         162 :     return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
     416          54 :             ARM::hGPRRegClass.contains(Dst));
     417             :   }
     418             :   return false;
     419             : }
     420             : 
     421        1204 : void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
     422             :                                    MachineBasicBlock &MBB) const {
     423        1204 :   MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
     424        1210 :   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
     425        1204 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     426        1204 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     427             :   const ThumbRegisterInfo *RegInfo =
     428        1204 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
     429             :   const Thumb1InstrInfo &TII =
     430        1204 :       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
     431             : 
     432        1204 :   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
     433        1204 :   int NumBytes = (int)MFI.getStackSize();
     434             :   assert((unsigned)NumBytes >= ArgRegsSaveSize &&
     435             :          "ArgRegsSaveSize is included in NumBytes");
     436        1204 :   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
     437        1204 :   unsigned FramePtr = RegInfo->getFrameRegister(MF);
     438             : 
     439        1204 :   if (!AFI->hasStackFrame()) {
     440         529 :     if (NumBytes - ArgRegsSaveSize != 0)
     441          28 :       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
     442             :   } else {
     443             :     // Unwind MBBI to point to first LDR / VLDRD.
     444         675 :     if (MBBI != MBB.begin()) {
     445             :       do
     446             :         --MBBI;
     447         892 :       while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
     448         641 :       if (!isCSRestore(*MBBI, CSRegs))
     449             :         ++MBBI;
     450             :     }
     451             : 
     452             :     // Move SP to start of FP callee save spill area.
     453        2025 :     NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
     454        1350 :                  AFI->getGPRCalleeSavedArea2Size() +
     455        1350 :                  AFI->getDPRCalleeSavedAreaSize() +
     456             :                  ArgRegsSaveSize);
     457             : 
     458         675 :     if (AFI->shouldRestoreSPFromFP()) {
     459          76 :       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
     460             :       // Reset SP based on frame pointer only if the stack frame extends beyond
     461             :       // frame pointer stack slot, the target is ELF and the function has FP, or
     462             :       // the target uses var sized objects.
     463          76 :       if (NumBytes) {
     464             :         assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
     465             :                "No scratch register to restore SP from FP!");
     466          76 :         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
     467             :                                   TII, *RegInfo);
     468         228 :         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
     469          76 :             .addReg(ARM::R4)
     470          76 :             .add(predOps(ARMCC::AL));
     471             :       } else
     472           0 :         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
     473           0 :             .addReg(FramePtr)
     474           0 :             .add(predOps(ARMCC::AL));
     475             :     } else {
     476        1205 :       if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
     477         609 :           &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
     478           0 :         MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
     479           0 :         if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
     480           0 :           emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
     481         599 :       } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
     482         592 :         emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
     483             :     }
     484             :   }
     485             : 
     486        1204 :   if (needPopSpecialFixUp(MF)) {
     487         673 :     bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
     488             :     (void)Done;
     489             :     assert(Done && "Emission of the special fixup failed!?");
     490             :   }
     491        1204 : }
     492             : 
     493          22 : bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
     494          22 :   if (!needPopSpecialFixUp(*MBB.getParent()))
     495             :     return true;
     496             : 
     497             :   MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
     498           0 :   return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
     499             : }
     500             : 
     501        1226 : bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
     502             :   ARMFunctionInfo *AFI =
     503        1226 :       const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
     504        1226 :   if (AFI->getArgRegsSaveSize())
     505             :     return true;
     506             : 
     507             :   // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
     508        1209 :   for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
     509         661 :     if (CSI.getReg() == ARM::LR)
     510             :       return true;
     511             : 
     512             :   return false;
     513             : }
     514             : 
     515         209 : static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
     516             :                                  const BitVector &PopFriendly,
     517             :                                  const LivePhysRegs &UsedRegs, unsigned &PopReg,
     518             :                                  unsigned &TmpReg) {
     519         209 :   PopReg = TmpReg = 0;
     520         526 :   for (auto Reg : GPRsNoLRSP.set_bits()) {
     521         516 :     if (!UsedRegs.contains(Reg)) {
     522             :       // Remember the first pop-friendly register and exit.
     523         209 :       if (PopFriendly.test(Reg)) {
     524         199 :         PopReg = Reg;
     525         199 :         TmpReg = 0;
     526         199 :         break;
     527             :       }
     528             :       // Otherwise, remember that the register will be available to
     529             :       // save a pop-friendly register.
     530          10 :       TmpReg = Reg;
     531             :     }
     532             :   }
     533         209 : }
     534             : 
     535         673 : bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
     536             :                                               bool DoIt) const {
     537         673 :   MachineFunction &MF = *MBB.getParent();
     538         673 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     539         673 :   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
     540         673 :   const TargetInstrInfo &TII = *STI.getInstrInfo();
     541             :   const ThumbRegisterInfo *RegInfo =
     542         673 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
     543             : 
     544             :   // If MBBI is a return instruction, or is a tPOP followed by a return
     545             :   // instruction in the successor BB, we may be able to directly restore
     546             :   // LR in the PC.
     547             :   // This is only possible with v5T ops (v4T can't change the Thumb bit via
     548             :   // a POP PC instruction), and only if we do not need to emit any SP update.
     549             :   // Otherwise, we need a temporary register to pop the value
     550             :   // and copy that value into LR.
     551         673 :   auto MBBI = MBB.getFirstTerminator();
     552         673 :   bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
     553             :   if (CanRestoreDirectly) {
     554         961 :     if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
     555         473 :       CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
     556             :                             MBBI->getOpcode() == ARM::tPOP_RET);
     557             :     else {
     558           9 :       auto MBBI_prev = MBBI;
     559             :       MBBI_prev--;
     560             :       assert(MBBI_prev->getOpcode() == ARM::tPOP);
     561             :       assert(MBB.succ_size() == 1);
     562          27 :       if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
     563           8 :         MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
     564             :       else
     565             :         CanRestoreDirectly = false;
     566             :     }
     567             :   }
     568             : 
     569         199 :   if (CanRestoreDirectly) {
     570        1422 :     if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
     571             :       return true;
     572             :     MachineInstrBuilder MIB =
     573          24 :         BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
     574           8 :             .add(predOps(ARMCC::AL));
     575             :     // Copy implicit ops and popped registers, if any.
     576          88 :     for (auto MO: MBBI->operands())
     577          88 :       if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
     578             :         MIB.add(MO);
     579           8 :     MIB.addReg(ARM::PC, RegState::Define);
     580             :     // Erase the old instruction (tBX_RET or tPOP).
     581           8 :     MBB.erase(MBBI);
     582           8 :     return true;
     583             :   }
     584             : 
     585             :   // Look for a temporary register to use.
     586             :   // First, compute the liveness information.
     587         199 :   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
     588             :   LivePhysRegs UsedRegs(TRI);
     589         199 :   UsedRegs.addLiveOuts(MBB);
     590             :   // The semantic of pristines changed recently and now,
     591             :   // the callee-saved registers that are touched in the function
     592             :   // are not part of the pristines set anymore.
     593             :   // Add those callee-saved now.
     594         199 :   const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
     595        6899 :   for (unsigned i = 0; CSRegs[i]; ++i)
     596        3350 :     UsedRegs.addReg(CSRegs[i]);
     597             : 
     598         199 :   DebugLoc dl = DebugLoc();
     599         199 :   if (MBBI != MBB.end()) {
     600             :     dl = MBBI->getDebugLoc();
     601         195 :     auto InstUpToMBBI = MBB.end();
     602         589 :     while (InstUpToMBBI != MBBI)
     603             :       // The pre-decrement is on purpose here.
     604             :       // We want to have the liveness right before MBBI.
     605         197 :       UsedRegs.stepBackward(*--InstUpToMBBI);
     606             :   }
     607             : 
     608             :   // Look for a register that can be directly use in the POP.
     609         199 :   unsigned PopReg = 0;
     610             :   // And some temporary register, just in case.
     611         199 :   unsigned TemporaryReg = 0;
     612             :   BitVector PopFriendly =
     613         398 :       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
     614             :   // R7 may be used as a frame pointer, hence marked as not generally
     615             :   // allocatable, however there's no reason to not use it as a temporary for
     616             :   // restoring LR.
     617         199 :   if (STI.useR7AsFramePointer())
     618             :     PopFriendly.set(ARM::R7);
     619             : 
     620             :   assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
     621             :   // Rebuild the GPRs from the high registers because they are removed
     622             :   // form the GPR reg class for thumb1.
     623             :   BitVector GPRsNoLRSP =
     624         398 :       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
     625         199 :   GPRsNoLRSP |= PopFriendly;
     626             :   GPRsNoLRSP.reset(ARM::LR);
     627             :   GPRsNoLRSP.reset(ARM::SP);
     628             :   GPRsNoLRSP.reset(ARM::PC);
     629         199 :   findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
     630             : 
     631             :   // If we couldn't find a pop-friendly register, try restoring LR before
     632             :   // popping the other callee-saved registers, so we could use one of them as a
     633             :   // temporary.
     634             :   bool UseLDRSP = false;
     635         209 :   if (!PopReg && MBBI != MBB.begin()) {
     636          10 :     auto PrevMBBI = MBBI;
     637             :     PrevMBBI--;
     638          20 :     if (PrevMBBI->getOpcode() == ARM::tPOP) {
     639          10 :       UsedRegs.stepBackward(*PrevMBBI);
     640          10 :       findTemporariesForLR(GPRsNoLRSP, PopFriendly, UsedRegs, PopReg, TemporaryReg);
     641          10 :       if (PopReg) {
     642          10 :         MBBI = PrevMBBI;
     643             :         UseLDRSP = true;
     644             :       }
     645             :     }
     646             :   }
     647             : 
     648         199 :   if (!DoIt && !PopReg && !TemporaryReg)
     649             :     return false;
     650             : 
     651             :   assert((PopReg || TemporaryReg) && "Cannot get LR");
     652             : 
     653         199 :   if (UseLDRSP) {
     654             :     assert(PopReg && "Do not know how to get LR");
     655             :     // Load the LR via LDR tmp, [SP, #off]
     656          30 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
     657          10 :       .addReg(PopReg, RegState::Define)
     658          20 :       .addReg(ARM::SP)
     659          10 :       .addImm(MBBI->getNumExplicitOperands() - 2)
     660          10 :       .add(predOps(ARMCC::AL));
     661             :     // Move from the temporary register to the LR.
     662          30 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     663          10 :       .addReg(ARM::LR, RegState::Define)
     664          10 :       .addReg(PopReg, RegState::Kill)
     665          20 :       .add(predOps(ARMCC::AL));
     666             :     // Advance past the pop instruction.
     667             :     MBBI++;
     668             :     // Increment the SP.
     669          10 :     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize + 4);
     670          10 :     return true;
     671             :   }
     672             : 
     673         189 :   if (TemporaryReg) {
     674             :     assert(!PopReg && "Unnecessary MOV is about to be inserted");
     675           0 :     PopReg = PopFriendly.find_first();
     676           0 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     677           0 :         .addReg(TemporaryReg, RegState::Define)
     678           0 :         .addReg(PopReg, RegState::Kill)
     679           0 :         .add(predOps(ARMCC::AL));
     680             :   }
     681             : 
     682         374 :   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
     683             :     // We couldn't use the direct restoration above, so
     684             :     // perform the opposite conversion: tPOP_RET to tPOP.
     685             :     MachineInstrBuilder MIB =
     686           0 :         BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
     687           0 :             .add(predOps(ARMCC::AL));
     688             :     bool Popped = false;
     689           0 :     for (auto MO: MBBI->operands())
     690           0 :       if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
     691           0 :           MO.getReg() != ARM::PC) {
     692             :         MIB.add(MO);
     693           0 :         if (!MO.isImplicit())
     694             :           Popped = true;
     695             :       }
     696             :     // Is there anything left to pop?
     697           0 :     if (!Popped)
     698             :       MBB.erase(MIB.getInstr());
     699             :     // Erase the old instruction.
     700           0 :     MBB.erase(MBBI);
     701           0 :     MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
     702           0 :                .add(predOps(ARMCC::AL));
     703             :   }
     704             : 
     705             :   assert(PopReg && "Do not know how to get LR");
     706         567 :   BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
     707         189 :       .add(predOps(ARMCC::AL))
     708         189 :       .addReg(PopReg, RegState::Define);
     709             : 
     710         189 :   emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
     711             : 
     712         567 :   BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     713         189 :       .addReg(ARM::LR, RegState::Define)
     714         189 :       .addReg(PopReg, RegState::Kill)
     715         378 :       .add(predOps(ARMCC::AL));
     716             : 
     717         189 :   if (TemporaryReg)
     718           0 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     719           0 :         .addReg(PopReg, RegState::Define)
     720           0 :         .addReg(TemporaryReg, RegState::Kill)
     721           0 :         .add(predOps(ARMCC::AL));
     722             : 
     723             :   return true;
     724             : }
     725             : 
     726             : using ARMRegSet = std::bitset<ARM::NUM_TARGET_REGS>;
     727             : 
     728             : // Return the first iteraror after CurrentReg which is present in EnabledRegs,
     729             : // or OrderEnd if no further registers are in that set. This does not advance
     730             : // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
     731             : static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
     732             :                                           const ARMRegSet &EnabledRegs,
     733             :                                           const unsigned *OrderEnd) {
     734       12123 :   while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
     735        5161 :     ++CurrentReg;
     736             :   return CurrentReg;
     737             : }
     738             : 
     739         625 : bool Thumb1FrameLowering::
     740             : spillCalleeSavedRegisters(MachineBasicBlock &MBB,
     741             :                           MachineBasicBlock::iterator MI,
     742             :                           const std::vector<CalleeSavedInfo> &CSI,
     743             :                           const TargetRegisterInfo *TRI) const {
     744         625 :   if (CSI.empty())
     745             :     return false;
     746             : 
     747         625 :   DebugLoc DL;
     748         625 :   const TargetInstrInfo &TII = *STI.getInstrInfo();
     749         625 :   MachineFunction &MF = *MBB.getParent();
     750             :   const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
     751         625 :       MF.getSubtarget().getRegisterInfo());
     752             : 
     753         625 :   ARMRegSet LoRegsToSave; // r0-r7, lr
     754         625 :   ARMRegSet HiRegsToSave; // r8-r11
     755         625 :   ARMRegSet CopyRegs;     // Registers which can be used after pushing
     756             :                           // LoRegs for saving HiRegs.
     757             : 
     758        1250 :   for (unsigned i = CSI.size(); i != 0; --i) {
     759        3520 :     unsigned Reg = CSI[i-1].getReg();
     760             : 
     761        3520 :     if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
     762        1706 :       LoRegsToSave[Reg] = true;
     763         108 :     } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
     764          54 :       HiRegsToSave[Reg] = true;
     765             :     } else {
     766           0 :       llvm_unreachable("callee-saved register of unexpected class");
     767             :     }
     768             : 
     769        4143 :     if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
     770        5170 :         !MF.getRegInfo().isLiveIn(Reg) &&
     771        2231 :         !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
     772        1547 :       CopyRegs[Reg] = true;
     773             :   }
     774             : 
     775             :   // Unused argument registers can be used for the high register saving.
     776        5625 :   for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
     777        2500 :     if (!MF.getRegInfo().isLiveIn(ArgReg))
     778        1830 :       CopyRegs[ArgReg] = true;
     779             : 
     780             :   // Push the low registers and lr
     781         625 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     782         625 :   if (!LoRegsToSave.none()) {
     783             :     MachineInstrBuilder MIB =
     784        1869 :         BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
     785        6853 :     for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
     786        6230 :       if (LoRegsToSave[Reg]) {
     787        1706 :         bool isKill = !MRI.isLiveIn(Reg);
     788        3410 :         if (isKill && !MRI.isReserved(Reg))
     789        1529 :           MBB.addLiveIn(Reg);
     790             : 
     791        1706 :         MIB.addReg(Reg, getKillRegState(isKill));
     792             :       }
     793             :     }
     794             :     MIB.setMIFlags(MachineInstr::FrameSetup);
     795             :   }
     796             : 
     797             :   // Push the high registers. There are no store instructions that can access
     798             :   // these registers directly, so we have to move them to low registers, and
     799             :   // push them. This might take multiple pushes, as it is possible for there to
     800             :   // be fewer low registers available than high registers which need saving.
     801             : 
     802             :   // These are in reverse order so that in the case where we need to use
     803             :   // multiple PUSH instructions, the order of the registers on the stack still
     804             :   // matches the unwind info. They need to be swicthed back to ascending order
     805             :   // before adding to the PUSH instruction.
     806             :   static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
     807             :                                          ARM::R5, ARM::R4, ARM::R3,
     808             :                                          ARM::R2, ARM::R1, ARM::R0};
     809             :   static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
     810             : 
     811             :   const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
     812             :   const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
     813             : 
     814             :   // Find the first register to save.
     815             :   const unsigned *HiRegToSave = findNextOrderedReg(
     816             :       std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
     817             : 
     818         663 :   while (HiRegToSave != AllHighRegsEnd) {
     819             :     // Find the first low register to use.
     820             :     const unsigned *CopyReg =
     821             :         findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
     822             : 
     823             :     // Create the PUSH, but don't insert it yet (the MOVs need to come first).
     824             :     MachineInstrBuilder PushMIB =
     825          38 :         BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
     826             : 
     827             :     SmallVector<unsigned, 4> RegsToPush;
     828          73 :     while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
     829         108 :       if (HiRegsToSave[*HiRegToSave]) {
     830          54 :         bool isKill = !MRI.isLiveIn(*HiRegToSave);
     831         108 :         if (isKill && !MRI.isReserved(*HiRegToSave))
     832          54 :           MBB.addLiveIn(*HiRegToSave);
     833             : 
     834             :         // Emit a MOV from the high reg to the low reg.
     835         162 :         BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
     836          54 :             .addReg(*CopyReg, RegState::Define)
     837          54 :             .addReg(*HiRegToSave, getKillRegState(isKill))
     838          54 :             .add(predOps(ARMCC::AL));
     839             : 
     840             :         // Record the register that must be added to the PUSH.
     841          54 :         RegsToPush.push_back(*CopyReg);
     842             : 
     843          54 :         CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
     844          54 :         HiRegToSave =
     845             :             findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
     846             :       }
     847             :     }
     848             : 
     849             :     // Add the low registers to the PUSH, in ascending order.
     850          73 :     for (unsigned Reg : llvm::reverse(RegsToPush))
     851          54 :       PushMIB.addReg(Reg, RegState::Kill);
     852             : 
     853             :     // Insert the PUSH instruction after the MOVs.
     854          19 :     MBB.insert(MI, PushMIB);
     855             :   }
     856             : 
     857             :   return true;
     858             : }
     859             : 
     860         675 : bool Thumb1FrameLowering::
     861             : restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
     862             :                             MachineBasicBlock::iterator MI,
     863             :                             std::vector<CalleeSavedInfo> &CSI,
     864             :                             const TargetRegisterInfo *TRI) const {
     865         675 :   if (CSI.empty())
     866             :     return false;
     867             : 
     868         675 :   MachineFunction &MF = *MBB.getParent();
     869         675 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     870         675 :   const TargetInstrInfo &TII = *STI.getInstrInfo();
     871             :   const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
     872         675 :       MF.getSubtarget().getRegisterInfo());
     873             : 
     874         675 :   bool isVarArg = AFI->getArgRegsSaveSize() > 0;
     875         681 :   DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
     876             : 
     877         675 :   ARMRegSet LoRegsToRestore;
     878         675 :   ARMRegSet HiRegsToRestore;
     879             :   // Low registers (r0-r7) which can be used to restore the high registers.
     880         675 :   ARMRegSet CopyRegs;
     881             : 
     882        2558 :   for (CalleeSavedInfo I : CSI) {
     883             :     unsigned Reg = I.getReg();
     884             : 
     885        3766 :     if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
     886        1829 :       LoRegsToRestore[Reg] = true;
     887         108 :     } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
     888          54 :       HiRegsToRestore[Reg] = true;
     889             :     } else {
     890           0 :       llvm_unreachable("callee-saved register of unexpected class");
     891             :     }
     892             : 
     893             :     // If this is a low register not used as the frame pointer, we may want to
     894             :     // use it for restoring the high registers.
     895        4922 :     if ((ARM::tGPRRegClass.contains(Reg)) &&
     896        1551 :         !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
     897         993 :       CopyRegs[Reg] = true;
     898             :   }
     899             : 
     900             :   // If this is a return block, we may be able to use some unused return value
     901             :   // registers for restoring the high regs.
     902         675 :   auto Terminator = MBB.getFirstTerminator();
     903        1344 :   if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
     904             :     CopyRegs[ARM::R0] = true;
     905             :     CopyRegs[ARM::R1] = true;
     906             :     CopyRegs[ARM::R2] = true;
     907             :     CopyRegs[ARM::R3] = true;
     908        1343 :     for (auto Op : Terminator->implicit_operands()) {
     909         347 :       if (Op.isReg())
     910         347 :         CopyRegs[Op.getReg()] = false;
     911             :     }
     912             :   }
     913             : 
     914             :   static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
     915             :                                          ARM::R4, ARM::R5, ARM::R6, ARM::R7};
     916             :   static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
     917             : 
     918             :   const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
     919             :   const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
     920             : 
     921             :   // Find the first register to restore.
     922             :   auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
     923             :                                            HiRegsToRestore, AllHighRegsEnd);
     924             : 
     925         713 :   while (HiRegToRestore != AllHighRegsEnd) {
     926             :     assert(!CopyRegs.none());
     927             :     // Find the first low register to use.
     928             :     auto CopyReg =
     929             :         findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
     930             : 
     931             :     // Create the POP instruction.
     932             :     MachineInstrBuilder PopMIB =
     933          57 :         BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
     934             : 
     935          73 :     while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
     936             :       // Add the low register to the POP.
     937          54 :       PopMIB.addReg(*CopyReg, RegState::Define);
     938             : 
     939             :       // Create the MOV from low to high register.
     940         162 :       BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
     941          54 :           .addReg(*HiRegToRestore, RegState::Define)
     942          54 :           .addReg(*CopyReg, RegState::Kill)
     943          54 :           .add(predOps(ARMCC::AL));
     944             : 
     945          54 :       CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
     946          54 :       HiRegToRestore =
     947             :           findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
     948             :     }
     949             :   }
     950             : 
     951             :   MachineInstrBuilder MIB =
     952        1350 :       BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
     953             : 
     954             :   bool NeedsPop = false;
     955        1350 :   for (unsigned i = CSI.size(); i != 0; --i) {
     956        1883 :     CalleeSavedInfo &Info = CSI[i-1];
     957        1883 :     unsigned Reg = Info.getReg();
     958             : 
     959             :     // High registers (excluding lr) have already been dealt with
     960        3820 :     if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
     961          54 :       continue;
     962             : 
     963        1829 :     if (Reg == ARM::LR) {
     964             :       Info.setRestored(false);
     965         679 :       if (!MBB.succ_empty() ||
     966        1321 :           MI->getOpcode() == ARM::TCRETURNdi ||
     967             :           MI->getOpcode() == ARM::TCRETURNri)
     968             :         // LR may only be popped into PC, as part of return sequence.
     969             :         // If this isn't the return sequence, we'll need emitPopSpecialFixUp
     970             :         // to restore LR the hard way.
     971             :         // FIXME: if we don't pass any stack arguments it would be actually
     972             :         // advantageous *and* correct to do the conversion to an ordinary call
     973             :         // instruction here.
     974          26 :         continue;
     975             :       // Special epilogue for vararg functions. See emitEpilogue
     976         664 :       if (isVarArg)
     977          17 :         continue;
     978             :       // ARMv4T requires BX, see emitEpilogue
     979         630 :       if (!STI.hasV5TOps())
     980         164 :         continue;
     981             : 
     982             :       // Pop LR into PC.
     983             :       Reg = ARM::PC;
     984         466 :       (*MIB).setDesc(TII.get(ARM::tPOP_RET));
     985         466 :       if (MI != MBB.end())
     986             :         MIB.copyImplicitOps(*MI);
     987         466 :       MI = MBB.erase(MI);
     988             :     }
     989        1622 :     MIB.addReg(Reg, getDefRegState(true));
     990             :     NeedsPop = true;
     991             :   }
     992             : 
     993             :   // It's illegal to emit pop instruction without operands.
     994         675 :   if (NeedsPop)
     995         666 :     MBB.insert(MI, &*MIB);
     996             :   else
     997           9 :     MF.DeleteMachineInstr(MIB);
     998             : 
     999             :   return true;
    1000             : }

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