LCOV - code coverage report
Current view: top level - lib/Target/ARM - Thumb1FrameLowering.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 417 444 93.9 %
Date: 2017-09-14 15:23:50 Functions: 11 11 100.0 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- Thumb1FrameLowering.cpp - Thumb1 Frame Information ----------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the Thumb1 implementation of TargetFrameLowering class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "Thumb1FrameLowering.h"
      15             : #include "ARMBaseInstrInfo.h"
      16             : #include "ARMBaseRegisterInfo.h"
      17             : #include "ARMMachineFunctionInfo.h"
      18             : #include "ARMSubtarget.h"
      19             : #include "MCTargetDesc/ARMBaseInfo.h"
      20             : #include "Thumb1InstrInfo.h"
      21             : #include "ThumbRegisterInfo.h"
      22             : #include "llvm/ADT/BitVector.h"
      23             : #include "llvm/ADT/STLExtras.h"
      24             : #include "llvm/ADT/SmallVector.h"
      25             : #include "llvm/CodeGen/LivePhysRegs.h"
      26             : #include "llvm/CodeGen/MachineBasicBlock.h"
      27             : #include "llvm/CodeGen/MachineFrameInfo.h"
      28             : #include "llvm/CodeGen/MachineFunction.h"
      29             : #include "llvm/CodeGen/MachineInstr.h"
      30             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      31             : #include "llvm/CodeGen/MachineModuleInfo.h"
      32             : #include "llvm/CodeGen/MachineOperand.h"
      33             : #include "llvm/CodeGen/MachineRegisterInfo.h"
      34             : #include "llvm/IR/DebugLoc.h"
      35             : #include "llvm/MC/MCDwarf.h"
      36             : #include "llvm/Support/Compiler.h"
      37             : #include "llvm/Support/ErrorHandling.h"
      38             : #include "llvm/Target/TargetInstrInfo.h"
      39             : #include "llvm/Target/TargetSubtargetInfo.h"
      40             : #include <bitset>
      41             : #include <cassert>
      42             : #include <iterator>
      43             : #include <vector>
      44             : 
      45             : using namespace llvm;
      46             : 
      47         423 : Thumb1FrameLowering::Thumb1FrameLowering(const ARMSubtarget &sti)
      48         423 :     : ARMFrameLowering(sti) {}
      49             : 
      50        4324 : bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
      51        4324 :   const MachineFrameInfo &MFI = MF.getFrameInfo();
      52        4324 :   unsigned CFSize = MFI.getMaxCallFrameSize();
      53             :   // It's not always a good idea to include the call frame as part of the
      54             :   // stack frame. ARM (especially Thumb) has small immediate offset to
      55             :   // address the stack frame. So a large call frame can cause poor codegen
      56             :   // and may even makes it impossible to scavenge a register.
      57        4324 :   if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4
      58             :     return false;
      59             : 
      60        4276 :   return !MFI.hasVarSizedObjects();
      61             : }
      62             : 
      63             : static void emitSPUpdate(MachineBasicBlock &MBB,
      64             :                          MachineBasicBlock::iterator &MBBI,
      65             :                          const TargetInstrInfo &TII, const DebugLoc &dl,
      66             :                          const ThumbRegisterInfo &MRI, int NumBytes,
      67             :                          unsigned MIFlags = MachineInstr::NoFlags) {
      68        1044 :   emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
      69             :                             MRI, MIFlags);
      70             : }
      71             : 
      72             : 
      73        1320 : MachineBasicBlock::iterator Thumb1FrameLowering::
      74             : eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
      75             :                               MachineBasicBlock::iterator I) const {
      76             :   const Thumb1InstrInfo &TII =
      77        1320 :       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
      78             :   const ThumbRegisterInfo *RegInfo =
      79        1320 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
      80        1320 :   if (!hasReservedCallFrame(MF)) {
      81             :     // If we have alloca, convert as follows:
      82             :     // ADJCALLSTACKDOWN -> sub, sp, sp, amount
      83             :     // ADJCALLSTACKUP   -> add, sp, sp, amount
      84         108 :     MachineInstr &Old = *I;
      85         324 :     DebugLoc dl = Old.getDebugLoc();
      86         216 :     unsigned Amount = TII.getFrameSize(Old);
      87         108 :     if (Amount != 0) {
      88             :       // We need to keep the stack aligned properly.  To do this, we round the
      89             :       // amount of space needed for the outgoing arguments up to the next
      90             :       // alignment boundary.
      91          16 :       Amount = alignTo(Amount, getStackAlignment());
      92             : 
      93             :       // Replace the pseudo instruction with a new instruction...
      94           8 :       unsigned Opc = Old.getOpcode();
      95           8 :       if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
      96           4 :         emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
      97             :       } else {
      98             :         assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
      99           4 :         emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
     100             :       }
     101             :     }
     102             :   }
     103        1320 :   return MBB.erase(I);
     104             : }
     105             : 
     106         911 : void Thumb1FrameLowering::emitPrologue(MachineFunction &MF,
     107             :                                        MachineBasicBlock &MBB) const {
     108         911 :   MachineBasicBlock::iterator MBBI = MBB.begin();
     109         911 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     110         911 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     111         911 :   MachineModuleInfo &MMI = MF.getMMI();
     112         911 :   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
     113             :   const ThumbRegisterInfo *RegInfo =
     114         911 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
     115             :   const Thumb1InstrInfo &TII =
     116         911 :       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
     117             : 
     118         911 :   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
     119         911 :   unsigned NumBytes = MFI.getStackSize();
     120             :   assert(NumBytes >= ArgRegsSaveSize &&
     121             :          "ArgRegsSaveSize is included in NumBytes");
     122         911 :   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
     123             : 
     124             :   // Debug location must be unknown since the first debug location is used
     125             :   // to determine the end of the prologue.
     126        1449 :   DebugLoc dl;
     127             :   
     128         911 :   unsigned FramePtr = RegInfo->getFrameRegister(MF);
     129         911 :   unsigned BasePtr = RegInfo->getBaseRegister();
     130         911 :   int CFAOffset = 0;
     131             : 
     132             :   // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4.
     133         911 :   NumBytes = (NumBytes + 3) & ~3;
     134        1822 :   MFI.setStackSize(NumBytes);
     135             : 
     136             :   // Determine the sizes of each callee-save spill areas and record which frame
     137             :   // belongs to which callee-save spill areas.
     138         911 :   unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
     139         911 :   int FramePtrSpillFI = 0;
     140             : 
     141         911 :   if (ArgRegsSaveSize) {
     142          26 :     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
     143             :                  MachineInstr::FrameSetup);
     144          13 :     CFAOffset -= ArgRegsSaveSize;
     145             :     unsigned CFIIndex = MF.addFrameInst(
     146          39 :         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     147          39 :     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     148          13 :         .addCFIIndex(CFIIndex)
     149          13 :         .setMIFlags(MachineInstr::FrameSetup);
     150             :   }
     151             : 
     152         911 :   if (!AFI->hasStackFrame()) {
     153         373 :     if (NumBytes - ArgRegsSaveSize != 0) {
     154          52 :       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
     155             :                    MachineInstr::FrameSetup);
     156          26 :       CFAOffset -= NumBytes - ArgRegsSaveSize;
     157             :       unsigned CFIIndex = MF.addFrameInst(
     158          78 :           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     159          78 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     160          26 :           .addCFIIndex(CFIIndex)
     161          26 :           .setMIFlags(MachineInstr::FrameSetup);
     162             :     }
     163         373 :     return;
     164             :   }
     165             : 
     166        2522 :   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
     167        2892 :     unsigned Reg = CSI[i].getReg();
     168        1446 :     int FI = CSI[i].getFrameIdx();
     169        1446 :     switch (Reg) {
     170          54 :     case ARM::R8:
     171             :     case ARM::R9:
     172             :     case ARM::R10:
     173             :     case ARM::R11:
     174          54 :       if (STI.splitFramePushPop(MF)) {
     175          54 :         GPRCS2Size += 4;
     176          54 :         break;
     177             :       }
     178             :       LLVM_FALLTHROUGH;
     179             :     case ARM::R4:
     180             :     case ARM::R5:
     181             :     case ARM::R6:
     182             :     case ARM::R7:
     183             :     case ARM::LR:
     184        1392 :       if (Reg == FramePtr)
     185         117 :         FramePtrSpillFI = FI;
     186        1392 :       GPRCS1Size += 4;
     187        1392 :       break;
     188           0 :     default:
     189           0 :       DPRCSSize += 8;
     190             :     }
     191             :   }
     192             : 
     193        2152 :   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
     194             :     ++MBBI;
     195             :   }
     196             : 
     197             :   // Determine starting offsets of spill areas.
     198         538 :   unsigned DPRCSOffset  = NumBytes - ArgRegsSaveSize - (GPRCS1Size + GPRCS2Size + DPRCSSize);
     199         538 :   unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
     200         538 :   unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
     201         538 :   bool HasFP = hasFP(MF);
     202         538 :   if (HasFP)
     203         117 :     AFI->setFramePtrSpillOffset(MFI.getObjectOffset(FramePtrSpillFI) +
     204             :                                 NumBytes);
     205        1076 :   AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
     206        1076 :   AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
     207        1076 :   AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
     208         538 :   NumBytes = DPRCSOffset;
     209             : 
     210         538 :   int FramePtrOffsetInBlock = 0;
     211         538 :   unsigned adjustedGPRCS1Size = GPRCS1Size;
     212        1058 :   if (GPRCS1Size > 0 && GPRCS2Size == 0 &&
     213        1040 :       tryFoldSPUpdateIntoPushPop(STI, MF, &*std::prev(MBBI), NumBytes)) {
     214           7 :     FramePtrOffsetInBlock = NumBytes;
     215           7 :     adjustedGPRCS1Size += NumBytes;
     216           7 :     NumBytes = 0;
     217             :   }
     218             : 
     219         538 :   if (adjustedGPRCS1Size) {
     220         536 :     CFAOffset -= adjustedGPRCS1Size;
     221             :     unsigned CFIIndex = MF.addFrameInst(
     222        1608 :         MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     223        1608 :     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     224         536 :         .addCFIIndex(CFIIndex)
     225         536 :         .setMIFlags(MachineInstr::FrameSetup);
     226             :   }
     227         538 :   for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
     228        2522 :          E = CSI.end(); I != E; ++I) {
     229        1446 :     unsigned Reg = I->getReg();
     230        1446 :     int FI = I->getFrameIdx();
     231        1446 :     switch (Reg) {
     232          54 :     case ARM::R8:
     233             :     case ARM::R9:
     234             :     case ARM::R10:
     235             :     case ARM::R11:
     236             :     case ARM::R12:
     237          54 :       if (STI.splitFramePushPop(MF))
     238             :         break;
     239             :       LLVM_FALLTHROUGH;
     240             :     case ARM::R0:
     241             :     case ARM::R1:
     242             :     case ARM::R2:
     243             :     case ARM::R3:
     244             :     case ARM::R4:
     245             :     case ARM::R5:
     246             :     case ARM::R6:
     247             :     case ARM::R7:
     248             :     case ARM::LR:
     249        5568 :       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
     250        4176 :           nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
     251        4176 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     252        1392 :           .addCFIIndex(CFIIndex)
     253        1392 :           .setMIFlags(MachineInstr::FrameSetup);
     254        1392 :       break;
     255             :     }
     256             :   }
     257             : 
     258             :   // Adjust FP so it point to the stack slot that contains the previous FP.
     259         538 :   if (HasFP) {
     260         117 :     FramePtrOffsetInBlock +=
     261         117 :         MFI.getObjectOffset(FramePtrSpillFI) + GPRCS1Size + ArgRegsSaveSize;
     262         351 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
     263         117 :         .addReg(ARM::SP)
     264         234 :         .addImm(FramePtrOffsetInBlock / 4)
     265         117 :         .setMIFlags(MachineInstr::FrameSetup)
     266         351 :         .add(predOps(ARMCC::AL));
     267         117 :     if(FramePtrOffsetInBlock) {
     268          64 :       CFAOffset += FramePtrOffsetInBlock;
     269         192 :       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfa(
     270         128 :           nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
     271         192 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     272          64 :           .addCFIIndex(CFIIndex)
     273          64 :           .setMIFlags(MachineInstr::FrameSetup);
     274             :     } else {
     275             :       unsigned CFIIndex =
     276         159 :           MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
     277         106 :               nullptr, MRI->getDwarfRegNum(FramePtr, true)));
     278         159 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     279          53 :           .addCFIIndex(CFIIndex)
     280          53 :           .setMIFlags(MachineInstr::FrameSetup);
     281             :     }
     282         117 :     if (NumBytes > 508)
     283             :       // If offset is > 508 then sp cannot be adjusted in a single instruction,
     284             :       // try restoring from fp instead.
     285             :       AFI->setShouldRestoreSPFromFP(true);
     286             :   }
     287             : 
     288             :   // Skip past the spilling of r8-r11, which could consist of multiple tPUSH
     289             :   // and tMOVr instructions. We don't need to add any call frame information
     290             :   // in-between these instructions, because they do not modify the high
     291             :   // registers.
     292             :   while (true) {
     293         557 :     MachineBasicBlock::iterator OldMBBI = MBBI;
     294             :     // Skip a run of tMOVr instructions
     295        2440 :     while (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tMOVr)
     296          54 :       MBBI++;
     297        2224 :     if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
     298          38 :       MBBI++;
     299             :     } else {
     300             :       // We have reached an instruction which is not a push, so the previous
     301             :       // run of tMOVr instructions (which may have been empty) was not part of
     302             :       // the prologue. Reset MBBI back to the last PUSH of the prologue.
     303         538 :       MBBI = OldMBBI;
     304         538 :       break;
     305             :     }
     306             :   }
     307             : 
     308             :   // Emit call frame information for the callee-saved high registers.
     309        3598 :   for (auto &I : CSI) {
     310        1446 :     unsigned Reg = I.getReg();
     311        1446 :     int FI = I.getFrameIdx();
     312        1446 :     switch (Reg) {
     313          54 :     case ARM::R8:
     314             :     case ARM::R9:
     315             :     case ARM::R10:
     316             :     case ARM::R11:
     317             :     case ARM::R12: {
     318         216 :       unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
     319         162 :           nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
     320         162 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     321          54 :           .addCFIIndex(CFIIndex)
     322          54 :           .setMIFlags(MachineInstr::FrameSetup);
     323          54 :       break;
     324             :     }
     325             :     default:
     326             :       break;
     327             :     }
     328             :   }
     329             : 
     330         538 :   if (NumBytes) {
     331             :     // Insert it after all the callee-save spills.
     332         560 :     emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
     333             :                  MachineInstr::FrameSetup);
     334         280 :     if (!HasFP) {
     335         236 :       CFAOffset -= NumBytes;
     336             :       unsigned CFIIndex = MF.addFrameInst(
     337         708 :           MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
     338         708 :       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
     339         236 :           .addCFIIndex(CFIIndex)
     340         236 :           .setMIFlags(MachineInstr::FrameSetup);
     341             :     }
     342             :   }
     343             : 
     344        1076 :   if (STI.isTargetELF() && HasFP)
     345         158 :     MFI.setOffsetAdjustment(MFI.getOffsetAdjustment() -
     346          79 :                             AFI->getFramePtrSpillOffset());
     347             : 
     348        1076 :   AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
     349        1076 :   AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
     350        1076 :   AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
     351             : 
     352             :   // Thumb1 does not currently support dynamic stack realignment.  Report a
     353             :   // fatal error rather then silently generate bad code.
     354         538 :   if (RegInfo->needsStackRealignment(MF))
     355           0 :       report_fatal_error("Dynamic stack realignment not supported for thumb1.");
     356             : 
     357             :   // If we need a base pointer, set it up here. It's whatever the value
     358             :   // of the stack pointer is at this point. Any variable size objects
     359             :   // will be allocated after this, so we can still use the base pointer
     360             :   // to reference locals.
     361         538 :   if (RegInfo->hasBasePointer(MF))
     362          42 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
     363          14 :         .addReg(ARM::SP)
     364          42 :         .add(predOps(ARMCC::AL));
     365             : 
     366             :   // If the frame has variable sized objects then the epilogue must restore
     367             :   // the sp from fp. We can assume there's an FP here since hasFP already
     368             :   // checks for hasVarSizedObjects.
     369         538 :   if (MFI.hasVarSizedObjects())
     370             :     AFI->setShouldRestoreSPFromFP(true);
     371             : 
     372             :   // In some cases, virtual registers have been introduced, e.g. by uses of
     373             :   // emitThumbRegPlusImmInReg.
     374        1076 :   MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs);
     375             : }
     376             : 
     377        1222 : static bool isCSRestore(MachineInstr &MI, const MCPhysReg *CSRegs) {
     378        2472 :   if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&
     379          28 :       isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
     380             :     return true;
     381        1222 :   else if (MI.getOpcode() == ARM::tPOP) {
     382             :     return true;
     383        1057 :   } else if (MI.getOpcode() == ARM::tMOVr) {
     384          54 :     unsigned Dst = MI.getOperand(0).getReg();
     385          54 :     unsigned Src = MI.getOperand(1).getReg();
     386         162 :     return ((ARM::tGPRRegClass.contains(Src) || Src == ARM::LR) &&
     387         108 :             ARM::hGPRRegClass.contains(Dst));
     388             :   }
     389             :   return false;
     390             : }
     391             : 
     392         993 : void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
     393             :                                    MachineBasicBlock &MBB) const {
     394         993 :   MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
     395        3972 :   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
     396         993 :   MachineFrameInfo &MFI = MF.getFrameInfo();
     397         993 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     398             :   const ThumbRegisterInfo *RegInfo =
     399         993 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
     400             :   const Thumb1InstrInfo &TII =
     401         993 :       *static_cast<const Thumb1InstrInfo *>(STI.getInstrInfo());
     402             : 
     403         993 :   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
     404         993 :   int NumBytes = (int)MFI.getStackSize();
     405             :   assert((unsigned)NumBytes >= ArgRegsSaveSize &&
     406             :          "ArgRegsSaveSize is included in NumBytes");
     407         993 :   const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
     408         993 :   unsigned FramePtr = RegInfo->getFrameRegister(MF);
     409             : 
     410         993 :   if (!AFI->hasStackFrame()) {
     411         403 :     if (NumBytes - ArgRegsSaveSize != 0)
     412          26 :       emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes - ArgRegsSaveSize);
     413             :   } else {
     414             :     // Unwind MBBI to point to first LDR / VLDRD.
     415        1180 :     if (MBBI != MBB.begin()) {
     416             :       do
     417         760 :         --MBBI;
     418        2179 :       while (MBBI != MBB.begin() && isCSRestore(*MBBI, CSRegs));
     419         563 :       if (!isCSRestore(*MBBI, CSRegs))
     420             :         ++MBBI;
     421             :     }
     422             : 
     423             :     // Move SP to start of FP callee save spill area.
     424        1770 :     NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
     425        1180 :                  AFI->getGPRCalleeSavedArea2Size() +
     426        1180 :                  AFI->getDPRCalleeSavedAreaSize() +
     427             :                  ArgRegsSaveSize);
     428             : 
     429         590 :     if (AFI->shouldRestoreSPFromFP()) {
     430          38 :       NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
     431             :       // Reset SP based on frame pointer only if the stack frame extends beyond
     432             :       // frame pointer stack slot, the target is ELF and the function has FP, or
     433             :       // the target uses var sized objects.
     434          38 :       if (NumBytes) {
     435             :         assert(!MFI.getPristineRegs(MF).test(ARM::R4) &&
     436             :                "No scratch register to restore SP from FP!");
     437          38 :         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
     438             :                                   TII, *RegInfo);
     439         114 :         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
     440          38 :             .addReg(ARM::R4)
     441         114 :             .add(predOps(ARMCC::AL));
     442             :       } else
     443           0 :         BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
     444           0 :             .addReg(FramePtr)
     445           0 :             .add(predOps(ARMCC::AL));
     446             :     } else {
     447        2215 :       if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tBX_RET &&
     448         581 :           &MBB.front() != &*MBBI && std::prev(MBBI)->getOpcode() == ARM::tPOP) {
     449           0 :         MachineBasicBlock::iterator PMBBI = std::prev(MBBI);
     450           0 :         if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*PMBBI, NumBytes))
     451           0 :           emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes);
     452        1104 :       } else if (!tryFoldSPUpdateIntoPushPop(STI, MF, &*MBBI, NumBytes))
     453         546 :         emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes);
     454             :     }
     455             :   }
     456             : 
     457         993 :   if (needPopSpecialFixUp(MF)) {
     458         588 :     bool Done = emitPopSpecialFixUp(MBB, /* DoIt */ true);
     459             :     (void)Done;
     460             :     assert(Done && "Emission of the special fixup failed!?");
     461             :   }
     462         993 : }
     463             : 
     464          22 : bool Thumb1FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
     465          22 :   if (!needPopSpecialFixUp(*MBB.getParent()))
     466             :     return true;
     467             : 
     468           0 :   MachineBasicBlock *TmpMBB = const_cast<MachineBasicBlock *>(&MBB);
     469           0 :   return emitPopSpecialFixUp(*TmpMBB, /* DoIt */ false);
     470             : }
     471             : 
     472        1015 : bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
     473             :   ARMFunctionInfo *AFI =
     474        1015 :       const_cast<MachineFunction *>(&MF)->getInfo<ARMFunctionInfo>();
     475        1015 :   if (AFI->getArgRegsSaveSize())
     476             :     return true;
     477             : 
     478             :   // LR cannot be encoded with Thumb1, i.e., it requires a special fix-up.
     479        4013 :   for (const CalleeSavedInfo &CSI : MF.getFrameInfo().getCalleeSavedInfo())
     480         580 :     if (CSI.getReg() == ARM::LR)
     481             :       return true;
     482             : 
     483             :   return false;
     484             : }
     485             : 
     486         588 : bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
     487             :                                               bool DoIt) const {
     488         588 :   MachineFunction &MF = *MBB.getParent();
     489         588 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     490         588 :   unsigned ArgRegsSaveSize = AFI->getArgRegsSaveSize();
     491         588 :   const TargetInstrInfo &TII = *STI.getInstrInfo();
     492             :   const ThumbRegisterInfo *RegInfo =
     493         588 :       static_cast<const ThumbRegisterInfo *>(STI.getRegisterInfo());
     494             : 
     495             :   // If MBBI is a return instruction, or is a tPOP followed by a return
     496             :   // instruction in the successor BB, we may be able to directly restore
     497             :   // LR in the PC.
     498             :   // This is only possible with v5T ops (v4T can't change the Thumb bit via
     499             :   // a POP PC instruction), and only if we do not need to emit any SP update.
     500             :   // Otherwise, we need a temporary register to pop the value
     501             :   // and copy that value into LR.
     502         588 :   auto MBBI = MBB.getFirstTerminator();
     503         588 :   bool CanRestoreDirectly = STI.hasV5TOps() && !ArgRegsSaveSize;
     504             :   if (CanRestoreDirectly) {
     505        1774 :     if (MBBI != MBB.end() && MBBI->getOpcode() != ARM::tB)
     506         872 :       CanRestoreDirectly = (MBBI->getOpcode() == ARM::tBX_RET ||
     507         436 :                             MBBI->getOpcode() == ARM::tPOP_RET);
     508             :     else {
     509           9 :       auto MBBI_prev = MBBI;
     510          18 :       MBBI_prev--;
     511             :       assert(MBBI_prev->getOpcode() == ARM::tPOP);
     512             :       assert(MBB.succ_size() == 1);
     513          36 :       if ((*MBB.succ_begin())->begin()->getOpcode() == ARM::tBX_RET)
     514           8 :         MBBI = MBBI_prev; // Replace the final tPOP with a tPOP_RET.
     515             :       else
     516             :         CanRestoreDirectly = false;
     517             :     }
     518             :   }
     519             : 
     520         151 :   if (CanRestoreDirectly) {
     521        1329 :     if (!DoIt || MBBI->getOpcode() == ARM::tPOP_RET)
     522             :       return true;
     523             :     MachineInstrBuilder MIB =
     524          40 :         BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP_RET))
     525          24 :             .add(predOps(ARMCC::AL));
     526             :     // Copy implicit ops and popped registers, if any.
     527          56 :     for (auto MO: MBBI->operands())
     528          88 :       if (MO.isReg() && (MO.isImplicit() || MO.isDef()))
     529             :         MIB.add(MO);
     530           8 :     MIB.addReg(ARM::PC, RegState::Define);
     531             :     // Erase the old instruction (tBX_RET or tPOP).
     532           8 :     MBB.erase(MBBI);
     533           8 :     return true;
     534             :   }
     535             : 
     536             :   // Look for a temporary register to use.
     537             :   // First, compute the liveness information.
     538         145 :   const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
     539         145 :   LivePhysRegs UsedRegs(TRI);
     540         145 :   UsedRegs.addLiveOuts(MBB);
     541             :   // The semantic of pristines changed recently and now,
     542             :   // the callee-saved registers that are touched in the function
     543             :   // are not part of the pristines set anymore.
     544             :   // Add those callee-saved now.
     545         145 :   const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF);
     546        2578 :   for (unsigned i = 0; CSRegs[i]; ++i)
     547        2433 :     UsedRegs.addReg(CSRegs[i]);
     548             : 
     549         435 :   DebugLoc dl = DebugLoc();
     550         290 :   if (MBBI != MBB.end()) {
     551         282 :     dl = MBBI->getDebugLoc();
     552         141 :     auto InstUpToMBBI = MBB.end();
     553         427 :     while (InstUpToMBBI != MBBI)
     554             :       // The pre-decrement is on purpose here.
     555             :       // We want to have the liveness right before MBBI.
     556         286 :       UsedRegs.stepBackward(*--InstUpToMBBI);
     557             :   }
     558             : 
     559             :   // Look for a register that can be directly use in the POP.
     560         145 :   unsigned PopReg = 0;
     561             :   // And some temporary register, just in case.
     562         145 :   unsigned TemporaryReg = 0;
     563             :   BitVector PopFriendly =
     564         435 :       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::tGPRRegClassID));
     565             :   assert(PopFriendly.any() && "No allocatable pop-friendly register?!");
     566             :   // Rebuild the GPRs from the high registers because they are removed
     567             :   // form the GPR reg class for thumb1.
     568             :   BitVector GPRsNoLRSP =
     569         435 :       TRI.getAllocatableSet(MF, TRI.getRegClass(ARM::hGPRRegClassID));
     570         145 :   GPRsNoLRSP |= PopFriendly;
     571         145 :   GPRsNoLRSP.reset(ARM::LR);
     572         145 :   GPRsNoLRSP.reset(ARM::SP);
     573         145 :   GPRsNoLRSP.reset(ARM::PC);
     574         437 :   for (unsigned Register : GPRsNoLRSP.set_bits()) {
     575         292 :     if (!UsedRegs.contains(Register)) {
     576             :       // Remember the first pop-friendly register and exit.
     577         145 :       if (PopFriendly.test(Register)) {
     578             :         PopReg = Register;
     579             :         TemporaryReg = 0;
     580             :         break;
     581             :       }
     582             :       // Otherwise, remember that the register will be available to
     583             :       // save a pop-friendly register.
     584             :       TemporaryReg = Register;
     585             :     }
     586             :   }
     587             : 
     588         145 :   if (!DoIt && !PopReg && !TemporaryReg)
     589             :     return false;
     590             : 
     591             :   assert((PopReg || TemporaryReg) && "Cannot get LR");
     592             : 
     593         145 :   if (TemporaryReg) {
     594             :     assert(!PopReg && "Unnecessary MOV is about to be inserted");
     595           5 :     PopReg = PopFriendly.find_first();
     596          15 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     597           5 :         .addReg(TemporaryReg, RegState::Define)
     598           5 :         .addReg(PopReg, RegState::Kill)
     599          15 :         .add(predOps(ARMCC::AL));
     600             :   }
     601             : 
     602         572 :   if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPOP_RET) {
     603             :     // We couldn't use the direct restoration above, so
     604             :     // perform the opposite conversion: tPOP_RET to tPOP.
     605             :     MachineInstrBuilder MIB =
     606           0 :         BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII.get(ARM::tPOP))
     607           0 :             .add(predOps(ARMCC::AL));
     608           0 :     bool Popped = false;
     609           0 :     for (auto MO: MBBI->operands())
     610           0 :       if (MO.isReg() && (MO.isImplicit() || MO.isDef()) &&
     611           0 :           MO.getReg() != ARM::PC) {
     612           0 :         MIB.add(MO);
     613           0 :         if (!MO.isImplicit())
     614           0 :           Popped = true;
     615             :       }
     616             :     // Is there anything left to pop?
     617           0 :     if (!Popped)
     618           0 :       MBB.erase(MIB.getInstr());
     619             :     // Erase the old instruction.
     620           0 :     MBB.erase(MBBI);
     621           0 :     MBBI = BuildMI(MBB, MBB.end(), dl, TII.get(ARM::tBX_RET))
     622           0 :                .add(predOps(ARMCC::AL));
     623             :   }
     624             : 
     625             :   assert(PopReg && "Do not know how to get LR");
     626         435 :   BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))
     627         580 :       .add(predOps(ARMCC::AL))
     628         145 :       .addReg(PopReg, RegState::Define);
     629             : 
     630         290 :   emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, ArgRegsSaveSize);
     631             : 
     632         435 :   BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     633         145 :       .addReg(ARM::LR, RegState::Define)
     634         145 :       .addReg(PopReg, RegState::Kill)
     635         435 :       .add(predOps(ARMCC::AL));
     636             : 
     637         145 :   if (TemporaryReg)
     638          15 :     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
     639           5 :         .addReg(PopReg, RegState::Define)
     640           5 :         .addReg(TemporaryReg, RegState::Kill)
     641          15 :         .add(predOps(ARMCC::AL));
     642             : 
     643             :   return true;
     644             : }
     645             : 
     646             : typedef std::bitset<ARM::NUM_TARGET_REGS> ARMRegSet;
     647             : 
     648             : // Return the first iteraror after CurrentReg which is present in EnabledRegs,
     649             : // or OrderEnd if no further registers are in that set. This does not advance
     650             : // the iterator fiorst, so returns CurrentReg if it is in EnabledRegs.
     651             : static const unsigned *findNextOrderedReg(const unsigned *CurrentReg,
     652             :                                           const ARMRegSet &EnabledRegs,
     653             :                                           const unsigned *OrderEnd) {
     654       10575 :   while (CurrentReg != OrderEnd && !EnabledRegs[*CurrentReg])
     655        4473 :     ++CurrentReg;
     656             :   return CurrentReg;
     657             : }
     658             : 
     659         538 : bool Thumb1FrameLowering::
     660             : spillCalleeSavedRegisters(MachineBasicBlock &MBB,
     661             :                           MachineBasicBlock::iterator MI,
     662             :                           const std::vector<CalleeSavedInfo> &CSI,
     663             :                           const TargetRegisterInfo *TRI) const {
     664         538 :   if (CSI.empty())
     665             :     return false;
     666             : 
     667         538 :   DebugLoc DL;
     668         538 :   const TargetInstrInfo &TII = *STI.getInstrInfo();
     669         538 :   MachineFunction &MF = *MBB.getParent();
     670             :   const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
     671         538 :       MF.getSubtarget().getRegisterInfo());
     672             : 
     673         538 :   ARMRegSet LoRegsToSave; // r0-r7, lr
     674         538 :   ARMRegSet HiRegsToSave; // r8-r11
     675         538 :   ARMRegSet CopyRegs;     // Registers which can be used after pushing
     676             :                           // LoRegs for saving HiRegs.
     677             : 
     678        1076 :   for (unsigned i = CSI.size(); i != 0; --i) {
     679        2892 :     unsigned Reg = CSI[i-1].getReg();
     680             : 
     681        2892 :     if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
     682        4176 :       LoRegsToSave[Reg] = true;
     683         108 :     } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
     684         162 :       HiRegsToSave[Reg] = true;
     685             :     } else {
     686           0 :       llvm_unreachable("callee-saved register of unexpected class");
     687             :     }
     688             : 
     689        4874 :     if ((ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) &&
     690        4228 :         !MF.getRegInfo().isLiveIn(Reg) &&
     691        1761 :         !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
     692        3819 :       CopyRegs[Reg] = true;
     693             :   }
     694             : 
     695             :   // Unused argument registers can be used for the high register saving.
     696        4842 :   for (unsigned ArgReg : {ARM::R0, ARM::R1, ARM::R2, ARM::R3})
     697        2152 :     if (!MF.getRegInfo().isLiveIn(ArgReg))
     698        4887 :       CopyRegs[ArgReg] = true;
     699             : 
     700             :   // Push the low registers and lr
     701         538 :   const MachineRegisterInfo &MRI = MF.getRegInfo();
     702         538 :   if (!LoRegsToSave.none()) {
     703             :     MachineInstrBuilder MIB =
     704        2680 :         BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
     705        3752 :     for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
     706        8040 :       if (LoRegsToSave[Reg]) {
     707        1392 :         bool isKill = !MRI.isLiveIn(Reg);
     708        2782 :         if (isKill && !MRI.isReserved(Reg))
     709        1259 :           MBB.addLiveIn(Reg);
     710             : 
     711        1392 :         MIB.addReg(Reg, getKillRegState(isKill));
     712             :       }
     713             :     }
     714         536 :     MIB.setMIFlags(MachineInstr::FrameSetup);
     715             :   }
     716             : 
     717             :   // Push the high registers. There are no store instructions that can access
     718             :   // these registers directly, so we have to move them to low registers, and
     719             :   // push them. This might take multiple pushes, as it is possible for there to
     720             :   // be fewer low registers available than high registers which need saving.
     721             : 
     722             :   // These are in reverse order so that in the case where we need to use
     723             :   // multiple PUSH instructions, the order of the registers on the stack still
     724             :   // matches the unwind info. They need to be swicthed back to ascending order
     725             :   // before adding to the PUSH instruction.
     726             :   static const unsigned AllCopyRegs[] = {ARM::LR, ARM::R7, ARM::R6,
     727             :                                          ARM::R5, ARM::R4, ARM::R3,
     728             :                                          ARM::R2, ARM::R1, ARM::R0};
     729             :   static const unsigned AllHighRegs[] = {ARM::R11, ARM::R10, ARM::R9, ARM::R8};
     730             : 
     731         538 :   const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
     732         538 :   const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
     733             : 
     734             :   // Find the first register to save.
     735         538 :   const unsigned *HiRegToSave = findNextOrderedReg(
     736             :       std::begin(AllHighRegs), HiRegsToSave, AllHighRegsEnd);
     737             : 
     738         576 :   while (HiRegToSave != AllHighRegsEnd) {
     739             :     // Find the first low register to use.
     740             :     const unsigned *CopyReg =
     741          19 :         findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
     742             : 
     743             :     // Create the PUSH, but don't insert it yet (the MOVs need to come first).
     744             :     MachineInstrBuilder PushMIB =
     745         114 :         BuildMI(MF, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
     746             : 
     747          19 :     SmallVector<unsigned, 4> RegsToPush;
     748          73 :     while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
     749         162 :       if (HiRegsToSave[*HiRegToSave]) {
     750          54 :         bool isKill = !MRI.isLiveIn(*HiRegToSave);
     751         108 :         if (isKill && !MRI.isReserved(*HiRegToSave))
     752          54 :           MBB.addLiveIn(*HiRegToSave);
     753             : 
     754             :         // Emit a MOV from the high reg to the low reg.
     755         162 :         BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
     756          54 :             .addReg(*CopyReg, RegState::Define)
     757          54 :             .addReg(*HiRegToSave, getKillRegState(isKill))
     758         162 :             .add(predOps(ARMCC::AL));
     759             : 
     760             :         // Record the register that must be added to the PUSH.
     761          54 :         RegsToPush.push_back(*CopyReg);
     762             : 
     763         108 :         CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
     764          54 :         HiRegToSave =
     765             :             findNextOrderedReg(++HiRegToSave, HiRegsToSave, AllHighRegsEnd);
     766             :       }
     767             :     }
     768             : 
     769             :     // Add the low registers to the PUSH, in ascending order.
     770         184 :     for (unsigned Reg : llvm::reverse(RegsToPush))
     771          54 :       PushMIB.addReg(Reg, RegState::Kill);
     772             : 
     773             :     // Insert the PUSH instruction after the MOVs.
     774          38 :     MBB.insert(MI, PushMIB);
     775             :   }
     776             : 
     777         538 :   return true;
     778             : }
     779             : 
     780         590 : bool Thumb1FrameLowering::
     781             : restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
     782             :                             MachineBasicBlock::iterator MI,
     783             :                             std::vector<CalleeSavedInfo> &CSI,
     784             :                             const TargetRegisterInfo *TRI) const {
     785         590 :   if (CSI.empty())
     786             :     return false;
     787             : 
     788         590 :   MachineFunction &MF = *MBB.getParent();
     789         590 :   ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     790         590 :   const TargetInstrInfo &TII = *STI.getInstrInfo();
     791             :   const ARMBaseRegisterInfo *RegInfo = static_cast<const ARMBaseRegisterInfo *>(
     792         590 :       MF.getSubtarget().getRegisterInfo());
     793             : 
     794         590 :   bool isVarArg = AFI->getArgRegsSaveSize() > 0;
     795        1770 :   DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
     796             : 
     797         590 :   ARMRegSet LoRegsToRestore;
     798         590 :   ARMRegSet HiRegsToRestore;
     799             :   // Low registers (r0-r7) which can be used to restore the high registers.
     800         590 :   ARMRegSet CopyRegs;
     801             : 
     802        3938 :   for (CalleeSavedInfo I : CSI) {
     803        1578 :     unsigned Reg = I.getReg();
     804             : 
     805        3156 :     if (ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR) {
     806        4572 :       LoRegsToRestore[Reg] = true;
     807         108 :     } else if (ARM::hGPRRegClass.contains(Reg) && Reg != ARM::LR) {
     808         162 :       HiRegsToRestore[Reg] = true;
     809             :     } else {
     810           0 :       llvm_unreachable("callee-saved register of unexpected class");
     811             :     }
     812             : 
     813             :     // If this is a low register not used as the frame pointer, we may want to
     814             :     // use it for restoring the high registers.
     815        4092 :     if ((ARM::tGPRRegClass.contains(Reg)) &&
     816        1217 :         !(hasFP(MF) && Reg == RegInfo->getFrameRegister(MF)))
     817        2433 :       CopyRegs[Reg] = true;
     818             :   }
     819             : 
     820             :   // If this is a return block, we may be able to use some unused return value
     821             :   // registers for restoring the high regs.
     822         590 :   auto Terminator = MBB.getFirstTerminator();
     823        2348 :   if (Terminator != MBB.end() && Terminator->getOpcode() == ARM::tBX_RET) {
     824        1138 :     CopyRegs[ARM::R0] = true;
     825        1138 :     CopyRegs[ARM::R1] = true;
     826        1138 :     CopyRegs[ARM::R2] = true;
     827        1138 :     CopyRegs[ARM::R3] = true;
     828        1405 :     for (auto Op : Terminator->implicit_operands()) {
     829         267 :       if (Op.isReg())
     830         801 :         CopyRegs[Op.getReg()] = false;
     831             :     }
     832             :   }
     833             : 
     834             :   static const unsigned AllCopyRegs[] = {ARM::R0, ARM::R1, ARM::R2, ARM::R3,
     835             :                                          ARM::R4, ARM::R5, ARM::R6, ARM::R7};
     836             :   static const unsigned AllHighRegs[] = {ARM::R8, ARM::R9, ARM::R10, ARM::R11};
     837             : 
     838         590 :   const unsigned *AllCopyRegsEnd = std::end(AllCopyRegs);
     839         590 :   const unsigned *AllHighRegsEnd = std::end(AllHighRegs);
     840             : 
     841             :   // Find the first register to restore.
     842         590 :   auto HiRegToRestore = findNextOrderedReg(std::begin(AllHighRegs),
     843             :                                            HiRegsToRestore, AllHighRegsEnd);
     844             : 
     845         628 :   while (HiRegToRestore != AllHighRegsEnd) {
     846             :     assert(!CopyRegs.none());
     847             :     // Find the first low register to use.
     848             :     auto CopyReg =
     849          19 :         findNextOrderedReg(std::begin(AllCopyRegs), CopyRegs, AllCopyRegsEnd);
     850             : 
     851             :     // Create the POP instruction.
     852             :     MachineInstrBuilder PopMIB =
     853          95 :         BuildMI(MBB, MI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
     854             : 
     855          73 :     while (HiRegToRestore != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
     856             :       // Add the low register to the POP.
     857          54 :       PopMIB.addReg(*CopyReg, RegState::Define);
     858             : 
     859             :       // Create the MOV from low to high register.
     860         162 :       BuildMI(MBB, MI, DL, TII.get(ARM::tMOVr))
     861          54 :           .addReg(*HiRegToRestore, RegState::Define)
     862          54 :           .addReg(*CopyReg, RegState::Kill)
     863         162 :           .add(predOps(ARMCC::AL));
     864             : 
     865         108 :       CopyReg = findNextOrderedReg(++CopyReg, CopyRegs, AllCopyRegsEnd);
     866          54 :       HiRegToRestore =
     867             :           findNextOrderedReg(++HiRegToRestore, HiRegsToRestore, AllHighRegsEnd);
     868             :     }
     869             :   }
     870             : 
     871             :   MachineInstrBuilder MIB =
     872        3540 :       BuildMI(MF, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL));
     873             : 
     874         590 :   bool NeedsPop = false;
     875        1180 :   for (unsigned i = CSI.size(); i != 0; --i) {
     876        3156 :     unsigned Reg = CSI[i-1].getReg();
     877             : 
     878             :     // High registers (excluding lr) have already been dealt with
     879        3210 :     if (!(ARM::tGPRRegClass.contains(Reg) || Reg == ARM::LR))
     880          54 :       continue;
     881             : 
     882        1524 :     if (Reg == ARM::LR) {
     883         608 :       if (MBB.succ_empty()) {
     884             :         // Special epilogue for vararg functions. See emitEpilogue
     885         568 :         if (isVarArg)
     886          13 :           continue;
     887             :         // ARMv4T requires BX, see emitEpilogue
     888         555 :         if (!STI.hasV5TOps())
     889         120 :           continue;
     890             :         // Tailcall optimization failed; change TCRETURN to a tBL
     891        1304 :         if (MI->getOpcode() == ARM::TCRETURNdi ||
     892         434 :             MI->getOpcode() == ARM::TCRETURNri) {
     893           1 :           unsigned Opcode = MI->getOpcode() == ARM::TCRETURNdi
     894           1 :                             ? ARM::tBL : ARM::tBLXr;
     895           3 :           MachineInstrBuilder BL = BuildMI(MF, DL, TII.get(Opcode));
     896           3 :           BL.add(predOps(ARMCC::AL));
     897           2 :           BL.add(MI->getOperand(0));
     898           2 :           MBB.insert(MI, &*BL);
     899             :         }
     900         435 :         Reg = ARM::PC;
     901        1305 :         (*MIB).setDesc(TII.get(ARM::tPOP_RET));
     902         870 :         if (MI != MBB.end())
     903         435 :           MIB.copyImplicitOps(*MI);
     904         435 :         MI = MBB.erase(MI);
     905             :       } else
     906             :         // LR may only be popped into PC, as part of return sequence.
     907             :         // If this isn't the return sequence, we'll need emitPopSpecialFixUp
     908             :         // to restore LR the hard way.
     909          20 :         continue;
     910             :     }
     911        1371 :     MIB.addReg(Reg, getDefRegState(true));
     912        1371 :     NeedsPop = true;
     913             :   }
     914             : 
     915             :   // It's illegal to emit pop instruction without operands.
     916         590 :   if (NeedsPop)
     917         581 :     MBB.insert(MI, &*MIB);
     918             :   else
     919           9 :     MF.DeleteMachineInstr(MIB);
     920             : 
     921         590 :   return true;
     922             : }

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