LCOV - code coverage report
Current view: top level - lib/Target/ARM - Thumb1InstrInfo.cpp (source / functions) Hit Total Coverage
Test: llvm-toolchain.info Lines: 60 63 95.2 %
Date: 2018-02-23 05:02:05 Functions: 7 8 87.5 %
Legend: Lines: hit not hit

          Line data    Source code
       1             : //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
       2             : //
       3             : //                     The LLVM Compiler Infrastructure
       4             : //
       5             : // This file is distributed under the University of Illinois Open Source
       6             : // License. See LICENSE.TXT for details.
       7             : //
       8             : //===----------------------------------------------------------------------===//
       9             : //
      10             : // This file contains the Thumb-1 implementation of the TargetInstrInfo class.
      11             : //
      12             : //===----------------------------------------------------------------------===//
      13             : 
      14             : #include "Thumb1InstrInfo.h"
      15             : #include "ARMSubtarget.h"
      16             : #include "llvm/CodeGen/MachineFrameInfo.h"
      17             : #include "llvm/CodeGen/MachineInstrBuilder.h"
      18             : #include "llvm/CodeGen/MachineMemOperand.h"
      19             : #include "llvm/MC/MCInst.h"
      20             : 
      21             : using namespace llvm;
      22             : 
      23         459 : Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
      24         459 :     : ARMBaseInstrInfo(STI), RI() {}
      25             : 
      26             : /// Return the noop instruction to use for a noop.
      27           1 : void Thumb1InstrInfo::getNoop(MCInst &NopInst) const {
      28             :   NopInst.setOpcode(ARM::tMOVr);
      29           2 :   NopInst.addOperand(MCOperand::createReg(ARM::R8));
      30           2 :   NopInst.addOperand(MCOperand::createReg(ARM::R8));
      31           2 :   NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
      32           2 :   NopInst.addOperand(MCOperand::createReg(0));
      33           1 : }
      34             : 
      35           0 : unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
      36           0 :   return 0;
      37             : }
      38             : 
      39        1053 : void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
      40             :                                   MachineBasicBlock::iterator I,
      41             :                                   const DebugLoc &DL, unsigned DestReg,
      42             :                                   unsigned SrcReg, bool KillSrc) const {
      43             :   // Need to check the arch.
      44        1053 :   MachineFunction &MF = *MBB.getParent();
      45        1053 :   const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
      46             : 
      47             :   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
      48             :          "Thumb1 can only copy GPR registers");
      49             : 
      50        1941 :   if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
      51        1765 :       || !ARM::tGPRRegClass.contains(DestReg))
      52        2118 :     BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
      53         706 :         .addReg(SrcReg, getKillRegState(KillSrc))
      54         706 :         .add(predOps(ARMCC::AL));
      55             :   else {
      56             :     // FIXME: Can also use 'mov hi, $src; mov $dst, hi',
      57             :     // with hi as either r10 or r11.
      58             : 
      59         347 :     const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
      60         347 :     if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
      61             :         == MachineBasicBlock::LQR_Dead) {
      62        1008 :       BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
      63         336 :           .addReg(SrcReg, getKillRegState(KillSrc))
      64         336 :           ->addRegisterDead(ARM::CPSR, RegInfo);
      65         336 :       return;
      66             :     }
      67             : 
      68             :     // 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
      69          33 :     BuildMI(MBB, I, DL, get(ARM::tPUSH))
      70          11 :         .add(predOps(ARMCC::AL))
      71          11 :         .addReg(SrcReg, getKillRegState(KillSrc));
      72          33 :     BuildMI(MBB, I, DL, get(ARM::tPOP))
      73          11 :         .add(predOps(ARMCC::AL))
      74          11 :         .addReg(DestReg, getDefRegState(true));
      75             :   }
      76             : }
      77             : 
      78         226 : void Thumb1InstrInfo::
      79             : storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
      80             :                     unsigned SrcReg, bool isKill, int FI,
      81             :                     const TargetRegisterClass *RC,
      82             :                     const TargetRegisterInfo *TRI) const {
      83             :   assert((RC == &ARM::tGPRRegClass ||
      84             :           (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
      85             :            isARMLowRegister(SrcReg))) && "Unknown regclass!");
      86             : 
      87         226 :   if (RC == &ARM::tGPRRegClass ||
      88             :       (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
      89             :        isARMLowRegister(SrcReg))) {
      90         226 :     DebugLoc DL;
      91         226 :     if (I != MBB.end()) DL = I->getDebugLoc();
      92             : 
      93         226 :     MachineFunction &MF = *MBB.getParent();
      94         226 :     MachineFrameInfo &MFI = MF.getFrameInfo();
      95         452 :     MachineMemOperand *MMO = MF.getMachineMemOperand(
      96             :         MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
      97         226 :         MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
      98         678 :     BuildMI(MBB, I, DL, get(ARM::tSTRspi))
      99         226 :         .addReg(SrcReg, getKillRegState(isKill))
     100             :         .addFrameIndex(FI)
     101             :         .addImm(0)
     102             :         .addMemOperand(MMO)
     103         226 :         .add(predOps(ARMCC::AL));
     104             :   }
     105         226 : }
     106             : 
     107         338 : void Thumb1InstrInfo::
     108             : loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     109             :                      unsigned DestReg, int FI,
     110             :                      const TargetRegisterClass *RC,
     111             :                      const TargetRegisterInfo *TRI) const {
     112             :   assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
     113             :           (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
     114             :            isARMLowRegister(DestReg))) && "Unknown regclass!");
     115             : 
     116         338 :   if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
     117             :       (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
     118             :        isARMLowRegister(DestReg))) {
     119         338 :     DebugLoc DL;
     120             :     if (I != MBB.end()) DL = I->getDebugLoc();
     121             : 
     122         338 :     MachineFunction &MF = *MBB.getParent();
     123         338 :     MachineFrameInfo &MFI = MF.getFrameInfo();
     124         676 :     MachineMemOperand *MMO = MF.getMachineMemOperand(
     125             :         MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
     126         338 :         MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
     127         676 :     BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
     128             :         .addFrameIndex(FI)
     129             :         .addImm(0)
     130             :         .addMemOperand(MMO)
     131         338 :         .add(predOps(ARMCC::AL));
     132             :   }
     133         338 : }
     134             : 
     135           6 : void Thumb1InstrInfo::expandLoadStackGuard(
     136             :     MachineBasicBlock::iterator MI) const {
     137           6 :   MachineFunction &MF = *MI->getParent()->getParent();
     138           6 :   const TargetMachine &TM = MF.getTarget();
     139           6 :   if (TM.isPositionIndependent())
     140           2 :     expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi);
     141             :   else
     142           4 :     expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
     143           6 : }
     144             : 
     145           4 : bool Thumb1InstrInfo::canCopyGluedNodeDuringSchedule(SDNode *N) const {
     146             :   // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
     147             :   // but this is not always possible there, so allow the Scheduler to clone tADCS and tSBCS
     148             :   // even if they have glue.
     149             :   // FIXME. Actually implement the cross-copy where it is possible (post v6)
     150             :   // because these copies entail more spilling.
     151           4 :   unsigned Opcode = N->getMachineOpcode();
     152           4 :   if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
     153             :     return true;
     154             : 
     155           0 :   return false;
     156             : }

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