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1 : //===- ThumbRegisterInfo.h - Thumb Register Information Impl -*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file contains the Thumb implementation of the TargetRegisterInfo
11 : // class. With the exception of emitLoadConstPool Thumb2 tracks
12 : // ARMBaseRegisterInfo, Thumb1 overloads the functions below.
13 : //
14 : //===----------------------------------------------------------------------===//
15 :
16 : #ifndef LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
17 : #define LLVM_LIB_TARGET_ARM_THUMB1REGISTERINFO_H
18 :
19 : #include "ARMBaseRegisterInfo.h"
20 : #include "llvm/CodeGen/TargetRegisterInfo.h"
21 :
22 : namespace llvm {
23 : class ARMSubtarget;
24 : class ARMBaseInstrInfo;
25 :
26 1912 : struct ThumbRegisterInfo : public ARMBaseRegisterInfo {
27 : public:
28 : ThumbRegisterInfo();
29 :
30 : const TargetRegisterClass *
31 : getLargestLegalSuperClass(const TargetRegisterClass *RC,
32 : const MachineFunction &MF) const override;
33 :
34 : const TargetRegisterClass *
35 : getPointerRegClass(const MachineFunction &MF,
36 : unsigned Kind = 0) const override;
37 :
38 : /// emitLoadConstPool - Emits a load from constpool to materialize the
39 : /// specified immediate.
40 : void
41 : emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
42 : const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
43 : int Val, ARMCC::CondCodes Pred = ARMCC::AL,
44 : unsigned PredReg = 0,
45 : unsigned MIFlags = MachineInstr::NoFlags) const override;
46 :
47 : // rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
48 : // however much remains to be handled. Return 'true' if no further
49 : // work is required.
50 : bool rewriteFrameIndex(MachineBasicBlock::iterator II, unsigned FrameRegIdx,
51 : unsigned FrameReg, int &Offset,
52 : const ARMBaseInstrInfo &TII) const;
53 : void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
54 : int64_t Offset) const override;
55 : bool saveScavengerRegister(MachineBasicBlock &MBB,
56 : MachineBasicBlock::iterator I,
57 : MachineBasicBlock::iterator &UseMI,
58 : const TargetRegisterClass *RC,
59 : unsigned Reg) const override;
60 : void eliminateFrameIndex(MachineBasicBlock::iterator II,
61 : int SPAdj, unsigned FIOperandNum,
62 : RegScavenger *RS = nullptr) const override;
63 : };
64 : }
65 :
66 : #endif
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