Bug Summary

File:lib/Target/AArch64/AArch64ISelLowering.cpp
Warning:line 7558, column 29
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AArch64ISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/lib/Target/AArch64 -I /build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64 -I /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn325118/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/lib/Target/AArch64 -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-14-150435-17243-1 -x c++ /build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp

/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp

1//===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the AArch64TargetLowering class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64ISelLowering.h"
15#include "AArch64CallingConvention.h"
16#include "AArch64MachineFunctionInfo.h"
17#include "AArch64PerfectShuffle.h"
18#include "AArch64RegisterInfo.h"
19#include "AArch64Subtarget.h"
20#include "MCTargetDesc/AArch64AddressingModes.h"
21#include "Utils/AArch64BaseInfo.h"
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/APInt.h"
24#include "llvm/ADT/ArrayRef.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SmallVector.h"
27#include "llvm/ADT/Statistic.h"
28#include "llvm/ADT/StringRef.h"
29#include "llvm/ADT/StringSwitch.h"
30#include "llvm/ADT/Triple.h"
31#include "llvm/ADT/Twine.h"
32#include "llvm/Analysis/VectorUtils.h"
33#include "llvm/CodeGen/CallingConvLower.h"
34#include "llvm/CodeGen/MachineBasicBlock.h"
35#include "llvm/CodeGen/MachineFrameInfo.h"
36#include "llvm/CodeGen/MachineFunction.h"
37#include "llvm/CodeGen/MachineInstr.h"
38#include "llvm/CodeGen/MachineInstrBuilder.h"
39#include "llvm/CodeGen/MachineMemOperand.h"
40#include "llvm/CodeGen/MachineRegisterInfo.h"
41#include "llvm/CodeGen/MachineValueType.h"
42#include "llvm/CodeGen/RuntimeLibcalls.h"
43#include "llvm/CodeGen/SelectionDAG.h"
44#include "llvm/CodeGen/SelectionDAGNodes.h"
45#include "llvm/CodeGen/TargetCallingConv.h"
46#include "llvm/CodeGen/TargetInstrInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/IR/Attributes.h"
49#include "llvm/IR/Constants.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DebugLoc.h"
52#include "llvm/IR/DerivedTypes.h"
53#include "llvm/IR/Function.h"
54#include "llvm/IR/GetElementPtrTypeIterator.h"
55#include "llvm/IR/GlobalValue.h"
56#include "llvm/IR/IRBuilder.h"
57#include "llvm/IR/Instruction.h"
58#include "llvm/IR/Instructions.h"
59#include "llvm/IR/Intrinsics.h"
60#include "llvm/IR/Module.h"
61#include "llvm/IR/OperandTraits.h"
62#include "llvm/IR/Type.h"
63#include "llvm/IR/Use.h"
64#include "llvm/IR/Value.h"
65#include "llvm/MC/MCRegisterInfo.h"
66#include "llvm/Support/Casting.h"
67#include "llvm/Support/CodeGen.h"
68#include "llvm/Support/CommandLine.h"
69#include "llvm/Support/Compiler.h"
70#include "llvm/Support/Debug.h"
71#include "llvm/Support/ErrorHandling.h"
72#include "llvm/Support/KnownBits.h"
73#include "llvm/Support/MathExtras.h"
74#include "llvm/Support/raw_ostream.h"
75#include "llvm/Target/TargetMachine.h"
76#include "llvm/Target/TargetOptions.h"
77#include <algorithm>
78#include <bitset>
79#include <cassert>
80#include <cctype>
81#include <cstdint>
82#include <cstdlib>
83#include <iterator>
84#include <limits>
85#include <tuple>
86#include <utility>
87#include <vector>
88
89using namespace llvm;
90
91#define DEBUG_TYPE"aarch64-lower" "aarch64-lower"
92
93STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"aarch64-lower", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
94STATISTIC(NumShiftInserts, "Number of vector shift inserts")static llvm::Statistic NumShiftInserts = {"aarch64-lower", "NumShiftInserts"
, "Number of vector shift inserts", {0}, {false}}
;
95STATISTIC(NumOptimizedImms, "Number of times immediates were optimized")static llvm::Statistic NumOptimizedImms = {"aarch64-lower", "NumOptimizedImms"
, "Number of times immediates were optimized", {0}, {false}}
;
96
97static cl::opt<bool>
98EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
99 cl::desc("Allow AArch64 SLI/SRI formation"),
100 cl::init(false));
101
102// FIXME: The necessary dtprel relocations don't seem to be supported
103// well in the GNU bfd and gold linkers at the moment. Therefore, by
104// default, for now, fall back to GeneralDynamic code generation.
105cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
106 "aarch64-elf-ldtls-generation", cl::Hidden,
107 cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
108 cl::init(false));
109
110static cl::opt<bool>
111EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden,
112 cl::desc("Enable AArch64 logical imm instruction "
113 "optimization"),
114 cl::init(true));
115
116/// Value type used for condition codes.
117static const MVT MVT_CC = MVT::i32;
118
119AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
120 const AArch64Subtarget &STI)
121 : TargetLowering(TM), Subtarget(&STI) {
122 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
123 // we have to make something up. Arbitrarily, choose ZeroOrOne.
124 setBooleanContents(ZeroOrOneBooleanContent);
125 // When comparing vectors the result sets the different elements in the
126 // vector to all-one or all-zero.
127 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
128
129 // Set up the register classes.
130 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
131 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
132
133 if (Subtarget->hasFPARMv8()) {
134 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
135 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
136 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
137 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
138 }
139
140 if (Subtarget->hasNEON()) {
141 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
142 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
143 // Someone set us up the NEON.
144 addDRTypeForNEON(MVT::v2f32);
145 addDRTypeForNEON(MVT::v8i8);
146 addDRTypeForNEON(MVT::v4i16);
147 addDRTypeForNEON(MVT::v2i32);
148 addDRTypeForNEON(MVT::v1i64);
149 addDRTypeForNEON(MVT::v1f64);
150 addDRTypeForNEON(MVT::v4f16);
151
152 addQRTypeForNEON(MVT::v4f32);
153 addQRTypeForNEON(MVT::v2f64);
154 addQRTypeForNEON(MVT::v16i8);
155 addQRTypeForNEON(MVT::v8i16);
156 addQRTypeForNEON(MVT::v4i32);
157 addQRTypeForNEON(MVT::v2i64);
158 addQRTypeForNEON(MVT::v8f16);
159 }
160
161 // Compute derived properties from the register classes
162 computeRegisterProperties(Subtarget->getRegisterInfo());
163
164 // Provide all sorts of operation actions
165 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
166 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
167 setOperationAction(ISD::SETCC, MVT::i32, Custom);
168 setOperationAction(ISD::SETCC, MVT::i64, Custom);
169 setOperationAction(ISD::SETCC, MVT::f16, Custom);
170 setOperationAction(ISD::SETCC, MVT::f32, Custom);
171 setOperationAction(ISD::SETCC, MVT::f64, Custom);
172 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
173 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
174 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
175 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
176 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
177 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
178 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
179 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
180 setOperationAction(ISD::SELECT, MVT::i32, Custom);
181 setOperationAction(ISD::SELECT, MVT::i64, Custom);
182 setOperationAction(ISD::SELECT, MVT::f16, Custom);
183 setOperationAction(ISD::SELECT, MVT::f32, Custom);
184 setOperationAction(ISD::SELECT, MVT::f64, Custom);
185 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
186 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
187 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
188 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
189 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
190 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
191 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
192
193 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
194 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
195 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
196
197 setOperationAction(ISD::FREM, MVT::f32, Expand);
198 setOperationAction(ISD::FREM, MVT::f64, Expand);
199 setOperationAction(ISD::FREM, MVT::f80, Expand);
200
201 // Custom lowering hooks are needed for XOR
202 // to fold it into CSINC/CSINV.
203 setOperationAction(ISD::XOR, MVT::i32, Custom);
204 setOperationAction(ISD::XOR, MVT::i64, Custom);
205
206 // Virtually no operation on f128 is legal, but LLVM can't expand them when
207 // there's a valid register class, so we need custom operations in most cases.
208 setOperationAction(ISD::FABS, MVT::f128, Expand);
209 setOperationAction(ISD::FADD, MVT::f128, Custom);
210 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
211 setOperationAction(ISD::FCOS, MVT::f128, Expand);
212 setOperationAction(ISD::FDIV, MVT::f128, Custom);
213 setOperationAction(ISD::FMA, MVT::f128, Expand);
214 setOperationAction(ISD::FMUL, MVT::f128, Custom);
215 setOperationAction(ISD::FNEG, MVT::f128, Expand);
216 setOperationAction(ISD::FPOW, MVT::f128, Expand);
217 setOperationAction(ISD::FREM, MVT::f128, Expand);
218 setOperationAction(ISD::FRINT, MVT::f128, Expand);
219 setOperationAction(ISD::FSIN, MVT::f128, Expand);
220 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
221 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
222 setOperationAction(ISD::FSUB, MVT::f128, Custom);
223 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
224 setOperationAction(ISD::SETCC, MVT::f128, Custom);
225 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
226 setOperationAction(ISD::SELECT, MVT::f128, Custom);
227 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
228 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
229
230 // Lowering for many of the conversions is actually specified by the non-f128
231 // type. The LowerXXX function will be trivial when f128 isn't involved.
232 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
233 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
234 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
235 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
236 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
237 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
238 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
239 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
240 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
241 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
242 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
243 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
244 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
245 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
246
247 // Variable arguments.
248 setOperationAction(ISD::VASTART, MVT::Other, Custom);
249 setOperationAction(ISD::VAARG, MVT::Other, Custom);
250 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
251 setOperationAction(ISD::VAEND, MVT::Other, Expand);
252
253 // Variable-sized objects.
254 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
255 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
256 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
257
258 // Constant pool entries
259 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
260
261 // BlockAddress
262 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
263
264 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
265 setOperationAction(ISD::ADDC, MVT::i32, Custom);
266 setOperationAction(ISD::ADDE, MVT::i32, Custom);
267 setOperationAction(ISD::SUBC, MVT::i32, Custom);
268 setOperationAction(ISD::SUBE, MVT::i32, Custom);
269 setOperationAction(ISD::ADDC, MVT::i64, Custom);
270 setOperationAction(ISD::ADDE, MVT::i64, Custom);
271 setOperationAction(ISD::SUBC, MVT::i64, Custom);
272 setOperationAction(ISD::SUBE, MVT::i64, Custom);
273
274 // AArch64 lacks both left-rotate and popcount instructions.
275 setOperationAction(ISD::ROTL, MVT::i32, Expand);
276 setOperationAction(ISD::ROTL, MVT::i64, Expand);
277 for (MVT VT : MVT::vector_valuetypes()) {
278 setOperationAction(ISD::ROTL, VT, Expand);
279 setOperationAction(ISD::ROTR, VT, Expand);
280 }
281
282 // AArch64 doesn't have {U|S}MUL_LOHI.
283 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
284 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
285
286 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
287 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
288
289 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
290 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
291 for (MVT VT : MVT::vector_valuetypes()) {
292 setOperationAction(ISD::SDIVREM, VT, Expand);
293 setOperationAction(ISD::UDIVREM, VT, Expand);
294 }
295 setOperationAction(ISD::SREM, MVT::i32, Expand);
296 setOperationAction(ISD::SREM, MVT::i64, Expand);
297 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
298 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
299 setOperationAction(ISD::UREM, MVT::i32, Expand);
300 setOperationAction(ISD::UREM, MVT::i64, Expand);
301
302 // Custom lower Add/Sub/Mul with overflow.
303 setOperationAction(ISD::SADDO, MVT::i32, Custom);
304 setOperationAction(ISD::SADDO, MVT::i64, Custom);
305 setOperationAction(ISD::UADDO, MVT::i32, Custom);
306 setOperationAction(ISD::UADDO, MVT::i64, Custom);
307 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
308 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
309 setOperationAction(ISD::USUBO, MVT::i32, Custom);
310 setOperationAction(ISD::USUBO, MVT::i64, Custom);
311 setOperationAction(ISD::SMULO, MVT::i32, Custom);
312 setOperationAction(ISD::SMULO, MVT::i64, Custom);
313 setOperationAction(ISD::UMULO, MVT::i32, Custom);
314 setOperationAction(ISD::UMULO, MVT::i64, Custom);
315
316 setOperationAction(ISD::FSIN, MVT::f32, Expand);
317 setOperationAction(ISD::FSIN, MVT::f64, Expand);
318 setOperationAction(ISD::FCOS, MVT::f32, Expand);
319 setOperationAction(ISD::FCOS, MVT::f64, Expand);
320 setOperationAction(ISD::FPOW, MVT::f32, Expand);
321 setOperationAction(ISD::FPOW, MVT::f64, Expand);
322 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
323 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
324 if (Subtarget->hasFullFP16())
325 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom);
326 else
327 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote);
328
329 setOperationAction(ISD::FREM, MVT::f16, Promote);
330 setOperationAction(ISD::FREM, MVT::v4f16, Promote);
331 setOperationAction(ISD::FREM, MVT::v8f16, Promote);
332 setOperationAction(ISD::FPOW, MVT::f16, Promote);
333 setOperationAction(ISD::FPOW, MVT::v4f16, Promote);
334 setOperationAction(ISD::FPOW, MVT::v8f16, Promote);
335 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
336 setOperationAction(ISD::FCOS, MVT::f16, Promote);
337 setOperationAction(ISD::FCOS, MVT::v4f16, Promote);
338 setOperationAction(ISD::FCOS, MVT::v8f16, Promote);
339 setOperationAction(ISD::FSIN, MVT::f16, Promote);
340 setOperationAction(ISD::FSIN, MVT::v4f16, Promote);
341 setOperationAction(ISD::FSIN, MVT::v8f16, Promote);
342 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
343 setOperationAction(ISD::FSINCOS, MVT::v4f16, Promote);
344 setOperationAction(ISD::FSINCOS, MVT::v8f16, Promote);
345 setOperationAction(ISD::FEXP, MVT::f16, Promote);
346 setOperationAction(ISD::FEXP, MVT::v4f16, Promote);
347 setOperationAction(ISD::FEXP, MVT::v8f16, Promote);
348 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
349 setOperationAction(ISD::FEXP2, MVT::v4f16, Promote);
350 setOperationAction(ISD::FEXP2, MVT::v8f16, Promote);
351 setOperationAction(ISD::FLOG, MVT::f16, Promote);
352 setOperationAction(ISD::FLOG, MVT::v4f16, Promote);
353 setOperationAction(ISD::FLOG, MVT::v8f16, Promote);
354 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
355 setOperationAction(ISD::FLOG2, MVT::v4f16, Promote);
356 setOperationAction(ISD::FLOG2, MVT::v8f16, Promote);
357 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
358 setOperationAction(ISD::FLOG10, MVT::v4f16, Promote);
359 setOperationAction(ISD::FLOG10, MVT::v8f16, Promote);
360
361 if (!Subtarget->hasFullFP16()) {
362 setOperationAction(ISD::SELECT, MVT::f16, Promote);
363 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
364 setOperationAction(ISD::SETCC, MVT::f16, Promote);
365 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
366 setOperationAction(ISD::FADD, MVT::f16, Promote);
367 setOperationAction(ISD::FSUB, MVT::f16, Promote);
368 setOperationAction(ISD::FMUL, MVT::f16, Promote);
369 setOperationAction(ISD::FDIV, MVT::f16, Promote);
370 setOperationAction(ISD::FMA, MVT::f16, Promote);
371 setOperationAction(ISD::FNEG, MVT::f16, Promote);
372 setOperationAction(ISD::FABS, MVT::f16, Promote);
373 setOperationAction(ISD::FCEIL, MVT::f16, Promote);
374 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
375 setOperationAction(ISD::FFLOOR, MVT::f16, Promote);
376 setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote);
377 setOperationAction(ISD::FRINT, MVT::f16, Promote);
378 setOperationAction(ISD::FROUND, MVT::f16, Promote);
379 setOperationAction(ISD::FTRUNC, MVT::f16, Promote);
380 setOperationAction(ISD::FMINNUM, MVT::f16, Promote);
381 setOperationAction(ISD::FMAXNUM, MVT::f16, Promote);
382 setOperationAction(ISD::FMINNAN, MVT::f16, Promote);
383 setOperationAction(ISD::FMAXNAN, MVT::f16, Promote);
384
385 // promote v4f16 to v4f32 when that is known to be safe.
386 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
387 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
388 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
389 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
390 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
391 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
392 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
393 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
394 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
395 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
396 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
397 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
398
399 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
400 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
401 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
402 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
403 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
404 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
405 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
406 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
407 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
408 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
409 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
410 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
411 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
412 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
413 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
414
415 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
416 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
417 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
418 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
419 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
420 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
421 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
422 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
423 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
424 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
425 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
426 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
427 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
428 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
429 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
430 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
431 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
432 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
433 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
434 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
435 }
436
437 // AArch64 has implementations of a lot of rounding-like FP operations.
438 for (MVT Ty : {MVT::f32, MVT::f64}) {
439 setOperationAction(ISD::FFLOOR, Ty, Legal);
440 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
441 setOperationAction(ISD::FCEIL, Ty, Legal);
442 setOperationAction(ISD::FRINT, Ty, Legal);
443 setOperationAction(ISD::FTRUNC, Ty, Legal);
444 setOperationAction(ISD::FROUND, Ty, Legal);
445 setOperationAction(ISD::FMINNUM, Ty, Legal);
446 setOperationAction(ISD::FMAXNUM, Ty, Legal);
447 setOperationAction(ISD::FMINNAN, Ty, Legal);
448 setOperationAction(ISD::FMAXNAN, Ty, Legal);
449 }
450
451 if (Subtarget->hasFullFP16()) {
452 setOperationAction(ISD::FNEARBYINT, MVT::f16, Legal);
453 setOperationAction(ISD::FFLOOR, MVT::f16, Legal);
454 setOperationAction(ISD::FCEIL, MVT::f16, Legal);
455 setOperationAction(ISD::FRINT, MVT::f16, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::f16, Legal);
457 setOperationAction(ISD::FROUND, MVT::f16, Legal);
458 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
459 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
460 setOperationAction(ISD::FMINNAN, MVT::f16, Legal);
461 setOperationAction(ISD::FMAXNAN, MVT::f16, Legal);
462 }
463
464 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
465
466 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
467 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
469 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
470 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
471
472 // Lower READCYCLECOUNTER using an mrs from PMCCNTR_EL0.
473 // This requires the Performance Monitors extension.
474 if (Subtarget->hasPerfMon())
475 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
476
477 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
478 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
479 // Issue __sincos_stret if available.
480 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
481 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
482 } else {
483 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
484 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
485 }
486
487 // Make floating-point constants legal for the large code model, so they don't
488 // become loads from the constant pool.
489 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
490 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
491 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
492 }
493
494 // AArch64 does not have floating-point extending loads, i1 sign-extending
495 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
496 for (MVT VT : MVT::fp_valuetypes()) {
497 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
498 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
499 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
500 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
501 }
502 for (MVT VT : MVT::integer_valuetypes())
503 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand);
504
505 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
506 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
507 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
508 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
509 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
510 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
511 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
512
513 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
514 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
515
516 // Indexed loads and stores are supported.
517 for (unsigned im = (unsigned)ISD::PRE_INC;
518 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
519 setIndexedLoadAction(im, MVT::i8, Legal);
520 setIndexedLoadAction(im, MVT::i16, Legal);
521 setIndexedLoadAction(im, MVT::i32, Legal);
522 setIndexedLoadAction(im, MVT::i64, Legal);
523 setIndexedLoadAction(im, MVT::f64, Legal);
524 setIndexedLoadAction(im, MVT::f32, Legal);
525 setIndexedLoadAction(im, MVT::f16, Legal);
526 setIndexedStoreAction(im, MVT::i8, Legal);
527 setIndexedStoreAction(im, MVT::i16, Legal);
528 setIndexedStoreAction(im, MVT::i32, Legal);
529 setIndexedStoreAction(im, MVT::i64, Legal);
530 setIndexedStoreAction(im, MVT::f64, Legal);
531 setIndexedStoreAction(im, MVT::f32, Legal);
532 setIndexedStoreAction(im, MVT::f16, Legal);
533 }
534
535 // Trap.
536 setOperationAction(ISD::TRAP, MVT::Other, Legal);
537
538 // We combine OR nodes for bitfield operations.
539 setTargetDAGCombine(ISD::OR);
540
541 // Vector add and sub nodes may conceal a high-half opportunity.
542 // Also, try to fold ADD into CSINC/CSINV..
543 setTargetDAGCombine(ISD::ADD);
544 setTargetDAGCombine(ISD::SUB);
545 setTargetDAGCombine(ISD::SRL);
546 setTargetDAGCombine(ISD::XOR);
547 setTargetDAGCombine(ISD::SINT_TO_FP);
548 setTargetDAGCombine(ISD::UINT_TO_FP);
549
550 setTargetDAGCombine(ISD::FP_TO_SINT);
551 setTargetDAGCombine(ISD::FP_TO_UINT);
552 setTargetDAGCombine(ISD::FDIV);
553
554 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
555
556 setTargetDAGCombine(ISD::ANY_EXTEND);
557 setTargetDAGCombine(ISD::ZERO_EXTEND);
558 setTargetDAGCombine(ISD::SIGN_EXTEND);
559 setTargetDAGCombine(ISD::BITCAST);
560 setTargetDAGCombine(ISD::CONCAT_VECTORS);
561 setTargetDAGCombine(ISD::STORE);
562 if (Subtarget->supportsAddressTopByteIgnored())
563 setTargetDAGCombine(ISD::LOAD);
564
565 setTargetDAGCombine(ISD::MUL);
566
567 setTargetDAGCombine(ISD::SELECT);
568 setTargetDAGCombine(ISD::VSELECT);
569
570 setTargetDAGCombine(ISD::INTRINSIC_VOID);
571 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
572 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
573
574 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
575 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
576 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
577
578 setStackPointerRegisterToSaveRestore(AArch64::SP);
579
580 setSchedulingPreference(Sched::Hybrid);
581
582 EnableExtLdPromotion = true;
583
584 // Set required alignment.
585 setMinFunctionAlignment(2);
586 // Set preferred alignments.
587 setPrefFunctionAlignment(STI.getPrefFunctionAlignment());
588 setPrefLoopAlignment(STI.getPrefLoopAlignment());
589
590 // Only change the limit for entries in a jump table if specified by
591 // the subtarget, but not at the command line.
592 unsigned MaxJT = STI.getMaximumJumpTableSize();
593 if (MaxJT && getMaximumJumpTableSize() == 0)
594 setMaximumJumpTableSize(MaxJT);
595
596 setHasExtractBitsInsn(true);
597
598 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
599
600 if (Subtarget->hasNEON()) {
601 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
602 // silliness like this:
603 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
604 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
605 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
606 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
607 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
608 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
609 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
610 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
611 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
612 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
613 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
614 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
615 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
616 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
617 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
618 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
619 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
620 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
621 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
622 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
623 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
624 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
625 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
626 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
627 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
628
629 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
630 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
631 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
632 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
633 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
634
635 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
636
637 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
638 // elements smaller than i32, so promote the input to i32 first.
639 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i8, MVT::v4i32);
640 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i8, MVT::v4i32);
641 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32);
642 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32);
643 // i8 and i16 vector elements also need promotion to i32 for v8i8 or v8i16
644 // -> v8f16 conversions.
645 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i8, MVT::v8i32);
646 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i8, MVT::v8i32);
647 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i16, MVT::v8i32);
648 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i16, MVT::v8i32);
649 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
650 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
651 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
652 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
653 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
654 // Or, direct i32 -> f16 vector conversion. Set it so custom, so the
655 // conversion happens in two steps: v4i32 -> v4f32 -> v4f16
656 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Custom);
657 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
658
659 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
660 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
661
662 setOperationAction(ISD::CTTZ, MVT::v2i8, Expand);
663 setOperationAction(ISD::CTTZ, MVT::v4i16, Expand);
664 setOperationAction(ISD::CTTZ, MVT::v2i32, Expand);
665 setOperationAction(ISD::CTTZ, MVT::v1i64, Expand);
666 setOperationAction(ISD::CTTZ, MVT::v16i8, Expand);
667 setOperationAction(ISD::CTTZ, MVT::v8i16, Expand);
668 setOperationAction(ISD::CTTZ, MVT::v4i32, Expand);
669 setOperationAction(ISD::CTTZ, MVT::v2i64, Expand);
670
671 // AArch64 doesn't have MUL.2d:
672 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
673 // Custom handling for some quad-vector types to detect MULL.
674 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
675 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
676 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
677
678 // Vector reductions
679 for (MVT VT : MVT::integer_valuetypes()) {
680 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
681 setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
682 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
683 setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
684 setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
685 }
686 for (MVT VT : MVT::fp_valuetypes()) {
687 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
688 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
689 }
690
691 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
692 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
693 // Likewise, narrowing and extending vector loads/stores aren't handled
694 // directly.
695 for (MVT VT : MVT::vector_valuetypes()) {
696 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
697
698 setOperationAction(ISD::MULHS, VT, Expand);
699 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
700 setOperationAction(ISD::MULHU, VT, Expand);
701 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
702
703 setOperationAction(ISD::BSWAP, VT, Expand);
704
705 for (MVT InnerVT : MVT::vector_valuetypes()) {
706 setTruncStoreAction(VT, InnerVT, Expand);
707 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
708 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
709 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
710 }
711 }
712
713 // AArch64 has implementations of a lot of rounding-like FP operations.
714 for (MVT Ty : {MVT::v2f32, MVT::v4f32, MVT::v2f64}) {
715 setOperationAction(ISD::FFLOOR, Ty, Legal);
716 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
717 setOperationAction(ISD::FCEIL, Ty, Legal);
718 setOperationAction(ISD::FRINT, Ty, Legal);
719 setOperationAction(ISD::FTRUNC, Ty, Legal);
720 setOperationAction(ISD::FROUND, Ty, Legal);
721 }
722 }
723
724 PredictableSelectIsExpensive = Subtarget->predictableSelectIsExpensive();
725}
726
727void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
728 assert(VT.isVector() && "VT should be a vector type")(static_cast <bool> (VT.isVector() && "VT should be a vector type"
) ? void (0) : __assert_fail ("VT.isVector() && \"VT should be a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 728, __extension__ __PRETTY_FUNCTION__))
;
729
730 if (VT.isFloatingPoint()) {
731 MVT PromoteTo = EVT(VT).changeVectorElementTypeToInteger().getSimpleVT();
732 setOperationPromotedToType(ISD::LOAD, VT, PromoteTo);
733 setOperationPromotedToType(ISD::STORE, VT, PromoteTo);
734 }
735
736 // Mark vector float intrinsics as expand.
737 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
738 setOperationAction(ISD::FSIN, VT, Expand);
739 setOperationAction(ISD::FCOS, VT, Expand);
740 setOperationAction(ISD::FPOW, VT, Expand);
741 setOperationAction(ISD::FLOG, VT, Expand);
742 setOperationAction(ISD::FLOG2, VT, Expand);
743 setOperationAction(ISD::FLOG10, VT, Expand);
744 setOperationAction(ISD::FEXP, VT, Expand);
745 setOperationAction(ISD::FEXP2, VT, Expand);
746
747 // But we do support custom-lowering for FCOPYSIGN.
748 setOperationAction(ISD::FCOPYSIGN, VT, Custom);
749 }
750
751 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
752 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
753 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
754 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
755 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
756 setOperationAction(ISD::SRA, VT, Custom);
757 setOperationAction(ISD::SRL, VT, Custom);
758 setOperationAction(ISD::SHL, VT, Custom);
759 setOperationAction(ISD::AND, VT, Custom);
760 setOperationAction(ISD::OR, VT, Custom);
761 setOperationAction(ISD::SETCC, VT, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
763
764 setOperationAction(ISD::SELECT, VT, Expand);
765 setOperationAction(ISD::SELECT_CC, VT, Expand);
766 setOperationAction(ISD::VSELECT, VT, Expand);
767 for (MVT InnerVT : MVT::all_valuetypes())
768 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
769
770 // CNT supports only B element sizes.
771 if (VT != MVT::v8i8 && VT != MVT::v16i8)
772 setOperationAction(ISD::CTPOP, VT, Expand);
773
774 setOperationAction(ISD::UDIV, VT, Expand);
775 setOperationAction(ISD::SDIV, VT, Expand);
776 setOperationAction(ISD::UREM, VT, Expand);
777 setOperationAction(ISD::SREM, VT, Expand);
778 setOperationAction(ISD::FREM, VT, Expand);
779
780 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
781 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
782
783 if (!VT.isFloatingPoint())
784 setOperationAction(ISD::ABS, VT, Legal);
785
786 // [SU][MIN|MAX] are available for all NEON types apart from i64.
787 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64)
788 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
789 setOperationAction(Opcode, VT, Legal);
790
791 // F[MIN|MAX][NUM|NAN] are available for all FP NEON types.
792 if (VT.isFloatingPoint() &&
793 (VT.getVectorElementType() != MVT::f16 || Subtarget->hasFullFP16()))
794 for (unsigned Opcode : {ISD::FMINNAN, ISD::FMAXNAN,
795 ISD::FMINNUM, ISD::FMAXNUM})
796 setOperationAction(Opcode, VT, Legal);
797
798 if (Subtarget->isLittleEndian()) {
799 for (unsigned im = (unsigned)ISD::PRE_INC;
800 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
801 setIndexedLoadAction(im, VT, Legal);
802 setIndexedStoreAction(im, VT, Legal);
803 }
804 }
805}
806
807void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
808 addRegisterClass(VT, &AArch64::FPR64RegClass);
809 addTypeForNEON(VT, MVT::v2i32);
810}
811
812void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
813 addRegisterClass(VT, &AArch64::FPR128RegClass);
814 addTypeForNEON(VT, MVT::v4i32);
815}
816
817EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
818 EVT VT) const {
819 if (!VT.isVector())
820 return MVT::i32;
821 return VT.changeVectorElementTypeToInteger();
822}
823
824static bool optimizeLogicalImm(SDValue Op, unsigned Size, uint64_t Imm,
825 const APInt &Demanded,
826 TargetLowering::TargetLoweringOpt &TLO,
827 unsigned NewOpc) {
828 uint64_t OldImm = Imm, NewImm, Enc;
829 uint64_t Mask = ((uint64_t)(-1LL) >> (64 - Size)), OrigMask = Mask;
830
831 // Return if the immediate is already all zeros, all ones, a bimm32 or a
832 // bimm64.
833 if (Imm == 0 || Imm == Mask ||
834 AArch64_AM::isLogicalImmediate(Imm & Mask, Size))
835 return false;
836
837 unsigned EltSize = Size;
838 uint64_t DemandedBits = Demanded.getZExtValue();
839
840 // Clear bits that are not demanded.
841 Imm &= DemandedBits;
842
843 while (true) {
844 // The goal here is to set the non-demanded bits in a way that minimizes
845 // the number of switching between 0 and 1. In order to achieve this goal,
846 // we set the non-demanded bits to the value of the preceding demanded bits.
847 // For example, if we have an immediate 0bx10xx0x1 ('x' indicates a
848 // non-demanded bit), we copy bit0 (1) to the least significant 'x',
849 // bit2 (0) to 'xx', and bit6 (1) to the most significant 'x'.
850 // The final result is 0b11000011.
851 uint64_t NonDemandedBits = ~DemandedBits;
852 uint64_t InvertedImm = ~Imm & DemandedBits;
853 uint64_t RotatedImm =
854 ((InvertedImm << 1) | (InvertedImm >> (EltSize - 1) & 1)) &
855 NonDemandedBits;
856 uint64_t Sum = RotatedImm + NonDemandedBits;
857 bool Carry = NonDemandedBits & ~Sum & (1ULL << (EltSize - 1));
858 uint64_t Ones = (Sum + Carry) & NonDemandedBits;
859 NewImm = (Imm | Ones) & Mask;
860
861 // If NewImm or its bitwise NOT is a shifted mask, it is a bitmask immediate
862 // or all-ones or all-zeros, in which case we can stop searching. Otherwise,
863 // we halve the element size and continue the search.
864 if (isShiftedMask_64(NewImm) || isShiftedMask_64(~(NewImm | ~Mask)))
865 break;
866
867 // We cannot shrink the element size any further if it is 2-bits.
868 if (EltSize == 2)
869 return false;
870
871 EltSize /= 2;
872 Mask >>= EltSize;
873 uint64_t Hi = Imm >> EltSize, DemandedBitsHi = DemandedBits >> EltSize;
874
875 // Return if there is mismatch in any of the demanded bits of Imm and Hi.
876 if (((Imm ^ Hi) & (DemandedBits & DemandedBitsHi) & Mask) != 0)
877 return false;
878
879 // Merge the upper and lower halves of Imm and DemandedBits.
880 Imm |= Hi;
881 DemandedBits |= DemandedBitsHi;
882 }
883
884 ++NumOptimizedImms;
885
886 // Replicate the element across the register width.
887 while (EltSize < Size) {
888 NewImm |= NewImm << EltSize;
889 EltSize *= 2;
890 }
891
892 (void)OldImm;
893 assert(((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 &&(static_cast <bool> (((OldImm ^ NewImm) & Demanded.
getZExtValue()) == 0 && "demanded bits should never be altered"
) ? void (0) : __assert_fail ("((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 && \"demanded bits should never be altered\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 894, __extension__ __PRETTY_FUNCTION__))
894 "demanded bits should never be altered")(static_cast <bool> (((OldImm ^ NewImm) & Demanded.
getZExtValue()) == 0 && "demanded bits should never be altered"
) ? void (0) : __assert_fail ("((OldImm ^ NewImm) & Demanded.getZExtValue()) == 0 && \"demanded bits should never be altered\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 894, __extension__ __PRETTY_FUNCTION__))
;
895 assert(OldImm != NewImm && "the new imm shouldn't be equal to the old imm")(static_cast <bool> (OldImm != NewImm && "the new imm shouldn't be equal to the old imm"
) ? void (0) : __assert_fail ("OldImm != NewImm && \"the new imm shouldn't be equal to the old imm\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 895, __extension__ __PRETTY_FUNCTION__))
;
896
897 // Create the new constant immediate node.
898 EVT VT = Op.getValueType();
899 SDLoc DL(Op);
900 SDValue New;
901
902 // If the new constant immediate is all-zeros or all-ones, let the target
903 // independent DAG combine optimize this node.
904 if (NewImm == 0 || NewImm == OrigMask) {
905 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0),
906 TLO.DAG.getConstant(NewImm, DL, VT));
907 // Otherwise, create a machine node so that target independent DAG combine
908 // doesn't undo this optimization.
909 } else {
910 Enc = AArch64_AM::encodeLogicalImmediate(NewImm, Size);
911 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT);
912 New = SDValue(
913 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0);
914 }
915
916 return TLO.CombineTo(Op, New);
917}
918
919bool AArch64TargetLowering::targetShrinkDemandedConstant(
920 SDValue Op, const APInt &Demanded, TargetLoweringOpt &TLO) const {
921 // Delay this optimization to as late as possible.
922 if (!TLO.LegalOps)
923 return false;
924
925 if (!EnableOptimizeLogicalImm)
926 return false;
927
928 EVT VT = Op.getValueType();
929 if (VT.isVector())
930 return false;
931
932 unsigned Size = VT.getSizeInBits();
933 assert((Size == 32 || Size == 64) &&(static_cast <bool> ((Size == 32 || Size == 64) &&
"i32 or i64 is expected after legalization.") ? void (0) : __assert_fail
("(Size == 32 || Size == 64) && \"i32 or i64 is expected after legalization.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 934, __extension__ __PRETTY_FUNCTION__))
934 "i32 or i64 is expected after legalization.")(static_cast <bool> ((Size == 32 || Size == 64) &&
"i32 or i64 is expected after legalization.") ? void (0) : __assert_fail
("(Size == 32 || Size == 64) && \"i32 or i64 is expected after legalization.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 934, __extension__ __PRETTY_FUNCTION__))
;
935
936 // Exit early if we demand all bits.
937 if (Demanded.countPopulation() == Size)
938 return false;
939
940 unsigned NewOpc;
941 switch (Op.getOpcode()) {
942 default:
943 return false;
944 case ISD::AND:
945 NewOpc = Size == 32 ? AArch64::ANDWri : AArch64::ANDXri;
946 break;
947 case ISD::OR:
948 NewOpc = Size == 32 ? AArch64::ORRWri : AArch64::ORRXri;
949 break;
950 case ISD::XOR:
951 NewOpc = Size == 32 ? AArch64::EORWri : AArch64::EORXri;
952 break;
953 }
954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
955 if (!C)
956 return false;
957 uint64_t Imm = C->getZExtValue();
958 return optimizeLogicalImm(Op, Size, Imm, Demanded, TLO, NewOpc);
959}
960
961/// computeKnownBitsForTargetNode - Determine which of the bits specified in
962/// Mask are known to be either zero or one and return them Known.
963void AArch64TargetLowering::computeKnownBitsForTargetNode(
964 const SDValue Op, KnownBits &Known,
965 const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const {
966 switch (Op.getOpcode()) {
967 default:
968 break;
969 case AArch64ISD::CSEL: {
970 KnownBits Known2;
971 DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
972 DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
973 Known.Zero &= Known2.Zero;
974 Known.One &= Known2.One;
975 break;
976 }
977 case ISD::INTRINSIC_W_CHAIN: {
978 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
979 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
980 switch (IntID) {
981 default: return;
982 case Intrinsic::aarch64_ldaxr:
983 case Intrinsic::aarch64_ldxr: {
984 unsigned BitWidth = Known.getBitWidth();
985 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
986 unsigned MemBits = VT.getScalarSizeInBits();
987 Known.Zero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
988 return;
989 }
990 }
991 break;
992 }
993 case ISD::INTRINSIC_WO_CHAIN:
994 case ISD::INTRINSIC_VOID: {
995 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
996 switch (IntNo) {
997 default:
998 break;
999 case Intrinsic::aarch64_neon_umaxv:
1000 case Intrinsic::aarch64_neon_uminv: {
1001 // Figure out the datatype of the vector operand. The UMINV instruction
1002 // will zero extend the result, so we can mark as known zero all the
1003 // bits larger than the element datatype. 32-bit or larget doesn't need
1004 // this as those are legal types and will be handled by isel directly.
1005 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
1006 unsigned BitWidth = Known.getBitWidth();
1007 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
1008 assert(BitWidth >= 8 && "Unexpected width!")(static_cast <bool> (BitWidth >= 8 && "Unexpected width!"
) ? void (0) : __assert_fail ("BitWidth >= 8 && \"Unexpected width!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1008, __extension__ __PRETTY_FUNCTION__))
;
1009 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
1010 Known.Zero |= Mask;
1011 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
1012 assert(BitWidth >= 16 && "Unexpected width!")(static_cast <bool> (BitWidth >= 16 && "Unexpected width!"
) ? void (0) : __assert_fail ("BitWidth >= 16 && \"Unexpected width!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1012, __extension__ __PRETTY_FUNCTION__))
;
1013 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
1014 Known.Zero |= Mask;
1015 }
1016 break;
1017 } break;
1018 }
1019 }
1020 }
1021}
1022
1023MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
1024 EVT) const {
1025 return MVT::i64;
1026}
1027
1028bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1029 unsigned AddrSpace,
1030 unsigned Align,
1031 bool *Fast) const {
1032 if (Subtarget->requiresStrictAlign())
1033 return false;
1034
1035 if (Fast) {
1036 // Some CPUs are fine with unaligned stores except for 128-bit ones.
1037 *Fast = !Subtarget->isMisaligned128StoreSlow() || VT.getStoreSize() != 16 ||
1038 // See comments in performSTORECombine() for more details about
1039 // these conditions.
1040
1041 // Code that uses clang vector extensions can mark that it
1042 // wants unaligned accesses to be treated as fast by
1043 // underspecifying alignment to be 1 or 2.
1044 Align <= 2 ||
1045
1046 // Disregard v2i64. Memcpy lowering produces those and splitting
1047 // them regresses performance on micro-benchmarks and olden/bh.
1048 VT == MVT::v2i64;
1049 }
1050 return true;
1051}
1052
1053FastISel *
1054AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1055 const TargetLibraryInfo *libInfo) const {
1056 return AArch64::createFastISel(funcInfo, libInfo);
1057}
1058
1059const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
1060 switch ((AArch64ISD::NodeType)Opcode) {
1061 case AArch64ISD::FIRST_NUMBER: break;
1062 case AArch64ISD::CALL: return "AArch64ISD::CALL";
1063 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
1064 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
1065 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
1066 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
1067 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
1068 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
1069 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
1070 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
1071 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
1072 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
1073 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
1074 case AArch64ISD::TLSDESC_CALLSEQ: return "AArch64ISD::TLSDESC_CALLSEQ";
1075 case AArch64ISD::ADC: return "AArch64ISD::ADC";
1076 case AArch64ISD::SBC: return "AArch64ISD::SBC";
1077 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
1078 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
1079 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
1080 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
1081 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
1082 case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
1083 case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
1084 case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
1085 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
1086 case AArch64ISD::DUP: return "AArch64ISD::DUP";
1087 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
1088 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
1089 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
1090 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
1091 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
1092 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
1093 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
1094 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
1095 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
1096 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
1097 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
1098 case AArch64ISD::BICi: return "AArch64ISD::BICi";
1099 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
1100 case AArch64ISD::BSL: return "AArch64ISD::BSL";
1101 case AArch64ISD::NEG: return "AArch64ISD::NEG";
1102 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
1103 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
1104 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
1105 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
1106 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
1107 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
1108 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
1109 case AArch64ISD::REV16: return "AArch64ISD::REV16";
1110 case AArch64ISD::REV32: return "AArch64ISD::REV32";
1111 case AArch64ISD::REV64: return "AArch64ISD::REV64";
1112 case AArch64ISD::EXT: return "AArch64ISD::EXT";
1113 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
1114 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
1115 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
1116 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
1117 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
1118 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
1119 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
1120 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
1121 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
1122 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
1123 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
1124 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
1125 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
1126 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
1127 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
1128 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
1129 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
1130 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
1131 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
1132 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
1133 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
1134 case AArch64ISD::SADDV: return "AArch64ISD::SADDV";
1135 case AArch64ISD::UADDV: return "AArch64ISD::UADDV";
1136 case AArch64ISD::SMINV: return "AArch64ISD::SMINV";
1137 case AArch64ISD::UMINV: return "AArch64ISD::UMINV";
1138 case AArch64ISD::SMAXV: return "AArch64ISD::SMAXV";
1139 case AArch64ISD::UMAXV: return "AArch64ISD::UMAXV";
1140 case AArch64ISD::NOT: return "AArch64ISD::NOT";
1141 case AArch64ISD::BIT: return "AArch64ISD::BIT";
1142 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
1143 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
1144 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
1145 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
1146 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
1147 case AArch64ISD::PREFETCH: return "AArch64ISD::PREFETCH";
1148 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
1149 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
1150 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
1151 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
1152 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
1153 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
1154 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
1155 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
1156 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
1157 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
1158 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
1159 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
1160 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
1161 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
1162 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
1163 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
1164 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
1165 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
1166 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
1167 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
1168 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
1169 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
1170 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
1171 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
1172 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
1173 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
1174 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
1175 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
1176 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
1177 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
1178 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
1179 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
1180 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
1181 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
1182 case AArch64ISD::FRECPE: return "AArch64ISD::FRECPE";
1183 case AArch64ISD::FRECPS: return "AArch64ISD::FRECPS";
1184 case AArch64ISD::FRSQRTE: return "AArch64ISD::FRSQRTE";
1185 case AArch64ISD::FRSQRTS: return "AArch64ISD::FRSQRTS";
1186 }
1187 return nullptr;
1188}
1189
1190MachineBasicBlock *
1191AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
1192 MachineBasicBlock *MBB) const {
1193 // We materialise the F128CSEL pseudo-instruction as some control flow and a
1194 // phi node:
1195
1196 // OrigBB:
1197 // [... previous instrs leading to comparison ...]
1198 // b.ne TrueBB
1199 // b EndBB
1200 // TrueBB:
1201 // ; Fallthrough
1202 // EndBB:
1203 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
1204
1205 MachineFunction *MF = MBB->getParent();
1206 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1207 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
1208 DebugLoc DL = MI.getDebugLoc();
1209 MachineFunction::iterator It = ++MBB->getIterator();
1210
1211 unsigned DestReg = MI.getOperand(0).getReg();
1212 unsigned IfTrueReg = MI.getOperand(1).getReg();
1213 unsigned IfFalseReg = MI.getOperand(2).getReg();
1214 unsigned CondCode = MI.getOperand(3).getImm();
1215 bool NZCVKilled = MI.getOperand(4).isKill();
1216
1217 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
1218 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
1219 MF->insert(It, TrueBB);
1220 MF->insert(It, EndBB);
1221
1222 // Transfer rest of current basic-block to EndBB
1223 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
1224 MBB->end());
1225 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
1226
1227 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
1228 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
1229 MBB->addSuccessor(TrueBB);
1230 MBB->addSuccessor(EndBB);
1231
1232 // TrueBB falls through to the end.
1233 TrueBB->addSuccessor(EndBB);
1234
1235 if (!NZCVKilled) {
1236 TrueBB->addLiveIn(AArch64::NZCV);
1237 EndBB->addLiveIn(AArch64::NZCV);
1238 }
1239
1240 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
1241 .addReg(IfTrueReg)
1242 .addMBB(TrueBB)
1243 .addReg(IfFalseReg)
1244 .addMBB(MBB);
1245
1246 MI.eraseFromParent();
1247 return EndBB;
1248}
1249
1250MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
1251 MachineInstr &MI, MachineBasicBlock *BB) const {
1252 switch (MI.getOpcode()) {
1253 default:
1254#ifndef NDEBUG
1255 MI.dump();
1256#endif
1257 llvm_unreachable("Unexpected instruction for custom inserter!")::llvm::llvm_unreachable_internal("Unexpected instruction for custom inserter!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1257)
;
1258
1259 case AArch64::F128CSEL:
1260 return EmitF128CSEL(MI, BB);
1261
1262 case TargetOpcode::STACKMAP:
1263 case TargetOpcode::PATCHPOINT:
1264 return emitPatchPoint(MI, BB);
1265 }
1266}
1267
1268//===----------------------------------------------------------------------===//
1269// AArch64 Lowering private implementation.
1270//===----------------------------------------------------------------------===//
1271
1272//===----------------------------------------------------------------------===//
1273// Lowering Code
1274//===----------------------------------------------------------------------===//
1275
1276/// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
1277/// CC
1278static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
1279 switch (CC) {
1280 default:
1281 llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1281)
;
1282 case ISD::SETNE:
1283 return AArch64CC::NE;
1284 case ISD::SETEQ:
1285 return AArch64CC::EQ;
1286 case ISD::SETGT:
1287 return AArch64CC::GT;
1288 case ISD::SETGE:
1289 return AArch64CC::GE;
1290 case ISD::SETLT:
1291 return AArch64CC::LT;
1292 case ISD::SETLE:
1293 return AArch64CC::LE;
1294 case ISD::SETUGT:
1295 return AArch64CC::HI;
1296 case ISD::SETUGE:
1297 return AArch64CC::HS;
1298 case ISD::SETULT:
1299 return AArch64CC::LO;
1300 case ISD::SETULE:
1301 return AArch64CC::LS;
1302 }
1303}
1304
1305/// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
1306static void changeFPCCToAArch64CC(ISD::CondCode CC,
1307 AArch64CC::CondCode &CondCode,
1308 AArch64CC::CondCode &CondCode2) {
1309 CondCode2 = AArch64CC::AL;
1310 switch (CC) {
1311 default:
1312 llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1312)
;
1313 case ISD::SETEQ:
1314 case ISD::SETOEQ:
1315 CondCode = AArch64CC::EQ;
1316 break;
1317 case ISD::SETGT:
1318 case ISD::SETOGT:
1319 CondCode = AArch64CC::GT;
1320 break;
1321 case ISD::SETGE:
1322 case ISD::SETOGE:
1323 CondCode = AArch64CC::GE;
1324 break;
1325 case ISD::SETOLT:
1326 CondCode = AArch64CC::MI;
1327 break;
1328 case ISD::SETOLE:
1329 CondCode = AArch64CC::LS;
1330 break;
1331 case ISD::SETONE:
1332 CondCode = AArch64CC::MI;
1333 CondCode2 = AArch64CC::GT;
1334 break;
1335 case ISD::SETO:
1336 CondCode = AArch64CC::VC;
1337 break;
1338 case ISD::SETUO:
1339 CondCode = AArch64CC::VS;
1340 break;
1341 case ISD::SETUEQ:
1342 CondCode = AArch64CC::EQ;
1343 CondCode2 = AArch64CC::VS;
1344 break;
1345 case ISD::SETUGT:
1346 CondCode = AArch64CC::HI;
1347 break;
1348 case ISD::SETUGE:
1349 CondCode = AArch64CC::PL;
1350 break;
1351 case ISD::SETLT:
1352 case ISD::SETULT:
1353 CondCode = AArch64CC::LT;
1354 break;
1355 case ISD::SETLE:
1356 case ISD::SETULE:
1357 CondCode = AArch64CC::LE;
1358 break;
1359 case ISD::SETNE:
1360 case ISD::SETUNE:
1361 CondCode = AArch64CC::NE;
1362 break;
1363 }
1364}
1365
1366/// Convert a DAG fp condition code to an AArch64 CC.
1367/// This differs from changeFPCCToAArch64CC in that it returns cond codes that
1368/// should be AND'ed instead of OR'ed.
1369static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
1370 AArch64CC::CondCode &CondCode,
1371 AArch64CC::CondCode &CondCode2) {
1372 CondCode2 = AArch64CC::AL;
1373 switch (CC) {
1374 default:
1375 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1376 assert(CondCode2 == AArch64CC::AL)(static_cast <bool> (CondCode2 == AArch64CC::AL) ? void
(0) : __assert_fail ("CondCode2 == AArch64CC::AL", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1376, __extension__ __PRETTY_FUNCTION__))
;
1377 break;
1378 case ISD::SETONE:
1379 // (a one b)
1380 // == ((a olt b) || (a ogt b))
1381 // == ((a ord b) && (a une b))
1382 CondCode = AArch64CC::VC;
1383 CondCode2 = AArch64CC::NE;
1384 break;
1385 case ISD::SETUEQ:
1386 // (a ueq b)
1387 // == ((a uno b) || (a oeq b))
1388 // == ((a ule b) && (a uge b))
1389 CondCode = AArch64CC::PL;
1390 CondCode2 = AArch64CC::LE;
1391 break;
1392 }
1393}
1394
1395/// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1396/// CC usable with the vector instructions. Fewer operations are available
1397/// without a real NZCV register, so we have to use less efficient combinations
1398/// to get the same effect.
1399static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1400 AArch64CC::CondCode &CondCode,
1401 AArch64CC::CondCode &CondCode2,
1402 bool &Invert) {
1403 Invert = false;
1404 switch (CC) {
1405 default:
1406 // Mostly the scalar mappings work fine.
1407 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1408 break;
1409 case ISD::SETUO:
1410 Invert = true;
1411 LLVM_FALLTHROUGH[[clang::fallthrough]];
1412 case ISD::SETO:
1413 CondCode = AArch64CC::MI;
1414 CondCode2 = AArch64CC::GE;
1415 break;
1416 case ISD::SETUEQ:
1417 case ISD::SETULT:
1418 case ISD::SETULE:
1419 case ISD::SETUGT:
1420 case ISD::SETUGE:
1421 // All of the compare-mask comparisons are ordered, but we can switch
1422 // between the two by a double inversion. E.g. ULE == !OGT.
1423 Invert = true;
1424 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1425 break;
1426 }
1427}
1428
1429static bool isLegalArithImmed(uint64_t C) {
1430 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1431 bool IsLegal = (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1432 DEBUG(dbgs() << "Is imm " << C << " legal: " << (IsLegal ? "yes\n" : "no\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Is imm " << C <<
" legal: " << (IsLegal ? "yes\n" : "no\n"); } } while (
false)
;
1433 return IsLegal;
1434}
1435
1436static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1437 const SDLoc &dl, SelectionDAG &DAG) {
1438 EVT VT = LHS.getValueType();
1439 const bool FullFP16 =
1440 static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
1441
1442 if (VT.isFloatingPoint()) {
1443 assert(VT != MVT::f128)(static_cast <bool> (VT != MVT::f128) ? void (0) : __assert_fail
("VT != MVT::f128", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1443, __extension__ __PRETTY_FUNCTION__))
;
1444 if (VT == MVT::f16 && !FullFP16) {
1445 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
1446 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
1447 VT = MVT::f32;
1448 }
1449 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1450 }
1451
1452 // The CMP instruction is just an alias for SUBS, and representing it as
1453 // SUBS means that it's possible to get CSE with subtract operations.
1454 // A later phase can perform the optimization of setting the destination
1455 // register to WZR/XZR if it ends up being unused.
1456 unsigned Opcode = AArch64ISD::SUBS;
1457
1458 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
1459 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1460 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1461 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1462 // can be set differently by this operation. It comes down to whether
1463 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1464 // everything is fine. If not then the optimization is wrong. Thus general
1465 // comparisons are only valid if op2 != 0.
1466
1467 // So, finally, the only LLVM-native comparisons that don't mention C and V
1468 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1469 // the absence of information about op2.
1470 Opcode = AArch64ISD::ADDS;
1471 RHS = RHS.getOperand(1);
1472 } else if (LHS.getOpcode() == ISD::AND && isNullConstant(RHS) &&
1473 !isUnsignedIntSetCC(CC)) {
1474 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1475 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1476 // of the signed comparisons.
1477 Opcode = AArch64ISD::ANDS;
1478 RHS = LHS.getOperand(1);
1479 LHS = LHS.getOperand(0);
1480 }
1481
1482 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
1483 .getValue(1);
1484}
1485
1486/// \defgroup AArch64CCMP CMP;CCMP matching
1487///
1488/// These functions deal with the formation of CMP;CCMP;... sequences.
1489/// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
1490/// a comparison. They set the NZCV flags to a predefined value if their
1491/// predicate is false. This allows to express arbitrary conjunctions, for
1492/// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
1493/// expressed as:
1494/// cmp A
1495/// ccmp B, inv(CB), CA
1496/// check for CB flags
1497///
1498/// In general we can create code for arbitrary "... (and (and A B) C)"
1499/// sequences. We can also implement some "or" expressions, because "(or A B)"
1500/// is equivalent to "not (and (not A) (not B))" and we can implement some
1501/// negation operations:
1502/// We can negate the results of a single comparison by inverting the flags
1503/// used when the predicate fails and inverting the flags tested in the next
1504/// instruction; We can also negate the results of the whole previous
1505/// conditional compare sequence by inverting the flags tested in the next
1506/// instruction. However there is no way to negate the result of a partial
1507/// sequence.
1508///
1509/// Therefore on encountering an "or" expression we can negate the subtree on
1510/// one side and have to be able to push the negate to the leafs of the subtree
1511/// on the other side (see also the comments in code). As complete example:
1512/// "or (or (setCA (cmp A)) (setCB (cmp B)))
1513/// (and (setCC (cmp C)) (setCD (cmp D)))"
1514/// is transformed to
1515/// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
1516/// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
1517/// and implemented as:
1518/// cmp C
1519/// ccmp D, inv(CD), CC
1520/// ccmp A, CA, inv(CD)
1521/// ccmp B, CB, inv(CA)
1522/// check for CB flags
1523/// A counterexample is "or (and A B) (and C D)" which cannot be implemented
1524/// by conditional compare sequences.
1525/// @{
1526
1527/// Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate.
1528static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
1529 ISD::CondCode CC, SDValue CCOp,
1530 AArch64CC::CondCode Predicate,
1531 AArch64CC::CondCode OutCC,
1532 const SDLoc &DL, SelectionDAG &DAG) {
1533 unsigned Opcode = 0;
1534 const bool FullFP16 =
1535 static_cast<const AArch64Subtarget &>(DAG.getSubtarget()).hasFullFP16();
1536
1537 if (LHS.getValueType().isFloatingPoint()) {
1538 assert(LHS.getValueType() != MVT::f128)(static_cast <bool> (LHS.getValueType() != MVT::f128) ?
void (0) : __assert_fail ("LHS.getValueType() != MVT::f128",
"/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1538, __extension__ __PRETTY_FUNCTION__))
;
1539 if (LHS.getValueType() == MVT::f16 && !FullFP16) {
1540 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS);
1541 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS);
1542 }
1543 Opcode = AArch64ISD::FCCMP;
1544 } else if (RHS.getOpcode() == ISD::SUB) {
1545 SDValue SubOp0 = RHS.getOperand(0);
1546 if (isNullConstant(SubOp0) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1547 // See emitComparison() on why we can only do this for SETEQ and SETNE.
1548 Opcode = AArch64ISD::CCMN;
1549 RHS = RHS.getOperand(1);
1550 }
1551 }
1552 if (Opcode == 0)
1553 Opcode = AArch64ISD::CCMP;
1554
1555 SDValue Condition = DAG.getConstant(Predicate, DL, MVT_CC);
1556 AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
1557 unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
1558 SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
1559 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
1560}
1561
1562/// Returns true if @p Val is a tree of AND/OR/SETCC operations.
1563/// CanPushNegate is set to true if we can push a negate operation through
1564/// the tree in a was that we are left with AND operations and negate operations
1565/// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
1566/// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
1567/// brought into such a form.
1568static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanNegate,
1569 unsigned Depth = 0) {
1570 if (!Val.hasOneUse())
1571 return false;
1572 unsigned Opcode = Val->getOpcode();
1573 if (Opcode == ISD::SETCC) {
1574 if (Val->getOperand(0).getValueType() == MVT::f128)
1575 return false;
1576 CanNegate = true;
1577 return true;
1578 }
1579 // Protect against exponential runtime and stack overflow.
1580 if (Depth > 6)
1581 return false;
1582 if (Opcode == ISD::AND || Opcode == ISD::OR) {
1583 SDValue O0 = Val->getOperand(0);
1584 SDValue O1 = Val->getOperand(1);
1585 bool CanNegateL;
1586 if (!isConjunctionDisjunctionTree(O0, CanNegateL, Depth+1))
1587 return false;
1588 bool CanNegateR;
1589 if (!isConjunctionDisjunctionTree(O1, CanNegateR, Depth+1))
1590 return false;
1591
1592 if (Opcode == ISD::OR) {
1593 // For an OR expression we need to be able to negate at least one side or
1594 // we cannot do the transformation at all.
1595 if (!CanNegateL && !CanNegateR)
1596 return false;
1597 // We can however change a (not (or x y)) to (and (not x) (not y)) if we
1598 // can negate the x and y subtrees.
1599 CanNegate = CanNegateL && CanNegateR;
1600 } else {
1601 // If the operands are OR expressions then we finally need to negate their
1602 // outputs, we can only do that for the operand with emitted last by
1603 // negating OutCC, not for both operands.
1604 bool NeedsNegOutL = O0->getOpcode() == ISD::OR;
1605 bool NeedsNegOutR = O1->getOpcode() == ISD::OR;
1606 if (NeedsNegOutL && NeedsNegOutR)
1607 return false;
1608 // We cannot negate an AND operation (it would become an OR),
1609 CanNegate = false;
1610 }
1611 return true;
1612 }
1613 return false;
1614}
1615
1616/// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1617/// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1618/// Tries to transform the given i1 producing node @p Val to a series compare
1619/// and conditional compare operations. @returns an NZCV flags producing node
1620/// and sets @p OutCC to the flags that should be tested or returns SDValue() if
1621/// transformation was not possible.
1622/// On recursive invocations @p PushNegate may be set to true to have negation
1623/// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
1624/// for the comparisons in the current subtree; @p Depth limits the search
1625/// depth to avoid stack overflow.
1626static SDValue emitConjunctionDisjunctionTreeRec(SelectionDAG &DAG, SDValue Val,
1627 AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp,
1628 AArch64CC::CondCode Predicate) {
1629 // We're at a tree leaf, produce a conditional comparison operation.
1630 unsigned Opcode = Val->getOpcode();
1631 if (Opcode == ISD::SETCC) {
1632 SDValue LHS = Val->getOperand(0);
1633 SDValue RHS = Val->getOperand(1);
1634 ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
1635 bool isInteger = LHS.getValueType().isInteger();
1636 if (Negate)
1637 CC = getSetCCInverse(CC, isInteger);
1638 SDLoc DL(Val);
1639 // Determine OutCC and handle FP special case.
1640 if (isInteger) {
1641 OutCC = changeIntCCToAArch64CC(CC);
1642 } else {
1643 assert(LHS.getValueType().isFloatingPoint())(static_cast <bool> (LHS.getValueType().isFloatingPoint
()) ? void (0) : __assert_fail ("LHS.getValueType().isFloatingPoint()"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1643, __extension__ __PRETTY_FUNCTION__))
;
1644 AArch64CC::CondCode ExtraCC;
1645 changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
1646 // Some floating point conditions can't be tested with a single condition
1647 // code. Construct an additional comparison in this case.
1648 if (ExtraCC != AArch64CC::AL) {
1649 SDValue ExtraCmp;
1650 if (!CCOp.getNode())
1651 ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
1652 else
1653 ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate,
1654 ExtraCC, DL, DAG);
1655 CCOp = ExtraCmp;
1656 Predicate = ExtraCC;
1657 }
1658 }
1659
1660 // Produce a normal comparison if we are first in the chain
1661 if (!CCOp)
1662 return emitComparison(LHS, RHS, CC, DL, DAG);
1663 // Otherwise produce a ccmp.
1664 return emitConditionalComparison(LHS, RHS, CC, CCOp, Predicate, OutCC, DL,
1665 DAG);
1666 }
1667 assert((Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) &&(static_cast <bool> ((Opcode == ISD::AND || (Opcode == ISD
::OR && Val->hasOneUse())) && "Valid conjunction/disjunction tree"
) ? void (0) : __assert_fail ("(Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1668, __extension__ __PRETTY_FUNCTION__))
1668 "Valid conjunction/disjunction tree")(static_cast <bool> ((Opcode == ISD::AND || (Opcode == ISD
::OR && Val->hasOneUse())) && "Valid conjunction/disjunction tree"
) ? void (0) : __assert_fail ("(Opcode == ISD::AND || (Opcode == ISD::OR && Val->hasOneUse())) && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1668, __extension__ __PRETTY_FUNCTION__))
;
1669
1670 // Check if both sides can be transformed.
1671 SDValue LHS = Val->getOperand(0);
1672 SDValue RHS = Val->getOperand(1);
1673
1674 // In case of an OR we need to negate our operands and the result.
1675 // (A v B) <=> not(not(A) ^ not(B))
1676 bool NegateOpsAndResult = Opcode == ISD::OR;
1677 // We can negate the results of all previous operations by inverting the
1678 // predicate flags giving us a free negation for one side. The other side
1679 // must be negatable by itself.
1680 if (NegateOpsAndResult) {
1681 // See which side we can negate.
1682 bool CanNegateL;
1683 bool isValidL = isConjunctionDisjunctionTree(LHS, CanNegateL);
1684 assert(isValidL && "Valid conjunction/disjunction tree")(static_cast <bool> (isValidL && "Valid conjunction/disjunction tree"
) ? void (0) : __assert_fail ("isValidL && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1684, __extension__ __PRETTY_FUNCTION__))
;
1685 (void)isValidL;
1686
1687#ifndef NDEBUG
1688 bool CanNegateR;
1689 bool isValidR = isConjunctionDisjunctionTree(RHS, CanNegateR);
1690 assert(isValidR && "Valid conjunction/disjunction tree")(static_cast <bool> (isValidR && "Valid conjunction/disjunction tree"
) ? void (0) : __assert_fail ("isValidR && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1690, __extension__ __PRETTY_FUNCTION__))
;
1691 assert((CanNegateL || CanNegateR) && "Valid conjunction/disjunction tree")(static_cast <bool> ((CanNegateL || CanNegateR) &&
"Valid conjunction/disjunction tree") ? void (0) : __assert_fail
("(CanNegateL || CanNegateR) && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1691, __extension__ __PRETTY_FUNCTION__))
;
1692#endif
1693
1694 // Order the side which we cannot negate to RHS so we can emit it first.
1695 if (!CanNegateL)
1696 std::swap(LHS, RHS);
1697 } else {
1698 bool NeedsNegOutL = LHS->getOpcode() == ISD::OR;
1699 assert((!NeedsNegOutL || RHS->getOpcode() != ISD::OR) &&(static_cast <bool> ((!NeedsNegOutL || RHS->getOpcode
() != ISD::OR) && "Valid conjunction/disjunction tree"
) ? void (0) : __assert_fail ("(!NeedsNegOutL || RHS->getOpcode() != ISD::OR) && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1700, __extension__ __PRETTY_FUNCTION__))
1700 "Valid conjunction/disjunction tree")(static_cast <bool> ((!NeedsNegOutL || RHS->getOpcode
() != ISD::OR) && "Valid conjunction/disjunction tree"
) ? void (0) : __assert_fail ("(!NeedsNegOutL || RHS->getOpcode() != ISD::OR) && \"Valid conjunction/disjunction tree\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1700, __extension__ __PRETTY_FUNCTION__))
;
1701 // Order the side where we need to negate the output flags to RHS so it
1702 // gets emitted first.
1703 if (NeedsNegOutL)
1704 std::swap(LHS, RHS);
1705 }
1706
1707 // Emit RHS. If we want to negate the tree we only need to push a negate
1708 // through if we are already in a PushNegate case, otherwise we can negate
1709 // the "flags to test" afterwards.
1710 AArch64CC::CondCode RHSCC;
1711 SDValue CmpR = emitConjunctionDisjunctionTreeRec(DAG, RHS, RHSCC, Negate,
1712 CCOp, Predicate);
1713 if (NegateOpsAndResult && !Negate)
1714 RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
1715 // Emit LHS. We may need to negate it.
1716 SDValue CmpL = emitConjunctionDisjunctionTreeRec(DAG, LHS, OutCC,
1717 NegateOpsAndResult, CmpR,
1718 RHSCC);
1719 // If we transformed an OR to and AND then we have to negate the result
1720 // (or absorb the Negate parameter).
1721 if (NegateOpsAndResult && !Negate)
1722 OutCC = AArch64CC::getInvertedCondCode(OutCC);
1723 return CmpL;
1724}
1725
1726/// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
1727/// of CCMP/CFCMP ops. See @ref AArch64CCMP.
1728/// \see emitConjunctionDisjunctionTreeRec().
1729static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
1730 AArch64CC::CondCode &OutCC) {
1731 bool CanNegate;
1732 if (!isConjunctionDisjunctionTree(Val, CanNegate))
1733 return SDValue();
1734
1735 return emitConjunctionDisjunctionTreeRec(DAG, Val, OutCC, false, SDValue(),
1736 AArch64CC::AL);
1737}
1738
1739/// @}
1740
1741static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1742 SDValue &AArch64cc, SelectionDAG &DAG,
1743 const SDLoc &dl) {
1744 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1745 EVT VT = RHS.getValueType();
1746 uint64_t C = RHSC->getZExtValue();
1747 if (!isLegalArithImmed(C)) {
1748 // Constant does not fit, try adjusting it by one?
1749 switch (CC) {
1750 default:
1751 break;
1752 case ISD::SETLT:
1753 case ISD::SETGE:
1754 if ((VT == MVT::i32 && C != 0x80000000 &&
1755 isLegalArithImmed((uint32_t)(C - 1))) ||
1756 (VT == MVT::i64 && C != 0x80000000ULL &&
1757 isLegalArithImmed(C - 1ULL))) {
1758 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1759 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1760 RHS = DAG.getConstant(C, dl, VT);
1761 }
1762 break;
1763 case ISD::SETULT:
1764 case ISD::SETUGE:
1765 if ((VT == MVT::i32 && C != 0 &&
1766 isLegalArithImmed((uint32_t)(C - 1))) ||
1767 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1768 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1769 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1770 RHS = DAG.getConstant(C, dl, VT);
1771 }
1772 break;
1773 case ISD::SETLE:
1774 case ISD::SETGT:
1775 if ((VT == MVT::i32 && C != INT32_MAX(2147483647) &&
1776 isLegalArithImmed((uint32_t)(C + 1))) ||
1777 (VT == MVT::i64 && C != INT64_MAX(9223372036854775807L) &&
1778 isLegalArithImmed(C + 1ULL))) {
1779 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1780 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1781 RHS = DAG.getConstant(C, dl, VT);
1782 }
1783 break;
1784 case ISD::SETULE:
1785 case ISD::SETUGT:
1786 if ((VT == MVT::i32 && C != UINT32_MAX(4294967295U) &&
1787 isLegalArithImmed((uint32_t)(C + 1))) ||
1788 (VT == MVT::i64 && C != UINT64_MAX(18446744073709551615UL) &&
1789 isLegalArithImmed(C + 1ULL))) {
1790 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1791 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1792 RHS = DAG.getConstant(C, dl, VT);
1793 }
1794 break;
1795 }
1796 }
1797 }
1798 SDValue Cmp;
1799 AArch64CC::CondCode AArch64CC;
1800 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1801 const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
1802
1803 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1804 // For the i8 operand, the largest immediate is 255, so this can be easily
1805 // encoded in the compare instruction. For the i16 operand, however, the
1806 // largest immediate cannot be encoded in the compare.
1807 // Therefore, use a sign extending load and cmn to avoid materializing the
1808 // -1 constant. For example,
1809 // movz w1, #65535
1810 // ldrh w0, [x0, #0]
1811 // cmp w0, w1
1812 // >
1813 // ldrsh w0, [x0, #0]
1814 // cmn w0, #1
1815 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1816 // if and only if (sext LHS) == (sext RHS). The checks are in place to
1817 // ensure both the LHS and RHS are truly zero extended and to make sure the
1818 // transformation is profitable.
1819 if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
1820 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1821 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1822 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1823 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1824 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1825 SDValue SExt =
1826 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1827 DAG.getValueType(MVT::i16));
1828 Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
1829 RHS.getValueType()),
1830 CC, dl, DAG);
1831 AArch64CC = changeIntCCToAArch64CC(CC);
1832 }
1833 }
1834
1835 if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
1836 if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
1837 if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
1838 AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
1839 }
1840 }
1841 }
1842
1843 if (!Cmp) {
1844 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1845 AArch64CC = changeIntCCToAArch64CC(CC);
1846 }
1847 AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
1848 return Cmp;
1849}
1850
1851static std::pair<SDValue, SDValue>
1852getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1853 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&(static_cast <bool> ((Op.getValueType() == MVT::i32 || Op
.getValueType() == MVT::i64) && "Unsupported value type"
) ? void (0) : __assert_fail ("(Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1854, __extension__ __PRETTY_FUNCTION__))
1854 "Unsupported value type")(static_cast <bool> ((Op.getValueType() == MVT::i32 || Op
.getValueType() == MVT::i64) && "Unsupported value type"
) ? void (0) : __assert_fail ("(Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1854, __extension__ __PRETTY_FUNCTION__))
;
1855 SDValue Value, Overflow;
1856 SDLoc DL(Op);
1857 SDValue LHS = Op.getOperand(0);
1858 SDValue RHS = Op.getOperand(1);
1859 unsigned Opc = 0;
1860 switch (Op.getOpcode()) {
1861 default:
1862 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1862)
;
1863 case ISD::SADDO:
1864 Opc = AArch64ISD::ADDS;
1865 CC = AArch64CC::VS;
1866 break;
1867 case ISD::UADDO:
1868 Opc = AArch64ISD::ADDS;
1869 CC = AArch64CC::HS;
1870 break;
1871 case ISD::SSUBO:
1872 Opc = AArch64ISD::SUBS;
1873 CC = AArch64CC::VS;
1874 break;
1875 case ISD::USUBO:
1876 Opc = AArch64ISD::SUBS;
1877 CC = AArch64CC::LO;
1878 break;
1879 // Multiply needs a little bit extra work.
1880 case ISD::SMULO:
1881 case ISD::UMULO: {
1882 CC = AArch64CC::NE;
1883 bool IsSigned = Op.getOpcode() == ISD::SMULO;
1884 if (Op.getValueType() == MVT::i32) {
1885 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1886 // For a 32 bit multiply with overflow check we want the instruction
1887 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1888 // need to generate the following pattern:
1889 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1890 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1891 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1892 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1893 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1894 DAG.getConstant(0, DL, MVT::i64));
1895 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1896 // operation. We need to clear out the upper 32 bits, because we used a
1897 // widening multiply that wrote all 64 bits. In the end this should be a
1898 // noop.
1899 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1900 if (IsSigned) {
1901 // The signed overflow check requires more than just a simple check for
1902 // any bit set in the upper 32 bits of the result. These bits could be
1903 // just the sign bits of a negative number. To perform the overflow
1904 // check we have to arithmetic shift right the 32nd bit of the result by
1905 // 31 bits. Then we compare the result to the upper 32 bits.
1906 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1907 DAG.getConstant(32, DL, MVT::i64));
1908 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1909 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1910 DAG.getConstant(31, DL, MVT::i64));
1911 // It is important that LowerBits is last, otherwise the arithmetic
1912 // shift will not be folded into the compare (SUBS).
1913 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1914 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1915 .getValue(1);
1916 } else {
1917 // The overflow check for unsigned multiply is easy. We only need to
1918 // check if any of the upper 32 bits are set. This can be done with a
1919 // CMP (shifted register). For that we need to generate the following
1920 // pattern:
1921 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1922 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1923 DAG.getConstant(32, DL, MVT::i64));
1924 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1925 Overflow =
1926 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1927 DAG.getConstant(0, DL, MVT::i64),
1928 UpperBits).getValue(1);
1929 }
1930 break;
1931 }
1932 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type")(static_cast <bool> (Op.getValueType() == MVT::i64 &&
"Expected an i64 value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i64 && \"Expected an i64 value type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 1932, __extension__ __PRETTY_FUNCTION__))
;
1933 // For the 64 bit multiply
1934 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1935 if (IsSigned) {
1936 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1937 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1938 DAG.getConstant(63, DL, MVT::i64));
1939 // It is important that LowerBits is last, otherwise the arithmetic
1940 // shift will not be folded into the compare (SUBS).
1941 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1942 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1943 .getValue(1);
1944 } else {
1945 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1946 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1947 Overflow =
1948 DAG.getNode(AArch64ISD::SUBS, DL, VTs,
1949 DAG.getConstant(0, DL, MVT::i64),
1950 UpperBits).getValue(1);
1951 }
1952 break;
1953 }
1954 } // switch (...)
1955
1956 if (Opc) {
1957 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1958
1959 // Emit the AArch64 operation with overflow check.
1960 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1961 Overflow = Value.getValue(1);
1962 }
1963 return std::make_pair(Value, Overflow);
1964}
1965
1966SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1967 RTLIB::Libcall Call) const {
1968 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
1969 return makeLibCall(DAG, Call, MVT::f128, Ops, false, SDLoc(Op)).first;
1970}
1971
1972// Returns true if the given Op is the overflow flag result of an overflow
1973// intrinsic operation.
1974static bool isOverflowIntrOpRes(SDValue Op) {
1975 unsigned Opc = Op.getOpcode();
1976 return (Op.getResNo() == 1 &&
1977 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
1978 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO));
1979}
1980
1981static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1982 SDValue Sel = Op.getOperand(0);
1983 SDValue Other = Op.getOperand(1);
1984 SDLoc dl(Sel);
1985
1986 // If the operand is an overflow checking operation, invert the condition
1987 // code and kill the Not operation. I.e., transform:
1988 // (xor (overflow_op_bool, 1))
1989 // -->
1990 // (csel 1, 0, invert(cc), overflow_op_bool)
1991 // ... which later gets transformed to just a cset instruction with an
1992 // inverted condition code, rather than a cset + eor sequence.
1993 if (isOneConstant(Other) && isOverflowIntrOpRes(Sel)) {
1994 // Only lower legal XALUO ops.
1995 if (!DAG.getTargetLoweringInfo().isTypeLegal(Sel->getValueType(0)))
1996 return SDValue();
1997
1998 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
1999 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
2000 AArch64CC::CondCode CC;
2001 SDValue Value, Overflow;
2002 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Sel.getValue(0), DAG);
2003 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
2004 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,
2005 CCVal, Overflow);
2006 }
2007 // If neither operand is a SELECT_CC, give up.
2008 if (Sel.getOpcode() != ISD::SELECT_CC)
2009 std::swap(Sel, Other);
2010 if (Sel.getOpcode() != ISD::SELECT_CC)
2011 return Op;
2012
2013 // The folding we want to perform is:
2014 // (xor x, (select_cc a, b, cc, 0, -1) )
2015 // -->
2016 // (csel x, (xor x, -1), cc ...)
2017 //
2018 // The latter will get matched to a CSINV instruction.
2019
2020 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
2021 SDValue LHS = Sel.getOperand(0);
2022 SDValue RHS = Sel.getOperand(1);
2023 SDValue TVal = Sel.getOperand(2);
2024 SDValue FVal = Sel.getOperand(3);
2025
2026 // FIXME: This could be generalized to non-integer comparisons.
2027 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
2028 return Op;
2029
2030 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
2031 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
2032
2033 // The values aren't constants, this isn't the pattern we're looking for.
2034 if (!CFVal || !CTVal)
2035 return Op;
2036
2037 // We can commute the SELECT_CC by inverting the condition. This
2038 // might be needed to make this fit into a CSINV pattern.
2039 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
2040 std::swap(TVal, FVal);
2041 std::swap(CTVal, CFVal);
2042 CC = ISD::getSetCCInverse(CC, true);
2043 }
2044
2045 // If the constants line up, perform the transform!
2046 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
2047 SDValue CCVal;
2048 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2049
2050 FVal = Other;
2051 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
2052 DAG.getConstant(-1ULL, dl, Other.getValueType()));
2053
2054 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
2055 CCVal, Cmp);
2056 }
2057
2058 return Op;
2059}
2060
2061static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2062 EVT VT = Op.getValueType();
2063
2064 // Let legalize expand this if it isn't a legal type yet.
2065 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
2066 return SDValue();
2067
2068 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
2069
2070 unsigned Opc;
2071 bool ExtraOp = false;
2072 switch (Op.getOpcode()) {
2073 default:
2074 llvm_unreachable("Invalid code")::llvm::llvm_unreachable_internal("Invalid code", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2074)
;
2075 case ISD::ADDC:
2076 Opc = AArch64ISD::ADDS;
2077 break;
2078 case ISD::SUBC:
2079 Opc = AArch64ISD::SUBS;
2080 break;
2081 case ISD::ADDE:
2082 Opc = AArch64ISD::ADCS;
2083 ExtraOp = true;
2084 break;
2085 case ISD::SUBE:
2086 Opc = AArch64ISD::SBCS;
2087 ExtraOp = true;
2088 break;
2089 }
2090
2091 if (!ExtraOp)
2092 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
2093 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
2094 Op.getOperand(2));
2095}
2096
2097static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
2098 // Let legalize expand this if it isn't a legal type yet.
2099 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
2100 return SDValue();
2101
2102 SDLoc dl(Op);
2103 AArch64CC::CondCode CC;
2104 // The actual operation that sets the overflow or carry flag.
2105 SDValue Value, Overflow;
2106 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
2107
2108 // We use 0 and 1 as false and true values.
2109 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
2110 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
2111
2112 // We use an inverted condition, because the conditional select is inverted
2113 // too. This will allow it to be selected to a single instruction:
2114 // CSINC Wd, WZR, WZR, invert(cond).
2115 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), dl, MVT::i32);
2116 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
2117 CCVal, Overflow);
2118
2119 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
2120 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
2121}
2122
2123// Prefetch operands are:
2124// 1: Address to prefetch
2125// 2: bool isWrite
2126// 3: int locality (0 = no locality ... 3 = extreme locality)
2127// 4: bool isDataCache
2128static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
2129 SDLoc DL(Op);
2130 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2131 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
2132 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2133
2134 bool IsStream = !Locality;
2135 // When the locality number is set
2136 if (Locality) {
2137 // The front-end should have filtered out the out-of-range values
2138 assert(Locality <= 3 && "Prefetch locality out-of-range")(static_cast <bool> (Locality <= 3 && "Prefetch locality out-of-range"
) ? void (0) : __assert_fail ("Locality <= 3 && \"Prefetch locality out-of-range\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2138, __extension__ __PRETTY_FUNCTION__))
;
2139 // The locality degree is the opposite of the cache speed.
2140 // Put the number the other way around.
2141 // The encoding starts at 0 for level 1
2142 Locality = 3 - Locality;
2143 }
2144
2145 // built the mask value encoding the expected behavior.
2146 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
2147 (!IsData << 3) | // IsDataCache bit
2148 (Locality << 1) | // Cache level bits
2149 (unsigned)IsStream; // Stream bit
2150 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
2151 DAG.getConstant(PrfOp, DL, MVT::i32), Op.getOperand(1));
2152}
2153
2154SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
2155 SelectionDAG &DAG) const {
2156 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering")(static_cast <bool> (Op.getValueType() == MVT::f128 &&
"Unexpected lowering") ? void (0) : __assert_fail ("Op.getValueType() == MVT::f128 && \"Unexpected lowering\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2156, __extension__ __PRETTY_FUNCTION__))
;
2157
2158 RTLIB::Libcall LC;
2159 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
2160
2161 return LowerF128Call(Op, DAG, LC);
2162}
2163
2164SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
2165 SelectionDAG &DAG) const {
2166 if (Op.getOperand(0).getValueType() != MVT::f128) {
2167 // It's legal except when f128 is involved
2168 return Op;
2169 }
2170
2171 RTLIB::Libcall LC;
2172 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
2173
2174 // FP_ROUND node has a second operand indicating whether it is known to be
2175 // precise. That doesn't take part in the LibCall so we can't directly use
2176 // LowerF128Call.
2177 SDValue SrcVal = Op.getOperand(0);
2178 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
2179 SDLoc(Op)).first;
2180}
2181
2182static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2183 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
2184 // Any additional optimization in this function should be recorded
2185 // in the cost tables.
2186 EVT InVT = Op.getOperand(0).getValueType();
2187 EVT VT = Op.getValueType();
2188 unsigned NumElts = InVT.getVectorNumElements();
2189
2190 // f16 vectors are promoted to f32 before a conversion.
2191 if (InVT.getVectorElementType() == MVT::f16) {
2192 MVT NewVT = MVT::getVectorVT(MVT::f32, NumElts);
2193 SDLoc dl(Op);
2194 return DAG.getNode(
2195 Op.getOpcode(), dl, Op.getValueType(),
2196 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0)));
2197 }
2198
2199 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
2200 SDLoc dl(Op);
2201 SDValue Cv =
2202 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
2203 Op.getOperand(0));
2204 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
2205 }
2206
2207 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
2208 SDLoc dl(Op);
2209 MVT ExtVT =
2210 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
2211 VT.getVectorNumElements());
2212 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
2213 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
2214 }
2215
2216 // Type changing conversions are illegal.
2217 return Op;
2218}
2219
2220SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
2221 SelectionDAG &DAG) const {
2222 if (Op.getOperand(0).getValueType().isVector())
2223 return LowerVectorFP_TO_INT(Op, DAG);
2224
2225 // f16 conversions are promoted to f32 when full fp16 is not supported.
2226 if (Op.getOperand(0).getValueType() == MVT::f16 &&
2227 !Subtarget->hasFullFP16()) {
2228 SDLoc dl(Op);
2229 return DAG.getNode(
2230 Op.getOpcode(), dl, Op.getValueType(),
2231 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0)));
2232 }
2233
2234 if (Op.getOperand(0).getValueType() != MVT::f128) {
2235 // It's legal except when f128 is involved
2236 return Op;
2237 }
2238
2239 RTLIB::Libcall LC;
2240 if (Op.getOpcode() == ISD::FP_TO_SINT)
2241 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2242 else
2243 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2244
2245 SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
2246 return makeLibCall(DAG, LC, Op.getValueType(), Ops, false, SDLoc(Op)).first;
2247}
2248
2249static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2250 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
2251 // Any additional optimization in this function should be recorded
2252 // in the cost tables.
2253 EVT VT = Op.getValueType();
2254 SDLoc dl(Op);
2255 SDValue In = Op.getOperand(0);
2256 EVT InVT = In.getValueType();
2257
2258 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
2259 MVT CastVT =
2260 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
2261 InVT.getVectorNumElements());
2262 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
2263 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl));
2264 }
2265
2266 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
2267 unsigned CastOpc =
2268 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2269 EVT CastVT = VT.changeVectorElementTypeToInteger();
2270 In = DAG.getNode(CastOpc, dl, CastVT, In);
2271 return DAG.getNode(Op.getOpcode(), dl, VT, In);
2272 }
2273
2274 return Op;
2275}
2276
2277SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
2278 SelectionDAG &DAG) const {
2279 if (Op.getValueType().isVector())
2280 return LowerVectorINT_TO_FP(Op, DAG);
2281
2282 // f16 conversions are promoted to f32 when full fp16 is not supported.
2283 if (Op.getValueType() == MVT::f16 &&
2284 !Subtarget->hasFullFP16()) {
2285 SDLoc dl(Op);
2286 return DAG.getNode(
2287 ISD::FP_ROUND, dl, MVT::f16,
2288 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)),
2289 DAG.getIntPtrConstant(0, dl));
2290 }
2291
2292 // i128 conversions are libcalls.
2293 if (Op.getOperand(0).getValueType() == MVT::i128)
2294 return SDValue();
2295
2296 // Other conversions are legal, unless it's to the completely software-based
2297 // fp128.
2298 if (Op.getValueType() != MVT::f128)
2299 return Op;
2300
2301 RTLIB::Libcall LC;
2302 if (Op.getOpcode() == ISD::SINT_TO_FP)
2303 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2304 else
2305 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2306
2307 return LowerF128Call(Op, DAG, LC);
2308}
2309
2310SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
2311 SelectionDAG &DAG) const {
2312 // For iOS, we want to call an alternative entry point: __sincos_stret,
2313 // which returns the values in two S / D registers.
2314 SDLoc dl(Op);
2315 SDValue Arg = Op.getOperand(0);
2316 EVT ArgVT = Arg.getValueType();
2317 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2318
2319 ArgListTy Args;
2320 ArgListEntry Entry;
2321
2322 Entry.Node = Arg;
2323 Entry.Ty = ArgTy;
2324 Entry.IsSExt = false;
2325 Entry.IsZExt = false;
2326 Args.push_back(Entry);
2327
2328 RTLIB::Libcall LC = ArgVT == MVT::f64 ? RTLIB::SINCOS_STRET_F64
2329 : RTLIB::SINCOS_STRET_F32;
2330 const char *LibcallName = getLibcallName(LC);
2331 SDValue Callee =
2332 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout()));
2333
2334 StructType *RetTy = StructType::get(ArgTy, ArgTy);
2335 TargetLowering::CallLoweringInfo CLI(DAG);
2336 CLI.setDebugLoc(dl)
2337 .setChain(DAG.getEntryNode())
2338 .setLibCallee(CallingConv::Fast, RetTy, Callee, std::move(Args));
2339
2340 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2341 return CallResult.first;
2342}
2343
2344static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
2345 if (Op.getValueType() != MVT::f16)
2346 return SDValue();
2347
2348 assert(Op.getOperand(0).getValueType() == MVT::i16)(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::i16) ? void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::i16"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2348, __extension__ __PRETTY_FUNCTION__))
;
2349 SDLoc DL(Op);
2350
2351 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
2352 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
2353 return SDValue(
2354 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
2355 DAG.getTargetConstant(AArch64::hsub, DL, MVT::i32)),
2356 0);
2357}
2358
2359static EVT getExtensionTo64Bits(const EVT &OrigVT) {
2360 if (OrigVT.getSizeInBits() >= 64)
2361 return OrigVT;
2362
2363 assert(OrigVT.isSimple() && "Expecting a simple value type")(static_cast <bool> (OrigVT.isSimple() && "Expecting a simple value type"
) ? void (0) : __assert_fail ("OrigVT.isSimple() && \"Expecting a simple value type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2363, __extension__ __PRETTY_FUNCTION__))
;
2364
2365 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
2366 switch (OrigSimpleTy) {
2367 default: llvm_unreachable("Unexpected Vector Type")::llvm::llvm_unreachable_internal("Unexpected Vector Type", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2367)
;
2368 case MVT::v2i8:
2369 case MVT::v2i16:
2370 return MVT::v2i32;
2371 case MVT::v4i8:
2372 return MVT::v4i16;
2373 }
2374}
2375
2376static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
2377 const EVT &OrigTy,
2378 const EVT &ExtTy,
2379 unsigned ExtOpcode) {
2380 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
2381 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
2382 // 64-bits we need to insert a new extension so that it will be 64-bits.
2383 assert(ExtTy.is128BitVector() && "Unexpected extension size")(static_cast <bool> (ExtTy.is128BitVector() && "Unexpected extension size"
) ? void (0) : __assert_fail ("ExtTy.is128BitVector() && \"Unexpected extension size\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2383, __extension__ __PRETTY_FUNCTION__))
;
2384 if (OrigTy.getSizeInBits() >= 64)
2385 return N;
2386
2387 // Must extend size to at least 64 bits to be used as an operand for VMULL.
2388 EVT NewVT = getExtensionTo64Bits(OrigTy);
2389
2390 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
2391}
2392
2393static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
2394 bool isSigned) {
2395 EVT VT = N->getValueType(0);
2396
2397 if (N->getOpcode() != ISD::BUILD_VECTOR)
2398 return false;
2399
2400 for (const SDValue &Elt : N->op_values()) {
2401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
2402 unsigned EltSize = VT.getScalarSizeInBits();
2403 unsigned HalfSize = EltSize / 2;
2404 if (isSigned) {
2405 if (!isIntN(HalfSize, C->getSExtValue()))
2406 return false;
2407 } else {
2408 if (!isUIntN(HalfSize, C->getZExtValue()))
2409 return false;
2410 }
2411 continue;
2412 }
2413 return false;
2414 }
2415
2416 return true;
2417}
2418
2419static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
2420 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
2421 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
2422 N->getOperand(0)->getValueType(0),
2423 N->getValueType(0),
2424 N->getOpcode());
2425
2426 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR")(static_cast <bool> (N->getOpcode() == ISD::BUILD_VECTOR
&& "expected BUILD_VECTOR") ? void (0) : __assert_fail
("N->getOpcode() == ISD::BUILD_VECTOR && \"expected BUILD_VECTOR\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2426, __extension__ __PRETTY_FUNCTION__))
;
2427 EVT VT = N->getValueType(0);
2428 SDLoc dl(N);
2429 unsigned EltSize = VT.getScalarSizeInBits() / 2;
2430 unsigned NumElts = VT.getVectorNumElements();
2431 MVT TruncVT = MVT::getIntegerVT(EltSize);
2432 SmallVector<SDValue, 8> Ops;
2433 for (unsigned i = 0; i != NumElts; ++i) {
2434 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
2435 const APInt &CInt = C->getAPIntValue();
2436 // Element types smaller than 32 bits are not legal, so use i32 elements.
2437 // The values are implicitly truncated so sext vs. zext doesn't matter.
2438 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
2439 }
2440 return DAG.getBuildVector(MVT::getVectorVT(TruncVT, NumElts), dl, Ops);
2441}
2442
2443static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
2444 return N->getOpcode() == ISD::SIGN_EXTEND ||
2445 isExtendedBUILD_VECTOR(N, DAG, true);
2446}
2447
2448static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
2449 return N->getOpcode() == ISD::ZERO_EXTEND ||
2450 isExtendedBUILD_VECTOR(N, DAG, false);
2451}
2452
2453static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
2454 unsigned Opcode = N->getOpcode();
2455 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2456 SDNode *N0 = N->getOperand(0).getNode();
2457 SDNode *N1 = N->getOperand(1).getNode();
2458 return N0->hasOneUse() && N1->hasOneUse() &&
2459 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
2460 }
2461 return false;
2462}
2463
2464static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
2465 unsigned Opcode = N->getOpcode();
2466 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2467 SDNode *N0 = N->getOperand(0).getNode();
2468 SDNode *N1 = N->getOperand(1).getNode();
2469 return N0->hasOneUse() && N1->hasOneUse() &&
2470 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
2471 }
2472 return false;
2473}
2474
2475static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
2476 // Multiplications are only custom-lowered for 128-bit vectors so that
2477 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2478 EVT VT = Op.getValueType();
2479 assert(VT.is128BitVector() && VT.isInteger() &&(static_cast <bool> (VT.is128BitVector() && VT.
isInteger() && "unexpected type for custom-lowering ISD::MUL"
) ? void (0) : __assert_fail ("VT.is128BitVector() && VT.isInteger() && \"unexpected type for custom-lowering ISD::MUL\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2480, __extension__ __PRETTY_FUNCTION__))
2480 "unexpected type for custom-lowering ISD::MUL")(static_cast <bool> (VT.is128BitVector() && VT.
isInteger() && "unexpected type for custom-lowering ISD::MUL"
) ? void (0) : __assert_fail ("VT.is128BitVector() && VT.isInteger() && \"unexpected type for custom-lowering ISD::MUL\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2480, __extension__ __PRETTY_FUNCTION__))
;
2481 SDNode *N0 = Op.getOperand(0).getNode();
2482 SDNode *N1 = Op.getOperand(1).getNode();
2483 unsigned NewOpc = 0;
2484 bool isMLA = false;
2485 bool isN0SExt = isSignExtended(N0, DAG);
2486 bool isN1SExt = isSignExtended(N1, DAG);
2487 if (isN0SExt && isN1SExt)
2488 NewOpc = AArch64ISD::SMULL;
2489 else {
2490 bool isN0ZExt = isZeroExtended(N0, DAG);
2491 bool isN1ZExt = isZeroExtended(N1, DAG);
2492 if (isN0ZExt && isN1ZExt)
2493 NewOpc = AArch64ISD::UMULL;
2494 else if (isN1SExt || isN1ZExt) {
2495 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
2496 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
2497 if (isN1SExt && isAddSubSExt(N0, DAG)) {
2498 NewOpc = AArch64ISD::SMULL;
2499 isMLA = true;
2500 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
2501 NewOpc = AArch64ISD::UMULL;
2502 isMLA = true;
2503 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
2504 std::swap(N0, N1);
2505 NewOpc = AArch64ISD::UMULL;
2506 isMLA = true;
2507 }
2508 }
2509
2510 if (!NewOpc) {
2511 if (VT == MVT::v2i64)
2512 // Fall through to expand this. It is not legal.
2513 return SDValue();
2514 else
2515 // Other vector multiplications are legal.
2516 return Op;
2517 }
2518 }
2519
2520 // Legalize to a S/UMULL instruction
2521 SDLoc DL(Op);
2522 SDValue Op0;
2523 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
2524 if (!isMLA) {
2525 Op0 = skipExtensionForVectorMULL(N0, DAG);
2526 assert(Op0.getValueType().is64BitVector() &&(static_cast <bool> (Op0.getValueType().is64BitVector()
&& Op1.getValueType().is64BitVector() && "unexpected types for extended operands to VMULL"
) ? void (0) : __assert_fail ("Op0.getValueType().is64BitVector() && Op1.getValueType().is64BitVector() && \"unexpected types for extended operands to VMULL\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2528, __extension__ __PRETTY_FUNCTION__))
2527 Op1.getValueType().is64BitVector() &&(static_cast <bool> (Op0.getValueType().is64BitVector()
&& Op1.getValueType().is64BitVector() && "unexpected types for extended operands to VMULL"
) ? void (0) : __assert_fail ("Op0.getValueType().is64BitVector() && Op1.getValueType().is64BitVector() && \"unexpected types for extended operands to VMULL\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2528, __extension__ __PRETTY_FUNCTION__))
2528 "unexpected types for extended operands to VMULL")(static_cast <bool> (Op0.getValueType().is64BitVector()
&& Op1.getValueType().is64BitVector() && "unexpected types for extended operands to VMULL"
) ? void (0) : __assert_fail ("Op0.getValueType().is64BitVector() && Op1.getValueType().is64BitVector() && \"unexpected types for extended operands to VMULL\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2528, __extension__ __PRETTY_FUNCTION__))
;
2529 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
2530 }
2531 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
2532 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
2533 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
2534 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
2535 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
2536 EVT Op1VT = Op1.getValueType();
2537 return DAG.getNode(N0->getOpcode(), DL, VT,
2538 DAG.getNode(NewOpc, DL, VT,
2539 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
2540 DAG.getNode(NewOpc, DL, VT,
2541 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
2542}
2543
2544SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2545 SelectionDAG &DAG) const {
2546 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2547 SDLoc dl(Op);
2548 switch (IntNo) {
2549 default: return SDValue(); // Don't custom lower most intrinsics.
2550 case Intrinsic::thread_pointer: {
2551 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2552 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT);
2553 }
2554 case Intrinsic::aarch64_neon_abs:
2555 return DAG.getNode(ISD::ABS, dl, Op.getValueType(),
2556 Op.getOperand(1));
2557 case Intrinsic::aarch64_neon_smax:
2558 return DAG.getNode(ISD::SMAX, dl, Op.getValueType(),
2559 Op.getOperand(1), Op.getOperand(2));
2560 case Intrinsic::aarch64_neon_umax:
2561 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
2562 Op.getOperand(1), Op.getOperand(2));
2563 case Intrinsic::aarch64_neon_smin:
2564 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(),
2565 Op.getOperand(1), Op.getOperand(2));
2566 case Intrinsic::aarch64_neon_umin:
2567 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(),
2568 Op.getOperand(1), Op.getOperand(2));
2569 }
2570}
2571
2572SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2573 SelectionDAG &DAG) const {
2574 DEBUG(dbgs() << "Custom lowering: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Custom lowering: "; } }
while (false)
;
2575 DEBUG(Op.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { Op.dump(); } } while (false)
;
2576
2577 switch (Op.getOpcode()) {
2578 default:
2579 llvm_unreachable("unimplemented operand")::llvm::llvm_unreachable_internal("unimplemented operand", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2579)
;
2580 return SDValue();
2581 case ISD::BITCAST:
2582 return LowerBITCAST(Op, DAG);
2583 case ISD::GlobalAddress:
2584 return LowerGlobalAddress(Op, DAG);
2585 case ISD::GlobalTLSAddress:
2586 return LowerGlobalTLSAddress(Op, DAG);
2587 case ISD::SETCC:
2588 return LowerSETCC(Op, DAG);
2589 case ISD::BR_CC:
2590 return LowerBR_CC(Op, DAG);
2591 case ISD::SELECT:
2592 return LowerSELECT(Op, DAG);
2593 case ISD::SELECT_CC:
2594 return LowerSELECT_CC(Op, DAG);
2595 case ISD::JumpTable:
2596 return LowerJumpTable(Op, DAG);
2597 case ISD::ConstantPool:
2598 return LowerConstantPool(Op, DAG);
2599 case ISD::BlockAddress:
2600 return LowerBlockAddress(Op, DAG);
2601 case ISD::VASTART:
2602 return LowerVASTART(Op, DAG);
2603 case ISD::VACOPY:
2604 return LowerVACOPY(Op, DAG);
2605 case ISD::VAARG:
2606 return LowerVAARG(Op, DAG);
2607 case ISD::ADDC:
2608 case ISD::ADDE:
2609 case ISD::SUBC:
2610 case ISD::SUBE:
2611 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2612 case ISD::SADDO:
2613 case ISD::UADDO:
2614 case ISD::SSUBO:
2615 case ISD::USUBO:
2616 case ISD::SMULO:
2617 case ISD::UMULO:
2618 return LowerXALUO(Op, DAG);
2619 case ISD::FADD:
2620 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
2621 case ISD::FSUB:
2622 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
2623 case ISD::FMUL:
2624 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
2625 case ISD::FDIV:
2626 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
2627 case ISD::FP_ROUND:
2628 return LowerFP_ROUND(Op, DAG);
2629 case ISD::FP_EXTEND:
2630 return LowerFP_EXTEND(Op, DAG);
2631 case ISD::FRAMEADDR:
2632 return LowerFRAMEADDR(Op, DAG);
2633 case ISD::RETURNADDR:
2634 return LowerRETURNADDR(Op, DAG);
2635 case ISD::INSERT_VECTOR_ELT:
2636 return LowerINSERT_VECTOR_ELT(Op, DAG);
2637 case ISD::EXTRACT_VECTOR_ELT:
2638 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2639 case ISD::BUILD_VECTOR:
2640 return LowerBUILD_VECTOR(Op, DAG);
2641 case ISD::VECTOR_SHUFFLE:
2642 return LowerVECTOR_SHUFFLE(Op, DAG);
2643 case ISD::EXTRACT_SUBVECTOR:
2644 return LowerEXTRACT_SUBVECTOR(Op, DAG);
2645 case ISD::SRA:
2646 case ISD::SRL:
2647 case ISD::SHL:
2648 return LowerVectorSRA_SRL_SHL(Op, DAG);
2649 case ISD::SHL_PARTS:
2650 return LowerShiftLeftParts(Op, DAG);
2651 case ISD::SRL_PARTS:
2652 case ISD::SRA_PARTS:
2653 return LowerShiftRightParts(Op, DAG);
2654 case ISD::CTPOP:
2655 return LowerCTPOP(Op, DAG);
2656 case ISD::FCOPYSIGN:
2657 return LowerFCOPYSIGN(Op, DAG);
2658 case ISD::AND:
2659 return LowerVectorAND(Op, DAG);
2660 case ISD::OR:
2661 return LowerVectorOR(Op, DAG);
2662 case ISD::XOR:
2663 return LowerXOR(Op, DAG);
2664 case ISD::PREFETCH:
2665 return LowerPREFETCH(Op, DAG);
2666 case ISD::SINT_TO_FP:
2667 case ISD::UINT_TO_FP:
2668 return LowerINT_TO_FP(Op, DAG);
2669 case ISD::FP_TO_SINT:
2670 case ISD::FP_TO_UINT:
2671 return LowerFP_TO_INT(Op, DAG);
2672 case ISD::FSINCOS:
2673 return LowerFSINCOS(Op, DAG);
2674 case ISD::MUL:
2675 return LowerMUL(Op, DAG);
2676 case ISD::INTRINSIC_WO_CHAIN:
2677 return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2678 case ISD::VECREDUCE_ADD:
2679 case ISD::VECREDUCE_SMAX:
2680 case ISD::VECREDUCE_SMIN:
2681 case ISD::VECREDUCE_UMAX:
2682 case ISD::VECREDUCE_UMIN:
2683 case ISD::VECREDUCE_FMAX:
2684 case ISD::VECREDUCE_FMIN:
2685 return LowerVECREDUCE(Op, DAG);
2686 case ISD::ATOMIC_LOAD_SUB:
2687 return LowerATOMIC_LOAD_SUB(Op, DAG);
2688 case ISD::ATOMIC_LOAD_AND:
2689 return LowerATOMIC_LOAD_AND(Op, DAG);
2690 }
2691}
2692
2693//===----------------------------------------------------------------------===//
2694// Calling Convention Implementation
2695//===----------------------------------------------------------------------===//
2696
2697#include "AArch64GenCallingConv.inc"
2698
2699/// Selects the correct CCAssignFn for a given CallingConvention value.
2700CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2701 bool IsVarArg) const {
2702 switch (CC) {
2703 default:
2704 report_fatal_error("Unsupported calling convention.");
2705 case CallingConv::WebKit_JS:
2706 return CC_AArch64_WebKit_JS;
2707 case CallingConv::GHC:
2708 return CC_AArch64_GHC;
2709 case CallingConv::C:
2710 case CallingConv::Fast:
2711 case CallingConv::PreserveMost:
2712 case CallingConv::CXX_FAST_TLS:
2713 case CallingConv::Swift:
2714 if (Subtarget->isTargetWindows() && IsVarArg)
2715 return CC_AArch64_Win64_VarArg;
2716 if (!Subtarget->isTargetDarwin())
2717 return CC_AArch64_AAPCS;
2718 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
2719 case CallingConv::Win64:
2720 return IsVarArg ? CC_AArch64_Win64_VarArg : CC_AArch64_AAPCS;
2721 }
2722}
2723
2724CCAssignFn *
2725AArch64TargetLowering::CCAssignFnForReturn(CallingConv::ID CC) const {
2726 return CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
2727 : RetCC_AArch64_AAPCS;
2728}
2729
2730SDValue AArch64TargetLowering::LowerFormalArguments(
2731 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2732 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
2733 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
2734 MachineFunction &MF = DAG.getMachineFunction();
2735 MachineFrameInfo &MFI = MF.getFrameInfo();
2736 bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
2737
2738 // Assign locations to all of the incoming arguments.
2739 SmallVector<CCValAssign, 16> ArgLocs;
2740 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2741 *DAG.getContext());
2742
2743 // At this point, Ins[].VT may already be promoted to i32. To correctly
2744 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2745 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2746 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2747 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2748 // LocVT.
2749 unsigned NumArgs = Ins.size();
2750 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
2751 unsigned CurArgIdx = 0;
2752 for (unsigned i = 0; i != NumArgs; ++i) {
2753 MVT ValVT = Ins[i].VT;
2754 if (Ins[i].isOrigArg()) {
2755 std::advance(CurOrigArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2756 CurArgIdx = Ins[i].getOrigArgIndex();
2757
2758 // Get type of the original argument.
2759 EVT ActualVT = getValueType(DAG.getDataLayout(), CurOrigArg->getType(),
2760 /*AllowUnknown*/ true);
2761 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2762 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2763 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2764 ValVT = MVT::i8;
2765 else if (ActualMVT == MVT::i16)
2766 ValVT = MVT::i16;
2767 }
2768 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2769 bool Res =
2770 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2771 assert(!Res && "Call operand has unhandled type")(static_cast <bool> (!Res && "Call operand has unhandled type"
) ? void (0) : __assert_fail ("!Res && \"Call operand has unhandled type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2771, __extension__ __PRETTY_FUNCTION__))
;
2772 (void)Res;
2773 }
2774 assert(ArgLocs.size() == Ins.size())(static_cast <bool> (ArgLocs.size() == Ins.size()) ? void
(0) : __assert_fail ("ArgLocs.size() == Ins.size()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2774, __extension__ __PRETTY_FUNCTION__))
;
2775 SmallVector<SDValue, 16> ArgValues;
2776 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2777 CCValAssign &VA = ArgLocs[i];
2778
2779 if (Ins[i].Flags.isByVal()) {
2780 // Byval is used for HFAs in the PCS, but the system should work in a
2781 // non-compliant manner for larger structs.
2782 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2783 int Size = Ins[i].Flags.getByValSize();
2784 unsigned NumRegs = (Size + 7) / 8;
2785
2786 // FIXME: This works on big-endian for composite byvals, which are the common
2787 // case. It should also work for fundamental types too.
2788 unsigned FrameIdx =
2789 MFI.CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2790 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrVT);
2791 InVals.push_back(FrameIdxN);
2792
2793 continue;
2794 }
2795
2796 if (VA.isRegLoc()) {
2797 // Arguments stored in registers.
2798 EVT RegVT = VA.getLocVT();
2799
2800 SDValue ArgValue;
2801 const TargetRegisterClass *RC;
2802
2803 if (RegVT == MVT::i32)
2804 RC = &AArch64::GPR32RegClass;
2805 else if (RegVT == MVT::i64)
2806 RC = &AArch64::GPR64RegClass;
2807 else if (RegVT == MVT::f16)
2808 RC = &AArch64::FPR16RegClass;
2809 else if (RegVT == MVT::f32)
2810 RC = &AArch64::FPR32RegClass;
2811 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2812 RC = &AArch64::FPR64RegClass;
2813 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2814 RC = &AArch64::FPR128RegClass;
2815 else
2816 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2816)
;
2817
2818 // Transform the arguments in physical registers into virtual ones.
2819 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2820 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2821
2822 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2823 // to 64 bits. Insert an assert[sz]ext to capture this, then
2824 // truncate to the right size.
2825 switch (VA.getLocInfo()) {
2826 default:
2827 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2827)
;
2828 case CCValAssign::Full:
2829 break;
2830 case CCValAssign::BCvt:
2831 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2832 break;
2833 case CCValAssign::AExt:
2834 case CCValAssign::SExt:
2835 case CCValAssign::ZExt:
2836 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2837 // nodes after our lowering.
2838 assert(RegVT == Ins[i].VT && "incorrect register location selected")(static_cast <bool> (RegVT == Ins[i].VT && "incorrect register location selected"
) ? void (0) : __assert_fail ("RegVT == Ins[i].VT && \"incorrect register location selected\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2838, __extension__ __PRETTY_FUNCTION__))
;
2839 break;
2840 }
2841
2842 InVals.push_back(ArgValue);
2843
2844 } else { // VA.isRegLoc()
2845 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem")(static_cast <bool> (VA.isMemLoc() && "CCValAssign is neither reg nor mem"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"CCValAssign is neither reg nor mem\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 2845, __extension__ __PRETTY_FUNCTION__))
;
2846 unsigned ArgOffset = VA.getLocMemOffset();
2847 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2848
2849 uint32_t BEAlign = 0;
2850 if (!Subtarget->isLittleEndian() && ArgSize < 8 &&
2851 !Ins[i].Flags.isInConsecutiveRegs())
2852 BEAlign = 8 - ArgSize;
2853
2854 int FI = MFI.CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2855
2856 // Create load nodes to retrieve arguments from the stack.
2857 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2858 SDValue ArgValue;
2859
2860 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2861 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2862 MVT MemVT = VA.getValVT();
2863
2864 switch (VA.getLocInfo()) {
2865 default:
2866 break;
2867 case CCValAssign::BCvt:
2868 MemVT = VA.getLocVT();
2869 break;
2870 case CCValAssign::SExt:
2871 ExtType = ISD::SEXTLOAD;
2872 break;
2873 case CCValAssign::ZExt:
2874 ExtType = ISD::ZEXTLOAD;
2875 break;
2876 case CCValAssign::AExt:
2877 ExtType = ISD::EXTLOAD;
2878 break;
2879 }
2880
2881 ArgValue = DAG.getExtLoad(
2882 ExtType, DL, VA.getLocVT(), Chain, FIN,
2883 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
2884 MemVT);
2885
2886 InVals.push_back(ArgValue);
2887 }
2888 }
2889
2890 // varargs
2891 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2892 if (isVarArg) {
2893 if (!Subtarget->isTargetDarwin() || IsWin64) {
2894 // The AAPCS variadic function ABI is identical to the non-variadic
2895 // one. As a result there may be more arguments in registers and we should
2896 // save them for future reference.
2897 // Win64 variadic functions also pass arguments in registers, but all float
2898 // arguments are passed in integer registers.
2899 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2900 }
2901
2902 // This will point to the next argument passed via stack.
2903 unsigned StackOffset = CCInfo.getNextStackOffset();
2904 // We currently pass all varargs at 8-byte alignment.
2905 StackOffset = ((StackOffset + 7) & ~7);
2906 FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
2907 }
2908
2909 unsigned StackArgSize = CCInfo.getNextStackOffset();
2910 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2911 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2912 // This is a non-standard ABI so by fiat I say we're allowed to make full
2913 // use of the stack area to be popped, which must be aligned to 16 bytes in
2914 // any case:
2915 StackArgSize = alignTo(StackArgSize, 16);
2916
2917 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2918 // a multiple of 16.
2919 FuncInfo->setArgumentStackToRestore(StackArgSize);
2920
2921 // This realignment carries over to the available bytes below. Our own
2922 // callers will guarantee the space is free by giving an aligned value to
2923 // CALLSEQ_START.
2924 }
2925 // Even if we're not expected to free up the space, it's useful to know how
2926 // much is there while considering tail calls (because we can reuse it).
2927 FuncInfo->setBytesInStackArgArea(StackArgSize);
2928
2929 return Chain;
2930}
2931
2932void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2933 SelectionDAG &DAG,
2934 const SDLoc &DL,
2935 SDValue &Chain) const {
2936 MachineFunction &MF = DAG.getMachineFunction();
2937 MachineFrameInfo &MFI = MF.getFrameInfo();
2938 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2939 auto PtrVT = getPointerTy(DAG.getDataLayout());
2940 bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
2941
2942 SmallVector<SDValue, 8> MemOps;
2943
2944 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2945 AArch64::X3, AArch64::X4, AArch64::X5,
2946 AArch64::X6, AArch64::X7 };
2947 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2948 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(GPRArgRegs);
2949
2950 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2951 int GPRIdx = 0;
2952 if (GPRSaveSize != 0) {
2953 if (IsWin64) {
2954 GPRIdx = MFI.CreateFixedObject(GPRSaveSize, -(int)GPRSaveSize, false);
2955 if (GPRSaveSize & 15)
2956 // The extra size here, if triggered, will always be 8.
2957 MFI.CreateFixedObject(16 - (GPRSaveSize & 15), -(int)alignTo(GPRSaveSize, 16), false);
2958 } else
2959 GPRIdx = MFI.CreateStackObject(GPRSaveSize, 8, false);
2960
2961 SDValue FIN = DAG.getFrameIndex(GPRIdx, PtrVT);
2962
2963 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2964 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2965 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2966 SDValue Store = DAG.getStore(
2967 Val.getValue(1), DL, Val, FIN,
2968 IsWin64
2969 ? MachinePointerInfo::getFixedStack(DAG.getMachineFunction(),
2970 GPRIdx,
2971 (i - FirstVariadicGPR) * 8)
2972 : MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 8));
2973 MemOps.push_back(Store);
2974 FIN =
2975 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2976 }
2977 }
2978 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2979 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2980
2981 if (Subtarget->hasFPARMv8() && !IsWin64) {
2982 static const MCPhysReg FPRArgRegs[] = {
2983 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2984 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2985 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2986 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(FPRArgRegs);
2987
2988 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2989 int FPRIdx = 0;
2990 if (FPRSaveSize != 0) {
2991 FPRIdx = MFI.CreateStackObject(FPRSaveSize, 16, false);
2992
2993 SDValue FIN = DAG.getFrameIndex(FPRIdx, PtrVT);
2994
2995 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2996 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2997 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2998
2999 SDValue Store = DAG.getStore(
3000 Val.getValue(1), DL, Val, FIN,
3001 MachinePointerInfo::getStack(DAG.getMachineFunction(), i * 16));
3002 MemOps.push_back(Store);
3003 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
3004 DAG.getConstant(16, DL, PtrVT));
3005 }
3006 }
3007 FuncInfo->setVarArgsFPRIndex(FPRIdx);
3008 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
3009 }
3010
3011 if (!MemOps.empty()) {
3012 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3013 }
3014}
3015
3016/// LowerCallResult - Lower the result values of a call into the
3017/// appropriate copies out of appropriate physical registers.
3018SDValue AArch64TargetLowering::LowerCallResult(
3019 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
3020 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3021 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
3022 SDValue ThisVal) const {
3023 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3024 ? RetCC_AArch64_WebKit_JS
3025 : RetCC_AArch64_AAPCS;
3026 // Assign locations to each value returned by this call.
3027 SmallVector<CCValAssign, 16> RVLocs;
3028 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3029 *DAG.getContext());
3030 CCInfo.AnalyzeCallResult(Ins, RetCC);
3031
3032 // Copy all of the result registers out of their specified physreg.
3033 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3034 CCValAssign VA = RVLocs[i];
3035
3036 // Pass 'this' value directly from the argument to return value, to avoid
3037 // reg unit interference
3038 if (i == 0 && isThisReturn) {
3039 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i64 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i64 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3040, __extension__ __PRETTY_FUNCTION__))
3040 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i64 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i64 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3040, __extension__ __PRETTY_FUNCTION__))
;
3041 InVals.push_back(ThisVal);
3042 continue;
3043 }
3044
3045 SDValue Val =
3046 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
3047 Chain = Val.getValue(1);
3048 InFlag = Val.getValue(2);
3049
3050 switch (VA.getLocInfo()) {
3051 default:
3052 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3052)
;
3053 case CCValAssign::Full:
3054 break;
3055 case CCValAssign::BCvt:
3056 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3057 break;
3058 }
3059
3060 InVals.push_back(Val);
3061 }
3062
3063 return Chain;
3064}
3065
3066/// Return true if the calling convention is one that we can guarantee TCO for.
3067static bool canGuaranteeTCO(CallingConv::ID CC) {
3068 return CC == CallingConv::Fast;
3069}
3070
3071/// Return true if we might ever do TCO for calls with this calling convention.
3072static bool mayTailCallThisCC(CallingConv::ID CC) {
3073 switch (CC) {
3074 case CallingConv::C:
3075 case CallingConv::PreserveMost:
3076 case CallingConv::Swift:
3077 return true;
3078 default:
3079 return canGuaranteeTCO(CC);
3080 }
3081}
3082
3083bool AArch64TargetLowering::isEligibleForTailCallOptimization(
3084 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3085 const SmallVectorImpl<ISD::OutputArg> &Outs,
3086 const SmallVectorImpl<SDValue> &OutVals,
3087 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3088 if (!mayTailCallThisCC(CalleeCC))
3089 return false;
3090
3091 MachineFunction &MF = DAG.getMachineFunction();
3092 const Function &CallerF = MF.getFunction();
3093 CallingConv::ID CallerCC = CallerF.getCallingConv();
3094 bool CCMatch = CallerCC == CalleeCC;
3095
3096 // Byval parameters hand the function a pointer directly into the stack area
3097 // we want to reuse during a tail call. Working around this *is* possible (see
3098 // X86) but less efficient and uglier in LowerCall.
3099 for (Function::const_arg_iterator i = CallerF.arg_begin(),
3100 e = CallerF.arg_end();
3101 i != e; ++i)
3102 if (i->hasByValAttr())
3103 return false;
3104
3105 if (getTargetMachine().Options.GuaranteedTailCallOpt)
3106 return canGuaranteeTCO(CalleeCC) && CCMatch;
3107
3108 // Externally-defined functions with weak linkage should not be
3109 // tail-called on AArch64 when the OS does not support dynamic
3110 // pre-emption of symbols, as the AAELF spec requires normal calls
3111 // to undefined weak functions to be replaced with a NOP or jump to the
3112 // next instruction. The behaviour of branch instructions in this
3113 // situation (as used for tail calls) is implementation-defined, so we
3114 // cannot rely on the linker replacing the tail call with a return.
3115 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3116 const GlobalValue *GV = G->getGlobal();
3117 const Triple &TT = getTargetMachine().getTargetTriple();
3118 if (GV->hasExternalWeakLinkage() &&
3119 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
3120 return false;
3121 }
3122
3123 // Now we search for cases where we can use a tail call without changing the
3124 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
3125 // concept.
3126
3127 // I want anyone implementing a new calling convention to think long and hard
3128 // about this assert.
3129 assert((!isVarArg || CalleeCC == CallingConv::C) &&(static_cast <bool> ((!isVarArg || CalleeCC == CallingConv
::C) && "Unexpected variadic calling convention") ? void
(0) : __assert_fail ("(!isVarArg || CalleeCC == CallingConv::C) && \"Unexpected variadic calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3130, __extension__ __PRETTY_FUNCTION__))
3130 "Unexpected variadic calling convention")(static_cast <bool> ((!isVarArg || CalleeCC == CallingConv
::C) && "Unexpected variadic calling convention") ? void
(0) : __assert_fail ("(!isVarArg || CalleeCC == CallingConv::C) && \"Unexpected variadic calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3130, __extension__ __PRETTY_FUNCTION__))
;
3131
3132 LLVMContext &C = *DAG.getContext();
3133 if (isVarArg && !Outs.empty()) {
3134 // At least two cases here: if caller is fastcc then we can't have any
3135 // memory arguments (we'd be expected to clean up the stack afterwards). If
3136 // caller is C then we could potentially use its argument area.
3137
3138 // FIXME: for now we take the most conservative of these in both cases:
3139 // disallow all variadic memory operands.
3140 SmallVector<CCValAssign, 16> ArgLocs;
3141 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3142
3143 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
3144 for (const CCValAssign &ArgLoc : ArgLocs)
3145 if (!ArgLoc.isRegLoc())
3146 return false;
3147 }
3148
3149 // Check that the call results are passed in the same way.
3150 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
3151 CCAssignFnForCall(CalleeCC, isVarArg),
3152 CCAssignFnForCall(CallerCC, isVarArg)))
3153 return false;
3154 // The callee has to preserve all registers the caller needs to preserve.
3155 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3156 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
3157 if (!CCMatch) {
3158 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
3159 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
3160 return false;
3161 }
3162
3163 // Nothing more to check if the callee is taking no arguments
3164 if (Outs.empty())
3165 return true;
3166
3167 SmallVector<CCValAssign, 16> ArgLocs;
3168 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
3169
3170 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
3171
3172 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3173
3174 // If the stack arguments for this call do not fit into our own save area then
3175 // the call cannot be made tail.
3176 if (CCInfo.getNextStackOffset() > FuncInfo->getBytesInStackArgArea())
3177 return false;
3178
3179 const MachineRegisterInfo &MRI = MF.getRegInfo();
3180 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
3181 return false;
3182
3183 return true;
3184}
3185
3186SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
3187 SelectionDAG &DAG,
3188 MachineFrameInfo &MFI,
3189 int ClobberedFI) const {
3190 SmallVector<SDValue, 8> ArgChains;
3191 int64_t FirstByte = MFI.getObjectOffset(ClobberedFI);
3192 int64_t LastByte = FirstByte + MFI.getObjectSize(ClobberedFI) - 1;
3193
3194 // Include the original chain at the beginning of the list. When this is
3195 // used by target LowerCall hooks, this helps legalize find the
3196 // CALLSEQ_BEGIN node.
3197 ArgChains.push_back(Chain);
3198
3199 // Add a chain value for each stack argument corresponding
3200 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
3201 UE = DAG.getEntryNode().getNode()->use_end();
3202 U != UE; ++U)
3203 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
3204 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
3205 if (FI->getIndex() < 0) {
3206 int64_t InFirstByte = MFI.getObjectOffset(FI->getIndex());
3207 int64_t InLastByte = InFirstByte;
3208 InLastByte += MFI.getObjectSize(FI->getIndex()) - 1;
3209
3210 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
3211 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
3212 ArgChains.push_back(SDValue(L, 1));
3213 }
3214
3215 // Build a tokenfactor for all the chains.
3216 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
3217}
3218
3219bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
3220 bool TailCallOpt) const {
3221 return CallCC == CallingConv::Fast && TailCallOpt;
3222}
3223
3224/// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
3225/// and add input and output parameter nodes.
3226SDValue
3227AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
3228 SmallVectorImpl<SDValue> &InVals) const {
3229 SelectionDAG &DAG = CLI.DAG;
3230 SDLoc &DL = CLI.DL;
3231 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3232 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3233 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3234 SDValue Chain = CLI.Chain;
3235 SDValue Callee = CLI.Callee;
3236 bool &IsTailCall = CLI.IsTailCall;
3237 CallingConv::ID CallConv = CLI.CallConv;
3238 bool IsVarArg = CLI.IsVarArg;
3239
3240 MachineFunction &MF = DAG.getMachineFunction();
3241 bool IsThisReturn = false;
3242
3243 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3244 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
3245 bool IsSibCall = false;
3246
3247 if (IsTailCall) {
3248 // Check if it's really possible to do a tail call.
3249 IsTailCall = isEligibleForTailCallOptimization(
3250 Callee, CallConv, IsVarArg, Outs, OutVals, Ins, DAG);
3251 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
3252 report_fatal_error("failed to perform tail call elimination on a call "
3253 "site marked musttail");
3254
3255 // A sibling call is one where we're under the usual C ABI and not planning
3256 // to change that but can still do a tail call:
3257 if (!TailCallOpt && IsTailCall)
3258 IsSibCall = true;
3259
3260 if (IsTailCall)
3261 ++NumTailCalls;
3262 }
3263
3264 // Analyze operands of the call, assigning locations to each operand.
3265 SmallVector<CCValAssign, 16> ArgLocs;
3266 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3267 *DAG.getContext());
3268
3269 if (IsVarArg) {
3270 // Handle fixed and variable vector arguments differently.
3271 // Variable vector arguments always go into memory.
3272 unsigned NumArgs = Outs.size();
3273
3274 for (unsigned i = 0; i != NumArgs; ++i) {
3275 MVT ArgVT = Outs[i].VT;
3276 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3277 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
3278 /*IsVarArg=*/ !Outs[i].IsFixed);
3279 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
3280 assert(!Res && "Call operand has unhandled type")(static_cast <bool> (!Res && "Call operand has unhandled type"
) ? void (0) : __assert_fail ("!Res && \"Call operand has unhandled type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3280, __extension__ __PRETTY_FUNCTION__))
;
3281 (void)Res;
3282 }
3283 } else {
3284 // At this point, Outs[].VT may already be promoted to i32. To correctly
3285 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
3286 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
3287 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
3288 // we use a special version of AnalyzeCallOperands to pass in ValVT and
3289 // LocVT.
3290 unsigned NumArgs = Outs.size();
3291 for (unsigned i = 0; i != NumArgs; ++i) {
3292 MVT ValVT = Outs[i].VT;
3293 // Get type of the original argument.
3294 EVT ActualVT = getValueType(DAG.getDataLayout(),
3295 CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
3296 /*AllowUnknown*/ true);
3297 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
3298 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3299 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
3300 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
3301 ValVT = MVT::i8;
3302 else if (ActualMVT == MVT::i16)
3303 ValVT = MVT::i16;
3304
3305 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
3306 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
3307 assert(!Res && "Call operand has unhandled type")(static_cast <bool> (!Res && "Call operand has unhandled type"
) ? void (0) : __assert_fail ("!Res && \"Call operand has unhandled type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3307, __extension__ __PRETTY_FUNCTION__))
;
3308 (void)Res;
3309 }
3310 }
3311
3312 // Get a count of how many bytes are to be pushed on the stack.
3313 unsigned NumBytes = CCInfo.getNextStackOffset();
3314
3315 if (IsSibCall) {
3316 // Since we're not changing the ABI to make this a tail call, the memory
3317 // operands are already available in the caller's incoming argument space.
3318 NumBytes = 0;
3319 }
3320
3321 // FPDiff is the byte offset of the call's argument area from the callee's.
3322 // Stores to callee stack arguments will be placed in FixedStackSlots offset
3323 // by this amount for a tail call. In a sibling call it must be 0 because the
3324 // caller will deallocate the entire stack and the callee still expects its
3325 // arguments to begin at SP+0. Completely unused for non-tail calls.
3326 int FPDiff = 0;
3327
3328 if (IsTailCall && !IsSibCall) {
3329 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
3330
3331 // Since callee will pop argument stack as a tail call, we must keep the
3332 // popped size 16-byte aligned.
3333 NumBytes = alignTo(NumBytes, 16);
3334
3335 // FPDiff will be negative if this tail call requires more space than we
3336 // would automatically have in our incoming argument space. Positive if we
3337 // can actually shrink the stack.
3338 FPDiff = NumReusableBytes - NumBytes;
3339
3340 // The stack pointer must be 16-byte aligned at all times it's used for a
3341 // memory operation, which in practice means at *all* times and in
3342 // particular across call boundaries. Therefore our own arguments started at
3343 // a 16-byte aligned SP and the delta applied for the tail call should
3344 // satisfy the same constraint.
3345 assert(FPDiff % 16 == 0 && "unaligned stack on tail call")(static_cast <bool> (FPDiff % 16 == 0 && "unaligned stack on tail call"
) ? void (0) : __assert_fail ("FPDiff % 16 == 0 && \"unaligned stack on tail call\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3345, __extension__ __PRETTY_FUNCTION__))
;
3346 }
3347
3348 // Adjust the stack pointer for the new arguments...
3349 // These operations are automatically eliminated by the prolog/epilog pass
3350 if (!IsSibCall)
3351 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, DL);
3352
3353 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP,
3354 getPointerTy(DAG.getDataLayout()));
3355
3356 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3357 SmallVector<SDValue, 8> MemOpChains;
3358 auto PtrVT = getPointerTy(DAG.getDataLayout());
3359
3360 // Walk the register/memloc assignments, inserting copies/loads.
3361 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
3362 ++i, ++realArgIdx) {
3363 CCValAssign &VA = ArgLocs[i];
3364 SDValue Arg = OutVals[realArgIdx];
3365 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
3366
3367 // Promote the value if needed.
3368 switch (VA.getLocInfo()) {
3369 default:
3370 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3370)
;
3371 case CCValAssign::Full:
3372 break;
3373 case CCValAssign::SExt:
3374 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
3375 break;
3376 case CCValAssign::ZExt:
3377 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3378 break;
3379 case CCValAssign::AExt:
3380 if (Outs[realArgIdx].ArgVT == MVT::i1) {
3381 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
3382 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3383 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
3384 }
3385 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
3386 break;
3387 case CCValAssign::BCvt:
3388 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3389 break;
3390 case CCValAssign::FPExt:
3391 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
3392 break;
3393 }
3394
3395 if (VA.isRegLoc()) {
3396 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
3397 Outs[0].VT == MVT::i64) {
3398 assert(VA.getLocVT() == MVT::i64 &&(static_cast <bool> (VA.getLocVT() == MVT::i64 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i64 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3399, __extension__ __PRETTY_FUNCTION__))
3399 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i64 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i64 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3399, __extension__ __PRETTY_FUNCTION__))
;
3400 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i64 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i64 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3401, __extension__ __PRETTY_FUNCTION__))
3401 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i64 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i64 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3401, __extension__ __PRETTY_FUNCTION__))
;
3402 IsThisReturn = true;
3403 }
3404 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3405 } else {
3406 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3406, __extension__ __PRETTY_FUNCTION__))
;
3407
3408 SDValue DstAddr;
3409 MachinePointerInfo DstInfo;
3410
3411 // FIXME: This works on big-endian for composite byvals, which are the
3412 // common case. It should also work for fundamental types too.
3413 uint32_t BEAlign = 0;
3414 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
3415 : VA.getValVT().getSizeInBits();
3416 OpSize = (OpSize + 7) / 8;
3417 if (!Subtarget->isLittleEndian() && !Flags.isByVal() &&
3418 !Flags.isInConsecutiveRegs()) {
3419 if (OpSize < 8)
3420 BEAlign = 8 - OpSize;
3421 }
3422 unsigned LocMemOffset = VA.getLocMemOffset();
3423 int32_t Offset = LocMemOffset + BEAlign;
3424 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3425 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3426
3427 if (IsTailCall) {
3428 Offset = Offset + FPDiff;
3429 int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true);
3430
3431 DstAddr = DAG.getFrameIndex(FI, PtrVT);
3432 DstInfo =
3433 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
3434
3435 // Make sure any stack arguments overlapping with where we're storing
3436 // are loaded before this eventual operation. Otherwise they'll be
3437 // clobbered.
3438 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
3439 } else {
3440 SDValue PtrOff = DAG.getIntPtrConstant(Offset, DL);
3441
3442 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3443 DstInfo = MachinePointerInfo::getStack(DAG.getMachineFunction(),
3444 LocMemOffset);
3445 }
3446
3447 if (Outs[i].Flags.isByVal()) {
3448 SDValue SizeNode =
3449 DAG.getConstant(Outs[i].Flags.getByValSize(), DL, MVT::i64);
3450 SDValue Cpy = DAG.getMemcpy(
3451 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
3452 /*isVol = */ false, /*AlwaysInline = */ false,
3453 /*isTailCall = */ false,
3454 DstInfo, MachinePointerInfo());
3455
3456 MemOpChains.push_back(Cpy);
3457 } else {
3458 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
3459 // promoted to a legal register type i32, we should truncate Arg back to
3460 // i1/i8/i16.
3461 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
3462 VA.getValVT() == MVT::i16)
3463 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
3464
3465 SDValue Store = DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo);
3466 MemOpChains.push_back(Store);
3467 }
3468 }
3469 }
3470
3471 if (!MemOpChains.empty())
3472 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3473
3474 // Build a sequence of copy-to-reg nodes chained together with token chain
3475 // and flag operands which copy the outgoing args into the appropriate regs.
3476 SDValue InFlag;
3477 for (auto &RegToPass : RegsToPass) {
3478 Chain = DAG.getCopyToReg(Chain, DL, RegToPass.first,
3479 RegToPass.second, InFlag);
3480 InFlag = Chain.getValue(1);
3481 }
3482
3483 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3484 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3485 // node so that legalize doesn't hack it.
3486 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3487 auto GV = G->getGlobal();
3488 if (Subtarget->classifyGlobalFunctionReference(GV, getTargetMachine()) ==
3489 AArch64II::MO_GOT) {
3490 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_GOT);
3491 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3492 } else if (Subtarget->isTargetCOFF() && GV->hasDLLImportStorageClass()) {
3493 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3494, __extension__ __PRETTY_FUNCTION__))
3494 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3494, __extension__ __PRETTY_FUNCTION__))
;
3495 Callee = getGOT(G, DAG, AArch64II::MO_DLLIMPORT);
3496 } else {
3497 const GlobalValue *GV = G->getGlobal();
3498 Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, 0);
3499 }
3500 } else if (auto *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3501 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3502 Subtarget->isTargetMachO()) {
3503 const char *Sym = S->getSymbol();
3504 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, AArch64II::MO_GOT);
3505 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee);
3506 } else {
3507 const char *Sym = S->getSymbol();
3508 Callee = DAG.getTargetExternalSymbol(Sym, PtrVT, 0);
3509 }
3510 }
3511
3512 // We don't usually want to end the call-sequence here because we would tidy
3513 // the frame up *after* the call, however in the ABI-changing tail-call case
3514 // we've carefully laid out the parameters so that when sp is reset they'll be
3515 // in the correct location.
3516 if (IsTailCall && !IsSibCall) {
3517 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3518 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3519 InFlag = Chain.getValue(1);
3520 }
3521
3522 std::vector<SDValue> Ops;
3523 Ops.push_back(Chain);
3524 Ops.push_back(Callee);
3525
3526 if (IsTailCall) {
3527 // Each tail call may have to adjust the stack by a different amount, so
3528 // this information must travel along with the operation for eventual
3529 // consumption by emitEpilogue.
3530 Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
3531 }
3532
3533 // Add argument registers to the end of the list so that they are known live
3534 // into the call.
3535 for (auto &RegToPass : RegsToPass)
3536 Ops.push_back(DAG.getRegister(RegToPass.first,
3537 RegToPass.second.getValueType()));
3538
3539 // Add a register mask operand representing the call-preserved registers.
3540 const uint32_t *Mask;
3541 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3542 if (IsThisReturn) {
3543 // For 'this' returns, use the X0-preserving mask if applicable
3544 Mask = TRI->getThisReturnPreservedMask(MF, CallConv);
3545 if (!Mask) {
3546 IsThisReturn = false;
3547 Mask = TRI->getCallPreservedMask(MF, CallConv);
3548 }
3549 } else
3550 Mask = TRI->getCallPreservedMask(MF, CallConv);
3551
3552 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3552, __extension__ __PRETTY_FUNCTION__))
;
3553 Ops.push_back(DAG.getRegisterMask(Mask));
3554
3555 if (InFlag.getNode())
3556 Ops.push_back(InFlag);
3557
3558 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3559
3560 // If we're doing a tall call, use a TC_RETURN here rather than an
3561 // actual call instruction.
3562 if (IsTailCall) {
3563 MF.getFrameInfo().setHasTailCall();
3564 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
3565 }
3566
3567 // Returns a chain and a flag for retval copy to use.
3568 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
3569 InFlag = Chain.getValue(1);
3570
3571 uint64_t CalleePopBytes =
3572 DoesCalleeRestoreStack(CallConv, TailCallOpt) ? alignTo(NumBytes, 16) : 0;
3573
3574 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, DL, true),
3575 DAG.getIntPtrConstant(CalleePopBytes, DL, true),
3576 InFlag, DL);
3577 if (!Ins.empty())
3578 InFlag = Chain.getValue(1);
3579
3580 // Handle result values, copying them out of physregs into vregs that we
3581 // return.
3582 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3583 InVals, IsThisReturn,
3584 IsThisReturn ? OutVals[0] : SDValue());
3585}
3586
3587bool AArch64TargetLowering::CanLowerReturn(
3588 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
3589 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
3590 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3591 ? RetCC_AArch64_WebKit_JS
3592 : RetCC_AArch64_AAPCS;
3593 SmallVector<CCValAssign, 16> RVLocs;
3594 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
3595 return CCInfo.CheckReturn(Outs, RetCC);
3596}
3597
3598SDValue
3599AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3600 bool isVarArg,
3601 const SmallVectorImpl<ISD::OutputArg> &Outs,
3602 const SmallVectorImpl<SDValue> &OutVals,
3603 const SDLoc &DL, SelectionDAG &DAG) const {
3604 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
3605 ? RetCC_AArch64_WebKit_JS
3606 : RetCC_AArch64_AAPCS;
3607 SmallVector<CCValAssign, 16> RVLocs;
3608 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3609 *DAG.getContext());
3610 CCInfo.AnalyzeReturn(Outs, RetCC);
3611
3612 // Copy the result values into the output registers.
3613 SDValue Flag;
3614 SmallVector<SDValue, 4> RetOps(1, Chain);
3615 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
3616 ++i, ++realRVLocIdx) {
3617 CCValAssign &VA = RVLocs[i];
3618 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3618, __extension__ __PRETTY_FUNCTION__))
;
3619 SDValue Arg = OutVals[realRVLocIdx];
3620
3621 switch (VA.getLocInfo()) {
3622 default:
3623 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3623)
;
3624 case CCValAssign::Full:
3625 if (Outs[i].ArgVT == MVT::i1) {
3626 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
3627 // value. This is strictly redundant on Darwin (which uses "zeroext
3628 // i1"), but will be optimised out before ISel.
3629 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
3630 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
3631 }
3632 break;
3633 case CCValAssign::BCvt:
3634 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
3635 break;
3636 }
3637
3638 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
3639 Flag = Chain.getValue(1);
3640 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3641 }
3642 const AArch64RegisterInfo *TRI = Subtarget->getRegisterInfo();
3643 const MCPhysReg *I =
3644 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3645 if (I) {
3646 for (; *I; ++I) {
3647 if (AArch64::GPR64RegClass.contains(*I))
3648 RetOps.push_back(DAG.getRegister(*I, MVT::i64));
3649 else if (AArch64::FPR64RegClass.contains(*I))
3650 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3651 else
3652 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3652)
;
3653 }
3654 }
3655
3656 RetOps[0] = Chain; // Update chain.
3657
3658 // Add the flag if we have it.
3659 if (Flag.getNode())
3660 RetOps.push_back(Flag);
3661
3662 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
3663}
3664
3665//===----------------------------------------------------------------------===//
3666// Other Lowering Code
3667//===----------------------------------------------------------------------===//
3668
3669SDValue AArch64TargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
3670 SelectionDAG &DAG,
3671 unsigned Flag) const {
3672 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
3673}
3674
3675SDValue AArch64TargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
3676 SelectionDAG &DAG,
3677 unsigned Flag) const {
3678 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
3679}
3680
3681SDValue AArch64TargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
3682 SelectionDAG &DAG,
3683 unsigned Flag) const {
3684 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
3685 N->getOffset(), Flag);
3686}
3687
3688SDValue AArch64TargetLowering::getTargetNode(BlockAddressSDNode* N, EVT Ty,
3689 SelectionDAG &DAG,
3690 unsigned Flag) const {
3691 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
3692}
3693
3694// (loadGOT sym)
3695template <class NodeTy>
3696SDValue AArch64TargetLowering::getGOT(NodeTy *N, SelectionDAG &DAG,
3697 unsigned Flags) const {
3698 DEBUG(dbgs() << "AArch64TargetLowering::getGOT\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "AArch64TargetLowering::getGOT\n"
; } } while (false)
;
3699 SDLoc DL(N);
3700 EVT Ty = getPointerTy(DAG.getDataLayout());
3701 SDValue GotAddr = getTargetNode(N, Ty, DAG, AArch64II::MO_GOT | Flags);
3702 // FIXME: Once remat is capable of dealing with instructions with register
3703 // operands, expand this into two nodes instead of using a wrapper node.
3704 return DAG.getNode(AArch64ISD::LOADgot, DL, Ty, GotAddr);
3705}
3706
3707// (wrapper %highest(sym), %higher(sym), %hi(sym), %lo(sym))
3708template <class NodeTy>
3709SDValue AArch64TargetLowering::getAddrLarge(NodeTy *N, SelectionDAG &DAG,
3710 unsigned Flags) const {
3711 DEBUG(dbgs() << "AArch64TargetLowering::getAddrLarge\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "AArch64TargetLowering::getAddrLarge\n"
; } } while (false)
;
3712 SDLoc DL(N);
3713 EVT Ty = getPointerTy(DAG.getDataLayout());
3714 const unsigned char MO_NC = AArch64II::MO_NC;
3715 return DAG.getNode(
3716 AArch64ISD::WrapperLarge, DL, Ty,
3717 getTargetNode(N, Ty, DAG, AArch64II::MO_G3 | Flags),
3718 getTargetNode(N, Ty, DAG, AArch64II::MO_G2 | MO_NC | Flags),
3719 getTargetNode(N, Ty, DAG, AArch64II::MO_G1 | MO_NC | Flags),
3720 getTargetNode(N, Ty, DAG, AArch64II::MO_G0 | MO_NC | Flags));
3721}
3722
3723// (addlow (adrp %hi(sym)) %lo(sym))
3724template <class NodeTy>
3725SDValue AArch64TargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
3726 unsigned Flags) const {
3727 DEBUG(dbgs() << "AArch64TargetLowering::getAddr\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "AArch64TargetLowering::getAddr\n"
; } } while (false)
;
3728 SDLoc DL(N);
3729 EVT Ty = getPointerTy(DAG.getDataLayout());
3730 SDValue Hi = getTargetNode(N, Ty, DAG, AArch64II::MO_PAGE | Flags);
3731 SDValue Lo = getTargetNode(N, Ty, DAG,
3732 AArch64II::MO_PAGEOFF | AArch64II::MO_NC | Flags);
3733 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, Ty, Hi);
3734 return DAG.getNode(AArch64ISD::ADDlow, DL, Ty, ADRP, Lo);
3735}
3736
3737SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3738 SelectionDAG &DAG) const {
3739 GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
3740 const GlobalValue *GV = GN->getGlobal();
3741 const AArch64II::TOF TargetFlags =
3742 (GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT
3743 : AArch64II::MO_NO_FLAG);
3744 unsigned char OpFlags =
3745 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
3746
3747 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&(static_cast <bool> (cast<GlobalAddressSDNode>(Op
)->getOffset() == 0 && "unexpected offset in global node"
) ? void (0) : __assert_fail ("cast<GlobalAddressSDNode>(Op)->getOffset() == 0 && \"unexpected offset in global node\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3748, __extension__ __PRETTY_FUNCTION__))
3748 "unexpected offset in global node")(static_cast <bool> (cast<GlobalAddressSDNode>(Op
)->getOffset() == 0 && "unexpected offset in global node"
) ? void (0) : __assert_fail ("cast<GlobalAddressSDNode>(Op)->getOffset() == 0 && \"unexpected offset in global node\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3748, __extension__ __PRETTY_FUNCTION__))
;
3749
3750 // This also catches the large code model case for Darwin.
3751 if ((OpFlags & AArch64II::MO_GOT) != 0) {
3752 return getGOT(GN, DAG, TargetFlags);
3753 }
3754
3755 SDValue Result;
3756 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3757 Result = getAddrLarge(GN, DAG, TargetFlags);
3758 } else {
3759 Result = getAddr(GN, DAG, TargetFlags);
3760 }
3761 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3762 SDLoc DL(GN);
3763 if (GV->hasDLLImportStorageClass())
3764 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3765 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3766 return Result;
3767}
3768
3769/// \brief Convert a TLS address reference into the correct sequence of loads
3770/// and calls to compute the variable's address (for Darwin, currently) and
3771/// return an SDValue containing the final node.
3772
3773/// Darwin only has one TLS scheme which must be capable of dealing with the
3774/// fully general situation, in the worst case. This means:
3775/// + "extern __thread" declaration.
3776/// + Defined in a possibly unknown dynamic library.
3777///
3778/// The general system is that each __thread variable has a [3 x i64] descriptor
3779/// which contains information used by the runtime to calculate the address. The
3780/// only part of this the compiler needs to know about is the first xword, which
3781/// contains a function pointer that must be called with the address of the
3782/// entire descriptor in "x0".
3783///
3784/// Since this descriptor may be in a different unit, in general even the
3785/// descriptor must be accessed via an indirect load. The "ideal" code sequence
3786/// is:
3787/// adrp x0, _var@TLVPPAGE
3788/// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
3789/// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
3790/// ; the function pointer
3791/// blr x1 ; Uses descriptor address in x0
3792/// ; Address of _var is now in x0.
3793///
3794/// If the address of _var's descriptor *is* known to the linker, then it can
3795/// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3796/// a slight efficiency gain.
3797SDValue
3798AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3799 SelectionDAG &DAG) const {
3800 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3801, __extension__ __PRETTY_FUNCTION__))
3801 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3801, __extension__ __PRETTY_FUNCTION__))
;
3802
3803 SDLoc DL(Op);
3804 MVT PtrVT = getPointerTy(DAG.getDataLayout());
3805 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3806
3807 SDValue TLVPAddr =
3808 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3809 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3810
3811 // The first entry in the descriptor is a function pointer that we must call
3812 // to obtain the address of the variable.
3813 SDValue Chain = DAG.getEntryNode();
3814 SDValue FuncTLVGet = DAG.getLoad(
3815 MVT::i64, DL, Chain, DescAddr,
3816 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
3817 /* Alignment = */ 8,
3818 MachineMemOperand::MONonTemporal | MachineMemOperand::MOInvariant |
3819 MachineMemOperand::MODereferenceable);
3820 Chain = FuncTLVGet.getValue(1);
3821
3822 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
3823 MFI.setAdjustsStack(true);
3824
3825 // TLS calls preserve all registers except those that absolutely must be
3826 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3827 // silly).
3828 const uint32_t *Mask =
3829 Subtarget->getRegisterInfo()->getTLSCallPreservedMask();
3830
3831 // Finally, we can make the call. This is just a degenerate version of a
3832 // normal AArch64 call node: x0 takes the address of the descriptor, and
3833 // returns the address of the variable in this thread.
3834 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3835 Chain =
3836 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3837 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3838 DAG.getRegisterMask(Mask), Chain.getValue(1));
3839 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3840}
3841
3842/// When accessing thread-local variables under either the general-dynamic or
3843/// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3844/// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3845/// is a function pointer to carry out the resolution.
3846///
3847/// The sequence is:
3848/// adrp x0, :tlsdesc:var
3849/// ldr x1, [x0, #:tlsdesc_lo12:var]
3850/// add x0, x0, #:tlsdesc_lo12:var
3851/// .tlsdesccall var
3852/// blr x1
3853/// (TPIDR_EL0 offset now in x0)
3854///
3855/// The above sequence must be produced unscheduled, to enable the linker to
3856/// optimize/relax this sequence.
3857/// Therefore, a pseudo-instruction (TLSDESC_CALLSEQ) is used to represent the
3858/// above sequence, and expanded really late in the compilation flow, to ensure
3859/// the sequence is produced as per above.
3860SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
3861 const SDLoc &DL,
3862 SelectionDAG &DAG) const {
3863 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3864
3865 SDValue Chain = DAG.getEntryNode();
3866 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3867
3868 Chain =
3869 DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, {Chain, SymAddr});
3870 SDValue Glue = Chain.getValue(1);
3871
3872 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3873}
3874
3875SDValue
3876AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3877 SelectionDAG &DAG) const {
3878 assert(Subtarget->isTargetELF() && "This function expects an ELF target")(static_cast <bool> (Subtarget->isTargetELF() &&
"This function expects an ELF target") ? void (0) : __assert_fail
("Subtarget->isTargetELF() && \"This function expects an ELF target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3878, __extension__ __PRETTY_FUNCTION__))
;
3879 assert(Subtarget->useSmallAddressing() &&(static_cast <bool> (Subtarget->useSmallAddressing()
&& "ELF TLS only supported in small memory model") ?
void (0) : __assert_fail ("Subtarget->useSmallAddressing() && \"ELF TLS only supported in small memory model\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3880, __extension__ __PRETTY_FUNCTION__))
3880 "ELF TLS only supported in small memory model")(static_cast <bool> (Subtarget->useSmallAddressing()
&& "ELF TLS only supported in small memory model") ?
void (0) : __assert_fail ("Subtarget->useSmallAddressing() && \"ELF TLS only supported in small memory model\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3880, __extension__ __PRETTY_FUNCTION__))
;
3881 // Different choices can be made for the maximum size of the TLS area for a
3882 // module. For the small address model, the default TLS size is 16MiB and the
3883 // maximum TLS size is 4GiB.
3884 // FIXME: add -mtls-size command line option and make it control the 16MiB
3885 // vs. 4GiB code sequence generation.
3886 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3887
3888 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3889
3890 if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
3891 if (Model == TLSModel::LocalDynamic)
3892 Model = TLSModel::GeneralDynamic;
3893 }
3894
3895 SDValue TPOff;
3896 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3897 SDLoc DL(Op);
3898 const GlobalValue *GV = GA->getGlobal();
3899
3900 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3901
3902 if (Model == TLSModel::LocalExec) {
3903 SDValue HiVar = DAG.getTargetGlobalAddress(
3904 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3905 SDValue LoVar = DAG.getTargetGlobalAddress(
3906 GV, DL, PtrVT, 0,
3907 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3908
3909 SDValue TPWithOff_lo =
3910 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, ThreadBase,
3911 HiVar,
3912 DAG.getTargetConstant(0, DL, MVT::i32)),
3913 0);
3914 SDValue TPWithOff =
3915 SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPWithOff_lo,
3916 LoVar,
3917 DAG.getTargetConstant(0, DL, MVT::i32)),
3918 0);
3919 return TPWithOff;
3920 } else if (Model == TLSModel::InitialExec) {
3921 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3922 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3923 } else if (Model == TLSModel::LocalDynamic) {
3924 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3925 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3926 // the beginning of the module's TLS region, followed by a DTPREL offset
3927 // calculation.
3928
3929 // These accesses will need deduplicating if there's more than one.
3930 AArch64FunctionInfo *MFI =
3931 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3932 MFI->incNumLocalDynamicTLSAccesses();
3933
3934 // The call needs a relocation too for linker relaxation. It doesn't make
3935 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3936 // the address.
3937 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3938 AArch64II::MO_TLS);
3939
3940 // Now we can calculate the offset from TPIDR_EL0 to this module's
3941 // thread-local area.
3942 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3943
3944 // Now use :dtprel_whatever: operations to calculate this variable's offset
3945 // in its thread-storage area.
3946 SDValue HiVar = DAG.getTargetGlobalAddress(
3947 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_HI12);
3948 SDValue LoVar = DAG.getTargetGlobalAddress(
3949 GV, DL, MVT::i64, 0,
3950 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3951
3952 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, HiVar,
3953 DAG.getTargetConstant(0, DL, MVT::i32)),
3954 0);
3955 TPOff = SDValue(DAG.getMachineNode(AArch64::ADDXri, DL, PtrVT, TPOff, LoVar,
3956 DAG.getTargetConstant(0, DL, MVT::i32)),
3957 0);
3958 } else if (Model == TLSModel::GeneralDynamic) {
3959 // The call needs a relocation too for linker relaxation. It doesn't make
3960 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3961 // the address.
3962 SDValue SymAddr =
3963 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3964
3965 // Finally we can make a call to calculate the offset from tpidr_el0.
3966 TPOff = LowerELFTLSDescCallSeq(SymAddr, DL, DAG);
3967 } else
3968 llvm_unreachable("Unsupported ELF TLS access model")::llvm::llvm_unreachable_internal("Unsupported ELF TLS access model"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3968)
;
3969
3970 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3971}
3972
3973SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3974 SelectionDAG &DAG) const {
3975 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3976 if (DAG.getTarget().Options.EmulatedTLS)
3977 return LowerToTLSEmulatedModel(GA, DAG);
3978
3979 if (Subtarget->isTargetDarwin())
3980 return LowerDarwinGlobalTLSAddress(Op, DAG);
3981 if (Subtarget->isTargetELF())
3982 return LowerELFGlobalTLSAddress(Op, DAG);
3983
3984 llvm_unreachable("Unexpected platform trying to use TLS")::llvm::llvm_unreachable_internal("Unexpected platform trying to use TLS"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 3984)
;
3985}
3986
3987SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3988 SDValue Chain = Op.getOperand(0);
3989 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3990 SDValue LHS = Op.getOperand(2);
3991 SDValue RHS = Op.getOperand(3);
3992 SDValue Dest = Op.getOperand(4);
3993 SDLoc dl(Op);
3994
3995 // Handle f128 first, since lowering it will result in comparing the return
3996 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3997 // is expecting to deal with.
3998 if (LHS.getValueType() == MVT::f128) {
3999 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
4000
4001 // If softenSetCCOperands returned a scalar, we need to compare the result
4002 // against zero to select between true and false values.
4003 if (!RHS.getNode()) {
4004 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4005 CC = ISD::SETNE;
4006 }
4007 }
4008
4009 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4010 // instruction.
4011 if (isOverflowIntrOpRes(LHS) && isOneConstant(RHS) &&
4012 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4013 // Only lower legal XALUO ops.
4014 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4015 return SDValue();
4016
4017 // The actual operation with overflow check.
4018 AArch64CC::CondCode OFCC;
4019 SDValue Value, Overflow;
4020 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
4021
4022 if (CC == ISD::SETNE)
4023 OFCC = getInvertedCondCode(OFCC);
4024 SDValue CCVal = DAG.getConstant(OFCC, dl, MVT::i32);
4025
4026 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
4027 Overflow);
4028 }
4029
4030 if (LHS.getValueType().isInteger()) {
4031 assert((LHS.getValueType() == RHS.getValueType()) &&(static_cast <bool> ((LHS.getValueType() == RHS.getValueType
()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType
() == MVT::i64)) ? void (0) : __assert_fail ("(LHS.getValueType() == RHS.getValueType()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4032, __extension__ __PRETTY_FUNCTION__))
4032 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64))(static_cast <bool> ((LHS.getValueType() == RHS.getValueType
()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType
() == MVT::i64)) ? void (0) : __assert_fail ("(LHS.getValueType() == RHS.getValueType()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4032, __extension__ __PRETTY_FUNCTION__))
;
4033
4034 // If the RHS of the comparison is zero, we can potentially fold this
4035 // to a specialized branch.
4036 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
4037 if (RHSC && RHSC->getZExtValue() == 0) {
4038 if (CC == ISD::SETEQ) {
4039 // See if we can use a TBZ to fold in an AND as well.
4040 // TBZ has a smaller branch displacement than CBZ. If the offset is
4041 // out of bounds, a late MI-layer pass rewrites branches.
4042 // 403.gcc is an example that hits this case.
4043 if (LHS.getOpcode() == ISD::AND &&
4044 isa<ConstantSDNode>(LHS.getOperand(1)) &&
4045 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
4046 SDValue Test = LHS.getOperand(0);
4047 uint64_t Mask = LHS.getConstantOperandVal(1);
4048 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
4049 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
4050 Dest);
4051 }
4052
4053 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
4054 } else if (CC == ISD::SETNE) {
4055 // See if we can use a TBZ to fold in an AND as well.
4056 // TBZ has a smaller branch displacement than CBZ. If the offset is
4057 // out of bounds, a late MI-layer pass rewrites branches.
4058 // 403.gcc is an example that hits this case.
4059 if (LHS.getOpcode() == ISD::AND &&
4060 isa<ConstantSDNode>(LHS.getOperand(1)) &&
4061 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
4062 SDValue Test = LHS.getOperand(0);
4063 uint64_t Mask = LHS.getConstantOperandVal(1);
4064 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
4065 DAG.getConstant(Log2_64(Mask), dl, MVT::i64),
4066 Dest);
4067 }
4068
4069 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
4070 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
4071 // Don't combine AND since emitComparison converts the AND to an ANDS
4072 // (a.k.a. TST) and the test in the test bit and branch instruction
4073 // becomes redundant. This would also increase register pressure.
4074 uint64_t Mask = LHS.getValueSizeInBits() - 1;
4075 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
4076 DAG.getConstant(Mask, dl, MVT::i64), Dest);
4077 }
4078 }
4079 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
4080 LHS.getOpcode() != ISD::AND) {
4081 // Don't combine AND since emitComparison converts the AND to an ANDS
4082 // (a.k.a. TST) and the test in the test bit and branch instruction
4083 // becomes redundant. This would also increase register pressure.
4084 uint64_t Mask = LHS.getValueSizeInBits() - 1;
4085 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
4086 DAG.getConstant(Mask, dl, MVT::i64), Dest);
4087 }
4088
4089 SDValue CCVal;
4090 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
4091 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
4092 Cmp);
4093 }
4094
4095 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||(static_cast <bool> (LHS.getValueType() == MVT::f16 || LHS
.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64
) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4096, __extension__ __PRETTY_FUNCTION__))
4096 LHS.getValueType() == MVT::f64)(static_cast <bool> (LHS.getValueType() == MVT::f16 || LHS
.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64
) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4096, __extension__ __PRETTY_FUNCTION__))
;
4097
4098 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
4099 // clean. Some of them require two branches to implement.
4100 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
4101 AArch64CC::CondCode CC1, CC2;
4102 changeFPCCToAArch64CC(CC, CC1, CC2);
4103 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
4104 SDValue BR1 =
4105 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
4106 if (CC2 != AArch64CC::AL) {
4107 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
4108 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
4109 Cmp);
4110 }
4111
4112 return BR1;
4113}
4114
4115SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
4116 SelectionDAG &DAG) const {
4117 EVT VT = Op.getValueType();
4118 SDLoc DL(Op);
4119
4120 SDValue In1 = Op.getOperand(0);
4121 SDValue In2 = Op.getOperand(1);
4122 EVT SrcVT = In2.getValueType();
4123
4124 if (SrcVT.bitsLT(VT))
4125 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
4126 else if (SrcVT.bitsGT(VT))
4127 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL));
4128
4129 EVT VecVT;
4130 uint64_t EltMask;
4131 SDValue VecVal1, VecVal2;
4132
4133 auto setVecVal = [&] (int Idx) {
4134 if (!VT.isVector()) {
4135 VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT,
4136 DAG.getUNDEF(VecVT), In1);
4137 VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT,
4138 DAG.getUNDEF(VecVT), In2);
4139 } else {
4140 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
4141 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
4142 }
4143 };
4144
4145 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
4146 VecVT = (VT == MVT::v2f32 ? MVT::v2i32 : MVT::v4i32);
4147 EltMask = 0x80000000ULL;
4148 setVecVal(AArch64::ssub);
4149 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
4150 VecVT = MVT::v2i64;
4151
4152 // We want to materialize a mask with the high bit set, but the AdvSIMD
4153 // immediate moves cannot materialize that in a single instruction for
4154 // 64-bit elements. Instead, materialize zero and then negate it.
4155 EltMask = 0;
4156
4157 setVecVal(AArch64::dsub);
4158 } else if (VT == MVT::f16 || VT == MVT::v4f16 || VT == MVT::v8f16) {
4159 VecVT = (VT == MVT::v4f16 ? MVT::v4i16 : MVT::v8i16);
4160 EltMask = 0x8000ULL;
4161 setVecVal(AArch64::hsub);
4162 } else {
4163 llvm_unreachable("Invalid type for copysign!")::llvm::llvm_unreachable_internal("Invalid type for copysign!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4163)
;
4164 }
4165
4166 SDValue BuildVec = DAG.getConstant(EltMask, DL, VecVT);
4167
4168 // If we couldn't materialize the mask above, then the mask vector will be
4169 // the zero vector, and we need to negate it here.
4170 if (VT == MVT::f64 || VT == MVT::v2f64) {
4171 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
4172 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
4173 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
4174 }
4175
4176 SDValue Sel =
4177 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
4178
4179 if (VT == MVT::f16)
4180 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, Sel);
4181 if (VT == MVT::f32)
4182 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
4183 else if (VT == MVT::f64)
4184 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
4185 else
4186 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
4187}
4188
4189SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
4190 if (DAG.getMachineFunction().getFunction().hasFnAttribute(
4191 Attribute::NoImplicitFloat))
4192 return SDValue();
4193
4194 if (!Subtarget->hasNEON())
4195 return SDValue();
4196
4197 // While there is no integer popcount instruction, it can
4198 // be more efficiently lowered to the following sequence that uses
4199 // AdvSIMD registers/instructions as long as the copies to/from
4200 // the AdvSIMD registers are cheap.
4201 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
4202 // CNT V0.8B, V0.8B // 8xbyte pop-counts
4203 // ADDV B0, V0.8B // sum 8xbyte pop-counts
4204 // UMOV X0, V0.B[0] // copy byte result back to integer reg
4205 SDValue Val = Op.getOperand(0);
4206 SDLoc DL(Op);
4207 EVT VT = Op.getValueType();
4208
4209 if (VT == MVT::i32)
4210 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val);
4211 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
4212
4213 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val);
4214 SDValue UaddLV = DAG.getNode(
4215 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
4216 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
4217
4218 if (VT == MVT::i64)
4219 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
4220 return UaddLV;
4221}
4222
4223SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
4224
4225 if (Op.getValueType().isVector())
4226 return LowerVSETCC(Op, DAG);
4227
4228 SDValue LHS = Op.getOperand(0);
4229 SDValue RHS = Op.getOperand(1);
4230 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
4231 SDLoc dl(Op);
4232
4233 // We chose ZeroOrOneBooleanContents, so use zero and one.
4234 EVT VT = Op.getValueType();
4235 SDValue TVal = DAG.getConstant(1, dl, VT);
4236 SDValue FVal = DAG.getConstant(0, dl, VT);
4237
4238 // Handle f128 first, since one possible outcome is a normal integer
4239 // comparison which gets picked up by the next if statement.
4240 if (LHS.getValueType() == MVT::f128) {
4241 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
4242
4243 // If softenSetCCOperands returned a scalar, use it.
4244 if (!RHS.getNode()) {
4245 assert(LHS.getValueType() == Op.getValueType() &&(static_cast <bool> (LHS.getValueType() == Op.getValueType
() && "Unexpected setcc expansion!") ? void (0) : __assert_fail
("LHS.getValueType() == Op.getValueType() && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4246, __extension__ __PRETTY_FUNCTION__))
4246 "Unexpected setcc expansion!")(static_cast <bool> (LHS.getValueType() == Op.getValueType
() && "Unexpected setcc expansion!") ? void (0) : __assert_fail
("LHS.getValueType() == Op.getValueType() && \"Unexpected setcc expansion!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4246, __extension__ __PRETTY_FUNCTION__))
;
4247 return LHS;
4248 }
4249 }
4250
4251 if (LHS.getValueType().isInteger()) {
4252 SDValue CCVal;
4253 SDValue Cmp =
4254 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
4255
4256 // Note that we inverted the condition above, so we reverse the order of
4257 // the true and false operands here. This will allow the setcc to be
4258 // matched to a single CSINC instruction.
4259 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
4260 }
4261
4262 // Now we know we're dealing with FP values.
4263 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||(static_cast <bool> (LHS.getValueType() == MVT::f16 || LHS
.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64
) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4264, __extension__ __PRETTY_FUNCTION__))
4264 LHS.getValueType() == MVT::f64)(static_cast <bool> (LHS.getValueType() == MVT::f16 || LHS
.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64
) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4264, __extension__ __PRETTY_FUNCTION__))
;
4265
4266 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
4267 // and do the comparison.
4268 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
4269
4270 AArch64CC::CondCode CC1, CC2;
4271 changeFPCCToAArch64CC(CC, CC1, CC2);
4272 if (CC2 == AArch64CC::AL) {
4273 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
4274 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
4275
4276 // Note that we inverted the condition above, so we reverse the order of
4277 // the true and false operands here. This will allow the setcc to be
4278 // matched to a single CSINC instruction.
4279 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
4280 } else {
4281 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
4282 // totally clean. Some of them require two CSELs to implement. As is in
4283 // this case, we emit the first CSEL and then emit a second using the output
4284 // of the first as the RHS. We're effectively OR'ing the two CC's together.
4285
4286 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
4287 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
4288 SDValue CS1 =
4289 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4290
4291 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
4292 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4293 }
4294}
4295
4296SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
4297 SDValue RHS, SDValue TVal,
4298 SDValue FVal, const SDLoc &dl,
4299 SelectionDAG &DAG) const {
4300 // Handle f128 first, because it will result in a comparison of some RTLIB
4301 // call result against zero.
4302 if (LHS.getValueType() == MVT::f128) {
4303 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
4304
4305 // If softenSetCCOperands returned a scalar, we need to compare the result
4306 // against zero to select between true and false values.
4307 if (!RHS.getNode()) {
4308 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4309 CC = ISD::SETNE;
4310 }
4311 }
4312
4313 // Also handle f16, for which we need to do a f32 comparison.
4314 if (LHS.getValueType() == MVT::f16 && !Subtarget->hasFullFP16()) {
4315 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS);
4316 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS);
4317 }
4318
4319 // Next, handle integers.
4320 if (LHS.getValueType().isInteger()) {
4321 assert((LHS.getValueType() == RHS.getValueType()) &&(static_cast <bool> ((LHS.getValueType() == RHS.getValueType
()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType
() == MVT::i64)) ? void (0) : __assert_fail ("(LHS.getValueType() == RHS.getValueType()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4322, __extension__ __PRETTY_FUNCTION__))
4322 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64))(static_cast <bool> ((LHS.getValueType() == RHS.getValueType
()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType
() == MVT::i64)) ? void (0) : __assert_fail ("(LHS.getValueType() == RHS.getValueType()) && (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64)"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4322, __extension__ __PRETTY_FUNCTION__))
;
4323
4324 unsigned Opcode = AArch64ISD::CSEL;
4325
4326 // If both the TVal and the FVal are constants, see if we can swap them in
4327 // order to for a CSINV or CSINC out of them.
4328 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
4329 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
4330
4331 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
4332 std::swap(TVal, FVal);
4333 std::swap(CTVal, CFVal);
4334 CC = ISD::getSetCCInverse(CC, true);
4335 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
4336 std::swap(TVal, FVal);
4337 std::swap(CTVal, CFVal);
4338 CC = ISD::getSetCCInverse(CC, true);
4339 } else if (TVal.getOpcode() == ISD::XOR) {
4340 // If TVal is a NOT we want to swap TVal and FVal so that we can match
4341 // with a CSINV rather than a CSEL.
4342 if (isAllOnesConstant(TVal.getOperand(1))) {
4343 std::swap(TVal, FVal);
4344 std::swap(CTVal, CFVal);
4345 CC = ISD::getSetCCInverse(CC, true);
4346 }
4347 } else if (TVal.getOpcode() == ISD::SUB) {
4348 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
4349 // that we can match with a CSNEG rather than a CSEL.
4350 if (isNullConstant(TVal.getOperand(0))) {
4351 std::swap(TVal, FVal);
4352 std::swap(CTVal, CFVal);
4353 CC = ISD::getSetCCInverse(CC, true);
4354 }
4355 } else if (CTVal && CFVal) {
4356 const int64_t TrueVal = CTVal->getSExtValue();
4357 const int64_t FalseVal = CFVal->getSExtValue();
4358 bool Swap = false;
4359
4360 // If both TVal and FVal are constants, see if FVal is the
4361 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
4362 // instead of a CSEL in that case.
4363 if (TrueVal == ~FalseVal) {
4364 Opcode = AArch64ISD::CSINV;
4365 } else if (TrueVal == -FalseVal) {
4366 Opcode = AArch64ISD::CSNEG;
4367 } else if (TVal.getValueType() == MVT::i32) {
4368 // If our operands are only 32-bit wide, make sure we use 32-bit
4369 // arithmetic for the check whether we can use CSINC. This ensures that
4370 // the addition in the check will wrap around properly in case there is
4371 // an overflow (which would not be the case if we do the check with
4372 // 64-bit arithmetic).
4373 const uint32_t TrueVal32 = CTVal->getZExtValue();
4374 const uint32_t FalseVal32 = CFVal->getZExtValue();
4375
4376 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
4377 Opcode = AArch64ISD::CSINC;
4378
4379 if (TrueVal32 > FalseVal32) {
4380 Swap = true;
4381 }
4382 }
4383 // 64-bit check whether we can use CSINC.
4384 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
4385 Opcode = AArch64ISD::CSINC;
4386
4387 if (TrueVal > FalseVal) {
4388 Swap = true;
4389 }
4390 }
4391
4392 // Swap TVal and FVal if necessary.
4393 if (Swap) {
4394 std::swap(TVal, FVal);
4395 std::swap(CTVal, CFVal);
4396 CC = ISD::getSetCCInverse(CC, true);
4397 }
4398
4399 if (Opcode != AArch64ISD::CSEL) {
4400 // Drop FVal since we can get its value by simply inverting/negating
4401 // TVal.
4402 FVal = TVal;
4403 }
4404 }
4405
4406 // Avoid materializing a constant when possible by reusing a known value in
4407 // a register. However, don't perform this optimization if the known value
4408 // is one, zero or negative one in the case of a CSEL. We can always
4409 // materialize these values using CSINC, CSEL and CSINV with wzr/xzr as the
4410 // FVal, respectively.
4411 ConstantSDNode *RHSVal = dyn_cast<ConstantSDNode>(RHS);
4412 if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
4413 !RHSVal->isNullValue() && !RHSVal->isAllOnesValue()) {
4414 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
4415 // Transform "a == C ? C : x" to "a == C ? a : x" and "a != C ? x : C" to
4416 // "a != C ? x : a" to avoid materializing C.
4417 if (CTVal && CTVal == RHSVal && AArch64CC == AArch64CC::EQ)
4418 TVal = LHS;
4419 else if (CFVal && CFVal == RHSVal && AArch64CC == AArch64CC::NE)
4420 FVal = LHS;
4421 } else if (Opcode == AArch64ISD::CSNEG && RHSVal && RHSVal->isOne()) {
4422 assert (CTVal && CFVal && "Expected constant operands for CSNEG.")(static_cast <bool> (CTVal && CFVal && "Expected constant operands for CSNEG."
) ? void (0) : __assert_fail ("CTVal && CFVal && \"Expected constant operands for CSNEG.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4422, __extension__ __PRETTY_FUNCTION__))
;
4423 // Use a CSINV to transform "a == C ? 1 : -1" to "a == C ? a : -1" to
4424 // avoid materializing C.
4425 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
4426 if (CTVal == RHSVal && AArch64CC == AArch64CC::EQ) {
4427 Opcode = AArch64ISD::CSINV;
4428 TVal = LHS;
4429 FVal = DAG.getConstant(0, dl, FVal.getValueType());
4430 }
4431 }
4432
4433 SDValue CCVal;
4434 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
4435 EVT VT = TVal.getValueType();
4436 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
4437 }
4438
4439 // Now we know we're dealing with FP values.
4440 assert(LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 ||(static_cast <bool> (LHS.getValueType() == MVT::f16 || LHS
.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64
) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4441, __extension__ __PRETTY_FUNCTION__))
4441 LHS.getValueType() == MVT::f64)(static_cast <bool> (LHS.getValueType() == MVT::f16 || LHS
.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64
) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f16 || LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4441, __extension__ __PRETTY_FUNCTION__))
;
4442 assert(LHS.getValueType() == RHS.getValueType())(static_cast <bool> (LHS.getValueType() == RHS.getValueType
()) ? void (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType()"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4442, __extension__ __PRETTY_FUNCTION__))
;
4443 EVT VT = TVal.getValueType();
4444 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
4445
4446 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
4447 // clean. Some of them require two CSELs to implement.
4448 AArch64CC::CondCode CC1, CC2;
4449 changeFPCCToAArch64CC(CC, CC1, CC2);
4450
4451 if (DAG.getTarget().Options.UnsafeFPMath) {
4452 // Transform "a == 0.0 ? 0.0 : x" to "a == 0.0 ? a : x" and
4453 // "a != 0.0 ? x : 0.0" to "a != 0.0 ? x : a" to avoid materializing 0.0.
4454 ConstantFPSDNode *RHSVal = dyn_cast<ConstantFPSDNode>(RHS);
4455 if (RHSVal && RHSVal->isZero()) {
4456 ConstantFPSDNode *CFVal = dyn_cast<ConstantFPSDNode>(FVal);
4457 ConstantFPSDNode *CTVal = dyn_cast<ConstantFPSDNode>(TVal);
4458
4459 if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETUEQ) &&
4460 CTVal && CTVal->isZero() && TVal.getValueType() == LHS.getValueType())
4461 TVal = LHS;
4462 else if ((CC == ISD::SETNE || CC == ISD::SETONE || CC == ISD::SETUNE) &&
4463 CFVal && CFVal->isZero() &&
4464 FVal.getValueType() == LHS.getValueType())
4465 FVal = LHS;
4466 }
4467 }
4468
4469 // Emit first, and possibly only, CSEL.
4470 SDValue CC1Val = DAG.getConstant(CC1, dl, MVT::i32);
4471 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4472
4473 // If we need a second CSEL, emit it, using the output of the first as the
4474 // RHS. We're effectively OR'ing the two CC's together.
4475 if (CC2 != AArch64CC::AL) {
4476 SDValue CC2Val = DAG.getConstant(CC2, dl, MVT::i32);
4477 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4478 }
4479
4480 // Otherwise, return the output of the first CSEL.
4481 return CS1;
4482}
4483
4484SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
4485 SelectionDAG &DAG) const {
4486 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4487 SDValue LHS = Op.getOperand(0);
4488 SDValue RHS = Op.getOperand(1);
4489 SDValue TVal = Op.getOperand(2);
4490 SDValue FVal = Op.getOperand(3);
4491 SDLoc DL(Op);
4492 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4493}
4494
4495SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
4496 SelectionDAG &DAG) const {
4497 SDValue CCVal = Op->getOperand(0);
4498 SDValue TVal = Op->getOperand(1);
4499 SDValue FVal = Op->getOperand(2);
4500 SDLoc DL(Op);
4501
4502 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4503 // instruction.
4504 if (isOverflowIntrOpRes(CCVal)) {
4505 // Only lower legal XALUO ops.
4506 if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
4507 return SDValue();
4508
4509 AArch64CC::CondCode OFCC;
4510 SDValue Value, Overflow;
4511 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
4512 SDValue CCVal = DAG.getConstant(OFCC, DL, MVT::i32);
4513
4514 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4515 CCVal, Overflow);
4516 }
4517
4518 // Lower it the same way as we would lower a SELECT_CC node.
4519 ISD::CondCode CC;
4520 SDValue LHS, RHS;
4521 if (CCVal.getOpcode() == ISD::SETCC) {
4522 LHS = CCVal.getOperand(0);
4523 RHS = CCVal.getOperand(1);
4524 CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
4525 } else {
4526 LHS = CCVal;
4527 RHS = DAG.getConstant(0, DL, CCVal.getValueType());
4528 CC = ISD::SETNE;
4529 }
4530 return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
4531}
4532
4533SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4534 SelectionDAG &DAG) const {
4535 // Jump table entries as PC relative offsets. No additional tweaking
4536 // is necessary here. Just get the address of the jump table.
4537 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4538
4539 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4540 !Subtarget->isTargetMachO()) {
4541 return getAddrLarge(JT, DAG);
4542 }
4543 return getAddr(JT, DAG);
4544}
4545
4546SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4547 SelectionDAG &DAG) const {
4548 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4549
4550 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
4551 // Use the GOT for the large code model on iOS.
4552 if (Subtarget->isTargetMachO()) {
4553 return getGOT(CP, DAG);
4554 }
4555 return getAddrLarge(CP, DAG);
4556 } else {
4557 return getAddr(CP, DAG);
4558 }
4559}
4560
4561SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4562 SelectionDAG &DAG) const {
4563 BlockAddressSDNode *BA = cast<BlockAddressSDNode>(Op);
4564 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
4565 !Subtarget->isTargetMachO()) {
4566 return getAddrLarge(BA, DAG);
4567 } else {
4568 return getAddr(BA, DAG);
4569 }
4570}
4571
4572SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4573 SelectionDAG &DAG) const {
4574 AArch64FunctionInfo *FuncInfo =
4575 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4576
4577 SDLoc DL(Op);
4578 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(),
4579 getPointerTy(DAG.getDataLayout()));
4580 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4581 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4582 MachinePointerInfo(SV));
4583}
4584
4585SDValue AArch64TargetLowering::LowerWin64_VASTART(SDValue Op,
4586 SelectionDAG &DAG) const {
4587 AArch64FunctionInfo *FuncInfo =
4588 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
4589
4590 SDLoc DL(Op);
4591 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsGPRSize() > 0
4592 ? FuncInfo->getVarArgsGPRIndex()
4593 : FuncInfo->getVarArgsStackIndex(),
4594 getPointerTy(DAG.getDataLayout()));
4595 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4596 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
4597 MachinePointerInfo(SV));
4598}
4599
4600SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4601 SelectionDAG &DAG) const {
4602 // The layout of the va_list struct is specified in the AArch64 Procedure Call
4603 // Standard, section B.3.
4604 MachineFunction &MF = DAG.getMachineFunction();
4605 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
4606 auto PtrVT = getPointerTy(DAG.getDataLayout());
4607 SDLoc DL(Op);
4608
4609 SDValue Chain = Op.getOperand(0);
4610 SDValue VAList = Op.getOperand(1);
4611 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4612 SmallVector<SDValue, 4> MemOps;
4613
4614 // void *__stack at offset 0
4615 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), PtrVT);
4616 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
4617 MachinePointerInfo(SV), /* Alignment = */ 8));
4618
4619 // void *__gr_top at offset 8
4620 int GPRSize = FuncInfo->getVarArgsGPRSize();
4621 if (GPRSize > 0) {
4622 SDValue GRTop, GRTopAddr;
4623
4624 GRTopAddr =
4625 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4626
4627 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
4628 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4629 DAG.getConstant(GPRSize, DL, PtrVT));
4630
4631 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
4632 MachinePointerInfo(SV, 8),
4633 /* Alignment = */ 8));
4634 }
4635
4636 // void *__vr_top at offset 16
4637 int FPRSize = FuncInfo->getVarArgsFPRSize();
4638 if (FPRSize > 0) {
4639 SDValue VRTop, VRTopAddr;
4640 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4641 DAG.getConstant(16, DL, PtrVT));
4642
4643 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
4644 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4645 DAG.getConstant(FPRSize, DL, PtrVT));
4646
4647 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
4648 MachinePointerInfo(SV, 16),
4649 /* Alignment = */ 8));
4650 }
4651
4652 // int __gr_offs at offset 24
4653 SDValue GROffsAddr =
4654 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4655 MemOps.push_back(DAG.getStore(
4656 Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32), GROffsAddr,
4657 MachinePointerInfo(SV, 24), /* Alignment = */ 4));
4658
4659 // int __vr_offs at offset 28
4660 SDValue VROffsAddr =
4661 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4662 MemOps.push_back(DAG.getStore(
4663 Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32), VROffsAddr,
4664 MachinePointerInfo(SV, 28), /* Alignment = */ 4));
4665
4666 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
4667}
4668
4669SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4670 SelectionDAG &DAG) const {
4671 MachineFunction &MF = DAG.getMachineFunction();
4672
4673 if (Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv()))
4674 return LowerWin64_VASTART(Op, DAG);
4675 else if (Subtarget->isTargetDarwin())
4676 return LowerDarwin_VASTART(Op, DAG);
4677 else
4678 return LowerAAPCS_VASTART(Op, DAG);
4679}
4680
4681SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4682 SelectionDAG &DAG) const {
4683 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
4684 // pointer.
4685 SDLoc DL(Op);
4686 unsigned VaListSize =
4687 Subtarget->isTargetDarwin() || Subtarget->isTargetWindows() ? 8 : 32;
4688 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
4689 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
4690
4691 return DAG.getMemcpy(Op.getOperand(0), DL, Op.getOperand(1),
4692 Op.getOperand(2),
4693 DAG.getConstant(VaListSize, DL, MVT::i32),
4694 8, false, false, false, MachinePointerInfo(DestSV),
4695 MachinePointerInfo(SrcSV));
4696}
4697
4698SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4699 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"automatic va_arg instruction only works on Darwin") ? void (
0) : __assert_fail ("Subtarget->isTargetDarwin() && \"automatic va_arg instruction only works on Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4700, __extension__ __PRETTY_FUNCTION__))
4700 "automatic va_arg instruction only works on Darwin")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"automatic va_arg instruction only works on Darwin") ? void (
0) : __assert_fail ("Subtarget->isTargetDarwin() && \"automatic va_arg instruction only works on Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4700, __extension__ __PRETTY_FUNCTION__))
;
4701
4702 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4703 EVT VT = Op.getValueType();
4704 SDLoc DL(Op);
4705 SDValue Chain = Op.getOperand(0);
4706 SDValue Addr = Op.getOperand(1);
4707 unsigned Align = Op.getConstantOperandVal(3);
4708 auto PtrVT = getPointerTy(DAG.getDataLayout());
4709
4710 SDValue VAList = DAG.getLoad(PtrVT, DL, Chain, Addr, MachinePointerInfo(V));
4711 Chain = VAList.getValue(1);
4712
4713 if (Align > 8) {
4714 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2")(static_cast <bool> (((Align & (Align - 1)) == 0) &&
"Expected Align to be a power of 2") ? void (0) : __assert_fail
("((Align & (Align - 1)) == 0) && \"Expected Align to be a power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4714, __extension__ __PRETTY_FUNCTION__))
;
4715 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4716 DAG.getConstant(Align - 1, DL, PtrVT));
4717 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
4718 DAG.getConstant(-(int64_t)Align, DL, PtrVT));
4719 }
4720
4721 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4722 uint64_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
4723
4724 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4725 // up to 64 bits. At the very least, we have to increase the striding of the
4726 // vaargs list to match this, and for FP values we need to introduce
4727 // FP_ROUND nodes as well.
4728 if (VT.isInteger() && !VT.isVector())
4729 ArgSize = 8;
4730 bool NeedFPTrunc = false;
4731 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4732 ArgSize = 8;
4733 NeedFPTrunc = true;
4734 }
4735
4736 // Increment the pointer, VAList, to the next vaarg
4737 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4738 DAG.getConstant(ArgSize, DL, PtrVT));
4739 // Store the incremented VAList to the legalized pointer
4740 SDValue APStore =
4741 DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V));
4742
4743 // Load the actual argument out of the pointer VAList
4744 if (NeedFPTrunc) {
4745 // Load the value as an f64.
4746 SDValue WideFP =
4747 DAG.getLoad(MVT::f64, DL, APStore, VAList, MachinePointerInfo());
4748 // Round the value down to an f32.
4749 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4750 DAG.getIntPtrConstant(1, DL));
4751 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4752 // Merge the rounded value with the chain output of the load.
4753 return DAG.getMergeValues(Ops, DL);
4754 }
4755
4756 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo());
4757}
4758
4759SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4760 SelectionDAG &DAG) const {
4761 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
4762 MFI.setFrameAddressIsTaken(true);
4763
4764 EVT VT = Op.getValueType();
4765 SDLoc DL(Op);
4766 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4767 SDValue FrameAddr =
4768 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4769 while (Depth--)
4770 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4771 MachinePointerInfo());
4772 return FrameAddr;
4773}
4774
4775// FIXME? Maybe this could be a TableGen attribute on some registers and
4776// this table could be generated automatically from RegInfo.
4777unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4778 SelectionDAG &DAG) const {
4779 unsigned Reg = StringSwitch<unsigned>(RegName)
4780 .Case("sp", AArch64::SP)
4781 .Case("x18", AArch64::X18)
4782 .Case("w18", AArch64::W18)
4783 .Default(0);
4784 if ((Reg == AArch64::X18 || Reg == AArch64::W18) &&
4785 !Subtarget->isX18Reserved())
4786 Reg = 0;
4787 if (Reg)
4788 return Reg;
4789 report_fatal_error(Twine("Invalid register name \""
4790 + StringRef(RegName) + "\"."));
4791}
4792
4793SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4794 SelectionDAG &DAG) const {
4795 MachineFunction &MF = DAG.getMachineFunction();
4796 MachineFrameInfo &MFI = MF.getFrameInfo();
4797 MFI.setReturnAddressIsTaken(true);
4798
4799 EVT VT = Op.getValueType();
4800 SDLoc DL(Op);
4801 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4802 if (Depth) {
4803 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4804 SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
4805 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4806 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4807 MachinePointerInfo());
4808 }
4809
4810 // Return LR, which contains the return address. Mark it an implicit live-in.
4811 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4812 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4813}
4814
4815/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4816/// i64 values and take a 2 x i64 value to shift plus a shift amount.
4817SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4818 SelectionDAG &DAG) const {
4819 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4819, __extension__ __PRETTY_FUNCTION__))
;
4820 EVT VT = Op.getValueType();
4821 unsigned VTBits = VT.getSizeInBits();
4822 SDLoc dl(Op);
4823 SDValue ShOpLo = Op.getOperand(0);
4824 SDValue ShOpHi = Op.getOperand(1);
4825 SDValue ShAmt = Op.getOperand(2);
4826 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4827
4828 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SRA_PARTS ||
Op.getOpcode() == ISD::SRL_PARTS) ? void (0) : __assert_fail
("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4828, __extension__ __PRETTY_FUNCTION__))
;
4829
4830 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4831 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4832 SDValue HiBitsForLo = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4833
4834 // Unfortunately, if ShAmt == 0, we just calculated "(SHL ShOpHi, 64)" which
4835 // is "undef". We wanted 0, so CSEL it directly.
4836 SDValue Cmp = emitComparison(ShAmt, DAG.getConstant(0, dl, MVT::i64),
4837 ISD::SETEQ, dl, DAG);
4838 SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);
4839 HiBitsForLo =
4840 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4841 HiBitsForLo, CCVal, Cmp);
4842
4843 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4844 DAG.getConstant(VTBits, dl, MVT::i64));
4845
4846 SDValue LoBitsForLo = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4847 SDValue LoForNormalShift =
4848 DAG.getNode(ISD::OR, dl, VT, LoBitsForLo, HiBitsForLo);
4849
4850 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE,
4851 dl, DAG);
4852 CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4853 SDValue LoForBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4854 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4855 LoForNormalShift, CCVal, Cmp);
4856
4857 // AArch64 shifts larger than the register width are wrapped rather than
4858 // clamped, so we can't just emit "hi >> x".
4859 SDValue HiForNormalShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4860 SDValue HiForBigShift =
4861 Opc == ISD::SRA
4862 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4863 DAG.getConstant(VTBits - 1, dl, MVT::i64))
4864 : DAG.getConstant(0, dl, VT);
4865 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4866 HiForNormalShift, CCVal, Cmp);
4867
4868 SDValue Ops[2] = { Lo, Hi };
4869 return DAG.getMergeValues(Ops, dl);
4870}
4871
4872/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4873/// i64 values and take a 2 x i64 value to shift plus a shift amount.
4874SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4875 SelectionDAG &DAG) const {
4876 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4876, __extension__ __PRETTY_FUNCTION__))
;
4877 EVT VT = Op.getValueType();
4878 unsigned VTBits = VT.getSizeInBits();
4879 SDLoc dl(Op);
4880 SDValue ShOpLo = Op.getOperand(0);
4881 SDValue ShOpHi = Op.getOperand(1);
4882 SDValue ShAmt = Op.getOperand(2);
4883
4884 assert(Op.getOpcode() == ISD::SHL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SHL_PARTS) ?
void (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 4884, __extension__ __PRETTY_FUNCTION__))
;
4885 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4886 DAG.getConstant(VTBits, dl, MVT::i64), ShAmt);
4887 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4888
4889 // Unfortunately, if ShAmt == 0, we just calculated "(SRL ShOpLo, 64)" which
4890 // is "undef". We wanted 0, so CSEL it directly.
4891 SDValue Cmp = emitComparison(ShAmt, DAG.getConstant(0, dl, MVT::i64),
4892 ISD::SETEQ, dl, DAG);
4893 SDValue CCVal = DAG.getConstant(AArch64CC::EQ, dl, MVT::i32);
4894 LoBitsForHi =
4895 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4896 LoBitsForHi, CCVal, Cmp);
4897
4898 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4899 DAG.getConstant(VTBits, dl, MVT::i64));
4900 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4901 SDValue HiForNormalShift =
4902 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi);
4903
4904 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4905
4906 Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, dl, MVT::i64), ISD::SETGE,
4907 dl, DAG);
4908 CCVal = DAG.getConstant(AArch64CC::GE, dl, MVT::i32);
4909 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4910 HiForNormalShift, CCVal, Cmp);
4911
4912 // AArch64 shifts of larger than register sizes are wrapped rather than
4913 // clamped, so we can't just emit "lo << a" if a is too big.
4914 SDValue LoForBigShift = DAG.getConstant(0, dl, VT);
4915 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4916 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4917 LoForNormalShift, CCVal, Cmp);
4918
4919 SDValue Ops[2] = { Lo, Hi };
4920 return DAG.getMergeValues(Ops, dl);
4921}
4922
4923bool AArch64TargetLowering::isOffsetFoldingLegal(
4924 const GlobalAddressSDNode *GA) const {
4925 DEBUG(dbgs() << "Skipping offset folding global address: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Skipping offset folding global address: "
; } } while (false)
;
4926 DEBUG(GA->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { GA->dump(); } } while (false)
;
4927 DEBUG(dbgs() << "AArch64 doesn't support folding offsets into global "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "AArch64 doesn't support folding offsets into global "
"addresses\n"; } } while (false)
4928 "addresses\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "AArch64 doesn't support folding offsets into global "
"addresses\n"; } } while (false)
;
4929 return false;
4930}
4931
4932bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4933 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4934 // FIXME: We should be able to handle f128 as well with a clever lowering.
4935 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 ||
4936 (VT == MVT::f16 && Subtarget->hasFullFP16()))) {
4937 DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Legal fp imm: materialize 0 using the zero register\n"
; } } while (false)
;
4938 return true;
4939 }
4940
4941 StringRef FPType;
4942 bool IsLegal = false;
4943 SmallString<128> ImmStrVal;
4944 Imm.toString(ImmStrVal);
4945
4946 if (VT == MVT::f64) {
4947 FPType = "f64";
4948 IsLegal = AArch64_AM::getFP64Imm(Imm) != -1;
4949 } else if (VT == MVT::f32) {
4950 FPType = "f32";
4951 IsLegal = AArch64_AM::getFP32Imm(Imm) != -1;
4952 } else if (VT == MVT::f16 && Subtarget->hasFullFP16()) {
4953 FPType = "f16";
4954 IsLegal = AArch64_AM::getFP16Imm(Imm) != -1;
4955 }
4956
4957 if (IsLegal) {
4958 DEBUG(dbgs() << "Legal " << FPType << " imm value: " << ImmStrVal << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Legal " << FPType
<< " imm value: " << ImmStrVal << "\n"; } }
while (false)
;
4959 return true;
4960 }
4961
4962 if (!FPType.empty())
4963 DEBUG(dbgs() << "Illegal " << FPType << " imm value: " << ImmStrVal << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Illegal " << FPType
<< " imm value: " << ImmStrVal << "\n"; } }
while (false)
;
4964 else
4965 DEBUG(dbgs() << "Illegal fp imm " << ImmStrVal << ": unsupported fp type\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Illegal fp imm " <<
ImmStrVal << ": unsupported fp type\n"; } } while (false
)
;
4966
4967 return false;
4968}
4969
4970//===----------------------------------------------------------------------===//
4971// AArch64 Optimization Hooks
4972//===----------------------------------------------------------------------===//
4973
4974static SDValue getEstimate(const AArch64Subtarget *ST, unsigned Opcode,
4975 SDValue Operand, SelectionDAG &DAG,
4976 int &ExtraSteps) {
4977 EVT VT = Operand.getValueType();
4978 if (ST->hasNEON() &&
4979 (VT == MVT::f64 || VT == MVT::v1f64 || VT == MVT::v2f64 ||
4980 VT == MVT::f32 || VT == MVT::v1f32 ||
4981 VT == MVT::v2f32 || VT == MVT::v4f32)) {
4982 if (ExtraSteps == TargetLoweringBase::ReciprocalEstimate::Unspecified)
4983 // For the reciprocal estimates, convergence is quadratic, so the number
4984 // of digits is doubled after each iteration. In ARMv8, the accuracy of
4985 // the initial estimate is 2^-8. Thus the number of extra steps to refine
4986 // the result for float (23 mantissa bits) is 2 and for double (52
4987 // mantissa bits) is 3.
4988 ExtraSteps = VT.getScalarType() == MVT::f64 ? 3 : 2;
4989
4990 return DAG.getNode(Opcode, SDLoc(Operand), VT, Operand);
4991 }
4992
4993 return SDValue();
4994}
4995
4996SDValue AArch64TargetLowering::getSqrtEstimate(SDValue Operand,
4997 SelectionDAG &DAG, int Enabled,
4998 int &ExtraSteps,
4999 bool &UseOneConst,
5000 bool Reciprocal) const {
5001 if (Enabled == ReciprocalEstimate::Enabled ||
5002 (Enabled == ReciprocalEstimate::Unspecified && Subtarget->useRSqrt()))
5003 if (SDValue Estimate = getEstimate(Subtarget, AArch64ISD::FRSQRTE, Operand,
5004 DAG, ExtraSteps)) {
5005 SDLoc DL(Operand);
5006 EVT VT = Operand.getValueType();
5007
5008 SDNodeFlags Flags;
5009 Flags.setUnsafeAlgebra(true);
5010
5011 // Newton reciprocal square root iteration: E * 0.5 * (3 - X * E^2)
5012 // AArch64 reciprocal square root iteration instruction: 0.5 * (3 - M * N)
5013 for (int i = ExtraSteps; i > 0; --i) {
5014 SDValue Step = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Estimate,
5015 Flags);
5016 Step = DAG.getNode(AArch64ISD::FRSQRTS, DL, VT, Operand, Step, Flags);
5017 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags);
5018 }
5019 if (!Reciprocal) {
5020 EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
5021 VT);
5022 SDValue FPZero = DAG.getConstantFP(0.0, DL, VT);
5023 SDValue Eq = DAG.getSetCC(DL, CCVT, Operand, FPZero, ISD::SETEQ);
5024
5025 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Operand, Estimate, Flags);
5026 // Correct the result if the operand is 0.0.
5027 Estimate = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL,
5028 VT, Eq, Operand, Estimate);
5029 }
5030
5031 ExtraSteps = 0;
5032 return Estimate;
5033 }
5034
5035 return SDValue();
5036}
5037
5038SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,
5039 SelectionDAG &DAG, int Enabled,
5040 int &ExtraSteps) const {
5041 if (Enabled == ReciprocalEstimate::Enabled)
5042 if (SDValue Estimate = getEstimate(Subtarget, AArch64ISD::FRECPE, Operand,
5043 DAG, ExtraSteps)) {
5044 SDLoc DL(Operand);
5045 EVT VT = Operand.getValueType();
5046
5047 SDNodeFlags Flags;
5048 Flags.setUnsafeAlgebra(true);
5049
5050 // Newton reciprocal iteration: E * (2 - X * E)
5051 // AArch64 reciprocal iteration instruction: (2 - M * N)
5052 for (int i = ExtraSteps; i > 0; --i) {
5053 SDValue Step = DAG.getNode(AArch64ISD::FRECPS, DL, VT, Operand,
5054 Estimate, Flags);
5055 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags);
5056 }
5057
5058 ExtraSteps = 0;
5059 return Estimate;
5060 }
5061
5062 return SDValue();
5063}
5064
5065//===----------------------------------------------------------------------===//
5066// AArch64 Inline Assembly Support
5067//===----------------------------------------------------------------------===//
5068
5069// Table of Constraints
5070// TODO: This is the current set of constraints supported by ARM for the
5071// compiler, not all of them may make sense, e.g. S may be difficult to support.
5072//
5073// r - A general register
5074// w - An FP/SIMD register of some size in the range v0-v31
5075// x - An FP/SIMD register of some size in the range v0-v15
5076// I - Constant that can be used with an ADD instruction
5077// J - Constant that can be used with a SUB instruction
5078// K - Constant that can be used with a 32-bit logical instruction
5079// L - Constant that can be used with a 64-bit logical instruction
5080// M - Constant that can be used as a 32-bit MOV immediate
5081// N - Constant that can be used as a 64-bit MOV immediate
5082// Q - A memory reference with base register and no offset
5083// S - A symbolic address
5084// Y - Floating point constant zero
5085// Z - Integer constant zero
5086//
5087// Note that general register operands will be output using their 64-bit x
5088// register name, whatever the size of the variable, unless the asm operand
5089// is prefixed by the %w modifier. Floating-point and SIMD register operands
5090// will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
5091// %q modifier.
5092const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
5093 // At this point, we have to lower this constraint to something else, so we
5094 // lower it to an "r" or "w". However, by doing this we will force the result
5095 // to be in register, while the X constraint is much more permissive.
5096 //
5097 // Although we are correct (we are free to emit anything, without
5098 // constraints), we might break use cases that would expect us to be more
5099 // efficient and emit something else.
5100 if (!Subtarget->hasFPARMv8())
5101 return "r";
5102
5103 if (ConstraintVT.isFloatingPoint())
5104 return "w";
5105
5106 if (ConstraintVT.isVector() &&
5107 (ConstraintVT.getSizeInBits() == 64 ||
5108 ConstraintVT.getSizeInBits() == 128))
5109 return "w";
5110
5111 return "r";
5112}
5113
5114/// getConstraintType - Given a constraint letter, return the type of
5115/// constraint it is for this target.
5116AArch64TargetLowering::ConstraintType
5117AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
5118 if (Constraint.size() == 1) {
5119 switch (Constraint[0]) {
5120 default:
5121 break;
5122 case 'z':
5123 return C_Other;
5124 case 'x':
5125 case 'w':
5126 return C_RegisterClass;
5127 // An address with a single base register. Due to the way we
5128 // currently handle addresses it is the same as 'r'.
5129 case 'Q':
5130 return C_Memory;
5131 }
5132 }
5133 return TargetLowering::getConstraintType(Constraint);
5134}
5135
5136/// Examine constraint type and operand type and determine a weight value.
5137/// This object must already have been set up with the operand type
5138/// and the current alternative constraint selected.
5139TargetLowering::ConstraintWeight
5140AArch64TargetLowering::getSingleConstraintMatchWeight(
5141 AsmOperandInfo &info, const char *constraint) const {
5142 ConstraintWeight weight = CW_Invalid;
5143 Value *CallOperandVal = info.CallOperandVal;
5144 // If we don't have a value, we can't do a match,
5145 // but allow it at the lowest weight.
5146 if (!CallOperandVal)
5147 return CW_Default;
5148 Type *type = CallOperandVal->getType();
5149 // Look at the constraint type.
5150 switch (*constraint) {
5151 default:
5152 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5153 break;
5154 case 'x':
5155 case 'w':
5156 if (type->isFloatingPointTy() || type->isVectorTy())
5157 weight = CW_Register;
5158 break;
5159 case 'z':
5160 weight = CW_Constant;
5161 break;
5162 }
5163 return weight;
5164}
5165
5166std::pair<unsigned, const TargetRegisterClass *>
5167AArch64TargetLowering::getRegForInlineAsmConstraint(
5168 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
5169 if (Constraint.size() == 1) {
5170 switch (Constraint[0]) {
5171 case 'r':
5172 if (VT.getSizeInBits() == 64)
5173 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
5174 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
5175 case 'w':
5176 if (VT.getSizeInBits() == 16)
5177 return std::make_pair(0U, &AArch64::FPR16RegClass);
5178 if (VT.getSizeInBits() == 32)
5179 return std::make_pair(0U, &AArch64::FPR32RegClass);
5180 if (VT.getSizeInBits() == 64)
5181 return std::make_pair(0U, &AArch64::FPR64RegClass);
5182 if (VT.getSizeInBits() == 128)
5183 return std::make_pair(0U, &AArch64::FPR128RegClass);
5184 break;
5185 // The instructions that this constraint is designed for can
5186 // only take 128-bit registers so just use that regclass.
5187 case 'x':
5188 if (VT.getSizeInBits() == 128)
5189 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
5190 break;
5191 }
5192 }
5193 if (StringRef("{cc}").equals_lower(Constraint))
5194 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
5195
5196 // Use the default implementation in TargetLowering to convert the register
5197 // constraint into a member of a register class.
5198 std::pair<unsigned, const TargetRegisterClass *> Res;
5199 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
5200
5201 // Not found as a standard register?
5202 if (!Res.second) {
5203 unsigned Size = Constraint.size();
5204 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
5205 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
5206 int RegNo;
5207 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
5208 if (!Failed && RegNo >= 0 && RegNo <= 31) {
5209 // v0 - v31 are aliases of q0 - q31 or d0 - d31 depending on size.
5210 // By default we'll emit v0-v31 for this unless there's a modifier where
5211 // we'll emit the correct register as well.
5212 if (VT != MVT::Other && VT.getSizeInBits() == 64) {
5213 Res.first = AArch64::FPR64RegClass.getRegister(RegNo);
5214 Res.second = &AArch64::FPR64RegClass;
5215 } else {
5216 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
5217 Res.second = &AArch64::FPR128RegClass;
5218 }
5219 }
5220 }
5221 }
5222
5223 return Res;
5224}
5225
5226/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5227/// vector. If it is invalid, don't add anything to Ops.
5228void AArch64TargetLowering::LowerAsmOperandForConstraint(
5229 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
5230 SelectionDAG &DAG) const {
5231 SDValue Result;
5232
5233 // Currently only support length 1 constraints.
5234 if (Constraint.length() != 1)
5235 return;
5236
5237 char ConstraintLetter = Constraint[0];
5238 switch (ConstraintLetter) {
5239 default:
5240 break;
5241
5242 // This set of constraints deal with valid constants for various instructions.
5243 // Validate and return a target constant for them if we can.
5244 case 'z': {
5245 // 'z' maps to xzr or wzr so it needs an input of 0.
5246 if (!isNullConstant(Op))
5247 return;
5248
5249 if (Op.getValueType() == MVT::i64)
5250 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
5251 else
5252 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
5253 break;
5254 }
5255
5256 case 'I':
5257 case 'J':
5258 case 'K':
5259 case 'L':
5260 case 'M':
5261 case 'N':
5262 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5263 if (!C)
5264 return;
5265
5266 // Grab the value and do some validation.
5267 uint64_t CVal = C->getZExtValue();
5268 switch (ConstraintLetter) {
5269 // The I constraint applies only to simple ADD or SUB immediate operands:
5270 // i.e. 0 to 4095 with optional shift by 12
5271 // The J constraint applies only to ADD or SUB immediates that would be
5272 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
5273 // instruction [or vice versa], in other words -1 to -4095 with optional
5274 // left shift by 12.
5275 case 'I':
5276 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
5277 break;
5278 return;
5279 case 'J': {
5280 uint64_t NVal = -C->getSExtValue();
5281 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
5282 CVal = C->getSExtValue();
5283 break;
5284 }
5285 return;
5286 }
5287 // The K and L constraints apply *only* to logical immediates, including
5288 // what used to be the MOVI alias for ORR (though the MOVI alias has now
5289 // been removed and MOV should be used). So these constraints have to
5290 // distinguish between bit patterns that are valid 32-bit or 64-bit
5291 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
5292 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
5293 // versa.
5294 case 'K':
5295 if (AArch64_AM::isLogicalImmediate(CVal, 32))
5296 break;
5297 return;
5298 case 'L':
5299 if (AArch64_AM::isLogicalImmediate(CVal, 64))
5300 break;
5301 return;
5302 // The M and N constraints are a superset of K and L respectively, for use
5303 // with the MOV (immediate) alias. As well as the logical immediates they
5304 // also match 32 or 64-bit immediates that can be loaded either using a
5305 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
5306 // (M) or 64-bit 0x1234000000000000 (N) etc.
5307 // As a note some of this code is liberally stolen from the asm parser.
5308 case 'M': {
5309 if (!isUInt<32>(CVal))
5310 return;
5311 if (AArch64_AM::isLogicalImmediate(CVal, 32))
5312 break;
5313 if ((CVal & 0xFFFF) == CVal)
5314 break;
5315 if ((CVal & 0xFFFF0000ULL) == CVal)
5316 break;
5317 uint64_t NCVal = ~(uint32_t)CVal;
5318 if ((NCVal & 0xFFFFULL) == NCVal)
5319 break;
5320 if ((NCVal & 0xFFFF0000ULL) == NCVal)
5321 break;
5322 return;
5323 }
5324 case 'N': {
5325 if (AArch64_AM::isLogicalImmediate(CVal, 64))
5326 break;
5327 if ((CVal & 0xFFFFULL) == CVal)
5328 break;
5329 if ((CVal & 0xFFFF0000ULL) == CVal)
5330 break;
5331 if ((CVal & 0xFFFF00000000ULL) == CVal)
5332 break;
5333 if ((CVal & 0xFFFF000000000000ULL) == CVal)
5334 break;
5335 uint64_t NCVal = ~CVal;
5336 if ((NCVal & 0xFFFFULL) == NCVal)
5337 break;
5338 if ((NCVal & 0xFFFF0000ULL) == NCVal)
5339 break;
5340 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
5341 break;
5342 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
5343 break;
5344 return;
5345 }
5346 default:
5347 return;
5348 }
5349
5350 // All assembler immediates are 64-bit integers.
5351 Result = DAG.getTargetConstant(CVal, SDLoc(Op), MVT::i64);
5352 break;
5353 }
5354
5355 if (Result.getNode()) {
5356 Ops.push_back(Result);
5357 return;
5358 }
5359
5360 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5361}
5362
5363//===----------------------------------------------------------------------===//
5364// AArch64 Advanced SIMD Support
5365//===----------------------------------------------------------------------===//
5366
5367/// WidenVector - Given a value in the V64 register class, produce the
5368/// equivalent value in the V128 register class.
5369static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
5370 EVT VT = V64Reg.getValueType();
5371 unsigned NarrowSize = VT.getVectorNumElements();
5372 MVT EltTy = VT.getVectorElementType().getSimpleVT();
5373 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
5374 SDLoc DL(V64Reg);
5375
5376 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
5377 V64Reg, DAG.getConstant(0, DL, MVT::i32));
5378}
5379
5380/// getExtFactor - Determine the adjustment factor for the position when
5381/// generating an "extract from vector registers" instruction.
5382static unsigned getExtFactor(SDValue &V) {
5383 EVT EltType = V.getValueType().getVectorElementType();
5384 return EltType.getSizeInBits() / 8;
5385}
5386
5387/// NarrowVector - Given a value in the V128 register class, produce the
5388/// equivalent value in the V64 register class.
5389static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
5390 EVT VT = V128Reg.getValueType();
5391 unsigned WideSize = VT.getVectorNumElements();
5392 MVT EltTy = VT.getVectorElementType().getSimpleVT();
5393 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
5394 SDLoc DL(V128Reg);
5395
5396 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
5397}
5398
5399// Gather data to see if the operation can be modelled as a
5400// shuffle in combination with VEXTs.
5401SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
5402 SelectionDAG &DAG) const {
5403 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!")(static_cast <bool> (Op.getOpcode() == ISD::BUILD_VECTOR
&& "Unknown opcode!") ? void (0) : __assert_fail ("Op.getOpcode() == ISD::BUILD_VECTOR && \"Unknown opcode!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5403, __extension__ __PRETTY_FUNCTION__))
;
5404 DEBUG(dbgs() << "AArch64TargetLowering::ReconstructShuffle\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "AArch64TargetLowering::ReconstructShuffle\n"
; } } while (false)
;
5405 SDLoc dl(Op);
5406 EVT VT = Op.getValueType();
5407 unsigned NumElts = VT.getVectorNumElements();
5408
5409 struct ShuffleSourceInfo {
5410 SDValue Vec;
5411 unsigned MinElt;
5412 unsigned MaxElt;
5413
5414 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
5415 // be compatible with the shuffle we intend to construct. As a result
5416 // ShuffleVec will be some sliding window into the original Vec.
5417 SDValue ShuffleVec;
5418
5419 // Code should guarantee that element i in Vec starts at element "WindowBase
5420 // + i * WindowScale in ShuffleVec".
5421 int WindowBase;
5422 int WindowScale;
5423
5424 ShuffleSourceInfo(SDValue Vec)
5425 : Vec(Vec), MinElt(std::numeric_limits<unsigned>::max()), MaxElt(0),
5426 ShuffleVec(Vec), WindowBase(0), WindowScale(1) {}
5427
5428 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
5429 };
5430
5431 // First gather all vectors used as an immediate source for this BUILD_VECTOR
5432 // node.
5433 SmallVector<ShuffleSourceInfo, 2> Sources;
5434 for (unsigned i = 0; i < NumElts; ++i) {
5435 SDValue V = Op.getOperand(i);
5436 if (V.isUndef())
5437 continue;
5438 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5439 !isa<ConstantSDNode>(V.getOperand(1))) {
5440 DEBUG(dbgs() << "Reshuffle failed: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: " "a shuffle can only come from building a vector from "
"various elements of other vectors, provided their " "indices are constant\n"
; } } while (false)
5441 "a shuffle can only come from building a vector from "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: " "a shuffle can only come from building a vector from "
"various elements of other vectors, provided their " "indices are constant\n"
; } } while (false)
5442 "various elements of other vectors, provided their "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: " "a shuffle can only come from building a vector from "
"various elements of other vectors, provided their " "indices are constant\n"
; } } while (false)
5443 "indices are constant\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: " "a shuffle can only come from building a vector from "
"various elements of other vectors, provided their " "indices are constant\n"
; } } while (false)
;
5444 return SDValue();
5445 }
5446
5447 // Add this element source to the list if it's not already there.
5448 SDValue SourceVec = V.getOperand(0);
5449 auto Source = find(Sources, SourceVec);
5450 if (Source == Sources.end())
5451 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
5452
5453 // Update the minimum and maximum lane number seen.
5454 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5455 Source->MinElt = std::min(Source->MinElt, EltNo);
5456 Source->MaxElt = std::max(Source->MaxElt, EltNo);
5457 }
5458
5459 if (Sources.size() > 2) {
5460 DEBUG(dbgs() << "Reshuffle failed: currently only do something sane when at "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: currently only do something sane when at "
"most two source vectors are involved\n"; } } while (false)
5461 "most two source vectors are involved\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: currently only do something sane when at "
"most two source vectors are involved\n"; } } while (false)
;
5462 return SDValue();
5463 }
5464
5465 // Find out the smallest element size among result and two sources, and use
5466 // it as element size to build the shuffle_vector.
5467 EVT SmallestEltTy = VT.getVectorElementType();
5468 for (auto &Source : Sources) {
5469 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
5470 if (SrcEltTy.bitsLT(SmallestEltTy)) {
5471 SmallestEltTy = SrcEltTy;
5472 }
5473 }
5474 unsigned ResMultiplier =
5475 VT.getScalarSizeInBits() / SmallestEltTy.getSizeInBits();
5476 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
5477 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
5478
5479 // If the source vector is too wide or too narrow, we may nevertheless be able
5480 // to construct a compatible shuffle either by concatenating it with UNDEF or
5481 // extracting a suitable range of elements.
5482 for (auto &Src : Sources) {
5483 EVT SrcVT = Src.ShuffleVec.getValueType();
5484
5485 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
5486 continue;
5487
5488 // This stage of the search produces a source with the same element type as
5489 // the original, but with a total width matching the BUILD_VECTOR output.
5490 EVT EltVT = SrcVT.getVectorElementType();
5491 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
5492 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
5493
5494 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
5495 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits())(static_cast <bool> (2 * SrcVT.getSizeInBits() == VT.getSizeInBits
()) ? void (0) : __assert_fail ("2 * SrcVT.getSizeInBits() == VT.getSizeInBits()"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5495, __extension__ __PRETTY_FUNCTION__))
;
5496 // We can pad out the smaller vector for free, so if it's part of a
5497 // shuffle...
5498 Src.ShuffleVec =
5499 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
5500 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
5501 continue;
5502 }
5503
5504 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits())(static_cast <bool> (SrcVT.getSizeInBits() == 2 * VT.getSizeInBits
()) ? void (0) : __assert_fail ("SrcVT.getSizeInBits() == 2 * VT.getSizeInBits()"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5504, __extension__ __PRETTY_FUNCTION__))
;
5505
5506 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
5507 DEBUG(dbgs() << "Reshuffle failed: span too large for a VEXT to cope\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: span too large for a VEXT to cope\n"
; } } while (false)
;
5508 return SDValue();
5509 }
5510
5511 if (Src.MinElt >= NumSrcElts) {
5512 // The extraction can just take the second half
5513 Src.ShuffleVec =
5514 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5515 DAG.getConstant(NumSrcElts, dl, MVT::i64));
5516 Src.WindowBase = -NumSrcElts;
5517 } else if (Src.MaxElt < NumSrcElts) {
5518 // The extraction can just take the first half
5519 Src.ShuffleVec =
5520 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5521 DAG.getConstant(0, dl, MVT::i64));
5522 } else {
5523 // An actual VEXT is needed
5524 SDValue VEXTSrc1 =
5525 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5526 DAG.getConstant(0, dl, MVT::i64));
5527 SDValue VEXTSrc2 =
5528 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5529 DAG.getConstant(NumSrcElts, dl, MVT::i64));
5530 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
5531
5532 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
5533 VEXTSrc2,
5534 DAG.getConstant(Imm, dl, MVT::i32));
5535 Src.WindowBase = -Src.MinElt;
5536 }
5537 }
5538
5539 // Another possible incompatibility occurs from the vector element types. We
5540 // can fix this by bitcasting the source vectors to the same type we intend
5541 // for the shuffle.
5542 for (auto &Src : Sources) {
5543 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
5544 if (SrcEltTy == SmallestEltTy)
5545 continue;
5546 assert(ShuffleVT.getVectorElementType() == SmallestEltTy)(static_cast <bool> (ShuffleVT.getVectorElementType() ==
SmallestEltTy) ? void (0) : __assert_fail ("ShuffleVT.getVectorElementType() == SmallestEltTy"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
;
5547 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
5548 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
5549 Src.WindowBase *= Src.WindowScale;
5550 }
5551
5552 // Final sanity check before we try to actually produce a shuffle.
5553 DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { for (auto Src : Sources) (static_cast <
bool> (Src.ShuffleVec.getValueType() == ShuffleVT) ? void (
0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5555, __extension__ __PRETTY_FUNCTION__));; } } while (false
)
5554 for (auto Src : Sources)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { for (auto Src : Sources) (static_cast <
bool> (Src.ShuffleVec.getValueType() == ShuffleVT) ? void (
0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5555, __extension__ __PRETTY_FUNCTION__));; } } while (false
)
5555 assert(Src.ShuffleVec.getValueType() == ShuffleVT);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { for (auto Src : Sources) (static_cast <
bool> (Src.ShuffleVec.getValueType() == ShuffleVT) ? void (
0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5555, __extension__ __PRETTY_FUNCTION__));; } } while (false
)
5556 )do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { for (auto Src : Sources) (static_cast <
bool> (Src.ShuffleVec.getValueType() == ShuffleVT) ? void (
0) : __assert_fail ("Src.ShuffleVec.getValueType() == ShuffleVT"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5555, __extension__ __PRETTY_FUNCTION__));; } } while (false
)
;
5557
5558 // The stars all align, our next step is to produce the mask for the shuffle.
5559 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
5560 int BitsPerShuffleLane = ShuffleVT.getScalarSizeInBits();
5561 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
5562 SDValue Entry = Op.getOperand(i);
5563 if (Entry.isUndef())
5564 continue;
5565
5566 auto Src = find(Sources, Entry.getOperand(0));
5567 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
5568
5569 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
5570 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
5571 // segment.
5572 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
5573 int BitsDefined =
5574 std::min(OrigEltTy.getSizeInBits(), VT.getScalarSizeInBits());
5575 int LanesDefined = BitsDefined / BitsPerShuffleLane;
5576
5577 // This source is expected to fill ResMultiplier lanes of the final shuffle,
5578 // starting at the appropriate offset.
5579 int *LaneMask = &Mask[i * ResMultiplier];
5580
5581 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
5582 ExtractBase += NumElts * (Src - Sources.begin());
5583 for (int j = 0; j < LanesDefined; ++j)
5584 LaneMask[j] = ExtractBase + j;
5585 }
5586
5587 // Final check before we try to produce nonsense...
5588 if (!isShuffleMaskLegal(Mask, ShuffleVT)) {
5589 DEBUG(dbgs() << "Reshuffle failed: illegal shuffle mask\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle failed: illegal shuffle mask\n"
; } } while (false)
;
5590 return SDValue();
5591 }
5592
5593 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
5594 for (unsigned i = 0; i < Sources.size(); ++i)
5595 ShuffleOps[i] = Sources[i].ShuffleVec;
5596
5597 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
5598 ShuffleOps[1], Mask);
5599 SDValue V = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
5600
5601 DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle, creating node: "
; Shuffle.dump(); dbgs() << "Reshuffle, creating node: "
; V.dump();; } } while (false)
5602 dbgs() << "Reshuffle, creating node: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle, creating node: "
; Shuffle.dump(); dbgs() << "Reshuffle, creating node: "
; V.dump();; } } while (false)
5603 Shuffle.dump();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle, creating node: "
; Shuffle.dump(); dbgs() << "Reshuffle, creating node: "
; V.dump();; } } while (false)
5604 dbgs() << "Reshuffle, creating node: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle, creating node: "
; Shuffle.dump(); dbgs() << "Reshuffle, creating node: "
; V.dump();; } } while (false)
5605 V.dump();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle, creating node: "
; Shuffle.dump(); dbgs() << "Reshuffle, creating node: "
; V.dump();; } } while (false)
5606 )do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("aarch64-lower")) { dbgs() << "Reshuffle, creating node: "
; Shuffle.dump(); dbgs() << "Reshuffle, creating node: "
; V.dump();; } } while (false)
;
5607
5608 return V;
5609}
5610
5611// check if an EXT instruction can handle the shuffle mask when the
5612// vector sources of the shuffle are the same.
5613static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
5614 unsigned NumElts = VT.getVectorNumElements();
5615
5616 // Assume that the first shuffle index is not UNDEF. Fail if it is.
5617 if (M[0] < 0)
5618 return false;
5619
5620 Imm = M[0];
5621
5622 // If this is a VEXT shuffle, the immediate value is the index of the first
5623 // element. The other shuffle indices must be the successive elements after
5624 // the first one.
5625 unsigned ExpectedElt = Imm;
5626 for (unsigned i = 1; i < NumElts; ++i) {
5627 // Increment the expected index. If it wraps around, just follow it
5628 // back to index zero and keep going.
5629 ++ExpectedElt;
5630 if (ExpectedElt == NumElts)
5631 ExpectedElt = 0;
5632
5633 if (M[i] < 0)
5634 continue; // ignore UNDEF indices
5635 if (ExpectedElt != static_cast<unsigned>(M[i]))
5636 return false;
5637 }
5638
5639 return true;
5640}
5641
5642// check if an EXT instruction can handle the shuffle mask when the
5643// vector sources of the shuffle are different.
5644static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
5645 unsigned &Imm) {
5646 // Look for the first non-undef element.
5647 const int *FirstRealElt = find_if(M, [](int Elt) { return Elt >= 0; });
5648
5649 // Benefit form APInt to handle overflow when calculating expected element.
5650 unsigned NumElts = VT.getVectorNumElements();
5651 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
5652 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
5653 // The following shuffle indices must be the successive elements after the
5654 // first real element.
5655 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
5656 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
5657 if (FirstWrongElt != M.end())
5658 return false;
5659
5660 // The index of an EXT is the first element if it is not UNDEF.
5661 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5662 // value of the first element. E.g.
5663 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
5664 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
5665 // ExpectedElt is the last mask index plus 1.
5666 Imm = ExpectedElt.getZExtValue();
5667
5668 // There are two difference cases requiring to reverse input vectors.
5669 // For example, for vector <4 x i32> we have the following cases,
5670 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
5671 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
5672 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
5673 // to reverse two input vectors.
5674 if (Imm < NumElts)
5675 ReverseEXT = true;
5676 else
5677 Imm -= NumElts;
5678
5679 return true;
5680}
5681
5682/// isREVMask - Check if a vector shuffle corresponds to a REV
5683/// instruction with the specified blocksize. (The order of the elements
5684/// within each block of the vector is reversed.)
5685static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5686 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&(static_cast <bool> ((BlockSize == 16 || BlockSize == 32
|| BlockSize == 64) && "Only possible block sizes for REV are: 16, 32, 64"
) ? void (0) : __assert_fail ("(BlockSize == 16 || BlockSize == 32 || BlockSize == 64) && \"Only possible block sizes for REV are: 16, 32, 64\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5687, __extension__ __PRETTY_FUNCTION__))
5687 "Only possible block sizes for REV are: 16, 32, 64")(static_cast <bool> ((BlockSize == 16 || BlockSize == 32
|| BlockSize == 64) && "Only possible block sizes for REV are: 16, 32, 64"
) ? void (0) : __assert_fail ("(BlockSize == 16 || BlockSize == 32 || BlockSize == 64) && \"Only possible block sizes for REV are: 16, 32, 64\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5687, __extension__ __PRETTY_FUNCTION__))
;
5688
5689 unsigned EltSz = VT.getScalarSizeInBits();
5690 if (EltSz == 64)
5691 return false;
5692
5693 unsigned NumElts = VT.getVectorNumElements();
5694 unsigned BlockElts = M[0] + 1;
5695 // If the first shuffle index is UNDEF, be optimistic.
5696 if (M[0] < 0)
5697 BlockElts = BlockSize / EltSz;
5698
5699 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5700 return false;
5701
5702 for (unsigned i = 0; i < NumElts; ++i) {
5703 if (M[i] < 0)
5704 continue; // ignore UNDEF indices
5705 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
5706 return false;
5707 }
5708
5709 return true;
5710}
5711
5712static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5713 unsigned NumElts = VT.getVectorNumElements();
5714 WhichResult = (M[0] == 0 ? 0 : 1);
5715 unsigned Idx = WhichResult * NumElts / 2;
5716 for (unsigned i = 0; i != NumElts; i += 2) {
5717 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5718 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
5719 return false;
5720 Idx += 1;
5721 }
5722
5723 return true;
5724}
5725
5726static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5727 unsigned NumElts = VT.getVectorNumElements();
5728 WhichResult = (M[0] == 0 ? 0 : 1);
5729 for (unsigned i = 0; i != NumElts; ++i) {
5730 if (M[i] < 0)
5731 continue; // ignore UNDEF indices
5732 if ((unsigned)M[i] != 2 * i + WhichResult)
5733 return false;
5734 }
5735
5736 return true;
5737}
5738
5739static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5740 unsigned NumElts = VT.getVectorNumElements();
5741 WhichResult = (M[0] == 0 ? 0 : 1);
5742 for (unsigned i = 0; i < NumElts; i += 2) {
5743 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5744 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
5745 return false;
5746 }
5747 return true;
5748}
5749
5750/// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
5751/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5752/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5753static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5754 unsigned NumElts = VT.getVectorNumElements();
5755 WhichResult = (M[0] == 0 ? 0 : 1);
5756 unsigned Idx = WhichResult * NumElts / 2;
5757 for (unsigned i = 0; i != NumElts; i += 2) {
5758 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
5759 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
5760 return false;
5761 Idx += 1;
5762 }
5763
5764 return true;
5765}
5766
5767/// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
5768/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5769/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5770static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5771 unsigned Half = VT.getVectorNumElements() / 2;
5772 WhichResult = (M[0] == 0 ? 0 : 1);
5773 for (unsigned j = 0; j != 2; ++j) {
5774 unsigned Idx = WhichResult;
5775 for (unsigned i = 0; i != Half; ++i) {
5776 int MIdx = M[i + j * Half];
5777 if (MIdx >= 0 && (unsigned)MIdx != Idx)
5778 return false;
5779 Idx += 2;
5780 }
5781 }
5782
5783 return true;
5784}
5785
5786/// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
5787/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5788/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5789static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5790 unsigned NumElts = VT.getVectorNumElements();
5791 WhichResult = (M[0] == 0 ? 0 : 1);
5792 for (unsigned i = 0; i < NumElts; i += 2) {
5793 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
5794 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
5795 return false;
5796 }
5797 return true;
5798}
5799
5800static bool isINSMask(ArrayRef<int> M, int NumInputElements,
5801 bool &DstIsLeft, int &Anomaly) {
5802 if (M.size() != static_cast<size_t>(NumInputElements))
5803 return false;
5804
5805 int NumLHSMatch = 0, NumRHSMatch = 0;
5806 int LastLHSMismatch = -1, LastRHSMismatch = -1;
5807
5808 for (int i = 0; i < NumInputElements; ++i) {
5809 if (M[i] == -1) {
5810 ++NumLHSMatch;
5811 ++NumRHSMatch;
5812 continue;
5813 }
5814
5815 if (M[i] == i)
5816 ++NumLHSMatch;
5817 else
5818 LastLHSMismatch = i;
5819
5820 if (M[i] == i + NumInputElements)
5821 ++NumRHSMatch;
5822 else
5823 LastRHSMismatch = i;
5824 }
5825
5826 if (NumLHSMatch == NumInputElements - 1) {
5827 DstIsLeft = true;
5828 Anomaly = LastLHSMismatch;
5829 return true;
5830 } else if (NumRHSMatch == NumInputElements - 1) {
5831 DstIsLeft = false;
5832 Anomaly = LastRHSMismatch;
5833 return true;
5834 }
5835
5836 return false;
5837}
5838
5839static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
5840 if (VT.getSizeInBits() != 128)
5841 return false;
5842
5843 unsigned NumElts = VT.getVectorNumElements();
5844
5845 for (int I = 0, E = NumElts / 2; I != E; I++) {
5846 if (Mask[I] != I)
5847 return false;
5848 }
5849
5850 int Offset = NumElts / 2;
5851 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
5852 if (Mask[I] != I + SplitLHS * Offset)
5853 return false;
5854 }
5855
5856 return true;
5857}
5858
5859static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
5860 SDLoc DL(Op);
5861 EVT VT = Op.getValueType();
5862 SDValue V0 = Op.getOperand(0);
5863 SDValue V1 = Op.getOperand(1);
5864 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
5865
5866 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
5867 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
5868 return SDValue();
5869
5870 bool SplitV0 = V0.getValueSizeInBits() == 128;
5871
5872 if (!isConcatMask(Mask, VT, SplitV0))
5873 return SDValue();
5874
5875 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
5876 VT.getVectorNumElements() / 2);
5877 if (SplitV0) {
5878 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
5879 DAG.getConstant(0, DL, MVT::i64));
5880 }
5881 if (V1.getValueSizeInBits() == 128) {
5882 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
5883 DAG.getConstant(0, DL, MVT::i64));
5884 }
5885 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
5886}
5887
5888/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5889/// the specified operations to build the shuffle.
5890static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5891 SDValue RHS, SelectionDAG &DAG,
5892 const SDLoc &dl) {
5893 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5894 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
5895 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
5896
5897 enum {
5898 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5899 OP_VREV,
5900 OP_VDUP0,
5901 OP_VDUP1,
5902 OP_VDUP2,
5903 OP_VDUP3,
5904 OP_VEXT1,
5905 OP_VEXT2,
5906 OP_VEXT3,
5907 OP_VUZPL, // VUZP, left result
5908 OP_VUZPR, // VUZP, right result
5909 OP_VZIPL, // VZIP, left result
5910 OP_VZIPR, // VZIP, right result
5911 OP_VTRNL, // VTRN, left result
5912 OP_VTRNR // VTRN, right result
5913 };
5914
5915 if (OpNum == OP_COPY) {
5916 if (LHSID == (1 * 9 + 2) * 9 + 3)
5917 return LHS;
5918 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!")(static_cast <bool> (LHSID == ((4 * 9 + 5) * 9 + 6) * 9
+ 7 && "Illegal OP_COPY!") ? void (0) : __assert_fail
("LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && \"Illegal OP_COPY!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5918, __extension__ __PRETTY_FUNCTION__))
;
5919 return RHS;
5920 }
5921
5922 SDValue OpLHS, OpRHS;
5923 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5924 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5925 EVT VT = OpLHS.getValueType();
5926
5927 switch (OpNum) {
5928 default:
5929 llvm_unreachable("Unknown shuffle opcode!")::llvm::llvm_unreachable_internal("Unknown shuffle opcode!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/AArch64/AArch64ISelLowering.cpp"
, 5929)
;
5930 case OP_VREV:
5931 // VREV divides the vector in half and swaps within the half.
5932 if (VT.getVectorElementType() == MVT::i32 ||
5933 VT.getVectorElementType() == MVT::f32)