Bug Summary

File:lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
Warning:line 320, column 8
Excessive padding in 'struct LdStNInstrDesc' (11 padding bytes, where 3 is optimal). Optimal fields order: Mnemonic, Layout, Opcode, ListOperand, NaturalOffset, HasLane, consider reordering the fields or adding explicit padding members

Annotated Source Code

1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an AArch64 MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AArch64InstPrinter.h"
15#include "MCTargetDesc/AArch64AddressingModes.h"
16#include "Utils/AArch64BaseInfo.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/ADT/StringExtras.h"
19#include "llvm/ADT/StringRef.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/Casting.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/Format.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/raw_ostream.h"
29#include <cassert>
30#include <cstdint>
31#include <string>
32
33using namespace llvm;
34
35#define DEBUG_TYPE"asm-printer" "asm-printer"
36
37#define GET_INSTRUCTION_NAME
38#define PRINT_ALIAS_INSTR
39#include "AArch64GenAsmWriter.inc"
40#define GET_INSTRUCTION_NAME
41#define PRINT_ALIAS_INSTR
42#include "AArch64GenAsmWriter1.inc"
43
44AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
45 const MCInstrInfo &MII,
46 const MCRegisterInfo &MRI)
47 : MCInstPrinter(MAI, MII, MRI) {}
48
49AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
50 const MCInstrInfo &MII,
51 const MCRegisterInfo &MRI)
52 : AArch64InstPrinter(MAI, MII, MRI) {}
53
54void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
55 // This is for .cfi directives.
56 OS << getRegisterName(RegNo);
57}
58
59void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
60 StringRef Annot,
61 const MCSubtargetInfo &STI) {
62 // Check for special encodings and print the canonical alias instead.
63
64 unsigned Opcode = MI->getOpcode();
65
66 if (Opcode == AArch64::SYSxt)
67 if (printSysAlias(MI, STI, O)) {
68 printAnnotation(O, Annot);
69 return;
70 }
71
72 // SBFM/UBFM should print to a nicer aliased form if possible.
73 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
74 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
75 const MCOperand &Op0 = MI->getOperand(0);
76 const MCOperand &Op1 = MI->getOperand(1);
77 const MCOperand &Op2 = MI->getOperand(2);
78 const MCOperand &Op3 = MI->getOperand(3);
79
80 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
81 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
83 const char *AsmMnemonic = nullptr;
84
85 switch (Op3.getImm()) {
86 default:
87 break;
88 case 7:
89 if (IsSigned)
90 AsmMnemonic = "sxtb";
91 else if (!Is64Bit)
92 AsmMnemonic = "uxtb";
93 break;
94 case 15:
95 if (IsSigned)
96 AsmMnemonic = "sxth";
97 else if (!Is64Bit)
98 AsmMnemonic = "uxth";
99 break;
100 case 31:
101 // *xtw is only valid for signed 64-bit operations.
102 if (Is64Bit && IsSigned)
103 AsmMnemonic = "sxtw";
104 break;
105 }
106
107 if (AsmMnemonic) {
108 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
109 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
110 printAnnotation(O, Annot);
111 return;
112 }
113 }
114
115 // All immediate shifts are aliases, implemented using the Bitfield
116 // instruction. In all cases the immediate shift amount shift must be in
117 // the range 0 to (reg.size -1).
118 if (Op2.isImm() && Op3.isImm()) {
119 const char *AsmMnemonic = nullptr;
120 int shift = 0;
121 int64_t immr = Op2.getImm();
122 int64_t imms = Op3.getImm();
123 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
124 AsmMnemonic = "lsl";
125 shift = 31 - imms;
126 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
127 ((imms + 1 == immr))) {
128 AsmMnemonic = "lsl";
129 shift = 63 - imms;
130 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
131 AsmMnemonic = "lsr";
132 shift = immr;
133 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
134 AsmMnemonic = "lsr";
135 shift = immr;
136 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
137 AsmMnemonic = "asr";
138 shift = immr;
139 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
140 AsmMnemonic = "asr";
141 shift = immr;
142 }
143 if (AsmMnemonic) {
144 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
145 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
146 printAnnotation(O, Annot);
147 return;
148 }
149 }
150
151 // SBFIZ/UBFIZ aliases
152 if (Op2.getImm() > Op3.getImm()) {
153 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
154 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
156 printAnnotation(O, Annot);
157 return;
158 }
159
160 // Otherwise SBFX/UBFX is the preferred form
161 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
162 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
164 printAnnotation(O, Annot);
165 return;
166 }
167
168 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
169 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
170 const MCOperand &Op2 = MI->getOperand(2);
171 int ImmR = MI->getOperand(3).getImm();
172 int ImmS = MI->getOperand(4).getImm();
173
174 if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
175 (ImmR == 0 || ImmS < ImmR)) {
176 // BFC takes precedence over its entire range, sligtly differently to BFI.
177 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
178 int LSB = (BitWidth - ImmR) % BitWidth;
179 int Width = ImmS + 1;
180
181 O << "\tbfc\t" << getRegisterName(Op0.getReg())
182 << ", #" << LSB << ", #" << Width;
183 printAnnotation(O, Annot);
184 return;
185 } else if (ImmS < ImmR) {
186 // BFI alias
187 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
188 int LSB = (BitWidth - ImmR) % BitWidth;
189 int Width = ImmS + 1;
190
191 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
192 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
193 printAnnotation(O, Annot);
194 return;
195 }
196
197 int LSB = ImmR;
198 int Width = ImmS - ImmR + 1;
199 // Otherwise BFXIL the preferred form
200 O << "\tbfxil\t"
201 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
202 << ", #" << LSB << ", #" << Width;
203 printAnnotation(O, Annot);
204 return;
205 }
206
207 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
208 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
209 // printed.
210 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
211 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
212 MI->getOperand(1).isExpr()) {
213 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
214 O << "\tmovz\t";
215 else
216 O << "\tmovn\t";
217
218 O << getRegisterName(MI->getOperand(0).getReg()) << ", #";
219 MI->getOperand(1).getExpr()->print(O, &MAI);
220 return;
221 }
222
223 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
224 MI->getOperand(2).isExpr()) {
225 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #";
226 MI->getOperand(2).getExpr()->print(O, &MAI);
227 return;
228 }
229
230 // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
231 // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
232 // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
233 // that can represent the move is the MOV alias, and the rest get printed
234 // normally.
235 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
236 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
237 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
238 int Shift = MI->getOperand(2).getImm();
239 uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
240
241 if (AArch64_AM::isMOVZMovAlias(Value, Shift,
242 Opcode == AArch64::MOVZXi ? 64 : 32)) {
243 O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
244 << formatImm(SignExtend64(Value, RegWidth));
245 return;
246 }
247 }
248
249 if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
250 MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
251 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
252 int Shift = MI->getOperand(2).getImm();
253 uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
254 if (RegWidth == 32)
255 Value = Value & 0xffffffff;
256
257 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
258 O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
259 << formatImm(SignExtend64(Value, RegWidth));
260 return;
261 }
262 }
263
264 if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
265 (MI->getOperand(1).getReg() == AArch64::XZR ||
266 MI->getOperand(1).getReg() == AArch64::WZR) &&
267 MI->getOperand(2).isImm()) {
268 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
269 uint64_t Value = AArch64_AM::decodeLogicalImmediate(
270 MI->getOperand(2).getImm(), RegWidth);
271 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
272 O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
273 << formatImm(SignExtend64(Value, RegWidth));
274 return;
275 }
276 }
277
278 if (!printAliasInstr(MI, STI, O))
279 printInstruction(MI, STI, O);
280
281 printAnnotation(O, Annot);
282}
283
284static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
285 bool &IsTbx) {
286 switch (Opcode) {
287 case AArch64::TBXv8i8One:
288 case AArch64::TBXv8i8Two:
289 case AArch64::TBXv8i8Three:
290 case AArch64::TBXv8i8Four:
291 IsTbx = true;
292 Layout = ".8b";
293 return true;
294 case AArch64::TBLv8i8One:
295 case AArch64::TBLv8i8Two:
296 case AArch64::TBLv8i8Three:
297 case AArch64::TBLv8i8Four:
298 IsTbx = false;
299 Layout = ".8b";
300 return true;
301 case AArch64::TBXv16i8One:
302 case AArch64::TBXv16i8Two:
303 case AArch64::TBXv16i8Three:
304 case AArch64::TBXv16i8Four:
305 IsTbx = true;
306 Layout = ".16b";
307 return true;
308 case AArch64::TBLv16i8One:
309 case AArch64::TBLv16i8Two:
310 case AArch64::TBLv16i8Three:
311 case AArch64::TBLv16i8Four:
312 IsTbx = false;
313 Layout = ".16b";
314 return true;
315 default:
316 return false;
317 }
318}
319
320struct LdStNInstrDesc {
Excessive padding in 'struct LdStNInstrDesc' (11 padding bytes, where 3 is optimal). Optimal fields order: Mnemonic, Layout, Opcode, ListOperand, NaturalOffset, HasLane, consider reordering the fields or adding explicit padding members
321 unsigned Opcode;
322 const char *Mnemonic;
323 const char *Layout;
324 int ListOperand;
325 bool HasLane;
326 int NaturalOffset;
327};
328
329static const LdStNInstrDesc LdStNInstInfo[] = {
330 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
331 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
332 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
333 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
334 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
335 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
336 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
337 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
338 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
339 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
340 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
341 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
342 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
343 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
344 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
345 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
346 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
347 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
348 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
349 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
350 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
351 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
352 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
353 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
354 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
355 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
356 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
357 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
358 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
359 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
360 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
361 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
362 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
363 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
364 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
365 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
366 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
367 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
368 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
369 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
370 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
371 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
372 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
373 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
374 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
375 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
376 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
377 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
378 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
379 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
380 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
381 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
382 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
383 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
384 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
385 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
386 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
387 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
388 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
389 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
390 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
391 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
392 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
393 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
394 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
395 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
396 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
397 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
398 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
399 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
400 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
401 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
402 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
403 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
404 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
405 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
406 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
407 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
408 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
409 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
410 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
411 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
412 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
413 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
414 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
415 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
416 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
417 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
418 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
419 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
420 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
421 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
422 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
423 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
424 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
425 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
426 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
427 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
428 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
429 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
430 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
431 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
432 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
433 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
434 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
435 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
436 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
437 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
438 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
439 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
440 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
441 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
442 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
443 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
444 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
445 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
446 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
447 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
448 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
449 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
450 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
451 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
452 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
453 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
454 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
455 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
456 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
457 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
458 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
459 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
460 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
461 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
462 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
463 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
464 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
465 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
466 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
467 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
468 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
469 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
470 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
471 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
472 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
473 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
474 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
475 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
476 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
477 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
478 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
479 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
480 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
481 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
482 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
483 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
484 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
485 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
486 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
487 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
488 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
489 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
490 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
491 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
492 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
493 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
494 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
495 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
496 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
497 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
498 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
499 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
500 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
501 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
502 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
503 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
504 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
505 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
506 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
507 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
508 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
509 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
510 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
511 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
512 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
513 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
514 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
515 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
516 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
517 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
518 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
519 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
520 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
521 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
522 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
523 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
524 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
525 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
526 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
527 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
528 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
529 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
530 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
531 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
532 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
533 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
534 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
535 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
536 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
537 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
538 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
539 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
540 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
541 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
542 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
543 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
544 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
545 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
546 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
547 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
548 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
549 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
550 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
551 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
552 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
553 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
554 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
555 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
556 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
557 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
558 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
559 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
560 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
561 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
562 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
563 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
564 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
565 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
566 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
567 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
568 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
569 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
570 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
571 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
572 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
573 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
574 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
575 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
576 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
577 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
578 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
579 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
580 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
581 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
582 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
583 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
584 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
585 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
586 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
587 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
588 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
589 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
590 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
591 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
592 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
593 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
594 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
595 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
596 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
597 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
598 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
599 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
600 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
601 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
602 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
603 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
604 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
605 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
606 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
607 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
608 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
609 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
610 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
611 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
612 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
613 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
614 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
615 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
616 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
617 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
618 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
619 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
620 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
621 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
622 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
623 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
624 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
625 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
626 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
627 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
628 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
629 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
630 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
631 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
632 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
633 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
634 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
635 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
636 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
637 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
638 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
639 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
640 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
641 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
642 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
643 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
644 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
645 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
646 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
647 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
648 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
649 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
650 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
651 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
652 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
653 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
654 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
655 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
656 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
657 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
658 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
659 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
660 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
661 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
662 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
663 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
664 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
665 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
666 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
667 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
668 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
669 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
670};
671
672static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
673 unsigned Idx;
674 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
675 if (LdStNInstInfo[Idx].Opcode == Opcode)
676 return &LdStNInstInfo[Idx];
677
678 return nullptr;
679}
680
681void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
682 StringRef Annot,
683 const MCSubtargetInfo &STI) {
684 unsigned Opcode = MI->getOpcode();
685 StringRef Layout, Mnemonic;
686
687 bool IsTbx;
688 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
689 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
690 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
691
692 unsigned ListOpNum = IsTbx ? 2 : 1;
693 printVectorList(MI, ListOpNum, STI, O, "");
694
695 O << ", "
696 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
697 printAnnotation(O, Annot);
698 return;
699 }
700
701 if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
702 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
703
704 // Now onto the operands: first a vector list with possible lane
705 // specifier. E.g. { v0 }[2]
706 int OpNum = LdStDesc->ListOperand;
707 printVectorList(MI, OpNum++, STI, O, "");
708
709 if (LdStDesc->HasLane)
710 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
711
712 // Next the address: [xN]
713 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
714 O << ", [" << getRegisterName(AddrReg) << ']';
715
716 // Finally, there might be a post-indexed offset.
717 if (LdStDesc->NaturalOffset != 0) {
718 unsigned Reg = MI->getOperand(OpNum++).getReg();
719 if (Reg != AArch64::XZR)
720 O << ", " << getRegisterName(Reg);
721 else {
722 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?")((LdStDesc->NaturalOffset && "no offset on post-inc instruction?"
) ? static_cast<void> (0) : __assert_fail ("LdStDesc->NaturalOffset && \"no offset on post-inc instruction?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 722, __PRETTY_FUNCTION__))
;
723 O << ", #" << LdStDesc->NaturalOffset;
724 }
725 }
726
727 printAnnotation(O, Annot);
728 return;
729 }
730
731 AArch64InstPrinter::printInst(MI, O, Annot, STI);
732}
733
734bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
735 const MCSubtargetInfo &STI,
736 raw_ostream &O) {
737#ifndef NDEBUG
738 unsigned Opcode = MI->getOpcode();
739 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!")((Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"
) ? static_cast<void> (0) : __assert_fail ("Opcode == AArch64::SYSxt && \"Invalid opcode for SYS alias!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 739, __PRETTY_FUNCTION__))
;
740#endif
741
742 const MCOperand &Op1 = MI->getOperand(0);
743 const MCOperand &Cn = MI->getOperand(1);
744 const MCOperand &Cm = MI->getOperand(2);
745 const MCOperand &Op2 = MI->getOperand(3);
746
747 unsigned Op1Val = Op1.getImm();
748 unsigned CnVal = Cn.getImm();
749 unsigned CmVal = Cm.getImm();
750 unsigned Op2Val = Op2.getImm();
751
752 uint16_t Encoding = Op2Val;
753 Encoding |= CmVal << 3;
754 Encoding |= CnVal << 7;
755 Encoding |= Op1Val << 11;
756
757 bool NeedsReg;
758 std::string Ins;
759 std::string Name;
760
761 if (CnVal == 7) {
762 switch (CmVal) {
763 default: return false;
764 // IC aliases
765 case 1: case 5: {
766 const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
767 if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
768 return false;
769
770 NeedsReg = IC->NeedsReg;
771 Ins = "ic\t";
772 Name = std::string(IC->Name);
773 }
774 break;
775 // DC aliases
776 case 4: case 6: case 10: case 11: case 12: case 14:
777 {
778 const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
779 if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
780 return false;
781
782 NeedsReg = true;
783 Ins = "dc\t";
784 Name = std::string(DC->Name);
785 }
786 break;
787 // AT aliases
788 case 8: case 9: {
789 const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
790 if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
791 return false;
792
793 NeedsReg = true;
794 Ins = "at\t";
795 Name = std::string(AT->Name);
796 }
797 break;
798 }
799 } else if (CnVal == 8) {
800 // TLBI aliases
801 const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
802 if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
803 return false;
804
805 NeedsReg = TLBI->NeedsReg;
806 Ins = "tlbi\t";
807 Name = std::string(TLBI->Name);
808 }
809 else
810 return false;
811
812 std::string Str = Ins + Name;
813 std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
814
815 O << '\t' << Str;
816 if (NeedsReg)
817 O << ", " << getRegisterName(MI->getOperand(4).getReg());
818
819 return true;
820}
821
822void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
823 const MCSubtargetInfo &STI,
824 raw_ostream &O) {
825 const MCOperand &Op = MI->getOperand(OpNo);
826 if (Op.isReg()) {
827 unsigned Reg = Op.getReg();
828 O << getRegisterName(Reg);
829 } else if (Op.isImm()) {
830 printImm(MI, OpNo, STI, O);
831 } else {
832 assert(Op.isExpr() && "unknown operand kind in printOperand")((Op.isExpr() && "unknown operand kind in printOperand"
) ? static_cast<void> (0) : __assert_fail ("Op.isExpr() && \"unknown operand kind in printOperand\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 832, __PRETTY_FUNCTION__))
;
833 Op.getExpr()->print(O, &MAI);
834 }
835}
836
837void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
838 const MCSubtargetInfo &STI,
839 raw_ostream &O) {
840 const MCOperand &Op = MI->getOperand(OpNo);
841 O << "#" << formatImm(Op.getImm());
842}
843
844void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
845 const MCSubtargetInfo &STI,
846 raw_ostream &O) {
847 const MCOperand &Op = MI->getOperand(OpNo);
848 O << format("#%#llx", Op.getImm());
849}
850
851void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
852 unsigned Imm, raw_ostream &O) {
853 const MCOperand &Op = MI->getOperand(OpNo);
854 if (Op.isReg()) {
855 unsigned Reg = Op.getReg();
856 if (Reg == AArch64::XZR)
857 O << "#" << Imm;
858 else
859 O << getRegisterName(Reg);
860 } else
861 llvm_unreachable("unknown operand kind in printPostIncOperand64")::llvm::llvm_unreachable_internal("unknown operand kind in printPostIncOperand64"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 861)
;
862}
863
864void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
865 const MCSubtargetInfo &STI,
866 raw_ostream &O) {
867 const MCOperand &Op = MI->getOperand(OpNo);
868 assert(Op.isReg() && "Non-register vreg operand!")((Op.isReg() && "Non-register vreg operand!") ? static_cast
<void> (0) : __assert_fail ("Op.isReg() && \"Non-register vreg operand!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 868, __PRETTY_FUNCTION__))
;
869 unsigned Reg = Op.getReg();
870 O << getRegisterName(Reg, AArch64::vreg);
871}
872
873void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
874 const MCSubtargetInfo &STI,
875 raw_ostream &O) {
876 const MCOperand &Op = MI->getOperand(OpNo);
877 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!")((Op.isImm() && "System instruction C[nm] operands must be immediates!"
) ? static_cast<void> (0) : __assert_fail ("Op.isImm() && \"System instruction C[nm] operands must be immediates!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 877, __PRETTY_FUNCTION__))
;
878 O << "c" << Op.getImm();
879}
880
881void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
882 const MCSubtargetInfo &STI,
883 raw_ostream &O) {
884 const MCOperand &MO = MI->getOperand(OpNum);
885 if (MO.isImm()) {
886 unsigned Val = (MO.getImm() & 0xfff);
887 assert(Val == MO.getImm() && "Add/sub immediate out of range!")((Val == MO.getImm() && "Add/sub immediate out of range!"
) ? static_cast<void> (0) : __assert_fail ("Val == MO.getImm() && \"Add/sub immediate out of range!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 887, __PRETTY_FUNCTION__))
;
888 unsigned Shift =
889 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
890 O << '#' << formatImm(Val);
891 if (Shift != 0)
892 printShifter(MI, OpNum + 1, STI, O);
893
894 if (CommentStream)
895 *CommentStream << '=' << formatImm(Val << Shift) << '\n';
896 } else {
897 assert(MO.isExpr() && "Unexpected operand type!")((MO.isExpr() && "Unexpected operand type!") ? static_cast
<void> (0) : __assert_fail ("MO.isExpr() && \"Unexpected operand type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 897, __PRETTY_FUNCTION__))
;
898 MO.getExpr()->print(O, &MAI);
899 printShifter(MI, OpNum + 1, STI, O);
900 }
901}
902
903void AArch64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
904 const MCSubtargetInfo &STI,
905 raw_ostream &O) {
906 uint64_t Val = MI->getOperand(OpNum).getImm();
907 O << "#0x";
908 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 32));
909}
910
911void AArch64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
912 const MCSubtargetInfo &STI,
913 raw_ostream &O) {
914 uint64_t Val = MI->getOperand(OpNum).getImm();
915 O << "#0x";
916 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 64));
917}
918
919void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
920 const MCSubtargetInfo &STI,
921 raw_ostream &O) {
922 unsigned Val = MI->getOperand(OpNum).getImm();
923 // LSL #0 should not be printed.
924 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
925 AArch64_AM::getShiftValue(Val) == 0)
926 return;
927 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
928 << " #" << AArch64_AM::getShiftValue(Val);
929}
930
931void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
932 const MCSubtargetInfo &STI,
933 raw_ostream &O) {
934 O << getRegisterName(MI->getOperand(OpNum).getReg());
935 printShifter(MI, OpNum + 1, STI, O);
936}
937
938void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
939 const MCSubtargetInfo &STI,
940 raw_ostream &O) {
941 O << getRegisterName(MI->getOperand(OpNum).getReg());
942 printArithExtend(MI, OpNum + 1, STI, O);
943}
944
945void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
946 const MCSubtargetInfo &STI,
947 raw_ostream &O) {
948 unsigned Val = MI->getOperand(OpNum).getImm();
949 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
950 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
951
952 // If the destination or first source register operand is [W]SP, print
953 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
954 // all.
955 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
956 unsigned Dest = MI->getOperand(0).getReg();
957 unsigned Src1 = MI->getOperand(1).getReg();
958 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
959 ExtType == AArch64_AM::UXTX) ||
960 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
961 ExtType == AArch64_AM::UXTW) ) {
962 if (ShiftVal != 0)
963 O << ", lsl #" << ShiftVal;
964 return;
965 }
966 }
967 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
968 if (ShiftVal != 0)
969 O << " #" << ShiftVal;
970}
971
972void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
973 raw_ostream &O, char SrcRegKind,
974 unsigned Width) {
975 unsigned SignExtend = MI->getOperand(OpNum).getImm();
976 unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
977
978 // sxtw, sxtx, uxtw or lsl (== uxtx)
979 bool IsLSL = !SignExtend && SrcRegKind == 'x';
980 if (IsLSL)
981 O << "lsl";
982 else
983 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
984
985 if (DoShift || IsLSL)
986 O << " #" << Log2_32(Width / 8);
987}
988
989void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
990 const MCSubtargetInfo &STI,
991 raw_ostream &O) {
992 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
993 O << AArch64CC::getCondCodeName(CC);
994}
995
996void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
997 const MCSubtargetInfo &STI,
998 raw_ostream &O) {
999 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1000 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1001}
1002
1003void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1004 const MCSubtargetInfo &STI,
1005 raw_ostream &O) {
1006 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1007}
1008
1009template<int Scale>
1010void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1011 const MCSubtargetInfo &STI,
1012 raw_ostream &O) {
1013 O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1014}
1015
1016void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1017 unsigned Scale, raw_ostream &O) {
1018 const MCOperand MO = MI->getOperand(OpNum);
1019 if (MO.isImm()) {
1020 O << "#" << formatImm(MO.getImm() * Scale);
1021 } else {
1022 assert(MO.isExpr() && "Unexpected operand type!")((MO.isExpr() && "Unexpected operand type!") ? static_cast
<void> (0) : __assert_fail ("MO.isExpr() && \"Unexpected operand type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 1022, __PRETTY_FUNCTION__))
;
1023 MO.getExpr()->print(O, &MAI);
1024 }
1025}
1026
1027void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1028 unsigned Scale, raw_ostream &O) {
1029 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1030 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1031 if (MO1.isImm()) {
1032 O << ", #" << formatImm(MO1.getImm() * Scale);
1033 } else {
1034 assert(MO1.isExpr() && "Unexpected operand type!")((MO1.isExpr() && "Unexpected operand type!") ? static_cast
<void> (0) : __assert_fail ("MO1.isExpr() && \"Unexpected operand type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 1034, __PRETTY_FUNCTION__))
;
1035 O << ", ";
1036 MO1.getExpr()->print(O, &MAI);
1037 }
1038 O << ']';
1039}
1040
1041void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1042 const MCSubtargetInfo &STI,
1043 raw_ostream &O) {
1044 unsigned prfop = MI->getOperand(OpNum).getImm();
1045 auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop);
1046 if (PRFM)
1047 O << PRFM->Name;
1048 else
1049 O << '#' << formatImm(prfop);
1050}
1051
1052void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1053 const MCSubtargetInfo &STI,
1054 raw_ostream &O) {
1055 unsigned psbhintop = MI->getOperand(OpNum).getImm();
1056 auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1057 if (PSB)
1058 O << PSB->Name;
1059 else
1060 O << '#' << formatImm(psbhintop);
1061}
1062
1063void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1064 const MCSubtargetInfo &STI,
1065 raw_ostream &O) {
1066 const MCOperand &MO = MI->getOperand(OpNum);
1067 float FPImm =
1068 MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
1069
1070 // 8 decimal places are enough to perfectly represent permitted floats.
1071 O << format("#%.8f", FPImm);
1072}
1073
1074static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1075 while (Stride--) {
1076 switch (Reg) {
1077 default:
1078 llvm_unreachable("Vector register expected!")::llvm::llvm_unreachable_internal("Vector register expected!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp"
, 1078)
;
1079 case AArch64::Q0: Reg = AArch64::Q1; break;
1080 case AArch64::Q1: Reg = AArch64::Q2; break;
1081 case AArch64::Q2: Reg = AArch64::Q3; break;
1082 case AArch64::Q3: Reg = AArch64::Q4; break;
1083 case AArch64::Q4: Reg = AArch64::Q5; break;
1084 case AArch64::Q5: Reg = AArch64::Q6; break;
1085 case AArch64::Q6: Reg = AArch64::Q7; break;
1086 case AArch64::Q7: Reg = AArch64::Q8; break;
1087 case AArch64::Q8: Reg = AArch64::Q9; break;
1088 case AArch64::Q9: Reg = AArch64::Q10; break;
1089 case AArch64::Q10: Reg = AArch64::Q11; break;
1090 case AArch64::Q11: Reg = AArch64::Q12; break;
1091 case AArch64::Q12: Reg = AArch64::Q13; break;
1092 case AArch64::Q13: Reg = AArch64::Q14; break;
1093 case AArch64::Q14: Reg = AArch64::Q15; break;
1094 case AArch64::Q15: Reg = AArch64::Q16; break;
1095 case AArch64::Q16: Reg = AArch64::Q17; break;
1096 case AArch64::Q17: Reg = AArch64::Q18; break;
1097 case AArch64::Q18: Reg = AArch64::Q19; break;
1098 case AArch64::Q19: Reg = AArch64::Q20; break;
1099 case AArch64::Q20: Reg = AArch64::Q21; break;
1100 case AArch64::Q21: Reg = AArch64::Q22; break;
1101 case AArch64::Q22: Reg = AArch64::Q23; break;
1102 case AArch64::Q23: Reg = AArch64::Q24; break;
1103 case AArch64::Q24: Reg = AArch64::Q25; break;
1104 case AArch64::Q25: Reg = AArch64::Q26; break;
1105 case AArch64::Q26: Reg = AArch64::Q27; break;
1106 case AArch64::Q27: Reg = AArch64::Q28; break;
1107 case AArch64::Q28: Reg = AArch64::Q29; break;
1108 case AArch64::Q29: Reg = AArch64::Q30; break;
1109 case AArch64::Q30: Reg = AArch64::Q31; break;
1110 // Vector lists can wrap around.
1111 case AArch64::Q31:
1112 Reg = AArch64::Q0;
1113 break;
1114 }
1115 }
1116 return Reg;
1117}
1118
1119template<unsigned size>
1120void AArch64InstPrinter::printGPRSeqPairsClassOperand(const MCInst *MI,
1121 unsigned OpNum,
1122 const MCSubtargetInfo &STI,
1123 raw_ostream &O) {
1124 static_assert(size == 64 || size == 32,
1125 "Template parameter must be either 32 or 64");
1126 unsigned Reg = MI->getOperand(OpNum).getReg();
1127
1128 unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1129 unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1130
1131 unsigned Even = MRI.getSubReg(Reg, Sube);
1132 unsigned Odd = MRI.getSubReg(Reg, Subo);
1133 O << getRegisterName(Even) << ", " << getRegisterName(Odd);
1134}
1135
1136void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1137 const MCSubtargetInfo &STI,
1138 raw_ostream &O,
1139 StringRef LayoutSuffix) {
1140 unsigned Reg = MI->getOperand(OpNum).getReg();
1141
1142 O << "{ ";
1143
1144 // Work out how many registers there are in the list (if there is an actual
1145 // list).
1146 unsigned NumRegs = 1;
1147 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1148 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1149 NumRegs = 2;
1150 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1151 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1152 NumRegs = 3;
1153 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1154 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1155 NumRegs = 4;
1156
1157 // Now forget about the list and find out what the first register is.
1158 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1159 Reg = FirstReg;
1160 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1161 Reg = FirstReg;
1162
1163 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1164 // printing (otherwise getRegisterName fails).
1165 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1166 const MCRegisterClass &FPR128RC =
1167 MRI.getRegClass(AArch64::FPR128RegClassID);
1168 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1169 }
1170
1171 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1172 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1173 if (i + 1 != NumRegs)
1174 O << ", ";
1175 }
1176
1177 O << " }";
1178}
1179
1180void
1181AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1182 unsigned OpNum,
1183 const MCSubtargetInfo &STI,
1184 raw_ostream &O) {
1185 printVectorList(MI, OpNum, STI, O, "");
1186}
1187
1188template <unsigned NumLanes, char LaneKind>
1189void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1190 const MCSubtargetInfo &STI,
1191 raw_ostream &O) {
1192 std::string Suffix(".");
1193 if (NumLanes)
1194 Suffix += itostr(NumLanes) + LaneKind;
1195 else
1196 Suffix += LaneKind;
1197
1198 printVectorList(MI, OpNum, STI, O, Suffix);
1199}
1200
1201void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1202 const MCSubtargetInfo &STI,
1203 raw_ostream &O) {
1204 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1205}
1206
1207void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
1208 const MCSubtargetInfo &STI,
1209 raw_ostream &O) {
1210 const MCOperand &Op = MI->getOperand(OpNum);
1211
1212 // If the label has already been resolved to an immediate offset (say, when
1213 // we're running the disassembler), just print the immediate.
1214 if (Op.isImm()) {
1215 O << "#" << formatImm(Op.getImm() * 4);
1216 return;
1217 }
1218
1219 // If the branch target is simply an address then print it in hex.
1220 const MCConstantExpr *BranchTarget =
1221 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1222 int64_t Address;
1223 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
1224 O << "0x";
1225 O.write_hex(Address);
1226 } else {
1227 // Otherwise, just print the expression.
1228 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1229 }
1230}
1231
1232void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1233 const MCSubtargetInfo &STI,
1234 raw_ostream &O) {
1235 const MCOperand &Op = MI->getOperand(OpNum);
1236
1237 // If the label has already been resolved to an immediate offset (say, when
1238 // we're running the disassembler), just print the immediate.
1239 if (Op.isImm()) {
1240 O << "#" << formatImm(Op.getImm() * (1 << 12));
1241 return;
1242 }
1243
1244 // Otherwise, just print the expression.
1245 MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1246}
1247
1248void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1249 const MCSubtargetInfo &STI,
1250 raw_ostream &O) {
1251 unsigned Val = MI->getOperand(OpNo).getImm();
1252 unsigned Opcode = MI->getOpcode();
1253
1254 StringRef Name;
1255 if (Opcode == AArch64::ISB) {
1256 auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1257 Name = ISB ? ISB->Name : "";
1258 } else {
1259 auto DB = AArch64DB::lookupDBByEncoding(Val);
1260 Name = DB ? DB->Name : "";
1261 }
1262 if (!Name.empty())
1263 O << Name;
1264 else
1265 O << "#" << Val;
1266}
1267
1268void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1269 const MCSubtargetInfo &STI,
1270 raw_ostream &O) {
1271 unsigned Val = MI->getOperand(OpNo).getImm();
1272
1273 // Horrible hack for the one register that has identical encodings but
1274 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1275 // going to get the wrong entry
1276 if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1277 O << "DBGDTRRX_EL0";
1278 return;
1279 }
1280
1281 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1282 if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
1283 O << Reg->Name;
1284 else
1285 O << AArch64SysReg::genericRegisterString(Val);
1286}
1287
1288void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1289 const MCSubtargetInfo &STI,
1290 raw_ostream &O) {
1291 unsigned Val = MI->getOperand(OpNo).getImm();
1292
1293 // Horrible hack for the one register that has identical encodings but
1294 // different names in MSR and MRS. Because of this, one of MRS and MSR is
1295 // going to get the wrong entry
1296 if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1297 O << "DBGDTRTX_EL0";
1298 return;
1299 }
1300
1301 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val);
1302 if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
1303 O << Reg->Name;
1304 else
1305 O << AArch64SysReg::genericRegisterString(Val);
1306}
1307
1308void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1309 const MCSubtargetInfo &STI,
1310 raw_ostream &O) {
1311 unsigned Val = MI->getOperand(OpNo).getImm();
1312
1313 auto PState = AArch64PState::lookupPStateByEncoding(Val);
1314 if (PState && PState->haveFeatures(STI.getFeatureBits()))
1315 O << PState->Name;
1316 else
1317 O << "#" << formatImm(Val);
1318}
1319
1320void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1321 const MCSubtargetInfo &STI,
1322 raw_ostream &O) {
1323 unsigned RawVal = MI->getOperand(OpNo).getImm();
1324 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1325 O << format("#%#016llx", Val);
1326}