Bug Summary

File:lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
Warning:line 2072, column 7
5th function call argument is an uninitialized value

Annotated Source Code

1//===- AMDGPUMachineCFGStructurizer.cpp - Machine code if conversion pass. ===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the machine instruction level CFG structurizer pass.
11//
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPU.h"
15#include "AMDGPUSubtarget.h"
16#include "SIInstrInfo.h"
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/DenseSet.h"
20#include "llvm/ADT/PostOrderIterator.h"
21#include "llvm/ADT/SetVector.h"
22#include "llvm/ADT/SmallPtrSet.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineOperand.h"
30#include "llvm/CodeGen/MachineRegionInfo.h"
31#include "llvm/CodeGen/MachineRegisterInfo.h"
32#include "llvm/IR/DebugLoc.h"
33#include "llvm/Pass.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#include "llvm/Target/TargetOpcodes.h"
39#include "llvm/Target/TargetRegisterInfo.h"
40#include <cassert>
41#include <tuple>
42#include <utility>
43
44using namespace llvm;
45
46#define DEBUG_TYPE"amdgpucfgstructurizer" "amdgpucfgstructurizer"
47
48namespace {
49
50class PHILinearizeDestIterator;
51
52class PHILinearize {
53 friend class PHILinearizeDestIterator;
54
55public:
56 using PHISourceT = std::pair<unsigned, MachineBasicBlock *>;
57
58private:
59 using PHISourcesT = DenseSet<PHISourceT>;
60 using PHIInfoElementT = struct {
61 unsigned DestReg;
62 DebugLoc DL;
63 PHISourcesT Sources;
64 };
65 using PHIInfoT = SmallPtrSet<PHIInfoElementT *, 2>;
66 PHIInfoT PHIInfo;
67
68 static unsigned phiInfoElementGetDest(PHIInfoElementT *Info);
69 static void phiInfoElementSetDef(PHIInfoElementT *Info, unsigned NewDef);
70 static PHISourcesT &phiInfoElementGetSources(PHIInfoElementT *Info);
71 static void phiInfoElementAddSource(PHIInfoElementT *Info, unsigned SourceReg,
72 MachineBasicBlock *SourceMBB);
73 static void phiInfoElementRemoveSource(PHIInfoElementT *Info,
74 unsigned SourceReg,
75 MachineBasicBlock *SourceMBB);
76 PHIInfoElementT *findPHIInfoElement(unsigned DestReg);
77 PHIInfoElementT *findPHIInfoElementFromSource(unsigned SourceReg,
78 MachineBasicBlock *SourceMBB);
79
80public:
81 bool findSourcesFromMBB(MachineBasicBlock *SourceMBB,
82 SmallVector<unsigned, 4> &Sources);
83 void addDest(unsigned DestReg, const DebugLoc &DL);
84 void replaceDef(unsigned OldDestReg, unsigned NewDestReg);
85 void deleteDef(unsigned DestReg);
86 void addSource(unsigned DestReg, unsigned SourceReg,
87 MachineBasicBlock *SourceMBB);
88 void removeSource(unsigned DestReg, unsigned SourceReg,
89 MachineBasicBlock *SourceMBB = nullptr);
90 bool findDest(unsigned SourceReg, MachineBasicBlock *SourceMBB,
91 unsigned &DestReg);
92 bool isSource(unsigned Reg, MachineBasicBlock *SourceMBB = nullptr);
93 unsigned getNumSources(unsigned DestReg);
94 void dump(MachineRegisterInfo *MRI);
95 void clear();
96
97 using source_iterator = PHISourcesT::iterator;
98 using dest_iterator = PHILinearizeDestIterator;
99
100 dest_iterator dests_begin();
101 dest_iterator dests_end();
102
103 source_iterator sources_begin(unsigned Reg);
104 source_iterator sources_end(unsigned Reg);
105};
106
107class PHILinearizeDestIterator {
108private:
109 PHILinearize::PHIInfoT::iterator Iter;
110
111public:
112 PHILinearizeDestIterator(PHILinearize::PHIInfoT::iterator I) : Iter(I) {}
113
114 unsigned operator*() { return PHILinearize::phiInfoElementGetDest(*Iter); }
115 PHILinearizeDestIterator &operator++() {
116 ++Iter;
117 return *this;
118 }
119 bool operator==(const PHILinearizeDestIterator &I) const {
120 return I.Iter == Iter;
121 }
122 bool operator!=(const PHILinearizeDestIterator &I) const {
123 return I.Iter != Iter;
124 }
125};
126
127} // end anonymous namespace
128
129unsigned PHILinearize::phiInfoElementGetDest(PHIInfoElementT *Info) {
130 return Info->DestReg;
131}
132
133void PHILinearize::phiInfoElementSetDef(PHIInfoElementT *Info,
134 unsigned NewDef) {
135 Info->DestReg = NewDef;
136}
137
138PHILinearize::PHISourcesT &
139PHILinearize::phiInfoElementGetSources(PHIInfoElementT *Info) {
140 return Info->Sources;
141}
142
143void PHILinearize::phiInfoElementAddSource(PHIInfoElementT *Info,
144 unsigned SourceReg,
145 MachineBasicBlock *SourceMBB) {
146 // Assertion ensures we don't use the same SourceMBB for the
147 // sources, because we cannot have different registers with
148 // identical predecessors, but we can have the same register for
149 // multiple predecessors.
150#if !defined(NDEBUG)
151 for (auto SI : phiInfoElementGetSources(Info)) {
152 assert((SI.second != SourceMBB || SourceReg == SI.first))(((SI.second != SourceMBB || SourceReg == SI.first)) ? static_cast
<void> (0) : __assert_fail ("(SI.second != SourceMBB || SourceReg == SI.first)"
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 152, __PRETTY_FUNCTION__))
;
153 }
154#endif
155
156 phiInfoElementGetSources(Info).insert(PHISourceT(SourceReg, SourceMBB));
157}
158
159void PHILinearize::phiInfoElementRemoveSource(PHIInfoElementT *Info,
160 unsigned SourceReg,
161 MachineBasicBlock *SourceMBB) {
162 auto &Sources = phiInfoElementGetSources(Info);
163 SmallVector<PHISourceT, 4> ElimiatedSources;
164 for (auto SI : Sources) {
165 if (SI.first == SourceReg &&
166 (SI.second == nullptr || SI.second == SourceMBB)) {
167 ElimiatedSources.push_back(PHISourceT(SI.first, SI.second));
168 }
169 }
170
171 for (auto &Source : ElimiatedSources) {
172 Sources.erase(Source);
173 }
174}
175
176PHILinearize::PHIInfoElementT *
177PHILinearize::findPHIInfoElement(unsigned DestReg) {
178 for (auto I : PHIInfo) {
179 if (phiInfoElementGetDest(I) == DestReg) {
180 return I;
181 }
182 }
183 return nullptr;
184}
185
186PHILinearize::PHIInfoElementT *
187PHILinearize::findPHIInfoElementFromSource(unsigned SourceReg,
188 MachineBasicBlock *SourceMBB) {
189 for (auto I : PHIInfo) {
190 for (auto SI : phiInfoElementGetSources(I)) {
191 if (SI.first == SourceReg &&
192 (SI.second == nullptr || SI.second == SourceMBB)) {
193 return I;
194 }
195 }
196 }
197 return nullptr;
198}
199
200bool PHILinearize::findSourcesFromMBB(MachineBasicBlock *SourceMBB,
201 SmallVector<unsigned, 4> &Sources) {
202 bool FoundSource = false;
203 for (auto I : PHIInfo) {
204 for (auto SI : phiInfoElementGetSources(I)) {
205 if (SI.second == SourceMBB) {
206 FoundSource = true;
207 Sources.push_back(SI.first);
208 }
209 }
210 }
211 return FoundSource;
212}
213
214void PHILinearize::addDest(unsigned DestReg, const DebugLoc &DL) {
215 assert(findPHIInfoElement(DestReg) == nullptr && "Dest already exsists")((findPHIInfoElement(DestReg) == nullptr && "Dest already exsists"
) ? static_cast<void> (0) : __assert_fail ("findPHIInfoElement(DestReg) == nullptr && \"Dest already exsists\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 215, __PRETTY_FUNCTION__))
;
216 PHISourcesT EmptySet;
217 PHIInfoElementT *NewElement = new PHIInfoElementT();
218 NewElement->DestReg = DestReg;
219 NewElement->DL = DL;
220 NewElement->Sources = EmptySet;
221 PHIInfo.insert(NewElement);
222}
223
224void PHILinearize::replaceDef(unsigned OldDestReg, unsigned NewDestReg) {
225 phiInfoElementSetDef(findPHIInfoElement(OldDestReg), NewDestReg);
226}
227
228void PHILinearize::deleteDef(unsigned DestReg) {
229 PHIInfoElementT *InfoElement = findPHIInfoElement(DestReg);
230 PHIInfo.erase(InfoElement);
231 delete InfoElement;
232}
233
234void PHILinearize::addSource(unsigned DestReg, unsigned SourceReg,
235 MachineBasicBlock *SourceMBB) {
236 phiInfoElementAddSource(findPHIInfoElement(DestReg), SourceReg, SourceMBB);
237}
238
239void PHILinearize::removeSource(unsigned DestReg, unsigned SourceReg,
240 MachineBasicBlock *SourceMBB) {
241 phiInfoElementRemoveSource(findPHIInfoElement(DestReg), SourceReg, SourceMBB);
242}
243
244bool PHILinearize::findDest(unsigned SourceReg, MachineBasicBlock *SourceMBB,
245 unsigned &DestReg) {
246 PHIInfoElementT *InfoElement =
247 findPHIInfoElementFromSource(SourceReg, SourceMBB);
248 if (InfoElement != nullptr) {
11
Assuming the condition is false
12
Taking false branch
249 DestReg = phiInfoElementGetDest(InfoElement);
250 return true;
251 }
252 return false;
253}
254
255bool PHILinearize::isSource(unsigned Reg, MachineBasicBlock *SourceMBB) {
256 unsigned DestReg;
257 return findDest(Reg, SourceMBB, DestReg);
258}
259
260unsigned PHILinearize::getNumSources(unsigned DestReg) {
261 return phiInfoElementGetSources(findPHIInfoElement(DestReg)).size();
262}
263
264#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
265LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void PHILinearize::dump(MachineRegisterInfo *MRI) {
266 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
267 dbgs() << "=PHIInfo Start=\n";
268 for (auto PII : this->PHIInfo) {
269 PHIInfoElementT &Element = *PII;
270 dbgs() << "Dest: " << PrintReg(Element.DestReg, TRI)
271 << " Sources: {";
272 for (auto &SI : Element.Sources) {
273 dbgs() << PrintReg(SI.first, TRI) << "(BB#"
274 << SI.second->getNumber() << "),";
275 }
276 dbgs() << "}\n";
277 }
278 dbgs() << "=PHIInfo End=\n";
279}
280#endif
281
282void PHILinearize::clear() { PHIInfo = PHIInfoT(); }
283
284PHILinearize::dest_iterator PHILinearize::dests_begin() {
285 return PHILinearizeDestIterator(PHIInfo.begin());
286}
287
288PHILinearize::dest_iterator PHILinearize::dests_end() {
289 return PHILinearizeDestIterator(PHIInfo.end());
290}
291
292PHILinearize::source_iterator PHILinearize::sources_begin(unsigned Reg) {
293 auto InfoElement = findPHIInfoElement(Reg);
294 return phiInfoElementGetSources(InfoElement).begin();
295}
296
297PHILinearize::source_iterator PHILinearize::sources_end(unsigned Reg) {
298 auto InfoElement = findPHIInfoElement(Reg);
299 return phiInfoElementGetSources(InfoElement).end();
300}
301
302static unsigned getPHINumInputs(MachineInstr &PHI) {
303 assert(PHI.isPHI())((PHI.isPHI()) ? static_cast<void> (0) : __assert_fail (
"PHI.isPHI()", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 303, __PRETTY_FUNCTION__))
;
304 return (PHI.getNumOperands() - 1) / 2;
305}
306
307static MachineBasicBlock *getPHIPred(MachineInstr &PHI, unsigned Index) {
308 assert(PHI.isPHI())((PHI.isPHI()) ? static_cast<void> (0) : __assert_fail (
"PHI.isPHI()", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 308, __PRETTY_FUNCTION__))
;
309 return PHI.getOperand(Index * 2 + 2).getMBB();
310}
311
312static void setPhiPred(MachineInstr &PHI, unsigned Index,
313 MachineBasicBlock *NewPred) {
314 PHI.getOperand(Index * 2 + 2).setMBB(NewPred);
315}
316
317static unsigned getPHISourceReg(MachineInstr &PHI, unsigned Index) {
318 assert(PHI.isPHI())((PHI.isPHI()) ? static_cast<void> (0) : __assert_fail (
"PHI.isPHI()", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 318, __PRETTY_FUNCTION__))
;
319 return PHI.getOperand(Index * 2 + 1).getReg();
320}
321
322static unsigned getPHIDestReg(MachineInstr &PHI) {
323 assert(PHI.isPHI())((PHI.isPHI()) ? static_cast<void> (0) : __assert_fail (
"PHI.isPHI()", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 323, __PRETTY_FUNCTION__))
;
324 return PHI.getOperand(0).getReg();
325}
326
327namespace {
328
329class RegionMRT;
330class MBBMRT;
331
332class LinearizedRegion {
333protected:
334 MachineBasicBlock *Entry;
335 // The exit block is part of the region, and is the last
336 // merge block before exiting the region.
337 MachineBasicBlock *Exit;
338 DenseSet<unsigned> LiveOuts;
339 SmallPtrSet<MachineBasicBlock *, 1> MBBs;
340 bool HasLoop;
341 LinearizedRegion *Parent;
342 RegionMRT *RMRT;
343
344 void storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg,
345 MachineInstr *DefInstr, const MachineRegisterInfo *MRI,
346 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
347
348 void storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg,
349 MachineInstr *DefInstr,
350 const MachineRegisterInfo *MRI,
351 const TargetRegisterInfo *TRI,
352 PHILinearize &PHIInfo);
353
354 void storeMBBLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
355 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo,
356 RegionMRT *TopRegion);
357
358 void storeLiveOuts(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
359 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
360
361 void storeLiveOuts(RegionMRT *Region, const MachineRegisterInfo *MRI,
362 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo,
363 RegionMRT *TopRegion = nullptr);
364
365public:
366 LinearizedRegion();
367 LinearizedRegion(MachineBasicBlock *MBB, const MachineRegisterInfo *MRI,
368 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
369 ~LinearizedRegion() = default;
370
371 void setRegionMRT(RegionMRT *Region) { RMRT = Region; }
372
373 RegionMRT *getRegionMRT() { return RMRT; }
374
375 void setParent(LinearizedRegion *P) { Parent = P; }
376
377 LinearizedRegion *getParent() { return Parent; }
378
379 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr);
380
381 void setBBSelectRegIn(unsigned Reg);
382
383 unsigned getBBSelectRegIn();
384
385 void setBBSelectRegOut(unsigned Reg, bool IsLiveOut);
386
387 unsigned getBBSelectRegOut();
388
389 void setHasLoop(bool Value);
390
391 bool getHasLoop();
392
393 void addLiveOut(unsigned VReg);
394
395 void removeLiveOut(unsigned Reg);
396
397 void replaceLiveOut(unsigned OldReg, unsigned NewReg);
398
399 void replaceRegister(unsigned Register, unsigned NewRegister,
400 MachineRegisterInfo *MRI, bool ReplaceInside,
401 bool ReplaceOutside, bool IncludeLoopPHIs);
402
403 void replaceRegisterInsideRegion(unsigned Register, unsigned NewRegister,
404 bool IncludeLoopPHIs,
405 MachineRegisterInfo *MRI);
406
407 void replaceRegisterOutsideRegion(unsigned Register, unsigned NewRegister,
408 bool IncludeLoopPHIs,
409 MachineRegisterInfo *MRI);
410
411 DenseSet<unsigned> *getLiveOuts();
412
413 void setEntry(MachineBasicBlock *NewEntry);
414
415 MachineBasicBlock *getEntry();
416
417 void setExit(MachineBasicBlock *NewExit);
418
419 MachineBasicBlock *getExit();
420
421 void addMBB(MachineBasicBlock *MBB);
422
423 void addMBBs(LinearizedRegion *InnerRegion);
424
425 bool contains(MachineBasicBlock *MBB);
426
427 bool isLiveOut(unsigned Reg);
428
429 bool hasNoDef(unsigned Reg, MachineRegisterInfo *MRI);
430
431 void removeFalseRegisterKills(MachineRegisterInfo *MRI);
432
433 void initLiveOut(RegionMRT *Region, const MachineRegisterInfo *MRI,
434 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
435};
436
437class MRT {
438protected:
439 RegionMRT *Parent;
440 unsigned BBSelectRegIn;
441 unsigned BBSelectRegOut;
442
443public:
444 virtual ~MRT() = default;
445
446 unsigned getBBSelectRegIn() { return BBSelectRegIn; }
447
448 unsigned getBBSelectRegOut() { return BBSelectRegOut; }
449
450 void setBBSelectRegIn(unsigned Reg) { BBSelectRegIn = Reg; }
451
452 void setBBSelectRegOut(unsigned Reg) { BBSelectRegOut = Reg; }
453
454 virtual RegionMRT *getRegionMRT() { return nullptr; }
455
456 virtual MBBMRT *getMBBMRT() { return nullptr; }
457
458 bool isRegion() { return getRegionMRT() != nullptr; }
459
460 bool isMBB() { return getMBBMRT() != nullptr; }
461
462 bool isRoot() { return Parent == nullptr; }
463
464 void setParent(RegionMRT *Region) { Parent = Region; }
465
466 RegionMRT *getParent() { return Parent; }
467
468 static MachineBasicBlock *
469 initializeMRT(MachineFunction &MF, const MachineRegionInfo *RegionInfo,
470 DenseMap<MachineRegion *, RegionMRT *> &RegionMap);
471
472 static RegionMRT *buildMRT(MachineFunction &MF,
473 const MachineRegionInfo *RegionInfo,
474 const SIInstrInfo *TII,
475 MachineRegisterInfo *MRI);
476
477 virtual void dump(const TargetRegisterInfo *TRI, int depth = 0) = 0;
478
479 void dumpDepth(int depth) {
480 for (int i = depth; i > 0; --i) {
481 dbgs() << " ";
482 }
483 }
484};
485
486class MBBMRT : public MRT {
487 MachineBasicBlock *MBB;
488
489public:
490 MBBMRT(MachineBasicBlock *BB) : MBB(BB) {
491 setParent(nullptr);
492 setBBSelectRegOut(0);
493 setBBSelectRegIn(0);
494 }
495
496 MBBMRT *getMBBMRT() override { return this; }
497
498 MachineBasicBlock *getMBB() { return MBB; }
499
500 void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
501 dumpDepth(depth);
502 dbgs() << "MBB: " << getMBB()->getNumber();
503 dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI);
504 dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n";
505 }
506};
507
508class RegionMRT : public MRT {
509protected:
510 MachineRegion *Region;
511 LinearizedRegion *LRegion = nullptr;
512 MachineBasicBlock *Succ = nullptr;
513 SetVector<MRT *> Children;
514
515public:
516 RegionMRT(MachineRegion *MachineRegion) : Region(MachineRegion) {
517 setParent(nullptr);
518 setBBSelectRegOut(0);
519 setBBSelectRegIn(0);
520 }
521
522 ~RegionMRT() override {
523 if (LRegion) {
524 delete LRegion;
525 }
526
527 for (auto CI : Children) {
528 delete &(*CI);
529 }
530 }
531
532 RegionMRT *getRegionMRT() override { return this; }
533
534 void setLinearizedRegion(LinearizedRegion *LinearizeRegion) {
535 LRegion = LinearizeRegion;
536 }
537
538 LinearizedRegion *getLinearizedRegion() { return LRegion; }
539
540 MachineRegion *getMachineRegion() { return Region; }
541
542 unsigned getInnerOutputRegister() {
543 return (*(Children.begin()))->getBBSelectRegOut();
544 }
545
546 void addChild(MRT *Tree) { Children.insert(Tree); }
547
548 SetVector<MRT *> *getChildren() { return &Children; }
549
550 void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
551 dumpDepth(depth);
552 dbgs() << "Region: " << (void *)Region;
553 dbgs() << " In: " << PrintReg(getBBSelectRegIn(), TRI);
554 dbgs() << ", Out: " << PrintReg(getBBSelectRegOut(), TRI) << "\n";
555
556 dumpDepth(depth);
557 if (getSucc())
558 dbgs() << "Succ: " << getSucc()->getNumber() << "\n";
559 else
560 dbgs() << "Succ: none \n";
561 for (auto MRTI : Children) {
562 MRTI->dump(TRI, depth + 1);
563 }
564 }
565
566 MRT *getEntryTree() { return Children.back(); }
567
568 MRT *getExitTree() { return Children.front(); }
569
570 MachineBasicBlock *getEntry() {
571 MRT *Tree = Children.back();
572 return (Tree->isRegion()) ? Tree->getRegionMRT()->getEntry()
573 : Tree->getMBBMRT()->getMBB();
574 }
575
576 MachineBasicBlock *getExit() {
577 MRT *Tree = Children.front();
578 return (Tree->isRegion()) ? Tree->getRegionMRT()->getExit()
579 : Tree->getMBBMRT()->getMBB();
580 }
581
582 void setSucc(MachineBasicBlock *MBB) { Succ = MBB; }
583
584 MachineBasicBlock *getSucc() { return Succ; }
585
586 bool contains(MachineBasicBlock *MBB) {
587 for (auto CI : Children) {
588 if (CI->isMBB()) {
589 if (MBB == CI->getMBBMRT()->getMBB()) {
590 return true;
591 }
592 } else {
593 if (CI->getRegionMRT()->contains(MBB)) {
594 return true;
595 } else if (CI->getRegionMRT()->getLinearizedRegion() != nullptr &&
596 CI->getRegionMRT()->getLinearizedRegion()->contains(MBB)) {
597 return true;
598 }
599 }
600 }
601 return false;
602 }
603
604 void replaceLiveOutReg(unsigned Register, unsigned NewRegister) {
605 LinearizedRegion *LRegion = getLinearizedRegion();
606 LRegion->replaceLiveOut(Register, NewRegister);
607 for (auto &CI : Children) {
608 if (CI->isRegion()) {
609 CI->getRegionMRT()->replaceLiveOutReg(Register, NewRegister);
610 }
611 }
612 }
613};
614
615} // end anonymous namespace
616
617static unsigned createBBSelectReg(const SIInstrInfo *TII,
618 MachineRegisterInfo *MRI) {
619 return MRI->createVirtualRegister(TII->getPreferredSelectRegClass(32));
620}
621
622MachineBasicBlock *
623MRT::initializeMRT(MachineFunction &MF, const MachineRegionInfo *RegionInfo,
624 DenseMap<MachineRegion *, RegionMRT *> &RegionMap) {
625 for (auto &MFI : MF) {
626 MachineBasicBlock *ExitMBB = &MFI;
627 if (ExitMBB->succ_size() == 0) {
628 return ExitMBB;
629 }
630 }
631 llvm_unreachable("CFG has no exit block")::llvm::llvm_unreachable_internal("CFG has no exit block", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 631)
;
632 return nullptr;
633}
634
635RegionMRT *MRT::buildMRT(MachineFunction &MF,
636 const MachineRegionInfo *RegionInfo,
637 const SIInstrInfo *TII, MachineRegisterInfo *MRI) {
638 SmallPtrSet<MachineRegion *, 4> PlacedRegions;
639 DenseMap<MachineRegion *, RegionMRT *> RegionMap;
640 MachineRegion *TopLevelRegion = RegionInfo->getTopLevelRegion();
641 RegionMRT *Result = new RegionMRT(TopLevelRegion);
642 RegionMap[TopLevelRegion] = Result;
643
644 // Insert the exit block first, we need it to be the merge node
645 // for the top level region.
646 MachineBasicBlock *Exit = initializeMRT(MF, RegionInfo, RegionMap);
647
648 unsigned BBSelectRegIn = createBBSelectReg(TII, MRI);
649 MBBMRT *ExitMRT = new MBBMRT(Exit);
650 RegionMap[RegionInfo->getRegionFor(Exit)]->addChild(ExitMRT);
651 ExitMRT->setBBSelectRegIn(BBSelectRegIn);
652
653 for (auto MBBI : post_order(&(MF.front()))) {
654 MachineBasicBlock *MBB = &(*MBBI);
655
656 // Skip Exit since we already added it
657 if (MBB == Exit) {
658 continue;
659 }
660
661 DEBUG(dbgs() << "Visiting BB#" << MBB->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Visiting BB#" <<
MBB->getNumber() << "\n"; } } while (false)
;
662 MBBMRT *NewMBB = new MBBMRT(MBB);
663 MachineRegion *Region = RegionInfo->getRegionFor(MBB);
664
665 // Ensure we have the MRT region
666 if (RegionMap.count(Region) == 0) {
667 RegionMRT *NewMRTRegion = new RegionMRT(Region);
668 RegionMap[Region] = NewMRTRegion;
669
670 // Ensure all parents are in the RegionMap
671 MachineRegion *Parent = Region->getParent();
672 while (RegionMap.count(Parent) == 0) {
673 RegionMRT *NewMRTParent = new RegionMRT(Parent);
674 NewMRTParent->addChild(NewMRTRegion);
675 NewMRTRegion->setParent(NewMRTParent);
676 RegionMap[Parent] = NewMRTParent;
677 NewMRTRegion = NewMRTParent;
678 Parent = Parent->getParent();
679 }
680 RegionMap[Parent]->addChild(NewMRTRegion);
681 NewMRTRegion->setParent(RegionMap[Parent]);
682 }
683
684 // Add MBB to Region MRT
685 RegionMap[Region]->addChild(NewMBB);
686 NewMBB->setParent(RegionMap[Region]);
687 RegionMap[Region]->setSucc(Region->getExit());
688 }
689 return Result;
690}
691
692void LinearizedRegion::storeLiveOutReg(MachineBasicBlock *MBB, unsigned Reg,
693 MachineInstr *DefInstr,
694 const MachineRegisterInfo *MRI,
695 const TargetRegisterInfo *TRI,
696 PHILinearize &PHIInfo) {
697 if (TRI->isVirtualRegister(Reg)) {
698 DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Considering Register: "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
;
699 // If this is a source register to a PHI we are chaining, it
700 // must be live out.
701 if (PHIInfo.isSource(Reg)) {
702 DEBUG(dbgs() << "Add LiveOut (PHI): " << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (PHI): "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
;
703 addLiveOut(Reg);
704 } else {
705 // If this is live out of the MBB
706 for (auto &UI : MRI->use_operands(Reg)) {
707 if (UI.getParent()->getParent() != MBB) {
708 DEBUG(dbgs() << "Add LiveOut (MBB BB#" << MBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (MBB BB#"
<< MBB->getNumber() << "): " << PrintReg
(Reg, TRI) << "\n"; } } while (false)
709 << "): " << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (MBB BB#"
<< MBB->getNumber() << "): " << PrintReg
(Reg, TRI) << "\n"; } } while (false)
;
710 addLiveOut(Reg);
711 } else {
712 // If the use is in the same MBB we have to make sure
713 // it is after the def, otherwise it is live out in a loop
714 MachineInstr *UseInstr = UI.getParent();
715 for (MachineBasicBlock::instr_iterator
716 MII = UseInstr->getIterator(),
717 MIE = UseInstr->getParent()->instr_end();
718 MII != MIE; ++MII) {
719 if ((&(*MII)) == DefInstr) {
720 DEBUG(dbgs() << "Add LiveOut (Loop): " << PrintReg(Reg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (Loop): "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
721 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (Loop): "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
;
722 addLiveOut(Reg);
723 }
724 }
725 }
726 }
727 }
728 }
729}
730
731void LinearizedRegion::storeLiveOutRegRegion(RegionMRT *Region, unsigned Reg,
732 MachineInstr *DefInstr,
733 const MachineRegisterInfo *MRI,
734 const TargetRegisterInfo *TRI,
735 PHILinearize &PHIInfo) {
736 if (TRI->isVirtualRegister(Reg)) {
737 DEBUG(dbgs() << "Considering Register: " << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Considering Register: "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
;
738 for (auto &UI : MRI->use_operands(Reg)) {
739 if (!Region->contains(UI.getParent()->getParent())) {
740 DEBUG(dbgs() << "Add LiveOut (Region " << (void *)Regiondo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (Region "
<< (void *)Region << "): " << PrintReg(Reg
, TRI) << "\n"; } } while (false)
741 << "): " << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (Region "
<< (void *)Region << "): " << PrintReg(Reg
, TRI) << "\n"; } } while (false)
;
742 addLiveOut(Reg);
743 }
744 }
745 }
746}
747
748void LinearizedRegion::storeLiveOuts(MachineBasicBlock *MBB,
749 const MachineRegisterInfo *MRI,
750 const TargetRegisterInfo *TRI,
751 PHILinearize &PHIInfo) {
752 DEBUG(dbgs() << "-Store Live Outs Begin (BB#" << MBB->getNumber() << ")-\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "-Store Live Outs Begin (BB#"
<< MBB->getNumber() << ")-\n"; } } while (false
)
;
753 for (auto &II : *MBB) {
754 for (auto &RI : II.defs()) {
755 storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo);
756 }
757 for (auto &IRI : II.implicit_operands()) {
758 if (IRI.isDef()) {
759 storeLiveOutReg(MBB, IRI.getReg(), IRI.getParent(), MRI, TRI, PHIInfo);
760 }
761 }
762 }
763
764 // If we have a successor with a PHI, source coming from this MBB we have to
765 // add the register as live out
766 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
767 E = MBB->succ_end();
768 SI != E; ++SI) {
769 for (auto &II : *(*SI)) {
770 if (II.isPHI()) {
771 MachineInstr &PHI = II;
772 int numPreds = getPHINumInputs(PHI);
773 for (int i = 0; i < numPreds; ++i) {
774 if (getPHIPred(PHI, i) == MBB) {
775 unsigned PHIReg = getPHISourceReg(PHI, i);
776 DEBUG(dbgs() << "Add LiveOut (PhiSource BB#" << MBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (PhiSource BB#"
<< MBB->getNumber() << " -> BB#" << (
*SI)->getNumber() << "): " << PrintReg(PHIReg,
TRI) << "\n"; } } while (false)
777 << " -> BB#" << (*SI)->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (PhiSource BB#"
<< MBB->getNumber() << " -> BB#" << (
*SI)->getNumber() << "): " << PrintReg(PHIReg,
TRI) << "\n"; } } while (false)
778 << "): " << PrintReg(PHIReg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (PhiSource BB#"
<< MBB->getNumber() << " -> BB#" << (
*SI)->getNumber() << "): " << PrintReg(PHIReg,
TRI) << "\n"; } } while (false)
;
779 addLiveOut(PHIReg);
780 }
781 }
782 }
783 }
784 }
785
786 DEBUG(dbgs() << "-Store Live Outs Endn-\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "-Store Live Outs Endn-\n"
; } } while (false)
;
787}
788
789void LinearizedRegion::storeMBBLiveOuts(MachineBasicBlock *MBB,
790 const MachineRegisterInfo *MRI,
791 const TargetRegisterInfo *TRI,
792 PHILinearize &PHIInfo,
793 RegionMRT *TopRegion) {
794 for (auto &II : *MBB) {
795 for (auto &RI : II.defs()) {
796 storeLiveOutRegRegion(TopRegion, RI.getReg(), RI.getParent(), MRI, TRI,
797 PHIInfo);
798 }
799 for (auto &IRI : II.implicit_operands()) {
800 if (IRI.isDef()) {
801 storeLiveOutRegRegion(TopRegion, IRI.getReg(), IRI.getParent(), MRI,
802 TRI, PHIInfo);
803 }
804 }
805 }
806}
807
808void LinearizedRegion::storeLiveOuts(RegionMRT *Region,
809 const MachineRegisterInfo *MRI,
810 const TargetRegisterInfo *TRI,
811 PHILinearize &PHIInfo,
812 RegionMRT *CurrentTopRegion) {
813 MachineBasicBlock *Exit = Region->getSucc();
814
815 RegionMRT *TopRegion =
816 CurrentTopRegion == nullptr ? Region : CurrentTopRegion;
817
818 // Check if exit is end of function, if so, no live outs.
819 if (Exit == nullptr)
820 return;
821
822 auto Children = Region->getChildren();
823 for (auto CI : *Children) {
824 if (CI->isMBB()) {
825 auto MBB = CI->getMBBMRT()->getMBB();
826 storeMBBLiveOuts(MBB, MRI, TRI, PHIInfo, TopRegion);
827 } else {
828 LinearizedRegion *SubRegion = CI->getRegionMRT()->getLinearizedRegion();
829 // We should be limited to only store registers that are live out from the
830 // lineaized region
831 for (auto MBBI : SubRegion->MBBs) {
832 storeMBBLiveOuts(MBBI, MRI, TRI, PHIInfo, TopRegion);
833 }
834 }
835 }
836
837 if (CurrentTopRegion == nullptr) {
838 auto Succ = Region->getSucc();
839 for (auto &II : *Succ) {
840 if (II.isPHI()) {
841 MachineInstr &PHI = II;
842 int numPreds = getPHINumInputs(PHI);
843 for (int i = 0; i < numPreds; ++i) {
844 if (Region->contains(getPHIPred(PHI, i))) {
845 unsigned PHIReg = getPHISourceReg(PHI, i);
846 DEBUG(dbgs() << "Add Region LiveOut (" << (void *)Regiondo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add Region LiveOut ("
<< (void *)Region << "): " << PrintReg(PHIReg
, TRI) << "\n"; } } while (false)
847 << "): " << PrintReg(PHIReg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add Region LiveOut ("
<< (void *)Region << "): " << PrintReg(PHIReg
, TRI) << "\n"; } } while (false)
;
848 addLiveOut(PHIReg);
849 }
850 }
851 }
852 }
853 }
854}
855
856#ifndef NDEBUG
857void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
858 OS << "Linearized Region {";
859 bool IsFirst = true;
860 for (const auto &MBB : MBBs) {
861 if (IsFirst) {
862 IsFirst = false;
863 } else {
864 OS << " ,";
865 }
866 OS << MBB->getNumber();
867 }
868 OS << "} (" << Entry->getNumber() << ", "
869 << (Exit == nullptr ? -1 : Exit->getNumber())
870 << "): In:" << PrintReg(getBBSelectRegIn(), TRI)
871 << " Out:" << PrintReg(getBBSelectRegOut(), TRI) << " {";
872 for (auto &LI : LiveOuts) {
873 OS << PrintReg(LI, TRI) << " ";
874 }
875 OS << "} \n";
876}
877#endif
878
879unsigned LinearizedRegion::getBBSelectRegIn() {
880 return getRegionMRT()->getBBSelectRegIn();
881}
882
883unsigned LinearizedRegion::getBBSelectRegOut() {
884 return getRegionMRT()->getBBSelectRegOut();
885}
886
887void LinearizedRegion::setHasLoop(bool Value) { HasLoop = Value; }
888
889bool LinearizedRegion::getHasLoop() { return HasLoop; }
890
891void LinearizedRegion::addLiveOut(unsigned VReg) { LiveOuts.insert(VReg); }
892
893void LinearizedRegion::removeLiveOut(unsigned Reg) {
894 if (isLiveOut(Reg))
895 LiveOuts.erase(Reg);
896}
897
898void LinearizedRegion::replaceLiveOut(unsigned OldReg, unsigned NewReg) {
899 if (isLiveOut(OldReg)) {
900 removeLiveOut(OldReg);
901 addLiveOut(NewReg);
902 }
903}
904
905void LinearizedRegion::replaceRegister(unsigned Register, unsigned NewRegister,
906 MachineRegisterInfo *MRI,
907 bool ReplaceInside, bool ReplaceOutside,
908 bool IncludeLoopPHI) {
909 assert(Register != NewRegister && "Cannot replace a reg with itself")((Register != NewRegister && "Cannot replace a reg with itself"
) ? static_cast<void> (0) : __assert_fail ("Register != NewRegister && \"Cannot replace a reg with itself\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 909, __PRETTY_FUNCTION__))
;
910
911 DEBUG(dbgs() << "Pepareing to replace register (region): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Pepareing to replace register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
912 << PrintReg(Register, MRI->getTargetRegisterInfo()) << " with "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Pepareing to replace register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
913 << PrintReg(NewRegister, MRI->getTargetRegisterInfo()) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Pepareing to replace register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
;
914
915 // If we are replacing outside, we also need to update the LiveOuts
916 if (ReplaceOutside &&
917 (isLiveOut(Register) || this->getParent()->isLiveOut(Register))) {
918 LinearizedRegion *Current = this;
919 while (Current != nullptr && Current->getEntry() != nullptr) {
920 DEBUG(dbgs() << "Region before register replace\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Region before register replace\n"
; } } while (false)
;
921 DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Current->print(dbgs(), MRI->
getTargetRegisterInfo()); } } while (false)
;
922 Current->replaceLiveOut(Register, NewRegister);
923 DEBUG(dbgs() << "Region after register replace\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Region after register replace\n"
; } } while (false)
;
924 DEBUG(Current->print(dbgs(), MRI->getTargetRegisterInfo()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Current->print(dbgs(), MRI->
getTargetRegisterInfo()); } } while (false)
;
925 Current = Current->getParent();
926 }
927 }
928
929 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
930 E = MRI->reg_end();
931 I != E;) {
932 MachineOperand &O = *I;
933 ++I;
934
935 // We don't rewrite defs.
936 if (O.isDef())
937 continue;
938
939 bool IsInside = contains(O.getParent()->getParent());
940 bool IsLoopPHI = IsInside && (O.getParent()->isPHI() &&
941 O.getParent()->getParent() == getEntry());
942 bool ShouldReplace = (IsInside && ReplaceInside) ||
943 (!IsInside && ReplaceOutside) ||
944 (IncludeLoopPHI && IsLoopPHI);
945 if (ShouldReplace) {
946
947 if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) {
948 DEBUG(dbgs() << "Trying to substitute physical register: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
949 << PrintReg(NewRegister, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
950 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
;
951 llvm_unreachable("Cannot substitute physical registers")::llvm::llvm_unreachable_internal("Cannot substitute physical registers"
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 951)
;
952 } else {
953 DEBUG(dbgs() << "Replacing register (region): "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
954 << PrintReg(Register, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
955 << " with "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
956 << PrintReg(NewRegister, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
957 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register (region): "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
;
958 O.setReg(NewRegister);
959 }
960 }
961 }
962}
963
964void LinearizedRegion::replaceRegisterInsideRegion(unsigned Register,
965 unsigned NewRegister,
966 bool IncludeLoopPHIs,
967 MachineRegisterInfo *MRI) {
968 replaceRegister(Register, NewRegister, MRI, true, false, IncludeLoopPHIs);
969}
970
971void LinearizedRegion::replaceRegisterOutsideRegion(unsigned Register,
972 unsigned NewRegister,
973 bool IncludeLoopPHIs,
974 MachineRegisterInfo *MRI) {
975 replaceRegister(Register, NewRegister, MRI, false, true, IncludeLoopPHIs);
976}
977
978DenseSet<unsigned> *LinearizedRegion::getLiveOuts() { return &LiveOuts; }
979
980void LinearizedRegion::setEntry(MachineBasicBlock *NewEntry) {
981 Entry = NewEntry;
982}
983
984MachineBasicBlock *LinearizedRegion::getEntry() { return Entry; }
985
986void LinearizedRegion::setExit(MachineBasicBlock *NewExit) { Exit = NewExit; }
987
988MachineBasicBlock *LinearizedRegion::getExit() { return Exit; }
989
990void LinearizedRegion::addMBB(MachineBasicBlock *MBB) { MBBs.insert(MBB); }
991
992void LinearizedRegion::addMBBs(LinearizedRegion *InnerRegion) {
993 for (const auto &MBB : InnerRegion->MBBs) {
994 addMBB(MBB);
995 }
996}
997
998bool LinearizedRegion::contains(MachineBasicBlock *MBB) {
999 return MBBs.count(MBB) == 1;
1000}
1001
1002bool LinearizedRegion::isLiveOut(unsigned Reg) {
1003 return LiveOuts.count(Reg) == 1;
1004}
1005
1006bool LinearizedRegion::hasNoDef(unsigned Reg, MachineRegisterInfo *MRI) {
1007 return MRI->def_begin(Reg) == MRI->def_end();
1008}
1009
1010// After the code has been structurized, what was flagged as kills
1011// before are no longer register kills.
1012void LinearizedRegion::removeFalseRegisterKills(MachineRegisterInfo *MRI) {
1013 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1014 for (auto MBBI : MBBs) {
1015 MachineBasicBlock *MBB = MBBI;
1016 for (auto &II : *MBB) {
1017 for (auto &RI : II.uses()) {
1018 if (RI.isReg()) {
1019 unsigned Reg = RI.getReg();
1020 if (TRI->isVirtualRegister(Reg)) {
1021 if (hasNoDef(Reg, MRI))
1022 continue;
1023 if (!MRI->hasOneDef(Reg)) {
1024 DEBUG(this->getEntry()->getParent()->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { this->getEntry()->getParent
()->dump(); } } while (false)
;
1025 DEBUG(dbgs() << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(Reg, TRI
) << "\n"; } } while (false)
;
1026 }
1027
1028 if (MRI->def_begin(Reg) == MRI->def_end()) {
1029 DEBUG(dbgs() << "Register "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"
; } } while (false)
1030 << PrintReg(Reg, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"
; } } while (false)
1031 << " has NO defs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"
; } } while (false)
;
1032 } else if (!MRI->hasOneDef(Reg)) {
1033 DEBUG(dbgs() << "Register "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"
; } } while (false)
1034 << PrintReg(Reg, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"
; } } while (false)
1035 << " has multiple defs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"
; } } while (false)
;
1036 }
1037
1038 assert(MRI->hasOneDef(Reg) && "Register has multiple definitions")((MRI->hasOneDef(Reg) && "Register has multiple definitions"
) ? static_cast<void> (0) : __assert_fail ("MRI->hasOneDef(Reg) && \"Register has multiple definitions\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 1038, __PRETTY_FUNCTION__))
;
1039 MachineOperand *Def = &(*(MRI->def_begin(Reg)));
1040 MachineOperand *UseOperand = &(RI);
1041 bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
1042 if (UseIsOutsideDefMBB && UseOperand->isKill()) {
1043 DEBUG(dbgs() << "Removing kill flag on register: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Removing kill flag on register: "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
1044 << PrintReg(Reg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Removing kill flag on register: "
<< PrintReg(Reg, TRI) << "\n"; } } while (false)
;
1045 UseOperand->setIsKill(false);
1046 }
1047 }
1048 }
1049 }
1050 }
1051 }
1052}
1053
1054void LinearizedRegion::initLiveOut(RegionMRT *Region,
1055 const MachineRegisterInfo *MRI,
1056 const TargetRegisterInfo *TRI,
1057 PHILinearize &PHIInfo) {
1058 storeLiveOuts(Region, MRI, TRI, PHIInfo);
1059}
1060
1061LinearizedRegion::LinearizedRegion(MachineBasicBlock *MBB,
1062 const MachineRegisterInfo *MRI,
1063 const TargetRegisterInfo *TRI,
1064 PHILinearize &PHIInfo) {
1065 setEntry(MBB);
1066 setExit(MBB);
1067 storeLiveOuts(MBB, MRI, TRI, PHIInfo);
1068 MBBs.insert(MBB);
1069 Parent = nullptr;
1070}
1071
1072LinearizedRegion::LinearizedRegion() {
1073 setEntry(nullptr);
1074 setExit(nullptr);
1075 Parent = nullptr;
1076}
1077
1078namespace {
1079
1080class AMDGPUMachineCFGStructurizer : public MachineFunctionPass {
1081private:
1082 const MachineRegionInfo *Regions;
1083 const SIInstrInfo *TII;
1084 const TargetRegisterInfo *TRI;
1085 MachineRegisterInfo *MRI;
1086 unsigned BBSelectRegister;
1087 PHILinearize PHIInfo;
1088 DenseMap<MachineBasicBlock *, MachineBasicBlock *> FallthroughMap;
1089 RegionMRT *RMRT;
1090
1091 void getPHIRegionIndices(RegionMRT *Region, MachineInstr &PHI,
1092 SmallVector<unsigned, 2> &RegionIndices);
1093 void getPHIRegionIndices(LinearizedRegion *Region, MachineInstr &PHI,
1094 SmallVector<unsigned, 2> &RegionIndices);
1095 void getPHINonRegionIndices(LinearizedRegion *Region, MachineInstr &PHI,
1096 SmallVector<unsigned, 2> &PHINonRegionIndices);
1097
1098 void storePHILinearizationInfoDest(
1099 unsigned LDestReg, MachineInstr &PHI,
1100 SmallVector<unsigned, 2> *RegionIndices = nullptr);
1101
1102 unsigned storePHILinearizationInfo(MachineInstr &PHI,
1103 SmallVector<unsigned, 2> *RegionIndices);
1104
1105 void extractKilledPHIs(MachineBasicBlock *MBB);
1106
1107 bool shrinkPHI(MachineInstr &PHI, SmallVector<unsigned, 2> &PHIIndices,
1108 unsigned *ReplaceReg);
1109
1110 bool shrinkPHI(MachineInstr &PHI, unsigned CombinedSourceReg,
1111 MachineBasicBlock *SourceMBB,
1112 SmallVector<unsigned, 2> &PHIIndices, unsigned *ReplaceReg);
1113
1114 void replacePHI(MachineInstr &PHI, unsigned CombinedSourceReg,
1115 MachineBasicBlock *LastMerge,
1116 SmallVector<unsigned, 2> &PHIRegionIndices);
1117 void replaceEntryPHI(MachineInstr &PHI, unsigned CombinedSourceReg,
1118 MachineBasicBlock *IfMBB,
1119 SmallVector<unsigned, 2> &PHIRegionIndices);
1120 void replaceLiveOutRegs(MachineInstr &PHI,
1121 SmallVector<unsigned, 2> &PHIRegionIndices,
1122 unsigned CombinedSourceReg,
1123 LinearizedRegion *LRegion);
1124 void rewriteRegionExitPHI(RegionMRT *Region, MachineBasicBlock *LastMerge,
1125 MachineInstr &PHI, LinearizedRegion *LRegion);
1126
1127 void rewriteRegionExitPHIs(RegionMRT *Region, MachineBasicBlock *LastMerge,
1128 LinearizedRegion *LRegion);
1129 void rewriteRegionEntryPHI(LinearizedRegion *Region, MachineBasicBlock *IfMBB,
1130 MachineInstr &PHI);
1131 void rewriteRegionEntryPHIs(LinearizedRegion *Region,
1132 MachineBasicBlock *IfMBB);
1133
1134 bool regionIsSimpleIf(RegionMRT *Region);
1135
1136 void transformSimpleIfRegion(RegionMRT *Region);
1137
1138 void eliminateDeadBranchOperands(MachineBasicBlock::instr_iterator &II);
1139
1140 void insertUnconditionalBranch(MachineBasicBlock *MBB,
1141 MachineBasicBlock *Dest,
1142 const DebugLoc &DL = DebugLoc());
1143
1144 MachineBasicBlock *createLinearizedExitBlock(RegionMRT *Region);
1145
1146 void insertMergePHI(MachineBasicBlock *IfBB, MachineBasicBlock *CodeBB,
1147 MachineBasicBlock *MergeBB, unsigned DestRegister,
1148 unsigned IfSourceRegister, unsigned CodeSourceRegister,
1149 bool IsUndefIfSource = false);
1150
1151 MachineBasicBlock *createIfBlock(MachineBasicBlock *MergeBB,
1152 MachineBasicBlock *CodeBBStart,
1153 MachineBasicBlock *CodeBBEnd,
1154 MachineBasicBlock *SelectBB, unsigned IfReg,
1155 bool InheritPreds);
1156
1157 void prunePHIInfo(MachineBasicBlock *MBB);
1158 void createEntryPHI(LinearizedRegion *CurrentRegion, unsigned DestReg);
1159
1160 void createEntryPHIs(LinearizedRegion *CurrentRegion);
1161 void resolvePHIInfos(MachineBasicBlock *FunctionEntry);
1162
1163 void replaceRegisterWith(unsigned Register, unsigned NewRegister);
1164
1165 MachineBasicBlock *createIfRegion(MachineBasicBlock *MergeBB,
1166 MachineBasicBlock *CodeBB,
1167 LinearizedRegion *LRegion,
1168 unsigned BBSelectRegIn,
1169 unsigned BBSelectRegOut);
1170
1171 MachineBasicBlock *
1172 createIfRegion(MachineBasicBlock *MergeMBB, LinearizedRegion *InnerRegion,
1173 LinearizedRegion *CurrentRegion, MachineBasicBlock *SelectBB,
1174 unsigned BBSelectRegIn, unsigned BBSelectRegOut);
1175 void ensureCondIsNotKilled(SmallVector<MachineOperand, 1> Cond);
1176
1177 void rewriteCodeBBTerminator(MachineBasicBlock *CodeBB,
1178 MachineBasicBlock *MergeBB,
1179 unsigned BBSelectReg);
1180
1181 MachineInstr *getDefInstr(unsigned Reg);
1182 void insertChainedPHI(MachineBasicBlock *IfBB, MachineBasicBlock *CodeBB,
1183 MachineBasicBlock *MergeBB,
1184 LinearizedRegion *InnerRegion, unsigned DestReg,
1185 unsigned SourceReg);
1186 bool containsDef(MachineBasicBlock *MBB, LinearizedRegion *InnerRegion,
1187 unsigned Register);
1188 void rewriteLiveOutRegs(MachineBasicBlock *IfBB, MachineBasicBlock *CodeBB,
1189 MachineBasicBlock *MergeBB,
1190 LinearizedRegion *InnerRegion,
1191 LinearizedRegion *LRegion);
1192
1193 void splitLoopPHI(MachineInstr &PHI, MachineBasicBlock *Entry,
1194 MachineBasicBlock *EntrySucc, LinearizedRegion *LRegion);
1195 void splitLoopPHIs(MachineBasicBlock *Entry, MachineBasicBlock *EntrySucc,
1196 LinearizedRegion *LRegion);
1197
1198 MachineBasicBlock *splitExit(LinearizedRegion *LRegion);
1199
1200 MachineBasicBlock *splitEntry(LinearizedRegion *LRegion);
1201
1202 LinearizedRegion *initLinearizedRegion(RegionMRT *Region);
1203
1204 bool structurizeComplexRegion(RegionMRT *Region);
1205
1206 bool structurizeRegion(RegionMRT *Region);
1207
1208 bool structurizeRegions(RegionMRT *Region, bool isTopRegion);
1209
1210public:
1211 static char ID;
1212
1213 AMDGPUMachineCFGStructurizer() : MachineFunctionPass(ID) {
1214 initializeAMDGPUMachineCFGStructurizerPass(*PassRegistry::getPassRegistry());
1215 }
1216
1217 void getAnalysisUsage(AnalysisUsage &AU) const override {
1218 AU.addRequired<MachineRegionInfoPass>();
1219 MachineFunctionPass::getAnalysisUsage(AU);
1220 }
1221
1222 void initFallthroughMap(MachineFunction &MF);
1223
1224 void createLinearizedRegion(RegionMRT *Region, unsigned SelectOut);
1225
1226 unsigned initializeSelectRegisters(MRT *MRT, unsigned ExistingExitReg,
1227 MachineRegisterInfo *MRI,
1228 const SIInstrInfo *TII);
1229
1230 void setRegionMRT(RegionMRT *RegionTree) { RMRT = RegionTree; }
1231
1232 RegionMRT *getRegionMRT() { return RMRT; }
1233
1234 bool runOnMachineFunction(MachineFunction &MF) override;
1235};
1236
1237} // end anonymous namespace
1238
1239char AMDGPUMachineCFGStructurizer::ID = 0;
1240
1241bool AMDGPUMachineCFGStructurizer::regionIsSimpleIf(RegionMRT *Region) {
1242 MachineBasicBlock *Entry = Region->getEntry();
1243 MachineBasicBlock *Succ = Region->getSucc();
1244 bool FoundBypass = false;
1245 bool FoundIf = false;
1246
1247 if (Entry->succ_size() != 2) {
1248 return false;
1249 }
1250
1251 for (MachineBasicBlock::const_succ_iterator SI = Entry->succ_begin(),
1252 E = Entry->succ_end();
1253 SI != E; ++SI) {
1254 MachineBasicBlock *Current = *SI;
1255
1256 if (Current == Succ) {
1257 FoundBypass = true;
1258 } else if ((Current->succ_size() == 1) &&
1259 *(Current->succ_begin()) == Succ) {
1260 FoundIf = true;
1261 }
1262 }
1263
1264 return FoundIf && FoundBypass;
1265}
1266
1267void AMDGPUMachineCFGStructurizer::transformSimpleIfRegion(RegionMRT *Region) {
1268 MachineBasicBlock *Entry = Region->getEntry();
1269 MachineBasicBlock *Exit = Region->getExit();
1270 TII->convertNonUniformIfRegion(Entry, Exit);
1271}
1272
1273static void fixMBBTerminator(MachineBasicBlock *MBB) {
1274 if (MBB->succ_size() == 1) {
1275 auto *Succ = *(MBB->succ_begin());
1276 for (auto &TI : MBB->terminators()) {
1277 for (auto &UI : TI.uses()) {
1278 if (UI.isMBB() && UI.getMBB() != Succ) {
1279 UI.setMBB(Succ);
1280 }
1281 }
1282 }
1283 }
1284}
1285
1286static void fixRegionTerminator(RegionMRT *Region) {
1287 MachineBasicBlock *InternalSucc = nullptr;
1288 MachineBasicBlock *ExternalSucc = nullptr;
1289 LinearizedRegion *LRegion = Region->getLinearizedRegion();
1290 auto Exit = LRegion->getExit();
1291
1292 SmallPtrSet<MachineBasicBlock *, 2> Successors;
1293 for (MachineBasicBlock::const_succ_iterator SI = Exit->succ_begin(),
1294 SE = Exit->succ_end();
1295 SI != SE; ++SI) {
1296 MachineBasicBlock *Succ = *SI;
1297 if (LRegion->contains(Succ)) {
1298 // Do not allow re-assign
1299 assert(InternalSucc == nullptr)((InternalSucc == nullptr) ? static_cast<void> (0) : __assert_fail
("InternalSucc == nullptr", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 1299, __PRETTY_FUNCTION__))
;
1300 InternalSucc = Succ;
1301 } else {
1302 // Do not allow re-assign
1303 assert(ExternalSucc == nullptr)((ExternalSucc == nullptr) ? static_cast<void> (0) : __assert_fail
("ExternalSucc == nullptr", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 1303, __PRETTY_FUNCTION__))
;
1304 ExternalSucc = Succ;
1305 }
1306 }
1307
1308 for (auto &TI : Exit->terminators()) {
1309 for (auto &UI : TI.uses()) {
1310 if (UI.isMBB()) {
1311 auto Target = UI.getMBB();
1312 if (Target != InternalSucc && Target != ExternalSucc) {
1313 UI.setMBB(ExternalSucc);
1314 }
1315 }
1316 }
1317 }
1318}
1319
1320// If a region region is just a sequence of regions (and the exit
1321// block in the case of the top level region), we can simply skip
1322// linearizing it, because it is already linear
1323bool regionIsSequence(RegionMRT *Region) {
1324 auto Children = Region->getChildren();
1325 for (auto CI : *Children) {
1326 if (!CI->isRegion()) {
1327 if (CI->getMBBMRT()->getMBB()->succ_size() > 1) {
1328 return false;
1329 }
1330 }
1331 }
1332 return true;
1333}
1334
1335void fixupRegionExits(RegionMRT *Region) {
1336 auto Children = Region->getChildren();
1337 for (auto CI : *Children) {
1338 if (!CI->isRegion()) {
1339 fixMBBTerminator(CI->getMBBMRT()->getMBB());
1340 } else {
1341 fixRegionTerminator(CI->getRegionMRT());
1342 }
1343 }
1344}
1345
1346void AMDGPUMachineCFGStructurizer::getPHIRegionIndices(
1347 RegionMRT *Region, MachineInstr &PHI,
1348 SmallVector<unsigned, 2> &PHIRegionIndices) {
1349 unsigned NumInputs = getPHINumInputs(PHI);
1350 for (unsigned i = 0; i < NumInputs; ++i) {
1351 MachineBasicBlock *Pred = getPHIPred(PHI, i);
1352 if (Region->contains(Pred)) {
1353 PHIRegionIndices.push_back(i);
1354 }
1355 }
1356}
1357
1358void AMDGPUMachineCFGStructurizer::getPHIRegionIndices(
1359 LinearizedRegion *Region, MachineInstr &PHI,
1360 SmallVector<unsigned, 2> &PHIRegionIndices) {
1361 unsigned NumInputs = getPHINumInputs(PHI);
1362 for (unsigned i = 0; i < NumInputs; ++i) {
1363 MachineBasicBlock *Pred = getPHIPred(PHI, i);
1364 if (Region->contains(Pred)) {
1365 PHIRegionIndices.push_back(i);
1366 }
1367 }
1368}
1369
1370void AMDGPUMachineCFGStructurizer::getPHINonRegionIndices(
1371 LinearizedRegion *Region, MachineInstr &PHI,
1372 SmallVector<unsigned, 2> &PHINonRegionIndices) {
1373 unsigned NumInputs = getPHINumInputs(PHI);
1374 for (unsigned i = 0; i < NumInputs; ++i) {
1375 MachineBasicBlock *Pred = getPHIPred(PHI, i);
1376 if (!Region->contains(Pred)) {
1377 PHINonRegionIndices.push_back(i);
1378 }
1379 }
1380}
1381
1382void AMDGPUMachineCFGStructurizer::storePHILinearizationInfoDest(
1383 unsigned LDestReg, MachineInstr &PHI,
1384 SmallVector<unsigned, 2> *RegionIndices) {
1385 if (RegionIndices) {
1386 for (auto i : *RegionIndices) {
1387 PHIInfo.addSource(LDestReg, getPHISourceReg(PHI, i), getPHIPred(PHI, i));
1388 }
1389 } else {
1390 unsigned NumInputs = getPHINumInputs(PHI);
1391 for (unsigned i = 0; i < NumInputs; ++i) {
1392 PHIInfo.addSource(LDestReg, getPHISourceReg(PHI, i), getPHIPred(PHI, i));
1393 }
1394 }
1395}
1396
1397unsigned AMDGPUMachineCFGStructurizer::storePHILinearizationInfo(
1398 MachineInstr &PHI, SmallVector<unsigned, 2> *RegionIndices) {
1399 unsigned DestReg = getPHIDestReg(PHI);
1400 unsigned LinearizeDestReg =
1401 MRI->createVirtualRegister(MRI->getRegClass(DestReg));
1402 PHIInfo.addDest(LinearizeDestReg, PHI.getDebugLoc());
1403 storePHILinearizationInfoDest(LinearizeDestReg, PHI, RegionIndices);
1404 return LinearizeDestReg;
1405}
1406
1407void AMDGPUMachineCFGStructurizer::extractKilledPHIs(MachineBasicBlock *MBB) {
1408 // We need to create a new chain for the killed phi, but there is no
1409 // need to do the renaming outside or inside the block.
1410 SmallPtrSet<MachineInstr *, 2> PHIs;
1411 for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
1412 E = MBB->instr_end();
1413 I != E; ++I) {
1414 MachineInstr &Instr = *I;
1415 if (Instr.isPHI()) {
1416 unsigned PHIDestReg = getPHIDestReg(Instr);
1417 DEBUG(dbgs() << "Extractking killed phi:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Extractking killed phi:\n"
; } } while (false)
;
1418 DEBUG(Instr.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Instr.dump(); } } while (false)
;
1419 PHIs.insert(&Instr);
1420 PHIInfo.addDest(PHIDestReg, Instr.getDebugLoc());
1421 storePHILinearizationInfoDest(PHIDestReg, Instr);
1422 }
1423 }
1424
1425 for (auto PI : PHIs) {
1426 PI->eraseFromParent();
1427 }
1428}
1429
1430static bool isPHIRegionIndex(SmallVector<unsigned, 2> PHIRegionIndices,
1431 unsigned Index) {
1432 for (auto i : PHIRegionIndices) {
1433 if (i == Index)
1434 return true;
1435 }
1436 return false;
1437}
1438
1439bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
1440 SmallVector<unsigned, 2> &PHIIndices,
1441 unsigned *ReplaceReg) {
1442 return shrinkPHI(PHI, 0, nullptr, PHIIndices, ReplaceReg);
1443}
1444
1445bool AMDGPUMachineCFGStructurizer::shrinkPHI(MachineInstr &PHI,
1446 unsigned CombinedSourceReg,
1447 MachineBasicBlock *SourceMBB,
1448 SmallVector<unsigned, 2> &PHIIndices,
1449 unsigned *ReplaceReg) {
1450 DEBUG(dbgs() << "Shrink PHI: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Shrink PHI: "; }
} while (false)
;
1451 DEBUG(PHI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHI.dump(); } } while (false)
;
1452 DEBUG(dbgs() << " to " << PrintReg(getPHIDestReg(PHI), TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " to " << PrintReg
(getPHIDestReg(PHI), TRI) << "<def> = PHI("; } } while
(false)
1453 << "<def> = PHI(")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " to " << PrintReg
(getPHIDestReg(PHI), TRI) << "<def> = PHI("; } } while
(false)
;
1454
1455 bool Replaced = false;
1456 unsigned NumInputs = getPHINumInputs(PHI);
1457 int SingleExternalEntryIndex = -1;
1458 for (unsigned i = 0; i < NumInputs; ++i) {
1459 if (!isPHIRegionIndex(PHIIndices, i)) {
1460 if (SingleExternalEntryIndex == -1) {
1461 // Single entry
1462 SingleExternalEntryIndex = i;
1463 } else {
1464 // Multiple entries
1465 SingleExternalEntryIndex = -2;
1466 }
1467 }
1468 }
1469
1470 if (SingleExternalEntryIndex > -1) {
1471 *ReplaceReg = getPHISourceReg(PHI, SingleExternalEntryIndex);
1472 // We should not rewrite the code, we should only pick up the single value
1473 // that represents the shrunk PHI.
1474 Replaced = true;
1475 } else {
1476 MachineBasicBlock *MBB = PHI.getParent();
1477 MachineInstrBuilder MIB =
1478 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1479 getPHIDestReg(PHI));
1480 if (SourceMBB) {
1481 MIB.addReg(CombinedSourceReg);
1482 MIB.addMBB(SourceMBB);
1483 DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CombinedSourceReg
, TRI) << ", BB#" << SourceMBB->getNumber(); }
} while (false)
1484 << SourceMBB->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CombinedSourceReg
, TRI) << ", BB#" << SourceMBB->getNumber(); }
} while (false)
;
1485 }
1486
1487 for (unsigned i = 0; i < NumInputs; ++i) {
1488 if (isPHIRegionIndex(PHIIndices, i)) {
1489 continue;
1490 }
1491 unsigned SourceReg = getPHISourceReg(PHI, i);
1492 MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
1493 MIB.addReg(SourceReg);
1494 MIB.addMBB(SourcePred);
1495 DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << SourcePred->getNumber(); }
} while (false)
1496 << SourcePred->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << SourcePred->getNumber(); }
} while (false)
;
1497 }
1498 DEBUG(dbgs() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << ")\n"; } } while
(false)
;
1499 }
1500 PHI.eraseFromParent();
1501 return Replaced;
1502}
1503
1504void AMDGPUMachineCFGStructurizer::replacePHI(
1505 MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *LastMerge,
1506 SmallVector<unsigned, 2> &PHIRegionIndices) {
1507 DEBUG(dbgs() << "Replace PHI: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replace PHI: ";
} } while (false)
;
1508 DEBUG(PHI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHI.dump(); } } while (false)
;
1509 DEBUG(dbgs() << " with " << PrintReg(getPHIDestReg(PHI), TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " with " <<
PrintReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("
; } } while (false)
1510 << "<def> = PHI(")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " with " <<
PrintReg(getPHIDestReg(PHI), TRI) << "<def> = PHI("
; } } while (false)
;
1511
1512 bool HasExternalEdge = false;
1513 unsigned NumInputs = getPHINumInputs(PHI);
1514 for (unsigned i = 0; i < NumInputs; ++i) {
1515 if (!isPHIRegionIndex(PHIRegionIndices, i)) {
1516 HasExternalEdge = true;
1517 }
1518 }
1519
1520 if (HasExternalEdge) {
1521 MachineBasicBlock *MBB = PHI.getParent();
1522 MachineInstrBuilder MIB =
1523 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1524 getPHIDestReg(PHI));
1525 MIB.addReg(CombinedSourceReg);
1526 MIB.addMBB(LastMerge);
1527 DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CombinedSourceReg
, TRI) << ", BB#" << LastMerge->getNumber(); }
} while (false)
1528 << LastMerge->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CombinedSourceReg
, TRI) << ", BB#" << LastMerge->getNumber(); }
} while (false)
;
1529 for (unsigned i = 0; i < NumInputs; ++i) {
1530 if (isPHIRegionIndex(PHIRegionIndices, i)) {
1531 continue;
1532 }
1533 unsigned SourceReg = getPHISourceReg(PHI, i);
1534 MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
1535 MIB.addReg(SourceReg);
1536 MIB.addMBB(SourcePred);
1537 DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << SourcePred->getNumber(); }
} while (false)
1538 << SourcePred->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << SourcePred->getNumber(); }
} while (false)
;
1539 }
1540 DEBUG(dbgs() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << ")\n"; } } while
(false)
;
1541 } else {
1542 replaceRegisterWith(getPHIDestReg(PHI), CombinedSourceReg);
1543 }
1544 PHI.eraseFromParent();
1545}
1546
1547void AMDGPUMachineCFGStructurizer::replaceEntryPHI(
1548 MachineInstr &PHI, unsigned CombinedSourceReg, MachineBasicBlock *IfMBB,
1549 SmallVector<unsigned, 2> &PHIRegionIndices) {
1550 DEBUG(dbgs() << "Replace entry PHI: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replace entry PHI: "
; } } while (false)
;
1551 DEBUG(PHI.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHI.dump(); } } while (false)
;
1552 DEBUG(dbgs() << " with ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " with "; } } while
(false)
;
1553
1554 unsigned NumInputs = getPHINumInputs(PHI);
1555 unsigned NumNonRegionInputs = NumInputs;
1556 for (unsigned i = 0; i < NumInputs; ++i) {
1557 if (isPHIRegionIndex(PHIRegionIndices, i)) {
1558 NumNonRegionInputs--;
1559 }
1560 }
1561
1562 if (NumNonRegionInputs == 0) {
1563 auto DestReg = getPHIDestReg(PHI);
1564 replaceRegisterWith(DestReg, CombinedSourceReg);
1565 DEBUG(dbgs() << " register " << PrintReg(CombinedSourceReg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " register " <<
PrintReg(CombinedSourceReg, TRI) << "\n"; } } while (false
)
;
1566 PHI.eraseFromParent();
1567 } else {
1568 DEBUG(dbgs() << PrintReg(getPHIDestReg(PHI), TRI) << "<def> = PHI(")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(getPHIDestReg
(PHI), TRI) << "<def> = PHI("; } } while (false)
;
1569 MachineBasicBlock *MBB = PHI.getParent();
1570 MachineInstrBuilder MIB =
1571 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1572 getPHIDestReg(PHI));
1573 MIB.addReg(CombinedSourceReg);
1574 MIB.addMBB(IfMBB);
1575 DEBUG(dbgs() << PrintReg(CombinedSourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CombinedSourceReg
, TRI) << ", BB#" << IfMBB->getNumber(); } } while
(false)
1576 << IfMBB->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CombinedSourceReg
, TRI) << ", BB#" << IfMBB->getNumber(); } } while
(false)
;
1577 unsigned NumInputs = getPHINumInputs(PHI);
1578 for (unsigned i = 0; i < NumInputs; ++i) {
1579 if (isPHIRegionIndex(PHIRegionIndices, i)) {
1580 continue;
1581 }
1582 unsigned SourceReg = getPHISourceReg(PHI, i);
1583 MachineBasicBlock *SourcePred = getPHIPred(PHI, i);
1584 MIB.addReg(SourceReg);
1585 MIB.addMBB(SourcePred);
1586 DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << SourcePred->getNumber(); }
} while (false)
1587 << SourcePred->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << SourcePred->getNumber(); }
} while (false)
;
1588 }
1589 DEBUG(dbgs() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << ")\n"; } } while
(false)
;
1590 PHI.eraseFromParent();
1591 }
1592}
1593
1594void AMDGPUMachineCFGStructurizer::replaceLiveOutRegs(
1595 MachineInstr &PHI, SmallVector<unsigned, 2> &PHIRegionIndices,
1596 unsigned CombinedSourceReg, LinearizedRegion *LRegion) {
1597 bool WasLiveOut = false;
1598 for (auto PII : PHIRegionIndices) {
1599 unsigned Reg = getPHISourceReg(PHI, PII);
1600 if (LRegion->isLiveOut(Reg)) {
1601 bool IsDead = true;
1602
1603 // Check if register is live out of the basic block
1604 MachineBasicBlock *DefMBB = getDefInstr(Reg)->getParent();
1605 for (auto UI = MRI->use_begin(Reg), E = MRI->use_end(); UI != E; ++UI) {
1606 if ((*UI).getParent()->getParent() != DefMBB) {
1607 IsDead = false;
1608 }
1609 }
1610
1611 DEBUG(dbgs() << "Register " << PrintReg(Reg, TRI) << " is "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, TRI) << " is " << (IsDead ? "dead"
: "alive") << " after PHI replace\n"; } } while (false
)
1612 << (IsDead ? "dead" : "alive") << " after PHI replace\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, TRI) << " is " << (IsDead ? "dead"
: "alive") << " after PHI replace\n"; } } while (false
)
;
1613 if (IsDead) {
1614 LRegion->removeLiveOut(Reg);
1615 }
1616 WasLiveOut = true;
1617 }
1618 }
1619
1620 if (WasLiveOut)
1621 LRegion->addLiveOut(CombinedSourceReg);
1622}
1623
1624void AMDGPUMachineCFGStructurizer::rewriteRegionExitPHI(RegionMRT *Region,
1625 MachineBasicBlock *LastMerge,
1626 MachineInstr &PHI,
1627 LinearizedRegion *LRegion) {
1628 SmallVector<unsigned, 2> PHIRegionIndices;
1629 getPHIRegionIndices(Region, PHI, PHIRegionIndices);
1630 unsigned LinearizedSourceReg =
1631 storePHILinearizationInfo(PHI, &PHIRegionIndices);
1632
1633 replacePHI(PHI, LinearizedSourceReg, LastMerge, PHIRegionIndices);
1634 replaceLiveOutRegs(PHI, PHIRegionIndices, LinearizedSourceReg, LRegion);
1635}
1636
1637void AMDGPUMachineCFGStructurizer::rewriteRegionEntryPHI(LinearizedRegion *Region,
1638 MachineBasicBlock *IfMBB,
1639 MachineInstr &PHI) {
1640 SmallVector<unsigned, 2> PHINonRegionIndices;
1641 getPHINonRegionIndices(Region, PHI, PHINonRegionIndices);
1642 unsigned LinearizedSourceReg =
1643 storePHILinearizationInfo(PHI, &PHINonRegionIndices);
1644 replaceEntryPHI(PHI, LinearizedSourceReg, IfMBB, PHINonRegionIndices);
1645}
1646
1647static void collectPHIs(MachineBasicBlock *MBB,
1648 SmallVector<MachineInstr *, 2> &PHIs) {
1649 for (auto &BBI : *MBB) {
1650 if (BBI.isPHI()) {
1651 PHIs.push_back(&BBI);
1652 }
1653 }
1654}
1655
1656void AMDGPUMachineCFGStructurizer::rewriteRegionExitPHIs(RegionMRT *Region,
1657 MachineBasicBlock *LastMerge,
1658 LinearizedRegion *LRegion) {
1659 SmallVector<MachineInstr *, 2> PHIs;
1660 auto Exit = Region->getSucc();
1661 if (Exit == nullptr)
1662 return;
1663
1664 collectPHIs(Exit, PHIs);
1665
1666 for (auto PHII : PHIs) {
1667 rewriteRegionExitPHI(Region, LastMerge, *PHII, LRegion);
1668 }
1669}
1670
1671void AMDGPUMachineCFGStructurizer::rewriteRegionEntryPHIs(LinearizedRegion *Region,
1672 MachineBasicBlock *IfMBB) {
1673 SmallVector<MachineInstr *, 2> PHIs;
1674 auto Entry = Region->getEntry();
1675
1676 collectPHIs(Entry, PHIs);
1677
1678 for (auto PHII : PHIs) {
1679 rewriteRegionEntryPHI(Region, IfMBB, *PHII);
1680 }
1681}
1682
1683void AMDGPUMachineCFGStructurizer::insertUnconditionalBranch(MachineBasicBlock *MBB,
1684 MachineBasicBlock *Dest,
1685 const DebugLoc &DL) {
1686 DEBUG(dbgs() << "Inserting unconditional branch: " << MBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting unconditional branch: "
<< MBB->getNumber() << " -> " << Dest
->getNumber() << "\n"; } } while (false)
1687 << " -> " << Dest->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting unconditional branch: "
<< MBB->getNumber() << " -> " << Dest
->getNumber() << "\n"; } } while (false)
;
1688 MachineBasicBlock::instr_iterator Terminator = MBB->getFirstInstrTerminator();
1689 bool HasTerminator = Terminator != MBB->instr_end();
1690 if (HasTerminator) {
1691 TII->ReplaceTailWithBranchTo(Terminator, Dest);
1692 }
1693 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(Dest)) {
1694 TII->insertUnconditionalBranch(*MBB, Dest, DL);
1695 }
1696}
1697
1698static MachineBasicBlock *getSingleExitNode(MachineFunction &MF) {
1699 MachineBasicBlock *result = nullptr;
1700 for (auto &MFI : MF) {
1701 if (MFI.succ_size() == 0) {
1702 if (result == nullptr) {
1703 result = &MFI;
1704 } else {
1705 return nullptr;
1706 }
1707 }
1708 }
1709
1710 return result;
1711}
1712
1713static bool hasOneExitNode(MachineFunction &MF) {
1714 return getSingleExitNode(MF) != nullptr;
1715}
1716
1717MachineBasicBlock *
1718AMDGPUMachineCFGStructurizer::createLinearizedExitBlock(RegionMRT *Region) {
1719 auto Exit = Region->getSucc();
1720
1721 // If the exit is the end of the function, we just use the existing
1722 MachineFunction *MF = Region->getEntry()->getParent();
1723 if (Exit == nullptr && hasOneExitNode(*MF)) {
1724 return &(*(--(Region->getEntry()->getParent()->end())));
1725 }
1726
1727 MachineBasicBlock *LastMerge = MF->CreateMachineBasicBlock();
1728 if (Exit == nullptr) {
1729 MachineFunction::iterator ExitIter = MF->end();
1730 MF->insert(ExitIter, LastMerge);
1731 } else {
1732 MachineFunction::iterator ExitIter = Exit->getIterator();
1733 MF->insert(ExitIter, LastMerge);
1734 LastMerge->addSuccessor(Exit);
1735 insertUnconditionalBranch(LastMerge, Exit);
1736 DEBUG(dbgs() << "Created exit block: " << LastMerge->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Created exit block: "
<< LastMerge->getNumber() << "\n"; } } while (
false)
;
1737 }
1738 return LastMerge;
1739}
1740
1741void AMDGPUMachineCFGStructurizer::insertMergePHI(MachineBasicBlock *IfBB,
1742 MachineBasicBlock *CodeBB,
1743 MachineBasicBlock *MergeBB,
1744 unsigned DestRegister,
1745 unsigned IfSourceRegister,
1746 unsigned CodeSourceRegister,
1747 bool IsUndefIfSource) {
1748 // If this is the function exit block, we don't need a phi.
1749 if (MergeBB->succ_begin() == MergeBB->succ_end()) {
1750 return;
1751 }
1752 DEBUG(dbgs() << "Merge PHI (BB#" << MergeBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Merge PHI (BB#"
<< MergeBB->getNumber() << "): " << PrintReg
(DestRegister, TRI) << "<def> = PHI(" << PrintReg
(IfSourceRegister, TRI) << ", BB#" << IfBB->getNumber
() << PrintReg(CodeSourceRegister, TRI) << ", BB#"
<< CodeBB->getNumber() << ")\n"; } } while (false
)
1753 << "): " << PrintReg(DestRegister, TRI) << "<def> = PHI("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Merge PHI (BB#"
<< MergeBB->getNumber() << "): " << PrintReg
(DestRegister, TRI) << "<def> = PHI(" << PrintReg
(IfSourceRegister, TRI) << ", BB#" << IfBB->getNumber
() << PrintReg(CodeSourceRegister, TRI) << ", BB#"
<< CodeBB->getNumber() << ")\n"; } } while (false
)
1754 << PrintReg(IfSourceRegister, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Merge PHI (BB#"
<< MergeBB->getNumber() << "): " << PrintReg
(DestRegister, TRI) << "<def> = PHI(" << PrintReg
(IfSourceRegister, TRI) << ", BB#" << IfBB->getNumber
() << PrintReg(CodeSourceRegister, TRI) << ", BB#"
<< CodeBB->getNumber() << ")\n"; } } while (false
)
1755 << IfBB->getNumber() << PrintReg(CodeSourceRegister, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Merge PHI (BB#"
<< MergeBB->getNumber() << "): " << PrintReg
(DestRegister, TRI) << "<def> = PHI(" << PrintReg
(IfSourceRegister, TRI) << ", BB#" << IfBB->getNumber
() << PrintReg(CodeSourceRegister, TRI) << ", BB#"
<< CodeBB->getNumber() << ")\n"; } } while (false
)
1756 << ", BB#" << CodeBB->getNumber() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Merge PHI (BB#"
<< MergeBB->getNumber() << "): " << PrintReg
(DestRegister, TRI) << "<def> = PHI(" << PrintReg
(IfSourceRegister, TRI) << ", BB#" << IfBB->getNumber
() << PrintReg(CodeSourceRegister, TRI) << ", BB#"
<< CodeBB->getNumber() << ")\n"; } } while (false
)
;
1757 const DebugLoc &DL = MergeBB->findDebugLoc(MergeBB->begin());
1758 MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL,
1759 TII->get(TargetOpcode::PHI), DestRegister);
1760 if (IsUndefIfSource && false) {
1761 MIB.addReg(IfSourceRegister, RegState::Undef);
1762 } else {
1763 MIB.addReg(IfSourceRegister);
1764 }
1765 MIB.addMBB(IfBB);
1766 MIB.addReg(CodeSourceRegister);
1767 MIB.addMBB(CodeBB);
1768}
1769
1770static void removeExternalCFGSuccessors(MachineBasicBlock *MBB) {
1771 for (MachineBasicBlock::succ_iterator PI = MBB->succ_begin(),
1772 E = MBB->succ_end();
1773 PI != E; ++PI) {
1774 if ((*PI) != MBB) {
1775 (MBB)->removeSuccessor(*PI);
1776 }
1777 }
1778}
1779
1780static void removeExternalCFGEdges(MachineBasicBlock *StartMBB,
1781 MachineBasicBlock *EndMBB) {
1782
1783 // We have to check against the StartMBB successor becasuse a
1784 // structurized region with a loop will have the entry block split,
1785 // and the backedge will go to the entry successor.
1786 DenseSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>> Succs;
1787 unsigned SuccSize = StartMBB->succ_size();
1788 if (SuccSize > 0) {
1789 MachineBasicBlock *StartMBBSucc = *(StartMBB->succ_begin());
1790 for (MachineBasicBlock::succ_iterator PI = EndMBB->succ_begin(),
1791 E = EndMBB->succ_end();
1792 PI != E; ++PI) {
1793 // Either we have a back-edge to the entry block, or a back-edge to the
1794 // successor of the entry block since the block may be split.
1795 if ((*PI) != StartMBB &&
1796 !((*PI) == StartMBBSucc && StartMBB != EndMBB && SuccSize == 1)) {
1797 Succs.insert(
1798 std::pair<MachineBasicBlock *, MachineBasicBlock *>(EndMBB, *PI));
1799 }
1800 }
1801 }
1802
1803 for (MachineBasicBlock::pred_iterator PI = StartMBB->pred_begin(),
1804 E = StartMBB->pred_end();
1805 PI != E; ++PI) {
1806 if ((*PI) != EndMBB) {
1807 Succs.insert(
1808 std::pair<MachineBasicBlock *, MachineBasicBlock *>(*PI, StartMBB));
1809 }
1810 }
1811
1812 for (auto SI : Succs) {
1813 std::pair<MachineBasicBlock *, MachineBasicBlock *> Edge = SI;
1814 DEBUG(dbgs() << "Removing edge: BB#" << Edge.first->getNumber() << " -> BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Removing edge: BB#"
<< Edge.first->getNumber() << " -> BB#" <<
Edge.second->getNumber() << "\n"; } } while (false)
1815 << Edge.second->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Removing edge: BB#"
<< Edge.first->getNumber() << " -> BB#" <<
Edge.second->getNumber() << "\n"; } } while (false)
;
1816 Edge.first->removeSuccessor(Edge.second);
1817 }
1818}
1819
1820MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfBlock(
1821 MachineBasicBlock *MergeBB, MachineBasicBlock *CodeBBStart,
1822 MachineBasicBlock *CodeBBEnd, MachineBasicBlock *SelectBB, unsigned IfReg,
1823 bool InheritPreds) {
1824 MachineFunction *MF = MergeBB->getParent();
1825 MachineBasicBlock *IfBB = MF->CreateMachineBasicBlock();
1826
1827 if (InheritPreds) {
1828 for (MachineBasicBlock::pred_iterator PI = CodeBBStart->pred_begin(),
1829 E = CodeBBStart->pred_end();
1830 PI != E; ++PI) {
1831 if ((*PI) != CodeBBEnd) {
1832 MachineBasicBlock *Pred = (*PI);
1833 Pred->addSuccessor(IfBB);
1834 }
1835 }
1836 }
1837
1838 removeExternalCFGEdges(CodeBBStart, CodeBBEnd);
1839
1840 auto CodeBBStartI = CodeBBStart->getIterator();
1841 auto CodeBBEndI = CodeBBEnd->getIterator();
1842 auto MergeIter = MergeBB->getIterator();
1843 MF->insert(MergeIter, IfBB);
1844 MF->splice(MergeIter, CodeBBStartI, ++CodeBBEndI);
1845 IfBB->addSuccessor(MergeBB);
1846 IfBB->addSuccessor(CodeBBStart);
1847
1848 DEBUG(dbgs() << "Created If block: " << IfBB->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Created If block: "
<< IfBB->getNumber() << "\n"; } } while (false
)
;
1849 // Ensure that the MergeBB is a successor of the CodeEndBB.
1850 if (!CodeBBEnd->isSuccessor(MergeBB))
1851 CodeBBEnd->addSuccessor(MergeBB);
1852
1853 DEBUG(dbgs() << "Moved MBB#" << CodeBBStart->getNumber() << " through MBB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Moved MBB#" <<
CodeBBStart->getNumber() << " through MBB#" <<
CodeBBEnd->getNumber() << "\n"; } } while (false)
1854 << CodeBBEnd->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Moved MBB#" <<
CodeBBStart->getNumber() << " through MBB#" <<
CodeBBEnd->getNumber() << "\n"; } } while (false)
;
1855
1856 // If we have a single predecessor we can find a reasonable debug location
1857 MachineBasicBlock *SinglePred =
1858 CodeBBStart->pred_size() == 1 ? *(CodeBBStart->pred_begin()) : nullptr;
1859 const DebugLoc &DL = SinglePred
1860 ? SinglePred->findDebugLoc(SinglePred->getFirstTerminator())
1861 : DebugLoc();
1862
1863 unsigned Reg =
1864 TII->insertEQ(IfBB, IfBB->begin(), DL, IfReg,
1865 SelectBB->getNumber() /* CodeBBStart->getNumber() */);
1866 if (&(*(IfBB->getParent()->begin())) == IfBB) {
1867 TII->materializeImmediate(*IfBB, IfBB->begin(), DL, IfReg,
1868 CodeBBStart->getNumber());
1869 }
1870 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
1871 ArrayRef<MachineOperand> Cond(RegOp);
1872 TII->insertBranch(*IfBB, MergeBB, CodeBBStart, Cond, DL);
1873
1874 return IfBB;
1875}
1876
1877void AMDGPUMachineCFGStructurizer::ensureCondIsNotKilled(
1878 SmallVector<MachineOperand, 1> Cond) {
1879 if (Cond.size() != 1)
1880 return;
1881 if (!Cond[0].isReg())
1882 return;
1883
1884 unsigned CondReg = Cond[0].getReg();
1885 for (auto UI = MRI->use_begin(CondReg), E = MRI->use_end(); UI != E; ++UI) {
1886 (*UI).setIsKill(false);
1887 }
1888}
1889
1890void AMDGPUMachineCFGStructurizer::rewriteCodeBBTerminator(MachineBasicBlock *CodeBB,
1891 MachineBasicBlock *MergeBB,
1892 unsigned BBSelectReg) {
1893 MachineBasicBlock *TrueBB = nullptr;
1894 MachineBasicBlock *FalseBB = nullptr;
1895 SmallVector<MachineOperand, 1> Cond;
1896 MachineBasicBlock *FallthroughBB = FallthroughMap[CodeBB];
1897 TII->analyzeBranch(*CodeBB, TrueBB, FalseBB, Cond);
1898
1899 const DebugLoc &DL = CodeBB->findDebugLoc(CodeBB->getFirstTerminator());
1900
1901 if (FalseBB == nullptr && TrueBB == nullptr && FallthroughBB == nullptr) {
1902 // This is an exit block, hence no successors. We will assign the
1903 // bb select register to the entry block.
1904 TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1905 BBSelectReg,
1906 CodeBB->getParent()->begin()->getNumber());
1907 insertUnconditionalBranch(CodeBB, MergeBB, DL);
1908 return;
1909 }
1910
1911 if (FalseBB == nullptr && TrueBB == nullptr) {
1912 TrueBB = FallthroughBB;
1913 } else if (TrueBB != nullptr) {
1914 FalseBB =
1915 (FallthroughBB && (FallthroughBB != TrueBB)) ? FallthroughBB : FalseBB;
1916 }
1917
1918 if ((TrueBB != nullptr && FalseBB == nullptr) || (TrueBB == FalseBB)) {
1919 TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1920 BBSelectReg, TrueBB->getNumber());
1921 } else {
1922 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
1923 unsigned TrueBBReg = MRI->createVirtualRegister(RegClass);
1924 unsigned FalseBBReg = MRI->createVirtualRegister(RegClass);
1925 TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1926 TrueBBReg, TrueBB->getNumber());
1927 TII->materializeImmediate(*CodeBB, CodeBB->getFirstTerminator(), DL,
1928 FalseBBReg, FalseBB->getNumber());
1929 ensureCondIsNotKilled(Cond);
1930 TII->insertVectorSelect(*CodeBB, CodeBB->getFirstTerminator(), DL,
1931 BBSelectReg, Cond, TrueBBReg, FalseBBReg);
1932 }
1933
1934 insertUnconditionalBranch(CodeBB, MergeBB, DL);
1935}
1936
1937MachineInstr *AMDGPUMachineCFGStructurizer::getDefInstr(unsigned Reg) {
1938 if (MRI->def_begin(Reg) == MRI->def_end()) {
1939 DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"
; } } while (false)
1940 << " has NO defs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has NO defs\n"
; } } while (false)
;
1941 } else if (!MRI->hasOneDef(Reg)) {
1942 DEBUG(dbgs() << "Register " << PrintReg(Reg, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"
; } } while (false)
1943 << " has multiple defs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Register " <<
PrintReg(Reg, MRI->getTargetRegisterInfo()) << " has multiple defs\n"
; } } while (false)
;
1944 DEBUG(dbgs() << "DEFS BEGIN:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "DEFS BEGIN:\n";
} } while (false)
;
1945 for (auto DI = MRI->def_begin(Reg), DE = MRI->def_end(); DI != DE; ++DI) {
1946 DEBUG(DI->getParent()->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { DI->getParent()->dump(); }
} while (false)
;
1947 }
1948 DEBUG(dbgs() << "DEFS END\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "DEFS END\n"; } }
while (false)
;
1949 }
1950
1951 assert(MRI->hasOneDef(Reg) && "Register has multiple definitions")((MRI->hasOneDef(Reg) && "Register has multiple definitions"
) ? static_cast<void> (0) : __assert_fail ("MRI->hasOneDef(Reg) && \"Register has multiple definitions\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 1951, __PRETTY_FUNCTION__))
;
1952 return (*(MRI->def_begin(Reg))).getParent();
1953}
1954
1955void AMDGPUMachineCFGStructurizer::insertChainedPHI(MachineBasicBlock *IfBB,
1956 MachineBasicBlock *CodeBB,
1957 MachineBasicBlock *MergeBB,
1958 LinearizedRegion *InnerRegion,
1959 unsigned DestReg,
1960 unsigned SourceReg) {
1961 // In this function we know we are part of a chain already, so we need
1962 // to add the registers to the existing chain, and rename the register
1963 // inside the region.
1964 bool IsSingleBB = InnerRegion->getEntry() == InnerRegion->getExit();
1965 MachineInstr *DefInstr = getDefInstr(SourceReg);
1966 if (DefInstr->isPHI() && DefInstr->getParent() == CodeBB && IsSingleBB) {
1967 // Handle the case where the def is a PHI-def inside a basic
1968 // block, then we only need to do renaming. Special care needs to
1969 // be taken if the PHI-def is part of an existing chain, or if a
1970 // new one needs to be created.
1971 InnerRegion->replaceRegisterInsideRegion(SourceReg, DestReg, true, MRI);
1972
1973 // We collect all PHI Information, and if we are at the region entry,
1974 // all PHIs will be removed, and then re-introduced if needed.
1975 storePHILinearizationInfoDest(DestReg, *DefInstr);
1976 // We have picked up all the information we need now and can remove
1977 // the PHI
1978 PHIInfo.removeSource(DestReg, SourceReg, CodeBB);
1979 DefInstr->eraseFromParent();
1980 } else {
1981 // If this is not a phi-def, or it is a phi-def but from a linearized region
1982 if (IsSingleBB && DefInstr->getParent() == InnerRegion->getEntry()) {
1983 // If this is a single BB and the definition is in this block we
1984 // need to replace any uses outside the region.
1985 InnerRegion->replaceRegisterOutsideRegion(SourceReg, DestReg, false, MRI);
1986 }
1987 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
1988 unsigned NextDestReg = MRI->createVirtualRegister(RegClass);
1989 bool IsLastDef = PHIInfo.getNumSources(DestReg) == 1;
1990 DEBUG(dbgs() << "Insert Chained PHI\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Insert Chained PHI\n"
; } } while (false)
;
1991 insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, DestReg, NextDestReg,
1992 SourceReg, IsLastDef);
1993
1994 PHIInfo.removeSource(DestReg, SourceReg, CodeBB);
1995 if (IsLastDef) {
1996 const DebugLoc &DL = IfBB->findDebugLoc(IfBB->getFirstTerminator());
1997 TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DL,
1998 NextDestReg, 0);
1999 PHIInfo.deleteDef(DestReg);
2000 } else {
2001 PHIInfo.replaceDef(DestReg, NextDestReg);
2002 }
2003 }
2004}
2005
2006bool AMDGPUMachineCFGStructurizer::containsDef(MachineBasicBlock *MBB,
2007 LinearizedRegion *InnerRegion,
2008 unsigned Register) {
2009 return getDefInstr(Register)->getParent() == MBB ||
2010 InnerRegion->contains(getDefInstr(Register)->getParent());
2011}
2012
2013void AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs(MachineBasicBlock *IfBB,
2014 MachineBasicBlock *CodeBB,
2015 MachineBasicBlock *MergeBB,
2016 LinearizedRegion *InnerRegion,
2017 LinearizedRegion *LRegion) {
2018 DenseSet<unsigned> *LiveOuts = InnerRegion->getLiveOuts();
2019 SmallVector<unsigned, 4> OldLiveOuts;
2020 bool IsSingleBB = InnerRegion->getEntry() == InnerRegion->getExit();
4
Assuming the condition is false
2021 for (auto OLI : *LiveOuts) {
2022 OldLiveOuts.push_back(OLI);
2023 }
2024
2025 for (auto LI : OldLiveOuts) {
5
Assuming '__begin' is equal to '__end'
2026 DEBUG(dbgs() << "LiveOut: " << PrintReg(LI, TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "LiveOut: " <<
PrintReg(LI, TRI); } } while (false)
;
2027 if (!containsDef(CodeBB, InnerRegion, LI) ||
2028 (!IsSingleBB && (getDefInstr(LI)->getParent() == LRegion->getExit()))) {
2029 // If the register simly lives through the CodeBB, we don't have
2030 // to rewrite anything since the register is not defined in this
2031 // part of the code.
2032 DEBUG(dbgs() << "- through")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "- through"; } }
while (false)
;
2033 continue;
2034 }
2035 DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "\n"; } } while (
false)
;
2036 unsigned Reg = LI;
2037 if (/*!PHIInfo.isSource(Reg) &&*/ Reg != InnerRegion->getBBSelectRegOut()) {
2038 // If the register is live out, we do want to create a phi,
2039 // unless it is from the Exit block, becasuse in that case there
2040 // is already a PHI, and no need to create a new one.
2041
2042 // If the register is just a live out def and not part of a phi
2043 // chain, we need to create a PHI node to handle the if region,
2044 // and replace all uses outside of the region with the new dest
2045 // register, unless it is the outgoing BB select register. We have
2046 // already creaed phi nodes for these.
2047 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2048 unsigned PHIDestReg = MRI->createVirtualRegister(RegClass);
2049 unsigned IfSourceReg = MRI->createVirtualRegister(RegClass);
2050 // Create initializer, this value is never used, but is needed
2051 // to satisfy SSA.
2052 DEBUG(dbgs() << "Initializer for reg: " << PrintReg(Reg) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Initializer for reg: "
<< PrintReg(Reg) << "\n"; } } while (false)
;
2053 TII->materializeImmediate(*IfBB, IfBB->getFirstTerminator(), DebugLoc(),
2054 IfSourceReg, 0);
2055
2056 InnerRegion->replaceRegisterOutsideRegion(Reg, PHIDestReg, true, MRI);
2057 DEBUG(dbgs() << "Insert Non-Chained Live out PHI\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Insert Non-Chained Live out PHI\n"
; } } while (false)
;
2058 insertMergePHI(IfBB, InnerRegion->getExit(), MergeBB, PHIDestReg,
2059 IfSourceReg, Reg, true);
2060 }
2061 }
2062
2063 // Handle the chained definitions in PHIInfo, checking if this basic block
2064 // is a source block for a definition.
2065 SmallVector<unsigned, 4> Sources;
2066 if (PHIInfo.findSourcesFromMBB(CodeBB, Sources)) {
6
Assuming the condition is true
7
Taking true branch
2067 DEBUG(dbgs() << "Inserting PHI Live Out from BB#" << CodeBB->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting PHI Live Out from BB#"
<< CodeBB->getNumber() << "\n"; } } while (false
)
2068 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting PHI Live Out from BB#"
<< CodeBB->getNumber() << "\n"; } } while (false
)
;
2069 for (auto SI : Sources) {
8
Assuming '__begin' is not equal to '__end'
2070 unsigned DestReg;
9
'DestReg' declared without an initial value
2071 PHIInfo.findDest(SI, CodeBB, DestReg);
10
Calling 'PHILinearize::findDest'
13
Returning from 'PHILinearize::findDest'
2072 insertChainedPHI(IfBB, CodeBB, MergeBB, InnerRegion, DestReg, SI);
14
5th function call argument is an uninitialized value
2073 }
2074 DEBUG(dbgs() << "Insertion done.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Insertion done.\n"
; } } while (false)
;
2075 }
2076
2077 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2078}
2079
2080void AMDGPUMachineCFGStructurizer::prunePHIInfo(MachineBasicBlock *MBB) {
2081 DEBUG(dbgs() << "Before PHI Prune\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Before PHI Prune\n"
; } } while (false)
;
2082 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2083 SmallVector<std::tuple<unsigned, unsigned, MachineBasicBlock *>, 4>
2084 ElimiatedSources;
2085 for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
2086 ++DRI) {
2087
2088 unsigned DestReg = *DRI;
2089 auto SE = PHIInfo.sources_end(DestReg);
2090
2091 bool MBBContainsPHISource = false;
2092 // Check if there is a PHI source in this MBB
2093 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2094 unsigned SourceReg = (*SRI).first;
2095 MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2096 if (Def->getParent()->getParent() == MBB) {
2097 MBBContainsPHISource = true;
2098 }
2099 }
2100
2101 // If so, all other sources are useless since we know this block
2102 // is always executed when the region is executed.
2103 if (MBBContainsPHISource) {
2104 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2105 PHILinearize::PHISourceT Source = *SRI;
2106 unsigned SourceReg = Source.first;
2107 MachineBasicBlock *SourceMBB = Source.second;
2108 MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2109 if (Def->getParent()->getParent() != MBB) {
2110 ElimiatedSources.push_back(
2111 std::make_tuple(DestReg, SourceReg, SourceMBB));
2112 }
2113 }
2114 }
2115 }
2116
2117 // Remove the PHI sources that are in the given MBB
2118 for (auto &SourceInfo : ElimiatedSources) {
2119 PHIInfo.removeSource(std::get<0>(SourceInfo), std::get<1>(SourceInfo),
2120 std::get<2>(SourceInfo));
2121 }
2122 DEBUG(dbgs() << "After PHI Prune\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "After PHI Prune\n"
; } } while (false)
;
2123 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2124}
2125
2126void AMDGPUMachineCFGStructurizer::createEntryPHI(LinearizedRegion *CurrentRegion,
2127 unsigned DestReg) {
2128 MachineBasicBlock *Entry = CurrentRegion->getEntry();
2129 MachineBasicBlock *Exit = CurrentRegion->getExit();
2130
2131 DEBUG(dbgs() << "RegionExit: " << Exit->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "RegionExit: " <<
Exit->getNumber() << " Pred: " << (*(Entry->
pred_begin()))->getNumber() << "\n"; } } while (false
)
2132 << " Pred: " << (*(Entry->pred_begin()))->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "RegionExit: " <<
Exit->getNumber() << " Pred: " << (*(Entry->
pred_begin()))->getNumber() << "\n"; } } while (false
)
;
2133
2134 int NumSources = 0;
2135 auto SE = PHIInfo.sources_end(DestReg);
2136
2137 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2138 NumSources++;
2139 }
2140
2141 if (NumSources == 1) {
2142 auto SRI = PHIInfo.sources_begin(DestReg);
2143 unsigned SourceReg = (*SRI).first;
2144 replaceRegisterWith(DestReg, SourceReg);
2145 } else {
2146 const DebugLoc &DL = Entry->findDebugLoc(Entry->begin());
2147 MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL,
2148 TII->get(TargetOpcode::PHI), DestReg);
2149 DEBUG(dbgs() << "Entry PHI " << PrintReg(DestReg, TRI) << "<def> = PHI(")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Entry PHI " <<
PrintReg(DestReg, TRI) << "<def> = PHI("; } } while
(false)
;
2150
2151 unsigned CurrentBackedgeReg = 0;
2152
2153 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) {
2154 unsigned SourceReg = (*SRI).first;
2155
2156 if (CurrentRegion->contains((*SRI).second)) {
2157 if (CurrentBackedgeReg == 0) {
2158 CurrentBackedgeReg = SourceReg;
2159 } else {
2160 MachineInstr *PHIDefInstr = getDefInstr(SourceReg);
2161 MachineBasicBlock *PHIDefMBB = PHIDefInstr->getParent();
2162 const TargetRegisterClass *RegClass =
2163 MRI->getRegClass(CurrentBackedgeReg);
2164 unsigned NewBackedgeReg = MRI->createVirtualRegister(RegClass);
2165 MachineInstrBuilder BackedgePHI =
2166 BuildMI(*PHIDefMBB, PHIDefMBB->instr_begin(), DL,
2167 TII->get(TargetOpcode::PHI), NewBackedgeReg);
2168 BackedgePHI.addReg(CurrentBackedgeReg);
2169 BackedgePHI.addMBB(getPHIPred(*PHIDefInstr, 0));
2170 BackedgePHI.addReg(getPHISourceReg(*PHIDefInstr, 1));
2171 BackedgePHI.addMBB((*SRI).second);
2172 CurrentBackedgeReg = NewBackedgeReg;
2173 DEBUG(dbgs() << "Inserting backedge PHI: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" <<
getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " <<
PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#"
<< (*SRI).second->getNumber(); } } while (false)
2174 << PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" <<
getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " <<
PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#"
<< (*SRI).second->getNumber(); } } while (false)
2175 << PrintReg(CurrentBackedgeReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" <<
getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " <<
PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#"
<< (*SRI).second->getNumber(); } } while (false)
2176 << getPHIPred(*PHIDefInstr, 0)->getNumber() << ", "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" <<
getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " <<
PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#"
<< (*SRI).second->getNumber(); } } while (false)
2177 << PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" <<
getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " <<
PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#"
<< (*SRI).second->getNumber(); } } while (false)
2178 << ", BB#" << (*SRI).second->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Inserting backedge PHI: "
<< PrintReg(NewBackedgeReg, TRI) << "<def> = PHI("
<< PrintReg(CurrentBackedgeReg, TRI) << ", BB#" <<
getPHIPred(*PHIDefInstr, 0)->getNumber() << ", " <<
PrintReg(getPHISourceReg(*PHIDefInstr, 1), TRI) << ", BB#"
<< (*SRI).second->getNumber(); } } while (false)
;
2179 }
2180 } else {
2181 MIB.addReg(SourceReg);
2182 MIB.addMBB((*SRI).second);
2183 DEBUG(dbgs() << PrintReg(SourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << (*SRI).second->getNumber(
) << ", "; } } while (false)
2184 << (*SRI).second->getNumber() << ", ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(SourceReg
, TRI) << ", BB#" << (*SRI).second->getNumber(
) << ", "; } } while (false)
;
2185 }
2186 }
2187
2188 // Add the final backedge register source to the entry phi
2189 if (CurrentBackedgeReg != 0) {
2190 MIB.addReg(CurrentBackedgeReg);
2191 MIB.addMBB(Exit);
2192 DEBUG(dbgs() << PrintReg(CurrentBackedgeReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CurrentBackedgeReg
, TRI) << ", BB#" << Exit->getNumber() <<
")\n"; } } while (false)
2193 << Exit->getNumber() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(CurrentBackedgeReg
, TRI) << ", BB#" << Exit->getNumber() <<
")\n"; } } while (false)
;
2194 } else {
2195 DEBUG(dbgs() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << ")\n"; } } while
(false)
;
2196 }
2197 }
2198}
2199
2200void AMDGPUMachineCFGStructurizer::createEntryPHIs(LinearizedRegion *CurrentRegion) {
2201 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2202
2203 for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
2204 ++DRI) {
2205
2206 unsigned DestReg = *DRI;
2207 createEntryPHI(CurrentRegion, DestReg);
2208 }
2209 PHIInfo.clear();
2210}
2211
2212void AMDGPUMachineCFGStructurizer::replaceRegisterWith(unsigned Register,
2213 unsigned NewRegister) {
2214 assert(Register != NewRegister && "Cannot replace a reg with itself")((Register != NewRegister && "Cannot replace a reg with itself"
) ? static_cast<void> (0) : __assert_fail ("Register != NewRegister && \"Cannot replace a reg with itself\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2214, __PRETTY_FUNCTION__))
;
2215
2216 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Register),
2217 E = MRI->reg_end();
2218 I != E;) {
2219 MachineOperand &O = *I;
2220 ++I;
2221 if (TargetRegisterInfo::isPhysicalRegister(NewRegister)) {
2222 DEBUG(dbgs() << "Trying to substitute physical register: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
2223 << PrintReg(NewRegister, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
2224 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Trying to substitute physical register: "
<< PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
;
2225 llvm_unreachable("Cannot substitute physical registers")::llvm::llvm_unreachable_internal("Cannot substitute physical registers"
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2225)
;
2226 // We don't handle physical registers, but if we need to
2227 // in the future This is how we do it:
2228 // O.substPhysReg(NewRegister, *TRI);
2229 } else {
2230 DEBUG(dbgs() << "Replacing register: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register: "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
2231 << PrintReg(Register, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register: "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
2232 << " with "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register: "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
2233 << PrintReg(NewRegister, MRI->getTargetRegisterInfo())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register: "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
2234 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Replacing register: "
<< PrintReg(Register, MRI->getTargetRegisterInfo())
<< " with " << PrintReg(NewRegister, MRI->getTargetRegisterInfo
()) << "\n"; } } while (false)
;
2235 O.setReg(NewRegister);
2236 }
2237 }
2238 PHIInfo.deleteDef(Register);
2239
2240 getRegionMRT()->replaceLiveOutReg(Register, NewRegister);
2241
2242 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2243}
2244
2245void AMDGPUMachineCFGStructurizer::resolvePHIInfos(MachineBasicBlock *FunctionEntry) {
2246 DEBUG(dbgs() << "Resolve PHI Infos\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Resolve PHI Infos\n"
; } } while (false)
;
2247 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2248 for (auto DRI = PHIInfo.dests_begin(), DE = PHIInfo.dests_end(); DRI != DE;
2249 ++DRI) {
2250 unsigned DestReg = *DRI;
2251 DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "DestReg: " <<
PrintReg(DestReg, TRI) << "\n"; } } while (false)
;
2252 auto SRI = PHIInfo.sources_begin(DestReg);
2253 unsigned SourceReg = (*SRI).first;
2254 DEBUG(dbgs() << "DestReg: " << PrintReg(DestReg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "DestReg: " <<
PrintReg(DestReg, TRI) << " SourceReg: " << PrintReg
(SourceReg, TRI) << "\n"; } } while (false)
2255 << " SourceReg: " << PrintReg(SourceReg, TRI) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "DestReg: " <<
PrintReg(DestReg, TRI) << " SourceReg: " << PrintReg
(SourceReg, TRI) << "\n"; } } while (false)
;
2256
2257 assert(PHIInfo.sources_end(DestReg) == ++SRI &&((PHIInfo.sources_end(DestReg) == ++SRI && "More than one phi source in entry node"
) ? static_cast<void> (0) : __assert_fail ("PHIInfo.sources_end(DestReg) == ++SRI && \"More than one phi source in entry node\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2258, __PRETTY_FUNCTION__))
2258 "More than one phi source in entry node")((PHIInfo.sources_end(DestReg) == ++SRI && "More than one phi source in entry node"
) ? static_cast<void> (0) : __assert_fail ("PHIInfo.sources_end(DestReg) == ++SRI && \"More than one phi source in entry node\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2258, __PRETTY_FUNCTION__))
;
2259 replaceRegisterWith(DestReg, SourceReg);
2260 }
2261}
2262
2263static bool isFunctionEntryBlock(MachineBasicBlock *MBB) {
2264 return ((&(*(MBB->getParent()->begin()))) == MBB);
2265}
2266
2267MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
2268 MachineBasicBlock *MergeBB, MachineBasicBlock *CodeBB,
2269 LinearizedRegion *CurrentRegion, unsigned BBSelectRegIn,
2270 unsigned BBSelectRegOut) {
2271 if (isFunctionEntryBlock(CodeBB) && !CurrentRegion->getHasLoop()) {
2272 // Handle non-loop function entry block.
2273 // We need to allow loops to the entry block and then
2274 rewriteCodeBBTerminator(CodeBB, MergeBB, BBSelectRegOut);
2275 resolvePHIInfos(CodeBB);
2276 removeExternalCFGSuccessors(CodeBB);
2277 CodeBB->addSuccessor(MergeBB);
2278 CurrentRegion->addMBB(CodeBB);
2279 return nullptr;
2280 }
2281 if (CurrentRegion->getEntry() == CodeBB && !CurrentRegion->getHasLoop()) {
2282 // Handle non-loop region entry block.
2283 MachineFunction *MF = MergeBB->getParent();
2284 auto MergeIter = MergeBB->getIterator();
2285 auto CodeBBStartIter = CodeBB->getIterator();
2286 auto CodeBBEndIter = ++(CodeBB->getIterator());
2287 if (CodeBBEndIter != MergeIter) {
2288 MF->splice(MergeIter, CodeBBStartIter, CodeBBEndIter);
2289 }
2290 rewriteCodeBBTerminator(CodeBB, MergeBB, BBSelectRegOut);
2291 prunePHIInfo(CodeBB);
2292 createEntryPHIs(CurrentRegion);
2293 removeExternalCFGSuccessors(CodeBB);
2294 CodeBB->addSuccessor(MergeBB);
2295 CurrentRegion->addMBB(CodeBB);
2296 return nullptr;
2297 } else {
2298 // Handle internal block.
2299 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2300 unsigned CodeBBSelectReg = MRI->createVirtualRegister(RegClass);
2301 rewriteCodeBBTerminator(CodeBB, MergeBB, CodeBBSelectReg);
2302 bool IsRegionEntryBB = CurrentRegion->getEntry() == CodeBB;
2303 MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeBB, CodeBB, CodeBB,
2304 BBSelectRegIn, IsRegionEntryBB);
2305 CurrentRegion->addMBB(IfBB);
2306 // If this is the entry block we need to make the If block the new
2307 // linearized region entry.
2308 if (IsRegionEntryBB) {
2309 CurrentRegion->setEntry(IfBB);
2310
2311 if (CurrentRegion->getHasLoop()) {
2312 MachineBasicBlock *RegionExit = CurrentRegion->getExit();
2313 MachineBasicBlock *ETrueBB = nullptr;
2314 MachineBasicBlock *EFalseBB = nullptr;
2315 SmallVector<MachineOperand, 1> ECond;
2316
2317 const DebugLoc &DL = DebugLoc();
2318 TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
2319 TII->removeBranch(*RegionExit);
2320
2321 // We need to create a backedge if there is a loop
2322 unsigned Reg = TII->insertNE(
2323 RegionExit, RegionExit->instr_end(), DL,
2324 CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
2325 CurrentRegion->getRegionMRT()->getEntry()->getNumber());
2326 MachineOperand RegOp =
2327 MachineOperand::CreateReg(Reg, false, false, true);
2328 ArrayRef<MachineOperand> Cond(RegOp);
2329 DEBUG(dbgs() << "RegionExitReg: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "RegionExitReg: "
; } } while (false)
;
2330 DEBUG(Cond[0].print(dbgs(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Cond[0].print(dbgs(), TRI); } } while
(false)
;
2331 DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "\n"; } } while (
false)
;
2332 TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
2333 Cond, DebugLoc());
2334 RegionExit->addSuccessor(CurrentRegion->getEntry());
2335 }
2336 }
2337 CurrentRegion->addMBB(CodeBB);
2338 LinearizedRegion InnerRegion(CodeBB, MRI, TRI, PHIInfo);
2339
2340 InnerRegion.setParent(CurrentRegion);
2341 DEBUG(dbgs() << "Insert BB Select PHI (BB)\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Insert BB Select PHI (BB)\n"
; } } while (false)
;
2342 insertMergePHI(IfBB, CodeBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
2343 CodeBBSelectReg);
2344 InnerRegion.addMBB(MergeBB);
2345
2346 DEBUG(InnerRegion.print(dbgs(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { InnerRegion.print(dbgs(), TRI); }
} while (false)
;
2347 rewriteLiveOutRegs(IfBB, CodeBB, MergeBB, &InnerRegion, CurrentRegion);
2348 extractKilledPHIs(CodeBB);
2349 if (IsRegionEntryBB) {
2350 createEntryPHIs(CurrentRegion);
2351 }
2352 return IfBB;
2353 }
2354}
2355
2356MachineBasicBlock *AMDGPUMachineCFGStructurizer::createIfRegion(
2357 MachineBasicBlock *MergeBB, LinearizedRegion *InnerRegion,
2358 LinearizedRegion *CurrentRegion, MachineBasicBlock *SelectBB,
2359 unsigned BBSelectRegIn, unsigned BBSelectRegOut) {
2360 unsigned CodeBBSelectReg =
2361 InnerRegion->getRegionMRT()->getInnerOutputRegister();
2362 MachineBasicBlock *CodeEntryBB = InnerRegion->getEntry();
2363 MachineBasicBlock *CodeExitBB = InnerRegion->getExit();
2364 MachineBasicBlock *IfBB = createIfBlock(MergeBB, CodeEntryBB, CodeExitBB,
2365 SelectBB, BBSelectRegIn, true);
2366 CurrentRegion->addMBB(IfBB);
2367 bool isEntry = CurrentRegion->getEntry() == InnerRegion->getEntry();
1
Assuming the condition is false
2368 if (isEntry) {
2
Taking false branch
2369
2370 if (CurrentRegion->getHasLoop()) {
2371 MachineBasicBlock *RegionExit = CurrentRegion->getExit();
2372 MachineBasicBlock *ETrueBB = nullptr;
2373 MachineBasicBlock *EFalseBB = nullptr;
2374 SmallVector<MachineOperand, 1> ECond;
2375
2376 const DebugLoc &DL = DebugLoc();
2377 TII->analyzeBranch(*RegionExit, ETrueBB, EFalseBB, ECond);
2378 TII->removeBranch(*RegionExit);
2379
2380 // We need to create a backedge if there is a loop
2381 unsigned Reg =
2382 TII->insertNE(RegionExit, RegionExit->instr_end(), DL,
2383 CurrentRegion->getRegionMRT()->getInnerOutputRegister(),
2384 CurrentRegion->getRegionMRT()->getEntry()->getNumber());
2385 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2386 ArrayRef<MachineOperand> Cond(RegOp);
2387 DEBUG(dbgs() << "RegionExitReg: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "RegionExitReg: "
; } } while (false)
;
2388 DEBUG(Cond[0].print(dbgs(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Cond[0].print(dbgs(), TRI); } } while
(false)
;
2389 DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "\n"; } } while (
false)
;
2390 TII->insertBranch(*RegionExit, CurrentRegion->getEntry(), RegionExit,
2391 Cond, DebugLoc());
2392 RegionExit->addSuccessor(IfBB);
2393 }
2394 }
2395 CurrentRegion->addMBBs(InnerRegion);
2396 DEBUG(dbgs() << "Insert BB Select PHI (region)\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Insert BB Select PHI (region)\n"
; } } while (false)
;
2397 insertMergePHI(IfBB, CodeExitBB, MergeBB, BBSelectRegOut, BBSelectRegIn,
2398 CodeBBSelectReg);
2399
2400 rewriteLiveOutRegs(IfBB, /* CodeEntryBB */ CodeExitBB, MergeBB, InnerRegion,
3
Calling 'AMDGPUMachineCFGStructurizer::rewriteLiveOutRegs'
2401 CurrentRegion);
2402
2403 rewriteRegionEntryPHIs(InnerRegion, IfBB);
2404
2405 if (isEntry) {
2406 CurrentRegion->setEntry(IfBB);
2407 }
2408
2409 if (isEntry) {
2410 createEntryPHIs(CurrentRegion);
2411 }
2412
2413 return IfBB;
2414}
2415
2416void AMDGPUMachineCFGStructurizer::splitLoopPHI(MachineInstr &PHI,
2417 MachineBasicBlock *Entry,
2418 MachineBasicBlock *EntrySucc,
2419 LinearizedRegion *LRegion) {
2420 SmallVector<unsigned, 2> PHIRegionIndices;
2421 getPHIRegionIndices(LRegion, PHI, PHIRegionIndices);
2422
2423 assert(PHIRegionIndices.size() == 1)((PHIRegionIndices.size() == 1) ? static_cast<void> (0)
: __assert_fail ("PHIRegionIndices.size() == 1", "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2423, __PRETTY_FUNCTION__))
;
2424
2425 unsigned RegionIndex = PHIRegionIndices[0];
2426 unsigned RegionSourceReg = getPHISourceReg(PHI, RegionIndex);
2427 MachineBasicBlock *RegionSourceMBB = getPHIPred(PHI, RegionIndex);
2428 unsigned PHIDest = getPHIDestReg(PHI);
2429 unsigned PHISource = PHIDest;
2430 unsigned ReplaceReg;
2431
2432 if (shrinkPHI(PHI, PHIRegionIndices, &ReplaceReg)) {
2433 PHISource = ReplaceReg;
2434 }
2435
2436 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
2437 unsigned NewDestReg = MRI->createVirtualRegister(RegClass);
2438 LRegion->replaceRegisterInsideRegion(PHIDest, NewDestReg, false, MRI);
2439 MachineInstrBuilder MIB =
2440 BuildMI(*EntrySucc, EntrySucc->instr_begin(), PHI.getDebugLoc(),
2441 TII->get(TargetOpcode::PHI), NewDestReg);
2442 DEBUG(dbgs() << "Split Entry PHI " << PrintReg(NewDestReg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Split Entry PHI "
<< PrintReg(NewDestReg, TRI) << "<def> = PHI("
; } } while (false)
2443 << "<def> = PHI(")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Split Entry PHI "
<< PrintReg(NewDestReg, TRI) << "<def> = PHI("
; } } while (false)
;
2444 MIB.addReg(PHISource);
2445 MIB.addMBB(Entry);
2446 DEBUG(dbgs() << PrintReg(PHISource, TRI) << ", BB#" << Entry->getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << PrintReg(PHISource
, TRI) << ", BB#" << Entry->getNumber(); } } while
(false)
;
2447 MIB.addReg(RegionSourceReg);
2448 MIB.addMBB(RegionSourceMBB);
2449 DEBUG(dbgs() << " ," << PrintReg(RegionSourceReg, TRI) << ", BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " ," << PrintReg
(RegionSourceReg, TRI) << ", BB#" << RegionSourceMBB
->getNumber() << ")\n"; } } while (false)
2450 << RegionSourceMBB->getNumber() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << " ," << PrintReg
(RegionSourceReg, TRI) << ", BB#" << RegionSourceMBB
->getNumber() << ")\n"; } } while (false)
;
2451}
2452
2453void AMDGPUMachineCFGStructurizer::splitLoopPHIs(MachineBasicBlock *Entry,
2454 MachineBasicBlock *EntrySucc,
2455 LinearizedRegion *LRegion) {
2456 SmallVector<MachineInstr *, 2> PHIs;
2457 collectPHIs(Entry, PHIs);
2458
2459 for (auto PHII : PHIs) {
2460 splitLoopPHI(*PHII, Entry, EntrySucc, LRegion);
2461 }
2462}
2463
2464// Split the exit block so that we can insert a end control flow
2465MachineBasicBlock *
2466AMDGPUMachineCFGStructurizer::splitExit(LinearizedRegion *LRegion) {
2467 auto MRTRegion = LRegion->getRegionMRT();
2468 auto Exit = LRegion->getExit();
2469 auto MF = Exit->getParent();
2470 auto Succ = MRTRegion->getSucc();
2471
2472 auto NewExit = MF->CreateMachineBasicBlock();
2473 auto AfterExitIter = Exit->getIterator();
2474 AfterExitIter++;
2475 MF->insert(AfterExitIter, NewExit);
2476 Exit->removeSuccessor(Succ);
2477 Exit->addSuccessor(NewExit);
2478 NewExit->addSuccessor(Succ);
2479 insertUnconditionalBranch(NewExit, Succ);
2480 LRegion->addMBB(NewExit);
2481 LRegion->setExit(NewExit);
2482
2483 DEBUG(dbgs() << "Created new exit block: " << NewExit->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Created new exit block: "
<< NewExit->getNumber() << "\n"; } } while (false
)
;
2484
2485 // Replace any PHI Predecessors in the successor with NewExit
2486 for (auto &II : *Succ) {
2487 MachineInstr &Instr = II;
2488
2489 // If we are past the PHI instructions we are done
2490 if (!Instr.isPHI())
2491 break;
2492
2493 int numPreds = getPHINumInputs(Instr);
2494 for (int i = 0; i < numPreds; ++i) {
2495 auto Pred = getPHIPred(Instr, i);
2496 if (Pred == Exit) {
2497 setPhiPred(Instr, i, NewExit);
2498 }
2499 }
2500 }
2501
2502 return NewExit;
2503}
2504
2505static MachineBasicBlock *split(MachineBasicBlock::iterator I) {
2506 // Create the fall-through block.
2507 MachineBasicBlock *MBB = (*I).getParent();
2508 MachineFunction *MF = MBB->getParent();
2509 MachineBasicBlock *SuccMBB = MF->CreateMachineBasicBlock();
2510 auto MBBIter = ++(MBB->getIterator());
2511 MF->insert(MBBIter, SuccMBB);
2512 SuccMBB->transferSuccessorsAndUpdatePHIs(MBB);
2513 MBB->addSuccessor(SuccMBB);
2514
2515 // Splice the code over.
2516 SuccMBB->splice(SuccMBB->end(), MBB, I, MBB->end());
2517
2518 return SuccMBB;
2519}
2520
2521// Split the entry block separating PHI-nodes and the rest of the code
2522// This is needed to insert an initializer for the bb select register
2523// inloop regions.
2524
2525MachineBasicBlock *
2526AMDGPUMachineCFGStructurizer::splitEntry(LinearizedRegion *LRegion) {
2527 MachineBasicBlock *Entry = LRegion->getEntry();
2528 MachineBasicBlock *EntrySucc = split(Entry->getFirstNonPHI());
2529 MachineBasicBlock *Exit = LRegion->getExit();
2530
2531 DEBUG(dbgs() << "Split BB#" << Entry->getNumber() << " to BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Split BB#" <<
Entry->getNumber() << " to BB#" << Entry->
getNumber() << " -> BB#" << EntrySucc->getNumber
() << "\n"; } } while (false)
2532 << Entry->getNumber() << " -> BB#" << EntrySucc->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Split BB#" <<
Entry->getNumber() << " to BB#" << Entry->
getNumber() << " -> BB#" << EntrySucc->getNumber
() << "\n"; } } while (false)
2533 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Split BB#" <<
Entry->getNumber() << " to BB#" << Entry->
getNumber() << " -> BB#" << EntrySucc->getNumber
() << "\n"; } } while (false)
;
2534 LRegion->addMBB(EntrySucc);
2535
2536 // Make the backedge go to Entry Succ
2537 if (Exit->isSuccessor(Entry)) {
2538 Exit->removeSuccessor(Entry);
2539 }
2540 Exit->addSuccessor(EntrySucc);
2541 MachineInstr &Branch = *(Exit->instr_rbegin());
2542 for (auto &UI : Branch.uses()) {
2543 if (UI.isMBB() && UI.getMBB() == Entry) {
2544 UI.setMBB(EntrySucc);
2545 }
2546 }
2547
2548 splitLoopPHIs(Entry, EntrySucc, LRegion);
2549
2550 return EntrySucc;
2551}
2552
2553LinearizedRegion *
2554AMDGPUMachineCFGStructurizer::initLinearizedRegion(RegionMRT *Region) {
2555 LinearizedRegion *LRegion = Region->getLinearizedRegion();
2556 LRegion->initLiveOut(Region, MRI, TRI, PHIInfo);
2557 LRegion->setEntry(Region->getEntry());
2558 return LRegion;
2559}
2560
2561static void removeOldExitPreds(RegionMRT *Region) {
2562 MachineBasicBlock *Exit = Region->getSucc();
2563 if (Exit == nullptr) {
2564 return;
2565 }
2566 for (MachineBasicBlock::pred_iterator PI = Exit->pred_begin(),
2567 E = Exit->pred_end();
2568 PI != E; ++PI) {
2569 if (Region->contains(*PI)) {
2570 (*PI)->removeSuccessor(Exit);
2571 }
2572 }
2573}
2574
2575static bool mbbHasBackEdge(MachineBasicBlock *MBB,
2576 SmallPtrSet<MachineBasicBlock *, 8> &MBBs) {
2577 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
2578 if (MBBs.count(*SI) != 0) {
2579 return true;
2580 }
2581 }
2582 return false;
2583}
2584
2585static bool containsNewBackedge(MRT *Tree,
2586 SmallPtrSet<MachineBasicBlock *, 8> &MBBs) {
2587 // Need to traverse this in reverse since it is in post order.
2588 if (Tree == nullptr)
2589 return false;
2590
2591 if (Tree->isMBB()) {
2592 MachineBasicBlock *MBB = Tree->getMBBMRT()->getMBB();
2593 MBBs.insert(MBB);
2594 if (mbbHasBackEdge(MBB, MBBs)) {
2595 return true;
2596 }
2597 } else {
2598 RegionMRT *Region = Tree->getRegionMRT();
2599 SetVector<MRT *> *Children = Region->getChildren();
2600 for (auto CI = Children->rbegin(), CE = Children->rend(); CI != CE; ++CI) {
2601 if (containsNewBackedge(*CI, MBBs))
2602 return true;
2603 }
2604 }
2605 return false;
2606}
2607
2608static bool containsNewBackedge(RegionMRT *Region) {
2609 SmallPtrSet<MachineBasicBlock *, 8> MBBs;
2610 return containsNewBackedge(Region, MBBs);
2611}
2612
2613bool AMDGPUMachineCFGStructurizer::structurizeComplexRegion(RegionMRT *Region) {
2614 auto *LRegion = initLinearizedRegion(Region);
2615 LRegion->setHasLoop(containsNewBackedge(Region));
2616 MachineBasicBlock *LastMerge = createLinearizedExitBlock(Region);
2617 MachineBasicBlock *CurrentMerge = LastMerge;
2618 LRegion->addMBB(LastMerge);
2619 LRegion->setExit(LastMerge);
2620
2621 rewriteRegionExitPHIs(Region, LastMerge, LRegion);
2622 removeOldExitPreds(Region);
2623
2624 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2625
2626 SetVector<MRT *> *Children = Region->getChildren();
2627 DEBUG(dbgs() << "===========If Region Start===============\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "===========If Region Start===============\n"
; } } while (false)
;
2628 if (LRegion->getHasLoop()) {
2629 DEBUG(dbgs() << "Has Backedge: Yes\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Has Backedge: Yes\n"
; } } while (false)
;
2630 } else {
2631 DEBUG(dbgs() << "Has Backedge: No\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Has Backedge: No\n"
; } } while (false)
;
2632 }
2633
2634 unsigned BBSelectRegIn;
2635 unsigned BBSelectRegOut;
2636 for (auto CI = Children->begin(), CE = Children->end(); CI != CE; ++CI) {
2637 DEBUG(dbgs() << "CurrentRegion: \n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "CurrentRegion: \n"
; } } while (false)
;
2638 DEBUG(LRegion->print(dbgs(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { LRegion->print(dbgs(), TRI); }
} while (false)
;
2639
2640 auto CNI = CI;
2641 ++CNI;
2642
2643 MRT *Child = (*CI);
2644
2645 if (Child->isRegion()) {
2646
2647 LinearizedRegion *InnerLRegion =
2648 Child->getRegionMRT()->getLinearizedRegion();
2649 // We found the block is the exit of an inner region, we need
2650 // to put it in the current linearized region.
2651
2652 DEBUG(dbgs() << "Linearizing region: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Linearizing region: "
; } } while (false)
;
2653 DEBUG(InnerLRegion->print(dbgs(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { InnerLRegion->print(dbgs(), TRI
); } } while (false)
;
2654 DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "\n"; } } while (
false)
;
2655
2656 MachineBasicBlock *InnerEntry = InnerLRegion->getEntry();
2657 if ((&(*(InnerEntry->getParent()->begin()))) == InnerEntry) {
2658 // Entry has already been linearized, no need to do this region.
2659 unsigned OuterSelect = InnerLRegion->getBBSelectRegOut();
2660 unsigned InnerSelectReg =
2661 InnerLRegion->getRegionMRT()->getInnerOutputRegister();
2662 replaceRegisterWith(InnerSelectReg, OuterSelect),
2663 resolvePHIInfos(InnerEntry);
2664 if (!InnerLRegion->getExit()->isSuccessor(CurrentMerge))
2665 InnerLRegion->getExit()->addSuccessor(CurrentMerge);
2666 continue;
2667 }
2668
2669 BBSelectRegOut = Child->getBBSelectRegOut();
2670 BBSelectRegIn = Child->getBBSelectRegIn();
2671
2672 DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegIn: "
<< PrintReg(BBSelectRegIn, TRI) << "\n"; } } while
(false)
2673 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegIn: "
<< PrintReg(BBSelectRegIn, TRI) << "\n"; } } while
(false)
;
2674 DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegOut: "
<< PrintReg(BBSelectRegOut, TRI) << "\n"; } } while
(false)
2675 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegOut: "
<< PrintReg(BBSelectRegOut, TRI) << "\n"; } } while
(false)
;
2676
2677 MachineBasicBlock *IfEnd = CurrentMerge;
2678 CurrentMerge = createIfRegion(CurrentMerge, InnerLRegion, LRegion,
2679 Child->getRegionMRT()->getEntry(),
2680 BBSelectRegIn, BBSelectRegOut);
2681 TII->convertNonUniformIfRegion(CurrentMerge, IfEnd);
2682 } else {
2683 MachineBasicBlock *MBB = Child->getMBBMRT()->getMBB();
2684 DEBUG(dbgs() << "Linearizing block: " << MBB->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Linearizing block: "
<< MBB->getNumber() << "\n"; } } while (false
)
;
2685
2686 if (MBB == getSingleExitNode(*(MBB->getParent()))) {
2687 // If this is the exit block then we need to skip to the next.
2688 // The "in" register will be transferred to "out" in the next
2689 // iteration.
2690 continue;
2691 }
2692
2693 BBSelectRegOut = Child->getBBSelectRegOut();
2694 BBSelectRegIn = Child->getBBSelectRegIn();
2695
2696 DEBUG(dbgs() << "BBSelectRegIn: " << PrintReg(BBSelectRegIn, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegIn: "
<< PrintReg(BBSelectRegIn, TRI) << "\n"; } } while
(false)
2697 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegIn: "
<< PrintReg(BBSelectRegIn, TRI) << "\n"; } } while
(false)
;
2698 DEBUG(dbgs() << "BBSelectRegOut: " << PrintReg(BBSelectRegOut, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegOut: "
<< PrintReg(BBSelectRegOut, TRI) << "\n"; } } while
(false)
2699 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "BBSelectRegOut: "
<< PrintReg(BBSelectRegOut, TRI) << "\n"; } } while
(false)
;
2700
2701 MachineBasicBlock *IfEnd = CurrentMerge;
2702 // This is a basic block that is not part of an inner region, we
2703 // need to put it in the current linearized region.
2704 CurrentMerge = createIfRegion(CurrentMerge, MBB, LRegion, BBSelectRegIn,
2705 BBSelectRegOut);
2706 if (CurrentMerge) {
2707 TII->convertNonUniformIfRegion(CurrentMerge, IfEnd);
2708 }
2709
2710 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2711 }
2712 }
2713
2714 LRegion->removeFalseRegisterKills(MRI);
2715
2716 if (LRegion->getHasLoop()) {
2717 MachineBasicBlock *NewSucc = splitEntry(LRegion);
2718 if (isFunctionEntryBlock(LRegion->getEntry())) {
2719 resolvePHIInfos(LRegion->getEntry());
2720 }
2721 const DebugLoc &DL = NewSucc->findDebugLoc(NewSucc->getFirstNonPHI());
2722 unsigned InReg = LRegion->getBBSelectRegIn();
2723 unsigned InnerSelectReg =
2724 MRI->createVirtualRegister(MRI->getRegClass(InReg));
2725 unsigned NewInReg = MRI->createVirtualRegister(MRI->getRegClass(InReg));
2726 TII->materializeImmediate(*(LRegion->getEntry()),
2727 LRegion->getEntry()->getFirstTerminator(), DL,
2728 NewInReg, Region->getEntry()->getNumber());
2729 // Need to be careful about updating the registers inside the region.
2730 LRegion->replaceRegisterInsideRegion(InReg, InnerSelectReg, false, MRI);
2731 DEBUG(dbgs() << "Loop BBSelect Merge PHI:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Loop BBSelect Merge PHI:\n"
; } } while (false)
;
2732 insertMergePHI(LRegion->getEntry(), LRegion->getExit(), NewSucc,
2733 InnerSelectReg, NewInReg,
2734 LRegion->getRegionMRT()->getInnerOutputRegister());
2735 splitExit(LRegion);
2736 TII->convertNonUniformLoopRegion(NewSucc, LastMerge);
2737 }
2738
2739 if (Region->isRoot()) {
2740 TII->insertReturn(*LastMerge);
2741 }
2742
2743 DEBUG(Region->getEntry()->getParent()->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Region->getEntry()->getParent
()->dump(); } } while (false)
;
2744 DEBUG(LRegion->print(dbgs(), TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { LRegion->print(dbgs(), TRI); }
} while (false)
;
2745 DEBUG(PHIInfo.dump(MRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { PHIInfo.dump(MRI); } } while (false
)
;
2746
2747 DEBUG(dbgs() << "===========If Region End===============\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "===========If Region End===============\n"
; } } while (false)
;
2748
2749 Region->setLinearizedRegion(LRegion);
2750 return true;
2751}
2752
2753bool AMDGPUMachineCFGStructurizer::structurizeRegion(RegionMRT *Region) {
2754 if (false && regionIsSimpleIf(Region)) {
2755 transformSimpleIfRegion(Region);
2756 return true;
2757 } else if (regionIsSequence(Region)) {
2758 fixupRegionExits(Region);
2759 return false;
2760 } else {
2761 structurizeComplexRegion(Region);
2762 }
2763 return false;
2764}
2765
2766static int structurize_once = 0;
2767
2768bool AMDGPUMachineCFGStructurizer::structurizeRegions(RegionMRT *Region,
2769 bool isTopRegion) {
2770 bool Changed = false;
2771
2772 auto Children = Region->getChildren();
2773 for (auto CI : *Children) {
2774 if (CI->isRegion()) {
2775 Changed |= structurizeRegions(CI->getRegionMRT(), false);
2776 }
2777 }
2778
2779 if (structurize_once < 2 || true) {
2780 Changed |= structurizeRegion(Region);
2781 structurize_once++;
2782 }
2783 return Changed;
2784}
2785
2786void AMDGPUMachineCFGStructurizer::initFallthroughMap(MachineFunction &MF) {
2787 DEBUG(dbgs() << "Fallthrough Map:\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Fallthrough Map:\n"
; } } while (false)
;
2788 for (auto &MBBI : MF) {
2789 MachineBasicBlock *MBB = MBBI.getFallThrough();
2790 if (MBB != nullptr) {
2791 DEBUG(dbgs() << "Fallthrough: " << MBBI.getNumber() << " -> "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Fallthrough: " <<
MBBI.getNumber() << " -> " << MBB->getNumber
() << "\n"; } } while (false)
2792 << MBB->getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Fallthrough: " <<
MBBI.getNumber() << " -> " << MBB->getNumber
() << "\n"; } } while (false)
;
2793 }
2794 FallthroughMap[&MBBI] = MBB;
2795 }
2796}
2797
2798void AMDGPUMachineCFGStructurizer::createLinearizedRegion(RegionMRT *Region,
2799 unsigned SelectOut) {
2800 LinearizedRegion *LRegion = new LinearizedRegion();
2801 if (SelectOut) {
2802 LRegion->addLiveOut(SelectOut);
2803 DEBUG(dbgs() << "Add LiveOut (BBSelect): " << PrintReg(SelectOut, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (BBSelect): "
<< PrintReg(SelectOut, TRI) << "\n"; } } while (
false)
2804 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "Add LiveOut (BBSelect): "
<< PrintReg(SelectOut, TRI) << "\n"; } } while (
false)
;
2805 }
2806 LRegion->setRegionMRT(Region);
2807 Region->setLinearizedRegion(LRegion);
2808 LRegion->setParent(Region->getParent()
2809 ? Region->getParent()->getLinearizedRegion()
2810 : nullptr);
2811}
2812
2813unsigned
2814AMDGPUMachineCFGStructurizer::initializeSelectRegisters(MRT *MRT, unsigned SelectOut,
2815 MachineRegisterInfo *MRI,
2816 const SIInstrInfo *TII) {
2817 if (MRT->isRegion()) {
2818 RegionMRT *Region = MRT->getRegionMRT();
2819 Region->setBBSelectRegOut(SelectOut);
2820 unsigned InnerSelectOut = createBBSelectReg(TII, MRI);
2821
2822 // Fixme: Move linearization creation to the original spot
2823 createLinearizedRegion(Region, SelectOut);
2824
2825 for (auto CI = Region->getChildren()->begin(),
2826 CE = Region->getChildren()->end();
2827 CI != CE; ++CI) {
2828 InnerSelectOut =
2829 initializeSelectRegisters((*CI), InnerSelectOut, MRI, TII);
2830 }
2831 MRT->setBBSelectRegIn(InnerSelectOut);
2832 return InnerSelectOut;
2833 } else {
2834 MRT->setBBSelectRegOut(SelectOut);
2835 unsigned NewSelectIn = createBBSelectReg(TII, MRI);
2836 MRT->setBBSelectRegIn(NewSelectIn);
2837 return NewSelectIn;
2838 }
2839}
2840
2841static void checkRegOnlyPHIInputs(MachineFunction &MF) {
2842 for (auto &MBBI : MF) {
2843 for (MachineBasicBlock::instr_iterator I = MBBI.instr_begin(),
2844 E = MBBI.instr_end();
2845 I != E; ++I) {
2846 MachineInstr &Instr = *I;
2847 if (Instr.isPHI()) {
2848 int numPreds = getPHINumInputs(Instr);
2849 for (int i = 0; i < numPreds; ++i) {
2850 assert(Instr.getOperand(i * 2 + 1).isReg() &&((Instr.getOperand(i * 2 + 1).isReg() && "PHI Operand not a register"
) ? static_cast<void> (0) : __assert_fail ("Instr.getOperand(i * 2 + 1).isReg() && \"PHI Operand not a register\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2851, __PRETTY_FUNCTION__))
2851 "PHI Operand not a register")((Instr.getOperand(i * 2 + 1).isReg() && "PHI Operand not a register"
) ? static_cast<void> (0) : __assert_fail ("Instr.getOperand(i * 2 + 1).isReg() && \"PHI Operand not a register\""
, "/build/llvm-toolchain-snapshot-6.0~svn316259/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp"
, 2851, __PRETTY_FUNCTION__))
;
2852 }
2853 }
2854 }
2855 }
2856}
2857
2858bool AMDGPUMachineCFGStructurizer::runOnMachineFunction(MachineFunction &MF) {
2859 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
2860 const SIInstrInfo *TII = ST.getInstrInfo();
2861 TRI = ST.getRegisterInfo();
2862 MRI = &(MF.getRegInfo());
2863 initFallthroughMap(MF);
2864
2865 checkRegOnlyPHIInputs(MF);
2866 DEBUG(dbgs() << "----STRUCTURIZER START----\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "----STRUCTURIZER START----\n"
; } } while (false)
;
2867 DEBUG(MF.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { MF.dump(); } } while (false)
;
2868
2869 Regions = &(getAnalysis<MachineRegionInfoPass>().getRegionInfo());
2870 DEBUG(Regions->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { Regions->dump(); } } while (false
)
;
2871
2872 RegionMRT *RTree = MRT::buildMRT(MF, Regions, TII, MRI);
2873 setRegionMRT(RTree);
2874 initializeSelectRegisters(RTree, 0, MRI, TII);
2875 DEBUG(RTree->dump(TRI))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { RTree->dump(TRI); } } while (
false)
;
2876 bool result = structurizeRegions(RTree, true);
2877 delete RTree;
2878 DEBUG(dbgs() << "----STRUCTURIZER END----\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("amdgpucfgstructurizer")) { dbgs() << "----STRUCTURIZER END----\n"
; } } while (false)
;
2879 initFallthroughMap(MF);
2880 return result;
2881}
2882
2883char AMDGPUMachineCFGStructurizerID = AMDGPUMachineCFGStructurizer::ID;
2884
2885INITIALIZE_PASS_BEGIN(AMDGPUMachineCFGStructurizer, "amdgpu-machine-cfg-structurizer",static void *initializeAMDGPUMachineCFGStructurizerPassOnce(PassRegistry
&Registry) {
2886 "AMDGPU Machine CFG Structurizer", false, false)static void *initializeAMDGPUMachineCFGStructurizerPassOnce(PassRegistry
&Registry) {
2887INITIALIZE_PASS_DEPENDENCY(MachineRegionInfoPass)initializeMachineRegionInfoPassPass(Registry);
2888INITIALIZE_PASS_END(AMDGPUMachineCFGStructurizer, "amdgpu-machine-cfg-structurizer",PassInfo *PI = new PassInfo( "AMDGPU Machine CFG Structurizer"
, "amdgpu-machine-cfg-structurizer", &AMDGPUMachineCFGStructurizer
::ID, PassInfo::NormalCtor_t(callDefaultCtor<AMDGPUMachineCFGStructurizer
>), false, false); Registry.registerPass(*PI, true); return
PI; } static llvm::once_flag InitializeAMDGPUMachineCFGStructurizerPassFlag
; void llvm::initializeAMDGPUMachineCFGStructurizerPass(PassRegistry
&Registry) { llvm::call_once(InitializeAMDGPUMachineCFGStructurizerPassFlag
, initializeAMDGPUMachineCFGStructurizerPassOnce, std::ref(Registry
)); }
2889 "AMDGPU Machine CFG Structurizer", false, false)PassInfo *PI = new PassInfo( "AMDGPU Machine CFG Structurizer"
, "amdgpu-machine-cfg-structurizer", &AMDGPUMachineCFGStructurizer
::ID, PassInfo::NormalCtor_t(callDefaultCtor<AMDGPUMachineCFGStructurizer
>), false, false); Registry.registerPass(*PI, true); return
PI; } static llvm::once_flag InitializeAMDGPUMachineCFGStructurizerPassFlag
; void llvm::initializeAMDGPUMachineCFGStructurizerPass(PassRegistry
&Registry) { llvm::call_once(InitializeAMDGPUMachineCFGStructurizerPassFlag
, initializeAMDGPUMachineCFGStructurizerPassOnce, std::ref(Registry
)); }
2890
2891FunctionPass *llvm::createAMDGPUMachineCFGStructurizerPass() {
2892 return new AMDGPUMachineCFGStructurizer();
2893}