Bug Summary

File:lib/Target/ARM/ARMAsmPrinter.cpp
Warning:line 366, column 14
The left operand of '==' is a garbage value

Annotated Source Code

/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp

1//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMAsmPrinter.h"
16#include "ARM.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMMachineFunctionInfo.h"
19#include "ARMTargetMachine.h"
20#include "ARMTargetObjectFile.h"
21#include "InstPrinter/ARMInstPrinter.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "MCTargetDesc/ARMMCExpr.h"
24#include "llvm/ADT/SetVector.h"
25#include "llvm/ADT/SmallString.h"
26#include "llvm/BinaryFormat/COFF.h"
27#include "llvm/BinaryFormat/ELF.h"
28#include "llvm/CodeGen/MachineFunctionPass.h"
29#include "llvm/CodeGen/MachineJumpTableInfo.h"
30#include "llvm/CodeGen/MachineModuleInfoImpls.h"
31#include "llvm/IR/Constants.h"
32#include "llvm/IR/DataLayout.h"
33#include "llvm/IR/DebugInfo.h"
34#include "llvm/IR/Mangler.h"
35#include "llvm/IR/Module.h"
36#include "llvm/IR/Type.h"
37#include "llvm/MC/MCAsmInfo.h"
38#include "llvm/MC/MCAssembler.h"
39#include "llvm/MC/MCContext.h"
40#include "llvm/MC/MCELFStreamer.h"
41#include "llvm/MC/MCInst.h"
42#include "llvm/MC/MCInstBuilder.h"
43#include "llvm/MC/MCObjectStreamer.h"
44#include "llvm/MC/MCSectionMachO.h"
45#include "llvm/MC/MCStreamer.h"
46#include "llvm/MC/MCSymbol.h"
47#include "llvm/Support/ARMBuildAttributes.h"
48#include "llvm/Support/Debug.h"
49#include "llvm/Support/ErrorHandling.h"
50#include "llvm/Support/TargetParser.h"
51#include "llvm/Support/TargetRegistry.h"
52#include "llvm/Support/raw_ostream.h"
53#include "llvm/Target/TargetMachine.h"
54#include <cctype>
55using namespace llvm;
56
57#define DEBUG_TYPE"asm-printer" "asm-printer"
58
59ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
60 std::unique_ptr<MCStreamer> Streamer)
61 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
62 InConstantPool(false), OptimizationGoals(-1) {}
63
64void ARMAsmPrinter::EmitFunctionBodyEnd() {
65 // Make sure to terminate any constant pools that were at the end
66 // of the function.
67 if (!InConstantPool)
68 return;
69 InConstantPool = false;
70 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
71}
72
73void ARMAsmPrinter::EmitFunctionEntryLabel() {
74 if (AFI->isThumbFunction()) {
75 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
76 OutStreamer->EmitThumbFunc(CurrentFnSym);
77 } else {
78 OutStreamer->EmitAssemblerFlag(MCAF_Code32);
79 }
80 OutStreamer->EmitLabel(CurrentFnSym);
81}
82
83void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
84 uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!")(static_cast <bool> (Size && "C++ constructor pointer had zero size!"
) ? void (0) : __assert_fail ("Size && \"C++ constructor pointer had zero size!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 85, __extension__ __PRETTY_FUNCTION__))
;
86
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!")(static_cast <bool> (GV && "C++ constructor pointer was not a GlobalValue!"
) ? void (0) : __assert_fail ("GV && \"C++ constructor pointer was not a GlobalValue!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 88, __extension__ __PRETTY_FUNCTION__))
;
89
90 const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
91 ARMII::MO_NO_FLAG),
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
95 OutContext);
96
97 OutStreamer->EmitValue(E, Size);
98}
99
100void ARMAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
101 if (PromotedGlobals.count(GV))
102 // The global was promoted into a constant pool. It should not be emitted.
103 return;
104 AsmPrinter::EmitGlobalVariable(GV);
105}
106
107/// runOnMachineFunction - This uses the EmitInstruction()
108/// method to print assembly for each instruction.
109///
110bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
111 AFI = MF.getInfo<ARMFunctionInfo>();
112 MCP = MF.getConstantPool();
113 Subtarget = &MF.getSubtarget<ARMSubtarget>();
114
115 SetupMachineFunction(MF);
116 const Function* F = MF.getFunction();
117 const TargetMachine& TM = MF.getTarget();
118
119 // Collect all globals that had their storage promoted to a constant pool.
120 // Functions are emitted before variables, so this accumulates promoted
121 // globals from all functions in PromotedGlobals.
122 for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
123 PromotedGlobals.insert(GV);
124
125 // Calculate this function's optimization goal.
126 unsigned OptimizationGoal;
127 if (F->hasFnAttribute(Attribute::OptimizeNone))
128 // For best debugging illusion, speed and small size sacrificed
129 OptimizationGoal = 6;
130 else if (F->optForMinSize())
131 // Aggressively for small size, speed and debug illusion sacrificed
132 OptimizationGoal = 4;
133 else if (F->optForSize())
134 // For small size, but speed and debugging illusion preserved
135 OptimizationGoal = 3;
136 else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
137 // Aggressively for speed, small size and debug illusion sacrificed
138 OptimizationGoal = 2;
139 else if (TM.getOptLevel() > CodeGenOpt::None)
140 // For speed, but small size and good debug illusion preserved
141 OptimizationGoal = 1;
142 else // TM.getOptLevel() == CodeGenOpt::None
143 // For good debugging, but speed and small size preserved
144 OptimizationGoal = 5;
145
146 // Combine a new optimization goal with existing ones.
147 if (OptimizationGoals == -1) // uninitialized goals
148 OptimizationGoals = OptimizationGoal;
149 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
150 OptimizationGoals = 0;
151
152 if (Subtarget->isTargetCOFF()) {
153 bool Internal = F->hasInternalLinkage();
154 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
155 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
156 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
157
158 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
159 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
160 OutStreamer->EmitCOFFSymbolType(Type);
161 OutStreamer->EndCOFFSymbolDef();
162 }
163
164 // Emit the rest of the function body.
165 EmitFunctionBody();
166
167 // Emit the XRay table for this function.
168 emitXRayTable();
169
170 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
171 // These are created per function, rather than per TU, since it's
172 // relatively easy to exceed the thumb branch range within a TU.
173 if (! ThumbIndirectPads.empty()) {
174 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
175 EmitAlignment(1);
176 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
177 OutStreamer->EmitLabel(TIP.second);
178 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
179 .addReg(TIP.first)
180 // Add predicate operands.
181 .addImm(ARMCC::AL)
182 .addReg(0));
183 }
184 ThumbIndirectPads.clear();
185 }
186
187 // We didn't modify anything.
188 return false;
189}
190
191void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
192 raw_ostream &O) {
193 const MachineOperand &MO = MI->getOperand(OpNum);
194 unsigned TF = MO.getTargetFlags();
195
196 switch (MO.getType()) {
197 default: llvm_unreachable("<unknown operand type>")::llvm::llvm_unreachable_internal("<unknown operand type>"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 197)
;
198 case MachineOperand::MO_Register: {
199 unsigned Reg = MO.getReg();
200 assert(TargetRegisterInfo::isPhysicalRegister(Reg))(static_cast <bool> (TargetRegisterInfo::isPhysicalRegister
(Reg)) ? void (0) : __assert_fail ("TargetRegisterInfo::isPhysicalRegister(Reg)"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 200, __extension__ __PRETTY_FUNCTION__))
;
201 assert(!MO.getSubReg() && "Subregs should be eliminated!")(static_cast <bool> (!MO.getSubReg() && "Subregs should be eliminated!"
) ? void (0) : __assert_fail ("!MO.getSubReg() && \"Subregs should be eliminated!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 201, __extension__ __PRETTY_FUNCTION__))
;
202 if(ARM::GPRPairRegClass.contains(Reg)) {
203 const MachineFunction &MF = *MI->getParent()->getParent();
204 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
205 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
206 }
207 O << ARMInstPrinter::getRegisterName(Reg);
208 break;
209 }
210 case MachineOperand::MO_Immediate: {
211 int64_t Imm = MO.getImm();
212 O << '#';
213 if (TF == ARMII::MO_LO16)
214 O << ":lower16:";
215 else if (TF == ARMII::MO_HI16)
216 O << ":upper16:";
217 O << Imm;
218 break;
219 }
220 case MachineOperand::MO_MachineBasicBlock:
221 MO.getMBB()->getSymbol()->print(O, MAI);
222 return;
223 case MachineOperand::MO_GlobalAddress: {
224 const GlobalValue *GV = MO.getGlobal();
225 if (TF & ARMII::MO_LO16)
226 O << ":lower16:";
227 else if (TF & ARMII::MO_HI16)
228 O << ":upper16:";
229 GetARMGVSymbol(GV, TF)->print(O, MAI);
230
231 printOffset(MO.getOffset(), O);
232 break;
233 }
234 case MachineOperand::MO_ConstantPoolIndex:
235 if (Subtarget->genExecuteOnly())
236 llvm_unreachable("execute-only should not generate constant pools")::llvm::llvm_unreachable_internal("execute-only should not generate constant pools"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 236)
;
237 GetCPISymbol(MO.getIndex())->print(O, MAI);
238 break;
239 }
240}
241
242//===--------------------------------------------------------------------===//
243
244MCSymbol *ARMAsmPrinter::
245GetARMJTIPICJumpTableLabel(unsigned uid) const {
246 const DataLayout &DL = getDataLayout();
247 SmallString<60> Name;
248 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
249 << getFunctionNumber() << '_' << uid;
250 return OutContext.getOrCreateSymbol(Name);
251}
252
253bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
254 unsigned AsmVariant, const char *ExtraCode,
255 raw_ostream &O) {
256 // Does this asm operand have a single letter operand modifier?
257 if (ExtraCode && ExtraCode[0]) {
1
Assuming 'ExtraCode' is non-null
2
Assuming the condition is true
3
Taking true branch
258 if (ExtraCode[1] != 0) return true; // Unknown modifier.
4
Assuming the condition is false
5
Taking false branch
259
260 switch (ExtraCode[0]) {
6
Control jumps to 'case 81:' at line 339
261 default:
262 // See if this is a generic print operand
263 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
264 case 'a': // Print as a memory address.
265 if (MI->getOperand(OpNum).isReg()) {
266 O << "["
267 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
268 << "]";
269 return false;
270 }
271 LLVM_FALLTHROUGH[[clang::fallthrough]];
272 case 'c': // Don't print "#" before an immediate operand.
273 if (!MI->getOperand(OpNum).isImm())
274 return true;
275 O << MI->getOperand(OpNum).getImm();
276 return false;
277 case 'P': // Print a VFP double precision register.
278 case 'q': // Print a NEON quad precision register.
279 printOperand(MI, OpNum, O);
280 return false;
281 case 'y': // Print a VFP single precision register as indexed double.
282 if (MI->getOperand(OpNum).isReg()) {
283 unsigned Reg = MI->getOperand(OpNum).getReg();
284 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
285 // Find the 'd' register that has this 's' register as a sub-register,
286 // and determine the lane number.
287 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
288 if (!ARM::DPRRegClass.contains(*SR))
289 continue;
290 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
291 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
292 return false;
293 }
294 }
295 return true;
296 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
297 if (!MI->getOperand(OpNum).isImm())
298 return true;
299 O << ~(MI->getOperand(OpNum).getImm());
300 return false;
301 case 'L': // The low 16 bits of an immediate constant.
302 if (!MI->getOperand(OpNum).isImm())
303 return true;
304 O << (MI->getOperand(OpNum).getImm() & 0xffff);
305 return false;
306 case 'M': { // A register range suitable for LDM/STM.
307 if (!MI->getOperand(OpNum).isReg())
308 return true;
309 const MachineOperand &MO = MI->getOperand(OpNum);
310 unsigned RegBegin = MO.getReg();
311 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
312 // already got the operands in registers that are operands to the
313 // inline asm statement.
314 O << "{";
315 if (ARM::GPRPairRegClass.contains(RegBegin)) {
316 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
318 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
319 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
320 }
321 O << ARMInstPrinter::getRegisterName(RegBegin);
322
323 // FIXME: The register allocator not only may not have given us the
324 // registers in sequence, but may not be in ascending registers. This
325 // will require changes in the register allocator that'll need to be
326 // propagated down here if the operands change.
327 unsigned RegOps = OpNum + 1;
328 while (MI->getOperand(RegOps).isReg()) {
329 O << ", "
330 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
331 RegOps++;
332 }
333
334 O << "}";
335
336 return false;
337 }
338 case 'R': // The most significant register of a pair.
339 case 'Q': { // The least significant register of a pair.
340 if (OpNum == 0)
7
Assuming 'OpNum' is not equal to 0
8
Taking false branch
341 return true;
342 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
343 if (!FlagsOP.isImm())
9
Taking false branch
344 return true;
345 unsigned Flags = FlagsOP.getImm();
346
347 // This operand may not be the one that actually provides the register. If
348 // it's tied to a previous one then we should refer instead to that one
349 // for registers and their classes.
350 unsigned TiedIdx;
351 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
10
Taking false branch
352 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
353 unsigned OpFlags = MI->getOperand(OpNum).getImm();
354 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
355 }
356 Flags = MI->getOperand(OpNum).getImm();
357
358 // Later code expects OpNum to be pointing at the register rather than
359 // the flags.
360 OpNum += 1;
361 }
362
363 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
364 unsigned RC;
11
'RC' declared without an initial value
365 InlineAsm::hasRegClassConstraint(Flags, RC);
12
Calling 'InlineAsm::hasRegClassConstraint'
16
Returning from 'InlineAsm::hasRegClassConstraint'
366 if (RC == ARM::GPRPairRegClassID) {
17
The left operand of '==' is a garbage value
367 if (NumVals != 1)
368 return true;
369 const MachineOperand &MO = MI->getOperand(OpNum);
370 if (!MO.isReg())
371 return true;
372 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
373 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
374 ARM::gsub_0 : ARM::gsub_1);
375 O << ARMInstPrinter::getRegisterName(Reg);
376 return false;
377 }
378 if (NumVals != 2)
379 return true;
380 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
381 if (RegOp >= MI->getNumOperands())
382 return true;
383 const MachineOperand &MO = MI->getOperand(RegOp);
384 if (!MO.isReg())
385 return true;
386 unsigned Reg = MO.getReg();
387 O << ARMInstPrinter::getRegisterName(Reg);
388 return false;
389 }
390
391 case 'e': // The low doubleword register of a NEON quad register.
392 case 'f': { // The high doubleword register of a NEON quad register.
393 if (!MI->getOperand(OpNum).isReg())
394 return true;
395 unsigned Reg = MI->getOperand(OpNum).getReg();
396 if (!ARM::QPRRegClass.contains(Reg))
397 return true;
398 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
399 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
400 ARM::dsub_0 : ARM::dsub_1);
401 O << ARMInstPrinter::getRegisterName(SubReg);
402 return false;
403 }
404
405 // This modifier is not yet supported.
406 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
407 return true;
408 case 'H': { // The highest-numbered register of a pair.
409 const MachineOperand &MO = MI->getOperand(OpNum);
410 if (!MO.isReg())
411 return true;
412 const MachineFunction &MF = *MI->getParent()->getParent();
413 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
414 unsigned Reg = MO.getReg();
415 if(!ARM::GPRPairRegClass.contains(Reg))
416 return false;
417 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
418 O << ARMInstPrinter::getRegisterName(Reg);
419 return false;
420 }
421 }
422 }
423
424 printOperand(MI, OpNum, O);
425 return false;
426}
427
428bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
429 unsigned OpNum, unsigned AsmVariant,
430 const char *ExtraCode,
431 raw_ostream &O) {
432 // Does this asm operand have a single letter operand modifier?
433 if (ExtraCode && ExtraCode[0]) {
434 if (ExtraCode[1] != 0) return true; // Unknown modifier.
435
436 switch (ExtraCode[0]) {
437 case 'A': // A memory operand for a VLD1/VST1 instruction.
438 default: return true; // Unknown modifier.
439 case 'm': // The base register of a memory operand.
440 if (!MI->getOperand(OpNum).isReg())
441 return true;
442 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
443 return false;
444 }
445 }
446
447 const MachineOperand &MO = MI->getOperand(OpNum);
448 assert(MO.isReg() && "unexpected inline asm memory operand")(static_cast <bool> (MO.isReg() && "unexpected inline asm memory operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"unexpected inline asm memory operand\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 448, __extension__ __PRETTY_FUNCTION__))
;
449 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
450 return false;
451}
452
453static bool isThumb(const MCSubtargetInfo& STI) {
454 return STI.getFeatureBits()[ARM::ModeThumb];
455}
456
457void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
458 const MCSubtargetInfo *EndInfo) const {
459 // If either end mode is unknown (EndInfo == NULL) or different than
460 // the start mode, then restore the start mode.
461 const bool WasThumb = isThumb(StartInfo);
462 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
463 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
464 }
465}
466
467void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
468 const Triple &TT = TM.getTargetTriple();
469 // Use unified assembler syntax.
470 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
471
472 // Emit ARM Build Attributes
473 if (TT.isOSBinFormatELF())
474 emitAttributes();
475
476 // Use the triple's architecture and subarchitecture to determine
477 // if we're thumb for the purposes of the top level code16 assembler
478 // flag.
479 if (!M.getModuleInlineAsm().empty() && TT.isThumb())
480 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
481}
482
483static void
484emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
485 MachineModuleInfoImpl::StubValueTy &MCSym) {
486 // L_foo$stub:
487 OutStreamer.EmitLabel(StubLabel);
488 // .indirect_symbol _foo
489 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
490
491 if (MCSym.getInt())
492 // External to current translation unit.
493 OutStreamer.EmitIntValue(0, 4/*size*/);
494 else
495 // Internal to current translation unit.
496 //
497 // When we place the LSDA into the TEXT section, the type info
498 // pointers need to be indirect and pc-rel. We accomplish this by
499 // using NLPs; however, sometimes the types are local to the file.
500 // We need to fill in the value for the NLP in those cases.
501 OutStreamer.EmitValue(
502 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
503 4 /*size*/);
504}
505
506
507void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
508 const Triple &TT = TM.getTargetTriple();
509 if (TT.isOSBinFormatMachO()) {
510 // All darwin targets use mach-o.
511 const TargetLoweringObjectFileMachO &TLOFMacho =
512 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
513 MachineModuleInfoMachO &MMIMacho =
514 MMI->getObjFileInfo<MachineModuleInfoMachO>();
515
516 // Output non-lazy-pointers for external and common global variables.
517 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
518
519 if (!Stubs.empty()) {
520 // Switch with ".non_lazy_symbol_pointer" directive.
521 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
522 EmitAlignment(2);
523
524 for (auto &Stub : Stubs)
525 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
526
527 Stubs.clear();
528 OutStreamer->AddBlankLine();
529 }
530
531 Stubs = MMIMacho.GetThreadLocalGVStubList();
532 if (!Stubs.empty()) {
533 // Switch with ".non_lazy_symbol_pointer" directive.
534 OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
535 EmitAlignment(2);
536
537 for (auto &Stub : Stubs)
538 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
539
540 Stubs.clear();
541 OutStreamer->AddBlankLine();
542 }
543
544 // Funny Darwin hack: This flag tells the linker that no global symbols
545 // contain code that falls through to other global symbols (e.g. the obvious
546 // implementation of multiple entry points). If this doesn't occur, the
547 // linker can safely perform dead code stripping. Since LLVM never
548 // generates code that does this, it is always safe to set.
549 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
550 }
551
552 if (TT.isOSBinFormatCOFF()) {
553 const auto &TLOF =
554 static_cast<const TargetLoweringObjectFileCOFF &>(getObjFileLowering());
555
556 std::string Flags;
557 raw_string_ostream OS(Flags);
558
559 for (const auto &Function : M)
560 TLOF.emitLinkerFlagsForGlobal(OS, &Function);
561 for (const auto &Global : M.globals())
562 TLOF.emitLinkerFlagsForGlobal(OS, &Global);
563 for (const auto &Alias : M.aliases())
564 TLOF.emitLinkerFlagsForGlobal(OS, &Alias);
565
566 OS.flush();
567
568 // Output collected flags
569 if (!Flags.empty()) {
570 OutStreamer->SwitchSection(TLOF.getDrectveSection());
571 OutStreamer->EmitBytes(Flags);
572 }
573 }
574
575 // The last attribute to be emitted is ABI_optimization_goals
576 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
577 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
578
579 if (OptimizationGoals > 0 &&
580 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
581 Subtarget->isTargetMuslAEABI()))
582 ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
583 OptimizationGoals = -1;
584
585 ATS.finishAttributeSection();
586}
587
588//===----------------------------------------------------------------------===//
589// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
590// FIXME:
591// The following seem like one-off assembler flags, but they actually need
592// to appear in the .ARM.attributes section in ELF.
593// Instead of subclassing the MCELFStreamer, we do the work here.
594
595// Returns true if all functions have the same function attribute value.
596// It also returns true when the module has no functions.
597static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
598 StringRef Value) {
599 return !any_of(M, [&](const Function &F) {
600 return F.getFnAttribute(Attr).getValueAsString() != Value;
601 });
602}
603
604void ARMAsmPrinter::emitAttributes() {
605 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
606 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
607
608 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
609
610 ATS.switchVendor("aeabi");
611
612 // Compute ARM ELF Attributes based on the default subtarget that
613 // we'd have constructed. The existing ARM behavior isn't LTO clean
614 // anyhow.
615 // FIXME: For ifunc related functions we could iterate over and look
616 // for a feature string that doesn't match the default one.
617 const Triple &TT = TM.getTargetTriple();
618 StringRef CPU = TM.getTargetCPU();
619 StringRef FS = TM.getTargetFeatureString();
620 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
621 if (!FS.empty()) {
622 if (!ArchFS.empty())
623 ArchFS = (Twine(ArchFS) + "," + FS).str();
624 else
625 ArchFS = FS;
626 }
627 const ARMBaseTargetMachine &ATM =
628 static_cast<const ARMBaseTargetMachine &>(TM);
629 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
630
631 // Emit build attributes for the available hardware.
632 ATS.emitTargetAttributes(STI);
633
634 // RW data addressing.
635 if (isPositionIndependent()) {
636 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
637 ARMBuildAttrs::AddressRWPCRel);
638 } else if (STI.isRWPI()) {
639 // RWPI specific attributes.
640 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
641 ARMBuildAttrs::AddressRWSBRel);
642 }
643
644 // RO data addressing.
645 if (isPositionIndependent() || STI.isROPI()) {
646 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
647 ARMBuildAttrs::AddressROPCRel);
648 }
649
650 // GOT use.
651 if (isPositionIndependent()) {
652 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
653 ARMBuildAttrs::AddressGOT);
654 } else {
655 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
656 ARMBuildAttrs::AddressDirect);
657 }
658
659 // Set FP Denormals.
660 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
661 "denormal-fp-math",
662 "preserve-sign") ||
663 TM.Options.FPDenormalMode == FPDenormal::PreserveSign)
664 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
665 ARMBuildAttrs::PreserveFPSign);
666 else if (checkFunctionsAttributeConsistency(*MMI->getModule(),
667 "denormal-fp-math",
668 "positive-zero") ||
669 TM.Options.FPDenormalMode == FPDenormal::PositiveZero)
670 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
671 ARMBuildAttrs::PositiveZero);
672 else if (!TM.Options.UnsafeFPMath)
673 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
674 ARMBuildAttrs::IEEEDenormals);
675 else {
676 if (!STI.hasVFP2()) {
677 // When the target doesn't have an FPU (by design or
678 // intention), the assumptions made on the software support
679 // mirror that of the equivalent hardware support *if it
680 // existed*. For v7 and better we indicate that denormals are
681 // flushed preserving sign, and for V6 we indicate that
682 // denormals are flushed to positive zero.
683 if (STI.hasV7Ops())
684 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
685 ARMBuildAttrs::PreserveFPSign);
686 } else if (STI.hasVFP3()) {
687 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
688 // the sign bit of the zero matches the sign bit of the input or
689 // result that is being flushed to zero.
690 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
691 ARMBuildAttrs::PreserveFPSign);
692 }
693 // For VFPv2 implementations it is implementation defined as
694 // to whether denormals are flushed to positive zero or to
695 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
696 // LLVM has chosen to flush this to positive zero (most likely for
697 // GCC compatibility), so that's the chosen value here (the
698 // absence of its emission implies zero).
699 }
700
701 // Set FP exceptions and rounding
702 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
703 "no-trapping-math", "true") ||
704 TM.Options.NoTrappingFPMath)
705 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
706 ARMBuildAttrs::Not_Allowed);
707 else if (!TM.Options.UnsafeFPMath) {
708 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
709
710 // If the user has permitted this code to choose the IEEE 754
711 // rounding at run-time, emit the rounding attribute.
712 if (TM.Options.HonorSignDependentRoundingFPMathOption)
713 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
714 }
715
716 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
717 // equivalent of GCC's -ffinite-math-only flag.
718 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
719 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
720 ARMBuildAttrs::Allowed);
721 else
722 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
723 ARMBuildAttrs::AllowIEEE754);
724
725 // FIXME: add more flags to ARMBuildAttributes.h
726 // 8-bytes alignment stuff.
727 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
728 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
729
730 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
731 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
732 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
733
734 // FIXME: To support emitting this build attribute as GCC does, the
735 // -mfp16-format option and associated plumbing must be
736 // supported. For now the __fp16 type is exposed by default, so this
737 // attribute should be emitted with value 1.
738 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
739 ARMBuildAttrs::FP16FormatIEEE);
740
741 if (MMI) {
742 if (const Module *SourceModule = MMI->getModule()) {
743 // ABI_PCS_wchar_t to indicate wchar_t width
744 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
745 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
746 SourceModule->getModuleFlag("wchar_size"))) {
747 int WCharWidth = WCharWidthValue->getZExtValue();
748 assert((WCharWidth == 2 || WCharWidth == 4) &&(static_cast <bool> ((WCharWidth == 2 || WCharWidth == 4
) && "wchar_t width must be 2 or 4 bytes") ? void (0)
: __assert_fail ("(WCharWidth == 2 || WCharWidth == 4) && \"wchar_t width must be 2 or 4 bytes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 749, __extension__ __PRETTY_FUNCTION__))
749 "wchar_t width must be 2 or 4 bytes")(static_cast <bool> ((WCharWidth == 2 || WCharWidth == 4
) && "wchar_t width must be 2 or 4 bytes") ? void (0)
: __assert_fail ("(WCharWidth == 2 || WCharWidth == 4) && \"wchar_t width must be 2 or 4 bytes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 749, __extension__ __PRETTY_FUNCTION__))
;
750 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
751 }
752
753 // ABI_enum_size to indicate enum width
754 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
755 // (all enums contain a value needing 32 bits to encode).
756 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
757 SourceModule->getModuleFlag("min_enum_size"))) {
758 int EnumWidth = EnumWidthValue->getZExtValue();
759 assert((EnumWidth == 1 || EnumWidth == 4) &&(static_cast <bool> ((EnumWidth == 1 || EnumWidth == 4)
&& "Minimum enum width must be 1 or 4 bytes") ? void
(0) : __assert_fail ("(EnumWidth == 1 || EnumWidth == 4) && \"Minimum enum width must be 1 or 4 bytes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 760, __extension__ __PRETTY_FUNCTION__))
760 "Minimum enum width must be 1 or 4 bytes")(static_cast <bool> ((EnumWidth == 1 || EnumWidth == 4)
&& "Minimum enum width must be 1 or 4 bytes") ? void
(0) : __assert_fail ("(EnumWidth == 1 || EnumWidth == 4) && \"Minimum enum width must be 1 or 4 bytes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 760, __extension__ __PRETTY_FUNCTION__))
;
761 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
762 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
763 }
764 }
765 }
766
767 // We currently do not support using R9 as the TLS pointer.
768 if (STI.isRWPI())
769 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
770 ARMBuildAttrs::R9IsSB);
771 else if (STI.isR9Reserved())
772 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
773 ARMBuildAttrs::R9Reserved);
774 else
775 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
776 ARMBuildAttrs::R9IsGPR);
777}
778
779//===----------------------------------------------------------------------===//
780
781static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
782 unsigned LabelId, MCContext &Ctx) {
783
784 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
785 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
786 return Label;
787}
788
789static MCSymbolRefExpr::VariantKind
790getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
791 switch (Modifier) {
792 case ARMCP::no_modifier:
793 return MCSymbolRefExpr::VK_None;
794 case ARMCP::TLSGD:
795 return MCSymbolRefExpr::VK_TLSGD;
796 case ARMCP::TPOFF:
797 return MCSymbolRefExpr::VK_TPOFF;
798 case ARMCP::GOTTPOFF:
799 return MCSymbolRefExpr::VK_GOTTPOFF;
800 case ARMCP::SBREL:
801 return MCSymbolRefExpr::VK_ARM_SBREL;
802 case ARMCP::GOT_PREL:
803 return MCSymbolRefExpr::VK_ARM_GOT_PREL;
804 case ARMCP::SECREL:
805 return MCSymbolRefExpr::VK_SECREL;
806 }
807 llvm_unreachable("Invalid ARMCPModifier!")::llvm::llvm_unreachable_internal("Invalid ARMCPModifier!", "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 807)
;
808}
809
810MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
811 unsigned char TargetFlags) {
812 if (Subtarget->isTargetMachO()) {
813 bool IsIndirect =
814 (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
815
816 if (!IsIndirect)
817 return getSymbol(GV);
818
819 // FIXME: Remove this when Darwin transition to @GOT like syntax.
820 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
821 MachineModuleInfoMachO &MMIMachO =
822 MMI->getObjFileInfo<MachineModuleInfoMachO>();
823 MachineModuleInfoImpl::StubValueTy &StubSym =
824 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
825 : MMIMachO.getGVStubEntry(MCSym);
826
827 if (!StubSym.getPointer())
828 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
829 !GV->hasInternalLinkage());
830 return MCSym;
831 } else if (Subtarget->isTargetCOFF()) {
832 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 833, __extension__ __PRETTY_FUNCTION__))
833 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 833, __extension__ __PRETTY_FUNCTION__))
;
834
835 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
836 if (!IsIndirect)
837 return getSymbol(GV);
838
839 SmallString<128> Name;
840 Name = "__imp_";
841 getNameWithPrefix(Name, GV);
842
843 return OutContext.getOrCreateSymbol(Name);
844 } else if (Subtarget->isTargetELF()) {
845 return getSymbol(GV);
846 }
847 llvm_unreachable("unexpected target")::llvm::llvm_unreachable_internal("unexpected target", "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 847)
;
848}
849
850void ARMAsmPrinter::
851EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
852 const DataLayout &DL = getDataLayout();
853 int Size = DL.getTypeAllocSize(MCPV->getType());
854
855 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
856
857 if (ACPV->isPromotedGlobal()) {
858 // This constant pool entry is actually a global whose storage has been
859 // promoted into the constant pool. This global may be referenced still
860 // by debug information, and due to the way AsmPrinter is set up, the debug
861 // info is immutable by the time we decide to promote globals to constant
862 // pools. Because of this, we need to ensure we emit a symbol for the global
863 // with private linkage (the default) so debug info can refer to it.
864 //
865 // However, if this global is promoted into several functions we must ensure
866 // we don't try and emit duplicate symbols!
867 auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
868 for (const auto *GV : ACPC->promotedGlobals()) {
869 if (!EmittedPromotedGlobalLabels.count(GV)) {
870 MCSymbol *GVSym = getSymbol(GV);
871 OutStreamer->EmitLabel(GVSym);
872 EmittedPromotedGlobalLabels.insert(GV);
873 }
874 }
875 return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
876 }
877
878 MCSymbol *MCSym;
879 if (ACPV->isLSDA()) {
880 MCSym = getCurExceptionSym();
881 } else if (ACPV->isBlockAddress()) {
882 const BlockAddress *BA =
883 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
884 MCSym = GetBlockAddressSymbol(BA);
885 } else if (ACPV->isGlobalValue()) {
886 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
887
888 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
889 // flag the global as MO_NONLAZY.
890 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
891 MCSym = GetARMGVSymbol(GV, TF);
892 } else if (ACPV->isMachineBasicBlock()) {
893 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
894 MCSym = MBB->getSymbol();
895 } else {
896 assert(ACPV->isExtSymbol() && "unrecognized constant pool value")(static_cast <bool> (ACPV->isExtSymbol() && "unrecognized constant pool value"
) ? void (0) : __assert_fail ("ACPV->isExtSymbol() && \"unrecognized constant pool value\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 896, __extension__ __PRETTY_FUNCTION__))
;
897 auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
898 MCSym = GetExternalSymbolSymbol(Sym);
899 }
900
901 // Create an MCSymbol for the reference.
902 const MCExpr *Expr =
903 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
904 OutContext);
905
906 if (ACPV->getPCAdjustment()) {
907 MCSymbol *PCLabel =
908 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
909 ACPV->getLabelId(), OutContext);
910 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
911 PCRelExpr =
912 MCBinaryExpr::createAdd(PCRelExpr,
913 MCConstantExpr::create(ACPV->getPCAdjustment(),
914 OutContext),
915 OutContext);
916 if (ACPV->mustAddCurrentAddress()) {
917 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
918 // label, so just emit a local label end reference that instead.
919 MCSymbol *DotSym = OutContext.createTempSymbol();
920 OutStreamer->EmitLabel(DotSym);
921 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
922 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
923 }
924 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
925 }
926 OutStreamer->EmitValue(Expr, Size);
927}
928
929void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
930 const MachineOperand &MO1 = MI->getOperand(1);
931 unsigned JTI = MO1.getIndex();
932
933 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
934 // ARM mode tables.
935 EmitAlignment(2);
936
937 // Emit a label for the jump table.
938 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
939 OutStreamer->EmitLabel(JTISymbol);
940
941 // Mark the jump table as data-in-code.
942 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
943
944 // Emit each entry of the table.
945 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
948
949 for (MachineBasicBlock *MBB : JTBBs) {
950 // Construct an MCExpr for the entry. We want a value of the form:
951 // (BasicBlockAddr - TableBeginAddr)
952 //
953 // For example, a table with entries jumping to basic blocks BB0 and BB1
954 // would look like:
955 // LJTI_0_0:
956 // .word (LBB0 - LJTI_0_0)
957 // .word (LBB1 - LJTI_0_0)
958 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
959
960 if (isPositionIndependent() || Subtarget->isROPI())
961 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
962 OutContext),
963 OutContext);
964 // If we're generating a table of Thumb addresses in static relocation
965 // model, we need to add one to keep interworking correctly.
966 else if (AFI->isThumbFunction())
967 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
968 OutContext);
969 OutStreamer->EmitValue(Expr, 4);
970 }
971 // Mark the end of jump table data-in-code region.
972 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
973}
974
975void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
976 const MachineOperand &MO1 = MI->getOperand(1);
977 unsigned JTI = MO1.getIndex();
978
979 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
980 // ARM mode tables.
981 EmitAlignment(2);
982
983 // Emit a label for the jump table.
984 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
985 OutStreamer->EmitLabel(JTISymbol);
986
987 // Emit each entry of the table.
988 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
989 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
990 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
991
992 for (MachineBasicBlock *MBB : JTBBs) {
993 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
994 OutContext);
995 // If this isn't a TBB or TBH, the entries are direct branch instructions.
996 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
997 .addExpr(MBBSymbolExpr)
998 .addImm(ARMCC::AL)
999 .addReg(0));
1000 }
1001}
1002
1003void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
1004 unsigned OffsetWidth) {
1005 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width")(static_cast <bool> ((OffsetWidth == 1 || OffsetWidth ==
2) && "invalid tbb/tbh width") ? void (0) : __assert_fail
("(OffsetWidth == 1 || OffsetWidth == 2) && \"invalid tbb/tbh width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1005, __extension__ __PRETTY_FUNCTION__))
;
1006 const MachineOperand &MO1 = MI->getOperand(1);
1007 unsigned JTI = MO1.getIndex();
1008
1009 if (Subtarget->isThumb1Only())
1010 EmitAlignment(2);
1011
1012 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1013 OutStreamer->EmitLabel(JTISymbol);
1014
1015 // Emit each entry of the table.
1016 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1017 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1018 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1019
1020 // Mark the jump table as data-in-code.
1021 OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1022 : MCDR_DataRegionJT16);
1023
1024 for (auto MBB : JTBBs) {
1025 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1026 OutContext);
1027 // Otherwise it's an offset from the dispatch instruction. Construct an
1028 // MCExpr for the entry. We want a value of the form:
1029 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1030 //
1031 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1032 // would look like:
1033 // LJTI_0_0:
1034 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1035 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1036 // where LCPI0_0 is a label defined just before the TBB instruction using
1037 // this table.
1038 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1039 const MCExpr *Expr = MCBinaryExpr::createAdd(
1040 MCSymbolRefExpr::create(TBInstPC, OutContext),
1041 MCConstantExpr::create(4, OutContext), OutContext);
1042 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1043 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1044 OutContext);
1045 OutStreamer->EmitValue(Expr, OffsetWidth);
1046 }
1047 // Mark the end of jump table data-in-code region. 32-bit offsets use
1048 // actual branch instructions here, so we don't mark those as a data-region
1049 // at all.
1050 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1051
1052 // Make sure the next instruction is 2-byte aligned.
1053 EmitAlignment(1);
1054}
1055
1056void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1057 assert(MI->getFlag(MachineInstr::FrameSetup) &&(static_cast <bool> (MI->getFlag(MachineInstr::FrameSetup
) && "Only instruction which are involved into frame setup code are allowed"
) ? void (0) : __assert_fail ("MI->getFlag(MachineInstr::FrameSetup) && \"Only instruction which are involved into frame setup code are allowed\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1058, __extension__ __PRETTY_FUNCTION__))
1058 "Only instruction which are involved into frame setup code are allowed")(static_cast <bool> (MI->getFlag(MachineInstr::FrameSetup
) && "Only instruction which are involved into frame setup code are allowed"
) ? void (0) : __assert_fail ("MI->getFlag(MachineInstr::FrameSetup) && \"Only instruction which are involved into frame setup code are allowed\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1058, __extension__ __PRETTY_FUNCTION__))
;
1059
1060 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1061 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1062 const MachineFunction &MF = *MI->getParent()->getParent();
1063 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1064 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1065
1066 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1067 unsigned Opc = MI->getOpcode();
1068 unsigned SrcReg, DstReg;
1069
1070 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1071 // Two special cases:
1072 // 1) tPUSH does not have src/dst regs.
1073 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1074 // load. Yes, this is pretty fragile, but for now I don't see better
1075 // way... :(
1076 SrcReg = DstReg = ARM::SP;
1077 } else {
1078 SrcReg = MI->getOperand(1).getReg();
1079 DstReg = MI->getOperand(0).getReg();
1080 }
1081
1082 // Try to figure out the unwinding opcode out of src / dst regs.
1083 if (MI->mayStore()) {
1084 // Register saves.
1085 assert(DstReg == ARM::SP &&(static_cast <bool> (DstReg == ARM::SP && "Only stack pointer as a destination reg is supported"
) ? void (0) : __assert_fail ("DstReg == ARM::SP && \"Only stack pointer as a destination reg is supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1086, __extension__ __PRETTY_FUNCTION__))
1086 "Only stack pointer as a destination reg is supported")(static_cast <bool> (DstReg == ARM::SP && "Only stack pointer as a destination reg is supported"
) ? void (0) : __assert_fail ("DstReg == ARM::SP && \"Only stack pointer as a destination reg is supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1086, __extension__ __PRETTY_FUNCTION__))
;
1087
1088 SmallVector<unsigned, 4> RegList;
1089 // Skip src & dst reg, and pred ops.
1090 unsigned StartOp = 2 + 2;
1091 // Use all the operands.
1092 unsigned NumOffset = 0;
1093
1094 switch (Opc) {
1095 default:
1096 MI->print(errs());
1097 llvm_unreachable("Unsupported opcode for unwinding information")::llvm::llvm_unreachable_internal("Unsupported opcode for unwinding information"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1097)
;
1098 case ARM::tPUSH:
1099 // Special case here: no src & dst reg, but two extra imp ops.
1100 StartOp = 2; NumOffset = 2;
1101 LLVM_FALLTHROUGH[[clang::fallthrough]];
1102 case ARM::STMDB_UPD:
1103 case ARM::t2STMDB_UPD:
1104 case ARM::VSTMDDB_UPD:
1105 assert(SrcReg == ARM::SP &&(static_cast <bool> (SrcReg == ARM::SP && "Only stack pointer as a source reg is supported"
) ? void (0) : __assert_fail ("SrcReg == ARM::SP && \"Only stack pointer as a source reg is supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1106, __extension__ __PRETTY_FUNCTION__))
1106 "Only stack pointer as a source reg is supported")(static_cast <bool> (SrcReg == ARM::SP && "Only stack pointer as a source reg is supported"
) ? void (0) : __assert_fail ("SrcReg == ARM::SP && \"Only stack pointer as a source reg is supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1106, __extension__ __PRETTY_FUNCTION__))
;
1107 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1108 i != NumOps; ++i) {
1109 const MachineOperand &MO = MI->getOperand(i);
1110 // Actually, there should never be any impdef stuff here. Skip it
1111 // temporary to workaround PR11902.
1112 if (MO.isImplicit())
1113 continue;
1114 RegList.push_back(MO.getReg());
1115 }
1116 break;
1117 case ARM::STR_PRE_IMM:
1118 case ARM::STR_PRE_REG:
1119 case ARM::t2STR_PRE:
1120 assert(MI->getOperand(2).getReg() == ARM::SP &&(static_cast <bool> (MI->getOperand(2).getReg() == ARM
::SP && "Only stack pointer as a source reg is supported"
) ? void (0) : __assert_fail ("MI->getOperand(2).getReg() == ARM::SP && \"Only stack pointer as a source reg is supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1121, __extension__ __PRETTY_FUNCTION__))
1121 "Only stack pointer as a source reg is supported")(static_cast <bool> (MI->getOperand(2).getReg() == ARM
::SP && "Only stack pointer as a source reg is supported"
) ? void (0) : __assert_fail ("MI->getOperand(2).getReg() == ARM::SP && \"Only stack pointer as a source reg is supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1121, __extension__ __PRETTY_FUNCTION__))
;
1122 RegList.push_back(SrcReg);
1123 break;
1124 }
1125 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1126 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1127 } else {
1128 // Changes of stack / frame pointer.
1129 if (SrcReg == ARM::SP) {
1130 int64_t Offset = 0;
1131 switch (Opc) {
1132 default:
1133 MI->print(errs());
1134 llvm_unreachable("Unsupported opcode for unwinding information")::llvm::llvm_unreachable_internal("Unsupported opcode for unwinding information"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1134)
;
1135 case ARM::MOVr:
1136 case ARM::tMOVr:
1137 Offset = 0;
1138 break;
1139 case ARM::ADDri:
1140 case ARM::t2ADDri:
1141 Offset = -MI->getOperand(2).getImm();
1142 break;
1143 case ARM::SUBri:
1144 case ARM::t2SUBri:
1145 Offset = MI->getOperand(2).getImm();
1146 break;
1147 case ARM::tSUBspi:
1148 Offset = MI->getOperand(2).getImm()*4;
1149 break;
1150 case ARM::tADDspi:
1151 case ARM::tADDrSPi:
1152 Offset = -MI->getOperand(2).getImm()*4;
1153 break;
1154 case ARM::tLDRpci: {
1155 // Grab the constpool index and check, whether it corresponds to
1156 // original or cloned constpool entry.
1157 unsigned CPI = MI->getOperand(1).getIndex();
1158 const MachineConstantPool *MCP = MF.getConstantPool();
1159 if (CPI >= MCP->getConstants().size())
1160 CPI = AFI.getOriginalCPIdx(CPI);
1161 assert(CPI != -1U && "Invalid constpool index")(static_cast <bool> (CPI != -1U && "Invalid constpool index"
) ? void (0) : __assert_fail ("CPI != -1U && \"Invalid constpool index\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1161, __extension__ __PRETTY_FUNCTION__))
;
1162
1163 // Derive the actual offset.
1164 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1165 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry")(static_cast <bool> (!CPE.isMachineConstantPoolEntry() &&
"Invalid constpool entry") ? void (0) : __assert_fail ("!CPE.isMachineConstantPoolEntry() && \"Invalid constpool entry\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1165, __extension__ __PRETTY_FUNCTION__))
;
1166 // FIXME: Check for user, it should be "add" instruction!
1167 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1168 break;
1169 }
1170 }
1171
1172 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1173 if (DstReg == FramePtr && FramePtr != ARM::SP)
1174 // Set-up of the frame pointer. Positive values correspond to "add"
1175 // instruction.
1176 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1177 else if (DstReg == ARM::SP) {
1178 // Change of SP by an offset. Positive values correspond to "sub"
1179 // instruction.
1180 ATS.emitPad(Offset);
1181 } else {
1182 // Move of SP to a register. Positive values correspond to an "add"
1183 // instruction.
1184 ATS.emitMovSP(DstReg, -Offset);
1185 }
1186 }
1187 } else if (DstReg == ARM::SP) {
1188 MI->print(errs());
1189 llvm_unreachable("Unsupported opcode for unwinding information")::llvm::llvm_unreachable_internal("Unsupported opcode for unwinding information"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1189)
;
1190 }
1191 else {
1192 MI->print(errs());
1193 llvm_unreachable("Unsupported opcode for unwinding information")::llvm::llvm_unreachable_internal("Unsupported opcode for unwinding information"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1193)
;
1194 }
1195 }
1196}
1197
1198// Simple pseudo-instructions have their lowering (with expansion to real
1199// instructions) auto-generated.
1200#include "ARMGenMCPseudoLowering.inc"
1201
1202void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1203 const DataLayout &DL = getDataLayout();
1204 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1205 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1206
1207 const MachineFunction &MF = *MI->getParent()->getParent();
1208 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
1209 unsigned FramePtr = STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
1210
1211 // If we just ended a constant pool, mark it as such.
1212 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1213 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1214 InConstantPool = false;
1215 }
1216
1217 // Emit unwinding stuff for frame-related instructions
1218 if (Subtarget->isTargetEHABICompatible() &&
1219 MI->getFlag(MachineInstr::FrameSetup))
1220 EmitUnwindingInstruction(MI);
1221
1222 // Do any auto-generated pseudo lowerings.
1223 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1224 return;
1225
1226 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&(static_cast <bool> (!convertAddSubFlagsOpcode(MI->getOpcode
()) && "Pseudo flag setting opcode should be expanded early"
) ? void (0) : __assert_fail ("!convertAddSubFlagsOpcode(MI->getOpcode()) && \"Pseudo flag setting opcode should be expanded early\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1227, __extension__ __PRETTY_FUNCTION__))
1227 "Pseudo flag setting opcode should be expanded early")(static_cast <bool> (!convertAddSubFlagsOpcode(MI->getOpcode
()) && "Pseudo flag setting opcode should be expanded early"
) ? void (0) : __assert_fail ("!convertAddSubFlagsOpcode(MI->getOpcode()) && \"Pseudo flag setting opcode should be expanded early\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1227, __extension__ __PRETTY_FUNCTION__))
;
1228
1229 // Check for manual lowerings.
1230 unsigned Opc = MI->getOpcode();
1231 switch (Opc) {
1232 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass")::llvm::llvm_unreachable_internal("Should be lowered by thumb2it pass"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1232)
;
1233 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing")::llvm::llvm_unreachable_internal("Should be handled by generic printing"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1233)
;
1234 case ARM::LEApcrel:
1235 case ARM::tLEApcrel:
1236 case ARM::t2LEApcrel: {
1237 // FIXME: Need to also handle globals and externals
1238 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1239 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1240 ARM::t2LEApcrel ? ARM::t2ADR
1241 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1242 : ARM::ADR))
1243 .addReg(MI->getOperand(0).getReg())
1244 .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1245 // Add predicate operands.
1246 .addImm(MI->getOperand(2).getImm())
1247 .addReg(MI->getOperand(3).getReg()));
1248 return;
1249 }
1250 case ARM::LEApcrelJT:
1251 case ARM::tLEApcrelJT:
1252 case ARM::t2LEApcrelJT: {
1253 MCSymbol *JTIPICSymbol =
1254 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1255 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1256 ARM::t2LEApcrelJT ? ARM::t2ADR
1257 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1258 : ARM::ADR))
1259 .addReg(MI->getOperand(0).getReg())
1260 .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1261 // Add predicate operands.
1262 .addImm(MI->getOperand(2).getImm())
1263 .addReg(MI->getOperand(3).getReg()));
1264 return;
1265 }
1266 // Darwin call instructions are just normal call instructions with different
1267 // clobber semantics (they clobber R9).
1268 case ARM::BX_CALL: {
1269 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1270 .addReg(ARM::LR)
1271 .addReg(ARM::PC)
1272 // Add predicate operands.
1273 .addImm(ARMCC::AL)
1274 .addReg(0)
1275 // Add 's' bit operand (always reg0 for this)
1276 .addReg(0));
1277
1278 assert(Subtarget->hasV4TOps())(static_cast <bool> (Subtarget->hasV4TOps()) ? void (
0) : __assert_fail ("Subtarget->hasV4TOps()", "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1278, __extension__ __PRETTY_FUNCTION__))
;
1279 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1280 .addReg(MI->getOperand(0).getReg()));
1281 return;
1282 }
1283 case ARM::tBX_CALL: {
1284 if (Subtarget->hasV5TOps())
1285 llvm_unreachable("Expected BLX to be selected for v5t+")::llvm::llvm_unreachable_internal("Expected BLX to be selected for v5t+"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1285)
;
1286
1287 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1288 // that the saved lr has its LSB set correctly (the arch doesn't
1289 // have blx).
1290 // So here we generate a bl to a small jump pad that does bx rN.
1291 // The jump pads are emitted after the function body.
1292
1293 unsigned TReg = MI->getOperand(0).getReg();
1294 MCSymbol *TRegSym = nullptr;
1295 for (std::pair<unsigned, MCSymbol *> &TIP : ThumbIndirectPads) {
1296 if (TIP.first == TReg) {
1297 TRegSym = TIP.second;
1298 break;
1299 }
1300 }
1301
1302 if (!TRegSym) {
1303 TRegSym = OutContext.createTempSymbol();
1304 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1305 }
1306
1307 // Create a link-saving branch to the Reg Indirect Jump Pad.
1308 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1309 // Predicate comes first here.
1310 .addImm(ARMCC::AL).addReg(0)
1311 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1312 return;
1313 }
1314 case ARM::BMOVPCRX_CALL: {
1315 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1316 .addReg(ARM::LR)
1317 .addReg(ARM::PC)
1318 // Add predicate operands.
1319 .addImm(ARMCC::AL)
1320 .addReg(0)
1321 // Add 's' bit operand (always reg0 for this)
1322 .addReg(0));
1323
1324 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1325 .addReg(ARM::PC)
1326 .addReg(MI->getOperand(0).getReg())
1327 // Add predicate operands.
1328 .addImm(ARMCC::AL)
1329 .addReg(0)
1330 // Add 's' bit operand (always reg0 for this)
1331 .addReg(0));
1332 return;
1333 }
1334 case ARM::BMOVPCB_CALL: {
1335 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1336 .addReg(ARM::LR)
1337 .addReg(ARM::PC)
1338 // Add predicate operands.
1339 .addImm(ARMCC::AL)
1340 .addReg(0)
1341 // Add 's' bit operand (always reg0 for this)
1342 .addReg(0));
1343
1344 const MachineOperand &Op = MI->getOperand(0);
1345 const GlobalValue *GV = Op.getGlobal();
1346 const unsigned TF = Op.getTargetFlags();
1347 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1348 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1349 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1350 .addExpr(GVSymExpr)
1351 // Add predicate operands.
1352 .addImm(ARMCC::AL)
1353 .addReg(0));
1354 return;
1355 }
1356 case ARM::MOVi16_ga_pcrel:
1357 case ARM::t2MOVi16_ga_pcrel: {
1358 MCInst TmpInst;
1359 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1360 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1361
1362 unsigned TF = MI->getOperand(1).getTargetFlags();
1363 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1364 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1365 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1366
1367 MCSymbol *LabelSym =
1368 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1369 MI->getOperand(2).getImm(), OutContext);
1370 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1371 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1372 const MCExpr *PCRelExpr =
1373 ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1374 MCBinaryExpr::createAdd(LabelSymExpr,
1375 MCConstantExpr::create(PCAdj, OutContext),
1376 OutContext), OutContext), OutContext);
1377 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1378
1379 // Add predicate operands.
1380 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1381 TmpInst.addOperand(MCOperand::createReg(0));
1382 // Add 's' bit operand (always reg0 for this)
1383 TmpInst.addOperand(MCOperand::createReg(0));
1384 EmitToStreamer(*OutStreamer, TmpInst);
1385 return;
1386 }
1387 case ARM::MOVTi16_ga_pcrel:
1388 case ARM::t2MOVTi16_ga_pcrel: {
1389 MCInst TmpInst;
1390 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1391 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1392 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1393 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1394
1395 unsigned TF = MI->getOperand(2).getTargetFlags();
1396 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1397 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1398 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1399
1400 MCSymbol *LabelSym =
1401 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1402 MI->getOperand(3).getImm(), OutContext);
1403 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1404 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1405 const MCExpr *PCRelExpr =
1406 ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1407 MCBinaryExpr::createAdd(LabelSymExpr,
1408 MCConstantExpr::create(PCAdj, OutContext),
1409 OutContext), OutContext), OutContext);
1410 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1411 // Add predicate operands.
1412 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1413 TmpInst.addOperand(MCOperand::createReg(0));
1414 // Add 's' bit operand (always reg0 for this)
1415 TmpInst.addOperand(MCOperand::createReg(0));
1416 EmitToStreamer(*OutStreamer, TmpInst);
1417 return;
1418 }
1419 case ARM::tPICADD: {
1420 // This is a pseudo op for a label + instruction sequence, which looks like:
1421 // LPC0:
1422 // add r0, pc
1423 // This adds the address of LPC0 to r0.
1424
1425 // Emit the label.
1426 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1427 getFunctionNumber(),
1428 MI->getOperand(2).getImm(), OutContext));
1429
1430 // Form and emit the add.
1431 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1432 .addReg(MI->getOperand(0).getReg())
1433 .addReg(MI->getOperand(0).getReg())
1434 .addReg(ARM::PC)
1435 // Add predicate operands.
1436 .addImm(ARMCC::AL)
1437 .addReg(0));
1438 return;
1439 }
1440 case ARM::PICADD: {
1441 // This is a pseudo op for a label + instruction sequence, which looks like:
1442 // LPC0:
1443 // add r0, pc, r0
1444 // This adds the address of LPC0 to r0.
1445
1446 // Emit the label.
1447 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1448 getFunctionNumber(),
1449 MI->getOperand(2).getImm(), OutContext));
1450
1451 // Form and emit the add.
1452 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1453 .addReg(MI->getOperand(0).getReg())
1454 .addReg(ARM::PC)
1455 .addReg(MI->getOperand(1).getReg())
1456 // Add predicate operands.
1457 .addImm(MI->getOperand(3).getImm())
1458 .addReg(MI->getOperand(4).getReg())
1459 // Add 's' bit operand (always reg0 for this)
1460 .addReg(0));
1461 return;
1462 }
1463 case ARM::PICSTR:
1464 case ARM::PICSTRB:
1465 case ARM::PICSTRH:
1466 case ARM::PICLDR:
1467 case ARM::PICLDRB:
1468 case ARM::PICLDRH:
1469 case ARM::PICLDRSB:
1470 case ARM::PICLDRSH: {
1471 // This is a pseudo op for a label + instruction sequence, which looks like:
1472 // LPC0:
1473 // OP r0, [pc, r0]
1474 // The LCP0 label is referenced by a constant pool entry in order to get
1475 // a PC-relative address at the ldr instruction.
1476
1477 // Emit the label.
1478 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1479 getFunctionNumber(),
1480 MI->getOperand(2).getImm(), OutContext));
1481
1482 // Form and emit the load
1483 unsigned Opcode;
1484 switch (MI->getOpcode()) {
1485 default:
1486 llvm_unreachable("Unexpected opcode!")::llvm::llvm_unreachable_internal("Unexpected opcode!", "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1486)
;
1487 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1488 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1489 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1490 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1491 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1492 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1493 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1494 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1495 }
1496 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1497 .addReg(MI->getOperand(0).getReg())
1498 .addReg(ARM::PC)
1499 .addReg(MI->getOperand(1).getReg())
1500 .addImm(0)
1501 // Add predicate operands.
1502 .addImm(MI->getOperand(3).getImm())
1503 .addReg(MI->getOperand(4).getReg()));
1504
1505 return;
1506 }
1507 case ARM::CONSTPOOL_ENTRY: {
1508 if (Subtarget->genExecuteOnly())
1509 llvm_unreachable("execute-only should not generate constant pools")::llvm::llvm_unreachable_internal("execute-only should not generate constant pools"
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1509)
;
1510
1511 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1512 /// in the function. The first operand is the ID# for this instruction, the
1513 /// second is the index into the MachineConstantPool that this is, the third
1514 /// is the size in bytes of this constant pool entry.
1515 /// The required alignment is specified on the basic block holding this MI.
1516 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1517 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1518
1519 // If this is the first entry of the pool, mark it.
1520 if (!InConstantPool) {
1521 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1522 InConstantPool = true;
1523 }
1524
1525 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1526
1527 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1528 if (MCPE.isMachineConstantPoolEntry())
1529 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1530 else
1531 EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1532 return;
1533 }
1534 case ARM::JUMPTABLE_ADDRS:
1535 EmitJumpTableAddrs(MI);
1536 return;
1537 case ARM::JUMPTABLE_INSTS:
1538 EmitJumpTableInsts(MI);
1539 return;
1540 case ARM::JUMPTABLE_TBB:
1541 case ARM::JUMPTABLE_TBH:
1542 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1543 return;
1544 case ARM::t2BR_JT: {
1545 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1546 .addReg(ARM::PC)
1547 .addReg(MI->getOperand(0).getReg())
1548 // Add predicate operands.
1549 .addImm(ARMCC::AL)
1550 .addReg(0));
1551 return;
1552 }
1553 case ARM::t2TBB_JT:
1554 case ARM::t2TBH_JT: {
1555 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1556 // Lower and emit the PC label, then the instruction itself.
1557 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1558 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1559 .addReg(MI->getOperand(0).getReg())
1560 .addReg(MI->getOperand(1).getReg())
1561 // Add predicate operands.
1562 .addImm(ARMCC::AL)
1563 .addReg(0));
1564 return;
1565 }
1566 case ARM::tTBB_JT:
1567 case ARM::tTBH_JT: {
1568
1569 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1570 unsigned Base = MI->getOperand(0).getReg();
1571 unsigned Idx = MI->getOperand(1).getReg();
1572 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!")(static_cast <bool> (MI->getOperand(1).isKill() &&
"We need the index register as scratch!") ? void (0) : __assert_fail
("MI->getOperand(1).isKill() && \"We need the index register as scratch!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1572, __extension__ __PRETTY_FUNCTION__))
;
1573
1574 // Multiply up idx if necessary.
1575 if (!Is8Bit)
1576 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1577 .addReg(Idx)
1578 .addReg(ARM::CPSR)
1579 .addReg(Idx)
1580 .addImm(1)
1581 // Add predicate operands.
1582 .addImm(ARMCC::AL)
1583 .addReg(0));
1584
1585 if (Base == ARM::PC) {
1586 // TBB [base, idx] =
1587 // ADDS idx, idx, base
1588 // LDRB idx, [idx, #4] ; or LDRH if TBH
1589 // LSLS idx, #1
1590 // ADDS pc, pc, idx
1591
1592 // When using PC as the base, it's important that there is no padding
1593 // between the last ADDS and the start of the jump table. The jump table
1594 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1595 //
1596 // FIXME: Ideally we could vary the LDRB index based on the padding
1597 // between the sequence and jump table, however that relies on MCExprs
1598 // for load indexes which are currently not supported.
1599 OutStreamer->EmitCodeAlignment(4);
1600 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1601 .addReg(Idx)
1602 .addReg(Idx)
1603 .addReg(Base)
1604 // Add predicate operands.
1605 .addImm(ARMCC::AL)
1606 .addReg(0));
1607
1608 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1609 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1610 .addReg(Idx)
1611 .addReg(Idx)
1612 .addImm(Is8Bit ? 4 : 2)
1613 // Add predicate operands.
1614 .addImm(ARMCC::AL)
1615 .addReg(0));
1616 } else {
1617 // TBB [base, idx] =
1618 // LDRB idx, [base, idx] ; or LDRH if TBH
1619 // LSLS idx, #1
1620 // ADDS pc, pc, idx
1621
1622 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1623 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1624 .addReg(Idx)
1625 .addReg(Base)
1626 .addReg(Idx)
1627 // Add predicate operands.
1628 .addImm(ARMCC::AL)
1629 .addReg(0));
1630 }
1631
1632 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1633 .addReg(Idx)
1634 .addReg(ARM::CPSR)
1635 .addReg(Idx)
1636 .addImm(1)
1637 // Add predicate operands.
1638 .addImm(ARMCC::AL)
1639 .addReg(0));
1640
1641 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1642 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1643 .addReg(ARM::PC)
1644 .addReg(ARM::PC)
1645 .addReg(Idx)
1646 // Add predicate operands.
1647 .addImm(ARMCC::AL)
1648 .addReg(0));
1649 return;
1650 }
1651 case ARM::tBR_JTr:
1652 case ARM::BR_JTr: {
1653 // mov pc, target
1654 MCInst TmpInst;
1655 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1656 ARM::MOVr : ARM::tMOVr;
1657 TmpInst.setOpcode(Opc);
1658 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1659 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1660 // Add predicate operands.
1661 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1662 TmpInst.addOperand(MCOperand::createReg(0));
1663 // Add 's' bit operand (always reg0 for this)
1664 if (Opc == ARM::MOVr)
1665 TmpInst.addOperand(MCOperand::createReg(0));
1666 EmitToStreamer(*OutStreamer, TmpInst);
1667 return;
1668 }
1669 case ARM::BR_JTm_i12: {
1670 // ldr pc, target
1671 MCInst TmpInst;
1672 TmpInst.setOpcode(ARM::LDRi12);
1673 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1674 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1675 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1676 // Add predicate operands.
1677 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1678 TmpInst.addOperand(MCOperand::createReg(0));
1679 EmitToStreamer(*OutStreamer, TmpInst);
1680 return;
1681 }
1682 case ARM::BR_JTm_rs: {
1683 // ldr pc, target
1684 MCInst TmpInst;
1685 TmpInst.setOpcode(ARM::LDRrs);
1686 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1687 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1688 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1689 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1690 // Add predicate operands.
1691 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1692 TmpInst.addOperand(MCOperand::createReg(0));
1693 EmitToStreamer(*OutStreamer, TmpInst);
1694 return;
1695 }
1696 case ARM::BR_JTadd: {
1697 // add pc, target, idx
1698 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1699 .addReg(ARM::PC)
1700 .addReg(MI->getOperand(0).getReg())
1701 .addReg(MI->getOperand(1).getReg())
1702 // Add predicate operands.
1703 .addImm(ARMCC::AL)
1704 .addReg(0)
1705 // Add 's' bit operand (always reg0 for this)
1706 .addReg(0));
1707 return;
1708 }
1709 case ARM::SPACE:
1710 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1711 return;
1712 case ARM::TRAP: {
1713 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1714 // FIXME: Remove this special case when they do.
1715 if (!Subtarget->isTargetMachO()) {
1716 uint32_t Val = 0xe7ffdefeUL;
1717 OutStreamer->AddComment("trap");
1718 ATS.emitInst(Val);
1719 return;
1720 }
1721 break;
1722 }
1723 case ARM::TRAPNaCl: {
1724 uint32_t Val = 0xe7fedef0UL;
1725 OutStreamer->AddComment("trap");
1726 ATS.emitInst(Val);
1727 return;
1728 }
1729 case ARM::tTRAP: {
1730 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1731 // FIXME: Remove this special case when they do.
1732 if (!Subtarget->isTargetMachO()) {
1733 uint16_t Val = 0xdefe;
1734 OutStreamer->AddComment("trap");
1735 ATS.emitInst(Val, 'n');
1736 return;
1737 }
1738 break;
1739 }
1740 case ARM::t2Int_eh_sjlj_setjmp:
1741 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1742 case ARM::tInt_eh_sjlj_setjmp: {
1743 // Two incoming args: GPR:$src, GPR:$val
1744 // mov $val, pc
1745 // adds $val, #7
1746 // str $val, [$src, #4]
1747 // movs r0, #0
1748 // b LSJLJEH
1749 // movs r0, #1
1750 // LSJLJEH:
1751 unsigned SrcReg = MI->getOperand(0).getReg();
1752 unsigned ValReg = MI->getOperand(1).getReg();
1753 MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1754 OutStreamer->AddComment("eh_setjmp begin");
1755 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1756 .addReg(ValReg)
1757 .addReg(ARM::PC)
1758 // Predicate.
1759 .addImm(ARMCC::AL)
1760 .addReg(0));
1761
1762 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1763 .addReg(ValReg)
1764 // 's' bit operand
1765 .addReg(ARM::CPSR)
1766 .addReg(ValReg)
1767 .addImm(7)
1768 // Predicate.
1769 .addImm(ARMCC::AL)
1770 .addReg(0));
1771
1772 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1773 .addReg(ValReg)
1774 .addReg(SrcReg)
1775 // The offset immediate is #4. The operand value is scaled by 4 for the
1776 // tSTR instruction.
1777 .addImm(1)
1778 // Predicate.
1779 .addImm(ARMCC::AL)
1780 .addReg(0));
1781
1782 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1783 .addReg(ARM::R0)
1784 .addReg(ARM::CPSR)
1785 .addImm(0)
1786 // Predicate.
1787 .addImm(ARMCC::AL)
1788 .addReg(0));
1789
1790 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1791 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1792 .addExpr(SymbolExpr)
1793 .addImm(ARMCC::AL)
1794 .addReg(0));
1795
1796 OutStreamer->AddComment("eh_setjmp end");
1797 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1798 .addReg(ARM::R0)
1799 .addReg(ARM::CPSR)
1800 .addImm(1)
1801 // Predicate.
1802 .addImm(ARMCC::AL)
1803 .addReg(0));
1804
1805 OutStreamer->EmitLabel(Label);
1806 return;
1807 }
1808
1809 case ARM::Int_eh_sjlj_setjmp_nofp:
1810 case ARM::Int_eh_sjlj_setjmp: {
1811 // Two incoming args: GPR:$src, GPR:$val
1812 // add $val, pc, #8
1813 // str $val, [$src, #+4]
1814 // mov r0, #0
1815 // add pc, pc, #0
1816 // mov r0, #1
1817 unsigned SrcReg = MI->getOperand(0).getReg();
1818 unsigned ValReg = MI->getOperand(1).getReg();
1819
1820 OutStreamer->AddComment("eh_setjmp begin");
1821 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1822 .addReg(ValReg)
1823 .addReg(ARM::PC)
1824 .addImm(8)
1825 // Predicate.
1826 .addImm(ARMCC::AL)
1827 .addReg(0)
1828 // 's' bit operand (always reg0 for this).
1829 .addReg(0));
1830
1831 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1832 .addReg(ValReg)
1833 .addReg(SrcReg)
1834 .addImm(4)
1835 // Predicate.
1836 .addImm(ARMCC::AL)
1837 .addReg(0));
1838
1839 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1840 .addReg(ARM::R0)
1841 .addImm(0)
1842 // Predicate.
1843 .addImm(ARMCC::AL)
1844 .addReg(0)
1845 // 's' bit operand (always reg0 for this).
1846 .addReg(0));
1847
1848 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1849 .addReg(ARM::PC)
1850 .addReg(ARM::PC)
1851 .addImm(0)
1852 // Predicate.
1853 .addImm(ARMCC::AL)
1854 .addReg(0)
1855 // 's' bit operand (always reg0 for this).
1856 .addReg(0));
1857
1858 OutStreamer->AddComment("eh_setjmp end");
1859 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1860 .addReg(ARM::R0)
1861 .addImm(1)
1862 // Predicate.
1863 .addImm(ARMCC::AL)
1864 .addReg(0)
1865 // 's' bit operand (always reg0 for this).
1866 .addReg(0));
1867 return;
1868 }
1869 case ARM::Int_eh_sjlj_longjmp: {
1870 // ldr sp, [$src, #8]
1871 // ldr $scratch, [$src, #4]
1872 // ldr r7, [$src]
1873 // bx $scratch
1874 unsigned SrcReg = MI->getOperand(0).getReg();
1875 unsigned ScratchReg = MI->getOperand(1).getReg();
1876 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1877 .addReg(ARM::SP)
1878 .addReg(SrcReg)
1879 .addImm(8)
1880 // Predicate.
1881 .addImm(ARMCC::AL)
1882 .addReg(0));
1883
1884 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1885 .addReg(ScratchReg)
1886 .addReg(SrcReg)
1887 .addImm(4)
1888 // Predicate.
1889 .addImm(ARMCC::AL)
1890 .addReg(0));
1891
1892 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1893 // These platforms always use the same frame register
1894 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1895 .addReg(FramePtr)
1896 .addReg(SrcReg)
1897 .addImm(0)
1898 // Predicate.
1899 .addImm(ARMCC::AL)
1900 .addReg(0));
1901 } else {
1902 // If the calling code might use either R7 or R11 as
1903 // frame pointer register, restore it into both.
1904 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1905 .addReg(ARM::R7)
1906 .addReg(SrcReg)
1907 .addImm(0)
1908 // Predicate.
1909 .addImm(ARMCC::AL)
1910 .addReg(0));
1911 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1912 .addReg(ARM::R11)
1913 .addReg(SrcReg)
1914 .addImm(0)
1915 // Predicate.
1916 .addImm(ARMCC::AL)
1917 .addReg(0));
1918 }
1919
1920 assert(Subtarget->hasV4TOps())(static_cast <bool> (Subtarget->hasV4TOps()) ? void (
0) : __assert_fail ("Subtarget->hasV4TOps()", "/build/llvm-toolchain-snapshot-6.0~svn318693/lib/Target/ARM/ARMAsmPrinter.cpp"
, 1920, __extension__ __PRETTY_FUNCTION__))
;
1921 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1922 .addReg(ScratchReg)
1923 // Predicate.
1924 .addImm(ARMCC::AL)
1925 .addReg(0));
1926 return;
1927 }
1928 case ARM::tInt_eh_sjlj_longjmp: {
1929 // ldr $scratch, [$src, #8]
1930 // mov sp, $scratch
1931 // ldr $scratch, [$src, #4]
1932 // ldr r7, [$src]
1933 // bx $scratch
1934 unsigned SrcReg = MI->getOperand(0).getReg();
1935 unsigned ScratchReg = MI->getOperand(1).getReg();
1936
1937 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1938 .addReg(ScratchReg)
1939 .addReg(SrcReg)
1940 // The offset immediate is #8. The operand value is scaled by 4 for the
1941 // tLDR instruction.
1942 .addImm(2)
1943 // Predicate.
1944 .addImm(ARMCC::AL)
1945 .addReg(0));
1946
1947 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1948 .addReg(ARM::SP)
1949 .addReg(ScratchReg)
1950 // Predicate.
1951 .addImm(ARMCC::AL)
1952 .addReg(0));
1953
1954 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1955 .addReg(ScratchReg)
1956 .addReg(SrcReg)
1957 .addImm(1)
1958 // Predicate.
1959 .addImm(ARMCC::AL)
1960 .addReg(0));
1961
1962 if (STI.isTargetDarwin() || STI.isTargetWindows()) {
1963 // These platforms always use the same frame register
1964 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1965 .addReg(FramePtr)
1966 .addReg(SrcReg)
1967 .addImm(0)
1968 // Predicate.
1969 .addImm(ARMCC::AL)
1970 .addReg(0));
1971 } else {
1972 // If the calling code might use either R7 or R11 as
1973 // frame pointer register, restore it into both.
1974 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1975 .addReg(ARM::R7)
1976 .addReg(SrcReg)
1977 .addImm(0)
1978 // Predicate.
1979 .addImm(ARMCC::AL)
1980 .addReg(0));
1981 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1982 .addReg(ARM::R11)
1983 .addReg(SrcReg)
1984 .addImm(0)
1985 // Predicate.
1986 .addImm(ARMCC::AL)
1987 .addReg(0));
1988 }
1989
1990 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
1991 .addReg(ScratchReg)
1992 // Predicate.
1993 .addImm(ARMCC::AL)
1994 .addReg(0));
1995 return;
1996 }
1997 case ARM::tInt_WIN_eh_sjlj_longjmp: {
1998 // ldr.w r11, [$src, #0]
1999 // ldr.w sp, [$src, #8]
2000 // ldr.w pc, [$src, #4]
2001
2002 unsigned SrcReg = MI->getOperand(0).getReg();
2003
2004 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2005 .addReg(ARM::R11)
2006 .addReg(SrcReg)
2007 .addImm(0)
2008 // Predicate
2009 .addImm(ARMCC::AL)
2010 .addReg(0));
2011 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2012 .addReg(ARM::SP)
2013 .addReg(SrcReg)
2014 .addImm(8)
2015 // Predicate
2016 .addImm(ARMCC::AL)
2017 .addReg(0));
2018 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
2019 .addReg(ARM::PC)
2020 .addReg(SrcReg)
2021 .addImm(4)
2022 // Predicate
2023 .addImm(ARMCC::AL)
2024 .addReg(0));
2025 return;
2026 }
2027 case ARM::PATCHABLE_FUNCTION_ENTER:
2028 LowerPATCHABLE_FUNCTION_ENTER(*MI);
2029 return;
2030 case ARM::PATCHABLE_FUNCTION_EXIT:
2031 LowerPATCHABLE_FUNCTION_EXIT(*MI);
2032 return;
2033 case ARM::PATCHABLE_TAIL_CALL:
2034 LowerPATCHABLE_TAIL_CALL(*MI);
2035 return;
2036 }
2037
2038 MCInst TmpInst;
2039 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
2040
2041 EmitToStreamer(*OutStreamer, TmpInst);
2042}
2043
2044//===----------------------------------------------------------------------===//
2045// Target Registry Stuff
2046//===----------------------------------------------------------------------===//
2047
2048// Force static initialization.
2049extern "C" void LLVMInitializeARMAsmPrinter() {
2050 RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2051 RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2052 RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2053 RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());
2054}

/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h

1//===- llvm/InlineAsm.h - Class to represent inline asm strings -*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class represents the inline asm strings, which are Value*'s that are
11// used as the callee operand of call instructions. InlineAsm's are uniqued
12// like constants, and created via InlineAsm::get(...).
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_IR_INLINEASM_H
17#define LLVM_IR_INLINEASM_H
18
19#include "llvm/ADT/StringRef.h"
20#include "llvm/IR/Value.h"
21#include <cassert>
22#include <string>
23#include <vector>
24
25namespace llvm {
26
27class FunctionType;
28class PointerType;
29template <class ConstantClass> class ConstantUniqueMap;
30
31class InlineAsm final : public Value {
32public:
33 enum AsmDialect {
34 AD_ATT,
35 AD_Intel
36 };
37
38private:
39 friend struct InlineAsmKeyType;
40 friend class ConstantUniqueMap<InlineAsm>;
41
42 std::string AsmString, Constraints;
43 FunctionType *FTy;
44 bool HasSideEffects;
45 bool IsAlignStack;
46 AsmDialect Dialect;
47
48 InlineAsm(FunctionType *Ty, const std::string &AsmString,
49 const std::string &Constraints, bool hasSideEffects,
50 bool isAlignStack, AsmDialect asmDialect);
51
52 /// When the ConstantUniqueMap merges two types and makes two InlineAsms
53 /// identical, it destroys one of them with this method.
54 void destroyConstant();
55
56public:
57 InlineAsm(const InlineAsm &) = delete;
58 InlineAsm &operator=(const InlineAsm &) = delete;
59
60 /// InlineAsm::get - Return the specified uniqued inline asm string.
61 ///
62 static InlineAsm *get(FunctionType *Ty, StringRef AsmString,
63 StringRef Constraints, bool hasSideEffects,
64 bool isAlignStack = false,
65 AsmDialect asmDialect = AD_ATT);
66
67 bool hasSideEffects() const { return HasSideEffects; }
68 bool isAlignStack() const { return IsAlignStack; }
69 AsmDialect getDialect() const { return Dialect; }
70
71 /// getType - InlineAsm's are always pointers.
72 ///
73 PointerType *getType() const {
74 return reinterpret_cast<PointerType*>(Value::getType());
75 }
76
77 /// getFunctionType - InlineAsm's are always pointers to functions.
78 ///
79 FunctionType *getFunctionType() const;
80
81 const std::string &getAsmString() const { return AsmString; }
82 const std::string &getConstraintString() const { return Constraints; }
83
84 /// Verify - This static method can be used by the parser to check to see if
85 /// the specified constraint string is legal for the type. This returns true
86 /// if legal, false if not.
87 ///
88 static bool Verify(FunctionType *Ty, StringRef Constraints);
89
90 // Constraint String Parsing
91 enum ConstraintPrefix {
92 isInput, // 'x'
93 isOutput, // '=x'
94 isClobber // '~x'
95 };
96
97 using ConstraintCodeVector = std::vector<std::string>;
98
99 struct SubConstraintInfo {
100 /// MatchingInput - If this is not -1, this is an output constraint where an
101 /// input constraint is required to match it (e.g. "0"). The value is the
102 /// constraint number that matches this one (for example, if this is
103 /// constraint #0 and constraint #4 has the value "0", this will be 4).
104 int MatchingInput = -1;
105
106 /// Code - The constraint code, either the register name (in braces) or the
107 /// constraint letter/number.
108 ConstraintCodeVector Codes;
109
110 /// Default constructor.
111 SubConstraintInfo() = default;
112 };
113
114 using SubConstraintInfoVector = std::vector<SubConstraintInfo>;
115 struct ConstraintInfo;
116 using ConstraintInfoVector = std::vector<ConstraintInfo>;
117
118 struct ConstraintInfo {
119 /// Type - The basic type of the constraint: input/output/clobber
120 ///
121 ConstraintPrefix Type = isInput;
122
123 /// isEarlyClobber - "&": output operand writes result before inputs are all
124 /// read. This is only ever set for an output operand.
125 bool isEarlyClobber = false;
126
127 /// MatchingInput - If this is not -1, this is an output constraint where an
128 /// input constraint is required to match it (e.g. "0"). The value is the
129 /// constraint number that matches this one (for example, if this is
130 /// constraint #0 and constraint #4 has the value "0", this will be 4).
131 int MatchingInput = -1;
132
133 /// hasMatchingInput - Return true if this is an output constraint that has
134 /// a matching input constraint.
135 bool hasMatchingInput() const { return MatchingInput != -1; }
136
137 /// isCommutative - This is set to true for a constraint that is commutative
138 /// with the next operand.
139 bool isCommutative = false;
140
141 /// isIndirect - True if this operand is an indirect operand. This means
142 /// that the address of the source or destination is present in the call
143 /// instruction, instead of it being returned or passed in explicitly. This
144 /// is represented with a '*' in the asm string.
145 bool isIndirect = false;
146
147 /// Code - The constraint code, either the register name (in braces) or the
148 /// constraint letter/number.
149 ConstraintCodeVector Codes;
150
151 /// isMultipleAlternative - '|': has multiple-alternative constraints.
152 bool isMultipleAlternative = false;
153
154 /// multipleAlternatives - If there are multiple alternative constraints,
155 /// this array will contain them. Otherwise it will be empty.
156 SubConstraintInfoVector multipleAlternatives;
157
158 /// The currently selected alternative constraint index.
159 unsigned currentAlternativeIndex = 0;
160
161 /// Default constructor.
162 ConstraintInfo() = default;
163
164 /// Parse - Analyze the specified string (e.g. "=*&{eax}") and fill in the
165 /// fields in this structure. If the constraint string is not understood,
166 /// return true, otherwise return false.
167 bool Parse(StringRef Str, ConstraintInfoVector &ConstraintsSoFar);
168
169 /// selectAlternative - Point this constraint to the alternative constraint
170 /// indicated by the index.
171 void selectAlternative(unsigned index);
172 };
173
174 /// ParseConstraints - Split up the constraint string into the specific
175 /// constraints and their prefixes. If this returns an empty vector, and if
176 /// the constraint string itself isn't empty, there was an error parsing.
177 static ConstraintInfoVector ParseConstraints(StringRef ConstraintString);
178
179 /// ParseConstraints - Parse the constraints of this inlineasm object,
180 /// returning them the same way that ParseConstraints(str) does.
181 ConstraintInfoVector ParseConstraints() const {
182 return ParseConstraints(Constraints);
183 }
184
185 // Methods for support type inquiry through isa, cast, and dyn_cast:
186 static bool classof(const Value *V) {
187 return V->getValueID() == Value::InlineAsmVal;
188 }
189
190 // These are helper methods for dealing with flags in the INLINEASM SDNode
191 // in the backend.
192 //
193 // The encoding of the flag word is currently:
194 // Bits 2-0 - A Kind_* value indicating the kind of the operand.
195 // Bits 15-3 - The number of SDNode operands associated with this inline
196 // assembly operand.
197 // If bit 31 is set:
198 // Bit 30-16 - The operand number that this operand must match.
199 // When bits 2-0 are Kind_Mem, the Constraint_* value must be
200 // obtained from the flags for this operand number.
201 // Else if bits 2-0 are Kind_Mem:
202 // Bit 30-16 - A Constraint_* value indicating the original constraint
203 // code.
204 // Else:
205 // Bit 30-16 - The register class ID to use for the operand.
206
207 enum : uint32_t {
208 // Fixed operands on an INLINEASM SDNode.
209 Op_InputChain = 0,
210 Op_AsmString = 1,
211 Op_MDNode = 2,
212 Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
213 Op_FirstOperand = 4,
214
215 // Fixed operands on an INLINEASM MachineInstr.
216 MIOp_AsmString = 0,
217 MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
218 MIOp_FirstOperand = 2,
219
220 // Interpretation of the MIOp_ExtraInfo bit field.
221 Extra_HasSideEffects = 1,
222 Extra_IsAlignStack = 2,
223 Extra_AsmDialect = 4,
224 Extra_MayLoad = 8,
225 Extra_MayStore = 16,
226 Extra_IsConvergent = 32,
227
228 // Inline asm operands map to multiple SDNode / MachineInstr operands.
229 // The first operand is an immediate describing the asm operand, the low
230 // bits is the kind:
231 Kind_RegUse = 1, // Input register, "r".
232 Kind_RegDef = 2, // Output register, "=r".
233 Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r".
234 Kind_Clobber = 4, // Clobbered register, "~r".
235 Kind_Imm = 5, // Immediate.
236 Kind_Mem = 6, // Memory operand, "m".
237
238 // Memory constraint codes.
239 // These could be tablegenerated but there's little need to do that since
240 // there's plenty of space in the encoding to support the union of all
241 // constraint codes for all targets.
242 Constraint_Unknown = 0,
243 Constraint_es,
244 Constraint_i,
245 Constraint_m,
246 Constraint_o,
247 Constraint_v,
248 Constraint_Q,
249 Constraint_R,
250 Constraint_S,
251 Constraint_T,
252 Constraint_Um,
253 Constraint_Un,
254 Constraint_Uq,
255 Constraint_Us,
256 Constraint_Ut,
257 Constraint_Uv,
258 Constraint_Uy,
259 Constraint_X,
260 Constraint_Z,
261 Constraint_ZC,
262 Constraint_Zy,
263 Constraints_Max = Constraint_Zy,
264 Constraints_ShiftAmount = 16,
265
266 Flag_MatchingOperand = 0x80000000
267 };
268
269 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) {
270 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!")(static_cast <bool> (((NumOps << 3) & ~0xffff
) == 0 && "Too many inline asm operands!") ? void (0)
: __assert_fail ("((NumOps << 3) & ~0xffff) == 0 && \"Too many inline asm operands!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 270, __extension__ __PRETTY_FUNCTION__))
;
271 assert(Kind >= Kind_RegUse && Kind <= Kind_Mem && "Invalid Kind")(static_cast <bool> (Kind >= Kind_RegUse && Kind
<= Kind_Mem && "Invalid Kind") ? void (0) : __assert_fail
("Kind >= Kind_RegUse && Kind <= Kind_Mem && \"Invalid Kind\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 271, __extension__ __PRETTY_FUNCTION__))
;
272 return Kind | (NumOps << 3);
273 }
274
275 static bool isRegDefKind(unsigned Flag){ return getKind(Flag) == Kind_RegDef;}
276 static bool isImmKind(unsigned Flag) { return getKind(Flag) == Kind_Imm; }
277 static bool isMemKind(unsigned Flag) { return getKind(Flag) == Kind_Mem; }
278 static bool isRegDefEarlyClobberKind(unsigned Flag) {
279 return getKind(Flag) == Kind_RegDefEarlyClobber;
280 }
281 static bool isClobberKind(unsigned Flag) {
282 return getKind(Flag) == Kind_Clobber;
283 }
284
285 /// getFlagWordForMatchingOp - Augment an existing flag word returned by
286 /// getFlagWord with information indicating that this input operand is tied
287 /// to a previous output operand.
288 static unsigned getFlagWordForMatchingOp(unsigned InputFlag,
289 unsigned MatchedOperandNo) {
290 assert(MatchedOperandNo <= 0x7fff && "Too big matched operand")(static_cast <bool> (MatchedOperandNo <= 0x7fff &&
"Too big matched operand") ? void (0) : __assert_fail ("MatchedOperandNo <= 0x7fff && \"Too big matched operand\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 290, __extension__ __PRETTY_FUNCTION__))
;
291 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data")(static_cast <bool> ((InputFlag & ~0xffff) == 0 &&
"High bits already contain data") ? void (0) : __assert_fail
("(InputFlag & ~0xffff) == 0 && \"High bits already contain data\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 291, __extension__ __PRETTY_FUNCTION__))
;
292 return InputFlag | Flag_MatchingOperand | (MatchedOperandNo << 16);
293 }
294
295 /// getFlagWordForRegClass - Augment an existing flag word returned by
296 /// getFlagWord with the required register class for the following register
297 /// operands.
298 /// A tied use operand cannot have a register class, use the register class
299 /// from the def operand instead.
300 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) {
301 // Store RC + 1, reserve the value 0 to mean 'no register class'.
302 ++RC;
303 assert(!isImmKind(InputFlag) && "Immediates cannot have a register class")(static_cast <bool> (!isImmKind(InputFlag) && "Immediates cannot have a register class"
) ? void (0) : __assert_fail ("!isImmKind(InputFlag) && \"Immediates cannot have a register class\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 303, __extension__ __PRETTY_FUNCTION__))
;
304 assert(!isMemKind(InputFlag) && "Memory operand cannot have a register class")(static_cast <bool> (!isMemKind(InputFlag) && "Memory operand cannot have a register class"
) ? void (0) : __assert_fail ("!isMemKind(InputFlag) && \"Memory operand cannot have a register class\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 304, __extension__ __PRETTY_FUNCTION__))
;
305 assert(RC <= 0x7fff && "Too large register class ID")(static_cast <bool> (RC <= 0x7fff && "Too large register class ID"
) ? void (0) : __assert_fail ("RC <= 0x7fff && \"Too large register class ID\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 305, __extension__ __PRETTY_FUNCTION__))
;
306 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data")(static_cast <bool> ((InputFlag & ~0xffff) == 0 &&
"High bits already contain data") ? void (0) : __assert_fail
("(InputFlag & ~0xffff) == 0 && \"High bits already contain data\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 306, __extension__ __PRETTY_FUNCTION__))
;
307 return InputFlag | (RC << 16);
308 }
309
310 /// Augment an existing flag word returned by getFlagWord with the constraint
311 /// code for a memory constraint.
312 static unsigned getFlagWordForMem(unsigned InputFlag, unsigned Constraint) {
313 assert(isMemKind(InputFlag) && "InputFlag is not a memory constraint!")(static_cast <bool> (isMemKind(InputFlag) && "InputFlag is not a memory constraint!"
) ? void (0) : __assert_fail ("isMemKind(InputFlag) && \"InputFlag is not a memory constraint!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 313, __extension__ __PRETTY_FUNCTION__))
;
314 assert(Constraint <= 0x7fff && "Too large a memory constraint ID")(static_cast <bool> (Constraint <= 0x7fff &&
"Too large a memory constraint ID") ? void (0) : __assert_fail
("Constraint <= 0x7fff && \"Too large a memory constraint ID\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 314, __extension__ __PRETTY_FUNCTION__))
;
315 assert(Constraint <= Constraints_Max && "Unknown constraint ID")(static_cast <bool> (Constraint <= Constraints_Max &&
"Unknown constraint ID") ? void (0) : __assert_fail ("Constraint <= Constraints_Max && \"Unknown constraint ID\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 315, __extension__ __PRETTY_FUNCTION__))
;
316 assert((InputFlag & ~0xffff) == 0 && "High bits already contain data")(static_cast <bool> ((InputFlag & ~0xffff) == 0 &&
"High bits already contain data") ? void (0) : __assert_fail
("(InputFlag & ~0xffff) == 0 && \"High bits already contain data\""
, "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 316, __extension__ __PRETTY_FUNCTION__))
;
317 return InputFlag | (Constraint << Constraints_ShiftAmount);
318 }
319
320 static unsigned convertMemFlagWordToMatchingFlagWord(unsigned InputFlag) {
321 assert(isMemKind(InputFlag))(static_cast <bool> (isMemKind(InputFlag)) ? void (0) :
__assert_fail ("isMemKind(InputFlag)", "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 321, __extension__ __PRETTY_FUNCTION__))
;
322 return InputFlag & ~(0x7fff << Constraints_ShiftAmount);
323 }
324
325 static unsigned getKind(unsigned Flags) {
326 return Flags & 7;
327 }
328
329 static unsigned getMemoryConstraintID(unsigned Flag) {
330 assert(isMemKind(Flag))(static_cast <bool> (isMemKind(Flag)) ? void (0) : __assert_fail
("isMemKind(Flag)", "/build/llvm-toolchain-snapshot-6.0~svn318693/include/llvm/IR/InlineAsm.h"
, 330, __extension__ __PRETTY_FUNCTION__))
;
331 return (Flag >> Constraints_ShiftAmount) & 0x7fff;
332 }
333
334 /// getNumOperandRegisters - Extract the number of registers field from the
335 /// inline asm operand flag.
336 static unsigned getNumOperandRegisters(unsigned Flag) {
337 return (Flag & 0xffff) >> 3;
338 }
339
340 /// isUseOperandTiedToDef - Return true if the flag of the inline asm
341 /// operand indicates it is an use operand that's matched to a def operand.
342 static bool isUseOperandTiedToDef(unsigned Flag, unsigned &Idx) {
343 if ((Flag & Flag_MatchingOperand) == 0)
344 return false;
345 Idx = (Flag & ~Flag_MatchingOperand) >> 16;
346 return true;
347 }
348
349 /// hasRegClassConstraint - Returns true if the flag contains a register
350 /// class constraint. Sets RC to the register class ID.
351 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) {
352 if (Flag & Flag_MatchingOperand)
13
Taking false branch
353 return false;
354 unsigned High = Flag >> 16;
355 // getFlagWordForRegClass() uses 0 to mean no register class, and otherwise
356 // stores RC + 1.
357 if (!High)
14
Assuming 'High' is 0
15
Taking true branch
358 return false;
359 RC = High - 1;
360 return true;
361 }
362};
363
364} // end namespace llvm
365
366#endif // LLVM_IR_INLINEASM_H