Bug Summary

File:lib/Target/ARM/ARMISelLowering.cpp
Warning:line 900, column 13
Excessive padding in 'struct (anonymous at /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp:900:13)' (8 padding bytes, where 0 is optimal). Optimal fields order: Name, Op, CC, consider reordering the fields or adding explicit padding members

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/ARM -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMISelLowering.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMPerfectShuffle.h"
22#include "ARMRegisterInfo.h"
23#include "ARMSelectionDAGInfo.h"
24#include "ARMSubtarget.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGNodes.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/IR/Attributes.h"
66#include "llvm/IR/CallingConv.h"
67#include "llvm/IR/Constant.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugLoc.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GlobalAlias.h"
74#include "llvm/IR/GlobalValue.h"
75#include "llvm/IR/GlobalVariable.h"
76#include "llvm/IR/IRBuilder.h"
77#include "llvm/IR/InlineAsm.h"
78#include "llvm/IR/Instruction.h"
79#include "llvm/IR/Instructions.h"
80#include "llvm/IR/IntrinsicInst.h"
81#include "llvm/IR/Intrinsics.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/Type.h"
84#include "llvm/IR/User.h"
85#include "llvm/IR/Value.h"
86#include "llvm/MC/MCInstrDesc.h"
87#include "llvm/MC/MCInstrItineraries.h"
88#include "llvm/MC/MCRegisterInfo.h"
89#include "llvm/MC/MCSchedule.h"
90#include "llvm/Support/AtomicOrdering.h"
91#include "llvm/Support/BranchProbability.h"
92#include "llvm/Support/Casting.h"
93#include "llvm/Support/CodeGen.h"
94#include "llvm/Support/CommandLine.h"
95#include "llvm/Support/Compiler.h"
96#include "llvm/Support/Debug.h"
97#include "llvm/Support/ErrorHandling.h"
98#include "llvm/Support/KnownBits.h"
99#include "llvm/Support/MachineValueType.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116
117#define DEBUG_TYPE"arm-isel" "arm-isel"
118
119STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
120STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt", {0}, {false}
}
;
121STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments", {0}, {false
}}
;
122STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
123 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
;
124
125static cl::opt<bool>
126ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
128 cl::init(true));
129
130static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
133 "constant pools"),
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
138 cl::init(64));
139static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142 cl::init(128));
143
144// The APCS parameter registers.
145static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
147};
148
149void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157 }
158
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
169 } else {
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
174 }
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
187 }
188
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197 }
198
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211}
212
213void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216}
217
218void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221}
222
223ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
228
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
239 }
240
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
249 } LibraryCalls[] = {
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303 };
304
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
309 }
310 }
311
312 // Set the correct calling convention for ARMv7k WatchOS. It's just
313 // AAPCS_VFP for functions as simple as libcalls.
314 if (Subtarget->isTargetWatchABI()) {
315 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i)
316 setLibcallCallingConv((RTLIB::Libcall)i, CallingConv::ARM_AAPCS_VFP);
317 }
318 }
319
320 // These libcalls are not available in 32-bit.
321 setLibcallName(RTLIB::SHL_I128, nullptr);
322 setLibcallName(RTLIB::SRL_I128, nullptr);
323 setLibcallName(RTLIB::SRA_I128, nullptr);
324
325 // RTLIB
326 if (Subtarget->isAAPCS_ABI() &&
327 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
328 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
329 static const struct {
330 const RTLIB::Libcall Op;
331 const char * const Name;
332 const CallingConv::ID CC;
333 const ISD::CondCode Cond;
334 } LibraryCalls[] = {
335 // Double-precision floating-point arithmetic helper functions
336 // RTABI chapter 4.1.2, Table 2
337 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341
342 // Double-precision floating-point comparison helper functions
343 // RTABI chapter 4.1.2, Table 3
344 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
345 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
346 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
347 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
348 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
349 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
350 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
351 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
352
353 // Single-precision floating-point arithmetic helper functions
354 // RTABI chapter 4.1.2, Table 4
355 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
356 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
357 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
358 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
359
360 // Single-precision floating-point comparison helper functions
361 // RTABI chapter 4.1.2, Table 5
362 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
363 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
364 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
365 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
366 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
367 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
368 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
369 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
370
371 // Floating-point to integer conversions.
372 // RTABI chapter 4.1.2, Table 6
373 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
375 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
376 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
377 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
381
382 // Conversions between floating types.
383 // RTABI chapter 4.1.2, Table 7
384 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387
388 // Integer to floating-point conversions.
389 // RTABI chapter 4.1.2, Table 8
390 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
392 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
393 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
394 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398
399 // Long long helper functions
400 // RTABI chapter 4.2, Table 9
401 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405
406 // Integer division functions
407 // RTABI chapter 4.3.1
408 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
410 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
411 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
412 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
413 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
414 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
415 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
416 };
417
418 for (const auto &LC : LibraryCalls) {
419 setLibcallName(LC.Op, LC.Name);
420 setLibcallCallingConv(LC.Op, LC.CC);
421 if (LC.Cond != ISD::SETCC_INVALID)
422 setCmpLibcallCC(LC.Op, LC.Cond);
423 }
424
425 // EABI dependent RTLIB
426 if (TM.Options.EABIVersion == EABI::EABI4 ||
427 TM.Options.EABIVersion == EABI::EABI5) {
428 static const struct {
429 const RTLIB::Libcall Op;
430 const char *const Name;
431 const CallingConv::ID CC;
432 const ISD::CondCode Cond;
433 } MemOpsLibraryCalls[] = {
434 // Memory operations
435 // RTABI chapter 4.3.4
436 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
437 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
438 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
439 };
440
441 for (const auto &LC : MemOpsLibraryCalls) {
442 setLibcallName(LC.Op, LC.Name);
443 setLibcallCallingConv(LC.Op, LC.CC);
444 if (LC.Cond != ISD::SETCC_INVALID)
445 setCmpLibcallCC(LC.Op, LC.Cond);
446 }
447 }
448 }
449
450 if (Subtarget->isTargetWindows()) {
451 static const struct {
452 const RTLIB::Libcall Op;
453 const char * const Name;
454 const CallingConv::ID CC;
455 } LibraryCalls[] = {
456 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
457 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
458 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
459 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
460 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
461 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
462 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
463 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
464 };
465
466 for (const auto &LC : LibraryCalls) {
467 setLibcallName(LC.Op, LC.Name);
468 setLibcallCallingConv(LC.Op, LC.CC);
469 }
470 }
471
472 // Use divmod compiler-rt calls for iOS 5.0 and later.
473 if (Subtarget->isTargetMachO() &&
474 !(Subtarget->isTargetIOS() &&
475 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
476 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
477 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
478 }
479
480 // The half <-> float conversion functions are always soft-float on
481 // non-watchos platforms, but are needed for some targets which use a
482 // hard-float calling convention by default.
483 if (!Subtarget->isTargetWatchABI()) {
484 if (Subtarget->isAAPCS_ABI()) {
485 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
486 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
487 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
488 } else {
489 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
490 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
491 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
492 }
493 }
494
495 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
496 // a __gnu_ prefix (which is the default).
497 if (Subtarget->isTargetAEABI()) {
498 static const struct {
499 const RTLIB::Libcall Op;
500 const char * const Name;
501 const CallingConv::ID CC;
502 } LibraryCalls[] = {
503 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
504 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
505 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
506 };
507
508 for (const auto &LC : LibraryCalls) {
509 setLibcallName(LC.Op, LC.Name);
510 setLibcallCallingConv(LC.Op, LC.CC);
511 }
512 }
513
514 if (Subtarget->isThumb1Only())
515 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
516 else
517 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
518
519 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
520 !Subtarget->isThumb1Only()) {
521 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
522 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
523 }
524
525 if (Subtarget->hasFullFP16()) {
526 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
527 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
528 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
529 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
530 }
531
532 for (MVT VT : MVT::vector_valuetypes()) {
533 for (MVT InnerVT : MVT::vector_valuetypes()) {
534 setTruncStoreAction(VT, InnerVT, Expand);
535 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
536 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
537 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
538 }
539
540 setOperationAction(ISD::MULHS, VT, Expand);
541 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
542 setOperationAction(ISD::MULHU, VT, Expand);
543 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
544
545 setOperationAction(ISD::BSWAP, VT, Expand);
546 }
547
548 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
549 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
550
551 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
552 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
553
554 if (Subtarget->hasNEON()) {
555 addDRTypeForNEON(MVT::v2f32);
556 addDRTypeForNEON(MVT::v8i8);
557 addDRTypeForNEON(MVT::v4i16);
558 addDRTypeForNEON(MVT::v2i32);
559 addDRTypeForNEON(MVT::v1i64);
560
561 addQRTypeForNEON(MVT::v4f32);
562 addQRTypeForNEON(MVT::v2f64);
563 addQRTypeForNEON(MVT::v16i8);
564 addQRTypeForNEON(MVT::v8i16);
565 addQRTypeForNEON(MVT::v4i32);
566 addQRTypeForNEON(MVT::v2i64);
567
568 if (Subtarget->hasFullFP16()) {
569 addQRTypeForNEON(MVT::v8f16);
570 addDRTypeForNEON(MVT::v4f16);
571 }
572
573 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
574 // neither Neon nor VFP support any arithmetic operations on it.
575 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
576 // supported for v4f32.
577 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
578 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
579 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
580 // FIXME: Code duplication: FDIV and FREM are expanded always, see
581 // ARMTargetLowering::addTypeForNEON method for details.
582 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
583 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
584 // FIXME: Create unittest.
585 // In another words, find a way when "copysign" appears in DAG with vector
586 // operands.
587 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
588 // FIXME: Code duplication: SETCC has custom operation action, see
589 // ARMTargetLowering::addTypeForNEON method for details.
590 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
591 // FIXME: Create unittest for FNEG and for FABS.
592 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
593 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
594 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
595 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
596 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
597 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
598 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
599 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
600 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
601 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
602 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
603 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
604 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
605 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
606 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
607 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
608 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
609 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
610
611 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
612 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
613 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
614 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
615 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
616 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
617 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
618 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
619 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
620 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
621 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
622 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
623 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
624 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
625
626 // Mark v2f32 intrinsics.
627 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
628 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
629 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
630 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
631 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
632 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
633 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
634 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
635 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
636 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
637 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
638 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
639 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
640 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
641
642 // Neon does not support some operations on v1i64 and v2i64 types.
643 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
644 // Custom handling for some quad-vector types to detect VMULL.
645 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
646 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
647 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
648 // Custom handling for some vector types to avoid expensive expansions
649 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
650 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
651 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
652 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
653 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
654 // a destination type that is wider than the source, and nor does
655 // it have a FP_TO_[SU]INT instruction with a narrower destination than
656 // source.
657 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
658 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
659 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
660 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
661
662 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
663 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
664
665 // NEON does not have single instruction CTPOP for vectors with element
666 // types wider than 8-bits. However, custom lowering can leverage the
667 // v8i8/v16i8 vcnt instruction.
668 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
669 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
670 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
671 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
672 setOperationAction(ISD::CTPOP, MVT::v1i64, Expand);
673 setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
674
675 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
676 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
677
678 // NEON does not have single instruction CTTZ for vectors.
679 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
680 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
683
684 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
685 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
686 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
687 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
688
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
693
694 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
695 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
696 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
697 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
698
699 // NEON only has FMA instructions as of VFP4.
700 if (!Subtarget->hasVFP4()) {
701 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
702 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
703 }
704
705 setTargetDAGCombine(ISD::INTRINSIC_VOID);
706 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
707 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
708 setTargetDAGCombine(ISD::SHL);
709 setTargetDAGCombine(ISD::SRL);
710 setTargetDAGCombine(ISD::SRA);
711 setTargetDAGCombine(ISD::SIGN_EXTEND);
712 setTargetDAGCombine(ISD::ZERO_EXTEND);
713 setTargetDAGCombine(ISD::ANY_EXTEND);
714 setTargetDAGCombine(ISD::BUILD_VECTOR);
715 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
716 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
717 setTargetDAGCombine(ISD::STORE);
718 setTargetDAGCombine(ISD::FP_TO_SINT);
719 setTargetDAGCombine(ISD::FP_TO_UINT);
720 setTargetDAGCombine(ISD::FDIV);
721 setTargetDAGCombine(ISD::LOAD);
722
723 // It is legal to extload from v4i8 to v4i16 or v4i32.
724 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
725 MVT::v2i32}) {
726 for (MVT VT : MVT::integer_vector_valuetypes()) {
727 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
728 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
729 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
730 }
731 }
732 }
733
734 if (Subtarget->isFPOnlySP()) {
735 // When targeting a floating-point unit with only single-precision
736 // operations, f64 is legal for the few double-precision instructions which
737 // are present However, no double-precision operations other than moves,
738 // loads and stores are provided by the hardware.
739 setOperationAction(ISD::FADD, MVT::f64, Expand);
740 setOperationAction(ISD::FSUB, MVT::f64, Expand);
741 setOperationAction(ISD::FMUL, MVT::f64, Expand);
742 setOperationAction(ISD::FMA, MVT::f64, Expand);
743 setOperationAction(ISD::FDIV, MVT::f64, Expand);
744 setOperationAction(ISD::FREM, MVT::f64, Expand);
745 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
746 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
747 setOperationAction(ISD::FNEG, MVT::f64, Expand);
748 setOperationAction(ISD::FABS, MVT::f64, Expand);
749 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
750 setOperationAction(ISD::FSIN, MVT::f64, Expand);
751 setOperationAction(ISD::FCOS, MVT::f64, Expand);
752 setOperationAction(ISD::FPOW, MVT::f64, Expand);
753 setOperationAction(ISD::FLOG, MVT::f64, Expand);
754 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
755 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
756 setOperationAction(ISD::FEXP, MVT::f64, Expand);
757 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
758 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
759 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
760 setOperationAction(ISD::FRINT, MVT::f64, Expand);
761 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
762 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
763 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
764 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
766 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
767 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
768 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
769 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
770 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
771 }
772
773 computeRegisterProperties(Subtarget->getRegisterInfo());
774
775 // ARM does not have floating-point extending loads.
776 for (MVT VT : MVT::fp_valuetypes()) {
777 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
778 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
779 }
780
781 // ... or truncating stores
782 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
783 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
784 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
785
786 // ARM does not have i1 sign extending load.
787 for (MVT VT : MVT::integer_valuetypes())
788 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
789
790 // ARM supports all 4 flavors of integer indexed load / store.
791 if (!Subtarget->isThumb1Only()) {
792 for (unsigned im = (unsigned)ISD::PRE_INC;
793 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
794 setIndexedLoadAction(im, MVT::i1, Legal);
795 setIndexedLoadAction(im, MVT::i8, Legal);
796 setIndexedLoadAction(im, MVT::i16, Legal);
797 setIndexedLoadAction(im, MVT::i32, Legal);
798 setIndexedStoreAction(im, MVT::i1, Legal);
799 setIndexedStoreAction(im, MVT::i8, Legal);
800 setIndexedStoreAction(im, MVT::i16, Legal);
801 setIndexedStoreAction(im, MVT::i32, Legal);
802 }
803 } else {
804 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
805 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
806 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
807 }
808
809 setOperationAction(ISD::SADDO, MVT::i32, Custom);
810 setOperationAction(ISD::UADDO, MVT::i32, Custom);
811 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
812 setOperationAction(ISD::USUBO, MVT::i32, Custom);
813
814 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
815 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
816
817 // i64 operation support.
818 setOperationAction(ISD::MUL, MVT::i64, Expand);
819 setOperationAction(ISD::MULHU, MVT::i32, Expand);
820 if (Subtarget->isThumb1Only()) {
821 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
822 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
823 }
824 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
825 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
826 setOperationAction(ISD::MULHS, MVT::i32, Expand);
827
828 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
829 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
830 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
831 setOperationAction(ISD::SRL, MVT::i64, Custom);
832 setOperationAction(ISD::SRA, MVT::i64, Custom);
833 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
834
835 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
836 if (Subtarget->isThumb1Only()) {
837 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
838 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
839 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
840 }
841
842 setOperationAction(ISD::ADDC, MVT::i32, Custom);
843 setOperationAction(ISD::ADDE, MVT::i32, Custom);
844 setOperationAction(ISD::SUBC, MVT::i32, Custom);
845 setOperationAction(ISD::SUBE, MVT::i32, Custom);
846
847 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
848 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
849
850 // ARM does not have ROTL.
851 setOperationAction(ISD::ROTL, MVT::i32, Expand);
852 for (MVT VT : MVT::vector_valuetypes()) {
853 setOperationAction(ISD::ROTL, VT, Expand);
854 setOperationAction(ISD::ROTR, VT, Expand);
855 }
856 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
857 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
858 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
859 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
860
861 // @llvm.readcyclecounter requires the Performance Monitors extension.
862 // Default to the 0 expansion on unsupported platforms.
863 // FIXME: Technically there are older ARM CPUs that have
864 // implementation-specific ways of obtaining this information.
865 if (Subtarget->hasPerfMon())
866 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
867
868 // Only ARMv6 has BSWAP.
869 if (!Subtarget->hasV6Ops())
870 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
871
872 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
873 : Subtarget->hasDivideInARMMode();
874 if (!hasDivide) {
875 // These are expanded into libcalls if the cpu doesn't have HW divider.
876 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
877 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
878 }
879
880 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
881 setOperationAction(ISD::SDIV, MVT::i32, Custom);
882 setOperationAction(ISD::UDIV, MVT::i32, Custom);
883
884 setOperationAction(ISD::SDIV, MVT::i64, Custom);
885 setOperationAction(ISD::UDIV, MVT::i64, Custom);
886 }
887
888 setOperationAction(ISD::SREM, MVT::i32, Expand);
889 setOperationAction(ISD::UREM, MVT::i32, Expand);
890
891 // Register based DivRem for AEABI (RTABI 4.2)
892 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
893 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
894 Subtarget->isTargetWindows()) {
895 setOperationAction(ISD::SREM, MVT::i64, Custom);
896 setOperationAction(ISD::UREM, MVT::i64, Custom);
897 HasStandaloneRem = false;
898
899 if (Subtarget->isTargetWindows()) {
900 const struct {
Excessive padding in 'struct (anonymous at /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp:900:13)' (8 padding bytes, where 0 is optimal). Optimal fields order: Name, Op, CC, consider reordering the fields or adding explicit padding members
901 const RTLIB::Libcall Op;
902 const char * const Name;
903 const CallingConv::ID CC;
904 } LibraryCalls[] = {
905 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
906 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
907 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
908 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
909
910 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
911 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
912 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
913 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
914 };
915
916 for (const auto &LC : LibraryCalls) {
917 setLibcallName(LC.Op, LC.Name);
918 setLibcallCallingConv(LC.Op, LC.CC);
919 }
920 } else {
921 const struct {
922 const RTLIB::Libcall Op;
923 const char * const Name;
924 const CallingConv::ID CC;
925 } LibraryCalls[] = {
926 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
927 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
928 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
929 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
930
931 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
932 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
933 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
934 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
935 };
936
937 for (const auto &LC : LibraryCalls) {
938 setLibcallName(LC.Op, LC.Name);
939 setLibcallCallingConv(LC.Op, LC.CC);
940 }
941 }
942
943 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
944 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
945 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
946 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
947 } else {
948 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
949 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
950 }
951
952 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
953 for (auto &VT : {MVT::f32, MVT::f64})
954 setOperationAction(ISD::FPOWI, VT, Custom);
955
956 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
957 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
958 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
959 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
960
961 setOperationAction(ISD::TRAP, MVT::Other, Legal);
962
963 // Use the default implementation.
964 setOperationAction(ISD::VASTART, MVT::Other, Custom);
965 setOperationAction(ISD::VAARG, MVT::Other, Expand);
966 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
967 setOperationAction(ISD::VAEND, MVT::Other, Expand);
968 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
969 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
970
971 if (Subtarget->isTargetWindows())
972 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
973 else
974 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
975
976 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
977 // the default expansion.
978 InsertFencesForAtomic = false;
979 if (Subtarget->hasAnyDataBarrier() &&
980 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
981 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
982 // to ldrex/strex loops already.
983 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
984 if (!Subtarget->isThumb() || !Subtarget->isMClass())
985 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
986
987 // On v8, we have particularly efficient implementations of atomic fences
988 // if they can be combined with nearby atomic loads and stores.
989 if (!Subtarget->hasV8Ops() || getTargetMachine().getOptLevel() == 0) {
990 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
991 InsertFencesForAtomic = true;
992 }
993 } else {
994 // If there's anything we can use as a barrier, go through custom lowering
995 // for ATOMIC_FENCE.
996 // If target has DMB in thumb, Fences can be inserted.
997 if (Subtarget->hasDataBarrier())
998 InsertFencesForAtomic = true;
999
1000 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1001 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1002
1003 // Set them all for expansion, which will force libcalls.
1004 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1007 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1008 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1009 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1010 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1011 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1012 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1013 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1014 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1015 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1016 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1017 // Unordered/Monotonic case.
1018 if (!InsertFencesForAtomic) {
1019 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1020 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1021 }
1022 }
1023
1024 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1025
1026 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1027 if (!Subtarget->hasV6Ops()) {
1028 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1029 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1030 }
1031 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1032
1033 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1034 !Subtarget->isThumb1Only()) {
1035 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1036 // iff target supports vfp2.
1037 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1038 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1039 }
1040
1041 // We want to custom lower some of our intrinsics.
1042 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1043 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1044 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1045 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1046 if (Subtarget->useSjLjEH())
1047 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1048
1049 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1050 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1051 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1052 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1053 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1054 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1055 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1056 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1057 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1058 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1059 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1060
1061 // Thumb-1 cannot currently select ARMISD::SUBE.
1062 if (!Subtarget->isThumb1Only())
1063 setOperationAction(ISD::SETCCE, MVT::i32, Custom);
1064
1065 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1066 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1067 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1068 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1069 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1070 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1071
1072 // We don't support sin/cos/fmod/copysign/pow
1073 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1074 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1075 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1076 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1077 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1078 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1079 setOperationAction(ISD::FREM, MVT::f64, Expand);
1080 setOperationAction(ISD::FREM, MVT::f32, Expand);
1081 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1082 !Subtarget->isThumb1Only()) {
1083 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1084 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1085 }
1086 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1087 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1088
1089 if (!Subtarget->hasVFP4()) {
1090 setOperationAction(ISD::FMA, MVT::f64, Expand);
1091 setOperationAction(ISD::FMA, MVT::f32, Expand);
1092 }
1093
1094 // Various VFP goodness
1095 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1096 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1097 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1098 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1099 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1100 }
1101
1102 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1103 if (!Subtarget->hasFP16()) {
1104 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1105 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1106 }
1107 }
1108
1109 // Use __sincos_stret if available.
1110 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1111 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1112 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1113 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1114 }
1115
1116 // FP-ARMv8 implements a lot of rounding-like FP operations.
1117 if (Subtarget->hasFPARMv8()) {
1118 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1119 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1120 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1121 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1122 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1123 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1124 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1125 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1126 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1127 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1128 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1129 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1130
1131 if (!Subtarget->isFPOnlySP()) {
1132 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1134 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1135 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1137 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1138 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1139 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1140 }
1141 }
1142
1143 if (Subtarget->hasNEON()) {
1144 // vmin and vmax aren't available in a scalar form, so we use
1145 // a NEON instruction with an undef lane instead.
1146 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1147 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
1148 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1149 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
1150 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
1151 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
1152 }
1153
1154 // We have target-specific dag combine patterns for the following nodes:
1155 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1156 setTargetDAGCombine(ISD::ADD);
1157 setTargetDAGCombine(ISD::SUB);
1158 setTargetDAGCombine(ISD::MUL);
1159 setTargetDAGCombine(ISD::AND);
1160 setTargetDAGCombine(ISD::OR);
1161 setTargetDAGCombine(ISD::XOR);
1162
1163 if (Subtarget->hasV6Ops())
1164 setTargetDAGCombine(ISD::SRL);
1165
1166 setStackPointerRegisterToSaveRestore(ARM::SP);
1167
1168 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1169 !Subtarget->hasVFP2())
1170 setSchedulingPreference(Sched::RegPressure);
1171 else
1172 setSchedulingPreference(Sched::Hybrid);
1173
1174 //// temporary - rewrite interface to use type
1175 MaxStoresPerMemset = 8;
1176 MaxStoresPerMemsetOptSize = 4;
1177 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1178 MaxStoresPerMemcpyOptSize = 2;
1179 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1180 MaxStoresPerMemmoveOptSize = 2;
1181
1182 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1183 // are at least 4 bytes aligned.
1184 setMinStackArgumentAlignment(4);
1185
1186 // Prefer likely predicted branches to selects on out-of-order cores.
1187 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1188
1189 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1190}
1191
1192bool ARMTargetLowering::useSoftFloat() const {
1193 return Subtarget->useSoftFloat();
1194}
1195
1196// FIXME: It might make sense to define the representative register class as the
1197// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1198// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1199// SPR's representative would be DPR_VFP2. This should work well if register
1200// pressure tracking were modified such that a register use would increment the
1201// pressure of the register class's representative and all of it's super
1202// classes' representatives transitively. We have not implemented this because
1203// of the difficulty prior to coalescing of modeling operand register classes
1204// due to the common occurrence of cross class copies and subregister insertions
1205// and extractions.
1206std::pair<const TargetRegisterClass *, uint8_t>
1207ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1208 MVT VT) const {
1209 const TargetRegisterClass *RRC = nullptr;
1210 uint8_t Cost = 1;
1211 switch (VT.SimpleTy) {
1212 default:
1213 return TargetLowering::findRepresentativeClass(TRI, VT);
1214 // Use DPR as representative register class for all floating point
1215 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1216 // the cost is 1 for both f32 and f64.
1217 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1218 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1219 RRC = &ARM::DPRRegClass;
1220 // When NEON is used for SP, only half of the register file is available
1221 // because operations that define both SP and DP results will be constrained
1222 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1223 // coalescing by double-counting the SP regs. See the FIXME above.
1224 if (Subtarget->useNEONForSinglePrecisionFP())
1225 Cost = 2;
1226 break;
1227 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1228 case MVT::v4f32: case MVT::v2f64:
1229 RRC = &ARM::DPRRegClass;
1230 Cost = 2;
1231 break;
1232 case MVT::v4i64:
1233 RRC = &ARM::DPRRegClass;
1234 Cost = 4;
1235 break;
1236 case MVT::v8i64:
1237 RRC = &ARM::DPRRegClass;
1238 Cost = 8;
1239 break;
1240 }
1241 return std::make_pair(RRC, Cost);
1242}
1243
1244const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1245 switch ((ARMISD::NodeType)Opcode) {
1246 case ARMISD::FIRST_NUMBER: break;
1247 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1248 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1249 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1250 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1251 case ARMISD::CALL: return "ARMISD::CALL";
1252 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1253 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1254 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1255 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1256 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1257 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1258 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1259 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1260 case ARMISD::CMP: return "ARMISD::CMP";
1261 case ARMISD::CMN: return "ARMISD::CMN";
1262 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1263 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1264 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1265 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1266 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1267
1268 case ARMISD::CMOV: return "ARMISD::CMOV";
1269
1270 case ARMISD::SSAT: return "ARMISD::SSAT";
1271 case ARMISD::USAT: return "ARMISD::USAT";
1272
1273 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1274 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1275 case ARMISD::RRX: return "ARMISD::RRX";
1276
1277 case ARMISD::ADDC: return "ARMISD::ADDC";
1278 case ARMISD::ADDE: return "ARMISD::ADDE";
1279 case ARMISD::SUBC: return "ARMISD::SUBC";
1280 case ARMISD::SUBE: return "ARMISD::SUBE";
1281
1282 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1283 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1284 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1285 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1286 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1287
1288 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1289 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1290 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1291
1292 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1293
1294 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1295
1296 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1297
1298 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1299
1300 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1301
1302 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1303 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1304
1305 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1306 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1307 case ARMISD::VCGE: return "ARMISD::VCGE";
1308 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1309 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1310 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1311 case ARMISD::VCGT: return "ARMISD::VCGT";
1312 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1313 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1314 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1315 case ARMISD::VTST: return "ARMISD::VTST";
1316
1317 case ARMISD::VSHL: return "ARMISD::VSHL";
1318 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1319 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1320 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1321 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1322 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1323 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1324 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1325 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1326 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1327 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1328 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1329 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1330 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1331 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1332 case ARMISD::VSLI: return "ARMISD::VSLI";
1333 case ARMISD::VSRI: return "ARMISD::VSRI";
1334 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1335 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1336 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1337 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1338 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1339 case ARMISD::VDUP: return "ARMISD::VDUP";
1340 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1341 case ARMISD::VEXT: return "ARMISD::VEXT";
1342 case ARMISD::VREV64: return "ARMISD::VREV64";
1343 case ARMISD::VREV32: return "ARMISD::VREV32";
1344 case ARMISD::VREV16: return "ARMISD::VREV16";
1345 case ARMISD::VZIP: return "ARMISD::VZIP";
1346 case ARMISD::VUZP: return "ARMISD::VUZP";
1347 case ARMISD::VTRN: return "ARMISD::VTRN";
1348 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1349 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1350 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1351 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1352 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1353 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1354 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1355 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1356 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1357 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1358 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1359 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1360 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1361 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1362 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1363 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1364 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1365 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1366 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1367 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1368 case ARMISD::BFI: return "ARMISD::BFI";
1369 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1370 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1371 case ARMISD::VBSL: return "ARMISD::VBSL";
1372 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1373 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1374 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1375 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1376 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1377 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1378 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1379 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1380 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1381 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1382 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1383 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1384 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1385 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1386 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1387 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1388 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1389 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1390 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1391 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1392 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1393 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1394 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1395 }
1396 return nullptr;
1397}
1398
1399EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1400 EVT VT) const {
1401 if (!VT.isVector())
1402 return getPointerTy(DL);
1403 return VT.changeVectorElementTypeToInteger();
1404}
1405
1406/// getRegClassFor - Return the register class that should be used for the
1407/// specified value type.
1408const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1409 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1410 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1411 // load / store 4 to 8 consecutive D registers.
1412 if (Subtarget->hasNEON()) {
1413 if (VT == MVT::v4i64)
1414 return &ARM::QQPRRegClass;
1415 if (VT == MVT::v8i64)
1416 return &ARM::QQQQPRRegClass;
1417 }
1418 return TargetLowering::getRegClassFor(VT);
1419}
1420
1421// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1422// source/dest is aligned and the copy size is large enough. We therefore want
1423// to align such objects passed to memory intrinsics.
1424bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1425 unsigned &PrefAlign) const {
1426 if (!isa<MemIntrinsic>(CI))
1427 return false;
1428 MinSize = 8;
1429 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1430 // cycle faster than 4-byte aligned LDM.
1431 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1432 return true;
1433}
1434
1435// Create a fast isel object.
1436FastISel *
1437ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1438 const TargetLibraryInfo *libInfo) const {
1439 return ARM::createFastISel(funcInfo, libInfo);
1440}
1441
1442Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1443 unsigned NumVals = N->getNumValues();
1444 if (!NumVals)
1445 return Sched::RegPressure;
1446
1447 for (unsigned i = 0; i != NumVals; ++i) {
1448 EVT VT = N->getValueType(i);
1449 if (VT == MVT::Glue || VT == MVT::Other)
1450 continue;
1451 if (VT.isFloatingPoint() || VT.isVector())
1452 return Sched::ILP;
1453 }
1454
1455 if (!N->isMachineOpcode())
1456 return Sched::RegPressure;
1457
1458 // Load are scheduled for latency even if there instruction itinerary
1459 // is not available.
1460 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1461 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1462
1463 if (MCID.getNumDefs() == 0)
1464 return Sched::RegPressure;
1465 if (!Itins->isEmpty() &&
1466 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1467 return Sched::ILP;
1468
1469 return Sched::RegPressure;
1470}
1471
1472//===----------------------------------------------------------------------===//
1473// Lowering Code
1474//===----------------------------------------------------------------------===//
1475
1476static bool isSRL16(const SDValue &Op) {
1477 if (Op.getOpcode() != ISD::SRL)
1478 return false;
1479 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1480 return Const->getZExtValue() == 16;
1481 return false;
1482}
1483
1484static bool isSRA16(const SDValue &Op) {
1485 if (Op.getOpcode() != ISD::SRA)
1486 return false;
1487 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1488 return Const->getZExtValue() == 16;
1489 return false;
1490}
1491
1492static bool isSHL16(const SDValue &Op) {
1493 if (Op.getOpcode() != ISD::SHL)
1494 return false;
1495 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1496 return Const->getZExtValue() == 16;
1497 return false;
1498}
1499
1500// Check for a signed 16-bit value. We special case SRA because it makes it
1501// more simple when also looking for SRAs that aren't sign extending a
1502// smaller value. Without the check, we'd need to take extra care with
1503// checking order for some operations.
1504static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1505 if (isSRA16(Op))
1506 return isSHL16(Op.getOperand(0));
1507 return DAG.ComputeNumSignBits(Op) == 17;
1508}
1509
1510/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1511static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1512 switch (CC) {
1513 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1513)
;
1514 case ISD::SETNE: return ARMCC::NE;
1515 case ISD::SETEQ: return ARMCC::EQ;
1516 case ISD::SETGT: return ARMCC::GT;
1517 case ISD::SETGE: return ARMCC::GE;
1518 case ISD::SETLT: return ARMCC::LT;
1519 case ISD::SETLE: return ARMCC::LE;
1520 case ISD::SETUGT: return ARMCC::HI;
1521 case ISD::SETUGE: return ARMCC::HS;
1522 case ISD::SETULT: return ARMCC::LO;
1523 case ISD::SETULE: return ARMCC::LS;
1524 }
1525}
1526
1527/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1528static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1529 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1530 CondCode2 = ARMCC::AL;
1531 InvalidOnQNaN = true;
1532 switch (CC) {
1533 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1533)
;
1534 case ISD::SETEQ:
1535 case ISD::SETOEQ:
1536 CondCode = ARMCC::EQ;
1537 InvalidOnQNaN = false;
1538 break;
1539 case ISD::SETGT:
1540 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1541 case ISD::SETGE:
1542 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1543 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1544 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1545 case ISD::SETONE:
1546 CondCode = ARMCC::MI;
1547 CondCode2 = ARMCC::GT;
1548 InvalidOnQNaN = false;
1549 break;
1550 case ISD::SETO: CondCode = ARMCC::VC; break;
1551 case ISD::SETUO: CondCode = ARMCC::VS; break;
1552 case ISD::SETUEQ:
1553 CondCode = ARMCC::EQ;
1554 CondCode2 = ARMCC::VS;
1555 InvalidOnQNaN = false;
1556 break;
1557 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1558 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1559 case ISD::SETLT:
1560 case ISD::SETULT: CondCode = ARMCC::LT; break;
1561 case ISD::SETLE:
1562 case ISD::SETULE: CondCode = ARMCC::LE; break;
1563 case ISD::SETNE:
1564 case ISD::SETUNE:
1565 CondCode = ARMCC::NE;
1566 InvalidOnQNaN = false;
1567 break;
1568 }
1569}
1570
1571//===----------------------------------------------------------------------===//
1572// Calling Convention Implementation
1573//===----------------------------------------------------------------------===//
1574
1575#include "ARMGenCallingConv.inc"
1576
1577/// getEffectiveCallingConv - Get the effective calling convention, taking into
1578/// account presence of floating point hardware and calling convention
1579/// limitations, such as support for variadic functions.
1580CallingConv::ID
1581ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1582 bool isVarArg) const {
1583 switch (CC) {
1584 default:
1585 report_fatal_error("Unsupported calling convention");
1586 case CallingConv::ARM_AAPCS:
1587 case CallingConv::ARM_APCS:
1588 case CallingConv::GHC:
1589 return CC;
1590 case CallingConv::PreserveMost:
1591 return CallingConv::PreserveMost;
1592 case CallingConv::ARM_AAPCS_VFP:
1593 case CallingConv::Swift:
1594 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1595 case CallingConv::C:
1596 if (!Subtarget->isAAPCS_ABI())
1597 return CallingConv::ARM_APCS;
1598 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1599 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1600 !isVarArg)
1601 return CallingConv::ARM_AAPCS_VFP;
1602 else
1603 return CallingConv::ARM_AAPCS;
1604 case CallingConv::Fast:
1605 case CallingConv::CXX_FAST_TLS:
1606 if (!Subtarget->isAAPCS_ABI()) {
1607 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1608 return CallingConv::Fast;
1609 return CallingConv::ARM_APCS;
1610 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1611 return CallingConv::ARM_AAPCS_VFP;
1612 else
1613 return CallingConv::ARM_AAPCS;
1614 }
1615}
1616
1617CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1618 bool isVarArg) const {
1619 return CCAssignFnForNode(CC, false, isVarArg);
1620}
1621
1622CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1623 bool isVarArg) const {
1624 return CCAssignFnForNode(CC, true, isVarArg);
1625}
1626
1627/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1628/// CallingConvention.
1629CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1630 bool Return,
1631 bool isVarArg) const {
1632 switch (getEffectiveCallingConv(CC, isVarArg)) {
1633 default:
1634 report_fatal_error("Unsupported calling convention");
1635 case CallingConv::ARM_APCS:
1636 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1637 case CallingConv::ARM_AAPCS:
1638 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1639 case CallingConv::ARM_AAPCS_VFP:
1640 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1641 case CallingConv::Fast:
1642 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1643 case CallingConv::GHC:
1644 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1645 case CallingConv::PreserveMost:
1646 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1647 }
1648}
1649
1650/// LowerCallResult - Lower the result values of a call into the
1651/// appropriate copies out of appropriate physical registers.
1652SDValue ARMTargetLowering::LowerCallResult(
1653 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1654 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1655 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1656 SDValue ThisVal) const {
1657 // Assign locations to each value returned by this call.
1658 SmallVector<CCValAssign, 16> RVLocs;
1659 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1660 *DAG.getContext());
1661 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1662
1663 // Copy all of the result registers out of their specified physreg.
1664 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1665 CCValAssign VA = RVLocs[i];
1666
1667 // Pass 'this' value directly from the argument to return value, to avoid
1668 // reg unit interference
1669 if (i == 0 && isThisReturn) {
1670 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1671, __extension__ __PRETTY_FUNCTION__))
1671 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1671, __extension__ __PRETTY_FUNCTION__))
;
1672 InVals.push_back(ThisVal);
1673 continue;
1674 }
1675
1676 SDValue Val;
1677 if (VA.needsCustom()) {
1678 // Handle f64 or half of a v2f64.
1679 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1680 InFlag);
1681 Chain = Lo.getValue(1);
1682 InFlag = Lo.getValue(2);
1683 VA = RVLocs[++i]; // skip ahead to next loc
1684 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1685 InFlag);
1686 Chain = Hi.getValue(1);
1687 InFlag = Hi.getValue(2);
1688 if (!Subtarget->isLittle())
1689 std::swap (Lo, Hi);
1690 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1691
1692 if (VA.getLocVT() == MVT::v2f64) {
1693 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1694 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1695 DAG.getConstant(0, dl, MVT::i32));
1696
1697 VA = RVLocs[++i]; // skip ahead to next loc
1698 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1699 Chain = Lo.getValue(1);
1700 InFlag = Lo.getValue(2);
1701 VA = RVLocs[++i]; // skip ahead to next loc
1702 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1703 Chain = Hi.getValue(1);
1704 InFlag = Hi.getValue(2);
1705 if (!Subtarget->isLittle())
1706 std::swap (Lo, Hi);
1707 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1708 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1709 DAG.getConstant(1, dl, MVT::i32));
1710 }
1711 } else {
1712 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1713 InFlag);
1714 Chain = Val.getValue(1);
1715 InFlag = Val.getValue(2);
1716 }
1717
1718 switch (VA.getLocInfo()) {
1719 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1719)
;
1720 case CCValAssign::Full: break;
1721 case CCValAssign::BCvt:
1722 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1723 break;
1724 }
1725
1726 InVals.push_back(Val);
1727 }
1728
1729 return Chain;
1730}
1731
1732/// LowerMemOpCallTo - Store the argument to the stack.
1733SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1734 SDValue Arg, const SDLoc &dl,
1735 SelectionDAG &DAG,
1736 const CCValAssign &VA,
1737 ISD::ArgFlagsTy Flags) const {
1738 unsigned LocMemOffset = VA.getLocMemOffset();
1739 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1740 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1741 StackPtr, PtrOff);
1742 return DAG.getStore(
1743 Chain, dl, Arg, PtrOff,
1744 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1745}
1746
1747void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1748 SDValue Chain, SDValue &Arg,
1749 RegsToPassVector &RegsToPass,
1750 CCValAssign &VA, CCValAssign &NextVA,
1751 SDValue &StackPtr,
1752 SmallVectorImpl<SDValue> &MemOpChains,
1753 ISD::ArgFlagsTy Flags) const {
1754 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1755 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1756 unsigned id = Subtarget->isLittle() ? 0 : 1;
1757 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1758
1759 if (NextVA.isRegLoc())
1760 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1761 else {
1762 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1762, __extension__ __PRETTY_FUNCTION__))
;
1763 if (!StackPtr.getNode())
1764 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1765 getPointerTy(DAG.getDataLayout()));
1766
1767 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1768 dl, DAG, NextVA,
1769 Flags));
1770 }
1771}
1772
1773/// LowerCall - Lowering a call into a callseq_start <-
1774/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1775/// nodes.
1776SDValue
1777ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1778 SmallVectorImpl<SDValue> &InVals) const {
1779 SelectionDAG &DAG = CLI.DAG;
1780 SDLoc &dl = CLI.DL;
1781 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1782 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1783 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1784 SDValue Chain = CLI.Chain;
1785 SDValue Callee = CLI.Callee;
1786 bool &isTailCall = CLI.IsTailCall;
1787 CallingConv::ID CallConv = CLI.CallConv;
1788 bool doesNotRet = CLI.DoesNotReturn;
1789 bool isVarArg = CLI.IsVarArg;
1790
1791 MachineFunction &MF = DAG.getMachineFunction();
1792 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1793 bool isThisReturn = false;
1794 bool isSibCall = false;
1795 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1796
1797 // Disable tail calls if they're not supported.
1798 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1799 isTailCall = false;
1800
1801 if (isTailCall) {
1802 // Check if it's really possible to do a tail call.
1803 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1804 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1805 Outs, OutVals, Ins, DAG);
1806 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1807 report_fatal_error("failed to perform tail call elimination on a call "
1808 "site marked musttail");
1809 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1810 // detected sibcalls.
1811 if (isTailCall) {
1812 ++NumTailCalls;
1813 isSibCall = true;
1814 }
1815 }
1816
1817 // Analyze operands of the call, assigning locations to each operand.
1818 SmallVector<CCValAssign, 16> ArgLocs;
1819 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1820 *DAG.getContext());
1821 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1822
1823 // Get a count of how many bytes are to be pushed on the stack.
1824 unsigned NumBytes = CCInfo.getNextStackOffset();
1825
1826 // For tail calls, memory operands are available in our caller's stack.
1827 if (isSibCall)
1828 NumBytes = 0;
1829
1830 // Adjust the stack pointer for the new arguments...
1831 // These operations are automatically eliminated by the prolog/epilog pass
1832 if (!isSibCall)
1833 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1834
1835 SDValue StackPtr =
1836 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1837
1838 RegsToPassVector RegsToPass;
1839 SmallVector<SDValue, 8> MemOpChains;
1840
1841 // Walk the register/memloc assignments, inserting copies/loads. In the case
1842 // of tail call optimization, arguments are handled later.
1843 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1844 i != e;
1845 ++i, ++realArgIdx) {
1846 CCValAssign &VA = ArgLocs[i];
1847 SDValue Arg = OutVals[realArgIdx];
1848 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1849 bool isByVal = Flags.isByVal();
1850
1851 // Promote the value if needed.
1852 switch (VA.getLocInfo()) {
1853 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1853)
;
1854 case CCValAssign::Full: break;
1855 case CCValAssign::SExt:
1856 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1857 break;
1858 case CCValAssign::ZExt:
1859 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1860 break;
1861 case CCValAssign::AExt:
1862 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1863 break;
1864 case CCValAssign::BCvt:
1865 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1866 break;
1867 }
1868
1869 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1870 if (VA.needsCustom()) {
1871 if (VA.getLocVT() == MVT::v2f64) {
1872 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1873 DAG.getConstant(0, dl, MVT::i32));
1874 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1875 DAG.getConstant(1, dl, MVT::i32));
1876
1877 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1878 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1879
1880 VA = ArgLocs[++i]; // skip ahead to next loc
1881 if (VA.isRegLoc()) {
1882 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1883 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1884 } else {
1885 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1885, __extension__ __PRETTY_FUNCTION__))
;
1886
1887 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1888 dl, DAG, VA, Flags));
1889 }
1890 } else {
1891 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1892 StackPtr, MemOpChains, Flags);
1893 }
1894 } else if (VA.isRegLoc()) {
1895 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1896 Outs[0].VT == MVT::i32) {
1897 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1898, __extension__ __PRETTY_FUNCTION__))
1898 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1898, __extension__ __PRETTY_FUNCTION__))
;
1899 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1900, __extension__ __PRETTY_FUNCTION__))
1900 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1900, __extension__ __PRETTY_FUNCTION__))
;
1901 isThisReturn = true;
1902 }
1903 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1904 } else if (isByVal) {
1905 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1905, __extension__ __PRETTY_FUNCTION__))
;
1906 unsigned offset = 0;
1907
1908 // True if this byval aggregate will be split between registers
1909 // and memory.
1910 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1911 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1912
1913 if (CurByValIdx < ByValArgsCount) {
1914
1915 unsigned RegBegin, RegEnd;
1916 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1917
1918 EVT PtrVT =
1919 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1920 unsigned int i, j;
1921 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1922 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1923 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1924 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1925 MachinePointerInfo(),
1926 DAG.InferPtrAlignment(AddArg));
1927 MemOpChains.push_back(Load.getValue(1));
1928 RegsToPass.push_back(std::make_pair(j, Load));
1929 }
1930
1931 // If parameter size outsides register area, "offset" value
1932 // helps us to calculate stack slot for remained part properly.
1933 offset = RegEnd - RegBegin;
1934
1935 CCInfo.nextInRegsParam();
1936 }
1937
1938 if (Flags.getByValSize() > 4*offset) {
1939 auto PtrVT = getPointerTy(DAG.getDataLayout());
1940 unsigned LocMemOffset = VA.getLocMemOffset();
1941 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1942 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1943 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1944 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1945 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1946 MVT::i32);
1947 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1948 MVT::i32);
1949
1950 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1951 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1952 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1953 Ops));
1954 }
1955 } else if (!isSibCall) {
1956 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 1956, __extension__ __PRETTY_FUNCTION__))
;
1957
1958 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1959 dl, DAG, VA, Flags));
1960 }
1961 }
1962
1963 if (!MemOpChains.empty())
1964 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1965
1966 // Build a sequence of copy-to-reg nodes chained together with token chain
1967 // and flag operands which copy the outgoing args into the appropriate regs.
1968 SDValue InFlag;
1969 // Tail call byval lowering might overwrite argument registers so in case of
1970 // tail call optimization the copies to registers are lowered later.
1971 if (!isTailCall)
1972 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1973 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1974 RegsToPass[i].second, InFlag);
1975 InFlag = Chain.getValue(1);
1976 }
1977
1978 // For tail calls lower the arguments to the 'real' stack slot.
1979 if (isTailCall) {
1980 // Force all the incoming stack arguments to be loaded from the stack
1981 // before any new outgoing arguments are stored to the stack, because the
1982 // outgoing stack slots may alias the incoming argument stack slots, and
1983 // the alias isn't otherwise explicit. This is slightly more conservative
1984 // than necessary, because it means that each store effectively depends
1985 // on every argument instead of just those arguments it would clobber.
1986
1987 // Do not flag preceding copytoreg stuff together with the following stuff.
1988 InFlag = SDValue();
1989 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1990 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1991 RegsToPass[i].second, InFlag);
1992 InFlag = Chain.getValue(1);
1993 }
1994 InFlag = SDValue();
1995 }
1996
1997 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1998 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1999 // node so that legalize doesn't hack it.
2000 bool isDirect = false;
2001
2002 const TargetMachine &TM = getTargetMachine();
2003 const Module *Mod = MF.getFunction().getParent();
2004 const GlobalValue *GV = nullptr;
2005 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2006 GV = G->getGlobal();
2007 bool isStub =
2008 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2009
2010 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2011 bool isLocalARMFunc = false;
2012 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2013 auto PtrVt = getPointerTy(DAG.getDataLayout());
2014
2015 if (Subtarget->genLongCalls()) {
2016 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2017, __extension__ __PRETTY_FUNCTION__))
2017 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2017, __extension__ __PRETTY_FUNCTION__))
;
2018 // Handle a global address or an external symbol. If it's not one of
2019 // those, the target's already in a register, so we don't need to do
2020 // anything extra.
2021 if (isa<GlobalAddressSDNode>(Callee)) {
2022 // Create a constant pool entry for the callee address
2023 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2024 ARMConstantPoolValue *CPV =
2025 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2026
2027 // Get the address of the callee into a register
2028 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2029 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2030 Callee = DAG.getLoad(
2031 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2032 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2033 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2034 const char *Sym = S->getSymbol();
2035
2036 // Create a constant pool entry for the callee address
2037 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2038 ARMConstantPoolValue *CPV =
2039 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2040 ARMPCLabelIndex, 0);
2041 // Get the address of the callee into a register
2042 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2043 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2044 Callee = DAG.getLoad(
2045 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2046 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2047 }
2048 } else if (isa<GlobalAddressSDNode>(Callee)) {
2049 // If we're optimizing for minimum size and the function is called three or
2050 // more times in this block, we can improve codesize by calling indirectly
2051 // as BLXr has a 16-bit encoding.
2052 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2053 auto *BB = CLI.CS.getParent();
2054 bool PreferIndirect =
2055 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2056 count_if(GV->users(), [&BB](const User *U) {
2057 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2058 }) > 2;
2059
2060 if (!PreferIndirect) {
2061 isDirect = true;
2062 bool isDef = GV->isStrongDefinitionForLinker();
2063
2064 // ARM call to a local ARM function is predicable.
2065 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2066 // tBX takes a register source operand.
2067 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2068 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2068, __extension__ __PRETTY_FUNCTION__))
;
2069 Callee = DAG.getNode(
2070 ARMISD::WrapperPIC, dl, PtrVt,
2071 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2072 Callee = DAG.getLoad(
2073 PtrVt, dl, DAG.getEntryNode(), Callee,
2074 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2075 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2076 MachineMemOperand::MOInvariant);
2077 } else if (Subtarget->isTargetCOFF()) {
2078 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2079, __extension__ __PRETTY_FUNCTION__))
2079 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2079, __extension__ __PRETTY_FUNCTION__))
;
2080 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2081 ? ARMII::MO_DLLIMPORT
2082 : ARMII::MO_NO_FLAG;
2083 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2084 TargetFlags);
2085 if (GV->hasDLLImportStorageClass())
2086 Callee =
2087 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2088 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2089 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2090 } else {
2091 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2092 }
2093 }
2094 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2095 isDirect = true;
2096 // tBX takes a register source operand.
2097 const char *Sym = S->getSymbol();
2098 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2099 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2100 ARMConstantPoolValue *CPV =
2101 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2102 ARMPCLabelIndex, 4);
2103 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2104 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2105 Callee = DAG.getLoad(
2106 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2107 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2108 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2109 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2110 } else {
2111 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2112 }
2113 }
2114
2115 // FIXME: handle tail calls differently.
2116 unsigned CallOpc;
2117 if (Subtarget->isThumb()) {
2118 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2119 CallOpc = ARMISD::CALL_NOLINK;
2120 else
2121 CallOpc = ARMISD::CALL;
2122 } else {
2123 if (!isDirect && !Subtarget->hasV5TOps())
2124 CallOpc = ARMISD::CALL_NOLINK;
2125 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2126 // Emit regular call when code size is the priority
2127 !MF.getFunction().optForMinSize())
2128 // "mov lr, pc; b _foo" to avoid confusing the RSP
2129 CallOpc = ARMISD::CALL_NOLINK;
2130 else
2131 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2132 }
2133
2134 std::vector<SDValue> Ops;
2135 Ops.push_back(Chain);
2136 Ops.push_back(Callee);
2137
2138 // Add argument registers to the end of the list so that they are known live
2139 // into the call.
2140 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2141 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2142 RegsToPass[i].second.getValueType()));
2143
2144 // Add a register mask operand representing the call-preserved registers.
2145 if (!isTailCall) {
2146 const uint32_t *Mask;
2147 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2148 if (isThisReturn) {
2149 // For 'this' returns, use the R0-preserving mask if applicable
2150 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2151 if (!Mask) {
2152 // Set isThisReturn to false if the calling convention is not one that
2153 // allows 'returned' to be modeled in this way, so LowerCallResult does
2154 // not try to pass 'this' straight through
2155 isThisReturn = false;
2156 Mask = ARI->getCallPreservedMask(MF, CallConv);
2157 }
2158 } else
2159 Mask = ARI->getCallPreservedMask(MF, CallConv);
2160
2161 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2161, __extension__ __PRETTY_FUNCTION__))
;
2162 Ops.push_back(DAG.getRegisterMask(Mask));
2163 }
2164
2165 if (InFlag.getNode())
2166 Ops.push_back(InFlag);
2167
2168 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2169 if (isTailCall) {
2170 MF.getFrameInfo().setHasTailCall();
2171 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2172 }
2173
2174 // Returns a chain and a flag for retval copy to use.
2175 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2176 InFlag = Chain.getValue(1);
2177
2178 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2179 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2180 if (!Ins.empty())
2181 InFlag = Chain.getValue(1);
2182
2183 // Handle result values, copying them out of physregs into vregs that we
2184 // return.
2185 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2186 InVals, isThisReturn,
2187 isThisReturn ? OutVals[0] : SDValue());
2188}
2189
2190/// HandleByVal - Every parameter *after* a byval parameter is passed
2191/// on the stack. Remember the next parameter register to allocate,
2192/// and then confiscate the rest of the parameter registers to insure
2193/// this.
2194void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2195 unsigned Align) const {
2196 // Byval (as with any stack) slots are always at least 4 byte aligned.
2197 Align = std::max(Align, 4U);
2198
2199 unsigned Reg = State->AllocateReg(GPRArgRegs);
2200 if (!Reg)
2201 return;
2202
2203 unsigned AlignInRegs = Align / 4;
2204 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2205 for (unsigned i = 0; i < Waste; ++i)
2206 Reg = State->AllocateReg(GPRArgRegs);
2207
2208 if (!Reg)
2209 return;
2210
2211 unsigned Excess = 4 * (ARM::R4 - Reg);
2212
2213 // Special case when NSAA != SP and parameter size greater than size of
2214 // all remained GPR regs. In that case we can't split parameter, we must
2215 // send it to stack. We also must set NCRN to R4, so waste all
2216 // remained registers.
2217 const unsigned NSAAOffset = State->getNextStackOffset();
2218 if (NSAAOffset != 0 && Size > Excess) {
2219 while (State->AllocateReg(GPRArgRegs))
2220 ;
2221 return;
2222 }
2223
2224 // First register for byval parameter is the first register that wasn't
2225 // allocated before this method call, so it would be "reg".
2226 // If parameter is small enough to be saved in range [reg, r4), then
2227 // the end (first after last) register would be reg + param-size-in-regs,
2228 // else parameter would be splitted between registers and stack,
2229 // end register would be r4 in this case.
2230 unsigned ByValRegBegin = Reg;
2231 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2232 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2233 // Note, first register is allocated in the beginning of function already,
2234 // allocate remained amount of registers we need.
2235 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2236 State->AllocateReg(GPRArgRegs);
2237 // A byval parameter that is split between registers and memory needs its
2238 // size truncated here.
2239 // In the case where the entire structure fits in registers, we set the
2240 // size in memory to zero.
2241 Size = std::max<int>(Size - Excess, 0);
2242}
2243
2244/// MatchingStackOffset - Return true if the given stack call argument is
2245/// already available in the same position (relatively) of the caller's
2246/// incoming argument stack.
2247static
2248bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2249 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2250 const TargetInstrInfo *TII) {
2251 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2252 int FI = std::numeric_limits<int>::max();
2253 if (Arg.getOpcode() == ISD::CopyFromReg) {
2254 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2255 if (!TargetRegisterInfo::isVirtualRegister(VR))
2256 return false;
2257 MachineInstr *Def = MRI->getVRegDef(VR);
2258 if (!Def)
2259 return false;
2260 if (!Flags.isByVal()) {
2261 if (!TII->isLoadFromStackSlot(*Def, FI))
2262 return false;
2263 } else {
2264 return false;
2265 }
2266 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2267 if (Flags.isByVal())
2268 // ByVal argument is passed in as a pointer but it's now being
2269 // dereferenced. e.g.
2270 // define @foo(%struct.X* %A) {
2271 // tail call @bar(%struct.X* byval %A)
2272 // }
2273 return false;
2274 SDValue Ptr = Ld->getBasePtr();
2275 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2276 if (!FINode)
2277 return false;
2278 FI = FINode->getIndex();
2279 } else
2280 return false;
2281
2282 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2282, __extension__ __PRETTY_FUNCTION__))
;
2283 if (!MFI.isFixedObjectIndex(FI))
2284 return false;
2285 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2286}
2287
2288/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2289/// for tail call optimization. Targets which want to do tail call
2290/// optimization should implement this function.
2291bool
2292ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2293 CallingConv::ID CalleeCC,
2294 bool isVarArg,
2295 bool isCalleeStructRet,
2296 bool isCallerStructRet,
2297 const SmallVectorImpl<ISD::OutputArg> &Outs,
2298 const SmallVectorImpl<SDValue> &OutVals,
2299 const SmallVectorImpl<ISD::InputArg> &Ins,
2300 SelectionDAG& DAG) const {
2301 MachineFunction &MF = DAG.getMachineFunction();
2302 const Function &CallerF = MF.getFunction();
2303 CallingConv::ID CallerCC = CallerF.getCallingConv();
2304
2305 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2305, __extension__ __PRETTY_FUNCTION__))
;
2306
2307 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2308 // to the call take up r0-r3. The reason is that there are no legal registers
2309 // left to hold the pointer to the function to be called.
2310 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2311 !isa<GlobalAddressSDNode>(Callee.getNode()))
2312 return false;
2313
2314 // Look for obvious safe cases to perform tail call optimization that do not
2315 // require ABI changes. This is what gcc calls sibcall.
2316
2317 // Exception-handling functions need a special set of instructions to indicate
2318 // a return to the hardware. Tail-calling another function would probably
2319 // break this.
2320 if (CallerF.hasFnAttribute("interrupt"))
2321 return false;
2322
2323 // Also avoid sibcall optimization if either caller or callee uses struct
2324 // return semantics.
2325 if (isCalleeStructRet || isCallerStructRet)
2326 return false;
2327
2328 // Externally-defined functions with weak linkage should not be
2329 // tail-called on ARM when the OS does not support dynamic
2330 // pre-emption of symbols, as the AAELF spec requires normal calls
2331 // to undefined weak functions to be replaced with a NOP or jump to the
2332 // next instruction. The behaviour of branch instructions in this
2333 // situation (as used for tail calls) is implementation-defined, so we
2334 // cannot rely on the linker replacing the tail call with a return.
2335 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2336 const GlobalValue *GV = G->getGlobal();
2337 const Triple &TT = getTargetMachine().getTargetTriple();
2338 if (GV->hasExternalWeakLinkage() &&
2339 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2340 return false;
2341 }
2342
2343 // Check that the call results are passed in the same way.
2344 LLVMContext &C = *DAG.getContext();
2345 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2346 CCAssignFnForReturn(CalleeCC, isVarArg),
2347 CCAssignFnForReturn(CallerCC, isVarArg)))
2348 return false;
2349 // The callee has to preserve all registers the caller needs to preserve.
2350 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2351 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2352 if (CalleeCC != CallerCC) {
2353 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2354 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2355 return false;
2356 }
2357
2358 // If Caller's vararg or byval argument has been split between registers and
2359 // stack, do not perform tail call, since part of the argument is in caller's
2360 // local frame.
2361 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2362 if (AFI_Caller->getArgRegsSaveSize())
2363 return false;
2364
2365 // If the callee takes no arguments then go on to check the results of the
2366 // call.
2367 if (!Outs.empty()) {
2368 // Check if stack adjustment is needed. For now, do not do this if any
2369 // argument is passed on the stack.
2370 SmallVector<CCValAssign, 16> ArgLocs;
2371 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2372 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2373 if (CCInfo.getNextStackOffset()) {
2374 // Check if the arguments are already laid out in the right way as
2375 // the caller's fixed stack objects.
2376 MachineFrameInfo &MFI = MF.getFrameInfo();
2377 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2378 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2379 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2380 i != e;
2381 ++i, ++realArgIdx) {
2382 CCValAssign &VA = ArgLocs[i];
2383 EVT RegVT = VA.getLocVT();
2384 SDValue Arg = OutVals[realArgIdx];
2385 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2386 if (VA.getLocInfo() == CCValAssign::Indirect)
2387 return false;
2388 if (VA.needsCustom()) {
2389 // f64 and vector types are split into multiple registers or
2390 // register/stack-slot combinations. The types will not match
2391 // the registers; give up on memory f64 refs until we figure
2392 // out what to do about this.
2393 if (!VA.isRegLoc())
2394 return false;
2395 if (!ArgLocs[++i].isRegLoc())
2396 return false;
2397 if (RegVT == MVT::v2f64) {
2398 if (!ArgLocs[++i].isRegLoc())
2399 return false;
2400 if (!ArgLocs[++i].isRegLoc())
2401 return false;
2402 }
2403 } else if (!VA.isRegLoc()) {
2404 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2405 MFI, MRI, TII))
2406 return false;
2407 }
2408 }
2409 }
2410
2411 const MachineRegisterInfo &MRI = MF.getRegInfo();
2412 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2413 return false;
2414 }
2415
2416 return true;
2417}
2418
2419bool
2420ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2421 MachineFunction &MF, bool isVarArg,
2422 const SmallVectorImpl<ISD::OutputArg> &Outs,
2423 LLVMContext &Context) const {
2424 SmallVector<CCValAssign, 16> RVLocs;
2425 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2426 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2427}
2428
2429static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2430 const SDLoc &DL, SelectionDAG &DAG) {
2431 const MachineFunction &MF = DAG.getMachineFunction();
2432 const Function &F = MF.getFunction();
2433
2434 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2435
2436 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2437 // version of the "preferred return address". These offsets affect the return
2438 // instruction if this is a return from PL1 without hypervisor extensions.
2439 // IRQ/FIQ: +4 "subs pc, lr, #4"
2440 // SWI: 0 "subs pc, lr, #0"
2441 // ABORT: +4 "subs pc, lr, #4"
2442 // UNDEF: +4/+2 "subs pc, lr, #0"
2443 // UNDEF varies depending on where the exception came from ARM or Thumb
2444 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2445
2446 int64_t LROffset;
2447 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2448 IntKind == "ABORT")
2449 LROffset = 4;
2450 else if (IntKind == "SWI" || IntKind == "UNDEF")
2451 LROffset = 0;
2452 else
2453 report_fatal_error("Unsupported interrupt attribute. If present, value "
2454 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2455
2456 RetOps.insert(RetOps.begin() + 1,
2457 DAG.getConstant(LROffset, DL, MVT::i32, false));
2458
2459 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2460}
2461
2462SDValue
2463ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2464 bool isVarArg,
2465 const SmallVectorImpl<ISD::OutputArg> &Outs,
2466 const SmallVectorImpl<SDValue> &OutVals,
2467 const SDLoc &dl, SelectionDAG &DAG) const {
2468 // CCValAssign - represent the assignment of the return value to a location.
2469 SmallVector<CCValAssign, 16> RVLocs;
2470
2471 // CCState - Info about the registers and stack slots.
2472 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2473 *DAG.getContext());
2474
2475 // Analyze outgoing return values.
2476 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2477
2478 SDValue Flag;
2479 SmallVector<SDValue, 4> RetOps;
2480 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2481 bool isLittleEndian = Subtarget->isLittle();
2482
2483 MachineFunction &MF = DAG.getMachineFunction();
2484 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2485 AFI->setReturnRegsCount(RVLocs.size());
2486
2487 // Copy the result values into the output registers.
2488 for (unsigned i = 0, realRVLocIdx = 0;
2489 i != RVLocs.size();
2490 ++i, ++realRVLocIdx) {
2491 CCValAssign &VA = RVLocs[i];
2492 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2492, __extension__ __PRETTY_FUNCTION__))
;
2493
2494 SDValue Arg = OutVals[realRVLocIdx];
2495 bool ReturnF16 = false;
2496
2497 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2498 // Half-precision return values can be returned like this:
2499 //
2500 // t11 f16 = fadd ...
2501 // t12: i16 = bitcast t11
2502 // t13: i32 = zero_extend t12
2503 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2504 //
2505 // to avoid code generation for bitcasts, we simply set Arg to the node
2506 // that produces the f16 value, t11 in this case.
2507 //
2508 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2509 SDValue ZE = Arg.getOperand(0);
2510 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2511 SDValue BC = ZE.getOperand(0);
2512 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2513 Arg = BC.getOperand(0);
2514 ReturnF16 = true;
2515 }
2516 }
2517 }
2518 }
2519
2520 switch (VA.getLocInfo()) {
2521 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2521)
;
2522 case CCValAssign::Full: break;
2523 case CCValAssign::BCvt:
2524 if (!ReturnF16)
2525 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2526 break;
2527 }
2528
2529 if (VA.needsCustom()) {
2530 if (VA.getLocVT() == MVT::v2f64) {
2531 // Extract the first half and return it in two registers.
2532 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2533 DAG.getConstant(0, dl, MVT::i32));
2534 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2535 DAG.getVTList(MVT::i32, MVT::i32), Half);
2536
2537 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2538 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2539 Flag);
2540 Flag = Chain.getValue(1);
2541 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2542 VA = RVLocs[++i]; // skip ahead to next loc
2543 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2544 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2545 Flag);
2546 Flag = Chain.getValue(1);
2547 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2548 VA = RVLocs[++i]; // skip ahead to next loc
2549
2550 // Extract the 2nd half and fall through to handle it as an f64 value.
2551 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2552 DAG.getConstant(1, dl, MVT::i32));
2553 }
2554 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2555 // available.
2556 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2557 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2558 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2559 fmrrd.getValue(isLittleEndian ? 0 : 1),
2560 Flag);
2561 Flag = Chain.getValue(1);
2562 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2563 VA = RVLocs[++i]; // skip ahead to next loc
2564 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2565 fmrrd.getValue(isLittleEndian ? 1 : 0),
2566 Flag);
2567 } else
2568 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2569
2570 // Guarantee that all emitted copies are
2571 // stuck together, avoiding something bad.
2572 Flag = Chain.getValue(1);
2573 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2574 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2575 }
2576 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2577 const MCPhysReg *I =
2578 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2579 if (I) {
2580 for (; *I; ++I) {
2581 if (ARM::GPRRegClass.contains(*I))
2582 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2583 else if (ARM::DPRRegClass.contains(*I))
2584 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2585 else
2586 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2586)
;
2587 }
2588 }
2589
2590 // Update chain and glue.
2591 RetOps[0] = Chain;
2592 if (Flag.getNode())
2593 RetOps.push_back(Flag);
2594
2595 // CPUs which aren't M-class use a special sequence to return from
2596 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2597 // though we use "subs pc, lr, #N").
2598 //
2599 // M-class CPUs actually use a normal return sequence with a special
2600 // (hardware-provided) value in LR, so the normal code path works.
2601 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2602 !Subtarget->isMClass()) {
2603 if (Subtarget->isThumb1Only())
2604 report_fatal_error("interrupt attribute is not supported in Thumb1");
2605 return LowerInterruptReturn(RetOps, dl, DAG);
2606 }
2607
2608 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2609}
2610
2611bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2612 if (N->getNumValues() != 1)
2613 return false;
2614 if (!N->hasNUsesOfValue(1, 0))
2615 return false;
2616
2617 SDValue TCChain = Chain;
2618 SDNode *Copy = *N->use_begin();
2619 if (Copy->getOpcode() == ISD::CopyToReg) {
2620 // If the copy has a glue operand, we conservatively assume it isn't safe to
2621 // perform a tail call.
2622 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2623 return false;
2624 TCChain = Copy->getOperand(0);
2625 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2626 SDNode *VMov = Copy;
2627 // f64 returned in a pair of GPRs.
2628 SmallPtrSet<SDNode*, 2> Copies;
2629 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2630 UI != UE; ++UI) {
2631 if (UI->getOpcode() != ISD::CopyToReg)
2632 return false;
2633 Copies.insert(*UI);
2634 }
2635 if (Copies.size() > 2)
2636 return false;
2637
2638 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2639 UI != UE; ++UI) {
2640 SDValue UseChain = UI->getOperand(0);
2641 if (Copies.count(UseChain.getNode()))
2642 // Second CopyToReg
2643 Copy = *UI;
2644 else {
2645 // We are at the top of this chain.
2646 // If the copy has a glue operand, we conservatively assume it
2647 // isn't safe to perform a tail call.
2648 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2649 return false;
2650 // First CopyToReg
2651 TCChain = UseChain;
2652 }
2653 }
2654 } else if (Copy->getOpcode() == ISD::BITCAST) {
2655 // f32 returned in a single GPR.
2656 if (!Copy->hasOneUse())
2657 return false;
2658 Copy = *Copy->use_begin();
2659 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2660 return false;
2661 // If the copy has a glue operand, we conservatively assume it isn't safe to
2662 // perform a tail call.
2663 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2664 return false;
2665 TCChain = Copy->getOperand(0);
2666 } else {
2667 return false;
2668 }
2669
2670 bool HasRet = false;
2671 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2672 UI != UE; ++UI) {
2673 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2674 UI->getOpcode() != ARMISD::INTRET_FLAG)
2675 return false;
2676 HasRet = true;
2677 }
2678
2679 if (!HasRet)
2680 return false;
2681
2682 Chain = TCChain;
2683 return true;
2684}
2685
2686bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2687 if (!Subtarget->supportsTailCall())
2688 return false;
2689
2690 auto Attr =
2691 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2692 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2693 return false;
2694
2695 return true;
2696}
2697
2698// Trying to write a 64 bit value so need to split into two 32 bit values first,
2699// and pass the lower and high parts through.
2700static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2701 SDLoc DL(Op);
2702 SDValue WriteValue = Op->getOperand(2);
2703
2704 // This function is only supposed to be called for i64 type argument.
2705 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2706, __extension__ __PRETTY_FUNCTION__))
2706 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2706, __extension__ __PRETTY_FUNCTION__))
;
2707
2708 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2709 DAG.getConstant(0, DL, MVT::i32));
2710 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2711 DAG.getConstant(1, DL, MVT::i32));
2712 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2713 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2714}
2715
2716// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2717// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2718// one of the above mentioned nodes. It has to be wrapped because otherwise
2719// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2720// be used to form addressing mode. These wrapped nodes will be selected
2721// into MOVi.
2722SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2723 SelectionDAG &DAG) const {
2724 EVT PtrVT = Op.getValueType();
2725 // FIXME there is no actual debug info here
2726 SDLoc dl(Op);
2727 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2728 SDValue Res;
2729
2730 // When generating execute-only code Constant Pools must be promoted to the
2731 // global data section. It's a bit ugly that we can't share them across basic
2732 // blocks, but this way we guarantee that execute-only behaves correct with
2733 // position-independent addressing modes.
2734 if (Subtarget->genExecuteOnly()) {
2735 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2736 auto T = const_cast<Type*>(CP->getType());
2737 auto C = const_cast<Constant*>(CP->getConstVal());
2738 auto M = const_cast<Module*>(DAG.getMachineFunction().
2739 getFunction().getParent());
2740 auto GV = new GlobalVariable(
2741 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2742 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2743 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2744 Twine(AFI->createPICLabelUId())
2745 );
2746 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2747 dl, PtrVT);
2748 return LowerGlobalAddress(GA, DAG);
2749 }
2750
2751 if (CP->isMachineConstantPoolEntry())
2752 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2753 CP->getAlignment());
2754 else
2755 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2756 CP->getAlignment());
2757 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2758}
2759
2760unsigned ARMTargetLowering::getJumpTableEncoding() const {
2761 return MachineJumpTableInfo::EK_Inline;
2762}
2763
2764SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2765 SelectionDAG &DAG) const {
2766 MachineFunction &MF = DAG.getMachineFunction();
2767 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2768 unsigned ARMPCLabelIndex = 0;
2769 SDLoc DL(Op);
2770 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2771 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2772 SDValue CPAddr;
2773 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2774 if (!IsPositionIndependent) {
2775 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2776 } else {
2777 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2778 ARMPCLabelIndex = AFI->createPICLabelUId();
2779 ARMConstantPoolValue *CPV =
2780 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2781 ARMCP::CPBlockAddress, PCAdj);
2782 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2783 }
2784 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2785 SDValue Result = DAG.getLoad(
2786 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2787 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2788 if (!IsPositionIndependent)
2789 return Result;
2790 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2791 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2792}
2793
2794/// \brief Convert a TLS address reference into the correct sequence of loads
2795/// and calls to compute the variable's address for Darwin, and return an
2796/// SDValue containing the final node.
2797
2798/// Darwin only has one TLS scheme which must be capable of dealing with the
2799/// fully general situation, in the worst case. This means:
2800/// + "extern __thread" declaration.
2801/// + Defined in a possibly unknown dynamic library.
2802///
2803/// The general system is that each __thread variable has a [3 x i32] descriptor
2804/// which contains information used by the runtime to calculate the address. The
2805/// only part of this the compiler needs to know about is the first word, which
2806/// contains a function pointer that must be called with the address of the
2807/// entire descriptor in "r0".
2808///
2809/// Since this descriptor may be in a different unit, in general access must
2810/// proceed along the usual ARM rules. A common sequence to produce is:
2811///
2812/// movw rT1, :lower16:_var$non_lazy_ptr
2813/// movt rT1, :upper16:_var$non_lazy_ptr
2814/// ldr r0, [rT1]
2815/// ldr rT2, [r0]
2816/// blx rT2
2817/// [...address now in r0...]
2818SDValue
2819ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2820 SelectionDAG &DAG) const {
2821 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2822, __extension__ __PRETTY_FUNCTION__))
2822 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2822, __extension__ __PRETTY_FUNCTION__))
;
2823 SDLoc DL(Op);
2824
2825 // First step is to get the address of the actua global symbol. This is where
2826 // the TLS descriptor lives.
2827 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2828
2829 // The first entry in the descriptor is a function pointer that we must call
2830 // to obtain the address of the variable.
2831 SDValue Chain = DAG.getEntryNode();
2832 SDValue FuncTLVGet = DAG.getLoad(
2833 MVT::i32, DL, Chain, DescAddr,
2834 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2835 /* Alignment = */ 4,
2836 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2837 MachineMemOperand::MOInvariant);
2838 Chain = FuncTLVGet.getValue(1);
2839
2840 MachineFunction &F = DAG.getMachineFunction();
2841 MachineFrameInfo &MFI = F.getFrameInfo();
2842 MFI.setAdjustsStack(true);
2843
2844 // TLS calls preserve all registers except those that absolutely must be
2845 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2846 // silly).
2847 auto TRI =
2848 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2849 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2850 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2851
2852 // Finally, we can make the call. This is just a degenerate version of a
2853 // normal AArch64 call node: r0 takes the address of the descriptor, and
2854 // returns the address of the variable in this thread.
2855 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2856 Chain =
2857 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2858 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2859 DAG.getRegisterMask(Mask), Chain.getValue(1));
2860 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2861}
2862
2863SDValue
2864ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2865 SelectionDAG &DAG) const {
2866 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2866, __extension__ __PRETTY_FUNCTION__))
;
2867
2868 SDValue Chain = DAG.getEntryNode();
2869 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2870 SDLoc DL(Op);
2871
2872 // Load the current TEB (thread environment block)
2873 SDValue Ops[] = {Chain,
2874 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2875 DAG.getConstant(15, DL, MVT::i32),
2876 DAG.getConstant(0, DL, MVT::i32),
2877 DAG.getConstant(13, DL, MVT::i32),
2878 DAG.getConstant(0, DL, MVT::i32),
2879 DAG.getConstant(2, DL, MVT::i32)};
2880 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2881 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2882
2883 SDValue TEB = CurrentTEB.getValue(0);
2884 Chain = CurrentTEB.getValue(1);
2885
2886 // Load the ThreadLocalStoragePointer from the TEB
2887 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2888 SDValue TLSArray =
2889 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2890 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2891
2892 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2893 // offset into the TLSArray.
2894
2895 // Load the TLS index from the C runtime
2896 SDValue TLSIndex =
2897 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2898 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2899 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2900
2901 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2902 DAG.getConstant(2, DL, MVT::i32));
2903 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2904 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2905 MachinePointerInfo());
2906
2907 // Get the offset of the start of the .tls section (section base)
2908 const auto *GA = cast<GlobalAddressSDNode>(Op);
2909 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2910 SDValue Offset = DAG.getLoad(
2911 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2912 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2913 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2914
2915 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2916}
2917
2918// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2919SDValue
2920ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2921 SelectionDAG &DAG) const {
2922 SDLoc dl(GA);
2923 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2924 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2925 MachineFunction &MF = DAG.getMachineFunction();
2926 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2927 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2928 ARMConstantPoolValue *CPV =
2929 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2930 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2931 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2932 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2933 Argument = DAG.getLoad(
2934 PtrVT, dl, DAG.getEntryNode(), Argument,
2935 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2936 SDValue Chain = Argument.getValue(1);
2937
2938 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2939 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2940
2941 // call __tls_get_addr.
2942 ArgListTy Args;
2943 ArgListEntry Entry;
2944 Entry.Node = Argument;
2945 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2946 Args.push_back(Entry);
2947
2948 // FIXME: is there useful debug info available here?
2949 TargetLowering::CallLoweringInfo CLI(DAG);
2950 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2951 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2952 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2953
2954 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2955 return CallResult.first;
2956}
2957
2958// Lower ISD::GlobalTLSAddress using the "initial exec" or
2959// "local exec" model.
2960SDValue
2961ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2962 SelectionDAG &DAG,
2963 TLSModel::Model model) const {
2964 const GlobalValue *GV = GA->getGlobal();
2965 SDLoc dl(GA);
2966 SDValue Offset;
2967 SDValue Chain = DAG.getEntryNode();
2968 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2969 // Get the Thread Pointer
2970 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2971
2972 if (model == TLSModel::InitialExec) {
2973 MachineFunction &MF = DAG.getMachineFunction();
2974 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2975 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2976 // Initial exec model.
2977 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2978 ARMConstantPoolValue *CPV =
2979 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2980 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2981 true);
2982 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2983 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2984 Offset = DAG.getLoad(
2985 PtrVT, dl, Chain, Offset,
2986 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2987 Chain = Offset.getValue(1);
2988
2989 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2990 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2991
2992 Offset = DAG.getLoad(
2993 PtrVT, dl, Chain, Offset,
2994 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2995 } else {
2996 // local exec model
2997 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 2997, __extension__ __PRETTY_FUNCTION__))
;
2998 ARMConstantPoolValue *CPV =
2999 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3000 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3001 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3002 Offset = DAG.getLoad(
3003 PtrVT, dl, Chain, Offset,
3004 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3005 }
3006
3007 // The address of the thread local variable is the add of the thread
3008 // pointer with the offset of the variable.
3009 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3010}
3011
3012SDValue
3013ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3014 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3015 if (DAG.getTarget().useEmulatedTLS())
3016 return LowerToTLSEmulatedModel(GA, DAG);
3017
3018 if (Subtarget->isTargetDarwin())
3019 return LowerGlobalTLSAddressDarwin(Op, DAG);
3020
3021 if (Subtarget->isTargetWindows())
3022 return LowerGlobalTLSAddressWindows(Op, DAG);
3023
3024 // TODO: implement the "local dynamic" model
3025 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3025, __extension__ __PRETTY_FUNCTION__))
;
3026 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3027
3028 switch (model) {
3029 case TLSModel::GeneralDynamic:
3030 case TLSModel::LocalDynamic:
3031 return LowerToTLSGeneralDynamicModel(GA, DAG);
3032 case TLSModel::InitialExec:
3033 case TLSModel::LocalExec:
3034 return LowerToTLSExecModels(GA, DAG, model);
3035 }
3036 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3036)
;
3037}
3038
3039/// Return true if all users of V are within function F, looking through
3040/// ConstantExprs.
3041static bool allUsersAreInFunction(const Value *V, const Function *F) {
3042 SmallVector<const User*,4> Worklist;
3043 for (auto *U : V->users())
3044 Worklist.push_back(U);
3045 while (!Worklist.empty()) {
3046 auto *U = Worklist.pop_back_val();
3047 if (isa<ConstantExpr>(U)) {
3048 for (auto *UU : U->users())
3049 Worklist.push_back(UU);
3050 continue;
3051 }
3052
3053 auto *I = dyn_cast<Instruction>(U);
3054 if (!I || I->getParent()->getParent() != F)
3055 return false;
3056 }
3057 return true;
3058}
3059
3060/// Return true if all users of V are within some (any) function, looking through
3061/// ConstantExprs. In other words, are there any global constant users?
3062static bool allUsersAreInFunctions(const Value *V) {
3063 SmallVector<const User*,4> Worklist;
3064 for (auto *U : V->users())
3065 Worklist.push_back(U);
3066 while (!Worklist.empty()) {
3067 auto *U = Worklist.pop_back_val();
3068 if (isa<ConstantExpr>(U)) {
3069 for (auto *UU : U->users())
3070 Worklist.push_back(UU);
3071 continue;
3072 }
3073
3074 if (!isa<Instruction>(U))
3075 return false;
3076 }
3077 return true;
3078}
3079
3080// Return true if T is an integer, float or an array/vector of either.
3081static bool isSimpleType(Type *T) {
3082 if (T->isIntegerTy() || T->isFloatingPointTy())
3083 return true;
3084 Type *SubT = nullptr;
3085 if (T->isArrayTy())
3086 SubT = T->getArrayElementType();
3087 else if (T->isVectorTy())
3088 SubT = T->getVectorElementType();
3089 else
3090 return false;
3091 return SubT->isIntegerTy() || SubT->isFloatingPointTy();
3092}
3093
3094static SDValue promoteToConstantPool(const GlobalValue *GV, SelectionDAG &DAG,
3095 EVT PtrVT, const SDLoc &dl) {
3096 // If we're creating a pool entry for a constant global with unnamed address,
3097 // and the global is small enough, we can emit it inline into the constant pool
3098 // to save ourselves an indirection.
3099 //
3100 // This is a win if the constant is only used in one function (so it doesn't
3101 // need to be duplicated) or duplicating the constant wouldn't increase code
3102 // size (implying the constant is no larger than 4 bytes).
3103 const Function &F = DAG.getMachineFunction().getFunction();
3104
3105 // We rely on this decision to inline being idemopotent and unrelated to the
3106 // use-site. We know that if we inline a variable at one use site, we'll
3107 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3108 // doesn't know about this optimization, so bail out if it's enabled else
3109 // we could decide to inline here (and thus never emit the GV) but require
3110 // the GV from fast-isel generated code.
3111 if (!EnableConstpoolPromotion ||
3112 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3113 return SDValue();
3114
3115 auto *GVar = dyn_cast<GlobalVariable>(GV);
3116 if (!GVar || !GVar->hasInitializer() ||
3117 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3118 !GVar->hasLocalLinkage())
3119 return SDValue();
3120
3121 // Ensure that we don't try and inline any type that contains pointers. If
3122 // we inline a value that contains relocations, we move the relocations from
3123 // .data to .text which is not ideal.
3124 auto *Init = GVar->getInitializer();
3125 if (!isSimpleType(Init->getType()))
3126 return SDValue();
3127
3128 // The constant islands pass can only really deal with alignment requests
3129 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3130 // any type wanting greater alignment requirements than 4 bytes. We also
3131 // can only promote constants that are multiples of 4 bytes in size or
3132 // are paddable to a multiple of 4. Currently we only try and pad constants
3133 // that are strings for simplicity.
3134 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3135 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3136 unsigned Align = GVar->getAlignment();
3137 unsigned RequiredPadding = 4 - (Size % 4);
3138 bool PaddingPossible =
3139 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3140 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3141 Size == 0)
3142 return SDValue();
3143
3144 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3145 MachineFunction &MF = DAG.getMachineFunction();
3146 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3147
3148 // We can't bloat the constant pool too much, else the ConstantIslands pass
3149 // may fail to converge. If we haven't promoted this global yet (it may have
3150 // multiple uses), and promoting it would increase the constant pool size (Sz
3151 // > 4), ensure we have space to do so up to MaxTotal.
3152 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3153 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3154 ConstpoolPromotionMaxTotal)
3155 return SDValue();
3156
3157 // This is only valid if all users are in a single function OR it has users
3158 // in multiple functions but it no larger than a pointer. We also check if
3159 // GVar has constant (non-ConstantExpr) users. If so, it essentially has its
3160 // address taken.
3161 if (!allUsersAreInFunction(GVar, &F) &&
3162 !(Size <= 4 && allUsersAreInFunctions(GVar)))
3163 return SDValue();
3164
3165 // We're going to inline this global. Pad it out if needed.
3166 if (RequiredPadding != 4) {
3167 StringRef S = CDAInit->getAsString();
3168
3169 SmallVector<uint8_t,16> V(S.size());
3170 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3171 while (RequiredPadding--)
3172 V.push_back(0);
3173 Init = ConstantDataArray::get(*DAG.getContext(), V);
3174 }
3175
3176 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3177 SDValue CPAddr =
3178 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3179 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3180 AFI->markGlobalAsPromotedToConstantPool(GVar);
3181 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3182 PaddedSize - 4);
3183 }
3184 ++NumConstpoolPromoted;
3185 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3186}
3187
3188bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3189 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3190 GV = GA->getBaseObject();
3191 return (isa<GlobalVariable>(GV) && cast<GlobalVariable>(GV)->isConstant()) ||
3192 isa<Function>(GV);
3193}
3194
3195SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3196 SelectionDAG &DAG) const {
3197 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3198 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3198)
;
3199 case Triple::COFF:
3200 return LowerGlobalAddressWindows(Op, DAG);
3201 case Triple::ELF:
3202 return LowerGlobalAddressELF(Op, DAG);
3203 case Triple::MachO:
3204 return LowerGlobalAddressDarwin(Op, DAG);
3205 }
3206}
3207
3208SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3209 SelectionDAG &DAG) const {
3210 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3211 SDLoc dl(Op);
3212 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3213 const TargetMachine &TM = getTargetMachine();
3214 bool IsRO = isReadOnly(GV);
3215
3216 // promoteToConstantPool only if not generating XO text section
3217 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3218 if (SDValue V = promoteToConstantPool(GV, DAG, PtrVT, dl))
3219 return V;
3220
3221 if (isPositionIndependent()) {
3222 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3223 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3224 UseGOT_PREL ? ARMII::MO_GOT : 0);
3225 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3226 if (UseGOT_PREL)
3227 Result =
3228 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3229 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3230 return Result;
3231 } else if (Subtarget->isROPI() && IsRO) {
3232 // PC-relative.
3233 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3234 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3235 return Result;
3236 } else if (Subtarget->isRWPI() && !IsRO) {
3237 // SB-relative.
3238 SDValue RelAddr;
3239 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3240 ++NumMovwMovt;
3241 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3242 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3243 } else { // use literal pool for address constant
3244 ARMConstantPoolValue *CPV =
3245 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3246 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3247 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3248 RelAddr = DAG.getLoad(
3249 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3250 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3251 }
3252 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3253 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3254 return Result;
3255 }
3256
3257 // If we have T2 ops, we can materialize the address directly via movt/movw
3258 // pair. This is always cheaper.
3259 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3260 ++NumMovwMovt;
3261 // FIXME: Once remat is capable of dealing with instructions with register
3262 // operands, expand this into two nodes.
3263 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3264 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3265 } else {
3266 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3267 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3268 return DAG.getLoad(
3269 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3270 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3271 }
3272}
3273
3274SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3275 SelectionDAG &DAG) const {
3276 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3277, __extension__ __PRETTY_FUNCTION__))
3277 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3277, __extension__ __PRETTY_FUNCTION__))
;
3278 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3279 SDLoc dl(Op);
3280 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3281
3282 if (Subtarget->useMovt(DAG.getMachineFunction()))
3283 ++NumMovwMovt;
3284
3285 // FIXME: Once remat is capable of dealing with instructions with register
3286 // operands, expand this into multiple nodes
3287 unsigned Wrapper =
3288 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3289
3290 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3291 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3292
3293 if (Subtarget->isGVIndirectSymbol(GV))
3294 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3295 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3296 return Result;
3297}
3298
3299SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3300 SelectionDAG &DAG) const {
3301 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3301, __extension__ __PRETTY_FUNCTION__))
;
3302 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3303, __extension__ __PRETTY_FUNCTION__))
3303 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3303, __extension__ __PRETTY_FUNCTION__))
;
3304 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3305, __extension__ __PRETTY_FUNCTION__))
3305 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3305, __extension__ __PRETTY_FUNCTION__))
;
3306
3307 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3308 const ARMII::TOF TargetFlags =
3309 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
3310 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3311 SDValue Result;
3312 SDLoc DL(Op);
3313
3314 ++NumMovwMovt;
3315
3316 // FIXME: Once remat is capable of dealing with instructions with register
3317 // operands, expand this into two nodes.
3318 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3319 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3320 TargetFlags));
3321 if (GV->hasDLLImportStorageClass())
3322 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3323 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3324 return Result;
3325}
3326
3327SDValue
3328ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3329 SDLoc dl(Op);
3330 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3331 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3332 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3333 Op.getOperand(1), Val);
3334}
3335
3336SDValue
3337ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3338 SDLoc dl(Op);
3339 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3340 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3341}
3342
3343SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3344 SelectionDAG &DAG) const {
3345 SDLoc dl(Op);
3346 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3347 Op.getOperand(0));
3348}
3349
3350SDValue
3351ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3352 const ARMSubtarget *Subtarget) const {
3353 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3354 SDLoc dl(Op);
3355 switch (IntNo) {
3356 default: return SDValue(); // Don't custom lower most intrinsics.
3357 case Intrinsic::thread_pointer: {
3358 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3359 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3360 }
3361 case Intrinsic::eh_sjlj_lsda: {
3362 MachineFunction &MF = DAG.getMachineFunction();
3363 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3364 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3365 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3366 SDValue CPAddr;
3367 bool IsPositionIndependent = isPositionIndependent();
3368 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3369 ARMConstantPoolValue *CPV =
3370 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3371 ARMCP::CPLSDA, PCAdj);
3372 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3373 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3374 SDValue Result = DAG.getLoad(
3375 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3376 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3377
3378 if (IsPositionIndependent) {
3379 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3380 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3381 }
3382 return Result;
3383 }
3384 case Intrinsic::arm_neon_vabs:
3385 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3386 Op.getOperand(1));
3387 case Intrinsic::arm_neon_vmulls:
3388 case Intrinsic::arm_neon_vmullu: {
3389 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3390 ? ARMISD::VMULLs : ARMISD::VMULLu;
3391 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3392 Op.getOperand(1), Op.getOperand(2));
3393 }
3394 case Intrinsic::arm_neon_vminnm:
3395 case Intrinsic::arm_neon_vmaxnm: {
3396 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3397 ? ISD::FMINNUM : ISD::FMAXNUM;
3398 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3399 Op.getOperand(1), Op.getOperand(2));
3400 }
3401 case Intrinsic::arm_neon_vminu:
3402 case Intrinsic::arm_neon_vmaxu: {
3403 if (Op.getValueType().isFloatingPoint())
3404 return SDValue();
3405 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3406 ? ISD::UMIN : ISD::UMAX;
3407 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3408 Op.getOperand(1), Op.getOperand(2));
3409 }
3410 case Intrinsic::arm_neon_vmins:
3411 case Intrinsic::arm_neon_vmaxs: {
3412 // v{min,max}s is overloaded between signed integers and floats.
3413 if (!Op.getValueType().isFloatingPoint()) {
3414 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3415 ? ISD::SMIN : ISD::SMAX;
3416 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3417 Op.getOperand(1), Op.getOperand(2));
3418 }
3419 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3420 ? ISD::FMINNAN : ISD::FMAXNAN;
3421 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3422 Op.getOperand(1), Op.getOperand(2));
3423 }
3424 case Intrinsic::arm_neon_vtbl1:
3425 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3426 Op.getOperand(1), Op.getOperand(2));
3427 case Intrinsic::arm_neon_vtbl2:
3428 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3429 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3430 }
3431}
3432
3433static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3434 const ARMSubtarget *Subtarget) {
3435 SDLoc dl(Op);
3436 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3437 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3438 if (SSID == SyncScope::SingleThread)
3439 return Op;
3440
3441 if (!Subtarget->hasDataBarrier()) {
3442 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3443 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3444 // here.
3445 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3446, __extension__ __PRETTY_FUNCTION__))
3446 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3446, __extension__ __PRETTY_FUNCTION__))
;
3447 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3448 DAG.getConstant(0, dl, MVT::i32));
3449 }
3450
3451 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3452 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3453 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3454 if (Subtarget->isMClass()) {
3455 // Only a full system barrier exists in the M-class architectures.
3456 Domain = ARM_MB::SY;
3457 } else if (Subtarget->preferISHSTBarriers() &&
3458 Ord == AtomicOrdering::Release) {
3459 // Swift happens to implement ISHST barriers in a way that's compatible with
3460 // Release semantics but weaker than ISH so we'd be fools not to use
3461 // it. Beware: other processors probably don't!
3462 Domain = ARM_MB::ISHST;
3463 }
3464
3465 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3466 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3467 DAG.getConstant(Domain, dl, MVT::i32));
3468}
3469
3470static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3471 const ARMSubtarget *Subtarget) {
3472 // ARM pre v5TE and Thumb1 does not have preload instructions.
3473 if (!(Subtarget->isThumb2() ||
3474 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3475 // Just preserve the chain.
3476 return Op.getOperand(0);
3477
3478 SDLoc dl(Op);
3479 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3480 if (!isRead &&
3481 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3482 // ARMv7 with MP extension has PLDW.
3483 return Op.getOperand(0);
3484
3485 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3486 if (Subtarget->isThumb()) {
3487 // Invert the bits.
3488 isRead = ~isRead & 1;
3489 isData = ~isData & 1;
3490 }
3491
3492 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3493 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3494 DAG.getConstant(isData, dl, MVT::i32));
3495}
3496
3497static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3498 MachineFunction &MF = DAG.getMachineFunction();
3499 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3500
3501 // vastart just stores the address of the VarArgsFrameIndex slot into the
3502 // memory location argument.
3503 SDLoc dl(Op);
3504 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3505 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3506 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3507 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3508 MachinePointerInfo(SV));
3509}
3510
3511SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3512 CCValAssign &NextVA,
3513 SDValue &Root,
3514 SelectionDAG &DAG,
3515 const SDLoc &dl) const {
3516 MachineFunction &MF = DAG.getMachineFunction();
3517 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3518
3519 const TargetRegisterClass *RC;
3520 if (AFI->isThumb1OnlyFunction())
3521 RC = &ARM::tGPRRegClass;
3522 else
3523 RC = &ARM::GPRRegClass;
3524
3525 // Transform the arguments stored in physical registers into virtual ones.
3526 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3527 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3528
3529 SDValue ArgValue2;
3530 if (NextVA.isMemLoc()) {
3531 MachineFrameInfo &MFI = MF.getFrameInfo();
3532 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3533
3534 // Create load node to retrieve arguments from the stack.
3535 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3536 ArgValue2 = DAG.getLoad(
3537 MVT::i32, dl, Root, FIN,
3538 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3539 } else {
3540 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3541 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3542 }
3543 if (!Subtarget->isLittle())
3544 std::swap (ArgValue, ArgValue2);
3545 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3546}
3547
3548// The remaining GPRs hold either the beginning of variable-argument
3549// data, or the beginning of an aggregate passed by value (usually
3550// byval). Either way, we allocate stack slots adjacent to the data
3551// provided by our caller, and store the unallocated registers there.
3552// If this is a variadic function, the va_list pointer will begin with
3553// these values; otherwise, this reassembles a (byval) structure that
3554// was split between registers and memory.
3555// Return: The frame index registers were stored into.
3556int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3557 const SDLoc &dl, SDValue &Chain,
3558 const Value *OrigArg,
3559 unsigned InRegsParamRecordIdx,
3560 int ArgOffset, unsigned ArgSize) const {
3561 // Currently, two use-cases possible:
3562 // Case #1. Non-var-args function, and we meet first byval parameter.
3563 // Setup first unallocated register as first byval register;
3564 // eat all remained registers
3565 // (these two actions are performed by HandleByVal method).
3566 // Then, here, we initialize stack frame with
3567 // "store-reg" instructions.
3568 // Case #2. Var-args function, that doesn't contain byval parameters.
3569 // The same: eat all remained unallocated registers,
3570 // initialize stack frame.
3571
3572 MachineFunction &MF = DAG.getMachineFunction();
3573 MachineFrameInfo &MFI = MF.getFrameInfo();
3574 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3575 unsigned RBegin, REnd;
3576 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3577 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3578 } else {
3579 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3580 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3581 REnd = ARM::R4;
3582 }
3583
3584 if (REnd != RBegin)
3585 ArgOffset = -4 * (ARM::R4 - RBegin);
3586
3587 auto PtrVT = getPointerTy(DAG.getDataLayout());
3588 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3589 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3590
3591 SmallVector<SDValue, 4> MemOps;
3592 const TargetRegisterClass *RC =
3593 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3594
3595 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3596 unsigned VReg = MF.addLiveIn(Reg, RC);
3597 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3598 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3599 MachinePointerInfo(OrigArg, 4 * i));
3600 MemOps.push_back(Store);
3601 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3602 }
3603
3604 if (!MemOps.empty())
3605 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3606 return FrameIndex;
3607}
3608
3609// Setup stack frame, the va_list pointer will start from.
3610void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3611 const SDLoc &dl, SDValue &Chain,
3612 unsigned ArgOffset,
3613 unsigned TotalArgRegsSaveSize,
3614 bool ForceMutable) const {
3615 MachineFunction &MF = DAG.getMachineFunction();
3616 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3617
3618 // Try to store any remaining integer argument regs
3619 // to their spots on the stack so that they may be loaded by dereferencing
3620 // the result of va_next.
3621 // If there is no regs to be stored, just point address after last
3622 // argument passed via stack.
3623 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3624 CCInfo.getInRegsParamsCount(),
3625 CCInfo.getNextStackOffset(), 4);
3626 AFI->setVarArgsFrameIndex(FrameIndex);
3627}
3628
3629SDValue ARMTargetLowering::LowerFormalArguments(
3630 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3631 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3632 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3633 MachineFunction &MF = DAG.getMachineFunction();
3634 MachineFrameInfo &MFI = MF.getFrameInfo();
3635
3636 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3637
3638 // Assign locations to all of the incoming arguments.
3639 SmallVector<CCValAssign, 16> ArgLocs;
3640 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3641 *DAG.getContext());
3642 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3643
3644 SmallVector<SDValue, 16> ArgValues;
3645 SDValue ArgValue;
3646 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3647 unsigned CurArgIdx = 0;
3648
3649 // Initially ArgRegsSaveSize is zero.
3650 // Then we increase this value each time we meet byval parameter.
3651 // We also increase this value in case of varargs function.
3652 AFI->setArgRegsSaveSize(0);
3653
3654 // Calculate the amount of stack space that we need to allocate to store
3655 // byval and variadic arguments that are passed in registers.
3656 // We need to know this before we allocate the first byval or variadic
3657 // argument, as they will be allocated a stack slot below the CFA (Canonical
3658 // Frame Address, the stack pointer at entry to the function).
3659 unsigned ArgRegBegin = ARM::R4;
3660 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3661 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3662 break;
3663
3664 CCValAssign &VA = ArgLocs[i];
3665 unsigned Index = VA.getValNo();
3666 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3667 if (!Flags.isByVal())
3668 continue;
3669
3670 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3670, __extension__ __PRETTY_FUNCTION__))
;
3671 unsigned RBegin, REnd;
3672 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3673 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3674
3675 CCInfo.nextInRegsParam();
3676 }
3677 CCInfo.rewindByValRegsInfo();
3678
3679 int lastInsIndex = -1;
3680 if (isVarArg && MFI.hasVAStart()) {
3681 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3682 if (RegIdx != array_lengthof(GPRArgRegs))
3683 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3684 }
3685
3686 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3687 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3688 auto PtrVT = getPointerTy(DAG.getDataLayout());
3689
3690 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3691 CCValAssign &VA = ArgLocs[i];
3692 if (Ins[VA.getValNo()].isOrigArg()) {
3693 std::advance(CurOrigArg,
3694 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3695 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3696 }
3697 // Arguments stored in registers.
3698 if (VA.isRegLoc()) {
3699 EVT RegVT = VA.getLocVT();
3700
3701 if (VA.needsCustom()) {
3702 // f64 and vector types are split up into multiple registers or
3703 // combinations of registers and stack slots.
3704 if (VA.getLocVT() == MVT::v2f64) {
3705 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3706 Chain, DAG, dl);
3707 VA = ArgLocs[++i]; // skip ahead to next loc
3708 SDValue ArgValue2;
3709 if (VA.isMemLoc()) {
3710 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3711 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3712 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3713 MachinePointerInfo::getFixedStack(
3714 DAG.getMachineFunction(), FI));
3715 } else {
3716 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3717 Chain, DAG, dl);
3718 }
3719 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3720 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3721 ArgValue, ArgValue1,
3722 DAG.getIntPtrConstant(0, dl));
3723 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3724 ArgValue, ArgValue2,
3725 DAG.getIntPtrConstant(1, dl));
3726 } else
3727 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3728 } else {
3729 const TargetRegisterClass *RC;
3730
3731
3732 if (RegVT == MVT::f16)
3733 RC = &ARM::HPRRegClass;
3734 else if (RegVT == MVT::f32)
3735 RC = &ARM::SPRRegClass;
3736 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
3737 RC = &ARM::DPRRegClass;
3738 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
3739 RC = &ARM::QPRRegClass;
3740 else if (RegVT == MVT::i32)
3741 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3742 : &ARM::GPRRegClass;
3743 else
3744 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3744)
;
3745
3746 // Transform the arguments in physical registers into virtual ones.
3747 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3748 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3749 }
3750
3751 // If this is an 8 or 16-bit value, it is really passed promoted
3752 // to 32 bits. Insert an assert[sz]ext to capture this, then
3753 // truncate to the right size.
3754 switch (VA.getLocInfo()) {
3755 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3755)
;
3756 case CCValAssign::Full: break;
3757 case CCValAssign::BCvt:
3758 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3759 break;
3760 case CCValAssign::SExt:
3761 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3762 DAG.getValueType(VA.getValVT()));
3763 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3764 break;
3765 case CCValAssign::ZExt:
3766 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3767 DAG.getValueType(VA.getValVT()));
3768 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3769 break;
3770 }
3771
3772 InVals.push_back(ArgValue);
3773 } else { // VA.isRegLoc()
3774 // sanity check
3775 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3775, __extension__ __PRETTY_FUNCTION__))
;
3776 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3776, __extension__ __PRETTY_FUNCTION__))
;
3777
3778 int index = VA.getValNo();
3779
3780 // Some Ins[] entries become multiple ArgLoc[] entries.
3781 // Process them only once.
3782 if (index != lastInsIndex)
3783 {
3784 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3785 // FIXME: For now, all byval parameter objects are marked mutable.
3786 // This can be changed with more analysis.
3787 // In case of tail call optimization mark all arguments mutable.
3788 // Since they could be overwritten by lowering of arguments in case of
3789 // a tail call.
3790 if (Flags.isByVal()) {
3791 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3792, __extension__ __PRETTY_FUNCTION__))
3792 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3792, __extension__ __PRETTY_FUNCTION__))
;
3793 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3794
3795 int FrameIndex = StoreByValRegs(
3796 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3797 VA.getLocMemOffset(), Flags.getByValSize());
3798 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3799 CCInfo.nextInRegsParam();
3800 } else {
3801 unsigned FIOffset = VA.getLocMemOffset();
3802 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3803 FIOffset, true);
3804
3805 // Create load nodes to retrieve arguments from the stack.
3806 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3807 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3808 MachinePointerInfo::getFixedStack(
3809 DAG.getMachineFunction(), FI)));
3810 }
3811 lastInsIndex = index;
3812 }
3813 }
3814 }
3815
3816 // varargs
3817 if (isVarArg && MFI.hasVAStart())
3818 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3819 CCInfo.getNextStackOffset(),
3820 TotalArgRegsSaveSize);
3821
3822 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3823
3824 return Chain;
3825}
3826
3827/// isFloatingPointZero - Return true if this is +0.0.
3828static bool isFloatingPointZero(SDValue Op) {
3829 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3830 return CFP->getValueAPF().isPosZero();
3831 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3832 // Maybe this has already been legalized into the constant pool?
3833 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3834 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3835 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3836 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3837 return CFP->getValueAPF().isPosZero();
3838 }
3839 } else if (Op->getOpcode() == ISD::BITCAST &&
3840 Op->getValueType(0) == MVT::f64) {
3841 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3842 // created by LowerConstantFP().
3843 SDValue BitcastOp = Op->getOperand(0);
3844 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3845 isNullConstant(BitcastOp->getOperand(0)))
3846 return true;
3847 }
3848 return false;
3849}
3850
3851/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3852/// the given operands.
3853SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3854 SDValue &ARMcc, SelectionDAG &DAG,
3855 const SDLoc &dl) const {
3856 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3857 unsigned C = RHSC->getZExtValue();
3858 if (!isLegalICmpImmediate(C)) {
3859 // Constant does not fit, try adjusting it by one?
3860 switch (CC) {
3861 default: break;
3862 case ISD::SETLT:
3863 case ISD::SETGE:
3864 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3865 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3866 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3867 }
3868 break;
3869 case ISD::SETULT:
3870 case ISD::SETUGE:
3871 if (C != 0 && isLegalICmpImmediate(C-1)) {
3872 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3873 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3874 }
3875 break;
3876 case ISD::SETLE:
3877 case ISD::SETGT:
3878 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3879 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3880 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3881 }
3882 break;
3883 case ISD::SETULE:
3884 case ISD::SETUGT:
3885 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3886 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3887 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3888 }
3889 break;
3890 }
3891 }
3892 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3893 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3894 // In ARM and Thumb-2, the compare instructions can shift their second
3895 // operand.
3896 CC = ISD::getSetCCSwappedOperands(CC);
3897 std::swap(LHS, RHS);
3898 }
3899
3900 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3901 ARMISD::NodeType CompareType;
3902 switch (CondCode) {
3903 default:
3904 CompareType = ARMISD::CMP;
3905 break;
3906 case ARMCC::EQ:
3907 case ARMCC::NE:
3908 // Uses only Z Flag
3909 CompareType = ARMISD::CMPZ;
3910 break;
3911 }
3912 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3913 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3914}
3915
3916/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3917SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3918 SelectionDAG &DAG, const SDLoc &dl,
3919 bool InvalidOnQNaN) const {
3920 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)(static_cast <bool> (!Subtarget->isFPOnlySP() || RHS
.getValueType() != MVT::f64) ? void (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3920, __extension__ __PRETTY_FUNCTION__))
;
3921 SDValue Cmp;
3922 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3923 if (!isFloatingPointZero(RHS))
3924 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3925 else
3926 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3927 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3928}
3929
3930/// duplicateCmp - Glue values can have only one use, so this function
3931/// duplicates a comparison node.
3932SDValue
3933ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3934 unsigned Opc = Cmp.getOpcode();
3935 SDLoc DL(Cmp);
3936 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3937 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3938
3939 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3939, __extension__ __PRETTY_FUNCTION__))
;
3940 Cmp = Cmp.getOperand(0);
3941 Opc = Cmp.getOpcode();
3942 if (Opc == ARMISD::CMPFP)
3943 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3944 Cmp.getOperand(1), Cmp.getOperand(2));
3945 else {
3946 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3946, __extension__ __PRETTY_FUNCTION__))
;
3947 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3948 Cmp.getOperand(1));
3949 }
3950 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3951}
3952
3953// This function returns three things: the arithmetic computation itself
3954// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3955// comparison and the condition code define the case in which the arithmetic
3956// computation *does not* overflow.
3957std::pair<SDValue, SDValue>
3958ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3959 SDValue &ARMcc) const {
3960 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3960, __extension__ __PRETTY_FUNCTION__))
;
3961
3962 SDValue Value, OverflowCmp;
3963 SDValue LHS = Op.getOperand(0);
3964 SDValue RHS = Op.getOperand(1);
3965 SDLoc dl(Op);
3966
3967 // FIXME: We are currently always generating CMPs because we don't support
3968 // generating CMN through the backend. This is not as good as the natural
3969 // CMP case because it causes a register dependency and cannot be folded
3970 // later.
3971
3972 switch (Op.getOpcode()) {
3973 default:
3974 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 3974)
;
3975 case ISD::SADDO:
3976 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3977 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3978 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3979 break;
3980 case ISD::UADDO:
3981 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3982 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3983 // We do not use it in the USUBO case as Value may not be used.
3984 Value = DAG.getNode(ARMISD::ADDC, dl,
3985 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3986 .getValue(0);
3987 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3988 break;
3989 case ISD::SSUBO:
3990 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3991 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3992 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3993 break;
3994 case ISD::USUBO:
3995 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3996 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3997 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3998 break;
3999 case ISD::UMULO:
4000 // We generate a UMUL_LOHI and then check if the high word is 0.
4001 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4002 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4003 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4004 LHS, RHS);
4005 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4006 DAG.getConstant(0, dl, MVT::i32));
4007 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4008 break;
4009 case ISD::SMULO:
4010 // We generate a SMUL_LOHI and then check if all the bits of the high word
4011 // are the same as the sign bit of the low word.
4012 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4013 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4014 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4015 LHS, RHS);
4016 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4017 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4018 Value.getValue(0),
4019 DAG.getConstant(31, dl, MVT::i32)));
4020 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4021 break;
4022 } // switch (...)
4023
4024 return std::make_pair(Value, OverflowCmp);
4025}
4026
4027SDValue
4028ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4029 // Let legalize expand this if it isn't a legal type yet.
4030 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4031 return SDValue();
4032
4033 SDValue Value, OverflowCmp;
4034 SDValue ARMcc;
4035 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4036 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4037 SDLoc dl(Op);
4038 // We use 0 and 1 as false and true values.
4039 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4040 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4041 EVT VT = Op.getValueType();
4042
4043 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4044 ARMcc, CCR, OverflowCmp);
4045
4046 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4047 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4048}
4049
4050static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4051 SelectionDAG &DAG) {
4052 SDLoc DL(BoolCarry);
4053 EVT CarryVT = BoolCarry.getValueType();
4054
4055 // This converts the boolean value carry into the carry flag by doing
4056 // ARMISD::SUBC Carry, 1
4057 return DAG.getNode(ARMISD::SUBC, DL, DAG.getVTList(CarryVT, MVT::i32),
4058 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4059}
4060
4061static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4062 SelectionDAG &DAG) {
4063 SDLoc DL(Flags);
4064
4065 // Now convert the carry flag into a boolean carry. We do this
4066 // using ARMISD:ADDE 0, 0, Carry
4067 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4068 DAG.getConstant(0, DL, MVT::i32),
4069 DAG.getConstant(0, DL, MVT::i32), Flags);
4070}
4071
4072SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4073 SelectionDAG &DAG) const {
4074 // Let legalize expand this if it isn't a legal type yet.
4075 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4076 return SDValue();
4077
4078 SDValue LHS = Op.getOperand(0);
4079 SDValue RHS = Op.getOperand(1);
4080 SDLoc dl(Op);
4081
4082 EVT VT = Op.getValueType();
4083 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4084 SDValue Value;
4085 SDValue Overflow;
4086 switch (Op.getOpcode()) {
4087 default:
4088 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4088)
;
4089 case ISD::UADDO:
4090 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4091 // Convert the carry flag into a boolean value.
4092 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4093 break;
4094 case ISD::USUBO: {
4095 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4096 // Convert the carry flag into a boolean value.
4097 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4098 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4099 // value. So compute 1 - C.
4100 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4101 DAG.getConstant(1, dl, MVT::i32), Overflow);
4102 break;
4103 }
4104 }
4105
4106 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4107}
4108
4109SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4110 SDValue Cond = Op.getOperand(0);
4111 SDValue SelectTrue = Op.getOperand(1);
4112 SDValue SelectFalse = Op.getOperand(2);
4113 SDLoc dl(Op);
4114 unsigned Opc = Cond.getOpcode();
4115
4116 if (Cond.getResNo() == 1 &&
4117 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4118 Opc == ISD::USUBO)) {
4119 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4120 return SDValue();
4121
4122 SDValue Value, OverflowCmp;
4123 SDValue ARMcc;
4124 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4125 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4126 EVT VT = Op.getValueType();
4127
4128 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4129 OverflowCmp, DAG);
4130 }
4131
4132 // Convert:
4133 //
4134 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4135 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4136 //
4137 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4138 const ConstantSDNode *CMOVTrue =
4139 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4140 const ConstantSDNode *CMOVFalse =
4141 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4142
4143 if (CMOVTrue && CMOVFalse) {
4144 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4145 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4146
4147 SDValue True;
4148 SDValue False;
4149 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4150 True = SelectTrue;
4151 False = SelectFalse;
4152 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4153 True = SelectFalse;
4154 False = SelectTrue;
4155 }
4156
4157 if (True.getNode() && False.getNode()) {
4158 EVT VT = Op.getValueType();
4159 SDValue ARMcc = Cond.getOperand(2);
4160 SDValue CCR = Cond.getOperand(3);
4161 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4162 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4162, __extension__ __PRETTY_FUNCTION__))
;
4163 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4164 }
4165 }
4166 }
4167
4168 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4169 // undefined bits before doing a full-word comparison with zero.
4170 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4171 DAG.getConstant(1, dl, Cond.getValueType()));
4172
4173 return DAG.getSelectCC(dl, Cond,
4174 DAG.getConstant(0, dl, Cond.getValueType()),
4175 SelectTrue, SelectFalse, ISD::SETNE);
4176}
4177
4178static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4179 bool &swpCmpOps, bool &swpVselOps) {
4180 // Start by selecting the GE condition code for opcodes that return true for
4181 // 'equality'
4182 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4183 CC == ISD::SETULE)
4184 CondCode = ARMCC::GE;
4185
4186 // and GT for opcodes that return false for 'equality'.
4187 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4188 CC == ISD::SETULT)
4189 CondCode = ARMCC::GT;
4190
4191 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4192 // to swap the compare operands.
4193 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4194 CC == ISD::SETULT)
4195 swpCmpOps = true;
4196
4197 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4198 // If we have an unordered opcode, we need to swap the operands to the VSEL
4199 // instruction (effectively negating the condition).
4200 //
4201 // This also has the effect of swapping which one of 'less' or 'greater'
4202 // returns true, so we also swap the compare operands. It also switches
4203 // whether we return true for 'equality', so we compensate by picking the
4204 // opposite condition code to our original choice.
4205 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4206 CC == ISD::SETUGT) {
4207 swpCmpOps = !swpCmpOps;
4208 swpVselOps = !swpVselOps;
4209 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4210 }
4211
4212 // 'ordered' is 'anything but unordered', so use the VS condition code and
4213 // swap the VSEL operands.
4214 if (CC == ISD::SETO) {
4215 CondCode = ARMCC::VS;
4216 swpVselOps = true;
4217 }
4218
4219 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4220 // code and swap the VSEL operands.
4221 if (CC == ISD::SETUNE) {
4222 CondCode = ARMCC::EQ;
4223 swpVselOps = true;
4224 }
4225}
4226
4227SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4228 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4229 SDValue Cmp, SelectionDAG &DAG) const {
4230 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4231 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4232 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4233 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4234 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4235
4236 SDValue TrueLow = TrueVal.getValue(0);
4237 SDValue TrueHigh = TrueVal.getValue(1);
4238 SDValue FalseLow = FalseVal.getValue(0);
4239 SDValue FalseHigh = FalseVal.getValue(1);
4240
4241 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4242 ARMcc, CCR, Cmp);
4243 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4244 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4245
4246 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4247 } else {
4248 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4249 Cmp);
4250 }
4251}
4252
4253static bool isGTorGE(ISD::CondCode CC) {
4254 return CC == ISD::SETGT || CC == ISD::SETGE;
4255}
4256
4257static bool isLTorLE(ISD::CondCode CC) {
4258 return CC == ISD::SETLT || CC == ISD::SETLE;
4259}
4260
4261// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4262// All of these conditions (and their <= and >= counterparts) will do:
4263// x < k ? k : x
4264// x > k ? x : k
4265// k < x ? x : k
4266// k > x ? k : x
4267static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4268 const SDValue TrueVal, const SDValue FalseVal,
4269 const ISD::CondCode CC, const SDValue K) {
4270 return (isGTorGE(CC) &&
4271 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4272 (isLTorLE(CC) &&
4273 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4274}
4275
4276// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4277static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4278 const SDValue TrueVal, const SDValue FalseVal,
4279 const ISD::CondCode CC, const SDValue K) {
4280 return (isGTorGE(CC) &&
4281 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4282 (isLTorLE(CC) &&
4283 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4284}
4285
4286// Check if two chained conditionals could be converted into SSAT or USAT.
4287//
4288// SSAT can replace a set of two conditional selectors that bound a number to an
4289// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4290//
4291// x < -k ? -k : (x > k ? k : x)
4292// x < -k ? -k : (x < k ? x : k)
4293// x > -k ? (x > k ? k : x) : -k
4294// x < k ? (x < -k ? -k : x) : k
4295// etc.
4296//
4297// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4298// a power of 2.
4299//
4300// It returns true if the conversion can be done, false otherwise.
4301// Additionally, the variable is returned in parameter V, the constant in K and
4302// usat is set to true if the conditional represents an unsigned saturation
4303static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4304 uint64_t &K, bool &usat) {
4305 SDValue LHS1 = Op.getOperand(0);
4306 SDValue RHS1 = Op.getOperand(1);
4307 SDValue TrueVal1 = Op.getOperand(2);
4308 SDValue FalseVal1 = Op.getOperand(3);
4309 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4310
4311 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4312 if (Op2.getOpcode() != ISD::SELECT_CC)
4313 return false;
4314
4315 SDValue LHS2 = Op2.getOperand(0);
4316 SDValue RHS2 = Op2.getOperand(1);
4317 SDValue TrueVal2 = Op2.getOperand(2);
4318 SDValue FalseVal2 = Op2.getOperand(3);
4319 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4320
4321 // Find out which are the constants and which are the variables
4322 // in each conditional
4323 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4324 ? &RHS1
4325 : nullptr;
4326 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4327 ? &RHS2
4328 : nullptr;
4329 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4330 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4331 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4332 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4333
4334 // We must detect cases where the original operations worked with 16- or
4335 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4336 // must work with sign-extended values but the select operations return
4337 // the original non-extended value.
4338 SDValue V2TmpReg = V2Tmp;
4339 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4340 V2TmpReg = V2Tmp->getOperand(0);
4341
4342 // Check that the registers and the constants have the correct values
4343 // in both conditionals
4344 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4345 V2TmpReg != V2)
4346 return false;
4347
4348 // Figure out which conditional is saturating the lower/upper bound.
4349 const SDValue *LowerCheckOp =
4350 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4351 ? &Op
4352 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4353 ? &Op2
4354 : nullptr;
4355 const SDValue *UpperCheckOp =
4356 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4357 ? &Op
4358 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4359 ? &Op2
4360 : nullptr;
4361
4362 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4363 return false;
4364
4365 // Check that the constant in the lower-bound check is
4366 // the opposite of the constant in the upper-bound check
4367 // in 1's complement.
4368 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4369 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4370 int64_t PosVal = std::max(Val1, Val2);
4371 int64_t NegVal = std::min(Val1, Val2);
4372
4373 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4374 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4375 isPowerOf2_64(PosVal + 1)) {
4376
4377 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4378 if (Val1 == ~Val2)
4379 usat = false;
4380 else if (NegVal == 0)
4381 usat = true;
4382 else
4383 return false;
4384
4385 V = V2;
4386 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4387
4388 return true;
4389 }
4390
4391 return false;
4392}
4393
4394// Check if a condition of the type x < k ? k : x can be converted into a
4395// bit operation instead of conditional moves.
4396// Currently this is allowed given:
4397// - The conditions and values match up
4398// - k is 0 or -1 (all ones)
4399// This function will not check the last condition, thats up to the caller
4400// It returns true if the transformation can be made, and in such case
4401// returns x in V, and k in SatK.
4402static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4403 SDValue &SatK)
4404{
4405 SDValue LHS = Op.getOperand(0);
4406 SDValue RHS = Op.getOperand(1);
4407 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4408 SDValue TrueVal = Op.getOperand(2);
4409 SDValue FalseVal = Op.getOperand(3);
4410
4411 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4412 ? &RHS
4413 : nullptr;
4414
4415 // No constant operation in comparison, early out
4416 if (!K)
4417 return false;
4418
4419 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4420 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4421 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4422
4423 // If the constant on left and right side, or variable on left and right,
4424 // does not match, early out
4425 if (*K != KTmp || V != VTmp)
4426 return false;
4427
4428 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4429 SatK = *K;
4430 return true;
4431 }
4432
4433 return false;
4434}
4435
4436SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4437 EVT VT = Op.getValueType();
4438 SDLoc dl(Op);
4439
4440 // Try to convert two saturating conditional selects into a single SSAT
4441 SDValue SatValue;
4442 uint64_t SatConstant;
4443 bool SatUSat;
4444 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4445 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4446 if (SatUSat)
4447 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4448 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4449 else
4450 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4451 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4452 }
4453
4454 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4455 // into more efficient bit operations, which is possible when k is 0 or -1
4456 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4457 // single instructions. On Thumb the shift and the bit operation will be two
4458 // instructions.
4459 // Only allow this transformation on full-width (32-bit) operations
4460 SDValue LowerSatConstant;
4461 if (VT == MVT::i32 &&
4462 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4463 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4464 DAG.getConstant(31, dl, VT));
4465 if (isNullConstant(LowerSatConstant)) {
4466 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4467 DAG.getAllOnesConstant(dl, VT));
4468 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4469 } else if (isAllOnesConstant(LowerSatConstant))
4470 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4471 }
4472
4473 SDValue LHS = Op.getOperand(0);
4474 SDValue RHS = Op.getOperand(1);
4475 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4476 SDValue TrueVal = Op.getOperand(2);
4477 SDValue FalseVal = Op.getOperand(3);
4478
4479 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4480 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4481 dl);
4482
4483 // If softenSetCCOperands only returned one value, we should compare it to
4484 // zero.
4485 if (!RHS.getNode()) {
4486 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4487 CC = ISD::SETNE;
4488 }
4489 }
4490
4491 if (LHS.getValueType() == MVT::i32) {
4492 // Try to generate VSEL on ARMv8.
4493 // The VSEL instruction can't use all the usual ARM condition
4494 // codes: it only has two bits to select the condition code, so it's
4495 // constrained to use only GE, GT, VS and EQ.
4496 //
4497 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4498 // swap the operands of the previous compare instruction (effectively
4499 // inverting the compare condition, swapping 'less' and 'greater') and
4500 // sometimes need to swap the operands to the VSEL (which inverts the
4501 // condition in the sense of firing whenever the previous condition didn't)
4502 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4503 TrueVal.getValueType() == MVT::f64)) {
4504 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4505 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4506 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4507 CC = ISD::getSetCCInverse(CC, true);
4508 std::swap(TrueVal, FalseVal);
4509 }
4510 }
4511
4512 SDValue ARMcc;
4513 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4514 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4515 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4516 }
4517
4518 ARMCC::CondCodes CondCode, CondCode2;
4519 bool InvalidOnQNaN;
4520 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4521
4522 // Normalize the fp compare. If RHS is zero we keep it there so we match
4523 // CMPFPw0 instead of CMPFP.
4524 if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
4525 (TrueVal.getValueType() == MVT::f32 || TrueVal.getValueType() == MVT::f64)) {
4526 bool swpCmpOps = false;
4527 bool swpVselOps = false;
4528 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4529
4530 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4531 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4532 if (swpCmpOps)
4533 std::swap(LHS, RHS);
4534 if (swpVselOps)
4535 std::swap(TrueVal, FalseVal);
4536 }
4537 }
4538
4539 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4540 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4541 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4542 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4543 if (CondCode2 != ARMCC::AL) {
4544 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4545 // FIXME: Needs another CMP because flag can have but one use.
4546 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4547 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4548 }
4549 return Result;
4550}
4551
4552/// canChangeToInt - Given the fp compare operand, return true if it is suitable
4553/// to morph to an integer compare sequence.
4554static bool canChangeToInt(SDValue Op, bool &SeenZero,
4555 const ARMSubtarget *Subtarget) {
4556 SDNode *N = Op.getNode();
4557 if (!N->hasOneUse())
4558 // Otherwise it requires moving the value from fp to integer registers.
4559 return false;
4560 if (!N->getNumValues())
4561 return false;
4562 EVT VT = Op.getValueType();
4563 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4564 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4565 // vmrs are very slow, e.g. cortex-a8.
4566 return false;
4567
4568 if (isFloatingPointZero(Op)) {
4569 SeenZero = true;
4570 return true;
4571 }
4572 return ISD::isNormalLoad(N);
4573}
4574
4575static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4576 if (isFloatingPointZero(Op))
4577 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4578
4579 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4580 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4581 Ld->getPointerInfo(), Ld->getAlignment(),
4582 Ld->getMemOperand()->getFlags());
4583
4584 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4584)
;
4585}
4586
4587static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4588 SDValue &RetVal1, SDValue &RetVal2) {
4589 SDLoc dl(Op);
4590
4591 if (isFloatingPointZero(Op)) {
4592 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4593 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4594 return;
4595 }
4596
4597 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4598 SDValue Ptr = Ld->getBasePtr();
4599 RetVal1 =
4600 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4601 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4602
4603 EVT PtrType = Ptr.getValueType();
4604 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4605 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4606 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4607 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4608 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4609 Ld->getMemOperand()->getFlags());
4610 return;
4611 }
4612
4613 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4613)
;
4614}
4615
4616/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4617/// f32 and even f64 comparisons to integer ones.
4618SDValue
4619ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4620 SDValue Chain = Op.getOperand(0);
4621 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4622 SDValue LHS = Op.getOperand(2);
4623 SDValue RHS = Op.getOperand(3);
4624 SDValue Dest = Op.getOperand(4);
4625 SDLoc dl(Op);
4626
4627 bool LHSSeenZero = false;
4628 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4629 bool RHSSeenZero = false;
4630 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4631 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4632 // If unsafe fp math optimization is enabled and there are no other uses of
4633 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4634 // to an integer comparison.
4635 if (CC == ISD::SETOEQ)
4636 CC = ISD::SETEQ;
4637 else if (CC == ISD::SETUNE)
4638 CC = ISD::SETNE;
4639
4640 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4641 SDValue ARMcc;
4642 if (LHS.getValueType() == MVT::f32) {
4643 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4644 bitcastf32Toi32(LHS, DAG), Mask);
4645 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4646 bitcastf32Toi32(RHS, DAG), Mask);
4647 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4648 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4649 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4650 Chain, Dest, ARMcc, CCR, Cmp);
4651 }
4652
4653 SDValue LHS1, LHS2;
4654 SDValue RHS1, RHS2;
4655 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4656 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4657 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4658 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4659 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4660 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4661 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4662 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4663 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4664 }
4665
4666 return SDValue();
4667}
4668
4669SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4670 SDValue Chain = Op.getOperand(0);
4671 SDValue Cond = Op.getOperand(1);
4672 SDValue Dest = Op.getOperand(2);
4673 SDLoc dl(Op);
4674
4675 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4676 // instruction.
4677 unsigned Opc = Cond.getOpcode();
4678 if (Cond.getResNo() == 1 &&
4679 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4680 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4681 // Only lower legal XALUO ops.
4682 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4683 return SDValue();
4684
4685 // The actual operation with overflow check.
4686 SDValue Value, OverflowCmp;
4687 SDValue ARMcc;
4688 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4689
4690 // Reverse the condition code.
4691 ARMCC::CondCodes CondCode =
4692 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4693 CondCode = ARMCC::getOppositeCondition(CondCode);
4694 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4695 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4696
4697 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4698 OverflowCmp);
4699 }
4700
4701 return SDValue();
4702}
4703
4704SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4705 SDValue Chain = Op.getOperand(0);
4706 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4707 SDValue LHS = Op.getOperand(2);
4708 SDValue RHS = Op.getOperand(3);
4709 SDValue Dest = Op.getOperand(4);
4710 SDLoc dl(Op);
4711
4712 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4713 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4714 dl);
4715
4716 // If softenSetCCOperands only returned one value, we should compare it to
4717 // zero.
4718 if (!RHS.getNode()) {
4719 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4720 CC = ISD::SETNE;
4721 }
4722 }
4723
4724 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4725 // instruction.
4726 unsigned Opc = LHS.getOpcode();
4727 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4728 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4729 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4730 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4731 // Only lower legal XALUO ops.
4732 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4733 return SDValue();
4734
4735 // The actual operation with overflow check.
4736 SDValue Value, OverflowCmp;
4737 SDValue ARMcc;
4738 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4739
4740 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4741 // Reverse the condition code.
4742 ARMCC::CondCodes CondCode =
4743 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4744 CondCode = ARMCC::getOppositeCondition(CondCode);
4745 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4746 }
4747 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4748
4749 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4750 OverflowCmp);
4751 }
4752
4753 if (LHS.getValueType() == MVT::i32) {
4754 SDValue ARMcc;
4755 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4756 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4757 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4758 Chain, Dest, ARMcc, CCR, Cmp);
4759 }
4760
4761 if (getTargetMachine().Options.UnsafeFPMath &&
4762 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4763 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4764 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4765 return Result;
4766 }
4767
4768 ARMCC::CondCodes CondCode, CondCode2;
4769 bool InvalidOnQNaN;
4770 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4771
4772 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4773 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4774 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4775 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4776 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4777 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4778 if (CondCode2 != ARMCC::AL) {
4779 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4780 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4781 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4782 }
4783 return Res;
4784}
4785
4786SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4787 SDValue Chain = Op.getOperand(0);
4788 SDValue Table = Op.getOperand(1);
4789 SDValue Index = Op.getOperand(2);
4790 SDLoc dl(Op);
4791
4792 EVT PTy = getPointerTy(DAG.getDataLayout());
4793 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4794 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4795 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4796 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4797 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4798 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4799 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4800 // which does another jump to the destination. This also makes it easier
4801 // to translate it to TBB / TBH later (Thumb2 only).
4802 // FIXME: This might not work if the function is extremely large.
4803 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4804 Addr, Op.getOperand(2), JTI);
4805 }
4806 if (isPositionIndependent() || Subtarget->isROPI()) {
4807 Addr =
4808 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4809 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4810 Chain = Addr.getValue(1);
4811 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4812 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4813 } else {
4814 Addr =
4815 DAG.getLoad(PTy, dl, Chain, Addr,
4816 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4817 Chain = Addr.getValue(1);
4818 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4819 }
4820}
4821
4822static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4823 EVT VT = Op.getValueType();
4824 SDLoc dl(Op);
4825
4826 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4827 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4828 return Op;
4829 return DAG.UnrollVectorOp(Op.getNode());
4830 }
4831
4832 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4833, __extension__ __PRETTY_FUNCTION__))
4833 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4833, __extension__ __PRETTY_FUNCTION__))
;
4834 if (VT != MVT::v4i16)
4835 return DAG.UnrollVectorOp(Op.getNode());
4836
4837 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
4838 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4839}
4840
4841SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4842 EVT VT = Op.getValueType();
4843 if (VT.isVector())
4844 return LowerVectorFP_TO_INT(Op, DAG);
4845 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4846 RTLIB::Libcall LC;
4847 if (Op.getOpcode() == ISD::FP_TO_SINT)
4848 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4849 Op.getValueType());
4850 else
4851 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4852 Op.getValueType());
4853 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4854 /*isSigned*/ false, SDLoc(Op)).first;
4855 }
4856
4857 return Op;
4858}
4859
4860static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4861 EVT VT = Op.getValueType();
4862 SDLoc dl(Op);
4863
4864 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4865 if (VT.getVectorElementType() == MVT::f32)
4866 return Op;
4867 return DAG.UnrollVectorOp(Op.getNode());
4868 }
4869
4870 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4871, __extension__ __PRETTY_FUNCTION__))
4871 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4871, __extension__ __PRETTY_FUNCTION__))
;
4872 if (VT != MVT::v4f32)
4873 return DAG.UnrollVectorOp(Op.getNode());
4874
4875 unsigned CastOpc;
4876 unsigned Opc;
4877 switch (Op.getOpcode()) {
4878 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 4878)
;
4879 case ISD::SINT_TO_FP:
4880 CastOpc = ISD::SIGN_EXTEND;
4881 Opc = ISD::SINT_TO_FP;
4882 break;
4883 case ISD::UINT_TO_FP:
4884 CastOpc = ISD::ZERO_EXTEND;
4885 Opc = ISD::UINT_TO_FP;
4886 break;
4887 }
4888
4889 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4890 return DAG.getNode(Opc, dl, VT, Op);
4891}
4892
4893SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4894 EVT VT = Op.getValueType();
4895 if (VT.isVector())
4896 return LowerVectorINT_TO_FP(Op, DAG);
4897 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4898 RTLIB::Libcall LC;
4899 if (Op.getOpcode() == ISD::SINT_TO_FP)
4900 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4901 Op.getValueType());
4902 else
4903 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4904 Op.getValueType());
4905 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4906 /*isSigned*/ false, SDLoc(Op)).first;
4907 }
4908
4909 return Op;
4910}
4911
4912SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4913 // Implement fcopysign with a fabs and a conditional fneg.
4914 SDValue Tmp0 = Op.getOperand(0);
4915 SDValue Tmp1 = Op.getOperand(1);
4916 SDLoc dl(Op);
4917 EVT VT = Op.getValueType();
4918 EVT SrcVT = Tmp1.getValueType();
4919 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4920 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4921 bool UseNEON = !InGPR && Subtarget->hasNEON();
4922
4923 if (UseNEON) {
4924 // Use VBSL to copy the sign bit.
4925 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4926 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4927 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4928 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4929 if (VT == MVT::f64)
4930 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4931 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4932 DAG.getConstant(32, dl, MVT::i32));
4933 else /*if (VT == MVT::f32)*/
4934 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4935 if (SrcVT == MVT::f32) {
4936 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4937 if (VT == MVT::f64)
4938 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4939 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4940 DAG.getConstant(32, dl, MVT::i32));
4941 } else if (VT == MVT::f32)
4942 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4943 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4944 DAG.getConstant(32, dl, MVT::i32));
4945 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4946 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4947
4948 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4949 dl, MVT::i32);
4950 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4951 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4952 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4953
4954 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4955 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4956 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4957 if (VT == MVT::f32) {
4958 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4959 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4960 DAG.getConstant(0, dl, MVT::i32));
4961 } else {
4962 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4963 }
4964
4965 return Res;
4966 }
4967
4968 // Bitcast operand 1 to i32.
4969 if (SrcVT == MVT::f64)
4970 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4971 Tmp1).getValue(1);
4972 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4973
4974 // Or in the signbit with integer operations.
4975 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4976 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4977 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4978 if (VT == MVT::f32) {
4979 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4980 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4981 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4982 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4983 }
4984
4985 // f64: Or the high part with signbit and then combine two parts.
4986 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4987 Tmp0);
4988 SDValue Lo = Tmp0.getValue(0);
4989 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4990 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4991 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4992}
4993
4994SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4995 MachineFunction &MF = DAG.getMachineFunction();
4996 MachineFrameInfo &MFI = MF.getFrameInfo();
4997 MFI.setReturnAddressIsTaken(true);
4998
4999 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5000 return SDValue();
5001
5002 EVT VT = Op.getValueType();
5003 SDLoc dl(Op);
5004 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5005 if (Depth) {
5006 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5007 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5008 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5009 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5010 MachinePointerInfo());
5011 }
5012
5013 // Return LR, which contains the return address. Mark it an implicit live-in.
5014 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5015 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5016}
5017
5018SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5019 const ARMBaseRegisterInfo &ARI =
5020 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5021 MachineFunction &MF = DAG.getMachineFunction();
5022 MachineFrameInfo &MFI = MF.getFrameInfo();
5023 MFI.setFrameAddressIsTaken(true);
5024
5025 EVT VT = Op.getValueType();
5026 SDLoc dl(Op); // FIXME probably not meaningful
5027 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5028 unsigned FrameReg = ARI.getFrameRegister(MF);
5029 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5030 while (Depth--)
5031 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5032 MachinePointerInfo());
5033 return FrameAddr;
5034}
5035
5036// FIXME? Maybe this could be a TableGen attribute on some registers and
5037// this table could be generated automatically from RegInfo.
5038unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5039 SelectionDAG &DAG) const {
5040 unsigned Reg = StringSwitch<unsigned>(RegName)
5041 .Case("sp", ARM::SP)
5042 .Default(0);
5043 if (Reg)
5044 return Reg;
5045 report_fatal_error(Twine("Invalid register name \""
5046 + StringRef(RegName) + "\"."));
5047}
5048
5049// Result is 64 bit value so split into two 32 bit values and return as a
5050// pair of values.
5051static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5052 SelectionDAG &DAG) {
5053 SDLoc DL(N);
5054
5055 // This function is only supposed to be called for i64 type destination.
5056 assert(N->getValueType(0) == MVT::i64(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5057, __extension__ __PRETTY_FUNCTION__))
5057 && "ExpandREAD_REGISTER called for non-i64 type result.")(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5057, __extension__ __PRETTY_FUNCTION__))
;
5058
5059 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5060 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5061 N->getOperand(0),
5062 N->getOperand(1));
5063
5064 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5065 Read.getValue(1)));
5066 Results.push_back(Read.getOperand(0));
5067}
5068
5069/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5070/// When \p DstVT, the destination type of \p BC, is on the vector
5071/// register bank and the source of bitcast, \p Op, operates on the same bank,
5072/// it might be possible to combine them, such that everything stays on the
5073/// vector register bank.
5074/// \p return The node that would replace \p BT, if the combine
5075/// is possible.
5076static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5077 SelectionDAG &DAG) {
5078 SDValue Op = BC->getOperand(0);
5079 EVT DstVT = BC->getValueType(0);
5080
5081 // The only vector instruction that can produce a scalar (remember,
5082 // since the bitcast was about to be turned into VMOVDRR, the source
5083 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5084 // Moreover, we can do this combine only if there is one use.
5085 // Finally, if the destination type is not a vector, there is not
5086 // much point on forcing everything on the vector bank.
5087 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5088 !Op.hasOneUse())
5089 return SDValue();
5090
5091 // If the index is not constant, we will introduce an additional
5092 // multiply that will stick.
5093 // Give up in that case.
5094 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5095 if (!Index)
5096 return SDValue();
5097 unsigned DstNumElt = DstVT.getVectorNumElements();
5098
5099 // Compute the new index.
5100 const APInt &APIntIndex = Index->getAPIntValue();
5101 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5102 NewIndex *= APIntIndex;
5103 // Check if the new constant index fits into i32.
5104 if (NewIndex.getBitWidth() > 32)
5105 return SDValue();
5106
5107 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5108 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5109 SDLoc dl(Op);
5110 SDValue ExtractSrc = Op.getOperand(0);
5111 EVT VecVT = EVT::getVectorVT(
5112 *DAG.getContext(), DstVT.getScalarType(),
5113 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5114 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5115 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5116 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5117}
5118
5119/// ExpandBITCAST - If the target supports VFP, this function is called to
5120/// expand a bit convert where either the source or destination type is i64 to
5121/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5122/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5123/// vectors), since the legalizer won't know what to do with that.
5124static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5125 const ARMSubtarget *Subtarget) {
5126 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5127 SDLoc dl(N);
5128 SDValue Op = N->getOperand(0);
5129
5130 // This function is only supposed to be called for i64 types, either as the
5131 // source or destination of the bit convert.
5132 EVT SrcVT = Op.getValueType();
5133 EVT DstVT = N->getValueType(0);
5134 const bool HasFullFP16 = Subtarget->hasFullFP16();
5135
5136 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5137 // FullFP16: half values are passed in S-registers, and we don't
5138 // need any of the bitcast and moves:
5139 //
5140 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5141 // t5: i32 = bitcast t2
5142 // t18: f16 = ARMISD::VMOVhr t5
5143 if (Op.getOpcode() != ISD::CopyFromReg ||
5144 Op.getValueType() != MVT::f32)
5145 return SDValue();
5146
5147 auto Move = N->use_begin();
5148 if (Move->getOpcode() != ARMISD::VMOVhr)
5149 return SDValue();
5150
5151 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5152 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5153 DAG.ReplaceAllUsesWith(*Move, &Copy);
5154 return Copy;
5155 }
5156
5157 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5158 if (!HasFullFP16)
5159 return SDValue();
5160 // SoftFP: read half-precision arguments:
5161 //
5162 // t2: i32,ch = ...
5163 // t7: i16 = truncate t2 <~~~~ Op
5164 // t8: f16 = bitcast t7 <~~~~ N
5165 //
5166 if (Op.getOperand(0).getValueType() == MVT::i32)
5167 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5168 MVT::f16, Op.getOperand(0));
5169
5170 return SDValue();
5171 }
5172
5173 // Half-precision return values
5174 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5175 if (!HasFullFP16)
5176 return SDValue();
5177 //
5178 // t11: f16 = fadd t8, t10
5179 // t12: i16 = bitcast t11 <~~~ SDNode N
5180 // t13: i32 = zero_extend t12
5181 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5182 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5183 //
5184 // transform this into:
5185 //
5186 // t20: i32 = ARMISD::VMOVrh t11
5187 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5188 //
5189 auto ZeroExtend = N->use_begin();
5190 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5191 ZeroExtend->getValueType(0) != MVT::i32)
5192 return SDValue();
5193
5194 auto Copy = ZeroExtend->use_begin();
5195 if (Copy->getOpcode() == ISD::CopyToReg &&
5196 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5197 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5198 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5199 return Cvt;
5200 }
5201 return SDValue();
5202 }
5203
5204 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5205 return SDValue();
5206
5207 // Turn i64->f64 into VMOVDRR.
5208 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5209 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5210 // if we can combine the bitcast with its source.
5211 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5212 return Val;
5213
5214 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5215 DAG.getConstant(0, dl, MVT::i32));
5216 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5217 DAG.getConstant(1, dl, MVT::i32));
5218 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5219 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5220 }
5221
5222 // Turn f64->i64 into VMOVRRD.
5223 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5224 SDValue Cvt;
5225 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5226 SrcVT.getVectorNumElements() > 1)
5227 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5228 DAG.getVTList(MVT::i32, MVT::i32),
5229 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5230 else
5231 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5232 DAG.getVTList(MVT::i32, MVT::i32), Op);
5233 // Merge the pieces into a single i64 value.
5234 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5235 }
5236
5237 return SDValue();
5238}
5239
5240/// getZeroVector - Returns a vector of specified type with all zero elements.
5241/// Zero vectors are used to represent vector negation and in those cases
5242/// will be implemented with the NEON VNEG instruction. However, VNEG does
5243/// not support i64 elements, so sometimes the zero vectors will need to be
5244/// explicitly constructed. Regardless, use a canonical VMOV to create the
5245/// zero vector.
5246static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5247 assert(VT.isVector() && "Expected a vector type")(static_cast <bool> (VT.isVector() && "Expected a vector type"
) ? void (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5247, __extension__ __PRETTY_FUNCTION__))
;
5248 // The canonical modified immediate encoding of a zero vector is....0!
5249 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5250 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5251 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5252 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5253}
5254
5255/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5256/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5257SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5258 SelectionDAG &DAG) const {
5259 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5259, __extension__ __PRETTY_FUNCTION__))
;
5260 EVT VT = Op.getValueType();
5261 unsigned VTBits = VT.getSizeInBits();
5262 SDLoc dl(Op);
5263 SDValue ShOpLo = Op.getOperand(0);
5264 SDValue ShOpHi = Op.getOperand(1);
5265 SDValue ShAmt = Op.getOperand(2);
5266 SDValue ARMcc;
5267 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5268 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5269
5270 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SRA_PARTS ||
Op.getOpcode() == ISD::SRL_PARTS) ? void (0) : __assert_fail
("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5270, __extension__ __PRETTY_FUNCTION__))
;
5271
5272 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5273 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5274 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5275 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5276 DAG.getConstant(VTBits, dl, MVT::i32));
5277 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5278 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5279 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5280 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5281 ISD::SETGE, ARMcc, DAG, dl);
5282 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5283 ARMcc, CCR, CmpLo);
5284
5285 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5286 SDValue HiBigShift = Opc == ISD::SRA
5287 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5288 DAG.getConstant(VTBits - 1, dl, VT))
5289 : DAG.getConstant(0, dl, VT);
5290 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5291 ISD::SETGE, ARMcc, DAG, dl);
5292 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5293 ARMcc, CCR, CmpHi);
5294
5295 SDValue Ops[2] = { Lo, Hi };
5296 return DAG.getMergeValues(Ops, dl);
5297}
5298
5299/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5300/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5301SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5302 SelectionDAG &DAG) const {
5303 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5303, __extension__ __PRETTY_FUNCTION__))
;
5304 EVT VT = Op.getValueType();
5305 unsigned VTBits = VT.getSizeInBits();
5306 SDLoc dl(Op);
5307 SDValue ShOpLo = Op.getOperand(0);
5308 SDValue ShOpHi = Op.getOperand(1);
5309 SDValue ShAmt = Op.getOperand(2);
5310 SDValue ARMcc;
5311 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5312
5313 assert(Op.getOpcode() == ISD::SHL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SHL_PARTS) ?
void (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5313, __extension__ __PRETTY_FUNCTION__))
;
5314 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5315 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5316 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5317 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5318 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5319
5320 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5321 DAG.getConstant(VTBits, dl, MVT::i32));
5322 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5323 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5324 ISD::SETGE, ARMcc, DAG, dl);
5325 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5326 ARMcc, CCR, CmpHi);
5327
5328 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5329 ISD::SETGE, ARMcc, DAG, dl);
5330 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5331 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5332 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5333
5334 SDValue Ops[2] = { Lo, Hi };
5335 return DAG.getMergeValues(Ops, dl);
5336}
5337
5338SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5339 SelectionDAG &DAG) const {
5340 // The rounding mode is in bits 23:22 of the FPSCR.
5341 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5342 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5343 // so that the shift + and get folded into a bitfield extract.
5344 SDLoc dl(Op);
5345 SDValue Ops[] = { DAG.getEntryNode(),
5346 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5347
5348 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5349 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5350 DAG.getConstant(1U << 22, dl, MVT::i32));
5351 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5352 DAG.getConstant(22, dl, MVT::i32));
5353 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5354 DAG.getConstant(3, dl, MVT::i32));
5355}
5356
5357static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5358 const ARMSubtarget *ST) {
5359 SDLoc dl(N);
5360 EVT VT = N->getValueType(0);
5361 if (VT.isVector()) {
5362 assert(ST->hasNEON())(static_cast <bool> (ST->hasNEON()) ? void (0) : __assert_fail
("ST->hasNEON()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5362, __extension__ __PRETTY_FUNCTION__))
;
5363
5364 // Compute the least significant set bit: LSB = X & -X
5365 SDValue X = N->getOperand(0);
5366 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5367 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5368
5369 EVT ElemTy = VT.getVectorElementType();
5370
5371 if (ElemTy == MVT::i8) {
5372 // Compute with: cttz(x) = ctpop(lsb - 1)
5373 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5374 DAG.getTargetConstant(1, dl, ElemTy));
5375 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5376 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5377 }
5378
5379 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5380 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5381 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5382 unsigned NumBits = ElemTy.getSizeInBits();
5383 SDValue WidthMinus1 =
5384 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5385 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5386 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5387 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5388 }
5389
5390 // Compute with: cttz(x) = ctpop(lsb - 1)
5391
5392 // Since we can only compute the number of bits in a byte with vcnt.8, we
5393 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
5394 // and i64.
5395
5396 // Compute LSB - 1.
5397 SDValue Bits;
5398 if (ElemTy == MVT::i64) {
5399 // Load constant 0xffff'ffff'ffff'ffff to register.
5400 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5401 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5402 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5403 } else {
5404 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5405 DAG.getTargetConstant(1, dl, ElemTy));
5406 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5407 }
5408
5409 // Count #bits with vcnt.8.
5410 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5411 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
5412 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
5413
5414 // Gather the #bits with vpaddl (pairwise add.)
5415 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5416 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
5417 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5418 Cnt8);
5419 if (ElemTy == MVT::i16)
5420 return Cnt16;
5421
5422 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
5423 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
5424 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5425 Cnt16);
5426 if (ElemTy == MVT::i32)
5427 return Cnt32;
5428
5429 assert(ElemTy == MVT::i64)(static_cast <bool> (ElemTy == MVT::i64) ? void (0) : __assert_fail
("ElemTy == MVT::i64", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5429, __extension__ __PRETTY_FUNCTION__))
;
5430 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5431 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5432 Cnt32);
5433 return Cnt64;
5434 }
5435
5436 if (!ST->hasV6T2Ops())
5437 return SDValue();
5438
5439 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5440 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5441}
5442
5443/// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
5444/// for each 16-bit element from operand, repeated. The basic idea is to
5445/// leverage vcnt to get the 8-bit counts, gather and add the results.
5446///
5447/// Trace for v4i16:
5448/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5449/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
5450/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
5451/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
5452/// [b0 b1 b2 b3 b4 b5 b6 b7]
5453/// +[b1 b0 b3 b2 b5 b4 b7 b6]
5454/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
5455/// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
5456static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
5457 EVT VT = N->getValueType(0);
5458 SDLoc DL(N);
5459
5460 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5461 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
5462 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
5463 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
5464 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
5465 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
5466}
5467
5468/// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
5469/// bit-count for each 16-bit element from the operand. We need slightly
5470/// different sequencing for v4i16 and v8i16 to stay within NEON's available
5471/// 64/128-bit registers.
5472///
5473/// Trace for v4i16:
5474/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5475/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
5476/// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
5477/// v4i16:Extracted = [k0 k1 k2 k3 ]
5478static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
5479 EVT VT = N->getValueType(0);
5480 SDLoc DL(N);
5481
5482 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
5483 if (VT.is64BitVector()) {
5484 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
5485 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
5486 DAG.getIntPtrConstant(0, DL));
5487 } else {
5488 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
5489 BitCounts, DAG.getIntPtrConstant(0, DL));
5490 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
5491 }
5492}
5493
5494/// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
5495/// bit-count for each 32-bit element from the operand. The idea here is
5496/// to split the vector into 16-bit elements, leverage the 16-bit count
5497/// routine, and then combine the results.
5498///
5499/// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
5500/// input = [v0 v1 ] (vi: 32-bit elements)
5501/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
5502/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
5503/// vrev: N0 = [k1 k0 k3 k2 ]
5504/// [k0 k1 k2 k3 ]
5505/// N1 =+[k1 k0 k3 k2 ]
5506/// [k0 k2 k1 k3 ]
5507/// N2 =+[k1 k3 k0 k2 ]
5508/// [k0 k2 k1 k3 ]
5509/// Extended =+[k1 k3 k0 k2 ]
5510/// [k0 k2 ]
5511/// Extracted=+[k1 k3 ]
5512///
5513static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
5514 EVT VT = N->getValueType(0);
5515 SDLoc DL(N);
5516
5517 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5518
5519 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
5520 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
5521 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
5522 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5523 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
5524
5525 if (VT.is64BitVector()) {
5526 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
5527 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
5528 DAG.getIntPtrConstant(0, DL));
5529 } else {
5530 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
5531 DAG.getIntPtrConstant(0, DL));
5532 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
5533 }
5534}
5535
5536static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5537 const ARMSubtarget *ST) {
5538 EVT VT = N->getValueType(0);
5539
5540 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")(static_cast <bool> (ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? void (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5540, __extension__ __PRETTY_FUNCTION__))
;
5541 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5542 VT == MVT::v4i16 || VT == MVT::v8i16) &&(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
5543 "Unexpected type for custom ctpop lowering")(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
;
5544
5545 if (VT.getVectorElementType() == MVT::i32)
5546 return lowerCTPOP32BitElements(N, DAG);
5547 else
5548 return lowerCTPOP16BitElements(N, DAG);
5549}
5550
5551static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5552 const ARMSubtarget *ST) {
5553 EVT VT = N->getValueType(0);
5554 SDLoc dl(N);
5555
5556 if (!VT.isVector())
5557 return SDValue();
5558
5559 // Lower vector shifts on NEON to use VSHL.
5560 assert(ST->hasNEON() && "unexpected vector shift")(static_cast <bool> (ST->hasNEON() && "unexpected vector shift"
) ? void (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5560, __extension__ __PRETTY_FUNCTION__))
;
5561
5562 // Left shifts translate directly to the vshiftu intrinsic.
5563 if (N->getOpcode() == ISD::SHL)
5564 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5565 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5566 MVT::i32),
5567 N->getOperand(0), N->getOperand(1));
5568
5569 assert((N->getOpcode() == ISD::SRA ||(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5570, __extension__ __PRETTY_FUNCTION__))
5570 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5570, __extension__ __PRETTY_FUNCTION__))
;
5571
5572 // NEON uses the same intrinsics for both left and right shifts. For
5573 // right shifts, the shift amounts are negative, so negate the vector of
5574 // shift amounts.
5575 EVT ShiftVT = N->getOperand(1).getValueType();
5576 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5577 getZeroVector(ShiftVT, DAG, dl),
5578 N->getOperand(1));
5579 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5580 Intrinsic::arm_neon_vshifts :
5581 Intrinsic::arm_neon_vshiftu);
5582 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5583 DAG.getConstant(vshiftInt, dl, MVT::i32),
5584 N->getOperand(0), NegatedCount);
5585}
5586
5587static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5588 const ARMSubtarget *ST) {
5589 EVT VT = N->getValueType(0);
5590 SDLoc dl(N);
5591
5592 // We can get here for a node like i32 = ISD::SHL i32, i64
5593 if (VT != MVT::i64)
5594 return SDValue();
5595
5596 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5597, __extension__ __PRETTY_FUNCTION__))
5597 "Unknown shift to lower!")(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5597, __extension__ __PRETTY_FUNCTION__))
;
5598
5599 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5600 if (!isOneConstant(N->getOperand(1)))
5601 return SDValue();
5602
5603 // If we are in thumb mode, we don't have RRX.
5604 if (ST->isThumb1Only()) return SDValue();
5605
5606 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5607 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5608 DAG.getConstant(0, dl, MVT::i32));
5609 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5610 DAG.getConstant(1, dl, MVT::i32));
5611
5612 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5613 // captures the result into a carry flag.
5614 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5615 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5616
5617 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5618 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5619
5620 // Merge the pieces into a single i64 value.
5621 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5622}
5623
5624static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5625 SDValue TmpOp0, TmpOp1;
5626 bool Invert = false;
5627 bool Swap = false;
5628 unsigned Opc = 0;
5629
5630 SDValue Op0 = Op.getOperand(0);
5631 SDValue Op1 = Op.getOperand(1);
5632 SDValue CC = Op.getOperand(2);
5633 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5634 EVT VT = Op.getValueType();
5635 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5636 SDLoc dl(Op);
5637
5638 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5639 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5640 // Special-case integer 64-bit equality comparisons. They aren't legal,
5641 // but they can be lowered with a few vector instructions.
5642 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5643 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5644 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5645 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5646 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5647 DAG.getCondCode(ISD::SETEQ));
5648 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5649 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5650 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5651 if (SetCCOpcode == ISD::SETNE)
5652 Merged = DAG.getNOT(dl, Merged, CmpVT);
5653 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5654 return Merged;
5655 }
5656
5657 if (CmpVT.getVectorElementType() == MVT::i64)
5658 // 64-bit comparisons are not legal in general.
5659 return SDValue();
5660
5661 if (Op1.getValueType().isFloatingPoint()) {
5662 switch (SetCCOpcode) {
5663 default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5663)
;
5664 case ISD::SETUNE:
5665 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5666 case ISD::SETOEQ:
5667 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5668 case ISD::SETOLT:
5669 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5670 case ISD::SETOGT:
5671 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5672 case ISD::SETOLE:
5673 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5674 case ISD::SETOGE:
5675 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5676 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5677 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5678 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5679 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5680 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5681 case ISD::SETONE:
5682 // Expand this to (OLT | OGT).
5683 TmpOp0 = Op0;
5684 TmpOp1 = Op1;
5685 Opc = ISD::OR;
5686 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5687 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5688 break;
5689 case ISD::SETUO:
5690 Invert = true;
5691 LLVM_FALLTHROUGH[[clang::fallthrough]];
5692 case ISD::SETO:
5693 // Expand this to (OLT | OGE).
5694 TmpOp0 = Op0;
5695 TmpOp1 = Op1;
5696 Opc = ISD::OR;
5697 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5698 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5699 break;
5700 }
5701 } else {
5702 // Integer comparisons.
5703 switch (SetCCOpcode) {
5704 default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5704)
;
5705 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5706 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5707 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5708 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5709 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5710 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5711 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5712 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5713 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5714 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5715 }
5716
5717 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5718 if (Opc == ARMISD::VCEQ) {
5719 SDValue AndOp;
5720 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5721 AndOp = Op0;
5722 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5723 AndOp = Op1;
5724
5725 // Ignore bitconvert.
5726 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5727 AndOp = AndOp.getOperand(0);
5728
5729 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5730 Opc = ARMISD::VTST;
5731 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5732 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5733 Invert = !Invert;
5734 }
5735 }
5736 }
5737
5738 if (Swap)
5739 std::swap(Op0, Op1);
5740
5741 // If one of the operands is a constant vector zero, attempt to fold the
5742 // comparison to a specialized compare-against-zero form.
5743 SDValue SingleOp;
5744 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5745 SingleOp = Op0;
5746 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5747 if (Opc == ARMISD::VCGE)
5748 Opc = ARMISD::VCLEZ;
5749 else if (Opc == ARMISD::VCGT)
5750 Opc = ARMISD::VCLTZ;
5751 SingleOp = Op1;
5752 }
5753
5754 SDValue Result;
5755 if (SingleOp.getNode()) {
5756 switch (Opc) {
5757 case ARMISD::VCEQ:
5758 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5759 case ARMISD::VCGE:
5760 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5761 case ARMISD::VCLEZ:
5762 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5763 case ARMISD::VCGT:
5764 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5765 case ARMISD::VCLTZ:
5766 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5767 default:
5768 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5769 }
5770 } else {
5771 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5772 }
5773
5774 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5775
5776 if (Invert)
5777 Result = DAG.getNOT(dl, Result, VT);
5778
5779 return Result;
5780}
5781
5782static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
5783 SDValue LHS = Op.getOperand(0);
5784 SDValue RHS = Op.getOperand(1);
5785 SDValue Carry = Op.getOperand(2);
5786 SDValue Cond = Op.getOperand(3);
5787 SDLoc DL(Op);
5788
5789 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.")(static_cast <bool> (LHS.getSimpleValueType().isInteger
() && "SETCCE is integer only.") ? void (0) : __assert_fail
("LHS.getSimpleValueType().isInteger() && \"SETCCE is integer only.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5789, __extension__ __PRETTY_FUNCTION__))
;
5790
5791 assert(Carry.getOpcode() != ISD::CARRY_FALSE)(static_cast <bool> (Carry.getOpcode() != ISD::CARRY_FALSE
) ? void (0) : __assert_fail ("Carry.getOpcode() != ISD::CARRY_FALSE"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5791, __extension__ __PRETTY_FUNCTION__))
;
5792 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5793 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5794
5795 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5796 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5797 SDValue ARMcc = DAG.getConstant(
5798 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5799 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5800 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5801 Cmp.getValue(1), SDValue());
5802 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5803 CCR, Chain.getValue(1));
5804}
5805
5806/// isNEONModifiedImm - Check if the specified splat value corresponds to a
5807/// valid vector constant for a NEON instruction with a "modified immediate"
5808/// operand (e.g., VMOV). If so, return the encoded value.
5809static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5810 unsigned SplatBitSize, SelectionDAG &DAG,
5811 const SDLoc &dl, EVT &VT, bool is128Bits,
5812 NEONModImmType type) {
5813 unsigned OpCmode, Imm;
5814
5815 // SplatBitSize is set to the smallest size that splats the vector, so a
5816 // zero vector will always have SplatBitSize == 8. However, NEON modified
5817 // immediate instructions others than VMOV do not support the 8-bit encoding
5818 // of a zero vector, and the default encoding of zero is supposed to be the
5819 // 32-bit version.
5820 if (SplatBits == 0)
5821 SplatBitSize = 32;
5822
5823 switch (SplatBitSize) {
5824 case 8:
5825 if (type != VMOVModImm)
5826 return SDValue();
5827 // Any 1-byte value is OK. Op=0, Cmode=1110.
5828 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(static_cast <bool> ((SplatBits & ~0xff) == 0 &&
"one byte splat value is too big") ? void (0) : __assert_fail
("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5828, __extension__ __PRETTY_FUNCTION__))
;
5829 OpCmode = 0xe;
5830 Imm = SplatBits;
5831 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5832 break;
5833
5834 case 16:
5835 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5836 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5837 if ((SplatBits & ~0xff) == 0) {
5838 // Value = 0x00nn: Op=x, Cmode=100x.
5839 OpCmode = 0x8;
5840 Imm = SplatBits;
5841 break;
5842 }
5843 if ((SplatBits & ~0xff00) == 0) {
5844 // Value = 0xnn00: Op=x, Cmode=101x.
5845 OpCmode = 0xa;
5846 Imm = SplatBits >> 8;
5847 break;
5848 }
5849 return SDValue();
5850
5851 case 32:
5852 // NEON's 32-bit VMOV supports splat values where:
5853 // * only one byte is nonzero, or
5854 // * the least significant byte is 0xff and the second byte is nonzero, or
5855 // * the least significant 2 bytes are 0xff and the third is nonzero.
5856 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5857 if ((SplatBits & ~0xff) == 0) {
5858 // Value = 0x000000nn: Op=x, Cmode=000x.
5859 OpCmode = 0;
5860 Imm = SplatBits;
5861 break;
5862 }
5863 if ((SplatBits & ~0xff00) == 0) {
5864 // Value = 0x0000nn00: Op=x, Cmode=001x.
5865 OpCmode = 0x2;
5866 Imm = SplatBits >> 8;
5867 break;
5868 }
5869 if ((SplatBits & ~0xff0000) == 0) {
5870 // Value = 0x00nn0000: Op=x, Cmode=010x.
5871 OpCmode = 0x4;
5872 Imm = SplatBits >> 16;
5873 break;
5874 }
5875 if ((SplatBits & ~0xff000000) == 0) {
5876 // Value = 0xnn000000: Op=x, Cmode=011x.
5877 OpCmode = 0x6;
5878 Imm = SplatBits >> 24;
5879 break;
5880 }
5881
5882 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5883 if (type == OtherModImm) return SDValue();
5884
5885 if ((SplatBits & ~0xffff) == 0 &&
5886 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5887 // Value = 0x0000nnff: Op=x, Cmode=1100.
5888 OpCmode = 0xc;
5889 Imm = SplatBits >> 8;
5890 break;
5891 }
5892
5893 if ((SplatBits & ~0xffffff) == 0 &&
5894 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5895 // Value = 0x00nnffff: Op=x, Cmode=1101.
5896 OpCmode = 0xd;
5897 Imm = SplatBits >> 16;
5898 break;
5899 }
5900
5901 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5902 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5903 // VMOV.I32. A (very) minor optimization would be to replicate the value
5904 // and fall through here to test for a valid 64-bit splat. But, then the
5905 // caller would also need to check and handle the change in size.
5906 return SDValue();
5907
5908 case 64: {
5909 if (type != VMOVModImm)
5910 return SDValue();
5911 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5912 uint64_t BitMask = 0xff;
5913 uint64_t Val = 0;
5914 unsigned ImmMask = 1;
5915 Imm = 0;
5916 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5917 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5918 Val |= BitMask;
5919 Imm |= ImmMask;
5920 } else if ((SplatBits & BitMask) != 0) {
5921 return SDValue();
5922 }
5923 BitMask <<= 8;
5924 ImmMask <<= 1;
5925 }
5926
5927 if (DAG.getDataLayout().isBigEndian())
5928 // swap higher and lower 32 bit word
5929 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5930
5931 // Op=1, Cmode=1110.
5932 OpCmode = 0x1e;
5933 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5934 break;
5935 }
5936
5937 default:
5938 llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5938)
;
5939 }
5940
5941 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5942 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5943}
5944
5945SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5946 const ARMSubtarget *ST) const {
5947 EVT VT = Op.getValueType();
5948 bool IsDouble = (VT == MVT::f64);
5949 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5950 const APFloat &FPVal = CFP->getValueAPF();
5951
5952 // Prevent floating-point constants from using literal loads
5953 // when execute-only is enabled.
5954 if (ST->genExecuteOnly()) {
5955 // If we can represent the constant as an immediate, don't lower it
5956 if (isFPImmLegal(FPVal, VT))
5957 return Op;
5958 // Otherwise, construct as integer, and move to float register
5959 APInt INTVal = FPVal.bitcastToAPInt();
5960 SDLoc DL(CFP);
5961 switch (VT.getSimpleVT().SimpleTy) {
5962 default:
5963 llvm_unreachable("Unknown floating point type!")::llvm::llvm_unreachable_internal("Unknown floating point type!"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/ARM/ARMISelLowering.cpp"
, 5963)
;
5964 break;
5965 case MVT::f64: {
5966 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);