Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 2515, column 20
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-11-29-190409-37574-1 -x c++ /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallPtrSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringExtras.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Triple.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/RuntimeLibcalls.h"
56#include "llvm/CodeGen/SelectionDAG.h"
57#include "llvm/CodeGen/SelectionDAGNodes.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/IR/Attributes.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/Constants.h"
68#include "llvm/IR/DataLayout.h"
69#include "llvm/IR/DebugLoc.h"
70#include "llvm/IR/DerivedTypes.h"
71#include "llvm/IR/Function.h"
72#include "llvm/IR/GlobalAlias.h"
73#include "llvm/IR/GlobalValue.h"
74#include "llvm/IR/GlobalVariable.h"
75#include "llvm/IR/IRBuilder.h"
76#include "llvm/IR/InlineAsm.h"
77#include "llvm/IR/Instruction.h"
78#include "llvm/IR/Instructions.h"
79#include "llvm/IR/IntrinsicInst.h"
80#include "llvm/IR/Intrinsics.h"
81#include "llvm/IR/IntrinsicsARM.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/PatternMatch.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MachineValueType.h"
101#include "llvm/Support/MathExtras.h"
102#include "llvm/Support/raw_ostream.h"
103#include "llvm/Target/TargetMachine.h"
104#include "llvm/Target/TargetOptions.h"
105#include <algorithm>
106#include <cassert>
107#include <cstdint>
108#include <cstdlib>
109#include <iterator>
110#include <limits>
111#include <string>
112#include <tuple>
113#include <utility>
114#include <vector>
115
116using namespace llvm;
117using namespace llvm::PatternMatch;
118
119#define DEBUG_TYPE"arm-isel" "arm-isel"
120
121STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
122STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
123STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
124STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
125 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
126
127static cl::opt<bool>
128ARMInterworking("arm-interworking", cl::Hidden,
129 cl::desc("Enable / disable ARM interworking (for debugging only)"),
130 cl::init(true));
131
132static cl::opt<bool> EnableConstpoolPromotion(
133 "arm-promote-constant", cl::Hidden,
134 cl::desc("Enable / disable promotion of unnamed_addr constants into "
135 "constant pools"),
136 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
137static cl::opt<unsigned> ConstpoolPromotionMaxSize(
138 "arm-promote-constant-max-size", cl::Hidden,
139 cl::desc("Maximum size of constant to promote into a constant pool"),
140 cl::init(64));
141static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
142 "arm-promote-constant-max-total", cl::Hidden,
143 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
144 cl::init(128));
145
146cl::opt<unsigned>
147MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
148 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
149 cl::init(2));
150
151// The APCS parameter registers.
152static const MCPhysReg GPRArgRegs[] = {
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
154};
155
156void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
157 MVT PromotedBitwiseVT) {
158 if (VT != PromotedLdStVT) {
159 setOperationAction(ISD::LOAD, VT, Promote);
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
161
162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
164 }
165
166 MVT ElemTy = VT.getVectorElementType();
167 if (ElemTy != MVT::f64)
168 setOperationAction(ISD::SETCC, VT, Custom);
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
171 if (ElemTy == MVT::i32) {
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
175 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
176 } else {
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
180 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 }
182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
186 setOperationAction(ISD::SELECT, VT, Expand);
187 setOperationAction(ISD::SELECT_CC, VT, Expand);
188 setOperationAction(ISD::VSELECT, VT, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 if (VT.isInteger()) {
191 setOperationAction(ISD::SHL, VT, Custom);
192 setOperationAction(ISD::SRA, VT, Custom);
193 setOperationAction(ISD::SRL, VT, Custom);
194 }
195
196 // Promote all bit-wise operations.
197 if (VT.isInteger() && VT != PromotedBitwiseVT) {
198 setOperationAction(ISD::AND, VT, Promote);
199 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
200 setOperationAction(ISD::OR, VT, Promote);
201 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
202 setOperationAction(ISD::XOR, VT, Promote);
203 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
204 }
205
206 // Neon does not support vector divide/remainder operations.
207 setOperationAction(ISD::SDIV, VT, Expand);
208 setOperationAction(ISD::UDIV, VT, Expand);
209 setOperationAction(ISD::FDIV, VT, Expand);
210 setOperationAction(ISD::SREM, VT, Expand);
211 setOperationAction(ISD::UREM, VT, Expand);
212 setOperationAction(ISD::FREM, VT, Expand);
213 setOperationAction(ISD::SDIVREM, VT, Expand);
214 setOperationAction(ISD::UDIVREM, VT, Expand);
215
216 if (!VT.isFloatingPoint() &&
217 VT != MVT::v2i64 && VT != MVT::v1i64)
218 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
219 setOperationAction(Opcode, VT, Legal);
220 if (!VT.isFloatingPoint())
221 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
222 setOperationAction(Opcode, VT, Legal);
223}
224
225void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
226 addRegisterClass(VT, &ARM::DPRRegClass);
227 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
228}
229
230void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
231 addRegisterClass(VT, &ARM::DPairRegClass);
232 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
233}
234
235void ARMTargetLowering::setAllExpand(MVT VT) {
236 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
237 setOperationAction(Opc, VT, Expand);
238
239 // We support these really simple operations even on types where all
240 // the actual arithmetic has to be broken down into simpler
241 // operations or turned into library calls.
242 setOperationAction(ISD::BITCAST, VT, Legal);
243 setOperationAction(ISD::LOAD, VT, Legal);
244 setOperationAction(ISD::STORE, VT, Legal);
245 setOperationAction(ISD::UNDEF, VT, Legal);
246}
247
248void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
249 LegalizeAction Action) {
250 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
251 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
252 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
253}
254
255void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
256 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
257
258 for (auto VT : IntTypes) {
259 addRegisterClass(VT, &ARM::MQPRRegClass);
260 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
261 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
262 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
263 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
264 setOperationAction(ISD::SHL, VT, Custom);
265 setOperationAction(ISD::SRA, VT, Custom);
266 setOperationAction(ISD::SRL, VT, Custom);
267 setOperationAction(ISD::SMIN, VT, Legal);
268 setOperationAction(ISD::SMAX, VT, Legal);
269 setOperationAction(ISD::UMIN, VT, Legal);
270 setOperationAction(ISD::UMAX, VT, Legal);
271 setOperationAction(ISD::ABS, VT, Legal);
272 setOperationAction(ISD::SETCC, VT, Custom);
273 setOperationAction(ISD::MLOAD, VT, Custom);
274 setOperationAction(ISD::MSTORE, VT, Legal);
275 setOperationAction(ISD::CTLZ, VT, Legal);
276 setOperationAction(ISD::CTTZ, VT, Custom);
277 setOperationAction(ISD::BITREVERSE, VT, Legal);
278 setOperationAction(ISD::BSWAP, VT, Legal);
279 setOperationAction(ISD::SADDSAT, VT, Legal);
280 setOperationAction(ISD::UADDSAT, VT, Legal);
281 setOperationAction(ISD::SSUBSAT, VT, Legal);
282 setOperationAction(ISD::USUBSAT, VT, Legal);
283
284 // No native support for these.
285 setOperationAction(ISD::UDIV, VT, Expand);
286 setOperationAction(ISD::SDIV, VT, Expand);
287 setOperationAction(ISD::UREM, VT, Expand);
288 setOperationAction(ISD::SREM, VT, Expand);
289 setOperationAction(ISD::UDIVREM, VT, Expand);
290 setOperationAction(ISD::SDIVREM, VT, Expand);
291 setOperationAction(ISD::CTPOP, VT, Expand);
292
293 // Vector reductions
294 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
295 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
296 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
299 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
300 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
301 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
302 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
303
304 if (!HasMVEFP) {
305 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
306 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 }
310
311 // Pre and Post inc are supported on loads and stores
312 for (unsigned im = (unsigned)ISD::PRE_INC;
313 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
314 setIndexedLoadAction(im, VT, Legal);
315 setIndexedStoreAction(im, VT, Legal);
316 setIndexedMaskedLoadAction(im, VT, Legal);
317 setIndexedMaskedStoreAction(im, VT, Legal);
318 }
319 }
320
321 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
322 for (auto VT : FloatTypes) {
323 addRegisterClass(VT, &ARM::MQPRRegClass);
324 if (!HasMVEFP)
325 setAllExpand(VT);
326
327 // These are legal or custom whether we have MVE.fp or not
328 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
329 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
330 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
331 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
332 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
333 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
335 setOperationAction(ISD::SETCC, VT, Custom);
336 setOperationAction(ISD::MLOAD, VT, Custom);
337 setOperationAction(ISD::MSTORE, VT, Legal);
338
339 // Pre and Post inc are supported on loads and stores
340 for (unsigned im = (unsigned)ISD::PRE_INC;
341 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
342 setIndexedLoadAction(im, VT, Legal);
343 setIndexedStoreAction(im, VT, Legal);
344 setIndexedMaskedLoadAction(im, VT, Legal);
345 setIndexedMaskedStoreAction(im, VT, Legal);
346 }
347
348 if (HasMVEFP) {
349 setOperationAction(ISD::FMINNUM, VT, Legal);
350 setOperationAction(ISD::FMAXNUM, VT, Legal);
351 setOperationAction(ISD::FROUND, VT, Legal);
352 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
353 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
354 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
355 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
356
357 // No native support for these.
358 setOperationAction(ISD::FDIV, VT, Expand);
359 setOperationAction(ISD::FREM, VT, Expand);
360 setOperationAction(ISD::FSQRT, VT, Expand);
361 setOperationAction(ISD::FSIN, VT, Expand);
362 setOperationAction(ISD::FCOS, VT, Expand);
363 setOperationAction(ISD::FPOW, VT, Expand);
364 setOperationAction(ISD::FLOG, VT, Expand);
365 setOperationAction(ISD::FLOG2, VT, Expand);
366 setOperationAction(ISD::FLOG10, VT, Expand);
367 setOperationAction(ISD::FEXP, VT, Expand);
368 setOperationAction(ISD::FEXP2, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, VT, Expand);
370 }
371 }
372
373 // Custom Expand smaller than legal vector reductions to prevent false zero
374 // items being added.
375 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
376 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
377 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
378 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
383
384 // We 'support' these types up to bitcast/load/store level, regardless of
385 // MVE integer-only / float support. Only doing FP data processing on the FP
386 // vector types is inhibited at integer-only level.
387 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
388 for (auto VT : LongTypes) {
389 addRegisterClass(VT, &ARM::MQPRRegClass);
390 setAllExpand(VT);
391 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
392 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
393 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
394 }
395 // We can do bitwise operations on v2i64 vectors
396 setOperationAction(ISD::AND, MVT::v2i64, Legal);
397 setOperationAction(ISD::OR, MVT::v2i64, Legal);
398 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
399
400 // It is legal to extload from v4i8 to v4i16 or v4i32.
401 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
402 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
403 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
404
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
410 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
411
412 // Some truncating stores are legal too.
413 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
414 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
415 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
416
417 // Pre and Post inc on these are legal, given the correct extends
418 for (unsigned im = (unsigned)ISD::PRE_INC;
419 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
420 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
421 setIndexedLoadAction(im, VT, Legal);
422 setIndexedStoreAction(im, VT, Legal);
423 setIndexedMaskedLoadAction(im, VT, Legal);
424 setIndexedMaskedStoreAction(im, VT, Legal);
425 }
426 }
427
428 // Predicate types
429 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
430 for (auto VT : pTypes) {
431 addRegisterClass(VT, &ARM::VCCRRegClass);
432 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
433 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
434 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
435 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
436 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
437 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
438 setOperationAction(ISD::SETCC, VT, Custom);
439 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
440 setOperationAction(ISD::LOAD, VT, Custom);
441 setOperationAction(ISD::STORE, VT, Custom);
442 }
443}
444
445ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
446 const ARMSubtarget &STI)
447 : TargetLowering(TM), Subtarget(&STI) {
448 RegInfo = Subtarget->getRegisterInfo();
449 Itins = Subtarget->getInstrItineraryData();
450
451 setBooleanContents(ZeroOrOneBooleanContent);
452 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
453
454 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
455 !Subtarget->isTargetWatchOS()) {
456 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
457 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
458 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
459 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
460 : CallingConv::ARM_AAPCS);
461 }
462
463 if (Subtarget->isTargetMachO()) {
464 // Uses VFP for Thumb libfuncs if available.
465 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
466 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
467 static const struct {
468 const RTLIB::Libcall Op;
469 const char * const Name;
470 const ISD::CondCode Cond;
471 } LibraryCalls[] = {
472 // Single-precision floating-point arithmetic.
473 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
474 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
475 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
476 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
477
478 // Double-precision floating-point arithmetic.
479 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
480 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
481 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
482 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
483
484 // Single-precision comparisons.
485 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
486 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
487 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
488 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
489 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
490 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
491 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
492
493 // Double-precision comparisons.
494 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
495 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
496 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
497 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
498 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
499 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
500 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
501
502 // Floating-point to integer conversions.
503 // i64 conversions are done via library routines even when generating VFP
504 // instructions, so use the same ones.
505 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
506 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
507 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
508 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
509
510 // Conversions between floating types.
511 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
512 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
513
514 // Integer to floating-point conversions.
515 // i64 conversions are done via library routines even when generating VFP
516 // instructions, so use the same ones.
517 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
518 // e.g., __floatunsidf vs. __floatunssidfvfp.
519 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
520 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
521 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
522 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
523 };
524
525 for (const auto &LC : LibraryCalls) {
526 setLibcallName(LC.Op, LC.Name);
527 if (LC.Cond != ISD::SETCC_INVALID)
528 setCmpLibcallCC(LC.Op, LC.Cond);
529 }
530 }
531 }
532
533 // These libcalls are not available in 32-bit.
534 setLibcallName(RTLIB::SHL_I128, nullptr);
535 setLibcallName(RTLIB::SRL_I128, nullptr);
536 setLibcallName(RTLIB::SRA_I128, nullptr);
537
538 // RTLIB
539 if (Subtarget->isAAPCS_ABI() &&
540 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
541 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
542 static const struct {
543 const RTLIB::Libcall Op;
544 const char * const Name;
545 const CallingConv::ID CC;
546 const ISD::CondCode Cond;
547 } LibraryCalls[] = {
548 // Double-precision floating-point arithmetic helper functions
549 // RTABI chapter 4.1.2, Table 2
550 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
551 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
552 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
553 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
554
555 // Double-precision floating-point comparison helper functions
556 // RTABI chapter 4.1.2, Table 3
557 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
558 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
559 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
560 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
561 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
562 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
563 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
564
565 // Single-precision floating-point arithmetic helper functions
566 // RTABI chapter 4.1.2, Table 4
567 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
568 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
569 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
570 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
571
572 // Single-precision floating-point comparison helper functions
573 // RTABI chapter 4.1.2, Table 5
574 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
575 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
576 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
577 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
578 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
579 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
580 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
581
582 // Floating-point to integer conversions.
583 // RTABI chapter 4.1.2, Table 6
584 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
585 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
586 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
587 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
588 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
589 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
590 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592
593 // Conversions between floating types.
594 // RTABI chapter 4.1.2, Table 7
595 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
596 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598
599 // Integer to floating-point conversions.
600 // RTABI chapter 4.1.2, Table 8
601 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
604 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
605 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
606 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
607 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609
610 // Long long helper functions
611 // RTABI chapter 4.2, Table 9
612 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
613 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
614 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616
617 // Integer division functions
618 // RTABI chapter 4.3.1
619 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
620 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
621 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
622 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
623 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
624 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 };
628
629 for (const auto &LC : LibraryCalls) {
630 setLibcallName(LC.Op, LC.Name);
631 setLibcallCallingConv(LC.Op, LC.CC);
632 if (LC.Cond != ISD::SETCC_INVALID)
633 setCmpLibcallCC(LC.Op, LC.Cond);
634 }
635
636 // EABI dependent RTLIB
637 if (TM.Options.EABIVersion == EABI::EABI4 ||
638 TM.Options.EABIVersion == EABI::EABI5) {
639 static const struct {
640 const RTLIB::Libcall Op;
641 const char *const Name;
642 const CallingConv::ID CC;
643 const ISD::CondCode Cond;
644 } MemOpsLibraryCalls[] = {
645 // Memory operations
646 // RTABI chapter 4.3.4
647 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
650 };
651
652 for (const auto &LC : MemOpsLibraryCalls) {
653 setLibcallName(LC.Op, LC.Name);
654 setLibcallCallingConv(LC.Op, LC.CC);
655 if (LC.Cond != ISD::SETCC_INVALID)
656 setCmpLibcallCC(LC.Op, LC.Cond);
657 }
658 }
659 }
660
661 if (Subtarget->isTargetWindows()) {
662 static const struct {
663 const RTLIB::Libcall Op;
664 const char * const Name;
665 const CallingConv::ID CC;
666 } LibraryCalls[] = {
667 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
668 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
669 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
670 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
671 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
672 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
673 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
674 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
675 };
676
677 for (const auto &LC : LibraryCalls) {
678 setLibcallName(LC.Op, LC.Name);
679 setLibcallCallingConv(LC.Op, LC.CC);
680 }
681 }
682
683 // Use divmod compiler-rt calls for iOS 5.0 and later.
684 if (Subtarget->isTargetMachO() &&
685 !(Subtarget->isTargetIOS() &&
686 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
687 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
688 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
689 }
690
691 // The half <-> float conversion functions are always soft-float on
692 // non-watchos platforms, but are needed for some targets which use a
693 // hard-float calling convention by default.
694 if (!Subtarget->isTargetWatchABI()) {
695 if (Subtarget->isAAPCS_ABI()) {
696 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
697 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
698 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
699 } else {
700 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
701 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
702 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
703 }
704 }
705
706 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
707 // a __gnu_ prefix (which is the default).
708 if (Subtarget->isTargetAEABI()) {
709 static const struct {
710 const RTLIB::Libcall Op;
711 const char * const Name;
712 const CallingConv::ID CC;
713 } LibraryCalls[] = {
714 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
715 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
716 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
717 };
718
719 for (const auto &LC : LibraryCalls) {
720 setLibcallName(LC.Op, LC.Name);
721 setLibcallCallingConv(LC.Op, LC.CC);
722 }
723 }
724
725 if (Subtarget->isThumb1Only())
726 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
727 else
728 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
729
730 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
731 Subtarget->hasFPRegs()) {
732 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
733 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
734 if (!Subtarget->hasVFP2Base())
735 setAllExpand(MVT::f32);
736 if (!Subtarget->hasFP64())
737 setAllExpand(MVT::f64);
738 }
739
740 if (Subtarget->hasFullFP16()) {
741 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
742 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
743 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
744
745 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
746 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
747 }
748
749 if (Subtarget->hasBF16()) {
750 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
751 setAllExpand(MVT::bf16);
752 if (!Subtarget->hasFullFP16())
753 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
754 }
755
756 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
757 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
758 setTruncStoreAction(VT, InnerVT, Expand);
759 addAllExtLoads(VT, InnerVT, Expand);
760 }
761
762 setOperationAction(ISD::MULHS, VT, Expand);
763 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
764 setOperationAction(ISD::MULHU, VT, Expand);
765 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
766
767 setOperationAction(ISD::BSWAP, VT, Expand);
768 }
769
770 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
771 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
772
773 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
774 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
775
776 if (Subtarget->hasMVEIntegerOps())
777 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
778
779 // Combine low-overhead loop intrinsics so that we can lower i1 types.
780 if (Subtarget->hasLOB()) {
781 setTargetDAGCombine(ISD::BRCOND);
782 setTargetDAGCombine(ISD::BR_CC);
783 }
784
785 if (Subtarget->hasNEON()) {
786 addDRTypeForNEON(MVT::v2f32);
787 addDRTypeForNEON(MVT::v8i8);
788 addDRTypeForNEON(MVT::v4i16);
789 addDRTypeForNEON(MVT::v2i32);
790 addDRTypeForNEON(MVT::v1i64);
791
792 addQRTypeForNEON(MVT::v4f32);
793 addQRTypeForNEON(MVT::v2f64);
794 addQRTypeForNEON(MVT::v16i8);
795 addQRTypeForNEON(MVT::v8i16);
796 addQRTypeForNEON(MVT::v4i32);
797 addQRTypeForNEON(MVT::v2i64);
798
799 if (Subtarget->hasFullFP16()) {
800 addQRTypeForNEON(MVT::v8f16);
801 addDRTypeForNEON(MVT::v4f16);
802 }
803
804 if (Subtarget->hasBF16()) {
805 addQRTypeForNEON(MVT::v8bf16);
806 addDRTypeForNEON(MVT::v4bf16);
807 }
808 }
809
810 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
811 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
812 // none of Neon, MVE or VFP supports any arithmetic operations on it.
813 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
814 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
815 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
816 // FIXME: Code duplication: FDIV and FREM are expanded always, see
817 // ARMTargetLowering::addTypeForNEON method for details.
818 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
819 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
820 // FIXME: Create unittest.
821 // In another words, find a way when "copysign" appears in DAG with vector
822 // operands.
823 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
824 // FIXME: Code duplication: SETCC has custom operation action, see
825 // ARMTargetLowering::addTypeForNEON method for details.
826 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
827 // FIXME: Create unittest for FNEG and for FABS.
828 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
829 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
831 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
832 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
833 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
834 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
835 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
836 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
837 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
838 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
839 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
840 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
841 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
842 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
843 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
844 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
845 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
846 }
847
848 if (Subtarget->hasNEON()) {
849 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
850 // supported for v4f32.
851 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
852 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
853 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
854 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
855 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
856 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
857 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
858 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
859 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
860 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
861 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
862 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
863 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
864 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
865
866 // Mark v2f32 intrinsics.
867 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
868 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
869 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
870 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
871 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
872 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
873 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
874 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
875 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
876 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
877 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
878 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
879 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
880 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
881
882 // Neon does not support some operations on v1i64 and v2i64 types.
883 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
884 // Custom handling for some quad-vector types to detect VMULL.
885 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
886 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
887 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
888 // Custom handling for some vector types to avoid expensive expansions
889 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
890 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
891 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
892 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
893 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
894 // a destination type that is wider than the source, and nor does
895 // it have a FP_TO_[SU]INT instruction with a narrower destination than
896 // source.
897 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
898 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
899 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
900 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
901 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
902 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
903 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
904 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
905
906 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
907 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
908
909 // NEON does not have single instruction CTPOP for vectors with element
910 // types wider than 8-bits. However, custom lowering can leverage the
911 // v8i8/v16i8 vcnt instruction.
912 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
913 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
914 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
915 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
916 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
917 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
918
919 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
920 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
921
922 // NEON does not have single instruction CTTZ for vectors.
923 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
924 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
925 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
926 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
927
928 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
929 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
930 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
931 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
932
933 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
934 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
935 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
936 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
937
938 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
939 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
940 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
941 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
942
943 // NEON only has FMA instructions as of VFP4.
944 if (!Subtarget->hasVFP4Base()) {
945 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
946 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
947 }
948
949 setTargetDAGCombine(ISD::SHL);
950 setTargetDAGCombine(ISD::SRL);
951 setTargetDAGCombine(ISD::SRA);
952 setTargetDAGCombine(ISD::FP_TO_SINT);
953 setTargetDAGCombine(ISD::FP_TO_UINT);
954 setTargetDAGCombine(ISD::FDIV);
955 setTargetDAGCombine(ISD::LOAD);
956
957 // It is legal to extload from v4i8 to v4i16 or v4i32.
958 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
959 MVT::v2i32}) {
960 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
961 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
962 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
964 }
965 }
966 }
967
968 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
969 setTargetDAGCombine(ISD::BUILD_VECTOR);
970 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
971 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
972 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
973 setTargetDAGCombine(ISD::STORE);
974 setTargetDAGCombine(ISD::SIGN_EXTEND);
975 setTargetDAGCombine(ISD::ZERO_EXTEND);
976 setTargetDAGCombine(ISD::ANY_EXTEND);
977 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
978 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
979 setTargetDAGCombine(ISD::INTRINSIC_VOID);
980 setTargetDAGCombine(ISD::VECREDUCE_ADD);
981 setTargetDAGCombine(ISD::ADD);
982 setTargetDAGCombine(ISD::BITCAST);
983 }
984 if (Subtarget->hasMVEIntegerOps()) {
985 setTargetDAGCombine(ISD::SMIN);
986 setTargetDAGCombine(ISD::UMIN);
987 setTargetDAGCombine(ISD::SMAX);
988 setTargetDAGCombine(ISD::UMAX);
989 setTargetDAGCombine(ISD::FP_EXTEND);
990 setTargetDAGCombine(ISD::SELECT);
991 setTargetDAGCombine(ISD::SELECT_CC);
992 }
993
994 if (!Subtarget->hasFP64()) {
995 // When targeting a floating-point unit with only single-precision
996 // operations, f64 is legal for the few double-precision instructions which
997 // are present However, no double-precision operations other than moves,
998 // loads and stores are provided by the hardware.
999 setOperationAction(ISD::FADD, MVT::f64, Expand);
1000 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1001 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1002 setOperationAction(ISD::FMA, MVT::f64, Expand);
1003 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1004 setOperationAction(ISD::FREM, MVT::f64, Expand);
1005 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1006 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1007 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1008 setOperationAction(ISD::FABS, MVT::f64, Expand);
1009 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1010 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1011 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1012 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1013 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1014 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1015 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1016 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1017 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1018 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1019 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1020 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1021 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1022 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1023 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1025 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1026 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1027 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1028 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1029 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1030 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1031 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1032 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1033 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1034 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1035 }
1036
1037 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1038 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1039 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1040 if (Subtarget->hasFullFP16()) {
1041 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1042 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1043 }
1044 }
1045
1046 if (!Subtarget->hasFP16()) {
1047 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1048 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1049 }
1050
1051 computeRegisterProperties(Subtarget->getRegisterInfo());
1052
1053 // ARM does not have floating-point extending loads.
1054 for (MVT VT : MVT::fp_valuetypes()) {
1055 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1056 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1057 }
1058
1059 // ... or truncating stores
1060 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1061 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1062 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1063
1064 // ARM does not have i1 sign extending load.
1065 for (MVT VT : MVT::integer_valuetypes())
1066 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1067
1068 // ARM supports all 4 flavors of integer indexed load / store.
1069 if (!Subtarget->isThumb1Only()) {
1070 for (unsigned im = (unsigned)ISD::PRE_INC;
1071 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1072 setIndexedLoadAction(im, MVT::i1, Legal);
1073 setIndexedLoadAction(im, MVT::i8, Legal);
1074 setIndexedLoadAction(im, MVT::i16, Legal);
1075 setIndexedLoadAction(im, MVT::i32, Legal);
1076 setIndexedStoreAction(im, MVT::i1, Legal);
1077 setIndexedStoreAction(im, MVT::i8, Legal);
1078 setIndexedStoreAction(im, MVT::i16, Legal);
1079 setIndexedStoreAction(im, MVT::i32, Legal);
1080 }
1081 } else {
1082 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1083 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1084 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1085 }
1086
1087 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1088 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1089 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1090 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1091
1092 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1093 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1094 if (Subtarget->hasDSP()) {
1095 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1096 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1097 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1098 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1099 }
1100 if (Subtarget->hasBaseDSP()) {
1101 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1102 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1103 }
1104
1105 // i64 operation support.
1106 setOperationAction(ISD::MUL, MVT::i64, Expand);
1107 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1108 if (Subtarget->isThumb1Only()) {
1109 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1110 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1111 }
1112 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1113 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1114 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1115
1116 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1117 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1118 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1119 setOperationAction(ISD::SRL, MVT::i64, Custom);
1120 setOperationAction(ISD::SRA, MVT::i64, Custom);
1121 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1122 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1123 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1124 setOperationAction(ISD::STORE, MVT::i64, Custom);
1125
1126 // MVE lowers 64 bit shifts to lsll and lsrl
1127 // assuming that ISD::SRL and SRA of i64 are already marked custom
1128 if (Subtarget->hasMVEIntegerOps())
1129 setOperationAction(ISD::SHL, MVT::i64, Custom);
1130
1131 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1132 if (Subtarget->isThumb1Only()) {
1133 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1134 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1135 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1136 }
1137
1138 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1139 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1140
1141 // ARM does not have ROTL.
1142 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1143 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1144 setOperationAction(ISD::ROTL, VT, Expand);
1145 setOperationAction(ISD::ROTR, VT, Expand);
1146 }
1147 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1148 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1149 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1150 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1151 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1152 }
1153
1154 // @llvm.readcyclecounter requires the Performance Monitors extension.
1155 // Default to the 0 expansion on unsupported platforms.
1156 // FIXME: Technically there are older ARM CPUs that have
1157 // implementation-specific ways of obtaining this information.
1158 if (Subtarget->hasPerfMon())
1159 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1160
1161 // Only ARMv6 has BSWAP.
1162 if (!Subtarget->hasV6Ops())
1163 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1164
1165 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1166 : Subtarget->hasDivideInARMMode();
1167 if (!hasDivide) {
1168 // These are expanded into libcalls if the cpu doesn't have HW divider.
1169 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1170 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1171 }
1172
1173 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1174 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1175 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1176
1177 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1178 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1179 }
1180
1181 setOperationAction(ISD::SREM, MVT::i32, Expand);
1182 setOperationAction(ISD::UREM, MVT::i32, Expand);
1183
1184 // Register based DivRem for AEABI (RTABI 4.2)
1185 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1186 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1187 Subtarget->isTargetWindows()) {
1188 setOperationAction(ISD::SREM, MVT::i64, Custom);
1189 setOperationAction(ISD::UREM, MVT::i64, Custom);
1190 HasStandaloneRem = false;
1191
1192 if (Subtarget->isTargetWindows()) {
1193 const struct {
1194 const RTLIB::Libcall Op;
1195 const char * const Name;
1196 const CallingConv::ID CC;
1197 } LibraryCalls[] = {
1198 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1199 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1200 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1201 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1202
1203 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1204 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1205 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1206 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1207 };
1208
1209 for (const auto &LC : LibraryCalls) {
1210 setLibcallName(LC.Op, LC.Name);
1211 setLibcallCallingConv(LC.Op, LC.CC);
1212 }
1213 } else {
1214 const struct {
1215 const RTLIB::Libcall Op;
1216 const char * const Name;
1217 const CallingConv::ID CC;
1218 } LibraryCalls[] = {
1219 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1220 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1221 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1222 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1223
1224 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1225 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1226 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1227 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1228 };
1229
1230 for (const auto &LC : LibraryCalls) {
1231 setLibcallName(LC.Op, LC.Name);
1232 setLibcallCallingConv(LC.Op, LC.CC);
1233 }
1234 }
1235
1236 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1237 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1238 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1239 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1240 } else {
1241 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1242 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1243 }
1244
1245 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1246 // MSVCRT doesn't have powi; fall back to pow
1247 setLibcallName(RTLIB::POWI_F32, nullptr);
1248 setLibcallName(RTLIB::POWI_F64, nullptr);
1249 }
1250
1251 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1252 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1253 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1254 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1255
1256 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1257 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1258
1259 // Use the default implementation.
1260 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1261 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1262 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1263 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1264 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1265 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1266
1267 if (Subtarget->isTargetWindows())
1268 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1269 else
1270 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1271
1272 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1273 // the default expansion.
1274 InsertFencesForAtomic = false;
1275 if (Subtarget->hasAnyDataBarrier() &&
1276 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1277 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1278 // to ldrex/strex loops already.
1279 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1280 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1281 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1282
1283 // On v8, we have particularly efficient implementations of atomic fences
1284 // if they can be combined with nearby atomic loads and stores.
1285 if (!Subtarget->hasAcquireRelease() ||
1286 getTargetMachine().getOptLevel() == 0) {
1287 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1288 InsertFencesForAtomic = true;
1289 }
1290 } else {
1291 // If there's anything we can use as a barrier, go through custom lowering
1292 // for ATOMIC_FENCE.
1293 // If target has DMB in thumb, Fences can be inserted.
1294 if (Subtarget->hasDataBarrier())
1295 InsertFencesForAtomic = true;
1296
1297 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1298 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1299
1300 // Set them all for expansion, which will force libcalls.
1301 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1302 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1303 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1304 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1305 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1306 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1307 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1308 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1309 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1310 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1311 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1312 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1313 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1314 // Unordered/Monotonic case.
1315 if (!InsertFencesForAtomic) {
1316 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1317 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1318 }
1319 }
1320
1321 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1322
1323 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1324 if (!Subtarget->hasV6Ops()) {
1325 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1327 }
1328 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1329
1330 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1331 !Subtarget->isThumb1Only()) {
1332 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1333 // iff target supports vfp2.
1334 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1335 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1336 }
1337
1338 // We want to custom lower some of our intrinsics.
1339 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1340 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1341 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1342 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1343 if (Subtarget->useSjLjEH())
1344 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1345
1346 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1347 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1348 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1349 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1350 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1351 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1352 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1353 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1354 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1355 if (Subtarget->hasFullFP16()) {
1356 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1357 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1358 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1359 }
1360
1361 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1362
1363 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1364 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1365 if (Subtarget->hasFullFP16())
1366 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1367 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1368 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1369 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1370
1371 // We don't support sin/cos/fmod/copysign/pow
1372 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1373 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1374 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1375 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1376 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1377 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1378 setOperationAction(ISD::FREM, MVT::f64, Expand);
1379 setOperationAction(ISD::FREM, MVT::f32, Expand);
1380 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1381 !Subtarget->isThumb1Only()) {
1382 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1383 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1384 }
1385 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1386 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1387
1388 if (!Subtarget->hasVFP4Base()) {
1389 setOperationAction(ISD::FMA, MVT::f64, Expand);
1390 setOperationAction(ISD::FMA, MVT::f32, Expand);
1391 }
1392
1393 // Various VFP goodness
1394 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1395 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1396 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1397 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1398 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1399 }
1400
1401 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1402 if (!Subtarget->hasFP16()) {
1403 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1404 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1405 }
1406
1407 // Strict floating-point comparisons need custom lowering.
1408 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1409 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1410 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1411 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1412 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1413 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1414 }
1415
1416 // Use __sincos_stret if available.
1417 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1418 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1419 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1420 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1421 }
1422
1423 // FP-ARMv8 implements a lot of rounding-like FP operations.
1424 if (Subtarget->hasFPARMv8Base()) {
1425 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1426 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1427 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1428 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1429 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1430 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1431 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1432 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1433 if (Subtarget->hasNEON()) {
1434 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1435 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1436 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1437 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1438 }
1439
1440 if (Subtarget->hasFP64()) {
1441 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1442 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1443 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1444 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1445 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1446 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1447 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1448 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1449 }
1450 }
1451
1452 // FP16 often need to be promoted to call lib functions
1453 if (Subtarget->hasFullFP16()) {
1454 setOperationAction(ISD::FREM, MVT::f16, Promote);
1455 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1456 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1457 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1458 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1459 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1460 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1461 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1462 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1463 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1464 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1465 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1466
1467 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1468 }
1469
1470 if (Subtarget->hasNEON()) {
1471 // vmin and vmax aren't available in a scalar form, so we can use
1472 // a NEON instruction with an undef lane instead. This has a performance
1473 // penalty on some cores, so we don't do this unless we have been
1474 // asked to by the core tuning model.
1475 if (Subtarget->useNEONForSinglePrecisionFP()) {
1476 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1477 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1478 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1479 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1480 }
1481 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1482 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1483 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1484 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1485
1486 if (Subtarget->hasFullFP16()) {
1487 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1488 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1489 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1490 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1491
1492 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1493 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1494 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1495 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1496 }
1497 }
1498
1499 // We have target-specific dag combine patterns for the following nodes:
1500 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1501 setTargetDAGCombine(ISD::ADD);
1502 setTargetDAGCombine(ISD::SUB);
1503 setTargetDAGCombine(ISD::MUL);
1504 setTargetDAGCombine(ISD::AND);
1505 setTargetDAGCombine(ISD::OR);
1506 setTargetDAGCombine(ISD::XOR);
1507
1508 if (Subtarget->hasMVEIntegerOps())
1509 setTargetDAGCombine(ISD::VSELECT);
1510
1511 if (Subtarget->hasV6Ops())
1512 setTargetDAGCombine(ISD::SRL);
1513 if (Subtarget->isThumb1Only())
1514 setTargetDAGCombine(ISD::SHL);
1515
1516 setStackPointerRegisterToSaveRestore(ARM::SP);
1517
1518 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1519 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1520 setSchedulingPreference(Sched::RegPressure);
1521 else
1522 setSchedulingPreference(Sched::Hybrid);
1523
1524 //// temporary - rewrite interface to use type
1525 MaxStoresPerMemset = 8;
1526 MaxStoresPerMemsetOptSize = 4;
1527 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1528 MaxStoresPerMemcpyOptSize = 2;
1529 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1530 MaxStoresPerMemmoveOptSize = 2;
1531
1532 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1533 // are at least 4 bytes aligned.
1534 setMinStackArgumentAlignment(Align(4));
1535
1536 // Prefer likely predicted branches to selects on out-of-order cores.
1537 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1538
1539 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1540
1541 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1542
1543 if (Subtarget->isThumb() || Subtarget->isThumb2())
1544 setTargetDAGCombine(ISD::ABS);
1545}
1546
1547bool ARMTargetLowering::useSoftFloat() const {
1548 return Subtarget->useSoftFloat();
1549}
1550
1551// FIXME: It might make sense to define the representative register class as the
1552// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1553// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1554// SPR's representative would be DPR_VFP2. This should work well if register
1555// pressure tracking were modified such that a register use would increment the
1556// pressure of the register class's representative and all of it's super
1557// classes' representatives transitively. We have not implemented this because
1558// of the difficulty prior to coalescing of modeling operand register classes
1559// due to the common occurrence of cross class copies and subregister insertions
1560// and extractions.
1561std::pair<const TargetRegisterClass *, uint8_t>
1562ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1563 MVT VT) const {
1564 const TargetRegisterClass *RRC = nullptr;
1565 uint8_t Cost = 1;
1566 switch (VT.SimpleTy) {
1567 default:
1568 return TargetLowering::findRepresentativeClass(TRI, VT);
1569 // Use DPR as representative register class for all floating point
1570 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1571 // the cost is 1 for both f32 and f64.
1572 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1573 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1574 RRC = &ARM::DPRRegClass;
1575 // When NEON is used for SP, only half of the register file is available
1576 // because operations that define both SP and DP results will be constrained
1577 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1578 // coalescing by double-counting the SP regs. See the FIXME above.
1579 if (Subtarget->useNEONForSinglePrecisionFP())
1580 Cost = 2;
1581 break;
1582 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1583 case MVT::v4f32: case MVT::v2f64:
1584 RRC = &ARM::DPRRegClass;
1585 Cost = 2;
1586 break;
1587 case MVT::v4i64:
1588 RRC = &ARM::DPRRegClass;
1589 Cost = 4;
1590 break;
1591 case MVT::v8i64:
1592 RRC = &ARM::DPRRegClass;
1593 Cost = 8;
1594 break;
1595 }
1596 return std::make_pair(RRC, Cost);
1597}
1598
1599const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1600 switch ((ARMISD::NodeType)Opcode) {
1601 case ARMISD::FIRST_NUMBER: break;
1602 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1603 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1604 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1605 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1606 case ARMISD::CALL: return "ARMISD::CALL";
1607 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1608 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1609 case ARMISD::tSECALL: return "ARMISD::tSECALL";
1610 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1611 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1612 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1613 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1614 case ARMISD::SERET_FLAG: return "ARMISD::SERET_FLAG";
1615 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1616 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1617 case ARMISD::CMP: return "ARMISD::CMP";
1618 case ARMISD::CMN: return "ARMISD::CMN";
1619 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1620 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1621 case ARMISD::CMPFPE: return "ARMISD::CMPFPE";
1622 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1623 case ARMISD::CMPFPEw0: return "ARMISD::CMPFPEw0";
1624 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1625 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1626
1627 case ARMISD::CMOV: return "ARMISD::CMOV";
1628 case ARMISD::SUBS: return "ARMISD::SUBS";
1629
1630 case ARMISD::SSAT: return "ARMISD::SSAT";
1631 case ARMISD::USAT: return "ARMISD::USAT";
1632
1633 case ARMISD::ASRL: return "ARMISD::ASRL";
1634 case ARMISD::LSRL: return "ARMISD::LSRL";
1635 case ARMISD::LSLL: return "ARMISD::LSLL";
1636
1637 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1638 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1639 case ARMISD::RRX: return "ARMISD::RRX";
1640
1641 case ARMISD::ADDC: return "ARMISD::ADDC";
1642 case ARMISD::ADDE: return "ARMISD::ADDE";
1643 case ARMISD::SUBC: return "ARMISD::SUBC";
1644 case ARMISD::SUBE: return "ARMISD::SUBE";
1645 case ARMISD::LSLS: return "ARMISD::LSLS";
1646
1647 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1648 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1649 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1650 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1651 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1652
1653 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1654 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1655 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1656
1657 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1658
1659 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1660
1661 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1662
1663 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1664
1665 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1666
1667 case ARMISD::LDRD: return "ARMISD::LDRD";
1668 case ARMISD::STRD: return "ARMISD::STRD";
1669
1670 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1671 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1672
1673 case ARMISD::PREDICATE_CAST: return "ARMISD::PREDICATE_CAST";
1674 case ARMISD::VECTOR_REG_CAST: return "ARMISD::VECTOR_REG_CAST";
1675 case ARMISD::VCMP: return "ARMISD::VCMP";
1676 case ARMISD::VCMPZ: return "ARMISD::VCMPZ";
1677 case ARMISD::VTST: return "ARMISD::VTST";
1678
1679 case ARMISD::VSHLs: return "ARMISD::VSHLs";
1680 case ARMISD::VSHLu: return "ARMISD::VSHLu";
1681 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM";
1682 case ARMISD::VSHRsIMM: return "ARMISD::VSHRsIMM";
1683 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM";
1684 case ARMISD::VRSHRsIMM: return "ARMISD::VRSHRsIMM";
1685 case ARMISD::VRSHRuIMM: return "ARMISD::VRSHRuIMM";
1686 case ARMISD::VRSHRNIMM: return "ARMISD::VRSHRNIMM";
1687 case ARMISD::VQSHLsIMM: return "ARMISD::VQSHLsIMM";
1688 case ARMISD::VQSHLuIMM: return "ARMISD::VQSHLuIMM";
1689 case ARMISD::VQSHLsuIMM: return "ARMISD::VQSHLsuIMM";
1690 case ARMISD::VQSHRNsIMM: return "ARMISD::VQSHRNsIMM";
1691 case ARMISD::VQSHRNuIMM: return "ARMISD::VQSHRNuIMM";
1692 case ARMISD::VQSHRNsuIMM: return "ARMISD::VQSHRNsuIMM";
1693 case ARMISD::VQRSHRNsIMM: return "ARMISD::VQRSHRNsIMM";
1694 case ARMISD::VQRSHRNuIMM: return "ARMISD::VQRSHRNuIMM";
1695 case ARMISD::VQRSHRNsuIMM: return "ARMISD::VQRSHRNsuIMM";
1696 case ARMISD::VSLIIMM: return "ARMISD::VSLIIMM";
1697 case ARMISD::VSRIIMM: return "ARMISD::VSRIIMM";
1698 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1699 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1700 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1701 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1702 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1703 case ARMISD::VDUP: return "ARMISD::VDUP";
1704 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1705 case ARMISD::VEXT: return "ARMISD::VEXT";
1706 case ARMISD::VREV64: return "ARMISD::VREV64";
1707 case ARMISD::VREV32: return "ARMISD::VREV32";
1708 case ARMISD::VREV16: return "ARMISD::VREV16";
1709 case ARMISD::VZIP: return "ARMISD::VZIP";
1710 case ARMISD::VUZP: return "ARMISD::VUZP";
1711 case ARMISD::VTRN: return "ARMISD::VTRN";
1712 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1713 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1714 case ARMISD::VMOVN: return "ARMISD::VMOVN";
1715 case ARMISD::VQMOVNs: return "ARMISD::VQMOVNs";
1716 case ARMISD::VQMOVNu: return "ARMISD::VQMOVNu";
1717 case ARMISD::VCVTN: return "ARMISD::VCVTN";
1718 case ARMISD::VCVTL: return "ARMISD::VCVTL";
1719 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1720 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1721 case ARMISD::VQDMULH: return "ARMISD::VQDMULH";
1722 case ARMISD::VADDVs: return "ARMISD::VADDVs";
1723 case ARMISD::VADDVu: return "ARMISD::VADDVu";
1724 case ARMISD::VADDVps: return "ARMISD::VADDVps";
1725 case ARMISD::VADDVpu: return "ARMISD::VADDVpu";
1726 case ARMISD::VADDLVs: return "ARMISD::VADDLVs";
1727 case ARMISD::VADDLVu: return "ARMISD::VADDLVu";
1728 case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs";
1729 case ARMISD::VADDLVAu: return "ARMISD::VADDLVAu";
1730 case ARMISD::VADDLVps: return "ARMISD::VADDLVps";
1731 case ARMISD::VADDLVpu: return "ARMISD::VADDLVpu";
1732 case ARMISD::VADDLVAps: return "ARMISD::VADDLVAps";
1733 case ARMISD::VADDLVApu: return "ARMISD::VADDLVApu";
1734 case ARMISD::VMLAVs: return "ARMISD::VMLAVs";
1735 case ARMISD::VMLAVu: return "ARMISD::VMLAVu";
1736 case ARMISD::VMLAVps: return "ARMISD::VMLAVps";
1737 case ARMISD::VMLAVpu: return "ARMISD::VMLAVpu";
1738 case ARMISD::VMLALVs: return "ARMISD::VMLALVs";
1739 case ARMISD::VMLALVu: return "ARMISD::VMLALVu";
1740 case ARMISD::VMLALVps: return "ARMISD::VMLALVps";
1741 case ARMISD::VMLALVpu: return "ARMISD::VMLALVpu";
1742 case ARMISD::VMLALVAs: return "ARMISD::VMLALVAs";
1743 case ARMISD::VMLALVAu: return "ARMISD::VMLALVAu";
1744 case ARMISD::VMLALVAps: return "ARMISD::VMLALVAps";
1745 case ARMISD::VMLALVApu: return "ARMISD::VMLALVApu";
1746 case ARMISD::VMINVu: return "ARMISD::VMINVu";
1747 case ARMISD::VMINVs: return "ARMISD::VMINVs";
1748 case ARMISD::VMAXVu: return "ARMISD::VMAXVu";
1749 case ARMISD::VMAXVs: return "ARMISD::VMAXVs";
1750 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1751 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1752 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1753 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1754 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1755 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1756 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1757 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1758 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1759 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1760 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1761 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1762 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1763 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1764 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1765 case ARMISD::QADD16b: return "ARMISD::QADD16b";
1766 case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
1767 case ARMISD::QADD8b: return "ARMISD::QADD8b";
1768 case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
1769 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1770 case ARMISD::BFI: return "ARMISD::BFI";
1771 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1772 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1773 case ARMISD::VBSP: return "ARMISD::VBSP";
1774 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1775 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1776 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1777 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1778 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1779 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1780 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1781 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1782 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1783 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1784 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1785 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1786 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1787 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1788 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1789 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1790 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1791 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1792 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1793 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1794 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1795 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1796 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1797 case ARMISD::WLS: return "ARMISD::WLS";
1798 case ARMISD::LE: return "ARMISD::LE";
1799 case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
1800 case ARMISD::CSINV: return "ARMISD::CSINV";
1801 case ARMISD::CSNEG: return "ARMISD::CSNEG";
1802 case ARMISD::CSINC: return "ARMISD::CSINC";
1803 }
1804 return nullptr;
1805}
1806
1807EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1808 EVT VT) const {
1809 if (!VT.isVector())
1810 return getPointerTy(DL);
1811
1812 // MVE has a predicate register.
1813 if (Subtarget->hasMVEIntegerOps() &&
1814 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1815 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1816 return VT.changeVectorElementTypeToInteger();
1817}
1818
1819/// getRegClassFor - Return the register class that should be used for the
1820/// specified value type.
1821const TargetRegisterClass *
1822ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1823 (void)isDivergent;
1824 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1825 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1826 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1827 // MVE Q registers.
1828 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1829 if (VT == MVT::v4i64)
1830 return &ARM::QQPRRegClass;
1831 if (VT == MVT::v8i64)
1832 return &ARM::QQQQPRRegClass;
1833 }
1834 return TargetLowering::getRegClassFor(VT);
1835}
1836
1837// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1838// source/dest is aligned and the copy size is large enough. We therefore want
1839// to align such objects passed to memory intrinsics.
1840bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1841 unsigned &PrefAlign) const {
1842 if (!isa<MemIntrinsic>(CI))
1843 return false;
1844 MinSize = 8;
1845 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1846 // cycle faster than 4-byte aligned LDM.
1847 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1848 return true;
1849}
1850
1851// Create a fast isel object.
1852FastISel *
1853ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1854 const TargetLibraryInfo *libInfo) const {
1855 return ARM::createFastISel(funcInfo, libInfo);
1856}
1857
1858Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1859 unsigned NumVals = N->getNumValues();
1860 if (!NumVals)
1861 return Sched::RegPressure;
1862
1863 for (unsigned i = 0; i != NumVals; ++i) {
1864 EVT VT = N->getValueType(i);
1865 if (VT == MVT::Glue || VT == MVT::Other)
1866 continue;
1867 if (VT.isFloatingPoint() || VT.isVector())
1868 return Sched::ILP;
1869 }
1870
1871 if (!N->isMachineOpcode())
1872 return Sched::RegPressure;
1873
1874 // Load are scheduled for latency even if there instruction itinerary
1875 // is not available.
1876 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1877 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1878
1879 if (MCID.getNumDefs() == 0)
1880 return Sched::RegPressure;
1881 if (!Itins->isEmpty() &&
1882 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1883 return Sched::ILP;
1884
1885 return Sched::RegPressure;
1886}
1887
1888//===----------------------------------------------------------------------===//
1889// Lowering Code
1890//===----------------------------------------------------------------------===//
1891
1892static bool isSRL16(const SDValue &Op) {
1893 if (Op.getOpcode() != ISD::SRL)
1894 return false;
1895 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1896 return Const->getZExtValue() == 16;
1897 return false;
1898}
1899
1900static bool isSRA16(const SDValue &Op) {
1901 if (Op.getOpcode() != ISD::SRA)
1902 return false;
1903 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1904 return Const->getZExtValue() == 16;
1905 return false;
1906}
1907
1908static bool isSHL16(const SDValue &Op) {
1909 if (Op.getOpcode() != ISD::SHL)
1910 return false;
1911 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1912 return Const->getZExtValue() == 16;
1913 return false;
1914}
1915
1916// Check for a signed 16-bit value. We special case SRA because it makes it
1917// more simple when also looking for SRAs that aren't sign extending a
1918// smaller value. Without the check, we'd need to take extra care with
1919// checking order for some operations.
1920static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1921 if (isSRA16(Op))
1922 return isSHL16(Op.getOperand(0));
1923 return DAG.ComputeNumSignBits(Op) == 17;
1924}
1925
1926/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1927static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1928 switch (CC) {
1929 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1929)
;
1930 case ISD::SETNE: return ARMCC::NE;
1931 case ISD::SETEQ: return ARMCC::EQ;
1932 case ISD::SETGT: return ARMCC::GT;
1933 case ISD::SETGE: return ARMCC::GE;
1934 case ISD::SETLT: return ARMCC::LT;
1935 case ISD::SETLE: return ARMCC::LE;
1936 case ISD::SETUGT: return ARMCC::HI;
1937 case ISD::SETUGE: return ARMCC::HS;
1938 case ISD::SETULT: return ARMCC::LO;
1939 case ISD::SETULE: return ARMCC::LS;
1940 }
1941}
1942
1943/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1944static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1945 ARMCC::CondCodes &CondCode2) {
1946 CondCode2 = ARMCC::AL;
1947 switch (CC) {
1948 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1948)
;
1949 case ISD::SETEQ:
1950 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1951 case ISD::SETGT:
1952 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1953 case ISD::SETGE:
1954 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1955 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1956 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1957 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1958 case ISD::SETO: CondCode = ARMCC::VC; break;
1959 case ISD::SETUO: CondCode = ARMCC::VS; break;
1960 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1961 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1962 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1963 case ISD::SETLT:
1964 case ISD::SETULT: CondCode = ARMCC::LT; break;
1965 case ISD::SETLE:
1966 case ISD::SETULE: CondCode = ARMCC::LE; break;
1967 case ISD::SETNE:
1968 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1969 }
1970}
1971
1972//===----------------------------------------------------------------------===//
1973// Calling Convention Implementation
1974//===----------------------------------------------------------------------===//
1975
1976/// getEffectiveCallingConv - Get the effective calling convention, taking into
1977/// account presence of floating point hardware and calling convention
1978/// limitations, such as support for variadic functions.
1979CallingConv::ID
1980ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1981 bool isVarArg) const {
1982 switch (CC) {
1983 default:
1984 report_fatal_error("Unsupported calling convention");
1985 case CallingConv::ARM_AAPCS:
1986 case CallingConv::ARM_APCS:
1987 case CallingConv::GHC:
1988 case CallingConv::CFGuard_Check:
1989 return CC;
1990 case CallingConv::PreserveMost:
1991 return CallingConv::PreserveMost;
1992 case CallingConv::ARM_AAPCS_VFP:
1993 case CallingConv::Swift:
1994 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1995 case CallingConv::C:
1996 if (!Subtarget->isAAPCS_ABI())
1997 return CallingConv::ARM_APCS;
1998 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
1999 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
2000 !isVarArg)
2001 return CallingConv::ARM_AAPCS_VFP;
2002 else
2003 return CallingConv::ARM_AAPCS;
2004 case CallingConv::Fast:
2005 case CallingConv::CXX_FAST_TLS:
2006 if (!Subtarget->isAAPCS_ABI()) {
2007 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2008 return CallingConv::Fast;
2009 return CallingConv::ARM_APCS;
2010 } else if (Subtarget->hasVFP2Base() &&
2011 !Subtarget->isThumb1Only() && !isVarArg)
2012 return CallingConv::ARM_AAPCS_VFP;
2013 else
2014 return CallingConv::ARM_AAPCS;
2015 }
2016}
2017
2018CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2019 bool isVarArg) const {
2020 return CCAssignFnForNode(CC, false, isVarArg);
2021}
2022
2023CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2024 bool isVarArg) const {
2025 return CCAssignFnForNode(CC, true, isVarArg);
2026}
2027
2028/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2029/// CallingConvention.
2030CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2031 bool Return,
2032 bool isVarArg) const {
2033 switch (getEffectiveCallingConv(CC, isVarArg)) {
2034 default:
2035 report_fatal_error("Unsupported calling convention");
2036 case CallingConv::ARM_APCS:
2037 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2038 case CallingConv::ARM_AAPCS:
2039 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2040 case CallingConv::ARM_AAPCS_VFP:
2041 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2042 case CallingConv::Fast:
2043 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2044 case CallingConv::GHC:
2045 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2046 case CallingConv::PreserveMost:
2047 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2048 case CallingConv::CFGuard_Check:
2049 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2050 }
2051}
2052
2053SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2054 MVT LocVT, MVT ValVT, SDValue Val) const {
2055 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2056 Val);
2057 if (Subtarget->hasFullFP16()) {
2058 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2059 } else {
2060 Val = DAG.getNode(ISD::TRUNCATE, dl,
2061 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2062 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2063 }
2064 return Val;
2065}
2066
2067SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2068 MVT LocVT, MVT ValVT,
2069 SDValue Val) const {
2070 if (Subtarget->hasFullFP16()) {
2071 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2072 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2073 } else {
2074 Val = DAG.getNode(ISD::BITCAST, dl,
2075 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2076 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2077 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2078 }
2079 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2080}
2081
2082/// LowerCallResult - Lower the result values of a call into the
2083/// appropriate copies out of appropriate physical registers.
2084SDValue ARMTargetLowering::LowerCallResult(
2085 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2086 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2087 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2088 SDValue ThisVal) const {
2089 // Assign locations to each value returned by this call.
2090 SmallVector<CCValAssign, 16> RVLocs;
2091 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2092 *DAG.getContext());
2093 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2094
2095 // Copy all of the result registers out of their specified physreg.
2096 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2097 CCValAssign VA = RVLocs[i];
2098
2099 // Pass 'this' value directly from the argument to return value, to avoid
2100 // reg unit interference
2101 if (i == 0 && isThisReturn) {
2102 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
2103 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2103, __PRETTY_FUNCTION__))
;
2104 InVals.push_back(ThisVal);
2105 continue;
2106 }
2107
2108 SDValue Val;
2109 if (VA.needsCustom() &&
2110 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2111 // Handle f64 or half of a v2f64.
2112 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2113 InFlag);
2114 Chain = Lo.getValue(1);
2115 InFlag = Lo.getValue(2);
2116 VA = RVLocs[++i]; // skip ahead to next loc
2117 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2118 InFlag);
2119 Chain = Hi.getValue(1);
2120 InFlag = Hi.getValue(2);
2121 if (!Subtarget->isLittle())
2122 std::swap (Lo, Hi);
2123 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2124
2125 if (VA.getLocVT() == MVT::v2f64) {
2126 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2127 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2128 DAG.getConstant(0, dl, MVT::i32));
2129
2130 VA = RVLocs[++i]; // skip ahead to next loc
2131 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2132 Chain = Lo.getValue(1);
2133 InFlag = Lo.getValue(2);
2134 VA = RVLocs[++i]; // skip ahead to next loc
2135 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2136 Chain = Hi.getValue(1);
2137 InFlag = Hi.getValue(2);
2138 if (!Subtarget->isLittle())
2139 std::swap (Lo, Hi);
2140 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2141 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2142 DAG.getConstant(1, dl, MVT::i32));
2143 }
2144 } else {
2145 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2146 InFlag);
2147 Chain = Val.getValue(1);
2148 InFlag = Val.getValue(2);
2149 }
2150
2151 switch (VA.getLocInfo()) {
2152 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2152)
;
2153 case CCValAssign::Full: break;
2154 case CCValAssign::BCvt:
2155 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2156 break;
2157 }
2158
2159 // f16 arguments have their size extended to 4 bytes and passed as if they
2160 // had been copied to the LSBs of a 32-bit register.
2161 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2162 if (VA.needsCustom() &&
2163 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2164 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2165
2166 InVals.push_back(Val);
2167 }
2168
2169 return Chain;
2170}
2171
2172/// LowerMemOpCallTo - Store the argument to the stack.
2173SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
2174 SDValue Arg, const SDLoc &dl,
2175 SelectionDAG &DAG,
2176 const CCValAssign &VA,
2177 ISD::ArgFlagsTy Flags) const {
2178 unsigned LocMemOffset = VA.getLocMemOffset();
2179 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2180 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2181 StackPtr, PtrOff);
2182 return DAG.getStore(
2183 Chain, dl, Arg, PtrOff,
2184 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
2185}
2186
2187void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2188 SDValue Chain, SDValue &Arg,
2189 RegsToPassVector &RegsToPass,
2190 CCValAssign &VA, CCValAssign &NextVA,
2191 SDValue &StackPtr,
2192 SmallVectorImpl<SDValue> &MemOpChains,
2193 ISD::ArgFlagsTy Flags) const {
2194 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2195 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2196 unsigned id = Subtarget->isLittle() ? 0 : 1;
2197 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2198
2199 if (NextVA.isRegLoc())
2200 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2201 else {
2202 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2202, __PRETTY_FUNCTION__))
;
2203 if (!StackPtr.getNode())
2204 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2205 getPointerTy(DAG.getDataLayout()));
2206
2207 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
2208 dl, DAG, NextVA,
2209 Flags));
2210 }
2211}
2212
2213/// LowerCall - Lowering a call into a callseq_start <-
2214/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2215/// nodes.
2216SDValue
2217ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2218 SmallVectorImpl<SDValue> &InVals) const {
2219 SelectionDAG &DAG = CLI.DAG;
2220 SDLoc &dl = CLI.DL;
2221 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2222 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2223 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2224 SDValue Chain = CLI.Chain;
2225 SDValue Callee = CLI.Callee;
2226 bool &isTailCall = CLI.IsTailCall;
2227 CallingConv::ID CallConv = CLI.CallConv;
2228 bool doesNotRet = CLI.DoesNotReturn;
2229 bool isVarArg = CLI.IsVarArg;
2230
2231 MachineFunction &MF = DAG.getMachineFunction();
2232 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2233 MachineFunction::CallSiteInfo CSInfo;
2234 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
2235 bool isThisReturn = false;
2236 bool isCmseNSCall = false;
2237 bool PreferIndirect = false;
2238
2239 // Determine whether this is a non-secure function call.
2240 if (CLI.CB && CLI.CB->getAttributes().hasFnAttribute("cmse_nonsecure_call"))
2
Assuming field 'CB' is null
3
Taking false branch
2241 isCmseNSCall = true;
2242
2243 // Disable tail calls if they're not supported.
2244 if (!Subtarget->supportsTailCall())
4
Assuming the condition is false
5
Taking false branch
2245 isTailCall = false;
2246
2247 // For both the non-secure calls and the returns from a CMSE entry function,
2248 // the function needs to do some extra work afte r the call, or before the
2249 // return, respectively, thus it cannot end with atail call
2250 if (isCmseNSCall
5.1
'isCmseNSCall' is false
|| AFI->isCmseNSEntryFunction())
6
Assuming the condition is false
7
Taking false branch
2251 isTailCall = false;
2252
2253 if (isa<GlobalAddressSDNode>(Callee)) {
8
Assuming 'Callee' is not a 'GlobalAddressSDNode'
9
Taking false branch
2254 // If we're optimizing for minimum size and the function is called three or
2255 // more times in this block, we can improve codesize by calling indirectly
2256 // as BLXr has a 16-bit encoding.
2257 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2258 if (CLI.CB) {
2259 auto *BB = CLI.CB->getParent();
2260 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2261 count_if(GV->users(), [&BB](const User *U) {
2262 return isa<Instruction>(U) &&
2263 cast<Instruction>(U)->getParent() == BB;
2264 }) > 2;
2265 }
2266 }
2267 if (isTailCall) {
10
Assuming 'isTailCall' is false
11
Taking false branch
2268 // Check if it's really possible to do a tail call.
2269 isTailCall = IsEligibleForTailCallOptimization(
2270 Callee, CallConv, isVarArg, isStructRet,
2271 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2272 PreferIndirect);
2273 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2274 report_fatal_error("failed to perform tail call elimination on a call "
2275 "site marked musttail");
2276 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2277 // detected sibcalls.
2278 if (isTailCall)
2279 ++NumTailCalls;
2280 }
2281
2282 // Analyze operands of the call, assigning locations to each operand.
2283 SmallVector<CCValAssign, 16> ArgLocs;
2284 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2285 *DAG.getContext());
2286 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2287
2288 // Get a count of how many bytes are to be pushed on the stack.
2289 unsigned NumBytes = CCInfo.getNextStackOffset();
2290
2291 if (isTailCall) {
12
Assuming 'isTailCall' is false
13
Taking false branch
2292 // For tail calls, memory operands are available in our caller's stack.
2293 NumBytes = 0;
2294 } else {
2295 // Adjust the stack pointer for the new arguments...
2296 // These operations are automatically eliminated by the prolog/epilog pass
2297 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
2298 }
2299
2300 SDValue StackPtr =
2301 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2302
2303 RegsToPassVector RegsToPass;
2304 SmallVector<SDValue, 8> MemOpChains;
2305
2306 // Walk the register/memloc assignments, inserting copies/loads. In the case
2307 // of tail call optimization, arguments are handled later.
2308 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
15
Loop condition is false. Execution continues on line 2450
2309 i != e;
14
Assuming 'i' is equal to 'e'
2310 ++i, ++realArgIdx) {
2311 CCValAssign &VA = ArgLocs[i];
2312 SDValue Arg = OutVals[realArgIdx];
2313 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2314 bool isByVal = Flags.isByVal();
2315
2316 // Promote the value if needed.
2317 switch (VA.getLocInfo()) {
2318 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2318)
;
2319 case CCValAssign::Full: break;
2320 case CCValAssign::SExt:
2321 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2322 break;
2323 case CCValAssign::ZExt:
2324 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2325 break;
2326 case CCValAssign::AExt:
2327 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2328 break;
2329 case CCValAssign::BCvt:
2330 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2331 break;
2332 }
2333
2334 // f16 arguments have their size extended to 4 bytes and passed as if they
2335 // had been copied to the LSBs of a 32-bit register.
2336 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2337 if (VA.needsCustom() &&
2338 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2339 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2340 } else {
2341 // f16 arguments could have been extended prior to argument lowering.
2342 // Mask them arguments if this is a CMSE nonsecure call.
2343 auto ArgVT = Outs[realArgIdx].ArgVT;
2344 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2345 auto LocBits = VA.getLocVT().getSizeInBits();
2346 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2347 SDValue Mask =
2348 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2349 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2350 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2351 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2352 }
2353 }
2354
2355 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2356 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2357 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2358 DAG.getConstant(0, dl, MVT::i32));
2359 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2360 DAG.getConstant(1, dl, MVT::i32));
2361
2362 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2363 StackPtr, MemOpChains, Flags);
2364
2365 VA = ArgLocs[++i]; // skip ahead to next loc
2366 if (VA.isRegLoc()) {
2367 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2368 StackPtr, MemOpChains, Flags);
2369 } else {
2370 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2370, __PRETTY_FUNCTION__))
;
2371
2372 MemOpChains.push_back(
2373 LowerMemOpCallTo(Chain, StackPtr, Op1, dl, DAG, VA, Flags));
2374 }
2375 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2376 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2377 StackPtr, MemOpChains, Flags);
2378 } else if (VA.isRegLoc()) {
2379 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2380 Outs[0].VT == MVT::i32) {
2381 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2382, __PRETTY_FUNCTION__))
2382 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2382, __PRETTY_FUNCTION__))
;
2383 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2384, __PRETTY_FUNCTION__))
2384 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2384, __PRETTY_FUNCTION__))
;
2385 isThisReturn = true;
2386 }
2387 const TargetOptions &Options = DAG.getTarget().Options;
2388 if (Options.EmitCallSiteInfo)
2389 CSInfo.emplace_back(VA.getLocReg(), i);
2390 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2391 } else if (isByVal) {
2392 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2392, __PRETTY_FUNCTION__))
;
2393 unsigned offset = 0;
2394
2395 // True if this byval aggregate will be split between registers
2396 // and memory.
2397 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2398 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2399
2400 if (CurByValIdx < ByValArgsCount) {
2401
2402 unsigned RegBegin, RegEnd;
2403 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2404
2405 EVT PtrVT =
2406 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2407 unsigned int i, j;
2408 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2409 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2410 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2411 SDValue Load =
2412 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2413 DAG.InferPtrAlign(AddArg));
2414 MemOpChains.push_back(Load.getValue(1));
2415 RegsToPass.push_back(std::make_pair(j, Load));
2416 }
2417
2418 // If parameter size outsides register area, "offset" value
2419 // helps us to calculate stack slot for remained part properly.
2420 offset = RegEnd - RegBegin;
2421
2422 CCInfo.nextInRegsParam();
2423 }
2424
2425 if (Flags.getByValSize() > 4*offset) {
2426 auto PtrVT = getPointerTy(DAG.getDataLayout());
2427 unsigned LocMemOffset = VA.getLocMemOffset();
2428 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2429 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2430 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2431 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2432 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2433 MVT::i32);
2434 SDValue AlignNode =
2435 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2436
2437 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2438 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2439 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2440 Ops));
2441 }
2442 } else if (!isTailCall) {
2443 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2443, __PRETTY_FUNCTION__))
;
2444
2445 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2446 dl, DAG, VA, Flags));
2447 }
2448 }
2449
2450 if (!MemOpChains.empty())
16
Taking true branch
2451 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2452
2453 // Build a sequence of copy-to-reg nodes chained together with token chain
2454 // and flag operands which copy the outgoing args into the appropriate regs.
2455 SDValue InFlag;
2456 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
17
Assuming 'i' is equal to 'e'
18
Loop condition is false. Execution continues on line 2465
2457 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2458 RegsToPass[i].second, InFlag);
2459 InFlag = Chain.getValue(1);
2460 }
2461
2462 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2463 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2464 // node so that legalize doesn't hack it.
2465 bool isDirect = false;
2466
2467 const TargetMachine &TM = getTargetMachine();
2468 const Module *Mod = MF.getFunction().getParent();
2469 const GlobalValue *GV = nullptr;
19
'GV' initialized to a null pointer value
2470 if (GlobalAddressSDNode *G
19.1
'G' is null
= dyn_cast<GlobalAddressSDNode>(Callee))
20
Taking false branch
2471 GV = G->getGlobal();
2472 bool isStub =
2473 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
21
Assuming the condition is false
2474
2475 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
22
Assuming the condition is true
2476 bool isLocalARMFunc = false;
2477 auto PtrVt = getPointerTy(DAG.getDataLayout());
2478
2479 if (Subtarget->genLongCalls()) {
23
Assuming the condition is false
24
Taking false branch
2480 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2481, __PRETTY_FUNCTION__))
2481 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2481, __PRETTY_FUNCTION__))
;
2482 // Handle a global address or an external symbol. If it's not one of
2483 // those, the target's already in a register, so we don't need to do
2484 // anything extra.
2485 if (isa<GlobalAddressSDNode>(Callee)) {
2486 // Create a constant pool entry for the callee address
2487 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2488 ARMConstantPoolValue *CPV =
2489 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2490
2491 // Get the address of the callee into a register
2492 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2493 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2494 Callee = DAG.getLoad(
2495 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2496 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2497 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2498 const char *Sym = S->getSymbol();
2499
2500 // Create a constant pool entry for the callee address
2501 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2502 ARMConstantPoolValue *CPV =
2503 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2504 ARMPCLabelIndex, 0);
2505 // Get the address of the callee into a register
2506 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2507 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2508 Callee = DAG.getLoad(
2509 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2510 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2511 }
2512 } else if (isa<GlobalAddressSDNode>(Callee)) {
25
Assuming 'Callee' is a 'GlobalAddressSDNode'
26
Taking true branch
2513 if (!PreferIndirect
26.1
'PreferIndirect' is false
) {
27
Taking true branch
2514 isDirect = true;
2515 bool isDef = GV->isStrongDefinitionForLinker();
28
Called C++ object pointer is null
2516
2517 // ARM call to a local ARM function is predicable.
2518 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2519 // tBX takes a register source operand.
2520 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2521 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2521, __PRETTY_FUNCTION__))
;
2522 Callee = DAG.getNode(
2523 ARMISD::WrapperPIC, dl, PtrVt,
2524 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2525 Callee = DAG.getLoad(
2526 PtrVt, dl, DAG.getEntryNode(), Callee,
2527 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2528 MachineMemOperand::MODereferenceable |
2529 MachineMemOperand::MOInvariant);
2530 } else if (Subtarget->isTargetCOFF()) {
2531 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2532, __PRETTY_FUNCTION__))
2532 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2532, __PRETTY_FUNCTION__))
;
2533 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2534 if (GV->hasDLLImportStorageClass())
2535 TargetFlags = ARMII::MO_DLLIMPORT;
2536 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2537 TargetFlags = ARMII::MO_COFFSTUB;
2538 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2539 TargetFlags);
2540 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2541 Callee =
2542 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2543 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2544 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2545 } else {
2546 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2547 }
2548 }
2549 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2550 isDirect = true;
2551 // tBX takes a register source operand.
2552 const char *Sym = S->getSymbol();
2553 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2554 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2555 ARMConstantPoolValue *CPV =
2556 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2557 ARMPCLabelIndex, 4);
2558 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2559 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2560 Callee = DAG.getLoad(
2561 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2562 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2563 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2564 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2565 } else {
2566 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2567 }
2568 }
2569
2570 if (isCmseNSCall) {
2571 assert(!isARMFunc && !isDirect &&((!isARMFunc && !isDirect && "Cannot handle call to ARM function or direct call"
) ? static_cast<void> (0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2572, __PRETTY_FUNCTION__))
2572 "Cannot handle call to ARM function or direct call")((!isARMFunc && !isDirect && "Cannot handle call to ARM function or direct call"
) ? static_cast<void> (0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2572, __PRETTY_FUNCTION__))
;
2573 if (NumBytes > 0) {
2574 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2575 "call to non-secure function would "
2576 "require passing arguments on stack",
2577 dl.getDebugLoc());
2578 DAG.getContext()->diagnose(Diag);
2579 }
2580 if (isStructRet) {
2581 DiagnosticInfoUnsupported Diag(
2582 DAG.getMachineFunction().getFunction(),
2583 "call to non-secure function would return value through pointer",
2584 dl.getDebugLoc());
2585 DAG.getContext()->diagnose(Diag);
2586 }
2587 }
2588
2589 // FIXME: handle tail calls differently.
2590 unsigned CallOpc;
2591 if (Subtarget->isThumb()) {
2592 if (isCmseNSCall)
2593 CallOpc = ARMISD::tSECALL;
2594 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2595 CallOpc = ARMISD::CALL_NOLINK;
2596 else
2597 CallOpc = ARMISD::CALL;
2598 } else {
2599 if (!isDirect && !Subtarget->hasV5TOps())
2600 CallOpc = ARMISD::CALL_NOLINK;
2601 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2602 // Emit regular call when code size is the priority
2603 !Subtarget->hasMinSize())
2604 // "mov lr, pc; b _foo" to avoid confusing the RSP
2605 CallOpc = ARMISD::CALL_NOLINK;
2606 else
2607 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2608 }
2609
2610 std::vector<SDValue> Ops;
2611 Ops.push_back(Chain);
2612 Ops.push_back(Callee);
2613
2614 // Add argument registers to the end of the list so that they are known live
2615 // into the call.
2616 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2617 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2618 RegsToPass[i].second.getValueType()));
2619
2620 // Add a register mask operand representing the call-preserved registers.
2621 if (!isTailCall) {
2622 const uint32_t *Mask;
2623 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2624 if (isThisReturn) {
2625 // For 'this' returns, use the R0-preserving mask if applicable
2626 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2627 if (!Mask) {
2628 // Set isThisReturn to false if the calling convention is not one that
2629 // allows 'returned' to be modeled in this way, so LowerCallResult does
2630 // not try to pass 'this' straight through
2631 isThisReturn = false;
2632 Mask = ARI->getCallPreservedMask(MF, CallConv);
2633 }
2634 } else
2635 Mask = ARI->getCallPreservedMask(MF, CallConv);
2636
2637 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2637, __PRETTY_FUNCTION__))
;
2638 Ops.push_back(DAG.getRegisterMask(Mask));
2639 }
2640
2641 if (InFlag.getNode())
2642 Ops.push_back(InFlag);
2643
2644 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2645 if (isTailCall) {
2646 MF.getFrameInfo().setHasTailCall();
2647 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2648 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2649 return Ret;
2650 }
2651
2652 // Returns a chain and a flag for retval copy to use.
2653 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2654 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2655 InFlag = Chain.getValue(1);
2656 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2657
2658 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2659 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2660 if (!Ins.empty())
2661 InFlag = Chain.getValue(1);
2662
2663 // Handle result values, copying them out of physregs into vregs that we
2664 // return.
2665 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2666 InVals, isThisReturn,
2667 isThisReturn ? OutVals[0] : SDValue());
2668}
2669
2670/// HandleByVal - Every parameter *after* a byval parameter is passed
2671/// on the stack. Remember the next parameter register to allocate,
2672/// and then confiscate the rest of the parameter registers to insure
2673/// this.
2674void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2675 Align Alignment) const {
2676 // Byval (as with any stack) slots are always at least 4 byte aligned.
2677 Alignment = std::max(Alignment, Align(4));
2678
2679 unsigned Reg = State->AllocateReg(GPRArgRegs);
2680 if (!Reg)
2681 return;
2682
2683 unsigned AlignInRegs = Alignment.value() / 4;
2684 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2685 for (unsigned i = 0; i < Waste; ++i)
2686 Reg = State->AllocateReg(GPRArgRegs);
2687
2688 if (!Reg)
2689 return;
2690
2691 unsigned Excess = 4 * (ARM::R4 - Reg);
2692
2693 // Special case when NSAA != SP and parameter size greater than size of
2694 // all remained GPR regs. In that case we can't split parameter, we must
2695 // send it to stack. We also must set NCRN to R4, so waste all
2696 // remained registers.
2697 const unsigned NSAAOffset = State->getNextStackOffset();
2698 if (NSAAOffset != 0 && Size > Excess) {
2699 while (State->AllocateReg(GPRArgRegs))
2700 ;
2701 return;
2702 }
2703
2704 // First register for byval parameter is the first register that wasn't
2705 // allocated before this method call, so it would be "reg".
2706 // If parameter is small enough to be saved in range [reg, r4), then
2707 // the end (first after last) register would be reg + param-size-in-regs,
2708 // else parameter would be splitted between registers and stack,
2709 // end register would be r4 in this case.
2710 unsigned ByValRegBegin = Reg;
2711 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2712 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2713 // Note, first register is allocated in the beginning of function already,
2714 // allocate remained amount of registers we need.
2715 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2716 State->AllocateReg(GPRArgRegs);
2717 // A byval parameter that is split between registers and memory needs its
2718 // size truncated here.
2719 // In the case where the entire structure fits in registers, we set the
2720 // size in memory to zero.
2721 Size = std::max<int>(Size - Excess, 0);
2722}
2723
2724/// MatchingStackOffset - Return true if the given stack call argument is
2725/// already available in the same position (relatively) of the caller's
2726/// incoming argument stack.
2727static
2728bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2729 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2730 const TargetInstrInfo *TII) {
2731 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2732 int FI = std::numeric_limits<int>::max();
2733 if (Arg.getOpcode() == ISD::CopyFromReg) {
2734 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2735 if (!Register::isVirtualRegister(VR))
2736 return false;
2737 MachineInstr *Def = MRI->getVRegDef(VR);
2738 if (!Def)
2739 return false;
2740 if (!Flags.isByVal()) {
2741 if (!TII->isLoadFromStackSlot(*Def, FI))
2742 return false;
2743 } else {
2744 return false;
2745 }
2746 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2747 if (Flags.isByVal())
2748 // ByVal argument is passed in as a pointer but it's now being
2749 // dereferenced. e.g.
2750 // define @foo(%struct.X* %A) {
2751 // tail call @bar(%struct.X* byval %A)
2752 // }
2753 return false;
2754 SDValue Ptr = Ld->getBasePtr();
2755 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2756 if (!FINode)
2757 return false;
2758 FI = FINode->getIndex();
2759 } else
2760 return false;
2761
2762 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2762, __PRETTY_FUNCTION__))
;
2763 if (!MFI.isFixedObjectIndex(FI))
2764 return false;
2765 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2766}
2767
2768/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2769/// for tail call optimization. Targets which want to do tail call
2770/// optimization should implement this function.
2771bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2772 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2773 bool isCalleeStructRet, bool isCallerStructRet,
2774 const SmallVectorImpl<ISD::OutputArg> &Outs,
2775 const SmallVectorImpl<SDValue> &OutVals,
2776 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2777 const bool isIndirect) const {
2778 MachineFunction &MF = DAG.getMachineFunction();
2779 const Function &CallerF = MF.getFunction();
2780 CallingConv::ID CallerCC = CallerF.getCallingConv();
2781
2782 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2782, __PRETTY_FUNCTION__))
;
2783
2784 // Indirect tail calls cannot be optimized for Thumb1 if the args
2785 // to the call take up r0-r3. The reason is that there are no legal registers
2786 // left to hold the pointer to the function to be called.
2787 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2788 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2789 return false;
2790
2791 // Look for obvious safe cases to perform tail call optimization that do not
2792 // require ABI changes. This is what gcc calls sibcall.
2793
2794 // Exception-handling functions need a special set of instructions to indicate
2795 // a return to the hardware. Tail-calling another function would probably
2796 // break this.
2797 if (CallerF.hasFnAttribute("interrupt"))
2798 return false;
2799
2800 // Also avoid sibcall optimization if either caller or callee uses struct
2801 // return semantics.
2802 if (isCalleeStructRet || isCallerStructRet)
2803 return false;
2804
2805 // Externally-defined functions with weak linkage should not be
2806 // tail-called on ARM when the OS does not support dynamic
2807 // pre-emption of symbols, as the AAELF spec requires normal calls
2808 // to undefined weak functions to be replaced with a NOP or jump to the
2809 // next instruction. The behaviour of branch instructions in this
2810 // situation (as used for tail calls) is implementation-defined, so we
2811 // cannot rely on the linker replacing the tail call with a return.
2812 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2813 const GlobalValue *GV = G->getGlobal();
2814 const Triple &TT = getTargetMachine().getTargetTriple();
2815 if (GV->hasExternalWeakLinkage() &&
2816 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2817 return false;
2818 }
2819
2820 // Check that the call results are passed in the same way.
2821 LLVMContext &C = *DAG.getContext();
2822 if (!CCState::resultsCompatible(
2823 getEffectiveCallingConv(CalleeCC, isVarArg),
2824 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
2825 CCAssignFnForReturn(CalleeCC, isVarArg),
2826 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
2827 return false;
2828 // The callee has to preserve all registers the caller needs to preserve.
2829 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2830 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2831 if (CalleeCC != CallerCC) {
2832 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2833 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2834 return false;
2835 }
2836
2837 // If Caller's vararg or byval argument has been split between registers and
2838 // stack, do not perform tail call, since part of the argument is in caller's
2839 // local frame.
2840 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2841 if (AFI_Caller->getArgRegsSaveSize())
2842 return false;
2843
2844 // If the callee takes no arguments then go on to check the results of the
2845 // call.
2846 if (!Outs.empty()) {
2847 // Check if stack adjustment is needed. For now, do not do this if any
2848 // argument is passed on the stack.
2849 SmallVector<CCValAssign, 16> ArgLocs;
2850 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2851 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2852 if (CCInfo.getNextStackOffset()) {
2853 // Check if the arguments are already laid out in the right way as
2854 // the caller's fixed stack objects.
2855 MachineFrameInfo &MFI = MF.getFrameInfo();
2856 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2857 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2858 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2859 i != e;
2860 ++i, ++realArgIdx) {
2861 CCValAssign &VA = ArgLocs[i];
2862 EVT RegVT = VA.getLocVT();
2863 SDValue Arg = OutVals[realArgIdx];
2864 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2865 if (VA.getLocInfo() == CCValAssign::Indirect)
2866 return false;
2867 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
2868 // f64 and vector types are split into multiple registers or
2869 // register/stack-slot combinations. The types will not match
2870 // the registers; give up on memory f64 refs until we figure
2871 // out what to do about this.
2872 if (!VA.isRegLoc())
2873 return false;
2874 if (!ArgLocs[++i].isRegLoc())
2875 return false;
2876 if (RegVT == MVT::v2f64) {
2877 if (!ArgLocs[++i].isRegLoc())
2878 return false;
2879 if (!ArgLocs[++i].isRegLoc())
2880 return false;
2881 }
2882 } else if (!VA.isRegLoc()) {
2883 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2884 MFI, MRI, TII))
2885 return false;
2886 }
2887 }
2888 }
2889
2890 const MachineRegisterInfo &MRI = MF.getRegInfo();
2891 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2892 return false;
2893 }
2894
2895 return true;
2896}
2897
2898bool
2899ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2900 MachineFunction &MF, bool isVarArg,
2901 const SmallVectorImpl<ISD::OutputArg> &Outs,
2902 LLVMContext &Context) const {
2903 SmallVector<CCValAssign, 16> RVLocs;
2904 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2905 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2906}
2907
2908static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2909 const SDLoc &DL, SelectionDAG &DAG) {
2910 const MachineFunction &MF = DAG.getMachineFunction();
2911 const Function &F = MF.getFunction();
2912
2913 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2914
2915 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2916 // version of the "preferred return address". These offsets affect the return
2917 // instruction if this is a return from PL1 without hypervisor extensions.
2918 // IRQ/FIQ: +4 "subs pc, lr, #4"
2919 // SWI: 0 "subs pc, lr, #0"
2920 // ABORT: +4 "subs pc, lr, #4"
2921 // UNDEF: +4/+2 "subs pc, lr, #0"
2922 // UNDEF varies depending on where the exception came from ARM or Thumb
2923 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2924
2925 int64_t LROffset;
2926 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2927 IntKind == "ABORT")
2928 LROffset = 4;
2929 else if (IntKind == "SWI" || IntKind == "UNDEF")
2930 LROffset = 0;
2931 else
2932 report_fatal_error("Unsupported interrupt attribute. If present, value "
2933 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2934
2935 RetOps.insert(RetOps.begin() + 1,
2936 DAG.getConstant(LROffset, DL, MVT::i32, false));
2937
2938 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2939}
2940
2941SDValue
2942ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2943 bool isVarArg,
2944 const SmallVectorImpl<ISD::OutputArg> &Outs,
2945 const SmallVectorImpl<SDValue> &OutVals,
2946 const SDLoc &dl, SelectionDAG &DAG) const {
2947 // CCValAssign - represent the assignment of the return value to a location.
2948 SmallVector<CCValAssign, 16> RVLocs;
2949
2950 // CCState - Info about the registers and stack slots.
2951 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2952 *DAG.getContext());
2953
2954 // Analyze outgoing return values.
2955 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2956
2957 SDValue Flag;
2958 SmallVector<SDValue, 4> RetOps;
2959 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2960 bool isLittleEndian = Subtarget->isLittle();
2961
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2964 AFI->setReturnRegsCount(RVLocs.size());
2965
2966 // Report error if cmse entry function returns structure through first ptr arg.
2967 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
2968 // Note: using an empty SDLoc(), as the first line of the function is a
2969 // better place to report than the last line.
2970 DiagnosticInfoUnsupported Diag(
2971 DAG.getMachineFunction().getFunction(),
2972 "secure entry function would return value through pointer",
2973 SDLoc().getDebugLoc());
2974 DAG.getContext()->diagnose(Diag);
2975 }
2976
2977 // Copy the result values into the output registers.
2978 for (unsigned i = 0, realRVLocIdx = 0;
2979 i != RVLocs.size();
2980 ++i, ++realRVLocIdx) {
2981 CCValAssign &VA = RVLocs[i];
2982 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2982, __PRETTY_FUNCTION__))
;
2983
2984 SDValue Arg = OutVals[realRVLocIdx];
2985 bool ReturnF16 = false;
2986
2987 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2988 // Half-precision return values can be returned like this:
2989 //
2990 // t11 f16 = fadd ...
2991 // t12: i16 = bitcast t11
2992 // t13: i32 = zero_extend t12
2993 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2994 //
2995 // to avoid code generation for bitcasts, we simply set Arg to the node
2996 // that produces the f16 value, t11 in this case.
2997 //
2998 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2999 SDValue ZE = Arg.getOperand(0);
3000 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
3001 SDValue BC = ZE.getOperand(0);
3002 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
3003 Arg = BC.getOperand(0);
3004 ReturnF16 = true;
3005 }
3006 }
3007 }
3008 }
3009
3010 switch (VA.getLocInfo()) {
3011 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3011)
;
3012 case CCValAssign::Full: break;
3013 case CCValAssign::BCvt:
3014 if (!ReturnF16)
3015 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3016 break;
3017 }
3018
3019 // Mask f16 arguments if this is a CMSE nonsecure entry.
3020 auto RetVT = Outs[realRVLocIdx].ArgVT;
3021 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3022 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3023 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3024 } else {
3025 auto LocBits = VA.getLocVT().getSizeInBits();
3026 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3027 SDValue Mask =
3028 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3029 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3030 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3031 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3032 }
3033 }
3034
3035 if (VA.needsCustom() &&
3036 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3037 if (VA.getLocVT() == MVT::v2f64) {
3038 // Extract the first half and return it in two registers.
3039 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3040 DAG.getConstant(0, dl, MVT::i32));
3041 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3042 DAG.getVTList(MVT::i32, MVT::i32), Half);
3043
3044 Chain =
3045 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3046 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3047 Flag = Chain.getValue(1);
3048 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3049 VA = RVLocs[++i]; // skip ahead to next loc
3050 Chain =
3051 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3052 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3053 Flag = Chain.getValue(1);
3054 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3055 VA = RVLocs[++i]; // skip ahead to next loc
3056
3057 // Extract the 2nd half and fall through to handle it as an f64 value.
3058 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3059 DAG.getConstant(1, dl, MVT::i32));
3060 }
3061 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3062 // available.
3063 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3064 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3065 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3066 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3067 Flag = Chain.getValue(1);
3068 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3069 VA = RVLocs[++i]; // skip ahead to next loc
3070 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3071 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3072 } else
3073 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3074
3075 // Guarantee that all emitted copies are
3076 // stuck together, avoiding something bad.
3077 Flag = Chain.getValue(1);
3078 RetOps.push_back(DAG.getRegister(
3079 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3080 }
3081 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3082 const MCPhysReg *I =
3083 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3084 if (I) {
3085 for (; *I; ++I) {
3086 if (ARM::GPRRegClass.contains(*I))
3087 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3088 else if (ARM::DPRRegClass.contains(*I))
3089 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3090 else
3091 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3091)
;
3092 }
3093 }
3094
3095 // Update chain and glue.
3096 RetOps[0] = Chain;
3097 if (Flag.getNode())
3098 RetOps.push_back(Flag);
3099
3100 // CPUs which aren't M-class use a special sequence to return from
3101 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3102 // though we use "subs pc, lr, #N").
3103 //
3104 // M-class CPUs actually use a normal return sequence with a special
3105 // (hardware-provided) value in LR, so the normal code path works.
3106 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3107 !Subtarget->isMClass()) {
3108 if (Subtarget->isThumb1Only())
3109 report_fatal_error("interrupt attribute is not supported in Thumb1");
3110 return LowerInterruptReturn(RetOps, dl, DAG);
3111 }
3112
3113 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3114 ARMISD::RET_FLAG;
3115 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3116}
3117
3118bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3119 if (N->getNumValues() != 1)
3120 return false;
3121 if (!N->hasNUsesOfValue(1, 0))
3122 return false;
3123
3124 SDValue TCChain = Chain;
3125 SDNode *Copy = *N->use_begin();
3126 if (Copy->getOpcode() == ISD::CopyToReg) {
3127 // If the copy has a glue operand, we conservatively assume it isn't safe to
3128 // perform a tail call.
3129 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3130 return false;
3131 TCChain = Copy->getOperand(0);
3132 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3133 SDNode *VMov = Copy;
3134 // f64 returned in a pair of GPRs.
3135 SmallPtrSet<SDNode*, 2> Copies;
3136 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3137 UI != UE; ++UI) {
3138 if (UI->getOpcode() != ISD::CopyToReg)
3139 return false;
3140 Copies.insert(*UI);
3141 }
3142 if (Copies.size() > 2)
3143 return false;
3144
3145 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3146 UI != UE; ++UI) {
3147 SDValue UseChain = UI->getOperand(0);
3148 if (Copies.count(UseChain.getNode()))
3149 // Second CopyToReg
3150 Copy = *UI;
3151 else {
3152 // We are at the top of this chain.
3153 // If the copy has a glue operand, we conservatively assume it
3154 // isn't safe to perform a tail call.
3155 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
3156 return false;
3157 // First CopyToReg
3158 TCChain = UseChain;
3159 }
3160 }
3161 } else if (Copy->getOpcode() == ISD::BITCAST) {
3162 // f32 returned in a single GPR.
3163 if (!Copy->hasOneUse())
3164 return false;
3165 Copy = *Copy->use_begin();
3166 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3167 return false;
3168 // If the copy has a glue operand, we conservatively assume it isn't safe to
3169 // perform a tail call.
3170 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3171 return false;
3172 TCChain = Copy->getOperand(0);
3173 } else {
3174 return false;
3175 }
3176
3177 bool HasRet = false;
3178 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3179 UI != UE; ++UI) {
3180 if (UI->getOpcode() != ARMISD::RET_FLAG &&
3181 UI->getOpcode() != ARMISD::INTRET_FLAG)
3182 return false;
3183 HasRet = true;
3184 }
3185
3186 if (!HasRet)
3187 return false;
3188
3189 Chain = TCChain;
3190 return true;
3191}
3192
3193bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3194 if (!Subtarget->supportsTailCall())
3195 return false;
3196
3197 if (!CI->isTailCall())
3198 return false;
3199
3200 return true;
3201}
3202
3203// Trying to write a 64 bit value so need to split into two 32 bit values first,
3204// and pass the lower and high parts through.
3205static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3206 SDLoc DL(Op);
3207 SDValue WriteValue = Op->getOperand(2);
3208
3209 // This function is only supposed to be called for i64 type argument.
3210 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3211, __PRETTY_FUNCTION__))
3211 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3211, __PRETTY_FUNCTION__))
;
3212
3213 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3214 DAG.getConstant(0, DL, MVT::i32));
3215 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3216 DAG.getConstant(1, DL, MVT::i32));
3217 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3218 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3219}
3220
3221// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3222// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3223// one of the above mentioned nodes. It has to be wrapped because otherwise
3224// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3225// be used to form addressing mode. These wrapped nodes will be selected
3226// into MOVi.
3227SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3228 SelectionDAG &DAG) const {
3229 EVT PtrVT = Op.getValueType();
3230 // FIXME there is no actual debug info here
3231 SDLoc dl(Op);
3232 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3233 SDValue Res;
3234
3235 // When generating execute-only code Constant Pools must be promoted to the
3236 // global data section. It's a bit ugly that we can't share them across basic
3237 // blocks, but this way we guarantee that execute-only behaves correct with
3238 // position-independent addressing modes.
3239 if (Subtarget->genExecuteOnly()) {
3240 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3241 auto T = const_cast<Type*>(CP->getType());
3242 auto C = const_cast<Constant*>(CP->getConstVal());
3243 auto M = const_cast<Module*>(DAG.getMachineFunction().
3244 getFunction().getParent());
3245 auto GV = new GlobalVariable(
3246 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3247 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3248 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3249 Twine(AFI->createPICLabelUId())
3250 );
3251 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3252 dl, PtrVT);
3253 return LowerGlobalAddress(GA, DAG);
3254 }
3255
3256 if (CP->isMachineConstantPoolEntry())
3257 Res =
3258 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3259 else
3260 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3261 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3262}
3263
3264unsigned ARMTargetLowering::getJumpTableEncoding() const {
3265 return MachineJumpTableInfo::EK_Inline;
3266}
3267
3268SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3269 SelectionDAG &DAG) const {
3270 MachineFunction &MF = DAG.getMachineFunction();
3271 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3272 unsigned ARMPCLabelIndex = 0;
3273 SDLoc DL(Op);
3274 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3275 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3276 SDValue CPAddr;
3277 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3278 if (!IsPositionIndependent) {
3279 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3280 } else {
3281 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3282 ARMPCLabelIndex = AFI->createPICLabelUId();
3283 ARMConstantPoolValue *CPV =
3284 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3285 ARMCP::CPBlockAddress, PCAdj);
3286 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3287 }
3288 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3289 SDValue Result = DAG.getLoad(
3290 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3291 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3292 if (!IsPositionIndependent)
3293 return Result;
3294 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3295 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3296}
3297
3298/// Convert a TLS address reference into the correct sequence of loads
3299/// and calls to compute the variable's address for Darwin, and return an
3300/// SDValue containing the final node.
3301
3302/// Darwin only has one TLS scheme which must be capable of dealing with the
3303/// fully general situation, in the worst case. This means:
3304/// + "extern __thread" declaration.
3305/// + Defined in a possibly unknown dynamic library.
3306///
3307/// The general system is that each __thread variable has a [3 x i32] descriptor
3308/// which contains information used by the runtime to calculate the address. The
3309/// only part of this the compiler needs to know about is the first word, which
3310/// contains a function pointer that must be called with the address of the
3311/// entire descriptor in "r0".
3312///
3313/// Since this descriptor may be in a different unit, in general access must
3314/// proceed along the usual ARM rules. A common sequence to produce is:
3315///
3316/// movw rT1, :lower16:_var$non_lazy_ptr
3317/// movt rT1, :upper16:_var$non_lazy_ptr
3318/// ldr r0, [rT1]
3319/// ldr rT2, [r0]
3320/// blx rT2
3321/// [...address now in r0...]
3322SDValue
3323ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3324 SelectionDAG &DAG) const {
3325 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3326, __PRETTY_FUNCTION__))
3326 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3326, __PRETTY_FUNCTION__))
;
3327 SDLoc DL(Op);
3328
3329 // First step is to get the address of the actua global symbol. This is where
3330 // the TLS descriptor lives.
3331 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3332
3333 // The first entry in the descriptor is a function pointer that we must call
3334 // to obtain the address of the variable.
3335 SDValue Chain = DAG.getEntryNode();
3336 SDValue FuncTLVGet = DAG.getLoad(
3337 MVT::i32, DL, Chain, DescAddr,
3338 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3339 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3340 MachineMemOperand::MOInvariant);
3341 Chain = FuncTLVGet.getValue(1);
3342
3343 MachineFunction &F = DAG.getMachineFunction();
3344 MachineFrameInfo &MFI = F.getFrameInfo();
3345 MFI.setAdjustsStack(true);
3346
3347 // TLS calls preserve all registers except those that absolutely must be
3348 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3349 // silly).
3350 auto TRI =
3351 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3352 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3353 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3354
3355 // Finally, we can make the call. This is just a degenerate version of a
3356 // normal AArch64 call node: r0 takes the address of the descriptor, and
3357 // returns the address of the variable in this thread.
3358 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3359 Chain =
3360 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3361 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3362 DAG.getRegisterMask(Mask), Chain.getValue(1));
3363 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3364}
3365
3366SDValue
3367ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3368 SelectionDAG &DAG) const {
3369 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3369, __PRETTY_FUNCTION__))
;
3370
3371 SDValue Chain = DAG.getEntryNode();
3372 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3373 SDLoc DL(Op);
3374
3375 // Load the current TEB (thread environment block)
3376 SDValue Ops[] = {Chain,
3377 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3378 DAG.getTargetConstant(15, DL, MVT::i32),
3379 DAG.getTargetConstant(0, DL, MVT::i32),
3380 DAG.getTargetConstant(13, DL, MVT::i32),
3381 DAG.getTargetConstant(0, DL, MVT::i32),
3382 DAG.getTargetConstant(2, DL, MVT::i32)};
3383 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3384 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3385
3386 SDValue TEB = CurrentTEB.getValue(0);
3387 Chain = CurrentTEB.getValue(1);
3388
3389 // Load the ThreadLocalStoragePointer from the TEB
3390 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3391 SDValue TLSArray =
3392 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3393 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3394
3395 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3396 // offset into the TLSArray.
3397
3398 // Load the TLS index from the C runtime
3399 SDValue TLSIndex =
3400 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3401 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3402 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3403
3404 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3405 DAG.getConstant(2, DL, MVT::i32));
3406 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3407 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3408 MachinePointerInfo());
3409
3410 // Get the offset of the start of the .tls section (section base)
3411 const auto *GA = cast<GlobalAddressSDNode>(Op);
3412 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3413 SDValue Offset = DAG.getLoad(
3414 PtrVT, DL, Chain,
3415 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3416 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3417 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3418
3419 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3420}
3421
3422// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3423SDValue
3424ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3425 SelectionDAG &DAG) const {
3426 SDLoc dl(GA);
3427 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3428 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3429 MachineFunction &MF = DAG.getMachineFunction();
3430 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3431 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3432 ARMConstantPoolValue *CPV =
3433 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3434 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3435 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3436 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3437 Argument = DAG.getLoad(
3438 PtrVT, dl, DAG.getEntryNode(), Argument,
3439 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3440 SDValue Chain = Argument.getValue(1);
3441
3442 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3443 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3444
3445 // call __tls_get_addr.
3446 ArgListTy Args;
3447 ArgListEntry Entry;
3448 Entry.Node = Argument;
3449 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3450 Args.push_back(Entry);
3451
3452 // FIXME: is there useful debug info available here?
3453 TargetLowering::CallLoweringInfo CLI(DAG);
3454 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3455 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3456 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3457
3458 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3459 return CallResult.first;
3460}
3461
3462// Lower ISD::GlobalTLSAddress using the "initial exec" or
3463// "local exec" model.
3464SDValue
3465ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3466 SelectionDAG &DAG,
3467 TLSModel::Model model) const {
3468 const GlobalValue *GV = GA->getGlobal();
3469 SDLoc dl(GA);
3470 SDValue Offset;
3471 SDValue Chain = DAG.getEntryNode();
3472 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3473 // Get the Thread Pointer
3474 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3475
3476 if (model == TLSModel::InitialExec) {
3477 MachineFunction &MF = DAG.getMachineFunction();
3478 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3479 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3480 // Initial exec model.
3481 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3482 ARMConstantPoolValue *CPV =
3483 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3484 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3485 true);
3486 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3487 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3488 Offset = DAG.getLoad(
3489 PtrVT, dl, Chain, Offset,
3490 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3491 Chain = Offset.getValue(1);
3492
3493 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3494 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3495
3496 Offset = DAG.getLoad(
3497 PtrVT, dl, Chain, Offset,
3498 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3499 } else {
3500 // local exec model
3501 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3501, __PRETTY_FUNCTION__))
;
3502 ARMConstantPoolValue *CPV =
3503 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3504 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3505 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3506 Offset = DAG.getLoad(
3507 PtrVT, dl, Chain, Offset,
3508 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3509 }
3510
3511 // The address of the thread local variable is the add of the thread
3512 // pointer with the offset of the variable.
3513 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3514}
3515
3516SDValue
3517ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3518 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3519 if (DAG.getTarget().useEmulatedTLS())
3520 return LowerToTLSEmulatedModel(GA, DAG);
3521
3522 if (Subtarget->isTargetDarwin())
3523 return LowerGlobalTLSAddressDarwin(Op, DAG);
3524
3525 if (Subtarget->isTargetWindows())
3526 return LowerGlobalTLSAddressWindows(Op, DAG);
3527
3528 // TODO: implement the "local dynamic" model
3529 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3529, __PRETTY_FUNCTION__))
;
3530 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3531
3532 switch (model) {
3533 case TLSModel::GeneralDynamic:
3534 case TLSModel::LocalDynamic:
3535 return LowerToTLSGeneralDynamicModel(GA, DAG);
3536 case TLSModel::InitialExec:
3537 case TLSModel::LocalExec:
3538 return LowerToTLSExecModels(GA, DAG, model);
3539 }
3540 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3540)
;
3541}
3542
3543/// Return true if all users of V are within function F, looking through
3544/// ConstantExprs.
3545static bool allUsersAreInFunction(const Value *V, const Function *F) {
3546 SmallVector<const User*,4> Worklist;
3547 for (auto *U : V->users())
3548 Worklist.push_back(U);
3549 while (!Worklist.empty()) {
3550 auto *U = Worklist.pop_back_val();
3551 if (isa<ConstantExpr>(U)) {
3552 for (auto *UU : U->users())
3553 Worklist.push_back(UU);
3554 continue;
3555 }
3556
3557 auto *I = dyn_cast<Instruction>(U);
3558 if (!I || I->getParent()->getParent() != F)
3559 return false;
3560 }
3561 return true;
3562}
3563
3564static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3565 const GlobalValue *GV, SelectionDAG &DAG,
3566 EVT PtrVT, const SDLoc &dl) {
3567 // If we're creating a pool entry for a constant global with unnamed address,
3568 // and the global is small enough, we can emit it inline into the constant pool
3569 // to save ourselves an indirection.
3570 //
3571 // This is a win if the constant is only used in one function (so it doesn't
3572 // need to be duplicated) or duplicating the constant wouldn't increase code
3573 // size (implying the constant is no larger than 4 bytes).
3574 const Function &F = DAG.getMachineFunction().getFunction();
3575
3576 // We rely on this decision to inline being idemopotent and unrelated to the
3577 // use-site. We know that if we inline a variable at one use site, we'll
3578 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3579 // doesn't know about this optimization, so bail out if it's enabled else
3580 // we could decide to inline here (and thus never emit the GV) but require
3581 // the GV from fast-isel generated code.
3582 if (!EnableConstpoolPromotion ||
3583 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3584 return SDValue();
3585
3586 auto *GVar = dyn_cast<GlobalVariable>(GV);
3587 if (!GVar || !GVar->hasInitializer() ||
3588 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3589 !GVar->hasLocalLinkage())
3590 return SDValue();
3591
3592 // If we inline a value that contains relocations, we move the relocations
3593 // from .data to .text. This is not allowed in position-independent code.
3594 auto *Init = GVar->getInitializer();
3595 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3596 Init->needsRelocation())
3597 return SDValue();
3598
3599 // The constant islands pass can only really deal with alignment requests
3600 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3601 // any type wanting greater alignment requirements than 4 bytes. We also
3602 // can only promote constants that are multiples of 4 bytes in size or
3603 // are paddable to a multiple of 4. Currently we only try and pad constants
3604 // that are strings for simplicity.
3605 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3606 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3607 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3608 unsigned RequiredPadding = 4 - (Size % 4);
3609 bool PaddingPossible =
3610 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3611 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3612 Size == 0)
3613 return SDValue();
3614
3615 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3616 MachineFunction &MF = DAG.getMachineFunction();
3617 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3618
3619 // We can't bloat the constant pool too much, else the ConstantIslands pass
3620 // may fail to converge. If we haven't promoted this global yet (it may have
3621 // multiple uses), and promoting it would increase the constant pool size (Sz
3622 // > 4), ensure we have space to do so up to MaxTotal.
3623 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3624 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3625 ConstpoolPromotionMaxTotal)
3626 return SDValue();
3627
3628 // This is only valid if all users are in a single function; we can't clone
3629 // the constant in general. The LLVM IR unnamed_addr allows merging
3630 // constants, but not cloning them.
3631 //
3632 // We could potentially allow cloning if we could prove all uses of the
3633 // constant in the current function don't care about the address, like
3634 // printf format strings. But that isn't implemented for now.
3635 if (!allUsersAreInFunction(GVar, &F))
3636 return SDValue();
3637
3638 // We're going to inline this global. Pad it out if needed.
3639 if (RequiredPadding != 4) {
3640 StringRef S = CDAInit->getAsString();
3641
3642 SmallVector<uint8_t,16> V(S.size());
3643 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3644 while (RequiredPadding--)
3645 V.push_back(0);
3646 Init = ConstantDataArray::get(*DAG.getContext(), V);
3647 }
3648
3649 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3650 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3651 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3652 AFI->markGlobalAsPromotedToConstantPool(GVar);
3653 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3654 PaddedSize - 4);
3655 }
3656 ++NumConstpoolPromoted;
3657 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3658}
3659
3660bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3661 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3662 if (!(GV = GA->getBaseObject()))
3663 return false;
3664 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3665 return V->isConstant();
3666 return isa<Function>(GV);
3667}
3668
3669SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3670 SelectionDAG &DAG) const {
3671 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3672 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3672)
;
3673 case Triple::COFF:
3674 return LowerGlobalAddressWindows(Op, DAG);
3675 case Triple::ELF:
3676 return LowerGlobalAddressELF(Op, DAG);
3677 case Triple::MachO:
3678 return LowerGlobalAddressDarwin(Op, DAG);
3679 }
3680}
3681
3682SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3683 SelectionDAG &DAG) const {
3684 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3685 SDLoc dl(Op);
3686 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3687 const TargetMachine &TM = getTargetMachine();
3688 bool IsRO = isReadOnly(GV);
3689
3690 // promoteToConstantPool only if not generating XO text section
3691 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3692 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3693 return V;
3694
3695 if (isPositionIndependent()) {
3696 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3697 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3698 UseGOT_PREL ? ARMII::MO_GOT : 0);
3699 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3700 if (UseGOT_PREL)
3701 Result =
3702 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3703 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3704 return Result;
3705 } else if (Subtarget->isROPI() && IsRO) {
3706 // PC-relative.
3707 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3708 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3709 return Result;
3710 } else if (Subtarget->isRWPI() && !IsRO) {
3711 // SB-relative.
3712 SDValue RelAddr;
3713 if (Subtarget->useMovt()) {
3714 ++NumMovwMovt;
3715 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3716 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3717 } else { // use literal pool for address constant
3718 ARMConstantPoolValue *CPV =
3719 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3720 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3721 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3722 RelAddr = DAG.getLoad(
3723 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3724 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3725 }
3726 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3727 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3728 return Result;
3729 }
3730
3731 // If we have T2 ops, we can materialize the address directly via movt/movw
3732 // pair. This is always cheaper.
3733 if (Subtarget->useMovt()) {
3734 ++NumMovwMovt;
3735 // FIXME: Once remat is capable of dealing with instructions with register
3736 // operands, expand this into two nodes.
3737 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3738 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3739 } else {
3740 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3741 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3742 return DAG.getLoad(
3743 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3744 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3745 }
3746}
3747
3748SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3749 SelectionDAG &DAG) const {
3750 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3751, __PRETTY_FUNCTION__))
3751 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3751, __PRETTY_FUNCTION__))
;
3752 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3753 SDLoc dl(Op);
3754 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3755
3756 if (Subtarget->useMovt())
3757 ++NumMovwMovt;
3758
3759 // FIXME: Once remat is capable of dealing with instructions with register
3760 // operands, expand this into multiple nodes
3761 unsigned Wrapper =
3762 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3763
3764 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3765 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3766
3767 if (Subtarget->isGVIndirectSymbol(GV))
3768 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3769 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3770 return Result;
3771}
3772
3773SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3774 SelectionDAG &DAG) const {
3775 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3775, __PRETTY_FUNCTION__))
;
3776 assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3777, __PRETTY_FUNCTION__))
3777 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3777, __PRETTY_FUNCTION__))
;
3778 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3779, __PRETTY_FUNCTION__))
3779 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3779, __PRETTY_FUNCTION__))
;
3780
3781 const TargetMachine &TM = getTargetMachine();
3782 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3783 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3784 if (GV->hasDLLImportStorageClass())
3785 TargetFlags = ARMII::MO_DLLIMPORT;
3786 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3787 TargetFlags = ARMII::MO_COFFSTUB;
3788 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3789 SDValue Result;
3790 SDLoc DL(Op);
3791
3792 ++NumMovwMovt;
3793
3794 // FIXME: Once remat is capable of dealing with instructions with register
3795 // operands, expand this into two nodes.
3796 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3797 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3798 TargetFlags));
3799 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3800 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3801 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3802 return Result;
3803}
3804
3805SDValue
3806ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3807 SDLoc dl(Op);
3808 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3809 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3810 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3811 Op.getOperand(1), Val);
3812}
3813
3814SDValue
3815ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3816 SDLoc dl(Op);
3817 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3818 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3819}
3820
3821SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3822 SelectionDAG &DAG) const {
3823 SDLoc dl(Op);
3824 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3825 Op.getOperand(0));
3826}
3827
3828SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3829 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3830 unsigned IntNo =
3831 cast<ConstantSDNode>(
3832 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3833 ->getZExtValue();
3834 switch (IntNo) {
3835 default:
3836 return SDValue(); // Don't custom lower most intrinsics.
3837 case Intrinsic::arm_gnu_eabi_mcount: {
3838 MachineFunction &MF = DAG.getMachineFunction();
3839 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3840 SDLoc dl(Op);
3841 SDValue Chain = Op.getOperand(0);
3842 // call "\01__gnu_mcount_nc"
3843 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3844 const uint32_t *Mask =
3845 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3846 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3846, __PRETTY_FUNCTION__))
;
3847 // Mark LR an implicit live-in.
3848 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3849 SDValue ReturnAddress =
3850 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3851 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3852 SDValue Callee =
3853 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3854 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3855 if (Subtarget->isThumb())
3856 return SDValue(
3857 DAG.getMachineNode(
3858 ARM::tBL_PUSHLR, dl, ResultTys,
3859 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3860 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3861 0);
3862 return SDValue(
3863 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3864 {ReturnAddress, Callee, RegisterMask, Chain}),
3865 0);
3866 }
3867 }
3868}
3869
3870SDValue
3871ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3872 const ARMSubtarget *Subtarget) const {
3873 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3874 SDLoc dl(Op);
3875 switch (IntNo) {
3876 default: return SDValue(); // Don't custom lower most intrinsics.
3877 case Intrinsic::thread_pointer: {
3878 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3879 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3880 }
3881 case Intrinsic::arm_cls: {
3882 const SDValue &Operand = Op.getOperand(1);
3883 const EVT VTy = Op.getValueType();
3884 SDValue SRA =
3885 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3886 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3887 SDValue SHL =
3888 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3889 SDValue OR =
3890 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3891 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3892 return Result;
3893 }
3894 case Intrinsic::arm_cls64: {
3895 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
3896 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
3897 const SDValue &Operand = Op.getOperand(1);
3898 const EVT VTy = Op.getValueType();
3899
3900 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3901 DAG.getConstant(1, dl, VTy));
3902 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3903 DAG.getConstant(0, dl, VTy));
3904 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
3905 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
3906 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
3907 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
3908 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
3909 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
3910 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
3911 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3912 SDValue CheckLo =
3913 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3914 SDValue HiIsZero =
3915 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
3916 SDValue AdjustedLo =
3917 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
3918 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
3919 SDValue Result =
3920 DAG.getSelect(dl, VTy, CheckLo,
3921 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
3922 return Result;
3923 }
3924 case Intrinsic::eh_sjlj_lsda: {
3925 MachineFunction &MF = DAG.getMachineFunction();
3926 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3927 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3928 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3929 SDValue CPAddr;
3930 bool IsPositionIndependent = isPositionIndependent();
3931 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3932 ARMConstantPoolValue *CPV =
3933 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3934 ARMCP::CPLSDA, PCAdj);
3935 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3936 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3937 SDValue Result = DAG.getLoad(
3938 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3939 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3940
3941 if (IsPositionIndependent) {
3942 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3943 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3944 }
3945 return Result;
3946 }
3947 case Intrinsic::arm_neon_vabs:
3948 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3949 Op.getOperand(1));
3950 case Intrinsic::arm_neon_vmulls:
3951 case Intrinsic::arm_neon_vmullu: {
3952 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3953 ? ARMISD::VMULLs : ARMISD::VMULLu;
3954 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3955 Op.getOperand(1), Op.getOperand(2));
3956 }
3957 case Intrinsic::arm_neon_vminnm:
3958 case Intrinsic::arm_neon_vmaxnm: {
3959 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3960 ? ISD::FMINNUM : ISD::FMAXNUM;
3961 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3962 Op.getOperand(1), Op.getOperand(2));
3963 }
3964 case Intrinsic::arm_neon_vminu:
3965 case Intrinsic::arm_neon_vmaxu: {
3966 if (Op.getValueType().isFloatingPoint())
3967 return SDValue();
3968 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3969 ? ISD::UMIN : ISD::UMAX;
3970 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3971 Op.getOperand(1), Op.getOperand(2));
3972 }
3973 case Intrinsic::arm_neon_vmins:
3974 case Intrinsic::arm_neon_vmaxs: {
3975 // v{min,max}s is overloaded between signed integers and floats.
3976 if (!Op.getValueType().isFloatingPoint()) {
3977 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3978 ? ISD::SMIN : ISD::SMAX;
3979 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3980 Op.getOperand(1), Op.getOperand(2));
3981 }
3982 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3983 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3984 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3985 Op.getOperand(1), Op.getOperand(2));
3986 }
3987 case Intrinsic::arm_neon_vtbl1:
3988 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3989 Op.getOperand(1), Op.getOperand(2));
3990 case Intrinsic::arm_neon_vtbl2:
3991 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3992 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3993 case Intrinsic::arm_mve_pred_i2v:
3994 case Intrinsic::arm_mve_pred_v2i:
3995 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
3996 Op.getOperand(1));
3997 case Intrinsic::arm_mve_vreinterpretq:
3998 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
3999 Op.getOperand(1));
4000 case Intrinsic::arm_mve_lsll:
4001 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
4002 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4003 case Intrinsic::arm_mve_asrl:
4004 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
4005 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
4006 }
4007}
4008
4009static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4010 const ARMSubtarget *Subtarget) {
4011 SDLoc dl(Op);
4012 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4013 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4014 if (SSID == SyncScope::SingleThread)
4015 return Op;
4016
4017 if (!Subtarget->hasDataBarrier()) {
4018 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4019 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4020 // here.
4021 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4022, __PRETTY_FUNCTION__))
4022 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4022, __PRETTY_FUNCTION__))
;
4023 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4024 DAG.getConstant(0, dl, MVT::i32));
4025 }
4026
4027 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4028 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4029 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4030 if (Subtarget->isMClass()) {
4031 // Only a full system barrier exists in the M-class architectures.
4032 Domain = ARM_MB::SY;
4033 } else if (Subtarget->preferISHSTBarriers() &&
4034 Ord == AtomicOrdering::Release) {
4035 // Swift happens to implement ISHST barriers in a way that's compatible with
4036 // Release semantics but weaker than ISH so we'd be fools not to use
4037 // it. Beware: other processors probably don't!
4038 Domain = ARM_MB::ISHST;
4039 }
4040
4041 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4042 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4043 DAG.getConstant(Domain, dl, MVT::i32));
4044}
4045
4046static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4047 const ARMSubtarget *Subtarget) {
4048 // ARM pre v5TE and Thumb1 does not have preload instructions.
4049 if (!(Subtarget->isThumb2() ||
4050 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4051 // Just preserve the chain.
4052 return Op.getOperand(0);
4053
4054 SDLoc dl(Op);
4055 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4056 if (!isRead &&
4057 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4058 // ARMv7 with MP extension has PLDW.
4059 return Op.getOperand(0);
4060
4061 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4062 if (Subtarget->isThumb()) {
4063 // Invert the bits.
4064 isRead = ~isRead & 1;
4065 isData = ~isData & 1;
4066 }
4067
4068 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4069 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4070 DAG.getConstant(isData, dl, MVT::i32));
4071}
4072
4073static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4074 MachineFunction &MF = DAG.getMachineFunction();
4075 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4076
4077 // vastart just stores the address of the VarArgsFrameIndex slot into the
4078 // memory location argument.
4079 SDLoc dl(Op);
4080 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4081 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4082 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4083 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4084 MachinePointerInfo(SV));
4085}
4086
4087SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4088 CCValAssign &NextVA,
4089 SDValue &Root,
4090 SelectionDAG &DAG,
4091 const SDLoc &dl) const {
4092 MachineFunction &MF = DAG.getMachineFunction();
4093 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4094
4095 const TargetRegisterClass *RC;
4096 if (AFI->isThumb1OnlyFunction())
4097 RC = &ARM::tGPRRegClass;
4098 else
4099 RC = &ARM::GPRRegClass;
4100
4101 // Transform the arguments stored in physical registers into virtual ones.
4102 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4103 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4104
4105 SDValue ArgValue2;
4106 if (NextVA.isMemLoc()) {
4107 MachineFrameInfo &MFI = MF.getFrameInfo();
4108 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4109
4110 // Create load node to retrieve arguments from the stack.
4111 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4112 ArgValue2 = DAG.getLoad(
4113 MVT::i32, dl, Root, FIN,
4114 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4115 } else {
4116 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4117 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4118 }
4119 if (!Subtarget->isLittle())
4120 std::swap (ArgValue, ArgValue2);
4121 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4122}
4123
4124// The remaining GPRs hold either the beginning of variable-argument
4125// data, or the beginning of an aggregate passed by value (usually
4126// byval). Either way, we allocate stack slots adjacent to the data
4127// provided by our caller, and store the unallocated registers there.
4128// If this is a variadic function, the va_list pointer will begin with
4129// these values; otherwise, this reassembles a (byval) structure that
4130// was split between registers and memory.
4131// Return: The frame index registers were stored into.
4132int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4133 const SDLoc &dl, SDValue &Chain,
4134 const Value *OrigArg,
4135 unsigned InRegsParamRecordIdx,
4136 int ArgOffset, unsigned ArgSize) const {
4137 // Currently, two use-cases possible:
4138 // Case #1. Non-var-args function, and we meet first byval parameter.
4139 // Setup first unallocated register as first byval register;
4140 // eat all remained registers
4141 // (these two actions are performed by HandleByVal method).
4142 // Then, here, we initialize stack frame with
4143 // "store-reg" instructions.
4144 // Case #2. Var-args function, that doesn't contain byval parameters.
4145 // The same: eat all remained unallocated registers,
4146 // initialize stack frame.
4147
4148 MachineFunction &MF = DAG.getMachineFunction();
4149 MachineFrameInfo &MFI = MF.getFrameInfo();
4150 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4151 unsigned RBegin, REnd;
4152 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4153 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4154 } else {
4155 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4156 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4157 REnd = ARM::R4;
4158 }
4159
4160 if (REnd != RBegin)
4161 ArgOffset = -4 * (ARM::R4 - RBegin);
4162
4163 auto PtrVT = getPointerTy(DAG.getDataLayout());
4164 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4165 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4166
4167 SmallVector<SDValue, 4> MemOps;
4168 const TargetRegisterClass *RC =
4169 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4170
4171 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4172 unsigned VReg = MF.addLiveIn(Reg, RC);
4173 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4174 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4175 MachinePointerInfo(OrigArg, 4 * i));
4176 MemOps.push_back(Store);
4177 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4178 }
4179
4180 if (!MemOps.empty())
4181 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4182 return FrameIndex;
4183}
4184
4185// Setup stack frame, the va_list pointer will start from.
4186void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4187 const SDLoc &dl, SDValue &Chain,
4188 unsigned ArgOffset,
4189 unsigned TotalArgRegsSaveSize,
4190 bool ForceMutable) const {
4191 MachineFunction &MF = DAG.getMachineFunction();
4192 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4193
4194 // Try to store any remaining integer argument regs
4195 // to their spots on the stack so that they may be loaded by dereferencing
4196 // the result of va_next.
4197 // If there is no regs to be stored, just point address after last
4198 // argument passed via stack.
4199 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4200 CCInfo.getInRegsParamsCount(),
4201 CCInfo.getNextStackOffset(),
4202 std::max(4U, TotalArgRegsSaveSize));
4203 AFI->setVarArgsFrameIndex(FrameIndex);
4204}
4205
4206bool ARMTargetLowering::splitValueIntoRegisterParts(
4207 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4208 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4209 bool IsABIRegCopy = CC.hasValue();
4210 EVT ValueVT = Val.getValueType();
4211 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4212 PartVT == MVT::f32) {
4213 unsigned ValueBits = ValueVT.getSizeInBits();
4214 unsigned PartBits = PartVT.getSizeInBits();
4215 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4216 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4217 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4218 Parts[0] = Val;
4219 return true;
4220 }
4221 return false;
4222}
4223
4224SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4225 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4226 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4227 bool IsABIRegCopy = CC.hasValue();
4228 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4229 PartVT == MVT::f32) {
4230 unsigned ValueBits = ValueVT.getSizeInBits();
4231 unsigned PartBits = PartVT.getSizeInBits();
4232 SDValue Val = Parts[0];
4233
4234 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4235 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4236 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4237 return Val;
4238 }
4239 return SDValue();
4240}
4241
4242SDValue ARMTargetLowering::LowerFormalArguments(
4243 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4244 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4245 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4246 MachineFunction &MF = DAG.getMachineFunction();
4247 MachineFrameInfo &MFI = MF.getFrameInfo();
4248
4249 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4250
4251 // Assign locations to all of the incoming arguments.
4252 SmallVector<CCValAssign, 16> ArgLocs;
4253 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4254 *DAG.getContext());
4255 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4256
4257 SmallVector<SDValue, 16> ArgValues;
4258 SDValue ArgValue;
4259 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4260 unsigned CurArgIdx = 0;
4261
4262 // Initially ArgRegsSaveSize is zero.
4263 // Then we increase this value each time we meet byval parameter.
4264 // We also increase this value in case of varargs function.
4265 AFI->setArgRegsSaveSize(0);
4266
4267 // Calculate the amount of stack space that we need to allocate to store
4268 // byval and variadic arguments that are passed in registers.
4269 // We need to know this before we allocate the first byval or variadic
4270 // argument, as they will be allocated a stack slot below the CFA (Canonical
4271 // Frame Address, the stack pointer at entry to the function).
4272 unsigned ArgRegBegin = ARM::R4;
4273 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4274 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4275 break;
4276
4277 CCValAssign &VA = ArgLocs[i];
4278 unsigned Index = VA.getValNo();
4279 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4280 if (!Flags.isByVal())
4281 continue;
4282
4283 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4283, __PRETTY_FUNCTION__))
;
4284 unsigned RBegin, REnd;
4285 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4286 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4287
4288 CCInfo.nextInRegsParam();
4289 }
4290 CCInfo.rewindByValRegsInfo();
4291
4292 int lastInsIndex = -1;
4293 if (isVarArg && MFI.hasVAStart()) {
4294 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4295 if (RegIdx != array_lengthof(GPRArgRegs))
4296 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4297 }
4298
4299 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4300 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4301 auto PtrVT = getPointerTy(DAG.getDataLayout());
4302
4303 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4304 CCValAssign &VA = ArgLocs[i];
4305 if (Ins[VA.getValNo()].isOrigArg()) {
4306 std::advance(CurOrigArg,
4307 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4308 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4309 }
4310 // Arguments stored in registers.
4311 if (VA.isRegLoc()) {
4312 EVT RegVT = VA.getLocVT();
4313
4314 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4315 // f64 and vector types are split up into multiple registers or
4316 // combinations of registers and stack slots.
4317 SDValue ArgValue1 =
4318 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4319 VA = ArgLocs[++i]; // skip ahead to next loc
4320 SDValue ArgValue2;
4321 if (VA.isMemLoc()) {
4322 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4323 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4324 ArgValue2 = DAG.getLoad(
4325 MVT::f64, dl, Chain, FIN,
4326 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4327 } else {
4328 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4329 }
4330 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4331 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4332 ArgValue1, DAG.getIntPtrConstant(0, dl));
4333 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4334 ArgValue2, DAG.getIntPtrConstant(1, dl));
4335 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4336 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4337 } else {
4338 const TargetRegisterClass *RC;
4339
4340 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4341 RC = &ARM::HPRRegClass;
4342 else if (RegVT == MVT::f32)
4343 RC = &ARM::SPRRegClass;
4344 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4345 RegVT == MVT::v4bf16)
4346 RC = &ARM::DPRRegClass;
4347 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4348 RegVT == MVT::v8bf16)
4349 RC = &ARM::QPRRegClass;
4350 else if (RegVT == MVT::i32)
4351 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4352 : &ARM::GPRRegClass;
4353 else
4354 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4354)
;
4355
4356 // Transform the arguments in physical registers into virtual ones.
4357 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4358 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4359
4360 // If this value is passed in r0 and has the returned attribute (e.g.
4361 // C++ 'structors), record this fact for later use.
4362 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4363 AFI->setPreservesR0();
4364 }
4365 }
4366
4367 // If this is an 8 or 16-bit value, it is really passed promoted
4368 // to 32 bits. Insert an assert[sz]ext to capture this, then
4369 // truncate to the right size.
4370 switch (VA.getLocInfo()) {
4371 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4371)
;
4372 case CCValAssign::Full: break;
4373 case CCValAssign::BCvt:
4374 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4375 break;
4376 case CCValAssign::SExt:
4377 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4378 DAG.getValueType(VA.getValVT()));
4379 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4380 break;
4381 case CCValAssign::ZExt:
4382 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4383 DAG.getValueType(VA.getValVT()));
4384 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4385 break;
4386 }
4387
4388 // f16 arguments have their size extended to 4 bytes and passed as if they
4389 // had been copied to the LSBs of a 32-bit register.
4390 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4391 if (VA.needsCustom() &&
4392 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4393 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4394
4395 InVals.push_back(ArgValue);
4396 } else { // VA.isRegLoc()
4397 // sanity check
4398 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4398, __PRETTY_FUNCTION__))
;
4399 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4399, __PRETTY_FUNCTION__))
;
4400
4401 int index = VA.getValNo();
4402
4403 // Some Ins[] entries become multiple ArgLoc[] entries.
4404 // Process them only once.
4405 if (index != lastInsIndex)
4406 {
4407 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4408 // FIXME: For now, all byval parameter objects are marked mutable.
4409 // This can be changed with more analysis.
4410 // In case of tail call optimization mark all arguments mutable.
4411 // Since they could be overwritten by lowering of arguments in case of
4412 // a tail call.
4413 if (Flags.isByVal()) {
4414 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4415, __PRETTY_FUNCTION__))
4415 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4415, __PRETTY_FUNCTION__))
;
4416 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4417
4418 int FrameIndex = StoreByValRegs(
4419 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4420 VA.getLocMemOffset(), Flags.getByValSize());
4421 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4422 CCInfo.nextInRegsParam();
4423 } else {
4424 unsigned FIOffset = VA.getLocMemOffset();
4425 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4426 FIOffset, true);
4427
4428 // Create load nodes to retrieve arguments from the stack.
4429 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4430 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4431 MachinePointerInfo::getFixedStack(
4432 DAG.getMachineFunction(), FI)));
4433 }
4434 lastInsIndex = index;
4435 }
4436 }
4437 }
4438
4439 // varargs
4440 if (isVarArg && MFI.hasVAStart()) {
4441 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset(),
4442 TotalArgRegsSaveSize);
4443 if (AFI->isCmseNSEntryFunction()) {
4444 DiagnosticInfoUnsupported Diag(
4445 DAG.getMachineFunction().getFunction(),
4446 "secure entry function must not be variadic", dl.getDebugLoc());
4447 DAG.getContext()->diagnose(Diag);
4448 }
4449 }
4450
4451 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
4452
4453 if (CCInfo.getNextStackOffset() > 0 && AFI->isCmseNSEntryFunction()) {
4454 DiagnosticInfoUnsupported Diag(
4455 DAG.getMachineFunction().getFunction(),
4456 "secure entry function requires arguments on stack", dl.getDebugLoc());
4457 DAG.getContext()->diagnose(Diag);
4458 }
4459
4460 return Chain;
4461}
4462
4463/// isFloatingPointZero - Return true if this is +0.0.
4464static bool isFloatingPointZero(SDValue Op) {
4465 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4466 return CFP->getValueAPF().isPosZero();
4467 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4468 // Maybe this has already been legalized into the constant pool?
4469 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4470 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4471 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4472 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4473 return CFP->getValueAPF().isPosZero();
4474 }
4475 } else if (Op->getOpcode() == ISD::BITCAST &&
4476 Op->getValueType(0) == MVT::f64) {
4477 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4478 // created by LowerConstantFP().
4479 SDValue BitcastOp = Op->getOperand(0);
4480 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4481 isNullConstant(BitcastOp->getOperand(0)))
4482 return true;
4483 }
4484 return false;
4485}
4486
4487/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4488/// the given operands.
4489SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4490 SDValue &ARMcc, SelectionDAG &DAG,
4491 const SDLoc &dl) const {
4492 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4493 unsigned C = RHSC->getZExtValue();
4494 if (!isLegalICmpImmediate((int32_t)C)) {
4495 // Constant does not fit, try adjusting it by one.
4496 switch (CC) {
4497 default: break;
4498 case ISD::SETLT:
4499 case ISD::SETGE:
4500 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4501 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4502 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4503 }
4504 break;
4505 case ISD::SETULT:
4506 case ISD::SETUGE:
4507 if (C != 0 && isLegalICmpImmediate(C-1)) {
4508 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4509 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4510 }
4511 break;
4512 case ISD::SETLE:
4513 case ISD::SETGT:
4514 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4515 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4516 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4517 }
4518 break;
4519 case ISD::SETULE:
4520 case ISD::SETUGT:
4521 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4522 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4523 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4524 }
4525 break;
4526 }
4527 }
4528 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4529 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4530 // In ARM and Thumb-2, the compare instructions can shift their second
4531 // operand.
4532 CC = ISD::getSetCCSwappedOperands(CC);
4533 std::swap(LHS, RHS);
4534 }
4535
4536 // Thumb1 has very limited immediate modes, so turning an "and" into a
4537 // shift can save multiple instructions.
4538 //
4539 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4540 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4541 // own. If it's the operand to an unsigned comparison with an immediate,
4542 // we can eliminate one of the shifts: we transform
4543 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4544 //
4545 // We avoid transforming cases which aren't profitable due to encoding
4546 // details:
4547 //
4548 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4549 // would not; in that case, we're essentially trading one immediate load for
4550 // another.
4551 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4552 // 3. C2 is zero; we have other code for this special case.
4553 //
4554 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4555 // instruction, since the AND is always one instruction anyway, but we could
4556 // use narrow instructions in some cases.
4557 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4558 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4559 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4560 !isSignedIntSetCC(CC)) {
4561 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4562 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4563 uint64_t RHSV = RHSC->getZExtValue();
4564 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4565 unsigned ShiftBits = countLeadingZeros(Mask);
4566 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4567 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4568 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4569 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4570 }
4571 }
4572 }
4573
4574 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4575 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4576 // way a cmp would.
4577 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4578 // some tweaks to the heuristics for the previous and->shift transform.
4579 // FIXME: Optimize cases where the LHS isn't a shift.
4580 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4581 isa<ConstantSDNode>(RHS) &&
4582 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4583 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4584 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4585 unsigned ShiftAmt =
4586 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4587 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4588 DAG.getVTList(MVT::i32, MVT::i32),
4589 LHS.getOperand(0),
4590 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4591 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4592 Shift.getValue(1), SDValue());
4593 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4594 return Chain.getValue(1);
4595 }
4596
4597 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4598
4599 // If the RHS is a constant zero then the V (overflow) flag will never be
4600 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4601 // simpler for other passes (like the peephole optimiser) to deal with.
4602 if (isNullConstant(RHS)) {
4603 switch (CondCode) {
4604 default: break;
4605 case ARMCC::GE:
4606 CondCode = ARMCC::PL;
4607 break;
4608 case ARMCC::LT:
4609 CondCode = ARMCC::MI;
4610 break;
4611 }
4612 }
4613
4614 ARMISD::NodeType CompareType;
4615 switch (CondCode) {
4616 default:
4617 CompareType = ARMISD::CMP;
4618 break;
4619 case ARMCC::EQ:
4620 case ARMCC::NE:
4621 // Uses only Z Flag
4622 CompareType = ARMISD::CMPZ;
4623 break;
4624 }
4625 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4626 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4627}
4628
4629/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4630SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4631 SelectionDAG &DAG, const SDLoc &dl,
4632 bool Signaling) const {
4633 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)((Subtarget->hasFP64() || RHS.getValueType() != MVT::f64) ?
static_cast<void> (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4633, __PRETTY_FUNCTION__))
;
4634 SDValue Cmp;
4635 if (!isFloatingPointZero(RHS))
4636 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4637 dl, MVT::Glue, LHS, RHS);
4638 else
4639 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4640 dl, MVT::Glue, LHS);
4641 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4642}
4643
4644/// duplicateCmp - Glue values can have only one use, so this function
4645/// duplicates a comparison node.
4646SDValue
4647ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4648 unsigned Opc = Cmp.getOpcode();
4649 SDLoc DL(Cmp);
4650 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4651 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4652
4653 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4653, __PRETTY_FUNCTION__))
;
4654 Cmp = Cmp.getOperand(0);
4655 Opc = Cmp.getOpcode();
4656 if (Opc == ARMISD::CMPFP)
4657 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4658 else {
4659 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4659, __PRETTY_FUNCTION__))
;
4660 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4661 }
4662 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4663}
4664
4665// This function returns three things: the arithmetic computation itself
4666// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4667// comparison and the condition code define the case in which the arithmetic
4668// computation *does not* overflow.
4669std::pair<SDValue, SDValue>
4670ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4671 SDValue &ARMcc) const {
4672 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4672, __PRETTY_FUNCTION__))
;
4673
4674 SDValue Value, OverflowCmp;
4675 SDValue LHS = Op.getOperand(0);
4676 SDValue RHS = Op.getOperand(1);
4677 SDLoc dl(Op);
4678
4679 // FIXME: We are currently always generating CMPs because we don't support
4680 // generating CMN through the backend. This is not as good as the natural
4681 // CMP case because it causes a register dependency and cannot be folded
4682 // later.
4683
4684 switch (Op.getOpcode()) {
4685 default:
4686 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4686)
;
4687 case ISD::SADDO:
4688 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4689 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4690 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4691 break;
4692 case ISD::UADDO:
4693 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4694 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4695 // We do not use it in the USUBO case as Value may not be used.
4696 Value = DAG.getNode(ARMISD::ADDC, dl,
4697 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4698 .getValue(0);
4699 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4700 break;
4701 case ISD::SSUBO:
4702 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4703 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4704 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4705 break;
4706 case ISD::USUBO:
4707 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4708 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4709 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4710 break;
4711 case ISD::UMULO:
4712 // We generate a UMUL_LOHI and then check if the high word is 0.
4713 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4714 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4715 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4716 LHS, RHS);
4717 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4718 DAG.getConstant(0, dl, MVT::i32));
4719 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4720 break;
4721 case ISD::SMULO:
4722 // We generate a SMUL_LOHI and then check if all the bits of the high word
4723 // are the same as the sign bit of the low word.
4724 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4725 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4726 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4727 LHS, RHS);
4728 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4729 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4730 Value.getValue(0),
4731 DAG.getConstant(31, dl, MVT::i32)));
4732 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4733 break;
4734 } // switch (...)
4735
4736 return std::make_pair(Value, OverflowCmp);
4737}
4738
4739SDValue
4740ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4741 // Let legalize expand this if it isn't a legal type yet.
4742 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4743 return SDValue();
4744
4745 SDValue Value, OverflowCmp;
4746 SDValue ARMcc;
4747 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4748 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4749 SDLoc dl(Op);
4750 // We use 0 and 1 as false and true values.
4751 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4752 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4753 EVT VT = Op.getValueType();
4754
4755 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4756 ARMcc, CCR, OverflowCmp);
4757
4758 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4759 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4760}
4761
4762static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4763 SelectionDAG &DAG) {
4764 SDLoc DL(BoolCarry);
4765 EVT CarryVT = BoolCarry.getValueType();
4766
4767 // This converts the boolean value carry into the carry flag by doing
4768 // ARMISD::SUBC Carry, 1
4769 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4770 DAG.getVTList(CarryVT, MVT::i32),
4771 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4772 return Carry.getValue(1);
4773}
4774
4775static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4776 SelectionDAG &DAG) {
4777 SDLoc DL(Flags);
4778
4779 // Now convert the carry flag into a boolean carry. We do this
4780 // using ARMISD:ADDE 0, 0, Carry
4781 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4782 DAG.getConstant(0, DL, MVT::i32),
4783 DAG.getConstant(0, DL, MVT::i32), Flags);
4784}
4785
4786SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4787 SelectionDAG &DAG) const {
4788 // Let legalize expand this if it isn't a legal type yet.
4789 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4790 return SDValue();
4791
4792 SDValue LHS = Op.getOperand(0);
4793 SDValue RHS = Op.getOperand(1);
4794 SDLoc dl(Op);
4795
4796 EVT VT = Op.getValueType();
4797 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4798 SDValue Value;
4799 SDValue Overflow;
4800 switch (Op.getOpcode()) {
4801 default:
4802 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4802)
;
4803 case ISD::UADDO:
4804 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4805 // Convert the carry flag into a boolean value.
4806 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4807 break;
4808 case ISD::USUBO: {
4809 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4810 // Convert the carry flag into a boolean value.
4811 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4812 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4813 // value. So compute 1 - C.
4814 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4815 DAG.getConstant(1, dl, MVT::i32), Overflow);
4816 break;
4817 }
4818 }
4819
4820 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4821}
4822
4823static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4824 const ARMSubtarget *Subtarget) {
4825 EVT VT = Op.getValueType();
4826 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
4827 return SDValue();
4828 if (!VT.isSimple())
4829 return SDValue();
4830
4831 unsigned NewOpcode;
4832 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4833 switch (VT.getSimpleVT().SimpleTy) {
4834 default:
4835 return SDValue();
4836 case MVT::i8:
4837 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4838 break;
4839 case MVT::i16:
4840 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4841 break;
4842 }
4843
4844 SDLoc dl(Op);
4845 SDValue Add =
4846 DAG.getNode(NewOpcode, dl, MVT::i32,
4847 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4848 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4849 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4850}
4851
4852SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4853 SDValue Cond = Op.getOperand(0);
4854 SDValue SelectTrue = Op.getOperand(1);
4855 SDValue SelectFalse = Op.getOperand(2);
4856 SDLoc dl(Op);
4857 unsigned Opc = Cond.getOpcode();
4858
4859 if (Cond.getResNo() == 1 &&
4860 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4861 Opc == ISD::USUBO)) {
4862 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4863 return SDValue();
4864
4865 SDValue Value, OverflowCmp;
4866 SDValue ARMcc;
4867 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4868 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4869 EVT VT = Op.getValueType();
4870
4871 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4872 OverflowCmp, DAG);
4873 }
4874
4875 // Convert:
4876 //
4877 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4878 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4879 //
4880 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4881 const ConstantSDNode *CMOVTrue =
4882 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4883 const ConstantSDNode *CMOVFalse =
4884 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4885
4886 if (CMOVTrue && CMOVFalse) {
4887 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4888 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4889
4890 SDValue True;
4891 SDValue False;
4892 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4893 True = SelectTrue;
4894 False = SelectFalse;
4895 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4896 True = SelectFalse;
4897 False = SelectTrue;
4898 }
4899
4900 if (True.getNode() && False.getNode()) {
4901 EVT VT = Op.getValueType();
4902 SDValue ARMcc = Cond.getOperand(2);
4903 SDValue CCR = Cond.getOperand(3);
4904 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4905 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4905, __PRETTY_FUNCTION__))
;
4906 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4907 }
4908 }
4909 }
4910
4911 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4912 // undefined bits before doing a full-word comparison with zero.
4913 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4914 DAG.getConstant(1, dl, Cond.getValueType()));
4915
4916 return DAG.getSelectCC(dl, Cond,
4917 DAG.getConstant(0, dl, Cond.getValueType()),
4918 SelectTrue, SelectFalse, ISD::SETNE);
4919}
4920
4921static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4922 bool &swpCmpOps, bool &swpVselOps) {
4923 // Start by selecting the GE condition code for opcodes that return true for
4924 // 'equality'
4925 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4926 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4927 CondCode = ARMCC::GE;
4928
4929 // and GT for opcodes that return false for 'equality'.
4930 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4931 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4932 CondCode = ARMCC::GT;
4933
4934 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4935 // to swap the compare operands.
4936 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4937 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4938 swpCmpOps = true;
4939
4940 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4941 // If we have an unordered opcode, we need to swap the operands to the VSEL
4942 // instruction (effectively negating the condition).
4943 //
4944 // This also has the effect of swapping which one of 'less' or 'greater'
4945 // returns true, so we also swap the compare operands. It also switches
4946 // whether we return true for 'equality', so we compensate by picking the
4947 // opposite condition code to our original choice.
4948 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4949 CC == ISD::SETUGT) {
4950 swpCmpOps = !swpCmpOps;
4951 swpVselOps = !swpVselOps;
4952 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4953 }
4954
4955 // 'ordered' is 'anything but unordered', so use the VS condition code and
4956 // swap the VSEL operands.
4957 if (CC == ISD::SETO) {
4958 CondCode = ARMCC::VS;
4959 swpVselOps = true;
4960 }
4961
4962 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4963 // code and swap the VSEL operands. Also do this if we don't care about the
4964 // unordered case.
4965 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4966 CondCode = ARMCC::EQ;
4967 swpVselOps = true;
4968 }
4969}
4970
4971SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4972 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4973 SDValue Cmp, SelectionDAG &DAG) const {
4974 if (!Subtarget->hasFP64() && VT == MVT::f64) {
4975 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4976 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4977 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4978 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4979
4980 SDValue TrueLow = TrueVal.getValue(0);
4981 SDValue TrueHigh = TrueVal.getValue(1);
4982 SDValue FalseLow = FalseVal.getValue(0);
4983 SDValue FalseHigh = FalseVal.getValue(1);
4984
4985 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4986 ARMcc, CCR, Cmp);
4987 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4988 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4989
4990 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4991 } else {
4992 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4993 Cmp);
4994 }
4995}
4996
4997static bool isGTorGE(ISD::CondCode CC) {
4998 return CC == ISD::SETGT || CC == ISD::SETGE;
4999}
5000
5001static bool isLTorLE(ISD::CondCode CC) {
5002 return CC == ISD::SETLT || CC == ISD::SETLE;
5003}
5004
5005// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
5006// All of these conditions (and their <= and >= counterparts) will do:
5007// x < k ? k : x
5008// x > k ? x : k
5009// k < x ? x : k
5010// k > x ? k : x
5011static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
5012 const SDValue TrueVal, const SDValue FalseVal,
5013 const ISD::CondCode CC, const SDValue K) {
5014 return (isGTorGE(CC) &&
5015 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
5016 (isLTorLE(CC) &&
5017 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
5018}
5019
5020// Check if two chained conditionals could be converted into SSAT or USAT.
5021//
5022// SSAT can replace a set of two conditional selectors that bound a number to an
5023// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5024//
5025// x < -k ? -k : (x > k ? k : x)
5026// x < -k ? -k : (x < k ? x : k)
5027// x > -k ? (x > k ? k : x) : -k
5028// x < k ? (x < -k ? -k : x) : k
5029// etc.
5030//
5031// LLVM canonicalizes these to either a min(max()) or a max(min())
5032// pattern. This function tries to match one of these and will return true
5033// if successful.
5034//
5035// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
5036// a power of 2.
5037//
5038// It returns true if the conversion can be done, false otherwise.
5039// Additionally, the variable is returned in parameter V, the constant in K and
5040// usat is set to true if the conditional represents an unsigned saturation
5041static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
5042 uint64_t &K, bool &Usat) {
5043 SDValue V1 = Op.getOperand(0);
5044 SDValue K1 = Op.getOperand(1);
5045 SDValue TrueVal1 = Op.getOperand(2);
5046 SDValue FalseVal1 = Op.getOperand(3);
5047 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5048
5049 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5050 if (Op2.getOpcode() != ISD::SELECT_CC)
5051 return false;
5052
5053 SDValue V2 = Op2.getOperand(0);
5054 SDValue K2 = Op2.getOperand(1);
5055 SDValue TrueVal2 = Op2.getOperand(2);
5056 SDValue FalseVal2 = Op2.getOperand(3);
5057 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5058
5059 SDValue V1Tmp = V1;
5060 SDValue V2Tmp = V2;
5061
5062 if (V1.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5063 V2.getOpcode() == ISD::SIGN_EXTEND_INREG) {
5064 V1Tmp = V1.getOperand(0);
5065 V2Tmp = V2.getOperand(0);
5066 }
5067
5068 // Check that the registers and the constants match a max(min()) or min(max())
5069 // pattern
5070 if (V1Tmp == TrueVal1 && V2Tmp == TrueVal2 && K1 == FalseVal1 &&
5071 K2 == FalseVal2 &&
5072 ((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2)))) {
5073
5074 // Check that the constant in the lower-bound check is
5075 // the opposite of the constant in the upper-bound check
5076 // in 1's complement.
5077 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5078 return false;
5079
5080 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5081 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5082 int64_t PosVal = std::max(Val1, Val2);
5083 int64_t NegVal = std::min(Val1, Val2);
5084
5085 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5086 !isPowerOf2_64(PosVal + 1))
5087 return false;
5088
5089 // Handle the difference between USAT (unsigned) and SSAT (signed)
5090 // saturation
5091 if (Val1 == ~Val2)
5092 Usat = false;
5093 else if (NegVal == 0)
5094 Usat = true;
5095 else
5096 return false;
5097
5098 V = V2Tmp;
5099 // At this point, PosVal is guaranteed to be positive
5100 K = (uint64_t) PosVal;
5101
5102 return true;
5103 }
5104 return false;
5105}
5106
5107// Check if a condition of the type x < k ? k : x can be converted into a
5108// bit operation instead of conditional moves.
5109// Currently this is allowed given:
5110// - The conditions and values match up
5111// - k is 0 or -1 (all ones)
5112// This function will not check the last condition, thats up to the caller
5113// It returns true if the transformation can be made, and in such case
5114// returns x in V, and k in SatK.
5115static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5116 SDValue &SatK)
5117{
5118 SDValue LHS = Op.getOperand(0);
5119 SDValue RHS = Op.getOperand(1);
5120 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5121 SDValue TrueVal = Op.getOperand(2);
5122 SDValue FalseVal = Op.getOperand(3);
5123
5124 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5125 ? &RHS
5126 : nullptr;
5127
5128 // No constant operation in comparison, early out
5129 if (!K)
5130 return false;
5131
5132 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5133 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5134 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5135
5136 // If the constant on left and right side, or variable on left and right,
5137 // does not match, early out
5138 if (*K != KTmp || V != VTmp)
5139 return false;
5140
5141 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5142 SatK = *K;
5143 return true;
5144 }
5145
5146 return false;
5147}
5148
5149bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5150 if (VT == MVT::f32)
5151 return !Subtarget->hasVFP2Base();
5152 if (VT == MVT::f64)
5153 return !Subtarget->hasFP64();
5154 if (VT == MVT::f16)
5155 return !Subtarget->hasFullFP16();
5156 return false;
5157}
5158
5159SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5160 EVT VT = Op.getValueType();
5161 SDLoc dl(Op);
5162
5163 // Try to convert two saturating conditional selects into a single SSAT
5164 SDValue SatValue;
5165 uint64_t SatConstant;
5166 bool SatUSat;
5167 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
5168 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
5169 if (SatUSat)
5170 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
5171 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
5172 else
5173 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
5174 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
5175 }
5176
5177 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5178 // into more efficient bit operations, which is possible when k is 0 or -1
5179 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5180 // single instructions. On Thumb the shift and the bit operation will be two
5181 // instructions.
5182 // Only allow this transformation on full-width (32-bit) operations
5183 SDValue LowerSatConstant;
5184 if (VT == MVT::i32 &&
5185 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5186 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5187 DAG.getConstant(31, dl, VT));
5188 if (isNullConstant(LowerSatConstant)) {
5189 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5190 DAG.getAllOnesConstant(dl, VT));
5191 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5192 } else if (isAllOnesConstant(LowerSatConstant))
5193 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5194 }
5195
5196 SDValue LHS = Op.getOperand(0);
5197 SDValue RHS = Op.getOperand(1);
5198 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5199 SDValue TrueVal = Op.getOperand(2);
5200 SDValue FalseVal = Op.getOperand(3);
5201 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5202 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5203
5204 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5205 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5206 unsigned TVal = CTVal->getZExtValue();
5207 unsigned FVal = CFVal->getZExtValue();
5208 unsigned Opcode = 0;
5209
5210 if (TVal == ~FVal) {
5211 Opcode = ARMISD::CSINV;
5212 } else if (TVal == ~FVal + 1) {
5213 Opcode = ARMISD::CSNEG;
5214 } else if (TVal + 1 == FVal) {
5215 Opcode = ARMISD::CSINC;
5216 } else if (TVal == FVal + 1) {
5217 Opcode = ARMISD::CSINC;
5218 std::swap(TrueVal, FalseVal);
5219 std::swap(TVal, FVal);
5220 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5221 }
5222
5223 if (Opcode) {
5224 // If one of the constants is cheaper than another, materialise the
5225 // cheaper one and let the csel generate the other.
5226 if (Opcode != ARMISD::CSINC &&
5227 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5228 std::swap(TrueVal, FalseVal);
5229 std::swap(TVal, FVal);
5230 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5231 }
5232
5233 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5234 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5235 // -(-a) == a, but (a+1)+1 != a).
5236 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5237 std::swap(TrueVal, FalseVal);
5238 std::swap(TVal, FVal);
5239 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5240 }
5241 if (TVal == 0)
5242 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
5243
5244 // Drops F's value because we can get it by inverting/negating TVal.
5245 FalseVal = TrueVal;
5246
5247 SDValue ARMcc;
5248 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5249 EVT VT = TrueVal.getValueType();
5250 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5251 }
5252 }
5253
5254 if (isUnsupportedFloatingType(LHS.getValueType())) {
5255 DAG.getTargetLoweringInfo().softenSetCCOperands(
5256 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5257
5258 // If softenSetCCOperands only returned one value, we should compare it to
5259 // zero.
5260 if (!RHS.getNode()) {
5261 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5262 CC = ISD::SETNE;
5263 }
5264 }
5265
5266 if (LHS.getValueType() == MVT::i32) {
5267 // Try to generate VSEL on ARMv8.
5268 // The VSEL instruction can't use all the usual ARM condition
5269 // codes: it only has two bits to select the condition code, so it's
5270 // constrained to use only GE, GT, VS and EQ.
5271 //
5272 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5273 // swap the operands of the previous compare instruction (effectively
5274 // inverting the compare condition, swapping 'less' and 'greater') and
5275 // sometimes need to swap the operands to the VSEL (which inverts the
5276 // condition in the sense of firing whenever the previous condition didn't)
5277 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5278 TrueVal.getValueType() == MVT::f32 ||
5279 TrueVal.getValueType() == MVT::f64)) {
5280 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5281 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5282 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5283 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5284 std::swap(TrueVal, FalseVal);
5285 }
5286 }
5287
5288 SDValue ARMcc;
5289 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5290 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5291 // Choose GE over PL, which vsel does now support
5292 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5293 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5294 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5295 }
5296
5297 ARMCC::CondCodes CondCode, CondCode2;
5298 FPCCToARMCC(CC, CondCode, CondCode2);
5299
5300 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5301 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5302 // must use VSEL (limited condition codes), due to not having conditional f16
5303 // moves.
5304 if (Subtarget->hasFPARMv8Base() &&
5305 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5306 (TrueVal.getValueType() == MVT::f16 ||
5307 TrueVal.getValueType() == MVT::f32 ||
5308 TrueVal.getValueType() == MVT::f64)) {
5309 bool swpCmpOps = false;
5310 bool swpVselOps = false;
5311 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5312
5313 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5314 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5315 if (swpCmpOps)
5316 std::swap(LHS, RHS);
5317 if (swpVselOps)
5318 std::swap(TrueVal, FalseVal);
5319 }
5320 }
5321
5322 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5323 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5324 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5325 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5326 if (CondCode2 != ARMCC::AL) {
5327 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5328 // FIXME: Needs another CMP because flag can have but one use.
5329 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5330 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5331 }
5332 return Result;
5333}
5334
5335/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5336/// to morph to an integer compare sequence.
5337static bool canChangeToInt(SDValue Op, bool &SeenZero,
5338 const ARMSubtarget *Subtarget) {
5339 SDNode *N = Op.getNode();
5340 if (!N->hasOneUse())
5341 // Otherwise it requires moving the value from fp to integer registers.
5342 return false;
5343 if (!N->getNumValues())
5344 return false;
5345 EVT VT = Op.getValueType();
5346 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5347 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5348 // vmrs are very slow, e.g. cortex-a8.
5349 return false;
5350
5351 if (isFloatingPointZero(Op)) {
5352 SeenZero = true;
5353 return true;
5354 }
5355 return ISD::isNormalLoad(N);
5356}
5357
5358static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5359 if (isFloatingPointZero(Op))
5360 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5361
5362 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5363 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5364 Ld->getPointerInfo(), Ld->getAlignment(),
5365 Ld->getMemOperand()->getFlags());
5366
5367 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5367)
;
5368}
5369
5370static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5371 SDValue &RetVal1, SDValue &RetVal2) {
5372 SDLoc dl(Op);
5373
5374 if (isFloatingPointZero(Op)) {
5375 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5376 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5377 return;
5378 }
5379
5380 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5381 SDValue Ptr = Ld->getBasePtr();
5382 RetVal1 =
5383 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5384 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5385
5386 EVT PtrType = Ptr.getValueType();
5387 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5388 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5389 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5390 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5391 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5392 Ld->getMemOperand()->getFlags());
5393 return;
5394 }
5395
5396 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5396)
;
5397}
5398
5399/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5400/// f32 and even f64 comparisons to integer ones.
5401SDValue
5402ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5403 SDValue Chain = Op.getOperand(0);
5404 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5405 SDValue LHS = Op.getOperand(2);
5406 SDValue RHS = Op.getOperand(3);
5407 SDValue Dest = Op.getOperand(4);
5408 SDLoc dl(Op);
5409
5410 bool LHSSeenZero = false;
5411 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5412 bool RHSSeenZero = false;
5413 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5414 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5415 // If unsafe fp math optimization is enabled and there are no other uses of
5416 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5417 // to an integer comparison.
5418 if (CC == ISD::SETOEQ)
5419 CC = ISD::SETEQ;
5420 else if (CC == ISD::SETUNE)
5421 CC = ISD::SETNE;
5422
5423 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5424 SDValue ARMcc;
5425 if (LHS.getValueType() == MVT::f32) {
5426 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5427 bitcastf32Toi32(LHS, DAG), Mask);
5428 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5429 bitcastf32Toi32(RHS, DAG), Mask);
5430 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5431 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5432 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5433 Chain, Dest, ARMcc, CCR, Cmp);
5434 }
5435
5436 SDValue LHS1, LHS2;
5437 SDValue RHS1, RHS2;
5438 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5439 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5440 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5441 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5442 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5443 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5444 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5445 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5446 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5447 }
5448
5449 return SDValue();
5450}
5451
5452SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5453 SDValue Chain = Op.getOperand(0);
5454 SDValue Cond = Op.getOperand(1);
5455 SDValue Dest = Op.getOperand(2);
5456 SDLoc dl(Op);
5457
5458 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5459 // instruction.
5460 unsigned Opc = Cond.getOpcode();
5461 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5462 !Subtarget->isThumb1Only();
5463 if (Cond.getResNo() == 1 &&
5464 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5465 Opc == ISD::USUBO || OptimizeMul)) {
5466 // Only lower legal XALUO ops.
5467 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5468 return SDValue();
5469
5470 // The actual operation with overflow check.
5471 SDValue Value, OverflowCmp;
5472 SDValue ARMcc;
5473 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5474
5475 // Reverse the condition code.
5476 ARMCC::CondCodes CondCode =
5477 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5478 CondCode = ARMCC::getOppositeCondition(CondCode);
5479 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5480 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5481
5482 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5483 OverflowCmp);
5484 }
5485
5486 return SDValue();
5487}
5488
5489SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5490 SDValue Chain = Op.getOperand(0);
5491 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5492 SDValue LHS = Op.getOperand(2);
5493 SDValue RHS = Op.getOperand(3);
5494 SDValue Dest = Op.getOperand(4);
5495 SDLoc dl(Op);
5496
5497 if (isUnsupportedFloatingType(LHS.getValueType())) {
5498 DAG.getTargetLoweringInfo().softenSetCCOperands(
5499 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5500
5501 // If softenSetCCOperands only returned one value, we should compare it to
5502 // zero.
5503 if (!RHS.getNode()) {
5504 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5505 CC = ISD::SETNE;
5506 }
5507 }
5508
5509 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5510 // instruction.
5511 unsigned Opc = LHS.getOpcode();
5512 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5513 !Subtarget->isThumb1Only();
5514 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5515 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5516 Opc == ISD::USUBO || OptimizeMul) &&
5517 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5518 // Only lower legal XALUO ops.
5519 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5520 return SDValue();
5521
5522 // The actual operation with overflow check.
5523 SDValue Value, OverflowCmp;
5524 SDValue ARMcc;
5525 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5526
5527 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5528 // Reverse the condition code.
5529 ARMCC::CondCodes CondCode =
5530 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5531 CondCode = ARMCC::getOppositeCondition(CondCode);
5532 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5533 }
5534 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5535
5536 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5537 OverflowCmp);
5538 }
5539
5540 if (LHS.getValueType() == MVT::i32) {
5541 SDValue ARMcc;
5542 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5543 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5544 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5545 Chain, Dest, ARMcc, CCR, Cmp);
5546 }
5547
5548 if (getTargetMachine().Options.UnsafeFPMath &&
5549 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5550 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5551 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5552 return Result;
5553 }
5554
5555 ARMCC::CondCodes CondCode, CondCode2;
5556 FPCCToARMCC(CC, CondCode, CondCode2);
5557
5558 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5559 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5560 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5561 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5562 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5563 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5564 if (CondCode2 != ARMCC::AL) {
5565 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5566 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5567 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5568 }
5569 return Res;
5570}
5571
5572SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5573 SDValue Chain = Op.getOperand(0);
5574 SDValue Table = Op.getOperand(1);
5575 SDValue Index = Op.getOperand(2);
5576 SDLoc dl(Op);
5577
5578 EVT PTy = getPointerTy(DAG.getDataLayout());
5579 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5580 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5581 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5582 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5583 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5584 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5585 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5586 // which does another jump to the destination. This also makes it easier
5587 // to translate it to TBB / TBH later (Thumb2 only).
5588 // FIXME: This might not work if the function is extremely large.
5589 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5590 Addr, Op.getOperand(2), JTI);
5591 }
5592 if (isPositionIndependent() || Subtarget->isROPI()) {
5593 Addr =
5594 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5595 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5596 Chain = Addr.getValue(1);
5597 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5598 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5599 } else {
5600 Addr =
5601 DAG.getLoad(PTy, dl, Chain, Addr,
5602 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5603 Chain = Addr.getValue(1);
5604 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5605 }
5606}
5607
5608static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5609 EVT VT = Op.getValueType();
5610 SDLoc dl(Op);
5611
5612 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5613 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5614 return Op;
5615 return DAG.UnrollVectorOp(Op.getNode());
5616 }
5617
5618 const bool HasFullFP16 =
5619 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5620
5621 EVT NewTy;
5622 const EVT OpTy = Op.getOperand(0).getValueType();
5623 if (OpTy == MVT::v4f32)
5624 NewTy = MVT::v4i32;
5625 else if (OpTy == MVT::v4f16 && HasFullFP16)
5626 NewTy = MVT::v4i16;
5627 else if (OpTy == MVT::v8f16 && HasFullFP16)
5628 NewTy = MVT::v8i16;
5629 else
5630 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5630)
;
5631
5632 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5633 return DAG.UnrollVectorOp(Op.getNode());
5634
5635 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5636 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5637}
5638
5639SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5640 EVT VT = Op.getValueType();
5641 if (VT.isVector())
5642 return LowerVectorFP_TO_INT(Op, DAG);
5643
5644 bool IsStrict = Op->isStrictFPOpcode();
5645 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5646
5647 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5648 RTLIB::Libcall LC;
5649 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5650 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5651 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5652 Op.getValueType());
5653 else
5654 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5655 Op.getValueType());
5656 SDLoc Loc(Op);
5657 MakeLibCallOptions CallOptions;
5658 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5659 SDValue Result;
5660 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5661 CallOptions, Loc, Chain);
5662 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5663 }
5664
5665 // FIXME: Remove this when we have strict fp instruction selection patterns
5666 if (IsStrict) {
5667 SDLoc Loc(Op);
5668 SDValue Result =
5669 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5670 : ISD::FP_TO_UINT,
5671 Loc, Op.getValueType(), SrcVal);
5672 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5673 }
5674
5675 return Op;
5676}
5677
5678static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5679 EVT VT = Op.getValueType();
5680 SDLoc dl(Op);
5681
5682 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5683 if (VT.getVectorElementType() == MVT::f32)
5684 return Op;
5685 return DAG.UnrollVectorOp(Op.getNode());
5686 }
5687
5688 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5690, __PRETTY_FUNCTION__))
5689 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5690, __PRETTY_FUNCTION__))
5690 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5690, __PRETTY_FUNCTION__))
;
5691
5692 const bool HasFullFP16 =
5693 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5694
5695 EVT DestVecType;
5696 if (VT == MVT::v4f32)
5697 DestVecType = MVT::v4i32;
5698 else if (VT == MVT::v4f16 && HasFullFP16)
5699 DestVecType = MVT::v4i16;
5700 else if (VT == MVT::v8f16 && HasFullFP16)
5701 DestVecType = MVT::v8i16;
5702 else
5703 return DAG.UnrollVectorOp(Op.getNode());
5704
5705 unsigned CastOpc;
5706 unsigned Opc;
5707 switch (Op.getOpcode()) {
5708 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5708)
;
5709 case ISD::SINT_TO_FP:
5710 CastOpc = ISD::SIGN_EXTEND;
5711 Opc = ISD::SINT_TO_FP;
5712 break;
5713 case ISD::UINT_TO_FP:
5714 CastOpc = ISD::ZERO_EXTEND;
5715 Opc = ISD::UINT_TO_FP;
5716 break;
5717 }
5718
5719 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5720 return DAG.getNode(Opc, dl, VT, Op);
5721}
5722
5723SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5724 EVT VT = Op.getValueType();
5725 if (VT.isVector())
5726 return LowerVectorINT_TO_FP(Op, DAG);
5727 if (isUnsupportedFloatingType(VT)) {
5728 RTLIB::Libcall LC;
5729 if (Op.getOpcode() == ISD::SINT_TO_FP)
5730 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5731 Op.getValueType());
5732 else
5733 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5734 Op.getValueType());
5735 MakeLibCallOptions CallOptions;
5736 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5737 CallOptions, SDLoc(Op)).first;
5738 }
5739
5740 return Op;
5741}
5742
5743SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5744 // Implement fcopysign with a fabs and a conditional fneg.
5745 SDValue Tmp0 = Op.getOperand(0);
5746 SDValue Tmp1 = Op.getOperand(1);
5747 SDLoc dl(Op);
5748 EVT VT = Op.getValueType();
5749 EVT SrcVT = Tmp1.getValueType();
5750 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5751 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5752 bool UseNEON = !InGPR && Subtarget->hasNEON();
5753
5754 if (UseNEON) {
5755 // Use VBSL to copy the sign bit.
5756 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5757 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5758 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5759 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5760 if (VT == MVT::f64)
5761 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5762 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5763 DAG.getConstant(32, dl, MVT::i32));
5764 else /*if (VT == MVT::f32)*/
5765 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5766 if (SrcVT == MVT::f32) {
5767 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5768 if (VT == MVT::f64)
5769 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5770 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5771 DAG.getConstant(32, dl, MVT::i32));
5772 } else if (VT == MVT::f32)
5773 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5774 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5775 DAG.getConstant(32, dl, MVT::i32));
5776 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5777 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5778
5779 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5780 dl, MVT::i32);
5781 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5782 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5783 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5784
5785 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5786 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5787 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5788 if (VT == MVT::f32) {
5789 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5790 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5791 DAG.getConstant(0, dl, MVT::i32));
5792 } else {
5793 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5794 }
5795
5796 return Res;
5797 }
5798
5799 // Bitcast operand 1 to i32.
5800 if (SrcVT == MVT::f64)
5801 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5802 Tmp1).getValue(1);
5803 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5804
5805 // Or in the signbit with integer operations.
5806 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5807 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5808 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5809 if (VT == MVT::f32) {
5810 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5811 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5812 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5813 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5814 }
5815
5816 // f64: Or the high part with signbit and then combine two parts.
5817 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5818 Tmp0);
5819 SDValue Lo = Tmp0.getValue(0);
5820 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5821 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5822 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5823}
5824
5825SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5826 MachineFunction &MF = DAG.getMachineFunction();
5827 MachineFrameInfo &MFI = MF.getFrameInfo();
5828 MFI.setReturnAddressIsTaken(true);
5829
5830 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5831 return SDValue();
5832
5833 EVT VT = Op.getValueType();
5834 SDLoc dl(Op);
5835 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5836 if (Depth) {
5837 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5838 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5839 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5840 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5841 MachinePointerInfo());
5842 }
5843
5844 // Return LR, which contains the return address. Mark it an implicit live-in.
5845 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5846 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5847}
5848
5849SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5850 const ARMBaseRegisterInfo &ARI =
5851 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5852 MachineFunction &MF = DAG.getMachineFunction();
5853 MachineFrameInfo &MFI = MF.getFrameInfo();
5854 MFI.setFrameAddressIsTaken(true);
5855
5856 EVT VT = Op.getValueType();
5857 SDLoc dl(Op); // FIXME probably not meaningful
5858 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5859 Register FrameReg = ARI.getFrameRegister(MF);
5860 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5861 while (Depth--)
5862 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5863 MachinePointerInfo());
5864 return FrameAddr;
5865}
5866
5867// FIXME? Maybe this could be a TableGen attribute on some registers and
5868// this table could be generated automatically from RegInfo.
5869Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
5870 const MachineFunction &MF) const {
5871 Register Reg = StringSwitch<unsigned>(RegName)
5872 .Case("sp", ARM::SP)
5873 .Default(0);
5874 if (Reg)
5875 return Reg;
5876 report_fatal_error(Twine("Invalid register name \""
5877 + StringRef(RegName) + "\"."));
5878}
5879
5880// Result is 64 bit value so split into two 32 bit values and return as a
5881// pair of values.
5882static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5883 SelectionDAG &DAG) {
5884 SDLoc DL(N);
5885
5886 // This function is only supposed to be called for i64 type destination.
5887 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5888, __PRETTY_FUNCTION__))
5888 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5888, __PRETTY_FUNCTION__))
;
5889
5890 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5891 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5892 N->getOperand(0),
5893 N->getOperand(1));
5894
5895 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5896 Read.getValue(1)));
5897 Results.push_back(Read.getOperand(0));
5898}
5899
5900/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5901/// When \p DstVT, the destination type of \p BC, is on the vector
5902/// register bank and the source of bitcast, \p Op, operates on the same bank,
5903/// it might be possible to combine them, such that everything stays on the
5904/// vector register bank.