Bug Summary

File:llvm/lib/Target/ARM/ARMISelLowering.cpp
Warning:line 2508, column 20
Called C++ object pointer is null

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b=. -ferror-limit 19 -fvisibility hidden -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-17-195756-12974-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallPtrSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringExtras.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Triple.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/RuntimeLibcalls.h"
56#include "llvm/CodeGen/SelectionDAG.h"
57#include "llvm/CodeGen/SelectionDAGNodes.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/IR/Attributes.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/Constants.h"
68#include "llvm/IR/DataLayout.h"
69#include "llvm/IR/DebugLoc.h"
70#include "llvm/IR/DerivedTypes.h"
71#include "llvm/IR/Function.h"
72#include "llvm/IR/GlobalAlias.h"
73#include "llvm/IR/GlobalValue.h"
74#include "llvm/IR/GlobalVariable.h"
75#include "llvm/IR/IRBuilder.h"
76#include "llvm/IR/InlineAsm.h"
77#include "llvm/IR/Instruction.h"
78#include "llvm/IR/Instructions.h"
79#include "llvm/IR/IntrinsicInst.h"
80#include "llvm/IR/Intrinsics.h"
81#include "llvm/IR/IntrinsicsARM.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/PatternMatch.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MachineValueType.h"
101#include "llvm/Support/MathExtras.h"
102#include "llvm/Support/raw_ostream.h"
103#include "llvm/Target/TargetMachine.h"
104#include "llvm/Target/TargetOptions.h"
105#include <algorithm>
106#include <cassert>
107#include <cstdint>
108#include <cstdlib>
109#include <iterator>
110#include <limits>
111#include <string>
112#include <tuple>
113#include <utility>
114#include <vector>
115
116using namespace llvm;
117using namespace llvm::PatternMatch;
118
119#define DEBUG_TYPE"arm-isel" "arm-isel"
120
121STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
122STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
123STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
124STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
125 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
126
127static cl::opt<bool>
128ARMInterworking("arm-interworking", cl::Hidden,
129 cl::desc("Enable / disable ARM interworking (for debugging only)"),
130 cl::init(true));
131
132static cl::opt<bool> EnableConstpoolPromotion(
133 "arm-promote-constant", cl::Hidden,
134 cl::desc("Enable / disable promotion of unnamed_addr constants into "
135 "constant pools"),
136 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
137static cl::opt<unsigned> ConstpoolPromotionMaxSize(
138 "arm-promote-constant-max-size", cl::Hidden,
139 cl::desc("Maximum size of constant to promote into a constant pool"),
140 cl::init(64));
141static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
142 "arm-promote-constant-max-total", cl::Hidden,
143 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
144 cl::init(128));
145
146cl::opt<unsigned>
147MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
148 cl::desc("Maximum interleave factor for MVE VLDn to generate."),
149 cl::init(2));
150
151// The APCS parameter registers.
152static const MCPhysReg GPRArgRegs[] = {
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
154};
155
156void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
157 MVT PromotedBitwiseVT) {
158 if (VT != PromotedLdStVT) {
159 setOperationAction(ISD::LOAD, VT, Promote);
160 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
161
162 setOperationAction(ISD::STORE, VT, Promote);
163 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
164 }
165
166 MVT ElemTy = VT.getVectorElementType();
167 if (ElemTy != MVT::f64)
168 setOperationAction(ISD::SETCC, VT, Custom);
169 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
171 if (ElemTy == MVT::i32) {
172 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
173 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
175 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
176 } else {
177 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
180 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
181 }
182 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
184 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
186 setOperationAction(ISD::SELECT, VT, Expand);
187 setOperationAction(ISD::SELECT_CC, VT, Expand);
188 setOperationAction(ISD::VSELECT, VT, Expand);
189 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
190 if (VT.isInteger()) {
191 setOperationAction(ISD::SHL, VT, Custom);
192 setOperationAction(ISD::SRA, VT, Custom);
193 setOperationAction(ISD::SRL, VT, Custom);
194 }
195
196 // Promote all bit-wise operations.
197 if (VT.isInteger() && VT != PromotedBitwiseVT) {
198 setOperationAction(ISD::AND, VT, Promote);
199 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
200 setOperationAction(ISD::OR, VT, Promote);
201 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
202 setOperationAction(ISD::XOR, VT, Promote);
203 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
204 }
205
206 // Neon does not support vector divide/remainder operations.
207 setOperationAction(ISD::SDIV, VT, Expand);
208 setOperationAction(ISD::UDIV, VT, Expand);
209 setOperationAction(ISD::FDIV, VT, Expand);
210 setOperationAction(ISD::SREM, VT, Expand);
211 setOperationAction(ISD::UREM, VT, Expand);
212 setOperationAction(ISD::FREM, VT, Expand);
213 setOperationAction(ISD::SDIVREM, VT, Expand);
214 setOperationAction(ISD::UDIVREM, VT, Expand);
215
216 if (!VT.isFloatingPoint() &&
217 VT != MVT::v2i64 && VT != MVT::v1i64)
218 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
219 setOperationAction(Opcode, VT, Legal);
220 if (!VT.isFloatingPoint())
221 for (auto Opcode : {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT})
222 setOperationAction(Opcode, VT, Legal);
223}
224
225void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
226 addRegisterClass(VT, &ARM::DPRRegClass);
227 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
228}
229
230void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
231 addRegisterClass(VT, &ARM::DPairRegClass);
232 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
233}
234
235void ARMTargetLowering::setAllExpand(MVT VT) {
236 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
237 setOperationAction(Opc, VT, Expand);
238
239 // We support these really simple operations even on types where all
240 // the actual arithmetic has to be broken down into simpler
241 // operations or turned into library calls.
242 setOperationAction(ISD::BITCAST, VT, Legal);
243 setOperationAction(ISD::LOAD, VT, Legal);
244 setOperationAction(ISD::STORE, VT, Legal);
245 setOperationAction(ISD::UNDEF, VT, Legal);
246}
247
248void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
249 LegalizeAction Action) {
250 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
251 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
252 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
253}
254
255void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
256 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
257
258 for (auto VT : IntTypes) {
259 addRegisterClass(VT, &ARM::MQPRRegClass);
260 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
261 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
262 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
263 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
264 setOperationAction(ISD::SHL, VT, Custom);
265 setOperationAction(ISD::SRA, VT, Custom);
266 setOperationAction(ISD::SRL, VT, Custom);
267 setOperationAction(ISD::SMIN, VT, Legal);
268 setOperationAction(ISD::SMAX, VT, Legal);
269 setOperationAction(ISD::UMIN, VT, Legal);
270 setOperationAction(ISD::UMAX, VT, Legal);
271 setOperationAction(ISD::ABS, VT, Legal);
272 setOperationAction(ISD::SETCC, VT, Custom);
273 setOperationAction(ISD::MLOAD, VT, Custom);
274 setOperationAction(ISD::MSTORE, VT, Legal);
275 setOperationAction(ISD::CTLZ, VT, Legal);
276 setOperationAction(ISD::CTTZ, VT, Custom);
277 setOperationAction(ISD::BITREVERSE, VT, Legal);
278 setOperationAction(ISD::BSWAP, VT, Legal);
279 setOperationAction(ISD::SADDSAT, VT, Legal);
280 setOperationAction(ISD::UADDSAT, VT, Legal);
281 setOperationAction(ISD::SSUBSAT, VT, Legal);
282 setOperationAction(ISD::USUBSAT, VT, Legal);
283
284 // No native support for these.
285 setOperationAction(ISD::UDIV, VT, Expand);
286 setOperationAction(ISD::SDIV, VT, Expand);
287 setOperationAction(ISD::UREM, VT, Expand);
288 setOperationAction(ISD::SREM, VT, Expand);
289 setOperationAction(ISD::UDIVREM, VT, Expand);
290 setOperationAction(ISD::SDIVREM, VT, Expand);
291 setOperationAction(ISD::CTPOP, VT, Expand);
292
293 // Vector reductions
294 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
295 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
296 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
297 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
298 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
299 setOperationAction(ISD::VECREDUCE_MUL, VT, Custom);
300 setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
301 setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
302 setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
303
304 if (!HasMVEFP) {
305 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
306 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 }
310
311 // Pre and Post inc are supported on loads and stores
312 for (unsigned im = (unsigned)ISD::PRE_INC;
313 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
314 setIndexedLoadAction(im, VT, Legal);
315 setIndexedStoreAction(im, VT, Legal);
316 setIndexedMaskedLoadAction(im, VT, Legal);
317 setIndexedMaskedStoreAction(im, VT, Legal);
318 }
319 }
320
321 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
322 for (auto VT : FloatTypes) {
323 addRegisterClass(VT, &ARM::MQPRRegClass);
324 if (!HasMVEFP)
325 setAllExpand(VT);
326
327 // These are legal or custom whether we have MVE.fp or not
328 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
329 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
330 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
331 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
332 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
333 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
334 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
335 setOperationAction(ISD::SETCC, VT, Custom);
336 setOperationAction(ISD::MLOAD, VT, Custom);
337 setOperationAction(ISD::MSTORE, VT, Legal);
338
339 // Pre and Post inc are supported on loads and stores
340 for (unsigned im = (unsigned)ISD::PRE_INC;
341 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
342 setIndexedLoadAction(im, VT, Legal);
343 setIndexedStoreAction(im, VT, Legal);
344 setIndexedMaskedLoadAction(im, VT, Legal);
345 setIndexedMaskedStoreAction(im, VT, Legal);
346 }
347
348 if (HasMVEFP) {
349 setOperationAction(ISD::FMINNUM, VT, Legal);
350 setOperationAction(ISD::FMAXNUM, VT, Legal);
351 setOperationAction(ISD::FROUND, VT, Legal);
352 setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
353 setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
354 setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
355 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
356
357 // No native support for these.
358 setOperationAction(ISD::FDIV, VT, Expand);
359 setOperationAction(ISD::FREM, VT, Expand);
360 setOperationAction(ISD::FSQRT, VT, Expand);
361 setOperationAction(ISD::FSIN, VT, Expand);
362 setOperationAction(ISD::FCOS, VT, Expand);
363 setOperationAction(ISD::FPOW, VT, Expand);
364 setOperationAction(ISD::FLOG, VT, Expand);
365 setOperationAction(ISD::FLOG2, VT, Expand);
366 setOperationAction(ISD::FLOG10, VT, Expand);
367 setOperationAction(ISD::FEXP, VT, Expand);
368 setOperationAction(ISD::FEXP2, VT, Expand);
369 setOperationAction(ISD::FNEARBYINT, VT, Expand);
370 }
371 }
372
373 // Custom Expand smaller than legal vector reductions to prevent false zero
374 // items being added.
375 setOperationAction(ISD::VECREDUCE_FADD, MVT::v4f16, Custom);
376 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v4f16, Custom);
377 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v4f16, Custom);
378 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom);
379 setOperationAction(ISD::VECREDUCE_FADD, MVT::v2f16, Custom);
380 setOperationAction(ISD::VECREDUCE_FMUL, MVT::v2f16, Custom);
381 setOperationAction(ISD::VECREDUCE_FMIN, MVT::v2f16, Custom);
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom);
383
384 // We 'support' these types up to bitcast/load/store level, regardless of
385 // MVE integer-only / float support. Only doing FP data processing on the FP
386 // vector types is inhibited at integer-only level.
387 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
388 for (auto VT : LongTypes) {
389 addRegisterClass(VT, &ARM::MQPRRegClass);
390 setAllExpand(VT);
391 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
392 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
393 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
394 }
395 // We can do bitwise operations on v2i64 vectors
396 setOperationAction(ISD::AND, MVT::v2i64, Legal);
397 setOperationAction(ISD::OR, MVT::v2i64, Legal);
398 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
399
400 // It is legal to extload from v4i8 to v4i16 or v4i32.
401 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
402 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
403 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
404
405 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal);
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Legal);
410 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
411
412 // Some truncating stores are legal too.
413 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
414 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
415 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
416
417 // Pre and Post inc on these are legal, given the correct extends
418 for (unsigned im = (unsigned)ISD::PRE_INC;
419 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
420 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) {
421 setIndexedLoadAction(im, VT, Legal);
422 setIndexedStoreAction(im, VT, Legal);
423 setIndexedMaskedLoadAction(im, VT, Legal);
424 setIndexedMaskedStoreAction(im, VT, Legal);
425 }
426 }
427
428 // Predicate types
429 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
430 for (auto VT : pTypes) {
431 addRegisterClass(VT, &ARM::VCCRRegClass);
432 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
433 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
434 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
435 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
436 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
437 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
438 setOperationAction(ISD::SETCC, VT, Custom);
439 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
440 setOperationAction(ISD::LOAD, VT, Custom);
441 setOperationAction(ISD::STORE, VT, Custom);
442 }
443}
444
445ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
446 const ARMSubtarget &STI)
447 : TargetLowering(TM), Subtarget(&STI) {
448 RegInfo = Subtarget->getRegisterInfo();
449 Itins = Subtarget->getInstrItineraryData();
450
451 setBooleanContents(ZeroOrOneBooleanContent);
452 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
453
454 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
455 !Subtarget->isTargetWatchOS()) {
456 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
457 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
458 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
459 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
460 : CallingConv::ARM_AAPCS);
461 }
462
463 if (Subtarget->isTargetMachO()) {
464 // Uses VFP for Thumb libfuncs if available.
465 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
466 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
467 static const struct {
468 const RTLIB::Libcall Op;
469 const char * const Name;
470 const ISD::CondCode Cond;
471 } LibraryCalls[] = {
472 // Single-precision floating-point arithmetic.
473 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
474 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
475 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
476 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
477
478 // Double-precision floating-point arithmetic.
479 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
480 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
481 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
482 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
483
484 // Single-precision comparisons.
485 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
486 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
487 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
488 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
489 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
490 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
491 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
492
493 // Double-precision comparisons.
494 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
495 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
496 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
497 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
498 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
499 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
500 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
501
502 // Floating-point to integer conversions.
503 // i64 conversions are done via library routines even when generating VFP
504 // instructions, so use the same ones.
505 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
506 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
507 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
508 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
509
510 // Conversions between floating types.
511 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
512 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
513
514 // Integer to floating-point conversions.
515 // i64 conversions are done via library routines even when generating VFP
516 // instructions, so use the same ones.
517 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
518 // e.g., __floatunsidf vs. __floatunssidfvfp.
519 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
520 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
521 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
522 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
523 };
524
525 for (const auto &LC : LibraryCalls) {
526 setLibcallName(LC.Op, LC.Name);
527 if (LC.Cond != ISD::SETCC_INVALID)
528 setCmpLibcallCC(LC.Op, LC.Cond);
529 }
530 }
531 }
532
533 // These libcalls are not available in 32-bit.
534 setLibcallName(RTLIB::SHL_I128, nullptr);
535 setLibcallName(RTLIB::SRL_I128, nullptr);
536 setLibcallName(RTLIB::SRA_I128, nullptr);
537
538 // RTLIB
539 if (Subtarget->isAAPCS_ABI() &&
540 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
541 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
542 static const struct {
543 const RTLIB::Libcall Op;
544 const char * const Name;
545 const CallingConv::ID CC;
546 const ISD::CondCode Cond;
547 } LibraryCalls[] = {
548 // Double-precision floating-point arithmetic helper functions
549 // RTABI chapter 4.1.2, Table 2
550 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
551 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
552 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
553 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
554
555 // Double-precision floating-point comparison helper functions
556 // RTABI chapter 4.1.2, Table 3
557 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
558 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
559 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
560 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
561 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
562 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
563 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
564
565 // Single-precision floating-point arithmetic helper functions
566 // RTABI chapter 4.1.2, Table 4
567 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
568 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
569 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
570 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
571
572 // Single-precision floating-point comparison helper functions
573 // RTABI chapter 4.1.2, Table 5
574 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
575 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
576 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
577 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
578 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
579 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
580 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
581
582 // Floating-point to integer conversions.
583 // RTABI chapter 4.1.2, Table 6
584 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
585 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
586 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
587 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
588 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
589 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
590 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
591 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
592
593 // Conversions between floating types.
594 // RTABI chapter 4.1.2, Table 7
595 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
596 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
597 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
598
599 // Integer to floating-point conversions.
600 // RTABI chapter 4.1.2, Table 8
601 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
602 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
603 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
604 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
605 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
606 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
607 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
608 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609
610 // Long long helper functions
611 // RTABI chapter 4.2, Table 9
612 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
613 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
614 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
615 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
616
617 // Integer division functions
618 // RTABI chapter 4.3.1
619 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
620 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
621 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
622 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
623 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
624 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
625 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
626 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
627 };
628
629 for (const auto &LC : LibraryCalls) {
630 setLibcallName(LC.Op, LC.Name);
631 setLibcallCallingConv(LC.Op, LC.CC);
632 if (LC.Cond != ISD::SETCC_INVALID)
633 setCmpLibcallCC(LC.Op, LC.Cond);
634 }
635
636 // EABI dependent RTLIB
637 if (TM.Options.EABIVersion == EABI::EABI4 ||
638 TM.Options.EABIVersion == EABI::EABI5) {
639 static const struct {
640 const RTLIB::Libcall Op;
641 const char *const Name;
642 const CallingConv::ID CC;
643 const ISD::CondCode Cond;
644 } MemOpsLibraryCalls[] = {
645 // Memory operations
646 // RTABI chapter 4.3.4
647 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
648 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
649 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
650 };
651
652 for (const auto &LC : MemOpsLibraryCalls) {
653 setLibcallName(LC.Op, LC.Name);
654 setLibcallCallingConv(LC.Op, LC.CC);
655 if (LC.Cond != ISD::SETCC_INVALID)
656 setCmpLibcallCC(LC.Op, LC.Cond);
657 }
658 }
659 }
660
661 if (Subtarget->isTargetWindows()) {
662 static const struct {
663 const RTLIB::Libcall Op;
664 const char * const Name;
665 const CallingConv::ID CC;
666 } LibraryCalls[] = {
667 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
668 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
669 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
670 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
671 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
672 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
673 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
674 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
675 };
676
677 for (const auto &LC : LibraryCalls) {
678 setLibcallName(LC.Op, LC.Name);
679 setLibcallCallingConv(LC.Op, LC.CC);
680 }
681 }
682
683 // Use divmod compiler-rt calls for iOS 5.0 and later.
684 if (Subtarget->isTargetMachO() &&
685 !(Subtarget->isTargetIOS() &&
686 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
687 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
688 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
689 }
690
691 // The half <-> float conversion functions are always soft-float on
692 // non-watchos platforms, but are needed for some targets which use a
693 // hard-float calling convention by default.
694 if (!Subtarget->isTargetWatchABI()) {
695 if (Subtarget->isAAPCS_ABI()) {
696 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
697 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
698 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
699 } else {
700 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
701 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
702 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
703 }
704 }
705
706 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
707 // a __gnu_ prefix (which is the default).
708 if (Subtarget->isTargetAEABI()) {
709 static const struct {
710 const RTLIB::Libcall Op;
711 const char * const Name;
712 const CallingConv::ID CC;
713 } LibraryCalls[] = {
714 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
715 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
716 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
717 };
718
719 for (const auto &LC : LibraryCalls) {
720 setLibcallName(LC.Op, LC.Name);
721 setLibcallCallingConv(LC.Op, LC.CC);
722 }
723 }
724
725 if (Subtarget->isThumb1Only())
726 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
727 else
728 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
729
730 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
731 Subtarget->hasFPRegs()) {
732 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
733 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
734 if (!Subtarget->hasVFP2Base())
735 setAllExpand(MVT::f32);
736 if (!Subtarget->hasFP64())
737 setAllExpand(MVT::f64);
738 }
739
740 if (Subtarget->hasFullFP16()) {
741 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
742 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
743 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
744
745 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
746 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
747 }
748
749 if (Subtarget->hasBF16()) {
750 addRegisterClass(MVT::bf16, &ARM::HPRRegClass);
751 setAllExpand(MVT::bf16);
752 if (!Subtarget->hasFullFP16())
753 setOperationAction(ISD::BITCAST, MVT::bf16, Custom);
754 }
755
756 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
757 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
758 setTruncStoreAction(VT, InnerVT, Expand);
759 addAllExtLoads(VT, InnerVT, Expand);
760 }
761
762 setOperationAction(ISD::MULHS, VT, Expand);
763 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
764 setOperationAction(ISD::MULHU, VT, Expand);
765 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
766
767 setOperationAction(ISD::BSWAP, VT, Expand);
768 }
769
770 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
771 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
772
773 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
774 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
775
776 if (Subtarget->hasMVEIntegerOps())
777 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
778
779 // Combine low-overhead loop intrinsics so that we can lower i1 types.
780 if (Subtarget->hasLOB()) {
781 setTargetDAGCombine(ISD::BRCOND);
782 setTargetDAGCombine(ISD::BR_CC);
783 }
784
785 if (Subtarget->hasNEON()) {
786 addDRTypeForNEON(MVT::v2f32);
787 addDRTypeForNEON(MVT::v8i8);
788 addDRTypeForNEON(MVT::v4i16);
789 addDRTypeForNEON(MVT::v2i32);
790 addDRTypeForNEON(MVT::v1i64);
791
792 addQRTypeForNEON(MVT::v4f32);
793 addQRTypeForNEON(MVT::v2f64);
794 addQRTypeForNEON(MVT::v16i8);
795 addQRTypeForNEON(MVT::v8i16);
796 addQRTypeForNEON(MVT::v4i32);
797 addQRTypeForNEON(MVT::v2i64);
798
799 if (Subtarget->hasFullFP16()) {
800 addQRTypeForNEON(MVT::v8f16);
801 addDRTypeForNEON(MVT::v4f16);
802 }
803
804 if (Subtarget->hasBF16()) {
805 addQRTypeForNEON(MVT::v8bf16);
806 addDRTypeForNEON(MVT::v4bf16);
807 }
808 }
809
810 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
811 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
812 // none of Neon, MVE or VFP supports any arithmetic operations on it.
813 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
814 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
815 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
816 // FIXME: Code duplication: FDIV and FREM are expanded always, see
817 // ARMTargetLowering::addTypeForNEON method for details.
818 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
819 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
820 // FIXME: Create unittest.
821 // In another words, find a way when "copysign" appears in DAG with vector
822 // operands.
823 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
824 // FIXME: Code duplication: SETCC has custom operation action, see
825 // ARMTargetLowering::addTypeForNEON method for details.
826 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
827 // FIXME: Create unittest for FNEG and for FABS.
828 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
829 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
831 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
832 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
833 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
834 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
835 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
836 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
837 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
838 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
839 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
840 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
841 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
842 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
843 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
844 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
845 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
846 }
847
848 if (Subtarget->hasNEON()) {
849 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
850 // supported for v4f32.
851 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
852 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
853 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
854 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
855 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
856 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
857 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
858 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
859 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
860 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
861 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
862 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
863 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
864 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
865
866 // Mark v2f32 intrinsics.
867 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
868 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
869 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
870 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
871 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
872 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
873 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
874 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
875 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
876 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
877 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
878 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
879 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
880 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
881
882 // Neon does not support some operations on v1i64 and v2i64 types.
883 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
884 // Custom handling for some quad-vector types to detect VMULL.
885 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
886 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
887 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
888 // Custom handling for some vector types to avoid expensive expansions
889 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
890 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
891 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
892 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
893 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
894 // a destination type that is wider than the source, and nor does
895 // it have a FP_TO_[SU]INT instruction with a narrower destination than
896 // source.
897 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
898 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
899 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
900 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
901 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
902 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
903 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
904 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
905
906 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
907 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
908
909 // NEON does not have single instruction CTPOP for vectors with element
910 // types wider than 8-bits. However, custom lowering can leverage the
911 // v8i8/v16i8 vcnt instruction.
912 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
913 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
914 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
915 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
916 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
917 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
918
919 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
920 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
921
922 // NEON does not have single instruction CTTZ for vectors.
923 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
924 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
925 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
926 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
927
928 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
929 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
930 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
931 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
932
933 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
934 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
935 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
936 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
937
938 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
939 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
940 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
941 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
942
943 // NEON only has FMA instructions as of VFP4.
944 if (!Subtarget->hasVFP4Base()) {
945 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
946 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
947 }
948
949 setTargetDAGCombine(ISD::SHL);
950 setTargetDAGCombine(ISD::SRL);
951 setTargetDAGCombine(ISD::SRA);
952 setTargetDAGCombine(ISD::FP_TO_SINT);
953 setTargetDAGCombine(ISD::FP_TO_UINT);
954 setTargetDAGCombine(ISD::FDIV);
955 setTargetDAGCombine(ISD::LOAD);
956
957 // It is legal to extload from v4i8 to v4i16 or v4i32.
958 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
959 MVT::v2i32}) {
960 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
961 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
962 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
963 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
964 }
965 }
966 }
967
968 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
969 setTargetDAGCombine(ISD::BUILD_VECTOR);
970 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
971 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
972 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
973 setTargetDAGCombine(ISD::STORE);
974 setTargetDAGCombine(ISD::SIGN_EXTEND);
975 setTargetDAGCombine(ISD::ZERO_EXTEND);
976 setTargetDAGCombine(ISD::ANY_EXTEND);
977 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
978 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
979 setTargetDAGCombine(ISD::INTRINSIC_VOID);
980 setTargetDAGCombine(ISD::VECREDUCE_ADD);
981 setTargetDAGCombine(ISD::ADD);
982 setTargetDAGCombine(ISD::BITCAST);
983 }
984 if (Subtarget->hasMVEIntegerOps()) {
985 setTargetDAGCombine(ISD::SMIN);
986 setTargetDAGCombine(ISD::UMIN);
987 setTargetDAGCombine(ISD::SMAX);
988 setTargetDAGCombine(ISD::UMAX);
989 setTargetDAGCombine(ISD::FP_EXTEND);
990 }
991
992 if (!Subtarget->hasFP64()) {
993 // When targeting a floating-point unit with only single-precision
994 // operations, f64 is legal for the few double-precision instructions which
995 // are present However, no double-precision operations other than moves,
996 // loads and stores are provided by the hardware.
997 setOperationAction(ISD::FADD, MVT::f64, Expand);
998 setOperationAction(ISD::FSUB, MVT::f64, Expand);
999 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1000 setOperationAction(ISD::FMA, MVT::f64, Expand);
1001 setOperationAction(ISD::FDIV, MVT::f64, Expand);
1002 setOperationAction(ISD::FREM, MVT::f64, Expand);
1003 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1004 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
1005 setOperationAction(ISD::FNEG, MVT::f64, Expand);
1006 setOperationAction(ISD::FABS, MVT::f64, Expand);
1007 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
1008 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1009 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1010 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1011 setOperationAction(ISD::FLOG, MVT::f64, Expand);
1012 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
1013 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
1014 setOperationAction(ISD::FEXP, MVT::f64, Expand);
1015 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
1016 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
1017 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
1018 setOperationAction(ISD::FRINT, MVT::f64, Expand);
1019 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
1020 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
1021 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1022 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1023 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1024 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1025 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
1026 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
1027 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1028 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
1029 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
1030 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::f64, Custom);
1031 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::f64, Custom);
1032 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
1033 }
1034
1035 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
1036 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
1037 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Custom);
1038 if (Subtarget->hasFullFP16()) {
1039 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1040 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1041 }
1042 }
1043
1044 if (!Subtarget->hasFP16()) {
1045 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
1046 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Custom);
1047 }
1048
1049 computeRegisterProperties(Subtarget->getRegisterInfo());
1050
1051 // ARM does not have floating-point extending loads.
1052 for (MVT VT : MVT::fp_valuetypes()) {
1053 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1054 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1055 }
1056
1057 // ... or truncating stores
1058 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1059 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1060 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1061
1062 // ARM does not have i1 sign extending load.
1063 for (MVT VT : MVT::integer_valuetypes())
1064 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1065
1066 // ARM supports all 4 flavors of integer indexed load / store.
1067 if (!Subtarget->isThumb1Only()) {
1068 for (unsigned im = (unsigned)ISD::PRE_INC;
1069 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1070 setIndexedLoadAction(im, MVT::i1, Legal);
1071 setIndexedLoadAction(im, MVT::i8, Legal);
1072 setIndexedLoadAction(im, MVT::i16, Legal);
1073 setIndexedLoadAction(im, MVT::i32, Legal);
1074 setIndexedStoreAction(im, MVT::i1, Legal);
1075 setIndexedStoreAction(im, MVT::i8, Legal);
1076 setIndexedStoreAction(im, MVT::i16, Legal);
1077 setIndexedStoreAction(im, MVT::i32, Legal);
1078 }
1079 } else {
1080 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1081 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1082 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1083 }
1084
1085 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1086 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1087 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1088 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1089
1090 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1091 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1092 if (Subtarget->hasDSP()) {
1093 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1094 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1095 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1096 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1097 }
1098 if (Subtarget->hasBaseDSP()) {
1099 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1100 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1101 }
1102
1103 // i64 operation support.
1104 setOperationAction(ISD::MUL, MVT::i64, Expand);
1105 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1106 if (Subtarget->isThumb1Only()) {
1107 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1108 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1109 }
1110 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1111 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1112 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1113
1114 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1115 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1116 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1117 setOperationAction(ISD::SRL, MVT::i64, Custom);
1118 setOperationAction(ISD::SRA, MVT::i64, Custom);
1119 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1121 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1122 setOperationAction(ISD::STORE, MVT::i64, Custom);
1123
1124 // MVE lowers 64 bit shifts to lsll and lsrl
1125 // assuming that ISD::SRL and SRA of i64 are already marked custom
1126 if (Subtarget->hasMVEIntegerOps())
1127 setOperationAction(ISD::SHL, MVT::i64, Custom);
1128
1129 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1130 if (Subtarget->isThumb1Only()) {
1131 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1132 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1133 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1134 }
1135
1136 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1137 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1138
1139 // ARM does not have ROTL.
1140 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1141 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1142 setOperationAction(ISD::ROTL, VT, Expand);
1143 setOperationAction(ISD::ROTR, VT, Expand);
1144 }
1145 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1146 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1147 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1148 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1149 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1150 }
1151
1152 // @llvm.readcyclecounter requires the Performance Monitors extension.
1153 // Default to the 0 expansion on unsupported platforms.
1154 // FIXME: Technically there are older ARM CPUs that have
1155 // implementation-specific ways of obtaining this information.
1156 if (Subtarget->hasPerfMon())
1157 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1158
1159 // Only ARMv6 has BSWAP.
1160 if (!Subtarget->hasV6Ops())
1161 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1162
1163 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1164 : Subtarget->hasDivideInARMMode();
1165 if (!hasDivide) {
1166 // These are expanded into libcalls if the cpu doesn't have HW divider.
1167 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1168 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1169 }
1170
1171 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1172 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1173 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1174
1175 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1176 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1177 }
1178
1179 setOperationAction(ISD::SREM, MVT::i32, Expand);
1180 setOperationAction(ISD::UREM, MVT::i32, Expand);
1181
1182 // Register based DivRem for AEABI (RTABI 4.2)
1183 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1184 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1185 Subtarget->isTargetWindows()) {
1186 setOperationAction(ISD::SREM, MVT::i64, Custom);
1187 setOperationAction(ISD::UREM, MVT::i64, Custom);
1188 HasStandaloneRem = false;
1189
1190 if (Subtarget->isTargetWindows()) {
1191 const struct {
1192 const RTLIB::Libcall Op;
1193 const char * const Name;
1194 const CallingConv::ID CC;
1195 } LibraryCalls[] = {
1196 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1197 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1198 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1199 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1200
1201 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1202 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1203 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1204 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1205 };
1206
1207 for (const auto &LC : LibraryCalls) {
1208 setLibcallName(LC.Op, LC.Name);
1209 setLibcallCallingConv(LC.Op, LC.CC);
1210 }
1211 } else {
1212 const struct {
1213 const RTLIB::Libcall Op;
1214 const char * const Name;
1215 const CallingConv::ID CC;
1216 } LibraryCalls[] = {
1217 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1218 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1219 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1220 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1221
1222 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1223 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1224 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1225 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1226 };
1227
1228 for (const auto &LC : LibraryCalls) {
1229 setLibcallName(LC.Op, LC.Name);
1230 setLibcallCallingConv(LC.Op, LC.CC);
1231 }
1232 }
1233
1234 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1235 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1236 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1237 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1238 } else {
1239 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1240 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1241 }
1242
1243 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1244 // MSVCRT doesn't have powi; fall back to pow
1245 setLibcallName(RTLIB::POWI_F32, nullptr);
1246 setLibcallName(RTLIB::POWI_F64, nullptr);
1247 }
1248
1249 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1250 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1251 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1252 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1253
1254 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1255 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1256
1257 // Use the default implementation.
1258 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1259 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1260 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1261 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1262 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1263 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1264
1265 if (Subtarget->isTargetWindows())
1266 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1267 else
1268 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1269
1270 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1271 // the default expansion.
1272 InsertFencesForAtomic = false;
1273 if (Subtarget->hasAnyDataBarrier() &&
1274 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1275 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1276 // to ldrex/strex loops already.
1277 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1278 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1279 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1280
1281 // On v8, we have particularly efficient implementations of atomic fences
1282 // if they can be combined with nearby atomic loads and stores.
1283 if (!Subtarget->hasAcquireRelease() ||
1284 getTargetMachine().getOptLevel() == 0) {
1285 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1286 InsertFencesForAtomic = true;
1287 }
1288 } else {
1289 // If there's anything we can use as a barrier, go through custom lowering
1290 // for ATOMIC_FENCE.
1291 // If target has DMB in thumb, Fences can be inserted.
1292 if (Subtarget->hasDataBarrier())
1293 InsertFencesForAtomic = true;
1294
1295 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1296 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1297
1298 // Set them all for expansion, which will force libcalls.
1299 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1300 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1301 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1302 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1303 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1304 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1305 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1306 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1307 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1308 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1309 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1310 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1311 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1312 // Unordered/Monotonic case.
1313 if (!InsertFencesForAtomic) {
1314 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1315 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1316 }
1317 }
1318
1319 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1320
1321 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1322 if (!Subtarget->hasV6Ops()) {
1323 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1324 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1325 }
1326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1327
1328 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1329 !Subtarget->isThumb1Only()) {
1330 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1331 // iff target supports vfp2.
1332 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1333 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1334 }
1335
1336 // We want to custom lower some of our intrinsics.
1337 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1338 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1339 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1340 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1341 if (Subtarget->useSjLjEH())
1342 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1343
1344 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1345 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1346 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1347 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1348 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1349 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1350 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1351 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1352 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1353 if (Subtarget->hasFullFP16()) {
1354 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1355 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1356 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1357 }
1358
1359 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1360
1361 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1362 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1363 if (Subtarget->hasFullFP16())
1364 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1365 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1366 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1367 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1368
1369 // We don't support sin/cos/fmod/copysign/pow
1370 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1371 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1372 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1373 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1374 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1375 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1376 setOperationAction(ISD::FREM, MVT::f64, Expand);
1377 setOperationAction(ISD::FREM, MVT::f32, Expand);
1378 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1379 !Subtarget->isThumb1Only()) {
1380 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1381 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1382 }
1383 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1384 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1385
1386 if (!Subtarget->hasVFP4Base()) {
1387 setOperationAction(ISD::FMA, MVT::f64, Expand);
1388 setOperationAction(ISD::FMA, MVT::f32, Expand);
1389 }
1390
1391 // Various VFP goodness
1392 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1393 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1394 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1395 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1396 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1397 }
1398
1399 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1400 if (!Subtarget->hasFP16()) {
1401 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1402 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1403 }
1404
1405 // Strict floating-point comparisons need custom lowering.
1406 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1407 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1408 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
1409 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
1410 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
1411 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
1412 }
1413
1414 // Use __sincos_stret if available.
1415 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1416 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1417 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1418 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1419 }
1420
1421 // FP-ARMv8 implements a lot of rounding-like FP operations.
1422 if (Subtarget->hasFPARMv8Base()) {
1423 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1424 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1425 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1426 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1427 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1428 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1429 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1430 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1431 if (Subtarget->hasNEON()) {
1432 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1433 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1434 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1435 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1436 }
1437
1438 if (Subtarget->hasFP64()) {
1439 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1440 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1441 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1442 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1443 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1444 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1445 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1446 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1447 }
1448 }
1449
1450 // FP16 often need to be promoted to call lib functions
1451 if (Subtarget->hasFullFP16()) {
1452 setOperationAction(ISD::FREM, MVT::f16, Promote);
1453 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1454 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1455 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1456 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1457 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1458 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1459 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1460 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1461 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1462 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1463 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1464
1465 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1466 }
1467
1468 if (Subtarget->hasNEON()) {
1469 // vmin and vmax aren't available in a scalar form, so we can use
1470 // a NEON instruction with an undef lane instead. This has a performance
1471 // penalty on some cores, so we don't do this unless we have been
1472 // asked to by the core tuning model.
1473 if (Subtarget->useNEONForSinglePrecisionFP()) {
1474 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1475 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1476 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1477 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1478 }
1479 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1480 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1481 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1482 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1483
1484 if (Subtarget->hasFullFP16()) {
1485 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1486 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1487 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1488 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1489
1490 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1491 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1492 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1493 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1494 }
1495 }
1496
1497 // We have target-specific dag combine patterns for the following nodes:
1498 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1499 setTargetDAGCombine(ISD::ADD);
1500 setTargetDAGCombine(ISD::SUB);
1501 setTargetDAGCombine(ISD::MUL);
1502 setTargetDAGCombine(ISD::AND);
1503 setTargetDAGCombine(ISD::OR);
1504 setTargetDAGCombine(ISD::XOR);
1505
1506 if (Subtarget->hasMVEIntegerOps())
1507 setTargetDAGCombine(ISD::VSELECT);
1508
1509 if (Subtarget->hasV6Ops())
1510 setTargetDAGCombine(ISD::SRL);
1511 if (Subtarget->isThumb1Only())
1512 setTargetDAGCombine(ISD::SHL);
1513
1514 setStackPointerRegisterToSaveRestore(ARM::SP);
1515
1516 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1517 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1518 setSchedulingPreference(Sched::RegPressure);
1519 else
1520 setSchedulingPreference(Sched::Hybrid);
1521
1522 //// temporary - rewrite interface to use type
1523 MaxStoresPerMemset = 8;
1524 MaxStoresPerMemsetOptSize = 4;
1525 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1526 MaxStoresPerMemcpyOptSize = 2;
1527 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1528 MaxStoresPerMemmoveOptSize = 2;
1529
1530 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1531 // are at least 4 bytes aligned.
1532 setMinStackArgumentAlignment(Align(4));
1533
1534 // Prefer likely predicted branches to selects on out-of-order cores.
1535 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1536
1537 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1538
1539 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1540
1541 if (Subtarget->isThumb() || Subtarget->isThumb2())
1542 setTargetDAGCombine(ISD::ABS);
1543}
1544
1545bool ARMTargetLowering::useSoftFloat() const {
1546 return Subtarget->useSoftFloat();
1547}
1548
1549// FIXME: It might make sense to define the representative register class as the
1550// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1551// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1552// SPR's representative would be DPR_VFP2. This should work well if register
1553// pressure tracking were modified such that a register use would increment the
1554// pressure of the register class's representative and all of it's super
1555// classes' representatives transitively. We have not implemented this because
1556// of the difficulty prior to coalescing of modeling operand register classes
1557// due to the common occurrence of cross class copies and subregister insertions
1558// and extractions.
1559std::pair<const TargetRegisterClass *, uint8_t>
1560ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1561 MVT VT) const {
1562 const TargetRegisterClass *RRC = nullptr;
1563 uint8_t Cost = 1;
1564 switch (VT.SimpleTy) {
1565 default:
1566 return TargetLowering::findRepresentativeClass(TRI, VT);
1567 // Use DPR as representative register class for all floating point
1568 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1569 // the cost is 1 for both f32 and f64.
1570 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1571 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1572 RRC = &ARM::DPRRegClass;
1573 // When NEON is used for SP, only half of the register file is available
1574 // because operations that define both SP and DP results will be constrained
1575 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1576 // coalescing by double-counting the SP regs. See the FIXME above.
1577 if (Subtarget->useNEONForSinglePrecisionFP())
1578 Cost = 2;
1579 break;
1580 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1581 case MVT::v4f32: case MVT::v2f64:
1582 RRC = &ARM::DPRRegClass;
1583 Cost = 2;
1584 break;
1585 case MVT::v4i64:
1586 RRC = &ARM::DPRRegClass;
1587 Cost = 4;
1588 break;
1589 case MVT::v8i64:
1590 RRC = &ARM::DPRRegClass;
1591 Cost = 8;
1592 break;
1593 }
1594 return std::make_pair(RRC, Cost);
1595}
1596
1597const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1598 switch ((ARMISD::NodeType)Opcode) {
1599 case ARMISD::FIRST_NUMBER: break;
1600 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1601 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1602 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1603 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1604 case ARMISD::CALL: return "ARMISD::CALL";
1605 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1606 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1607 case ARMISD::tSECALL: return "ARMISD::tSECALL";
1608 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1609 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1610 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1611 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1612 case ARMISD::SERET_FLAG: return "ARMISD::SERET_FLAG";
1613 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1614 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1615 case ARMISD::CMP: return "ARMISD::CMP";
1616 case ARMISD::CMN: return "ARMISD::CMN";
1617 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1618 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1619 case ARMISD::CMPFPE: return "ARMISD::CMPFPE";
1620 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1621 case ARMISD::CMPFPEw0: return "ARMISD::CMPFPEw0";
1622 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1623 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1624
1625 case ARMISD::CMOV: return "ARMISD::CMOV";
1626 case ARMISD::SUBS: return "ARMISD::SUBS";
1627
1628 case ARMISD::SSAT: return "ARMISD::SSAT";
1629 case ARMISD::USAT: return "ARMISD::USAT";
1630
1631 case ARMISD::ASRL: return "ARMISD::ASRL";
1632 case ARMISD::LSRL: return "ARMISD::LSRL";
1633 case ARMISD::LSLL: return "ARMISD::LSLL";
1634
1635 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1636 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1637 case ARMISD::RRX: return "ARMISD::RRX";
1638
1639 case ARMISD::ADDC: return "ARMISD::ADDC";
1640 case ARMISD::ADDE: return "ARMISD::ADDE";
1641 case ARMISD::SUBC: return "ARMISD::SUBC";
1642 case ARMISD::SUBE: return "ARMISD::SUBE";
1643 case ARMISD::LSLS: return "ARMISD::LSLS";
1644
1645 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1646 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1647 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1648 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1649 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1650
1651 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1652 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1653 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1654
1655 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1656
1657 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1658
1659 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1660
1661 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1662
1663 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1664
1665 case ARMISD::LDRD: return "ARMISD::LDRD";
1666 case ARMISD::STRD: return "ARMISD::STRD";
1667
1668 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1669 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1670
1671 case ARMISD::PREDICATE_CAST: return "ARMISD::PREDICATE_CAST";
1672 case ARMISD::VECTOR_REG_CAST: return "ARMISD::VECTOR_REG_CAST";
1673 case ARMISD::VCMP: return "ARMISD::VCMP";
1674 case ARMISD::VCMPZ: return "ARMISD::VCMPZ";
1675 case ARMISD::VTST: return "ARMISD::VTST";
1676
1677 case ARMISD::VSHLs: return "ARMISD::VSHLs";
1678 case ARMISD::VSHLu: return "ARMISD::VSHLu";
1679 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM";
1680 case ARMISD::VSHRsIMM: return "ARMISD::VSHRsIMM";
1681 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM";
1682 case ARMISD::VRSHRsIMM: return "ARMISD::VRSHRsIMM";
1683 case ARMISD::VRSHRuIMM: return "ARMISD::VRSHRuIMM";
1684 case ARMISD::VRSHRNIMM: return "ARMISD::VRSHRNIMM";
1685 case ARMISD::VQSHLsIMM: return "ARMISD::VQSHLsIMM";
1686 case ARMISD::VQSHLuIMM: return "ARMISD::VQSHLuIMM";
1687 case ARMISD::VQSHLsuIMM: return "ARMISD::VQSHLsuIMM";
1688 case ARMISD::VQSHRNsIMM: return "ARMISD::VQSHRNsIMM";
1689 case ARMISD::VQSHRNuIMM: return "ARMISD::VQSHRNuIMM";
1690 case ARMISD::VQSHRNsuIMM: return "ARMISD::VQSHRNsuIMM";
1691 case ARMISD::VQRSHRNsIMM: return "ARMISD::VQRSHRNsIMM";
1692 case ARMISD::VQRSHRNuIMM: return "ARMISD::VQRSHRNuIMM";
1693 case ARMISD::VQRSHRNsuIMM: return "ARMISD::VQRSHRNsuIMM";
1694 case ARMISD::VSLIIMM: return "ARMISD::VSLIIMM";
1695 case ARMISD::VSRIIMM: return "ARMISD::VSRIIMM";
1696 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1697 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1698 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1699 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1700 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1701 case ARMISD::VDUP: return "ARMISD::VDUP";
1702 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1703 case ARMISD::VEXT: return "ARMISD::VEXT";
1704 case ARMISD::VREV64: return "ARMISD::VREV64";
1705 case ARMISD::VREV32: return "ARMISD::VREV32";
1706 case ARMISD::VREV16: return "ARMISD::VREV16";
1707 case ARMISD::VZIP: return "ARMISD::VZIP";
1708 case ARMISD::VUZP: return "ARMISD::VUZP";
1709 case ARMISD::VTRN: return "ARMISD::VTRN";
1710 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1711 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1712 case ARMISD::VMOVN: return "ARMISD::VMOVN";
1713 case ARMISD::VQMOVNs: return "ARMISD::VQMOVNs";
1714 case ARMISD::VQMOVNu: return "ARMISD::VQMOVNu";
1715 case ARMISD::VCVTN: return "ARMISD::VCVTN";
1716 case ARMISD::VCVTL: return "ARMISD::VCVTL";
1717 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1718 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1719 case ARMISD::VADDVs: return "ARMISD::VADDVs";
1720 case ARMISD::VADDVu: return "ARMISD::VADDVu";
1721 case ARMISD::VADDVps: return "ARMISD::VADDVps";
1722 case ARMISD::VADDVpu: return "ARMISD::VADDVpu";
1723 case ARMISD::VADDLVs: return "ARMISD::VADDLVs";
1724 case ARMISD::VADDLVu: return "ARMISD::VADDLVu";
1725 case ARMISD::VADDLVAs: return "ARMISD::VADDLVAs";
1726 case ARMISD::VADDLVAu: return "ARMISD::VADDLVAu";
1727 case ARMISD::VADDLVps: return "ARMISD::VADDLVps";
1728 case ARMISD::VADDLVpu: return "ARMISD::VADDLVpu";
1729 case ARMISD::VADDLVAps: return "ARMISD::VADDLVAps";
1730 case ARMISD::VADDLVApu: return "ARMISD::VADDLVApu";
1731 case ARMISD::VMLAVs: return "ARMISD::VMLAVs";
1732 case ARMISD::VMLAVu: return "ARMISD::VMLAVu";
1733 case ARMISD::VMLAVps: return "ARMISD::VMLAVps";
1734 case ARMISD::VMLAVpu: return "ARMISD::VMLAVpu";
1735 case ARMISD::VMLALVs: return "ARMISD::VMLALVs";
1736 case ARMISD::VMLALVu: return "ARMISD::VMLALVu";
1737 case ARMISD::VMLALVps: return "ARMISD::VMLALVps";
1738 case ARMISD::VMLALVpu: return "ARMISD::VMLALVpu";
1739 case ARMISD::VMLALVAs: return "ARMISD::VMLALVAs";
1740 case ARMISD::VMLALVAu: return "ARMISD::VMLALVAu";
1741 case ARMISD::VMLALVAps: return "ARMISD::VMLALVAps";
1742 case ARMISD::VMLALVApu: return "ARMISD::VMLALVApu";
1743 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1744 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1745 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1746 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1747 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1748 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1749 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1750 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1751 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1752 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1753 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1754 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1755 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1756 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1757 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1758 case ARMISD::QADD16b: return "ARMISD::QADD16b";
1759 case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
1760 case ARMISD::QADD8b: return "ARMISD::QADD8b";
1761 case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
1762 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1763 case ARMISD::BFI: return "ARMISD::BFI";
1764 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1765 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1766 case ARMISD::VBSP: return "ARMISD::VBSP";
1767 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1768 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1769 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1770 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1771 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1772 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1773 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1774 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1775 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1776 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1777 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1778 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1779 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1780 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1781 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1782 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1783 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1784 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1785 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1786 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1787 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1788 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1789 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1790 case ARMISD::WLS: return "ARMISD::WLS";
1791 case ARMISD::LE: return "ARMISD::LE";
1792 case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
1793 case ARMISD::CSINV: return "ARMISD::CSINV";
1794 case ARMISD::CSNEG: return "ARMISD::CSNEG";
1795 case ARMISD::CSINC: return "ARMISD::CSINC";
1796 }
1797 return nullptr;
1798}
1799
1800EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1801 EVT VT) const {
1802 if (!VT.isVector())
1803 return getPointerTy(DL);
1804
1805 // MVE has a predicate register.
1806 if (Subtarget->hasMVEIntegerOps() &&
1807 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1808 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1809 return VT.changeVectorElementTypeToInteger();
1810}
1811
1812/// getRegClassFor - Return the register class that should be used for the
1813/// specified value type.
1814const TargetRegisterClass *
1815ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1816 (void)isDivergent;
1817 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1818 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1819 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1820 // MVE Q registers.
1821 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1822 if (VT == MVT::v4i64)
1823 return &ARM::QQPRRegClass;
1824 if (VT == MVT::v8i64)
1825 return &ARM::QQQQPRRegClass;
1826 }
1827 return TargetLowering::getRegClassFor(VT);
1828}
1829
1830// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1831// source/dest is aligned and the copy size is large enough. We therefore want
1832// to align such objects passed to memory intrinsics.
1833bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1834 unsigned &PrefAlign) const {
1835 if (!isa<MemIntrinsic>(CI))
1836 return false;
1837 MinSize = 8;
1838 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1839 // cycle faster than 4-byte aligned LDM.
1840 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1841 return true;
1842}
1843
1844// Create a fast isel object.
1845FastISel *
1846ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1847 const TargetLibraryInfo *libInfo) const {
1848 return ARM::createFastISel(funcInfo, libInfo);
1849}
1850
1851Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1852 unsigned NumVals = N->getNumValues();
1853 if (!NumVals)
1854 return Sched::RegPressure;
1855
1856 for (unsigned i = 0; i != NumVals; ++i) {
1857 EVT VT = N->getValueType(i);
1858 if (VT == MVT::Glue || VT == MVT::Other)
1859 continue;
1860 if (VT.isFloatingPoint() || VT.isVector())
1861 return Sched::ILP;
1862 }
1863
1864 if (!N->isMachineOpcode())
1865 return Sched::RegPressure;
1866
1867 // Load are scheduled for latency even if there instruction itinerary
1868 // is not available.
1869 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1870 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1871
1872 if (MCID.getNumDefs() == 0)
1873 return Sched::RegPressure;
1874 if (!Itins->isEmpty() &&
1875 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1876 return Sched::ILP;
1877
1878 return Sched::RegPressure;
1879}
1880
1881//===----------------------------------------------------------------------===//
1882// Lowering Code
1883//===----------------------------------------------------------------------===//
1884
1885static bool isSRL16(const SDValue &Op) {
1886 if (Op.getOpcode() != ISD::SRL)
1887 return false;
1888 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1889 return Const->getZExtValue() == 16;
1890 return false;
1891}
1892
1893static bool isSRA16(const SDValue &Op) {
1894 if (Op.getOpcode() != ISD::SRA)
1895 return false;
1896 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1897 return Const->getZExtValue() == 16;
1898 return false;
1899}
1900
1901static bool isSHL16(const SDValue &Op) {
1902 if (Op.getOpcode() != ISD::SHL)
1903 return false;
1904 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1905 return Const->getZExtValue() == 16;
1906 return false;
1907}
1908
1909// Check for a signed 16-bit value. We special case SRA because it makes it
1910// more simple when also looking for SRAs that aren't sign extending a
1911// smaller value. Without the check, we'd need to take extra care with
1912// checking order for some operations.
1913static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1914 if (isSRA16(Op))
1915 return isSHL16(Op.getOperand(0));
1916 return DAG.ComputeNumSignBits(Op) == 17;
1917}
1918
1919/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1920static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1921 switch (CC) {
1922 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1922)
;
1923 case ISD::SETNE: return ARMCC::NE;
1924 case ISD::SETEQ: return ARMCC::EQ;
1925 case ISD::SETGT: return ARMCC::GT;
1926 case ISD::SETGE: return ARMCC::GE;
1927 case ISD::SETLT: return ARMCC::LT;
1928 case ISD::SETLE: return ARMCC::LE;
1929 case ISD::SETUGT: return ARMCC::HI;
1930 case ISD::SETUGE: return ARMCC::HS;
1931 case ISD::SETULT: return ARMCC::LO;
1932 case ISD::SETULE: return ARMCC::LS;
1933 }
1934}
1935
1936/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1937static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1938 ARMCC::CondCodes &CondCode2) {
1939 CondCode2 = ARMCC::AL;
1940 switch (CC) {
1941 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1941)
;
1942 case ISD::SETEQ:
1943 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1944 case ISD::SETGT:
1945 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1946 case ISD::SETGE:
1947 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1948 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1949 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1950 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1951 case ISD::SETO: CondCode = ARMCC::VC; break;
1952 case ISD::SETUO: CondCode = ARMCC::VS; break;
1953 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1954 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1955 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1956 case ISD::SETLT:
1957 case ISD::SETULT: CondCode = ARMCC::LT; break;
1958 case ISD::SETLE:
1959 case ISD::SETULE: CondCode = ARMCC::LE; break;
1960 case ISD::SETNE:
1961 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1962 }
1963}
1964
1965//===----------------------------------------------------------------------===//
1966// Calling Convention Implementation
1967//===----------------------------------------------------------------------===//
1968
1969/// getEffectiveCallingConv - Get the effective calling convention, taking into
1970/// account presence of floating point hardware and calling convention
1971/// limitations, such as support for variadic functions.
1972CallingConv::ID
1973ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1974 bool isVarArg) const {
1975 switch (CC) {
1976 default:
1977 report_fatal_error("Unsupported calling convention");
1978 case CallingConv::ARM_AAPCS:
1979 case CallingConv::ARM_APCS:
1980 case CallingConv::GHC:
1981 case CallingConv::CFGuard_Check:
1982 return CC;
1983 case CallingConv::PreserveMost:
1984 return CallingConv::PreserveMost;
1985 case CallingConv::ARM_AAPCS_VFP:
1986 case CallingConv::Swift:
1987 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1988 case CallingConv::C:
1989 if (!Subtarget->isAAPCS_ABI())
1990 return CallingConv::ARM_APCS;
1991 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
1992 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1993 !isVarArg)
1994 return CallingConv::ARM_AAPCS_VFP;
1995 else
1996 return CallingConv::ARM_AAPCS;
1997 case CallingConv::Fast:
1998 case CallingConv::CXX_FAST_TLS:
1999 if (!Subtarget->isAAPCS_ABI()) {
2000 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
2001 return CallingConv::Fast;
2002 return CallingConv::ARM_APCS;
2003 } else if (Subtarget->hasVFP2Base() &&
2004 !Subtarget->isThumb1Only() && !isVarArg)
2005 return CallingConv::ARM_AAPCS_VFP;
2006 else
2007 return CallingConv::ARM_AAPCS;
2008 }
2009}
2010
2011CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2012 bool isVarArg) const {
2013 return CCAssignFnForNode(CC, false, isVarArg);
2014}
2015
2016CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
2017 bool isVarArg) const {
2018 return CCAssignFnForNode(CC, true, isVarArg);
2019}
2020
2021/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
2022/// CallingConvention.
2023CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
2024 bool Return,
2025 bool isVarArg) const {
2026 switch (getEffectiveCallingConv(CC, isVarArg)) {
2027 default:
2028 report_fatal_error("Unsupported calling convention");
2029 case CallingConv::ARM_APCS:
2030 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
2031 case CallingConv::ARM_AAPCS:
2032 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2033 case CallingConv::ARM_AAPCS_VFP:
2034 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
2035 case CallingConv::Fast:
2036 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
2037 case CallingConv::GHC:
2038 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
2039 case CallingConv::PreserveMost:
2040 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
2041 case CallingConv::CFGuard_Check:
2042 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
2043 }
2044}
2045
2046SDValue ARMTargetLowering::MoveToHPR(const SDLoc &dl, SelectionDAG &DAG,
2047 MVT LocVT, MVT ValVT, SDValue Val) const {
2048 Val = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocVT.getSizeInBits()),
2049 Val);
2050 if (Subtarget->hasFullFP16()) {
2051 Val = DAG.getNode(ARMISD::VMOVhr, dl, ValVT, Val);
2052 } else {
2053 Val = DAG.getNode(ISD::TRUNCATE, dl,
2054 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2055 Val = DAG.getNode(ISD::BITCAST, dl, ValVT, Val);
2056 }
2057 return Val;
2058}
2059
2060SDValue ARMTargetLowering::MoveFromHPR(const SDLoc &dl, SelectionDAG &DAG,
2061 MVT LocVT, MVT ValVT,
2062 SDValue Val) const {
2063 if (Subtarget->hasFullFP16()) {
2064 Val = DAG.getNode(ARMISD::VMOVrh, dl,
2065 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2066 } else {
2067 Val = DAG.getNode(ISD::BITCAST, dl,
2068 MVT::getIntegerVT(ValVT.getSizeInBits()), Val);
2069 Val = DAG.getNode(ISD::ZERO_EXTEND, dl,
2070 MVT::getIntegerVT(LocVT.getSizeInBits()), Val);
2071 }
2072 return DAG.getNode(ISD::BITCAST, dl, LocVT, Val);
2073}
2074
2075/// LowerCallResult - Lower the result values of a call into the
2076/// appropriate copies out of appropriate physical registers.
2077SDValue ARMTargetLowering::LowerCallResult(
2078 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2079 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
2080 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2081 SDValue ThisVal) const {
2082 // Assign locations to each value returned by this call.
2083 SmallVector<CCValAssign, 16> RVLocs;
2084 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2085 *DAG.getContext());
2086 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
2087
2088 // Copy all of the result registers out of their specified physreg.
2089 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2090 CCValAssign VA = RVLocs[i];
2091
2092 // Pass 'this' value directly from the argument to return value, to avoid
2093 // reg unit interference
2094 if (i == 0 && isThisReturn) {
2095 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2096, __PRETTY_FUNCTION__))
2096 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2096, __PRETTY_FUNCTION__))
;
2097 InVals.push_back(ThisVal);
2098 continue;
2099 }
2100
2101 SDValue Val;
2102 if (VA.needsCustom() &&
2103 (VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2f64)) {
2104 // Handle f64 or half of a v2f64.
2105 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2106 InFlag);
2107 Chain = Lo.getValue(1);
2108 InFlag = Lo.getValue(2);
2109 VA = RVLocs[++i]; // skip ahead to next loc
2110 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
2111 InFlag);
2112 Chain = Hi.getValue(1);
2113 InFlag = Hi.getValue(2);
2114 if (!Subtarget->isLittle())
2115 std::swap (Lo, Hi);
2116 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2117
2118 if (VA.getLocVT() == MVT::v2f64) {
2119 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2120 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2121 DAG.getConstant(0, dl, MVT::i32));
2122
2123 VA = RVLocs[++i]; // skip ahead to next loc
2124 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2125 Chain = Lo.getValue(1);
2126 InFlag = Lo.getValue(2);
2127 VA = RVLocs[++i]; // skip ahead to next loc
2128 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
2129 Chain = Hi.getValue(1);
2130 InFlag = Hi.getValue(2);
2131 if (!Subtarget->isLittle())
2132 std::swap (Lo, Hi);
2133 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2134 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
2135 DAG.getConstant(1, dl, MVT::i32));
2136 }
2137 } else {
2138 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
2139 InFlag);
2140 Chain = Val.getValue(1);
2141 InFlag = Val.getValue(2);
2142 }
2143
2144 switch (VA.getLocInfo()) {
2145 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2145)
;
2146 case CCValAssign::Full: break;
2147 case CCValAssign::BCvt:
2148 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
2149 break;
2150 }
2151
2152 // f16 arguments have their size extended to 4 bytes and passed as if they
2153 // had been copied to the LSBs of a 32-bit register.
2154 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2155 if (VA.needsCustom() &&
2156 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2157 Val = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Val);
2158
2159 InVals.push_back(Val);
2160 }
2161
2162 return Chain;
2163}
2164
2165/// LowerMemOpCallTo - Store the argument to the stack.
2166SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
2167 SDValue Arg, const SDLoc &dl,
2168 SelectionDAG &DAG,
2169 const CCValAssign &VA,
2170 ISD::ArgFlagsTy Flags) const {
2171 unsigned LocMemOffset = VA.getLocMemOffset();
2172 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2173 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2174 StackPtr, PtrOff);
2175 return DAG.getStore(
2176 Chain, dl, Arg, PtrOff,
2177 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
2178}
2179
2180void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2181 SDValue Chain, SDValue &Arg,
2182 RegsToPassVector &RegsToPass,
2183 CCValAssign &VA, CCValAssign &NextVA,
2184 SDValue &StackPtr,
2185 SmallVectorImpl<SDValue> &MemOpChains,
2186 ISD::ArgFlagsTy Flags) const {
2187 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2188 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2189 unsigned id = Subtarget->isLittle() ? 0 : 1;
2190 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2191
2192 if (NextVA.isRegLoc())
2193 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2194 else {
2195 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2195, __PRETTY_FUNCTION__))
;
2196 if (!StackPtr.getNode())
2197 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2198 getPointerTy(DAG.getDataLayout()));
2199
2200 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
2201 dl, DAG, NextVA,
2202 Flags));
2203 }
2204}
2205
2206/// LowerCall - Lowering a call into a callseq_start <-
2207/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2208/// nodes.
2209SDValue
2210ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2211 SmallVectorImpl<SDValue> &InVals) const {
2212 SelectionDAG &DAG = CLI.DAG;
2213 SDLoc &dl = CLI.DL;
2214 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2215 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2216 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2217 SDValue Chain = CLI.Chain;
2218 SDValue Callee = CLI.Callee;
2219 bool &isTailCall = CLI.IsTailCall;
2220 CallingConv::ID CallConv = CLI.CallConv;
2221 bool doesNotRet = CLI.DoesNotReturn;
2222 bool isVarArg = CLI.IsVarArg;
2223
2224 MachineFunction &MF = DAG.getMachineFunction();
2225 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2226 MachineFunction::CallSiteInfo CSInfo;
2227 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
2228 bool isThisReturn = false;
2229 bool isCmseNSCall = false;
2230 bool PreferIndirect = false;
2231
2232 // Determine whether this is a non-secure function call.
2233 if (CLI.CB && CLI.CB->getAttributes().hasFnAttribute("cmse_nonsecure_call"))
2
Assuming field 'CB' is null
3
Taking false branch
2234 isCmseNSCall = true;
2235
2236 // Disable tail calls if they're not supported.
2237 if (!Subtarget->supportsTailCall())
4
Assuming the condition is false
5
Taking false branch
2238 isTailCall = false;
2239
2240 // For both the non-secure calls and the returns from a CMSE entry function,
2241 // the function needs to do some extra work afte r the call, or before the
2242 // return, respectively, thus it cannot end with atail call
2243 if (isCmseNSCall
5.1
'isCmseNSCall' is false
|| AFI->isCmseNSEntryFunction())
6
Assuming the condition is false
7
Taking false branch
2244 isTailCall = false;
2245
2246 if (isa<GlobalAddressSDNode>(Callee)) {
8
Assuming 'Callee' is not a 'GlobalAddressSDNode'
9
Taking false branch
2247 // If we're optimizing for minimum size and the function is called three or
2248 // more times in this block, we can improve codesize by calling indirectly
2249 // as BLXr has a 16-bit encoding.
2250 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2251 if (CLI.CB) {
2252 auto *BB = CLI.CB->getParent();
2253 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2254 count_if(GV->users(), [&BB](const User *U) {
2255 return isa<Instruction>(U) &&
2256 cast<Instruction>(U)->getParent() == BB;
2257 }) > 2;
2258 }
2259 }
2260 if (isTailCall) {
10
Assuming 'isTailCall' is false
11
Taking false branch
2261 // Check if it's really possible to do a tail call.
2262 isTailCall = IsEligibleForTailCallOptimization(
2263 Callee, CallConv, isVarArg, isStructRet,
2264 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2265 PreferIndirect);
2266 if (!isTailCall && CLI.CB && CLI.CB->isMustTailCall())
2267 report_fatal_error("failed to perform tail call elimination on a call "
2268 "site marked musttail");
2269 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2270 // detected sibcalls.
2271 if (isTailCall)
2272 ++NumTailCalls;
2273 }
2274
2275 // Analyze operands of the call, assigning locations to each operand.
2276 SmallVector<CCValAssign, 16> ArgLocs;
2277 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2278 *DAG.getContext());
2279 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2280
2281 // Get a count of how many bytes are to be pushed on the stack.
2282 unsigned NumBytes = CCInfo.getNextStackOffset();
2283
2284 if (isTailCall) {
12
Assuming 'isTailCall' is false
13
Taking false branch
2285 // For tail calls, memory operands are available in our caller's stack.
2286 NumBytes = 0;
2287 } else {
2288 // Adjust the stack pointer for the new arguments...
2289 // These operations are automatically eliminated by the prolog/epilog pass
2290 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
2291 }
2292
2293 SDValue StackPtr =
2294 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2295
2296 RegsToPassVector RegsToPass;
2297 SmallVector<SDValue, 8> MemOpChains;
2298
2299 // Walk the register/memloc assignments, inserting copies/loads. In the case
2300 // of tail call optimization, arguments are handled later.
2301 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
15
Loop condition is false. Execution continues on line 2443
2302 i != e;
14
Assuming 'i' is equal to 'e'
2303 ++i, ++realArgIdx) {
2304 CCValAssign &VA = ArgLocs[i];
2305 SDValue Arg = OutVals[realArgIdx];
2306 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2307 bool isByVal = Flags.isByVal();
2308
2309 // Promote the value if needed.
2310 switch (VA.getLocInfo()) {
2311 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2311)
;
2312 case CCValAssign::Full: break;
2313 case CCValAssign::SExt:
2314 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2315 break;
2316 case CCValAssign::ZExt:
2317 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2318 break;
2319 case CCValAssign::AExt:
2320 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2321 break;
2322 case CCValAssign::BCvt:
2323 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2324 break;
2325 }
2326
2327 // f16 arguments have their size extended to 4 bytes and passed as if they
2328 // had been copied to the LSBs of a 32-bit register.
2329 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
2330 if (VA.needsCustom() &&
2331 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2332 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
2333 } else {
2334 // f16 arguments could have been extended prior to argument lowering.
2335 // Mask them arguments if this is a CMSE nonsecure call.
2336 auto ArgVT = Outs[realArgIdx].ArgVT;
2337 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2338 auto LocBits = VA.getLocVT().getSizeInBits();
2339 auto MaskValue = APInt::getLowBitsSet(LocBits, ArgVT.getSizeInBits());
2340 SDValue Mask =
2341 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
2342 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
2343 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
2344 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2345 }
2346 }
2347
2348 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2349 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
2350 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2351 DAG.getConstant(0, dl, MVT::i32));
2352 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2353 DAG.getConstant(1, dl, MVT::i32));
2354
2355 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
2356 StackPtr, MemOpChains, Flags);
2357
2358 VA = ArgLocs[++i]; // skip ahead to next loc
2359 if (VA.isRegLoc()) {
2360 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, VA, ArgLocs[++i],
2361 StackPtr, MemOpChains, Flags);
2362 } else {
2363 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2363, __PRETTY_FUNCTION__))
;
2364
2365 MemOpChains.push_back(
2366 LowerMemOpCallTo(Chain, StackPtr, Op1, dl, DAG, VA, Flags));
2367 }
2368 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
2369 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2370 StackPtr, MemOpChains, Flags);
2371 } else if (VA.isRegLoc()) {
2372 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2373 Outs[0].VT == MVT::i32) {
2374 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2375, __PRETTY_FUNCTION__))
2375 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2375, __PRETTY_FUNCTION__))
;
2376 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2377, __PRETTY_FUNCTION__))
2377 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2377, __PRETTY_FUNCTION__))
;
2378 isThisReturn = true;
2379 }
2380 const TargetOptions &Options = DAG.getTarget().Options;
2381 if (Options.EmitCallSiteInfo)
2382 CSInfo.emplace_back(VA.getLocReg(), i);
2383 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2384 } else if (isByVal) {
2385 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2385, __PRETTY_FUNCTION__))
;
2386 unsigned offset = 0;
2387
2388 // True if this byval aggregate will be split between registers
2389 // and memory.
2390 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2391 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2392
2393 if (CurByValIdx < ByValArgsCount) {
2394
2395 unsigned RegBegin, RegEnd;
2396 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2397
2398 EVT PtrVT =
2399 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2400 unsigned int i, j;
2401 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2402 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2403 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2404 SDValue Load =
2405 DAG.getLoad(PtrVT, dl, Chain, AddArg, MachinePointerInfo(),
2406 DAG.InferPtrAlign(AddArg));
2407 MemOpChains.push_back(Load.getValue(1));
2408 RegsToPass.push_back(std::make_pair(j, Load));
2409 }
2410
2411 // If parameter size outsides register area, "offset" value
2412 // helps us to calculate stack slot for remained part properly.
2413 offset = RegEnd - RegBegin;
2414
2415 CCInfo.nextInRegsParam();
2416 }
2417
2418 if (Flags.getByValSize() > 4*offset) {
2419 auto PtrVT = getPointerTy(DAG.getDataLayout());
2420 unsigned LocMemOffset = VA.getLocMemOffset();
2421 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2422 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2423 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2424 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2425 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2426 MVT::i32);
2427 SDValue AlignNode =
2428 DAG.getConstant(Flags.getNonZeroByValAlign().value(), dl, MVT::i32);
2429
2430 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2431 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2432 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2433 Ops));
2434 }
2435 } else if (!isTailCall) {
2436 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2436, __PRETTY_FUNCTION__))
;
2437
2438 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2439 dl, DAG, VA, Flags));
2440 }
2441 }
2442
2443 if (!MemOpChains.empty())
16
Taking true branch
2444 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2445
2446 // Build a sequence of copy-to-reg nodes chained together with token chain
2447 // and flag operands which copy the outgoing args into the appropriate regs.
2448 SDValue InFlag;
2449 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
17
Assuming 'i' is equal to 'e'
18
Loop condition is false. Execution continues on line 2458
2450 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2451 RegsToPass[i].second, InFlag);
2452 InFlag = Chain.getValue(1);
2453 }
2454
2455 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2456 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2457 // node so that legalize doesn't hack it.
2458 bool isDirect = false;
2459
2460 const TargetMachine &TM = getTargetMachine();
2461 const Module *Mod = MF.getFunction().getParent();
2462 const GlobalValue *GV = nullptr;
19
'GV' initialized to a null pointer value
2463 if (GlobalAddressSDNode *G
19.1
'G' is null
= dyn_cast<GlobalAddressSDNode>(Callee))
20
Taking false branch
2464 GV = G->getGlobal();
2465 bool isStub =
2466 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
21
Assuming the condition is false
2467
2468 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
22
Assuming the condition is true
2469 bool isLocalARMFunc = false;
2470 auto PtrVt = getPointerTy(DAG.getDataLayout());
2471
2472 if (Subtarget->genLongCalls()) {
23
Assuming the condition is false
24
Taking false branch
2473 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2474, __PRETTY_FUNCTION__))
2474 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2474, __PRETTY_FUNCTION__))
;
2475 // Handle a global address or an external symbol. If it's not one of
2476 // those, the target's already in a register, so we don't need to do
2477 // anything extra.
2478 if (isa<GlobalAddressSDNode>(Callee)) {
2479 // Create a constant pool entry for the callee address
2480 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2481 ARMConstantPoolValue *CPV =
2482 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2483
2484 // Get the address of the callee into a register
2485 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2486 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2487 Callee = DAG.getLoad(
2488 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2489 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2490 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2491 const char *Sym = S->getSymbol();
2492
2493 // Create a constant pool entry for the callee address
2494 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2495 ARMConstantPoolValue *CPV =
2496 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2497 ARMPCLabelIndex, 0);
2498 // Get the address of the callee into a register
2499 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2500 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2501 Callee = DAG.getLoad(
2502 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2503 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2504 }
2505 } else if (isa<GlobalAddressSDNode>(Callee)) {
25
Assuming 'Callee' is a 'GlobalAddressSDNode'
26
Taking true branch
2506 if (!PreferIndirect
26.1
'PreferIndirect' is false
) {
27
Taking true branch
2507 isDirect = true;
2508 bool isDef = GV->isStrongDefinitionForLinker();
28
Called C++ object pointer is null
2509
2510 // ARM call to a local ARM function is predicable.
2511 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2512 // tBX takes a register source operand.
2513 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2514 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2514, __PRETTY_FUNCTION__))
;
2515 Callee = DAG.getNode(
2516 ARMISD::WrapperPIC, dl, PtrVt,
2517 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2518 Callee = DAG.getLoad(
2519 PtrVt, dl, DAG.getEntryNode(), Callee,
2520 MachinePointerInfo::getGOT(DAG.getMachineFunction()), MaybeAlign(),
2521 MachineMemOperand::MODereferenceable |
2522 MachineMemOperand::MOInvariant);
2523 } else if (Subtarget->isTargetCOFF()) {
2524 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2525, __PRETTY_FUNCTION__))
2525 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2525, __PRETTY_FUNCTION__))
;
2526 unsigned TargetFlags = ARMII::MO_NO_FLAG;
2527 if (GV->hasDLLImportStorageClass())
2528 TargetFlags = ARMII::MO_DLLIMPORT;
2529 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
2530 TargetFlags = ARMII::MO_COFFSTUB;
2531 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2532 TargetFlags);
2533 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
2534 Callee =
2535 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2536 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2537 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2538 } else {
2539 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2540 }
2541 }
2542 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2543 isDirect = true;
2544 // tBX takes a register source operand.
2545 const char *Sym = S->getSymbol();
2546 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2547 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2548 ARMConstantPoolValue *CPV =
2549 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2550 ARMPCLabelIndex, 4);
2551 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, Align(4));
2552 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2553 Callee = DAG.getLoad(
2554 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2555 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2556 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2557 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2558 } else {
2559 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2560 }
2561 }
2562
2563 if (isCmseNSCall) {
2564 assert(!isARMFunc && !isDirect &&((!isARMFunc && !isDirect && "Cannot handle call to ARM function or direct call"
) ? static_cast<void> (0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2565, __PRETTY_FUNCTION__))
2565 "Cannot handle call to ARM function or direct call")((!isARMFunc && !isDirect && "Cannot handle call to ARM function or direct call"
) ? static_cast<void> (0) : __assert_fail ("!isARMFunc && !isDirect && \"Cannot handle call to ARM function or direct call\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2565, __PRETTY_FUNCTION__))
;
2566 if (NumBytes > 0) {
2567 DiagnosticInfoUnsupported Diag(DAG.getMachineFunction().getFunction(),
2568 "call to non-secure function would "
2569 "require passing arguments on stack",
2570 dl.getDebugLoc());
2571 DAG.getContext()->diagnose(Diag);
2572 }
2573 if (isStructRet) {
2574 DiagnosticInfoUnsupported Diag(
2575 DAG.getMachineFunction().getFunction(),
2576 "call to non-secure function would return value through pointer",
2577 dl.getDebugLoc());
2578 DAG.getContext()->diagnose(Diag);
2579 }
2580 }
2581
2582 // FIXME: handle tail calls differently.
2583 unsigned CallOpc;
2584 if (Subtarget->isThumb()) {
2585 if (isCmseNSCall)
2586 CallOpc = ARMISD::tSECALL;
2587 else if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2588 CallOpc = ARMISD::CALL_NOLINK;
2589 else
2590 CallOpc = ARMISD::CALL;
2591 } else {
2592 if (!isDirect && !Subtarget->hasV5TOps())
2593 CallOpc = ARMISD::CALL_NOLINK;
2594 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2595 // Emit regular call when code size is the priority
2596 !Subtarget->hasMinSize())
2597 // "mov lr, pc; b _foo" to avoid confusing the RSP
2598 CallOpc = ARMISD::CALL_NOLINK;
2599 else
2600 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2601 }
2602
2603 std::vector<SDValue> Ops;
2604 Ops.push_back(Chain);
2605 Ops.push_back(Callee);
2606
2607 // Add argument registers to the end of the list so that they are known live
2608 // into the call.
2609 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2610 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2611 RegsToPass[i].second.getValueType()));
2612
2613 // Add a register mask operand representing the call-preserved registers.
2614 if (!isTailCall) {
2615 const uint32_t *Mask;
2616 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2617 if (isThisReturn) {
2618 // For 'this' returns, use the R0-preserving mask if applicable
2619 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2620 if (!Mask) {
2621 // Set isThisReturn to false if the calling convention is not one that
2622 // allows 'returned' to be modeled in this way, so LowerCallResult does
2623 // not try to pass 'this' straight through
2624 isThisReturn = false;
2625 Mask = ARI->getCallPreservedMask(MF, CallConv);
2626 }
2627 } else
2628 Mask = ARI->getCallPreservedMask(MF, CallConv);
2629
2630 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2630, __PRETTY_FUNCTION__))
;
2631 Ops.push_back(DAG.getRegisterMask(Mask));
2632 }
2633
2634 if (InFlag.getNode())
2635 Ops.push_back(InFlag);
2636
2637 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2638 if (isTailCall) {
2639 MF.getFrameInfo().setHasTailCall();
2640 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2641 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2642 return Ret;
2643 }
2644
2645 // Returns a chain and a flag for retval copy to use.
2646 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2647 DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
2648 InFlag = Chain.getValue(1);
2649 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2650
2651 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2652 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2653 if (!Ins.empty())
2654 InFlag = Chain.getValue(1);
2655
2656 // Handle result values, copying them out of physregs into vregs that we
2657 // return.
2658 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2659 InVals, isThisReturn,
2660 isThisReturn ? OutVals[0] : SDValue());
2661}
2662
2663/// HandleByVal - Every parameter *after* a byval parameter is passed
2664/// on the stack. Remember the next parameter register to allocate,
2665/// and then confiscate the rest of the parameter registers to insure
2666/// this.
2667void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2668 Align Alignment) const {
2669 // Byval (as with any stack) slots are always at least 4 byte aligned.
2670 Alignment = std::max(Alignment, Align(4));
2671
2672 unsigned Reg = State->AllocateReg(GPRArgRegs);
2673 if (!Reg)
2674 return;
2675
2676 unsigned AlignInRegs = Alignment.value() / 4;
2677 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2678 for (unsigned i = 0; i < Waste; ++i)
2679 Reg = State->AllocateReg(GPRArgRegs);
2680
2681 if (!Reg)
2682 return;
2683
2684 unsigned Excess = 4 * (ARM::R4 - Reg);
2685
2686 // Special case when NSAA != SP and parameter size greater than size of
2687 // all remained GPR regs. In that case we can't split parameter, we must
2688 // send it to stack. We also must set NCRN to R4, so waste all
2689 // remained registers.
2690 const unsigned NSAAOffset = State->getNextStackOffset();
2691 if (NSAAOffset != 0 && Size > Excess) {
2692 while (State->AllocateReg(GPRArgRegs))
2693 ;
2694 return;
2695 }
2696
2697 // First register for byval parameter is the first register that wasn't
2698 // allocated before this method call, so it would be "reg".
2699 // If parameter is small enough to be saved in range [reg, r4), then
2700 // the end (first after last) register would be reg + param-size-in-regs,
2701 // else parameter would be splitted between registers and stack,
2702 // end register would be r4 in this case.
2703 unsigned ByValRegBegin = Reg;
2704 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2705 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2706 // Note, first register is allocated in the beginning of function already,
2707 // allocate remained amount of registers we need.
2708 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2709 State->AllocateReg(GPRArgRegs);
2710 // A byval parameter that is split between registers and memory needs its
2711 // size truncated here.
2712 // In the case where the entire structure fits in registers, we set the
2713 // size in memory to zero.
2714 Size = std::max<int>(Size - Excess, 0);
2715}
2716
2717/// MatchingStackOffset - Return true if the given stack call argument is
2718/// already available in the same position (relatively) of the caller's
2719/// incoming argument stack.
2720static
2721bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2722 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2723 const TargetInstrInfo *TII) {
2724 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2725 int FI = std::numeric_limits<int>::max();
2726 if (Arg.getOpcode() == ISD::CopyFromReg) {
2727 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2728 if (!Register::isVirtualRegister(VR))
2729 return false;
2730 MachineInstr *Def = MRI->getVRegDef(VR);
2731 if (!Def)
2732 return false;
2733 if (!Flags.isByVal()) {
2734 if (!TII->isLoadFromStackSlot(*Def, FI))
2735 return false;
2736 } else {
2737 return false;
2738 }
2739 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2740 if (Flags.isByVal())
2741 // ByVal argument is passed in as a pointer but it's now being
2742 // dereferenced. e.g.
2743 // define @foo(%struct.X* %A) {
2744 // tail call @bar(%struct.X* byval %A)
2745 // }
2746 return false;
2747 SDValue Ptr = Ld->getBasePtr();
2748 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2749 if (!FINode)
2750 return false;
2751 FI = FINode->getIndex();
2752 } else
2753 return false;
2754
2755 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2755, __PRETTY_FUNCTION__))
;
2756 if (!MFI.isFixedObjectIndex(FI))
2757 return false;
2758 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2759}
2760
2761/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2762/// for tail call optimization. Targets which want to do tail call
2763/// optimization should implement this function.
2764bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2765 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2766 bool isCalleeStructRet, bool isCallerStructRet,
2767 const SmallVectorImpl<ISD::OutputArg> &Outs,
2768 const SmallVectorImpl<SDValue> &OutVals,
2769 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2770 const bool isIndirect) const {
2771 MachineFunction &MF = DAG.getMachineFunction();
2772 const Function &CallerF = MF.getFunction();
2773 CallingConv::ID CallerCC = CallerF.getCallingConv();
2774
2775 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2775, __PRETTY_FUNCTION__))
;
2776
2777 // Indirect tail calls cannot be optimized for Thumb1 if the args
2778 // to the call take up r0-r3. The reason is that there are no legal registers
2779 // left to hold the pointer to the function to be called.
2780 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2781 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2782 return false;
2783
2784 // Look for obvious safe cases to perform tail call optimization that do not
2785 // require ABI changes. This is what gcc calls sibcall.
2786
2787 // Exception-handling functions need a special set of instructions to indicate
2788 // a return to the hardware. Tail-calling another function would probably
2789 // break this.
2790 if (CallerF.hasFnAttribute("interrupt"))
2791 return false;
2792
2793 // Also avoid sibcall optimization if either caller or callee uses struct
2794 // return semantics.
2795 if (isCalleeStructRet || isCallerStructRet)
2796 return false;
2797
2798 // Externally-defined functions with weak linkage should not be
2799 // tail-called on ARM when the OS does not support dynamic
2800 // pre-emption of symbols, as the AAELF spec requires normal calls
2801 // to undefined weak functions to be replaced with a NOP or jump to the
2802 // next instruction. The behaviour of branch instructions in this
2803 // situation (as used for tail calls) is implementation-defined, so we
2804 // cannot rely on the linker replacing the tail call with a return.
2805 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2806 const GlobalValue *GV = G->getGlobal();
2807 const Triple &TT = getTargetMachine().getTargetTriple();
2808 if (GV->hasExternalWeakLinkage() &&
2809 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2810 return false;
2811 }
2812
2813 // Check that the call results are passed in the same way.
2814 LLVMContext &C = *DAG.getContext();
2815 if (!CCState::resultsCompatible(
2816 getEffectiveCallingConv(CalleeCC, isVarArg),
2817 getEffectiveCallingConv(CallerCC, CallerF.isVarArg()), MF, C, Ins,
2818 CCAssignFnForReturn(CalleeCC, isVarArg),
2819 CCAssignFnForReturn(CallerCC, CallerF.isVarArg())))
2820 return false;
2821 // The callee has to preserve all registers the caller needs to preserve.
2822 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2823 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2824 if (CalleeCC != CallerCC) {
2825 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2826 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2827 return false;
2828 }
2829
2830 // If Caller's vararg or byval argument has been split between registers and
2831 // stack, do not perform tail call, since part of the argument is in caller's
2832 // local frame.
2833 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2834 if (AFI_Caller->getArgRegsSaveSize())
2835 return false;
2836
2837 // If the callee takes no arguments then go on to check the results of the
2838 // call.
2839 if (!Outs.empty()) {
2840 // Check if stack adjustment is needed. For now, do not do this if any
2841 // argument is passed on the stack.
2842 SmallVector<CCValAssign, 16> ArgLocs;
2843 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2844 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2845 if (CCInfo.getNextStackOffset()) {
2846 // Check if the arguments are already laid out in the right way as
2847 // the caller's fixed stack objects.
2848 MachineFrameInfo &MFI = MF.getFrameInfo();
2849 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2850 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2851 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2852 i != e;
2853 ++i, ++realArgIdx) {
2854 CCValAssign &VA = ArgLocs[i];
2855 EVT RegVT = VA.getLocVT();
2856 SDValue Arg = OutVals[realArgIdx];
2857 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2858 if (VA.getLocInfo() == CCValAssign::Indirect)
2859 return false;
2860 if (VA.needsCustom() && (RegVT == MVT::f64 || RegVT == MVT::v2f64)) {
2861 // f64 and vector types are split into multiple registers or
2862 // register/stack-slot combinations. The types will not match
2863 // the registers; give up on memory f64 refs until we figure
2864 // out what to do about this.
2865 if (!VA.isRegLoc())
2866 return false;
2867 if (!ArgLocs[++i].isRegLoc())
2868 return false;
2869 if (RegVT == MVT::v2f64) {
2870 if (!ArgLocs[++i].isRegLoc())
2871 return false;
2872 if (!ArgLocs[++i].isRegLoc())
2873 return false;
2874 }
2875 } else if (!VA.isRegLoc()) {
2876 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2877 MFI, MRI, TII))
2878 return false;
2879 }
2880 }
2881 }
2882
2883 const MachineRegisterInfo &MRI = MF.getRegInfo();
2884 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2885 return false;
2886 }
2887
2888 return true;
2889}
2890
2891bool
2892ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2893 MachineFunction &MF, bool isVarArg,
2894 const SmallVectorImpl<ISD::OutputArg> &Outs,
2895 LLVMContext &Context) const {
2896 SmallVector<CCValAssign, 16> RVLocs;
2897 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2898 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2899}
2900
2901static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2902 const SDLoc &DL, SelectionDAG &DAG) {
2903 const MachineFunction &MF = DAG.getMachineFunction();
2904 const Function &F = MF.getFunction();
2905
2906 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2907
2908 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2909 // version of the "preferred return address". These offsets affect the return
2910 // instruction if this is a return from PL1 without hypervisor extensions.
2911 // IRQ/FIQ: +4 "subs pc, lr, #4"
2912 // SWI: 0 "subs pc, lr, #0"
2913 // ABORT: +4 "subs pc, lr, #4"
2914 // UNDEF: +4/+2 "subs pc, lr, #0"
2915 // UNDEF varies depending on where the exception came from ARM or Thumb
2916 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2917
2918 int64_t LROffset;
2919 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2920 IntKind == "ABORT")
2921 LROffset = 4;
2922 else if (IntKind == "SWI" || IntKind == "UNDEF")
2923 LROffset = 0;
2924 else
2925 report_fatal_error("Unsupported interrupt attribute. If present, value "
2926 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2927
2928 RetOps.insert(RetOps.begin() + 1,
2929 DAG.getConstant(LROffset, DL, MVT::i32, false));
2930
2931 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2932}
2933
2934SDValue
2935ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2936 bool isVarArg,
2937 const SmallVectorImpl<ISD::OutputArg> &Outs,
2938 const SmallVectorImpl<SDValue> &OutVals,
2939 const SDLoc &dl, SelectionDAG &DAG) const {
2940 // CCValAssign - represent the assignment of the return value to a location.
2941 SmallVector<CCValAssign, 16> RVLocs;
2942
2943 // CCState - Info about the registers and stack slots.
2944 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2945 *DAG.getContext());
2946
2947 // Analyze outgoing return values.
2948 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2949
2950 SDValue Flag;
2951 SmallVector<SDValue, 4> RetOps;
2952 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2953 bool isLittleEndian = Subtarget->isLittle();
2954
2955 MachineFunction &MF = DAG.getMachineFunction();
2956 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2957 AFI->setReturnRegsCount(RVLocs.size());
2958
2959 // Report error if cmse entry function returns structure through first ptr arg.
2960 if (AFI->isCmseNSEntryFunction() && MF.getFunction().hasStructRetAttr()) {
2961 // Note: using an empty SDLoc(), as the first line of the function is a
2962 // better place to report than the last line.
2963 DiagnosticInfoUnsupported Diag(
2964 DAG.getMachineFunction().getFunction(),
2965 "secure entry function would return value through pointer",
2966 SDLoc().getDebugLoc());
2967 DAG.getContext()->diagnose(Diag);
2968 }
2969
2970 // Copy the result values into the output registers.
2971 for (unsigned i = 0, realRVLocIdx = 0;
2972 i != RVLocs.size();
2973 ++i, ++realRVLocIdx) {
2974 CCValAssign &VA = RVLocs[i];
2975 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2975, __PRETTY_FUNCTION__))
;
2976
2977 SDValue Arg = OutVals[realRVLocIdx];
2978 bool ReturnF16 = false;
2979
2980 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2981 // Half-precision return values can be returned like this:
2982 //
2983 // t11 f16 = fadd ...
2984 // t12: i16 = bitcast t11
2985 // t13: i32 = zero_extend t12
2986 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2987 //
2988 // to avoid code generation for bitcasts, we simply set Arg to the node
2989 // that produces the f16 value, t11 in this case.
2990 //
2991 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2992 SDValue ZE = Arg.getOperand(0);
2993 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2994 SDValue BC = ZE.getOperand(0);
2995 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2996 Arg = BC.getOperand(0);
2997 ReturnF16 = true;
2998 }
2999 }
3000 }
3001 }
3002
3003 switch (VA.getLocInfo()) {
3004 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3004)
;
3005 case CCValAssign::Full: break;
3006 case CCValAssign::BCvt:
3007 if (!ReturnF16)
3008 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3009 break;
3010 }
3011
3012 // Mask f16 arguments if this is a CMSE nonsecure entry.
3013 auto RetVT = Outs[realRVLocIdx].ArgVT;
3014 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3015 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
3016 Arg = MoveFromHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), Arg);
3017 } else {
3018 auto LocBits = VA.getLocVT().getSizeInBits();
3019 auto MaskValue = APInt::getLowBitsSet(LocBits, RetVT.getSizeInBits());
3020 SDValue Mask =
3021 DAG.getConstant(MaskValue, dl, MVT::getIntegerVT(LocBits));
3022 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::getIntegerVT(LocBits), Arg);
3023 Arg = DAG.getNode(ISD::AND, dl, MVT::getIntegerVT(LocBits), Arg, Mask);
3024 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
3025 }
3026 }
3027
3028 if (VA.needsCustom() &&
3029 (VA.getLocVT() == MVT::v2f64 || VA.getLocVT() == MVT::f64)) {
3030 if (VA.getLocVT() == MVT::v2f64) {
3031 // Extract the first half and return it in two registers.
3032 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3033 DAG.getConstant(0, dl, MVT::i32));
3034 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
3035 DAG.getVTList(MVT::i32, MVT::i32), Half);
3036
3037 Chain =
3038 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3039 HalfGPRs.getValue(isLittleEndian ? 0 : 1), Flag);
3040 Flag = Chain.getValue(1);
3041 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3042 VA = RVLocs[++i]; // skip ahead to next loc
3043 Chain =
3044 DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3045 HalfGPRs.getValue(isLittleEndian ? 1 : 0), Flag);
3046 Flag = Chain.getValue(1);
3047 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3048 VA = RVLocs[++i]; // skip ahead to next loc
3049
3050 // Extract the 2nd half and fall through to handle it as an f64 value.
3051 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
3052 DAG.getConstant(1, dl, MVT::i32));
3053 }
3054 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
3055 // available.
3056 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
3057 DAG.getVTList(MVT::i32, MVT::i32), Arg);
3058 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3059 fmrrd.getValue(isLittleEndian ? 0 : 1), Flag);
3060 Flag = Chain.getValue(1);
3061 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3062 VA = RVLocs[++i]; // skip ahead to next loc
3063 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3064 fmrrd.getValue(isLittleEndian ? 1 : 0), Flag);
3065 } else
3066 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
3067
3068 // Guarantee that all emitted copies are
3069 // stuck together, avoiding something bad.
3070 Flag = Chain.getValue(1);
3071 RetOps.push_back(DAG.getRegister(
3072 VA.getLocReg(), ReturnF16 ? Arg.getValueType() : VA.getLocVT()));
3073 }
3074 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
3075 const MCPhysReg *I =
3076 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
3077 if (I) {
3078 for (; *I; ++I) {
3079 if (ARM::GPRRegClass.contains(*I))
3080 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
3081 else if (ARM::DPRRegClass.contains(*I))
3082 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
3083 else
3084 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3084)
;
3085 }
3086 }
3087
3088 // Update chain and glue.
3089 RetOps[0] = Chain;
3090 if (Flag.getNode())
3091 RetOps.push_back(Flag);
3092
3093 // CPUs which aren't M-class use a special sequence to return from
3094 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
3095 // though we use "subs pc, lr, #N").
3096 //
3097 // M-class CPUs actually use a normal return sequence with a special
3098 // (hardware-provided) value in LR, so the normal code path works.
3099 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
3100 !Subtarget->isMClass()) {
3101 if (Subtarget->isThumb1Only())
3102 report_fatal_error("interrupt attribute is not supported in Thumb1");
3103 return LowerInterruptReturn(RetOps, dl, DAG);
3104 }
3105
3106 ARMISD::NodeType RetNode = AFI->isCmseNSEntryFunction() ? ARMISD::SERET_FLAG :
3107 ARMISD::RET_FLAG;
3108 return DAG.getNode(RetNode, dl, MVT::Other, RetOps);
3109}
3110
3111bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
3112 if (N->getNumValues() != 1)
3113 return false;
3114 if (!N->hasNUsesOfValue(1, 0))
3115 return false;
3116
3117 SDValue TCChain = Chain;
3118 SDNode *Copy = *N->use_begin();
3119 if (Copy->getOpcode() == ISD::CopyToReg) {
3120 // If the copy has a glue operand, we conservatively assume it isn't safe to
3121 // perform a tail call.
3122 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3123 return false;
3124 TCChain = Copy->getOperand(0);
3125 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
3126 SDNode *VMov = Copy;
3127 // f64 returned in a pair of GPRs.
3128 SmallPtrSet<SDNode*, 2> Copies;
3129 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3130 UI != UE; ++UI) {
3131 if (UI->getOpcode() != ISD::CopyToReg)
3132 return false;
3133 Copies.insert(*UI);
3134 }
3135 if (Copies.size() > 2)
3136 return false;
3137
3138 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
3139 UI != UE; ++UI) {
3140 SDValue UseChain = UI->getOperand(0);
3141 if (Copies.count(UseChain.getNode()))
3142 // Second CopyToReg
3143 Copy = *UI;
3144 else {
3145 // We are at the top of this chain.
3146 // If the copy has a glue operand, we conservatively assume it
3147 // isn't safe to perform a tail call.
3148 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
3149 return false;
3150 // First CopyToReg
3151 TCChain = UseChain;
3152 }
3153 }
3154 } else if (Copy->getOpcode() == ISD::BITCAST) {
3155 // f32 returned in a single GPR.
3156 if (!Copy->hasOneUse())
3157 return false;
3158 Copy = *Copy->use_begin();
3159 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
3160 return false;
3161 // If the copy has a glue operand, we conservatively assume it isn't safe to
3162 // perform a tail call.
3163 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
3164 return false;
3165 TCChain = Copy->getOperand(0);
3166 } else {
3167 return false;
3168 }
3169
3170 bool HasRet = false;
3171 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
3172 UI != UE; ++UI) {
3173 if (UI->getOpcode() != ARMISD::RET_FLAG &&
3174 UI->getOpcode() != ARMISD::INTRET_FLAG)
3175 return false;
3176 HasRet = true;
3177 }
3178
3179 if (!HasRet)
3180 return false;
3181
3182 Chain = TCChain;
3183 return true;
3184}
3185
3186bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
3187 if (!Subtarget->supportsTailCall())
3188 return false;
3189
3190 if (!CI->isTailCall())
3191 return false;
3192
3193 return true;
3194}
3195
3196// Trying to write a 64 bit value so need to split into two 32 bit values first,
3197// and pass the lower and high parts through.
3198static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
3199 SDLoc DL(Op);
3200 SDValue WriteValue = Op->getOperand(2);
3201
3202 // This function is only supposed to be called for i64 type argument.
3203 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3204, __PRETTY_FUNCTION__))
3204 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3204, __PRETTY_FUNCTION__))
;
3205
3206 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3207 DAG.getConstant(0, DL, MVT::i32));
3208 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
3209 DAG.getConstant(1, DL, MVT::i32));
3210 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
3211 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
3212}
3213
3214// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3215// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
3216// one of the above mentioned nodes. It has to be wrapped because otherwise
3217// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3218// be used to form addressing mode. These wrapped nodes will be selected
3219// into MOVi.
3220SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
3221 SelectionDAG &DAG) const {
3222 EVT PtrVT = Op.getValueType();
3223 // FIXME there is no actual debug info here
3224 SDLoc dl(Op);
3225 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3226 SDValue Res;
3227
3228 // When generating execute-only code Constant Pools must be promoted to the
3229 // global data section. It's a bit ugly that we can't share them across basic
3230 // blocks, but this way we guarantee that execute-only behaves correct with
3231 // position-independent addressing modes.
3232 if (Subtarget->genExecuteOnly()) {
3233 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3234 auto T = const_cast<Type*>(CP->getType());
3235 auto C = const_cast<Constant*>(CP->getConstVal());
3236 auto M = const_cast<Module*>(DAG.getMachineFunction().
3237 getFunction().getParent());
3238 auto GV = new GlobalVariable(
3239 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3240 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3241 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3242 Twine(AFI->createPICLabelUId())
3243 );
3244 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3245 dl, PtrVT);
3246 return LowerGlobalAddress(GA, DAG);
3247 }
3248
3249 if (CP->isMachineConstantPoolEntry())
3250 Res =
3251 DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, CP->getAlign());
3252 else
3253 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign());
3254 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3255}
3256
3257unsigned ARMTargetLowering::getJumpTableEncoding() const {
3258 return MachineJumpTableInfo::EK_Inline;
3259}
3260
3261SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3262 SelectionDAG &DAG) const {
3263 MachineFunction &MF = DAG.getMachineFunction();
3264 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3265 unsigned ARMPCLabelIndex = 0;
3266 SDLoc DL(Op);
3267 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3268 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3269 SDValue CPAddr;
3270 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3271 if (!IsPositionIndependent) {
3272 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, Align(4));
3273 } else {
3274 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3275 ARMPCLabelIndex = AFI->createPICLabelUId();
3276 ARMConstantPoolValue *CPV =
3277 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3278 ARMCP::CPBlockAddress, PCAdj);
3279 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3280 }
3281 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3282 SDValue Result = DAG.getLoad(
3283 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3284 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3285 if (!IsPositionIndependent)
3286 return Result;
3287 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3288 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3289}
3290
3291/// Convert a TLS address reference into the correct sequence of loads
3292/// and calls to compute the variable's address for Darwin, and return an
3293/// SDValue containing the final node.
3294
3295/// Darwin only has one TLS scheme which must be capable of dealing with the
3296/// fully general situation, in the worst case. This means:
3297/// + "extern __thread" declaration.
3298/// + Defined in a possibly unknown dynamic library.
3299///
3300/// The general system is that each __thread variable has a [3 x i32] descriptor
3301/// which contains information used by the runtime to calculate the address. The
3302/// only part of this the compiler needs to know about is the first word, which
3303/// contains a function pointer that must be called with the address of the
3304/// entire descriptor in "r0".
3305///
3306/// Since this descriptor may be in a different unit, in general access must
3307/// proceed along the usual ARM rules. A common sequence to produce is:
3308///
3309/// movw rT1, :lower16:_var$non_lazy_ptr
3310/// movt rT1, :upper16:_var$non_lazy_ptr
3311/// ldr r0, [rT1]
3312/// ldr rT2, [r0]
3313/// blx rT2
3314/// [...address now in r0...]
3315SDValue
3316ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3317 SelectionDAG &DAG) const {
3318 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3319, __PRETTY_FUNCTION__))
3319 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3319, __PRETTY_FUNCTION__))
;
3320 SDLoc DL(Op);
3321
3322 // First step is to get the address of the actua global symbol. This is where
3323 // the TLS descriptor lives.
3324 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3325
3326 // The first entry in the descriptor is a function pointer that we must call
3327 // to obtain the address of the variable.
3328 SDValue Chain = DAG.getEntryNode();
3329 SDValue FuncTLVGet = DAG.getLoad(
3330 MVT::i32, DL, Chain, DescAddr,
3331 MachinePointerInfo::getGOT(DAG.getMachineFunction()), Align(4),
3332 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3333 MachineMemOperand::MOInvariant);
3334 Chain = FuncTLVGet.getValue(1);
3335
3336 MachineFunction &F = DAG.getMachineFunction();
3337 MachineFrameInfo &MFI = F.getFrameInfo();
3338 MFI.setAdjustsStack(true);
3339
3340 // TLS calls preserve all registers except those that absolutely must be
3341 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3342 // silly).
3343 auto TRI =
3344 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3345 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3346 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3347
3348 // Finally, we can make the call. This is just a degenerate version of a
3349 // normal AArch64 call node: r0 takes the address of the descriptor, and
3350 // returns the address of the variable in this thread.
3351 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3352 Chain =
3353 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3354 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3355 DAG.getRegisterMask(Mask), Chain.getValue(1));
3356 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3357}
3358
3359SDValue
3360ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3361 SelectionDAG &DAG) const {
3362 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3362, __PRETTY_FUNCTION__))
;
3363
3364 SDValue Chain = DAG.getEntryNode();
3365 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3366 SDLoc DL(Op);
3367
3368 // Load the current TEB (thread environment block)
3369 SDValue Ops[] = {Chain,
3370 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3371 DAG.getTargetConstant(15, DL, MVT::i32),
3372 DAG.getTargetConstant(0, DL, MVT::i32),
3373 DAG.getTargetConstant(13, DL, MVT::i32),
3374 DAG.getTargetConstant(0, DL, MVT::i32),
3375 DAG.getTargetConstant(2, DL, MVT::i32)};
3376 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3377 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3378
3379 SDValue TEB = CurrentTEB.getValue(0);
3380 Chain = CurrentTEB.getValue(1);
3381
3382 // Load the ThreadLocalStoragePointer from the TEB
3383 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3384 SDValue TLSArray =
3385 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3386 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3387
3388 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3389 // offset into the TLSArray.
3390
3391 // Load the TLS index from the C runtime
3392 SDValue TLSIndex =
3393 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3394 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3395 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3396
3397 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3398 DAG.getConstant(2, DL, MVT::i32));
3399 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3400 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3401 MachinePointerInfo());
3402
3403 // Get the offset of the start of the .tls section (section base)
3404 const auto *GA = cast<GlobalAddressSDNode>(Op);
3405 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3406 SDValue Offset = DAG.getLoad(
3407 PtrVT, DL, Chain,
3408 DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3409 DAG.getTargetConstantPool(CPV, PtrVT, Align(4))),
3410 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3411
3412 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3413}
3414
3415// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3416SDValue
3417ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3418 SelectionDAG &DAG) const {
3419 SDLoc dl(GA);
3420 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3421 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3422 MachineFunction &MF = DAG.getMachineFunction();
3423 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3424 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3425 ARMConstantPoolValue *CPV =
3426 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3427 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3428 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3429 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3430 Argument = DAG.getLoad(
3431 PtrVT, dl, DAG.getEntryNode(), Argument,
3432 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3433 SDValue Chain = Argument.getValue(1);
3434
3435 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3436 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3437
3438 // call __tls_get_addr.
3439 ArgListTy Args;
3440 ArgListEntry Entry;
3441 Entry.Node = Argument;
3442 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3443 Args.push_back(Entry);
3444
3445 // FIXME: is there useful debug info available here?
3446 TargetLowering::CallLoweringInfo CLI(DAG);
3447 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3448 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3449 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3450
3451 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3452 return CallResult.first;
3453}
3454
3455// Lower ISD::GlobalTLSAddress using the "initial exec" or
3456// "local exec" model.
3457SDValue
3458ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3459 SelectionDAG &DAG,
3460 TLSModel::Model model) const {
3461 const GlobalValue *GV = GA->getGlobal();
3462 SDLoc dl(GA);
3463 SDValue Offset;
3464 SDValue Chain = DAG.getEntryNode();
3465 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3466 // Get the Thread Pointer
3467 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3468
3469 if (model == TLSModel::InitialExec) {
3470 MachineFunction &MF = DAG.getMachineFunction();
3471 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3472 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3473 // Initial exec model.
3474 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3475 ARMConstantPoolValue *CPV =
3476 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3477 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3478 true);
3479 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3480 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3481 Offset = DAG.getLoad(
3482 PtrVT, dl, Chain, Offset,
3483 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3484 Chain = Offset.getValue(1);
3485
3486 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3487 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3488
3489 Offset = DAG.getLoad(
3490 PtrVT, dl, Chain, Offset,
3491 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3492 } else {
3493 // local exec model
3494 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3494, __PRETTY_FUNCTION__))
;
3495 ARMConstantPoolValue *CPV =
3496 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3497 Offset = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3498 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3499 Offset = DAG.getLoad(
3500 PtrVT, dl, Chain, Offset,
3501 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3502 }
3503
3504 // The address of the thread local variable is the add of the thread
3505 // pointer with the offset of the variable.
3506 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3507}
3508
3509SDValue
3510ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3511 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3512 if (DAG.getTarget().useEmulatedTLS())
3513 return LowerToTLSEmulatedModel(GA, DAG);
3514
3515 if (Subtarget->isTargetDarwin())
3516 return LowerGlobalTLSAddressDarwin(Op, DAG);
3517
3518 if (Subtarget->isTargetWindows())
3519 return LowerGlobalTLSAddressWindows(Op, DAG);
3520
3521 // TODO: implement the "local dynamic" model
3522 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3522, __PRETTY_FUNCTION__))
;
3523 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3524
3525 switch (model) {
3526 case TLSModel::GeneralDynamic:
3527 case TLSModel::LocalDynamic:
3528 return LowerToTLSGeneralDynamicModel(GA, DAG);
3529 case TLSModel::InitialExec:
3530 case TLSModel::LocalExec:
3531 return LowerToTLSExecModels(GA, DAG, model);
3532 }
3533 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3533)
;
3534}
3535
3536/// Return true if all users of V are within function F, looking through
3537/// ConstantExprs.
3538static bool allUsersAreInFunction(const Value *V, const Function *F) {
3539 SmallVector<const User*,4> Worklist;
3540 for (auto *U : V->users())
3541 Worklist.push_back(U);
3542 while (!Worklist.empty()) {
3543 auto *U = Worklist.pop_back_val();
3544 if (isa<ConstantExpr>(U)) {
3545 for (auto *UU : U->users())
3546 Worklist.push_back(UU);
3547 continue;
3548 }
3549
3550 auto *I = dyn_cast<Instruction>(U);
3551 if (!I || I->getParent()->getParent() != F)
3552 return false;
3553 }
3554 return true;
3555}
3556
3557static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3558 const GlobalValue *GV, SelectionDAG &DAG,
3559 EVT PtrVT, const SDLoc &dl) {
3560 // If we're creating a pool entry for a constant global with unnamed address,
3561 // and the global is small enough, we can emit it inline into the constant pool
3562 // to save ourselves an indirection.
3563 //
3564 // This is a win if the constant is only used in one function (so it doesn't
3565 // need to be duplicated) or duplicating the constant wouldn't increase code
3566 // size (implying the constant is no larger than 4 bytes).
3567 const Function &F = DAG.getMachineFunction().getFunction();
3568
3569 // We rely on this decision to inline being idemopotent and unrelated to the
3570 // use-site. We know that if we inline a variable at one use site, we'll
3571 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3572 // doesn't know about this optimization, so bail out if it's enabled else
3573 // we could decide to inline here (and thus never emit the GV) but require
3574 // the GV from fast-isel generated code.
3575 if (!EnableConstpoolPromotion ||
3576 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3577 return SDValue();
3578
3579 auto *GVar = dyn_cast<GlobalVariable>(GV);
3580 if (!GVar || !GVar->hasInitializer() ||
3581 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3582 !GVar->hasLocalLinkage())
3583 return SDValue();
3584
3585 // If we inline a value that contains relocations, we move the relocations
3586 // from .data to .text. This is not allowed in position-independent code.
3587 auto *Init = GVar->getInitializer();
3588 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3589 Init->needsRelocation())
3590 return SDValue();
3591
3592 // The constant islands pass can only really deal with alignment requests
3593 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3594 // any type wanting greater alignment requirements than 4 bytes. We also
3595 // can only promote constants that are multiples of 4 bytes in size or
3596 // are paddable to a multiple of 4. Currently we only try and pad constants
3597 // that are strings for simplicity.
3598 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3599 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3600 Align PrefAlign = DAG.getDataLayout().getPreferredAlign(GVar);
3601 unsigned RequiredPadding = 4 - (Size % 4);
3602 bool PaddingPossible =
3603 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3604 if (!PaddingPossible || PrefAlign > 4 || Size > ConstpoolPromotionMaxSize ||
3605 Size == 0)
3606 return SDValue();
3607
3608 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3609 MachineFunction &MF = DAG.getMachineFunction();
3610 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3611
3612 // We can't bloat the constant pool too much, else the ConstantIslands pass
3613 // may fail to converge. If we haven't promoted this global yet (it may have
3614 // multiple uses), and promoting it would increase the constant pool size (Sz
3615 // > 4), ensure we have space to do so up to MaxTotal.
3616 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3617 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3618 ConstpoolPromotionMaxTotal)
3619 return SDValue();
3620
3621 // This is only valid if all users are in a single function; we can't clone
3622 // the constant in general. The LLVM IR unnamed_addr allows merging
3623 // constants, but not cloning them.
3624 //
3625 // We could potentially allow cloning if we could prove all uses of the
3626 // constant in the current function don't care about the address, like
3627 // printf format strings. But that isn't implemented for now.
3628 if (!allUsersAreInFunction(GVar, &F))
3629 return SDValue();
3630
3631 // We're going to inline this global. Pad it out if needed.
3632 if (RequiredPadding != 4) {
3633 StringRef S = CDAInit->getAsString();
3634
3635 SmallVector<uint8_t,16> V(S.size());
3636 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3637 while (RequiredPadding--)
3638 V.push_back(0);
3639 Init = ConstantDataArray::get(*DAG.getContext(), V);
3640 }
3641
3642 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3643 SDValue CPAddr = DAG.getTargetConstantPool(CPVal, PtrVT, Align(4));
3644 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3645 AFI->markGlobalAsPromotedToConstantPool(GVar);
3646 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3647 PaddedSize - 4);
3648 }
3649 ++NumConstpoolPromoted;
3650 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3651}
3652
3653bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3654 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3655 if (!(GV = GA->getBaseObject()))
3656 return false;
3657 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3658 return V->isConstant();
3659 return isa<Function>(GV);
3660}
3661
3662SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3663 SelectionDAG &DAG) const {
3664 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3665 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3665)
;
3666 case Triple::COFF:
3667 return LowerGlobalAddressWindows(Op, DAG);
3668 case Triple::ELF:
3669 return LowerGlobalAddressELF(Op, DAG);
3670 case Triple::MachO:
3671 return LowerGlobalAddressDarwin(Op, DAG);
3672 }
3673}
3674
3675SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3676 SelectionDAG &DAG) const {
3677 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3678 SDLoc dl(Op);
3679 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3680 const TargetMachine &TM = getTargetMachine();
3681 bool IsRO = isReadOnly(GV);
3682
3683 // promoteToConstantPool only if not generating XO text section
3684 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3685 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3686 return V;
3687
3688 if (isPositionIndependent()) {
3689 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3690 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3691 UseGOT_PREL ? ARMII::MO_GOT : 0);
3692 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3693 if (UseGOT_PREL)
3694 Result =
3695 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3696 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3697 return Result;
3698 } else if (Subtarget->isROPI() && IsRO) {
3699 // PC-relative.
3700 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3701 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3702 return Result;
3703 } else if (Subtarget->isRWPI() && !IsRO) {
3704 // SB-relative.
3705 SDValue RelAddr;
3706 if (Subtarget->useMovt()) {
3707 ++NumMovwMovt;
3708 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3709 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3710 } else { // use literal pool for address constant
3711 ARMConstantPoolValue *CPV =
3712 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3713 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3714 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3715 RelAddr = DAG.getLoad(
3716 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3717 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3718 }
3719 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3720 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3721 return Result;
3722 }
3723
3724 // If we have T2 ops, we can materialize the address directly via movt/movw
3725 // pair. This is always cheaper.
3726 if (Subtarget->useMovt()) {
3727 ++NumMovwMovt;
3728 // FIXME: Once remat is capable of dealing with instructions with register
3729 // operands, expand this into two nodes.
3730 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3731 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3732 } else {
3733 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, Align(4));
3734 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3735 return DAG.getLoad(
3736 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3737 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3738 }
3739}
3740
3741SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3742 SelectionDAG &DAG) const {
3743 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3744, __PRETTY_FUNCTION__))
3744 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3744, __PRETTY_FUNCTION__))
;
3745 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3746 SDLoc dl(Op);
3747 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3748
3749 if (Subtarget->useMovt())
3750 ++NumMovwMovt;
3751
3752 // FIXME: Once remat is capable of dealing with instructions with register
3753 // operands, expand this into multiple nodes
3754 unsigned Wrapper =
3755 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3756
3757 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3758 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3759
3760 if (Subtarget->isGVIndirectSymbol(GV))
3761 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3762 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3763 return Result;
3764}
3765
3766SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3767 SelectionDAG &DAG) const {
3768 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3768, __PRETTY_FUNCTION__))
;
3769 assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3770, __PRETTY_FUNCTION__))
3770 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3770, __PRETTY_FUNCTION__))
;
3771 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3772, __PRETTY_FUNCTION__))
3772 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3772, __PRETTY_FUNCTION__))
;
3773
3774 const TargetMachine &TM = getTargetMachine();
3775 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3776 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3777 if (GV->hasDLLImportStorageClass())
3778 TargetFlags = ARMII::MO_DLLIMPORT;
3779 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3780 TargetFlags = ARMII::MO_COFFSTUB;
3781 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3782 SDValue Result;
3783 SDLoc DL(Op);
3784
3785 ++NumMovwMovt;
3786
3787 // FIXME: Once remat is capable of dealing with instructions with register
3788 // operands, expand this into two nodes.
3789 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3790 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3791 TargetFlags));
3792 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3793 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3794 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3795 return Result;
3796}
3797
3798SDValue
3799ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3800 SDLoc dl(Op);
3801 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3802 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3803 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3804 Op.getOperand(1), Val);
3805}
3806
3807SDValue
3808ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3809 SDLoc dl(Op);
3810 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3811 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3812}
3813
3814SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3815 SelectionDAG &DAG) const {
3816 SDLoc dl(Op);
3817 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3818 Op.getOperand(0));
3819}
3820
3821SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3822 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3823 unsigned IntNo =
3824 cast<ConstantSDNode>(
3825 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3826 ->getZExtValue();
3827 switch (IntNo) {
3828 default:
3829 return SDValue(); // Don't custom lower most intrinsics.
3830 case Intrinsic::arm_gnu_eabi_mcount: {
3831 MachineFunction &MF = DAG.getMachineFunction();
3832 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3833 SDLoc dl(Op);
3834 SDValue Chain = Op.getOperand(0);
3835 // call "\01__gnu_mcount_nc"
3836 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3837 const uint32_t *Mask =
3838 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3839 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3839, __PRETTY_FUNCTION__))
;
3840 // Mark LR an implicit live-in.
3841 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3842 SDValue ReturnAddress =
3843 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3844 constexpr EVT ResultTys[] = {MVT::Other, MVT::Glue};
3845 SDValue Callee =
3846 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3847 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3848 if (Subtarget->isThumb())
3849 return SDValue(
3850 DAG.getMachineNode(
3851 ARM::tBL_PUSHLR, dl, ResultTys,
3852 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3853 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3854 0);
3855 return SDValue(
3856 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3857 {ReturnAddress, Callee, RegisterMask, Chain}),
3858 0);
3859 }
3860 }
3861}
3862
3863SDValue
3864ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3865 const ARMSubtarget *Subtarget) const {
3866 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3867 SDLoc dl(Op);
3868 switch (IntNo) {
3869 default: return SDValue(); // Don't custom lower most intrinsics.
3870 case Intrinsic::thread_pointer: {
3871 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3872 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3873 }
3874 case Intrinsic::arm_cls: {
3875 const SDValue &Operand = Op.getOperand(1);
3876 const EVT VTy = Op.getValueType();
3877 SDValue SRA =
3878 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3879 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3880 SDValue SHL =
3881 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3882 SDValue OR =
3883 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3884 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3885 return Result;
3886 }
3887 case Intrinsic::arm_cls64: {
3888 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
3889 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
3890 const SDValue &Operand = Op.getOperand(1);
3891 const EVT VTy = Op.getValueType();
3892
3893 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3894 DAG.getConstant(1, dl, VTy));
3895 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3896 DAG.getConstant(0, dl, VTy));
3897 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
3898 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
3899 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
3900 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
3901 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
3902 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
3903 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
3904 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3905 SDValue CheckLo =
3906 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3907 SDValue HiIsZero =
3908 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
3909 SDValue AdjustedLo =
3910 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
3911 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
3912 SDValue Result =
3913 DAG.getSelect(dl, VTy, CheckLo,
3914 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
3915 return Result;
3916 }
3917 case Intrinsic::eh_sjlj_lsda: {
3918 MachineFunction &MF = DAG.getMachineFunction();
3919 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3920 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3921 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3922 SDValue CPAddr;
3923 bool IsPositionIndependent = isPositionIndependent();
3924 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3925 ARMConstantPoolValue *CPV =
3926 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3927 ARMCP::CPLSDA, PCAdj);
3928 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4));
3929 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3930 SDValue Result = DAG.getLoad(
3931 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3932 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3933
3934 if (IsPositionIndependent) {
3935 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3936 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3937 }
3938 return Result;
3939 }
3940 case Intrinsic::arm_neon_vabs:
3941 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3942 Op.getOperand(1));
3943 case Intrinsic::arm_neon_vmulls:
3944 case Intrinsic::arm_neon_vmullu: {
3945 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3946 ? ARMISD::VMULLs : ARMISD::VMULLu;
3947 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3948 Op.getOperand(1), Op.getOperand(2));
3949 }
3950 case Intrinsic::arm_neon_vminnm:
3951 case Intrinsic::arm_neon_vmaxnm: {
3952 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3953 ? ISD::FMINNUM : ISD::FMAXNUM;
3954 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3955 Op.getOperand(1), Op.getOperand(2));
3956 }
3957 case Intrinsic::arm_neon_vminu:
3958 case Intrinsic::arm_neon_vmaxu: {
3959 if (Op.getValueType().isFloatingPoint())
3960 return SDValue();
3961 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3962 ? ISD::UMIN : ISD::UMAX;
3963 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3964 Op.getOperand(1), Op.getOperand(2));
3965 }
3966 case Intrinsic::arm_neon_vmins:
3967 case Intrinsic::arm_neon_vmaxs: {
3968 // v{min,max}s is overloaded between signed integers and floats.
3969 if (!Op.getValueType().isFloatingPoint()) {
3970 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3971 ? ISD::SMIN : ISD::SMAX;
3972 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3973 Op.getOperand(1), Op.getOperand(2));
3974 }
3975 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3976 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3977 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3978 Op.getOperand(1), Op.getOperand(2));
3979 }
3980 case Intrinsic::arm_neon_vtbl1:
3981 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3982 Op.getOperand(1), Op.getOperand(2));
3983 case Intrinsic::arm_neon_vtbl2:
3984 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3985 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3986 case Intrinsic::arm_mve_pred_i2v:
3987 case Intrinsic::arm_mve_pred_v2i:
3988 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
3989 Op.getOperand(1));
3990 case Intrinsic::arm_mve_vreinterpretq:
3991 return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
3992 Op.getOperand(1));
3993 case Intrinsic::arm_mve_lsll:
3994 return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
3995 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3996 case Intrinsic::arm_mve_asrl:
3997 return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
3998 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3999 }
4000}
4001
4002static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
4003 const ARMSubtarget *Subtarget) {
4004 SDLoc dl(Op);
4005 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
4006 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
4007 if (SSID == SyncScope::SingleThread)
4008 return Op;
4009
4010 if (!Subtarget->hasDataBarrier()) {
4011 // Some ARMv6 cpus can support data barriers with an mcr instruction.
4012 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
4013 // here.
4014 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4015, __PRETTY_FUNCTION__))
4015 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4015, __PRETTY_FUNCTION__))
;
4016 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
4017 DAG.getConstant(0, dl, MVT::i32));
4018 }
4019
4020 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
4021 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
4022 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
4023 if (Subtarget->isMClass()) {
4024 // Only a full system barrier exists in the M-class architectures.
4025 Domain = ARM_MB::SY;
4026 } else if (Subtarget->preferISHSTBarriers() &&
4027 Ord == AtomicOrdering::Release) {
4028 // Swift happens to implement ISHST barriers in a way that's compatible with
4029 // Release semantics but weaker than ISH so we'd be fools not to use
4030 // it. Beware: other processors probably don't!
4031 Domain = ARM_MB::ISHST;
4032 }
4033
4034 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
4035 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
4036 DAG.getConstant(Domain, dl, MVT::i32));
4037}
4038
4039static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
4040 const ARMSubtarget *Subtarget) {
4041 // ARM pre v5TE and Thumb1 does not have preload instructions.
4042 if (!(Subtarget->isThumb2() ||
4043 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
4044 // Just preserve the chain.
4045 return Op.getOperand(0);
4046
4047 SDLoc dl(Op);
4048 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
4049 if (!isRead &&
4050 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
4051 // ARMv7 with MP extension has PLDW.
4052 return Op.getOperand(0);
4053
4054 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
4055 if (Subtarget->isThumb()) {
4056 // Invert the bits.
4057 isRead = ~isRead & 1;
4058 isData = ~isData & 1;
4059 }
4060
4061 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
4062 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
4063 DAG.getConstant(isData, dl, MVT::i32));
4064}
4065
4066static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
4067 MachineFunction &MF = DAG.getMachineFunction();
4068 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
4069
4070 // vastart just stores the address of the VarArgsFrameIndex slot into the
4071 // memory location argument.
4072 SDLoc dl(Op);
4073 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4074 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
4075 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
4076 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
4077 MachinePointerInfo(SV));
4078}
4079
4080SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
4081 CCValAssign &NextVA,
4082 SDValue &Root,
4083 SelectionDAG &DAG,
4084 const SDLoc &dl) const {
4085 MachineFunction &MF = DAG.getMachineFunction();
4086 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4087
4088 const TargetRegisterClass *RC;
4089 if (AFI->isThumb1OnlyFunction())
4090 RC = &ARM::tGPRRegClass;
4091 else
4092 RC = &ARM::GPRRegClass;
4093
4094 // Transform the arguments stored in physical registers into virtual ones.
4095 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4096 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4097
4098 SDValue ArgValue2;
4099 if (NextVA.isMemLoc()) {
4100 MachineFrameInfo &MFI = MF.getFrameInfo();
4101 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
4102
4103 // Create load node to retrieve arguments from the stack.
4104 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4105 ArgValue2 = DAG.getLoad(
4106 MVT::i32, dl, Root, FIN,
4107 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4108 } else {
4109 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
4110 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
4111 }
4112 if (!Subtarget->isLittle())
4113 std::swap (ArgValue, ArgValue2);
4114 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
4115}
4116
4117// The remaining GPRs hold either the beginning of variable-argument
4118// data, or the beginning of an aggregate passed by value (usually
4119// byval). Either way, we allocate stack slots adjacent to the data
4120// provided by our caller, and store the unallocated registers there.
4121// If this is a variadic function, the va_list pointer will begin with
4122// these values; otherwise, this reassembles a (byval) structure that
4123// was split between registers and memory.
4124// Return: The frame index registers were stored into.
4125int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
4126 const SDLoc &dl, SDValue &Chain,
4127 const Value *OrigArg,
4128 unsigned InRegsParamRecordIdx,
4129 int ArgOffset, unsigned ArgSize) const {
4130 // Currently, two use-cases possible:
4131 // Case #1. Non-var-args function, and we meet first byval parameter.
4132 // Setup first unallocated register as first byval register;
4133 // eat all remained registers
4134 // (these two actions are performed by HandleByVal method).
4135 // Then, here, we initialize stack frame with
4136 // "store-reg" instructions.
4137 // Case #2. Var-args function, that doesn't contain byval parameters.
4138 // The same: eat all remained unallocated registers,
4139 // initialize stack frame.
4140
4141 MachineFunction &MF = DAG.getMachineFunction();
4142 MachineFrameInfo &MFI = MF.getFrameInfo();
4143 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4144 unsigned RBegin, REnd;
4145 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
4146 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
4147 } else {
4148 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4149 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
4150 REnd = ARM::R4;
4151 }
4152
4153 if (REnd != RBegin)
4154 ArgOffset = -4 * (ARM::R4 - RBegin);
4155
4156 auto PtrVT = getPointerTy(DAG.getDataLayout());
4157 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
4158 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
4159
4160 SmallVector<SDValue, 4> MemOps;
4161 const TargetRegisterClass *RC =
4162 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
4163
4164 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
4165 unsigned VReg = MF.addLiveIn(Reg, RC);
4166 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
4167 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
4168 MachinePointerInfo(OrigArg, 4 * i));
4169 MemOps.push_back(Store);
4170 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
4171 }
4172
4173 if (!MemOps.empty())
4174 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
4175 return FrameIndex;
4176}
4177
4178// Setup stack frame, the va_list pointer will start from.
4179void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
4180 const SDLoc &dl, SDValue &Chain,
4181 unsigned ArgOffset,
4182 unsigned TotalArgRegsSaveSize,
4183 bool ForceMutable) const {
4184 MachineFunction &MF = DAG.getMachineFunction();
4185 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4186
4187 // Try to store any remaining integer argument regs
4188 // to their spots on the stack so that they may be loaded by dereferencing
4189 // the result of va_next.
4190 // If there is no regs to be stored, just point address after last
4191 // argument passed via stack.
4192 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
4193 CCInfo.getInRegsParamsCount(),
4194 CCInfo.getNextStackOffset(),
4195 std::max(4U, TotalArgRegsSaveSize));
4196 AFI->setVarArgsFrameIndex(FrameIndex);
4197}
4198
4199bool ARMTargetLowering::splitValueIntoRegisterParts(
4200 SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
4201 unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
4202 bool IsABIRegCopy = CC.hasValue();
4203 EVT ValueVT = Val.getValueType();
4204 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4205 PartVT == MVT::f32) {
4206 unsigned ValueBits = ValueVT.getSizeInBits();
4207 unsigned PartBits = PartVT.getSizeInBits();
4208 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(ValueBits), Val);
4209 Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::getIntegerVT(PartBits), Val);
4210 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
4211 Parts[0] = Val;
4212 return true;
4213 }
4214 return false;
4215}
4216
4217SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
4218 SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
4219 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
4220 bool IsABIRegCopy = CC.hasValue();
4221 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4222 PartVT == MVT::f32) {
4223 unsigned ValueBits = ValueVT.getSizeInBits();
4224 unsigned PartBits = PartVT.getSizeInBits();
4225 SDValue Val = Parts[0];
4226
4227 Val = DAG.getNode(ISD::BITCAST, DL, MVT::getIntegerVT(PartBits), Val);
4228 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::getIntegerVT(ValueBits), Val);
4229 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
4230 return Val;
4231 }
4232 return SDValue();
4233}
4234
4235SDValue ARMTargetLowering::LowerFormalArguments(
4236 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
4237 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
4238 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
4239 MachineFunction &MF = DAG.getMachineFunction();
4240 MachineFrameInfo &MFI = MF.getFrameInfo();
4241
4242 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
4243
4244 // Assign locations to all of the incoming arguments.
4245 SmallVector<CCValAssign, 16> ArgLocs;
4246 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4247 *DAG.getContext());
4248 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
4249
4250 SmallVector<SDValue, 16> ArgValues;
4251 SDValue ArgValue;
4252 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
4253 unsigned CurArgIdx = 0;
4254
4255 // Initially ArgRegsSaveSize is zero.
4256 // Then we increase this value each time we meet byval parameter.
4257 // We also increase this value in case of varargs function.
4258 AFI->setArgRegsSaveSize(0);
4259
4260 // Calculate the amount of stack space that we need to allocate to store
4261 // byval and variadic arguments that are passed in registers.
4262 // We need to know this before we allocate the first byval or variadic
4263 // argument, as they will be allocated a stack slot below the CFA (Canonical
4264 // Frame Address, the stack pointer at entry to the function).
4265 unsigned ArgRegBegin = ARM::R4;
4266 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4267 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
4268 break;
4269
4270 CCValAssign &VA = ArgLocs[i];
4271 unsigned Index = VA.getValNo();
4272 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
4273 if (!Flags.isByVal())
4274 continue;
4275
4276 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4276, __PRETTY_FUNCTION__))
;
4277 unsigned RBegin, REnd;
4278 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
4279 ArgRegBegin = std::min(ArgRegBegin, RBegin);
4280
4281 CCInfo.nextInRegsParam();
4282 }
4283 CCInfo.rewindByValRegsInfo();
4284
4285 int lastInsIndex = -1;
4286 if (isVarArg && MFI.hasVAStart()) {
4287 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4288 if (RegIdx != array_lengthof(GPRArgRegs))
4289 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4290 }
4291
4292 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4293 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4294 auto PtrVT = getPointerTy(DAG.getDataLayout());
4295
4296 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4297 CCValAssign &VA = ArgLocs[i];
4298 if (Ins[VA.getValNo()].isOrigArg()) {
4299 std::advance(CurOrigArg,
4300 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4301 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4302 }
4303 // Arguments stored in registers.
4304 if (VA.isRegLoc()) {
4305 EVT RegVT = VA.getLocVT();
4306
4307 if (VA.needsCustom() && VA.getLocVT() == MVT::v2f64) {
4308 // f64 and vector types are split up into multiple registers or
4309 // combinations of registers and stack slots.
4310 SDValue ArgValue1 =
4311 GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4312 VA = ArgLocs[++i]; // skip ahead to next loc
4313 SDValue ArgValue2;
4314 if (VA.isMemLoc()) {
4315 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4316 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4317 ArgValue2 = DAG.getLoad(
4318 MVT::f64, dl, Chain, FIN,
4319 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
4320 } else {
4321 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4322 }
4323 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4324 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4325 ArgValue1, DAG.getIntPtrConstant(0, dl));
4326 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, ArgValue,
4327 ArgValue2, DAG.getIntPtrConstant(1, dl));
4328 } else if (VA.needsCustom() && VA.getLocVT() == MVT::f64) {
4329 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4330 } else {
4331 const TargetRegisterClass *RC;
4332
4333 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4334 RC = &ARM::HPRRegClass;
4335 else if (RegVT == MVT::f32)
4336 RC = &ARM::SPRRegClass;
4337 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16 ||
4338 RegVT == MVT::v4bf16)
4339 RC = &ARM::DPRRegClass;
4340 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16 ||
4341 RegVT == MVT::v8bf16)
4342 RC = &ARM::QPRRegClass;
4343 else if (RegVT == MVT::i32)
4344 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4345 : &ARM::GPRRegClass;
4346 else
4347 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4347)
;
4348
4349 // Transform the arguments in physical registers into virtual ones.
4350 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4351 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4352
4353 // If this value is passed in r0 and has the returned attribute (e.g.
4354 // C++ 'structors), record this fact for later use.
4355 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4356 AFI->setPreservesR0();
4357 }
4358 }
4359
4360 // If this is an 8 or 16-bit value, it is really passed promoted
4361 // to 32 bits. Insert an assert[sz]ext to capture this, then
4362 // truncate to the right size.
4363 switch (VA.getLocInfo()) {
4364 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4364)
;
4365 case CCValAssign::Full: break;
4366 case CCValAssign::BCvt:
4367 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4368 break;
4369 case CCValAssign::SExt:
4370 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4371 DAG.getValueType(VA.getValVT()));
4372 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4373 break;
4374 case CCValAssign::ZExt:
4375 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4376 DAG.getValueType(VA.getValVT()));
4377 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4378 break;
4379 }
4380
4381 // f16 arguments have their size extended to 4 bytes and passed as if they
4382 // had been copied to the LSBs of a 32-bit register.
4383 // For that, it's passed extended to i32 (soft ABI) or to f32 (hard ABI)
4384 if (VA.needsCustom() &&
4385 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
4386 ArgValue = MoveToHPR(dl, DAG, VA.getLocVT(), VA.getValVT(), ArgValue);
4387
4388 InVals.push_back(ArgValue);
4389 } else { // VA.isRegLoc()
4390 // sanity check
4391 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4391, __PRETTY_FUNCTION__))
;
4392 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4392, __PRETTY_FUNCTION__))
;
4393
4394 int index = VA.getValNo();
4395
4396 // Some Ins[] entries become multiple ArgLoc[] entries.
4397 // Process them only once.
4398 if (index != lastInsIndex)
4399 {
4400 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4401 // FIXME: For now, all byval parameter objects are marked mutable.
4402 // This can be changed with more analysis.
4403 // In case of tail call optimization mark all arguments mutable.
4404 // Since they could be overwritten by lowering of arguments in case of
4405 // a tail call.
4406 if (Flags.isByVal()) {
4407 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4408, __PRETTY_FUNCTION__))
4408 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4408, __PRETTY_FUNCTION__))
;
4409 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4410
4411 int FrameIndex = StoreByValRegs(
4412 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4413 VA.getLocMemOffset(), Flags.getByValSize());
4414 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4415 CCInfo.nextInRegsParam();
4416 } else {
4417 unsigned FIOffset = VA.getLocMemOffset();
4418 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4419 FIOffset, true);
4420
4421 // Create load nodes to retrieve arguments from the stack.
4422 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4423 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4424 MachinePointerInfo::getFixedStack(
4425 DAG.getMachineFunction(), FI)));
4426 }
4427 lastInsIndex = index;
4428 }
4429 }
4430 }
4431
4432 // varargs
4433 if (isVarArg && MFI.hasVAStart())
4434 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
4435 CCInfo.getNextStackOffset(),
4436 TotalArgRegsSaveSize);
4437
4438 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
4439
4440 return Chain;
4441}
4442
4443/// isFloatingPointZero - Return true if this is +0.0.
4444static bool isFloatingPointZero(SDValue Op) {
4445 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
4446 return CFP->getValueAPF().isPosZero();
4447 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4448 // Maybe this has already been legalized into the constant pool?
4449 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
4450 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4451 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4452 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4453 return CFP->getValueAPF().isPosZero();
4454 }
4455 } else if (Op->getOpcode() == ISD::BITCAST &&
4456 Op->getValueType(0) == MVT::f64) {
4457 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4458 // created by LowerConstantFP().
4459 SDValue BitcastOp = Op->getOperand(0);
4460 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4461 isNullConstant(BitcastOp->getOperand(0)))
4462 return true;
4463 }
4464 return false;
4465}
4466
4467/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4468/// the given operands.
4469SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4470 SDValue &ARMcc, SelectionDAG &DAG,
4471 const SDLoc &dl) const {
4472 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4473 unsigned C = RHSC->getZExtValue();
4474 if (!isLegalICmpImmediate((int32_t)C)) {
4475 // Constant does not fit, try adjusting it by one.
4476 switch (CC) {
4477 default: break;
4478 case ISD::SETLT:
4479 case ISD::SETGE:
4480 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4481 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4482 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4483 }
4484 break;
4485 case ISD::SETULT:
4486 case ISD::SETUGE:
4487 if (C != 0 && isLegalICmpImmediate(C-1)) {
4488 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4489 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4490 }
4491 break;
4492 case ISD::SETLE:
4493 case ISD::SETGT:
4494 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4495 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4496 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4497 }
4498 break;
4499 case ISD::SETULE:
4500 case ISD::SETUGT:
4501 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4502 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4503 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4504 }
4505 break;
4506 }
4507 }
4508 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4509 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4510 // In ARM and Thumb-2, the compare instructions can shift their second
4511 // operand.
4512 CC = ISD::getSetCCSwappedOperands(CC);
4513 std::swap(LHS, RHS);
4514 }
4515
4516 // Thumb1 has very limited immediate modes, so turning an "and" into a
4517 // shift can save multiple instructions.
4518 //
4519 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4520 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4521 // own. If it's the operand to an unsigned comparison with an immediate,
4522 // we can eliminate one of the shifts: we transform
4523 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4524 //
4525 // We avoid transforming cases which aren't profitable due to encoding
4526 // details:
4527 //
4528 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4529 // would not; in that case, we're essentially trading one immediate load for
4530 // another.
4531 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4532 // 3. C2 is zero; we have other code for this special case.
4533 //
4534 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4535 // instruction, since the AND is always one instruction anyway, but we could
4536 // use narrow instructions in some cases.
4537 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4538 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4539 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4540 !isSignedIntSetCC(CC)) {
4541 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4542 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4543 uint64_t RHSV = RHSC->getZExtValue();
4544 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4545 unsigned ShiftBits = countLeadingZeros(Mask);
4546 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4547 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4548 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4549 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4550 }
4551 }
4552 }
4553
4554 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4555 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4556 // way a cmp would.
4557 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4558 // some tweaks to the heuristics for the previous and->shift transform.
4559 // FIXME: Optimize cases where the LHS isn't a shift.
4560 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4561 isa<ConstantSDNode>(RHS) &&
4562 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4563 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4564 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4565 unsigned ShiftAmt =
4566 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4567 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4568 DAG.getVTList(MVT::i32, MVT::i32),
4569 LHS.getOperand(0),
4570 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4571 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4572 Shift.getValue(1), SDValue());
4573 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4574 return Chain.getValue(1);
4575 }
4576
4577 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4578
4579 // If the RHS is a constant zero then the V (overflow) flag will never be
4580 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4581 // simpler for other passes (like the peephole optimiser) to deal with.
4582 if (isNullConstant(RHS)) {
4583 switch (CondCode) {
4584 default: break;
4585 case ARMCC::GE:
4586 CondCode = ARMCC::PL;
4587 break;
4588 case ARMCC::LT:
4589 CondCode = ARMCC::MI;
4590 break;
4591 }
4592 }
4593
4594 ARMISD::NodeType CompareType;
4595 switch (CondCode) {
4596 default:
4597 CompareType = ARMISD::CMP;
4598 break;
4599 case ARMCC::EQ:
4600 case ARMCC::NE:
4601 // Uses only Z Flag
4602 CompareType = ARMISD::CMPZ;
4603 break;
4604 }
4605 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4606 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4607}
4608
4609/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4610SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4611 SelectionDAG &DAG, const SDLoc &dl,
4612 bool Signaling) const {
4613 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)((Subtarget->hasFP64() || RHS.getValueType() != MVT::f64) ?
static_cast<void> (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4613, __PRETTY_FUNCTION__))
;
4614 SDValue Cmp;
4615 if (!isFloatingPointZero(RHS))
4616 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4617 dl, MVT::Glue, LHS, RHS);
4618 else
4619 Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4620 dl, MVT::Glue, LHS);
4621 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4622}
4623
4624/// duplicateCmp - Glue values can have only one use, so this function
4625/// duplicates a comparison node.
4626SDValue
4627ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4628 unsigned Opc = Cmp.getOpcode();
4629 SDLoc DL(Cmp);
4630 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4631 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4632
4633 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4633, __PRETTY_FUNCTION__))
;
4634 Cmp = Cmp.getOperand(0);
4635 Opc = Cmp.getOpcode();
4636 if (Opc == ARMISD::CMPFP)
4637 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4638 else {
4639 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4639, __PRETTY_FUNCTION__))
;
4640 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4641 }
4642 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4643}
4644
4645// This function returns three things: the arithmetic computation itself
4646// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4647// comparison and the condition code define the case in which the arithmetic
4648// computation *does not* overflow.
4649std::pair<SDValue, SDValue>
4650ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4651 SDValue &ARMcc) const {
4652 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4652, __PRETTY_FUNCTION__))
;
4653
4654 SDValue Value, OverflowCmp;
4655 SDValue LHS = Op.getOperand(0);
4656 SDValue RHS = Op.getOperand(1);
4657 SDLoc dl(Op);
4658
4659 // FIXME: We are currently always generating CMPs because we don't support
4660 // generating CMN through the backend. This is not as good as the natural
4661 // CMP case because it causes a register dependency and cannot be folded
4662 // later.
4663
4664 switch (Op.getOpcode()) {
4665 default:
4666 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4666)
;
4667 case ISD::SADDO:
4668 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4669 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4670 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4671 break;
4672 case ISD::UADDO:
4673 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4674 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4675 // We do not use it in the USUBO case as Value may not be used.
4676 Value = DAG.getNode(ARMISD::ADDC, dl,
4677 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4678 .getValue(0);
4679 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4680 break;
4681 case ISD::SSUBO:
4682 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4683 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4684 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4685 break;
4686 case ISD::USUBO:
4687 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4688 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4689 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4690 break;
4691 case ISD::UMULO:
4692 // We generate a UMUL_LOHI and then check if the high word is 0.
4693 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4694 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4695 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4696 LHS, RHS);
4697 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4698 DAG.getConstant(0, dl, MVT::i32));
4699 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4700 break;
4701 case ISD::SMULO:
4702 // We generate a SMUL_LOHI and then check if all the bits of the high word
4703 // are the same as the sign bit of the low word.
4704 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4705 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4706 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4707 LHS, RHS);
4708 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4709 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4710 Value.getValue(0),
4711 DAG.getConstant(31, dl, MVT::i32)));
4712 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4713 break;
4714 } // switch (...)
4715
4716 return std::make_pair(Value, OverflowCmp);
4717}
4718
4719SDValue
4720ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4721 // Let legalize expand this if it isn't a legal type yet.
4722 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4723 return SDValue();
4724
4725 SDValue Value, OverflowCmp;
4726 SDValue ARMcc;
4727 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4728 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4729 SDLoc dl(Op);
4730 // We use 0 and 1 as false and true values.
4731 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4732 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4733 EVT VT = Op.getValueType();
4734
4735 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4736 ARMcc, CCR, OverflowCmp);
4737
4738 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4739 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4740}
4741
4742static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4743 SelectionDAG &DAG) {
4744 SDLoc DL(BoolCarry);
4745 EVT CarryVT = BoolCarry.getValueType();
4746
4747 // This converts the boolean value carry into the carry flag by doing
4748 // ARMISD::SUBC Carry, 1
4749 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4750 DAG.getVTList(CarryVT, MVT::i32),
4751 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4752 return Carry.getValue(1);
4753}
4754
4755static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4756 SelectionDAG &DAG) {
4757 SDLoc DL(Flags);
4758
4759 // Now convert the carry flag into a boolean carry. We do this
4760 // using ARMISD:ADDE 0, 0, Carry
4761 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4762 DAG.getConstant(0, DL, MVT::i32),
4763 DAG.getConstant(0, DL, MVT::i32), Flags);
4764}
4765
4766SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4767 SelectionDAG &DAG) const {
4768 // Let legalize expand this if it isn't a legal type yet.
4769 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4770 return SDValue();
4771
4772 SDValue LHS = Op.getOperand(0);
4773 SDValue RHS = Op.getOperand(1);
4774 SDLoc dl(Op);
4775
4776 EVT VT = Op.getValueType();
4777 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4778 SDValue Value;
4779 SDValue Overflow;
4780 switch (Op.getOpcode()) {
4781 default:
4782 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4782)
;
4783 case ISD::UADDO:
4784 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4785 // Convert the carry flag into a boolean value.
4786 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4787 break;
4788 case ISD::USUBO: {
4789 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4790 // Convert the carry flag into a boolean value.
4791 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4792 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4793 // value. So compute 1 - C.
4794 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4795 DAG.getConstant(1, dl, MVT::i32), Overflow);
4796 break;
4797 }
4798 }
4799
4800 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4801}
4802
4803static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4804 const ARMSubtarget *Subtarget) {
4805 EVT VT = Op.getValueType();
4806 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())
4807 return SDValue();
4808 if (!VT.isSimple())
4809 return SDValue();
4810
4811 unsigned NewOpcode;
4812 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4813 switch (VT.getSimpleVT().SimpleTy) {
4814 default:
4815 return SDValue();
4816 case MVT::i8:
4817 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4818 break;
4819 case MVT::i16:
4820 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4821 break;
4822 }
4823
4824 SDLoc dl(Op);
4825 SDValue Add =
4826 DAG.getNode(NewOpcode, dl, MVT::i32,
4827 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4828 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4829 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4830}
4831
4832SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4833 SDValue Cond = Op.getOperand(0);
4834 SDValue SelectTrue = Op.getOperand(1);
4835 SDValue SelectFalse = Op.getOperand(2);
4836 SDLoc dl(Op);
4837 unsigned Opc = Cond.getOpcode();
4838
4839 if (Cond.getResNo() == 1 &&
4840 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4841 Opc == ISD::USUBO)) {
4842 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4843 return SDValue();
4844
4845 SDValue Value, OverflowCmp;
4846 SDValue ARMcc;
4847 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4848 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4849 EVT VT = Op.getValueType();
4850
4851 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4852 OverflowCmp, DAG);
4853 }
4854
4855 // Convert:
4856 //
4857 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4858 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4859 //
4860 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4861 const ConstantSDNode *CMOVTrue =
4862 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4863 const ConstantSDNode *CMOVFalse =
4864 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4865
4866 if (CMOVTrue && CMOVFalse) {
4867 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4868 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4869
4870 SDValue True;
4871 SDValue False;
4872 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4873 True = SelectTrue;
4874 False = SelectFalse;
4875 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4876 True = SelectFalse;
4877 False = SelectTrue;
4878 }
4879
4880 if (True.getNode() && False.getNode()) {
4881 EVT VT = Op.getValueType();
4882 SDValue ARMcc = Cond.getOperand(2);
4883 SDValue CCR = Cond.getOperand(3);
4884 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4885 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4885, __PRETTY_FUNCTION__))
;
4886 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4887 }
4888 }
4889 }
4890
4891 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4892 // undefined bits before doing a full-word comparison with zero.
4893 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4894 DAG.getConstant(1, dl, Cond.getValueType()));
4895
4896 return DAG.getSelectCC(dl, Cond,
4897 DAG.getConstant(0, dl, Cond.getValueType()),
4898 SelectTrue, SelectFalse, ISD::SETNE);
4899}
4900
4901static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4902 bool &swpCmpOps, bool &swpVselOps) {
4903 // Start by selecting the GE condition code for opcodes that return true for
4904 // 'equality'
4905 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4906 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4907 CondCode = ARMCC::GE;
4908
4909 // and GT for opcodes that return false for 'equality'.
4910 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4911 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4912 CondCode = ARMCC::GT;
4913
4914 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4915 // to swap the compare operands.
4916 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4917 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4918 swpCmpOps = true;
4919
4920 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4921 // If we have an unordered opcode, we need to swap the operands to the VSEL
4922 // instruction (effectively negating the condition).
4923 //
4924 // This also has the effect of swapping which one of 'less' or 'greater'
4925 // returns true, so we also swap the compare operands. It also switches
4926 // whether we return true for 'equality', so we compensate by picking the
4927 // opposite condition code to our original choice.
4928 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4929 CC == ISD::SETUGT) {
4930 swpCmpOps = !swpCmpOps;
4931 swpVselOps = !swpVselOps;
4932 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4933 }
4934
4935 // 'ordered' is 'anything but unordered', so use the VS condition code and
4936 // swap the VSEL operands.
4937 if (CC == ISD::SETO) {
4938 CondCode = ARMCC::VS;
4939 swpVselOps = true;
4940 }
4941
4942 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4943 // code and swap the VSEL operands. Also do this if we don't care about the
4944 // unordered case.
4945 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4946 CondCode = ARMCC::EQ;
4947 swpVselOps = true;
4948 }
4949}
4950
4951SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4952 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4953 SDValue Cmp, SelectionDAG &DAG) const {
4954 if (!Subtarget->hasFP64() && VT == MVT::f64) {
4955 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4956 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4957 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4958 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4959
4960 SDValue TrueLow = TrueVal.getValue(0);
4961 SDValue TrueHigh = TrueVal.getValue(1);
4962 SDValue FalseLow = FalseVal.getValue(0);
4963 SDValue FalseHigh = FalseVal.getValue(1);
4964
4965 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4966 ARMcc, CCR, Cmp);
4967 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4968 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4969
4970 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4971 } else {
4972 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4973 Cmp);
4974 }
4975}
4976
4977static bool isGTorGE(ISD::CondCode CC) {
4978 return CC == ISD::SETGT || CC == ISD::SETGE;
4979}
4980
4981static bool isLTorLE(ISD::CondCode CC) {
4982 return CC == ISD::SETLT || CC == ISD::SETLE;
4983}
4984
4985// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4986// All of these conditions (and their <= and >= counterparts) will do:
4987// x < k ? k : x
4988// x > k ? x : k
4989// k < x ? x : k
4990// k > x ? k : x
4991static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4992 const SDValue TrueVal, const SDValue FalseVal,
4993 const ISD::CondCode CC, const SDValue K) {
4994 return (isGTorGE(CC) &&
4995 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4996 (isLTorLE(CC) &&
4997 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4998}
4999
5000// Check if two chained conditionals could be converted into SSAT or USAT.
5001//
5002// SSAT can replace a set of two conditional selectors that bound a number to an
5003// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
5004//
5005// x < -k ? -k : (x > k ? k : x)
5006// x < -k ? -k : (x < k ? x : k)
5007// x > -k ? (x > k ? k : x) : -k
5008// x < k ? (x < -k ? -k : x) : k
5009// etc.
5010//
5011// LLVM canonicalizes these to either a min(max()) or a max(min())
5012// pattern. This function tries to match one of these and will return true
5013// if successful.
5014//
5015// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
5016// a power of 2.
5017//
5018// It returns true if the conversion can be done, false otherwise.
5019// Additionally, the variable is returned in parameter V, the constant in K and
5020// usat is set to true if the conditional represents an unsigned saturation
5021static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
5022 uint64_t &K, bool &Usat) {
5023 SDValue V1 = Op.getOperand(0);
5024 SDValue K1 = Op.getOperand(1);
5025 SDValue TrueVal1 = Op.getOperand(2);
5026 SDValue FalseVal1 = Op.getOperand(3);
5027 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5028
5029 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
5030 if (Op2.getOpcode() != ISD::SELECT_CC)
5031 return false;
5032
5033 SDValue V2 = Op2.getOperand(0);
5034 SDValue K2 = Op2.getOperand(1);
5035 SDValue TrueVal2 = Op2.getOperand(2);
5036 SDValue FalseVal2 = Op2.getOperand(3);
5037 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
5038
5039 SDValue V1Tmp = V1;
5040 SDValue V2Tmp = V2;
5041
5042 if (V1.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5043 V2.getOpcode() == ISD::SIGN_EXTEND_INREG) {
5044 V1Tmp = V1.getOperand(0);
5045 V2Tmp = V2.getOperand(0);
5046 }
5047
5048 // Check that the registers and the constants match a max(min()) or min(max())
5049 // pattern
5050 if (V1Tmp == TrueVal1 && V2Tmp == TrueVal2 && K1 == FalseVal1 &&
5051 K2 == FalseVal2 &&
5052 ((isGTorGE(CC1) && isLTorLE(CC2)) || (isLTorLE(CC1) && isGTorGE(CC2)))) {
5053
5054 // Check that the constant in the lower-bound check is
5055 // the opposite of the constant in the upper-bound check
5056 // in 1's complement.
5057 if (!isa<ConstantSDNode>(K1) || !isa<ConstantSDNode>(K2))
5058 return false;
5059
5060 int64_t Val1 = cast<ConstantSDNode>(K1)->getSExtValue();
5061 int64_t Val2 = cast<ConstantSDNode>(K2)->getSExtValue();
5062 int64_t PosVal = std::max(Val1, Val2);
5063 int64_t NegVal = std::min(Val1, Val2);
5064
5065 if (!((Val1 > Val2 && isLTorLE(CC1)) || (Val1 < Val2 && isLTorLE(CC2))) ||
5066 !isPowerOf2_64(PosVal + 1))
5067 return false;
5068
5069 // Handle the difference between USAT (unsigned) and SSAT (signed)
5070 // saturation
5071 if (Val1 == ~Val2)
5072 Usat = false;
5073 else if (NegVal == 0)
5074 Usat = true;
5075 else
5076 return false;
5077
5078 V = V2Tmp;
5079 // At this point, PosVal is guaranteed to be positive
5080 K = (uint64_t) PosVal;
5081
5082 return true;
5083 }
5084 return false;
5085}
5086
5087// Check if a condition of the type x < k ? k : x can be converted into a
5088// bit operation instead of conditional moves.
5089// Currently this is allowed given:
5090// - The conditions and values match up
5091// - k is 0 or -1 (all ones)
5092// This function will not check the last condition, thats up to the caller
5093// It returns true if the transformation can be made, and in such case
5094// returns x in V, and k in SatK.
5095static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
5096 SDValue &SatK)
5097{
5098 SDValue LHS = Op.getOperand(0);
5099 SDValue RHS = Op.getOperand(1);
5100 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5101 SDValue TrueVal = Op.getOperand(2);
5102 SDValue FalseVal = Op.getOperand(3);
5103
5104 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
5105 ? &RHS
5106 : nullptr;
5107
5108 // No constant operation in comparison, early out
5109 if (!K)
5110 return false;
5111
5112 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
5113 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
5114 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
5115
5116 // If the constant on left and right side, or variable on left and right,
5117 // does not match, early out
5118 if (*K != KTmp || V != VTmp)
5119 return false;
5120
5121 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
5122 SatK = *K;
5123 return true;
5124 }
5125
5126 return false;
5127}
5128
5129bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
5130 if (VT == MVT::f32)
5131 return !Subtarget->hasVFP2Base();
5132 if (VT == MVT::f64)
5133 return !Subtarget->hasFP64();
5134 if (VT == MVT::f16)
5135 return !Subtarget->hasFullFP16();
5136 return false;
5137}
5138
5139SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5140 EVT VT = Op.getValueType();
5141 SDLoc dl(Op);
5142
5143 // Try to convert two saturating conditional selects into a single SSAT
5144 SDValue SatValue;
5145 uint64_t SatConstant;
5146 bool SatUSat;
5147 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
5148 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
5149 if (SatUSat)
5150 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
5151 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
5152 else
5153 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
5154 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
5155 }
5156
5157 // Try to convert expressions of the form x < k ? k : x (and similar forms)
5158 // into more efficient bit operations, which is possible when k is 0 or -1
5159 // On ARM and Thumb-2 which have flexible operand 2 this will result in
5160 // single instructions. On Thumb the shift and the bit operation will be two
5161 // instructions.
5162 // Only allow this transformation on full-width (32-bit) operations
5163 SDValue LowerSatConstant;
5164 if (VT == MVT::i32 &&
5165 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
5166 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
5167 DAG.getConstant(31, dl, VT));
5168 if (isNullConstant(LowerSatConstant)) {
5169 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
5170 DAG.getAllOnesConstant(dl, VT));
5171 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
5172 } else if (isAllOnesConstant(LowerSatConstant))
5173 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
5174 }
5175
5176 SDValue LHS = Op.getOperand(0);
5177 SDValue RHS = Op.getOperand(1);
5178 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5179 SDValue TrueVal = Op.getOperand(2);
5180 SDValue FalseVal = Op.getOperand(3);
5181 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
5182 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
5183
5184 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
5185 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
5186 unsigned TVal = CTVal->getZExtValue();
5187 unsigned FVal = CFVal->getZExtValue();
5188 unsigned Opcode = 0;
5189
5190 if (TVal == ~FVal) {
5191 Opcode = ARMISD::CSINV;
5192 } else if (TVal == ~FVal + 1) {
5193 Opcode = ARMISD::CSNEG;
5194 } else if (TVal + 1 == FVal) {
5195 Opcode = ARMISD::CSINC;
5196 } else if (TVal == FVal + 1) {
5197 Opcode = ARMISD::CSINC;
5198 std::swap(TrueVal, FalseVal);
5199 std::swap(TVal, FVal);
5200 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5201 }
5202
5203 if (Opcode) {
5204 // If one of the constants is cheaper than another, materialise the
5205 // cheaper one and let the csel generate the other.
5206 if (Opcode != ARMISD::CSINC &&
5207 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
5208 std::swap(TrueVal, FalseVal);
5209 std::swap(TVal, FVal);
5210 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5211 }
5212
5213 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
5214 // to get there. CSINC not is invertable like the other two (~(~a) == a,
5215 // -(-a) == a, but (a+1)+1 != a).
5216 if (FVal == 0 && Opcode != ARMISD::CSINC) {
5217 std::swap(TrueVal, FalseVal);
5218 std::swap(TVal, FVal);
5219 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5220 }
5221 if (TVal == 0)
5222 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
5223
5224 // Drops F's value because we can get it by inverting/negating TVal.
5225 FalseVal = TrueVal;
5226
5227 SDValue ARMcc;
5228 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5229 EVT VT = TrueVal.getValueType();
5230 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
5231 }
5232 }
5233
5234 if (isUnsupportedFloatingType(LHS.getValueType())) {
5235 DAG.getTargetLoweringInfo().softenSetCCOperands(
5236 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5237
5238 // If softenSetCCOperands only returned one value, we should compare it to
5239 // zero.
5240 if (!RHS.getNode()) {
5241 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5242 CC = ISD::SETNE;
5243 }
5244 }
5245
5246 if (LHS.getValueType() == MVT::i32) {
5247 // Try to generate VSEL on ARMv8.
5248 // The VSEL instruction can't use all the usual ARM condition
5249 // codes: it only has two bits to select the condition code, so it's
5250 // constrained to use only GE, GT, VS and EQ.
5251 //
5252 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
5253 // swap the operands of the previous compare instruction (effectively
5254 // inverting the compare condition, swapping 'less' and 'greater') and
5255 // sometimes need to swap the operands to the VSEL (which inverts the
5256 // condition in the sense of firing whenever the previous condition didn't)
5257 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5258 TrueVal.getValueType() == MVT::f32 ||
5259 TrueVal.getValueType() == MVT::f64)) {
5260 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5261 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5262 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5263 CC = ISD::getSetCCInverse(CC, LHS.getValueType());
5264 std::swap(TrueVal, FalseVal);
5265 }
5266 }
5267
5268 SDValue ARMcc;
5269 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5270 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5271 // Choose GE over PL, which vsel does now support
5272 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5273 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5274 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5275 }
5276
5277 ARMCC::CondCodes CondCode, CondCode2;
5278 FPCCToARMCC(CC, CondCode, CondCode2);
5279
5280 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5281 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5282 // must use VSEL (limited condition codes), due to not having conditional f16
5283 // moves.
5284 if (Subtarget->hasFPARMv8Base() &&
5285 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5286 (TrueVal.getValueType() == MVT::f16 ||
5287 TrueVal.getValueType() == MVT::f32 ||
5288 TrueVal.getValueType() == MVT::f64)) {
5289 bool swpCmpOps = false;
5290 bool swpVselOps = false;
5291 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5292
5293 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5294 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5295 if (swpCmpOps)
5296 std::swap(LHS, RHS);
5297 if (swpVselOps)
5298 std::swap(TrueVal, FalseVal);
5299 }
5300 }
5301
5302 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5303 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5304 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5305 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5306 if (CondCode2 != ARMCC::AL) {
5307 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5308 // FIXME: Needs another CMP because flag can have but one use.
5309 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5310 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5311 }
5312 return Result;
5313}
5314
5315/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5316/// to morph to an integer compare sequence.
5317static bool canChangeToInt(SDValue Op, bool &SeenZero,
5318 const ARMSubtarget *Subtarget) {
5319 SDNode *N = Op.getNode();
5320 if (!N->hasOneUse())
5321 // Otherwise it requires moving the value from fp to integer registers.
5322 return false;
5323 if (!N->getNumValues())
5324 return false;
5325 EVT VT = Op.getValueType();
5326 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5327 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5328 // vmrs are very slow, e.g. cortex-a8.
5329 return false;
5330
5331 if (isFloatingPointZero(Op)) {
5332 SeenZero = true;
5333 return true;
5334 }
5335 return ISD::isNormalLoad(N);
5336}
5337
5338static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5339 if (isFloatingPointZero(Op))
5340 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5341
5342 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5343 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5344 Ld->getPointerInfo(), Ld->getAlignment(),
5345 Ld->getMemOperand()->getFlags());
5346
5347 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5347)
;
5348}
5349
5350static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5351 SDValue &RetVal1, SDValue &RetVal2) {
5352 SDLoc dl(Op);
5353
5354 if (isFloatingPointZero(Op)) {
5355 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5356 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5357 return;
5358 }
5359
5360 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5361 SDValue Ptr = Ld->getBasePtr();
5362 RetVal1 =
5363 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5364 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5365
5366 EVT PtrType = Ptr.getValueType();
5367 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5368 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5369 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5370 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5371 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5372 Ld->getMemOperand()->getFlags());
5373 return;
5374 }
5375
5376 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5376)
;
5377}
5378
5379/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5380/// f32 and even f64 comparisons to integer ones.
5381SDValue
5382ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5383 SDValue Chain = Op.getOperand(0);
5384 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5385 SDValue LHS = Op.getOperand(2);
5386 SDValue RHS = Op.getOperand(3);
5387 SDValue Dest = Op.getOperand(4);
5388 SDLoc dl(Op);
5389
5390 bool LHSSeenZero = false;
5391 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5392 bool RHSSeenZero = false;
5393 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5394 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5395 // If unsafe fp math optimization is enabled and there are no other uses of
5396 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5397 // to an integer comparison.
5398 if (CC == ISD::SETOEQ)
5399 CC = ISD::SETEQ;
5400 else if (CC == ISD::SETUNE)
5401 CC = ISD::SETNE;
5402
5403 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5404 SDValue ARMcc;
5405 if (LHS.getValueType() == MVT::f32) {
5406 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5407 bitcastf32Toi32(LHS, DAG), Mask);
5408 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5409 bitcastf32Toi32(RHS, DAG), Mask);
5410 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5411 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5412 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5413 Chain, Dest, ARMcc, CCR, Cmp);
5414 }
5415
5416 SDValue LHS1, LHS2;
5417 SDValue RHS1, RHS2;
5418 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5419 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5420 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5421 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5422 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5423 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5424 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5425 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5426 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5427 }
5428
5429 return SDValue();
5430}
5431
5432SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5433 SDValue Chain = Op.getOperand(0);
5434 SDValue Cond = Op.getOperand(1);
5435 SDValue Dest = Op.getOperand(2);
5436 SDLoc dl(Op);
5437
5438 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5439 // instruction.
5440 unsigned Opc = Cond.getOpcode();
5441 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5442 !Subtarget->isThumb1Only();
5443 if (Cond.getResNo() == 1 &&
5444 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5445 Opc == ISD::USUBO || OptimizeMul)) {
5446 // Only lower legal XALUO ops.
5447 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5448 return SDValue();
5449
5450 // The actual operation with overflow check.
5451 SDValue Value, OverflowCmp;
5452 SDValue ARMcc;
5453 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5454
5455 // Reverse the condition code.
5456 ARMCC::CondCodes CondCode =
5457 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5458 CondCode = ARMCC::getOppositeCondition(CondCode);
5459 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5460 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5461
5462 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5463 OverflowCmp);
5464 }
5465
5466 return SDValue();
5467}
5468
5469SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5470 SDValue Chain = Op.getOperand(0);
5471 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5472 SDValue LHS = Op.getOperand(2);
5473 SDValue RHS = Op.getOperand(3);
5474 SDValue Dest = Op.getOperand(4);
5475 SDLoc dl(Op);
5476
5477 if (isUnsupportedFloatingType(LHS.getValueType())) {
5478 DAG.getTargetLoweringInfo().softenSetCCOperands(
5479 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5480
5481 // If softenSetCCOperands only returned one value, we should compare it to
5482 // zero.
5483 if (!RHS.getNode()) {
5484 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5485 CC = ISD::SETNE;
5486 }
5487 }
5488
5489 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5490 // instruction.
5491 unsigned Opc = LHS.getOpcode();
5492 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5493 !Subtarget->isThumb1Only();
5494 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5495 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5496 Opc == ISD::USUBO || OptimizeMul) &&
5497 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5498 // Only lower legal XALUO ops.
5499 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5500 return SDValue();
5501
5502 // The actual operation with overflow check.
5503 SDValue Value, OverflowCmp;
5504 SDValue ARMcc;
5505 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5506
5507 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5508 // Reverse the condition code.
5509 ARMCC::CondCodes CondCode =
5510 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5511 CondCode = ARMCC::getOppositeCondition(CondCode);
5512 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5513 }
5514 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5515
5516 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5517 OverflowCmp);
5518 }
5519
5520 if (LHS.getValueType() == MVT::i32) {
5521 SDValue ARMcc;
5522 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5523 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5524 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5525 Chain, Dest, ARMcc, CCR, Cmp);
5526 }
5527
5528 if (getTargetMachine().Options.UnsafeFPMath &&
5529 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5530 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5531 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5532 return Result;
5533 }
5534
5535 ARMCC::CondCodes CondCode, CondCode2;
5536 FPCCToARMCC(CC, CondCode, CondCode2);
5537
5538 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5539 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5541 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5542 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5543 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5544 if (CondCode2 != ARMCC::AL) {
5545 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5546 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5547 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5548 }
5549 return Res;
5550}
5551
5552SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5553 SDValue Chain = Op.getOperand(0);
5554 SDValue Table = Op.getOperand(1);
5555 SDValue Index = Op.getOperand(2);
5556 SDLoc dl(Op);
5557
5558 EVT PTy = getPointerTy(DAG.getDataLayout());
5559 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5560 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5561 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5562 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5563 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5564 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5565 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5566 // which does another jump to the destination. This also makes it easier
5567 // to translate it to TBB / TBH later (Thumb2 only).
5568 // FIXME: This might not work if the function is extremely large.
5569 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5570 Addr, Op.getOperand(2), JTI);
5571 }
5572 if (isPositionIndependent() || Subtarget->isROPI()) {
5573 Addr =
5574 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5575 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5576 Chain = Addr.getValue(1);
5577 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5578 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5579 } else {
5580 Addr =
5581 DAG.getLoad(PTy, dl, Chain, Addr,
5582 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5583 Chain = Addr.getValue(1);
5584 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5585 }
5586}
5587
5588static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5589 EVT VT = Op.getValueType();
5590 SDLoc dl(Op);
5591
5592 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5593 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5594 return Op;
5595 return DAG.UnrollVectorOp(Op.getNode());
5596 }
5597
5598 const bool HasFullFP16 =
5599 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5600
5601 EVT NewTy;
5602 const EVT OpTy = Op.getOperand(0).getValueType();
5603 if (OpTy == MVT::v4f32)
5604 NewTy = MVT::v4i32;
5605 else if (OpTy == MVT::v4f16 && HasFullFP16)
5606 NewTy = MVT::v4i16;
5607 else if (OpTy == MVT::v8f16 && HasFullFP16)
5608 NewTy = MVT::v8i16;
5609 else
5610 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5610)
;
5611
5612 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5613 return DAG.UnrollVectorOp(Op.getNode());
5614
5615 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5616 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5617}
5618
5619SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5620 EVT VT = Op.getValueType();
5621 if (VT.isVector())
5622 return LowerVectorFP_TO_INT(Op, DAG);
5623
5624 bool IsStrict = Op->isStrictFPOpcode();
5625 SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
5626
5627 if (isUnsupportedFloatingType(SrcVal.getValueType())) {
5628 RTLIB::Libcall LC;
5629 if (Op.getOpcode() == ISD::FP_TO_SINT ||
5630 Op.getOpcode() == ISD::STRICT_FP_TO_SINT)
5631 LC = RTLIB::getFPTOSINT(SrcVal.getValueType(),
5632 Op.getValueType());
5633 else
5634 LC = RTLIB::getFPTOUINT(SrcVal.getValueType(),
5635 Op.getValueType());
5636 SDLoc Loc(Op);
5637 MakeLibCallOptions CallOptions;
5638 SDValue Chain = IsStrict ? Op.getOperand(0) : SDValue();
5639 SDValue Result;
5640 std::tie(Result, Chain) = makeLibCall(DAG, LC, Op.getValueType(), SrcVal,
5641 CallOptions, Loc, Chain);
5642 return IsStrict ? DAG.getMergeValues({Result, Chain}, Loc) : Result;
5643 }
5644
5645 // FIXME: Remove this when we have strict fp instruction selection patterns
5646 if (IsStrict) {
5647 SDLoc Loc(Op);
5648 SDValue Result =
5649 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT
5650 : ISD::FP_TO_UINT,
5651 Loc, Op.getValueType(), SrcVal);
5652 return DAG.getMergeValues({Result, Op.getOperand(0)}, Loc);
5653 }
5654
5655 return Op;
5656}
5657
5658static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5659 EVT VT = Op.getValueType();
5660 SDLoc dl(Op);
5661
5662 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5663 if (VT.getVectorElementType() == MVT::f32)
5664 return Op;
5665 return DAG.UnrollVectorOp(Op.getNode());
5666 }
5667
5668 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5670, __PRETTY_FUNCTION__))
5669 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5670, __PRETTY_FUNCTION__))
5670 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5670, __PRETTY_FUNCTION__))
;
5671
5672 const bool HasFullFP16 =
5673 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5674
5675 EVT DestVecType;
5676 if (VT == MVT::v4f32)
5677 DestVecType = MVT::v4i32;
5678 else if (VT == MVT::v4f16 && HasFullFP16)
5679 DestVecType = MVT::v4i16;
5680 else if (VT == MVT::v8f16 && HasFullFP16)
5681 DestVecType = MVT::v8i16;
5682 else
5683 return DAG.UnrollVectorOp(Op.getNode());
5684
5685 unsigned CastOpc;
5686 unsigned Opc;
5687 switch (Op.getOpcode()) {
5688 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5688)
;
5689 case ISD::SINT_TO_FP:
5690 CastOpc = ISD::SIGN_EXTEND;
5691 Opc = ISD::SINT_TO_FP;
5692 break;
5693 case ISD::UINT_TO_FP:
5694 CastOpc = ISD::ZERO_EXTEND;
5695 Opc = ISD::UINT_TO_FP;
5696 break;
5697 }
5698
5699 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5700 return DAG.getNode(Opc, dl, VT, Op);
5701}
5702
5703SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5704 EVT VT = Op.getValueType();
5705 if (VT.isVector())
5706 return LowerVectorINT_TO_FP(Op, DAG);
5707 if (isUnsupportedFloatingType(VT)) {
5708 RTLIB::Libcall LC;
5709 if (Op.getOpcode() == ISD::SINT_TO_FP)
5710 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5711 Op.getValueType());
5712 else
5713 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5714 Op.getValueType());
5715 MakeLibCallOptions CallOptions;
5716 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5717 CallOptions, SDLoc(Op)).first;
5718 }
5719
5720 return Op;
5721}
5722
5723SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5724 // Implement fcopysign with a fabs and a conditional fneg.
5725 SDValue Tmp0 = Op.getOperand(0);
5726 SDValue Tmp1 = Op.getOperand(1);
5727 SDLoc dl(Op);
5728 EVT VT = Op.getValueType();
5729 EVT SrcVT = Tmp1.getValueType();
5730 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5731 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5732 bool UseNEON = !InGPR && Subtarget->hasNEON();
5733
5734 if (UseNEON) {
5735 // Use VBSL to copy the sign bit.
5736 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5737 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5738 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5739 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5740 if (VT == MVT::f64)
5741 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5742 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5743 DAG.getConstant(32, dl, MVT::i32));
5744 else /*if (VT == MVT::f32)*/
5745 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5746 if (SrcVT == MVT::f32) {
5747 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5748 if (VT == MVT::f64)
5749 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5750 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5751 DAG.getConstant(32, dl, MVT::i32));
5752 } else if (VT == MVT::f32)
5753 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5754 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5755 DAG.getConstant(32, dl, MVT::i32));
5756 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5757 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5758
5759 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5760 dl, MVT::i32);
5761 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5762 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5763 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5764
5765 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5766 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5767 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5768 if (VT == MVT::f32) {
5769 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5770 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5771 DAG.getConstant(0, dl, MVT::i32));
5772 } else {
5773 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5774 }
5775
5776 return Res;
5777 }
5778
5779 // Bitcast operand 1 to i32.
5780 if (SrcVT == MVT::f64)
5781 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5782 Tmp1).getValue(1);
5783 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5784
5785 // Or in the signbit with integer operations.
5786 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5787 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5788 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5789 if (VT == MVT::f32) {
5790 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5791 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5792 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5793 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5794 }
5795
5796 // f64: Or the high part with signbit and then combine two parts.
5797 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5798 Tmp0);
5799 SDValue Lo = Tmp0.getValue(0);
5800 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5801 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5802 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5803}
5804
5805SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5806 MachineFunction &MF = DAG.getMachineFunction();
5807 MachineFrameInfo &MFI = MF.getFrameInfo();
5808 MFI.setReturnAddressIsTaken(true);
5809
5810 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5811 return SDValue();
5812
5813 EVT VT = Op.getValueType();
5814 SDLoc dl(Op);
5815 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5816 if (Depth) {
5817 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5818 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5819 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5820 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5821 MachinePointerInfo());
5822 }
5823
5824 // Return LR, which contains the return address. Mark it an implicit live-in.
5825 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5826 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5827}
5828
5829SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5830 const ARMBaseRegisterInfo &ARI =
5831 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5832 MachineFunction &MF = DAG.getMachineFunction();
5833 MachineFrameInfo &MFI = MF.getFrameInfo();
5834 MFI.setFrameAddressIsTaken(true);
5835
5836 EVT VT = Op.getValueType();
5837 SDLoc dl(Op); // FIXME probably not meaningful
5838 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5839 Register FrameReg = ARI.getFrameRegister(MF);
5840 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5841 while (Depth--)
5842 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5843 MachinePointerInfo());
5844 return FrameAddr;
5845}
5846
5847// FIXME? Maybe this could be a TableGen attribute on some registers and
5848// this table could be generated automatically from RegInfo.
5849Register ARMTargetLowering::getRegisterByName(const char* RegName, LLT VT,
5850 const MachineFunction &MF) const {
5851 Register Reg = StringSwitch<unsigned>(RegName)
5852 .Case("sp", ARM::SP)
5853 .Default(0);
5854 if (Reg)
5855 return Reg;
5856 report_fatal_error(Twine("Invalid register name \""
5857 + StringRef(RegName) + "\"."));
5858}
5859
5860// Result is 64 bit value so split into two 32 bit values and return as a
5861// pair of values.
5862static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5863 SelectionDAG &DAG) {
5864 SDLoc DL(N);
5865
5866 // This function is only supposed to be called for i64 type destination.
5867 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5868, __PRETTY_FUNCTION__))
5868 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5868, __PRETTY_FUNCTION__))
;
5869
5870 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5871 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5872 N->getOperand(0),
5873 N->getOperand(1));
5874
5875 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5876 Read.getValue(1)));
5877 Results.push_back(Read.getOperand(0));
5878}
5879
5880/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5881/// When \p DstVT, the destination type of \p BC, is on the vector
5882/// register bank and the source of bitcast, \p Op, operates on the same bank,
5883/// it might be possible to combine them, such that everything stays on the
5884/// vector register bank.
5885/// \p return The node that would replace \p BT, if the combine
5886/// is possible.
5887static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5888 SelectionDAG &DAG) {
5889 SDValue Op = BC->getOperand(0);
5890 EVT DstVT = BC->getValueType(0);
5891
5892 // The only vector instruction that can produce a scalar (remember,
5893 // since the bitcast was about to be turned into VMOVDRR, the source
5894 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5895 // Moreover, we can do this combine only if there is one use.
5896 // Finally, if the destination type is not a vector, there is not
5897 // much point on forcing everything on the vector bank.
5898 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5899 !Op.hasOneUse())
5900 return SDValue();
5901
5902 // If the index is not constant, we will introduce an additional
5903 // multiply that will stick.
5904 // Give up in that case.
5905 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op