Bug Summary

File:lib/Target/ARM/ARMISelLowering.cpp
Warning:line 7030, column 14
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn325118/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/lib/Target/ARM -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-14-150435-17243-1 -x c++ /build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMISelLowering.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMPerfectShuffle.h"
22#include "ARMRegisterInfo.h"
23#include "ARMSelectionDAGInfo.h"
24#include "ARMSubtarget.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/MachineValueType.h"
57#include "llvm/CodeGen/RuntimeLibcalls.h"
58#include "llvm/CodeGen/SelectionDAG.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/Module.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116
117#define DEBUG_TYPE"arm-isel" "arm-isel"
118
119STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
120STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt", {0}, {false}
}
;
121STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments", {0}, {false
}}
;
122STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
123 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
;
124
125static cl::opt<bool>
126ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
128 cl::init(true));
129
130static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
133 "constant pools"),
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
138 cl::init(64));
139static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142 cl::init(128));
143
144// The APCS parameter registers.
145static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
147};
148
149void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157 }
158
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
169 } else {
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
174 }
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
187 }
188
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197 }
198
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211}
212
213void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216}
217
218void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221}
222
223ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
228
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
239 }
240
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
249 } LibraryCalls[] = {
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303 };
304
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
309 }
310 }
311
312 // Set the correct calling convention for ARMv7k WatchOS. It's just
313 // AAPCS_VFP for functions as simple as libcalls.
314 if (Subtarget->isTargetWatchABI()) {
315 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i)
316 setLibcallCallingConv((RTLIB::Libcall)i, CallingConv::ARM_AAPCS_VFP);
317 }
318 }
319
320 // These libcalls are not available in 32-bit.
321 setLibcallName(RTLIB::SHL_I128, nullptr);
322 setLibcallName(RTLIB::SRL_I128, nullptr);
323 setLibcallName(RTLIB::SRA_I128, nullptr);
324
325 // RTLIB
326 if (Subtarget->isAAPCS_ABI() &&
327 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
328 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
329 static const struct {
330 const RTLIB::Libcall Op;
331 const char * const Name;
332 const CallingConv::ID CC;
333 const ISD::CondCode Cond;
334 } LibraryCalls[] = {
335 // Double-precision floating-point arithmetic helper functions
336 // RTABI chapter 4.1.2, Table 2
337 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341
342 // Double-precision floating-point comparison helper functions
343 // RTABI chapter 4.1.2, Table 3
344 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
345 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
346 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
347 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
348 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
349 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
350 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
351 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
352
353 // Single-precision floating-point arithmetic helper functions
354 // RTABI chapter 4.1.2, Table 4
355 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
356 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
357 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
358 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
359
360 // Single-precision floating-point comparison helper functions
361 // RTABI chapter 4.1.2, Table 5
362 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
363 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
364 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
365 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
366 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
367 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
368 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
369 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
370
371 // Floating-point to integer conversions.
372 // RTABI chapter 4.1.2, Table 6
373 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
375 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
376 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
377 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
381
382 // Conversions between floating types.
383 // RTABI chapter 4.1.2, Table 7
384 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387
388 // Integer to floating-point conversions.
389 // RTABI chapter 4.1.2, Table 8
390 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
392 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
393 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
394 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398
399 // Long long helper functions
400 // RTABI chapter 4.2, Table 9
401 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405
406 // Integer division functions
407 // RTABI chapter 4.3.1
408 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
410 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
411 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
412 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
413 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
414 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
415 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
416 };
417
418 for (const auto &LC : LibraryCalls) {
419 setLibcallName(LC.Op, LC.Name);
420 setLibcallCallingConv(LC.Op, LC.CC);
421 if (LC.Cond != ISD::SETCC_INVALID)
422 setCmpLibcallCC(LC.Op, LC.Cond);
423 }
424
425 // EABI dependent RTLIB
426 if (TM.Options.EABIVersion == EABI::EABI4 ||
427 TM.Options.EABIVersion == EABI::EABI5) {
428 static const struct {
429 const RTLIB::Libcall Op;
430 const char *const Name;
431 const CallingConv::ID CC;
432 const ISD::CondCode Cond;
433 } MemOpsLibraryCalls[] = {
434 // Memory operations
435 // RTABI chapter 4.3.4
436 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
437 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
438 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
439 };
440
441 for (const auto &LC : MemOpsLibraryCalls) {
442 setLibcallName(LC.Op, LC.Name);
443 setLibcallCallingConv(LC.Op, LC.CC);
444 if (LC.Cond != ISD::SETCC_INVALID)
445 setCmpLibcallCC(LC.Op, LC.Cond);
446 }
447 }
448 }
449
450 if (Subtarget->isTargetWindows()) {
451 static const struct {
452 const RTLIB::Libcall Op;
453 const char * const Name;
454 const CallingConv::ID CC;
455 } LibraryCalls[] = {
456 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
457 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
458 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
459 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
460 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
461 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
462 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
463 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
464 };
465
466 for (const auto &LC : LibraryCalls) {
467 setLibcallName(LC.Op, LC.Name);
468 setLibcallCallingConv(LC.Op, LC.CC);
469 }
470 }
471
472 // Use divmod compiler-rt calls for iOS 5.0 and later.
473 if (Subtarget->isTargetMachO() &&
474 !(Subtarget->isTargetIOS() &&
475 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
476 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
477 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
478 }
479
480 // The half <-> float conversion functions are always soft-float on
481 // non-watchos platforms, but are needed for some targets which use a
482 // hard-float calling convention by default.
483 if (!Subtarget->isTargetWatchABI()) {
484 if (Subtarget->isAAPCS_ABI()) {
485 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
486 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
487 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
488 } else {
489 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
490 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
491 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
492 }
493 }
494
495 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
496 // a __gnu_ prefix (which is the default).
497 if (Subtarget->isTargetAEABI()) {
498 static const struct {
499 const RTLIB::Libcall Op;
500 const char * const Name;
501 const CallingConv::ID CC;
502 } LibraryCalls[] = {
503 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
504 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
505 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
506 };
507
508 for (const auto &LC : LibraryCalls) {
509 setLibcallName(LC.Op, LC.Name);
510 setLibcallCallingConv(LC.Op, LC.CC);
511 }
512 }
513
514 if (Subtarget->isThumb1Only())
515 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
516 else
517 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
518
519 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
520 !Subtarget->isThumb1Only()) {
521 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
522 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
523 }
524
525 if (Subtarget->hasFullFP16()) {
526 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
527 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
528 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
529 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
530 }
531
532 for (MVT VT : MVT::vector_valuetypes()) {
533 for (MVT InnerVT : MVT::vector_valuetypes()) {
534 setTruncStoreAction(VT, InnerVT, Expand);
535 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
536 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
537 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
538 }
539
540 setOperationAction(ISD::MULHS, VT, Expand);
541 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
542 setOperationAction(ISD::MULHU, VT, Expand);
543 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
544
545 setOperationAction(ISD::BSWAP, VT, Expand);
546 }
547
548 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
549 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
550
551 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
552 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
553
554 if (Subtarget->hasNEON()) {
555 addDRTypeForNEON(MVT::v2f32);
556 addDRTypeForNEON(MVT::v8i8);
557 addDRTypeForNEON(MVT::v4i16);
558 addDRTypeForNEON(MVT::v2i32);
559 addDRTypeForNEON(MVT::v1i64);
560
561 addQRTypeForNEON(MVT::v4f32);
562 addQRTypeForNEON(MVT::v2f64);
563 addQRTypeForNEON(MVT::v16i8);
564 addQRTypeForNEON(MVT::v8i16);
565 addQRTypeForNEON(MVT::v4i32);
566 addQRTypeForNEON(MVT::v2i64);
567
568 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
569 // neither Neon nor VFP support any arithmetic operations on it.
570 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
571 // supported for v4f32.
572 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
573 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
574 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
575 // FIXME: Code duplication: FDIV and FREM are expanded always, see
576 // ARMTargetLowering::addTypeForNEON method for details.
577 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
578 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
579 // FIXME: Create unittest.
580 // In another words, find a way when "copysign" appears in DAG with vector
581 // operands.
582 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
583 // FIXME: Code duplication: SETCC has custom operation action, see
584 // ARMTargetLowering::addTypeForNEON method for details.
585 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
586 // FIXME: Create unittest for FNEG and for FABS.
587 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
588 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
589 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
590 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
591 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
592 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
593 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
594 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
595 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
596 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
597 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
598 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
599 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
600 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
601 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
602 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
603 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
604 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
605
606 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
607 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
608 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
609 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
610 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
611 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
612 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
613 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
614 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
615 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
616 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
617 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
618 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
619 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
620
621 // Mark v2f32 intrinsics.
622 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
623 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
624 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
625 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
626 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
627 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
628 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
629 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
630 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
631 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
632 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
633 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
634 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
635 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
636
637 // Neon does not support some operations on v1i64 and v2i64 types.
638 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
639 // Custom handling for some quad-vector types to detect VMULL.
640 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
641 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
642 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
643 // Custom handling for some vector types to avoid expensive expansions
644 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
645 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
646 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
647 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
648 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
649 // a destination type that is wider than the source, and nor does
650 // it have a FP_TO_[SU]INT instruction with a narrower destination than
651 // source.
652 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
653 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
654 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
655 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
656
657 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
658 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
659
660 // NEON does not have single instruction CTPOP for vectors with element
661 // types wider than 8-bits. However, custom lowering can leverage the
662 // v8i8/v16i8 vcnt instruction.
663 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
664 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
665 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
666 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
667 setOperationAction(ISD::CTPOP, MVT::v1i64, Expand);
668 setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
669
670 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
671 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
672
673 // NEON does not have single instruction CTTZ for vectors.
674 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
675 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
676 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
677 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
678
679 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
680 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
683
684 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
685 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
686 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
687 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
688
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
693
694 // NEON only has FMA instructions as of VFP4.
695 if (!Subtarget->hasVFP4()) {
696 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
697 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
698 }
699
700 setTargetDAGCombine(ISD::INTRINSIC_VOID);
701 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
702 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
703 setTargetDAGCombine(ISD::SHL);
704 setTargetDAGCombine(ISD::SRL);
705 setTargetDAGCombine(ISD::SRA);
706 setTargetDAGCombine(ISD::SIGN_EXTEND);
707 setTargetDAGCombine(ISD::ZERO_EXTEND);
708 setTargetDAGCombine(ISD::ANY_EXTEND);
709 setTargetDAGCombine(ISD::BUILD_VECTOR);
710 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
711 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
712 setTargetDAGCombine(ISD::STORE);
713 setTargetDAGCombine(ISD::FP_TO_SINT);
714 setTargetDAGCombine(ISD::FP_TO_UINT);
715 setTargetDAGCombine(ISD::FDIV);
716 setTargetDAGCombine(ISD::LOAD);
717
718 // It is legal to extload from v4i8 to v4i16 or v4i32.
719 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
720 MVT::v2i32}) {
721 for (MVT VT : MVT::integer_vector_valuetypes()) {
722 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
723 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
724 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
725 }
726 }
727 }
728
729 if (Subtarget->isFPOnlySP()) {
730 // When targeting a floating-point unit with only single-precision
731 // operations, f64 is legal for the few double-precision instructions which
732 // are present However, no double-precision operations other than moves,
733 // loads and stores are provided by the hardware.
734 setOperationAction(ISD::FADD, MVT::f64, Expand);
735 setOperationAction(ISD::FSUB, MVT::f64, Expand);
736 setOperationAction(ISD::FMUL, MVT::f64, Expand);
737 setOperationAction(ISD::FMA, MVT::f64, Expand);
738 setOperationAction(ISD::FDIV, MVT::f64, Expand);
739 setOperationAction(ISD::FREM, MVT::f64, Expand);
740 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
741 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FNEG, MVT::f64, Expand);
743 setOperationAction(ISD::FABS, MVT::f64, Expand);
744 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
745 setOperationAction(ISD::FSIN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOS, MVT::f64, Expand);
747 setOperationAction(ISD::FPOW, MVT::f64, Expand);
748 setOperationAction(ISD::FLOG, MVT::f64, Expand);
749 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
750 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
751 setOperationAction(ISD::FEXP, MVT::f64, Expand);
752 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
753 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
754 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
755 setOperationAction(ISD::FRINT, MVT::f64, Expand);
756 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
757 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
758 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
759 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
760 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
761 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
762 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
763 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
764 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
765 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
766 }
767
768 computeRegisterProperties(Subtarget->getRegisterInfo());
769
770 // ARM does not have floating-point extending loads.
771 for (MVT VT : MVT::fp_valuetypes()) {
772 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
773 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
774 }
775
776 // ... or truncating stores
777 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
778 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
779 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
780
781 // ARM does not have i1 sign extending load.
782 for (MVT VT : MVT::integer_valuetypes())
783 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
784
785 // ARM supports all 4 flavors of integer indexed load / store.
786 if (!Subtarget->isThumb1Only()) {
787 for (unsigned im = (unsigned)ISD::PRE_INC;
788 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
789 setIndexedLoadAction(im, MVT::i1, Legal);
790 setIndexedLoadAction(im, MVT::i8, Legal);
791 setIndexedLoadAction(im, MVT::i16, Legal);
792 setIndexedLoadAction(im, MVT::i32, Legal);
793 setIndexedStoreAction(im, MVT::i1, Legal);
794 setIndexedStoreAction(im, MVT::i8, Legal);
795 setIndexedStoreAction(im, MVT::i16, Legal);
796 setIndexedStoreAction(im, MVT::i32, Legal);
797 }
798 } else {
799 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
800 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
801 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
802 }
803
804 setOperationAction(ISD::SADDO, MVT::i32, Custom);
805 setOperationAction(ISD::UADDO, MVT::i32, Custom);
806 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
807 setOperationAction(ISD::USUBO, MVT::i32, Custom);
808
809 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
810 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
811
812 // i64 operation support.
813 setOperationAction(ISD::MUL, MVT::i64, Expand);
814 setOperationAction(ISD::MULHU, MVT::i32, Expand);
815 if (Subtarget->isThumb1Only()) {
816 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
817 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
818 }
819 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
820 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
821 setOperationAction(ISD::MULHS, MVT::i32, Expand);
822
823 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
824 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
825 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
826 setOperationAction(ISD::SRL, MVT::i64, Custom);
827 setOperationAction(ISD::SRA, MVT::i64, Custom);
828 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
829
830 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
831 if (Subtarget->isThumb1Only()) {
832 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
833 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
834 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
835 }
836
837 setOperationAction(ISD::ADDC, MVT::i32, Custom);
838 setOperationAction(ISD::ADDE, MVT::i32, Custom);
839 setOperationAction(ISD::SUBC, MVT::i32, Custom);
840 setOperationAction(ISD::SUBE, MVT::i32, Custom);
841
842 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
843 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
844
845 // ARM does not have ROTL.
846 setOperationAction(ISD::ROTL, MVT::i32, Expand);
847 for (MVT VT : MVT::vector_valuetypes()) {
848 setOperationAction(ISD::ROTL, VT, Expand);
849 setOperationAction(ISD::ROTR, VT, Expand);
850 }
851 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
853 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
854 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
855
856 // @llvm.readcyclecounter requires the Performance Monitors extension.
857 // Default to the 0 expansion on unsupported platforms.
858 // FIXME: Technically there are older ARM CPUs that have
859 // implementation-specific ways of obtaining this information.
860 if (Subtarget->hasPerfMon())
861 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
862
863 // Only ARMv6 has BSWAP.
864 if (!Subtarget->hasV6Ops())
865 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
866
867 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
868 : Subtarget->hasDivideInARMMode();
869 if (!hasDivide) {
870 // These are expanded into libcalls if the cpu doesn't have HW divider.
871 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
872 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
873 }
874
875 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
876 setOperationAction(ISD::SDIV, MVT::i32, Custom);
877 setOperationAction(ISD::UDIV, MVT::i32, Custom);
878
879 setOperationAction(ISD::SDIV, MVT::i64, Custom);
880 setOperationAction(ISD::UDIV, MVT::i64, Custom);
881 }
882
883 setOperationAction(ISD::SREM, MVT::i32, Expand);
884 setOperationAction(ISD::UREM, MVT::i32, Expand);
885
886 // Register based DivRem for AEABI (RTABI 4.2)
887 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
888 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
889 Subtarget->isTargetWindows()) {
890 setOperationAction(ISD::SREM, MVT::i64, Custom);
891 setOperationAction(ISD::UREM, MVT::i64, Custom);
892 HasStandaloneRem = false;
893
894 if (Subtarget->isTargetWindows()) {
895 const struct {
896 const RTLIB::Libcall Op;
897 const char * const Name;
898 const CallingConv::ID CC;
899 } LibraryCalls[] = {
900 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
901 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
902 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
903 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
904
905 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
906 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
907 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
908 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
909 };
910
911 for (const auto &LC : LibraryCalls) {
912 setLibcallName(LC.Op, LC.Name);
913 setLibcallCallingConv(LC.Op, LC.CC);
914 }
915 } else {
916 const struct {
917 const RTLIB::Libcall Op;
918 const char * const Name;
919 const CallingConv::ID CC;
920 } LibraryCalls[] = {
921 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
922 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
923 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
924 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
925
926 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
927 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
928 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
929 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
930 };
931
932 for (const auto &LC : LibraryCalls) {
933 setLibcallName(LC.Op, LC.Name);
934 setLibcallCallingConv(LC.Op, LC.CC);
935 }
936 }
937
938 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
939 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
940 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
941 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
942 } else {
943 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
944 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
945 }
946
947 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
948 for (auto &VT : {MVT::f32, MVT::f64})
949 setOperationAction(ISD::FPOWI, VT, Custom);
950
951 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
952 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
953 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
954 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
955
956 setOperationAction(ISD::TRAP, MVT::Other, Legal);
957
958 // Use the default implementation.
959 setOperationAction(ISD::VASTART, MVT::Other, Custom);
960 setOperationAction(ISD::VAARG, MVT::Other, Expand);
961 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
962 setOperationAction(ISD::VAEND, MVT::Other, Expand);
963 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
964 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
965
966 if (Subtarget->isTargetWindows())
967 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
968 else
969 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
970
971 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
972 // the default expansion.
973 InsertFencesForAtomic = false;
974 if (Subtarget->hasAnyDataBarrier() &&
975 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
976 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
977 // to ldrex/strex loops already.
978 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
979 if (!Subtarget->isThumb() || !Subtarget->isMClass())
980 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
981
982 // On v8, we have particularly efficient implementations of atomic fences
983 // if they can be combined with nearby atomic loads and stores.
984 if (!Subtarget->hasV8Ops() || getTargetMachine().getOptLevel() == 0) {
985 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
986 InsertFencesForAtomic = true;
987 }
988 } else {
989 // If there's anything we can use as a barrier, go through custom lowering
990 // for ATOMIC_FENCE.
991 // If target has DMB in thumb, Fences can be inserted.
992 if (Subtarget->hasDataBarrier())
993 InsertFencesForAtomic = true;
994
995 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
996 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
997
998 // Set them all for expansion, which will force libcalls.
999 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1000 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1001 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1002 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1003 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1004 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1007 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1008 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1009 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1010 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1011 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1012 // Unordered/Monotonic case.
1013 if (!InsertFencesForAtomic) {
1014 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1015 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1016 }
1017 }
1018
1019 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1020
1021 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1022 if (!Subtarget->hasV6Ops()) {
1023 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1024 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1025 }
1026 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1027
1028 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1029 !Subtarget->isThumb1Only()) {
1030 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1031 // iff target supports vfp2.
1032 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1033 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1034 }
1035
1036 // We want to custom lower some of our intrinsics.
1037 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1038 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1039 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1040 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1041 if (Subtarget->useSjLjEH())
1042 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1043
1044 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1045 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1046 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1047 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1048 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1049 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1050 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1051 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1052 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1053 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1054
1055 // Thumb-1 cannot currently select ARMISD::SUBE.
1056 if (!Subtarget->isThumb1Only())
1057 setOperationAction(ISD::SETCCE, MVT::i32, Custom);
1058
1059 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1060 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1061 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1062 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1063 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1064
1065 // We don't support sin/cos/fmod/copysign/pow
1066 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1067 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1068 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1069 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1070 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1071 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1072 setOperationAction(ISD::FREM, MVT::f64, Expand);
1073 setOperationAction(ISD::FREM, MVT::f32, Expand);
1074 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1075 !Subtarget->isThumb1Only()) {
1076 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1077 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1078 }
1079 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1080 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1081
1082 if (!Subtarget->hasVFP4()) {
1083 setOperationAction(ISD::FMA, MVT::f64, Expand);
1084 setOperationAction(ISD::FMA, MVT::f32, Expand);
1085 }
1086
1087 // Various VFP goodness
1088 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1089 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1090 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1091 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1092 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1093 }
1094
1095 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1096 if (!Subtarget->hasFP16()) {
1097 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1098 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1099 }
1100 }
1101
1102 // Use __sincos_stret if available.
1103 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1104 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1105 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1106 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1107 }
1108
1109 // FP-ARMv8 implements a lot of rounding-like FP operations.
1110 if (Subtarget->hasFPARMv8()) {
1111 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1112 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1113 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1114 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1115 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1116 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1117 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1118 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1119 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1120 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1121 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1122 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1123
1124 if (!Subtarget->isFPOnlySP()) {
1125 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1126 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1127 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1128 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1129 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1130 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1131 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1132 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1133 }
1134 }
1135
1136 if (Subtarget->hasNEON()) {
1137 // vmin and vmax aren't available in a scalar form, so we use
1138 // a NEON instruction with an undef lane instead.
1139 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1140 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
1141 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1142 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
1143 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
1144 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
1145 }
1146
1147 // We have target-specific dag combine patterns for the following nodes:
1148 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1149 setTargetDAGCombine(ISD::ADD);
1150 setTargetDAGCombine(ISD::SUB);
1151 setTargetDAGCombine(ISD::MUL);
1152 setTargetDAGCombine(ISD::AND);
1153 setTargetDAGCombine(ISD::OR);
1154 setTargetDAGCombine(ISD::XOR);
1155
1156 if (Subtarget->hasV6Ops())
1157 setTargetDAGCombine(ISD::SRL);
1158
1159 setStackPointerRegisterToSaveRestore(ARM::SP);
1160
1161 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1162 !Subtarget->hasVFP2())
1163 setSchedulingPreference(Sched::RegPressure);
1164 else
1165 setSchedulingPreference(Sched::Hybrid);
1166
1167 //// temporary - rewrite interface to use type
1168 MaxStoresPerMemset = 8;
1169 MaxStoresPerMemsetOptSize = 4;
1170 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1171 MaxStoresPerMemcpyOptSize = 2;
1172 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1173 MaxStoresPerMemmoveOptSize = 2;
1174
1175 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1176 // are at least 4 bytes aligned.
1177 setMinStackArgumentAlignment(4);
1178
1179 // Prefer likely predicted branches to selects on out-of-order cores.
1180 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1181
1182 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1183}
1184
1185bool ARMTargetLowering::useSoftFloat() const {
1186 return Subtarget->useSoftFloat();
1187}
1188
1189// FIXME: It might make sense to define the representative register class as the
1190// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1191// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1192// SPR's representative would be DPR_VFP2. This should work well if register
1193// pressure tracking were modified such that a register use would increment the
1194// pressure of the register class's representative and all of it's super
1195// classes' representatives transitively. We have not implemented this because
1196// of the difficulty prior to coalescing of modeling operand register classes
1197// due to the common occurrence of cross class copies and subregister insertions
1198// and extractions.
1199std::pair<const TargetRegisterClass *, uint8_t>
1200ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1201 MVT VT) const {
1202 const TargetRegisterClass *RRC = nullptr;
1203 uint8_t Cost = 1;
1204 switch (VT.SimpleTy) {
1205 default:
1206 return TargetLowering::findRepresentativeClass(TRI, VT);
1207 // Use DPR as representative register class for all floating point
1208 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1209 // the cost is 1 for both f32 and f64.
1210 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1211 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1212 RRC = &ARM::DPRRegClass;
1213 // When NEON is used for SP, only half of the register file is available
1214 // because operations that define both SP and DP results will be constrained
1215 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1216 // coalescing by double-counting the SP regs. See the FIXME above.
1217 if (Subtarget->useNEONForSinglePrecisionFP())
1218 Cost = 2;
1219 break;
1220 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1221 case MVT::v4f32: case MVT::v2f64:
1222 RRC = &ARM::DPRRegClass;
1223 Cost = 2;
1224 break;
1225 case MVT::v4i64:
1226 RRC = &ARM::DPRRegClass;
1227 Cost = 4;
1228 break;
1229 case MVT::v8i64:
1230 RRC = &ARM::DPRRegClass;
1231 Cost = 8;
1232 break;
1233 }
1234 return std::make_pair(RRC, Cost);
1235}
1236
1237const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1238 switch ((ARMISD::NodeType)Opcode) {
1239 case ARMISD::FIRST_NUMBER: break;
1240 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1241 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1242 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1243 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1244 case ARMISD::CALL: return "ARMISD::CALL";
1245 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1246 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1247 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1248 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1249 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1250 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1251 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1252 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1253 case ARMISD::CMP: return "ARMISD::CMP";
1254 case ARMISD::CMN: return "ARMISD::CMN";
1255 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1256 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1257 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1258 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1259 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1260
1261 case ARMISD::CMOV: return "ARMISD::CMOV";
1262
1263 case ARMISD::SSAT: return "ARMISD::SSAT";
1264 case ARMISD::USAT: return "ARMISD::USAT";
1265
1266 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1267 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1268 case ARMISD::RRX: return "ARMISD::RRX";
1269
1270 case ARMISD::ADDC: return "ARMISD::ADDC";
1271 case ARMISD::ADDE: return "ARMISD::ADDE";
1272 case ARMISD::SUBC: return "ARMISD::SUBC";
1273 case ARMISD::SUBE: return "ARMISD::SUBE";
1274
1275 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1276 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1277 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1278 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1279
1280 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1281 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1282 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1283
1284 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1285
1286 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1287
1288 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1289
1290 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1291
1292 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1293
1294 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1295 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1296
1297 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1298 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1299 case ARMISD::VCGE: return "ARMISD::VCGE";
1300 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1301 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1302 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1303 case ARMISD::VCGT: return "ARMISD::VCGT";
1304 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1305 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1306 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1307 case ARMISD::VTST: return "ARMISD::VTST";
1308
1309 case ARMISD::VSHL: return "ARMISD::VSHL";
1310 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1311 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1312 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1313 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1314 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1315 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1316 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1317 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1318 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1319 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1320 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1321 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1322 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1323 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1324 case ARMISD::VSLI: return "ARMISD::VSLI";
1325 case ARMISD::VSRI: return "ARMISD::VSRI";
1326 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1327 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1328 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1329 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1330 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1331 case ARMISD::VDUP: return "ARMISD::VDUP";
1332 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1333 case ARMISD::VEXT: return "ARMISD::VEXT";
1334 case ARMISD::VREV64: return "ARMISD::VREV64";
1335 case ARMISD::VREV32: return "ARMISD::VREV32";
1336 case ARMISD::VREV16: return "ARMISD::VREV16";
1337 case ARMISD::VZIP: return "ARMISD::VZIP";
1338 case ARMISD::VUZP: return "ARMISD::VUZP";
1339 case ARMISD::VTRN: return "ARMISD::VTRN";
1340 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1341 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1342 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1343 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1344 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1345 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1346 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1347 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1348 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1349 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1350 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1351 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1352 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1353 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1354 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1355 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1356 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1357 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1358 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1359 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1360 case ARMISD::BFI: return "ARMISD::BFI";
1361 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1362 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1363 case ARMISD::VBSL: return "ARMISD::VBSL";
1364 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1365 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1366 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1367 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1368 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1369 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1370 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1371 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1372 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1373 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1374 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1375 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1376 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1377 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1378 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1379 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1380 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1381 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1382 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1383 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1384 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1385 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1386 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1387 }
1388 return nullptr;
1389}
1390
1391EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1392 EVT VT) const {
1393 if (!VT.isVector())
1394 return getPointerTy(DL);
1395 return VT.changeVectorElementTypeToInteger();
1396}
1397
1398/// getRegClassFor - Return the register class that should be used for the
1399/// specified value type.
1400const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1401 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1402 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1403 // load / store 4 to 8 consecutive D registers.
1404 if (Subtarget->hasNEON()) {
1405 if (VT == MVT::v4i64)
1406 return &ARM::QQPRRegClass;
1407 if (VT == MVT::v8i64)
1408 return &ARM::QQQQPRRegClass;
1409 }
1410 return TargetLowering::getRegClassFor(VT);
1411}
1412
1413// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1414// source/dest is aligned and the copy size is large enough. We therefore want
1415// to align such objects passed to memory intrinsics.
1416bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1417 unsigned &PrefAlign) const {
1418 if (!isa<MemIntrinsic>(CI))
1419 return false;
1420 MinSize = 8;
1421 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1422 // cycle faster than 4-byte aligned LDM.
1423 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1424 return true;
1425}
1426
1427// Create a fast isel object.
1428FastISel *
1429ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1430 const TargetLibraryInfo *libInfo) const {
1431 return ARM::createFastISel(funcInfo, libInfo);
1432}
1433
1434Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1435 unsigned NumVals = N->getNumValues();
1436 if (!NumVals)
1437 return Sched::RegPressure;
1438
1439 for (unsigned i = 0; i != NumVals; ++i) {
1440 EVT VT = N->getValueType(i);
1441 if (VT == MVT::Glue || VT == MVT::Other)
1442 continue;
1443 if (VT.isFloatingPoint() || VT.isVector())
1444 return Sched::ILP;
1445 }
1446
1447 if (!N->isMachineOpcode())
1448 return Sched::RegPressure;
1449
1450 // Load are scheduled for latency even if there instruction itinerary
1451 // is not available.
1452 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1453 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1454
1455 if (MCID.getNumDefs() == 0)
1456 return Sched::RegPressure;
1457 if (!Itins->isEmpty() &&
1458 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1459 return Sched::ILP;
1460
1461 return Sched::RegPressure;
1462}
1463
1464//===----------------------------------------------------------------------===//
1465// Lowering Code
1466//===----------------------------------------------------------------------===//
1467
1468static bool isSRL16(const SDValue &Op) {
1469 if (Op.getOpcode() != ISD::SRL)
1470 return false;
1471 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1472 return Const->getZExtValue() == 16;
1473 return false;
1474}
1475
1476static bool isSRA16(const SDValue &Op) {
1477 if (Op.getOpcode() != ISD::SRA)
1478 return false;
1479 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1480 return Const->getZExtValue() == 16;
1481 return false;
1482}
1483
1484static bool isSHL16(const SDValue &Op) {
1485 if (Op.getOpcode() != ISD::SHL)
1486 return false;
1487 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1488 return Const->getZExtValue() == 16;
1489 return false;
1490}
1491
1492// Check for a signed 16-bit value. We special case SRA because it makes it
1493// more simple when also looking for SRAs that aren't sign extending a
1494// smaller value. Without the check, we'd need to take extra care with
1495// checking order for some operations.
1496static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1497 if (isSRA16(Op))
1498 return isSHL16(Op.getOperand(0));
1499 return DAG.ComputeNumSignBits(Op) == 17;
1500}
1501
1502/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1503static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1504 switch (CC) {
1505 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1505)
;
1506 case ISD::SETNE: return ARMCC::NE;
1507 case ISD::SETEQ: return ARMCC::EQ;
1508 case ISD::SETGT: return ARMCC::GT;
1509 case ISD::SETGE: return ARMCC::GE;
1510 case ISD::SETLT: return ARMCC::LT;
1511 case ISD::SETLE: return ARMCC::LE;
1512 case ISD::SETUGT: return ARMCC::HI;
1513 case ISD::SETUGE: return ARMCC::HS;
1514 case ISD::SETULT: return ARMCC::LO;
1515 case ISD::SETULE: return ARMCC::LS;
1516 }
1517}
1518
1519/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1520static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1521 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1522 CondCode2 = ARMCC::AL;
1523 InvalidOnQNaN = true;
1524 switch (CC) {
1525 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1525)
;
1526 case ISD::SETEQ:
1527 case ISD::SETOEQ:
1528 CondCode = ARMCC::EQ;
1529 InvalidOnQNaN = false;
1530 break;
1531 case ISD::SETGT:
1532 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1533 case ISD::SETGE:
1534 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1535 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1536 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1537 case ISD::SETONE:
1538 CondCode = ARMCC::MI;
1539 CondCode2 = ARMCC::GT;
1540 InvalidOnQNaN = false;
1541 break;
1542 case ISD::SETO: CondCode = ARMCC::VC; break;
1543 case ISD::SETUO: CondCode = ARMCC::VS; break;
1544 case ISD::SETUEQ:
1545 CondCode = ARMCC::EQ;
1546 CondCode2 = ARMCC::VS;
1547 InvalidOnQNaN = false;
1548 break;
1549 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1550 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1551 case ISD::SETLT:
1552 case ISD::SETULT: CondCode = ARMCC::LT; break;
1553 case ISD::SETLE:
1554 case ISD::SETULE: CondCode = ARMCC::LE; break;
1555 case ISD::SETNE:
1556 case ISD::SETUNE:
1557 CondCode = ARMCC::NE;
1558 InvalidOnQNaN = false;
1559 break;
1560 }
1561}
1562
1563//===----------------------------------------------------------------------===//
1564// Calling Convention Implementation
1565//===----------------------------------------------------------------------===//
1566
1567#include "ARMGenCallingConv.inc"
1568
1569/// getEffectiveCallingConv - Get the effective calling convention, taking into
1570/// account presence of floating point hardware and calling convention
1571/// limitations, such as support for variadic functions.
1572CallingConv::ID
1573ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1574 bool isVarArg) const {
1575 switch (CC) {
1576 default:
1577 report_fatal_error("Unsupported calling convention");
1578 case CallingConv::ARM_AAPCS:
1579 case CallingConv::ARM_APCS:
1580 case CallingConv::GHC:
1581 return CC;
1582 case CallingConv::PreserveMost:
1583 return CallingConv::PreserveMost;
1584 case CallingConv::ARM_AAPCS_VFP:
1585 case CallingConv::Swift:
1586 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1587 case CallingConv::C:
1588 if (!Subtarget->isAAPCS_ABI())
1589 return CallingConv::ARM_APCS;
1590 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1591 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1592 !isVarArg)
1593 return CallingConv::ARM_AAPCS_VFP;
1594 else
1595 return CallingConv::ARM_AAPCS;
1596 case CallingConv::Fast:
1597 case CallingConv::CXX_FAST_TLS:
1598 if (!Subtarget->isAAPCS_ABI()) {
1599 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1600 return CallingConv::Fast;
1601 return CallingConv::ARM_APCS;
1602 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1603 return CallingConv::ARM_AAPCS_VFP;
1604 else
1605 return CallingConv::ARM_AAPCS;
1606 }
1607}
1608
1609CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1610 bool isVarArg) const {
1611 return CCAssignFnForNode(CC, false, isVarArg);
1612}
1613
1614CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1615 bool isVarArg) const {
1616 return CCAssignFnForNode(CC, true, isVarArg);
1617}
1618
1619/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1620/// CallingConvention.
1621CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1622 bool Return,
1623 bool isVarArg) const {
1624 switch (getEffectiveCallingConv(CC, isVarArg)) {
1625 default:
1626 report_fatal_error("Unsupported calling convention");
1627 case CallingConv::ARM_APCS:
1628 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1629 case CallingConv::ARM_AAPCS:
1630 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1631 case CallingConv::ARM_AAPCS_VFP:
1632 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1633 case CallingConv::Fast:
1634 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1635 case CallingConv::GHC:
1636 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1637 case CallingConv::PreserveMost:
1638 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1639 }
1640}
1641
1642/// LowerCallResult - Lower the result values of a call into the
1643/// appropriate copies out of appropriate physical registers.
1644SDValue ARMTargetLowering::LowerCallResult(
1645 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1646 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1647 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1648 SDValue ThisVal) const {
1649 // Assign locations to each value returned by this call.
1650 SmallVector<CCValAssign, 16> RVLocs;
1651 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1652 *DAG.getContext());
1653 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1654
1655 // Copy all of the result registers out of their specified physreg.
1656 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1657 CCValAssign VA = RVLocs[i];
1658
1659 // Pass 'this' value directly from the argument to return value, to avoid
1660 // reg unit interference
1661 if (i == 0 && isThisReturn) {
1662 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1663, __extension__ __PRETTY_FUNCTION__))
1663 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1663, __extension__ __PRETTY_FUNCTION__))
;
1664 InVals.push_back(ThisVal);
1665 continue;
1666 }
1667
1668 SDValue Val;
1669 if (VA.needsCustom()) {
1670 // Handle f64 or half of a v2f64.
1671 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1672 InFlag);
1673 Chain = Lo.getValue(1);
1674 InFlag = Lo.getValue(2);
1675 VA = RVLocs[++i]; // skip ahead to next loc
1676 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1677 InFlag);
1678 Chain = Hi.getValue(1);
1679 InFlag = Hi.getValue(2);
1680 if (!Subtarget->isLittle())
1681 std::swap (Lo, Hi);
1682 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1683
1684 if (VA.getLocVT() == MVT::v2f64) {
1685 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1686 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1687 DAG.getConstant(0, dl, MVT::i32));
1688
1689 VA = RVLocs[++i]; // skip ahead to next loc
1690 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1691 Chain = Lo.getValue(1);
1692 InFlag = Lo.getValue(2);
1693 VA = RVLocs[++i]; // skip ahead to next loc
1694 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1695 Chain = Hi.getValue(1);
1696 InFlag = Hi.getValue(2);
1697 if (!Subtarget->isLittle())
1698 std::swap (Lo, Hi);
1699 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1700 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1701 DAG.getConstant(1, dl, MVT::i32));
1702 }
1703 } else {
1704 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1705 InFlag);
1706 Chain = Val.getValue(1);
1707 InFlag = Val.getValue(2);
1708 }
1709
1710 switch (VA.getLocInfo()) {
1711 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1711)
;
1712 case CCValAssign::Full: break;
1713 case CCValAssign::BCvt:
1714 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1715 break;
1716 }
1717
1718 InVals.push_back(Val);
1719 }
1720
1721 return Chain;
1722}
1723
1724/// LowerMemOpCallTo - Store the argument to the stack.
1725SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1726 SDValue Arg, const SDLoc &dl,
1727 SelectionDAG &DAG,
1728 const CCValAssign &VA,
1729 ISD::ArgFlagsTy Flags) const {
1730 unsigned LocMemOffset = VA.getLocMemOffset();
1731 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1732 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1733 StackPtr, PtrOff);
1734 return DAG.getStore(
1735 Chain, dl, Arg, PtrOff,
1736 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1737}
1738
1739void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1740 SDValue Chain, SDValue &Arg,
1741 RegsToPassVector &RegsToPass,
1742 CCValAssign &VA, CCValAssign &NextVA,
1743 SDValue &StackPtr,
1744 SmallVectorImpl<SDValue> &MemOpChains,
1745 ISD::ArgFlagsTy Flags) const {
1746 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1747 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1748 unsigned id = Subtarget->isLittle() ? 0 : 1;
1749 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1750
1751 if (NextVA.isRegLoc())
1752 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1753 else {
1754 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1754, __extension__ __PRETTY_FUNCTION__))
;
1755 if (!StackPtr.getNode())
1756 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1757 getPointerTy(DAG.getDataLayout()));
1758
1759 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1760 dl, DAG, NextVA,
1761 Flags));
1762 }
1763}
1764
1765/// LowerCall - Lowering a call into a callseq_start <-
1766/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1767/// nodes.
1768SDValue
1769ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1770 SmallVectorImpl<SDValue> &InVals) const {
1771 SelectionDAG &DAG = CLI.DAG;
1772 SDLoc &dl = CLI.DL;
1773 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1774 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1775 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1776 SDValue Chain = CLI.Chain;
1777 SDValue Callee = CLI.Callee;
1778 bool &isTailCall = CLI.IsTailCall;
1779 CallingConv::ID CallConv = CLI.CallConv;
1780 bool doesNotRet = CLI.DoesNotReturn;
1781 bool isVarArg = CLI.IsVarArg;
1782
1783 MachineFunction &MF = DAG.getMachineFunction();
1784 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1785 bool isThisReturn = false;
1786 bool isSibCall = false;
1787 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1788
1789 // Disable tail calls if they're not supported.
1790 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1791 isTailCall = false;
1792
1793 if (isTailCall) {
1794 // Check if it's really possible to do a tail call.
1795 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1796 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1797 Outs, OutVals, Ins, DAG);
1798 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1799 report_fatal_error("failed to perform tail call elimination on a call "
1800 "site marked musttail");
1801 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1802 // detected sibcalls.
1803 if (isTailCall) {
1804 ++NumTailCalls;
1805 isSibCall = true;
1806 }
1807 }
1808
1809 // Analyze operands of the call, assigning locations to each operand.
1810 SmallVector<CCValAssign, 16> ArgLocs;
1811 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1812 *DAG.getContext());
1813 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1814
1815 // Get a count of how many bytes are to be pushed on the stack.
1816 unsigned NumBytes = CCInfo.getNextStackOffset();
1817
1818 // For tail calls, memory operands are available in our caller's stack.
1819 if (isSibCall)
1820 NumBytes = 0;
1821
1822 // Adjust the stack pointer for the new arguments...
1823 // These operations are automatically eliminated by the prolog/epilog pass
1824 if (!isSibCall)
1825 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1826
1827 SDValue StackPtr =
1828 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1829
1830 RegsToPassVector RegsToPass;
1831 SmallVector<SDValue, 8> MemOpChains;
1832
1833 // Walk the register/memloc assignments, inserting copies/loads. In the case
1834 // of tail call optimization, arguments are handled later.
1835 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1836 i != e;
1837 ++i, ++realArgIdx) {
1838 CCValAssign &VA = ArgLocs[i];
1839 SDValue Arg = OutVals[realArgIdx];
1840 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1841 bool isByVal = Flags.isByVal();
1842
1843 // Promote the value if needed.
1844 switch (VA.getLocInfo()) {
1845 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1845)
;
1846 case CCValAssign::Full: break;
1847 case CCValAssign::SExt:
1848 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1849 break;
1850 case CCValAssign::ZExt:
1851 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1852 break;
1853 case CCValAssign::AExt:
1854 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1855 break;
1856 case CCValAssign::BCvt:
1857 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1858 break;
1859 }
1860
1861 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1862 if (VA.needsCustom()) {
1863 if (VA.getLocVT() == MVT::v2f64) {
1864 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1865 DAG.getConstant(0, dl, MVT::i32));
1866 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1867 DAG.getConstant(1, dl, MVT::i32));
1868
1869 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1870 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1871
1872 VA = ArgLocs[++i]; // skip ahead to next loc
1873 if (VA.isRegLoc()) {
1874 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1875 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1876 } else {
1877 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1877, __extension__ __PRETTY_FUNCTION__))
;
1878
1879 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1880 dl, DAG, VA, Flags));
1881 }
1882 } else {
1883 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1884 StackPtr, MemOpChains, Flags);
1885 }
1886 } else if (VA.isRegLoc()) {
1887 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1888 Outs[0].VT == MVT::i32) {
1889 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1890, __extension__ __PRETTY_FUNCTION__))
1890 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1890, __extension__ __PRETTY_FUNCTION__))
;
1891 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1892, __extension__ __PRETTY_FUNCTION__))
1892 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1892, __extension__ __PRETTY_FUNCTION__))
;
1893 isThisReturn = true;
1894 }
1895 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1896 } else if (isByVal) {
1897 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1897, __extension__ __PRETTY_FUNCTION__))
;
1898 unsigned offset = 0;
1899
1900 // True if this byval aggregate will be split between registers
1901 // and memory.
1902 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1903 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1904
1905 if (CurByValIdx < ByValArgsCount) {
1906
1907 unsigned RegBegin, RegEnd;
1908 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1909
1910 EVT PtrVT =
1911 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1912 unsigned int i, j;
1913 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1914 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1915 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1916 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1917 MachinePointerInfo(),
1918 DAG.InferPtrAlignment(AddArg));
1919 MemOpChains.push_back(Load.getValue(1));
1920 RegsToPass.push_back(std::make_pair(j, Load));
1921 }
1922
1923 // If parameter size outsides register area, "offset" value
1924 // helps us to calculate stack slot for remained part properly.
1925 offset = RegEnd - RegBegin;
1926
1927 CCInfo.nextInRegsParam();
1928 }
1929
1930 if (Flags.getByValSize() > 4*offset) {
1931 auto PtrVT = getPointerTy(DAG.getDataLayout());
1932 unsigned LocMemOffset = VA.getLocMemOffset();
1933 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1934 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1935 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1936 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1937 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1938 MVT::i32);
1939 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1940 MVT::i32);
1941
1942 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1943 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1944 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1945 Ops));
1946 }
1947 } else if (!isSibCall) {
1948 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 1948, __extension__ __PRETTY_FUNCTION__))
;
1949
1950 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1951 dl, DAG, VA, Flags));
1952 }
1953 }
1954
1955 if (!MemOpChains.empty())
1956 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1957
1958 // Build a sequence of copy-to-reg nodes chained together with token chain
1959 // and flag operands which copy the outgoing args into the appropriate regs.
1960 SDValue InFlag;
1961 // Tail call byval lowering might overwrite argument registers so in case of
1962 // tail call optimization the copies to registers are lowered later.
1963 if (!isTailCall)
1964 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1965 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1966 RegsToPass[i].second, InFlag);
1967 InFlag = Chain.getValue(1);
1968 }
1969
1970 // For tail calls lower the arguments to the 'real' stack slot.
1971 if (isTailCall) {
1972 // Force all the incoming stack arguments to be loaded from the stack
1973 // before any new outgoing arguments are stored to the stack, because the
1974 // outgoing stack slots may alias the incoming argument stack slots, and
1975 // the alias isn't otherwise explicit. This is slightly more conservative
1976 // than necessary, because it means that each store effectively depends
1977 // on every argument instead of just those arguments it would clobber.
1978
1979 // Do not flag preceding copytoreg stuff together with the following stuff.
1980 InFlag = SDValue();
1981 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1982 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1983 RegsToPass[i].second, InFlag);
1984 InFlag = Chain.getValue(1);
1985 }
1986 InFlag = SDValue();
1987 }
1988
1989 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1990 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1991 // node so that legalize doesn't hack it.
1992 bool isDirect = false;
1993
1994 const TargetMachine &TM = getTargetMachine();
1995 const Module *Mod = MF.getFunction().getParent();
1996 const GlobalValue *GV = nullptr;
1997 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1998 GV = G->getGlobal();
1999 bool isStub =
2000 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2001
2002 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2003 bool isLocalARMFunc = false;
2004 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2005 auto PtrVt = getPointerTy(DAG.getDataLayout());
2006
2007 if (Subtarget->genLongCalls()) {
2008 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2009, __extension__ __PRETTY_FUNCTION__))
2009 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2009, __extension__ __PRETTY_FUNCTION__))
;
2010 // Handle a global address or an external symbol. If it's not one of
2011 // those, the target's already in a register, so we don't need to do
2012 // anything extra.
2013 if (isa<GlobalAddressSDNode>(Callee)) {
2014 // Create a constant pool entry for the callee address
2015 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2016 ARMConstantPoolValue *CPV =
2017 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2018
2019 // Get the address of the callee into a register
2020 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2021 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2022 Callee = DAG.getLoad(
2023 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2024 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2025 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2026 const char *Sym = S->getSymbol();
2027
2028 // Create a constant pool entry for the callee address
2029 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2030 ARMConstantPoolValue *CPV =
2031 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2032 ARMPCLabelIndex, 0);
2033 // Get the address of the callee into a register
2034 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2035 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2036 Callee = DAG.getLoad(
2037 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2038 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2039 }
2040 } else if (isa<GlobalAddressSDNode>(Callee)) {
2041 // If we're optimizing for minimum size and the function is called three or
2042 // more times in this block, we can improve codesize by calling indirectly
2043 // as BLXr has a 16-bit encoding.
2044 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2045 auto *BB = CLI.CS.getParent();
2046 bool PreferIndirect =
2047 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2048 count_if(GV->users(), [&BB](const User *U) {
2049 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2050 }) > 2;
2051
2052 if (!PreferIndirect) {
2053 isDirect = true;
2054 bool isDef = GV->isStrongDefinitionForLinker();
2055
2056 // ARM call to a local ARM function is predicable.
2057 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2058 // tBX takes a register source operand.
2059 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2060 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2060, __extension__ __PRETTY_FUNCTION__))
;
2061 Callee = DAG.getNode(
2062 ARMISD::WrapperPIC, dl, PtrVt,
2063 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2064 Callee = DAG.getLoad(
2065 PtrVt, dl, DAG.getEntryNode(), Callee,
2066 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2067 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2068 MachineMemOperand::MOInvariant);
2069 } else if (Subtarget->isTargetCOFF()) {
2070 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2071, __extension__ __PRETTY_FUNCTION__))
2071 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2071, __extension__ __PRETTY_FUNCTION__))
;
2072 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2073 ? ARMII::MO_DLLIMPORT
2074 : ARMII::MO_NO_FLAG;
2075 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2076 TargetFlags);
2077 if (GV->hasDLLImportStorageClass())
2078 Callee =
2079 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2080 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2081 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2082 } else {
2083 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2084 }
2085 }
2086 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2087 isDirect = true;
2088 // tBX takes a register source operand.
2089 const char *Sym = S->getSymbol();
2090 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2091 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2092 ARMConstantPoolValue *CPV =
2093 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2094 ARMPCLabelIndex, 4);
2095 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2096 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2097 Callee = DAG.getLoad(
2098 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2099 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2100 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2101 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2102 } else {
2103 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2104 }
2105 }
2106
2107 // FIXME: handle tail calls differently.
2108 unsigned CallOpc;
2109 if (Subtarget->isThumb()) {
2110 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2111 CallOpc = ARMISD::CALL_NOLINK;
2112 else
2113 CallOpc = ARMISD::CALL;
2114 } else {
2115 if (!isDirect && !Subtarget->hasV5TOps())
2116 CallOpc = ARMISD::CALL_NOLINK;
2117 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2118 // Emit regular call when code size is the priority
2119 !MF.getFunction().optForMinSize())
2120 // "mov lr, pc; b _foo" to avoid confusing the RSP
2121 CallOpc = ARMISD::CALL_NOLINK;
2122 else
2123 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2124 }
2125
2126 std::vector<SDValue> Ops;
2127 Ops.push_back(Chain);
2128 Ops.push_back(Callee);
2129
2130 // Add argument registers to the end of the list so that they are known live
2131 // into the call.
2132 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2133 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2134 RegsToPass[i].second.getValueType()));
2135
2136 // Add a register mask operand representing the call-preserved registers.
2137 if (!isTailCall) {
2138 const uint32_t *Mask;
2139 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2140 if (isThisReturn) {
2141 // For 'this' returns, use the R0-preserving mask if applicable
2142 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2143 if (!Mask) {
2144 // Set isThisReturn to false if the calling convention is not one that
2145 // allows 'returned' to be modeled in this way, so LowerCallResult does
2146 // not try to pass 'this' straight through
2147 isThisReturn = false;
2148 Mask = ARI->getCallPreservedMask(MF, CallConv);
2149 }
2150 } else
2151 Mask = ARI->getCallPreservedMask(MF, CallConv);
2152
2153 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2153, __extension__ __PRETTY_FUNCTION__))
;
2154 Ops.push_back(DAG.getRegisterMask(Mask));
2155 }
2156
2157 if (InFlag.getNode())
2158 Ops.push_back(InFlag);
2159
2160 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2161 if (isTailCall) {
2162 MF.getFrameInfo().setHasTailCall();
2163 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2164 }
2165
2166 // Returns a chain and a flag for retval copy to use.
2167 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2168 InFlag = Chain.getValue(1);
2169
2170 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2171 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2172 if (!Ins.empty())
2173 InFlag = Chain.getValue(1);
2174
2175 // Handle result values, copying them out of physregs into vregs that we
2176 // return.
2177 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2178 InVals, isThisReturn,
2179 isThisReturn ? OutVals[0] : SDValue());
2180}
2181
2182/// HandleByVal - Every parameter *after* a byval parameter is passed
2183/// on the stack. Remember the next parameter register to allocate,
2184/// and then confiscate the rest of the parameter registers to insure
2185/// this.
2186void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2187 unsigned Align) const {
2188 // Byval (as with any stack) slots are always at least 4 byte aligned.
2189 Align = std::max(Align, 4U);
2190
2191 unsigned Reg = State->AllocateReg(GPRArgRegs);
2192 if (!Reg)
2193 return;
2194
2195 unsigned AlignInRegs = Align / 4;
2196 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2197 for (unsigned i = 0; i < Waste; ++i)
2198 Reg = State->AllocateReg(GPRArgRegs);
2199
2200 if (!Reg)
2201 return;
2202
2203 unsigned Excess = 4 * (ARM::R4 - Reg);
2204
2205 // Special case when NSAA != SP and parameter size greater than size of
2206 // all remained GPR regs. In that case we can't split parameter, we must
2207 // send it to stack. We also must set NCRN to R4, so waste all
2208 // remained registers.
2209 const unsigned NSAAOffset = State->getNextStackOffset();
2210 if (NSAAOffset != 0 && Size > Excess) {
2211 while (State->AllocateReg(GPRArgRegs))
2212 ;
2213 return;
2214 }
2215
2216 // First register for byval parameter is the first register that wasn't
2217 // allocated before this method call, so it would be "reg".
2218 // If parameter is small enough to be saved in range [reg, r4), then
2219 // the end (first after last) register would be reg + param-size-in-regs,
2220 // else parameter would be splitted between registers and stack,
2221 // end register would be r4 in this case.
2222 unsigned ByValRegBegin = Reg;
2223 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2224 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2225 // Note, first register is allocated in the beginning of function already,
2226 // allocate remained amount of registers we need.
2227 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2228 State->AllocateReg(GPRArgRegs);
2229 // A byval parameter that is split between registers and memory needs its
2230 // size truncated here.
2231 // In the case where the entire structure fits in registers, we set the
2232 // size in memory to zero.
2233 Size = std::max<int>(Size - Excess, 0);
2234}
2235
2236/// MatchingStackOffset - Return true if the given stack call argument is
2237/// already available in the same position (relatively) of the caller's
2238/// incoming argument stack.
2239static
2240bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2241 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2242 const TargetInstrInfo *TII) {
2243 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2244 int FI = std::numeric_limits<int>::max();
2245 if (Arg.getOpcode() == ISD::CopyFromReg) {
2246 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2247 if (!TargetRegisterInfo::isVirtualRegister(VR))
2248 return false;
2249 MachineInstr *Def = MRI->getVRegDef(VR);
2250 if (!Def)
2251 return false;
2252 if (!Flags.isByVal()) {
2253 if (!TII->isLoadFromStackSlot(*Def, FI))
2254 return false;
2255 } else {
2256 return false;
2257 }
2258 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2259 if (Flags.isByVal())
2260 // ByVal argument is passed in as a pointer but it's now being
2261 // dereferenced. e.g.
2262 // define @foo(%struct.X* %A) {
2263 // tail call @bar(%struct.X* byval %A)
2264 // }
2265 return false;
2266 SDValue Ptr = Ld->getBasePtr();
2267 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2268 if (!FINode)
2269 return false;
2270 FI = FINode->getIndex();
2271 } else
2272 return false;
2273
2274 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2274, __extension__ __PRETTY_FUNCTION__))
;
2275 if (!MFI.isFixedObjectIndex(FI))
2276 return false;
2277 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2278}
2279
2280/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2281/// for tail call optimization. Targets which want to do tail call
2282/// optimization should implement this function.
2283bool
2284ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2285 CallingConv::ID CalleeCC,
2286 bool isVarArg,
2287 bool isCalleeStructRet,
2288 bool isCallerStructRet,
2289 const SmallVectorImpl<ISD::OutputArg> &Outs,
2290 const SmallVectorImpl<SDValue> &OutVals,
2291 const SmallVectorImpl<ISD::InputArg> &Ins,
2292 SelectionDAG& DAG) const {
2293 MachineFunction &MF = DAG.getMachineFunction();
2294 const Function &CallerF = MF.getFunction();
2295 CallingConv::ID CallerCC = CallerF.getCallingConv();
2296
2297 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2297, __extension__ __PRETTY_FUNCTION__))
;
2298
2299 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2300 // to the call take up r0-r3. The reason is that there are no legal registers
2301 // left to hold the pointer to the function to be called.
2302 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2303 !isa<GlobalAddressSDNode>(Callee.getNode()))
2304 return false;
2305
2306 // Look for obvious safe cases to perform tail call optimization that do not
2307 // require ABI changes. This is what gcc calls sibcall.
2308
2309 // Exception-handling functions need a special set of instructions to indicate
2310 // a return to the hardware. Tail-calling another function would probably
2311 // break this.
2312 if (CallerF.hasFnAttribute("interrupt"))
2313 return false;
2314
2315 // Also avoid sibcall optimization if either caller or callee uses struct
2316 // return semantics.
2317 if (isCalleeStructRet || isCallerStructRet)
2318 return false;
2319
2320 // Externally-defined functions with weak linkage should not be
2321 // tail-called on ARM when the OS does not support dynamic
2322 // pre-emption of symbols, as the AAELF spec requires normal calls
2323 // to undefined weak functions to be replaced with a NOP or jump to the
2324 // next instruction. The behaviour of branch instructions in this
2325 // situation (as used for tail calls) is implementation-defined, so we
2326 // cannot rely on the linker replacing the tail call with a return.
2327 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2328 const GlobalValue *GV = G->getGlobal();
2329 const Triple &TT = getTargetMachine().getTargetTriple();
2330 if (GV->hasExternalWeakLinkage() &&
2331 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2332 return false;
2333 }
2334
2335 // Check that the call results are passed in the same way.
2336 LLVMContext &C = *DAG.getContext();
2337 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2338 CCAssignFnForReturn(CalleeCC, isVarArg),
2339 CCAssignFnForReturn(CallerCC, isVarArg)))
2340 return false;
2341 // The callee has to preserve all registers the caller needs to preserve.
2342 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2343 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2344 if (CalleeCC != CallerCC) {
2345 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2346 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2347 return false;
2348 }
2349
2350 // If Caller's vararg or byval argument has been split between registers and
2351 // stack, do not perform tail call, since part of the argument is in caller's
2352 // local frame.
2353 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2354 if (AFI_Caller->getArgRegsSaveSize())
2355 return false;
2356
2357 // If the callee takes no arguments then go on to check the results of the
2358 // call.
2359 if (!Outs.empty()) {
2360 // Check if stack adjustment is needed. For now, do not do this if any
2361 // argument is passed on the stack.
2362 SmallVector<CCValAssign, 16> ArgLocs;
2363 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2364 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2365 if (CCInfo.getNextStackOffset()) {
2366 // Check if the arguments are already laid out in the right way as
2367 // the caller's fixed stack objects.
2368 MachineFrameInfo &MFI = MF.getFrameInfo();
2369 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2370 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2371 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2372 i != e;
2373 ++i, ++realArgIdx) {
2374 CCValAssign &VA = ArgLocs[i];
2375 EVT RegVT = VA.getLocVT();
2376 SDValue Arg = OutVals[realArgIdx];
2377 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2378 if (VA.getLocInfo() == CCValAssign::Indirect)
2379 return false;
2380 if (VA.needsCustom()) {
2381 // f64 and vector types are split into multiple registers or
2382 // register/stack-slot combinations. The types will not match
2383 // the registers; give up on memory f64 refs until we figure
2384 // out what to do about this.
2385 if (!VA.isRegLoc())
2386 return false;
2387 if (!ArgLocs[++i].isRegLoc())
2388 return false;
2389 if (RegVT == MVT::v2f64) {
2390 if (!ArgLocs[++i].isRegLoc())
2391 return false;
2392 if (!ArgLocs[++i].isRegLoc())
2393 return false;
2394 }
2395 } else if (!VA.isRegLoc()) {
2396 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2397 MFI, MRI, TII))
2398 return false;
2399 }
2400 }
2401 }
2402
2403 const MachineRegisterInfo &MRI = MF.getRegInfo();
2404 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2405 return false;
2406 }
2407
2408 return true;
2409}
2410
2411bool
2412ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2413 MachineFunction &MF, bool isVarArg,
2414 const SmallVectorImpl<ISD::OutputArg> &Outs,
2415 LLVMContext &Context) const {
2416 SmallVector<CCValAssign, 16> RVLocs;
2417 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2418 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2419}
2420
2421static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2422 const SDLoc &DL, SelectionDAG &DAG) {
2423 const MachineFunction &MF = DAG.getMachineFunction();
2424 const Function &F = MF.getFunction();
2425
2426 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2427
2428 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2429 // version of the "preferred return address". These offsets affect the return
2430 // instruction if this is a return from PL1 without hypervisor extensions.
2431 // IRQ/FIQ: +4 "subs pc, lr, #4"
2432 // SWI: 0 "subs pc, lr, #0"
2433 // ABORT: +4 "subs pc, lr, #4"
2434 // UNDEF: +4/+2 "subs pc, lr, #0"
2435 // UNDEF varies depending on where the exception came from ARM or Thumb
2436 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2437
2438 int64_t LROffset;
2439 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2440 IntKind == "ABORT")
2441 LROffset = 4;
2442 else if (IntKind == "SWI" || IntKind == "UNDEF")
2443 LROffset = 0;
2444 else
2445 report_fatal_error("Unsupported interrupt attribute. If present, value "
2446 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2447
2448 RetOps.insert(RetOps.begin() + 1,
2449 DAG.getConstant(LROffset, DL, MVT::i32, false));
2450
2451 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2452}
2453
2454SDValue
2455ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2456 bool isVarArg,
2457 const SmallVectorImpl<ISD::OutputArg> &Outs,
2458 const SmallVectorImpl<SDValue> &OutVals,
2459 const SDLoc &dl, SelectionDAG &DAG) const {
2460 // CCValAssign - represent the assignment of the return value to a location.
2461 SmallVector<CCValAssign, 16> RVLocs;
2462
2463 // CCState - Info about the registers and stack slots.
2464 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2465 *DAG.getContext());
2466
2467 // Analyze outgoing return values.
2468 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2469
2470 SDValue Flag;
2471 SmallVector<SDValue, 4> RetOps;
2472 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2473 bool isLittleEndian = Subtarget->isLittle();
2474
2475 MachineFunction &MF = DAG.getMachineFunction();
2476 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2477 AFI->setReturnRegsCount(RVLocs.size());
2478
2479 // Copy the result values into the output registers.
2480 for (unsigned i = 0, realRVLocIdx = 0;
2481 i != RVLocs.size();
2482 ++i, ++realRVLocIdx) {
2483 CCValAssign &VA = RVLocs[i];
2484 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2484, __extension__ __PRETTY_FUNCTION__))
;
2485
2486 SDValue Arg = OutVals[realRVLocIdx];
2487 bool ReturnF16 = false;
2488
2489 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2490 // Half-precision return values can be returned like this:
2491 //
2492 // t11 f16 = fadd ...
2493 // t12: i16 = bitcast t11
2494 // t13: i32 = zero_extend t12
2495 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2496 //
2497 // to avoid code generation for bitcasts, we simply set Arg to the node
2498 // that produces the f16 value, t11 in this case.
2499 //
2500 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2501 SDValue ZE = Arg.getOperand(0);
2502 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2503 SDValue BC = ZE.getOperand(0);
2504 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2505 Arg = BC.getOperand(0);
2506 ReturnF16 = true;
2507 }
2508 }
2509 }
2510 }
2511
2512 switch (VA.getLocInfo()) {
2513 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2513)
;
2514 case CCValAssign::Full: break;
2515 case CCValAssign::BCvt:
2516 if (!ReturnF16)
2517 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2518 break;
2519 }
2520
2521 if (VA.needsCustom()) {
2522 if (VA.getLocVT() == MVT::v2f64) {
2523 // Extract the first half and return it in two registers.
2524 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2525 DAG.getConstant(0, dl, MVT::i32));
2526 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2527 DAG.getVTList(MVT::i32, MVT::i32), Half);
2528
2529 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2530 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2531 Flag);
2532 Flag = Chain.getValue(1);
2533 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2534 VA = RVLocs[++i]; // skip ahead to next loc
2535 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2536 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2537 Flag);
2538 Flag = Chain.getValue(1);
2539 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2540 VA = RVLocs[++i]; // skip ahead to next loc
2541
2542 // Extract the 2nd half and fall through to handle it as an f64 value.
2543 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2544 DAG.getConstant(1, dl, MVT::i32));
2545 }
2546 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2547 // available.
2548 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2549 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2550 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2551 fmrrd.getValue(isLittleEndian ? 0 : 1),
2552 Flag);
2553 Flag = Chain.getValue(1);
2554 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2555 VA = RVLocs[++i]; // skip ahead to next loc
2556 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2557 fmrrd.getValue(isLittleEndian ? 1 : 0),
2558 Flag);
2559 } else
2560 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2561
2562 // Guarantee that all emitted copies are
2563 // stuck together, avoiding something bad.
2564 Flag = Chain.getValue(1);
2565 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2566 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2567 }
2568 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2569 const MCPhysReg *I =
2570 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2571 if (I) {
2572 for (; *I; ++I) {
2573 if (ARM::GPRRegClass.contains(*I))
2574 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2575 else if (ARM::DPRRegClass.contains(*I))
2576 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2577 else
2578 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2578)
;
2579 }
2580 }
2581
2582 // Update chain and glue.
2583 RetOps[0] = Chain;
2584 if (Flag.getNode())
2585 RetOps.push_back(Flag);
2586
2587 // CPUs which aren't M-class use a special sequence to return from
2588 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2589 // though we use "subs pc, lr, #N").
2590 //
2591 // M-class CPUs actually use a normal return sequence with a special
2592 // (hardware-provided) value in LR, so the normal code path works.
2593 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2594 !Subtarget->isMClass()) {
2595 if (Subtarget->isThumb1Only())
2596 report_fatal_error("interrupt attribute is not supported in Thumb1");
2597 return LowerInterruptReturn(RetOps, dl, DAG);
2598 }
2599
2600 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2601}
2602
2603bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2604 if (N->getNumValues() != 1)
2605 return false;
2606 if (!N->hasNUsesOfValue(1, 0))
2607 return false;
2608
2609 SDValue TCChain = Chain;
2610 SDNode *Copy = *N->use_begin();
2611 if (Copy->getOpcode() == ISD::CopyToReg) {
2612 // If the copy has a glue operand, we conservatively assume it isn't safe to
2613 // perform a tail call.
2614 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2615 return false;
2616 TCChain = Copy->getOperand(0);
2617 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2618 SDNode *VMov = Copy;
2619 // f64 returned in a pair of GPRs.
2620 SmallPtrSet<SDNode*, 2> Copies;
2621 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2622 UI != UE; ++UI) {
2623 if (UI->getOpcode() != ISD::CopyToReg)
2624 return false;
2625 Copies.insert(*UI);
2626 }
2627 if (Copies.size() > 2)
2628 return false;
2629
2630 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2631 UI != UE; ++UI) {
2632 SDValue UseChain = UI->getOperand(0);
2633 if (Copies.count(UseChain.getNode()))
2634 // Second CopyToReg
2635 Copy = *UI;
2636 else {
2637 // We are at the top of this chain.
2638 // If the copy has a glue operand, we conservatively assume it
2639 // isn't safe to perform a tail call.
2640 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2641 return false;
2642 // First CopyToReg
2643 TCChain = UseChain;
2644 }
2645 }
2646 } else if (Copy->getOpcode() == ISD::BITCAST) {
2647 // f32 returned in a single GPR.
2648 if (!Copy->hasOneUse())
2649 return false;
2650 Copy = *Copy->use_begin();
2651 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2652 return false;
2653 // If the copy has a glue operand, we conservatively assume it isn't safe to
2654 // perform a tail call.
2655 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2656 return false;
2657 TCChain = Copy->getOperand(0);
2658 } else {
2659 return false;
2660 }
2661
2662 bool HasRet = false;
2663 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2664 UI != UE; ++UI) {
2665 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2666 UI->getOpcode() != ARMISD::INTRET_FLAG)
2667 return false;
2668 HasRet = true;
2669 }
2670
2671 if (!HasRet)
2672 return false;
2673
2674 Chain = TCChain;
2675 return true;
2676}
2677
2678bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2679 if (!Subtarget->supportsTailCall())
2680 return false;
2681
2682 auto Attr =
2683 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2684 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2685 return false;
2686
2687 return true;
2688}
2689
2690// Trying to write a 64 bit value so need to split into two 32 bit values first,
2691// and pass the lower and high parts through.
2692static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2693 SDLoc DL(Op);
2694 SDValue WriteValue = Op->getOperand(2);
2695
2696 // This function is only supposed to be called for i64 type argument.
2697 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2698, __extension__ __PRETTY_FUNCTION__))
2698 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2698, __extension__ __PRETTY_FUNCTION__))
;
2699
2700 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2701 DAG.getConstant(0, DL, MVT::i32));
2702 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2703 DAG.getConstant(1, DL, MVT::i32));
2704 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2705 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2706}
2707
2708// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2709// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2710// one of the above mentioned nodes. It has to be wrapped because otherwise
2711// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2712// be used to form addressing mode. These wrapped nodes will be selected
2713// into MOVi.
2714SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2715 SelectionDAG &DAG) const {
2716 EVT PtrVT = Op.getValueType();
2717 // FIXME there is no actual debug info here
2718 SDLoc dl(Op);
2719 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2720 SDValue Res;
2721
2722 // When generating execute-only code Constant Pools must be promoted to the
2723 // global data section. It's a bit ugly that we can't share them across basic
2724 // blocks, but this way we guarantee that execute-only behaves correct with
2725 // position-independent addressing modes.
2726 if (Subtarget->genExecuteOnly()) {
2727 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2728 auto T = const_cast<Type*>(CP->getType());
2729 auto C = const_cast<Constant*>(CP->getConstVal());
2730 auto M = const_cast<Module*>(DAG.getMachineFunction().
2731 getFunction().getParent());
2732 auto GV = new GlobalVariable(
2733 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2734 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2735 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2736 Twine(AFI->createPICLabelUId())
2737 );
2738 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2739 dl, PtrVT);
2740 return LowerGlobalAddress(GA, DAG);
2741 }
2742
2743 if (CP->isMachineConstantPoolEntry())
2744 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2745 CP->getAlignment());
2746 else
2747 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2748 CP->getAlignment());
2749 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2750}
2751
2752unsigned ARMTargetLowering::getJumpTableEncoding() const {
2753 return MachineJumpTableInfo::EK_Inline;
2754}
2755
2756SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2757 SelectionDAG &DAG) const {
2758 MachineFunction &MF = DAG.getMachineFunction();
2759 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2760 unsigned ARMPCLabelIndex = 0;
2761 SDLoc DL(Op);
2762 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2763 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2764 SDValue CPAddr;
2765 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2766 if (!IsPositionIndependent) {
2767 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2768 } else {
2769 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2770 ARMPCLabelIndex = AFI->createPICLabelUId();
2771 ARMConstantPoolValue *CPV =
2772 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2773 ARMCP::CPBlockAddress, PCAdj);
2774 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2775 }
2776 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2777 SDValue Result = DAG.getLoad(
2778 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2779 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2780 if (!IsPositionIndependent)
2781 return Result;
2782 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2783 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2784}
2785
2786/// \brief Convert a TLS address reference into the correct sequence of loads
2787/// and calls to compute the variable's address for Darwin, and return an
2788/// SDValue containing the final node.
2789
2790/// Darwin only has one TLS scheme which must be capable of dealing with the
2791/// fully general situation, in the worst case. This means:
2792/// + "extern __thread" declaration.
2793/// + Defined in a possibly unknown dynamic library.
2794///
2795/// The general system is that each __thread variable has a [3 x i32] descriptor
2796/// which contains information used by the runtime to calculate the address. The
2797/// only part of this the compiler needs to know about is the first word, which
2798/// contains a function pointer that must be called with the address of the
2799/// entire descriptor in "r0".
2800///
2801/// Since this descriptor may be in a different unit, in general access must
2802/// proceed along the usual ARM rules. A common sequence to produce is:
2803///
2804/// movw rT1, :lower16:_var$non_lazy_ptr
2805/// movt rT1, :upper16:_var$non_lazy_ptr
2806/// ldr r0, [rT1]
2807/// ldr rT2, [r0]
2808/// blx rT2
2809/// [...address now in r0...]
2810SDValue
2811ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2812 SelectionDAG &DAG) const {
2813 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2814, __extension__ __PRETTY_FUNCTION__))
2814 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2814, __extension__ __PRETTY_FUNCTION__))
;
2815 SDLoc DL(Op);
2816
2817 // First step is to get the address of the actua global symbol. This is where
2818 // the TLS descriptor lives.
2819 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2820
2821 // The first entry in the descriptor is a function pointer that we must call
2822 // to obtain the address of the variable.
2823 SDValue Chain = DAG.getEntryNode();
2824 SDValue FuncTLVGet = DAG.getLoad(
2825 MVT::i32, DL, Chain, DescAddr,
2826 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2827 /* Alignment = */ 4,
2828 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2829 MachineMemOperand::MOInvariant);
2830 Chain = FuncTLVGet.getValue(1);
2831
2832 MachineFunction &F = DAG.getMachineFunction();
2833 MachineFrameInfo &MFI = F.getFrameInfo();
2834 MFI.setAdjustsStack(true);
2835
2836 // TLS calls preserve all registers except those that absolutely must be
2837 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2838 // silly).
2839 auto TRI =
2840 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2841 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2842 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2843
2844 // Finally, we can make the call. This is just a degenerate version of a
2845 // normal AArch64 call node: r0 takes the address of the descriptor, and
2846 // returns the address of the variable in this thread.
2847 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2848 Chain =
2849 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2850 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2851 DAG.getRegisterMask(Mask), Chain.getValue(1));
2852 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2853}
2854
2855SDValue
2856ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2857 SelectionDAG &DAG) const {
2858 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2858, __extension__ __PRETTY_FUNCTION__))
;
2859
2860 SDValue Chain = DAG.getEntryNode();
2861 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2862 SDLoc DL(Op);
2863
2864 // Load the current TEB (thread environment block)
2865 SDValue Ops[] = {Chain,
2866 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2867 DAG.getConstant(15, DL, MVT::i32),
2868 DAG.getConstant(0, DL, MVT::i32),
2869 DAG.getConstant(13, DL, MVT::i32),
2870 DAG.getConstant(0, DL, MVT::i32),
2871 DAG.getConstant(2, DL, MVT::i32)};
2872 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2873 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2874
2875 SDValue TEB = CurrentTEB.getValue(0);
2876 Chain = CurrentTEB.getValue(1);
2877
2878 // Load the ThreadLocalStoragePointer from the TEB
2879 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2880 SDValue TLSArray =
2881 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2882 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2883
2884 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2885 // offset into the TLSArray.
2886
2887 // Load the TLS index from the C runtime
2888 SDValue TLSIndex =
2889 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2890 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2891 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2892
2893 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2894 DAG.getConstant(2, DL, MVT::i32));
2895 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2896 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2897 MachinePointerInfo());
2898
2899 // Get the offset of the start of the .tls section (section base)
2900 const auto *GA = cast<GlobalAddressSDNode>(Op);
2901 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2902 SDValue Offset = DAG.getLoad(
2903 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2904 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2905 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2906
2907 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2908}
2909
2910// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2911SDValue
2912ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2913 SelectionDAG &DAG) const {
2914 SDLoc dl(GA);
2915 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2916 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2917 MachineFunction &MF = DAG.getMachineFunction();
2918 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2919 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2920 ARMConstantPoolValue *CPV =
2921 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2922 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2923 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2924 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2925 Argument = DAG.getLoad(
2926 PtrVT, dl, DAG.getEntryNode(), Argument,
2927 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2928 SDValue Chain = Argument.getValue(1);
2929
2930 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2931 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2932
2933 // call __tls_get_addr.
2934 ArgListTy Args;
2935 ArgListEntry Entry;
2936 Entry.Node = Argument;
2937 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2938 Args.push_back(Entry);
2939
2940 // FIXME: is there useful debug info available here?
2941 TargetLowering::CallLoweringInfo CLI(DAG);
2942 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2943 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2944 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2945
2946 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2947 return CallResult.first;
2948}
2949
2950// Lower ISD::GlobalTLSAddress using the "initial exec" or
2951// "local exec" model.
2952SDValue
2953ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2954 SelectionDAG &DAG,
2955 TLSModel::Model model) const {
2956 const GlobalValue *GV = GA->getGlobal();
2957 SDLoc dl(GA);
2958 SDValue Offset;
2959 SDValue Chain = DAG.getEntryNode();
2960 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2961 // Get the Thread Pointer
2962 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2963
2964 if (model == TLSModel::InitialExec) {
2965 MachineFunction &MF = DAG.getMachineFunction();
2966 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2967 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2968 // Initial exec model.
2969 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2970 ARMConstantPoolValue *CPV =
2971 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2972 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2973 true);
2974 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2975 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2976 Offset = DAG.getLoad(
2977 PtrVT, dl, Chain, Offset,
2978 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2979 Chain = Offset.getValue(1);
2980
2981 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2982 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2983
2984 Offset = DAG.getLoad(
2985 PtrVT, dl, Chain, Offset,
2986 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2987 } else {
2988 // local exec model
2989 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 2989, __extension__ __PRETTY_FUNCTION__))
;
2990 ARMConstantPoolValue *CPV =
2991 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2992 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2993 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2994 Offset = DAG.getLoad(
2995 PtrVT, dl, Chain, Offset,
2996 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2997 }
2998
2999 // The address of the thread local variable is the add of the thread
3000 // pointer with the offset of the variable.
3001 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3002}
3003
3004SDValue
3005ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3006 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3007 if (DAG.getTarget().Options.EmulatedTLS)
3008 return LowerToTLSEmulatedModel(GA, DAG);
3009
3010 if (Subtarget->isTargetDarwin())
3011 return LowerGlobalTLSAddressDarwin(Op, DAG);
3012
3013 if (Subtarget->isTargetWindows())
3014 return LowerGlobalTLSAddressWindows(Op, DAG);
3015
3016 // TODO: implement the "local dynamic" model
3017 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3017, __extension__ __PRETTY_FUNCTION__))
;
3018 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3019
3020 switch (model) {
3021 case TLSModel::GeneralDynamic:
3022 case TLSModel::LocalDynamic:
3023 return LowerToTLSGeneralDynamicModel(GA, DAG);
3024 case TLSModel::InitialExec:
3025 case TLSModel::LocalExec:
3026 return LowerToTLSExecModels(GA, DAG, model);
3027 }
3028 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3028)
;
3029}
3030
3031/// Return true if all users of V are within function F, looking through
3032/// ConstantExprs.
3033static bool allUsersAreInFunction(const Value *V, const Function *F) {
3034 SmallVector<const User*,4> Worklist;
3035 for (auto *U : V->users())
3036 Worklist.push_back(U);
3037 while (!Worklist.empty()) {
3038 auto *U = Worklist.pop_back_val();
3039 if (isa<ConstantExpr>(U)) {
3040 for (auto *UU : U->users())
3041 Worklist.push_back(UU);
3042 continue;
3043 }
3044
3045 auto *I = dyn_cast<Instruction>(U);
3046 if (!I || I->getParent()->getParent() != F)
3047 return false;
3048 }
3049 return true;
3050}
3051
3052/// Return true if all users of V are within some (any) function, looking through
3053/// ConstantExprs. In other words, are there any global constant users?
3054static bool allUsersAreInFunctions(const Value *V) {
3055 SmallVector<const User*,4> Worklist;
3056 for (auto *U : V->users())
3057 Worklist.push_back(U);
3058 while (!Worklist.empty()) {
3059 auto *U = Worklist.pop_back_val();
3060 if (isa<ConstantExpr>(U)) {
3061 for (auto *UU : U->users())
3062 Worklist.push_back(UU);
3063 continue;
3064 }
3065
3066 if (!isa<Instruction>(U))
3067 return false;
3068 }
3069 return true;
3070}
3071
3072// Return true if T is an integer, float or an array/vector of either.
3073static bool isSimpleType(Type *T) {
3074 if (T->isIntegerTy() || T->isFloatingPointTy())
3075 return true;
3076 Type *SubT = nullptr;
3077 if (T->isArrayTy())
3078 SubT = T->getArrayElementType();
3079 else if (T->isVectorTy())
3080 SubT = T->getVectorElementType();
3081 else
3082 return false;
3083 return SubT->isIntegerTy() || SubT->isFloatingPointTy();
3084}
3085
3086static SDValue promoteToConstantPool(const GlobalValue *GV, SelectionDAG &DAG,
3087 EVT PtrVT, const SDLoc &dl) {
3088 // If we're creating a pool entry for a constant global with unnamed address,
3089 // and the global is small enough, we can emit it inline into the constant pool
3090 // to save ourselves an indirection.
3091 //
3092 // This is a win if the constant is only used in one function (so it doesn't
3093 // need to be duplicated) or duplicating the constant wouldn't increase code
3094 // size (implying the constant is no larger than 4 bytes).
3095 const Function &F = DAG.getMachineFunction().getFunction();
3096
3097 // We rely on this decision to inline being idemopotent and unrelated to the
3098 // use-site. We know that if we inline a variable at one use site, we'll
3099 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3100 // doesn't know about this optimization, so bail out if it's enabled else
3101 // we could decide to inline here (and thus never emit the GV) but require
3102 // the GV from fast-isel generated code.
3103 if (!EnableConstpoolPromotion ||
3104 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3105 return SDValue();
3106
3107 auto *GVar = dyn_cast<GlobalVariable>(GV);
3108 if (!GVar || !GVar->hasInitializer() ||
3109 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3110 !GVar->hasLocalLinkage())
3111 return SDValue();
3112
3113 // Ensure that we don't try and inline any type that contains pointers. If
3114 // we inline a value that contains relocations, we move the relocations from
3115 // .data to .text which is not ideal.
3116 auto *Init = GVar->getInitializer();
3117 if (!isSimpleType(Init->getType()))
3118 return SDValue();
3119
3120 // The constant islands pass can only really deal with alignment requests
3121 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3122 // any type wanting greater alignment requirements than 4 bytes. We also
3123 // can only promote constants that are multiples of 4 bytes in size or
3124 // are paddable to a multiple of 4. Currently we only try and pad constants
3125 // that are strings for simplicity.
3126 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3127 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3128 unsigned Align = GVar->getAlignment();
3129 unsigned RequiredPadding = 4 - (Size % 4);
3130 bool PaddingPossible =
3131 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3132 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3133 Size == 0)
3134 return SDValue();
3135
3136 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3137 MachineFunction &MF = DAG.getMachineFunction();
3138 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3139
3140 // We can't bloat the constant pool too much, else the ConstantIslands pass
3141 // may fail to converge. If we haven't promoted this global yet (it may have
3142 // multiple uses), and promoting it would increase the constant pool size (Sz
3143 // > 4), ensure we have space to do so up to MaxTotal.
3144 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3145 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3146 ConstpoolPromotionMaxTotal)
3147 return SDValue();
3148
3149 // This is only valid if all users are in a single function OR it has users
3150 // in multiple functions but it no larger than a pointer. We also check if
3151 // GVar has constant (non-ConstantExpr) users. If so, it essentially has its
3152 // address taken.
3153 if (!allUsersAreInFunction(GVar, &F) &&
3154 !(Size <= 4 && allUsersAreInFunctions(GVar)))
3155 return SDValue();
3156
3157 // We're going to inline this global. Pad it out if needed.
3158 if (RequiredPadding != 4) {
3159 StringRef S = CDAInit->getAsString();
3160
3161 SmallVector<uint8_t,16> V(S.size());
3162 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3163 while (RequiredPadding--)
3164 V.push_back(0);
3165 Init = ConstantDataArray::get(*DAG.getContext(), V);
3166 }
3167
3168 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3169 SDValue CPAddr =
3170 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3171 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3172 AFI->markGlobalAsPromotedToConstantPool(GVar);
3173 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3174 PaddedSize - 4);
3175 }
3176 ++NumConstpoolPromoted;
3177 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3178}
3179
3180bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3181 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3182 GV = GA->getBaseObject();
3183 return (isa<GlobalVariable>(GV) && cast<GlobalVariable>(GV)->isConstant()) ||
3184 isa<Function>(GV);
3185}
3186
3187SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3188 SelectionDAG &DAG) const {
3189 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3190 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3190)
;
3191 case Triple::COFF:
3192 return LowerGlobalAddressWindows(Op, DAG);
3193 case Triple::ELF:
3194 return LowerGlobalAddressELF(Op, DAG);
3195 case Triple::MachO:
3196 return LowerGlobalAddressDarwin(Op, DAG);
3197 }
3198}
3199
3200SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3201 SelectionDAG &DAG) const {
3202 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3203 SDLoc dl(Op);
3204 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3205 const TargetMachine &TM = getTargetMachine();
3206 bool IsRO = isReadOnly(GV);
3207
3208 // promoteToConstantPool only if not generating XO text section
3209 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3210 if (SDValue V = promoteToConstantPool(GV, DAG, PtrVT, dl))
3211 return V;
3212
3213 if (isPositionIndependent()) {
3214 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3215 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3216 UseGOT_PREL ? ARMII::MO_GOT : 0);
3217 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3218 if (UseGOT_PREL)
3219 Result =
3220 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3221 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3222 return Result;
3223 } else if (Subtarget->isROPI() && IsRO) {
3224 // PC-relative.
3225 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3226 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3227 return Result;
3228 } else if (Subtarget->isRWPI() && !IsRO) {
3229 // SB-relative.
3230 SDValue RelAddr;
3231 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3232 ++NumMovwMovt;
3233 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3234 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3235 } else { // use literal pool for address constant
3236 ARMConstantPoolValue *CPV =
3237 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3238 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3239 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3240 RelAddr = DAG.getLoad(
3241 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3242 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3243 }
3244 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3245 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3246 return Result;
3247 }
3248
3249 // If we have T2 ops, we can materialize the address directly via movt/movw
3250 // pair. This is always cheaper.
3251 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3252 ++NumMovwMovt;
3253 // FIXME: Once remat is capable of dealing with instructions with register
3254 // operands, expand this into two nodes.
3255 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3256 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3257 } else {
3258 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3259 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3260 return DAG.getLoad(
3261 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3262 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3263 }
3264}
3265
3266SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3267 SelectionDAG &DAG) const {
3268 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3269, __extension__ __PRETTY_FUNCTION__))
3269 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3269, __extension__ __PRETTY_FUNCTION__))
;
3270 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3271 SDLoc dl(Op);
3272 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3273
3274 if (Subtarget->useMovt(DAG.getMachineFunction()))
3275 ++NumMovwMovt;
3276
3277 // FIXME: Once remat is capable of dealing with instructions with register
3278 // operands, expand this into multiple nodes
3279 unsigned Wrapper =
3280 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3281
3282 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3283 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3284
3285 if (Subtarget->isGVIndirectSymbol(GV))
3286 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3287 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3288 return Result;
3289}
3290
3291SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3292 SelectionDAG &DAG) const {
3293 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3293, __extension__ __PRETTY_FUNCTION__))
;
3294 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3295, __extension__ __PRETTY_FUNCTION__))
3295 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3295, __extension__ __PRETTY_FUNCTION__))
;
3296 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3297, __extension__ __PRETTY_FUNCTION__))
3297 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3297, __extension__ __PRETTY_FUNCTION__))
;
3298
3299 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3300 const ARMII::TOF TargetFlags =
3301 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
3302 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3303 SDValue Result;
3304 SDLoc DL(Op);
3305
3306 ++NumMovwMovt;
3307
3308 // FIXME: Once remat is capable of dealing with instructions with register
3309 // operands, expand this into two nodes.
3310 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3311 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3312 TargetFlags));
3313 if (GV->hasDLLImportStorageClass())
3314 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3315 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3316 return Result;
3317}
3318
3319SDValue
3320ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3321 SDLoc dl(Op);
3322 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3323 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3324 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3325 Op.getOperand(1), Val);
3326}
3327
3328SDValue
3329ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3330 SDLoc dl(Op);
3331 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3332 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3333}
3334
3335SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3336 SelectionDAG &DAG) const {
3337 SDLoc dl(Op);
3338 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3339 Op.getOperand(0));
3340}
3341
3342SDValue
3343ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3344 const ARMSubtarget *Subtarget) const {
3345 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3346 SDLoc dl(Op);
3347 switch (IntNo) {
3348 default: return SDValue(); // Don't custom lower most intrinsics.
3349 case Intrinsic::thread_pointer: {
3350 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3351 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3352 }
3353 case Intrinsic::eh_sjlj_lsda: {
3354 MachineFunction &MF = DAG.getMachineFunction();
3355 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3356 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3357 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3358 SDValue CPAddr;
3359 bool IsPositionIndependent = isPositionIndependent();
3360 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3361 ARMConstantPoolValue *CPV =
3362 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3363 ARMCP::CPLSDA, PCAdj);
3364 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3365 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3366 SDValue Result = DAG.getLoad(
3367 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3368 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3369
3370 if (IsPositionIndependent) {
3371 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3372 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3373 }
3374 return Result;
3375 }
3376 case Intrinsic::arm_neon_vabs:
3377 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3378 Op.getOperand(1));
3379 case Intrinsic::arm_neon_vmulls:
3380 case Intrinsic::arm_neon_vmullu: {
3381 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3382 ? ARMISD::VMULLs : ARMISD::VMULLu;
3383 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3384 Op.getOperand(1), Op.getOperand(2));
3385 }
3386 case Intrinsic::arm_neon_vminnm:
3387 case Intrinsic::arm_neon_vmaxnm: {
3388 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3389 ? ISD::FMINNUM : ISD::FMAXNUM;
3390 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3391 Op.getOperand(1), Op.getOperand(2));
3392 }
3393 case Intrinsic::arm_neon_vminu:
3394 case Intrinsic::arm_neon_vmaxu: {
3395 if (Op.getValueType().isFloatingPoint())
3396 return SDValue();
3397 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3398 ? ISD::UMIN : ISD::UMAX;
3399 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3400 Op.getOperand(1), Op.getOperand(2));
3401 }
3402 case Intrinsic::arm_neon_vmins:
3403 case Intrinsic::arm_neon_vmaxs: {
3404 // v{min,max}s is overloaded between signed integers and floats.
3405 if (!Op.getValueType().isFloatingPoint()) {
3406 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3407 ? ISD::SMIN : ISD::SMAX;
3408 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3409 Op.getOperand(1), Op.getOperand(2));
3410 }
3411 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3412 ? ISD::FMINNAN : ISD::FMAXNAN;
3413 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3414 Op.getOperand(1), Op.getOperand(2));
3415 }
3416 case Intrinsic::arm_neon_vtbl1:
3417 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3418 Op.getOperand(1), Op.getOperand(2));
3419 case Intrinsic::arm_neon_vtbl2:
3420 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3421 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3422 }
3423}
3424
3425static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3426 const ARMSubtarget *Subtarget) {
3427 SDLoc dl(Op);
3428 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3429 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3430 if (SSID == SyncScope::SingleThread)
3431 return Op;
3432
3433 if (!Subtarget->hasDataBarrier()) {
3434 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3435 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3436 // here.
3437 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3438, __extension__ __PRETTY_FUNCTION__))
3438 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3438, __extension__ __PRETTY_FUNCTION__))
;
3439 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3440 DAG.getConstant(0, dl, MVT::i32));
3441 }
3442
3443 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3444 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3445 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3446 if (Subtarget->isMClass()) {
3447 // Only a full system barrier exists in the M-class architectures.
3448 Domain = ARM_MB::SY;
3449 } else if (Subtarget->preferISHSTBarriers() &&
3450 Ord == AtomicOrdering::Release) {
3451 // Swift happens to implement ISHST barriers in a way that's compatible with
3452 // Release semantics but weaker than ISH so we'd be fools not to use
3453 // it. Beware: other processors probably don't!
3454 Domain = ARM_MB::ISHST;
3455 }
3456
3457 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3458 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3459 DAG.getConstant(Domain, dl, MVT::i32));
3460}
3461
3462static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3463 const ARMSubtarget *Subtarget) {
3464 // ARM pre v5TE and Thumb1 does not have preload instructions.
3465 if (!(Subtarget->isThumb2() ||
3466 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3467 // Just preserve the chain.
3468 return Op.getOperand(0);
3469
3470 SDLoc dl(Op);
3471 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3472 if (!isRead &&
3473 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3474 // ARMv7 with MP extension has PLDW.
3475 return Op.getOperand(0);
3476
3477 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3478 if (Subtarget->isThumb()) {
3479 // Invert the bits.
3480 isRead = ~isRead & 1;
3481 isData = ~isData & 1;
3482 }
3483
3484 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3485 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3486 DAG.getConstant(isData, dl, MVT::i32));
3487}
3488
3489static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3490 MachineFunction &MF = DAG.getMachineFunction();
3491 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3492
3493 // vastart just stores the address of the VarArgsFrameIndex slot into the
3494 // memory location argument.
3495 SDLoc dl(Op);
3496 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3497 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3498 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3499 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3500 MachinePointerInfo(SV));
3501}
3502
3503SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3504 CCValAssign &NextVA,
3505 SDValue &Root,
3506 SelectionDAG &DAG,
3507 const SDLoc &dl) const {
3508 MachineFunction &MF = DAG.getMachineFunction();
3509 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3510
3511 const TargetRegisterClass *RC;
3512 if (AFI->isThumb1OnlyFunction())
3513 RC = &ARM::tGPRRegClass;
3514 else
3515 RC = &ARM::GPRRegClass;
3516
3517 // Transform the arguments stored in physical registers into virtual ones.
3518 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3519 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3520
3521 SDValue ArgValue2;
3522 if (NextVA.isMemLoc()) {
3523 MachineFrameInfo &MFI = MF.getFrameInfo();
3524 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3525
3526 // Create load node to retrieve arguments from the stack.
3527 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3528 ArgValue2 = DAG.getLoad(
3529 MVT::i32, dl, Root, FIN,
3530 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3531 } else {
3532 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3533 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3534 }
3535 if (!Subtarget->isLittle())
3536 std::swap (ArgValue, ArgValue2);
3537 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3538}
3539
3540// The remaining GPRs hold either the beginning of variable-argument
3541// data, or the beginning of an aggregate passed by value (usually
3542// byval). Either way, we allocate stack slots adjacent to the data
3543// provided by our caller, and store the unallocated registers there.
3544// If this is a variadic function, the va_list pointer will begin with
3545// these values; otherwise, this reassembles a (byval) structure that
3546// was split between registers and memory.
3547// Return: The frame index registers were stored into.
3548int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3549 const SDLoc &dl, SDValue &Chain,
3550 const Value *OrigArg,
3551 unsigned InRegsParamRecordIdx,
3552 int ArgOffset, unsigned ArgSize) const {
3553 // Currently, two use-cases possible:
3554 // Case #1. Non-var-args function, and we meet first byval parameter.
3555 // Setup first unallocated register as first byval register;
3556 // eat all remained registers
3557 // (these two actions are performed by HandleByVal method).
3558 // Then, here, we initialize stack frame with
3559 // "store-reg" instructions.
3560 // Case #2. Var-args function, that doesn't contain byval parameters.
3561 // The same: eat all remained unallocated registers,
3562 // initialize stack frame.
3563
3564 MachineFunction &MF = DAG.getMachineFunction();
3565 MachineFrameInfo &MFI = MF.getFrameInfo();
3566 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3567 unsigned RBegin, REnd;
3568 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3569 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3570 } else {
3571 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3572 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3573 REnd = ARM::R4;
3574 }
3575
3576 if (REnd != RBegin)
3577 ArgOffset = -4 * (ARM::R4 - RBegin);
3578
3579 auto PtrVT = getPointerTy(DAG.getDataLayout());
3580 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3581 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3582
3583 SmallVector<SDValue, 4> MemOps;
3584 const TargetRegisterClass *RC =
3585 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3586
3587 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3588 unsigned VReg = MF.addLiveIn(Reg, RC);
3589 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3590 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3591 MachinePointerInfo(OrigArg, 4 * i));
3592 MemOps.push_back(Store);
3593 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3594 }
3595
3596 if (!MemOps.empty())
3597 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3598 return FrameIndex;
3599}
3600
3601// Setup stack frame, the va_list pointer will start from.
3602void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3603 const SDLoc &dl, SDValue &Chain,
3604 unsigned ArgOffset,
3605 unsigned TotalArgRegsSaveSize,
3606 bool ForceMutable) const {
3607 MachineFunction &MF = DAG.getMachineFunction();
3608 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3609
3610 // Try to store any remaining integer argument regs
3611 // to their spots on the stack so that they may be loaded by dereferencing
3612 // the result of va_next.
3613 // If there is no regs to be stored, just point address after last
3614 // argument passed via stack.
3615 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3616 CCInfo.getInRegsParamsCount(),
3617 CCInfo.getNextStackOffset(), 4);
3618 AFI->setVarArgsFrameIndex(FrameIndex);
3619}
3620
3621SDValue ARMTargetLowering::LowerFormalArguments(
3622 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3623 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3624 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3625 MachineFunction &MF = DAG.getMachineFunction();
3626 MachineFrameInfo &MFI = MF.getFrameInfo();
3627
3628 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3629
3630 // Assign locations to all of the incoming arguments.
3631 SmallVector<CCValAssign, 16> ArgLocs;
3632 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3633 *DAG.getContext());
3634 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3635
3636 SmallVector<SDValue, 16> ArgValues;
3637 SDValue ArgValue;
3638 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3639 unsigned CurArgIdx = 0;
3640
3641 // Initially ArgRegsSaveSize is zero.
3642 // Then we increase this value each time we meet byval parameter.
3643 // We also increase this value in case of varargs function.
3644 AFI->setArgRegsSaveSize(0);
3645
3646 // Calculate the amount of stack space that we need to allocate to store
3647 // byval and variadic arguments that are passed in registers.
3648 // We need to know this before we allocate the first byval or variadic
3649 // argument, as they will be allocated a stack slot below the CFA (Canonical
3650 // Frame Address, the stack pointer at entry to the function).
3651 unsigned ArgRegBegin = ARM::R4;
3652 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3653 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3654 break;
3655
3656 CCValAssign &VA = ArgLocs[i];
3657 unsigned Index = VA.getValNo();
3658 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3659 if (!Flags.isByVal())
3660 continue;
3661
3662 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3662, __extension__ __PRETTY_FUNCTION__))
;
3663 unsigned RBegin, REnd;
3664 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3665 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3666
3667 CCInfo.nextInRegsParam();
3668 }
3669 CCInfo.rewindByValRegsInfo();
3670
3671 int lastInsIndex = -1;
3672 if (isVarArg && MFI.hasVAStart()) {
3673 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3674 if (RegIdx != array_lengthof(GPRArgRegs))
3675 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3676 }
3677
3678 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3679 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3680 auto PtrVT = getPointerTy(DAG.getDataLayout());
3681
3682 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3683 CCValAssign &VA = ArgLocs[i];
3684 if (Ins[VA.getValNo()].isOrigArg()) {
3685 std::advance(CurOrigArg,
3686 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3687 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3688 }
3689 // Arguments stored in registers.
3690 if (VA.isRegLoc()) {
3691 EVT RegVT = VA.getLocVT();
3692
3693 if (VA.needsCustom()) {
3694 // f64 and vector types are split up into multiple registers or
3695 // combinations of registers and stack slots.
3696 if (VA.getLocVT() == MVT::v2f64) {
3697 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3698 Chain, DAG, dl);
3699 VA = ArgLocs[++i]; // skip ahead to next loc
3700 SDValue ArgValue2;
3701 if (VA.isMemLoc()) {
3702 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3703 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3704 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3705 MachinePointerInfo::getFixedStack(
3706 DAG.getMachineFunction(), FI));
3707 } else {
3708 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3709 Chain, DAG, dl);
3710 }
3711 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3712 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3713 ArgValue, ArgValue1,
3714 DAG.getIntPtrConstant(0, dl));
3715 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3716 ArgValue, ArgValue2,
3717 DAG.getIntPtrConstant(1, dl));
3718 } else
3719 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3720 } else {
3721 const TargetRegisterClass *RC;
3722
3723
3724 if (RegVT == MVT::f16)
3725 RC = &ARM::HPRRegClass;
3726 else if (RegVT == MVT::f32)
3727 RC = &ARM::SPRRegClass;
3728 else if (RegVT == MVT::f64)
3729 RC = &ARM::DPRRegClass;
3730 else if (RegVT == MVT::v2f64)
3731 RC = &ARM::QPRRegClass;
3732 else if (RegVT == MVT::i32)
3733 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3734 : &ARM::GPRRegClass;
3735 else
3736 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3736)
;
3737
3738 // Transform the arguments in physical registers into virtual ones.
3739 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3740 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3741 }
3742
3743 // If this is an 8 or 16-bit value, it is really passed promoted
3744 // to 32 bits. Insert an assert[sz]ext to capture this, then
3745 // truncate to the right size.
3746 switch (VA.getLocInfo()) {
3747 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3747)
;
3748 case CCValAssign::Full: break;
3749 case CCValAssign::BCvt:
3750 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3751 break;
3752 case CCValAssign::SExt:
3753 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3754 DAG.getValueType(VA.getValVT()));
3755 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3756 break;
3757 case CCValAssign::ZExt:
3758 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3759 DAG.getValueType(VA.getValVT()));
3760 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3761 break;
3762 }
3763
3764 InVals.push_back(ArgValue);
3765 } else { // VA.isRegLoc()
3766 // sanity check
3767 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3767, __extension__ __PRETTY_FUNCTION__))
;
3768 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3768, __extension__ __PRETTY_FUNCTION__))
;
3769
3770 int index = VA.getValNo();
3771
3772 // Some Ins[] entries become multiple ArgLoc[] entries.
3773 // Process them only once.
3774 if (index != lastInsIndex)
3775 {
3776 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3777 // FIXME: For now, all byval parameter objects are marked mutable.
3778 // This can be changed with more analysis.
3779 // In case of tail call optimization mark all arguments mutable.
3780 // Since they could be overwritten by lowering of arguments in case of
3781 // a tail call.
3782 if (Flags.isByVal()) {
3783 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3784, __extension__ __PRETTY_FUNCTION__))
3784 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3784, __extension__ __PRETTY_FUNCTION__))
;
3785 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3786
3787 int FrameIndex = StoreByValRegs(
3788 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3789 VA.getLocMemOffset(), Flags.getByValSize());
3790 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3791 CCInfo.nextInRegsParam();
3792 } else {
3793 unsigned FIOffset = VA.getLocMemOffset();
3794 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3795 FIOffset, true);
3796
3797 // Create load nodes to retrieve arguments from the stack.
3798 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3799 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3800 MachinePointerInfo::getFixedStack(
3801 DAG.getMachineFunction(), FI)));
3802 }
3803 lastInsIndex = index;
3804 }
3805 }
3806 }
3807
3808 // varargs
3809 if (isVarArg && MFI.hasVAStart())
3810 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3811 CCInfo.getNextStackOffset(),
3812 TotalArgRegsSaveSize);
3813
3814 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3815
3816 return Chain;
3817}
3818
3819/// isFloatingPointZero - Return true if this is +0.0.
3820static bool isFloatingPointZero(SDValue Op) {
3821 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3822 return CFP->getValueAPF().isPosZero();
3823 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3824 // Maybe this has already been legalized into the constant pool?
3825 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3826 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3827 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3828 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3829 return CFP->getValueAPF().isPosZero();
3830 }
3831 } else if (Op->getOpcode() == ISD::BITCAST &&
3832 Op->getValueType(0) == MVT::f64) {
3833 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3834 // created by LowerConstantFP().
3835 SDValue BitcastOp = Op->getOperand(0);
3836 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3837 isNullConstant(BitcastOp->getOperand(0)))
3838 return true;
3839 }
3840 return false;
3841}
3842
3843/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3844/// the given operands.
3845SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3846 SDValue &ARMcc, SelectionDAG &DAG,
3847 const SDLoc &dl) const {
3848 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3849 unsigned C = RHSC->getZExtValue();
3850 if (!isLegalICmpImmediate(C)) {
3851 // Constant does not fit, try adjusting it by one?
3852 switch (CC) {
3853 default: break;
3854 case ISD::SETLT:
3855 case ISD::SETGE:
3856 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3857 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3858 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3859 }
3860 break;
3861 case ISD::SETULT:
3862 case ISD::SETUGE:
3863 if (C != 0 && isLegalICmpImmediate(C-1)) {
3864 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3865 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3866 }
3867 break;
3868 case ISD::SETLE:
3869 case ISD::SETGT:
3870 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3871 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3872 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3873 }
3874 break;
3875 case ISD::SETULE:
3876 case ISD::SETUGT:
3877 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3878 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3879 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3880 }
3881 break;
3882 }
3883 }
3884 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3885 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3886 // In ARM and Thumb-2, the compare instructions can shift their second
3887 // operand.
3888 CC = ISD::getSetCCSwappedOperands(CC);
3889 std::swap(LHS, RHS);
3890 }
3891
3892 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3893 ARMISD::NodeType CompareType;
3894 switch (CondCode) {
3895 default:
3896 CompareType = ARMISD::CMP;
3897 break;
3898 case ARMCC::EQ:
3899 case ARMCC::NE:
3900 // Uses only Z Flag
3901 CompareType = ARMISD::CMPZ;
3902 break;
3903 }
3904 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3905 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3906}
3907
3908/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3909SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3910 SelectionDAG &DAG, const SDLoc &dl,
3911 bool InvalidOnQNaN) const {
3912 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)(static_cast <bool> (!Subtarget->isFPOnlySP() || RHS
.getValueType() != MVT::f64) ? void (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3912, __extension__ __PRETTY_FUNCTION__))
;
3913 SDValue Cmp;
3914 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3915 if (!isFloatingPointZero(RHS))
3916 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3917 else
3918 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3919 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3920}
3921
3922/// duplicateCmp - Glue values can have only one use, so this function
3923/// duplicates a comparison node.
3924SDValue
3925ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3926 unsigned Opc = Cmp.getOpcode();
3927 SDLoc DL(Cmp);
3928 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3929 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3930
3931 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3931, __extension__ __PRETTY_FUNCTION__))
;
3932 Cmp = Cmp.getOperand(0);
3933 Opc = Cmp.getOpcode();
3934 if (Opc == ARMISD::CMPFP)
3935 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3936 Cmp.getOperand(1), Cmp.getOperand(2));
3937 else {
3938 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3938, __extension__ __PRETTY_FUNCTION__))
;
3939 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3940 Cmp.getOperand(1));
3941 }
3942 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3943}
3944
3945// This function returns three things: the arithmetic computation itself
3946// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3947// comparison and the condition code define the case in which the arithmetic
3948// computation *does not* overflow.
3949std::pair<SDValue, SDValue>
3950ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3951 SDValue &ARMcc) const {
3952 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3952, __extension__ __PRETTY_FUNCTION__))
;
3953
3954 SDValue Value, OverflowCmp;
3955 SDValue LHS = Op.getOperand(0);
3956 SDValue RHS = Op.getOperand(1);
3957 SDLoc dl(Op);
3958
3959 // FIXME: We are currently always generating CMPs because we don't support
3960 // generating CMN through the backend. This is not as good as the natural
3961 // CMP case because it causes a register dependency and cannot be folded
3962 // later.
3963
3964 switch (Op.getOpcode()) {
3965 default:
3966 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 3966)
;
3967 case ISD::SADDO:
3968 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3969 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3970 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3971 break;
3972 case ISD::UADDO:
3973 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3974 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3975 // We do not use it in the USUBO case as Value may not be used.
3976 Value = DAG.getNode(ARMISD::ADDC, dl,
3977 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3978 .getValue(0);
3979 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3980 break;
3981 case ISD::SSUBO:
3982 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3983 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3984 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3985 break;
3986 case ISD::USUBO:
3987 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3988 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3989 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3990 break;
3991 case ISD::UMULO:
3992 // We generate a UMUL_LOHI and then check if the high word is 0.
3993 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3994 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3995 DAG.getVTList(Op.getValueType(), Op.getValueType()),
3996 LHS, RHS);
3997 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
3998 DAG.getConstant(0, dl, MVT::i32));
3999 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4000 break;
4001 case ISD::SMULO:
4002 // We generate a SMUL_LOHI and then check if all the bits of the high word
4003 // are the same as the sign bit of the low word.
4004 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4005 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4006 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4007 LHS, RHS);
4008 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4009 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4010 Value.getValue(0),
4011 DAG.getConstant(31, dl, MVT::i32)));
4012 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4013 break;
4014 } // switch (...)
4015
4016 return std::make_pair(Value, OverflowCmp);
4017}
4018
4019SDValue
4020ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4021 // Let legalize expand this if it isn't a legal type yet.
4022 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4023 return SDValue();
4024
4025 SDValue Value, OverflowCmp;
4026 SDValue ARMcc;
4027 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4028 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4029 SDLoc dl(Op);
4030 // We use 0 and 1 as false and true values.
4031 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4032 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4033 EVT VT = Op.getValueType();
4034
4035 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4036 ARMcc, CCR, OverflowCmp);
4037
4038 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4039 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4040}
4041
4042static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4043 SelectionDAG &DAG) {
4044 SDLoc DL(BoolCarry);
4045 EVT CarryVT = BoolCarry.getValueType();
4046
4047 APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits());
4048 // This converts the boolean value carry into the carry flag by doing
4049 // ARMISD::ADDC Carry, ~0
4050 return DAG.getNode(ARMISD::ADDC, DL, DAG.getVTList(CarryVT, MVT::i32),
4051 BoolCarry, DAG.getConstant(NegOne, DL, CarryVT));
4052}
4053
4054static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4055 SelectionDAG &DAG) {
4056 SDLoc DL(Flags);
4057
4058 // Now convert the carry flag into a boolean carry. We do this
4059 // using ARMISD:ADDE 0, 0, Carry
4060 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4061 DAG.getConstant(0, DL, MVT::i32),
4062 DAG.getConstant(0, DL, MVT::i32), Flags);
4063}
4064
4065SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4066 SelectionDAG &DAG) const {
4067 // Let legalize expand this if it isn't a legal type yet.
4068 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4069 return SDValue();
4070
4071 SDValue LHS = Op.getOperand(0);
4072 SDValue RHS = Op.getOperand(1);
4073 SDLoc dl(Op);
4074
4075 EVT VT = Op.getValueType();
4076 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4077 SDValue Value;
4078 SDValue Overflow;
4079 switch (Op.getOpcode()) {
4080 default:
4081 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4081)
;
4082 case ISD::UADDO:
4083 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4084 // Convert the carry flag into a boolean value.
4085 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4086 break;
4087 case ISD::USUBO: {
4088 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4089 // Convert the carry flag into a boolean value.
4090 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4091 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4092 // value. So compute 1 - C.
4093 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4094 DAG.getConstant(1, dl, MVT::i32), Overflow);
4095 break;
4096 }
4097 }
4098
4099 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4100}
4101
4102SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4103 SDValue Cond = Op.getOperand(0);
4104 SDValue SelectTrue = Op.getOperand(1);
4105 SDValue SelectFalse = Op.getOperand(2);
4106 SDLoc dl(Op);
4107 unsigned Opc = Cond.getOpcode();
4108
4109 if (Cond.getResNo() == 1 &&
4110 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4111 Opc == ISD::USUBO)) {
4112 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4113 return SDValue();
4114
4115 SDValue Value, OverflowCmp;
4116 SDValue ARMcc;
4117 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4118 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4119 EVT VT = Op.getValueType();
4120
4121 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4122 OverflowCmp, DAG);
4123 }
4124
4125 // Convert:
4126 //
4127 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4128 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4129 //
4130 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4131 const ConstantSDNode *CMOVTrue =
4132 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4133 const ConstantSDNode *CMOVFalse =
4134 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4135
4136 if (CMOVTrue && CMOVFalse) {
4137 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4138 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4139
4140 SDValue True;
4141 SDValue False;
4142 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4143 True = SelectTrue;
4144 False = SelectFalse;
4145 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4146 True = SelectFalse;
4147 False = SelectTrue;
4148 }
4149
4150 if (True.getNode() && False.getNode()) {
4151 EVT VT = Op.getValueType();
4152 SDValue ARMcc = Cond.getOperand(2);
4153 SDValue CCR = Cond.getOperand(3);
4154 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4155 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4155, __extension__ __PRETTY_FUNCTION__))
;
4156 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4157 }
4158 }
4159 }
4160
4161 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4162 // undefined bits before doing a full-word comparison with zero.
4163 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4164 DAG.getConstant(1, dl, Cond.getValueType()));
4165
4166 return DAG.getSelectCC(dl, Cond,
4167 DAG.getConstant(0, dl, Cond.getValueType()),
4168 SelectTrue, SelectFalse, ISD::SETNE);
4169}
4170
4171static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4172 bool &swpCmpOps, bool &swpVselOps) {
4173 // Start by selecting the GE condition code for opcodes that return true for
4174 // 'equality'
4175 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4176 CC == ISD::SETULE)
4177 CondCode = ARMCC::GE;
4178
4179 // and GT for opcodes that return false for 'equality'.
4180 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4181 CC == ISD::SETULT)
4182 CondCode = ARMCC::GT;
4183
4184 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4185 // to swap the compare operands.
4186 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4187 CC == ISD::SETULT)
4188 swpCmpOps = true;
4189
4190 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4191 // If we have an unordered opcode, we need to swap the operands to the VSEL
4192 // instruction (effectively negating the condition).
4193 //
4194 // This also has the effect of swapping which one of 'less' or 'greater'
4195 // returns true, so we also swap the compare operands. It also switches
4196 // whether we return true for 'equality', so we compensate by picking the
4197 // opposite condition code to our original choice.
4198 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4199 CC == ISD::SETUGT) {
4200 swpCmpOps = !swpCmpOps;
4201 swpVselOps = !swpVselOps;
4202 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4203 }
4204
4205 // 'ordered' is 'anything but unordered', so use the VS condition code and
4206 // swap the VSEL operands.
4207 if (CC == ISD::SETO) {
4208 CondCode = ARMCC::VS;
4209 swpVselOps = true;
4210 }
4211
4212 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4213 // code and swap the VSEL operands.
4214 if (CC == ISD::SETUNE) {
4215 CondCode = ARMCC::EQ;
4216 swpVselOps = true;
4217 }
4218}
4219
4220SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4221 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4222 SDValue Cmp, SelectionDAG &DAG) const {
4223 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4224 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4225 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4226 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4227 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4228
4229 SDValue TrueLow = TrueVal.getValue(0);
4230 SDValue TrueHigh = TrueVal.getValue(1);
4231 SDValue FalseLow = FalseVal.getValue(0);
4232 SDValue FalseHigh = FalseVal.getValue(1);
4233
4234 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4235 ARMcc, CCR, Cmp);
4236 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4237 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4238
4239 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4240 } else {
4241 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4242 Cmp);
4243 }
4244}
4245
4246static bool isGTorGE(ISD::CondCode CC) {
4247 return CC == ISD::SETGT || CC == ISD::SETGE;
4248}
4249
4250static bool isLTorLE(ISD::CondCode CC) {
4251 return CC == ISD::SETLT || CC == ISD::SETLE;
4252}
4253
4254// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4255// All of these conditions (and their <= and >= counterparts) will do:
4256// x < k ? k : x
4257// x > k ? x : k
4258// k < x ? x : k
4259// k > x ? k : x
4260static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4261 const SDValue TrueVal, const SDValue FalseVal,
4262 const ISD::CondCode CC, const SDValue K) {
4263 return (isGTorGE(CC) &&
4264 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4265 (isLTorLE(CC) &&
4266 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4267}
4268
4269// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4270static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4271 const SDValue TrueVal, const SDValue FalseVal,
4272 const ISD::CondCode CC, const SDValue K) {
4273 return (isGTorGE(CC) &&
4274 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4275 (isLTorLE(CC) &&
4276 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4277}
4278
4279// Check if two chained conditionals could be converted into SSAT or USAT.
4280//
4281// SSAT can replace a set of two conditional selectors that bound a number to an
4282// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4283//
4284// x < -k ? -k : (x > k ? k : x)
4285// x < -k ? -k : (x < k ? x : k)
4286// x > -k ? (x > k ? k : x) : -k
4287// x < k ? (x < -k ? -k : x) : k
4288// etc.
4289//
4290// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4291// a power of 2.
4292//
4293// It returns true if the conversion can be done, false otherwise.
4294// Additionally, the variable is returned in parameter V, the constant in K and
4295// usat is set to true if the conditional represents an unsigned saturation
4296static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4297 uint64_t &K, bool &usat) {
4298 SDValue LHS1 = Op.getOperand(0);
4299 SDValue RHS1 = Op.getOperand(1);
4300 SDValue TrueVal1 = Op.getOperand(2);
4301 SDValue FalseVal1 = Op.getOperand(3);
4302 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4303
4304 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4305 if (Op2.getOpcode() != ISD::SELECT_CC)
4306 return false;
4307
4308 SDValue LHS2 = Op2.getOperand(0);
4309 SDValue RHS2 = Op2.getOperand(1);
4310 SDValue TrueVal2 = Op2.getOperand(2);
4311 SDValue FalseVal2 = Op2.getOperand(3);
4312 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4313
4314 // Find out which are the constants and which are the variables
4315 // in each conditional
4316 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4317 ? &RHS1
4318 : nullptr;
4319 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4320 ? &RHS2
4321 : nullptr;
4322 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4323 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4324 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4325 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4326
4327 // We must detect cases where the original operations worked with 16- or
4328 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4329 // must work with sign-extended values but the select operations return
4330 // the original non-extended value.
4331 SDValue V2TmpReg = V2Tmp;
4332 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4333 V2TmpReg = V2Tmp->getOperand(0);
4334
4335 // Check that the registers and the constants have the correct values
4336 // in both conditionals
4337 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4338 V2TmpReg != V2)
4339 return false;
4340
4341 // Figure out which conditional is saturating the lower/upper bound.
4342 const SDValue *LowerCheckOp =
4343 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4344 ? &Op
4345 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4346 ? &Op2
4347 : nullptr;
4348 const SDValue *UpperCheckOp =
4349 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4350 ? &Op
4351 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4352 ? &Op2
4353 : nullptr;
4354
4355 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4356 return false;
4357
4358 // Check that the constant in the lower-bound check is
4359 // the opposite of the constant in the upper-bound check
4360 // in 1's complement.
4361 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4362 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4363 int64_t PosVal = std::max(Val1, Val2);
4364 int64_t NegVal = std::min(Val1, Val2);
4365
4366 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4367 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4368 isPowerOf2_64(PosVal + 1)) {
4369
4370 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4371 if (Val1 == ~Val2)
4372 usat = false;
4373 else if (NegVal == 0)
4374 usat = true;
4375 else
4376 return false;
4377
4378 V = V2;
4379 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4380
4381 return true;
4382 }
4383
4384 return false;
4385}
4386
4387SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4388 EVT VT = Op.getValueType();
4389 SDLoc dl(Op);
4390
4391 // Try to convert two saturating conditional selects into a single SSAT
4392 SDValue SatValue;
4393 uint64_t SatConstant;
4394 bool SatUSat;
4395 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4396 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4397 if (SatUSat)
4398 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4399 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4400 else
4401 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4402 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4403 }
4404
4405 SDValue LHS = Op.getOperand(0);
4406 SDValue RHS = Op.getOperand(1);
4407 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4408 SDValue TrueVal = Op.getOperand(2);
4409 SDValue FalseVal = Op.getOperand(3);
4410
4411 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4412 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4413 dl);
4414
4415 // If softenSetCCOperands only returned one value, we should compare it to
4416 // zero.
4417 if (!RHS.getNode()) {
4418 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4419 CC = ISD::SETNE;
4420 }
4421 }
4422
4423 if (LHS.getValueType() == MVT::i32) {
4424 // Try to generate VSEL on ARMv8.
4425 // The VSEL instruction can't use all the usual ARM condition
4426 // codes: it only has two bits to select the condition code, so it's
4427 // constrained to use only GE, GT, VS and EQ.
4428 //
4429 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4430 // swap the operands of the previous compare instruction (effectively
4431 // inverting the compare condition, swapping 'less' and 'greater') and
4432 // sometimes need to swap the operands to the VSEL (which inverts the
4433 // condition in the sense of firing whenever the previous condition didn't)
4434 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4435 TrueVal.getValueType() == MVT::f64)) {
4436 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4437 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4438 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4439 CC = ISD::getSetCCInverse(CC, true);
4440 std::swap(TrueVal, FalseVal);
4441 }
4442 }
4443
4444 SDValue ARMcc;
4445 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4446 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4447 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4448 }
4449
4450 ARMCC::CondCodes CondCode, CondCode2;
4451 bool InvalidOnQNaN;
4452 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4453
4454 // Try to generate VMAXNM/VMINNM on ARMv8.
4455 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4456 TrueVal.getValueType() == MVT::f64)) {
4457 bool swpCmpOps = false;
4458 bool swpVselOps = false;
4459 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4460
4461 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4462 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4463 if (swpCmpOps)
4464 std::swap(LHS, RHS);
4465 if (swpVselOps)
4466 std::swap(TrueVal, FalseVal);
4467 }
4468 }
4469
4470 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4471 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4472 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4473 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4474 if (CondCode2 != ARMCC::AL) {
4475 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4476 // FIXME: Needs another CMP because flag can have but one use.
4477 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4478 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4479 }
4480 return Result;
4481}
4482
4483/// canChangeToInt - Given the fp compare operand, return true if it is suitable
4484/// to morph to an integer compare sequence.
4485static bool canChangeToInt(SDValue Op, bool &SeenZero,
4486 const ARMSubtarget *Subtarget) {
4487 SDNode *N = Op.getNode();
4488 if (!N->hasOneUse())
4489 // Otherwise it requires moving the value from fp to integer registers.
4490 return false;
4491 if (!N->getNumValues())
4492 return false;
4493 EVT VT = Op.getValueType();
4494 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4495 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4496 // vmrs are very slow, e.g. cortex-a8.
4497 return false;
4498
4499 if (isFloatingPointZero(Op)) {
4500 SeenZero = true;
4501 return true;
4502 }
4503 return ISD::isNormalLoad(N);
4504}
4505
4506static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4507 if (isFloatingPointZero(Op))
4508 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4509
4510 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4511 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4512 Ld->getPointerInfo(), Ld->getAlignment(),
4513 Ld->getMemOperand()->getFlags());
4514
4515 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4515)
;
4516}
4517
4518static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4519 SDValue &RetVal1, SDValue &RetVal2) {
4520 SDLoc dl(Op);
4521
4522 if (isFloatingPointZero(Op)) {
4523 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4524 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4525 return;
4526 }
4527
4528 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4529 SDValue Ptr = Ld->getBasePtr();
4530 RetVal1 =
4531 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4532 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4533
4534 EVT PtrType = Ptr.getValueType();
4535 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4536 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4537 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4538 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4539 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4540 Ld->getMemOperand()->getFlags());
4541 return;
4542 }
4543
4544 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4544)
;
4545}
4546
4547/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4548/// f32 and even f64 comparisons to integer ones.
4549SDValue
4550ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4551 SDValue Chain = Op.getOperand(0);
4552 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4553 SDValue LHS = Op.getOperand(2);
4554 SDValue RHS = Op.getOperand(3);
4555 SDValue Dest = Op.getOperand(4);
4556 SDLoc dl(Op);
4557
4558 bool LHSSeenZero = false;
4559 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4560 bool RHSSeenZero = false;
4561 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4562 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4563 // If unsafe fp math optimization is enabled and there are no other uses of
4564 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4565 // to an integer comparison.
4566 if (CC == ISD::SETOEQ)
4567 CC = ISD::SETEQ;
4568 else if (CC == ISD::SETUNE)
4569 CC = ISD::SETNE;
4570
4571 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4572 SDValue ARMcc;
4573 if (LHS.getValueType() == MVT::f32) {
4574 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4575 bitcastf32Toi32(LHS, DAG), Mask);
4576 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4577 bitcastf32Toi32(RHS, DAG), Mask);
4578 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4579 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4580 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4581 Chain, Dest, ARMcc, CCR, Cmp);
4582 }
4583
4584 SDValue LHS1, LHS2;
4585 SDValue RHS1, RHS2;
4586 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4587 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4588 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4589 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4590 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4591 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4592 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4593 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4594 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4595 }
4596
4597 return SDValue();
4598}
4599
4600SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4601 SDValue Chain = Op.getOperand(0);
4602 SDValue Cond = Op.getOperand(1);
4603 SDValue Dest = Op.getOperand(2);
4604 SDLoc dl(Op);
4605
4606 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4607 // instruction.
4608 unsigned Opc = Cond.getOpcode();
4609 if (Cond.getResNo() == 1 &&
4610 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4611 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4612 // Only lower legal XALUO ops.
4613 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4614 return SDValue();
4615
4616 // The actual operation with overflow check.
4617 SDValue Value, OverflowCmp;
4618 SDValue ARMcc;
4619 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4620
4621 // Reverse the condition code.
4622 ARMCC::CondCodes CondCode =
4623 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4624 CondCode = ARMCC::getOppositeCondition(CondCode);
4625 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4626 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4627
4628 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4629 OverflowCmp);
4630 }
4631
4632 return SDValue();
4633}
4634
4635SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4636 SDValue Chain = Op.getOperand(0);
4637 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4638 SDValue LHS = Op.getOperand(2);
4639 SDValue RHS = Op.getOperand(3);
4640 SDValue Dest = Op.getOperand(4);
4641 SDLoc dl(Op);
4642
4643 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4644 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4645 dl);
4646
4647 // If softenSetCCOperands only returned one value, we should compare it to
4648 // zero.
4649 if (!RHS.getNode()) {
4650 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4651 CC = ISD::SETNE;
4652 }
4653 }
4654
4655 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4656 // instruction.
4657 unsigned Opc = LHS.getOpcode();
4658 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4659 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4660 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4661 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4662 // Only lower legal XALUO ops.
4663 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4664 return SDValue();
4665
4666 // The actual operation with overflow check.
4667 SDValue Value, OverflowCmp;
4668 SDValue ARMcc;
4669 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4670
4671 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4672 // Reverse the condition code.
4673 ARMCC::CondCodes CondCode =
4674 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4675 CondCode = ARMCC::getOppositeCondition(CondCode);
4676 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4677 }
4678 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4679
4680 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4681 OverflowCmp);
4682 }
4683
4684 if (LHS.getValueType() == MVT::i32) {
4685 SDValue ARMcc;
4686 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4687 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4688 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4689 Chain, Dest, ARMcc, CCR, Cmp);
4690 }
4691
4692 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64)(static_cast <bool> (LHS.getValueType() == MVT::f32 || LHS
.getValueType() == MVT::f64) ? void (0) : __assert_fail ("LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4692, __extension__ __PRETTY_FUNCTION__))
;
4693
4694 if (getTargetMachine().Options.UnsafeFPMath &&
4695 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4696 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4697 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4698 return Result;
4699 }
4700
4701 ARMCC::CondCodes CondCode, CondCode2;
4702 bool InvalidOnQNaN;
4703 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4704
4705 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4706 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4707 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4708 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4709 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4710 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4711 if (CondCode2 != ARMCC::AL) {
4712 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4713 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4714 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4715 }
4716 return Res;
4717}
4718
4719SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4720 SDValue Chain = Op.getOperand(0);
4721 SDValue Table = Op.getOperand(1);
4722 SDValue Index = Op.getOperand(2);
4723 SDLoc dl(Op);
4724
4725 EVT PTy = getPointerTy(DAG.getDataLayout());
4726 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4727 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4728 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4729 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4730 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4731 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4732 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4733 // which does another jump to the destination. This also makes it easier
4734 // to translate it to TBB / TBH later (Thumb2 only).
4735 // FIXME: This might not work if the function is extremely large.
4736 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4737 Addr, Op.getOperand(2), JTI);
4738 }
4739 if (isPositionIndependent() || Subtarget->isROPI()) {
4740 Addr =
4741 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4742 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4743 Chain = Addr.getValue(1);
4744 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4745 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4746 } else {
4747 Addr =
4748 DAG.getLoad(PTy, dl, Chain, Addr,
4749 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4750 Chain = Addr.getValue(1);
4751 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4752 }
4753}
4754
4755static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4756 EVT VT = Op.getValueType();
4757 SDLoc dl(Op);
4758
4759 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4760 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4761 return Op;
4762 return DAG.UnrollVectorOp(Op.getNode());
4763 }
4764
4765 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4766, __extension__ __PRETTY_FUNCTION__))
4766 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4766, __extension__ __PRETTY_FUNCTION__))
;
4767 if (VT != MVT::v4i16)
4768 return DAG.UnrollVectorOp(Op.getNode());
4769
4770 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
4771 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4772}
4773
4774SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4775 EVT VT = Op.getValueType();
4776 if (VT.isVector())
4777 return LowerVectorFP_TO_INT(Op, DAG);
4778 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4779 RTLIB::Libcall LC;
4780 if (Op.getOpcode() == ISD::FP_TO_SINT)
4781 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4782 Op.getValueType());
4783 else
4784 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4785 Op.getValueType());
4786 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4787 /*isSigned*/ false, SDLoc(Op)).first;
4788 }
4789
4790 return Op;
4791}
4792
4793static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4794 EVT VT = Op.getValueType();
4795 SDLoc dl(Op);
4796
4797 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4798 if (VT.getVectorElementType() == MVT::f32)
4799 return Op;
4800 return DAG.UnrollVectorOp(Op.getNode());
4801 }
4802
4803 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4804, __extension__ __PRETTY_FUNCTION__))
4804 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4804, __extension__ __PRETTY_FUNCTION__))
;
4805 if (VT != MVT::v4f32)
4806 return DAG.UnrollVectorOp(Op.getNode());
4807
4808 unsigned CastOpc;
4809 unsigned Opc;
4810 switch (Op.getOpcode()) {
4811 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4811)
;
4812 case ISD::SINT_TO_FP:
4813 CastOpc = ISD::SIGN_EXTEND;
4814 Opc = ISD::SINT_TO_FP;
4815 break;
4816 case ISD::UINT_TO_FP:
4817 CastOpc = ISD::ZERO_EXTEND;
4818 Opc = ISD::UINT_TO_FP;
4819 break;
4820 }
4821
4822 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4823 return DAG.getNode(Opc, dl, VT, Op);
4824}
4825
4826SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4827 EVT VT = Op.getValueType();
4828 if (VT.isVector())
4829 return LowerVectorINT_TO_FP(Op, DAG);
4830 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4831 RTLIB::Libcall LC;
4832 if (Op.getOpcode() == ISD::SINT_TO_FP)
4833 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4834 Op.getValueType());
4835 else
4836 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4837 Op.getValueType());
4838 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4839 /*isSigned*/ false, SDLoc(Op)).first;
4840 }
4841
4842 return Op;
4843}
4844
4845SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4846 // Implement fcopysign with a fabs and a conditional fneg.
4847 SDValue Tmp0 = Op.getOperand(0);
4848 SDValue Tmp1 = Op.getOperand(1);
4849 SDLoc dl(Op);
4850 EVT VT = Op.getValueType();
4851 EVT SrcVT = Tmp1.getValueType();
4852 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4853 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4854 bool UseNEON = !InGPR && Subtarget->hasNEON();
4855
4856 if (UseNEON) {
4857 // Use VBSL to copy the sign bit.
4858 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4859 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4860 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4861 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4862 if (VT == MVT::f64)
4863 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4864 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4865 DAG.getConstant(32, dl, MVT::i32));
4866 else /*if (VT == MVT::f32)*/
4867 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4868 if (SrcVT == MVT::f32) {
4869 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4870 if (VT == MVT::f64)
4871 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4872 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4873 DAG.getConstant(32, dl, MVT::i32));
4874 } else if (VT == MVT::f32)
4875 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4876 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4877 DAG.getConstant(32, dl, MVT::i32));
4878 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4879 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4880
4881 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4882 dl, MVT::i32);
4883 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4884 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4885 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4886
4887 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4888 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4889 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4890 if (VT == MVT::f32) {
4891 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4892 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4893 DAG.getConstant(0, dl, MVT::i32));
4894 } else {
4895 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4896 }
4897
4898 return Res;
4899 }
4900
4901 // Bitcast operand 1 to i32.
4902 if (SrcVT == MVT::f64)
4903 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4904 Tmp1).getValue(1);
4905 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4906
4907 // Or in the signbit with integer operations.
4908 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4909 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4910 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4911 if (VT == MVT::f32) {
4912 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4913 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4914 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4915 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4916 }
4917
4918 // f64: Or the high part with signbit and then combine two parts.
4919 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4920 Tmp0);
4921 SDValue Lo = Tmp0.getValue(0);
4922 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4923 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4924 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4925}
4926
4927SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4928 MachineFunction &MF = DAG.getMachineFunction();
4929 MachineFrameInfo &MFI = MF.getFrameInfo();
4930 MFI.setReturnAddressIsTaken(true);
4931
4932 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4933 return SDValue();
4934
4935 EVT VT = Op.getValueType();
4936 SDLoc dl(Op);
4937 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4938 if (Depth) {
4939 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4940 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
4941 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4942 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4943 MachinePointerInfo());
4944 }
4945
4946 // Return LR, which contains the return address. Mark it an implicit live-in.
4947 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4948 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4949}
4950
4951SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4952 const ARMBaseRegisterInfo &ARI =
4953 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4954 MachineFunction &MF = DAG.getMachineFunction();
4955 MachineFrameInfo &MFI = MF.getFrameInfo();
4956 MFI.setFrameAddressIsTaken(true);
4957
4958 EVT VT = Op.getValueType();
4959 SDLoc dl(Op); // FIXME probably not meaningful
4960 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4961 unsigned FrameReg = ARI.getFrameRegister(MF);
4962 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4963 while (Depth--)
4964 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4965 MachinePointerInfo());
4966 return FrameAddr;
4967}
4968
4969// FIXME? Maybe this could be a TableGen attribute on some registers and
4970// this table could be generated automatically from RegInfo.
4971unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4972 SelectionDAG &DAG) const {
4973 unsigned Reg = StringSwitch<unsigned>(RegName)
4974 .Case("sp", ARM::SP)
4975 .Default(0);
4976 if (Reg)
4977 return Reg;
4978 report_fatal_error(Twine("Invalid register name \""
4979 + StringRef(RegName) + "\"."));
4980}
4981
4982// Result is 64 bit value so split into two 32 bit values and return as a
4983// pair of values.
4984static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
4985 SelectionDAG &DAG) {
4986 SDLoc DL(N);
4987
4988 // This function is only supposed to be called for i64 type destination.
4989 assert(N->getValueType(0) == MVT::i64(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4990, __extension__ __PRETTY_FUNCTION__))
4990 && "ExpandREAD_REGISTER called for non-i64 type result.")(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 4990, __extension__ __PRETTY_FUNCTION__))
;
4991
4992 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
4993 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
4994 N->getOperand(0),
4995 N->getOperand(1));
4996
4997 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
4998 Read.getValue(1)));
4999 Results.push_back(Read.getOperand(0));
5000}
5001
5002/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5003/// When \p DstVT, the destination type of \p BC, is on the vector
5004/// register bank and the source of bitcast, \p Op, operates on the same bank,
5005/// it might be possible to combine them, such that everything stays on the
5006/// vector register bank.
5007/// \p return The node that would replace \p BT, if the combine
5008/// is possible.
5009static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5010 SelectionDAG &DAG) {
5011 SDValue Op = BC->getOperand(0);
5012 EVT DstVT = BC->getValueType(0);
5013
5014 // The only vector instruction that can produce a scalar (remember,
5015 // since the bitcast was about to be turned into VMOVDRR, the source
5016 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5017 // Moreover, we can do this combine only if there is one use.
5018 // Finally, if the destination type is not a vector, there is not
5019 // much point on forcing everything on the vector bank.
5020 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5021 !Op.hasOneUse())
5022 return SDValue();
5023
5024 // If the index is not constant, we will introduce an additional
5025 // multiply that will stick.
5026 // Give up in that case.
5027 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5028 if (!Index)
5029 return SDValue();
5030 unsigned DstNumElt = DstVT.getVectorNumElements();
5031
5032 // Compute the new index.
5033 const APInt &APIntIndex = Index->getAPIntValue();
5034 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5035 NewIndex *= APIntIndex;
5036 // Check if the new constant index fits into i32.
5037 if (NewIndex.getBitWidth() > 32)
5038 return SDValue();
5039
5040 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5041 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5042 SDLoc dl(Op);
5043 SDValue ExtractSrc = Op.getOperand(0);
5044 EVT VecVT = EVT::getVectorVT(
5045 *DAG.getContext(), DstVT.getScalarType(),
5046 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5047 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5048 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5049 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5050}
5051
5052/// ExpandBITCAST - If the target supports VFP, this function is called to
5053/// expand a bit convert where either the source or destination type is i64 to
5054/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5055/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5056/// vectors), since the legalizer won't know what to do with that.
5057static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5058 const ARMSubtarget *Subtarget) {
5059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5060 SDLoc dl(N);
5061 SDValue Op = N->getOperand(0);
5062
5063 // This function is only supposed to be called for i64 types, either as the
5064 // source or destination of the bit convert.
5065 EVT SrcVT = Op.getValueType();
5066 EVT DstVT = N->getValueType(0);
5067 const bool HasFullFP16 = Subtarget->hasFullFP16();
5068
5069 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5070 // FullFP16: half values are passed in S-registers, and we don't
5071 // need any of the bitcast and moves:
5072 //
5073 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5074 // t5: i32 = bitcast t2
5075 // t18: f16 = ARMISD::VMOVhr t5
5076 if (Op.getOpcode() != ISD::CopyFromReg ||
5077 Op.getValueType() != MVT::f32)
5078 return SDValue();
5079
5080 auto Move = N->use_begin();
5081 if (Move->getOpcode() != ARMISD::VMOVhr)
5082 return SDValue();
5083
5084 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5085 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5086 DAG.ReplaceAllUsesWith(*Move, &Copy);
5087 return Copy;
5088 }
5089
5090 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5091 if (!HasFullFP16)
5092 return SDValue();
5093 // SoftFP: read half-precision arguments:
5094 //
5095 // t2: i32,ch = ...
5096 // t7: i16 = truncate t2 <~~~~ Op
5097 // t8: f16 = bitcast t7 <~~~~ N
5098 //
5099 if (Op.getOperand(0).getValueType() == MVT::i32)
5100 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5101 MVT::f16, Op.getOperand(0));
5102
5103 return SDValue();
5104 }
5105
5106 // Half-precision return values
5107 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5108 if (!HasFullFP16)
5109 return SDValue();
5110 //
5111 // t11: f16 = fadd t8, t10
5112 // t12: i16 = bitcast t11 <~~~ SDNode N
5113 // t13: i32 = zero_extend t12
5114 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5115 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5116 //
5117 // transform this into:
5118 //
5119 // t20: i32 = ARMISD::VMOVrh t11
5120 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5121 //
5122 auto ZeroExtend = N->use_begin();
5123 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5124 ZeroExtend->getValueType(0) != MVT::i32)
5125 return SDValue();
5126
5127 auto Copy = ZeroExtend->use_begin();
5128 if (Copy->getOpcode() == ISD::CopyToReg &&
5129 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5130 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5131 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5132 return Cvt;
5133 }
5134 return SDValue();
5135 }
5136
5137 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5138 return SDValue();
5139
5140 // Turn i64->f64 into VMOVDRR.
5141 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5142 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5143 // if we can combine the bitcast with its source.
5144 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5145 return Val;
5146
5147 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5148 DAG.getConstant(0, dl, MVT::i32));
5149 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5150 DAG.getConstant(1, dl, MVT::i32));
5151 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5152 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5153 }
5154
5155 // Turn f64->i64 into VMOVRRD.
5156 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5157 SDValue Cvt;
5158 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5159 SrcVT.getVectorNumElements() > 1)
5160 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5161 DAG.getVTList(MVT::i32, MVT::i32),
5162 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5163 else
5164 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5165 DAG.getVTList(MVT::i32, MVT::i32), Op);
5166 // Merge the pieces into a single i64 value.
5167 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5168 }
5169
5170 return SDValue();
5171}
5172
5173/// getZeroVector - Returns a vector of specified type with all zero elements.
5174/// Zero vectors are used to represent vector negation and in those cases
5175/// will be implemented with the NEON VNEG instruction. However, VNEG does
5176/// not support i64 elements, so sometimes the zero vectors will need to be
5177/// explicitly constructed. Regardless, use a canonical VMOV to create the
5178/// zero vector.
5179static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5180 assert(VT.isVector() && "Expected a vector type")(static_cast <bool> (VT.isVector() && "Expected a vector type"
) ? void (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5180, __extension__ __PRETTY_FUNCTION__))
;
5181 // The canonical modified immediate encoding of a zero vector is....0!
5182 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5183 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5184 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5185 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5186}
5187
5188/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5189/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5190SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5191 SelectionDAG &DAG) const {
5192 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5192, __extension__ __PRETTY_FUNCTION__))
;
5193 EVT VT = Op.getValueType();
5194 unsigned VTBits = VT.getSizeInBits();
5195 SDLoc dl(Op);
5196 SDValue ShOpLo = Op.getOperand(0);
5197 SDValue ShOpHi = Op.getOperand(1);
5198 SDValue ShAmt = Op.getOperand(2);
5199 SDValue ARMcc;
5200 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5201 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5202
5203 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SRA_PARTS ||
Op.getOpcode() == ISD::SRL_PARTS) ? void (0) : __assert_fail
("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5203, __extension__ __PRETTY_FUNCTION__))
;
5204
5205 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5206 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5207 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5208 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5209 DAG.getConstant(VTBits, dl, MVT::i32));
5210 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5211 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5212 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5213 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5214 ISD::SETGE, ARMcc, DAG, dl);
5215 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5216 ARMcc, CCR, CmpLo);
5217
5218 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5219 SDValue HiBigShift = Opc == ISD::SRA
5220 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5221 DAG.getConstant(VTBits - 1, dl, VT))
5222 : DAG.getConstant(0, dl, VT);
5223 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5224 ISD::SETGE, ARMcc, DAG, dl);
5225 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5226 ARMcc, CCR, CmpHi);
5227
5228 SDValue Ops[2] = { Lo, Hi };
5229 return DAG.getMergeValues(Ops, dl);
5230}
5231
5232/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5233/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5234SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5235 SelectionDAG &DAG) const {
5236 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5236, __extension__ __PRETTY_FUNCTION__))
;
5237 EVT VT = Op.getValueType();
5238 unsigned VTBits = VT.getSizeInBits();
5239 SDLoc dl(Op);
5240 SDValue ShOpLo = Op.getOperand(0);
5241 SDValue ShOpHi = Op.getOperand(1);
5242 SDValue ShAmt = Op.getOperand(2);
5243 SDValue ARMcc;
5244 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5245
5246 assert(Op.getOpcode() == ISD::SHL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SHL_PARTS) ?
void (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5246, __extension__ __PRETTY_FUNCTION__))
;
5247 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5248 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5249 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5250 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5251 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5252
5253 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5254 DAG.getConstant(VTBits, dl, MVT::i32));
5255 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5256 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5257 ISD::SETGE, ARMcc, DAG, dl);
5258 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5259 ARMcc, CCR, CmpHi);
5260
5261 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5262 ISD::SETGE, ARMcc, DAG, dl);
5263 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5264 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5265 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5266
5267 SDValue Ops[2] = { Lo, Hi };
5268 return DAG.getMergeValues(Ops, dl);
5269}
5270
5271SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5272 SelectionDAG &DAG) const {
5273 // The rounding mode is in bits 23:22 of the FPSCR.
5274 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5275 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5276 // so that the shift + and get folded into a bitfield extract.
5277 SDLoc dl(Op);
5278 SDValue Ops[] = { DAG.getEntryNode(),
5279 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5280
5281 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5282 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5283 DAG.getConstant(1U << 22, dl, MVT::i32));
5284 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5285 DAG.getConstant(22, dl, MVT::i32));
5286 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5287 DAG.getConstant(3, dl, MVT::i32));
5288}
5289
5290static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5291 const ARMSubtarget *ST) {
5292 SDLoc dl(N);
5293 EVT VT = N->getValueType(0);
5294 if (VT.isVector()) {
5295 assert(ST->hasNEON())(static_cast <bool> (ST->hasNEON()) ? void (0) : __assert_fail
("ST->hasNEON()", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5295, __extension__ __PRETTY_FUNCTION__))
;
5296
5297 // Compute the least significant set bit: LSB = X & -X
5298 SDValue X = N->getOperand(0);
5299 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5300 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5301
5302 EVT ElemTy = VT.getVectorElementType();
5303
5304 if (ElemTy == MVT::i8) {
5305 // Compute with: cttz(x) = ctpop(lsb - 1)
5306 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5307 DAG.getTargetConstant(1, dl, ElemTy));
5308 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5309 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5310 }
5311
5312 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5313 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5314 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5315 unsigned NumBits = ElemTy.getSizeInBits();
5316 SDValue WidthMinus1 =
5317 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5318 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5319 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5320 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5321 }
5322
5323 // Compute with: cttz(x) = ctpop(lsb - 1)
5324
5325 // Since we can only compute the number of bits in a byte with vcnt.8, we
5326 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
5327 // and i64.
5328
5329 // Compute LSB - 1.
5330 SDValue Bits;
5331 if (ElemTy == MVT::i64) {
5332 // Load constant 0xffff'ffff'ffff'ffff to register.
5333 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5334 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5335 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5336 } else {
5337 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5338 DAG.getTargetConstant(1, dl, ElemTy));
5339 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5340 }
5341
5342 // Count #bits with vcnt.8.
5343 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5344 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
5345 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
5346
5347 // Gather the #bits with vpaddl (pairwise add.)
5348 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5349 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
5350 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5351 Cnt8);
5352 if (ElemTy == MVT::i16)
5353 return Cnt16;
5354
5355 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
5356 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
5357 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5358 Cnt16);
5359 if (ElemTy == MVT::i32)
5360 return Cnt32;
5361
5362 assert(ElemTy == MVT::i64)(static_cast <bool> (ElemTy == MVT::i64) ? void (0) : __assert_fail
("ElemTy == MVT::i64", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5362, __extension__ __PRETTY_FUNCTION__))
;
5363 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5364 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5365 Cnt32);
5366 return Cnt64;
5367 }
5368
5369 if (!ST->hasV6T2Ops())
5370 return SDValue();
5371
5372 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5373 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5374}
5375
5376/// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
5377/// for each 16-bit element from operand, repeated. The basic idea is to
5378/// leverage vcnt to get the 8-bit counts, gather and add the results.
5379///
5380/// Trace for v4i16:
5381/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5382/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
5383/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
5384/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
5385/// [b0 b1 b2 b3 b4 b5 b6 b7]
5386/// +[b1 b0 b3 b2 b5 b4 b7 b6]
5387/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
5388/// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
5389static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
5390 EVT VT = N->getValueType(0);
5391 SDLoc DL(N);
5392
5393 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5394 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
5395 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
5396 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
5397 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
5398 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
5399}
5400
5401/// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
5402/// bit-count for each 16-bit element from the operand. We need slightly
5403/// different sequencing for v4i16 and v8i16 to stay within NEON's available
5404/// 64/128-bit registers.
5405///
5406/// Trace for v4i16:
5407/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5408/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
5409/// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
5410/// v4i16:Extracted = [k0 k1 k2 k3 ]
5411static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
5412 EVT VT = N->getValueType(0);
5413 SDLoc DL(N);
5414
5415 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
5416 if (VT.is64BitVector()) {
5417 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
5418 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
5419 DAG.getIntPtrConstant(0, DL));
5420 } else {
5421 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
5422 BitCounts, DAG.getIntPtrConstant(0, DL));
5423 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
5424 }
5425}
5426
5427/// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
5428/// bit-count for each 32-bit element from the operand. The idea here is
5429/// to split the vector into 16-bit elements, leverage the 16-bit count
5430/// routine, and then combine the results.
5431///
5432/// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
5433/// input = [v0 v1 ] (vi: 32-bit elements)
5434/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
5435/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
5436/// vrev: N0 = [k1 k0 k3 k2 ]
5437/// [k0 k1 k2 k3 ]
5438/// N1 =+[k1 k0 k3 k2 ]
5439/// [k0 k2 k1 k3 ]
5440/// N2 =+[k1 k3 k0 k2 ]
5441/// [k0 k2 k1 k3 ]
5442/// Extended =+[k1 k3 k0 k2 ]
5443/// [k0 k2 ]
5444/// Extracted=+[k1 k3 ]
5445///
5446static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
5447 EVT VT = N->getValueType(0);
5448 SDLoc DL(N);
5449
5450 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5451
5452 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
5453 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
5454 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
5455 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5456 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
5457
5458 if (VT.is64BitVector()) {
5459 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
5460 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
5461 DAG.getIntPtrConstant(0, DL));
5462 } else {
5463 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
5464 DAG.getIntPtrConstant(0, DL));
5465 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
5466 }
5467}
5468
5469static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5470 const ARMSubtarget *ST) {
5471 EVT VT = N->getValueType(0);
5472
5473 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")(static_cast <bool> (ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? void (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5473, __extension__ __PRETTY_FUNCTION__))
;
5474 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5476, __extension__ __PRETTY_FUNCTION__))
5475 VT == MVT::v4i16 || VT == MVT::v8i16) &&(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5476, __extension__ __PRETTY_FUNCTION__))
5476 "Unexpected type for custom ctpop lowering")(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5476, __extension__ __PRETTY_FUNCTION__))
;
5477
5478 if (VT.getVectorElementType() == MVT::i32)
5479 return lowerCTPOP32BitElements(N, DAG);
5480 else
5481 return lowerCTPOP16BitElements(N, DAG);
5482}
5483
5484static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5485 const ARMSubtarget *ST) {
5486 EVT VT = N->getValueType(0);
5487 SDLoc dl(N);
5488
5489 if (!VT.isVector())
5490 return SDValue();
5491
5492 // Lower vector shifts on NEON to use VSHL.
5493 assert(ST->hasNEON() && "unexpected vector shift")(static_cast <bool> (ST->hasNEON() && "unexpected vector shift"
) ? void (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5493, __extension__ __PRETTY_FUNCTION__))
;
5494
5495 // Left shifts translate directly to the vshiftu intrinsic.
5496 if (N->getOpcode() == ISD::SHL)
5497 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5498 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5499 MVT::i32),
5500 N->getOperand(0), N->getOperand(1));
5501
5502 assert((N->getOpcode() == ISD::SRA ||(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5503, __extension__ __PRETTY_FUNCTION__))
5503 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5503, __extension__ __PRETTY_FUNCTION__))
;
5504
5505 // NEON uses the same intrinsics for both left and right shifts. For
5506 // right shifts, the shift amounts are negative, so negate the vector of
5507 // shift amounts.
5508 EVT ShiftVT = N->getOperand(1).getValueType();
5509 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5510 getZeroVector(ShiftVT, DAG, dl),
5511 N->getOperand(1));
5512 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5513 Intrinsic::arm_neon_vshifts :
5514 Intrinsic::arm_neon_vshiftu);
5515 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5516 DAG.getConstant(vshiftInt, dl, MVT::i32),
5517 N->getOperand(0), NegatedCount);
5518}
5519
5520static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5521 const ARMSubtarget *ST) {
5522 EVT VT = N->getValueType(0);
5523 SDLoc dl(N);
5524
5525 // We can get here for a node like i32 = ISD::SHL i32, i64
5526 if (VT != MVT::i64)
5527 return SDValue();
5528
5529 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5530, __extension__ __PRETTY_FUNCTION__))
5530 "Unknown shift to lower!")(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5530, __extension__ __PRETTY_FUNCTION__))
;
5531
5532 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5533 if (!isOneConstant(N->getOperand(1)))
5534 return SDValue();
5535
5536 // If we are in thumb mode, we don't have RRX.
5537 if (ST->isThumb1Only()) return SDValue();
5538
5539 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5540 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5541 DAG.getConstant(0, dl, MVT::i32));
5542 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5543 DAG.getConstant(1, dl, MVT::i32));
5544
5545 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5546 // captures the result into a carry flag.
5547 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5548 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5549
5550 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5551 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5552
5553 // Merge the pieces into a single i64 value.
5554 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5555}
5556
5557static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5558 SDValue TmpOp0, TmpOp1;
5559 bool Invert = false;
5560 bool Swap = false;
5561 unsigned Opc = 0;
5562
5563 SDValue Op0 = Op.getOperand(0);
5564 SDValue Op1 = Op.getOperand(1);
5565 SDValue CC = Op.getOperand(2);
5566 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5567 EVT VT = Op.getValueType();
5568 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5569 SDLoc dl(Op);
5570
5571 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5572 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5573 // Special-case integer 64-bit equality comparisons. They aren't legal,
5574 // but they can be lowered with a few vector instructions.
5575 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5576 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5577 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5578 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5579 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5580 DAG.getCondCode(ISD::SETEQ));
5581 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5582 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5583 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5584 if (SetCCOpcode == ISD::SETNE)
5585 Merged = DAG.getNOT(dl, Merged, CmpVT);
5586 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5587 return Merged;
5588 }
5589
5590 if (CmpVT.getVectorElementType() == MVT::i64)
5591 // 64-bit comparisons are not legal in general.
5592 return SDValue();
5593
5594 if (Op1.getValueType().isFloatingPoint()) {
5595 switch (SetCCOpcode) {
5596 default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5596)
;
5597 case ISD::SETUNE:
5598 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5599 case ISD::SETOEQ:
5600 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5601 case ISD::SETOLT:
5602 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5603 case ISD::SETOGT:
5604 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5605 case ISD::SETOLE:
5606 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5607 case ISD::SETOGE:
5608 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5609 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5610 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5611 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5612 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5613 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5614 case ISD::SETONE:
5615 // Expand this to (OLT | OGT).
5616 TmpOp0 = Op0;
5617 TmpOp1 = Op1;
5618 Opc = ISD::OR;
5619 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5620 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5621 break;
5622 case ISD::SETUO:
5623 Invert = true;
5624 LLVM_FALLTHROUGH[[clang::fallthrough]];
5625 case ISD::SETO:
5626 // Expand this to (OLT | OGE).
5627 TmpOp0 = Op0;
5628 TmpOp1 = Op1;
5629 Opc = ISD::OR;
5630 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5631 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5632 break;
5633 }
5634 } else {
5635 // Integer comparisons.
5636 switch (SetCCOpcode) {
5637 default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5637)
;
5638 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5639 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5640 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5641 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5642 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5643 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5644 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5645 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5646 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5647 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5648 }
5649
5650 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5651 if (Opc == ARMISD::VCEQ) {
5652 SDValue AndOp;
5653 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5654 AndOp = Op0;
5655 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5656 AndOp = Op1;
5657
5658 // Ignore bitconvert.
5659 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5660 AndOp = AndOp.getOperand(0);
5661
5662 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5663 Opc = ARMISD::VTST;
5664 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5665 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5666 Invert = !Invert;
5667 }
5668 }
5669 }
5670
5671 if (Swap)
5672 std::swap(Op0, Op1);
5673
5674 // If one of the operands is a constant vector zero, attempt to fold the
5675 // comparison to a specialized compare-against-zero form.
5676 SDValue SingleOp;
5677 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5678 SingleOp = Op0;
5679 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5680 if (Opc == ARMISD::VCGE)
5681 Opc = ARMISD::VCLEZ;
5682 else if (Opc == ARMISD::VCGT)
5683 Opc = ARMISD::VCLTZ;
5684 SingleOp = Op1;
5685 }
5686
5687 SDValue Result;
5688 if (SingleOp.getNode()) {
5689 switch (Opc) {
5690 case ARMISD::VCEQ:
5691 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5692 case ARMISD::VCGE:
5693 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5694 case ARMISD::VCLEZ:
5695 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5696 case ARMISD::VCGT:
5697 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5698 case ARMISD::VCLTZ:
5699 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5700 default:
5701 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5702 }
5703 } else {
5704 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5705 }
5706
5707 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5708
5709 if (Invert)
5710 Result = DAG.getNOT(dl, Result, VT);
5711
5712 return Result;
5713}
5714
5715static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
5716 SDValue LHS = Op.getOperand(0);
5717 SDValue RHS = Op.getOperand(1);
5718 SDValue Carry = Op.getOperand(2);
5719 SDValue Cond = Op.getOperand(3);
5720 SDLoc DL(Op);
5721
5722 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.")(static_cast <bool> (LHS.getSimpleValueType().isInteger
() && "SETCCE is integer only.") ? void (0) : __assert_fail
("LHS.getSimpleValueType().isInteger() && \"SETCCE is integer only.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5722, __extension__ __PRETTY_FUNCTION__))
;
5723
5724 assert(Carry.getOpcode() != ISD::CARRY_FALSE)(static_cast <bool> (Carry.getOpcode() != ISD::CARRY_FALSE
) ? void (0) : __assert_fail ("Carry.getOpcode() != ISD::CARRY_FALSE"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5724, __extension__ __PRETTY_FUNCTION__))
;
5725 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5726 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5727
5728 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5729 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5730 SDValue ARMcc = DAG.getConstant(
5731 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5732 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5733 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5734 Cmp.getValue(1), SDValue());
5735 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5736 CCR, Chain.getValue(1));
5737}
5738
5739/// isNEONModifiedImm - Check if the specified splat value corresponds to a
5740/// valid vector constant for a NEON instruction with a "modified immediate"
5741/// operand (e.g., VMOV). If so, return the encoded value.
5742static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5743 unsigned SplatBitSize, SelectionDAG &DAG,
5744 const SDLoc &dl, EVT &VT, bool is128Bits,
5745 NEONModImmType type) {
5746 unsigned OpCmode, Imm;
5747
5748 // SplatBitSize is set to the smallest size that splats the vector, so a
5749 // zero vector will always have SplatBitSize == 8. However, NEON modified
5750 // immediate instructions others than VMOV do not support the 8-bit encoding
5751 // of a zero vector, and the default encoding of zero is supposed to be the
5752 // 32-bit version.
5753 if (SplatBits == 0)
5754 SplatBitSize = 32;
5755
5756 switch (SplatBitSize) {
5757 case 8:
5758 if (type != VMOVModImm)
5759 return SDValue();
5760 // Any 1-byte value is OK. Op=0, Cmode=1110.
5761 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(static_cast <bool> ((SplatBits & ~0xff) == 0 &&
"one byte splat value is too big") ? void (0) : __assert_fail
("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5761, __extension__ __PRETTY_FUNCTION__))
;
5762 OpCmode = 0xe;
5763 Imm = SplatBits;
5764 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5765 break;
5766
5767 case 16:
5768 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5769 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5770 if ((SplatBits & ~0xff) == 0) {
5771 // Value = 0x00nn: Op=x, Cmode=100x.
5772 OpCmode = 0x8;
5773 Imm = SplatBits;
5774 break;
5775 }
5776 if ((SplatBits & ~0xff00) == 0) {
5777 // Value = 0xnn00: Op=x, Cmode=101x.
5778 OpCmode = 0xa;
5779 Imm = SplatBits >> 8;
5780 break;
5781 }
5782 return SDValue();
5783
5784 case 32:
5785 // NEON's 32-bit VMOV supports splat values where:
5786 // * only one byte is nonzero, or
5787 // * the least significant byte is 0xff and the second byte is nonzero, or
5788 // * the least significant 2 bytes are 0xff and the third is nonzero.
5789 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5790 if ((SplatBits & ~0xff) == 0) {
5791 // Value = 0x000000nn: Op=x, Cmode=000x.
5792 OpCmode = 0;
5793 Imm = SplatBits;
5794 break;
5795 }
5796 if ((SplatBits & ~0xff00) == 0) {
5797 // Value = 0x0000nn00: Op=x, Cmode=001x.
5798 OpCmode = 0x2;
5799 Imm = SplatBits >> 8;
5800 break;
5801 }
5802 if ((SplatBits & ~0xff0000) == 0) {
5803 // Value = 0x00nn0000: Op=x, Cmode=010x.
5804 OpCmode = 0x4;
5805 Imm = SplatBits >> 16;
5806 break;
5807 }
5808 if ((SplatBits & ~0xff000000) == 0) {
5809 // Value = 0xnn000000: Op=x, Cmode=011x.
5810 OpCmode = 0x6;
5811 Imm = SplatBits >> 24;
5812 break;
5813 }
5814
5815 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5816 if (type == OtherModImm) return SDValue();
5817
5818 if ((SplatBits & ~0xffff) == 0 &&
5819 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5820 // Value = 0x0000nnff: Op=x, Cmode=1100.
5821 OpCmode = 0xc;
5822 Imm = SplatBits >> 8;
5823 break;
5824 }
5825
5826 if ((SplatBits & ~0xffffff) == 0 &&
5827 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5828 // Value = 0x00nnffff: Op=x, Cmode=1101.
5829 OpCmode = 0xd;
5830 Imm = SplatBits >> 16;
5831 break;
5832 }
5833
5834 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5835 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5836 // VMOV.I32. A (very) minor optimization would be to replicate the value
5837 // and fall through here to test for a valid 64-bit splat. But, then the
5838 // caller would also need to check and handle the change in size.
5839 return SDValue();
5840
5841 case 64: {
5842 if (type != VMOVModImm)
5843 return SDValue();
5844 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5845 uint64_t BitMask = 0xff;
5846 uint64_t Val = 0;
5847 unsigned ImmMask = 1;
5848 Imm = 0;
5849 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5850 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5851 Val |= BitMask;
5852 Imm |= ImmMask;
5853 } else if ((SplatBits & BitMask) != 0) {
5854 return SDValue();
5855 }
5856 BitMask <<= 8;
5857 ImmMask <<= 1;
5858 }
5859
5860 if (DAG.getDataLayout().isBigEndian())
5861 // swap higher and lower 32 bit word
5862 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5863
5864 // Op=1, Cmode=1110.
5865 OpCmode = 0x1e;
5866 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5867 break;
5868 }
5869
5870 default:
5871 llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/Target/ARM/ARMISelLowering.cpp"
, 5871)
;
5872 }
5873
5874 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5875 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5876}
5877
5878SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5879 const ARMSubtarget *ST) const {
5880 bool IsDouble = Op.getValueType() == MVT::f64;
5881 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5882 const APFloat &FPVal = CFP->getValueAPF();
5883
5884 // Prevent floating-point constants from using literal loads
5885 // when execute-only is enabled.
5886 if (ST->genExecuteOnly()) {
5887 APInt INTVal = FPVal.bitcastToAPInt();
5888 SDLoc DL(CFP);
5889 if (IsDouble) {
5890 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
5891 SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
5892 if (!ST->isLittle())
5893 std::swap(Lo, Hi);
5894 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
5895 } else {
5896 return DAG.getConstant(INTVal, DL, MVT::i32);
5897 }
5898 }
5899
5900 if (!ST->hasVFP3())
5901 return SDValue();
5902
5903 // Use the default (constant pool) lowering for double constants when we have
5904 // an SP-only FPU
5905 if (IsDouble && Subtarget->isFPOnlySP())
5906 return SDValue();
5907
5908 // Try splatting with a VMOV.f32...
5909 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
5910
5911 if (ImmVal != -1) {
5912 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
5913 // We have code in place to select a valid ConstantFP already, no need to
5914 // do any mangling.
5915 return Op;
5916 }
5917
5918 // It's a float and we are trying to use NEON operations where
5919 // possible. Lower it to a splat followed by an extract.
5920 SDLoc DL(Op);
5921 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
5922 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
5923 NewVal);
5924 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
5925 DAG.getConstant(0, DL, MVT::i32));
5926 }
5927
5928 // The rest of our options are NEON only, make sure that's allowed before
5929 // proceeding..
5930 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
5931 return SDValue();
5932
5933 EVT VMovVT;
5934 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
5935
5936 // It wouldn't really be worth bothering for doubles except for one very
5937 // important value, which does happen to match: 0.0. So make sure we don't do
5938 // anything stupid.
5939 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
5940 return SDValue();
5941
5942 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
5943 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
5944 VMovVT, false, VMOVModImm);
5945 if (NewVal != SDValue()) {
5946 SDLoc DL(Op);
5947 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
5948 NewVal);
5949 if (IsDouble)
5950 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5951
5952 // It's a float: cast and extract a vector element.
5953 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5954 VecConstant);
5955 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5956 DAG.getConstant(0, DL, MVT::i32));
5957 }
5958
5959 // Finally, try a VMVN.i32
5960 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
5961 false, VMVNModImm);
5962 if (NewVal != SDValue()) {
5963 SDLoc DL(Op);
5964 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
5965
5966 if (IsDouble)