Bug Summary

File:lib/Target/ARM/ARMISelLowering.cpp
Warning:line 7116, column 14
1st function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn338205/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/ARM -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-29-043837-17923-1 -x c++ /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp -faddrsig
1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMISelLowering.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMPerfectShuffle.h"
22#include "ARMRegisterInfo.h"
23#include "ARMSelectionDAGInfo.h"
24#include "ARMSubtarget.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/RuntimeLibcalls.h"
57#include "llvm/CodeGen/SelectionDAG.h"
58#include "llvm/CodeGen/SelectionDAGNodes.h"
59#include "llvm/CodeGen/TargetInstrInfo.h"
60#include "llvm/CodeGen/TargetLowering.h"
61#include "llvm/CodeGen/TargetOpcodes.h"
62#include "llvm/CodeGen/TargetRegisterInfo.h"
63#include "llvm/CodeGen/TargetSubtargetInfo.h"
64#include "llvm/CodeGen/ValueTypes.h"
65#include "llvm/IR/Attributes.h"
66#include "llvm/IR/CallingConv.h"
67#include "llvm/IR/Constant.h"
68#include "llvm/IR/Constants.h"
69#include "llvm/IR/DataLayout.h"
70#include "llvm/IR/DebugLoc.h"
71#include "llvm/IR/DerivedTypes.h"
72#include "llvm/IR/Function.h"
73#include "llvm/IR/GlobalAlias.h"
74#include "llvm/IR/GlobalValue.h"
75#include "llvm/IR/GlobalVariable.h"
76#include "llvm/IR/IRBuilder.h"
77#include "llvm/IR/InlineAsm.h"
78#include "llvm/IR/Instruction.h"
79#include "llvm/IR/Instructions.h"
80#include "llvm/IR/IntrinsicInst.h"
81#include "llvm/IR/Intrinsics.h"
82#include "llvm/IR/Module.h"
83#include "llvm/IR/Type.h"
84#include "llvm/IR/User.h"
85#include "llvm/IR/Value.h"
86#include "llvm/MC/MCInstrDesc.h"
87#include "llvm/MC/MCInstrItineraries.h"
88#include "llvm/MC/MCRegisterInfo.h"
89#include "llvm/MC/MCSchedule.h"
90#include "llvm/Support/AtomicOrdering.h"
91#include "llvm/Support/BranchProbability.h"
92#include "llvm/Support/Casting.h"
93#include "llvm/Support/CodeGen.h"
94#include "llvm/Support/CommandLine.h"
95#include "llvm/Support/Compiler.h"
96#include "llvm/Support/Debug.h"
97#include "llvm/Support/ErrorHandling.h"
98#include "llvm/Support/KnownBits.h"
99#include "llvm/Support/MachineValueType.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116
117#define DEBUG_TYPE"arm-isel" "arm-isel"
118
119STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
120STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt", {0}, {false}
}
;
121STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments", {0}, {false
}}
;
122STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
123 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
;
124
125static cl::opt<bool>
126ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
128 cl::init(true));
129
130static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
133 "constant pools"),
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
138 cl::init(64));
139static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142 cl::init(128));
143
144// The APCS parameter registers.
145static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
147};
148
149void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157 }
158
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
169 } else {
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
174 }
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
187 }
188
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197 }
198
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211}
212
213void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216}
217
218void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221}
222
223ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
228
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
239 }
240
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
249 } LibraryCalls[] = {
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303 };
304
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
309 }
310 }
311 }
312
313 // These libcalls are not available in 32-bit.
314 setLibcallName(RTLIB::SHL_I128, nullptr);
315 setLibcallName(RTLIB::SRL_I128, nullptr);
316 setLibcallName(RTLIB::SRA_I128, nullptr);
317
318 // RTLIB
319 if (Subtarget->isAAPCS_ABI() &&
320 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
321 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
322 static const struct {
323 const RTLIB::Libcall Op;
324 const char * const Name;
325 const CallingConv::ID CC;
326 const ISD::CondCode Cond;
327 } LibraryCalls[] = {
328 // Double-precision floating-point arithmetic helper functions
329 // RTABI chapter 4.1.2, Table 2
330 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334
335 // Double-precision floating-point comparison helper functions
336 // RTABI chapter 4.1.2, Table 3
337 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
338 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
339 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
340 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
341 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
342 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
343 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
344 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
345
346 // Single-precision floating-point arithmetic helper functions
347 // RTABI chapter 4.1.2, Table 4
348 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
351 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
352
353 // Single-precision floating-point comparison helper functions
354 // RTABI chapter 4.1.2, Table 5
355 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
356 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
357 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
358 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
359 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
360 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
361 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
362 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
363
364 // Floating-point to integer conversions.
365 // RTABI chapter 4.1.2, Table 6
366 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
367 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
368 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
369 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
370 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
371 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
372 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
373 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374
375 // Conversions between floating types.
376 // RTABI chapter 4.1.2, Table 7
377 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380
381 // Integer to floating-point conversions.
382 // RTABI chapter 4.1.2, Table 8
383 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
384 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
388 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
389 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
390 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391
392 // Long long helper functions
393 // RTABI chapter 4.2, Table 9
394 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398
399 // Integer division functions
400 // RTABI chapter 4.3.1
401 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
406 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
407 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
408 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409 };
410
411 for (const auto &LC : LibraryCalls) {
412 setLibcallName(LC.Op, LC.Name);
413 setLibcallCallingConv(LC.Op, LC.CC);
414 if (LC.Cond != ISD::SETCC_INVALID)
415 setCmpLibcallCC(LC.Op, LC.Cond);
416 }
417
418 // EABI dependent RTLIB
419 if (TM.Options.EABIVersion == EABI::EABI4 ||
420 TM.Options.EABIVersion == EABI::EABI5) {
421 static const struct {
422 const RTLIB::Libcall Op;
423 const char *const Name;
424 const CallingConv::ID CC;
425 const ISD::CondCode Cond;
426 } MemOpsLibraryCalls[] = {
427 // Memory operations
428 // RTABI chapter 4.3.4
429 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
430 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
431 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
432 };
433
434 for (const auto &LC : MemOpsLibraryCalls) {
435 setLibcallName(LC.Op, LC.Name);
436 setLibcallCallingConv(LC.Op, LC.CC);
437 if (LC.Cond != ISD::SETCC_INVALID)
438 setCmpLibcallCC(LC.Op, LC.Cond);
439 }
440 }
441 }
442
443 if (Subtarget->isTargetWindows()) {
444 static const struct {
445 const RTLIB::Libcall Op;
446 const char * const Name;
447 const CallingConv::ID CC;
448 } LibraryCalls[] = {
449 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
450 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
451 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
452 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
453 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
454 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
455 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
456 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
457 };
458
459 for (const auto &LC : LibraryCalls) {
460 setLibcallName(LC.Op, LC.Name);
461 setLibcallCallingConv(LC.Op, LC.CC);
462 }
463 }
464
465 // Use divmod compiler-rt calls for iOS 5.0 and later.
466 if (Subtarget->isTargetMachO() &&
467 !(Subtarget->isTargetIOS() &&
468 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
469 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
470 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
471 }
472
473 // The half <-> float conversion functions are always soft-float on
474 // non-watchos platforms, but are needed for some targets which use a
475 // hard-float calling convention by default.
476 if (!Subtarget->isTargetWatchABI()) {
477 if (Subtarget->isAAPCS_ABI()) {
478 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
479 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
480 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
481 } else {
482 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
483 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
484 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
485 }
486 }
487
488 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
489 // a __gnu_ prefix (which is the default).
490 if (Subtarget->isTargetAEABI()) {
491 static const struct {
492 const RTLIB::Libcall Op;
493 const char * const Name;
494 const CallingConv::ID CC;
495 } LibraryCalls[] = {
496 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
497 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
498 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
499 };
500
501 for (const auto &LC : LibraryCalls) {
502 setLibcallName(LC.Op, LC.Name);
503 setLibcallCallingConv(LC.Op, LC.CC);
504 }
505 }
506
507 if (Subtarget->isThumb1Only())
508 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
509 else
510 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
511
512 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
513 !Subtarget->isThumb1Only()) {
514 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
515 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
516 }
517
518 if (Subtarget->hasFullFP16()) {
519 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
520 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
521 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
522 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
523
524 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
525 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
526 }
527
528 for (MVT VT : MVT::vector_valuetypes()) {
529 for (MVT InnerVT : MVT::vector_valuetypes()) {
530 setTruncStoreAction(VT, InnerVT, Expand);
531 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
532 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
533 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
534 }
535
536 setOperationAction(ISD::MULHS, VT, Expand);
537 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
538 setOperationAction(ISD::MULHU, VT, Expand);
539 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
540
541 setOperationAction(ISD::BSWAP, VT, Expand);
542 }
543
544 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
545 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
546
547 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
548 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
549
550 if (Subtarget->hasNEON()) {
551 addDRTypeForNEON(MVT::v2f32);
552 addDRTypeForNEON(MVT::v8i8);
553 addDRTypeForNEON(MVT::v4i16);
554 addDRTypeForNEON(MVT::v2i32);
555 addDRTypeForNEON(MVT::v1i64);
556
557 addQRTypeForNEON(MVT::v4f32);
558 addQRTypeForNEON(MVT::v2f64);
559 addQRTypeForNEON(MVT::v16i8);
560 addQRTypeForNEON(MVT::v8i16);
561 addQRTypeForNEON(MVT::v4i32);
562 addQRTypeForNEON(MVT::v2i64);
563
564 if (Subtarget->hasFullFP16()) {
565 addQRTypeForNEON(MVT::v8f16);
566 addDRTypeForNEON(MVT::v4f16);
567 }
568
569 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
570 // neither Neon nor VFP support any arithmetic operations on it.
571 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
572 // supported for v4f32.
573 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
574 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
575 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
576 // FIXME: Code duplication: FDIV and FREM are expanded always, see
577 // ARMTargetLowering::addTypeForNEON method for details.
578 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
579 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
580 // FIXME: Create unittest.
581 // In another words, find a way when "copysign" appears in DAG with vector
582 // operands.
583 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
584 // FIXME: Code duplication: SETCC has custom operation action, see
585 // ARMTargetLowering::addTypeForNEON method for details.
586 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
587 // FIXME: Create unittest for FNEG and for FABS.
588 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
589 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
590 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
591 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
592 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
593 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
594 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
595 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
596 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
597 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
598 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
599 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
600 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
601 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
602 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
603 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
604 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
605 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
606
607 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
608 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
609 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
610 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
611 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
612 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
613 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
614 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
615 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
616 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
617 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
618 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
619 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
620 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
621
622 // Mark v2f32 intrinsics.
623 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
624 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
625 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
626 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
627 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
628 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
629 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
630 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
631 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
632 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
633 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
634 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
635 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
636 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
637
638 // Neon does not support some operations on v1i64 and v2i64 types.
639 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
640 // Custom handling for some quad-vector types to detect VMULL.
641 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
642 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
643 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
644 // Custom handling for some vector types to avoid expensive expansions
645 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
646 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
647 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
648 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
649 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
650 // a destination type that is wider than the source, and nor does
651 // it have a FP_TO_[SU]INT instruction with a narrower destination than
652 // source.
653 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
654 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
655 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
656 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
657
658 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
659 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
660
661 // NEON does not have single instruction CTPOP for vectors with element
662 // types wider than 8-bits. However, custom lowering can leverage the
663 // v8i8/v16i8 vcnt instruction.
664 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
665 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
666 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
667 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
668 setOperationAction(ISD::CTPOP, MVT::v1i64, Expand);
669 setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
670
671 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
672 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
673
674 // NEON does not have single instruction CTTZ for vectors.
675 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
676 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
677 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
678 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
679
680 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
683 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
684
685 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
686 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
687 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
688 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
689
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
693 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
694
695 // NEON only has FMA instructions as of VFP4.
696 if (!Subtarget->hasVFP4()) {
697 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
698 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
699 }
700
701 setTargetDAGCombine(ISD::INTRINSIC_VOID);
702 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
703 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
704 setTargetDAGCombine(ISD::SHL);
705 setTargetDAGCombine(ISD::SRL);
706 setTargetDAGCombine(ISD::SRA);
707 setTargetDAGCombine(ISD::SIGN_EXTEND);
708 setTargetDAGCombine(ISD::ZERO_EXTEND);
709 setTargetDAGCombine(ISD::ANY_EXTEND);
710 setTargetDAGCombine(ISD::BUILD_VECTOR);
711 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
712 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
713 setTargetDAGCombine(ISD::STORE);
714 setTargetDAGCombine(ISD::FP_TO_SINT);
715 setTargetDAGCombine(ISD::FP_TO_UINT);
716 setTargetDAGCombine(ISD::FDIV);
717 setTargetDAGCombine(ISD::LOAD);
718
719 // It is legal to extload from v4i8 to v4i16 or v4i32.
720 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
721 MVT::v2i32}) {
722 for (MVT VT : MVT::integer_vector_valuetypes()) {
723 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
724 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
725 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
726 }
727 }
728 }
729
730 if (Subtarget->isFPOnlySP()) {
731 // When targeting a floating-point unit with only single-precision
732 // operations, f64 is legal for the few double-precision instructions which
733 // are present However, no double-precision operations other than moves,
734 // loads and stores are provided by the hardware.
735 setOperationAction(ISD::FADD, MVT::f64, Expand);
736 setOperationAction(ISD::FSUB, MVT::f64, Expand);
737 setOperationAction(ISD::FMUL, MVT::f64, Expand);
738 setOperationAction(ISD::FMA, MVT::f64, Expand);
739 setOperationAction(ISD::FDIV, MVT::f64, Expand);
740 setOperationAction(ISD::FREM, MVT::f64, Expand);
741 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FNEG, MVT::f64, Expand);
744 setOperationAction(ISD::FABS, MVT::f64, Expand);
745 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
746 setOperationAction(ISD::FSIN, MVT::f64, Expand);
747 setOperationAction(ISD::FCOS, MVT::f64, Expand);
748 setOperationAction(ISD::FPOW, MVT::f64, Expand);
749 setOperationAction(ISD::FLOG, MVT::f64, Expand);
750 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
751 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
752 setOperationAction(ISD::FEXP, MVT::f64, Expand);
753 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
754 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
755 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
756 setOperationAction(ISD::FRINT, MVT::f64, Expand);
757 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
758 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
759 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
760 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
761 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
762 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
763 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
764 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
765 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
766 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
767 }
768
769 computeRegisterProperties(Subtarget->getRegisterInfo());
770
771 // ARM does not have floating-point extending loads.
772 for (MVT VT : MVT::fp_valuetypes()) {
773 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
774 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
775 }
776
777 // ... or truncating stores
778 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
779 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
780 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
781
782 // ARM does not have i1 sign extending load.
783 for (MVT VT : MVT::integer_valuetypes())
784 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
785
786 // ARM supports all 4 flavors of integer indexed load / store.
787 if (!Subtarget->isThumb1Only()) {
788 for (unsigned im = (unsigned)ISD::PRE_INC;
789 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
790 setIndexedLoadAction(im, MVT::i1, Legal);
791 setIndexedLoadAction(im, MVT::i8, Legal);
792 setIndexedLoadAction(im, MVT::i16, Legal);
793 setIndexedLoadAction(im, MVT::i32, Legal);
794 setIndexedStoreAction(im, MVT::i1, Legal);
795 setIndexedStoreAction(im, MVT::i8, Legal);
796 setIndexedStoreAction(im, MVT::i16, Legal);
797 setIndexedStoreAction(im, MVT::i32, Legal);
798 }
799 } else {
800 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
801 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
802 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
803 }
804
805 setOperationAction(ISD::SADDO, MVT::i32, Custom);
806 setOperationAction(ISD::UADDO, MVT::i32, Custom);
807 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
808 setOperationAction(ISD::USUBO, MVT::i32, Custom);
809
810 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
811 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
812
813 // i64 operation support.
814 setOperationAction(ISD::MUL, MVT::i64, Expand);
815 setOperationAction(ISD::MULHU, MVT::i32, Expand);
816 if (Subtarget->isThumb1Only()) {
817 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
818 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
819 }
820 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
821 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
822 setOperationAction(ISD::MULHS, MVT::i32, Expand);
823
824 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
825 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
826 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
827 setOperationAction(ISD::SRL, MVT::i64, Custom);
828 setOperationAction(ISD::SRA, MVT::i64, Custom);
829 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
830
831 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
832 if (Subtarget->isThumb1Only()) {
833 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
834 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
835 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
836 }
837
838 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
839 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
840
841 // ARM does not have ROTL.
842 setOperationAction(ISD::ROTL, MVT::i32, Expand);
843 for (MVT VT : MVT::vector_valuetypes()) {
844 setOperationAction(ISD::ROTL, VT, Expand);
845 setOperationAction(ISD::ROTR, VT, Expand);
846 }
847 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
848 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
849 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
850 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
851
852 // @llvm.readcyclecounter requires the Performance Monitors extension.
853 // Default to the 0 expansion on unsupported platforms.
854 // FIXME: Technically there are older ARM CPUs that have
855 // implementation-specific ways of obtaining this information.
856 if (Subtarget->hasPerfMon())
857 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
858
859 // Only ARMv6 has BSWAP.
860 if (!Subtarget->hasV6Ops())
861 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
862
863 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
864 : Subtarget->hasDivideInARMMode();
865 if (!hasDivide) {
866 // These are expanded into libcalls if the cpu doesn't have HW divider.
867 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
868 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
869 }
870
871 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
872 setOperationAction(ISD::SDIV, MVT::i32, Custom);
873 setOperationAction(ISD::UDIV, MVT::i32, Custom);
874
875 setOperationAction(ISD::SDIV, MVT::i64, Custom);
876 setOperationAction(ISD::UDIV, MVT::i64, Custom);
877 }
878
879 setOperationAction(ISD::SREM, MVT::i32, Expand);
880 setOperationAction(ISD::UREM, MVT::i32, Expand);
881
882 // Register based DivRem for AEABI (RTABI 4.2)
883 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
884 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
885 Subtarget->isTargetWindows()) {
886 setOperationAction(ISD::SREM, MVT::i64, Custom);
887 setOperationAction(ISD::UREM, MVT::i64, Custom);
888 HasStandaloneRem = false;
889
890 if (Subtarget->isTargetWindows()) {
891 const struct {
892 const RTLIB::Libcall Op;
893 const char * const Name;
894 const CallingConv::ID CC;
895 } LibraryCalls[] = {
896 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
897 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
898 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
899 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
900
901 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
902 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
903 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
904 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
905 };
906
907 for (const auto &LC : LibraryCalls) {
908 setLibcallName(LC.Op, LC.Name);
909 setLibcallCallingConv(LC.Op, LC.CC);
910 }
911 } else {
912 const struct {
913 const RTLIB::Libcall Op;
914 const char * const Name;
915 const CallingConv::ID CC;
916 } LibraryCalls[] = {
917 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
918 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
919 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
920 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
921
922 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
923 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
924 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
925 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
926 };
927
928 for (const auto &LC : LibraryCalls) {
929 setLibcallName(LC.Op, LC.Name);
930 setLibcallCallingConv(LC.Op, LC.CC);
931 }
932 }
933
934 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
935 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
936 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
937 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
938 } else {
939 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
940 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
941 }
942
943 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
944 for (auto &VT : {MVT::f32, MVT::f64})
945 setOperationAction(ISD::FPOWI, VT, Custom);
946
947 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
948 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
949 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
950 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
951
952 setOperationAction(ISD::TRAP, MVT::Other, Legal);
953
954 // Use the default implementation.
955 setOperationAction(ISD::VASTART, MVT::Other, Custom);
956 setOperationAction(ISD::VAARG, MVT::Other, Expand);
957 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
958 setOperationAction(ISD::VAEND, MVT::Other, Expand);
959 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
960 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
961
962 if (Subtarget->isTargetWindows())
963 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
964 else
965 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
966
967 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
968 // the default expansion.
969 InsertFencesForAtomic = false;
970 if (Subtarget->hasAnyDataBarrier() &&
971 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
972 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
973 // to ldrex/strex loops already.
974 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
975 if (!Subtarget->isThumb() || !Subtarget->isMClass())
976 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
977
978 // On v8, we have particularly efficient implementations of atomic fences
979 // if they can be combined with nearby atomic loads and stores.
980 if (!Subtarget->hasV8Ops() || getTargetMachine().getOptLevel() == 0) {
981 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
982 InsertFencesForAtomic = true;
983 }
984 } else {
985 // If there's anything we can use as a barrier, go through custom lowering
986 // for ATOMIC_FENCE.
987 // If target has DMB in thumb, Fences can be inserted.
988 if (Subtarget->hasDataBarrier())
989 InsertFencesForAtomic = true;
990
991 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
992 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
993
994 // Set them all for expansion, which will force libcalls.
995 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
996 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
997 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
998 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
999 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1000 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1001 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1002 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1003 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1004 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1007 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1008 // Unordered/Monotonic case.
1009 if (!InsertFencesForAtomic) {
1010 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1011 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1012 }
1013 }
1014
1015 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1016
1017 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1018 if (!Subtarget->hasV6Ops()) {
1019 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1020 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1021 }
1022 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1023
1024 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1025 !Subtarget->isThumb1Only()) {
1026 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1027 // iff target supports vfp2.
1028 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1029 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1030 }
1031
1032 // We want to custom lower some of our intrinsics.
1033 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1034 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1035 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1036 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1037 if (Subtarget->useSjLjEH())
1038 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1039
1040 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1041 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1042 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1043 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1044 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1045 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1046 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1047 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1048 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1049 if (Subtarget->hasFullFP16()) {
1050 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1051 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1052 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1053 }
1054
1055 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1056
1057 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1058 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1059 if (Subtarget->hasFullFP16())
1060 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1061 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1062 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1063 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1064
1065 // We don't support sin/cos/fmod/copysign/pow
1066 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1067 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1068 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1069 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1070 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1071 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1072 setOperationAction(ISD::FREM, MVT::f64, Expand);
1073 setOperationAction(ISD::FREM, MVT::f32, Expand);
1074 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1075 !Subtarget->isThumb1Only()) {
1076 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1077 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1078 }
1079 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1080 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1081
1082 if (!Subtarget->hasVFP4()) {
1083 setOperationAction(ISD::FMA, MVT::f64, Expand);
1084 setOperationAction(ISD::FMA, MVT::f32, Expand);
1085 }
1086
1087 // Various VFP goodness
1088 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1089 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1090 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1091 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1092 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1093 }
1094
1095 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1096 if (!Subtarget->hasFP16()) {
1097 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1098 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1099 }
1100 }
1101
1102 // Use __sincos_stret if available.
1103 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1104 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1105 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1106 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1107 }
1108
1109 // FP-ARMv8 implements a lot of rounding-like FP operations.
1110 if (Subtarget->hasFPARMv8()) {
1111 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1112 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1113 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1114 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1115 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1116 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1117 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1118 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1119 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1120 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1121 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1122 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1123
1124 if (!Subtarget->isFPOnlySP()) {
1125 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1126 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1127 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1128 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1129 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1130 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1131 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1132 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1133 }
1134 }
1135
1136 if (Subtarget->hasNEON()) {
1137 // vmin and vmax aren't available in a scalar form, so we use
1138 // a NEON instruction with an undef lane instead.
1139 setOperationAction(ISD::FMINNAN, MVT::f16, Legal);
1140 setOperationAction(ISD::FMAXNAN, MVT::f16, Legal);
1141 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1142 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
1143 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1144 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
1145 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
1146 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
1147 }
1148
1149 // We have target-specific dag combine patterns for the following nodes:
1150 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1151 setTargetDAGCombine(ISD::ADD);
1152 setTargetDAGCombine(ISD::SUB);
1153 setTargetDAGCombine(ISD::MUL);
1154 setTargetDAGCombine(ISD::AND);
1155 setTargetDAGCombine(ISD::OR);
1156 setTargetDAGCombine(ISD::XOR);
1157
1158 if (Subtarget->hasV6Ops())
1159 setTargetDAGCombine(ISD::SRL);
1160
1161 setStackPointerRegisterToSaveRestore(ARM::SP);
1162
1163 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1164 !Subtarget->hasVFP2())
1165 setSchedulingPreference(Sched::RegPressure);
1166 else
1167 setSchedulingPreference(Sched::Hybrid);
1168
1169 //// temporary - rewrite interface to use type
1170 MaxStoresPerMemset = 8;
1171 MaxStoresPerMemsetOptSize = 4;
1172 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1173 MaxStoresPerMemcpyOptSize = 2;
1174 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1175 MaxStoresPerMemmoveOptSize = 2;
1176
1177 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1178 // are at least 4 bytes aligned.
1179 setMinStackArgumentAlignment(4);
1180
1181 // Prefer likely predicted branches to selects on out-of-order cores.
1182 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1183
1184 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1185}
1186
1187bool ARMTargetLowering::useSoftFloat() const {
1188 return Subtarget->useSoftFloat();
1189}
1190
1191// FIXME: It might make sense to define the representative register class as the
1192// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1193// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1194// SPR's representative would be DPR_VFP2. This should work well if register
1195// pressure tracking were modified such that a register use would increment the
1196// pressure of the register class's representative and all of it's super
1197// classes' representatives transitively. We have not implemented this because
1198// of the difficulty prior to coalescing of modeling operand register classes
1199// due to the common occurrence of cross class copies and subregister insertions
1200// and extractions.
1201std::pair<const TargetRegisterClass *, uint8_t>
1202ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1203 MVT VT) const {
1204 const TargetRegisterClass *RRC = nullptr;
1205 uint8_t Cost = 1;
1206 switch (VT.SimpleTy) {
1207 default:
1208 return TargetLowering::findRepresentativeClass(TRI, VT);
1209 // Use DPR as representative register class for all floating point
1210 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1211 // the cost is 1 for both f32 and f64.
1212 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1213 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1214 RRC = &ARM::DPRRegClass;
1215 // When NEON is used for SP, only half of the register file is available
1216 // because operations that define both SP and DP results will be constrained
1217 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1218 // coalescing by double-counting the SP regs. See the FIXME above.
1219 if (Subtarget->useNEONForSinglePrecisionFP())
1220 Cost = 2;
1221 break;
1222 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1223 case MVT::v4f32: case MVT::v2f64:
1224 RRC = &ARM::DPRRegClass;
1225 Cost = 2;
1226 break;
1227 case MVT::v4i64:
1228 RRC = &ARM::DPRRegClass;
1229 Cost = 4;
1230 break;
1231 case MVT::v8i64:
1232 RRC = &ARM::DPRRegClass;
1233 Cost = 8;
1234 break;
1235 }
1236 return std::make_pair(RRC, Cost);
1237}
1238
1239const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1240 switch ((ARMISD::NodeType)Opcode) {
1241 case ARMISD::FIRST_NUMBER: break;
1242 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1243 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1244 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1245 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1246 case ARMISD::CALL: return "ARMISD::CALL";
1247 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1248 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1249 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1250 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1251 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1252 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1253 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1254 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1255 case ARMISD::CMP: return "ARMISD::CMP";
1256 case ARMISD::CMN: return "ARMISD::CMN";
1257 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1258 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1259 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1260 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1261 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1262
1263 case ARMISD::CMOV: return "ARMISD::CMOV";
1264
1265 case ARMISD::SSAT: return "ARMISD::SSAT";
1266 case ARMISD::USAT: return "ARMISD::USAT";
1267
1268 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1269 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1270 case ARMISD::RRX: return "ARMISD::RRX";
1271
1272 case ARMISD::ADDC: return "ARMISD::ADDC";
1273 case ARMISD::ADDE: return "ARMISD::ADDE";
1274 case ARMISD::SUBC: return "ARMISD::SUBC";
1275 case ARMISD::SUBE: return "ARMISD::SUBE";
1276
1277 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1278 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1279 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1280 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1281 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1282
1283 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1284 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1285 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1286
1287 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1288
1289 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1290
1291 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1292
1293 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1294
1295 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1296
1297 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1298 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1299
1300 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1301 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1302 case ARMISD::VCGE: return "ARMISD::VCGE";
1303 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1304 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1305 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1306 case ARMISD::VCGT: return "ARMISD::VCGT";
1307 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1308 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1309 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1310 case ARMISD::VTST: return "ARMISD::VTST";
1311
1312 case ARMISD::VSHL: return "ARMISD::VSHL";
1313 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1314 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1315 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1316 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1317 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1318 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1319 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1320 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1321 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1322 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1323 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1324 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1325 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1326 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1327 case ARMISD::VSLI: return "ARMISD::VSLI";
1328 case ARMISD::VSRI: return "ARMISD::VSRI";
1329 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1330 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1331 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1332 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1333 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1334 case ARMISD::VDUP: return "ARMISD::VDUP";
1335 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1336 case ARMISD::VEXT: return "ARMISD::VEXT";
1337 case ARMISD::VREV64: return "ARMISD::VREV64";
1338 case ARMISD::VREV32: return "ARMISD::VREV32";
1339 case ARMISD::VREV16: return "ARMISD::VREV16";
1340 case ARMISD::VZIP: return "ARMISD::VZIP";
1341 case ARMISD::VUZP: return "ARMISD::VUZP";
1342 case ARMISD::VTRN: return "ARMISD::VTRN";
1343 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1344 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1345 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1346 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1347 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1348 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1349 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1350 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1351 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1352 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1353 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1354 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1355 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1356 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1357 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1358 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1359 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1360 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1361 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1362 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1363 case ARMISD::BFI: return "ARMISD::BFI";
1364 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1365 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1366 case ARMISD::VBSL: return "ARMISD::VBSL";
1367 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1368 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1369 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1370 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1371 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1372 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1373 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1374 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1375 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1376 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1377 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1378 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1379 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1380 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1381 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1382 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1383 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1384 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1385 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1386 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1387 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1388 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1389 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1390 }
1391 return nullptr;
1392}
1393
1394EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1395 EVT VT) const {
1396 if (!VT.isVector())
1397 return getPointerTy(DL);
1398 return VT.changeVectorElementTypeToInteger();
1399}
1400
1401/// getRegClassFor - Return the register class that should be used for the
1402/// specified value type.
1403const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1404 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1405 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1406 // load / store 4 to 8 consecutive D registers.
1407 if (Subtarget->hasNEON()) {
1408 if (VT == MVT::v4i64)
1409 return &ARM::QQPRRegClass;
1410 if (VT == MVT::v8i64)
1411 return &ARM::QQQQPRRegClass;
1412 }
1413 return TargetLowering::getRegClassFor(VT);
1414}
1415
1416// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1417// source/dest is aligned and the copy size is large enough. We therefore want
1418// to align such objects passed to memory intrinsics.
1419bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1420 unsigned &PrefAlign) const {
1421 if (!isa<MemIntrinsic>(CI))
1422 return false;
1423 MinSize = 8;
1424 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1425 // cycle faster than 4-byte aligned LDM.
1426 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1427 return true;
1428}
1429
1430// Create a fast isel object.
1431FastISel *
1432ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1433 const TargetLibraryInfo *libInfo) const {
1434 return ARM::createFastISel(funcInfo, libInfo);
1435}
1436
1437Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1438 unsigned NumVals = N->getNumValues();
1439 if (!NumVals)
1440 return Sched::RegPressure;
1441
1442 for (unsigned i = 0; i != NumVals; ++i) {
1443 EVT VT = N->getValueType(i);
1444 if (VT == MVT::Glue || VT == MVT::Other)
1445 continue;
1446 if (VT.isFloatingPoint() || VT.isVector())
1447 return Sched::ILP;
1448 }
1449
1450 if (!N->isMachineOpcode())
1451 return Sched::RegPressure;
1452
1453 // Load are scheduled for latency even if there instruction itinerary
1454 // is not available.
1455 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1456 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1457
1458 if (MCID.getNumDefs() == 0)
1459 return Sched::RegPressure;
1460 if (!Itins->isEmpty() &&
1461 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1462 return Sched::ILP;
1463
1464 return Sched::RegPressure;
1465}
1466
1467//===----------------------------------------------------------------------===//
1468// Lowering Code
1469//===----------------------------------------------------------------------===//
1470
1471static bool isSRL16(const SDValue &Op) {
1472 if (Op.getOpcode() != ISD::SRL)
1473 return false;
1474 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1475 return Const->getZExtValue() == 16;
1476 return false;
1477}
1478
1479static bool isSRA16(const SDValue &Op) {
1480 if (Op.getOpcode() != ISD::SRA)
1481 return false;
1482 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1483 return Const->getZExtValue() == 16;
1484 return false;
1485}
1486
1487static bool isSHL16(const SDValue &Op) {
1488 if (Op.getOpcode() != ISD::SHL)
1489 return false;
1490 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1491 return Const->getZExtValue() == 16;
1492 return false;
1493}
1494
1495// Check for a signed 16-bit value. We special case SRA because it makes it
1496// more simple when also looking for SRAs that aren't sign extending a
1497// smaller value. Without the check, we'd need to take extra care with
1498// checking order for some operations.
1499static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1500 if (isSRA16(Op))
1501 return isSHL16(Op.getOperand(0));
1502 return DAG.ComputeNumSignBits(Op) == 17;
1503}
1504
1505/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1506static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1507 switch (CC) {
1508 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1508)
;
1509 case ISD::SETNE: return ARMCC::NE;
1510 case ISD::SETEQ: return ARMCC::EQ;
1511 case ISD::SETGT: return ARMCC::GT;
1512 case ISD::SETGE: return ARMCC::GE;
1513 case ISD::SETLT: return ARMCC::LT;
1514 case ISD::SETLE: return ARMCC::LE;
1515 case ISD::SETUGT: return ARMCC::HI;
1516 case ISD::SETUGE: return ARMCC::HS;
1517 case ISD::SETULT: return ARMCC::LO;
1518 case ISD::SETULE: return ARMCC::LS;
1519 }
1520}
1521
1522/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1523static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1524 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1525 CondCode2 = ARMCC::AL;
1526 InvalidOnQNaN = true;
1527 switch (CC) {
1528 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1528)
;
1529 case ISD::SETEQ:
1530 case ISD::SETOEQ:
1531 CondCode = ARMCC::EQ;
1532 InvalidOnQNaN = false;
1533 break;
1534 case ISD::SETGT:
1535 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1536 case ISD::SETGE:
1537 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1538 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1539 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1540 case ISD::SETONE:
1541 CondCode = ARMCC::MI;
1542 CondCode2 = ARMCC::GT;
1543 InvalidOnQNaN = false;
1544 break;
1545 case ISD::SETO: CondCode = ARMCC::VC; break;
1546 case ISD::SETUO: CondCode = ARMCC::VS; break;
1547 case ISD::SETUEQ:
1548 CondCode = ARMCC::EQ;
1549 CondCode2 = ARMCC::VS;
1550 InvalidOnQNaN = false;
1551 break;
1552 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1553 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1554 case ISD::SETLT:
1555 case ISD::SETULT: CondCode = ARMCC::LT; break;
1556 case ISD::SETLE:
1557 case ISD::SETULE: CondCode = ARMCC::LE; break;
1558 case ISD::SETNE:
1559 case ISD::SETUNE:
1560 CondCode = ARMCC::NE;
1561 InvalidOnQNaN = false;
1562 break;
1563 }
1564}
1565
1566//===----------------------------------------------------------------------===//
1567// Calling Convention Implementation
1568//===----------------------------------------------------------------------===//
1569
1570#include "ARMGenCallingConv.inc"
1571
1572/// getEffectiveCallingConv - Get the effective calling convention, taking into
1573/// account presence of floating point hardware and calling convention
1574/// limitations, such as support for variadic functions.
1575CallingConv::ID
1576ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1577 bool isVarArg) const {
1578 switch (CC) {
1579 default:
1580 report_fatal_error("Unsupported calling convention");
1581 case CallingConv::ARM_AAPCS:
1582 case CallingConv::ARM_APCS:
1583 case CallingConv::GHC:
1584 return CC;
1585 case CallingConv::PreserveMost:
1586 return CallingConv::PreserveMost;
1587 case CallingConv::ARM_AAPCS_VFP:
1588 case CallingConv::Swift:
1589 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1590 case CallingConv::C:
1591 if (!Subtarget->isAAPCS_ABI())
1592 return CallingConv::ARM_APCS;
1593 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1594 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1595 !isVarArg)
1596 return CallingConv::ARM_AAPCS_VFP;
1597 else
1598 return CallingConv::ARM_AAPCS;
1599 case CallingConv::Fast:
1600 case CallingConv::CXX_FAST_TLS:
1601 if (!Subtarget->isAAPCS_ABI()) {
1602 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1603 return CallingConv::Fast;
1604 return CallingConv::ARM_APCS;
1605 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1606 return CallingConv::ARM_AAPCS_VFP;
1607 else
1608 return CallingConv::ARM_AAPCS;
1609 }
1610}
1611
1612CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1613 bool isVarArg) const {
1614 return CCAssignFnForNode(CC, false, isVarArg);
1615}
1616
1617CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1618 bool isVarArg) const {
1619 return CCAssignFnForNode(CC, true, isVarArg);
1620}
1621
1622/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1623/// CallingConvention.
1624CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1625 bool Return,
1626 bool isVarArg) const {
1627 switch (getEffectiveCallingConv(CC, isVarArg)) {
1628 default:
1629 report_fatal_error("Unsupported calling convention");
1630 case CallingConv::ARM_APCS:
1631 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1632 case CallingConv::ARM_AAPCS:
1633 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1634 case CallingConv::ARM_AAPCS_VFP:
1635 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1636 case CallingConv::Fast:
1637 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1638 case CallingConv::GHC:
1639 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1640 case CallingConv::PreserveMost:
1641 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1642 }
1643}
1644
1645/// LowerCallResult - Lower the result values of a call into the
1646/// appropriate copies out of appropriate physical registers.
1647SDValue ARMTargetLowering::LowerCallResult(
1648 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1649 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1650 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1651 SDValue ThisVal) const {
1652 // Assign locations to each value returned by this call.
1653 SmallVector<CCValAssign, 16> RVLocs;
1654 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1655 *DAG.getContext());
1656 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1657
1658 // Copy all of the result registers out of their specified physreg.
1659 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1660 CCValAssign VA = RVLocs[i];
1661
1662 // Pass 'this' value directly from the argument to return value, to avoid
1663 // reg unit interference
1664 if (i == 0 && isThisReturn) {
1665 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1666, __extension__ __PRETTY_FUNCTION__))
1666 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1666, __extension__ __PRETTY_FUNCTION__))
;
1667 InVals.push_back(ThisVal);
1668 continue;
1669 }
1670
1671 SDValue Val;
1672 if (VA.needsCustom()) {
1673 // Handle f64 or half of a v2f64.
1674 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1675 InFlag);
1676 Chain = Lo.getValue(1);
1677 InFlag = Lo.getValue(2);
1678 VA = RVLocs[++i]; // skip ahead to next loc
1679 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1680 InFlag);
1681 Chain = Hi.getValue(1);
1682 InFlag = Hi.getValue(2);
1683 if (!Subtarget->isLittle())
1684 std::swap (Lo, Hi);
1685 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1686
1687 if (VA.getLocVT() == MVT::v2f64) {
1688 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1689 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1690 DAG.getConstant(0, dl, MVT::i32));
1691
1692 VA = RVLocs[++i]; // skip ahead to next loc
1693 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1694 Chain = Lo.getValue(1);
1695 InFlag = Lo.getValue(2);
1696 VA = RVLocs[++i]; // skip ahead to next loc
1697 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1698 Chain = Hi.getValue(1);
1699 InFlag = Hi.getValue(2);
1700 if (!Subtarget->isLittle())
1701 std::swap (Lo, Hi);
1702 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1703 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1704 DAG.getConstant(1, dl, MVT::i32));
1705 }
1706 } else {
1707 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1708 InFlag);
1709 Chain = Val.getValue(1);
1710 InFlag = Val.getValue(2);
1711 }
1712
1713 switch (VA.getLocInfo()) {
1714 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1714)
;
1715 case CCValAssign::Full: break;
1716 case CCValAssign::BCvt:
1717 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1718 break;
1719 }
1720
1721 InVals.push_back(Val);
1722 }
1723
1724 return Chain;
1725}
1726
1727/// LowerMemOpCallTo - Store the argument to the stack.
1728SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1729 SDValue Arg, const SDLoc &dl,
1730 SelectionDAG &DAG,
1731 const CCValAssign &VA,
1732 ISD::ArgFlagsTy Flags) const {
1733 unsigned LocMemOffset = VA.getLocMemOffset();
1734 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1735 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1736 StackPtr, PtrOff);
1737 return DAG.getStore(
1738 Chain, dl, Arg, PtrOff,
1739 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1740}
1741
1742void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1743 SDValue Chain, SDValue &Arg,
1744 RegsToPassVector &RegsToPass,
1745 CCValAssign &VA, CCValAssign &NextVA,
1746 SDValue &StackPtr,
1747 SmallVectorImpl<SDValue> &MemOpChains,
1748 ISD::ArgFlagsTy Flags) const {
1749 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1750 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1751 unsigned id = Subtarget->isLittle() ? 0 : 1;
1752 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1753
1754 if (NextVA.isRegLoc())
1755 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1756 else {
1757 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1757, __extension__ __PRETTY_FUNCTION__))
;
1758 if (!StackPtr.getNode())
1759 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1760 getPointerTy(DAG.getDataLayout()));
1761
1762 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1763 dl, DAG, NextVA,
1764 Flags));
1765 }
1766}
1767
1768/// LowerCall - Lowering a call into a callseq_start <-
1769/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1770/// nodes.
1771SDValue
1772ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1773 SmallVectorImpl<SDValue> &InVals) const {
1774 SelectionDAG &DAG = CLI.DAG;
1775 SDLoc &dl = CLI.DL;
1776 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1777 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1778 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1779 SDValue Chain = CLI.Chain;
1780 SDValue Callee = CLI.Callee;
1781 bool &isTailCall = CLI.IsTailCall;
1782 CallingConv::ID CallConv = CLI.CallConv;
1783 bool doesNotRet = CLI.DoesNotReturn;
1784 bool isVarArg = CLI.IsVarArg;
1785
1786 MachineFunction &MF = DAG.getMachineFunction();
1787 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1788 bool isThisReturn = false;
1789 bool isSibCall = false;
1790 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1791
1792 // Disable tail calls if they're not supported.
1793 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1794 isTailCall = false;
1795
1796 if (isTailCall) {
1797 // Check if it's really possible to do a tail call.
1798 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1799 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1800 Outs, OutVals, Ins, DAG);
1801 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1802 report_fatal_error("failed to perform tail call elimination on a call "
1803 "site marked musttail");
1804 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1805 // detected sibcalls.
1806 if (isTailCall) {
1807 ++NumTailCalls;
1808 isSibCall = true;
1809 }
1810 }
1811
1812 // Analyze operands of the call, assigning locations to each operand.
1813 SmallVector<CCValAssign, 16> ArgLocs;
1814 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1815 *DAG.getContext());
1816 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1817
1818 // Get a count of how many bytes are to be pushed on the stack.
1819 unsigned NumBytes = CCInfo.getNextStackOffset();
1820
1821 // For tail calls, memory operands are available in our caller's stack.
1822 if (isSibCall)
1823 NumBytes = 0;
1824
1825 // Adjust the stack pointer for the new arguments...
1826 // These operations are automatically eliminated by the prolog/epilog pass
1827 if (!isSibCall)
1828 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1829
1830 SDValue StackPtr =
1831 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1832
1833 RegsToPassVector RegsToPass;
1834 SmallVector<SDValue, 8> MemOpChains;
1835
1836 // Walk the register/memloc assignments, inserting copies/loads. In the case
1837 // of tail call optimization, arguments are handled later.
1838 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1839 i != e;
1840 ++i, ++realArgIdx) {
1841 CCValAssign &VA = ArgLocs[i];
1842 SDValue Arg = OutVals[realArgIdx];
1843 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1844 bool isByVal = Flags.isByVal();
1845
1846 // Promote the value if needed.
1847 switch (VA.getLocInfo()) {
1848 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1848)
;
1849 case CCValAssign::Full: break;
1850 case CCValAssign::SExt:
1851 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1852 break;
1853 case CCValAssign::ZExt:
1854 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1855 break;
1856 case CCValAssign::AExt:
1857 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1858 break;
1859 case CCValAssign::BCvt:
1860 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1861 break;
1862 }
1863
1864 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1865 if (VA.needsCustom()) {
1866 if (VA.getLocVT() == MVT::v2f64) {
1867 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1868 DAG.getConstant(0, dl, MVT::i32));
1869 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1870 DAG.getConstant(1, dl, MVT::i32));
1871
1872 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1873 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1874
1875 VA = ArgLocs[++i]; // skip ahead to next loc
1876 if (VA.isRegLoc()) {
1877 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1878 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1879 } else {
1880 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1880, __extension__ __PRETTY_FUNCTION__))
;
1881
1882 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1883 dl, DAG, VA, Flags));
1884 }
1885 } else {
1886 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1887 StackPtr, MemOpChains, Flags);
1888 }
1889 } else if (VA.isRegLoc()) {
1890 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1891 Outs[0].VT == MVT::i32) {
1892 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1893, __extension__ __PRETTY_FUNCTION__))
1893 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1893, __extension__ __PRETTY_FUNCTION__))
;
1894 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1895, __extension__ __PRETTY_FUNCTION__))
1895 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1895, __extension__ __PRETTY_FUNCTION__))
;
1896 isThisReturn = true;
1897 }
1898 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1899 } else if (isByVal) {
1900 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1900, __extension__ __PRETTY_FUNCTION__))
;
1901 unsigned offset = 0;
1902
1903 // True if this byval aggregate will be split between registers
1904 // and memory.
1905 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1906 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1907
1908 if (CurByValIdx < ByValArgsCount) {
1909
1910 unsigned RegBegin, RegEnd;
1911 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1912
1913 EVT PtrVT =
1914 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1915 unsigned int i, j;
1916 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1917 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1918 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1919 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1920 MachinePointerInfo(),
1921 DAG.InferPtrAlignment(AddArg));
1922 MemOpChains.push_back(Load.getValue(1));
1923 RegsToPass.push_back(std::make_pair(j, Load));
1924 }
1925
1926 // If parameter size outsides register area, "offset" value
1927 // helps us to calculate stack slot for remained part properly.
1928 offset = RegEnd - RegBegin;
1929
1930 CCInfo.nextInRegsParam();
1931 }
1932
1933 if (Flags.getByValSize() > 4*offset) {
1934 auto PtrVT = getPointerTy(DAG.getDataLayout());
1935 unsigned LocMemOffset = VA.getLocMemOffset();
1936 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1937 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1938 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1939 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1940 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1941 MVT::i32);
1942 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1943 MVT::i32);
1944
1945 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1946 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1947 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1948 Ops));
1949 }
1950 } else if (!isSibCall) {
1951 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 1951, __extension__ __PRETTY_FUNCTION__))
;
1952
1953 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1954 dl, DAG, VA, Flags));
1955 }
1956 }
1957
1958 if (!MemOpChains.empty())
1959 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1960
1961 // Build a sequence of copy-to-reg nodes chained together with token chain
1962 // and flag operands which copy the outgoing args into the appropriate regs.
1963 SDValue InFlag;
1964 // Tail call byval lowering might overwrite argument registers so in case of
1965 // tail call optimization the copies to registers are lowered later.
1966 if (!isTailCall)
1967 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1968 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1969 RegsToPass[i].second, InFlag);
1970 InFlag = Chain.getValue(1);
1971 }
1972
1973 // For tail calls lower the arguments to the 'real' stack slot.
1974 if (isTailCall) {
1975 // Force all the incoming stack arguments to be loaded from the stack
1976 // before any new outgoing arguments are stored to the stack, because the
1977 // outgoing stack slots may alias the incoming argument stack slots, and
1978 // the alias isn't otherwise explicit. This is slightly more conservative
1979 // than necessary, because it means that each store effectively depends
1980 // on every argument instead of just those arguments it would clobber.
1981
1982 // Do not flag preceding copytoreg stuff together with the following stuff.
1983 InFlag = SDValue();
1984 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1985 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1986 RegsToPass[i].second, InFlag);
1987 InFlag = Chain.getValue(1);
1988 }
1989 InFlag = SDValue();
1990 }
1991
1992 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1993 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1994 // node so that legalize doesn't hack it.
1995 bool isDirect = false;
1996
1997 const TargetMachine &TM = getTargetMachine();
1998 const Module *Mod = MF.getFunction().getParent();
1999 const GlobalValue *GV = nullptr;
2000 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2001 GV = G->getGlobal();
2002 bool isStub =
2003 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2004
2005 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2006 bool isLocalARMFunc = false;
2007 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2008 auto PtrVt = getPointerTy(DAG.getDataLayout());
2009
2010 if (Subtarget->genLongCalls()) {
2011 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2012, __extension__ __PRETTY_FUNCTION__))
2012 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2012, __extension__ __PRETTY_FUNCTION__))
;
2013 // Handle a global address or an external symbol. If it's not one of
2014 // those, the target's already in a register, so we don't need to do
2015 // anything extra.
2016 if (isa<GlobalAddressSDNode>(Callee)) {
2017 // Create a constant pool entry for the callee address
2018 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2019 ARMConstantPoolValue *CPV =
2020 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2021
2022 // Get the address of the callee into a register
2023 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2024 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2025 Callee = DAG.getLoad(
2026 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2027 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2028 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2029 const char *Sym = S->getSymbol();
2030
2031 // Create a constant pool entry for the callee address
2032 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2033 ARMConstantPoolValue *CPV =
2034 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2035 ARMPCLabelIndex, 0);
2036 // Get the address of the callee into a register
2037 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2038 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2039 Callee = DAG.getLoad(
2040 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2041 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2042 }
2043 } else if (isa<GlobalAddressSDNode>(Callee)) {
2044 // If we're optimizing for minimum size and the function is called three or
2045 // more times in this block, we can improve codesize by calling indirectly
2046 // as BLXr has a 16-bit encoding.
2047 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2048 auto *BB = CLI.CS.getParent();
2049 bool PreferIndirect =
2050 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2051 count_if(GV->users(), [&BB](const User *U) {
2052 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2053 }) > 2;
2054
2055 if (!PreferIndirect) {
2056 isDirect = true;
2057 bool isDef = GV->isStrongDefinitionForLinker();
2058
2059 // ARM call to a local ARM function is predicable.
2060 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2061 // tBX takes a register source operand.
2062 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2063 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2063, __extension__ __PRETTY_FUNCTION__))
;
2064 Callee = DAG.getNode(
2065 ARMISD::WrapperPIC, dl, PtrVt,
2066 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2067 Callee = DAG.getLoad(
2068 PtrVt, dl, DAG.getEntryNode(), Callee,
2069 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2070 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2071 MachineMemOperand::MOInvariant);
2072 } else if (Subtarget->isTargetCOFF()) {
2073 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2074, __extension__ __PRETTY_FUNCTION__))
2074 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2074, __extension__ __PRETTY_FUNCTION__))
;
2075 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2076 ? ARMII::MO_DLLIMPORT
2077 : ARMII::MO_NO_FLAG;
2078 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2079 TargetFlags);
2080 if (GV->hasDLLImportStorageClass())
2081 Callee =
2082 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2083 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2084 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2085 } else {
2086 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2087 }
2088 }
2089 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2090 isDirect = true;
2091 // tBX takes a register source operand.
2092 const char *Sym = S->getSymbol();
2093 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2094 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2095 ARMConstantPoolValue *CPV =
2096 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2097 ARMPCLabelIndex, 4);
2098 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2099 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2100 Callee = DAG.getLoad(
2101 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2102 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2103 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2104 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2105 } else {
2106 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2107 }
2108 }
2109
2110 // FIXME: handle tail calls differently.
2111 unsigned CallOpc;
2112 if (Subtarget->isThumb()) {
2113 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2114 CallOpc = ARMISD::CALL_NOLINK;
2115 else
2116 CallOpc = ARMISD::CALL;
2117 } else {
2118 if (!isDirect && !Subtarget->hasV5TOps())
2119 CallOpc = ARMISD::CALL_NOLINK;
2120 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2121 // Emit regular call when code size is the priority
2122 !MF.getFunction().optForMinSize())
2123 // "mov lr, pc; b _foo" to avoid confusing the RSP
2124 CallOpc = ARMISD::CALL_NOLINK;
2125 else
2126 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2127 }
2128
2129 std::vector<SDValue> Ops;
2130 Ops.push_back(Chain);
2131 Ops.push_back(Callee);
2132
2133 // Add argument registers to the end of the list so that they are known live
2134 // into the call.
2135 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2136 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2137 RegsToPass[i].second.getValueType()));
2138
2139 // Add a register mask operand representing the call-preserved registers.
2140 if (!isTailCall) {
2141 const uint32_t *Mask;
2142 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2143 if (isThisReturn) {
2144 // For 'this' returns, use the R0-preserving mask if applicable
2145 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2146 if (!Mask) {
2147 // Set isThisReturn to false if the calling convention is not one that
2148 // allows 'returned' to be modeled in this way, so LowerCallResult does
2149 // not try to pass 'this' straight through
2150 isThisReturn = false;
2151 Mask = ARI->getCallPreservedMask(MF, CallConv);
2152 }
2153 } else
2154 Mask = ARI->getCallPreservedMask(MF, CallConv);
2155
2156 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2156, __extension__ __PRETTY_FUNCTION__))
;
2157 Ops.push_back(DAG.getRegisterMask(Mask));
2158 }
2159
2160 if (InFlag.getNode())
2161 Ops.push_back(InFlag);
2162
2163 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2164 if (isTailCall) {
2165 MF.getFrameInfo().setHasTailCall();
2166 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2167 }
2168
2169 // Returns a chain and a flag for retval copy to use.
2170 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2171 InFlag = Chain.getValue(1);
2172
2173 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2174 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2175 if (!Ins.empty())
2176 InFlag = Chain.getValue(1);
2177
2178 // Handle result values, copying them out of physregs into vregs that we
2179 // return.
2180 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2181 InVals, isThisReturn,
2182 isThisReturn ? OutVals[0] : SDValue());
2183}
2184
2185/// HandleByVal - Every parameter *after* a byval parameter is passed
2186/// on the stack. Remember the next parameter register to allocate,
2187/// and then confiscate the rest of the parameter registers to insure
2188/// this.
2189void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2190 unsigned Align) const {
2191 // Byval (as with any stack) slots are always at least 4 byte aligned.
2192 Align = std::max(Align, 4U);
2193
2194 unsigned Reg = State->AllocateReg(GPRArgRegs);
2195 if (!Reg)
2196 return;
2197
2198 unsigned AlignInRegs = Align / 4;
2199 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2200 for (unsigned i = 0; i < Waste; ++i)
2201 Reg = State->AllocateReg(GPRArgRegs);
2202
2203 if (!Reg)
2204 return;
2205
2206 unsigned Excess = 4 * (ARM::R4 - Reg);
2207
2208 // Special case when NSAA != SP and parameter size greater than size of
2209 // all remained GPR regs. In that case we can't split parameter, we must
2210 // send it to stack. We also must set NCRN to R4, so waste all
2211 // remained registers.
2212 const unsigned NSAAOffset = State->getNextStackOffset();
2213 if (NSAAOffset != 0 && Size > Excess) {
2214 while (State->AllocateReg(GPRArgRegs))
2215 ;
2216 return;
2217 }
2218
2219 // First register for byval parameter is the first register that wasn't
2220 // allocated before this method call, so it would be "reg".
2221 // If parameter is small enough to be saved in range [reg, r4), then
2222 // the end (first after last) register would be reg + param-size-in-regs,
2223 // else parameter would be splitted between registers and stack,
2224 // end register would be r4 in this case.
2225 unsigned ByValRegBegin = Reg;
2226 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2227 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2228 // Note, first register is allocated in the beginning of function already,
2229 // allocate remained amount of registers we need.
2230 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2231 State->AllocateReg(GPRArgRegs);
2232 // A byval parameter that is split between registers and memory needs its
2233 // size truncated here.
2234 // In the case where the entire structure fits in registers, we set the
2235 // size in memory to zero.
2236 Size = std::max<int>(Size - Excess, 0);
2237}
2238
2239/// MatchingStackOffset - Return true if the given stack call argument is
2240/// already available in the same position (relatively) of the caller's
2241/// incoming argument stack.
2242static
2243bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2244 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2245 const TargetInstrInfo *TII) {
2246 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2247 int FI = std::numeric_limits<int>::max();
2248 if (Arg.getOpcode() == ISD::CopyFromReg) {
2249 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2250 if (!TargetRegisterInfo::isVirtualRegister(VR))
2251 return false;
2252 MachineInstr *Def = MRI->getVRegDef(VR);
2253 if (!Def)
2254 return false;
2255 if (!Flags.isByVal()) {
2256 if (!TII->isLoadFromStackSlot(*Def, FI))
2257 return false;
2258 } else {
2259 return false;
2260 }
2261 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2262 if (Flags.isByVal())
2263 // ByVal argument is passed in as a pointer but it's now being
2264 // dereferenced. e.g.
2265 // define @foo(%struct.X* %A) {
2266 // tail call @bar(%struct.X* byval %A)
2267 // }
2268 return false;
2269 SDValue Ptr = Ld->getBasePtr();
2270 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2271 if (!FINode)
2272 return false;
2273 FI = FINode->getIndex();
2274 } else
2275 return false;
2276
2277 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2277, __extension__ __PRETTY_FUNCTION__))
;
2278 if (!MFI.isFixedObjectIndex(FI))
2279 return false;
2280 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2281}
2282
2283/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2284/// for tail call optimization. Targets which want to do tail call
2285/// optimization should implement this function.
2286bool
2287ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2288 CallingConv::ID CalleeCC,
2289 bool isVarArg,
2290 bool isCalleeStructRet,
2291 bool isCallerStructRet,
2292 const SmallVectorImpl<ISD::OutputArg> &Outs,
2293 const SmallVectorImpl<SDValue> &OutVals,
2294 const SmallVectorImpl<ISD::InputArg> &Ins,
2295 SelectionDAG& DAG) const {
2296 MachineFunction &MF = DAG.getMachineFunction();
2297 const Function &CallerF = MF.getFunction();
2298 CallingConv::ID CallerCC = CallerF.getCallingConv();
2299
2300 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2300, __extension__ __PRETTY_FUNCTION__))
;
2301
2302 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2303 // to the call take up r0-r3. The reason is that there are no legal registers
2304 // left to hold the pointer to the function to be called.
2305 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2306 !isa<GlobalAddressSDNode>(Callee.getNode()))
2307 return false;
2308
2309 // Look for obvious safe cases to perform tail call optimization that do not
2310 // require ABI changes. This is what gcc calls sibcall.
2311
2312 // Exception-handling functions need a special set of instructions to indicate
2313 // a return to the hardware. Tail-calling another function would probably
2314 // break this.
2315 if (CallerF.hasFnAttribute("interrupt"))
2316 return false;
2317
2318 // Also avoid sibcall optimization if either caller or callee uses struct
2319 // return semantics.
2320 if (isCalleeStructRet || isCallerStructRet)
2321 return false;
2322
2323 // Externally-defined functions with weak linkage should not be
2324 // tail-called on ARM when the OS does not support dynamic
2325 // pre-emption of symbols, as the AAELF spec requires normal calls
2326 // to undefined weak functions to be replaced with a NOP or jump to the
2327 // next instruction. The behaviour of branch instructions in this
2328 // situation (as used for tail calls) is implementation-defined, so we
2329 // cannot rely on the linker replacing the tail call with a return.
2330 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2331 const GlobalValue *GV = G->getGlobal();
2332 const Triple &TT = getTargetMachine().getTargetTriple();
2333 if (GV->hasExternalWeakLinkage() &&
2334 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2335 return false;
2336 }
2337
2338 // Check that the call results are passed in the same way.
2339 LLVMContext &C = *DAG.getContext();
2340 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2341 CCAssignFnForReturn(CalleeCC, isVarArg),
2342 CCAssignFnForReturn(CallerCC, isVarArg)))
2343 return false;
2344 // The callee has to preserve all registers the caller needs to preserve.
2345 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2346 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2347 if (CalleeCC != CallerCC) {
2348 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2349 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2350 return false;
2351 }
2352
2353 // If Caller's vararg or byval argument has been split between registers and
2354 // stack, do not perform tail call, since part of the argument is in caller's
2355 // local frame.
2356 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2357 if (AFI_Caller->getArgRegsSaveSize())
2358 return false;
2359
2360 // If the callee takes no arguments then go on to check the results of the
2361 // call.
2362 if (!Outs.empty()) {
2363 // Check if stack adjustment is needed. For now, do not do this if any
2364 // argument is passed on the stack.
2365 SmallVector<CCValAssign, 16> ArgLocs;
2366 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2367 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2368 if (CCInfo.getNextStackOffset()) {
2369 // Check if the arguments are already laid out in the right way as
2370 // the caller's fixed stack objects.
2371 MachineFrameInfo &MFI = MF.getFrameInfo();
2372 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2373 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2374 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2375 i != e;
2376 ++i, ++realArgIdx) {
2377 CCValAssign &VA = ArgLocs[i];
2378 EVT RegVT = VA.getLocVT();
2379 SDValue Arg = OutVals[realArgIdx];
2380 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2381 if (VA.getLocInfo() == CCValAssign::Indirect)
2382 return false;
2383 if (VA.needsCustom()) {
2384 // f64 and vector types are split into multiple registers or
2385 // register/stack-slot combinations. The types will not match
2386 // the registers; give up on memory f64 refs until we figure
2387 // out what to do about this.
2388 if (!VA.isRegLoc())
2389 return false;
2390 if (!ArgLocs[++i].isRegLoc())
2391 return false;
2392 if (RegVT == MVT::v2f64) {
2393 if (!ArgLocs[++i].isRegLoc())
2394 return false;
2395 if (!ArgLocs[++i].isRegLoc())
2396 return false;
2397 }
2398 } else if (!VA.isRegLoc()) {
2399 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2400 MFI, MRI, TII))
2401 return false;
2402 }
2403 }
2404 }
2405
2406 const MachineRegisterInfo &MRI = MF.getRegInfo();
2407 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2408 return false;
2409 }
2410
2411 return true;
2412}
2413
2414bool
2415ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2416 MachineFunction &MF, bool isVarArg,
2417 const SmallVectorImpl<ISD::OutputArg> &Outs,
2418 LLVMContext &Context) const {
2419 SmallVector<CCValAssign, 16> RVLocs;
2420 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2421 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2422}
2423
2424static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2425 const SDLoc &DL, SelectionDAG &DAG) {
2426 const MachineFunction &MF = DAG.getMachineFunction();
2427 const Function &F = MF.getFunction();
2428
2429 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2430
2431 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2432 // version of the "preferred return address". These offsets affect the return
2433 // instruction if this is a return from PL1 without hypervisor extensions.
2434 // IRQ/FIQ: +4 "subs pc, lr, #4"
2435 // SWI: 0 "subs pc, lr, #0"
2436 // ABORT: +4 "subs pc, lr, #4"
2437 // UNDEF: +4/+2 "subs pc, lr, #0"
2438 // UNDEF varies depending on where the exception came from ARM or Thumb
2439 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2440
2441 int64_t LROffset;
2442 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2443 IntKind == "ABORT")
2444 LROffset = 4;
2445 else if (IntKind == "SWI" || IntKind == "UNDEF")
2446 LROffset = 0;
2447 else
2448 report_fatal_error("Unsupported interrupt attribute. If present, value "
2449 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2450
2451 RetOps.insert(RetOps.begin() + 1,
2452 DAG.getConstant(LROffset, DL, MVT::i32, false));
2453
2454 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2455}
2456
2457SDValue
2458ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2459 bool isVarArg,
2460 const SmallVectorImpl<ISD::OutputArg> &Outs,
2461 const SmallVectorImpl<SDValue> &OutVals,
2462 const SDLoc &dl, SelectionDAG &DAG) const {
2463 // CCValAssign - represent the assignment of the return value to a location.
2464 SmallVector<CCValAssign, 16> RVLocs;
2465
2466 // CCState - Info about the registers and stack slots.
2467 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2468 *DAG.getContext());
2469
2470 // Analyze outgoing return values.
2471 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2472
2473 SDValue Flag;
2474 SmallVector<SDValue, 4> RetOps;
2475 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2476 bool isLittleEndian = Subtarget->isLittle();
2477
2478 MachineFunction &MF = DAG.getMachineFunction();
2479 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2480 AFI->setReturnRegsCount(RVLocs.size());
2481
2482 // Copy the result values into the output registers.
2483 for (unsigned i = 0, realRVLocIdx = 0;
2484 i != RVLocs.size();
2485 ++i, ++realRVLocIdx) {
2486 CCValAssign &VA = RVLocs[i];
2487 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2487, __extension__ __PRETTY_FUNCTION__))
;
2488
2489 SDValue Arg = OutVals[realRVLocIdx];
2490 bool ReturnF16 = false;
2491
2492 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2493 // Half-precision return values can be returned like this:
2494 //
2495 // t11 f16 = fadd ...
2496 // t12: i16 = bitcast t11
2497 // t13: i32 = zero_extend t12
2498 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2499 //
2500 // to avoid code generation for bitcasts, we simply set Arg to the node
2501 // that produces the f16 value, t11 in this case.
2502 //
2503 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2504 SDValue ZE = Arg.getOperand(0);
2505 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2506 SDValue BC = ZE.getOperand(0);
2507 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2508 Arg = BC.getOperand(0);
2509 ReturnF16 = true;
2510 }
2511 }
2512 }
2513 }
2514
2515 switch (VA.getLocInfo()) {
2516 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2516)
;
2517 case CCValAssign::Full: break;
2518 case CCValAssign::BCvt:
2519 if (!ReturnF16)
2520 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2521 break;
2522 }
2523
2524 if (VA.needsCustom()) {
2525 if (VA.getLocVT() == MVT::v2f64) {
2526 // Extract the first half and return it in two registers.
2527 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2528 DAG.getConstant(0, dl, MVT::i32));
2529 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2530 DAG.getVTList(MVT::i32, MVT::i32), Half);
2531
2532 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2533 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2534 Flag);
2535 Flag = Chain.getValue(1);
2536 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2537 VA = RVLocs[++i]; // skip ahead to next loc
2538 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2539 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2540 Flag);
2541 Flag = Chain.getValue(1);
2542 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2543 VA = RVLocs[++i]; // skip ahead to next loc
2544
2545 // Extract the 2nd half and fall through to handle it as an f64 value.
2546 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2547 DAG.getConstant(1, dl, MVT::i32));
2548 }
2549 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2550 // available.
2551 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2552 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2554 fmrrd.getValue(isLittleEndian ? 0 : 1),
2555 Flag);
2556 Flag = Chain.getValue(1);
2557 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2558 VA = RVLocs[++i]; // skip ahead to next loc
2559 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2560 fmrrd.getValue(isLittleEndian ? 1 : 0),
2561 Flag);
2562 } else
2563 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2564
2565 // Guarantee that all emitted copies are
2566 // stuck together, avoiding something bad.
2567 Flag = Chain.getValue(1);
2568 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2569 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2570 }
2571 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2572 const MCPhysReg *I =
2573 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2574 if (I) {
2575 for (; *I; ++I) {
2576 if (ARM::GPRRegClass.contains(*I))
2577 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2578 else if (ARM::DPRRegClass.contains(*I))
2579 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2580 else
2581 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2581)
;
2582 }
2583 }
2584
2585 // Update chain and glue.
2586 RetOps[0] = Chain;
2587 if (Flag.getNode())
2588 RetOps.push_back(Flag);
2589
2590 // CPUs which aren't M-class use a special sequence to return from
2591 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2592 // though we use "subs pc, lr, #N").
2593 //
2594 // M-class CPUs actually use a normal return sequence with a special
2595 // (hardware-provided) value in LR, so the normal code path works.
2596 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2597 !Subtarget->isMClass()) {
2598 if (Subtarget->isThumb1Only())
2599 report_fatal_error("interrupt attribute is not supported in Thumb1");
2600 return LowerInterruptReturn(RetOps, dl, DAG);
2601 }
2602
2603 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2604}
2605
2606bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2607 if (N->getNumValues() != 1)
2608 return false;
2609 if (!N->hasNUsesOfValue(1, 0))
2610 return false;
2611
2612 SDValue TCChain = Chain;
2613 SDNode *Copy = *N->use_begin();
2614 if (Copy->getOpcode() == ISD::CopyToReg) {
2615 // If the copy has a glue operand, we conservatively assume it isn't safe to
2616 // perform a tail call.
2617 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2618 return false;
2619 TCChain = Copy->getOperand(0);
2620 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2621 SDNode *VMov = Copy;
2622 // f64 returned in a pair of GPRs.
2623 SmallPtrSet<SDNode*, 2> Copies;
2624 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2625 UI != UE; ++UI) {
2626 if (UI->getOpcode() != ISD::CopyToReg)
2627 return false;
2628 Copies.insert(*UI);
2629 }
2630 if (Copies.size() > 2)
2631 return false;
2632
2633 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2634 UI != UE; ++UI) {
2635 SDValue UseChain = UI->getOperand(0);
2636 if (Copies.count(UseChain.getNode()))
2637 // Second CopyToReg
2638 Copy = *UI;
2639 else {
2640 // We are at the top of this chain.
2641 // If the copy has a glue operand, we conservatively assume it
2642 // isn't safe to perform a tail call.
2643 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2644 return false;
2645 // First CopyToReg
2646 TCChain = UseChain;
2647 }
2648 }
2649 } else if (Copy->getOpcode() == ISD::BITCAST) {
2650 // f32 returned in a single GPR.
2651 if (!Copy->hasOneUse())
2652 return false;
2653 Copy = *Copy->use_begin();
2654 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2655 return false;
2656 // If the copy has a glue operand, we conservatively assume it isn't safe to
2657 // perform a tail call.
2658 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2659 return false;
2660 TCChain = Copy->getOperand(0);
2661 } else {
2662 return false;
2663 }
2664
2665 bool HasRet = false;
2666 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2667 UI != UE; ++UI) {
2668 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2669 UI->getOpcode() != ARMISD::INTRET_FLAG)
2670 return false;
2671 HasRet = true;
2672 }
2673
2674 if (!HasRet)
2675 return false;
2676
2677 Chain = TCChain;
2678 return true;
2679}
2680
2681bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2682 if (!Subtarget->supportsTailCall())
2683 return false;
2684
2685 auto Attr =
2686 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2687 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2688 return false;
2689
2690 return true;
2691}
2692
2693// Trying to write a 64 bit value so need to split into two 32 bit values first,
2694// and pass the lower and high parts through.
2695static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2696 SDLoc DL(Op);
2697 SDValue WriteValue = Op->getOperand(2);
2698
2699 // This function is only supposed to be called for i64 type argument.
2700 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2701, __extension__ __PRETTY_FUNCTION__))
2701 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2701, __extension__ __PRETTY_FUNCTION__))
;
2702
2703 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2704 DAG.getConstant(0, DL, MVT::i32));
2705 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2706 DAG.getConstant(1, DL, MVT::i32));
2707 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2708 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2709}
2710
2711// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2712// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2713// one of the above mentioned nodes. It has to be wrapped because otherwise
2714// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2715// be used to form addressing mode. These wrapped nodes will be selected
2716// into MOVi.
2717SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2718 SelectionDAG &DAG) const {
2719 EVT PtrVT = Op.getValueType();
2720 // FIXME there is no actual debug info here
2721 SDLoc dl(Op);
2722 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2723 SDValue Res;
2724
2725 // When generating execute-only code Constant Pools must be promoted to the
2726 // global data section. It's a bit ugly that we can't share them across basic
2727 // blocks, but this way we guarantee that execute-only behaves correct with
2728 // position-independent addressing modes.
2729 if (Subtarget->genExecuteOnly()) {
2730 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2731 auto T = const_cast<Type*>(CP->getType());
2732 auto C = const_cast<Constant*>(CP->getConstVal());
2733 auto M = const_cast<Module*>(DAG.getMachineFunction().
2734 getFunction().getParent());
2735 auto GV = new GlobalVariable(
2736 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2737 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2738 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2739 Twine(AFI->createPICLabelUId())
2740 );
2741 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2742 dl, PtrVT);
2743 return LowerGlobalAddress(GA, DAG);
2744 }
2745
2746 if (CP->isMachineConstantPoolEntry())
2747 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2748 CP->getAlignment());
2749 else
2750 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2751 CP->getAlignment());
2752 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2753}
2754
2755unsigned ARMTargetLowering::getJumpTableEncoding() const {
2756 return MachineJumpTableInfo::EK_Inline;
2757}
2758
2759SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2760 SelectionDAG &DAG) const {
2761 MachineFunction &MF = DAG.getMachineFunction();
2762 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2763 unsigned ARMPCLabelIndex = 0;
2764 SDLoc DL(Op);
2765 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2766 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2767 SDValue CPAddr;
2768 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2769 if (!IsPositionIndependent) {
2770 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2771 } else {
2772 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2773 ARMPCLabelIndex = AFI->createPICLabelUId();
2774 ARMConstantPoolValue *CPV =
2775 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2776 ARMCP::CPBlockAddress, PCAdj);
2777 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2778 }
2779 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2780 SDValue Result = DAG.getLoad(
2781 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2782 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2783 if (!IsPositionIndependent)
2784 return Result;
2785 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2786 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2787}
2788
2789/// Convert a TLS address reference into the correct sequence of loads
2790/// and calls to compute the variable's address for Darwin, and return an
2791/// SDValue containing the final node.
2792
2793/// Darwin only has one TLS scheme which must be capable of dealing with the
2794/// fully general situation, in the worst case. This means:
2795/// + "extern __thread" declaration.
2796/// + Defined in a possibly unknown dynamic library.
2797///
2798/// The general system is that each __thread variable has a [3 x i32] descriptor
2799/// which contains information used by the runtime to calculate the address. The
2800/// only part of this the compiler needs to know about is the first word, which
2801/// contains a function pointer that must be called with the address of the
2802/// entire descriptor in "r0".
2803///
2804/// Since this descriptor may be in a different unit, in general access must
2805/// proceed along the usual ARM rules. A common sequence to produce is:
2806///
2807/// movw rT1, :lower16:_var$non_lazy_ptr
2808/// movt rT1, :upper16:_var$non_lazy_ptr
2809/// ldr r0, [rT1]
2810/// ldr rT2, [r0]
2811/// blx rT2
2812/// [...address now in r0...]
2813SDValue
2814ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2815 SelectionDAG &DAG) const {
2816 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2817, __extension__ __PRETTY_FUNCTION__))
2817 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2817, __extension__ __PRETTY_FUNCTION__))
;
2818 SDLoc DL(Op);
2819
2820 // First step is to get the address of the actua global symbol. This is where
2821 // the TLS descriptor lives.
2822 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2823
2824 // The first entry in the descriptor is a function pointer that we must call
2825 // to obtain the address of the variable.
2826 SDValue Chain = DAG.getEntryNode();
2827 SDValue FuncTLVGet = DAG.getLoad(
2828 MVT::i32, DL, Chain, DescAddr,
2829 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2830 /* Alignment = */ 4,
2831 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2832 MachineMemOperand::MOInvariant);
2833 Chain = FuncTLVGet.getValue(1);
2834
2835 MachineFunction &F = DAG.getMachineFunction();
2836 MachineFrameInfo &MFI = F.getFrameInfo();
2837 MFI.setAdjustsStack(true);
2838
2839 // TLS calls preserve all registers except those that absolutely must be
2840 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2841 // silly).
2842 auto TRI =
2843 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2844 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2845 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2846
2847 // Finally, we can make the call. This is just a degenerate version of a
2848 // normal AArch64 call node: r0 takes the address of the descriptor, and
2849 // returns the address of the variable in this thread.
2850 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2851 Chain =
2852 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2853 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2854 DAG.getRegisterMask(Mask), Chain.getValue(1));
2855 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2856}
2857
2858SDValue
2859ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2860 SelectionDAG &DAG) const {
2861 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2861, __extension__ __PRETTY_FUNCTION__))
;
2862
2863 SDValue Chain = DAG.getEntryNode();
2864 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2865 SDLoc DL(Op);
2866
2867 // Load the current TEB (thread environment block)
2868 SDValue Ops[] = {Chain,
2869 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2870 DAG.getConstant(15, DL, MVT::i32),
2871 DAG.getConstant(0, DL, MVT::i32),
2872 DAG.getConstant(13, DL, MVT::i32),
2873 DAG.getConstant(0, DL, MVT::i32),
2874 DAG.getConstant(2, DL, MVT::i32)};
2875 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2876 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2877
2878 SDValue TEB = CurrentTEB.getValue(0);
2879 Chain = CurrentTEB.getValue(1);
2880
2881 // Load the ThreadLocalStoragePointer from the TEB
2882 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2883 SDValue TLSArray =
2884 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2885 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2886
2887 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2888 // offset into the TLSArray.
2889
2890 // Load the TLS index from the C runtime
2891 SDValue TLSIndex =
2892 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2893 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2894 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2895
2896 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2897 DAG.getConstant(2, DL, MVT::i32));
2898 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2899 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2900 MachinePointerInfo());
2901
2902 // Get the offset of the start of the .tls section (section base)
2903 const auto *GA = cast<GlobalAddressSDNode>(Op);
2904 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2905 SDValue Offset = DAG.getLoad(
2906 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2907 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2908 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2909
2910 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2911}
2912
2913// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2914SDValue
2915ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2916 SelectionDAG &DAG) const {
2917 SDLoc dl(GA);
2918 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2919 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2920 MachineFunction &MF = DAG.getMachineFunction();
2921 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2922 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2923 ARMConstantPoolValue *CPV =
2924 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2925 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2926 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2927 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2928 Argument = DAG.getLoad(
2929 PtrVT, dl, DAG.getEntryNode(), Argument,
2930 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2931 SDValue Chain = Argument.getValue(1);
2932
2933 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2934 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2935
2936 // call __tls_get_addr.
2937 ArgListTy Args;
2938 ArgListEntry Entry;
2939 Entry.Node = Argument;
2940 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2941 Args.push_back(Entry);
2942
2943 // FIXME: is there useful debug info available here?
2944 TargetLowering::CallLoweringInfo CLI(DAG);
2945 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2946 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2947 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2948
2949 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2950 return CallResult.first;
2951}
2952
2953// Lower ISD::GlobalTLSAddress using the "initial exec" or
2954// "local exec" model.
2955SDValue
2956ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2957 SelectionDAG &DAG,
2958 TLSModel::Model model) const {
2959 const GlobalValue *GV = GA->getGlobal();
2960 SDLoc dl(GA);
2961 SDValue Offset;
2962 SDValue Chain = DAG.getEntryNode();
2963 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2964 // Get the Thread Pointer
2965 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2966
2967 if (model == TLSModel::InitialExec) {
2968 MachineFunction &MF = DAG.getMachineFunction();
2969 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2970 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2971 // Initial exec model.
2972 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2973 ARMConstantPoolValue *CPV =
2974 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2975 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2976 true);
2977 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2978 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2979 Offset = DAG.getLoad(
2980 PtrVT, dl, Chain, Offset,
2981 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2982 Chain = Offset.getValue(1);
2983
2984 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2985 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2986
2987 Offset = DAG.getLoad(
2988 PtrVT, dl, Chain, Offset,
2989 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2990 } else {
2991 // local exec model
2992 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 2992, __extension__ __PRETTY_FUNCTION__))
;
2993 ARMConstantPoolValue *CPV =
2994 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2995 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2996 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2997 Offset = DAG.getLoad(
2998 PtrVT, dl, Chain, Offset,
2999 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3000 }
3001
3002 // The address of the thread local variable is the add of the thread
3003 // pointer with the offset of the variable.
3004 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3005}
3006
3007SDValue
3008ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3009 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3010 if (DAG.getTarget().useEmulatedTLS())
3011 return LowerToTLSEmulatedModel(GA, DAG);
3012
3013 if (Subtarget->isTargetDarwin())
3014 return LowerGlobalTLSAddressDarwin(Op, DAG);
3015
3016 if (Subtarget->isTargetWindows())
3017 return LowerGlobalTLSAddressWindows(Op, DAG);
3018
3019 // TODO: implement the "local dynamic" model
3020 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3020, __extension__ __PRETTY_FUNCTION__))
;
3021 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3022
3023 switch (model) {
3024 case TLSModel::GeneralDynamic:
3025 case TLSModel::LocalDynamic:
3026 return LowerToTLSGeneralDynamicModel(GA, DAG);
3027 case TLSModel::InitialExec:
3028 case TLSModel::LocalExec:
3029 return LowerToTLSExecModels(GA, DAG, model);
3030 }
3031 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3031)
;
3032}
3033
3034/// Return true if all users of V are within function F, looking through
3035/// ConstantExprs.
3036static bool allUsersAreInFunction(const Value *V, const Function *F) {
3037 SmallVector<const User*,4> Worklist;
3038 for (auto *U : V->users())
3039 Worklist.push_back(U);
3040 while (!Worklist.empty()) {
3041 auto *U = Worklist.pop_back_val();
3042 if (isa<ConstantExpr>(U)) {
3043 for (auto *UU : U->users())
3044 Worklist.push_back(UU);
3045 continue;
3046 }
3047
3048 auto *I = dyn_cast<Instruction>(U);
3049 if (!I || I->getParent()->getParent() != F)
3050 return false;
3051 }
3052 return true;
3053}
3054
3055/// Return true if all users of V are within some (any) function, looking through
3056/// ConstantExprs. In other words, are there any global constant users?
3057static bool allUsersAreInFunctions(const Value *V) {
3058 SmallVector<const User*,4> Worklist;
3059 for (auto *U : V->users())
3060 Worklist.push_back(U);
3061 while (!Worklist.empty()) {
3062 auto *U = Worklist.pop_back_val();
3063 if (isa<ConstantExpr>(U)) {
3064 for (auto *UU : U->users())
3065 Worklist.push_back(UU);
3066 continue;
3067 }
3068
3069 if (!isa<Instruction>(U))
3070 return false;
3071 }
3072 return true;
3073}
3074
3075// Return true if T is an integer, float or an array/vector of either.
3076static bool isSimpleType(Type *T) {
3077 if (T->isIntegerTy() || T->isFloatingPointTy())
3078 return true;
3079 Type *SubT = nullptr;
3080 if (T->isArrayTy())
3081 SubT = T->getArrayElementType();
3082 else if (T->isVectorTy())
3083 SubT = T->getVectorElementType();
3084 else
3085 return false;
3086 return SubT->isIntegerTy() || SubT->isFloatingPointTy();
3087}
3088
3089static SDValue promoteToConstantPool(const GlobalValue *GV, SelectionDAG &DAG,
3090 EVT PtrVT, const SDLoc &dl) {
3091 // If we're creating a pool entry for a constant global with unnamed address,
3092 // and the global is small enough, we can emit it inline into the constant pool
3093 // to save ourselves an indirection.
3094 //
3095 // This is a win if the constant is only used in one function (so it doesn't
3096 // need to be duplicated) or duplicating the constant wouldn't increase code
3097 // size (implying the constant is no larger than 4 bytes).
3098 const Function &F = DAG.getMachineFunction().getFunction();
3099
3100 // We rely on this decision to inline being idemopotent and unrelated to the
3101 // use-site. We know that if we inline a variable at one use site, we'll
3102 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3103 // doesn't know about this optimization, so bail out if it's enabled else
3104 // we could decide to inline here (and thus never emit the GV) but require
3105 // the GV from fast-isel generated code.
3106 if (!EnableConstpoolPromotion ||
3107 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3108 return SDValue();
3109
3110 auto *GVar = dyn_cast<GlobalVariable>(GV);
3111 if (!GVar || !GVar->hasInitializer() ||
3112 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3113 !GVar->hasLocalLinkage())
3114 return SDValue();
3115
3116 // Ensure that we don't try and inline any type that contains pointers. If
3117 // we inline a value that contains relocations, we move the relocations from
3118 // .data to .text which is not ideal.
3119 auto *Init = GVar->getInitializer();
3120 if (!isSimpleType(Init->getType()))
3121 return SDValue();
3122
3123 // The constant islands pass can only really deal with alignment requests
3124 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3125 // any type wanting greater alignment requirements than 4 bytes. We also
3126 // can only promote constants that are multiples of 4 bytes in size or
3127 // are paddable to a multiple of 4. Currently we only try and pad constants
3128 // that are strings for simplicity.
3129 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3130 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3131 unsigned Align = GVar->getAlignment();
3132 unsigned RequiredPadding = 4 - (Size % 4);
3133 bool PaddingPossible =
3134 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3135 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3136 Size == 0)
3137 return SDValue();
3138
3139 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3140 MachineFunction &MF = DAG.getMachineFunction();
3141 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3142
3143 // We can't bloat the constant pool too much, else the ConstantIslands pass
3144 // may fail to converge. If we haven't promoted this global yet (it may have
3145 // multiple uses), and promoting it would increase the constant pool size (Sz
3146 // > 4), ensure we have space to do so up to MaxTotal.
3147 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3148 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3149 ConstpoolPromotionMaxTotal)
3150 return SDValue();
3151
3152 // This is only valid if all users are in a single function OR it has users
3153 // in multiple functions but it no larger than a pointer. We also check if
3154 // GVar has constant (non-ConstantExpr) users. If so, it essentially has its
3155 // address taken.
3156 if (!allUsersAreInFunction(GVar, &F) &&
3157 !(Size <= 4 && allUsersAreInFunctions(GVar)))
3158 return SDValue();
3159
3160 // We're going to inline this global. Pad it out if needed.
3161 if (RequiredPadding != 4) {
3162 StringRef S = CDAInit->getAsString();
3163
3164 SmallVector<uint8_t,16> V(S.size());
3165 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3166 while (RequiredPadding--)
3167 V.push_back(0);
3168 Init = ConstantDataArray::get(*DAG.getContext(), V);
3169 }
3170
3171 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3172 SDValue CPAddr =
3173 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3174 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3175 AFI->markGlobalAsPromotedToConstantPool(GVar);
3176 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3177 PaddedSize - 4);
3178 }
3179 ++NumConstpoolPromoted;
3180 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3181}
3182
3183bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3184 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3185 GV = GA->getBaseObject();
3186 return (isa<GlobalVariable>(GV) && cast<GlobalVariable>(GV)->isConstant()) ||
3187 isa<Function>(GV);
3188}
3189
3190SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3191 SelectionDAG &DAG) const {
3192 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3193 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3193)
;
3194 case Triple::COFF:
3195 return LowerGlobalAddressWindows(Op, DAG);
3196 case Triple::ELF:
3197 return LowerGlobalAddressELF(Op, DAG);
3198 case Triple::MachO:
3199 return LowerGlobalAddressDarwin(Op, DAG);
3200 }
3201}
3202
3203SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3204 SelectionDAG &DAG) const {
3205 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3206 SDLoc dl(Op);
3207 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3208 const TargetMachine &TM = getTargetMachine();
3209 bool IsRO = isReadOnly(GV);
3210
3211 // promoteToConstantPool only if not generating XO text section
3212 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3213 if (SDValue V = promoteToConstantPool(GV, DAG, PtrVT, dl))
3214 return V;
3215
3216 if (isPositionIndependent()) {
3217 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3218 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3219 UseGOT_PREL ? ARMII::MO_GOT : 0);
3220 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3221 if (UseGOT_PREL)
3222 Result =
3223 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3224 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3225 return Result;
3226 } else if (Subtarget->isROPI() && IsRO) {
3227 // PC-relative.
3228 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3229 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3230 return Result;
3231 } else if (Subtarget->isRWPI() && !IsRO) {
3232 // SB-relative.
3233 SDValue RelAddr;
3234 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3235 ++NumMovwMovt;
3236 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3237 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3238 } else { // use literal pool for address constant
3239 ARMConstantPoolValue *CPV =
3240 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3241 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3242 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3243 RelAddr = DAG.getLoad(
3244 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3245 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3246 }
3247 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3248 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3249 return Result;
3250 }
3251
3252 // If we have T2 ops, we can materialize the address directly via movt/movw
3253 // pair. This is always cheaper.
3254 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3255 ++NumMovwMovt;
3256 // FIXME: Once remat is capable of dealing with instructions with register
3257 // operands, expand this into two nodes.
3258 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3259 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3260 } else {
3261 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3262 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3263 return DAG.getLoad(
3264 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3265 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3266 }
3267}
3268
3269SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3270 SelectionDAG &DAG) const {
3271 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3272, __extension__ __PRETTY_FUNCTION__))
3272 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3272, __extension__ __PRETTY_FUNCTION__))
;
3273 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3274 SDLoc dl(Op);
3275 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3276
3277 if (Subtarget->useMovt(DAG.getMachineFunction()))
3278 ++NumMovwMovt;
3279
3280 // FIXME: Once remat is capable of dealing with instructions with register
3281 // operands, expand this into multiple nodes
3282 unsigned Wrapper =
3283 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3284
3285 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3286 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3287
3288 if (Subtarget->isGVIndirectSymbol(GV))
3289 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3290 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3291 return Result;
3292}
3293
3294SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3295 SelectionDAG &DAG) const {
3296 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3296, __extension__ __PRETTY_FUNCTION__))
;
3297 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3298, __extension__ __PRETTY_FUNCTION__))
3298 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3298, __extension__ __PRETTY_FUNCTION__))
;
3299 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3300, __extension__ __PRETTY_FUNCTION__))
3300 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3300, __extension__ __PRETTY_FUNCTION__))
;
3301
3302 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3303 const ARMII::TOF TargetFlags =
3304 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
3305 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3306 SDValue Result;
3307 SDLoc DL(Op);
3308
3309 ++NumMovwMovt;
3310
3311 // FIXME: Once remat is capable of dealing with instructions with register
3312 // operands, expand this into two nodes.
3313 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3314 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3315 TargetFlags));
3316 if (GV->hasDLLImportStorageClass())
3317 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3318 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3319 return Result;
3320}
3321
3322SDValue
3323ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3324 SDLoc dl(Op);
3325 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3326 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3327 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3328 Op.getOperand(1), Val);
3329}
3330
3331SDValue
3332ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3333 SDLoc dl(Op);
3334 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3335 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3336}
3337
3338SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3339 SelectionDAG &DAG) const {
3340 SDLoc dl(Op);
3341 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3342 Op.getOperand(0));
3343}
3344
3345SDValue
3346ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3347 const ARMSubtarget *Subtarget) const {
3348 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3349 SDLoc dl(Op);
3350 switch (IntNo) {
3351 default: return SDValue(); // Don't custom lower most intrinsics.
3352 case Intrinsic::thread_pointer: {
3353 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3354 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3355 }
3356 case Intrinsic::eh_sjlj_lsda: {
3357 MachineFunction &MF = DAG.getMachineFunction();
3358 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3359 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3360 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3361 SDValue CPAddr;
3362 bool IsPositionIndependent = isPositionIndependent();
3363 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3364 ARMConstantPoolValue *CPV =
3365 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3366 ARMCP::CPLSDA, PCAdj);
3367 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3368 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3369 SDValue Result = DAG.getLoad(
3370 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3371 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3372
3373 if (IsPositionIndependent) {
3374 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3375 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3376 }
3377 return Result;
3378 }
3379 case Intrinsic::arm_neon_vabs:
3380 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3381 Op.getOperand(1));
3382 case Intrinsic::arm_neon_vmulls:
3383 case Intrinsic::arm_neon_vmullu: {
3384 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3385 ? ARMISD::VMULLs : ARMISD::VMULLu;
3386 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3387 Op.getOperand(1), Op.getOperand(2));
3388 }
3389 case Intrinsic::arm_neon_vminnm:
3390 case Intrinsic::arm_neon_vmaxnm: {
3391 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3392 ? ISD::FMINNUM : ISD::FMAXNUM;
3393 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3394 Op.getOperand(1), Op.getOperand(2));
3395 }
3396 case Intrinsic::arm_neon_vminu:
3397 case Intrinsic::arm_neon_vmaxu: {
3398 if (Op.getValueType().isFloatingPoint())
3399 return SDValue();
3400 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3401 ? ISD::UMIN : ISD::UMAX;
3402 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3403 Op.getOperand(1), Op.getOperand(2));
3404 }
3405 case Intrinsic::arm_neon_vmins:
3406 case Intrinsic::arm_neon_vmaxs: {
3407 // v{min,max}s is overloaded between signed integers and floats.
3408 if (!Op.getValueType().isFloatingPoint()) {
3409 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3410 ? ISD::SMIN : ISD::SMAX;
3411 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3412 Op.getOperand(1), Op.getOperand(2));
3413 }
3414 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3415 ? ISD::FMINNAN : ISD::FMAXNAN;
3416 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3417 Op.getOperand(1), Op.getOperand(2));
3418 }
3419 case Intrinsic::arm_neon_vtbl1:
3420 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3421 Op.getOperand(1), Op.getOperand(2));
3422 case Intrinsic::arm_neon_vtbl2:
3423 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3424 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3425 }
3426}
3427
3428static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3429 const ARMSubtarget *Subtarget) {
3430 SDLoc dl(Op);
3431 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3432 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3433 if (SSID == SyncScope::SingleThread)
3434 return Op;
3435
3436 if (!Subtarget->hasDataBarrier()) {
3437 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3438 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3439 // here.
3440 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3441, __extension__ __PRETTY_FUNCTION__))
3441 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3441, __extension__ __PRETTY_FUNCTION__))
;
3442 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3443 DAG.getConstant(0, dl, MVT::i32));
3444 }
3445
3446 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3447 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3448 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3449 if (Subtarget->isMClass()) {
3450 // Only a full system barrier exists in the M-class architectures.
3451 Domain = ARM_MB::SY;
3452 } else if (Subtarget->preferISHSTBarriers() &&
3453 Ord == AtomicOrdering::Release) {
3454 // Swift happens to implement ISHST barriers in a way that's compatible with
3455 // Release semantics but weaker than ISH so we'd be fools not to use
3456 // it. Beware: other processors probably don't!
3457 Domain = ARM_MB::ISHST;
3458 }
3459
3460 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3461 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3462 DAG.getConstant(Domain, dl, MVT::i32));
3463}
3464
3465static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3466 const ARMSubtarget *Subtarget) {
3467 // ARM pre v5TE and Thumb1 does not have preload instructions.
3468 if (!(Subtarget->isThumb2() ||
3469 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3470 // Just preserve the chain.
3471 return Op.getOperand(0);
3472
3473 SDLoc dl(Op);
3474 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3475 if (!isRead &&
3476 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3477 // ARMv7 with MP extension has PLDW.
3478 return Op.getOperand(0);
3479
3480 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3481 if (Subtarget->isThumb()) {
3482 // Invert the bits.
3483 isRead = ~isRead & 1;
3484 isData = ~isData & 1;
3485 }
3486
3487 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3488 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3489 DAG.getConstant(isData, dl, MVT::i32));
3490}
3491
3492static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3493 MachineFunction &MF = DAG.getMachineFunction();
3494 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3495
3496 // vastart just stores the address of the VarArgsFrameIndex slot into the
3497 // memory location argument.
3498 SDLoc dl(Op);
3499 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3500 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3501 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3502 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3503 MachinePointerInfo(SV));
3504}
3505
3506SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3507 CCValAssign &NextVA,
3508 SDValue &Root,
3509 SelectionDAG &DAG,
3510 const SDLoc &dl) const {
3511 MachineFunction &MF = DAG.getMachineFunction();
3512 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3513
3514 const TargetRegisterClass *RC;
3515 if (AFI->isThumb1OnlyFunction())
3516 RC = &ARM::tGPRRegClass;
3517 else
3518 RC = &ARM::GPRRegClass;
3519
3520 // Transform the arguments stored in physical registers into virtual ones.
3521 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3522 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3523
3524 SDValue ArgValue2;
3525 if (NextVA.isMemLoc()) {
3526 MachineFrameInfo &MFI = MF.getFrameInfo();
3527 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3528
3529 // Create load node to retrieve arguments from the stack.
3530 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3531 ArgValue2 = DAG.getLoad(
3532 MVT::i32, dl, Root, FIN,
3533 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3534 } else {
3535 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3536 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3537 }
3538 if (!Subtarget->isLittle())
3539 std::swap (ArgValue, ArgValue2);
3540 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3541}
3542
3543// The remaining GPRs hold either the beginning of variable-argument
3544// data, or the beginning of an aggregate passed by value (usually
3545// byval). Either way, we allocate stack slots adjacent to the data
3546// provided by our caller, and store the unallocated registers there.
3547// If this is a variadic function, the va_list pointer will begin with
3548// these values; otherwise, this reassembles a (byval) structure that
3549// was split between registers and memory.
3550// Return: The frame index registers were stored into.
3551int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3552 const SDLoc &dl, SDValue &Chain,
3553 const Value *OrigArg,
3554 unsigned InRegsParamRecordIdx,
3555 int ArgOffset, unsigned ArgSize) const {
3556 // Currently, two use-cases possible:
3557 // Case #1. Non-var-args function, and we meet first byval parameter.
3558 // Setup first unallocated register as first byval register;
3559 // eat all remained registers
3560 // (these two actions are performed by HandleByVal method).
3561 // Then, here, we initialize stack frame with
3562 // "store-reg" instructions.
3563 // Case #2. Var-args function, that doesn't contain byval parameters.
3564 // The same: eat all remained unallocated registers,
3565 // initialize stack frame.
3566
3567 MachineFunction &MF = DAG.getMachineFunction();
3568 MachineFrameInfo &MFI = MF.getFrameInfo();
3569 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3570 unsigned RBegin, REnd;
3571 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3572 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3573 } else {
3574 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3575 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3576 REnd = ARM::R4;
3577 }
3578
3579 if (REnd != RBegin)
3580 ArgOffset = -4 * (ARM::R4 - RBegin);
3581
3582 auto PtrVT = getPointerTy(DAG.getDataLayout());
3583 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3584 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3585
3586 SmallVector<SDValue, 4> MemOps;
3587 const TargetRegisterClass *RC =
3588 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3589
3590 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3591 unsigned VReg = MF.addLiveIn(Reg, RC);
3592 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3593 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3594 MachinePointerInfo(OrigArg, 4 * i));
3595 MemOps.push_back(Store);
3596 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3597 }
3598
3599 if (!MemOps.empty())
3600 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3601 return FrameIndex;
3602}
3603
3604// Setup stack frame, the va_list pointer will start from.
3605void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3606 const SDLoc &dl, SDValue &Chain,
3607 unsigned ArgOffset,
3608 unsigned TotalArgRegsSaveSize,
3609 bool ForceMutable) const {
3610 MachineFunction &MF = DAG.getMachineFunction();
3611 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3612
3613 // Try to store any remaining integer argument regs
3614 // to their spots on the stack so that they may be loaded by dereferencing
3615 // the result of va_next.
3616 // If there is no regs to be stored, just point address after last
3617 // argument passed via stack.
3618 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3619 CCInfo.getInRegsParamsCount(),
3620 CCInfo.getNextStackOffset(), 4);
3621 AFI->setVarArgsFrameIndex(FrameIndex);
3622}
3623
3624SDValue ARMTargetLowering::LowerFormalArguments(
3625 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3626 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3627 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3628 MachineFunction &MF = DAG.getMachineFunction();
3629 MachineFrameInfo &MFI = MF.getFrameInfo();
3630
3631 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3632
3633 // Assign locations to all of the incoming arguments.
3634 SmallVector<CCValAssign, 16> ArgLocs;
3635 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3636 *DAG.getContext());
3637 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3638
3639 SmallVector<SDValue, 16> ArgValues;
3640 SDValue ArgValue;
3641 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3642 unsigned CurArgIdx = 0;
3643
3644 // Initially ArgRegsSaveSize is zero.
3645 // Then we increase this value each time we meet byval parameter.
3646 // We also increase this value in case of varargs function.
3647 AFI->setArgRegsSaveSize(0);
3648
3649 // Calculate the amount of stack space that we need to allocate to store
3650 // byval and variadic arguments that are passed in registers.
3651 // We need to know this before we allocate the first byval or variadic
3652 // argument, as they will be allocated a stack slot below the CFA (Canonical
3653 // Frame Address, the stack pointer at entry to the function).
3654 unsigned ArgRegBegin = ARM::R4;
3655 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3656 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3657 break;
3658
3659 CCValAssign &VA = ArgLocs[i];
3660 unsigned Index = VA.getValNo();
3661 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3662 if (!Flags.isByVal())
3663 continue;
3664
3665 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3665, __extension__ __PRETTY_FUNCTION__))
;
3666 unsigned RBegin, REnd;
3667 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3668 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3669
3670 CCInfo.nextInRegsParam();
3671 }
3672 CCInfo.rewindByValRegsInfo();
3673
3674 int lastInsIndex = -1;
3675 if (isVarArg && MFI.hasVAStart()) {
3676 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3677 if (RegIdx != array_lengthof(GPRArgRegs))
3678 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3679 }
3680
3681 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3682 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3683 auto PtrVT = getPointerTy(DAG.getDataLayout());
3684
3685 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3686 CCValAssign &VA = ArgLocs[i];
3687 if (Ins[VA.getValNo()].isOrigArg()) {
3688 std::advance(CurOrigArg,
3689 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3690 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3691 }
3692 // Arguments stored in registers.
3693 if (VA.isRegLoc()) {
3694 EVT RegVT = VA.getLocVT();
3695
3696 if (VA.needsCustom()) {
3697 // f64 and vector types are split up into multiple registers or
3698 // combinations of registers and stack slots.
3699 if (VA.getLocVT() == MVT::v2f64) {
3700 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3701 Chain, DAG, dl);
3702 VA = ArgLocs[++i]; // skip ahead to next loc
3703 SDValue ArgValue2;
3704 if (VA.isMemLoc()) {
3705 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3706 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3707 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3708 MachinePointerInfo::getFixedStack(
3709 DAG.getMachineFunction(), FI));
3710 } else {
3711 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3712 Chain, DAG, dl);
3713 }
3714 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3715 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3716 ArgValue, ArgValue1,
3717 DAG.getIntPtrConstant(0, dl));
3718 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3719 ArgValue, ArgValue2,
3720 DAG.getIntPtrConstant(1, dl));
3721 } else
3722 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3723 } else {
3724 const TargetRegisterClass *RC;
3725
3726
3727 if (RegVT == MVT::f16)
3728 RC = &ARM::HPRRegClass;
3729 else if (RegVT == MVT::f32)
3730 RC = &ARM::SPRRegClass;
3731 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
3732 RC = &ARM::DPRRegClass;
3733 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
3734 RC = &ARM::QPRRegClass;
3735 else if (RegVT == MVT::i32)
3736 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3737 : &ARM::GPRRegClass;
3738 else
3739 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3739)
;
3740
3741 // Transform the arguments in physical registers into virtual ones.
3742 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3743 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3744 }
3745
3746 // If this is an 8 or 16-bit value, it is really passed promoted
3747 // to 32 bits. Insert an assert[sz]ext to capture this, then
3748 // truncate to the right size.
3749 switch (VA.getLocInfo()) {
3750 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3750)
;
3751 case CCValAssign::Full: break;
3752 case CCValAssign::BCvt:
3753 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3754 break;
3755 case CCValAssign::SExt:
3756 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3757 DAG.getValueType(VA.getValVT()));
3758 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3759 break;
3760 case CCValAssign::ZExt:
3761 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3762 DAG.getValueType(VA.getValVT()));
3763 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3764 break;
3765 }
3766
3767 InVals.push_back(ArgValue);
3768 } else { // VA.isRegLoc()
3769 // sanity check
3770 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3770, __extension__ __PRETTY_FUNCTION__))
;
3771 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3771, __extension__ __PRETTY_FUNCTION__))
;
3772
3773 int index = VA.getValNo();
3774
3775 // Some Ins[] entries become multiple ArgLoc[] entries.
3776 // Process them only once.
3777 if (index != lastInsIndex)
3778 {
3779 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3780 // FIXME: For now, all byval parameter objects are marked mutable.
3781 // This can be changed with more analysis.
3782 // In case of tail call optimization mark all arguments mutable.
3783 // Since they could be overwritten by lowering of arguments in case of
3784 // a tail call.
3785 if (Flags.isByVal()) {
3786 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3787, __extension__ __PRETTY_FUNCTION__))
3787 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3787, __extension__ __PRETTY_FUNCTION__))
;
3788 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3789
3790 int FrameIndex = StoreByValRegs(
3791 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3792 VA.getLocMemOffset(), Flags.getByValSize());
3793 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3794 CCInfo.nextInRegsParam();
3795 } else {
3796 unsigned FIOffset = VA.getLocMemOffset();
3797 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3798 FIOffset, true);
3799
3800 // Create load nodes to retrieve arguments from the stack.
3801 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3802 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3803 MachinePointerInfo::getFixedStack(
3804 DAG.getMachineFunction(), FI)));
3805 }
3806 lastInsIndex = index;
3807 }
3808 }
3809 }
3810
3811 // varargs
3812 if (isVarArg && MFI.hasVAStart())
3813 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3814 CCInfo.getNextStackOffset(),
3815 TotalArgRegsSaveSize);
3816
3817 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3818
3819 return Chain;
3820}
3821
3822/// isFloatingPointZero - Return true if this is +0.0.
3823static bool isFloatingPointZero(SDValue Op) {
3824 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3825 return CFP->getValueAPF().isPosZero();
3826 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3827 // Maybe this has already been legalized into the constant pool?
3828 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3829 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3830 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3831 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3832 return CFP->getValueAPF().isPosZero();
3833 }
3834 } else if (Op->getOpcode() == ISD::BITCAST &&
3835 Op->getValueType(0) == MVT::f64) {
3836 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3837 // created by LowerConstantFP().
3838 SDValue BitcastOp = Op->getOperand(0);
3839 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3840 isNullConstant(BitcastOp->getOperand(0)))
3841 return true;
3842 }
3843 return false;
3844}
3845
3846/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3847/// the given operands.
3848SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3849 SDValue &ARMcc, SelectionDAG &DAG,
3850 const SDLoc &dl) const {
3851 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3852 unsigned C = RHSC->getZExtValue();
3853 if (!isLegalICmpImmediate((int32_t)C)) {
3854 // Constant does not fit, try adjusting it by one.
3855 switch (CC) {
3856 default: break;
3857 case ISD::SETLT:
3858 case ISD::SETGE:
3859 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3860 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3861 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3862 }
3863 break;
3864 case ISD::SETULT:
3865 case ISD::SETUGE:
3866 if (C != 0 && isLegalICmpImmediate(C-1)) {
3867 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3868 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3869 }
3870 break;
3871 case ISD::SETLE:
3872 case ISD::SETGT:
3873 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3874 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3875 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3876 }
3877 break;
3878 case ISD::SETULE:
3879 case ISD::SETUGT:
3880 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3881 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3882 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3883 }
3884 break;
3885 }
3886 }
3887 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3888 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3889 // In ARM and Thumb-2, the compare instructions can shift their second
3890 // operand.
3891 CC = ISD::getSetCCSwappedOperands(CC);
3892 std::swap(LHS, RHS);
3893 }
3894
3895 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3896 ARMISD::NodeType CompareType;
3897 switch (CondCode) {
3898 default:
3899 CompareType = ARMISD::CMP;
3900 break;
3901 case ARMCC::EQ:
3902 case ARMCC::NE:
3903 // Uses only Z Flag
3904 CompareType = ARMISD::CMPZ;
3905 break;
3906 }
3907 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3908 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3909}
3910
3911/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3912SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3913 SelectionDAG &DAG, const SDLoc &dl,
3914 bool InvalidOnQNaN) const {
3915 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)(static_cast <bool> (!Subtarget->isFPOnlySP() || RHS
.getValueType() != MVT::f64) ? void (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3915, __extension__ __PRETTY_FUNCTION__))
;
3916 SDValue Cmp;
3917 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3918 if (!isFloatingPointZero(RHS))
3919 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3920 else
3921 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3922 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3923}
3924
3925/// duplicateCmp - Glue values can have only one use, so this function
3926/// duplicates a comparison node.
3927SDValue
3928ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3929 unsigned Opc = Cmp.getOpcode();
3930 SDLoc DL(Cmp);
3931 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3932 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3933
3934 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3934, __extension__ __PRETTY_FUNCTION__))
;
3935 Cmp = Cmp.getOperand(0);
3936 Opc = Cmp.getOpcode();
3937 if (Opc == ARMISD::CMPFP)
3938 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3939 Cmp.getOperand(1), Cmp.getOperand(2));
3940 else {
3941 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3941, __extension__ __PRETTY_FUNCTION__))
;
3942 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3943 Cmp.getOperand(1));
3944 }
3945 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3946}
3947
3948// This function returns three things: the arithmetic computation itself
3949// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3950// comparison and the condition code define the case in which the arithmetic
3951// computation *does not* overflow.
3952std::pair<SDValue, SDValue>
3953ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3954 SDValue &ARMcc) const {
3955 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3955, __extension__ __PRETTY_FUNCTION__))
;
3956
3957 SDValue Value, OverflowCmp;
3958 SDValue LHS = Op.getOperand(0);
3959 SDValue RHS = Op.getOperand(1);
3960 SDLoc dl(Op);
3961
3962 // FIXME: We are currently always generating CMPs because we don't support
3963 // generating CMN through the backend. This is not as good as the natural
3964 // CMP case because it causes a register dependency and cannot be folded
3965 // later.
3966
3967 switch (Op.getOpcode()) {
3968 default:
3969 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 3969)
;
3970 case ISD::SADDO:
3971 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3972 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3973 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3974 break;
3975 case ISD::UADDO:
3976 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3977 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3978 // We do not use it in the USUBO case as Value may not be used.
3979 Value = DAG.getNode(ARMISD::ADDC, dl,
3980 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3981 .getValue(0);
3982 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3983 break;
3984 case ISD::SSUBO:
3985 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3986 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3987 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3988 break;
3989 case ISD::USUBO:
3990 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3991 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3992 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3993 break;
3994 case ISD::UMULO:
3995 // We generate a UMUL_LOHI and then check if the high word is 0.
3996 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3997 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3998 DAG.getVTList(Op.getValueType(), Op.getValueType()),
3999 LHS, RHS);
4000 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4001 DAG.getConstant(0, dl, MVT::i32));
4002 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4003 break;
4004 case ISD::SMULO:
4005 // We generate a SMUL_LOHI and then check if all the bits of the high word
4006 // are the same as the sign bit of the low word.
4007 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4008 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4009 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4010 LHS, RHS);
4011 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4012 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4013 Value.getValue(0),
4014 DAG.getConstant(31, dl, MVT::i32)));
4015 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4016 break;
4017 } // switch (...)
4018
4019 return std::make_pair(Value, OverflowCmp);
4020}
4021
4022SDValue
4023ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4024 // Let legalize expand this if it isn't a legal type yet.
4025 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4026 return SDValue();
4027
4028 SDValue Value, OverflowCmp;
4029 SDValue ARMcc;
4030 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4031 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4032 SDLoc dl(Op);
4033 // We use 0 and 1 as false and true values.
4034 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4035 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4036 EVT VT = Op.getValueType();
4037
4038 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4039 ARMcc, CCR, OverflowCmp);
4040
4041 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4042 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4043}
4044
4045static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4046 SelectionDAG &DAG) {
4047 SDLoc DL(BoolCarry);
4048 EVT CarryVT = BoolCarry.getValueType();
4049
4050 // This converts the boolean value carry into the carry flag by doing
4051 // ARMISD::SUBC Carry, 1
4052 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4053 DAG.getVTList(CarryVT, MVT::i32),
4054 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4055 return Carry.getValue(1);
4056}
4057
4058static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4059 SelectionDAG &DAG) {
4060 SDLoc DL(Flags);
4061
4062 // Now convert the carry flag into a boolean carry. We do this
4063 // using ARMISD:ADDE 0, 0, Carry
4064 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4065 DAG.getConstant(0, DL, MVT::i32),
4066 DAG.getConstant(0, DL, MVT::i32), Flags);
4067}
4068
4069SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4070 SelectionDAG &DAG) const {
4071 // Let legalize expand this if it isn't a legal type yet.
4072 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4073 return SDValue();
4074
4075 SDValue LHS = Op.getOperand(0);
4076 SDValue RHS = Op.getOperand(1);
4077 SDLoc dl(Op);
4078
4079 EVT VT = Op.getValueType();
4080 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4081 SDValue Value;
4082 SDValue Overflow;
4083 switch (Op.getOpcode()) {
4084 default:
4085 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4085)
;
4086 case ISD::UADDO:
4087 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4088 // Convert the carry flag into a boolean value.
4089 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4090 break;
4091 case ISD::USUBO: {
4092 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4093 // Convert the carry flag into a boolean value.
4094 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4095 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4096 // value. So compute 1 - C.
4097 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4098 DAG.getConstant(1, dl, MVT::i32), Overflow);
4099 break;
4100 }
4101 }
4102
4103 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4104}
4105
4106SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4107 SDValue Cond = Op.getOperand(0);
4108 SDValue SelectTrue = Op.getOperand(1);
4109 SDValue SelectFalse = Op.getOperand(2);
4110 SDLoc dl(Op);
4111 unsigned Opc = Cond.getOpcode();
4112
4113 if (Cond.getResNo() == 1 &&
4114 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4115 Opc == ISD::USUBO)) {
4116 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4117 return SDValue();
4118
4119 SDValue Value, OverflowCmp;
4120 SDValue ARMcc;
4121 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4122 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4123 EVT VT = Op.getValueType();
4124
4125 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4126 OverflowCmp, DAG);
4127 }
4128
4129 // Convert:
4130 //
4131 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4132 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4133 //
4134 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4135 const ConstantSDNode *CMOVTrue =
4136 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4137 const ConstantSDNode *CMOVFalse =
4138 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4139
4140 if (CMOVTrue && CMOVFalse) {
4141 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4142 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4143
4144 SDValue True;
4145 SDValue False;
4146 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4147 True = SelectTrue;
4148 False = SelectFalse;
4149 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4150 True = SelectFalse;
4151 False = SelectTrue;
4152 }
4153
4154 if (True.getNode() && False.getNode()) {
4155 EVT VT = Op.getValueType();
4156 SDValue ARMcc = Cond.getOperand(2);
4157 SDValue CCR = Cond.getOperand(3);
4158 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4159 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4159, __extension__ __PRETTY_FUNCTION__))
;
4160 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4161 }
4162 }
4163 }
4164
4165 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4166 // undefined bits before doing a full-word comparison with zero.
4167 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4168 DAG.getConstant(1, dl, Cond.getValueType()));
4169
4170 return DAG.getSelectCC(dl, Cond,
4171 DAG.getConstant(0, dl, Cond.getValueType()),
4172 SelectTrue, SelectFalse, ISD::SETNE);
4173}
4174
4175static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4176 bool &swpCmpOps, bool &swpVselOps) {
4177 // Start by selecting the GE condition code for opcodes that return true for
4178 // 'equality'
4179 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4180 CC == ISD::SETULE)
4181 CondCode = ARMCC::GE;
4182
4183 // and GT for opcodes that return false for 'equality'.
4184 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4185 CC == ISD::SETULT)
4186 CondCode = ARMCC::GT;
4187
4188 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4189 // to swap the compare operands.
4190 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4191 CC == ISD::SETULT)
4192 swpCmpOps = true;
4193
4194 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4195 // If we have an unordered opcode, we need to swap the operands to the VSEL
4196 // instruction (effectively negating the condition).
4197 //
4198 // This also has the effect of swapping which one of 'less' or 'greater'
4199 // returns true, so we also swap the compare operands. It also switches
4200 // whether we return true for 'equality', so we compensate by picking the
4201 // opposite condition code to our original choice.
4202 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4203 CC == ISD::SETUGT) {
4204 swpCmpOps = !swpCmpOps;
4205 swpVselOps = !swpVselOps;
4206 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4207 }
4208
4209 // 'ordered' is 'anything but unordered', so use the VS condition code and
4210 // swap the VSEL operands.
4211 if (CC == ISD::SETO) {
4212 CondCode = ARMCC::VS;
4213 swpVselOps = true;
4214 }
4215
4216 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4217 // code and swap the VSEL operands.
4218 if (CC == ISD::SETUNE) {
4219 CondCode = ARMCC::EQ;
4220 swpVselOps = true;
4221 }
4222}
4223
4224SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4225 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4226 SDValue Cmp, SelectionDAG &DAG) const {
4227 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4228 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4229 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4230 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4231 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4232
4233 SDValue TrueLow = TrueVal.getValue(0);
4234 SDValue TrueHigh = TrueVal.getValue(1);
4235 SDValue FalseLow = FalseVal.getValue(0);
4236 SDValue FalseHigh = FalseVal.getValue(1);
4237
4238 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4239 ARMcc, CCR, Cmp);
4240 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4241 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4242
4243 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4244 } else {
4245 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4246 Cmp);
4247 }
4248}
4249
4250static bool isGTorGE(ISD::CondCode CC) {
4251 return CC == ISD::SETGT || CC == ISD::SETGE;
4252}
4253
4254static bool isLTorLE(ISD::CondCode CC) {
4255 return CC == ISD::SETLT || CC == ISD::SETLE;
4256}
4257
4258// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4259// All of these conditions (and their <= and >= counterparts) will do:
4260// x < k ? k : x
4261// x > k ? x : k
4262// k < x ? x : k
4263// k > x ? k : x
4264static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4265 const SDValue TrueVal, const SDValue FalseVal,
4266 const ISD::CondCode CC, const SDValue K) {
4267 return (isGTorGE(CC) &&
4268 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4269 (isLTorLE(CC) &&
4270 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4271}
4272
4273// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4274static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4275 const SDValue TrueVal, const SDValue FalseVal,
4276 const ISD::CondCode CC, const SDValue K) {
4277 return (isGTorGE(CC) &&
4278 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4279 (isLTorLE(CC) &&
4280 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4281}
4282
4283// Check if two chained conditionals could be converted into SSAT or USAT.
4284//
4285// SSAT can replace a set of two conditional selectors that bound a number to an
4286// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4287//
4288// x < -k ? -k : (x > k ? k : x)
4289// x < -k ? -k : (x < k ? x : k)
4290// x > -k ? (x > k ? k : x) : -k
4291// x < k ? (x < -k ? -k : x) : k
4292// etc.
4293//
4294// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4295// a power of 2.
4296//
4297// It returns true if the conversion can be done, false otherwise.
4298// Additionally, the variable is returned in parameter V, the constant in K and
4299// usat is set to true if the conditional represents an unsigned saturation
4300static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4301 uint64_t &K, bool &usat) {
4302 SDValue LHS1 = Op.getOperand(0);
4303 SDValue RHS1 = Op.getOperand(1);
4304 SDValue TrueVal1 = Op.getOperand(2);
4305 SDValue FalseVal1 = Op.getOperand(3);
4306 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4307
4308 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4309 if (Op2.getOpcode() != ISD::SELECT_CC)
4310 return false;
4311
4312 SDValue LHS2 = Op2.getOperand(0);
4313 SDValue RHS2 = Op2.getOperand(1);
4314 SDValue TrueVal2 = Op2.getOperand(2);
4315 SDValue FalseVal2 = Op2.getOperand(3);
4316 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4317
4318 // Find out which are the constants and which are the variables
4319 // in each conditional
4320 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4321 ? &RHS1
4322 : nullptr;
4323 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4324 ? &RHS2
4325 : nullptr;
4326 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4327 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4328 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4329 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4330
4331 // We must detect cases where the original operations worked with 16- or
4332 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4333 // must work with sign-extended values but the select operations return
4334 // the original non-extended value.
4335 SDValue V2TmpReg = V2Tmp;
4336 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4337 V2TmpReg = V2Tmp->getOperand(0);
4338
4339 // Check that the registers and the constants have the correct values
4340 // in both conditionals
4341 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4342 V2TmpReg != V2)
4343 return false;
4344
4345 // Figure out which conditional is saturating the lower/upper bound.
4346 const SDValue *LowerCheckOp =
4347 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4348 ? &Op
4349 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4350 ? &Op2
4351 : nullptr;
4352 const SDValue *UpperCheckOp =
4353 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4354 ? &Op
4355 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4356 ? &Op2
4357 : nullptr;
4358
4359 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4360 return false;
4361
4362 // Check that the constant in the lower-bound check is
4363 // the opposite of the constant in the upper-bound check
4364 // in 1's complement.
4365 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4366 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4367 int64_t PosVal = std::max(Val1, Val2);
4368 int64_t NegVal = std::min(Val1, Val2);
4369
4370 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4371 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4372 isPowerOf2_64(PosVal + 1)) {
4373
4374 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4375 if (Val1 == ~Val2)
4376 usat = false;
4377 else if (NegVal == 0)
4378 usat = true;
4379 else
4380 return false;
4381
4382 V = V2;
4383 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4384
4385 return true;
4386 }
4387
4388 return false;
4389}
4390
4391// Check if a condition of the type x < k ? k : x can be converted into a
4392// bit operation instead of conditional moves.
4393// Currently this is allowed given:
4394// - The conditions and values match up
4395// - k is 0 or -1 (all ones)
4396// This function will not check the last condition, thats up to the caller
4397// It returns true if the transformation can be made, and in such case
4398// returns x in V, and k in SatK.
4399static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4400 SDValue &SatK)
4401{
4402 SDValue LHS = Op.getOperand(0);
4403 SDValue RHS = Op.getOperand(1);
4404 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4405 SDValue TrueVal = Op.getOperand(2);
4406 SDValue FalseVal = Op.getOperand(3);
4407
4408 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4409 ? &RHS
4410 : nullptr;
4411
4412 // No constant operation in comparison, early out
4413 if (!K)
4414 return false;
4415
4416 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4417 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4418 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4419
4420 // If the constant on left and right side, or variable on left and right,
4421 // does not match, early out
4422 if (*K != KTmp || V != VTmp)
4423 return false;
4424
4425 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4426 SatK = *K;
4427 return true;
4428 }
4429
4430 return false;
4431}
4432
4433SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4434 EVT VT = Op.getValueType();
4435 SDLoc dl(Op);
4436
4437 // Try to convert two saturating conditional selects into a single SSAT
4438 SDValue SatValue;
4439 uint64_t SatConstant;
4440 bool SatUSat;
4441 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4442 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4443 if (SatUSat)
4444 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4445 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4446 else
4447 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4448 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4449 }
4450
4451 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4452 // into more efficient bit operations, which is possible when k is 0 or -1
4453 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4454 // single instructions. On Thumb the shift and the bit operation will be two
4455 // instructions.
4456 // Only allow this transformation on full-width (32-bit) operations
4457 SDValue LowerSatConstant;
4458 if (VT == MVT::i32 &&
4459 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4460 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4461 DAG.getConstant(31, dl, VT));
4462 if (isNullConstant(LowerSatConstant)) {
4463 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4464 DAG.getAllOnesConstant(dl, VT));
4465 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4466 } else if (isAllOnesConstant(LowerSatConstant))
4467 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4468 }
4469
4470 SDValue LHS = Op.getOperand(0);
4471 SDValue RHS = Op.getOperand(1);
4472 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4473 SDValue TrueVal = Op.getOperand(2);
4474 SDValue FalseVal = Op.getOperand(3);
4475
4476 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4477 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4478 dl);
4479
4480 // If softenSetCCOperands only returned one value, we should compare it to
4481 // zero.
4482 if (!RHS.getNode()) {
4483 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4484 CC = ISD::SETNE;
4485 }
4486 }
4487
4488 if (LHS.getValueType() == MVT::i32) {
4489 // Try to generate VSEL on ARMv8.
4490 // The VSEL instruction can't use all the usual ARM condition
4491 // codes: it only has two bits to select the condition code, so it's
4492 // constrained to use only GE, GT, VS and EQ.
4493 //
4494 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4495 // swap the operands of the previous compare instruction (effectively
4496 // inverting the compare condition, swapping 'less' and 'greater') and
4497 // sometimes need to swap the operands to the VSEL (which inverts the
4498 // condition in the sense of firing whenever the previous condition didn't)
4499 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4500 TrueVal.getValueType() == MVT::f64)) {
4501 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4502 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4503 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4504 CC = ISD::getSetCCInverse(CC, true);
4505 std::swap(TrueVal, FalseVal);
4506 }
4507 }
4508
4509 SDValue ARMcc;
4510 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4511 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4512 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4513 }
4514
4515 ARMCC::CondCodes CondCode, CondCode2;
4516 bool InvalidOnQNaN;
4517 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4518
4519 // Normalize the fp compare. If RHS is zero we keep it there so we match
4520 // CMPFPw0 instead of CMPFP.
4521 if (Subtarget->hasFPARMv8() && !isFloatingPointZero(RHS) &&
4522 (TrueVal.getValueType() == MVT::f16 ||
4523 TrueVal.getValueType() == MVT::f32 ||
4524 TrueVal.getValueType() == MVT::f64)) {
4525 bool swpCmpOps = false;
4526 bool swpVselOps = false;
4527 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4528
4529 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4530 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4531 if (swpCmpOps)
4532 std::swap(LHS, RHS);
4533 if (swpVselOps)
4534 std::swap(TrueVal, FalseVal);
4535 }
4536 }
4537
4538 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4539 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4540 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4541 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4542 if (CondCode2 != ARMCC::AL) {
4543 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4544 // FIXME: Needs another CMP because flag can have but one use.
4545 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4546 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4547 }
4548 return Result;
4549}
4550
4551/// canChangeToInt - Given the fp compare operand, return true if it is suitable
4552/// to morph to an integer compare sequence.
4553static bool canChangeToInt(SDValue Op, bool &SeenZero,
4554 const ARMSubtarget *Subtarget) {
4555 SDNode *N = Op.getNode();
4556 if (!N->hasOneUse())
4557 // Otherwise it requires moving the value from fp to integer registers.
4558 return false;
4559 if (!N->getNumValues())
4560 return false;
4561 EVT VT = Op.getValueType();
4562 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4563 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4564 // vmrs are very slow, e.g. cortex-a8.
4565 return false;
4566
4567 if (isFloatingPointZero(Op)) {
4568 SeenZero = true;
4569 return true;
4570 }
4571 return ISD::isNormalLoad(N);
4572}
4573
4574static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4575 if (isFloatingPointZero(Op))
4576 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4577
4578 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4579 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4580 Ld->getPointerInfo(), Ld->getAlignment(),
4581 Ld->getMemOperand()->getFlags());
4582
4583 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4583)
;
4584}
4585
4586static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4587 SDValue &RetVal1, SDValue &RetVal2) {
4588 SDLoc dl(Op);
4589
4590 if (isFloatingPointZero(Op)) {
4591 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4592 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4593 return;
4594 }
4595
4596 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4597 SDValue Ptr = Ld->getBasePtr();
4598 RetVal1 =
4599 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4600 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4601
4602 EVT PtrType = Ptr.getValueType();
4603 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4604 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4605 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4606 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4607 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4608 Ld->getMemOperand()->getFlags());
4609 return;
4610 }
4611
4612 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4612)
;
4613}
4614
4615/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4616/// f32 and even f64 comparisons to integer ones.
4617SDValue
4618ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4619 SDValue Chain = Op.getOperand(0);
4620 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4621 SDValue LHS = Op.getOperand(2);
4622 SDValue RHS = Op.getOperand(3);
4623 SDValue Dest = Op.getOperand(4);
4624 SDLoc dl(Op);
4625
4626 bool LHSSeenZero = false;
4627 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4628 bool RHSSeenZero = false;
4629 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4630 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4631 // If unsafe fp math optimization is enabled and there are no other uses of
4632 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4633 // to an integer comparison.
4634 if (CC == ISD::SETOEQ)
4635 CC = ISD::SETEQ;
4636 else if (CC == ISD::SETUNE)
4637 CC = ISD::SETNE;
4638
4639 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4640 SDValue ARMcc;
4641 if (LHS.getValueType() == MVT::f32) {
4642 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4643 bitcastf32Toi32(LHS, DAG), Mask);
4644 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4645 bitcastf32Toi32(RHS, DAG), Mask);
4646 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4647 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4648 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4649 Chain, Dest, ARMcc, CCR, Cmp);
4650 }
4651
4652 SDValue LHS1, LHS2;
4653 SDValue RHS1, RHS2;
4654 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4655 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4656 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4657 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4658 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4659 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4660 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4661 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4662 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4663 }
4664
4665 return SDValue();
4666}
4667
4668SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4669 SDValue Chain = Op.getOperand(0);
4670 SDValue Cond = Op.getOperand(1);
4671 SDValue Dest = Op.getOperand(2);
4672 SDLoc dl(Op);
4673
4674 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4675 // instruction.
4676 unsigned Opc = Cond.getOpcode();
4677 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4678 !Subtarget->isThumb1Only();
4679 if (Cond.getResNo() == 1 &&
4680 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4681 Opc == ISD::USUBO || OptimizeMul)) {
4682 // Only lower legal XALUO ops.
4683 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4684 return SDValue();
4685
4686 // The actual operation with overflow check.
4687 SDValue Value, OverflowCmp;
4688 SDValue ARMcc;
4689 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4690
4691 // Reverse the condition code.
4692 ARMCC::CondCodes CondCode =
4693 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4694 CondCode = ARMCC::getOppositeCondition(CondCode);
4695 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4696 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4697
4698 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4699 OverflowCmp);
4700 }
4701
4702 return SDValue();
4703}
4704
4705SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4706 SDValue Chain = Op.getOperand(0);
4707 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4708 SDValue LHS = Op.getOperand(2);
4709 SDValue RHS = Op.getOperand(3);
4710 SDValue Dest = Op.getOperand(4);
4711 SDLoc dl(Op);
4712
4713 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4714 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4715 dl);
4716
4717 // If softenSetCCOperands only returned one value, we should compare it to
4718 // zero.
4719 if (!RHS.getNode()) {
4720 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4721 CC = ISD::SETNE;
4722 }
4723 }
4724
4725 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4726 // instruction.
4727 unsigned Opc = LHS.getOpcode();
4728 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4729 !Subtarget->isThumb1Only();
4730 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4731 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4732 Opc == ISD::USUBO || OptimizeMul) &&
4733 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4734 // Only lower legal XALUO ops.
4735 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4736 return SDValue();
4737
4738 // The actual operation with overflow check.
4739 SDValue Value, OverflowCmp;
4740 SDValue ARMcc;
4741 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4742
4743 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4744 // Reverse the condition code.
4745 ARMCC::CondCodes CondCode =
4746 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4747 CondCode = ARMCC::getOppositeCondition(CondCode);
4748 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4749 }
4750 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4751
4752 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4753 OverflowCmp);
4754 }
4755
4756 if (LHS.getValueType() == MVT::i32) {
4757 SDValue ARMcc;
4758 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4759 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4760 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4761 Chain, Dest, ARMcc, CCR, Cmp);
4762 }
4763
4764 if (getTargetMachine().Options.UnsafeFPMath &&
4765 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4766 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4767 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4768 return Result;
4769 }
4770
4771 ARMCC::CondCodes CondCode, CondCode2;
4772 bool InvalidOnQNaN;
4773 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4774
4775 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4776 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4777 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4778 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4779 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4780 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4781 if (CondCode2 != ARMCC::AL) {
4782 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4783 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4784 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4785 }
4786 return Res;
4787}
4788
4789SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4790 SDValue Chain = Op.getOperand(0);
4791 SDValue Table = Op.getOperand(1);
4792 SDValue Index = Op.getOperand(2);
4793 SDLoc dl(Op);
4794
4795 EVT PTy = getPointerTy(DAG.getDataLayout());
4796 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4797 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4798 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4799 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4800 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4801 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4802 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4803 // which does another jump to the destination. This also makes it easier
4804 // to translate it to TBB / TBH later (Thumb2 only).
4805 // FIXME: This might not work if the function is extremely large.
4806 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4807 Addr, Op.getOperand(2), JTI);
4808 }
4809 if (isPositionIndependent() || Subtarget->isROPI()) {
4810 Addr =
4811 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4812 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4813 Chain = Addr.getValue(1);
4814 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4815 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4816 } else {
4817 Addr =
4818 DAG.getLoad(PTy, dl, Chain, Addr,
4819 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4820 Chain = Addr.getValue(1);
4821 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4822 }
4823}
4824
4825static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4826 EVT VT = Op.getValueType();
4827 SDLoc dl(Op);
4828
4829 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4830 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4831 return Op;
4832 return DAG.UnrollVectorOp(Op.getNode());
4833 }
4834
4835 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4836, __extension__ __PRETTY_FUNCTION__))
4836 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4836, __extension__ __PRETTY_FUNCTION__))
;
4837 if (VT != MVT::v4i16)
4838 return DAG.UnrollVectorOp(Op.getNode());
4839
4840 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
4841 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4842}
4843
4844SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4845 EVT VT = Op.getValueType();
4846 if (VT.isVector())
4847 return LowerVectorFP_TO_INT(Op, DAG);
4848 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4849 RTLIB::Libcall LC;
4850 if (Op.getOpcode() == ISD::FP_TO_SINT)
4851 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4852 Op.getValueType());
4853 else
4854 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4855 Op.getValueType());
4856 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4857 /*isSigned*/ false, SDLoc(Op)).first;
4858 }
4859
4860 return Op;
4861}
4862
4863static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4864 EVT VT = Op.getValueType();
4865 SDLoc dl(Op);
4866
4867 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4868 if (VT.getVectorElementType() == MVT::f32)
4869 return Op;
4870 return DAG.UnrollVectorOp(Op.getNode());
4871 }
4872
4873 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4874, __extension__ __PRETTY_FUNCTION__))
4874 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4874, __extension__ __PRETTY_FUNCTION__))
;
4875 if (VT != MVT::v4f32)
4876 return DAG.UnrollVectorOp(Op.getNode());
4877
4878 unsigned CastOpc;
4879 unsigned Opc;
4880 switch (Op.getOpcode()) {
4881 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 4881)
;
4882 case ISD::SINT_TO_FP:
4883 CastOpc = ISD::SIGN_EXTEND;
4884 Opc = ISD::SINT_TO_FP;
4885 break;
4886 case ISD::UINT_TO_FP:
4887 CastOpc = ISD::ZERO_EXTEND;
4888 Opc = ISD::UINT_TO_FP;
4889 break;
4890 }
4891
4892 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4893 return DAG.getNode(Opc, dl, VT, Op);
4894}
4895
4896SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4897 EVT VT = Op.getValueType();
4898 if (VT.isVector())
4899 return LowerVectorINT_TO_FP(Op, DAG);
4900 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4901 RTLIB::Libcall LC;
4902 if (Op.getOpcode() == ISD::SINT_TO_FP)
4903 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4904 Op.getValueType());
4905 else
4906 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4907 Op.getValueType());
4908 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4909 /*isSigned*/ false, SDLoc(Op)).first;
4910 }
4911
4912 return Op;
4913}
4914
4915SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4916 // Implement fcopysign with a fabs and a conditional fneg.
4917 SDValue Tmp0 = Op.getOperand(0);
4918 SDValue Tmp1 = Op.getOperand(1);
4919 SDLoc dl(Op);
4920 EVT VT = Op.getValueType();
4921 EVT SrcVT = Tmp1.getValueType();
4922 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4923 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4924 bool UseNEON = !InGPR && Subtarget->hasNEON();
4925
4926 if (UseNEON) {
4927 // Use VBSL to copy the sign bit.
4928 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4929 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4930 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4931 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4932 if (VT == MVT::f64)
4933 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4934 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4935 DAG.getConstant(32, dl, MVT::i32));
4936 else /*if (VT == MVT::f32)*/
4937 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4938 if (SrcVT == MVT::f32) {
4939 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4940 if (VT == MVT::f64)
4941 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4942 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4943 DAG.getConstant(32, dl, MVT::i32));
4944 } else if (VT == MVT::f32)
4945 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4946 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4947 DAG.getConstant(32, dl, MVT::i32));
4948 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4949 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4950
4951 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4952 dl, MVT::i32);
4953 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4954 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4955 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4956
4957 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4958 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4959 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4960 if (VT == MVT::f32) {
4961 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4962 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4963 DAG.getConstant(0, dl, MVT::i32));
4964 } else {
4965 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4966 }
4967
4968 return Res;
4969 }
4970
4971 // Bitcast operand 1 to i32.
4972 if (SrcVT == MVT::f64)
4973 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4974 Tmp1).getValue(1);
4975 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4976
4977 // Or in the signbit with integer operations.
4978 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4979 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4980 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4981 if (VT == MVT::f32) {
4982 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4983 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4984 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4985 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4986 }
4987
4988 // f64: Or the high part with signbit and then combine two parts.
4989 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4990 Tmp0);
4991 SDValue Lo = Tmp0.getValue(0);
4992 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4993 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4994 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4995}
4996
4997SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4998 MachineFunction &MF = DAG.getMachineFunction();
4999 MachineFrameInfo &MFI = MF.getFrameInfo();
5000 MFI.setReturnAddressIsTaken(true);
5001
5002 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5003 return SDValue();
5004
5005 EVT VT = Op.getValueType();
5006 SDLoc dl(Op);
5007 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5008 if (Depth) {
5009 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5010 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5011 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5012 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5013 MachinePointerInfo());
5014 }
5015
5016 // Return LR, which contains the return address. Mark it an implicit live-in.
5017 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5018 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5019}
5020
5021SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5022 const ARMBaseRegisterInfo &ARI =
5023 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5024 MachineFunction &MF = DAG.getMachineFunction();
5025 MachineFrameInfo &MFI = MF.getFrameInfo();
5026 MFI.setFrameAddressIsTaken(true);
5027
5028 EVT VT = Op.getValueType();
5029 SDLoc dl(Op); // FIXME probably not meaningful
5030 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5031 unsigned FrameReg = ARI.getFrameRegister(MF);
5032 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5033 while (Depth--)
5034 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5035 MachinePointerInfo());
5036 return FrameAddr;
5037}
5038
5039// FIXME? Maybe this could be a TableGen attribute on some registers and
5040// this table could be generated automatically from RegInfo.
5041unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5042 SelectionDAG &DAG) const {
5043 unsigned Reg = StringSwitch<unsigned>(RegName)
5044 .Case("sp", ARM::SP)
5045 .Default(0);
5046 if (Reg)
5047 return Reg;
5048 report_fatal_error(Twine("Invalid register name \""
5049 + StringRef(RegName) + "\"."));
5050}
5051
5052// Result is 64 bit value so split into two 32 bit values and return as a
5053// pair of values.
5054static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5055 SelectionDAG &DAG) {
5056 SDLoc DL(N);
5057
5058 // This function is only supposed to be called for i64 type destination.
5059 assert(N->getValueType(0) == MVT::i64(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5060, __extension__ __PRETTY_FUNCTION__))
5060 && "ExpandREAD_REGISTER called for non-i64 type result.")(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5060, __extension__ __PRETTY_FUNCTION__))
;
5061
5062 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5063 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5064 N->getOperand(0),
5065 N->getOperand(1));
5066
5067 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5068 Read.getValue(1)));
5069 Results.push_back(Read.getOperand(0));
5070}
5071
5072/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5073/// When \p DstVT, the destination type of \p BC, is on the vector
5074/// register bank and the source of bitcast, \p Op, operates on the same bank,
5075/// it might be possible to combine them, such that everything stays on the
5076/// vector register bank.
5077/// \p return The node that would replace \p BT, if the combine
5078/// is possible.
5079static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5080 SelectionDAG &DAG) {
5081 SDValue Op = BC->getOperand(0);
5082 EVT DstVT = BC->getValueType(0);
5083
5084 // The only vector instruction that can produce a scalar (remember,
5085 // since the bitcast was about to be turned into VMOVDRR, the source
5086 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5087 // Moreover, we can do this combine only if there is one use.
5088 // Finally, if the destination type is not a vector, there is not
5089 // much point on forcing everything on the vector bank.
5090 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5091 !Op.hasOneUse())
5092 return SDValue();
5093
5094 // If the index is not constant, we will introduce an additional
5095 // multiply that will stick.
5096 // Give up in that case.
5097 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5098 if (!Index)
5099 return SDValue();
5100 unsigned DstNumElt = DstVT.getVectorNumElements();
5101
5102 // Compute the new index.
5103 const APInt &APIntIndex = Index->getAPIntValue();
5104 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5105 NewIndex *= APIntIndex;
5106 // Check if the new constant index fits into i32.
5107 if (NewIndex.getBitWidth() > 32)
5108 return SDValue();
5109
5110 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5111 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5112 SDLoc dl(Op);
5113 SDValue ExtractSrc = Op.getOperand(0);
5114 EVT VecVT = EVT::getVectorVT(
5115 *DAG.getContext(), DstVT.getScalarType(),
5116 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5117 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5118 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5119 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5120}
5121
5122/// ExpandBITCAST - If the target supports VFP, this function is called to
5123/// expand a bit convert where either the source or destination type is i64 to
5124/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5125/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5126/// vectors), since the legalizer won't know what to do with that.
5127static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5128 const ARMSubtarget *Subtarget) {
5129 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5130 SDLoc dl(N);
5131 SDValue Op = N->getOperand(0);
5132
5133 // This function is only supposed to be called for i64 types, either as the
5134 // source or destination of the bit convert.
5135 EVT SrcVT = Op.getValueType();
5136 EVT DstVT = N->getValueType(0);
5137 const bool HasFullFP16 = Subtarget->hasFullFP16();
5138
5139 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5140 // FullFP16: half values are passed in S-registers, and we don't
5141 // need any of the bitcast and moves:
5142 //
5143 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5144 // t5: i32 = bitcast t2
5145 // t18: f16 = ARMISD::VMOVhr t5
5146 if (Op.getOpcode() != ISD::CopyFromReg ||
5147 Op.getValueType() != MVT::f32)
5148 return SDValue();
5149
5150 auto Move = N->use_begin();
5151 if (Move->getOpcode() != ARMISD::VMOVhr)
5152 return SDValue();
5153
5154 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5155 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5156 DAG.ReplaceAllUsesWith(*Move, &Copy);
5157 return Copy;
5158 }
5159
5160 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5161 if (!HasFullFP16)
5162 return SDValue();
5163 // SoftFP: read half-precision arguments:
5164 //
5165 // t2: i32,ch = ...
5166 // t7: i16 = truncate t2 <~~~~ Op
5167 // t8: f16 = bitcast t7 <~~~~ N
5168 //
5169 if (Op.getOperand(0).getValueType() == MVT::i32)
5170 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5171 MVT::f16, Op.getOperand(0));
5172
5173 return SDValue();
5174 }
5175
5176 // Half-precision return values
5177 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5178 if (!HasFullFP16)
5179 return SDValue();
5180 //
5181 // t11: f16 = fadd t8, t10
5182 // t12: i16 = bitcast t11 <~~~ SDNode N
5183 // t13: i32 = zero_extend t12
5184 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5185 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5186 //
5187 // transform this into:
5188 //
5189 // t20: i32 = ARMISD::VMOVrh t11
5190 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5191 //
5192 auto ZeroExtend = N->use_begin();
5193 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5194 ZeroExtend->getValueType(0) != MVT::i32)
5195 return SDValue();
5196
5197 auto Copy = ZeroExtend->use_begin();
5198 if (Copy->getOpcode() == ISD::CopyToReg &&
5199 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5200 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5201 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5202 return Cvt;
5203 }
5204 return SDValue();
5205 }
5206
5207 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5208 return SDValue();
5209
5210 // Turn i64->f64 into VMOVDRR.
5211 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5212 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5213 // if we can combine the bitcast with its source.
5214 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5215 return Val;
5216
5217 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5218 DAG.getConstant(0, dl, MVT::i32));
5219 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5220 DAG.getConstant(1, dl, MVT::i32));
5221 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5222 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5223 }
5224
5225 // Turn f64->i64 into VMOVRRD.
5226 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5227 SDValue Cvt;
5228 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5229 SrcVT.getVectorNumElements() > 1)
5230 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5231 DAG.getVTList(MVT::i32, MVT::i32),
5232 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5233 else
5234 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5235 DAG.getVTList(MVT::i32, MVT::i32), Op);
5236 // Merge the pieces into a single i64 value.
5237 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5238 }
5239
5240 return SDValue();
5241}
5242
5243/// getZeroVector - Returns a vector of specified type with all zero elements.
5244/// Zero vectors are used to represent vector negation and in those cases
5245/// will be implemented with the NEON VNEG instruction. However, VNEG does
5246/// not support i64 elements, so sometimes the zero vectors will need to be
5247/// explicitly constructed. Regardless, use a canonical VMOV to create the
5248/// zero vector.
5249static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5250 assert(VT.isVector() && "Expected a vector type")(static_cast <bool> (VT.isVector() && "Expected a vector type"
) ? void (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5250, __extension__ __PRETTY_FUNCTION__))
;
5251 // The canonical modified immediate encoding of a zero vector is....0!
5252 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5253 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5254 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5255 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5256}
5257
5258/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5259/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5260SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5261 SelectionDAG &DAG) const {
5262 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5262, __extension__ __PRETTY_FUNCTION__))
;
5263 EVT VT = Op.getValueType();
5264 unsigned VTBits = VT.getSizeInBits();
5265 SDLoc dl(Op);
5266 SDValue ShOpLo = Op.getOperand(0);
5267 SDValue ShOpHi = Op.getOperand(1);
5268 SDValue ShAmt = Op.getOperand(2);
5269 SDValue ARMcc;
5270 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5271 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5272
5273 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SRA_PARTS ||
Op.getOpcode() == ISD::SRL_PARTS) ? void (0) : __assert_fail
("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5273, __extension__ __PRETTY_FUNCTION__))
;
5274
5275 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5276 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5277 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5278 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5279 DAG.getConstant(VTBits, dl, MVT::i32));
5280 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5281 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5282 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5283 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5284 ISD::SETGE, ARMcc, DAG, dl);
5285 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5286 ARMcc, CCR, CmpLo);
5287
5288 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5289 SDValue HiBigShift = Opc == ISD::SRA
5290 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5291 DAG.getConstant(VTBits - 1, dl, VT))
5292 : DAG.getConstant(0, dl, VT);
5293 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5294 ISD::SETGE, ARMcc, DAG, dl);
5295 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5296 ARMcc, CCR, CmpHi);
5297
5298 SDValue Ops[2] = { Lo, Hi };
5299 return DAG.getMergeValues(Ops, dl);
5300}
5301
5302/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5303/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5304SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5305 SelectionDAG &DAG) const {
5306 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5306, __extension__ __PRETTY_FUNCTION__))
;
5307 EVT VT = Op.getValueType();
5308 unsigned VTBits = VT.getSizeInBits();
5309 SDLoc dl(Op);
5310 SDValue ShOpLo = Op.getOperand(0);
5311 SDValue ShOpHi = Op.getOperand(1);
5312 SDValue ShAmt = Op.getOperand(2);
5313 SDValue ARMcc;
5314 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5315
5316 assert(Op.getOpcode() == ISD::SHL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SHL_PARTS) ?
void (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5316, __extension__ __PRETTY_FUNCTION__))
;
5317 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5318 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5319 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5320 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5321 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5322
5323 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5324 DAG.getConstant(VTBits, dl, MVT::i32));
5325 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5326 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5327 ISD::SETGE, ARMcc, DAG, dl);
5328 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5329 ARMcc, CCR, CmpHi);
5330
5331 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5332 ISD::SETGE, ARMcc, DAG, dl);
5333 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5334 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5335 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5336
5337 SDValue Ops[2] = { Lo, Hi };
5338 return DAG.getMergeValues(Ops, dl);
5339}
5340
5341SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5342 SelectionDAG &DAG) const {
5343 // The rounding mode is in bits 23:22 of the FPSCR.
5344 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5345 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5346 // so that the shift + and get folded into a bitfield extract.
5347 SDLoc dl(Op);
5348 SDValue Ops[] = { DAG.getEntryNode(),
5349 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5350
5351 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5352 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5353 DAG.getConstant(1U << 22, dl, MVT::i32));
5354 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5355 DAG.getConstant(22, dl, MVT::i32));
5356 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5357 DAG.getConstant(3, dl, MVT::i32));
5358}
5359
5360static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5361 const ARMSubtarget *ST) {
5362 SDLoc dl(N);
5363 EVT VT = N->getValueType(0);
5364 if (VT.isVector()) {
5365 assert(ST->hasNEON())(static_cast <bool> (ST->hasNEON()) ? void (0) : __assert_fail
("ST->hasNEON()", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5365, __extension__ __PRETTY_FUNCTION__))
;
5366
5367 // Compute the least significant set bit: LSB = X & -X
5368 SDValue X = N->getOperand(0);
5369 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5370 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5371
5372 EVT ElemTy = VT.getVectorElementType();
5373
5374 if (ElemTy == MVT::i8) {
5375 // Compute with: cttz(x) = ctpop(lsb - 1)
5376 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5377 DAG.getTargetConstant(1, dl, ElemTy));
5378 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5379 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5380 }
5381
5382 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5383 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5384 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5385 unsigned NumBits = ElemTy.getSizeInBits();
5386 SDValue WidthMinus1 =
5387 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5388 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5389 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5390 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5391 }
5392
5393 // Compute with: cttz(x) = ctpop(lsb - 1)
5394
5395 // Since we can only compute the number of bits in a byte with vcnt.8, we
5396 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
5397 // and i64.
5398
5399 // Compute LSB - 1.
5400 SDValue Bits;
5401 if (ElemTy == MVT::i64) {
5402 // Load constant 0xffff'ffff'ffff'ffff to register.
5403 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5404 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5405 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5406 } else {
5407 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5408 DAG.getTargetConstant(1, dl, ElemTy));
5409 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5410 }
5411
5412 // Count #bits with vcnt.8.
5413 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5414 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
5415 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
5416
5417 // Gather the #bits with vpaddl (pairwise add.)
5418 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5419 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
5420 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5421 Cnt8);
5422 if (ElemTy == MVT::i16)
5423 return Cnt16;
5424
5425 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
5426 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
5427 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5428 Cnt16);
5429 if (ElemTy == MVT::i32)
5430 return Cnt32;
5431
5432 assert(ElemTy == MVT::i64)(static_cast <bool> (ElemTy == MVT::i64) ? void (0) : __assert_fail
("ElemTy == MVT::i64", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5432, __extension__ __PRETTY_FUNCTION__))
;
5433 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5434 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5435 Cnt32);
5436 return Cnt64;
5437 }
5438
5439 if (!ST->hasV6T2Ops())
5440 return SDValue();
5441
5442 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5443 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5444}
5445
5446/// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
5447/// for each 16-bit element from operand, repeated. The basic idea is to
5448/// leverage vcnt to get the 8-bit counts, gather and add the results.
5449///
5450/// Trace for v4i16:
5451/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5452/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
5453/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
5454/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
5455/// [b0 b1 b2 b3 b4 b5 b6 b7]
5456/// +[b1 b0 b3 b2 b5 b4 b7 b6]
5457/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
5458/// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
5459static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
5460 EVT VT = N->getValueType(0);
5461 SDLoc DL(N);
5462
5463 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5464 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
5465 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
5466 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
5467 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
5468 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
5469}
5470
5471/// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
5472/// bit-count for each 16-bit element from the operand. We need slightly
5473/// different sequencing for v4i16 and v8i16 to stay within NEON's available
5474/// 64/128-bit registers.
5475///
5476/// Trace for v4i16:
5477/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5478/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
5479/// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
5480/// v4i16:Extracted = [k0 k1 k2 k3 ]
5481static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
5482 EVT VT = N->getValueType(0);
5483 SDLoc DL(N);
5484
5485 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
5486 if (VT.is64BitVector()) {
5487 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
5488 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
5489 DAG.getIntPtrConstant(0, DL));
5490 } else {
5491 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
5492 BitCounts, DAG.getIntPtrConstant(0, DL));
5493 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
5494 }
5495}
5496
5497/// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
5498/// bit-count for each 32-bit element from the operand. The idea here is
5499/// to split the vector into 16-bit elements, leverage the 16-bit count
5500/// routine, and then combine the results.
5501///
5502/// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
5503/// input = [v0 v1 ] (vi: 32-bit elements)
5504/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
5505/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
5506/// vrev: N0 = [k1 k0 k3 k2 ]
5507/// [k0 k1 k2 k3 ]
5508/// N1 =+[k1 k0 k3 k2 ]
5509/// [k0 k2 k1 k3 ]
5510/// N2 =+[k1 k3 k0 k2 ]
5511/// [k0 k2 k1 k3 ]
5512/// Extended =+[k1 k3 k0 k2 ]
5513/// [k0 k2 ]
5514/// Extracted=+[k1 k3 ]
5515///
5516static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
5517 EVT VT = N->getValueType(0);
5518 SDLoc DL(N);
5519
5520 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5521
5522 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
5523 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
5524 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
5525 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5526 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
5527
5528 if (VT.is64BitVector()) {
5529 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
5530 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
5531 DAG.getIntPtrConstant(0, DL));
5532 } else {
5533 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
5534 DAG.getIntPtrConstant(0, DL));
5535 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
5536 }
5537}
5538
5539static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5540 const ARMSubtarget *ST) {
5541 EVT VT = N->getValueType(0);
5542
5543 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")(static_cast <bool> (ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? void (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5543, __extension__ __PRETTY_FUNCTION__))
;
5544 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
5545 VT == MVT::v4i16 || VT == MVT::v8i16) &&(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
5546 "Unexpected type for custom ctpop lowering")(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5546, __extension__ __PRETTY_FUNCTION__))
;
5547
5548 if (VT.getVectorElementType() == MVT::i32)
5549 return lowerCTPOP32BitElements(N, DAG);
5550 else
5551 return lowerCTPOP16BitElements(N, DAG);
5552}
5553
5554static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5555 const ARMSubtarget *ST) {
5556 EVT VT = N->getValueType(0);
5557 SDLoc dl(N);
5558
5559 if (!VT.isVector())
5560 return SDValue();
5561
5562 // Lower vector shifts on NEON to use VSHL.
5563 assert(ST->hasNEON() && "unexpected vector shift")(static_cast <bool> (ST->hasNEON() && "unexpected vector shift"
) ? void (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5563, __extension__ __PRETTY_FUNCTION__))
;
5564
5565 // Left shifts translate directly to the vshiftu intrinsic.
5566 if (N->getOpcode() == ISD::SHL)
5567 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5568 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5569 MVT::i32),
5570 N->getOperand(0), N->getOperand(1));
5571
5572 assert((N->getOpcode() == ISD::SRA ||(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5573, __extension__ __PRETTY_FUNCTION__))
5573 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5573, __extension__ __PRETTY_FUNCTION__))
;
5574
5575 // NEON uses the same intrinsics for both left and right shifts. For
5576 // right shifts, the shift amounts are negative, so negate the vector of
5577 // shift amounts.
5578 EVT ShiftVT = N->getOperand(1).getValueType();
5579 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5580 getZeroVector(ShiftVT, DAG, dl),
5581 N->getOperand(1));
5582 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5583 Intrinsic::arm_neon_vshifts :
5584 Intrinsic::arm_neon_vshiftu);
5585 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5586 DAG.getConstant(vshiftInt, dl, MVT::i32),
5587 N->getOperand(0), NegatedCount);
5588}
5589
5590static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5591 const ARMSubtarget *ST) {
5592 EVT VT = N->getValueType(0);
5593 SDLoc dl(N);
5594
5595 // We can get here for a node like i32 = ISD::SHL i32, i64
5596 if (VT != MVT::i64)
5597 return SDValue();
5598
5599 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5600, __extension__ __PRETTY_FUNCTION__))
5600 "Unknown shift to lower!")(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5600, __extension__ __PRETTY_FUNCTION__))
;
5601
5602 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5603 if (!isOneConstant(N->getOperand(1)))
5604 return SDValue();
5605
5606 // If we are in thumb mode, we don't have RRX.
5607 if (ST->isThumb1Only()) return SDValue();
5608
5609 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5610 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5611 DAG.getConstant(0, dl, MVT::i32));
5612 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5613 DAG.getConstant(1, dl, MVT::i32));
5614
5615 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5616 // captures the result into a carry flag.
5617 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5618 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5619
5620 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5621 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5622
5623 // Merge the pieces into a single i64 value.
5624 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5625}
5626
5627static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5628 SDValue TmpOp0, TmpOp1;
5629 bool Invert = false;
5630 bool Swap = false;
5631 unsigned Opc = 0;
5632
5633 SDValue Op0 = Op.getOperand(0);
5634 SDValue Op1 = Op.getOperand(1);
5635 SDValue CC = Op.getOperand(2);
5636 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5637 EVT VT = Op.getValueType();
5638 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5639 SDLoc dl(Op);
5640
5641 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5642 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5643 // Special-case integer 64-bit equality comparisons. They aren't legal,
5644 // but they can be lowered with a few vector instructions.
5645 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5646 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5647 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5648 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5649 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5650 DAG.getCondCode(ISD::SETEQ));
5651 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5652 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5653 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5654 if (SetCCOpcode == ISD::SETNE)
5655 Merged = DAG.getNOT(dl, Merged, CmpVT);
5656 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5657 return Merged;
5658 }
5659
5660 if (CmpVT.getVectorElementType() == MVT::i64)
5661 // 64-bit comparisons are not legal in general.
5662 return SDValue();
5663
5664 if (Op1.getValueType().isFloatingPoint()) {
5665 switch (SetCCOpcode) {
5666 default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5666)
;
5667 case ISD::SETUNE:
5668 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5669 case ISD::SETOEQ:
5670 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5671 case ISD::SETOLT:
5672 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5673 case ISD::SETOGT:
5674 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5675 case ISD::SETOLE:
5676 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5677 case ISD::SETOGE:
5678 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5679 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5680 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5681 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5682 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5683 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5684 case ISD::SETONE:
5685 // Expand this to (OLT | OGT).
5686 TmpOp0 = Op0;
5687 TmpOp1 = Op1;
5688 Opc = ISD::OR;
5689 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5690 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5691 break;
5692 case ISD::SETUO:
5693 Invert = true;
5694 LLVM_FALLTHROUGH[[clang::fallthrough]];
5695 case ISD::SETO:
5696 // Expand this to (OLT | OGE).
5697 TmpOp0 = Op0;
5698 TmpOp1 = Op1;
5699 Opc = ISD::OR;
5700 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5701 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5702 break;
5703 }
5704 } else {
5705 // Integer comparisons.
5706 switch (SetCCOpcode) {
5707 default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5707)
;
5708 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5709 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5710 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5711 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5712 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5713 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5714 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5715 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5716 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5717 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5718 }
5719
5720 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5721 if (Opc == ARMISD::VCEQ) {
5722 SDValue AndOp;
5723 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5724 AndOp = Op0;
5725 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5726 AndOp = Op1;
5727
5728 // Ignore bitconvert.
5729 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5730 AndOp = AndOp.getOperand(0);
5731
5732 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5733 Opc = ARMISD::VTST;
5734 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5735 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5736 Invert = !Invert;
5737 }
5738 }
5739 }
5740
5741 if (Swap)
5742 std::swap(Op0, Op1);
5743
5744 // If one of the operands is a constant vector zero, attempt to fold the
5745 // comparison to a specialized compare-against-zero form.
5746 SDValue SingleOp;
5747 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5748 SingleOp = Op0;
5749 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5750 if (Opc == ARMISD::VCGE)
5751 Opc = ARMISD::VCLEZ;
5752 else if (Opc == ARMISD::VCGT)
5753 Opc = ARMISD::VCLTZ;
5754 SingleOp = Op1;
5755 }
5756
5757 SDValue Result;
5758 if (SingleOp.getNode()) {
5759 switch (Opc) {
5760 case ARMISD::VCEQ:
5761 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5762 case ARMISD::VCGE:
5763 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5764 case ARMISD::VCLEZ:
5765 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5766 case ARMISD::VCGT:
5767 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5768 case ARMISD::VCLTZ:
5769 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5770 default:
5771 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5772 }
5773 } else {
5774 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5775 }
5776
5777 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5778
5779 if (Invert)
5780 Result = DAG.getNOT(dl, Result, VT);
5781
5782 return Result;
5783}
5784
5785static SDValue LowerSETCCCARRY(SDValue Op, SelectionDAG &DAG) {
5786 SDValue LHS = Op.getOperand(0);
5787 SDValue RHS = Op.getOperand(1);
5788 SDValue Carry = Op.getOperand(2);
5789 SDValue Cond = Op.getOperand(3);
5790 SDLoc DL(Op);
5791
5792 assert(LHS.getSimpleValueType().isInteger() && "SETCCCARRY is integer only.")(static_cast <bool> (LHS.getSimpleValueType().isInteger
() && "SETCCCARRY is integer only.") ? void (0) : __assert_fail
("LHS.getSimpleValueType().isInteger() && \"SETCCCARRY is integer only.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5792, __extension__ __PRETTY_FUNCTION__))
;
5793
5794 // ARMISD::SUBE expects a carry not a borrow like ISD::SUBCARRY so we
5795 // have to invert the carry first.
5796 Carry = DAG.getNode(ISD::SUB, DL, MVT::i32,
5797 DAG.getConstant(1, DL, MVT::i32), Carry);
5798 // This converts the boolean value carry into the carry flag.
5799 Carry = ConvertBooleanCarryToCarryFlag(Carry, DAG);
5800
5801 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5802 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5803
5804 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5805 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5806 SDValue ARMcc = DAG.getConstant(
5807 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5808 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5809 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5810 Cmp.getValue(1), SDValue());
5811 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5812 CCR, Chain.getValue(1));
5813}
5814
5815/// isNEONModifiedImm - Check if the specified splat value corresponds to a
5816/// valid vector constant for a NEON instruction with a "modified immediate"
5817/// operand (e.g., VMOV). If so, return the encoded value.
5818static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5819 unsigned SplatBitSize, SelectionDAG &DAG,
5820 const SDLoc &dl, EVT &VT, bool is128Bits,
5821 NEONModImmType type) {
5822 unsigned OpCmode, Imm;
5823
5824 // SplatBitSize is set to the smallest size that splats the vector, so a
5825 // zero vector will always have SplatBitSize == 8. However, NEON modified
5826 // immediate instructions others than VMOV do not support the 8-bit encoding
5827 // of a zero vector, and the default encoding of zero is supposed to be the
5828 // 32-bit version.
5829 if (SplatBits == 0)
5830 SplatBitSize = 32;
5831
5832 switch (SplatBitSize) {
5833 case 8:
5834 if (type != VMOVModImm)
5835 return SDValue();
5836 // Any 1-byte value is OK. Op=0, Cmode=1110.
5837 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(static_cast <bool> ((SplatBits & ~0xff) == 0 &&
"one byte splat value is too big") ? void (0) : __assert_fail
("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5837, __extension__ __PRETTY_FUNCTION__))
;
5838 OpCmode = 0xe;
5839 Imm = SplatBits;
5840 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5841 break;
5842
5843 case 16:
5844 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5845 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5846 if ((SplatBits & ~0xff) == 0) {
5847 // Value = 0x00nn: Op=x, Cmode=100x.
5848 OpCmode = 0x8;
5849 Imm = SplatBits;
5850 break;
5851 }
5852 if ((SplatBits & ~0xff00) == 0) {
5853 // Value = 0xnn00: Op=x, Cmode=101x.
5854 OpCmode = 0xa;
5855 Imm = SplatBits >> 8;
5856 break;
5857 }
5858 return SDValue();
5859
5860 case 32:
5861 // NEON's 32-bit VMOV supports splat values where:
5862 // * only one byte is nonzero, or
5863 // * the least significant byte is 0xff and the second byte is nonzero, or
5864 // * the least significant 2 bytes are 0xff and the third is nonzero.
5865 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5866 if ((SplatBits & ~0xff) == 0) {
5867 // Value = 0x000000nn: Op=x, Cmode=000x.
5868 OpCmode = 0;
5869 Imm = SplatBits;
5870 break;
5871 }
5872 if ((SplatBits & ~0xff00) == 0) {
5873 // Value = 0x0000nn00: Op=x, Cmode=001x.
5874 OpCmode = 0x2;
5875 Imm = SplatBits >> 8;
5876 break;
5877 }
5878 if ((SplatBits & ~0xff0000) == 0) {
5879 // Value = 0x00nn0000: Op=x, Cmode=010x.
5880 OpCmode = 0x4;
5881 Imm = SplatBits >> 16;
5882 break;
5883 }
5884 if ((SplatBits & ~0xff000000) == 0) {
5885 // Value = 0xnn000000: Op=x, Cmode=011x.
5886 OpCmode = 0x6;
5887 Imm = SplatBits >> 24;
5888 break;
5889 }
5890
5891 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5892 if (type == OtherModImm) return SDValue();
5893
5894 if ((SplatBits & ~0xffff) == 0 &&
5895 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5896 // Value = 0x0000nnff: Op=x, Cmode=1100.
5897 OpCmode = 0xc;
5898 Imm = SplatBits >> 8;
5899 break;
5900 }
5901
5902 if ((SplatBits & ~0xffffff) == 0 &&
5903 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5904 // Value = 0x00nnffff: Op=x, Cmode=1101.
5905 OpCmode = 0xd;
5906 Imm = SplatBits >> 16;
5907 break;
5908 }
5909
5910 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5911 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5912 // VMOV.I32. A (very) minor optimization would be to replicate the value
5913 // and fall through here to test for a valid 64-bit splat. But, then the
5914 // caller would also need to check and handle the change in size.
5915 return SDValue();
5916
5917 case 64: {
5918 if (type != VMOVModImm)
5919 return SDValue();
5920 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5921 uint64_t BitMask = 0xff;
5922 uint64_t Val = 0;
5923 unsigned ImmMask = 1;
5924 Imm = 0;
5925 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5926 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5927 Val |= BitMask;
5928 Imm |= ImmMask;
5929 } else if ((SplatBits & BitMask) != 0) {
5930 return SDValue();
5931 }
5932 BitMask <<= 8;
5933 ImmMask <<= 1;
5934 }
5935
5936 if (DAG.getDataLayout().isBigEndian())
5937 // swap higher and lower 32 bit word
5938 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5939
5940 // Op=1, Cmode=1110.
5941 OpCmode = 0x1e;
5942 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5943 break;
5944 }
5945
5946 default:
5947 llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/ARM/ARMISelLowering.cpp"
, 5947)
;
5948 }
5949
5950 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5951 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5952}
5953
5954SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5955 const ARMSubtarget *ST) const {
5956 EVT VT = Op.getValueType();
5957 bool IsDouble = (VT == MVT::f64);
5958 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5959 const APFloat &FPVal = CFP->getValueAPF();
5960
5961 // Prevent floating-point constants from using literal loads
5962 // when execute-only is enabled.
5963 if (ST->genExecuteOnly()) {
5964 // If we can represent the constant as an immediate, don't lower it
5965 if (isFPImmLegal(FPVal, VT))