Bug Summary

File:llvm/include/llvm/CodeGen/SelectionDAGNodes.h
Warning:line 1171, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -fno-rounding-math -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/include -I /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/build-llvm/lib/Target/ARM -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-12-11-181444-25759-1 -x c++ /build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that ARM uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMISelLowering.h"
15#include "ARMBaseInstrInfo.h"
16#include "ARMBaseRegisterInfo.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSelectionDAGInfo.h"
23#include "ARMSubtarget.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMBaseInfo.h"
26#include "Utils/ARMBaseInfo.h"
27#include "llvm/ADT/APFloat.h"
28#include "llvm/ADT/APInt.h"
29#include "llvm/ADT/ArrayRef.h"
30#include "llvm/ADT/BitVector.h"
31#include "llvm/ADT/DenseMap.h"
32#include "llvm/ADT/STLExtras.h"
33#include "llvm/ADT/SmallPtrSet.h"
34#include "llvm/ADT/SmallVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/StringExtras.h"
37#include "llvm/ADT/StringRef.h"
38#include "llvm/ADT/StringSwitch.h"
39#include "llvm/ADT/Triple.h"
40#include "llvm/ADT/Twine.h"
41#include "llvm/Analysis/VectorUtils.h"
42#include "llvm/CodeGen/CallingConvLower.h"
43#include "llvm/CodeGen/ISDOpcodes.h"
44#include "llvm/CodeGen/IntrinsicLowering.h"
45#include "llvm/CodeGen/MachineBasicBlock.h"
46#include "llvm/CodeGen/MachineConstantPool.h"
47#include "llvm/CodeGen/MachineFrameInfo.h"
48#include "llvm/CodeGen/MachineFunction.h"
49#include "llvm/CodeGen/MachineInstr.h"
50#include "llvm/CodeGen/MachineInstrBuilder.h"
51#include "llvm/CodeGen/MachineJumpTableInfo.h"
52#include "llvm/CodeGen/MachineMemOperand.h"
53#include "llvm/CodeGen/MachineOperand.h"
54#include "llvm/CodeGen/MachineRegisterInfo.h"
55#include "llvm/CodeGen/RuntimeLibcalls.h"
56#include "llvm/CodeGen/SelectionDAG.h"
57#include "llvm/CodeGen/SelectionDAGNodes.h"
58#include "llvm/CodeGen/TargetInstrInfo.h"
59#include "llvm/CodeGen/TargetLowering.h"
60#include "llvm/CodeGen/TargetOpcodes.h"
61#include "llvm/CodeGen/TargetRegisterInfo.h"
62#include "llvm/CodeGen/TargetSubtargetInfo.h"
63#include "llvm/CodeGen/ValueTypes.h"
64#include "llvm/IR/Attributes.h"
65#include "llvm/IR/CallingConv.h"
66#include "llvm/IR/Constant.h"
67#include "llvm/IR/Constants.h"
68#include "llvm/IR/DataLayout.h"
69#include "llvm/IR/DebugLoc.h"
70#include "llvm/IR/DerivedTypes.h"
71#include "llvm/IR/Function.h"
72#include "llvm/IR/GlobalAlias.h"
73#include "llvm/IR/GlobalValue.h"
74#include "llvm/IR/GlobalVariable.h"
75#include "llvm/IR/IRBuilder.h"
76#include "llvm/IR/InlineAsm.h"
77#include "llvm/IR/Instruction.h"
78#include "llvm/IR/Instructions.h"
79#include "llvm/IR/IntrinsicInst.h"
80#include "llvm/IR/Intrinsics.h"
81#include "llvm/IR/Module.h"
82#include "llvm/IR/PatternMatch.h"
83#include "llvm/IR/Type.h"
84#include "llvm/IR/User.h"
85#include "llvm/IR/Value.h"
86#include "llvm/MC/MCInstrDesc.h"
87#include "llvm/MC/MCInstrItineraries.h"
88#include "llvm/MC/MCRegisterInfo.h"
89#include "llvm/MC/MCSchedule.h"
90#include "llvm/Support/AtomicOrdering.h"
91#include "llvm/Support/BranchProbability.h"
92#include "llvm/Support/Casting.h"
93#include "llvm/Support/CodeGen.h"
94#include "llvm/Support/CommandLine.h"
95#include "llvm/Support/Compiler.h"
96#include "llvm/Support/Debug.h"
97#include "llvm/Support/ErrorHandling.h"
98#include "llvm/Support/KnownBits.h"
99#include "llvm/Support/MachineValueType.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116using namespace llvm::PatternMatch;
117
118#define DEBUG_TYPE"arm-isel" "arm-isel"
119
120STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls"}
;
121STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt"}
;
122STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments"}
;
123STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
124 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
}
;
125
126static cl::opt<bool>
127ARMInterworking("arm-interworking", cl::Hidden,
128 cl::desc("Enable / disable ARM interworking (for debugging only)"),
129 cl::init(true));
130
131static cl::opt<bool> EnableConstpoolPromotion(
132 "arm-promote-constant", cl::Hidden,
133 cl::desc("Enable / disable promotion of unnamed_addr constants into "
134 "constant pools"),
135 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
136static cl::opt<unsigned> ConstpoolPromotionMaxSize(
137 "arm-promote-constant-max-size", cl::Hidden,
138 cl::desc("Maximum size of constant to promote into a constant pool"),
139 cl::init(64));
140static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
141 "arm-promote-constant-max-total", cl::Hidden,
142 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
143 cl::init(128));
144
145// The APCS parameter registers.
146static const MCPhysReg GPRArgRegs[] = {
147 ARM::R0, ARM::R1, ARM::R2, ARM::R3
148};
149
150void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
151 MVT PromotedBitwiseVT) {
152 if (VT != PromotedLdStVT) {
153 setOperationAction(ISD::LOAD, VT, Promote);
154 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
155
156 setOperationAction(ISD::STORE, VT, Promote);
157 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
158 }
159
160 MVT ElemTy = VT.getVectorElementType();
161 if (ElemTy != MVT::f64)
162 setOperationAction(ISD::SETCC, VT, Custom);
163 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
164 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
165 if (ElemTy == MVT::i32) {
166 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
168 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
169 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
170 } else {
171 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
173 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
174 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
175 }
176 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
177 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
178 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
179 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
180 setOperationAction(ISD::SELECT, VT, Expand);
181 setOperationAction(ISD::SELECT_CC, VT, Expand);
182 setOperationAction(ISD::VSELECT, VT, Expand);
183 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
184 if (VT.isInteger()) {
185 setOperationAction(ISD::SHL, VT, Custom);
186 setOperationAction(ISD::SRA, VT, Custom);
187 setOperationAction(ISD::SRL, VT, Custom);
188 }
189
190 // Promote all bit-wise operations.
191 if (VT.isInteger() && VT != PromotedBitwiseVT) {
192 setOperationAction(ISD::AND, VT, Promote);
193 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
194 setOperationAction(ISD::OR, VT, Promote);
195 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
196 setOperationAction(ISD::XOR, VT, Promote);
197 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
198 }
199
200 // Neon does not support vector divide/remainder operations.
201 setOperationAction(ISD::SDIV, VT, Expand);
202 setOperationAction(ISD::UDIV, VT, Expand);
203 setOperationAction(ISD::FDIV, VT, Expand);
204 setOperationAction(ISD::SREM, VT, Expand);
205 setOperationAction(ISD::UREM, VT, Expand);
206 setOperationAction(ISD::FREM, VT, Expand);
207
208 if (!VT.isFloatingPoint() &&
209 VT != MVT::v2i64 && VT != MVT::v1i64)
210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
211 setOperationAction(Opcode, VT, Legal);
212}
213
214void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
215 addRegisterClass(VT, &ARM::DPRRegClass);
216 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
217}
218
219void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
220 addRegisterClass(VT, &ARM::DPairRegClass);
221 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
222}
223
224void ARMTargetLowering::setAllExpand(MVT VT) {
225 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
226 setOperationAction(Opc, VT, Expand);
227
228 // We support these really simple operations even on types where all
229 // the actual arithmetic has to be broken down into simpler
230 // operations or turned into library calls.
231 setOperationAction(ISD::BITCAST, VT, Legal);
232 setOperationAction(ISD::LOAD, VT, Legal);
233 setOperationAction(ISD::STORE, VT, Legal);
234 setOperationAction(ISD::UNDEF, VT, Legal);
235}
236
237void ARMTargetLowering::addAllExtLoads(const MVT From, const MVT To,
238 LegalizeAction Action) {
239 setLoadExtAction(ISD::EXTLOAD, From, To, Action);
240 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
241 setLoadExtAction(ISD::SEXTLOAD, From, To, Action);
242}
243
244void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
245 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
246
247 for (auto VT : IntTypes) {
248 addRegisterClass(VT, &ARM::MQPRRegClass);
249 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
250 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
251 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
252 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
253 setOperationAction(ISD::SHL, VT, Custom);
254 setOperationAction(ISD::SRA, VT, Custom);
255 setOperationAction(ISD::SRL, VT, Custom);
256 setOperationAction(ISD::SMIN, VT, Legal);
257 setOperationAction(ISD::SMAX, VT, Legal);
258 setOperationAction(ISD::UMIN, VT, Legal);
259 setOperationAction(ISD::UMAX, VT, Legal);
260 setOperationAction(ISD::ABS, VT, Legal);
261 setOperationAction(ISD::SETCC, VT, Custom);
262 setOperationAction(ISD::MLOAD, VT, Custom);
263 setOperationAction(ISD::MSTORE, VT, Legal);
264 setOperationAction(ISD::CTLZ, VT, Legal);
265 setOperationAction(ISD::CTTZ, VT, Custom);
266 setOperationAction(ISD::BITREVERSE, VT, Legal);
267 setOperationAction(ISD::BSWAP, VT, Legal);
268 setOperationAction(ISD::SADDSAT, VT, Legal);
269 setOperationAction(ISD::UADDSAT, VT, Legal);
270 setOperationAction(ISD::SSUBSAT, VT, Legal);
271 setOperationAction(ISD::USUBSAT, VT, Legal);
272
273 // No native support for these.
274 setOperationAction(ISD::UDIV, VT, Expand);
275 setOperationAction(ISD::SDIV, VT, Expand);
276 setOperationAction(ISD::UREM, VT, Expand);
277 setOperationAction(ISD::SREM, VT, Expand);
278 setOperationAction(ISD::CTPOP, VT, Expand);
279
280 // Vector reductions
281 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
282 setOperationAction(ISD::VECREDUCE_SMAX, VT, Legal);
283 setOperationAction(ISD::VECREDUCE_UMAX, VT, Legal);
284 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal);
285 setOperationAction(ISD::VECREDUCE_UMIN, VT, Legal);
286
287 if (!HasMVEFP) {
288 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
289 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
290 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
291 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
292 }
293
294 // Pre and Post inc are supported on loads and stores
295 for (unsigned im = (unsigned)ISD::PRE_INC;
296 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
297 setIndexedLoadAction(im, VT, Legal);
298 setIndexedStoreAction(im, VT, Legal);
299 }
300 }
301
302 const MVT FloatTypes[] = { MVT::v8f16, MVT::v4f32 };
303 for (auto VT : FloatTypes) {
304 addRegisterClass(VT, &ARM::MQPRRegClass);
305 if (!HasMVEFP)
306 setAllExpand(VT);
307
308 // These are legal or custom whether we have MVE.fp or not
309 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
310 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
311 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getVectorElementType(), Custom);
312 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
313 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
314 setOperationAction(ISD::BUILD_VECTOR, VT.getVectorElementType(), Custom);
315 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
316 setOperationAction(ISD::SETCC, VT, Custom);
317 setOperationAction(ISD::MLOAD, VT, Custom);
318 setOperationAction(ISD::MSTORE, VT, Legal);
319
320 // Pre and Post inc are supported on loads and stores
321 for (unsigned im = (unsigned)ISD::PRE_INC;
322 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
323 setIndexedLoadAction(im, VT, Legal);
324 setIndexedStoreAction(im, VT, Legal);
325 }
326
327 if (HasMVEFP) {
328 setOperationAction(ISD::FMINNUM, VT, Legal);
329 setOperationAction(ISD::FMAXNUM, VT, Legal);
330 setOperationAction(ISD::FROUND, VT, Legal);
331
332 // No native support for these.
333 setOperationAction(ISD::FDIV, VT, Expand);
334 setOperationAction(ISD::FREM, VT, Expand);
335 setOperationAction(ISD::FSQRT, VT, Expand);
336 setOperationAction(ISD::FSIN, VT, Expand);
337 setOperationAction(ISD::FCOS, VT, Expand);
338 setOperationAction(ISD::FPOW, VT, Expand);
339 setOperationAction(ISD::FLOG, VT, Expand);
340 setOperationAction(ISD::FLOG2, VT, Expand);
341 setOperationAction(ISD::FLOG10, VT, Expand);
342 setOperationAction(ISD::FEXP, VT, Expand);
343 setOperationAction(ISD::FEXP2, VT, Expand);
344 setOperationAction(ISD::FNEARBYINT, VT, Expand);
345 }
346 }
347
348 // We 'support' these types up to bitcast/load/store level, regardless of
349 // MVE integer-only / float support. Only doing FP data processing on the FP
350 // vector types is inhibited at integer-only level.
351 const MVT LongTypes[] = { MVT::v2i64, MVT::v2f64 };
352 for (auto VT : LongTypes) {
353 addRegisterClass(VT, &ARM::MQPRRegClass);
354 setAllExpand(VT);
355 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
356 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
357 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
358 }
359 // We can do bitwise operations on v2i64 vectors
360 setOperationAction(ISD::AND, MVT::v2i64, Legal);
361 setOperationAction(ISD::OR, MVT::v2i64, Legal);
362 setOperationAction(ISD::XOR, MVT::v2i64, Legal);
363
364 // It is legal to extload from v4i8 to v4i16 or v4i32.
365 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
366 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal);
367 addAllExtLoads(MVT::v4i32, MVT::v4i8, Legal);
368
369 // Some truncating stores are legal too.
370 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
371 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
372 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
373
374 // Pre and Post inc on these are legal, given the correct extends
375 for (unsigned im = (unsigned)ISD::PRE_INC;
376 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
377 setIndexedLoadAction(im, MVT::v8i8, Legal);
378 setIndexedStoreAction(im, MVT::v8i8, Legal);
379 setIndexedLoadAction(im, MVT::v4i8, Legal);
380 setIndexedStoreAction(im, MVT::v4i8, Legal);
381 setIndexedLoadAction(im, MVT::v4i16, Legal);
382 setIndexedStoreAction(im, MVT::v4i16, Legal);
383 }
384
385 // Predicate types
386 const MVT pTypes[] = {MVT::v16i1, MVT::v8i1, MVT::v4i1};
387 for (auto VT : pTypes) {
388 addRegisterClass(VT, &ARM::VCCRRegClass);
389 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
390 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
391 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
392 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
393 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
394 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
395 setOperationAction(ISD::SETCC, VT, Custom);
396 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
397 setOperationAction(ISD::LOAD, VT, Custom);
398 setOperationAction(ISD::STORE, VT, Custom);
399 }
400}
401
402ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
403 const ARMSubtarget &STI)
404 : TargetLowering(TM), Subtarget(&STI) {
405 RegInfo = Subtarget->getRegisterInfo();
406 Itins = Subtarget->getInstrItineraryData();
407
408 setBooleanContents(ZeroOrOneBooleanContent);
409 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
410
411 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
412 !Subtarget->isTargetWatchOS()) {
413 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
414 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
415 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
416 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
417 : CallingConv::ARM_AAPCS);
418 }
419
420 if (Subtarget->isTargetMachO()) {
421 // Uses VFP for Thumb libfuncs if available.
422 if (Subtarget->isThumb() && Subtarget->hasVFP2Base() &&
423 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
424 static const struct {
425 const RTLIB::Libcall Op;
426 const char * const Name;
427 const ISD::CondCode Cond;
428 } LibraryCalls[] = {
429 // Single-precision floating-point arithmetic.
430 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
431 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
432 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
433 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
434
435 // Double-precision floating-point arithmetic.
436 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
437 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
438 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
439 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
440
441 // Single-precision comparisons.
442 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
443 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
444 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
445 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
446 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
447 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
448 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
449 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
450
451 // Double-precision comparisons.
452 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
453 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
454 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
455 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
456 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
457 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
458 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
459 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
460
461 // Floating-point to integer conversions.
462 // i64 conversions are done via library routines even when generating VFP
463 // instructions, so use the same ones.
464 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
465 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
466 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
467 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
468
469 // Conversions between floating types.
470 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
471 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
472
473 // Integer to floating-point conversions.
474 // i64 conversions are done via library routines even when generating VFP
475 // instructions, so use the same ones.
476 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
477 // e.g., __floatunsidf vs. __floatunssidfvfp.
478 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
479 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
480 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
481 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
482 };
483
484 for (const auto &LC : LibraryCalls) {
485 setLibcallName(LC.Op, LC.Name);
486 if (LC.Cond != ISD::SETCC_INVALID)
487 setCmpLibcallCC(LC.Op, LC.Cond);
488 }
489 }
490 }
491
492 // These libcalls are not available in 32-bit.
493 setLibcallName(RTLIB::SHL_I128, nullptr);
494 setLibcallName(RTLIB::SRL_I128, nullptr);
495 setLibcallName(RTLIB::SRA_I128, nullptr);
496
497 // RTLIB
498 if (Subtarget->isAAPCS_ABI() &&
499 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
500 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
501 static const struct {
502 const RTLIB::Libcall Op;
503 const char * const Name;
504 const CallingConv::ID CC;
505 const ISD::CondCode Cond;
506 } LibraryCalls[] = {
507 // Double-precision floating-point arithmetic helper functions
508 // RTABI chapter 4.1.2, Table 2
509 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
510 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
511 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
512 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
513
514 // Double-precision floating-point comparison helper functions
515 // RTABI chapter 4.1.2, Table 3
516 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
517 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
518 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
519 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
520 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
521 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
522 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
523 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
524
525 // Single-precision floating-point arithmetic helper functions
526 // RTABI chapter 4.1.2, Table 4
527 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
528 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
529 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
530 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
531
532 // Single-precision floating-point comparison helper functions
533 // RTABI chapter 4.1.2, Table 5
534 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
535 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
536 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
537 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
538 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
539 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
540 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
541 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
542
543 // Floating-point to integer conversions.
544 // RTABI chapter 4.1.2, Table 6
545 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
546 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
547 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
548 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
549 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
550 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
551 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
552 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
553
554 // Conversions between floating types.
555 // RTABI chapter 4.1.2, Table 7
556 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
557 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
558 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
559
560 // Integer to floating-point conversions.
561 // RTABI chapter 4.1.2, Table 8
562 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
563 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
564 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
565 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
566 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
567 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
568 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
569 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
570
571 // Long long helper functions
572 // RTABI chapter 4.2, Table 9
573 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
574 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
575 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
576 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
577
578 // Integer division functions
579 // RTABI chapter 4.3.1
580 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
581 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
582 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
583 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
584 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
585 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
586 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
587 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
588 };
589
590 for (const auto &LC : LibraryCalls) {
591 setLibcallName(LC.Op, LC.Name);
592 setLibcallCallingConv(LC.Op, LC.CC);
593 if (LC.Cond != ISD::SETCC_INVALID)
594 setCmpLibcallCC(LC.Op, LC.Cond);
595 }
596
597 // EABI dependent RTLIB
598 if (TM.Options.EABIVersion == EABI::EABI4 ||
599 TM.Options.EABIVersion == EABI::EABI5) {
600 static const struct {
601 const RTLIB::Libcall Op;
602 const char *const Name;
603 const CallingConv::ID CC;
604 const ISD::CondCode Cond;
605 } MemOpsLibraryCalls[] = {
606 // Memory operations
607 // RTABI chapter 4.3.4
608 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
609 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
610 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
611 };
612
613 for (const auto &LC : MemOpsLibraryCalls) {
614 setLibcallName(LC.Op, LC.Name);
615 setLibcallCallingConv(LC.Op, LC.CC);
616 if (LC.Cond != ISD::SETCC_INVALID)
617 setCmpLibcallCC(LC.Op, LC.Cond);
618 }
619 }
620 }
621
622 if (Subtarget->isTargetWindows()) {
623 static const struct {
624 const RTLIB::Libcall Op;
625 const char * const Name;
626 const CallingConv::ID CC;
627 } LibraryCalls[] = {
628 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
629 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
630 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
631 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
632 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
633 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
634 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
635 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
636 };
637
638 for (const auto &LC : LibraryCalls) {
639 setLibcallName(LC.Op, LC.Name);
640 setLibcallCallingConv(LC.Op, LC.CC);
641 }
642 }
643
644 // Use divmod compiler-rt calls for iOS 5.0 and later.
645 if (Subtarget->isTargetMachO() &&
646 !(Subtarget->isTargetIOS() &&
647 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
648 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
649 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
650 }
651
652 // The half <-> float conversion functions are always soft-float on
653 // non-watchos platforms, but are needed for some targets which use a
654 // hard-float calling convention by default.
655 if (!Subtarget->isTargetWatchABI()) {
656 if (Subtarget->isAAPCS_ABI()) {
657 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
658 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
659 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
660 } else {
661 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
662 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
663 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
664 }
665 }
666
667 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
668 // a __gnu_ prefix (which is the default).
669 if (Subtarget->isTargetAEABI()) {
670 static const struct {
671 const RTLIB::Libcall Op;
672 const char * const Name;
673 const CallingConv::ID CC;
674 } LibraryCalls[] = {
675 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
676 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
677 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
678 };
679
680 for (const auto &LC : LibraryCalls) {
681 setLibcallName(LC.Op, LC.Name);
682 setLibcallCallingConv(LC.Op, LC.CC);
683 }
684 }
685
686 if (Subtarget->isThumb1Only())
687 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
688 else
689 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
690
691 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only() &&
692 Subtarget->hasFPRegs()) {
693 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
694 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
695 if (!Subtarget->hasVFP2Base())
696 setAllExpand(MVT::f32);
697 if (!Subtarget->hasFP64())
698 setAllExpand(MVT::f64);
699 }
700
701 if (Subtarget->hasFullFP16()) {
702 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
703 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
704 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
705 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
706
707 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
708 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
709 }
710
711 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
712 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) {
713 setTruncStoreAction(VT, InnerVT, Expand);
714 addAllExtLoads(VT, InnerVT, Expand);
715 }
716
717 setOperationAction(ISD::MULHS, VT, Expand);
718 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
719 setOperationAction(ISD::MULHU, VT, Expand);
720 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
721
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 }
724
725 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
726 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
727
728 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
729 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
730
731 if (Subtarget->hasMVEIntegerOps())
732 addMVEVectorTypes(Subtarget->hasMVEFloatOps());
733
734 // Combine low-overhead loop intrinsics so that we can lower i1 types.
735 if (Subtarget->hasLOB()) {
736 setTargetDAGCombine(ISD::BRCOND);
737 setTargetDAGCombine(ISD::BR_CC);
738 }
739
740 if (Subtarget->hasNEON()) {
741 addDRTypeForNEON(MVT::v2f32);
742 addDRTypeForNEON(MVT::v8i8);
743 addDRTypeForNEON(MVT::v4i16);
744 addDRTypeForNEON(MVT::v2i32);
745 addDRTypeForNEON(MVT::v1i64);
746
747 addQRTypeForNEON(MVT::v4f32);
748 addQRTypeForNEON(MVT::v2f64);
749 addQRTypeForNEON(MVT::v16i8);
750 addQRTypeForNEON(MVT::v8i16);
751 addQRTypeForNEON(MVT::v4i32);
752 addQRTypeForNEON(MVT::v2i64);
753
754 if (Subtarget->hasFullFP16()) {
755 addQRTypeForNEON(MVT::v8f16);
756 addDRTypeForNEON(MVT::v4f16);
757 }
758 }
759
760 if (Subtarget->hasMVEIntegerOps() || Subtarget->hasNEON()) {
761 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
762 // none of Neon, MVE or VFP supports any arithmetic operations on it.
763 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
764 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
765 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
766 // FIXME: Code duplication: FDIV and FREM are expanded always, see
767 // ARMTargetLowering::addTypeForNEON method for details.
768 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
769 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
770 // FIXME: Create unittest.
771 // In another words, find a way when "copysign" appears in DAG with vector
772 // operands.
773 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
774 // FIXME: Code duplication: SETCC has custom operation action, see
775 // ARMTargetLowering::addTypeForNEON method for details.
776 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
777 // FIXME: Create unittest for FNEG and for FABS.
778 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
779 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
780 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
781 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
782 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
783 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
784 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
785 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
786 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
787 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
788 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
789 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
790 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
791 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
792 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
793 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
794 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
795 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
796 }
797
798 if (Subtarget->hasNEON()) {
799 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
800 // supported for v4f32.
801 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
802 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
803 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
804 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
805 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
806 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
807 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
808 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
809 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
810 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
811 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
812 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
813 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
814 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
815
816 // Mark v2f32 intrinsics.
817 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
818 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
819 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
820 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
821 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
822 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
823 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
824 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
825 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
826 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
827 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
828 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
829 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
830 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
831
832 // Neon does not support some operations on v1i64 and v2i64 types.
833 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
834 // Custom handling for some quad-vector types to detect VMULL.
835 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
836 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
837 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
838 // Custom handling for some vector types to avoid expensive expansions
839 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
840 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
841 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
842 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
843 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
844 // a destination type that is wider than the source, and nor does
845 // it have a FP_TO_[SU]INT instruction with a narrower destination than
846 // source.
847 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
848 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
849 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
850 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
851 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
852 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custom);
853 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
854 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
855
856 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
857 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
858
859 // NEON does not have single instruction CTPOP for vectors with element
860 // types wider than 8-bits. However, custom lowering can leverage the
861 // v8i8/v16i8 vcnt instruction.
862 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
863 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
864 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
865 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
866 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom);
867 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
868
869 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
870 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
871
872 // NEON does not have single instruction CTTZ for vectors.
873 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
874 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
875 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
876 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
877
878 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
879 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
880 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
881 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
882
883 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
884 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
885 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
886 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
887
888 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
889 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
890 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
891 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
892
893 // NEON only has FMA instructions as of VFP4.
894 if (!Subtarget->hasVFP4Base()) {
895 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
896 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
897 }
898
899 setTargetDAGCombine(ISD::INTRINSIC_VOID);
900 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
901 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
902 setTargetDAGCombine(ISD::SHL);
903 setTargetDAGCombine(ISD::SRL);
904 setTargetDAGCombine(ISD::SRA);
905 setTargetDAGCombine(ISD::FP_TO_SINT);
906 setTargetDAGCombine(ISD::FP_TO_UINT);
907 setTargetDAGCombine(ISD::FDIV);
908 setTargetDAGCombine(ISD::LOAD);
909
910 // It is legal to extload from v4i8 to v4i16 or v4i32.
911 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
912 MVT::v2i32}) {
913 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
914 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
915 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
916 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
917 }
918 }
919 }
920
921 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
922 setTargetDAGCombine(ISD::BUILD_VECTOR);
923 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
924 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
925 setTargetDAGCombine(ISD::STORE);
926 setTargetDAGCombine(ISD::SIGN_EXTEND);
927 setTargetDAGCombine(ISD::ZERO_EXTEND);
928 setTargetDAGCombine(ISD::ANY_EXTEND);
929 }
930
931 if (!Subtarget->hasFP64()) {
932 // When targeting a floating-point unit with only single-precision
933 // operations, f64 is legal for the few double-precision instructions which
934 // are present However, no double-precision operations other than moves,
935 // loads and stores are provided by the hardware.
936 setOperationAction(ISD::FADD, MVT::f64, Expand);
937 setOperationAction(ISD::FSUB, MVT::f64, Expand);
938 setOperationAction(ISD::FMUL, MVT::f64, Expand);
939 setOperationAction(ISD::FMA, MVT::f64, Expand);
940 setOperationAction(ISD::FDIV, MVT::f64, Expand);
941 setOperationAction(ISD::FREM, MVT::f64, Expand);
942 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
943 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
944 setOperationAction(ISD::FNEG, MVT::f64, Expand);
945 setOperationAction(ISD::FABS, MVT::f64, Expand);
946 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
947 setOperationAction(ISD::FSIN, MVT::f64, Expand);
948 setOperationAction(ISD::FCOS, MVT::f64, Expand);
949 setOperationAction(ISD::FPOW, MVT::f64, Expand);
950 setOperationAction(ISD::FLOG, MVT::f64, Expand);
951 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
952 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
953 setOperationAction(ISD::FEXP, MVT::f64, Expand);
954 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
955 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
956 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
957 setOperationAction(ISD::FRINT, MVT::f64, Expand);
958 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
959 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
960 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
961 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
962 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
963 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
964 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
965 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
966 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
967 }
968
969 if (!Subtarget->hasFP64() || !Subtarget->hasFPARMv8Base()) {
970 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
971 if (Subtarget->hasFullFP16())
972 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
973 }
974
975 if (!Subtarget->hasFP16())
976 setOperationAction(ISD::FP_EXTEND, MVT::f32, Custom);
977
978 if (!Subtarget->hasFP64())
979 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
980
981 computeRegisterProperties(Subtarget->getRegisterInfo());
982
983 // ARM does not have floating-point extending loads.
984 for (MVT VT : MVT::fp_valuetypes()) {
985 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
986 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
987 }
988
989 // ... or truncating stores
990 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
991 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
992 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
993
994 // ARM does not have i1 sign extending load.
995 for (MVT VT : MVT::integer_valuetypes())
996 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
997
998 // ARM supports all 4 flavors of integer indexed load / store.
999 if (!Subtarget->isThumb1Only()) {
1000 for (unsigned im = (unsigned)ISD::PRE_INC;
1001 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
1002 setIndexedLoadAction(im, MVT::i1, Legal);
1003 setIndexedLoadAction(im, MVT::i8, Legal);
1004 setIndexedLoadAction(im, MVT::i16, Legal);
1005 setIndexedLoadAction(im, MVT::i32, Legal);
1006 setIndexedStoreAction(im, MVT::i1, Legal);
1007 setIndexedStoreAction(im, MVT::i8, Legal);
1008 setIndexedStoreAction(im, MVT::i16, Legal);
1009 setIndexedStoreAction(im, MVT::i32, Legal);
1010 }
1011 } else {
1012 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
1013 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
1014 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
1015 }
1016
1017 setOperationAction(ISD::SADDO, MVT::i32, Custom);
1018 setOperationAction(ISD::UADDO, MVT::i32, Custom);
1019 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
1020 setOperationAction(ISD::USUBO, MVT::i32, Custom);
1021
1022 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
1023 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
1024 if (Subtarget->hasDSP()) {
1025 setOperationAction(ISD::SADDSAT, MVT::i8, Custom);
1026 setOperationAction(ISD::SSUBSAT, MVT::i8, Custom);
1027 setOperationAction(ISD::SADDSAT, MVT::i16, Custom);
1028 setOperationAction(ISD::SSUBSAT, MVT::i16, Custom);
1029 }
1030 if (Subtarget->hasBaseDSP()) {
1031 setOperationAction(ISD::SADDSAT, MVT::i32, Legal);
1032 setOperationAction(ISD::SSUBSAT, MVT::i32, Legal);
1033 }
1034
1035 // i64 operation support.
1036 setOperationAction(ISD::MUL, MVT::i64, Expand);
1037 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1038 if (Subtarget->isThumb1Only()) {
1039 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1040 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1041 }
1042 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
1043 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
1044 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1045
1046 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
1047 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
1048 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
1049 setOperationAction(ISD::SRL, MVT::i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::i64, Custom);
1051 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1052 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1053
1054 // MVE lowers 64 bit shifts to lsll and lsrl
1055 // assuming that ISD::SRL and SRA of i64 are already marked custom
1056 if (Subtarget->hasMVEIntegerOps())
1057 setOperationAction(ISD::SHL, MVT::i64, Custom);
1058
1059 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
1060 if (Subtarget->isThumb1Only()) {
1061 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1062 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1063 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1064 }
1065
1066 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
1067 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1068
1069 // ARM does not have ROTL.
1070 setOperationAction(ISD::ROTL, MVT::i32, Expand);
1071 for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
1072 setOperationAction(ISD::ROTL, VT, Expand);
1073 setOperationAction(ISD::ROTR, VT, Expand);
1074 }
1075 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
1076 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1077 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
1078 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
1079 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
1080 }
1081
1082 // @llvm.readcyclecounter requires the Performance Monitors extension.
1083 // Default to the 0 expansion on unsupported platforms.
1084 // FIXME: Technically there are older ARM CPUs that have
1085 // implementation-specific ways of obtaining this information.
1086 if (Subtarget->hasPerfMon())
1087 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1088
1089 // Only ARMv6 has BSWAP.
1090 if (!Subtarget->hasV6Ops())
1091 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1092
1093 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
1094 : Subtarget->hasDivideInARMMode();
1095 if (!hasDivide) {
1096 // These are expanded into libcalls if the cpu doesn't have HW divider.
1097 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
1098 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
1099 }
1100
1101 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
1102 setOperationAction(ISD::SDIV, MVT::i32, Custom);
1103 setOperationAction(ISD::UDIV, MVT::i32, Custom);
1104
1105 setOperationAction(ISD::SDIV, MVT::i64, Custom);
1106 setOperationAction(ISD::UDIV, MVT::i64, Custom);
1107 }
1108
1109 setOperationAction(ISD::SREM, MVT::i32, Expand);
1110 setOperationAction(ISD::UREM, MVT::i32, Expand);
1111
1112 // Register based DivRem for AEABI (RTABI 4.2)
1113 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
1114 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
1115 Subtarget->isTargetWindows()) {
1116 setOperationAction(ISD::SREM, MVT::i64, Custom);
1117 setOperationAction(ISD::UREM, MVT::i64, Custom);
1118 HasStandaloneRem = false;
1119
1120 if (Subtarget->isTargetWindows()) {
1121 const struct {
1122 const RTLIB::Libcall Op;
1123 const char * const Name;
1124 const CallingConv::ID CC;
1125 } LibraryCalls[] = {
1126 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
1127 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
1128 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
1129 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
1130
1131 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
1132 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
1133 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
1134 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
1135 };
1136
1137 for (const auto &LC : LibraryCalls) {
1138 setLibcallName(LC.Op, LC.Name);
1139 setLibcallCallingConv(LC.Op, LC.CC);
1140 }
1141 } else {
1142 const struct {
1143 const RTLIB::Libcall Op;
1144 const char * const Name;
1145 const CallingConv::ID CC;
1146 } LibraryCalls[] = {
1147 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1148 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1149 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
1150 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
1151
1152 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1153 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1154 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
1155 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
1156 };
1157
1158 for (const auto &LC : LibraryCalls) {
1159 setLibcallName(LC.Op, LC.Name);
1160 setLibcallCallingConv(LC.Op, LC.CC);
1161 }
1162 }
1163
1164 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
1165 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
1166 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
1167 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
1168 } else {
1169 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1170 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1171 }
1172
1173 if (Subtarget->getTargetTriple().isOSMSVCRT()) {
1174 // MSVCRT doesn't have powi; fall back to pow
1175 setLibcallName(RTLIB::POWI_F32, nullptr);
1176 setLibcallName(RTLIB::POWI_F64, nullptr);
1177 }
1178
1179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1180 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1181 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1182 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1183
1184 setOperationAction(ISD::TRAP, MVT::Other, Legal);
1185 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
1186
1187 // Use the default implementation.
1188 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1189 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1190 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
1191 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1192 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1193 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1194
1195 if (Subtarget->isTargetWindows())
1196 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1197 else
1198 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
1199
1200 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
1201 // the default expansion.
1202 InsertFencesForAtomic = false;
1203 if (Subtarget->hasAnyDataBarrier() &&
1204 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
1205 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
1206 // to ldrex/strex loops already.
1207 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1208 if (!Subtarget->isThumb() || !Subtarget->isMClass())
1209 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
1210
1211 // On v8, we have particularly efficient implementations of atomic fences
1212 // if they can be combined with nearby atomic loads and stores.
1213 if (!Subtarget->hasAcquireRelease() ||
1214 getTargetMachine().getOptLevel() == 0) {
1215 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
1216 InsertFencesForAtomic = true;
1217 }
1218 } else {
1219 // If there's anything we can use as a barrier, go through custom lowering
1220 // for ATOMIC_FENCE.
1221 // If target has DMB in thumb, Fences can be inserted.
1222 if (Subtarget->hasDataBarrier())
1223 InsertFencesForAtomic = true;
1224
1225 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
1226 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
1227
1228 // Set them all for expansion, which will force libcalls.
1229 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1230 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1231 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1232 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1233 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1234 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1235 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1236 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1237 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1238 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1239 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1240 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1241 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1242 // Unordered/Monotonic case.
1243 if (!InsertFencesForAtomic) {
1244 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1245 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1246 }
1247 }
1248
1249 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1250
1251 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1252 if (!Subtarget->hasV6Ops()) {
1253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1254 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1255 }
1256 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1257
1258 if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
1259 !Subtarget->isThumb1Only()) {
1260 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1261 // iff target supports vfp2.
1262 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1263 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1264 }
1265
1266 // We want to custom lower some of our intrinsics.
1267 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1268 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1269 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1270 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1271 if (Subtarget->useSjLjEH())
1272 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1273
1274 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1275 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1276 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1277 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1278 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1279 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1280 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1281 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1282 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1283 if (Subtarget->hasFullFP16()) {
1284 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1285 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1286 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1287 }
1288
1289 setOperationAction(ISD::SETCCCARRY, MVT::i32, Custom);
1290
1291 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1292 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1293 if (Subtarget->hasFullFP16())
1294 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1295 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1296 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1297 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1298
1299 // We don't support sin/cos/fmod/copysign/pow
1300 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1301 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1302 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1303 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1304 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1305 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1306 setOperationAction(ISD::FREM, MVT::f64, Expand);
1307 setOperationAction(ISD::FREM, MVT::f32, Expand);
1308 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2Base() &&
1309 !Subtarget->isThumb1Only()) {
1310 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1311 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1312 }
1313 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1314 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1315
1316 if (!Subtarget->hasVFP4Base()) {
1317 setOperationAction(ISD::FMA, MVT::f64, Expand);
1318 setOperationAction(ISD::FMA, MVT::f32, Expand);
1319 }
1320
1321 // Various VFP goodness
1322 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1323 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1324 if (!Subtarget->hasFPARMv8Base() || !Subtarget->hasFP64()) {
1325 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1326 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1327 }
1328
1329 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1330 if (!Subtarget->hasFP16()) {
1331 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1332 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1333 }
1334 }
1335
1336 // Use __sincos_stret if available.
1337 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1338 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1339 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1340 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1341 }
1342
1343 // FP-ARMv8 implements a lot of rounding-like FP operations.
1344 if (Subtarget->hasFPARMv8Base()) {
1345 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1346 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1347 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1348 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1349 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1350 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1351 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1352 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1353 if (Subtarget->hasNEON()) {
1354 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1355 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1356 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1357 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1358 }
1359
1360 if (Subtarget->hasFP64()) {
1361 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1362 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1363 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1364 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1365 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1366 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1367 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1368 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1369 }
1370 }
1371
1372 // FP16 often need to be promoted to call lib functions
1373 if (Subtarget->hasFullFP16()) {
1374 setOperationAction(ISD::FREM, MVT::f16, Promote);
1375 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1376 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1377 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1378 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1379 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1380 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1381 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1382 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1383 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1384 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1385 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1386
1387 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1388 }
1389
1390 if (Subtarget->hasNEON()) {
1391 // vmin and vmax aren't available in a scalar form, so we use
1392 // a NEON instruction with an undef lane instead.
1393 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1394 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
1395 setOperationAction(ISD::FMINIMUM, MVT::f32, Legal);
1396 setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal);
1397 setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal);
1398 setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal);
1399 setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
1400 setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
1401
1402 if (Subtarget->hasFullFP16()) {
1403 setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
1404 setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
1405 setOperationAction(ISD::FMINNUM, MVT::v8f16, Legal);
1406 setOperationAction(ISD::FMAXNUM, MVT::v8f16, Legal);
1407
1408 setOperationAction(ISD::FMINIMUM, MVT::v4f16, Legal);
1409 setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
1410 setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
1411 setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1412 }
1413 }
1414
1415 // We have target-specific dag combine patterns for the following nodes:
1416 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1417 setTargetDAGCombine(ISD::ADD);
1418 setTargetDAGCombine(ISD::SUB);
1419 setTargetDAGCombine(ISD::MUL);
1420 setTargetDAGCombine(ISD::AND);
1421 setTargetDAGCombine(ISD::OR);
1422 setTargetDAGCombine(ISD::XOR);
1423
1424 if (Subtarget->hasV6Ops())
1425 setTargetDAGCombine(ISD::SRL);
1426 if (Subtarget->isThumb1Only())
1427 setTargetDAGCombine(ISD::SHL);
1428
1429 setStackPointerRegisterToSaveRestore(ARM::SP);
1430
1431 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1432 !Subtarget->hasVFP2Base() || Subtarget->hasMinSize())
1433 setSchedulingPreference(Sched::RegPressure);
1434 else
1435 setSchedulingPreference(Sched::Hybrid);
1436
1437 //// temporary - rewrite interface to use type
1438 MaxStoresPerMemset = 8;
1439 MaxStoresPerMemsetOptSize = 4;
1440 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1441 MaxStoresPerMemcpyOptSize = 2;
1442 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1443 MaxStoresPerMemmoveOptSize = 2;
1444
1445 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1446 // are at least 4 bytes aligned.
1447 setMinStackArgumentAlignment(Align(4));
1448
1449 // Prefer likely predicted branches to selects on out-of-order cores.
1450 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1451
1452 setPrefLoopAlignment(Align(1ULL << Subtarget->getPrefLoopLogAlignment()));
1453
1454 setMinFunctionAlignment(Subtarget->isThumb() ? Align(2) : Align(4));
1455
1456 if (Subtarget->isThumb() || Subtarget->isThumb2())
1457 setTargetDAGCombine(ISD::ABS);
1458}
1459
1460bool ARMTargetLowering::useSoftFloat() const {
1461 return Subtarget->useSoftFloat();
1462}
1463
1464// FIXME: It might make sense to define the representative register class as the
1465// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1466// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1467// SPR's representative would be DPR_VFP2. This should work well if register
1468// pressure tracking were modified such that a register use would increment the
1469// pressure of the register class's representative and all of it's super
1470// classes' representatives transitively. We have not implemented this because
1471// of the difficulty prior to coalescing of modeling operand register classes
1472// due to the common occurrence of cross class copies and subregister insertions
1473// and extractions.
1474std::pair<const TargetRegisterClass *, uint8_t>
1475ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1476 MVT VT) const {
1477 const TargetRegisterClass *RRC = nullptr;
1478 uint8_t Cost = 1;
1479 switch (VT.SimpleTy) {
1480 default:
1481 return TargetLowering::findRepresentativeClass(TRI, VT);
1482 // Use DPR as representative register class for all floating point
1483 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1484 // the cost is 1 for both f32 and f64.
1485 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1486 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1487 RRC = &ARM::DPRRegClass;
1488 // When NEON is used for SP, only half of the register file is available
1489 // because operations that define both SP and DP results will be constrained
1490 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1491 // coalescing by double-counting the SP regs. See the FIXME above.
1492 if (Subtarget->useNEONForSinglePrecisionFP())
1493 Cost = 2;
1494 break;
1495 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1496 case MVT::v4f32: case MVT::v2f64:
1497 RRC = &ARM::DPRRegClass;
1498 Cost = 2;
1499 break;
1500 case MVT::v4i64:
1501 RRC = &ARM::DPRRegClass;
1502 Cost = 4;
1503 break;
1504 case MVT::v8i64:
1505 RRC = &ARM::DPRRegClass;
1506 Cost = 8;
1507 break;
1508 }
1509 return std::make_pair(RRC, Cost);
1510}
1511
1512const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1513 switch ((ARMISD::NodeType)Opcode) {
1514 case ARMISD::FIRST_NUMBER: break;
1515 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1516 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1517 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1518 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1519 case ARMISD::CALL: return "ARMISD::CALL";
1520 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1521 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1522 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1523 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1524 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1525 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1526 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1527 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1528 case ARMISD::CMP: return "ARMISD::CMP";
1529 case ARMISD::CMN: return "ARMISD::CMN";
1530 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1531 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1532 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1533 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1534 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1535
1536 case ARMISD::CMOV: return "ARMISD::CMOV";
1537 case ARMISD::SUBS: return "ARMISD::SUBS";
1538
1539 case ARMISD::SSAT: return "ARMISD::SSAT";
1540 case ARMISD::USAT: return "ARMISD::USAT";
1541
1542 case ARMISD::ASRL: return "ARMISD::ASRL";
1543 case ARMISD::LSRL: return "ARMISD::LSRL";
1544 case ARMISD::LSLL: return "ARMISD::LSLL";
1545
1546 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1547 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1548 case ARMISD::RRX: return "ARMISD::RRX";
1549
1550 case ARMISD::ADDC: return "ARMISD::ADDC";
1551 case ARMISD::ADDE: return "ARMISD::ADDE";
1552 case ARMISD::SUBC: return "ARMISD::SUBC";
1553 case ARMISD::SUBE: return "ARMISD::SUBE";
1554 case ARMISD::LSLS: return "ARMISD::LSLS";
1555
1556 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1557 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1558 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1559 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1560 case ARMISD::VMOVSR: return "ARMISD::VMOVSR";
1561
1562 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1563 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1564 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1565
1566 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1567
1568 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1569
1570 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1571
1572 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1573
1574 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1575
1576 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1577 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1578
1579 case ARMISD::PREDICATE_CAST: return "ARMISD::PREDICATE_CAST";
1580 case ARMISD::VCMP: return "ARMISD::VCMP";
1581 case ARMISD::VCMPZ: return "ARMISD::VCMPZ";
1582 case ARMISD::VTST: return "ARMISD::VTST";
1583
1584 case ARMISD::VSHLs: return "ARMISD::VSHLs";
1585 case ARMISD::VSHLu: return "ARMISD::VSHLu";
1586 case ARMISD::VSHLIMM: return "ARMISD::VSHLIMM";
1587 case ARMISD::VSHRsIMM: return "ARMISD::VSHRsIMM";
1588 case ARMISD::VSHRuIMM: return "ARMISD::VSHRuIMM";
1589 case ARMISD::VRSHRsIMM: return "ARMISD::VRSHRsIMM";
1590 case ARMISD::VRSHRuIMM: return "ARMISD::VRSHRuIMM";
1591 case ARMISD::VRSHRNIMM: return "ARMISD::VRSHRNIMM";
1592 case ARMISD::VQSHLsIMM: return "ARMISD::VQSHLsIMM";
1593 case ARMISD::VQSHLuIMM: return "ARMISD::VQSHLuIMM";
1594 case ARMISD::VQSHLsuIMM: return "ARMISD::VQSHLsuIMM";
1595 case ARMISD::VQSHRNsIMM: return "ARMISD::VQSHRNsIMM";
1596 case ARMISD::VQSHRNuIMM: return "ARMISD::VQSHRNuIMM";
1597 case ARMISD::VQSHRNsuIMM: return "ARMISD::VQSHRNsuIMM";
1598 case ARMISD::VQRSHRNsIMM: return "ARMISD::VQRSHRNsIMM";
1599 case ARMISD::VQRSHRNuIMM: return "ARMISD::VQRSHRNuIMM";
1600 case ARMISD::VQRSHRNsuIMM: return "ARMISD::VQRSHRNsuIMM";
1601 case ARMISD::VSLIIMM: return "ARMISD::VSLIIMM";
1602 case ARMISD::VSRIIMM: return "ARMISD::VSRIIMM";
1603 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1604 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1605 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1606 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1607 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1608 case ARMISD::VDUP: return "ARMISD::VDUP";
1609 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1610 case ARMISD::VEXT: return "ARMISD::VEXT";
1611 case ARMISD::VREV64: return "ARMISD::VREV64";
1612 case ARMISD::VREV32: return "ARMISD::VREV32";
1613 case ARMISD::VREV16: return "ARMISD::VREV16";
1614 case ARMISD::VZIP: return "ARMISD::VZIP";
1615 case ARMISD::VUZP: return "ARMISD::VUZP";
1616 case ARMISD::VTRN: return "ARMISD::VTRN";
1617 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1618 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1619 case ARMISD::VMOVN: return "ARMISD::VMOVN";
1620 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1621 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1622 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1623 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1624 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1625 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1626 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1627 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1628 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1629 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1630 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1631 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1632 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1633 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1634 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1635 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1636 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1637 case ARMISD::QADD16b: return "ARMISD::QADD16b";
1638 case ARMISD::QSUB16b: return "ARMISD::QSUB16b";
1639 case ARMISD::QADD8b: return "ARMISD::QADD8b";
1640 case ARMISD::QSUB8b: return "ARMISD::QSUB8b";
1641 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1642 case ARMISD::BFI: return "ARMISD::BFI";
1643 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1644 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1645 case ARMISD::VBSL: return "ARMISD::VBSL";
1646 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1647 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1648 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1649 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1650 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1651 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1652 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1653 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1654 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1655 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1656 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1657 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1658 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1659 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1660 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1661 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1662 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1663 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1664 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1665 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1666 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1667 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1668 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1669 case ARMISD::WLS: return "ARMISD::WLS";
1670 case ARMISD::LE: return "ARMISD::LE";
1671 case ARMISD::LOOP_DEC: return "ARMISD::LOOP_DEC";
1672 case ARMISD::CSINV: return "ARMISD::CSINV";
1673 case ARMISD::CSNEG: return "ARMISD::CSNEG";
1674 case ARMISD::CSINC: return "ARMISD::CSINC";
1675 }
1676 return nullptr;
1677}
1678
1679EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1680 EVT VT) const {
1681 if (!VT.isVector())
1682 return getPointerTy(DL);
1683
1684 // MVE has a predicate register.
1685 if (Subtarget->hasMVEIntegerOps() &&
1686 (VT == MVT::v4i32 || VT == MVT::v8i16 || VT == MVT::v16i8))
1687 return MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
1688 return VT.changeVectorElementTypeToInteger();
1689}
1690
1691/// getRegClassFor - Return the register class that should be used for the
1692/// specified value type.
1693const TargetRegisterClass *
1694ARMTargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
1695 (void)isDivergent;
1696 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1697 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1698 // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
1699 // MVE Q registers.
1700 if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
1701 if (VT == MVT::v4i64)
1702 return &ARM::QQPRRegClass;
1703 if (VT == MVT::v8i64)
1704 return &ARM::QQQQPRRegClass;
1705 }
1706 return TargetLowering::getRegClassFor(VT);
1707}
1708
1709// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1710// source/dest is aligned and the copy size is large enough. We therefore want
1711// to align such objects passed to memory intrinsics.
1712bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1713 unsigned &PrefAlign) const {
1714 if (!isa<MemIntrinsic>(CI))
1715 return false;
1716 MinSize = 8;
1717 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1718 // cycle faster than 4-byte aligned LDM.
1719 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1720 return true;
1721}
1722
1723// Create a fast isel object.
1724FastISel *
1725ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1726 const TargetLibraryInfo *libInfo) const {
1727 return ARM::createFastISel(funcInfo, libInfo);
1728}
1729
1730Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1731 unsigned NumVals = N->getNumValues();
1732 if (!NumVals)
1733 return Sched::RegPressure;
1734
1735 for (unsigned i = 0; i != NumVals; ++i) {
1736 EVT VT = N->getValueType(i);
1737 if (VT == MVT::Glue || VT == MVT::Other)
1738 continue;
1739 if (VT.isFloatingPoint() || VT.isVector())
1740 return Sched::ILP;
1741 }
1742
1743 if (!N->isMachineOpcode())
1744 return Sched::RegPressure;
1745
1746 // Load are scheduled for latency even if there instruction itinerary
1747 // is not available.
1748 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1749 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1750
1751 if (MCID.getNumDefs() == 0)
1752 return Sched::RegPressure;
1753 if (!Itins->isEmpty() &&
1754 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1755 return Sched::ILP;
1756
1757 return Sched::RegPressure;
1758}
1759
1760//===----------------------------------------------------------------------===//
1761// Lowering Code
1762//===----------------------------------------------------------------------===//
1763
1764static bool isSRL16(const SDValue &Op) {
1765 if (Op.getOpcode() != ISD::SRL)
1766 return false;
1767 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1768 return Const->getZExtValue() == 16;
1769 return false;
1770}
1771
1772static bool isSRA16(const SDValue &Op) {
1773 if (Op.getOpcode() != ISD::SRA)
1774 return false;
1775 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1776 return Const->getZExtValue() == 16;
1777 return false;
1778}
1779
1780static bool isSHL16(const SDValue &Op) {
1781 if (Op.getOpcode() != ISD::SHL)
1782 return false;
1783 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1784 return Const->getZExtValue() == 16;
1785 return false;
1786}
1787
1788// Check for a signed 16-bit value. We special case SRA because it makes it
1789// more simple when also looking for SRAs that aren't sign extending a
1790// smaller value. Without the check, we'd need to take extra care with
1791// checking order for some operations.
1792static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1793 if (isSRA16(Op))
1794 return isSHL16(Op.getOperand(0));
1795 return DAG.ComputeNumSignBits(Op) == 17;
1796}
1797
1798/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1799static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1800 switch (CC) {
1801 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1801)
;
1802 case ISD::SETNE: return ARMCC::NE;
1803 case ISD::SETEQ: return ARMCC::EQ;
1804 case ISD::SETGT: return ARMCC::GT;
1805 case ISD::SETGE: return ARMCC::GE;
1806 case ISD::SETLT: return ARMCC::LT;
1807 case ISD::SETLE: return ARMCC::LE;
1808 case ISD::SETUGT: return ARMCC::HI;
1809 case ISD::SETUGE: return ARMCC::HS;
1810 case ISD::SETULT: return ARMCC::LO;
1811 case ISD::SETULE: return ARMCC::LS;
1812 }
1813}
1814
1815/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1816static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1817 ARMCC::CondCodes &CondCode2) {
1818 CondCode2 = ARMCC::AL;
1819 switch (CC) {
1820 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1820)
;
1821 case ISD::SETEQ:
1822 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1823 case ISD::SETGT:
1824 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1825 case ISD::SETGE:
1826 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1827 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1828 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1829 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1830 case ISD::SETO: CondCode = ARMCC::VC; break;
1831 case ISD::SETUO: CondCode = ARMCC::VS; break;
1832 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1833 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1834 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1835 case ISD::SETLT:
1836 case ISD::SETULT: CondCode = ARMCC::LT; break;
1837 case ISD::SETLE:
1838 case ISD::SETULE: CondCode = ARMCC::LE; break;
1839 case ISD::SETNE:
1840 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1841 }
1842}
1843
1844//===----------------------------------------------------------------------===//
1845// Calling Convention Implementation
1846//===----------------------------------------------------------------------===//
1847
1848/// getEffectiveCallingConv - Get the effective calling convention, taking into
1849/// account presence of floating point hardware and calling convention
1850/// limitations, such as support for variadic functions.
1851CallingConv::ID
1852ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1853 bool isVarArg) const {
1854 switch (CC) {
1855 default:
1856 report_fatal_error("Unsupported calling convention");
1857 case CallingConv::ARM_AAPCS:
1858 case CallingConv::ARM_APCS:
1859 case CallingConv::GHC:
1860 case CallingConv::CFGuard_Check:
1861 return CC;
1862 case CallingConv::PreserveMost:
1863 return CallingConv::PreserveMost;
1864 case CallingConv::ARM_AAPCS_VFP:
1865 case CallingConv::Swift:
1866 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1867 case CallingConv::C:
1868 if (!Subtarget->isAAPCS_ABI())
1869 return CallingConv::ARM_APCS;
1870 else if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() &&
1871 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1872 !isVarArg)
1873 return CallingConv::ARM_AAPCS_VFP;
1874 else
1875 return CallingConv::ARM_AAPCS;
1876 case CallingConv::Fast:
1877 case CallingConv::CXX_FAST_TLS:
1878 if (!Subtarget->isAAPCS_ABI()) {
1879 if (Subtarget->hasVFP2Base() && !Subtarget->isThumb1Only() && !isVarArg)
1880 return CallingConv::Fast;
1881 return CallingConv::ARM_APCS;
1882 } else if (Subtarget->hasVFP2Base() &&
1883 !Subtarget->isThumb1Only() && !isVarArg)
1884 return CallingConv::ARM_AAPCS_VFP;
1885 else
1886 return CallingConv::ARM_AAPCS;
1887 }
1888}
1889
1890CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1891 bool isVarArg) const {
1892 return CCAssignFnForNode(CC, false, isVarArg);
1893}
1894
1895CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1896 bool isVarArg) const {
1897 return CCAssignFnForNode(CC, true, isVarArg);
1898}
1899
1900/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1901/// CallingConvention.
1902CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1903 bool Return,
1904 bool isVarArg) const {
1905 switch (getEffectiveCallingConv(CC, isVarArg)) {
1906 default:
1907 report_fatal_error("Unsupported calling convention");
1908 case CallingConv::ARM_APCS:
1909 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1910 case CallingConv::ARM_AAPCS:
1911 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1912 case CallingConv::ARM_AAPCS_VFP:
1913 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1914 case CallingConv::Fast:
1915 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1916 case CallingConv::GHC:
1917 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1918 case CallingConv::PreserveMost:
1919 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1920 case CallingConv::CFGuard_Check:
1921 return (Return ? RetCC_ARM_AAPCS : CC_ARM_Win32_CFGuard_Check);
1922 }
1923}
1924
1925/// LowerCallResult - Lower the result values of a call into the
1926/// appropriate copies out of appropriate physical registers.
1927SDValue ARMTargetLowering::LowerCallResult(
1928 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1929 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1930 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1931 SDValue ThisVal) const {
1932 // Assign locations to each value returned by this call.
1933 SmallVector<CCValAssign, 16> RVLocs;
1934 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1935 *DAG.getContext());
1936 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1937
1938 // Copy all of the result registers out of their specified physreg.
1939 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1940 CCValAssign VA = RVLocs[i];
1941
1942 // Pass 'this' value directly from the argument to return value, to avoid
1943 // reg unit interference
1944 if (i == 0 && isThisReturn) {
1945 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1946, __PRETTY_FUNCTION__))
1946 "unexpected return calling convention register assignment")((!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
"unexpected return calling convention register assignment") ?
static_cast<void> (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1946, __PRETTY_FUNCTION__))
;
1947 InVals.push_back(ThisVal);
1948 continue;
1949 }
1950
1951 SDValue Val;
1952 if (VA.needsCustom()) {
1953 // Handle f64 or half of a v2f64.
1954 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1955 InFlag);
1956 Chain = Lo.getValue(1);
1957 InFlag = Lo.getValue(2);
1958 VA = RVLocs[++i]; // skip ahead to next loc
1959 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1960 InFlag);
1961 Chain = Hi.getValue(1);
1962 InFlag = Hi.getValue(2);
1963 if (!Subtarget->isLittle())
1964 std::swap (Lo, Hi);
1965 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1966
1967 if (VA.getLocVT() == MVT::v2f64) {
1968 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1969 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1970 DAG.getConstant(0, dl, MVT::i32));
1971
1972 VA = RVLocs[++i]; // skip ahead to next loc
1973 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1974 Chain = Lo.getValue(1);
1975 InFlag = Lo.getValue(2);
1976 VA = RVLocs[++i]; // skip ahead to next loc
1977 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1978 Chain = Hi.getValue(1);
1979 InFlag = Hi.getValue(2);
1980 if (!Subtarget->isLittle())
1981 std::swap (Lo, Hi);
1982 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1983 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1984 DAG.getConstant(1, dl, MVT::i32));
1985 }
1986 } else {
1987 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1988 InFlag);
1989 Chain = Val.getValue(1);
1990 InFlag = Val.getValue(2);
1991 }
1992
1993 switch (VA.getLocInfo()) {
1994 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 1994)
;
1995 case CCValAssign::Full: break;
1996 case CCValAssign::BCvt:
1997 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1998 break;
1999 }
2000
2001 InVals.push_back(Val);
2002 }
2003
2004 return Chain;
2005}
2006
2007/// LowerMemOpCallTo - Store the argument to the stack.
2008SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
2009 SDValue Arg, const SDLoc &dl,
2010 SelectionDAG &DAG,
2011 const CCValAssign &VA,
2012 ISD::ArgFlagsTy Flags) const {
2013 unsigned LocMemOffset = VA.getLocMemOffset();
2014 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2015 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2016 StackPtr, PtrOff);
2017 return DAG.getStore(
2018 Chain, dl, Arg, PtrOff,
2019 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
2020}
2021
2022void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
2023 SDValue Chain, SDValue &Arg,
2024 RegsToPassVector &RegsToPass,
2025 CCValAssign &VA, CCValAssign &NextVA,
2026 SDValue &StackPtr,
2027 SmallVectorImpl<SDValue> &MemOpChains,
2028 ISD::ArgFlagsTy Flags) const {
2029 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2030 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2031 unsigned id = Subtarget->isLittle() ? 0 : 1;
2032 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
2033
2034 if (NextVA.isRegLoc())
2035 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
2036 else {
2037 assert(NextVA.isMemLoc())((NextVA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2037, __PRETTY_FUNCTION__))
;
2038 if (!StackPtr.getNode())
2039 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
2040 getPointerTy(DAG.getDataLayout()));
2041
2042 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
2043 dl, DAG, NextVA,
2044 Flags));
2045 }
2046}
2047
2048/// LowerCall - Lowering a call into a callseq_start <-
2049/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
2050/// nodes.
2051SDValue
2052ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2053 SmallVectorImpl<SDValue> &InVals) const {
2054 SelectionDAG &DAG = CLI.DAG;
2055 SDLoc &dl = CLI.DL;
2056 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2057 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2058 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2059 SDValue Chain = CLI.Chain;
2060 SDValue Callee = CLI.Callee;
2061 bool &isTailCall = CLI.IsTailCall;
2062 CallingConv::ID CallConv = CLI.CallConv;
2063 bool doesNotRet = CLI.DoesNotReturn;
2064 bool isVarArg = CLI.IsVarArg;
2065
2066 MachineFunction &MF = DAG.getMachineFunction();
2067 MachineFunction::CallSiteInfo CSInfo;
2068 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2069 bool isThisReturn = false;
2070 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
2071 bool PreferIndirect = false;
2072
2073 // Disable tail calls if they're not supported.
2074 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
2075 isTailCall = false;
2076
2077 if (isa<GlobalAddressSDNode>(Callee)) {
2078 // If we're optimizing for minimum size and the function is called three or
2079 // more times in this block, we can improve codesize by calling indirectly
2080 // as BLXr has a 16-bit encoding.
2081 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2082 if (CLI.CS) {
2083 auto *BB = CLI.CS.getParent();
2084 PreferIndirect = Subtarget->isThumb() && Subtarget->hasMinSize() &&
2085 count_if(GV->users(), [&BB](const User *U) {
2086 return isa<Instruction>(U) &&
2087 cast<Instruction>(U)->getParent() == BB;
2088 }) > 2;
2089 }
2090 }
2091 if (isTailCall) {
2092 // Check if it's really possible to do a tail call.
2093 isTailCall = IsEligibleForTailCallOptimization(
2094 Callee, CallConv, isVarArg, isStructRet,
2095 MF.getFunction().hasStructRetAttr(), Outs, OutVals, Ins, DAG,
2096 PreferIndirect);
2097 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
2098 report_fatal_error("failed to perform tail call elimination on a call "
2099 "site marked musttail");
2100 // We don't support GuaranteedTailCallOpt for ARM, only automatically
2101 // detected sibcalls.
2102 if (isTailCall)
2103 ++NumTailCalls;
2104 }
2105
2106 // Analyze operands of the call, assigning locations to each operand.
2107 SmallVector<CCValAssign, 16> ArgLocs;
2108 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2109 *DAG.getContext());
2110 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
2111
2112 // Get a count of how many bytes are to be pushed on the stack.
2113 unsigned NumBytes = CCInfo.getNextStackOffset();
2114
2115 if (isTailCall) {
2116 // For tail calls, memory operands are available in our caller's stack.
2117 NumBytes = 0;
2118 } else {
2119 // Adjust the stack pointer for the new arguments...
2120 // These operations are automatically eliminated by the prolog/epilog pass
2121 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
2122 }
2123
2124 SDValue StackPtr =
2125 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
2126
2127 RegsToPassVector RegsToPass;
2128 SmallVector<SDValue, 8> MemOpChains;
2129
2130 // Walk the register/memloc assignments, inserting copies/loads. In the case
2131 // of tail call optimization, arguments are handled later.
2132 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2133 i != e;
2134 ++i, ++realArgIdx) {
2135 CCValAssign &VA = ArgLocs[i];
2136 SDValue Arg = OutVals[realArgIdx];
2137 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2138 bool isByVal = Flags.isByVal();
2139
2140 // Promote the value if needed.
2141 switch (VA.getLocInfo()) {
2142 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2142)
;
2143 case CCValAssign::Full: break;
2144 case CCValAssign::SExt:
2145 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
2146 break;
2147 case CCValAssign::ZExt:
2148 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
2149 break;
2150 case CCValAssign::AExt:
2151 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
2152 break;
2153 case CCValAssign::BCvt:
2154 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2155 break;
2156 }
2157
2158 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
2159 if (VA.needsCustom()) {
2160 if (VA.getLocVT() == MVT::v2f64) {
2161 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2162 DAG.getConstant(0, dl, MVT::i32));
2163 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2164 DAG.getConstant(1, dl, MVT::i32));
2165
2166 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
2167 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
2168
2169 VA = ArgLocs[++i]; // skip ahead to next loc
2170 if (VA.isRegLoc()) {
2171 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
2172 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
2173 } else {
2174 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2174, __PRETTY_FUNCTION__))
;
2175
2176 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
2177 dl, DAG, VA, Flags));
2178 }
2179 } else {
2180 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
2181 StackPtr, MemOpChains, Flags);
2182 }
2183 } else if (VA.isRegLoc()) {
2184 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
2185 Outs[0].VT == MVT::i32) {
2186 assert(VA.getLocVT() == MVT::i32 &&((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2187, __PRETTY_FUNCTION__))
2187 "unexpected calling convention register assignment")((VA.getLocVT() == MVT::i32 && "unexpected calling convention register assignment"
) ? static_cast<void> (0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2187, __PRETTY_FUNCTION__))
;
2188 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2189, __PRETTY_FUNCTION__))
2189 "unexpected use of 'returned'")((!Ins.empty() && Ins[0].VT == MVT::i32 && "unexpected use of 'returned'"
) ? static_cast<void> (0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2189, __PRETTY_FUNCTION__))
;
2190 isThisReturn = true;
2191 }
2192 const TargetOptions &Options = DAG.getTarget().Options;
2193 if (Options.EnableDebugEntryValues)
2194 CSInfo.emplace_back(VA.getLocReg(), i);
2195 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2196 } else if (isByVal) {
2197 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2197, __PRETTY_FUNCTION__))
;
2198 unsigned offset = 0;
2199
2200 // True if this byval aggregate will be split between registers
2201 // and memory.
2202 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
2203 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
2204
2205 if (CurByValIdx < ByValArgsCount) {
2206
2207 unsigned RegBegin, RegEnd;
2208 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
2209
2210 EVT PtrVT =
2211 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2212 unsigned int i, j;
2213 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
2214 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
2215 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2216 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
2217 MachinePointerInfo(),
2218 DAG.InferPtrAlignment(AddArg));
2219 MemOpChains.push_back(Load.getValue(1));
2220 RegsToPass.push_back(std::make_pair(j, Load));
2221 }
2222
2223 // If parameter size outsides register area, "offset" value
2224 // helps us to calculate stack slot for remained part properly.
2225 offset = RegEnd - RegBegin;
2226
2227 CCInfo.nextInRegsParam();
2228 }
2229
2230 if (Flags.getByValSize() > 4*offset) {
2231 auto PtrVT = getPointerTy(DAG.getDataLayout());
2232 unsigned LocMemOffset = VA.getLocMemOffset();
2233 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2234 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
2235 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
2236 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
2237 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
2238 MVT::i32);
2239 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
2240 MVT::i32);
2241
2242 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2243 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
2244 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
2245 Ops));
2246 }
2247 } else if (!isTailCall) {
2248 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2248, __PRETTY_FUNCTION__))
;
2249
2250 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2251 dl, DAG, VA, Flags));
2252 }
2253 }
2254
2255 if (!MemOpChains.empty())
2256 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2257
2258 // Build a sequence of copy-to-reg nodes chained together with token chain
2259 // and flag operands which copy the outgoing args into the appropriate regs.
2260 SDValue InFlag;
2261 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2262 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2263 RegsToPass[i].second, InFlag);
2264 InFlag = Chain.getValue(1);
2265 }
2266
2267 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2268 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2269 // node so that legalize doesn't hack it.
2270 bool isDirect = false;
2271
2272 const TargetMachine &TM = getTargetMachine();
2273 const Module *Mod = MF.getFunction().getParent();
2274 const GlobalValue *GV = nullptr;
2275 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2276 GV = G->getGlobal();
2277 bool isStub =
2278 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2279
2280 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2281 bool isLocalARMFunc = false;
2282 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2283 auto PtrVt = getPointerTy(DAG.getDataLayout());
2284
2285 if (Subtarget->genLongCalls()) {
2286 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2287, __PRETTY_FUNCTION__))
2287 "long-calls codegen is not position independent!")(((!isPositionIndependent() || Subtarget->isTargetWindows(
)) && "long-calls codegen is not position independent!"
) ? static_cast<void> (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2287, __PRETTY_FUNCTION__))
;
2288 // Handle a global address or an external symbol. If it's not one of
2289 // those, the target's already in a register, so we don't need to do
2290 // anything extra.
2291 if (isa<GlobalAddressSDNode>(Callee)) {
2292 // Create a constant pool entry for the callee address
2293 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2294 ARMConstantPoolValue *CPV =
2295 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2296
2297 // Get the address of the callee into a register
2298 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2299 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2300 Callee = DAG.getLoad(
2301 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2302 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2303 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2304 const char *Sym = S->getSymbol();
2305
2306 // Create a constant pool entry for the callee address
2307 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2308 ARMConstantPoolValue *CPV =
2309 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2310 ARMPCLabelIndex, 0);
2311 // Get the address of the callee into a register
2312 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2313 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2314 Callee = DAG.getLoad(
2315 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2316 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2317 }
2318 } else if (isa<GlobalAddressSDNode>(Callee)) {
2319 if (!PreferIndirect) {
2320 isDirect = true;
2321 bool isDef = GV->isStrongDefinitionForLinker();
2322
2323 // ARM call to a local ARM function is predicable.
2324 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2325 // tBX takes a register source operand.
2326 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2327 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")((Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2327, __PRETTY_FUNCTION__))
;
2328 Callee = DAG.getNode(
2329 ARMISD::WrapperPIC, dl, PtrVt,
2330 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2331 Callee = DAG.getLoad(
2332 PtrVt, dl, DAG.getEntryNode(), Callee,
2333 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2334 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2335 MachineMemOperand::MOInvariant);
2336 } else if (Subtarget->isTargetCOFF()) {
2337 assert(Subtarget->isTargetWindows() &&((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2338, __PRETTY_FUNCTION__))
2338 "Windows is the only supported COFF target")((Subtarget->isTargetWindows() && "Windows is the only supported COFF target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2338, __PRETTY_FUNCTION__))
;
2339 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2340 ? ARMII::MO_DLLIMPORT
2341 : ARMII::MO_NO_FLAG;
2342 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*offset=*/0,
2343 TargetFlags);
2344 if (GV->hasDLLImportStorageClass())
2345 Callee =
2346 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2347 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2348 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2349 } else {
2350 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2351 }
2352 }
2353 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2354 isDirect = true;
2355 // tBX takes a register source operand.
2356 const char *Sym = S->getSymbol();
2357 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2358 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2359 ARMConstantPoolValue *CPV =
2360 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2361 ARMPCLabelIndex, 4);
2362 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2363 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2364 Callee = DAG.getLoad(
2365 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2366 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2367 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2368 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2369 } else {
2370 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2371 }
2372 }
2373
2374 // FIXME: handle tail calls differently.
2375 unsigned CallOpc;
2376 if (Subtarget->isThumb()) {
2377 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2378 CallOpc = ARMISD::CALL_NOLINK;
2379 else
2380 CallOpc = ARMISD::CALL;
2381 } else {
2382 if (!isDirect && !Subtarget->hasV5TOps())
2383 CallOpc = ARMISD::CALL_NOLINK;
2384 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2385 // Emit regular call when code size is the priority
2386 !Subtarget->hasMinSize())
2387 // "mov lr, pc; b _foo" to avoid confusing the RSP
2388 CallOpc = ARMISD::CALL_NOLINK;
2389 else
2390 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2391 }
2392
2393 std::vector<SDValue> Ops;
2394 Ops.push_back(Chain);
2395 Ops.push_back(Callee);
2396
2397 // Add argument registers to the end of the list so that they are known live
2398 // into the call.
2399 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2400 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2401 RegsToPass[i].second.getValueType()));
2402
2403 // Add a register mask operand representing the call-preserved registers.
2404 if (!isTailCall) {
2405 const uint32_t *Mask;
2406 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2407 if (isThisReturn) {
2408 // For 'this' returns, use the R0-preserving mask if applicable
2409 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2410 if (!Mask) {
2411 // Set isThisReturn to false if the calling convention is not one that
2412 // allows 'returned' to be modeled in this way, so LowerCallResult does
2413 // not try to pass 'this' straight through
2414 isThisReturn = false;
2415 Mask = ARI->getCallPreservedMask(MF, CallConv);
2416 }
2417 } else
2418 Mask = ARI->getCallPreservedMask(MF, CallConv);
2419
2420 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2420, __PRETTY_FUNCTION__))
;
2421 Ops.push_back(DAG.getRegisterMask(Mask));
2422 }
2423
2424 if (InFlag.getNode())
2425 Ops.push_back(InFlag);
2426
2427 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2428 if (isTailCall) {
2429 MF.getFrameInfo().setHasTailCall();
2430 SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2431 DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
2432 return Ret;
2433 }
2434
2435 // Returns a chain and a flag for retval copy to use.
2436 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2437 InFlag = Chain.getValue(1);
2438 DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo));
2439
2440 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2441 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2442 if (!Ins.empty())
2443 InFlag = Chain.getValue(1);
2444
2445 // Handle result values, copying them out of physregs into vregs that we
2446 // return.
2447 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2448 InVals, isThisReturn,
2449 isThisReturn ? OutVals[0] : SDValue());
2450}
2451
2452/// HandleByVal - Every parameter *after* a byval parameter is passed
2453/// on the stack. Remember the next parameter register to allocate,
2454/// and then confiscate the rest of the parameter registers to insure
2455/// this.
2456void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2457 unsigned Align) const {
2458 // Byval (as with any stack) slots are always at least 4 byte aligned.
2459 Align = std::max(Align, 4U);
2460
2461 unsigned Reg = State->AllocateReg(GPRArgRegs);
2462 if (!Reg)
2463 return;
2464
2465 unsigned AlignInRegs = Align / 4;
2466 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2467 for (unsigned i = 0; i < Waste; ++i)
2468 Reg = State->AllocateReg(GPRArgRegs);
2469
2470 if (!Reg)
2471 return;
2472
2473 unsigned Excess = 4 * (ARM::R4 - Reg);
2474
2475 // Special case when NSAA != SP and parameter size greater than size of
2476 // all remained GPR regs. In that case we can't split parameter, we must
2477 // send it to stack. We also must set NCRN to R4, so waste all
2478 // remained registers.
2479 const unsigned NSAAOffset = State->getNextStackOffset();
2480 if (NSAAOffset != 0 && Size > Excess) {
2481 while (State->AllocateReg(GPRArgRegs))
2482 ;
2483 return;
2484 }
2485
2486 // First register for byval parameter is the first register that wasn't
2487 // allocated before this method call, so it would be "reg".
2488 // If parameter is small enough to be saved in range [reg, r4), then
2489 // the end (first after last) register would be reg + param-size-in-regs,
2490 // else parameter would be splitted between registers and stack,
2491 // end register would be r4 in this case.
2492 unsigned ByValRegBegin = Reg;
2493 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2494 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2495 // Note, first register is allocated in the beginning of function already,
2496 // allocate remained amount of registers we need.
2497 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2498 State->AllocateReg(GPRArgRegs);
2499 // A byval parameter that is split between registers and memory needs its
2500 // size truncated here.
2501 // In the case where the entire structure fits in registers, we set the
2502 // size in memory to zero.
2503 Size = std::max<int>(Size - Excess, 0);
2504}
2505
2506/// MatchingStackOffset - Return true if the given stack call argument is
2507/// already available in the same position (relatively) of the caller's
2508/// incoming argument stack.
2509static
2510bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2511 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2512 const TargetInstrInfo *TII) {
2513 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2514 int FI = std::numeric_limits<int>::max();
2515 if (Arg.getOpcode() == ISD::CopyFromReg) {
2516 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2517 if (!Register::isVirtualRegister(VR))
2518 return false;
2519 MachineInstr *Def = MRI->getVRegDef(VR);
2520 if (!Def)
2521 return false;
2522 if (!Flags.isByVal()) {
2523 if (!TII->isLoadFromStackSlot(*Def, FI))
2524 return false;
2525 } else {
2526 return false;
2527 }
2528 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2529 if (Flags.isByVal())
2530 // ByVal argument is passed in as a pointer but it's now being
2531 // dereferenced. e.g.
2532 // define @foo(%struct.X* %A) {
2533 // tail call @bar(%struct.X* byval %A)
2534 // }
2535 return false;
2536 SDValue Ptr = Ld->getBasePtr();
2537 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2538 if (!FINode)
2539 return false;
2540 FI = FINode->getIndex();
2541 } else
2542 return false;
2543
2544 assert(FI != std::numeric_limits<int>::max())((FI != std::numeric_limits<int>::max()) ? static_cast<
void> (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2544, __PRETTY_FUNCTION__))
;
2545 if (!MFI.isFixedObjectIndex(FI))
2546 return false;
2547 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2548}
2549
2550/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2551/// for tail call optimization. Targets which want to do tail call
2552/// optimization should implement this function.
2553bool ARMTargetLowering::IsEligibleForTailCallOptimization(
2554 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2555 bool isCalleeStructRet, bool isCallerStructRet,
2556 const SmallVectorImpl<ISD::OutputArg> &Outs,
2557 const SmallVectorImpl<SDValue> &OutVals,
2558 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
2559 const bool isIndirect) const {
2560 MachineFunction &MF = DAG.getMachineFunction();
2561 const Function &CallerF = MF.getFunction();
2562 CallingConv::ID CallerCC = CallerF.getCallingConv();
2563
2564 assert(Subtarget->supportsTailCall())((Subtarget->supportsTailCall()) ? static_cast<void>
(0) : __assert_fail ("Subtarget->supportsTailCall()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2564, __PRETTY_FUNCTION__))
;
2565
2566 // Indirect tail calls cannot be optimized for Thumb1 if the args
2567 // to the call take up r0-r3. The reason is that there are no legal registers
2568 // left to hold the pointer to the function to be called.
2569 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2570 (!isa<GlobalAddressSDNode>(Callee.getNode()) || isIndirect))
2571 return false;
2572
2573 // Look for obvious safe cases to perform tail call optimization that do not
2574 // require ABI changes. This is what gcc calls sibcall.
2575
2576 // Exception-handling functions need a special set of instructions to indicate
2577 // a return to the hardware. Tail-calling another function would probably
2578 // break this.
2579 if (CallerF.hasFnAttribute("interrupt"))
2580 return false;
2581
2582 // Also avoid sibcall optimization if either caller or callee uses struct
2583 // return semantics.
2584 if (isCalleeStructRet || isCallerStructRet)
2585 return false;
2586
2587 // Externally-defined functions with weak linkage should not be
2588 // tail-called on ARM when the OS does not support dynamic
2589 // pre-emption of symbols, as the AAELF spec requires normal calls
2590 // to undefined weak functions to be replaced with a NOP or jump to the
2591 // next instruction. The behaviour of branch instructions in this
2592 // situation (as used for tail calls) is implementation-defined, so we
2593 // cannot rely on the linker replacing the tail call with a return.
2594 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2595 const GlobalValue *GV = G->getGlobal();
2596 const Triple &TT = getTargetMachine().getTargetTriple();
2597 if (GV->hasExternalWeakLinkage() &&
2598 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2599 return false;
2600 }
2601
2602 // Check that the call results are passed in the same way.
2603 LLVMContext &C = *DAG.getContext();
2604 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2605 CCAssignFnForReturn(CalleeCC, isVarArg),
2606 CCAssignFnForReturn(CallerCC, isVarArg)))
2607 return false;
2608 // The callee has to preserve all registers the caller needs to preserve.
2609 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2610 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2611 if (CalleeCC != CallerCC) {
2612 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2613 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2614 return false;
2615 }
2616
2617 // If Caller's vararg or byval argument has been split between registers and
2618 // stack, do not perform tail call, since part of the argument is in caller's
2619 // local frame.
2620 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2621 if (AFI_Caller->getArgRegsSaveSize())
2622 return false;
2623
2624 // If the callee takes no arguments then go on to check the results of the
2625 // call.
2626 if (!Outs.empty()) {
2627 // Check if stack adjustment is needed. For now, do not do this if any
2628 // argument is passed on the stack.
2629 SmallVector<CCValAssign, 16> ArgLocs;
2630 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2631 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2632 if (CCInfo.getNextStackOffset()) {
2633 // Check if the arguments are already laid out in the right way as
2634 // the caller's fixed stack objects.
2635 MachineFrameInfo &MFI = MF.getFrameInfo();
2636 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2637 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2638 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2639 i != e;
2640 ++i, ++realArgIdx) {
2641 CCValAssign &VA = ArgLocs[i];
2642 EVT RegVT = VA.getLocVT();
2643 SDValue Arg = OutVals[realArgIdx];
2644 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2645 if (VA.getLocInfo() == CCValAssign::Indirect)
2646 return false;
2647 if (VA.needsCustom()) {
2648 // f64 and vector types are split into multiple registers or
2649 // register/stack-slot combinations. The types will not match
2650 // the registers; give up on memory f64 refs until we figure
2651 // out what to do about this.
2652 if (!VA.isRegLoc())
2653 return false;
2654 if (!ArgLocs[++i].isRegLoc())
2655 return false;
2656 if (RegVT == MVT::v2f64) {
2657 if (!ArgLocs[++i].isRegLoc())
2658 return false;
2659 if (!ArgLocs[++i].isRegLoc())
2660 return false;
2661 }
2662 } else if (!VA.isRegLoc()) {
2663 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2664 MFI, MRI, TII))
2665 return false;
2666 }
2667 }
2668 }
2669
2670 const MachineRegisterInfo &MRI = MF.getRegInfo();
2671 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2672 return false;
2673 }
2674
2675 return true;
2676}
2677
2678bool
2679ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2680 MachineFunction &MF, bool isVarArg,
2681 const SmallVectorImpl<ISD::OutputArg> &Outs,
2682 LLVMContext &Context) const {
2683 SmallVector<CCValAssign, 16> RVLocs;
2684 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2685 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2686}
2687
2688static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2689 const SDLoc &DL, SelectionDAG &DAG) {
2690 const MachineFunction &MF = DAG.getMachineFunction();
2691 const Function &F = MF.getFunction();
2692
2693 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2694
2695 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2696 // version of the "preferred return address". These offsets affect the return
2697 // instruction if this is a return from PL1 without hypervisor extensions.
2698 // IRQ/FIQ: +4 "subs pc, lr, #4"
2699 // SWI: 0 "subs pc, lr, #0"
2700 // ABORT: +4 "subs pc, lr, #4"
2701 // UNDEF: +4/+2 "subs pc, lr, #0"
2702 // UNDEF varies depending on where the exception came from ARM or Thumb
2703 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2704
2705 int64_t LROffset;
2706 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2707 IntKind == "ABORT")
2708 LROffset = 4;
2709 else if (IntKind == "SWI" || IntKind == "UNDEF")
2710 LROffset = 0;
2711 else
2712 report_fatal_error("Unsupported interrupt attribute. If present, value "
2713 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2714
2715 RetOps.insert(RetOps.begin() + 1,
2716 DAG.getConstant(LROffset, DL, MVT::i32, false));
2717
2718 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2719}
2720
2721SDValue
2722ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2723 bool isVarArg,
2724 const SmallVectorImpl<ISD::OutputArg> &Outs,
2725 const SmallVectorImpl<SDValue> &OutVals,
2726 const SDLoc &dl, SelectionDAG &DAG) const {
2727 // CCValAssign - represent the assignment of the return value to a location.
2728 SmallVector<CCValAssign, 16> RVLocs;
2729
2730 // CCState - Info about the registers and stack slots.
2731 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2732 *DAG.getContext());
2733
2734 // Analyze outgoing return values.
2735 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2736
2737 SDValue Flag;
2738 SmallVector<SDValue, 4> RetOps;
2739 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2740 bool isLittleEndian = Subtarget->isLittle();
2741
2742 MachineFunction &MF = DAG.getMachineFunction();
2743 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2744 AFI->setReturnRegsCount(RVLocs.size());
2745
2746 // Copy the result values into the output registers.
2747 for (unsigned i = 0, realRVLocIdx = 0;
2748 i != RVLocs.size();
2749 ++i, ++realRVLocIdx) {
2750 CCValAssign &VA = RVLocs[i];
2751 assert(VA.isRegLoc() && "Can only return in registers!")((VA.isRegLoc() && "Can only return in registers!") ?
static_cast<void> (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2751, __PRETTY_FUNCTION__))
;
2752
2753 SDValue Arg = OutVals[realRVLocIdx];
2754 bool ReturnF16 = false;
2755
2756 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2757 // Half-precision return values can be returned like this:
2758 //
2759 // t11 f16 = fadd ...
2760 // t12: i16 = bitcast t11
2761 // t13: i32 = zero_extend t12
2762 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2763 //
2764 // to avoid code generation for bitcasts, we simply set Arg to the node
2765 // that produces the f16 value, t11 in this case.
2766 //
2767 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2768 SDValue ZE = Arg.getOperand(0);
2769 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2770 SDValue BC = ZE.getOperand(0);
2771 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2772 Arg = BC.getOperand(0);
2773 ReturnF16 = true;
2774 }
2775 }
2776 }
2777 }
2778
2779 switch (VA.getLocInfo()) {
2780 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2780)
;
2781 case CCValAssign::Full: break;
2782 case CCValAssign::BCvt:
2783 if (!ReturnF16)
2784 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2785 break;
2786 }
2787
2788 if (VA.needsCustom()) {
2789 if (VA.getLocVT() == MVT::v2f64) {
2790 // Extract the first half and return it in two registers.
2791 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2792 DAG.getConstant(0, dl, MVT::i32));
2793 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2794 DAG.getVTList(MVT::i32, MVT::i32), Half);
2795
2796 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2797 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2798 Flag);
2799 Flag = Chain.getValue(1);
2800 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2801 VA = RVLocs[++i]; // skip ahead to next loc
2802 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2803 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2804 Flag);
2805 Flag = Chain.getValue(1);
2806 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2807 VA = RVLocs[++i]; // skip ahead to next loc
2808
2809 // Extract the 2nd half and fall through to handle it as an f64 value.
2810 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2811 DAG.getConstant(1, dl, MVT::i32));
2812 }
2813 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2814 // available.
2815 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2816 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2817 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2818 fmrrd.getValue(isLittleEndian ? 0 : 1),
2819 Flag);
2820 Flag = Chain.getValue(1);
2821 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2822 VA = RVLocs[++i]; // skip ahead to next loc
2823 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2824 fmrrd.getValue(isLittleEndian ? 1 : 0),
2825 Flag);
2826 } else
2827 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2828
2829 // Guarantee that all emitted copies are
2830 // stuck together, avoiding something bad.
2831 Flag = Chain.getValue(1);
2832 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2833 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2834 }
2835 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2836 const MCPhysReg *I =
2837 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2838 if (I) {
2839 for (; *I; ++I) {
2840 if (ARM::GPRRegClass.contains(*I))
2841 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2842 else if (ARM::DPRRegClass.contains(*I))
2843 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2844 else
2845 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2845)
;
2846 }
2847 }
2848
2849 // Update chain and glue.
2850 RetOps[0] = Chain;
2851 if (Flag.getNode())
2852 RetOps.push_back(Flag);
2853
2854 // CPUs which aren't M-class use a special sequence to return from
2855 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2856 // though we use "subs pc, lr, #N").
2857 //
2858 // M-class CPUs actually use a normal return sequence with a special
2859 // (hardware-provided) value in LR, so the normal code path works.
2860 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2861 !Subtarget->isMClass()) {
2862 if (Subtarget->isThumb1Only())
2863 report_fatal_error("interrupt attribute is not supported in Thumb1");
2864 return LowerInterruptReturn(RetOps, dl, DAG);
2865 }
2866
2867 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2868}
2869
2870bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2871 if (N->getNumValues() != 1)
2872 return false;
2873 if (!N->hasNUsesOfValue(1, 0))
2874 return false;
2875
2876 SDValue TCChain = Chain;
2877 SDNode *Copy = *N->use_begin();
2878 if (Copy->getOpcode() == ISD::CopyToReg) {
2879 // If the copy has a glue operand, we conservatively assume it isn't safe to
2880 // perform a tail call.
2881 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2882 return false;
2883 TCChain = Copy->getOperand(0);
2884 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2885 SDNode *VMov = Copy;
2886 // f64 returned in a pair of GPRs.
2887 SmallPtrSet<SDNode*, 2> Copies;
2888 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2889 UI != UE; ++UI) {
2890 if (UI->getOpcode() != ISD::CopyToReg)
2891 return false;
2892 Copies.insert(*UI);
2893 }
2894 if (Copies.size() > 2)
2895 return false;
2896
2897 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2898 UI != UE; ++UI) {
2899 SDValue UseChain = UI->getOperand(0);
2900 if (Copies.count(UseChain.getNode()))
2901 // Second CopyToReg
2902 Copy = *UI;
2903 else {
2904 // We are at the top of this chain.
2905 // If the copy has a glue operand, we conservatively assume it
2906 // isn't safe to perform a tail call.
2907 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2908 return false;
2909 // First CopyToReg
2910 TCChain = UseChain;
2911 }
2912 }
2913 } else if (Copy->getOpcode() == ISD::BITCAST) {
2914 // f32 returned in a single GPR.
2915 if (!Copy->hasOneUse())
2916 return false;
2917 Copy = *Copy->use_begin();
2918 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2919 return false;
2920 // If the copy has a glue operand, we conservatively assume it isn't safe to
2921 // perform a tail call.
2922 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2923 return false;
2924 TCChain = Copy->getOperand(0);
2925 } else {
2926 return false;
2927 }
2928
2929 bool HasRet = false;
2930 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2931 UI != UE; ++UI) {
2932 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2933 UI->getOpcode() != ARMISD::INTRET_FLAG)
2934 return false;
2935 HasRet = true;
2936 }
2937
2938 if (!HasRet)
2939 return false;
2940
2941 Chain = TCChain;
2942 return true;
2943}
2944
2945bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2946 if (!Subtarget->supportsTailCall())
2947 return false;
2948
2949 auto Attr =
2950 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2951 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2952 return false;
2953
2954 return true;
2955}
2956
2957// Trying to write a 64 bit value so need to split into two 32 bit values first,
2958// and pass the lower and high parts through.
2959static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2960 SDLoc DL(Op);
2961 SDValue WriteValue = Op->getOperand(2);
2962
2963 // This function is only supposed to be called for i64 type argument.
2964 assert(WriteValue.getValueType() == MVT::i64((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2965, __PRETTY_FUNCTION__))
2965 && "LowerWRITE_REGISTER called for non-i64 type argument.")((WriteValue.getValueType() == MVT::i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? static_cast<void> (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 2965, __PRETTY_FUNCTION__))
;
2966
2967 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2968 DAG.getConstant(0, DL, MVT::i32));
2969 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2970 DAG.getConstant(1, DL, MVT::i32));
2971 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2972 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2973}
2974
2975// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2976// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2977// one of the above mentioned nodes. It has to be wrapped because otherwise
2978// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2979// be used to form addressing mode. These wrapped nodes will be selected
2980// into MOVi.
2981SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2982 SelectionDAG &DAG) const {
2983 EVT PtrVT = Op.getValueType();
2984 // FIXME there is no actual debug info here
2985 SDLoc dl(Op);
2986 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2987 SDValue Res;
2988
2989 // When generating execute-only code Constant Pools must be promoted to the
2990 // global data section. It's a bit ugly that we can't share them across basic
2991 // blocks, but this way we guarantee that execute-only behaves correct with
2992 // position-independent addressing modes.
2993 if (Subtarget->genExecuteOnly()) {
2994 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2995 auto T = const_cast<Type*>(CP->getType());
2996 auto C = const_cast<Constant*>(CP->getConstVal());
2997 auto M = const_cast<Module*>(DAG.getMachineFunction().
2998 getFunction().getParent());
2999 auto GV = new GlobalVariable(
3000 *M, T, /*isConstant=*/true, GlobalVariable::InternalLinkage, C,
3001 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
3002 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
3003 Twine(AFI->createPICLabelUId())
3004 );
3005 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
3006 dl, PtrVT);
3007 return LowerGlobalAddress(GA, DAG);
3008 }
3009
3010 if (CP->isMachineConstantPoolEntry())
3011 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
3012 CP->getAlignment());
3013 else
3014 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
3015 CP->getAlignment());
3016 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
3017}
3018
3019unsigned ARMTargetLowering::getJumpTableEncoding() const {
3020 return MachineJumpTableInfo::EK_Inline;
3021}
3022
3023SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
3024 SelectionDAG &DAG) const {
3025 MachineFunction &MF = DAG.getMachineFunction();
3026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3027 unsigned ARMPCLabelIndex = 0;
3028 SDLoc DL(Op);
3029 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3030 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3031 SDValue CPAddr;
3032 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
3033 if (!IsPositionIndependent) {
3034 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
3035 } else {
3036 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
3037 ARMPCLabelIndex = AFI->createPICLabelUId();
3038 ARMConstantPoolValue *CPV =
3039 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
3040 ARMCP::CPBlockAddress, PCAdj);
3041 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3042 }
3043 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
3044 SDValue Result = DAG.getLoad(
3045 PtrVT, DL, DAG.getEntryNode(), CPAddr,
3046 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3047 if (!IsPositionIndependent)
3048 return Result;
3049 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
3050 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
3051}
3052
3053/// Convert a TLS address reference into the correct sequence of loads
3054/// and calls to compute the variable's address for Darwin, and return an
3055/// SDValue containing the final node.
3056
3057/// Darwin only has one TLS scheme which must be capable of dealing with the
3058/// fully general situation, in the worst case. This means:
3059/// + "extern __thread" declaration.
3060/// + Defined in a possibly unknown dynamic library.
3061///
3062/// The general system is that each __thread variable has a [3 x i32] descriptor
3063/// which contains information used by the runtime to calculate the address. The
3064/// only part of this the compiler needs to know about is the first word, which
3065/// contains a function pointer that must be called with the address of the
3066/// entire descriptor in "r0".
3067///
3068/// Since this descriptor may be in a different unit, in general access must
3069/// proceed along the usual ARM rules. A common sequence to produce is:
3070///
3071/// movw rT1, :lower16:_var$non_lazy_ptr
3072/// movt rT1, :upper16:_var$non_lazy_ptr
3073/// ldr r0, [rT1]
3074/// ldr rT2, [r0]
3075/// blx rT2
3076/// [...address now in r0...]
3077SDValue
3078ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
3079 SelectionDAG &DAG) const {
3080 assert(Subtarget->isTargetDarwin() &&((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3081, __PRETTY_FUNCTION__))
3081 "This function expects a Darwin target")((Subtarget->isTargetDarwin() && "This function expects a Darwin target"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3081, __PRETTY_FUNCTION__))
;
3082 SDLoc DL(Op);
3083
3084 // First step is to get the address of the actua global symbol. This is where
3085 // the TLS descriptor lives.
3086 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
3087
3088 // The first entry in the descriptor is a function pointer that we must call
3089 // to obtain the address of the variable.
3090 SDValue Chain = DAG.getEntryNode();
3091 SDValue FuncTLVGet = DAG.getLoad(
3092 MVT::i32, DL, Chain, DescAddr,
3093 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
3094 /* Alignment = */ 4,
3095 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
3096 MachineMemOperand::MOInvariant);
3097 Chain = FuncTLVGet.getValue(1);
3098
3099 MachineFunction &F = DAG.getMachineFunction();
3100 MachineFrameInfo &MFI = F.getFrameInfo();
3101 MFI.setAdjustsStack(true);
3102
3103 // TLS calls preserve all registers except those that absolutely must be
3104 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
3105 // silly).
3106 auto TRI =
3107 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
3108 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
3109 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
3110
3111 // Finally, we can make the call. This is just a degenerate version of a
3112 // normal AArch64 call node: r0 takes the address of the descriptor, and
3113 // returns the address of the variable in this thread.
3114 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
3115 Chain =
3116 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3117 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
3118 DAG.getRegisterMask(Mask), Chain.getValue(1));
3119 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
3120}
3121
3122SDValue
3123ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
3124 SelectionDAG &DAG) const {
3125 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")((Subtarget->isTargetWindows() && "Windows specific TLS lowering"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3125, __PRETTY_FUNCTION__))
;
3126
3127 SDValue Chain = DAG.getEntryNode();
3128 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3129 SDLoc DL(Op);
3130
3131 // Load the current TEB (thread environment block)
3132 SDValue Ops[] = {Chain,
3133 DAG.getTargetConstant(Intrinsic::arm_mrc, DL, MVT::i32),
3134 DAG.getTargetConstant(15, DL, MVT::i32),
3135 DAG.getTargetConstant(0, DL, MVT::i32),
3136 DAG.getTargetConstant(13, DL, MVT::i32),
3137 DAG.getTargetConstant(0, DL, MVT::i32),
3138 DAG.getTargetConstant(2, DL, MVT::i32)};
3139 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
3140 DAG.getVTList(MVT::i32, MVT::Other), Ops);
3141
3142 SDValue TEB = CurrentTEB.getValue(0);
3143 Chain = CurrentTEB.getValue(1);
3144
3145 // Load the ThreadLocalStoragePointer from the TEB
3146 // A pointer to the TLS array is located at offset 0x2c from the TEB.
3147 SDValue TLSArray =
3148 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
3149 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
3150
3151 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
3152 // offset into the TLSArray.
3153
3154 // Load the TLS index from the C runtime
3155 SDValue TLSIndex =
3156 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
3157 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
3158 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
3159
3160 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
3161 DAG.getConstant(2, DL, MVT::i32));
3162 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
3163 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
3164 MachinePointerInfo());
3165
3166 // Get the offset of the start of the .tls section (section base)
3167 const auto *GA = cast<GlobalAddressSDNode>(Op);
3168 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
3169 SDValue Offset = DAG.getLoad(
3170 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
3171 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
3172 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3173
3174 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
3175}
3176
3177// Lower ISD::GlobalTLSAddress using the "general dynamic" model
3178SDValue
3179ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
3180 SelectionDAG &DAG) const {
3181 SDLoc dl(GA);
3182 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3183 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3184 MachineFunction &MF = DAG.getMachineFunction();
3185 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3186 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3187 ARMConstantPoolValue *CPV =
3188 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3189 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
3190 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3191 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
3192 Argument = DAG.getLoad(
3193 PtrVT, dl, DAG.getEntryNode(), Argument,
3194 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3195 SDValue Chain = Argument.getValue(1);
3196
3197 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3198 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
3199
3200 // call __tls_get_addr.
3201 ArgListTy Args;
3202 ArgListEntry Entry;
3203 Entry.Node = Argument;
3204 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
3205 Args.push_back(Entry);
3206
3207 // FIXME: is there useful debug info available here?
3208 TargetLowering::CallLoweringInfo CLI(DAG);
3209 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
3210 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
3211 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
3212
3213 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
3214 return CallResult.first;
3215}
3216
3217// Lower ISD::GlobalTLSAddress using the "initial exec" or
3218// "local exec" model.
3219SDValue
3220ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
3221 SelectionDAG &DAG,
3222 TLSModel::Model model) const {
3223 const GlobalValue *GV = GA->getGlobal();
3224 SDLoc dl(GA);
3225 SDValue Offset;
3226 SDValue Chain = DAG.getEntryNode();
3227 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3228 // Get the Thread Pointer
3229 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3230
3231 if (model == TLSModel::InitialExec) {
3232 MachineFunction &MF = DAG.getMachineFunction();
3233 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3234 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3235 // Initial exec model.
3236 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
3237 ARMConstantPoolValue *CPV =
3238 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
3239 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
3240 true);
3241 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3242 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3243 Offset = DAG.getLoad(
3244 PtrVT, dl, Chain, Offset,
3245 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3246 Chain = Offset.getValue(1);
3247
3248 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3249 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
3250
3251 Offset = DAG.getLoad(
3252 PtrVT, dl, Chain, Offset,
3253 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3254 } else {
3255 // local exec model
3256 assert(model == TLSModel::LocalExec)((model == TLSModel::LocalExec) ? static_cast<void> (0)
: __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3256, __PRETTY_FUNCTION__))
;
3257 ARMConstantPoolValue *CPV =
3258 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
3259 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3260 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
3261 Offset = DAG.getLoad(
3262 PtrVT, dl, Chain, Offset,
3263 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3264 }
3265
3266 // The address of the thread local variable is the add of the thread
3267 // pointer with the offset of the variable.
3268 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3269}
3270
3271SDValue
3272ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3273 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3274 if (DAG.getTarget().useEmulatedTLS())
3275 return LowerToTLSEmulatedModel(GA, DAG);
3276
3277 if (Subtarget->isTargetDarwin())
3278 return LowerGlobalTLSAddressDarwin(Op, DAG);
3279
3280 if (Subtarget->isTargetWindows())
3281 return LowerGlobalTLSAddressWindows(Op, DAG);
3282
3283 // TODO: implement the "local dynamic" model
3284 assert(Subtarget->isTargetELF() && "Only ELF implemented here")((Subtarget->isTargetELF() && "Only ELF implemented here"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3284, __PRETTY_FUNCTION__))
;
3285 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3286
3287 switch (model) {
3288 case TLSModel::GeneralDynamic:
3289 case TLSModel::LocalDynamic:
3290 return LowerToTLSGeneralDynamicModel(GA, DAG);
3291 case TLSModel::InitialExec:
3292 case TLSModel::LocalExec:
3293 return LowerToTLSExecModels(GA, DAG, model);
3294 }
3295 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3295)
;
3296}
3297
3298/// Return true if all users of V are within function F, looking through
3299/// ConstantExprs.
3300static bool allUsersAreInFunction(const Value *V, const Function *F) {
3301 SmallVector<const User*,4> Worklist;
3302 for (auto *U : V->users())
3303 Worklist.push_back(U);
3304 while (!Worklist.empty()) {
3305 auto *U = Worklist.pop_back_val();
3306 if (isa<ConstantExpr>(U)) {
3307 for (auto *UU : U->users())
3308 Worklist.push_back(UU);
3309 continue;
3310 }
3311
3312 auto *I = dyn_cast<Instruction>(U);
3313 if (!I || I->getParent()->getParent() != F)
3314 return false;
3315 }
3316 return true;
3317}
3318
3319static SDValue promoteToConstantPool(const ARMTargetLowering *TLI,
3320 const GlobalValue *GV, SelectionDAG &DAG,
3321 EVT PtrVT, const SDLoc &dl) {
3322 // If we're creating a pool entry for a constant global with unnamed address,
3323 // and the global is small enough, we can emit it inline into the constant pool
3324 // to save ourselves an indirection.
3325 //
3326 // This is a win if the constant is only used in one function (so it doesn't
3327 // need to be duplicated) or duplicating the constant wouldn't increase code
3328 // size (implying the constant is no larger than 4 bytes).
3329 const Function &F = DAG.getMachineFunction().getFunction();
3330
3331 // We rely on this decision to inline being idemopotent and unrelated to the
3332 // use-site. We know that if we inline a variable at one use site, we'll
3333 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3334 // doesn't know about this optimization, so bail out if it's enabled else
3335 // we could decide to inline here (and thus never emit the GV) but require
3336 // the GV from fast-isel generated code.
3337 if (!EnableConstpoolPromotion ||
3338 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3339 return SDValue();
3340
3341 auto *GVar = dyn_cast<GlobalVariable>(GV);
3342 if (!GVar || !GVar->hasInitializer() ||
3343 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3344 !GVar->hasLocalLinkage())
3345 return SDValue();
3346
3347 // If we inline a value that contains relocations, we move the relocations
3348 // from .data to .text. This is not allowed in position-independent code.
3349 auto *Init = GVar->getInitializer();
3350 if ((TLI->isPositionIndependent() || TLI->getSubtarget()->isROPI()) &&
3351 Init->needsRelocation())
3352 return SDValue();
3353
3354 // The constant islands pass can only really deal with alignment requests
3355 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3356 // any type wanting greater alignment requirements than 4 bytes. We also
3357 // can only promote constants that are multiples of 4 bytes in size or
3358 // are paddable to a multiple of 4. Currently we only try and pad constants
3359 // that are strings for simplicity.
3360 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3361 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3362 unsigned Align = DAG.getDataLayout().getPreferredAlignment(GVar);
3363 unsigned RequiredPadding = 4 - (Size % 4);
3364 bool PaddingPossible =
3365 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3366 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3367 Size == 0)
3368 return SDValue();
3369
3370 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3371 MachineFunction &MF = DAG.getMachineFunction();
3372 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3373
3374 // We can't bloat the constant pool too much, else the ConstantIslands pass
3375 // may fail to converge. If we haven't promoted this global yet (it may have
3376 // multiple uses), and promoting it would increase the constant pool size (Sz
3377 // > 4), ensure we have space to do so up to MaxTotal.
3378 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3379 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3380 ConstpoolPromotionMaxTotal)
3381 return SDValue();
3382
3383 // This is only valid if all users are in a single function; we can't clone
3384 // the constant in general. The LLVM IR unnamed_addr allows merging
3385 // constants, but not cloning them.
3386 //
3387 // We could potentially allow cloning if we could prove all uses of the
3388 // constant in the current function don't care about the address, like
3389 // printf format strings. But that isn't implemented for now.
3390 if (!allUsersAreInFunction(GVar, &F))
3391 return SDValue();
3392
3393 // We're going to inline this global. Pad it out if needed.
3394 if (RequiredPadding != 4) {
3395 StringRef S = CDAInit->getAsString();
3396
3397 SmallVector<uint8_t,16> V(S.size());
3398 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3399 while (RequiredPadding--)
3400 V.push_back(0);
3401 Init = ConstantDataArray::get(*DAG.getContext(), V);
3402 }
3403
3404 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3405 SDValue CPAddr =
3406 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3407 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3408 AFI->markGlobalAsPromotedToConstantPool(GVar);
3409 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3410 PaddedSize - 4);
3411 }
3412 ++NumConstpoolPromoted;
3413 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3414}
3415
3416bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3417 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3418 if (!(GV = GA->getBaseObject()))
3419 return false;
3420 if (const auto *V = dyn_cast<GlobalVariable>(GV))
3421 return V->isConstant();
3422 return isa<Function>(GV);
3423}
3424
3425SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3426 SelectionDAG &DAG) const {
3427 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3428 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3428)
;
3429 case Triple::COFF:
3430 return LowerGlobalAddressWindows(Op, DAG);
3431 case Triple::ELF:
3432 return LowerGlobalAddressELF(Op, DAG);
3433 case Triple::MachO:
3434 return LowerGlobalAddressDarwin(Op, DAG);
3435 }
3436}
3437
3438SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3439 SelectionDAG &DAG) const {
3440 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3441 SDLoc dl(Op);
3442 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3443 const TargetMachine &TM = getTargetMachine();
3444 bool IsRO = isReadOnly(GV);
3445
3446 // promoteToConstantPool only if not generating XO text section
3447 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3448 if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl))
3449 return V;
3450
3451 if (isPositionIndependent()) {
3452 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3453 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3454 UseGOT_PREL ? ARMII::MO_GOT : 0);
3455 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3456 if (UseGOT_PREL)
3457 Result =
3458 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3459 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3460 return Result;
3461 } else if (Subtarget->isROPI() && IsRO) {
3462 // PC-relative.
3463 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3464 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3465 return Result;
3466 } else if (Subtarget->isRWPI() && !IsRO) {
3467 // SB-relative.
3468 SDValue RelAddr;
3469 if (Subtarget->useMovt()) {
3470 ++NumMovwMovt;
3471 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3472 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3473 } else { // use literal pool for address constant
3474 ARMConstantPoolValue *CPV =
3475 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3476 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3477 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3478 RelAddr = DAG.getLoad(
3479 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3480 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3481 }
3482 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3483 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3484 return Result;
3485 }
3486
3487 // If we have T2 ops, we can materialize the address directly via movt/movw
3488 // pair. This is always cheaper.
3489 if (Subtarget->useMovt()) {
3490 ++NumMovwMovt;
3491 // FIXME: Once remat is capable of dealing with instructions with register
3492 // operands, expand this into two nodes.
3493 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3494 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3495 } else {
3496 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3497 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3498 return DAG.getLoad(
3499 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3500 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3501 }
3502}
3503
3504SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3505 SelectionDAG &DAG) const {
3506 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3507, __PRETTY_FUNCTION__))
3507 "ROPI/RWPI not currently supported for Darwin")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Darwin") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3507, __PRETTY_FUNCTION__))
;
3508 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3509 SDLoc dl(Op);
3510 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3511
3512 if (Subtarget->useMovt())
3513 ++NumMovwMovt;
3514
3515 // FIXME: Once remat is capable of dealing with instructions with register
3516 // operands, expand this into multiple nodes
3517 unsigned Wrapper =
3518 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3519
3520 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3521 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3522
3523 if (Subtarget->isGVIndirectSymbol(GV))
3524 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3525 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3526 return Result;
3527}
3528
3529SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3530 SelectionDAG &DAG) const {
3531 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")((Subtarget->isTargetWindows() && "non-Windows COFF is not supported"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3531, __PRETTY_FUNCTION__))
;
3532 assert(Subtarget->useMovt() &&((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3533, __PRETTY_FUNCTION__))
3533 "Windows on ARM expects to use movw/movt")((Subtarget->useMovt() && "Windows on ARM expects to use movw/movt"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->useMovt() && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3533, __PRETTY_FUNCTION__))
;
3534 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3535, __PRETTY_FUNCTION__))
3535 "ROPI/RWPI not currently supported for Windows")((!Subtarget->isROPI() && !Subtarget->isRWPI() &&
"ROPI/RWPI not currently supported for Windows") ? static_cast
<void> (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3535, __PRETTY_FUNCTION__))
;
3536
3537 const TargetMachine &TM = getTargetMachine();
3538 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3539 ARMII::TOF TargetFlags = ARMII::MO_NO_FLAG;
3540 if (GV->hasDLLImportStorageClass())
3541 TargetFlags = ARMII::MO_DLLIMPORT;
3542 else if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
3543 TargetFlags = ARMII::MO_COFFSTUB;
3544 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3545 SDValue Result;
3546 SDLoc DL(Op);
3547
3548 ++NumMovwMovt;
3549
3550 // FIXME: Once remat is capable of dealing with instructions with register
3551 // operands, expand this into two nodes.
3552 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3553 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*offset=*/0,
3554 TargetFlags));
3555 if (TargetFlags & (ARMII::MO_DLLIMPORT | ARMII::MO_COFFSTUB))
3556 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3557 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3558 return Result;
3559}
3560
3561SDValue
3562ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3563 SDLoc dl(Op);
3564 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3565 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3566 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3567 Op.getOperand(1), Val);
3568}
3569
3570SDValue
3571ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3572 SDLoc dl(Op);
3573 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3574 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3575}
3576
3577SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3578 SelectionDAG &DAG) const {
3579 SDLoc dl(Op);
3580 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3581 Op.getOperand(0));
3582}
3583
3584SDValue ARMTargetLowering::LowerINTRINSIC_VOID(
3585 SDValue Op, SelectionDAG &DAG, const ARMSubtarget *Subtarget) const {
3586 unsigned IntNo =
3587 cast<ConstantSDNode>(
3588 Op.getOperand(Op.getOperand(0).getValueType() == MVT::Other))
3589 ->getZExtValue();
3590 switch (IntNo) {
3591 default:
3592 return SDValue(); // Don't custom lower most intrinsics.
3593 case Intrinsic::arm_gnu_eabi_mcount: {
3594 MachineFunction &MF = DAG.getMachineFunction();
3595 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3596 SDLoc dl(Op);
3597 SDValue Chain = Op.getOperand(0);
3598 // call "\01__gnu_mcount_nc"
3599 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
3600 const uint32_t *Mask =
3601 ARI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
3602 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3602, __PRETTY_FUNCTION__))
;
3603 // Mark LR an implicit live-in.
3604 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3605 SDValue ReturnAddress =
3606 DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, PtrVT);
3607 std::vector<EVT> ResultTys = {MVT::Other, MVT::Glue};
3608 SDValue Callee =
3609 DAG.getTargetExternalSymbol("\01__gnu_mcount_nc", PtrVT, 0);
3610 SDValue RegisterMask = DAG.getRegisterMask(Mask);
3611 if (Subtarget->isThumb())
3612 return SDValue(
3613 DAG.getMachineNode(
3614 ARM::tBL_PUSHLR, dl, ResultTys,
3615 {ReturnAddress, DAG.getTargetConstant(ARMCC::AL, dl, PtrVT),
3616 DAG.getRegister(0, PtrVT), Callee, RegisterMask, Chain}),
3617 0);
3618 return SDValue(
3619 DAG.getMachineNode(ARM::BL_PUSHLR, dl, ResultTys,
3620 {ReturnAddress, Callee, RegisterMask, Chain}),
3621 0);
3622 }
3623 }
3624}
3625
3626SDValue
3627ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3628 const ARMSubtarget *Subtarget) const {
3629 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3630 SDLoc dl(Op);
3631 switch (IntNo) {
3632 default: return SDValue(); // Don't custom lower most intrinsics.
3633 case Intrinsic::thread_pointer: {
3634 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3635 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3636 }
3637 case Intrinsic::arm_cls: {
3638 const SDValue &Operand = Op.getOperand(1);
3639 const EVT VTy = Op.getValueType();
3640 SDValue SRA =
3641 DAG.getNode(ISD::SRA, dl, VTy, Operand, DAG.getConstant(31, dl, VTy));
3642 SDValue XOR = DAG.getNode(ISD::XOR, dl, VTy, SRA, Operand);
3643 SDValue SHL =
3644 DAG.getNode(ISD::SHL, dl, VTy, XOR, DAG.getConstant(1, dl, VTy));
3645 SDValue OR =
3646 DAG.getNode(ISD::OR, dl, VTy, SHL, DAG.getConstant(1, dl, VTy));
3647 SDValue Result = DAG.getNode(ISD::CTLZ, dl, VTy, OR);
3648 return Result;
3649 }
3650 case Intrinsic::arm_cls64: {
3651 // cls(x) = if cls(hi(x)) != 31 then cls(hi(x))
3652 // else 31 + clz(if hi(x) == 0 then lo(x) else not(lo(x)))
3653 const SDValue &Operand = Op.getOperand(1);
3654 const EVT VTy = Op.getValueType();
3655
3656 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3657 DAG.getConstant(1, dl, VTy));
3658 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VTy, Operand,
3659 DAG.getConstant(0, dl, VTy));
3660 SDValue Constant0 = DAG.getConstant(0, dl, VTy);
3661 SDValue Constant1 = DAG.getConstant(1, dl, VTy);
3662 SDValue Constant31 = DAG.getConstant(31, dl, VTy);
3663 SDValue SRAHi = DAG.getNode(ISD::SRA, dl, VTy, Hi, Constant31);
3664 SDValue XORHi = DAG.getNode(ISD::XOR, dl, VTy, SRAHi, Hi);
3665 SDValue SHLHi = DAG.getNode(ISD::SHL, dl, VTy, XORHi, Constant1);
3666 SDValue ORHi = DAG.getNode(ISD::OR, dl, VTy, SHLHi, Constant1);
3667 SDValue CLSHi = DAG.getNode(ISD::CTLZ, dl, VTy, ORHi);
3668 SDValue CheckLo =
3669 DAG.getSetCC(dl, MVT::i1, CLSHi, Constant31, ISD::CondCode::SETEQ);
3670 SDValue HiIsZero =
3671 DAG.getSetCC(dl, MVT::i1, Hi, Constant0, ISD::CondCode::SETEQ);
3672 SDValue AdjustedLo =
3673 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy));
3674 SDValue CLZAdjustedLo = DAG.getNode(ISD::CTLZ, dl, VTy, AdjustedLo);
3675 SDValue Result =
3676 DAG.getSelect(dl, VTy, CheckLo,
3677 DAG.getNode(ISD::ADD, dl, VTy, CLZAdjustedLo, Constant31), CLSHi);
3678 return Result;
3679 }
3680 case Intrinsic::eh_sjlj_lsda: {
3681 MachineFunction &MF = DAG.getMachineFunction();
3682 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3683 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3684 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3685 SDValue CPAddr;
3686 bool IsPositionIndependent = isPositionIndependent();
3687 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3688 ARMConstantPoolValue *CPV =
3689 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3690 ARMCP::CPLSDA, PCAdj);
3691 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3692 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3693 SDValue Result = DAG.getLoad(
3694 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3695 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3696
3697 if (IsPositionIndependent) {
3698 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3699 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3700 }
3701 return Result;
3702 }
3703 case Intrinsic::arm_neon_vabs:
3704 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3705 Op.getOperand(1));
3706 case Intrinsic::arm_neon_vmulls:
3707 case Intrinsic::arm_neon_vmullu: {
3708 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3709 ? ARMISD::VMULLs : ARMISD::VMULLu;
3710 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3711 Op.getOperand(1), Op.getOperand(2));
3712 }
3713 case Intrinsic::arm_neon_vminnm:
3714 case Intrinsic::arm_neon_vmaxnm: {
3715 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3716 ? ISD::FMINNUM : ISD::FMAXNUM;
3717 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3718 Op.getOperand(1), Op.getOperand(2));
3719 }
3720 case Intrinsic::arm_neon_vminu:
3721 case Intrinsic::arm_neon_vmaxu: {
3722 if (Op.getValueType().isFloatingPoint())
3723 return SDValue();
3724 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3725 ? ISD::UMIN : ISD::UMAX;
3726 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3727 Op.getOperand(1), Op.getOperand(2));
3728 }
3729 case Intrinsic::arm_neon_vmins:
3730 case Intrinsic::arm_neon_vmaxs: {
3731 // v{min,max}s is overloaded between signed integers and floats.
3732 if (!Op.getValueType().isFloatingPoint()) {
3733 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3734 ? ISD::SMIN : ISD::SMAX;
3735 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3736 Op.getOperand(1), Op.getOperand(2));
3737 }
3738 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3739 ? ISD::FMINIMUM : ISD::FMAXIMUM;
3740 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3741 Op.getOperand(1), Op.getOperand(2));
3742 }
3743 case Intrinsic::arm_neon_vtbl1:
3744 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3745 Op.getOperand(1), Op.getOperand(2));
3746 case Intrinsic::arm_neon_vtbl2:
3747 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3748 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3749 case Intrinsic::arm_mve_pred_i2v:
3750 case Intrinsic::arm_mve_pred_v2i:
3751 return DAG.getNode(ARMISD::PREDICATE_CAST, SDLoc(Op), Op.getValueType(),
3752 Op.getOperand(1));
3753 }
3754}
3755
3756static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3757 const ARMSubtarget *Subtarget) {
3758 SDLoc dl(Op);
3759 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3760 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3761 if (SSID == SyncScope::SingleThread)
3762 return Op;
3763
3764 if (!Subtarget->hasDataBarrier()) {
3765 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3766 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3767 // here.
3768 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3769, __PRETTY_FUNCTION__))
3769 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")((Subtarget->hasV6Ops() && !Subtarget->isThumb(
) && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? static_cast<void> (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3769, __PRETTY_FUNCTION__))
;
3770 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3771 DAG.getConstant(0, dl, MVT::i32));
3772 }
3773
3774 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3775 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3776 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3777 if (Subtarget->isMClass()) {
3778 // Only a full system barrier exists in the M-class architectures.
3779 Domain = ARM_MB::SY;
3780 } else if (Subtarget->preferISHSTBarriers() &&
3781 Ord == AtomicOrdering::Release) {
3782 // Swift happens to implement ISHST barriers in a way that's compatible with
3783 // Release semantics but weaker than ISH so we'd be fools not to use
3784 // it. Beware: other processors probably don't!
3785 Domain = ARM_MB::ISHST;
3786 }
3787
3788 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3789 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3790 DAG.getConstant(Domain, dl, MVT::i32));
3791}
3792
3793static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3794 const ARMSubtarget *Subtarget) {
3795 // ARM pre v5TE and Thumb1 does not have preload instructions.
3796 if (!(Subtarget->isThumb2() ||
3797 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3798 // Just preserve the chain.
3799 return Op.getOperand(0);
3800
3801 SDLoc dl(Op);
3802 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3803 if (!isRead &&
3804 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3805 // ARMv7 with MP extension has PLDW.
3806 return Op.getOperand(0);
3807
3808 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3809 if (Subtarget->isThumb()) {
3810 // Invert the bits.
3811 isRead = ~isRead & 1;
3812 isData = ~isData & 1;
3813 }
3814
3815 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3816 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3817 DAG.getConstant(isData, dl, MVT::i32));
3818}
3819
3820static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3821 MachineFunction &MF = DAG.getMachineFunction();
3822 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3823
3824 // vastart just stores the address of the VarArgsFrameIndex slot into the
3825 // memory location argument.
3826 SDLoc dl(Op);
3827 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3828 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3829 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3830 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3831 MachinePointerInfo(SV));
3832}
3833
3834SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3835 CCValAssign &NextVA,
3836 SDValue &Root,
3837 SelectionDAG &DAG,
3838 const SDLoc &dl) const {
3839 MachineFunction &MF = DAG.getMachineFunction();
3840 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3841
3842 const TargetRegisterClass *RC;
3843 if (AFI->isThumb1OnlyFunction())
3844 RC = &ARM::tGPRRegClass;
3845 else
3846 RC = &ARM::GPRRegClass;
3847
3848 // Transform the arguments stored in physical registers into virtual ones.
3849 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3850 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3851
3852 SDValue ArgValue2;
3853 if (NextVA.isMemLoc()) {
3854 MachineFrameInfo &MFI = MF.getFrameInfo();
3855 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3856
3857 // Create load node to retrieve arguments from the stack.
3858 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3859 ArgValue2 = DAG.getLoad(
3860 MVT::i32, dl, Root, FIN,
3861 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3862 } else {
3863 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3864 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3865 }
3866 if (!Subtarget->isLittle())
3867 std::swap (ArgValue, ArgValue2);
3868 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3869}
3870
3871// The remaining GPRs hold either the beginning of variable-argument
3872// data, or the beginning of an aggregate passed by value (usually
3873// byval). Either way, we allocate stack slots adjacent to the data
3874// provided by our caller, and store the unallocated registers there.
3875// If this is a variadic function, the va_list pointer will begin with
3876// these values; otherwise, this reassembles a (byval) structure that
3877// was split between registers and memory.
3878// Return: The frame index registers were stored into.
3879int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3880 const SDLoc &dl, SDValue &Chain,
3881 const Value *OrigArg,
3882 unsigned InRegsParamRecordIdx,
3883 int ArgOffset, unsigned ArgSize) const {
3884 // Currently, two use-cases possible:
3885 // Case #1. Non-var-args function, and we meet first byval parameter.
3886 // Setup first unallocated register as first byval register;
3887 // eat all remained registers
3888 // (these two actions are performed by HandleByVal method).
3889 // Then, here, we initialize stack frame with
3890 // "store-reg" instructions.
3891 // Case #2. Var-args function, that doesn't contain byval parameters.
3892 // The same: eat all remained unallocated registers,
3893 // initialize stack frame.
3894
3895 MachineFunction &MF = DAG.getMachineFunction();
3896 MachineFrameInfo &MFI = MF.getFrameInfo();
3897 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3898 unsigned RBegin, REnd;
3899 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3900 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3901 } else {
3902 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3903 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3904 REnd = ARM::R4;
3905 }
3906
3907 if (REnd != RBegin)
3908 ArgOffset = -4 * (ARM::R4 - RBegin);
3909
3910 auto PtrVT = getPointerTy(DAG.getDataLayout());
3911 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3912 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3913
3914 SmallVector<SDValue, 4> MemOps;
3915 const TargetRegisterClass *RC =
3916 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3917
3918 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3919 unsigned VReg = MF.addLiveIn(Reg, RC);
3920 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3921 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3922 MachinePointerInfo(OrigArg, 4 * i));
3923 MemOps.push_back(Store);
3924 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3925 }
3926
3927 if (!MemOps.empty())
3928 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3929 return FrameIndex;
3930}
3931
3932// Setup stack frame, the va_list pointer will start from.
3933void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3934 const SDLoc &dl, SDValue &Chain,
3935 unsigned ArgOffset,
3936 unsigned TotalArgRegsSaveSize,
3937 bool ForceMutable) const {
3938 MachineFunction &MF = DAG.getMachineFunction();
3939 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3940
3941 // Try to store any remaining integer argument regs
3942 // to their spots on the stack so that they may be loaded by dereferencing
3943 // the result of va_next.
3944 // If there is no regs to be stored, just point address after last
3945 // argument passed via stack.
3946 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3947 CCInfo.getInRegsParamsCount(),
3948 CCInfo.getNextStackOffset(),
3949 std::max(4U, TotalArgRegsSaveSize));
3950 AFI->setVarArgsFrameIndex(FrameIndex);
3951}
3952
3953SDValue ARMTargetLowering::LowerFormalArguments(
3954 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3955 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3956 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3957 MachineFunction &MF = DAG.getMachineFunction();
3958 MachineFrameInfo &MFI = MF.getFrameInfo();
3959
3960 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3961
3962 // Assign locations to all of the incoming arguments.
3963 SmallVector<CCValAssign, 16> ArgLocs;
3964 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3965 *DAG.getContext());
3966 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3967
3968 SmallVector<SDValue, 16> ArgValues;
3969 SDValue ArgValue;
3970 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3971 unsigned CurArgIdx = 0;
3972
3973 // Initially ArgRegsSaveSize is zero.
3974 // Then we increase this value each time we meet byval parameter.
3975 // We also increase this value in case of varargs function.
3976 AFI->setArgRegsSaveSize(0);
3977
3978 // Calculate the amount of stack space that we need to allocate to store
3979 // byval and variadic arguments that are passed in registers.
3980 // We need to know this before we allocate the first byval or variadic
3981 // argument, as they will be allocated a stack slot below the CFA (Canonical
3982 // Frame Address, the stack pointer at entry to the function).
3983 unsigned ArgRegBegin = ARM::R4;
3984 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3985 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3986 break;
3987
3988 CCValAssign &VA = ArgLocs[i];
3989 unsigned Index = VA.getValNo();
3990 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3991 if (!Flags.isByVal())
3992 continue;
3993
3994 assert(VA.isMemLoc() && "unexpected byval pointer in reg")((VA.isMemLoc() && "unexpected byval pointer in reg")
? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 3994, __PRETTY_FUNCTION__))
;
3995 unsigned RBegin, REnd;
3996 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3997 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3998
3999 CCInfo.nextInRegsParam();
4000 }
4001 CCInfo.rewindByValRegsInfo();
4002
4003 int lastInsIndex = -1;
4004 if (isVarArg && MFI.hasVAStart()) {
4005 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
4006 if (RegIdx != array_lengthof(GPRArgRegs))
4007 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
4008 }
4009
4010 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
4011 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
4012 auto PtrVT = getPointerTy(DAG.getDataLayout());
4013
4014 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
4015 CCValAssign &VA = ArgLocs[i];
4016 if (Ins[VA.getValNo()].isOrigArg()) {
4017 std::advance(CurOrigArg,
4018 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
4019 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
4020 }
4021 // Arguments stored in registers.
4022 if (VA.isRegLoc()) {
4023 EVT RegVT = VA.getLocVT();
4024
4025 if (VA.needsCustom()) {
4026 // f64 and vector types are split up into multiple registers or
4027 // combinations of registers and stack slots.
4028 if (VA.getLocVT() == MVT::v2f64) {
4029 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
4030 Chain, DAG, dl);
4031 VA = ArgLocs[++i]; // skip ahead to next loc
4032 SDValue ArgValue2;
4033 if (VA.isMemLoc()) {
4034 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
4035 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4036 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
4037 MachinePointerInfo::getFixedStack(
4038 DAG.getMachineFunction(), FI));
4039 } else {
4040 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
4041 Chain, DAG, dl);
4042 }
4043 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4044 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4045 ArgValue, ArgValue1,
4046 DAG.getIntPtrConstant(0, dl));
4047 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
4048 ArgValue, ArgValue2,
4049 DAG.getIntPtrConstant(1, dl));
4050 } else
4051 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
4052 } else {
4053 const TargetRegisterClass *RC;
4054
4055
4056 if (RegVT == MVT::f16)
4057 RC = &ARM::HPRRegClass;
4058 else if (RegVT == MVT::f32)
4059 RC = &ARM::SPRRegClass;
4060 else if (RegVT == MVT::f64 || RegVT == MVT::v4f16)
4061 RC = &ARM::DPRRegClass;
4062 else if (RegVT == MVT::v2f64 || RegVT == MVT::v8f16)
4063 RC = &ARM::QPRRegClass;
4064 else if (RegVT == MVT::i32)
4065 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
4066 : &ARM::GPRRegClass;
4067 else
4068 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4068)
;
4069
4070 // Transform the arguments in physical registers into virtual ones.
4071 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
4072 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
4073
4074 // If this value is passed in r0 and has the returned attribute (e.g.
4075 // C++ 'structors), record this fact for later use.
4076 if (VA.getLocReg() == ARM::R0 && Ins[VA.getValNo()].Flags.isReturned()) {
4077 AFI->setPreservesR0();
4078 }
4079 }
4080
4081 // If this is an 8 or 16-bit value, it is really passed promoted
4082 // to 32 bits. Insert an assert[sz]ext to capture this, then
4083 // truncate to the right size.
4084 switch (VA.getLocInfo()) {
4085 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4085)
;
4086 case CCValAssign::Full: break;
4087 case CCValAssign::BCvt:
4088 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
4089 break;
4090 case CCValAssign::SExt:
4091 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
4092 DAG.getValueType(VA.getValVT()));
4093 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4094 break;
4095 case CCValAssign::ZExt:
4096 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
4097 DAG.getValueType(VA.getValVT()));
4098 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
4099 break;
4100 }
4101
4102 InVals.push_back(ArgValue);
4103 } else { // VA.isRegLoc()
4104 // sanity check
4105 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4105, __PRETTY_FUNCTION__))
;
4106 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")((VA.getValVT() != MVT::i64 && "i64 should already be lowered"
) ? static_cast<void> (0) : __assert_fail ("VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4106, __PRETTY_FUNCTION__))
;
4107
4108 int index = VA.getValNo();
4109
4110 // Some Ins[] entries become multiple ArgLoc[] entries.
4111 // Process them only once.
4112 if (index != lastInsIndex)
4113 {
4114 ISD::ArgFlagsTy Flags = Ins[index].Flags;
4115 // FIXME: For now, all byval parameter objects are marked mutable.
4116 // This can be changed with more analysis.
4117 // In case of tail call optimization mark all arguments mutable.
4118 // Since they could be overwritten by lowering of arguments in case of
4119 // a tail call.
4120 if (Flags.isByVal()) {
4121 assert(Ins[index].isOrigArg() &&((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4122, __PRETTY_FUNCTION__))
4122 "Byval arguments cannot be implicit")((Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? static_cast<void> (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4122, __PRETTY_FUNCTION__))
;
4123 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
4124
4125 int FrameIndex = StoreByValRegs(
4126 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
4127 VA.getLocMemOffset(), Flags.getByValSize());
4128 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
4129 CCInfo.nextInRegsParam();
4130 } else {
4131 unsigned FIOffset = VA.getLocMemOffset();
4132 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
4133 FIOffset, true);
4134
4135 // Create load nodes to retrieve arguments from the stack.
4136 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
4137 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
4138 MachinePointerInfo::getFixedStack(
4139 DAG.getMachineFunction(), FI)));
4140 }
4141 lastInsIndex = index;
4142 }
4143 }
4144 }
4145
4146 // varargs
4147 if (isVarArg && MFI.hasVAStart())
4148 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
4149 CCInfo.getNextStackOffset(),
4150 TotalArgRegsSaveSize);
4151
4152 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
4153
4154 return Chain;
4155}
4156
4157/// isFloatingPointZero - Return true if this is +0.0.
4158static bool isFloatingPointZero(SDValue Op) {
4159 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3
Calling 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
18
Returning from 'dyn_cast<llvm::ConstantFPSDNode, llvm::SDValue>'
19
Assuming 'CFP' is null
20
Taking false branch
4160 return CFP->getValueAPF().isPosZero();
4161 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
4162 // Maybe this has already been legalized into the constant pool?
4163 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
21
Calling 'SDValue::getOperand'
4164 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
4165 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
4166 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
4167 return CFP->getValueAPF().isPosZero();
4168 }
4169 } else if (Op->getOpcode() == ISD::BITCAST &&
4170 Op->getValueType(0) == MVT::f64) {
4171 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
4172 // created by LowerConstantFP().
4173 SDValue BitcastOp = Op->getOperand(0);
4174 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
4175 isNullConstant(BitcastOp->getOperand(0)))
4176 return true;
4177 }
4178 return false;
4179}
4180
4181/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
4182/// the given operands.
4183SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
4184 SDValue &ARMcc, SelectionDAG &DAG,
4185 const SDLoc &dl) const {
4186 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
4187 unsigned C = RHSC->getZExtValue();
4188 if (!isLegalICmpImmediate((int32_t)C)) {
4189 // Constant does not fit, try adjusting it by one.
4190 switch (CC) {
4191 default: break;
4192 case ISD::SETLT:
4193 case ISD::SETGE:
4194 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
4195 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
4196 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4197 }
4198 break;
4199 case ISD::SETULT:
4200 case ISD::SETUGE:
4201 if (C != 0 && isLegalICmpImmediate(C-1)) {
4202 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
4203 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
4204 }
4205 break;
4206 case ISD::SETLE:
4207 case ISD::SETGT:
4208 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
4209 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
4210 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4211 }
4212 break;
4213 case ISD::SETULE:
4214 case ISD::SETUGT:
4215 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
4216 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
4217 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
4218 }
4219 break;
4220 }
4221 }
4222 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
4223 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
4224 // In ARM and Thumb-2, the compare instructions can shift their second
4225 // operand.
4226 CC = ISD::getSetCCSwappedOperands(CC);
4227 std::swap(LHS, RHS);
4228 }
4229
4230 // Thumb1 has very limited immediate modes, so turning an "and" into a
4231 // shift can save multiple instructions.
4232 //
4233 // If we have (x & C1), and C1 is an appropriate mask, we can transform it
4234 // into "((x << n) >> n)". But that isn't necessarily profitable on its
4235 // own. If it's the operand to an unsigned comparison with an immediate,
4236 // we can eliminate one of the shifts: we transform
4237 // "((x << n) >> n) == C2" to "(x << n) == (C2 << n)".
4238 //
4239 // We avoid transforming cases which aren't profitable due to encoding
4240 // details:
4241 //
4242 // 1. C2 fits into the immediate field of a cmp, and the transformed version
4243 // would not; in that case, we're essentially trading one immediate load for
4244 // another.
4245 // 2. C1 is 255 or 65535, so we can use uxtb or uxth.
4246 // 3. C2 is zero; we have other code for this special case.
4247 //
4248 // FIXME: Figure out profitability for Thumb2; we usually can't save an
4249 // instruction, since the AND is always one instruction anyway, but we could
4250 // use narrow instructions in some cases.
4251 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::AND &&
4252 LHS->hasOneUse() && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4253 LHS.getValueType() == MVT::i32 && isa<ConstantSDNode>(RHS) &&
4254 !isSignedIntSetCC(CC)) {
4255 unsigned Mask = cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue();
4256 auto *RHSC = cast<ConstantSDNode>(RHS.getNode());
4257 uint64_t RHSV = RHSC->getZExtValue();
4258 if (isMask_32(Mask) && (RHSV & ~Mask) == 0 && Mask != 255 && Mask != 65535) {
4259 unsigned ShiftBits = countLeadingZeros(Mask);
4260 if (RHSV && (RHSV > 255 || (RHSV << ShiftBits) <= 255)) {
4261 SDValue ShiftAmt = DAG.getConstant(ShiftBits, dl, MVT::i32);
4262 LHS = DAG.getNode(ISD::SHL, dl, MVT::i32, LHS.getOperand(0), ShiftAmt);
4263 RHS = DAG.getConstant(RHSV << ShiftBits, dl, MVT::i32);
4264 }
4265 }
4266 }
4267
4268 // The specific comparison "(x<<c) > 0x80000000U" can be optimized to a
4269 // single "lsls x, c+1". The shift sets the "C" and "Z" flags the same
4270 // way a cmp would.
4271 // FIXME: Add support for ARM/Thumb2; this would need isel patterns, and
4272 // some tweaks to the heuristics for the previous and->shift transform.
4273 // FIXME: Optimize cases where the LHS isn't a shift.
4274 if (Subtarget->isThumb1Only() && LHS->getOpcode() == ISD::SHL &&
4275 isa<ConstantSDNode>(RHS) &&
4276 cast<ConstantSDNode>(RHS)->getZExtValue() == 0x80000000U &&
4277 CC == ISD::SETUGT && isa<ConstantSDNode>(LHS.getOperand(1)) &&
4278 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() < 31) {
4279 unsigned ShiftAmt =
4280 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() + 1;
4281 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl,
4282 DAG.getVTList(MVT::i32, MVT::i32),
4283 LHS.getOperand(0),
4284 DAG.getConstant(ShiftAmt, dl, MVT::i32));
4285 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,
4286 Shift.getValue(1), SDValue());
4287 ARMcc = DAG.getConstant(ARMCC::HI, dl, MVT::i32);
4288 return Chain.getValue(1);
4289 }
4290
4291 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4292
4293 // If the RHS is a constant zero then the V (overflow) flag will never be
4294 // set. This can allow us to simplify GE to PL or LT to MI, which can be
4295 // simpler for other passes (like the peephole optimiser) to deal with.
4296 if (isNullConstant(RHS)) {
4297 switch (CondCode) {
4298 default: break;
4299 case ARMCC::GE:
4300 CondCode = ARMCC::PL;
4301 break;
4302 case ARMCC::LT:
4303 CondCode = ARMCC::MI;
4304 break;
4305 }
4306 }
4307
4308 ARMISD::NodeType CompareType;
4309 switch (CondCode) {
4310 default:
4311 CompareType = ARMISD::CMP;
4312 break;
4313 case ARMCC::EQ:
4314 case ARMCC::NE:
4315 // Uses only Z Flag
4316 CompareType = ARMISD::CMPZ;
4317 break;
4318 }
4319 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4320 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
4321}
4322
4323/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
4324SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
4325 SelectionDAG &DAG, const SDLoc &dl) const {
4326 assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64)((Subtarget->hasFP64() || RHS.getValueType() != MVT::f64) ?
static_cast<void> (0) : __assert_fail ("Subtarget->hasFP64() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4326, __PRETTY_FUNCTION__))
;
4327 SDValue Cmp;
4328 if (!isFloatingPointZero(RHS))
4329 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
4330 else
4331 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
4332 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
4333}
4334
4335/// duplicateCmp - Glue values can have only one use, so this function
4336/// duplicates a comparison node.
4337SDValue
4338ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
4339 unsigned Opc = Cmp.getOpcode();
4340 SDLoc DL(Cmp);
4341 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
4342 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4343
4344 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")((Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4344, __PRETTY_FUNCTION__))
;
4345 Cmp = Cmp.getOperand(0);
4346 Opc = Cmp.getOpcode();
4347 if (Opc == ARMISD::CMPFP)
4348 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4349 else {
4350 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")((Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? static_cast<void> (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4350, __PRETTY_FUNCTION__))
;
4351 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
4352 }
4353 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
4354}
4355
4356// This function returns three things: the arithmetic computation itself
4357// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
4358// comparison and the condition code define the case in which the arithmetic
4359// computation *does not* overflow.
4360std::pair<SDValue, SDValue>
4361ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
4362 SDValue &ARMcc) const {
4363 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")((Op.getValueType() == MVT::i32 && "Unsupported value type"
) ? static_cast<void> (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4363, __PRETTY_FUNCTION__))
;
4364
4365 SDValue Value, OverflowCmp;
4366 SDValue LHS = Op.getOperand(0);
4367 SDValue RHS = Op.getOperand(1);
4368 SDLoc dl(Op);
4369
4370 // FIXME: We are currently always generating CMPs because we don't support
4371 // generating CMN through the backend. This is not as good as the natural
4372 // CMP case because it causes a register dependency and cannot be folded
4373 // later.
4374
4375 switch (Op.getOpcode()) {
4376 default:
4377 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4377)
;
4378 case ISD::SADDO:
4379 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4380 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
4381 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4382 break;
4383 case ISD::UADDO:
4384 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4385 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
4386 // We do not use it in the USUBO case as Value may not be used.
4387 Value = DAG.getNode(ARMISD::ADDC, dl,
4388 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
4389 .getValue(0);
4390 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
4391 break;
4392 case ISD::SSUBO:
4393 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
4394 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4395 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4396 break;
4397 case ISD::USUBO:
4398 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
4399 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
4400 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
4401 break;
4402 case ISD::UMULO:
4403 // We generate a UMUL_LOHI and then check if the high word is 0.
4404 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4405 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
4406 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4407 LHS, RHS);
4408 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4409 DAG.getConstant(0, dl, MVT::i32));
4410 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4411 break;
4412 case ISD::SMULO:
4413 // We generate a SMUL_LOHI and then check if all the bits of the high word
4414 // are the same as the sign bit of the low word.
4415 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4416 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4417 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4418 LHS, RHS);
4419 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4420 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4421 Value.getValue(0),
4422 DAG.getConstant(31, dl, MVT::i32)));
4423 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4424 break;
4425 } // switch (...)
4426
4427 return std::make_pair(Value, OverflowCmp);
4428}
4429
4430SDValue
4431ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4432 // Let legalize expand this if it isn't a legal type yet.
4433 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4434 return SDValue();
4435
4436 SDValue Value, OverflowCmp;
4437 SDValue ARMcc;
4438 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4439 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4440 SDLoc dl(Op);
4441 // We use 0 and 1 as false and true values.
4442 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4443 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4444 EVT VT = Op.getValueType();
4445
4446 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4447 ARMcc, CCR, OverflowCmp);
4448
4449 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4450 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4451}
4452
4453static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4454 SelectionDAG &DAG) {
4455 SDLoc DL(BoolCarry);
4456 EVT CarryVT = BoolCarry.getValueType();
4457
4458 // This converts the boolean value carry into the carry flag by doing
4459 // ARMISD::SUBC Carry, 1
4460 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL,
4461 DAG.getVTList(CarryVT, MVT::i32),
4462 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4463 return Carry.getValue(1);
4464}
4465
4466static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4467 SelectionDAG &DAG) {
4468 SDLoc DL(Flags);
4469
4470 // Now convert the carry flag into a boolean carry. We do this
4471 // using ARMISD:ADDE 0, 0, Carry
4472 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4473 DAG.getConstant(0, DL, MVT::i32),
4474 DAG.getConstant(0, DL, MVT::i32), Flags);
4475}
4476
4477SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4478 SelectionDAG &DAG) const {
4479 // Let legalize expand this if it isn't a legal type yet.
4480 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4481 return SDValue();
4482
4483 SDValue LHS = Op.getOperand(0);
4484 SDValue RHS = Op.getOperand(1);
4485 SDLoc dl(Op);
4486
4487 EVT VT = Op.getValueType();
4488 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4489 SDValue Value;
4490 SDValue Overflow;
4491 switch (Op.getOpcode()) {
4492 default:
4493 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4493)
;
4494 case ISD::UADDO:
4495 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4496 // Convert the carry flag into a boolean value.
4497 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4498 break;
4499 case ISD::USUBO: {
4500 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4501 // Convert the carry flag into a boolean value.
4502 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4503 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4504 // value. So compute 1 - C.
4505 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4506 DAG.getConstant(1, dl, MVT::i32), Overflow);
4507 break;
4508 }
4509 }
4510
4511 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4512}
4513
4514static SDValue LowerSADDSUBSAT(SDValue Op, SelectionDAG &DAG,
4515 const ARMSubtarget *Subtarget) {
4516 EVT VT = Op.getValueType();
4517 if (!Subtarget->hasDSP())
4518 return SDValue();
4519 if (!VT.isSimple())
4520 return SDValue();
4521
4522 unsigned NewOpcode;
4523 bool IsAdd = Op->getOpcode() == ISD::SADDSAT;
4524 switch (VT.getSimpleVT().SimpleTy) {
4525 default:
4526 return SDValue();
4527 case MVT::i8:
4528 NewOpcode = IsAdd ? ARMISD::QADD8b : ARMISD::QSUB8b;
4529 break;
4530 case MVT::i16:
4531 NewOpcode = IsAdd ? ARMISD::QADD16b : ARMISD::QSUB16b;
4532 break;
4533 }
4534
4535 SDLoc dl(Op);
4536 SDValue Add =
4537 DAG.getNode(NewOpcode, dl, MVT::i32,
4538 DAG.getSExtOrTrunc(Op->getOperand(0), dl, MVT::i32),
4539 DAG.getSExtOrTrunc(Op->getOperand(1), dl, MVT::i32));
4540 return DAG.getNode(ISD::TRUNCATE, dl, VT, Add);
4541}
4542
4543SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4544 SDValue Cond = Op.getOperand(0);
4545 SDValue SelectTrue = Op.getOperand(1);
4546 SDValue SelectFalse = Op.getOperand(2);
4547 SDLoc dl(Op);
4548 unsigned Opc = Cond.getOpcode();
4549
4550 if (Cond.getResNo() == 1 &&
4551 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4552 Opc == ISD::USUBO)) {
4553 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4554 return SDValue();
4555
4556 SDValue Value, OverflowCmp;
4557 SDValue ARMcc;
4558 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4559 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4560 EVT VT = Op.getValueType();
4561
4562 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4563 OverflowCmp, DAG);
4564 }
4565
4566 // Convert:
4567 //
4568 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4569 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4570 //
4571 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
4572 const ConstantSDNode *CMOVTrue =
4573 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4574 const ConstantSDNode *CMOVFalse =
4575 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4576
4577 if (CMOVTrue && CMOVFalse) {
4578 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4579 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4580
4581 SDValue True;
4582 SDValue False;
4583 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
4584 True = SelectTrue;
4585 False = SelectFalse;
4586 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4587 True = SelectFalse;
4588 False = SelectTrue;
4589 }
4590
4591 if (True.getNode() && False.getNode()) {
4592 EVT VT = Op.getValueType();
4593 SDValue ARMcc = Cond.getOperand(2);
4594 SDValue CCR = Cond.getOperand(3);
4595 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4596 assert(True.getValueType() == VT)((True.getValueType() == VT) ? static_cast<void> (0) : __assert_fail
("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 4596, __PRETTY_FUNCTION__))
;
4597 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4598 }
4599 }
4600 }
4601
4602 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4603 // undefined bits before doing a full-word comparison with zero.
4604 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4605 DAG.getConstant(1, dl, Cond.getValueType()));
4606
4607 return DAG.getSelectCC(dl, Cond,
4608 DAG.getConstant(0, dl, Cond.getValueType()),
4609 SelectTrue, SelectFalse, ISD::SETNE);
4610}
4611
4612static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4613 bool &swpCmpOps, bool &swpVselOps) {
4614 // Start by selecting the GE condition code for opcodes that return true for
4615 // 'equality'
4616 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4617 CC == ISD::SETULE || CC == ISD::SETGE || CC == ISD::SETLE)
4618 CondCode = ARMCC::GE;
4619
4620 // and GT for opcodes that return false for 'equality'.
4621 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4622 CC == ISD::SETULT || CC == ISD::SETGT || CC == ISD::SETLT)
4623 CondCode = ARMCC::GT;
4624
4625 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4626 // to swap the compare operands.
4627 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4628 CC == ISD::SETULT || CC == ISD::SETLE || CC == ISD::SETLT)
4629 swpCmpOps = true;
4630
4631 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4632 // If we have an unordered opcode, we need to swap the operands to the VSEL
4633 // instruction (effectively negating the condition).
4634 //
4635 // This also has the effect of swapping which one of 'less' or 'greater'
4636 // returns true, so we also swap the compare operands. It also switches
4637 // whether we return true for 'equality', so we compensate by picking the
4638 // opposite condition code to our original choice.
4639 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4640 CC == ISD::SETUGT) {
4641 swpCmpOps = !swpCmpOps;
4642 swpVselOps = !swpVselOps;
4643 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4644 }
4645
4646 // 'ordered' is 'anything but unordered', so use the VS condition code and
4647 // swap the VSEL operands.
4648 if (CC == ISD::SETO) {
4649 CondCode = ARMCC::VS;
4650 swpVselOps = true;
4651 }
4652
4653 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4654 // code and swap the VSEL operands. Also do this if we don't care about the
4655 // unordered case.
4656 if (CC == ISD::SETUNE || CC == ISD::SETNE) {
4657 CondCode = ARMCC::EQ;
4658 swpVselOps = true;
4659 }
4660}
4661
4662SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4663 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4664 SDValue Cmp, SelectionDAG &DAG) const {
4665 if (!Subtarget->hasFP64() && VT == MVT::f64) {
4666 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4667 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4668 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4669 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4670
4671 SDValue TrueLow = TrueVal.getValue(0);
4672 SDValue TrueHigh = TrueVal.getValue(1);
4673 SDValue FalseLow = FalseVal.getValue(0);
4674 SDValue FalseHigh = FalseVal.getValue(1);
4675
4676 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4677 ARMcc, CCR, Cmp);
4678 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4679 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4680
4681 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4682 } else {
4683 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4684 Cmp);
4685 }
4686}
4687
4688static bool isGTorGE(ISD::CondCode CC) {
4689 return CC == ISD::SETGT || CC == ISD::SETGE;
4690}
4691
4692static bool isLTorLE(ISD::CondCode CC) {
4693 return CC == ISD::SETLT || CC == ISD::SETLE;
4694}
4695
4696// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4697// All of these conditions (and their <= and >= counterparts) will do:
4698// x < k ? k : x
4699// x > k ? x : k
4700// k < x ? x : k
4701// k > x ? k : x
4702static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4703 const SDValue TrueVal, const SDValue FalseVal,
4704 const ISD::CondCode CC, const SDValue K) {
4705 return (isGTorGE(CC) &&
4706 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4707 (isLTorLE(CC) &&
4708 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4709}
4710
4711// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4712static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4713 const SDValue TrueVal, const SDValue FalseVal,
4714 const ISD::CondCode CC, const SDValue K) {
4715 return (isGTorGE(CC) &&
4716 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4717 (isLTorLE(CC) &&
4718 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4719}
4720
4721// Check if two chained conditionals could be converted into SSAT or USAT.
4722//
4723// SSAT can replace a set of two conditional selectors that bound a number to an
4724// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4725//
4726// x < -k ? -k : (x > k ? k : x)
4727// x < -k ? -k : (x < k ? x : k)
4728// x > -k ? (x > k ? k : x) : -k
4729// x < k ? (x < -k ? -k : x) : k
4730// etc.
4731//
4732// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4733// a power of 2.
4734//
4735// It returns true if the conversion can be done, false otherwise.
4736// Additionally, the variable is returned in parameter V, the constant in K and
4737// usat is set to true if the conditional represents an unsigned saturation
4738static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4739 uint64_t &K, bool &usat) {
4740 SDValue LHS1 = Op.getOperand(0);
4741 SDValue RHS1 = Op.getOperand(1);
4742 SDValue TrueVal1 = Op.getOperand(2);
4743 SDValue FalseVal1 = Op.getOperand(3);
4744 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4745
4746 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4747 if (Op2.getOpcode() != ISD::SELECT_CC)
4748 return false;
4749
4750 SDValue LHS2 = Op2.getOperand(0);
4751 SDValue RHS2 = Op2.getOperand(1);
4752 SDValue TrueVal2 = Op2.getOperand(2);
4753 SDValue FalseVal2 = Op2.getOperand(3);
4754 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4755
4756 // Find out which are the constants and which are the variables
4757 // in each conditional
4758 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4759 ? &RHS1
4760 : nullptr;
4761 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4762 ? &RHS2
4763 : nullptr;
4764 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4765 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4766 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4767 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4768
4769 // We must detect cases where the original operations worked with 16- or
4770 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4771 // must work with sign-extended values but the select operations return
4772 // the original non-extended value.
4773 SDValue V2TmpReg = V2Tmp;
4774 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4775 V2TmpReg = V2Tmp->getOperand(0);
4776
4777 // Check that the registers and the constants have the correct values
4778 // in both conditionals
4779 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4780 V2TmpReg != V2)
4781 return false;
4782
4783 // Figure out which conditional is saturating the lower/upper bound.
4784 const SDValue *LowerCheckOp =
4785 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4786 ? &Op
4787 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4788 ? &Op2
4789 : nullptr;
4790 const SDValue *UpperCheckOp =
4791 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4792 ? &Op
4793 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4794 ? &Op2
4795 : nullptr;
4796
4797 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4798 return false;
4799
4800 // Check that the constant in the lower-bound check is
4801 // the opposite of the constant in the upper-bound check
4802 // in 1's complement.
4803 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4804 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4805 int64_t PosVal = std::max(Val1, Val2);
4806 int64_t NegVal = std::min(Val1, Val2);
4807
4808 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4809 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4810 isPowerOf2_64(PosVal + 1)) {
4811
4812 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4813 if (Val1 == ~Val2)
4814 usat = false;
4815 else if (NegVal == 0)
4816 usat = true;
4817 else
4818 return false;
4819
4820 V = V2;
4821 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4822
4823 return true;
4824 }
4825
4826 return false;
4827}
4828
4829// Check if a condition of the type x < k ? k : x can be converted into a
4830// bit operation instead of conditional moves.
4831// Currently this is allowed given:
4832// - The conditions and values match up
4833// - k is 0 or -1 (all ones)
4834// This function will not check the last condition, thats up to the caller
4835// It returns true if the transformation can be made, and in such case
4836// returns x in V, and k in SatK.
4837static bool isLowerSaturatingConditional(const SDValue &Op, SDValue &V,
4838 SDValue &SatK)
4839{
4840 SDValue LHS = Op.getOperand(0);
4841 SDValue RHS = Op.getOperand(1);
4842 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4843 SDValue TrueVal = Op.getOperand(2);
4844 SDValue FalseVal = Op.getOperand(3);
4845
4846 SDValue *K = isa<ConstantSDNode>(LHS) ? &LHS : isa<ConstantSDNode>(RHS)
4847 ? &RHS
4848 : nullptr;
4849
4850 // No constant operation in comparison, early out
4851 if (!K)
4852 return false;
4853
4854 SDValue KTmp = isa<ConstantSDNode>(TrueVal) ? TrueVal : FalseVal;
4855 V = (KTmp == TrueVal) ? FalseVal : TrueVal;
4856 SDValue VTmp = (K && *K == LHS) ? RHS : LHS;
4857
4858 // If the constant on left and right side, or variable on left and right,
4859 // does not match, early out
4860 if (*K != KTmp || V != VTmp)
4861 return false;
4862
4863 if (isLowerSaturate(LHS, RHS, TrueVal, FalseVal, CC, *K)) {
4864 SatK = *K;
4865 return true;
4866 }
4867
4868 return false;
4869}
4870
4871bool ARMTargetLowering::isUnsupportedFloatingType(EVT VT) const {
4872 if (VT == MVT::f32)
4873 return !Subtarget->hasVFP2Base();
4874 if (VT == MVT::f64)
4875 return !Subtarget->hasFP64();
4876 if (VT == MVT::f16)
4877 return !Subtarget->hasFullFP16();
4878 return false;
4879}
4880
4881SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4882 EVT VT = Op.getValueType();
4883 SDLoc dl(Op);
4884
4885 // Try to convert two saturating conditional selects into a single SSAT
4886 SDValue SatValue;
4887 uint64_t SatConstant;
4888 bool SatUSat;
4889 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4890 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4891 if (SatUSat)
4892 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4893 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4894 else
4895 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4896 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4897 }
4898
4899 // Try to convert expressions of the form x < k ? k : x (and similar forms)
4900 // into more efficient bit operations, which is possible when k is 0 or -1
4901 // On ARM and Thumb-2 which have flexible operand 2 this will result in
4902 // single instructions. On Thumb the shift and the bit operation will be two
4903 // instructions.
4904 // Only allow this transformation on full-width (32-bit) operations
4905 SDValue LowerSatConstant;
4906 if (VT == MVT::i32 &&
4907 isLowerSaturatingConditional(Op, SatValue, LowerSatConstant)) {
4908 SDValue ShiftV = DAG.getNode(ISD::SRA, dl, VT, SatValue,
4909 DAG.getConstant(31, dl, VT));
4910 if (isNullConstant(LowerSatConstant)) {
4911 SDValue NotShiftV = DAG.getNode(ISD::XOR, dl, VT, ShiftV,
4912 DAG.getAllOnesConstant(dl, VT));
4913 return DAG.getNode(ISD::AND, dl, VT, SatValue, NotShiftV);
4914 } else if (isAllOnesConstant(LowerSatConstant))
4915 return DAG.getNode(ISD::OR, dl, VT, SatValue, ShiftV);
4916 }
4917
4918 SDValue LHS = Op.getOperand(0);
4919 SDValue RHS = Op.getOperand(1);
4920 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4921 SDValue TrueVal = Op.getOperand(2);
4922 SDValue FalseVal = Op.getOperand(3);
4923 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FalseVal);
4924 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TrueVal);
4925
4926 if (Subtarget->hasV8_1MMainlineOps() && CFVal && CTVal &&
4927 LHS.getValueType() == MVT::i32 && RHS.getValueType() == MVT::i32) {
4928 unsigned TVal = CTVal->getZExtValue();
4929 unsigned FVal = CFVal->getZExtValue();
4930 unsigned Opcode = 0;
4931
4932 if (TVal == ~FVal) {
4933 Opcode = ARMISD::CSINV;
4934 } else if (TVal == ~FVal + 1) {
4935 Opcode = ARMISD::CSNEG;
4936 } else if (TVal + 1 == FVal) {
4937 Opcode = ARMISD::CSINC;
4938 } else if (TVal == FVal + 1) {
4939 Opcode = ARMISD::CSINC;
4940 std::swap(TrueVal, FalseVal);
4941 std::swap(TVal, FVal);
4942 CC = ISD::getSetCCInverse(CC, true);
4943 }
4944
4945 if (Opcode) {
4946 // If one of the constants is cheaper than another, materialise the
4947 // cheaper one and let the csel generate the other.
4948 if (Opcode != ARMISD::CSINC &&
4949 HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) {
4950 std::swap(TrueVal, FalseVal);
4951 std::swap(TVal, FVal);
4952 CC = ISD::getSetCCInverse(CC, true);
4953 }
4954
4955 // Attempt to use ZR checking TVal is 0, possibly inverting the condition
4956 // to get there. CSINC not is invertable like the other two (~(~a) == a,
4957 // -(-a) == a, but (a+1)+1 != a).
4958 if (FVal == 0 && Opcode != ARMISD::CSINC) {
4959 std::swap(TrueVal, FalseVal);
4960 std::swap(TVal, FVal);
4961 CC = ISD::getSetCCInverse(CC, true);
4962 }
4963 if (TVal == 0)
4964 TrueVal = DAG.getRegister(ARM::ZR, MVT::i32);
4965
4966 // Drops F's value because we can get it by inverting/negating TVal.
4967 FalseVal = TrueVal;
4968
4969 SDValue ARMcc;
4970 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4971 EVT VT = TrueVal.getValueType();
4972 return DAG.getNode(Opcode, dl, VT, TrueVal, FalseVal, ARMcc, Cmp);
4973 }
4974 }
4975
4976 if (isUnsupportedFloatingType(LHS.getValueType())) {
4977 DAG.getTargetLoweringInfo().softenSetCCOperands(
4978 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
4979
4980 // If softenSetCCOperands only returned one value, we should compare it to
4981 // zero.
4982 if (!RHS.getNode()) {
4983 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4984 CC = ISD::SETNE;
4985 }
4986 }
4987
4988 if (LHS.getValueType() == MVT::i32) {
4989 // Try to generate VSEL on ARMv8.
4990 // The VSEL instruction can't use all the usual ARM condition
4991 // codes: it only has two bits to select the condition code, so it's
4992 // constrained to use only GE, GT, VS and EQ.
4993 //
4994 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4995 // swap the operands of the previous compare instruction (effectively
4996 // inverting the compare condition, swapping 'less' and 'greater') and
4997 // sometimes need to swap the operands to the VSEL (which inverts the
4998 // condition in the sense of firing whenever the previous condition didn't)
4999 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5000 TrueVal.getValueType() == MVT::f32 ||
5001 TrueVal.getValueType() == MVT::f64)) {
5002 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5003 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
5004 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
5005 CC = ISD::getSetCCInverse(CC, true);
5006 std::swap(TrueVal, FalseVal);
5007 }
5008 }
5009
5010 SDValue ARMcc;
5011 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5012 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5013 // Choose GE over PL, which vsel does now support
5014 if (cast<ConstantSDNode>(ARMcc)->getZExtValue() == ARMCC::PL)
5015 ARMcc = DAG.getConstant(ARMCC::GE, dl, MVT::i32);
5016 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5017 }
5018
5019 ARMCC::CondCodes CondCode, CondCode2;
5020 FPCCToARMCC(CC, CondCode, CondCode2);
5021
5022 // Normalize the fp compare. If RHS is zero we prefer to keep it there so we
5023 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5024 // must use VSEL (limited condition codes), due to not having conditional f16
5025 // moves.
5026 if (Subtarget->hasFPARMv8Base() &&
5027 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5028 (TrueVal.getValueType() == MVT::f16 ||
5029 TrueVal.getValueType() == MVT::f32 ||
5030 TrueVal.getValueType() == MVT::f64)) {
5031 bool swpCmpOps = false;
5032 bool swpVselOps = false;
5033 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
5034
5035 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
5036 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
5037 if (swpCmpOps)
5038 std::swap(LHS, RHS);
5039 if (swpVselOps)
5040 std::swap(TrueVal, FalseVal);
5041 }
5042 }
5043
5044 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5045 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5046 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5047 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
5048 if (CondCode2 != ARMCC::AL) {
5049 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
5050 // FIXME: Needs another CMP because flag can have but one use.
5051 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
5052 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
5053 }
5054 return Result;
5055}
5056
5057/// canChangeToInt - Given the fp compare operand, return true if it is suitable
5058/// to morph to an integer compare sequence.
5059static bool canChangeToInt(SDValue Op, bool &SeenZero,
5060 const ARMSubtarget *Subtarget) {
5061 SDNode *N = Op.getNode();
5062 if (!N->hasOneUse())
5063 // Otherwise it requires moving the value from fp to integer registers.
5064 return false;
5065 if (!N->getNumValues())
5066 return false;
5067 EVT VT = Op.getValueType();
5068 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
5069 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
5070 // vmrs are very slow, e.g. cortex-a8.
5071 return false;
5072
5073 if (isFloatingPointZero(Op)) {
5074 SeenZero = true;
5075 return true;
5076 }
5077 return ISD::isNormalLoad(N);
5078}
5079
5080static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
5081 if (isFloatingPointZero(Op))
1
Value assigned to 'Op.Node'
2
Calling 'isFloatingPointZero'
5082 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
5083
5084 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
5085 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
5086 Ld->getPointerInfo(), Ld->getAlignment(),
5087 Ld->getMemOperand()->getFlags());
5088
5089 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5089)
;
5090}
5091
5092static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
5093 SDValue &RetVal1, SDValue &RetVal2) {
5094 SDLoc dl(Op);
5095
5096 if (isFloatingPointZero(Op)) {
5097 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
5098 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
5099 return;
5100 }
5101
5102 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
5103 SDValue Ptr = Ld->getBasePtr();
5104 RetVal1 =
5105 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
5106 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
5107
5108 EVT PtrType = Ptr.getValueType();
5109 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
5110 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
5111 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
5112 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
5113 Ld->getPointerInfo().getWithOffset(4), NewAlign,
5114 Ld->getMemOperand()->getFlags());
5115 return;
5116 }
5117
5118 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5118)
;
5119}
5120
5121/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
5122/// f32 and even f64 comparisons to integer ones.
5123SDValue
5124ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
5125 SDValue Chain = Op.getOperand(0);
5126 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5127 SDValue LHS = Op.getOperand(2);
5128 SDValue RHS = Op.getOperand(3);
5129 SDValue Dest = Op.getOperand(4);
5130 SDLoc dl(Op);
5131
5132 bool LHSSeenZero = false;
5133 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
5134 bool RHSSeenZero = false;
5135 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
5136 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
5137 // If unsafe fp math optimization is enabled and there are no other uses of
5138 // the CMP operands, and the condition code is EQ or NE, we can optimize it
5139 // to an integer comparison.
5140 if (CC == ISD::SETOEQ)
5141 CC = ISD::SETEQ;
5142 else if (CC == ISD::SETUNE)
5143 CC = ISD::SETNE;
5144
5145 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5146 SDValue ARMcc;
5147 if (LHS.getValueType() == MVT::f32) {
5148 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5149 bitcastf32Toi32(LHS, DAG), Mask);
5150 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
5151 bitcastf32Toi32(RHS, DAG), Mask);
5152 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5153 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5154 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5155 Chain, Dest, ARMcc, CCR, Cmp);
5156 }
5157
5158 SDValue LHS1, LHS2;
5159 SDValue RHS1, RHS2;
5160 expandf64Toi32(LHS, DAG, LHS1, LHS2);
5161 expandf64Toi32(RHS, DAG, RHS1, RHS2);
5162 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
5163 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
5164 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
5165 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5166 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5167 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
5168 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
5169 }
5170
5171 return SDValue();
5172}
5173
5174SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
5175 SDValue Chain = Op.getOperand(0);
5176 SDValue Cond = Op.getOperand(1);
5177 SDValue Dest = Op.getOperand(2);
5178 SDLoc dl(Op);
5179
5180 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5181 // instruction.
5182 unsigned Opc = Cond.getOpcode();
5183 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5184 !Subtarget->isThumb1Only();
5185 if (Cond.getResNo() == 1 &&
5186 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5187 Opc == ISD::USUBO || OptimizeMul)) {
5188 // Only lower legal XALUO ops.
5189 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
5190 return SDValue();
5191
5192 // The actual operation with overflow check.
5193 SDValue Value, OverflowCmp;
5194 SDValue ARMcc;
5195 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
5196
5197 // Reverse the condition code.
5198 ARMCC::CondCodes CondCode =
5199 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5200 CondCode = ARMCC::getOppositeCondition(CondCode);
5201 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5202 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5203
5204 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5205 OverflowCmp);
5206 }
5207
5208 return SDValue();
5209}
5210
5211SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
5212 SDValue Chain = Op.getOperand(0);
5213 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
5214 SDValue LHS = Op.getOperand(2);
5215 SDValue RHS = Op.getOperand(3);
5216 SDValue Dest = Op.getOperand(4);
5217 SDLoc dl(Op);
5218
5219 if (isUnsupportedFloatingType(LHS.getValueType())) {
5220 DAG.getTargetLoweringInfo().softenSetCCOperands(
5221 DAG, LHS.getValueType(), LHS, RHS, CC, dl, LHS, RHS);
5222
5223 // If softenSetCCOperands only returned one value, we should compare it to
5224 // zero.
5225 if (!RHS.getNode()) {
5226 RHS = DAG.getConstant(0, dl, LHS.getValueType());
5227 CC = ISD::SETNE;
5228 }
5229 }
5230
5231 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
5232 // instruction.
5233 unsigned Opc = LHS.getOpcode();
5234 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) &&
5235 !Subtarget->isThumb1Only();
5236 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
5237 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
5238 Opc == ISD::USUBO || OptimizeMul) &&
5239 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5240 // Only lower legal XALUO ops.
5241 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
5242 return SDValue();
5243
5244 // The actual operation with overflow check.
5245 SDValue Value, OverflowCmp;
5246 SDValue ARMcc;
5247 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
5248
5249 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
5250 // Reverse the condition code.
5251 ARMCC::CondCodes CondCode =
5252 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
5253 CondCode = ARMCC::getOppositeCondition(CondCode);
5254 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
5255 }
5256 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5257
5258 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
5259 OverflowCmp);
5260 }
5261
5262 if (LHS.getValueType() == MVT::i32) {
5263 SDValue ARMcc;
5264 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
5265 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5266 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
5267 Chain, Dest, ARMcc, CCR, Cmp);
5268 }
5269
5270 if (getTargetMachine().Options.UnsafeFPMath &&
5271 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
5272 CC == ISD::SETNE || CC == ISD::SETUNE)) {
5273 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
5274 return Result;
5275 }
5276
5277 ARMCC::CondCodes CondCode, CondCode2;
5278 FPCCToARMCC(CC, CondCode, CondCode2);
5279
5280 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
5281 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
5282 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5283 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
5284 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
5285 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5286 if (CondCode2 != ARMCC::AL) {
5287 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
5288 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
5289 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
5290 }
5291 return Res;
5292}
5293
5294SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
5295 SDValue Chain = Op.getOperand(0);
5296 SDValue Table = Op.getOperand(1);
5297 SDValue Index = Op.getOperand(2);
5298 SDLoc dl(Op);
5299
5300 EVT PTy = getPointerTy(DAG.getDataLayout());
5301 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
5302 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
5303 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
5304 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
5305 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
5306 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
5307 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
5308 // which does another jump to the destination. This also makes it easier
5309 // to translate it to TBB / TBH later (Thumb2 only).
5310 // FIXME: This might not work if the function is extremely large.
5311 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
5312 Addr, Op.getOperand(2), JTI);
5313 }
5314 if (isPositionIndependent() || Subtarget->isROPI()) {
5315 Addr =
5316 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
5317 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5318 Chain = Addr.getValue(1);
5319 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
5320 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5321 } else {
5322 Addr =
5323 DAG.getLoad(PTy, dl, Chain, Addr,
5324 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
5325 Chain = Addr.getValue(1);
5326 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
5327 }
5328}
5329
5330static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
5331 EVT VT = Op.getValueType();
5332 SDLoc dl(Op);
5333
5334 if (Op.getValueType().getVectorElementType() == MVT::i32) {
5335 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
5336 return Op;
5337 return DAG.UnrollVectorOp(Op.getNode());
5338 }
5339
5340 const bool HasFullFP16 =
5341 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5342
5343 EVT NewTy;
5344 const EVT OpTy = Op.getOperand(0).getValueType();
5345 if (OpTy == MVT::v4f32)
5346 NewTy = MVT::v4i32;
5347 else if (OpTy == MVT::v4f16 && HasFullFP16)
5348 NewTy = MVT::v4i16;
5349 else if (OpTy == MVT::v8f16 && HasFullFP16)
5350 NewTy = MVT::v8i16;
5351 else
5352 llvm_unreachable("Invalid type for custom lowering!")::llvm::llvm_unreachable_internal("Invalid type for custom lowering!"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5352)
;
5353
5354 if (VT != MVT::v4i16 && VT != MVT::v8i16)
5355 return DAG.UnrollVectorOp(Op.getNode());
5356
5357 Op = DAG.getNode(Op.getOpcode(), dl, NewTy, Op.getOperand(0));
5358 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
5359}
5360
5361SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
5362 EVT VT = Op.getValueType();
5363 if (VT.isVector())
5364 return LowerVectorFP_TO_INT(Op, DAG);
5365 if (isUnsupportedFloatingType(Op.getOperand(0).getValueType())) {
5366 RTLIB::Libcall LC;
5367 if (Op.getOpcode() == ISD::FP_TO_SINT)
5368 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
5369 Op.getValueType());
5370 else
5371 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
5372 Op.getValueType());
5373 MakeLibCallOptions CallOptions;
5374 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5375 CallOptions, SDLoc(Op)).first;
5376 }
5377
5378 return Op;
5379}
5380
5381static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5382 EVT VT = Op.getValueType();
5383 SDLoc dl(Op);
5384
5385 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
5386 if (VT.getVectorElementType() == MVT::f32)
5387 return Op;
5388 return DAG.UnrollVectorOp(Op.getNode());
5389 }
5390
5391 assert((Op.getOperand(0).getValueType() == MVT::v4i16 ||(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5393, __PRETTY_FUNCTION__))
5392 Op.getOperand(0).getValueType() == MVT::v8i16) &&(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5393, __PRETTY_FUNCTION__))
5393 "Invalid type for custom lowering!")(((Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand
(0).getValueType() == MVT::v8i16) && "Invalid type for custom lowering!"
) ? static_cast<void> (0) : __assert_fail ("(Op.getOperand(0).getValueType() == MVT::v4i16 || Op.getOperand(0).getValueType() == MVT::v8i16) && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5393, __PRETTY_FUNCTION__))
;
5394
5395 const bool HasFullFP16 =
5396 static_cast<const ARMSubtarget&>(DAG.getSubtarget()).hasFullFP16();
5397
5398 EVT DestVecType;
5399 if (VT == MVT::v4f32)
5400 DestVecType = MVT::v4i32;
5401 else if (VT == MVT::v4f16 && HasFullFP16)
5402 DestVecType = MVT::v4i16;
5403 else if (VT == MVT::v8f16 && HasFullFP16)
5404 DestVecType = MVT::v8i16;
5405 else
5406 return DAG.UnrollVectorOp(Op.getNode());
5407
5408 unsigned CastOpc;
5409 unsigned Opc;
5410 switch (Op.getOpcode()) {
5411 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5411)
;
5412 case ISD::SINT_TO_FP:
5413 CastOpc = ISD::SIGN_EXTEND;
5414 Opc = ISD::SINT_TO_FP;
5415 break;
5416 case ISD::UINT_TO_FP:
5417 CastOpc = ISD::ZERO_EXTEND;
5418 Opc = ISD::UINT_TO_FP;
5419 break;
5420 }
5421
5422 Op = DAG.getNode(CastOpc, dl, DestVecType, Op.getOperand(0));
5423 return DAG.getNode(Opc, dl, VT, Op);
5424}
5425
5426SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
5427 EVT VT = Op.getValueType();
5428 if (VT.isVector())
5429 return LowerVectorINT_TO_FP(Op, DAG);
5430 if (isUnsupportedFloatingType(VT)) {
5431 RTLIB::Libcall LC;
5432 if (Op.getOpcode() == ISD::SINT_TO_FP)
5433 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
5434 Op.getValueType());
5435 else
5436 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
5437 Op.getValueType());
5438 MakeLibCallOptions CallOptions;
5439 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
5440 CallOptions, SDLoc(Op)).first;
5441 }
5442
5443 return Op;
5444}
5445
5446SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
5447 // Implement fcopysign with a fabs and a conditional fneg.
5448 SDValue Tmp0 = Op.getOperand(0);
5449 SDValue Tmp1 = Op.getOperand(1);
5450 SDLoc dl(Op);
5451 EVT VT = Op.getValueType();
5452 EVT SrcVT = Tmp1.getValueType();
5453 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
5454 Tmp0.getOpcode() == ARMISD::VMOVDRR;
5455 bool UseNEON = !InGPR && Subtarget->hasNEON();
5456
5457 if (UseNEON) {
5458 // Use VBSL to copy the sign bit.
5459 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80);
5460 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
5461 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
5462 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
5463 if (VT == MVT::f64)
5464 Mask = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5465 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
5466 DAG.getConstant(32, dl, MVT::i32));
5467 else /*if (VT == MVT::f32)*/
5468 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
5469 if (SrcVT == MVT::f32) {
5470 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
5471 if (VT == MVT::f64)
5472 Tmp1 = DAG.getNode(ARMISD::VSHLIMM, dl, OpVT,
5473 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
5474 DAG.getConstant(32, dl, MVT::i32));
5475 } else if (VT == MVT::f32)
5476 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64,
5477 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
5478 DAG.getConstant(32, dl, MVT::i32));
5479 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
5480 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
5481
5482 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff),
5483 dl, MVT::i32);
5484 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
5485 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
5486 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
5487
5488 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
5489 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
5490 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
5491 if (VT == MVT::f32) {
5492 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
5493 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
5494 DAG.getConstant(0, dl, MVT::i32));
5495 } else {
5496 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
5497 }
5498
5499 return Res;
5500 }
5501
5502 // Bitcast operand 1 to i32.
5503 if (SrcVT == MVT::f64)
5504 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5505 Tmp1).getValue(1);
5506 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
5507
5508 // Or in the signbit with integer operations.
5509 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
5510 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
5511 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
5512 if (VT == MVT::f32) {
5513 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
5514 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
5515 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
5516 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
5517 }
5518
5519 // f64: Or the high part with signbit and then combine two parts.
5520 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
5521 Tmp0);
5522 SDValue Lo = Tmp0.getValue(0);
5523 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
5524 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
5525 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
5526}
5527
5528SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
5529 MachineFunction &MF = DAG.getMachineFunction();
5530 MachineFrameInfo &MFI = MF.getFrameInfo();
5531 MFI.setReturnAddressIsTaken(true);
5532
5533 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
5534 return SDValue();
5535
5536 EVT VT = Op.getValueType();
5537 SDLoc dl(Op);
5538 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5539 if (Depth) {
5540 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5541 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
5542 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
5543 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
5544 MachinePointerInfo());
5545 }
5546
5547 // Return LR, which contains the return address. Mark it an implicit live-in.
5548 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
5549 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
5550}
5551
5552SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
5553 const ARMBaseRegisterInfo &ARI =
5554 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
5555 MachineFunction &MF = DAG.getMachineFunction();
5556 MachineFrameInfo &MFI = MF.getFrameInfo();
5557 MFI.setFrameAddressIsTaken(true);
5558
5559 EVT VT = Op.getValueType();
5560 SDLoc dl(Op); // FIXME probably not meaningful
5561 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5562 Register FrameReg = ARI.getFrameRegister(MF);
5563 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
5564 while (Depth--)
5565 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
5566 MachinePointerInfo());
5567 return FrameAddr;
5568}
5569
5570// FIXME? Maybe this could be a TableGen attribute on some registers and
5571// this table could be generated automatically from RegInfo.
5572Register ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
5573 const MachineFunction &MF) const {
5574 Register Reg = StringSwitch<unsigned>(RegName)
5575 .Case("sp", ARM::SP)
5576 .Default(0);
5577 if (Reg)
5578 return Reg;
5579 report_fatal_error(Twine("Invalid register name \""
5580 + StringRef(RegName) + "\"."));
5581}
5582
5583// Result is 64 bit value so split into two 32 bit values and return as a
5584// pair of values.
5585static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
5586 SelectionDAG &DAG) {
5587 SDLoc DL(N);
5588
5589 // This function is only supposed to be called for i64 type destination.
5590 assert(N->getValueType(0) == MVT::i64((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5591, __PRETTY_FUNCTION__))
5591 && "ExpandREAD_REGISTER called for non-i64 type result.")((N->getValueType(0) == MVT::i64 && "ExpandREAD_REGISTER called for non-i64 type result."
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5591, __PRETTY_FUNCTION__))
;
5592
5593 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
5594 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
5595 N->getOperand(0),
5596 N->getOperand(1));
5597
5598 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
5599 Read.getValue(1)));
5600 Results.push_back(Read.getOperand(0));
5601}
5602
5603/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5604/// When \p DstVT, the destination type of \p BC, is on the vector
5605/// register bank and the source of bitcast, \p Op, operates on the same bank,
5606/// it might be possible to combine them, such that everything stays on the
5607/// vector register bank.
5608/// \p return The node that would replace \p BT, if the combine
5609/// is possible.
5610static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5611 SelectionDAG &DAG) {
5612 SDValue Op = BC->getOperand(0);
5613 EVT DstVT = BC->getValueType(0);
5614
5615 // The only vector instruction that can produce a scalar (remember,
5616 // since the bitcast was about to be turned into VMOVDRR, the source
5617 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5618 // Moreover, we can do this combine only if there is one use.
5619 // Finally, if the destination type is not a vector, there is not
5620 // much point on forcing everything on the vector bank.
5621 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5622 !Op.hasOneUse())
5623 return SDValue();
5624
5625 // If the index is not constant, we will introduce an additional
5626 // multiply that will stick.
5627 // Give up in that case.
5628 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5629 if (!Index)
5630 return SDValue();
5631 unsigned DstNumElt = DstVT.getVectorNumElements();
5632
5633 // Compute the new index.
5634 const APInt &APIntIndex = Index->getAPIntValue();
5635 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5636 NewIndex *= APIntIndex;
5637 // Check if the new constant index fits into i32.
5638 if (NewIndex.getBitWidth() > 32)
5639 return SDValue();
5640
5641 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5642 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5643 SDLoc dl(Op);
5644 SDValue ExtractSrc = Op.getOperand(0);
5645 EVT VecVT = EVT::getVectorVT(
5646 *DAG.getContext(), DstVT.getScalarType(),
5647 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5648 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5649 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5650 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5651}
5652
5653/// ExpandBITCAST - If the target supports VFP, this function is called to
5654/// expand a bit convert where either the source or destination type is i64 to
5655/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5656/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5657/// vectors), since the legalizer won't know what to do with that.
5658static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5659 const ARMSubtarget *Subtarget) {
5660 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5661 SDLoc dl(N);
5662 SDValue Op = N->getOperand(0);
5663
5664 // This function is only supposed to be called for i64 types, either as the
5665 // source or destination of the bit convert.
5666 EVT SrcVT = Op.getValueType();
5667 EVT DstVT = N->getValueType(0);
5668 const bool HasFullFP16 = Subtarget->hasFullFP16();
5669
5670 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5671 // FullFP16: half values are passed in S-registers, and we don't
5672 // need any of the bitcast and moves:
5673 //
5674 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5675 // t5: i32 = bitcast t2
5676 // t18: f16 = ARMISD::VMOVhr t5
5677 if (Op.getOpcode() != ISD::CopyFromReg ||
5678 Op.getValueType() != MVT::f32)
5679 return SDValue();
5680
5681 auto Move = N->use_begin();
5682 if (Move->getOpcode() != ARMISD::VMOVhr)
5683 return SDValue();
5684
5685 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5686 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5687 DAG.ReplaceAllUsesWith(*Move, &Copy);
5688 return Copy;
5689 }
5690
5691 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5692 if (!HasFullFP16)
5693 return SDValue();
5694 // SoftFP: read half-precision arguments:
5695 //
5696 // t2: i32,ch = ...
5697 // t7: i16 = truncate t2 <~~~~ Op
5698 // t8: f16 = bitcast t7 <~~~~ N
5699 //
5700 if (Op.getOperand(0).getValueType() == MVT::i32)
5701 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5702 MVT::f16, Op.getOperand(0));
5703
5704 return SDValue();
5705 }
5706
5707 // Half-precision return values
5708 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5709 if (!HasFullFP16)
5710 return SDValue();
5711 //
5712 // t11: f16 = fadd t8, t10
5713 // t12: i16 = bitcast t11 <~~~ SDNode N
5714 // t13: i32 = zero_extend t12
5715 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5716 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5717 //
5718 // transform this into:
5719 //
5720 // t20: i32 = ARMISD::VMOVrh t11
5721 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5722 //
5723 auto ZeroExtend = N->use_begin();
5724 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5725 ZeroExtend->getValueType(0) != MVT::i32)
5726 return SDValue();
5727
5728 auto Copy = ZeroExtend->use_begin();
5729 if (Copy->getOpcode() == ISD::CopyToReg &&
5730 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5731 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5732 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5733 return Cvt;
5734 }
5735 return SDValue();
5736 }
5737
5738 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5739 return SDValue();
5740
5741 // Turn i64->f64 into VMOVDRR.
5742 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5743 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5744 // if we can combine the bitcast with its source.
5745 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5746 return Val;
5747
5748 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5749 DAG.getConstant(0, dl, MVT::i32));
5750 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5751 DAG.getConstant(1, dl, MVT::i32));
5752 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5753 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5754 }
5755
5756 // Turn f64->i64 into VMOVRRD.
5757 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5758 SDValue Cvt;
5759 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5760 SrcVT.getVectorNumElements() > 1)
5761 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5762 DAG.getVTList(MVT::i32, MVT::i32),
5763 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5764 else
5765 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5766 DAG.getVTList(MVT::i32, MVT::i32), Op);
5767 // Merge the pieces into a single i64 value.
5768 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5769 }
5770
5771 return SDValue();
5772}
5773
5774/// getZeroVector - Returns a vector of specified type with all zero elements.
5775/// Zero vectors are used to represent vector negation and in those cases
5776/// will be implemented with the NEON VNEG instruction. However, VNEG does
5777/// not support i64 elements, so sometimes the zero vectors will need to be
5778/// explicitly constructed. Regardless, use a canonical VMOV to create the
5779/// zero vector.
5780static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5781 assert(VT.isVector() && "Expected a vector type")((VT.isVector() && "Expected a vector type") ? static_cast
<void> (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5781, __PRETTY_FUNCTION__))
;
5782 // The canonical modified immediate encoding of a zero vector is....0!
5783 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5784 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5785 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5786 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5787}
5788
5789/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5790/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5791SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5792 SelectionDAG &DAG) const {
5793 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5793, __PRETTY_FUNCTION__))
;
5794 EVT VT = Op.getValueType();
5795 unsigned VTBits = VT.getSizeInBits();
5796 SDLoc dl(Op);
5797 SDValue ShOpLo = Op.getOperand(0);
5798 SDValue ShOpHi = Op.getOperand(1);
5799 SDValue ShAmt = Op.getOperand(2);
5800 SDValue ARMcc;
5801 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5802 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5803
5804 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)((Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::
SRL_PARTS) ? static_cast<void> (0) : __assert_fail ("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5804, __PRETTY_FUNCTION__))
;
5805
5806 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5807 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5808 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5809 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5810 DAG.getConstant(VTBits, dl, MVT::i32));
5811 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5812 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5813 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5814 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5815 ISD::SETGE, ARMcc, DAG, dl);
5816 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5817 ARMcc, CCR, CmpLo);
5818
5819 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5820 SDValue HiBigShift = Opc == ISD::SRA
5821 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5822 DAG.getConstant(VTBits - 1, dl, VT))
5823 : DAG.getConstant(0, dl, VT);
5824 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5825 ISD::SETGE, ARMcc, DAG, dl);
5826 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5827 ARMcc, CCR, CmpHi);
5828
5829 SDValue Ops[2] = { Lo, Hi };
5830 return DAG.getMergeValues(Ops, dl);
5831}
5832
5833/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5834/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5835SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5836 SelectionDAG &DAG) const {
5837 assert(Op.getNumOperands() == 3 && "Not a double-shift!")((Op.getNumOperands() == 3 && "Not a double-shift!") ?
static_cast<void> (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5837, __PRETTY_FUNCTION__))
;
5838 EVT VT = Op.getValueType();
5839 unsigned VTBits = VT.getSizeInBits();
5840 SDLoc dl(Op);
5841 SDValue ShOpLo = Op.getOperand(0);
5842 SDValue ShOpHi = Op.getOperand(1);
5843 SDValue ShAmt = Op.getOperand(2);
5844 SDValue ARMcc;
5845 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5846
5847 assert(Op.getOpcode() == ISD::SHL_PARTS)((Op.getOpcode() == ISD::SHL_PARTS) ? static_cast<void>
(0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS", "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5847, __PRETTY_FUNCTION__))
;
5848 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5849 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5850 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5851 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5852 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5853
5854 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5855 DAG.getConstant(VTBits, dl, MVT::i32));
5856 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5857 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5858 ISD::SETGE, ARMcc, DAG, dl);
5859 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5860 ARMcc, CCR, CmpHi);
5861
5862 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5863 ISD::SETGE, ARMcc, DAG, dl);
5864 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5865 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5866 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5867
5868 SDValue Ops[2] = { Lo, Hi };
5869 return DAG.getMergeValues(Ops, dl);
5870}
5871
5872SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5873 SelectionDAG &DAG) const {
5874 // The rounding mode is in bits 23:22 of the FPSCR.
5875 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5876 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5877 // so that the shift + and get folded into a bitfield extract.
5878 SDLoc dl(Op);
5879 SDValue Ops[] = { DAG.getEntryNode(),
5880 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5881
5882 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5883 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5884 DAG.getConstant(1U << 22, dl, MVT::i32));
5885 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5886 DAG.getConstant(22, dl, MVT::i32));
5887 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5888 DAG.getConstant(3, dl, MVT::i32));
5889}
5890
5891static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5892 const ARMSubtarget *ST) {
5893 SDLoc dl(N);
5894 EVT VT = N->getValueType(0);
5895 if (VT.isVector() && ST->hasNEON()) {
5896
5897 // Compute the least significant set bit: LSB = X & -X
5898 SDValue X = N->getOperand(0);
5899 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5900 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5901
5902 EVT ElemTy = VT.getVectorElementType();
5903
5904 if (ElemTy == MVT::i8) {
5905 // Compute with: cttz(x) = ctpop(lsb - 1)
5906 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5907 DAG.getTargetConstant(1, dl, ElemTy));
5908 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5909 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5910 }
5911
5912 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5913 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5914 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5915 unsigned NumBits = ElemTy.getSizeInBits();
5916 SDValue WidthMinus1 =
5917 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5918 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5919 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5920 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5921 }
5922
5923 // Compute with: cttz(x) = ctpop(lsb - 1)
5924
5925 // Compute LSB - 1.
5926 SDValue Bits;
5927 if (ElemTy == MVT::i64) {
5928 // Load constant 0xffff'ffff'ffff'ffff to register.
5929 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5930 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5931 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5932 } else {
5933 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5934 DAG.getTargetConstant(1, dl, ElemTy));
5935 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5936 }
5937 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5938 }
5939
5940 if (!ST->hasV6T2Ops())
5941 return SDValue();
5942
5943 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5944 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5945}
5946
5947static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5948 const ARMSubtarget *ST) {
5949 EVT VT = N->getValueType(0);
5950 SDLoc DL(N);
5951
5952 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")((ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? static_cast<void> (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5952, __PRETTY_FUNCTION__))
;
5953 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5955, __PRETTY_FUNCTION__))
5954 VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5955, __PRETTY_FUNCTION__))
5955 "Unexpected type for custom ctpop lowering")(((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 ||
VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) &&
"Unexpected type for custom ctpop lowering") ? static_cast<
void> (0) : __assert_fail ("(VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-10~+201911111502510600c19528f1809/llvm/lib/Target/ARM/ARMISelLowering.cpp"
, 5955, __PRETTY_FUNCTION__))
;
5956
5957 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5958 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5959 SDValue Res = DAG.getBitcast(VT8Bit, N->getOperand(0));
5960 Res = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Res);
5961
5962 // Widen v8i8/v16i8 CTPOP result to VT by repeatedly widening pairwise adds.
5963 unsigned EltSize = 8;
5964 unsigned NumElts = VT.is64BitVector() ? 8 : 16;
5965 while (EltSize != VT.getScalarSizeInBits()) {
5966 SmallVector<SDValue, 8> Ops;
5967 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddlu, DL,
5968 TLI.getPointerTy(DAG.getDataLayout())));
5969 Ops.push_back(Res);