Bug Summary

File:lib/Target/ARM/ARMISelLowering.cpp
Warning:line 1045, column 10
Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name ARMISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn326246/build-llvm/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM -I /build/llvm-toolchain-snapshot-7~svn326246/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn326246/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn326246/build-llvm/lib/Target/ARM -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-28-041547-14988-1 -x c++ /build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp

/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp

1//===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARMISelLowering.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMMachineFunctionInfo.h"
21#include "ARMPerfectShuffle.h"
22#include "ARMRegisterInfo.h"
23#include "ARMSelectionDAGInfo.h"
24#include "ARMSubtarget.h"
25#include "MCTargetDesc/ARMAddressingModes.h"
26#include "MCTargetDesc/ARMBaseInfo.h"
27#include "Utils/ARMBaseInfo.h"
28#include "llvm/ADT/APFloat.h"
29#include "llvm/ADT/APInt.h"
30#include "llvm/ADT/ArrayRef.h"
31#include "llvm/ADT/BitVector.h"
32#include "llvm/ADT/DenseMap.h"
33#include "llvm/ADT/STLExtras.h"
34#include "llvm/ADT/SmallPtrSet.h"
35#include "llvm/ADT/SmallVector.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/ADT/StringExtras.h"
38#include "llvm/ADT/StringRef.h"
39#include "llvm/ADT/StringSwitch.h"
40#include "llvm/ADT/Triple.h"
41#include "llvm/ADT/Twine.h"
42#include "llvm/Analysis/VectorUtils.h"
43#include "llvm/CodeGen/CallingConvLower.h"
44#include "llvm/CodeGen/ISDOpcodes.h"
45#include "llvm/CodeGen/IntrinsicLowering.h"
46#include "llvm/CodeGen/MachineBasicBlock.h"
47#include "llvm/CodeGen/MachineConstantPool.h"
48#include "llvm/CodeGen/MachineFrameInfo.h"
49#include "llvm/CodeGen/MachineFunction.h"
50#include "llvm/CodeGen/MachineInstr.h"
51#include "llvm/CodeGen/MachineInstrBuilder.h"
52#include "llvm/CodeGen/MachineJumpTableInfo.h"
53#include "llvm/CodeGen/MachineMemOperand.h"
54#include "llvm/CodeGen/MachineOperand.h"
55#include "llvm/CodeGen/MachineRegisterInfo.h"
56#include "llvm/CodeGen/MachineValueType.h"
57#include "llvm/CodeGen/RuntimeLibcalls.h"
58#include "llvm/CodeGen/SelectionDAG.h"
59#include "llvm/CodeGen/SelectionDAGNodes.h"
60#include "llvm/CodeGen/TargetInstrInfo.h"
61#include "llvm/CodeGen/TargetLowering.h"
62#include "llvm/CodeGen/TargetOpcodes.h"
63#include "llvm/CodeGen/TargetRegisterInfo.h"
64#include "llvm/CodeGen/TargetSubtargetInfo.h"
65#include "llvm/CodeGen/ValueTypes.h"
66#include "llvm/IR/Attributes.h"
67#include "llvm/IR/CallingConv.h"
68#include "llvm/IR/Constant.h"
69#include "llvm/IR/Constants.h"
70#include "llvm/IR/DataLayout.h"
71#include "llvm/IR/DebugLoc.h"
72#include "llvm/IR/DerivedTypes.h"
73#include "llvm/IR/Function.h"
74#include "llvm/IR/GlobalAlias.h"
75#include "llvm/IR/GlobalValue.h"
76#include "llvm/IR/GlobalVariable.h"
77#include "llvm/IR/IRBuilder.h"
78#include "llvm/IR/InlineAsm.h"
79#include "llvm/IR/Instruction.h"
80#include "llvm/IR/Instructions.h"
81#include "llvm/IR/IntrinsicInst.h"
82#include "llvm/IR/Intrinsics.h"
83#include "llvm/IR/Module.h"
84#include "llvm/IR/Type.h"
85#include "llvm/IR/User.h"
86#include "llvm/IR/Value.h"
87#include "llvm/MC/MCInstrDesc.h"
88#include "llvm/MC/MCInstrItineraries.h"
89#include "llvm/MC/MCRegisterInfo.h"
90#include "llvm/MC/MCSchedule.h"
91#include "llvm/Support/AtomicOrdering.h"
92#include "llvm/Support/BranchProbability.h"
93#include "llvm/Support/Casting.h"
94#include "llvm/Support/CodeGen.h"
95#include "llvm/Support/CommandLine.h"
96#include "llvm/Support/Compiler.h"
97#include "llvm/Support/Debug.h"
98#include "llvm/Support/ErrorHandling.h"
99#include "llvm/Support/KnownBits.h"
100#include "llvm/Support/MathExtras.h"
101#include "llvm/Support/raw_ostream.h"
102#include "llvm/Target/TargetMachine.h"
103#include "llvm/Target/TargetOptions.h"
104#include <algorithm>
105#include <cassert>
106#include <cstdint>
107#include <cstdlib>
108#include <iterator>
109#include <limits>
110#include <string>
111#include <tuple>
112#include <utility>
113#include <vector>
114
115using namespace llvm;
116
117#define DEBUG_TYPE"arm-isel" "arm-isel"
118
119STATISTIC(NumTailCalls, "Number of tail calls")static llvm::Statistic NumTailCalls = {"arm-isel", "NumTailCalls"
, "Number of tail calls", {0}, {false}}
;
120STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt")static llvm::Statistic NumMovwMovt = {"arm-isel", "NumMovwMovt"
, "Number of GAs materialized with movw + movt", {0}, {false}
}
;
121STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments")static llvm::Statistic NumLoopByVals = {"arm-isel", "NumLoopByVals"
, "Number of loops generated for byval arguments", {0}, {false
}}
;
122STATISTIC(NumConstpoolPromoted,static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
123 "Number of constants with their storage promoted into constant pools")static llvm::Statistic NumConstpoolPromoted = {"arm-isel", "NumConstpoolPromoted"
, "Number of constants with their storage promoted into constant pools"
, {0}, {false}}
;
124
125static cl::opt<bool>
126ARMInterworking("arm-interworking", cl::Hidden,
127 cl::desc("Enable / disable ARM interworking (for debugging only)"),
128 cl::init(true));
129
130static cl::opt<bool> EnableConstpoolPromotion(
131 "arm-promote-constant", cl::Hidden,
132 cl::desc("Enable / disable promotion of unnamed_addr constants into "
133 "constant pools"),
134 cl::init(false)); // FIXME: set to true by default once PR32780 is fixed
135static cl::opt<unsigned> ConstpoolPromotionMaxSize(
136 "arm-promote-constant-max-size", cl::Hidden,
137 cl::desc("Maximum size of constant to promote into a constant pool"),
138 cl::init(64));
139static cl::opt<unsigned> ConstpoolPromotionMaxTotal(
140 "arm-promote-constant-max-total", cl::Hidden,
141 cl::desc("Maximum size of ALL constants to promote into a constant pool"),
142 cl::init(128));
143
144// The APCS parameter registers.
145static const MCPhysReg GPRArgRegs[] = {
146 ARM::R0, ARM::R1, ARM::R2, ARM::R3
147};
148
149void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
150 MVT PromotedBitwiseVT) {
151 if (VT != PromotedLdStVT) {
152 setOperationAction(ISD::LOAD, VT, Promote);
153 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
154
155 setOperationAction(ISD::STORE, VT, Promote);
156 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
157 }
158
159 MVT ElemTy = VT.getVectorElementType();
160 if (ElemTy != MVT::f64)
161 setOperationAction(ISD::SETCC, VT, Custom);
162 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
163 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
164 if (ElemTy == MVT::i32) {
165 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
166 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
167 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
168 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
169 } else {
170 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
171 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
172 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
173 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
174 }
175 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
176 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
177 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
179 setOperationAction(ISD::SELECT, VT, Expand);
180 setOperationAction(ISD::SELECT_CC, VT, Expand);
181 setOperationAction(ISD::VSELECT, VT, Expand);
182 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
183 if (VT.isInteger()) {
184 setOperationAction(ISD::SHL, VT, Custom);
185 setOperationAction(ISD::SRA, VT, Custom);
186 setOperationAction(ISD::SRL, VT, Custom);
187 }
188
189 // Promote all bit-wise operations.
190 if (VT.isInteger() && VT != PromotedBitwiseVT) {
191 setOperationAction(ISD::AND, VT, Promote);
192 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
193 setOperationAction(ISD::OR, VT, Promote);
194 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
195 setOperationAction(ISD::XOR, VT, Promote);
196 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
197 }
198
199 // Neon does not support vector divide/remainder operations.
200 setOperationAction(ISD::SDIV, VT, Expand);
201 setOperationAction(ISD::UDIV, VT, Expand);
202 setOperationAction(ISD::FDIV, VT, Expand);
203 setOperationAction(ISD::SREM, VT, Expand);
204 setOperationAction(ISD::UREM, VT, Expand);
205 setOperationAction(ISD::FREM, VT, Expand);
206
207 if (!VT.isFloatingPoint() &&
208 VT != MVT::v2i64 && VT != MVT::v1i64)
209 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
210 setOperationAction(Opcode, VT, Legal);
211}
212
213void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
214 addRegisterClass(VT, &ARM::DPRRegClass);
215 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
216}
217
218void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
219 addRegisterClass(VT, &ARM::DPairRegClass);
220 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
221}
222
223ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
224 const ARMSubtarget &STI)
225 : TargetLowering(TM), Subtarget(&STI) {
226 RegInfo = Subtarget->getRegisterInfo();
227 Itins = Subtarget->getInstrItineraryData();
228
229 setBooleanContents(ZeroOrOneBooleanContent);
230 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231
232 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetIOS() &&
233 !Subtarget->isTargetWatchOS()) {
234 bool IsHFTarget = TM.Options.FloatABIType == FloatABI::Hard;
235 for (int LCID = 0; LCID < RTLIB::UNKNOWN_LIBCALL; ++LCID)
236 setLibcallCallingConv(static_cast<RTLIB::Libcall>(LCID),
237 IsHFTarget ? CallingConv::ARM_AAPCS_VFP
238 : CallingConv::ARM_AAPCS);
239 }
240
241 if (Subtarget->isTargetMachO()) {
242 // Uses VFP for Thumb libfuncs if available.
243 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
244 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
245 static const struct {
246 const RTLIB::Libcall Op;
247 const char * const Name;
248 const ISD::CondCode Cond;
249 } LibraryCalls[] = {
250 // Single-precision floating-point arithmetic.
251 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
252 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
253 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
254 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
255
256 // Double-precision floating-point arithmetic.
257 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
258 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
259 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
260 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
261
262 // Single-precision comparisons.
263 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
264 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
265 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
266 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
267 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
268 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
269 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
270 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
271
272 // Double-precision comparisons.
273 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
274 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
275 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
276 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
277 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
278 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
279 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
280 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
281
282 // Floating-point to integer conversions.
283 // i64 conversions are done via library routines even when generating VFP
284 // instructions, so use the same ones.
285 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
286 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
287 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
288 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
289
290 // Conversions between floating types.
291 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
292 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
293
294 // Integer to floating-point conversions.
295 // i64 conversions are done via library routines even when generating VFP
296 // instructions, so use the same ones.
297 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
298 // e.g., __floatunsidf vs. __floatunssidfvfp.
299 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
300 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
301 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
302 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
303 };
304
305 for (const auto &LC : LibraryCalls) {
306 setLibcallName(LC.Op, LC.Name);
307 if (LC.Cond != ISD::SETCC_INVALID)
308 setCmpLibcallCC(LC.Op, LC.Cond);
309 }
310 }
311
312 // Set the correct calling convention for ARMv7k WatchOS. It's just
313 // AAPCS_VFP for functions as simple as libcalls.
314 if (Subtarget->isTargetWatchABI()) {
315 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i)
316 setLibcallCallingConv((RTLIB::Libcall)i, CallingConv::ARM_AAPCS_VFP);
317 }
318 }
319
320 // These libcalls are not available in 32-bit.
321 setLibcallName(RTLIB::SHL_I128, nullptr);
322 setLibcallName(RTLIB::SRL_I128, nullptr);
323 setLibcallName(RTLIB::SRA_I128, nullptr);
324
325 // RTLIB
326 if (Subtarget->isAAPCS_ABI() &&
327 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
328 Subtarget->isTargetMuslAEABI() || Subtarget->isTargetAndroid())) {
329 static const struct {
330 const RTLIB::Libcall Op;
331 const char * const Name;
332 const CallingConv::ID CC;
333 const ISD::CondCode Cond;
334 } LibraryCalls[] = {
335 // Double-precision floating-point arithmetic helper functions
336 // RTABI chapter 4.1.2, Table 2
337 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341
342 // Double-precision floating-point comparison helper functions
343 // RTABI chapter 4.1.2, Table 3
344 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
345 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
346 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
347 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
348 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
349 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
350 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
351 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
352
353 // Single-precision floating-point arithmetic helper functions
354 // RTABI chapter 4.1.2, Table 4
355 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
356 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
357 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
358 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
359
360 // Single-precision floating-point comparison helper functions
361 // RTABI chapter 4.1.2, Table 5
362 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
363 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
364 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
365 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
366 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
367 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
368 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
369 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
370
371 // Floating-point to integer conversions.
372 // RTABI chapter 4.1.2, Table 6
373 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
374 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
375 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
376 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
377 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
378 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
379 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
380 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
381
382 // Conversions between floating types.
383 // RTABI chapter 4.1.2, Table 7
384 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
385 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
386 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
387
388 // Integer to floating-point conversions.
389 // RTABI chapter 4.1.2, Table 8
390 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
391 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
392 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
393 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
394 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
395 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
396 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
397 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
398
399 // Long long helper functions
400 // RTABI chapter 4.2, Table 9
401 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
402 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
403 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
404 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
405
406 // Integer division functions
407 // RTABI chapter 4.3.1
408 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
409 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
410 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
411 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
412 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
413 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
414 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
415 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
416 };
417
418 for (const auto &LC : LibraryCalls) {
419 setLibcallName(LC.Op, LC.Name);
420 setLibcallCallingConv(LC.Op, LC.CC);
421 if (LC.Cond != ISD::SETCC_INVALID)
422 setCmpLibcallCC(LC.Op, LC.Cond);
423 }
424
425 // EABI dependent RTLIB
426 if (TM.Options.EABIVersion == EABI::EABI4 ||
427 TM.Options.EABIVersion == EABI::EABI5) {
428 static const struct {
429 const RTLIB::Libcall Op;
430 const char *const Name;
431 const CallingConv::ID CC;
432 const ISD::CondCode Cond;
433 } MemOpsLibraryCalls[] = {
434 // Memory operations
435 // RTABI chapter 4.3.4
436 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
437 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
438 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
439 };
440
441 for (const auto &LC : MemOpsLibraryCalls) {
442 setLibcallName(LC.Op, LC.Name);
443 setLibcallCallingConv(LC.Op, LC.CC);
444 if (LC.Cond != ISD::SETCC_INVALID)
445 setCmpLibcallCC(LC.Op, LC.Cond);
446 }
447 }
448 }
449
450 if (Subtarget->isTargetWindows()) {
451 static const struct {
452 const RTLIB::Libcall Op;
453 const char * const Name;
454 const CallingConv::ID CC;
455 } LibraryCalls[] = {
456 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
457 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
458 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
459 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
460 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
461 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
462 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
463 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
464 };
465
466 for (const auto &LC : LibraryCalls) {
467 setLibcallName(LC.Op, LC.Name);
468 setLibcallCallingConv(LC.Op, LC.CC);
469 }
470 }
471
472 // Use divmod compiler-rt calls for iOS 5.0 and later.
473 if (Subtarget->isTargetMachO() &&
474 !(Subtarget->isTargetIOS() &&
475 Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
476 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
477 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
478 }
479
480 // The half <-> float conversion functions are always soft-float on
481 // non-watchos platforms, but are needed for some targets which use a
482 // hard-float calling convention by default.
483 if (!Subtarget->isTargetWatchABI()) {
484 if (Subtarget->isAAPCS_ABI()) {
485 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
486 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
487 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
488 } else {
489 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
490 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
491 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
492 }
493 }
494
495 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
496 // a __gnu_ prefix (which is the default).
497 if (Subtarget->isTargetAEABI()) {
498 static const struct {
499 const RTLIB::Libcall Op;
500 const char * const Name;
501 const CallingConv::ID CC;
502 } LibraryCalls[] = {
503 { RTLIB::FPROUND_F32_F16, "__aeabi_f2h", CallingConv::ARM_AAPCS },
504 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS },
505 { RTLIB::FPEXT_F16_F32, "__aeabi_h2f", CallingConv::ARM_AAPCS },
506 };
507
508 for (const auto &LC : LibraryCalls) {
509 setLibcallName(LC.Op, LC.Name);
510 setLibcallCallingConv(LC.Op, LC.CC);
511 }
512 }
513
514 if (Subtarget->isThumb1Only())
515 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
516 else
517 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
518
519 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
520 !Subtarget->isThumb1Only()) {
521 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
522 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
523 }
524
525 if (Subtarget->hasFullFP16()) {
526 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
527 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
528 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
529 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
530 }
531
532 for (MVT VT : MVT::vector_valuetypes()) {
533 for (MVT InnerVT : MVT::vector_valuetypes()) {
534 setTruncStoreAction(VT, InnerVT, Expand);
535 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
536 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
537 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
538 }
539
540 setOperationAction(ISD::MULHS, VT, Expand);
541 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
542 setOperationAction(ISD::MULHU, VT, Expand);
543 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
544
545 setOperationAction(ISD::BSWAP, VT, Expand);
546 }
547
548 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
549 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
550
551 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
552 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
553
554 if (Subtarget->hasNEON()) {
555 addDRTypeForNEON(MVT::v2f32);
556 addDRTypeForNEON(MVT::v8i8);
557 addDRTypeForNEON(MVT::v4i16);
558 addDRTypeForNEON(MVT::v2i32);
559 addDRTypeForNEON(MVT::v1i64);
560
561 addQRTypeForNEON(MVT::v4f32);
562 addQRTypeForNEON(MVT::v2f64);
563 addQRTypeForNEON(MVT::v16i8);
564 addQRTypeForNEON(MVT::v8i16);
565 addQRTypeForNEON(MVT::v4i32);
566 addQRTypeForNEON(MVT::v2i64);
567
568 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
569 // neither Neon nor VFP support any arithmetic operations on it.
570 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
571 // supported for v4f32.
572 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
573 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
574 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
575 // FIXME: Code duplication: FDIV and FREM are expanded always, see
576 // ARMTargetLowering::addTypeForNEON method for details.
577 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
578 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
579 // FIXME: Create unittest.
580 // In another words, find a way when "copysign" appears in DAG with vector
581 // operands.
582 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
583 // FIXME: Code duplication: SETCC has custom operation action, see
584 // ARMTargetLowering::addTypeForNEON method for details.
585 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
586 // FIXME: Create unittest for FNEG and for FABS.
587 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
588 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
589 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
590 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
591 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
592 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
593 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
594 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
595 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
596 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
597 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
598 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
599 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
600 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
601 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
602 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
603 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
604 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
605
606 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
607 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
608 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
609 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
610 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
611 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
612 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
613 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
614 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
615 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
616 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
617 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
618 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
619 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
620
621 // Mark v2f32 intrinsics.
622 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
623 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
624 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
625 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
626 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
627 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
628 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
629 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
630 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
631 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
632 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
633 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
634 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
635 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
636
637 // Neon does not support some operations on v1i64 and v2i64 types.
638 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
639 // Custom handling for some quad-vector types to detect VMULL.
640 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
641 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
642 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
643 // Custom handling for some vector types to avoid expensive expansions
644 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
645 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
646 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
647 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
648 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
649 // a destination type that is wider than the source, and nor does
650 // it have a FP_TO_[SU]INT instruction with a narrower destination than
651 // source.
652 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
653 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
654 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
655 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
656
657 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
658 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
659
660 // NEON does not have single instruction CTPOP for vectors with element
661 // types wider than 8-bits. However, custom lowering can leverage the
662 // v8i8/v16i8 vcnt instruction.
663 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
664 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
665 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
666 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
667 setOperationAction(ISD::CTPOP, MVT::v1i64, Expand);
668 setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
669
670 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand);
671 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
672
673 // NEON does not have single instruction CTTZ for vectors.
674 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
675 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
676 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
677 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
678
679 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
680 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
681 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
682 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
683
684 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
685 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
686 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
687 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
688
689 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
690 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
691 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
692 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
693
694 // NEON only has FMA instructions as of VFP4.
695 if (!Subtarget->hasVFP4()) {
696 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
697 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
698 }
699
700 setTargetDAGCombine(ISD::INTRINSIC_VOID);
701 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
702 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
703 setTargetDAGCombine(ISD::SHL);
704 setTargetDAGCombine(ISD::SRL);
705 setTargetDAGCombine(ISD::SRA);
706 setTargetDAGCombine(ISD::SIGN_EXTEND);
707 setTargetDAGCombine(ISD::ZERO_EXTEND);
708 setTargetDAGCombine(ISD::ANY_EXTEND);
709 setTargetDAGCombine(ISD::BUILD_VECTOR);
710 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
711 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
712 setTargetDAGCombine(ISD::STORE);
713 setTargetDAGCombine(ISD::FP_TO_SINT);
714 setTargetDAGCombine(ISD::FP_TO_UINT);
715 setTargetDAGCombine(ISD::FDIV);
716 setTargetDAGCombine(ISD::LOAD);
717
718 // It is legal to extload from v4i8 to v4i16 or v4i32.
719 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
720 MVT::v2i32}) {
721 for (MVT VT : MVT::integer_vector_valuetypes()) {
722 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
723 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
724 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
725 }
726 }
727 }
728
729 if (Subtarget->isFPOnlySP()) {
730 // When targeting a floating-point unit with only single-precision
731 // operations, f64 is legal for the few double-precision instructions which
732 // are present However, no double-precision operations other than moves,
733 // loads and stores are provided by the hardware.
734 setOperationAction(ISD::FADD, MVT::f64, Expand);
735 setOperationAction(ISD::FSUB, MVT::f64, Expand);
736 setOperationAction(ISD::FMUL, MVT::f64, Expand);
737 setOperationAction(ISD::FMA, MVT::f64, Expand);
738 setOperationAction(ISD::FDIV, MVT::f64, Expand);
739 setOperationAction(ISD::FREM, MVT::f64, Expand);
740 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
741 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
742 setOperationAction(ISD::FNEG, MVT::f64, Expand);
743 setOperationAction(ISD::FABS, MVT::f64, Expand);
744 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
745 setOperationAction(ISD::FSIN, MVT::f64, Expand);
746 setOperationAction(ISD::FCOS, MVT::f64, Expand);
747 setOperationAction(ISD::FPOW, MVT::f64, Expand);
748 setOperationAction(ISD::FLOG, MVT::f64, Expand);
749 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
750 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
751 setOperationAction(ISD::FEXP, MVT::f64, Expand);
752 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
753 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
754 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
755 setOperationAction(ISD::FRINT, MVT::f64, Expand);
756 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
757 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
758 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
759 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
760 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
761 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
762 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
763 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
764 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
765 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
766 }
767
768 computeRegisterProperties(Subtarget->getRegisterInfo());
769
770 // ARM does not have floating-point extending loads.
771 for (MVT VT : MVT::fp_valuetypes()) {
772 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
773 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
774 }
775
776 // ... or truncating stores
777 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
778 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
779 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
780
781 // ARM does not have i1 sign extending load.
782 for (MVT VT : MVT::integer_valuetypes())
783 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
784
785 // ARM supports all 4 flavors of integer indexed load / store.
786 if (!Subtarget->isThumb1Only()) {
787 for (unsigned im = (unsigned)ISD::PRE_INC;
788 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
789 setIndexedLoadAction(im, MVT::i1, Legal);
790 setIndexedLoadAction(im, MVT::i8, Legal);
791 setIndexedLoadAction(im, MVT::i16, Legal);
792 setIndexedLoadAction(im, MVT::i32, Legal);
793 setIndexedStoreAction(im, MVT::i1, Legal);
794 setIndexedStoreAction(im, MVT::i8, Legal);
795 setIndexedStoreAction(im, MVT::i16, Legal);
796 setIndexedStoreAction(im, MVT::i32, Legal);
797 }
798 } else {
799 // Thumb-1 has limited post-inc load/store support - LDM r0!, {r1}.
800 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal);
801 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal);
802 }
803
804 setOperationAction(ISD::SADDO, MVT::i32, Custom);
805 setOperationAction(ISD::UADDO, MVT::i32, Custom);
806 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
807 setOperationAction(ISD::USUBO, MVT::i32, Custom);
808
809 setOperationAction(ISD::ADDCARRY, MVT::i32, Custom);
810 setOperationAction(ISD::SUBCARRY, MVT::i32, Custom);
811
812 // i64 operation support.
813 setOperationAction(ISD::MUL, MVT::i64, Expand);
814 setOperationAction(ISD::MULHU, MVT::i32, Expand);
815 if (Subtarget->isThumb1Only()) {
816 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
817 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
818 }
819 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
820 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
821 setOperationAction(ISD::MULHS, MVT::i32, Expand);
822
823 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
824 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
825 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
826 setOperationAction(ISD::SRL, MVT::i64, Custom);
827 setOperationAction(ISD::SRA, MVT::i64, Custom);
828 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
829
830 // Expand to __aeabi_l{lsl,lsr,asr} calls for Thumb1.
831 if (Subtarget->isThumb1Only()) {
832 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
833 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
834 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
835 }
836
837 setOperationAction(ISD::ADDC, MVT::i32, Custom);
838 setOperationAction(ISD::ADDE, MVT::i32, Custom);
839 setOperationAction(ISD::SUBC, MVT::i32, Custom);
840 setOperationAction(ISD::SUBE, MVT::i32, Custom);
841
842 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
843 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
844
845 // ARM does not have ROTL.
846 setOperationAction(ISD::ROTL, MVT::i32, Expand);
847 for (MVT VT : MVT::vector_valuetypes()) {
848 setOperationAction(ISD::ROTL, VT, Expand);
849 setOperationAction(ISD::ROTR, VT, Expand);
850 }
851 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
853 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
854 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
855
856 // @llvm.readcyclecounter requires the Performance Monitors extension.
857 // Default to the 0 expansion on unsupported platforms.
858 // FIXME: Technically there are older ARM CPUs that have
859 // implementation-specific ways of obtaining this information.
860 if (Subtarget->hasPerfMon())
861 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
862
863 // Only ARMv6 has BSWAP.
864 if (!Subtarget->hasV6Ops())
865 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
866
867 bool hasDivide = Subtarget->isThumb() ? Subtarget->hasDivideInThumbMode()
868 : Subtarget->hasDivideInARMMode();
869 if (!hasDivide) {
870 // These are expanded into libcalls if the cpu doesn't have HW divider.
871 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
872 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
873 }
874
875 if (Subtarget->isTargetWindows() && !Subtarget->hasDivideInThumbMode()) {
876 setOperationAction(ISD::SDIV, MVT::i32, Custom);
877 setOperationAction(ISD::UDIV, MVT::i32, Custom);
878
879 setOperationAction(ISD::SDIV, MVT::i64, Custom);
880 setOperationAction(ISD::UDIV, MVT::i64, Custom);
881 }
882
883 setOperationAction(ISD::SREM, MVT::i32, Expand);
884 setOperationAction(ISD::UREM, MVT::i32, Expand);
885
886 // Register based DivRem for AEABI (RTABI 4.2)
887 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid() ||
888 Subtarget->isTargetGNUAEABI() || Subtarget->isTargetMuslAEABI() ||
889 Subtarget->isTargetWindows()) {
890 setOperationAction(ISD::SREM, MVT::i64, Custom);
891 setOperationAction(ISD::UREM, MVT::i64, Custom);
892 HasStandaloneRem = false;
893
894 if (Subtarget->isTargetWindows()) {
895 const struct {
896 const RTLIB::Libcall Op;
897 const char * const Name;
898 const CallingConv::ID CC;
899 } LibraryCalls[] = {
900 { RTLIB::SDIVREM_I8, "__rt_sdiv", CallingConv::ARM_AAPCS },
901 { RTLIB::SDIVREM_I16, "__rt_sdiv", CallingConv::ARM_AAPCS },
902 { RTLIB::SDIVREM_I32, "__rt_sdiv", CallingConv::ARM_AAPCS },
903 { RTLIB::SDIVREM_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS },
904
905 { RTLIB::UDIVREM_I8, "__rt_udiv", CallingConv::ARM_AAPCS },
906 { RTLIB::UDIVREM_I16, "__rt_udiv", CallingConv::ARM_AAPCS },
907 { RTLIB::UDIVREM_I32, "__rt_udiv", CallingConv::ARM_AAPCS },
908 { RTLIB::UDIVREM_I64, "__rt_udiv64", CallingConv::ARM_AAPCS },
909 };
910
911 for (const auto &LC : LibraryCalls) {
912 setLibcallName(LC.Op, LC.Name);
913 setLibcallCallingConv(LC.Op, LC.CC);
914 }
915 } else {
916 const struct {
917 const RTLIB::Libcall Op;
918 const char * const Name;
919 const CallingConv::ID CC;
920 } LibraryCalls[] = {
921 { RTLIB::SDIVREM_I8, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
922 { RTLIB::SDIVREM_I16, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
923 { RTLIB::SDIVREM_I32, "__aeabi_idivmod", CallingConv::ARM_AAPCS },
924 { RTLIB::SDIVREM_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS },
925
926 { RTLIB::UDIVREM_I8, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
927 { RTLIB::UDIVREM_I16, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
928 { RTLIB::UDIVREM_I32, "__aeabi_uidivmod", CallingConv::ARM_AAPCS },
929 { RTLIB::UDIVREM_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS },
930 };
931
932 for (const auto &LC : LibraryCalls) {
933 setLibcallName(LC.Op, LC.Name);
934 setLibcallCallingConv(LC.Op, LC.CC);
935 }
936 }
937
938 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
939 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
940 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
941 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
942 } else {
943 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
944 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
945 }
946
947 if (Subtarget->isTargetWindows() && Subtarget->getTargetTriple().isOSMSVCRT())
948 for (auto &VT : {MVT::f32, MVT::f64})
949 setOperationAction(ISD::FPOWI, VT, Custom);
950
951 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
952 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
953 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
954 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
955
956 setOperationAction(ISD::TRAP, MVT::Other, Legal);
957
958 // Use the default implementation.
959 setOperationAction(ISD::VASTART, MVT::Other, Custom);
960 setOperationAction(ISD::VAARG, MVT::Other, Expand);
961 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
962 setOperationAction(ISD::VAEND, MVT::Other, Expand);
963 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
964 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
965
966 if (Subtarget->isTargetWindows())
967 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
968 else
969 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
970
971 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
972 // the default expansion.
973 InsertFencesForAtomic = false;
974 if (Subtarget->hasAnyDataBarrier() &&
975 (!Subtarget->isThumb() || Subtarget->hasV8MBaselineOps())) {
976 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
977 // to ldrex/strex loops already.
978 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
979 if (!Subtarget->isThumb() || !Subtarget->isMClass())
980 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
981
982 // On v8, we have particularly efficient implementations of atomic fences
983 // if they can be combined with nearby atomic loads and stores.
984 if (!Subtarget->hasV8Ops() || getTargetMachine().getOptLevel() == 0) {
985 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
986 InsertFencesForAtomic = true;
987 }
988 } else {
989 // If there's anything we can use as a barrier, go through custom lowering
990 // for ATOMIC_FENCE.
991 // If target has DMB in thumb, Fences can be inserted.
992 if (Subtarget->hasDataBarrier())
993 InsertFencesForAtomic = true;
994
995 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
996 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
997
998 // Set them all for expansion, which will force libcalls.
999 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
1000 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
1001 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
1002 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
1003 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
1004 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
1005 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
1006 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
1007 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
1008 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
1009 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
1010 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
1011 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
1012 // Unordered/Monotonic case.
1013 if (!InsertFencesForAtomic) {
1014 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1015 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1016 }
1017 }
1018
1019 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1020
1021 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
1022 if (!Subtarget->hasV6Ops()) {
1023 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1024 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
1025 }
1026 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1027
1028 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1029 !Subtarget->isThumb1Only()) {
1030 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
1031 // iff target supports vfp2.
1032 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
1033 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
1034 }
1035
1036 // We want to custom lower some of our intrinsics.
1037 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1038 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
1039 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
1040 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
1041 if (Subtarget->useSjLjEH())
1042 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
1043
1044 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1045 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1046 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1047 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1048 setOperationAction(ISD::SELECT, MVT::i32, Custom);
1049 setOperationAction(ISD::SELECT, MVT::f32, Custom);
1050 setOperationAction(ISD::SELECT, MVT::f64, Custom);
1051 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1052 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1053 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1054
1055 // Thumb-1 cannot currently select ARMISD::SUBE.
1056 if (!Subtarget->isThumb1Only())
1057 setOperationAction(ISD::SETCCE, MVT::i32, Custom);
1058
1059 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
1060 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1061 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1062 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1063 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1064 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
1065
1066 // We don't support sin/cos/fmod/copysign/pow
1067 setOperationAction(ISD::FSIN, MVT::f64, Expand);
1068 setOperationAction(ISD::FSIN, MVT::f32, Expand);
1069 setOperationAction(ISD::FCOS, MVT::f32, Expand);
1070 setOperationAction(ISD::FCOS, MVT::f64, Expand);
1071 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1072 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1073 setOperationAction(ISD::FREM, MVT::f64, Expand);
1074 setOperationAction(ISD::FREM, MVT::f32, Expand);
1075 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
1076 !Subtarget->isThumb1Only()) {
1077 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
1078 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
1079 }
1080 setOperationAction(ISD::FPOW, MVT::f64, Expand);
1081 setOperationAction(ISD::FPOW, MVT::f32, Expand);
1082
1083 if (!Subtarget->hasVFP4()) {
1084 setOperationAction(ISD::FMA, MVT::f64, Expand);
1085 setOperationAction(ISD::FMA, MVT::f32, Expand);
1086 }
1087
1088 // Various VFP goodness
1089 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
1090 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1091 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
1092 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1093 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1094 }
1095
1096 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1097 if (!Subtarget->hasFP16()) {
1098 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1099 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1100 }
1101 }
1102
1103 // Use __sincos_stret if available.
1104 if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
1105 getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
1106 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1107 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1108 }
1109
1110 // FP-ARMv8 implements a lot of rounding-like FP operations.
1111 if (Subtarget->hasFPARMv8()) {
1112 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1113 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1114 setOperationAction(ISD::FROUND, MVT::f32, Legal);
1115 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1116 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1117 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1118 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1119 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1120 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
1121 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
1122 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
1123 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
1124
1125 if (!Subtarget->isFPOnlySP()) {
1126 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1127 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1128 setOperationAction(ISD::FROUND, MVT::f64, Legal);
1129 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1130 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1131 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1132 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1133 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1134 }
1135 }
1136
1137 if (Subtarget->hasNEON()) {
1138 // vmin and vmax aren't available in a scalar form, so we use
1139 // a NEON instruction with an undef lane instead.
1140 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1141 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
1142 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1143 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
1144 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
1145 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
1146 }
1147
1148 // We have target-specific dag combine patterns for the following nodes:
1149 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1150 setTargetDAGCombine(ISD::ADD);
1151 setTargetDAGCombine(ISD::SUB);
1152 setTargetDAGCombine(ISD::MUL);
1153 setTargetDAGCombine(ISD::AND);
1154 setTargetDAGCombine(ISD::OR);
1155 setTargetDAGCombine(ISD::XOR);
1156
1157 if (Subtarget->hasV6Ops())
1158 setTargetDAGCombine(ISD::SRL);
1159
1160 setStackPointerRegisterToSaveRestore(ARM::SP);
1161
1162 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1163 !Subtarget->hasVFP2())
1164 setSchedulingPreference(Sched::RegPressure);
1165 else
1166 setSchedulingPreference(Sched::Hybrid);
1167
1168 //// temporary - rewrite interface to use type
1169 MaxStoresPerMemset = 8;
1170 MaxStoresPerMemsetOptSize = 4;
1171 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1172 MaxStoresPerMemcpyOptSize = 2;
1173 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1174 MaxStoresPerMemmoveOptSize = 2;
1175
1176 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1177 // are at least 4 bytes aligned.
1178 setMinStackArgumentAlignment(4);
1179
1180 // Prefer likely predicted branches to selects on out-of-order cores.
1181 PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
1182
1183 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1184}
1185
1186bool ARMTargetLowering::useSoftFloat() const {
1187 return Subtarget->useSoftFloat();
1188}
1189
1190// FIXME: It might make sense to define the representative register class as the
1191// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1192// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1193// SPR's representative would be DPR_VFP2. This should work well if register
1194// pressure tracking were modified such that a register use would increment the
1195// pressure of the register class's representative and all of it's super
1196// classes' representatives transitively. We have not implemented this because
1197// of the difficulty prior to coalescing of modeling operand register classes
1198// due to the common occurrence of cross class copies and subregister insertions
1199// and extractions.
1200std::pair<const TargetRegisterClass *, uint8_t>
1201ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1202 MVT VT) const {
1203 const TargetRegisterClass *RRC = nullptr;
1204 uint8_t Cost = 1;
1205 switch (VT.SimpleTy) {
1206 default:
1207 return TargetLowering::findRepresentativeClass(TRI, VT);
1208 // Use DPR as representative register class for all floating point
1209 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1210 // the cost is 1 for both f32 and f64.
1211 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1212 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1213 RRC = &ARM::DPRRegClass;
1214 // When NEON is used for SP, only half of the register file is available
1215 // because operations that define both SP and DP results will be constrained
1216 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1217 // coalescing by double-counting the SP regs. See the FIXME above.
1218 if (Subtarget->useNEONForSinglePrecisionFP())
1219 Cost = 2;
1220 break;
1221 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1222 case MVT::v4f32: case MVT::v2f64:
1223 RRC = &ARM::DPRRegClass;
1224 Cost = 2;
1225 break;
1226 case MVT::v4i64:
1227 RRC = &ARM::DPRRegClass;
1228 Cost = 4;
1229 break;
1230 case MVT::v8i64:
1231 RRC = &ARM::DPRRegClass;
1232 Cost = 8;
1233 break;
1234 }
1235 return std::make_pair(RRC, Cost);
1236}
1237
1238const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1239 switch ((ARMISD::NodeType)Opcode) {
1240 case ARMISD::FIRST_NUMBER: break;
1241 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1242 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1243 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1244 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1245 case ARMISD::CALL: return "ARMISD::CALL";
1246 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1247 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1248 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1249 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1250 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1251 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1252 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1253 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1254 case ARMISD::CMP: return "ARMISD::CMP";
1255 case ARMISD::CMN: return "ARMISD::CMN";
1256 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1257 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1258 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1259 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1260 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1261
1262 case ARMISD::CMOV: return "ARMISD::CMOV";
1263
1264 case ARMISD::SSAT: return "ARMISD::SSAT";
1265 case ARMISD::USAT: return "ARMISD::USAT";
1266
1267 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1268 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1269 case ARMISD::RRX: return "ARMISD::RRX";
1270
1271 case ARMISD::ADDC: return "ARMISD::ADDC";
1272 case ARMISD::ADDE: return "ARMISD::ADDE";
1273 case ARMISD::SUBC: return "ARMISD::SUBC";
1274 case ARMISD::SUBE: return "ARMISD::SUBE";
1275
1276 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1277 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1278 case ARMISD::VMOVhr: return "ARMISD::VMOVhr";
1279 case ARMISD::VMOVrh: return "ARMISD::VMOVrh";
1280
1281 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1282 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1283 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1284
1285 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1286
1287 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1288
1289 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1290
1291 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1292
1293 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1294
1295 case ARMISD::WIN__CHKSTK: return "ARMISD::WIN__CHKSTK";
1296 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1297
1298 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1299 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1300 case ARMISD::VCGE: return "ARMISD::VCGE";
1301 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1302 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1303 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1304 case ARMISD::VCGT: return "ARMISD::VCGT";
1305 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1306 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1307 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1308 case ARMISD::VTST: return "ARMISD::VTST";
1309
1310 case ARMISD::VSHL: return "ARMISD::VSHL";
1311 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1312 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1313 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1314 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1315 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1316 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1317 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1318 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1319 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1320 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1321 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1322 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1323 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1324 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1325 case ARMISD::VSLI: return "ARMISD::VSLI";
1326 case ARMISD::VSRI: return "ARMISD::VSRI";
1327 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1328 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1329 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1330 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1331 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1332 case ARMISD::VDUP: return "ARMISD::VDUP";
1333 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1334 case ARMISD::VEXT: return "ARMISD::VEXT";
1335 case ARMISD::VREV64: return "ARMISD::VREV64";
1336 case ARMISD::VREV32: return "ARMISD::VREV32";
1337 case ARMISD::VREV16: return "ARMISD::VREV16";
1338 case ARMISD::VZIP: return "ARMISD::VZIP";
1339 case ARMISD::VUZP: return "ARMISD::VUZP";
1340 case ARMISD::VTRN: return "ARMISD::VTRN";
1341 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1342 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1343 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1344 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1345 case ARMISD::UMAAL: return "ARMISD::UMAAL";
1346 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1347 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1348 case ARMISD::SMLALBB: return "ARMISD::SMLALBB";
1349 case ARMISD::SMLALBT: return "ARMISD::SMLALBT";
1350 case ARMISD::SMLALTB: return "ARMISD::SMLALTB";
1351 case ARMISD::SMLALTT: return "ARMISD::SMLALTT";
1352 case ARMISD::SMULWB: return "ARMISD::SMULWB";
1353 case ARMISD::SMULWT: return "ARMISD::SMULWT";
1354 case ARMISD::SMLALD: return "ARMISD::SMLALD";
1355 case ARMISD::SMLALDX: return "ARMISD::SMLALDX";
1356 case ARMISD::SMLSLD: return "ARMISD::SMLSLD";
1357 case ARMISD::SMLSLDX: return "ARMISD::SMLSLDX";
1358 case ARMISD::SMMLAR: return "ARMISD::SMMLAR";
1359 case ARMISD::SMMLSR: return "ARMISD::SMMLSR";
1360 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1361 case ARMISD::BFI: return "ARMISD::BFI";
1362 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1363 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1364 case ARMISD::VBSL: return "ARMISD::VBSL";
1365 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1366 case ARMISD::VLD1DUP: return "ARMISD::VLD1DUP";
1367 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1368 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1369 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1370 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1371 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1372 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1373 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1374 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1375 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1376 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1377 case ARMISD::VLD1DUP_UPD: return "ARMISD::VLD1DUP_UPD";
1378 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1379 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1380 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1381 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1382 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1383 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1384 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1385 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1386 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1387 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1388 }
1389 return nullptr;
1390}
1391
1392EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1393 EVT VT) const {
1394 if (!VT.isVector())
1395 return getPointerTy(DL);
1396 return VT.changeVectorElementTypeToInteger();
1397}
1398
1399/// getRegClassFor - Return the register class that should be used for the
1400/// specified value type.
1401const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1402 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1403 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1404 // load / store 4 to 8 consecutive D registers.
1405 if (Subtarget->hasNEON()) {
1406 if (VT == MVT::v4i64)
1407 return &ARM::QQPRRegClass;
1408 if (VT == MVT::v8i64)
1409 return &ARM::QQQQPRRegClass;
1410 }
1411 return TargetLowering::getRegClassFor(VT);
1412}
1413
1414// memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1415// source/dest is aligned and the copy size is large enough. We therefore want
1416// to align such objects passed to memory intrinsics.
1417bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1418 unsigned &PrefAlign) const {
1419 if (!isa<MemIntrinsic>(CI))
1420 return false;
1421 MinSize = 8;
1422 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1423 // cycle faster than 4-byte aligned LDM.
1424 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1425 return true;
1426}
1427
1428// Create a fast isel object.
1429FastISel *
1430ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1431 const TargetLibraryInfo *libInfo) const {
1432 return ARM::createFastISel(funcInfo, libInfo);
1433}
1434
1435Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1436 unsigned NumVals = N->getNumValues();
1437 if (!NumVals)
1438 return Sched::RegPressure;
1439
1440 for (unsigned i = 0; i != NumVals; ++i) {
1441 EVT VT = N->getValueType(i);
1442 if (VT == MVT::Glue || VT == MVT::Other)
1443 continue;
1444 if (VT.isFloatingPoint() || VT.isVector())
1445 return Sched::ILP;
1446 }
1447
1448 if (!N->isMachineOpcode())
1449 return Sched::RegPressure;
1450
1451 // Load are scheduled for latency even if there instruction itinerary
1452 // is not available.
1453 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1454 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1455
1456 if (MCID.getNumDefs() == 0)
1457 return Sched::RegPressure;
1458 if (!Itins->isEmpty() &&
1459 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1460 return Sched::ILP;
1461
1462 return Sched::RegPressure;
1463}
1464
1465//===----------------------------------------------------------------------===//
1466// Lowering Code
1467//===----------------------------------------------------------------------===//
1468
1469static bool isSRL16(const SDValue &Op) {
1470 if (Op.getOpcode() != ISD::SRL)
1471 return false;
1472 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1473 return Const->getZExtValue() == 16;
1474 return false;
1475}
1476
1477static bool isSRA16(const SDValue &Op) {
1478 if (Op.getOpcode() != ISD::SRA)
1479 return false;
1480 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1481 return Const->getZExtValue() == 16;
1482 return false;
1483}
1484
1485static bool isSHL16(const SDValue &Op) {
1486 if (Op.getOpcode() != ISD::SHL)
1487 return false;
1488 if (auto Const = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
1489 return Const->getZExtValue() == 16;
1490 return false;
1491}
1492
1493// Check for a signed 16-bit value. We special case SRA because it makes it
1494// more simple when also looking for SRAs that aren't sign extending a
1495// smaller value. Without the check, we'd need to take extra care with
1496// checking order for some operations.
1497static bool isS16(const SDValue &Op, SelectionDAG &DAG) {
1498 if (isSRA16(Op))
1499 return isSHL16(Op.getOperand(0));
1500 return DAG.ComputeNumSignBits(Op) == 17;
1501}
1502
1503/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1504static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1505 switch (CC) {
1506 default: llvm_unreachable("Unknown condition code!")::llvm::llvm_unreachable_internal("Unknown condition code!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1506)
;
1507 case ISD::SETNE: return ARMCC::NE;
1508 case ISD::SETEQ: return ARMCC::EQ;
1509 case ISD::SETGT: return ARMCC::GT;
1510 case ISD::SETGE: return ARMCC::GE;
1511 case ISD::SETLT: return ARMCC::LT;
1512 case ISD::SETLE: return ARMCC::LE;
1513 case ISD::SETUGT: return ARMCC::HI;
1514 case ISD::SETUGE: return ARMCC::HS;
1515 case ISD::SETULT: return ARMCC::LO;
1516 case ISD::SETULE: return ARMCC::LS;
1517 }
1518}
1519
1520/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1521static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1522 ARMCC::CondCodes &CondCode2, bool &InvalidOnQNaN) {
1523 CondCode2 = ARMCC::AL;
1524 InvalidOnQNaN = true;
1525 switch (CC) {
1526 default: llvm_unreachable("Unknown FP condition!")::llvm::llvm_unreachable_internal("Unknown FP condition!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1526)
;
1527 case ISD::SETEQ:
1528 case ISD::SETOEQ:
1529 CondCode = ARMCC::EQ;
1530 InvalidOnQNaN = false;
1531 break;
1532 case ISD::SETGT:
1533 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1534 case ISD::SETGE:
1535 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1536 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1537 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1538 case ISD::SETONE:
1539 CondCode = ARMCC::MI;
1540 CondCode2 = ARMCC::GT;
1541 InvalidOnQNaN = false;
1542 break;
1543 case ISD::SETO: CondCode = ARMCC::VC; break;
1544 case ISD::SETUO: CondCode = ARMCC::VS; break;
1545 case ISD::SETUEQ:
1546 CondCode = ARMCC::EQ;
1547 CondCode2 = ARMCC::VS;
1548 InvalidOnQNaN = false;
1549 break;
1550 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1551 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1552 case ISD::SETLT:
1553 case ISD::SETULT: CondCode = ARMCC::LT; break;
1554 case ISD::SETLE:
1555 case ISD::SETULE: CondCode = ARMCC::LE; break;
1556 case ISD::SETNE:
1557 case ISD::SETUNE:
1558 CondCode = ARMCC::NE;
1559 InvalidOnQNaN = false;
1560 break;
1561 }
1562}
1563
1564//===----------------------------------------------------------------------===//
1565// Calling Convention Implementation
1566//===----------------------------------------------------------------------===//
1567
1568#include "ARMGenCallingConv.inc"
1569
1570/// getEffectiveCallingConv - Get the effective calling convention, taking into
1571/// account presence of floating point hardware and calling convention
1572/// limitations, such as support for variadic functions.
1573CallingConv::ID
1574ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1575 bool isVarArg) const {
1576 switch (CC) {
1577 default:
1578 report_fatal_error("Unsupported calling convention");
1579 case CallingConv::ARM_AAPCS:
1580 case CallingConv::ARM_APCS:
1581 case CallingConv::GHC:
1582 return CC;
1583 case CallingConv::PreserveMost:
1584 return CallingConv::PreserveMost;
1585 case CallingConv::ARM_AAPCS_VFP:
1586 case CallingConv::Swift:
1587 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1588 case CallingConv::C:
1589 if (!Subtarget->isAAPCS_ABI())
1590 return CallingConv::ARM_APCS;
1591 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1592 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1593 !isVarArg)
1594 return CallingConv::ARM_AAPCS_VFP;
1595 else
1596 return CallingConv::ARM_AAPCS;
1597 case CallingConv::Fast:
1598 case CallingConv::CXX_FAST_TLS:
1599 if (!Subtarget->isAAPCS_ABI()) {
1600 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1601 return CallingConv::Fast;
1602 return CallingConv::ARM_APCS;
1603 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1604 return CallingConv::ARM_AAPCS_VFP;
1605 else
1606 return CallingConv::ARM_AAPCS;
1607 }
1608}
1609
1610CCAssignFn *ARMTargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1611 bool isVarArg) const {
1612 return CCAssignFnForNode(CC, false, isVarArg);
1613}
1614
1615CCAssignFn *ARMTargetLowering::CCAssignFnForReturn(CallingConv::ID CC,
1616 bool isVarArg) const {
1617 return CCAssignFnForNode(CC, true, isVarArg);
1618}
1619
1620/// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1621/// CallingConvention.
1622CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1623 bool Return,
1624 bool isVarArg) const {
1625 switch (getEffectiveCallingConv(CC, isVarArg)) {
1626 default:
1627 report_fatal_error("Unsupported calling convention");
1628 case CallingConv::ARM_APCS:
1629 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1630 case CallingConv::ARM_AAPCS:
1631 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1632 case CallingConv::ARM_AAPCS_VFP:
1633 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1634 case CallingConv::Fast:
1635 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1636 case CallingConv::GHC:
1637 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1638 case CallingConv::PreserveMost:
1639 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1640 }
1641}
1642
1643/// LowerCallResult - Lower the result values of a call into the
1644/// appropriate copies out of appropriate physical registers.
1645SDValue ARMTargetLowering::LowerCallResult(
1646 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1647 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1648 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1649 SDValue ThisVal) const {
1650 // Assign locations to each value returned by this call.
1651 SmallVector<CCValAssign, 16> RVLocs;
1652 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1653 *DAG.getContext());
1654 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForReturn(CallConv, isVarArg));
1655
1656 // Copy all of the result registers out of their specified physreg.
1657 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1658 CCValAssign VA = RVLocs[i];
1659
1660 // Pass 'this' value directly from the argument to return value, to avoid
1661 // reg unit interference
1662 if (i == 0 && isThisReturn) {
1663 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1664, __extension__ __PRETTY_FUNCTION__))
1664 "unexpected return calling convention register assignment")(static_cast <bool> (!VA.needsCustom() && VA.getLocVT
() == MVT::i32 && "unexpected return calling convention register assignment"
) ? void (0) : __assert_fail ("!VA.needsCustom() && VA.getLocVT() == MVT::i32 && \"unexpected return calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1664, __extension__ __PRETTY_FUNCTION__))
;
1665 InVals.push_back(ThisVal);
1666 continue;
1667 }
1668
1669 SDValue Val;
1670 if (VA.needsCustom()) {
1671 // Handle f64 or half of a v2f64.
1672 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1673 InFlag);
1674 Chain = Lo.getValue(1);
1675 InFlag = Lo.getValue(2);
1676 VA = RVLocs[++i]; // skip ahead to next loc
1677 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1678 InFlag);
1679 Chain = Hi.getValue(1);
1680 InFlag = Hi.getValue(2);
1681 if (!Subtarget->isLittle())
1682 std::swap (Lo, Hi);
1683 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1684
1685 if (VA.getLocVT() == MVT::v2f64) {
1686 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1687 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1688 DAG.getConstant(0, dl, MVT::i32));
1689
1690 VA = RVLocs[++i]; // skip ahead to next loc
1691 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1692 Chain = Lo.getValue(1);
1693 InFlag = Lo.getValue(2);
1694 VA = RVLocs[++i]; // skip ahead to next loc
1695 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1696 Chain = Hi.getValue(1);
1697 InFlag = Hi.getValue(2);
1698 if (!Subtarget->isLittle())
1699 std::swap (Lo, Hi);
1700 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1701 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1702 DAG.getConstant(1, dl, MVT::i32));
1703 }
1704 } else {
1705 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1706 InFlag);
1707 Chain = Val.getValue(1);
1708 InFlag = Val.getValue(2);
1709 }
1710
1711 switch (VA.getLocInfo()) {
1712 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1712)
;
1713 case CCValAssign::Full: break;
1714 case CCValAssign::BCvt:
1715 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1716 break;
1717 }
1718
1719 InVals.push_back(Val);
1720 }
1721
1722 return Chain;
1723}
1724
1725/// LowerMemOpCallTo - Store the argument to the stack.
1726SDValue ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
1727 SDValue Arg, const SDLoc &dl,
1728 SelectionDAG &DAG,
1729 const CCValAssign &VA,
1730 ISD::ArgFlagsTy Flags) const {
1731 unsigned LocMemOffset = VA.getLocMemOffset();
1732 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1733 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1734 StackPtr, PtrOff);
1735 return DAG.getStore(
1736 Chain, dl, Arg, PtrOff,
1737 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
1738}
1739
1740void ARMTargetLowering::PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG,
1741 SDValue Chain, SDValue &Arg,
1742 RegsToPassVector &RegsToPass,
1743 CCValAssign &VA, CCValAssign &NextVA,
1744 SDValue &StackPtr,
1745 SmallVectorImpl<SDValue> &MemOpChains,
1746 ISD::ArgFlagsTy Flags) const {
1747 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1748 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1749 unsigned id = Subtarget->isLittle() ? 0 : 1;
1750 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1751
1752 if (NextVA.isRegLoc())
1753 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1754 else {
1755 assert(NextVA.isMemLoc())(static_cast <bool> (NextVA.isMemLoc()) ? void (0) : __assert_fail
("NextVA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1755, __extension__ __PRETTY_FUNCTION__))
;
1756 if (!StackPtr.getNode())
1757 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1758 getPointerTy(DAG.getDataLayout()));
1759
1760 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1761 dl, DAG, NextVA,
1762 Flags));
1763 }
1764}
1765
1766/// LowerCall - Lowering a call into a callseq_start <-
1767/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1768/// nodes.
1769SDValue
1770ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1771 SmallVectorImpl<SDValue> &InVals) const {
1772 SelectionDAG &DAG = CLI.DAG;
1773 SDLoc &dl = CLI.DL;
1774 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1775 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1776 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1777 SDValue Chain = CLI.Chain;
1778 SDValue Callee = CLI.Callee;
1779 bool &isTailCall = CLI.IsTailCall;
1780 CallingConv::ID CallConv = CLI.CallConv;
1781 bool doesNotRet = CLI.DoesNotReturn;
1782 bool isVarArg = CLI.IsVarArg;
1783
1784 MachineFunction &MF = DAG.getMachineFunction();
1785 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1786 bool isThisReturn = false;
1787 bool isSibCall = false;
1788 auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
1789
1790 // Disable tail calls if they're not supported.
1791 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1792 isTailCall = false;
1793
1794 if (isTailCall) {
1795 // Check if it's really possible to do a tail call.
1796 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1797 isVarArg, isStructRet, MF.getFunction().hasStructRetAttr(),
1798 Outs, OutVals, Ins, DAG);
1799 if (!isTailCall && CLI.CS && CLI.CS.isMustTailCall())
1800 report_fatal_error("failed to perform tail call elimination on a call "
1801 "site marked musttail");
1802 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1803 // detected sibcalls.
1804 if (isTailCall) {
1805 ++NumTailCalls;
1806 isSibCall = true;
1807 }
1808 }
1809
1810 // Analyze operands of the call, assigning locations to each operand.
1811 SmallVector<CCValAssign, 16> ArgLocs;
1812 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1813 *DAG.getContext());
1814 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CallConv, isVarArg));
1815
1816 // Get a count of how many bytes are to be pushed on the stack.
1817 unsigned NumBytes = CCInfo.getNextStackOffset();
1818
1819 // For tail calls, memory operands are available in our caller's stack.
1820 if (isSibCall)
1821 NumBytes = 0;
1822
1823 // Adjust the stack pointer for the new arguments...
1824 // These operations are automatically eliminated by the prolog/epilog pass
1825 if (!isSibCall)
1826 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
1827
1828 SDValue StackPtr =
1829 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1830
1831 RegsToPassVector RegsToPass;
1832 SmallVector<SDValue, 8> MemOpChains;
1833
1834 // Walk the register/memloc assignments, inserting copies/loads. In the case
1835 // of tail call optimization, arguments are handled later.
1836 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1837 i != e;
1838 ++i, ++realArgIdx) {
1839 CCValAssign &VA = ArgLocs[i];
1840 SDValue Arg = OutVals[realArgIdx];
1841 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1842 bool isByVal = Flags.isByVal();
1843
1844 // Promote the value if needed.
1845 switch (VA.getLocInfo()) {
1846 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1846)
;
1847 case CCValAssign::Full: break;
1848 case CCValAssign::SExt:
1849 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1850 break;
1851 case CCValAssign::ZExt:
1852 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1853 break;
1854 case CCValAssign::AExt:
1855 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1856 break;
1857 case CCValAssign::BCvt:
1858 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1859 break;
1860 }
1861
1862 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1863 if (VA.needsCustom()) {
1864 if (VA.getLocVT() == MVT::v2f64) {
1865 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1866 DAG.getConstant(0, dl, MVT::i32));
1867 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1868 DAG.getConstant(1, dl, MVT::i32));
1869
1870 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1871 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1872
1873 VA = ArgLocs[++i]; // skip ahead to next loc
1874 if (VA.isRegLoc()) {
1875 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1876 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1877 } else {
1878 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1878, __extension__ __PRETTY_FUNCTION__))
;
1879
1880 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1881 dl, DAG, VA, Flags));
1882 }
1883 } else {
1884 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1885 StackPtr, MemOpChains, Flags);
1886 }
1887 } else if (VA.isRegLoc()) {
1888 if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
1889 Outs[0].VT == MVT::i32) {
1890 assert(VA.getLocVT() == MVT::i32 &&(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1891, __extension__ __PRETTY_FUNCTION__))
1891 "unexpected calling convention register assignment")(static_cast <bool> (VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment") ? void (
0) : __assert_fail ("VA.getLocVT() == MVT::i32 && \"unexpected calling convention register assignment\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1891, __extension__ __PRETTY_FUNCTION__))
;
1892 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1893, __extension__ __PRETTY_FUNCTION__))
1893 "unexpected use of 'returned'")(static_cast <bool> (!Ins.empty() && Ins[0].VT ==
MVT::i32 && "unexpected use of 'returned'") ? void (
0) : __assert_fail ("!Ins.empty() && Ins[0].VT == MVT::i32 && \"unexpected use of 'returned'\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1893, __extension__ __PRETTY_FUNCTION__))
;
1894 isThisReturn = true;
1895 }
1896 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1897 } else if (isByVal) {
1898 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1898, __extension__ __PRETTY_FUNCTION__))
;
1899 unsigned offset = 0;
1900
1901 // True if this byval aggregate will be split between registers
1902 // and memory.
1903 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1904 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1905
1906 if (CurByValIdx < ByValArgsCount) {
1907
1908 unsigned RegBegin, RegEnd;
1909 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1910
1911 EVT PtrVT =
1912 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1913 unsigned int i, j;
1914 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1915 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1916 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1917 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1918 MachinePointerInfo(),
1919 DAG.InferPtrAlignment(AddArg));
1920 MemOpChains.push_back(Load.getValue(1));
1921 RegsToPass.push_back(std::make_pair(j, Load));
1922 }
1923
1924 // If parameter size outsides register area, "offset" value
1925 // helps us to calculate stack slot for remained part properly.
1926 offset = RegEnd - RegBegin;
1927
1928 CCInfo.nextInRegsParam();
1929 }
1930
1931 if (Flags.getByValSize() > 4*offset) {
1932 auto PtrVT = getPointerTy(DAG.getDataLayout());
1933 unsigned LocMemOffset = VA.getLocMemOffset();
1934 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1935 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1936 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1937 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1938 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1939 MVT::i32);
1940 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1941 MVT::i32);
1942
1943 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1944 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1945 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1946 Ops));
1947 }
1948 } else if (!isSibCall) {
1949 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 1949, __extension__ __PRETTY_FUNCTION__))
;
1950
1951 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1952 dl, DAG, VA, Flags));
1953 }
1954 }
1955
1956 if (!MemOpChains.empty())
1957 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1958
1959 // Build a sequence of copy-to-reg nodes chained together with token chain
1960 // and flag operands which copy the outgoing args into the appropriate regs.
1961 SDValue InFlag;
1962 // Tail call byval lowering might overwrite argument registers so in case of
1963 // tail call optimization the copies to registers are lowered later.
1964 if (!isTailCall)
1965 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1966 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1967 RegsToPass[i].second, InFlag);
1968 InFlag = Chain.getValue(1);
1969 }
1970
1971 // For tail calls lower the arguments to the 'real' stack slot.
1972 if (isTailCall) {
1973 // Force all the incoming stack arguments to be loaded from the stack
1974 // before any new outgoing arguments are stored to the stack, because the
1975 // outgoing stack slots may alias the incoming argument stack slots, and
1976 // the alias isn't otherwise explicit. This is slightly more conservative
1977 // than necessary, because it means that each store effectively depends
1978 // on every argument instead of just those arguments it would clobber.
1979
1980 // Do not flag preceding copytoreg stuff together with the following stuff.
1981 InFlag = SDValue();
1982 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1983 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1984 RegsToPass[i].second, InFlag);
1985 InFlag = Chain.getValue(1);
1986 }
1987 InFlag = SDValue();
1988 }
1989
1990 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1991 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1992 // node so that legalize doesn't hack it.
1993 bool isDirect = false;
1994
1995 const TargetMachine &TM = getTargetMachine();
1996 const Module *Mod = MF.getFunction().getParent();
1997 const GlobalValue *GV = nullptr;
1998 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1999 GV = G->getGlobal();
2000 bool isStub =
2001 !TM.shouldAssumeDSOLocal(*Mod, GV) && Subtarget->isTargetMachO();
2002
2003 bool isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
2004 bool isLocalARMFunc = false;
2005 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2006 auto PtrVt = getPointerTy(DAG.getDataLayout());
2007
2008 if (Subtarget->genLongCalls()) {
2009 assert((!isPositionIndependent() || Subtarget->isTargetWindows()) &&(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2010, __extension__ __PRETTY_FUNCTION__))
2010 "long-calls codegen is not position independent!")(static_cast <bool> ((!isPositionIndependent() || Subtarget
->isTargetWindows()) && "long-calls codegen is not position independent!"
) ? void (0) : __assert_fail ("(!isPositionIndependent() || Subtarget->isTargetWindows()) && \"long-calls codegen is not position independent!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2010, __extension__ __PRETTY_FUNCTION__))
;
2011 // Handle a global address or an external symbol. If it's not one of
2012 // those, the target's already in a register, so we don't need to do
2013 // anything extra.
2014 if (isa<GlobalAddressSDNode>(Callee)) {
2015 // Create a constant pool entry for the callee address
2016 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2017 ARMConstantPoolValue *CPV =
2018 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
2019
2020 // Get the address of the callee into a register
2021 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2022 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2023 Callee = DAG.getLoad(
2024 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2025 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2026 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
2027 const char *Sym = S->getSymbol();
2028
2029 // Create a constant pool entry for the callee address
2030 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2031 ARMConstantPoolValue *CPV =
2032 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2033 ARMPCLabelIndex, 0);
2034 // Get the address of the callee into a register
2035 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2036 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2037 Callee = DAG.getLoad(
2038 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2039 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2040 }
2041 } else if (isa<GlobalAddressSDNode>(Callee)) {
2042 // If we're optimizing for minimum size and the function is called three or
2043 // more times in this block, we can improve codesize by calling indirectly
2044 // as BLXr has a 16-bit encoding.
2045 auto *GV = cast<GlobalAddressSDNode>(Callee)->getGlobal();
2046 auto *BB = CLI.CS.getParent();
2047 bool PreferIndirect =
2048 Subtarget->isThumb() && MF.getFunction().optForMinSize() &&
2049 count_if(GV->users(), [&BB](const User *U) {
2050 return isa<Instruction>(U) && cast<Instruction>(U)->getParent() == BB;
2051 }) > 2;
2052
2053 if (!PreferIndirect) {
2054 isDirect = true;
2055 bool isDef = GV->isStrongDefinitionForLinker();
2056
2057 // ARM call to a local ARM function is predicable.
2058 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
2059 // tBX takes a register source operand.
2060 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2061 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?")(static_cast <bool> (Subtarget->isTargetMachO() &&
"WrapperPIC use on non-MachO?") ? void (0) : __assert_fail (
"Subtarget->isTargetMachO() && \"WrapperPIC use on non-MachO?\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2061, __extension__ __PRETTY_FUNCTION__))
;
2062 Callee = DAG.getNode(
2063 ARMISD::WrapperPIC, dl, PtrVt,
2064 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
2065 Callee = DAG.getLoad(
2066 PtrVt, dl, DAG.getEntryNode(), Callee,
2067 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2068 /* Alignment = */ 0, MachineMemOperand::MODereferenceable |
2069 MachineMemOperand::MOInvariant);
2070 } else if (Subtarget->isTargetCOFF()) {
2071 assert(Subtarget->isTargetWindows() &&(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2072, __extension__ __PRETTY_FUNCTION__))
2072 "Windows is the only supported COFF target")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows is the only supported COFF target") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"Windows is the only supported COFF target\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2072, __extension__ __PRETTY_FUNCTION__))
;
2073 unsigned TargetFlags = GV->hasDLLImportStorageClass()
2074 ? ARMII::MO_DLLIMPORT
2075 : ARMII::MO_NO_FLAG;
2076 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0,
2077 TargetFlags);
2078 if (GV->hasDLLImportStorageClass())
2079 Callee =
2080 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
2081 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
2082 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2083 } else {
2084 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, 0);
2085 }
2086 }
2087 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2088 isDirect = true;
2089 // tBX takes a register source operand.
2090 const char *Sym = S->getSymbol();
2091 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
2092 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2093 ARMConstantPoolValue *CPV =
2094 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
2095 ARMPCLabelIndex, 4);
2096 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
2097 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2098 Callee = DAG.getLoad(
2099 PtrVt, dl, DAG.getEntryNode(), CPAddr,
2100 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2101 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2102 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
2103 } else {
2104 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, 0);
2105 }
2106 }
2107
2108 // FIXME: handle tail calls differently.
2109 unsigned CallOpc;
2110 if (Subtarget->isThumb()) {
2111 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
2112 CallOpc = ARMISD::CALL_NOLINK;
2113 else
2114 CallOpc = ARMISD::CALL;
2115 } else {
2116 if (!isDirect && !Subtarget->hasV5TOps())
2117 CallOpc = ARMISD::CALL_NOLINK;
2118 else if (doesNotRet && isDirect && Subtarget->hasRetAddrStack() &&
2119 // Emit regular call when code size is the priority
2120 !MF.getFunction().optForMinSize())
2121 // "mov lr, pc; b _foo" to avoid confusing the RSP
2122 CallOpc = ARMISD::CALL_NOLINK;
2123 else
2124 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
2125 }
2126
2127 std::vector<SDValue> Ops;
2128 Ops.push_back(Chain);
2129 Ops.push_back(Callee);
2130
2131 // Add argument registers to the end of the list so that they are known live
2132 // into the call.
2133 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2134 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2135 RegsToPass[i].second.getValueType()));
2136
2137 // Add a register mask operand representing the call-preserved registers.
2138 if (!isTailCall) {
2139 const uint32_t *Mask;
2140 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
2141 if (isThisReturn) {
2142 // For 'this' returns, use the R0-preserving mask if applicable
2143 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
2144 if (!Mask) {
2145 // Set isThisReturn to false if the calling convention is not one that
2146 // allows 'returned' to be modeled in this way, so LowerCallResult does
2147 // not try to pass 'this' straight through
2148 isThisReturn = false;
2149 Mask = ARI->getCallPreservedMask(MF, CallConv);
2150 }
2151 } else
2152 Mask = ARI->getCallPreservedMask(MF, CallConv);
2153
2154 assert(Mask && "Missing call preserved mask for calling convention")(static_cast <bool> (Mask && "Missing call preserved mask for calling convention"
) ? void (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2154, __extension__ __PRETTY_FUNCTION__))
;
2155 Ops.push_back(DAG.getRegisterMask(Mask));
2156 }
2157
2158 if (InFlag.getNode())
2159 Ops.push_back(InFlag);
2160
2161 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2162 if (isTailCall) {
2163 MF.getFrameInfo().setHasTailCall();
2164 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
2165 }
2166
2167 // Returns a chain and a flag for retval copy to use.
2168 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
2169 InFlag = Chain.getValue(1);
2170
2171 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
2172 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
2173 if (!Ins.empty())
2174 InFlag = Chain.getValue(1);
2175
2176 // Handle result values, copying them out of physregs into vregs that we
2177 // return.
2178 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
2179 InVals, isThisReturn,
2180 isThisReturn ? OutVals[0] : SDValue());
2181}
2182
2183/// HandleByVal - Every parameter *after* a byval parameter is passed
2184/// on the stack. Remember the next parameter register to allocate,
2185/// and then confiscate the rest of the parameter registers to insure
2186/// this.
2187void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
2188 unsigned Align) const {
2189 // Byval (as with any stack) slots are always at least 4 byte aligned.
2190 Align = std::max(Align, 4U);
2191
2192 unsigned Reg = State->AllocateReg(GPRArgRegs);
2193 if (!Reg)
2194 return;
2195
2196 unsigned AlignInRegs = Align / 4;
2197 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
2198 for (unsigned i = 0; i < Waste; ++i)
2199 Reg = State->AllocateReg(GPRArgRegs);
2200
2201 if (!Reg)
2202 return;
2203
2204 unsigned Excess = 4 * (ARM::R4 - Reg);
2205
2206 // Special case when NSAA != SP and parameter size greater than size of
2207 // all remained GPR regs. In that case we can't split parameter, we must
2208 // send it to stack. We also must set NCRN to R4, so waste all
2209 // remained registers.
2210 const unsigned NSAAOffset = State->getNextStackOffset();
2211 if (NSAAOffset != 0 && Size > Excess) {
2212 while (State->AllocateReg(GPRArgRegs))
2213 ;
2214 return;
2215 }
2216
2217 // First register for byval parameter is the first register that wasn't
2218 // allocated before this method call, so it would be "reg".
2219 // If parameter is small enough to be saved in range [reg, r4), then
2220 // the end (first after last) register would be reg + param-size-in-regs,
2221 // else parameter would be splitted between registers and stack,
2222 // end register would be r4 in this case.
2223 unsigned ByValRegBegin = Reg;
2224 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2225 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2226 // Note, first register is allocated in the beginning of function already,
2227 // allocate remained amount of registers we need.
2228 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2229 State->AllocateReg(GPRArgRegs);
2230 // A byval parameter that is split between registers and memory needs its
2231 // size truncated here.
2232 // In the case where the entire structure fits in registers, we set the
2233 // size in memory to zero.
2234 Size = std::max<int>(Size - Excess, 0);
2235}
2236
2237/// MatchingStackOffset - Return true if the given stack call argument is
2238/// already available in the same position (relatively) of the caller's
2239/// incoming argument stack.
2240static
2241bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2242 MachineFrameInfo &MFI, const MachineRegisterInfo *MRI,
2243 const TargetInstrInfo *TII) {
2244 unsigned Bytes = Arg.getValueSizeInBits() / 8;
2245 int FI = std::numeric_limits<int>::max();
2246 if (Arg.getOpcode() == ISD::CopyFromReg) {
2247 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2248 if (!TargetRegisterInfo::isVirtualRegister(VR))
2249 return false;
2250 MachineInstr *Def = MRI->getVRegDef(VR);
2251 if (!Def)
2252 return false;
2253 if (!Flags.isByVal()) {
2254 if (!TII->isLoadFromStackSlot(*Def, FI))
2255 return false;
2256 } else {
2257 return false;
2258 }
2259 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2260 if (Flags.isByVal())
2261 // ByVal argument is passed in as a pointer but it's now being
2262 // dereferenced. e.g.
2263 // define @foo(%struct.X* %A) {
2264 // tail call @bar(%struct.X* byval %A)
2265 // }
2266 return false;
2267 SDValue Ptr = Ld->getBasePtr();
2268 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2269 if (!FINode)
2270 return false;
2271 FI = FINode->getIndex();
2272 } else
2273 return false;
2274
2275 assert(FI != std::numeric_limits<int>::max())(static_cast <bool> (FI != std::numeric_limits<int>
::max()) ? void (0) : __assert_fail ("FI != std::numeric_limits<int>::max()"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2275, __extension__ __PRETTY_FUNCTION__))
;
2276 if (!MFI.isFixedObjectIndex(FI))
2277 return false;
2278 return Offset == MFI.getObjectOffset(FI) && Bytes == MFI.getObjectSize(FI);
2279}
2280
2281/// IsEligibleForTailCallOptimization - Check whether the call is eligible
2282/// for tail call optimization. Targets which want to do tail call
2283/// optimization should implement this function.
2284bool
2285ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2286 CallingConv::ID CalleeCC,
2287 bool isVarArg,
2288 bool isCalleeStructRet,
2289 bool isCallerStructRet,
2290 const SmallVectorImpl<ISD::OutputArg> &Outs,
2291 const SmallVectorImpl<SDValue> &OutVals,
2292 const SmallVectorImpl<ISD::InputArg> &Ins,
2293 SelectionDAG& DAG) const {
2294 MachineFunction &MF = DAG.getMachineFunction();
2295 const Function &CallerF = MF.getFunction();
2296 CallingConv::ID CallerCC = CallerF.getCallingConv();
2297
2298 assert(Subtarget->supportsTailCall())(static_cast <bool> (Subtarget->supportsTailCall()) ?
void (0) : __assert_fail ("Subtarget->supportsTailCall()"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2298, __extension__ __PRETTY_FUNCTION__))
;
2299
2300 // Tail calls to function pointers cannot be optimized for Thumb1 if the args
2301 // to the call take up r0-r3. The reason is that there are no legal registers
2302 // left to hold the pointer to the function to be called.
2303 if (Subtarget->isThumb1Only() && Outs.size() >= 4 &&
2304 !isa<GlobalAddressSDNode>(Callee.getNode()))
2305 return false;
2306
2307 // Look for obvious safe cases to perform tail call optimization that do not
2308 // require ABI changes. This is what gcc calls sibcall.
2309
2310 // Exception-handling functions need a special set of instructions to indicate
2311 // a return to the hardware. Tail-calling another function would probably
2312 // break this.
2313 if (CallerF.hasFnAttribute("interrupt"))
2314 return false;
2315
2316 // Also avoid sibcall optimization if either caller or callee uses struct
2317 // return semantics.
2318 if (isCalleeStructRet || isCallerStructRet)
2319 return false;
2320
2321 // Externally-defined functions with weak linkage should not be
2322 // tail-called on ARM when the OS does not support dynamic
2323 // pre-emption of symbols, as the AAELF spec requires normal calls
2324 // to undefined weak functions to be replaced with a NOP or jump to the
2325 // next instruction. The behaviour of branch instructions in this
2326 // situation (as used for tail calls) is implementation-defined, so we
2327 // cannot rely on the linker replacing the tail call with a return.
2328 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2329 const GlobalValue *GV = G->getGlobal();
2330 const Triple &TT = getTargetMachine().getTargetTriple();
2331 if (GV->hasExternalWeakLinkage() &&
2332 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2333 return false;
2334 }
2335
2336 // Check that the call results are passed in the same way.
2337 LLVMContext &C = *DAG.getContext();
2338 if (!CCState::resultsCompatible(CalleeCC, CallerCC, MF, C, Ins,
2339 CCAssignFnForReturn(CalleeCC, isVarArg),
2340 CCAssignFnForReturn(CallerCC, isVarArg)))
2341 return false;
2342 // The callee has to preserve all registers the caller needs to preserve.
2343 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2344 const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
2345 if (CalleeCC != CallerCC) {
2346 const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
2347 if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
2348 return false;
2349 }
2350
2351 // If Caller's vararg or byval argument has been split between registers and
2352 // stack, do not perform tail call, since part of the argument is in caller's
2353 // local frame.
2354 const ARMFunctionInfo *AFI_Caller = MF.getInfo<ARMFunctionInfo>();
2355 if (AFI_Caller->getArgRegsSaveSize())
2356 return false;
2357
2358 // If the callee takes no arguments then go on to check the results of the
2359 // call.
2360 if (!Outs.empty()) {
2361 // Check if stack adjustment is needed. For now, do not do this if any
2362 // argument is passed on the stack.
2363 SmallVector<CCValAssign, 16> ArgLocs;
2364 CCState CCInfo(CalleeCC, isVarArg, MF, ArgLocs, C);
2365 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2366 if (CCInfo.getNextStackOffset()) {
2367 // Check if the arguments are already laid out in the right way as
2368 // the caller's fixed stack objects.
2369 MachineFrameInfo &MFI = MF.getFrameInfo();
2370 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2371 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2372 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2373 i != e;
2374 ++i, ++realArgIdx) {
2375 CCValAssign &VA = ArgLocs[i];
2376 EVT RegVT = VA.getLocVT();
2377 SDValue Arg = OutVals[realArgIdx];
2378 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2379 if (VA.getLocInfo() == CCValAssign::Indirect)
2380 return false;
2381 if (VA.needsCustom()) {
2382 // f64 and vector types are split into multiple registers or
2383 // register/stack-slot combinations. The types will not match
2384 // the registers; give up on memory f64 refs until we figure
2385 // out what to do about this.
2386 if (!VA.isRegLoc())
2387 return false;
2388 if (!ArgLocs[++i].isRegLoc())
2389 return false;
2390 if (RegVT == MVT::v2f64) {
2391 if (!ArgLocs[++i].isRegLoc())
2392 return false;
2393 if (!ArgLocs[++i].isRegLoc())
2394 return false;
2395 }
2396 } else if (!VA.isRegLoc()) {
2397 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2398 MFI, MRI, TII))
2399 return false;
2400 }
2401 }
2402 }
2403
2404 const MachineRegisterInfo &MRI = MF.getRegInfo();
2405 if (!parametersInCSRMatch(MRI, CallerPreserved, ArgLocs, OutVals))
2406 return false;
2407 }
2408
2409 return true;
2410}
2411
2412bool
2413ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2414 MachineFunction &MF, bool isVarArg,
2415 const SmallVectorImpl<ISD::OutputArg> &Outs,
2416 LLVMContext &Context) const {
2417 SmallVector<CCValAssign, 16> RVLocs;
2418 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2419 return CCInfo.CheckReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2420}
2421
2422static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2423 const SDLoc &DL, SelectionDAG &DAG) {
2424 const MachineFunction &MF = DAG.getMachineFunction();
2425 const Function &F = MF.getFunction();
2426
2427 StringRef IntKind = F.getFnAttribute("interrupt").getValueAsString();
2428
2429 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2430 // version of the "preferred return address". These offsets affect the return
2431 // instruction if this is a return from PL1 without hypervisor extensions.
2432 // IRQ/FIQ: +4 "subs pc, lr, #4"
2433 // SWI: 0 "subs pc, lr, #0"
2434 // ABORT: +4 "subs pc, lr, #4"
2435 // UNDEF: +4/+2 "subs pc, lr, #0"
2436 // UNDEF varies depending on where the exception came from ARM or Thumb
2437 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2438
2439 int64_t LROffset;
2440 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2441 IntKind == "ABORT")
2442 LROffset = 4;
2443 else if (IntKind == "SWI" || IntKind == "UNDEF")
2444 LROffset = 0;
2445 else
2446 report_fatal_error("Unsupported interrupt attribute. If present, value "
2447 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2448
2449 RetOps.insert(RetOps.begin() + 1,
2450 DAG.getConstant(LROffset, DL, MVT::i32, false));
2451
2452 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2453}
2454
2455SDValue
2456ARMTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2457 bool isVarArg,
2458 const SmallVectorImpl<ISD::OutputArg> &Outs,
2459 const SmallVectorImpl<SDValue> &OutVals,
2460 const SDLoc &dl, SelectionDAG &DAG) const {
2461 // CCValAssign - represent the assignment of the return value to a location.
2462 SmallVector<CCValAssign, 16> RVLocs;
2463
2464 // CCState - Info about the registers and stack slots.
2465 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2466 *DAG.getContext());
2467
2468 // Analyze outgoing return values.
2469 CCInfo.AnalyzeReturn(Outs, CCAssignFnForReturn(CallConv, isVarArg));
2470
2471 SDValue Flag;
2472 SmallVector<SDValue, 4> RetOps;
2473 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2474 bool isLittleEndian = Subtarget->isLittle();
2475
2476 MachineFunction &MF = DAG.getMachineFunction();
2477 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2478 AFI->setReturnRegsCount(RVLocs.size());
2479
2480 // Copy the result values into the output registers.
2481 for (unsigned i = 0, realRVLocIdx = 0;
2482 i != RVLocs.size();
2483 ++i, ++realRVLocIdx) {
2484 CCValAssign &VA = RVLocs[i];
2485 assert(VA.isRegLoc() && "Can only return in registers!")(static_cast <bool> (VA.isRegLoc() && "Can only return in registers!"
) ? void (0) : __assert_fail ("VA.isRegLoc() && \"Can only return in registers!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2485, __extension__ __PRETTY_FUNCTION__))
;
2486
2487 SDValue Arg = OutVals[realRVLocIdx];
2488 bool ReturnF16 = false;
2489
2490 if (Subtarget->hasFullFP16() && Subtarget->isTargetHardFloat()) {
2491 // Half-precision return values can be returned like this:
2492 //
2493 // t11 f16 = fadd ...
2494 // t12: i16 = bitcast t11
2495 // t13: i32 = zero_extend t12
2496 // t14: f32 = bitcast t13 <~~~~~~~ Arg
2497 //
2498 // to avoid code generation for bitcasts, we simply set Arg to the node
2499 // that produces the f16 value, t11 in this case.
2500 //
2501 if (Arg.getValueType() == MVT::f32 && Arg.getOpcode() == ISD::BITCAST) {
2502 SDValue ZE = Arg.getOperand(0);
2503 if (ZE.getOpcode() == ISD::ZERO_EXTEND && ZE.getValueType() == MVT::i32) {
2504 SDValue BC = ZE.getOperand(0);
2505 if (BC.getOpcode() == ISD::BITCAST && BC.getValueType() == MVT::i16) {
2506 Arg = BC.getOperand(0);
2507 ReturnF16 = true;
2508 }
2509 }
2510 }
2511 }
2512
2513 switch (VA.getLocInfo()) {
2514 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2514)
;
2515 case CCValAssign::Full: break;
2516 case CCValAssign::BCvt:
2517 if (!ReturnF16)
2518 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2519 break;
2520 }
2521
2522 if (VA.needsCustom()) {
2523 if (VA.getLocVT() == MVT::v2f64) {
2524 // Extract the first half and return it in two registers.
2525 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2526 DAG.getConstant(0, dl, MVT::i32));
2527 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2528 DAG.getVTList(MVT::i32, MVT::i32), Half);
2529
2530 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2531 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2532 Flag);
2533 Flag = Chain.getValue(1);
2534 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2535 VA = RVLocs[++i]; // skip ahead to next loc
2536 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2537 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2538 Flag);
2539 Flag = Chain.getValue(1);
2540 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2541 VA = RVLocs[++i]; // skip ahead to next loc
2542
2543 // Extract the 2nd half and fall through to handle it as an f64 value.
2544 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2545 DAG.getConstant(1, dl, MVT::i32));
2546 }
2547 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2548 // available.
2549 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2550 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2551 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2552 fmrrd.getValue(isLittleEndian ? 0 : 1),
2553 Flag);
2554 Flag = Chain.getValue(1);
2555 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2556 VA = RVLocs[++i]; // skip ahead to next loc
2557 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2558 fmrrd.getValue(isLittleEndian ? 1 : 0),
2559 Flag);
2560 } else
2561 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2562
2563 // Guarantee that all emitted copies are
2564 // stuck together, avoiding something bad.
2565 Flag = Chain.getValue(1);
2566 RetOps.push_back(DAG.getRegister(VA.getLocReg(),
2567 ReturnF16 ? MVT::f16 : VA.getLocVT()));
2568 }
2569 const ARMBaseRegisterInfo *TRI = Subtarget->getRegisterInfo();
2570 const MCPhysReg *I =
2571 TRI->getCalleeSavedRegsViaCopy(&DAG.getMachineFunction());
2572 if (I) {
2573 for (; *I; ++I) {
2574 if (ARM::GPRRegClass.contains(*I))
2575 RetOps.push_back(DAG.getRegister(*I, MVT::i32));
2576 else if (ARM::DPRRegClass.contains(*I))
2577 RetOps.push_back(DAG.getRegister(*I, MVT::getFloatingPointVT(64)));
2578 else
2579 llvm_unreachable("Unexpected register class in CSRsViaCopy!")::llvm::llvm_unreachable_internal("Unexpected register class in CSRsViaCopy!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2579)
;
2580 }
2581 }
2582
2583 // Update chain and glue.
2584 RetOps[0] = Chain;
2585 if (Flag.getNode())
2586 RetOps.push_back(Flag);
2587
2588 // CPUs which aren't M-class use a special sequence to return from
2589 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2590 // though we use "subs pc, lr, #N").
2591 //
2592 // M-class CPUs actually use a normal return sequence with a special
2593 // (hardware-provided) value in LR, so the normal code path works.
2594 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt") &&
2595 !Subtarget->isMClass()) {
2596 if (Subtarget->isThumb1Only())
2597 report_fatal_error("interrupt attribute is not supported in Thumb1");
2598 return LowerInterruptReturn(RetOps, dl, DAG);
2599 }
2600
2601 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2602}
2603
2604bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2605 if (N->getNumValues() != 1)
2606 return false;
2607 if (!N->hasNUsesOfValue(1, 0))
2608 return false;
2609
2610 SDValue TCChain = Chain;
2611 SDNode *Copy = *N->use_begin();
2612 if (Copy->getOpcode() == ISD::CopyToReg) {
2613 // If the copy has a glue operand, we conservatively assume it isn't safe to
2614 // perform a tail call.
2615 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2616 return false;
2617 TCChain = Copy->getOperand(0);
2618 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2619 SDNode *VMov = Copy;
2620 // f64 returned in a pair of GPRs.
2621 SmallPtrSet<SDNode*, 2> Copies;
2622 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2623 UI != UE; ++UI) {
2624 if (UI->getOpcode() != ISD::CopyToReg)
2625 return false;
2626 Copies.insert(*UI);
2627 }
2628 if (Copies.size() > 2)
2629 return false;
2630
2631 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2632 UI != UE; ++UI) {
2633 SDValue UseChain = UI->getOperand(0);
2634 if (Copies.count(UseChain.getNode()))
2635 // Second CopyToReg
2636 Copy = *UI;
2637 else {
2638 // We are at the top of this chain.
2639 // If the copy has a glue operand, we conservatively assume it
2640 // isn't safe to perform a tail call.
2641 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2642 return false;
2643 // First CopyToReg
2644 TCChain = UseChain;
2645 }
2646 }
2647 } else if (Copy->getOpcode() == ISD::BITCAST) {
2648 // f32 returned in a single GPR.
2649 if (!Copy->hasOneUse())
2650 return false;
2651 Copy = *Copy->use_begin();
2652 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2653 return false;
2654 // If the copy has a glue operand, we conservatively assume it isn't safe to
2655 // perform a tail call.
2656 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2657 return false;
2658 TCChain = Copy->getOperand(0);
2659 } else {
2660 return false;
2661 }
2662
2663 bool HasRet = false;
2664 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2665 UI != UE; ++UI) {
2666 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2667 UI->getOpcode() != ARMISD::INTRET_FLAG)
2668 return false;
2669 HasRet = true;
2670 }
2671
2672 if (!HasRet)
2673 return false;
2674
2675 Chain = TCChain;
2676 return true;
2677}
2678
2679bool ARMTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
2680 if (!Subtarget->supportsTailCall())
2681 return false;
2682
2683 auto Attr =
2684 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2685 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2686 return false;
2687
2688 return true;
2689}
2690
2691// Trying to write a 64 bit value so need to split into two 32 bit values first,
2692// and pass the lower and high parts through.
2693static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2694 SDLoc DL(Op);
2695 SDValue WriteValue = Op->getOperand(2);
2696
2697 // This function is only supposed to be called for i64 type argument.
2698 assert(WriteValue.getValueType() == MVT::i64(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2699, __extension__ __PRETTY_FUNCTION__))
2699 && "LowerWRITE_REGISTER called for non-i64 type argument.")(static_cast <bool> (WriteValue.getValueType() == MVT::
i64 && "LowerWRITE_REGISTER called for non-i64 type argument."
) ? void (0) : __assert_fail ("WriteValue.getValueType() == MVT::i64 && \"LowerWRITE_REGISTER called for non-i64 type argument.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2699, __extension__ __PRETTY_FUNCTION__))
;
2700
2701 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2702 DAG.getConstant(0, DL, MVT::i32));
2703 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2704 DAG.getConstant(1, DL, MVT::i32));
2705 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2706 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2707}
2708
2709// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2710// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2711// one of the above mentioned nodes. It has to be wrapped because otherwise
2712// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2713// be used to form addressing mode. These wrapped nodes will be selected
2714// into MOVi.
2715SDValue ARMTargetLowering::LowerConstantPool(SDValue Op,
2716 SelectionDAG &DAG) const {
2717 EVT PtrVT = Op.getValueType();
2718 // FIXME there is no actual debug info here
2719 SDLoc dl(Op);
2720 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2721 SDValue Res;
2722
2723 // When generating execute-only code Constant Pools must be promoted to the
2724 // global data section. It's a bit ugly that we can't share them across basic
2725 // blocks, but this way we guarantee that execute-only behaves correct with
2726 // position-independent addressing modes.
2727 if (Subtarget->genExecuteOnly()) {
2728 auto AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2729 auto T = const_cast<Type*>(CP->getType());
2730 auto C = const_cast<Constant*>(CP->getConstVal());
2731 auto M = const_cast<Module*>(DAG.getMachineFunction().
2732 getFunction().getParent());
2733 auto GV = new GlobalVariable(
2734 *M, T, /*isConst=*/true, GlobalVariable::InternalLinkage, C,
2735 Twine(DAG.getDataLayout().getPrivateGlobalPrefix()) + "CP" +
2736 Twine(DAG.getMachineFunction().getFunctionNumber()) + "_" +
2737 Twine(AFI->createPICLabelUId())
2738 );
2739 SDValue GA = DAG.getTargetGlobalAddress(dyn_cast<GlobalValue>(GV),
2740 dl, PtrVT);
2741 return LowerGlobalAddress(GA, DAG);
2742 }
2743
2744 if (CP->isMachineConstantPoolEntry())
2745 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2746 CP->getAlignment());
2747 else
2748 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2749 CP->getAlignment());
2750 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2751}
2752
2753unsigned ARMTargetLowering::getJumpTableEncoding() const {
2754 return MachineJumpTableInfo::EK_Inline;
2755}
2756
2757SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2758 SelectionDAG &DAG) const {
2759 MachineFunction &MF = DAG.getMachineFunction();
2760 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2761 unsigned ARMPCLabelIndex = 0;
2762 SDLoc DL(Op);
2763 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2764 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2765 SDValue CPAddr;
2766 bool IsPositionIndependent = isPositionIndependent() || Subtarget->isROPI();
2767 if (!IsPositionIndependent) {
2768 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2769 } else {
2770 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2771 ARMPCLabelIndex = AFI->createPICLabelUId();
2772 ARMConstantPoolValue *CPV =
2773 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2774 ARMCP::CPBlockAddress, PCAdj);
2775 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2776 }
2777 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2778 SDValue Result = DAG.getLoad(
2779 PtrVT, DL, DAG.getEntryNode(), CPAddr,
2780 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2781 if (!IsPositionIndependent)
2782 return Result;
2783 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2784 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2785}
2786
2787/// \brief Convert a TLS address reference into the correct sequence of loads
2788/// and calls to compute the variable's address for Darwin, and return an
2789/// SDValue containing the final node.
2790
2791/// Darwin only has one TLS scheme which must be capable of dealing with the
2792/// fully general situation, in the worst case. This means:
2793/// + "extern __thread" declaration.
2794/// + Defined in a possibly unknown dynamic library.
2795///
2796/// The general system is that each __thread variable has a [3 x i32] descriptor
2797/// which contains information used by the runtime to calculate the address. The
2798/// only part of this the compiler needs to know about is the first word, which
2799/// contains a function pointer that must be called with the address of the
2800/// entire descriptor in "r0".
2801///
2802/// Since this descriptor may be in a different unit, in general access must
2803/// proceed along the usual ARM rules. A common sequence to produce is:
2804///
2805/// movw rT1, :lower16:_var$non_lazy_ptr
2806/// movt rT1, :upper16:_var$non_lazy_ptr
2807/// ldr r0, [rT1]
2808/// ldr rT2, [r0]
2809/// blx rT2
2810/// [...address now in r0...]
2811SDValue
2812ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2813 SelectionDAG &DAG) const {
2814 assert(Subtarget->isTargetDarwin() &&(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2815, __extension__ __PRETTY_FUNCTION__))
2815 "This function expects a Darwin target")(static_cast <bool> (Subtarget->isTargetDarwin() &&
"This function expects a Darwin target") ? void (0) : __assert_fail
("Subtarget->isTargetDarwin() && \"This function expects a Darwin target\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2815, __extension__ __PRETTY_FUNCTION__))
;
2816 SDLoc DL(Op);
2817
2818 // First step is to get the address of the actua global symbol. This is where
2819 // the TLS descriptor lives.
2820 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2821
2822 // The first entry in the descriptor is a function pointer that we must call
2823 // to obtain the address of the variable.
2824 SDValue Chain = DAG.getEntryNode();
2825 SDValue FuncTLVGet = DAG.getLoad(
2826 MVT::i32, DL, Chain, DescAddr,
2827 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2828 /* Alignment = */ 4,
2829 MachineMemOperand::MONonTemporal | MachineMemOperand::MODereferenceable |
2830 MachineMemOperand::MOInvariant);
2831 Chain = FuncTLVGet.getValue(1);
2832
2833 MachineFunction &F = DAG.getMachineFunction();
2834 MachineFrameInfo &MFI = F.getFrameInfo();
2835 MFI.setAdjustsStack(true);
2836
2837 // TLS calls preserve all registers except those that absolutely must be
2838 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2839 // silly).
2840 auto TRI =
2841 getTargetMachine().getSubtargetImpl(F.getFunction())->getRegisterInfo();
2842 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2843 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2844
2845 // Finally, we can make the call. This is just a degenerate version of a
2846 // normal AArch64 call node: r0 takes the address of the descriptor, and
2847 // returns the address of the variable in this thread.
2848 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2849 Chain =
2850 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2851 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2852 DAG.getRegisterMask(Mask), Chain.getValue(1));
2853 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2854}
2855
2856SDValue
2857ARMTargetLowering::LowerGlobalTLSAddressWindows(SDValue Op,
2858 SelectionDAG &DAG) const {
2859 assert(Subtarget->isTargetWindows() && "Windows specific TLS lowering")(static_cast <bool> (Subtarget->isTargetWindows() &&
"Windows specific TLS lowering") ? void (0) : __assert_fail (
"Subtarget->isTargetWindows() && \"Windows specific TLS lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2859, __extension__ __PRETTY_FUNCTION__))
;
2860
2861 SDValue Chain = DAG.getEntryNode();
2862 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2863 SDLoc DL(Op);
2864
2865 // Load the current TEB (thread environment block)
2866 SDValue Ops[] = {Chain,
2867 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
2868 DAG.getConstant(15, DL, MVT::i32),
2869 DAG.getConstant(0, DL, MVT::i32),
2870 DAG.getConstant(13, DL, MVT::i32),
2871 DAG.getConstant(0, DL, MVT::i32),
2872 DAG.getConstant(2, DL, MVT::i32)};
2873 SDValue CurrentTEB = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
2874 DAG.getVTList(MVT::i32, MVT::Other), Ops);
2875
2876 SDValue TEB = CurrentTEB.getValue(0);
2877 Chain = CurrentTEB.getValue(1);
2878
2879 // Load the ThreadLocalStoragePointer from the TEB
2880 // A pointer to the TLS array is located at offset 0x2c from the TEB.
2881 SDValue TLSArray =
2882 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x2c, DL));
2883 TLSArray = DAG.getLoad(PtrVT, DL, Chain, TLSArray, MachinePointerInfo());
2884
2885 // The pointer to the thread's TLS data area is at the TLS Index scaled by 4
2886 // offset into the TLSArray.
2887
2888 // Load the TLS index from the C runtime
2889 SDValue TLSIndex =
2890 DAG.getTargetExternalSymbol("_tls_index", PtrVT, ARMII::MO_NO_FLAG);
2891 TLSIndex = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, TLSIndex);
2892 TLSIndex = DAG.getLoad(PtrVT, DL, Chain, TLSIndex, MachinePointerInfo());
2893
2894 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex,
2895 DAG.getConstant(2, DL, MVT::i32));
2896 SDValue TLS = DAG.getLoad(PtrVT, DL, Chain,
2897 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot),
2898 MachinePointerInfo());
2899
2900 // Get the offset of the start of the .tls section (section base)
2901 const auto *GA = cast<GlobalAddressSDNode>(Op);
2902 auto *CPV = ARMConstantPoolConstant::Create(GA->getGlobal(), ARMCP::SECREL);
2903 SDValue Offset = DAG.getLoad(
2904 PtrVT, DL, Chain, DAG.getNode(ARMISD::Wrapper, DL, MVT::i32,
2905 DAG.getTargetConstantPool(CPV, PtrVT, 4)),
2906 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2907
2908 return DAG.getNode(ISD::ADD, DL, PtrVT, TLS, Offset);
2909}
2910
2911// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2912SDValue
2913ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2914 SelectionDAG &DAG) const {
2915 SDLoc dl(GA);
2916 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2917 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2918 MachineFunction &MF = DAG.getMachineFunction();
2919 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2920 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2921 ARMConstantPoolValue *CPV =
2922 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2923 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2924 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2925 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2926 Argument = DAG.getLoad(
2927 PtrVT, dl, DAG.getEntryNode(), Argument,
2928 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2929 SDValue Chain = Argument.getValue(1);
2930
2931 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2932 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2933
2934 // call __tls_get_addr.
2935 ArgListTy Args;
2936 ArgListEntry Entry;
2937 Entry.Node = Argument;
2938 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2939 Args.push_back(Entry);
2940
2941 // FIXME: is there useful debug info available here?
2942 TargetLowering::CallLoweringInfo CLI(DAG);
2943 CLI.setDebugLoc(dl).setChain(Chain).setLibCallee(
2944 CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2945 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args));
2946
2947 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2948 return CallResult.first;
2949}
2950
2951// Lower ISD::GlobalTLSAddress using the "initial exec" or
2952// "local exec" model.
2953SDValue
2954ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2955 SelectionDAG &DAG,
2956 TLSModel::Model model) const {
2957 const GlobalValue *GV = GA->getGlobal();
2958 SDLoc dl(GA);
2959 SDValue Offset;
2960 SDValue Chain = DAG.getEntryNode();
2961 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2962 // Get the Thread Pointer
2963 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2964
2965 if (model == TLSModel::InitialExec) {
2966 MachineFunction &MF = DAG.getMachineFunction();
2967 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2968 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2969 // Initial exec model.
2970 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2971 ARMConstantPoolValue *CPV =
2972 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2973 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2974 true);
2975 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2976 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2977 Offset = DAG.getLoad(
2978 PtrVT, dl, Chain, Offset,
2979 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2980 Chain = Offset.getValue(1);
2981
2982 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2983 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2984
2985 Offset = DAG.getLoad(
2986 PtrVT, dl, Chain, Offset,
2987 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2988 } else {
2989 // local exec model
2990 assert(model == TLSModel::LocalExec)(static_cast <bool> (model == TLSModel::LocalExec) ? void
(0) : __assert_fail ("model == TLSModel::LocalExec", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 2990, __extension__ __PRETTY_FUNCTION__))
;
2991 ARMConstantPoolValue *CPV =
2992 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2993 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2994 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2995 Offset = DAG.getLoad(
2996 PtrVT, dl, Chain, Offset,
2997 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
2998 }
2999
3000 // The address of the thread local variable is the add of the thread
3001 // pointer with the offset of the variable.
3002 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
3003}
3004
3005SDValue
3006ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
3007 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3008 if (DAG.getTarget().Options.EmulatedTLS)
3009 return LowerToTLSEmulatedModel(GA, DAG);
3010
3011 if (Subtarget->isTargetDarwin())
3012 return LowerGlobalTLSAddressDarwin(Op, DAG);
3013
3014 if (Subtarget->isTargetWindows())
3015 return LowerGlobalTLSAddressWindows(Op, DAG);
3016
3017 // TODO: implement the "local dynamic" model
3018 assert(Subtarget->isTargetELF() && "Only ELF implemented here")(static_cast <bool> (Subtarget->isTargetELF() &&
"Only ELF implemented here") ? void (0) : __assert_fail ("Subtarget->isTargetELF() && \"Only ELF implemented here\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3018, __extension__ __PRETTY_FUNCTION__))
;
3019 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
3020
3021 switch (model) {
3022 case TLSModel::GeneralDynamic:
3023 case TLSModel::LocalDynamic:
3024 return LowerToTLSGeneralDynamicModel(GA, DAG);
3025 case TLSModel::InitialExec:
3026 case TLSModel::LocalExec:
3027 return LowerToTLSExecModels(GA, DAG, model);
3028 }
3029 llvm_unreachable("bogus TLS model")::llvm::llvm_unreachable_internal("bogus TLS model", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3029)
;
3030}
3031
3032/// Return true if all users of V are within function F, looking through
3033/// ConstantExprs.
3034static bool allUsersAreInFunction(const Value *V, const Function *F) {
3035 SmallVector<const User*,4> Worklist;
3036 for (auto *U : V->users())
3037 Worklist.push_back(U);
3038 while (!Worklist.empty()) {
3039 auto *U = Worklist.pop_back_val();
3040 if (isa<ConstantExpr>(U)) {
3041 for (auto *UU : U->users())
3042 Worklist.push_back(UU);
3043 continue;
3044 }
3045
3046 auto *I = dyn_cast<Instruction>(U);
3047 if (!I || I->getParent()->getParent() != F)
3048 return false;
3049 }
3050 return true;
3051}
3052
3053/// Return true if all users of V are within some (any) function, looking through
3054/// ConstantExprs. In other words, are there any global constant users?
3055static bool allUsersAreInFunctions(const Value *V) {
3056 SmallVector<const User*,4> Worklist;
3057 for (auto *U : V->users())
3058 Worklist.push_back(U);
3059 while (!Worklist.empty()) {
3060 auto *U = Worklist.pop_back_val();
3061 if (isa<ConstantExpr>(U)) {
3062 for (auto *UU : U->users())
3063 Worklist.push_back(UU);
3064 continue;
3065 }
3066
3067 if (!isa<Instruction>(U))
3068 return false;
3069 }
3070 return true;
3071}
3072
3073// Return true if T is an integer, float or an array/vector of either.
3074static bool isSimpleType(Type *T) {
3075 if (T->isIntegerTy() || T->isFloatingPointTy())
3076 return true;
3077 Type *SubT = nullptr;
3078 if (T->isArrayTy())
3079 SubT = T->getArrayElementType();
3080 else if (T->isVectorTy())
3081 SubT = T->getVectorElementType();
3082 else
3083 return false;
3084 return SubT->isIntegerTy() || SubT->isFloatingPointTy();
3085}
3086
3087static SDValue promoteToConstantPool(const GlobalValue *GV, SelectionDAG &DAG,
3088 EVT PtrVT, const SDLoc &dl) {
3089 // If we're creating a pool entry for a constant global with unnamed address,
3090 // and the global is small enough, we can emit it inline into the constant pool
3091 // to save ourselves an indirection.
3092 //
3093 // This is a win if the constant is only used in one function (so it doesn't
3094 // need to be duplicated) or duplicating the constant wouldn't increase code
3095 // size (implying the constant is no larger than 4 bytes).
3096 const Function &F = DAG.getMachineFunction().getFunction();
3097
3098 // We rely on this decision to inline being idemopotent and unrelated to the
3099 // use-site. We know that if we inline a variable at one use site, we'll
3100 // inline it elsewhere too (and reuse the constant pool entry). Fast-isel
3101 // doesn't know about this optimization, so bail out if it's enabled else
3102 // we could decide to inline here (and thus never emit the GV) but require
3103 // the GV from fast-isel generated code.
3104 if (!EnableConstpoolPromotion ||
3105 DAG.getMachineFunction().getTarget().Options.EnableFastISel)
3106 return SDValue();
3107
3108 auto *GVar = dyn_cast<GlobalVariable>(GV);
3109 if (!GVar || !GVar->hasInitializer() ||
3110 !GVar->isConstant() || !GVar->hasGlobalUnnamedAddr() ||
3111 !GVar->hasLocalLinkage())
3112 return SDValue();
3113
3114 // Ensure that we don't try and inline any type that contains pointers. If
3115 // we inline a value that contains relocations, we move the relocations from
3116 // .data to .text which is not ideal.
3117 auto *Init = GVar->getInitializer();
3118 if (!isSimpleType(Init->getType()))
3119 return SDValue();
3120
3121 // The constant islands pass can only really deal with alignment requests
3122 // <= 4 bytes and cannot pad constants itself. Therefore we cannot promote
3123 // any type wanting greater alignment requirements than 4 bytes. We also
3124 // can only promote constants that are multiples of 4 bytes in size or
3125 // are paddable to a multiple of 4. Currently we only try and pad constants
3126 // that are strings for simplicity.
3127 auto *CDAInit = dyn_cast<ConstantDataArray>(Init);
3128 unsigned Size = DAG.getDataLayout().getTypeAllocSize(Init->getType());
3129 unsigned Align = GVar->getAlignment();
3130 unsigned RequiredPadding = 4 - (Size % 4);
3131 bool PaddingPossible =
3132 RequiredPadding == 4 || (CDAInit && CDAInit->isString());
3133 if (!PaddingPossible || Align > 4 || Size > ConstpoolPromotionMaxSize ||
3134 Size == 0)
3135 return SDValue();
3136
3137 unsigned PaddedSize = Size + ((RequiredPadding == 4) ? 0 : RequiredPadding);
3138 MachineFunction &MF = DAG.getMachineFunction();
3139 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3140
3141 // We can't bloat the constant pool too much, else the ConstantIslands pass
3142 // may fail to converge. If we haven't promoted this global yet (it may have
3143 // multiple uses), and promoting it would increase the constant pool size (Sz
3144 // > 4), ensure we have space to do so up to MaxTotal.
3145 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar) && Size > 4)
3146 if (AFI->getPromotedConstpoolIncrease() + PaddedSize - 4 >=
3147 ConstpoolPromotionMaxTotal)
3148 return SDValue();
3149
3150 // This is only valid if all users are in a single function OR it has users
3151 // in multiple functions but it no larger than a pointer. We also check if
3152 // GVar has constant (non-ConstantExpr) users. If so, it essentially has its
3153 // address taken.
3154 if (!allUsersAreInFunction(GVar, &F) &&
3155 !(Size <= 4 && allUsersAreInFunctions(GVar)))
3156 return SDValue();
3157
3158 // We're going to inline this global. Pad it out if needed.
3159 if (RequiredPadding != 4) {
3160 StringRef S = CDAInit->getAsString();
3161
3162 SmallVector<uint8_t,16> V(S.size());
3163 std::copy(S.bytes_begin(), S.bytes_end(), V.begin());
3164 while (RequiredPadding--)
3165 V.push_back(0);
3166 Init = ConstantDataArray::get(*DAG.getContext(), V);
3167 }
3168
3169 auto CPVal = ARMConstantPoolConstant::Create(GVar, Init);
3170 SDValue CPAddr =
3171 DAG.getTargetConstantPool(CPVal, PtrVT, /*Align=*/4);
3172 if (!AFI->getGlobalsPromotedToConstantPool().count(GVar)) {
3173 AFI->markGlobalAsPromotedToConstantPool(GVar);
3174 AFI->setPromotedConstpoolIncrease(AFI->getPromotedConstpoolIncrease() +
3175 PaddedSize - 4);
3176 }
3177 ++NumConstpoolPromoted;
3178 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3179}
3180
3181bool ARMTargetLowering::isReadOnly(const GlobalValue *GV) const {
3182 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
3183 GV = GA->getBaseObject();
3184 return (isa<GlobalVariable>(GV) && cast<GlobalVariable>(GV)->isConstant()) ||
3185 isa<Function>(GV);
3186}
3187
3188SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op,
3189 SelectionDAG &DAG) const {
3190 switch (Subtarget->getTargetTriple().getObjectFormat()) {
3191 default: llvm_unreachable("unknown object format")::llvm::llvm_unreachable_internal("unknown object format", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3191)
;
3192 case Triple::COFF:
3193 return LowerGlobalAddressWindows(Op, DAG);
3194 case Triple::ELF:
3195 return LowerGlobalAddressELF(Op, DAG);
3196 case Triple::MachO:
3197 return LowerGlobalAddressDarwin(Op, DAG);
3198 }
3199}
3200
3201SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
3202 SelectionDAG &DAG) const {
3203 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3204 SDLoc dl(Op);
3205 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3206 const TargetMachine &TM = getTargetMachine();
3207 bool IsRO = isReadOnly(GV);
3208
3209 // promoteToConstantPool only if not generating XO text section
3210 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV) && !Subtarget->genExecuteOnly())
3211 if (SDValue V = promoteToConstantPool(GV, DAG, PtrVT, dl))
3212 return V;
3213
3214 if (isPositionIndependent()) {
3215 bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
3216 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
3217 UseGOT_PREL ? ARMII::MO_GOT : 0);
3218 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3219 if (UseGOT_PREL)
3220 Result =
3221 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3222 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3223 return Result;
3224 } else if (Subtarget->isROPI() && IsRO) {
3225 // PC-relative.
3226 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
3227 SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G);
3228 return Result;
3229 } else if (Subtarget->isRWPI() && !IsRO) {
3230 // SB-relative.
3231 SDValue RelAddr;
3232 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3233 ++NumMovwMovt;
3234 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_SBREL);
3235 RelAddr = DAG.getNode(ARMISD::Wrapper, dl, PtrVT, G);
3236 } else { // use literal pool for address constant
3237 ARMConstantPoolValue *CPV =
3238 ARMConstantPoolConstant::Create(GV, ARMCP::SBREL);
3239 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3240 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3241 RelAddr = DAG.getLoad(
3242 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3243 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3244 }
3245 SDValue SB = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT);
3246 SDValue Result = DAG.getNode(ISD::ADD, dl, PtrVT, SB, RelAddr);
3247 return Result;
3248 }
3249
3250 // If we have T2 ops, we can materialize the address directly via movt/movw
3251 // pair. This is always cheaper.
3252 if (Subtarget->useMovt(DAG.getMachineFunction())) {
3253 ++NumMovwMovt;
3254 // FIXME: Once remat is capable of dealing with instructions with register
3255 // operands, expand this into two nodes.
3256 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
3257 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
3258 } else {
3259 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
3260 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3261 return DAG.getLoad(
3262 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3263 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3264 }
3265}
3266
3267SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
3268 SelectionDAG &DAG) const {
3269 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3270, __extension__ __PRETTY_FUNCTION__))
3270 "ROPI/RWPI not currently supported for Darwin")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Darwin"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Darwin\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3270, __extension__ __PRETTY_FUNCTION__))
;
3271 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3272 SDLoc dl(Op);
3273 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3274
3275 if (Subtarget->useMovt(DAG.getMachineFunction()))
3276 ++NumMovwMovt;
3277
3278 // FIXME: Once remat is capable of dealing with instructions with register
3279 // operands, expand this into multiple nodes
3280 unsigned Wrapper =
3281 isPositionIndependent() ? ARMISD::WrapperPIC : ARMISD::Wrapper;
3282
3283 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
3284 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
3285
3286 if (Subtarget->isGVIndirectSymbol(GV))
3287 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
3288 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3289 return Result;
3290}
3291
3292SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
3293 SelectionDAG &DAG) const {
3294 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported")(static_cast <bool> (Subtarget->isTargetWindows() &&
"non-Windows COFF is not supported") ? void (0) : __assert_fail
("Subtarget->isTargetWindows() && \"non-Windows COFF is not supported\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3294, __extension__ __PRETTY_FUNCTION__))
;
3295 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3296, __extension__ __PRETTY_FUNCTION__))
3296 "Windows on ARM expects to use movw/movt")(static_cast <bool> (Subtarget->useMovt(DAG.getMachineFunction
()) && "Windows on ARM expects to use movw/movt") ? void
(0) : __assert_fail ("Subtarget->useMovt(DAG.getMachineFunction()) && \"Windows on ARM expects to use movw/movt\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3296, __extension__ __PRETTY_FUNCTION__))
;
3297 assert(!Subtarget->isROPI() && !Subtarget->isRWPI() &&(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3298, __extension__ __PRETTY_FUNCTION__))
3298 "ROPI/RWPI not currently supported for Windows")(static_cast <bool> (!Subtarget->isROPI() &&
!Subtarget->isRWPI() && "ROPI/RWPI not currently supported for Windows"
) ? void (0) : __assert_fail ("!Subtarget->isROPI() && !Subtarget->isRWPI() && \"ROPI/RWPI not currently supported for Windows\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3298, __extension__ __PRETTY_FUNCTION__))
;
3299
3300 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3301 const ARMII::TOF TargetFlags =
3302 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
3303 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3304 SDValue Result;
3305 SDLoc DL(Op);
3306
3307 ++NumMovwMovt;
3308
3309 // FIXME: Once remat is capable of dealing with instructions with register
3310 // operands, expand this into two nodes.
3311 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
3312 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
3313 TargetFlags));
3314 if (GV->hasDLLImportStorageClass())
3315 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
3316 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
3317 return Result;
3318}
3319
3320SDValue
3321ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
3322 SDLoc dl(Op);
3323 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
3324 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
3325 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
3326 Op.getOperand(1), Val);
3327}
3328
3329SDValue
3330ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
3331 SDLoc dl(Op);
3332 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
3333 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
3334}
3335
3336SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
3337 SelectionDAG &DAG) const {
3338 SDLoc dl(Op);
3339 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
3340 Op.getOperand(0));
3341}
3342
3343SDValue
3344ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
3345 const ARMSubtarget *Subtarget) const {
3346 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3347 SDLoc dl(Op);
3348 switch (IntNo) {
3349 default: return SDValue(); // Don't custom lower most intrinsics.
3350 case Intrinsic::thread_pointer: {
3351 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3352 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
3353 }
3354 case Intrinsic::eh_sjlj_lsda: {
3355 MachineFunction &MF = DAG.getMachineFunction();
3356 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3357 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
3358 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3359 SDValue CPAddr;
3360 bool IsPositionIndependent = isPositionIndependent();
3361 unsigned PCAdj = IsPositionIndependent ? (Subtarget->isThumb() ? 4 : 8) : 0;
3362 ARMConstantPoolValue *CPV =
3363 ARMConstantPoolConstant::Create(&MF.getFunction(), ARMPCLabelIndex,
3364 ARMCP::CPLSDA, PCAdj);
3365 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
3366 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
3367 SDValue Result = DAG.getLoad(
3368 PtrVT, dl, DAG.getEntryNode(), CPAddr,
3369 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
3370
3371 if (IsPositionIndependent) {
3372 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
3373 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
3374 }
3375 return Result;
3376 }
3377 case Intrinsic::arm_neon_vabs:
3378 return DAG.getNode(ISD::ABS, SDLoc(Op), Op.getValueType(),
3379 Op.getOperand(1));
3380 case Intrinsic::arm_neon_vmulls:
3381 case Intrinsic::arm_neon_vmullu: {
3382 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
3383 ? ARMISD::VMULLs : ARMISD::VMULLu;
3384 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3385 Op.getOperand(1), Op.getOperand(2));
3386 }
3387 case Intrinsic::arm_neon_vminnm:
3388 case Intrinsic::arm_neon_vmaxnm: {
3389 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
3390 ? ISD::FMINNUM : ISD::FMAXNUM;
3391 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3392 Op.getOperand(1), Op.getOperand(2));
3393 }
3394 case Intrinsic::arm_neon_vminu:
3395 case Intrinsic::arm_neon_vmaxu: {
3396 if (Op.getValueType().isFloatingPoint())
3397 return SDValue();
3398 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
3399 ? ISD::UMIN : ISD::UMAX;
3400 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3401 Op.getOperand(1), Op.getOperand(2));
3402 }
3403 case Intrinsic::arm_neon_vmins:
3404 case Intrinsic::arm_neon_vmaxs: {
3405 // v{min,max}s is overloaded between signed integers and floats.
3406 if (!Op.getValueType().isFloatingPoint()) {
3407 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3408 ? ISD::SMIN : ISD::SMAX;
3409 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3410 Op.getOperand(1), Op.getOperand(2));
3411 }
3412 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
3413 ? ISD::FMINNAN : ISD::FMAXNAN;
3414 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
3415 Op.getOperand(1), Op.getOperand(2));
3416 }
3417 case Intrinsic::arm_neon_vtbl1:
3418 return DAG.getNode(ARMISD::VTBL1, SDLoc(Op), Op.getValueType(),
3419 Op.getOperand(1), Op.getOperand(2));
3420 case Intrinsic::arm_neon_vtbl2:
3421 return DAG.getNode(ARMISD::VTBL2, SDLoc(Op), Op.getValueType(),
3422 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3423 }
3424}
3425
3426static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
3427 const ARMSubtarget *Subtarget) {
3428 SDLoc dl(Op);
3429 ConstantSDNode *SSIDNode = cast<ConstantSDNode>(Op.getOperand(2));
3430 auto SSID = static_cast<SyncScope::ID>(SSIDNode->getZExtValue());
3431 if (SSID == SyncScope::SingleThread)
3432 return Op;
3433
3434 if (!Subtarget->hasDataBarrier()) {
3435 // Some ARMv6 cpus can support data barriers with an mcr instruction.
3436 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
3437 // here.
3438 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3439, __extension__ __PRETTY_FUNCTION__))
3439 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!")(static_cast <bool> (Subtarget->hasV6Ops() &&
!Subtarget->isThumb() && "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!"
) ? void (0) : __assert_fail ("Subtarget->hasV6Ops() && !Subtarget->isThumb() && \"Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3439, __extension__ __PRETTY_FUNCTION__))
;
3440 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
3441 DAG.getConstant(0, dl, MVT::i32));
3442 }
3443
3444 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
3445 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
3446 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
3447 if (Subtarget->isMClass()) {
3448 // Only a full system barrier exists in the M-class architectures.
3449 Domain = ARM_MB::SY;
3450 } else if (Subtarget->preferISHSTBarriers() &&
3451 Ord == AtomicOrdering::Release) {
3452 // Swift happens to implement ISHST barriers in a way that's compatible with
3453 // Release semantics but weaker than ISH so we'd be fools not to use
3454 // it. Beware: other processors probably don't!
3455 Domain = ARM_MB::ISHST;
3456 }
3457
3458 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
3459 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
3460 DAG.getConstant(Domain, dl, MVT::i32));
3461}
3462
3463static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
3464 const ARMSubtarget *Subtarget) {
3465 // ARM pre v5TE and Thumb1 does not have preload instructions.
3466 if (!(Subtarget->isThumb2() ||
3467 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
3468 // Just preserve the chain.
3469 return Op.getOperand(0);
3470
3471 SDLoc dl(Op);
3472 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
3473 if (!isRead &&
3474 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
3475 // ARMv7 with MP extension has PLDW.
3476 return Op.getOperand(0);
3477
3478 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3479 if (Subtarget->isThumb()) {
3480 // Invert the bits.
3481 isRead = ~isRead & 1;
3482 isData = ~isData & 1;
3483 }
3484
3485 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
3486 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
3487 DAG.getConstant(isData, dl, MVT::i32));
3488}
3489
3490static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
3491 MachineFunction &MF = DAG.getMachineFunction();
3492 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
3493
3494 // vastart just stores the address of the VarArgsFrameIndex slot into the
3495 // memory location argument.
3496 SDLoc dl(Op);
3497 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
3498 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3499 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3500 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3501 MachinePointerInfo(SV));
3502}
3503
3504SDValue ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA,
3505 CCValAssign &NextVA,
3506 SDValue &Root,
3507 SelectionDAG &DAG,
3508 const SDLoc &dl) const {
3509 MachineFunction &MF = DAG.getMachineFunction();
3510 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3511
3512 const TargetRegisterClass *RC;
3513 if (AFI->isThumb1OnlyFunction())
3514 RC = &ARM::tGPRRegClass;
3515 else
3516 RC = &ARM::GPRRegClass;
3517
3518 // Transform the arguments stored in physical registers into virtual ones.
3519 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3520 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3521
3522 SDValue ArgValue2;
3523 if (NextVA.isMemLoc()) {
3524 MachineFrameInfo &MFI = MF.getFrameInfo();
3525 int FI = MFI.CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3526
3527 // Create load node to retrieve arguments from the stack.
3528 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3529 ArgValue2 = DAG.getLoad(
3530 MVT::i32, dl, Root, FIN,
3531 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3532 } else {
3533 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3534 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3535 }
3536 if (!Subtarget->isLittle())
3537 std::swap (ArgValue, ArgValue2);
3538 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3539}
3540
3541// The remaining GPRs hold either the beginning of variable-argument
3542// data, or the beginning of an aggregate passed by value (usually
3543// byval). Either way, we allocate stack slots adjacent to the data
3544// provided by our caller, and store the unallocated registers there.
3545// If this is a variadic function, the va_list pointer will begin with
3546// these values; otherwise, this reassembles a (byval) structure that
3547// was split between registers and memory.
3548// Return: The frame index registers were stored into.
3549int ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3550 const SDLoc &dl, SDValue &Chain,
3551 const Value *OrigArg,
3552 unsigned InRegsParamRecordIdx,
3553 int ArgOffset, unsigned ArgSize) const {
3554 // Currently, two use-cases possible:
3555 // Case #1. Non-var-args function, and we meet first byval parameter.
3556 // Setup first unallocated register as first byval register;
3557 // eat all remained registers
3558 // (these two actions are performed by HandleByVal method).
3559 // Then, here, we initialize stack frame with
3560 // "store-reg" instructions.
3561 // Case #2. Var-args function, that doesn't contain byval parameters.
3562 // The same: eat all remained unallocated registers,
3563 // initialize stack frame.
3564
3565 MachineFunction &MF = DAG.getMachineFunction();
3566 MachineFrameInfo &MFI = MF.getFrameInfo();
3567 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3568 unsigned RBegin, REnd;
3569 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3570 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3571 } else {
3572 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3573 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3574 REnd = ARM::R4;
3575 }
3576
3577 if (REnd != RBegin)
3578 ArgOffset = -4 * (ARM::R4 - RBegin);
3579
3580 auto PtrVT = getPointerTy(DAG.getDataLayout());
3581 int FrameIndex = MFI.CreateFixedObject(ArgSize, ArgOffset, false);
3582 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3583
3584 SmallVector<SDValue, 4> MemOps;
3585 const TargetRegisterClass *RC =
3586 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3587
3588 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3589 unsigned VReg = MF.addLiveIn(Reg, RC);
3590 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3591 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3592 MachinePointerInfo(OrigArg, 4 * i));
3593 MemOps.push_back(Store);
3594 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3595 }
3596
3597 if (!MemOps.empty())
3598 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3599 return FrameIndex;
3600}
3601
3602// Setup stack frame, the va_list pointer will start from.
3603void ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3604 const SDLoc &dl, SDValue &Chain,
3605 unsigned ArgOffset,
3606 unsigned TotalArgRegsSaveSize,
3607 bool ForceMutable) const {
3608 MachineFunction &MF = DAG.getMachineFunction();
3609 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3610
3611 // Try to store any remaining integer argument regs
3612 // to their spots on the stack so that they may be loaded by dereferencing
3613 // the result of va_next.
3614 // If there is no regs to be stored, just point address after last
3615 // argument passed via stack.
3616 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3617 CCInfo.getInRegsParamsCount(),
3618 CCInfo.getNextStackOffset(), 4);
3619 AFI->setVarArgsFrameIndex(FrameIndex);
3620}
3621
3622SDValue ARMTargetLowering::LowerFormalArguments(
3623 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
3624 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
3625 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3626 MachineFunction &MF = DAG.getMachineFunction();
3627 MachineFrameInfo &MFI = MF.getFrameInfo();
3628
3629 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3630
3631 // Assign locations to all of the incoming arguments.
3632 SmallVector<CCValAssign, 16> ArgLocs;
3633 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3634 *DAG.getContext());
3635 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, isVarArg));
3636
3637 SmallVector<SDValue, 16> ArgValues;
3638 SDValue ArgValue;
3639 Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
3640 unsigned CurArgIdx = 0;
3641
3642 // Initially ArgRegsSaveSize is zero.
3643 // Then we increase this value each time we meet byval parameter.
3644 // We also increase this value in case of varargs function.
3645 AFI->setArgRegsSaveSize(0);
3646
3647 // Calculate the amount of stack space that we need to allocate to store
3648 // byval and variadic arguments that are passed in registers.
3649 // We need to know this before we allocate the first byval or variadic
3650 // argument, as they will be allocated a stack slot below the CFA (Canonical
3651 // Frame Address, the stack pointer at entry to the function).
3652 unsigned ArgRegBegin = ARM::R4;
3653 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3654 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3655 break;
3656
3657 CCValAssign &VA = ArgLocs[i];
3658 unsigned Index = VA.getValNo();
3659 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3660 if (!Flags.isByVal())
3661 continue;
3662
3663 assert(VA.isMemLoc() && "unexpected byval pointer in reg")(static_cast <bool> (VA.isMemLoc() && "unexpected byval pointer in reg"
) ? void (0) : __assert_fail ("VA.isMemLoc() && \"unexpected byval pointer in reg\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3663, __extension__ __PRETTY_FUNCTION__))
;
3664 unsigned RBegin, REnd;
3665 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3666 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3667
3668 CCInfo.nextInRegsParam();
3669 }
3670 CCInfo.rewindByValRegsInfo();
3671
3672 int lastInsIndex = -1;
3673 if (isVarArg && MFI.hasVAStart()) {
3674 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3675 if (RegIdx != array_lengthof(GPRArgRegs))
3676 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3677 }
3678
3679 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3680 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3681 auto PtrVT = getPointerTy(DAG.getDataLayout());
3682
3683 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3684 CCValAssign &VA = ArgLocs[i];
3685 if (Ins[VA.getValNo()].isOrigArg()) {
3686 std::advance(CurOrigArg,
3687 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3688 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3689 }
3690 // Arguments stored in registers.
3691 if (VA.isRegLoc()) {
3692 EVT RegVT = VA.getLocVT();
3693
3694 if (VA.needsCustom()) {
3695 // f64 and vector types are split up into multiple registers or
3696 // combinations of registers and stack slots.
3697 if (VA.getLocVT() == MVT::v2f64) {
3698 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3699 Chain, DAG, dl);
3700 VA = ArgLocs[++i]; // skip ahead to next loc
3701 SDValue ArgValue2;
3702 if (VA.isMemLoc()) {
3703 int FI = MFI.CreateFixedObject(8, VA.getLocMemOffset(), true);
3704 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3705 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3706 MachinePointerInfo::getFixedStack(
3707 DAG.getMachineFunction(), FI));
3708 } else {
3709 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3710 Chain, DAG, dl);
3711 }
3712 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3713 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3714 ArgValue, ArgValue1,
3715 DAG.getIntPtrConstant(0, dl));
3716 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3717 ArgValue, ArgValue2,
3718 DAG.getIntPtrConstant(1, dl));
3719 } else
3720 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3721 } else {
3722 const TargetRegisterClass *RC;
3723
3724
3725 if (RegVT == MVT::f16)
3726 RC = &ARM::HPRRegClass;
3727 else if (RegVT == MVT::f32)
3728 RC = &ARM::SPRRegClass;
3729 else if (RegVT == MVT::f64)
3730 RC = &ARM::DPRRegClass;
3731 else if (RegVT == MVT::v2f64)
3732 RC = &ARM::QPRRegClass;
3733 else if (RegVT == MVT::i32)
3734 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3735 : &ARM::GPRRegClass;
3736 else
3737 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering")::llvm::llvm_unreachable_internal("RegVT not supported by FORMAL_ARGUMENTS Lowering"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3737)
;
3738
3739 // Transform the arguments in physical registers into virtual ones.
3740 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3741 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3742 }
3743
3744 // If this is an 8 or 16-bit value, it is really passed promoted
3745 // to 32 bits. Insert an assert[sz]ext to capture this, then
3746 // truncate to the right size.
3747 switch (VA.getLocInfo()) {
3748 default: llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3748)
;
3749 case CCValAssign::Full: break;
3750 case CCValAssign::BCvt:
3751 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3752 break;
3753 case CCValAssign::SExt:
3754 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3755 DAG.getValueType(VA.getValVT()));
3756 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3757 break;
3758 case CCValAssign::ZExt:
3759 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3760 DAG.getValueType(VA.getValVT()));
3761 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3762 break;
3763 }
3764
3765 InVals.push_back(ArgValue);
3766 } else { // VA.isRegLoc()
3767 // sanity check
3768 assert(VA.isMemLoc())(static_cast <bool> (VA.isMemLoc()) ? void (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3768, __extension__ __PRETTY_FUNCTION__))
;
3769 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered")(static_cast <bool> (VA.getValVT() != MVT::i64 &&
"i64 should already be lowered") ? void (0) : __assert_fail (
"VA.getValVT() != MVT::i64 && \"i64 should already be lowered\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3769, __extension__ __PRETTY_FUNCTION__))
;
3770
3771 int index = VA.getValNo();
3772
3773 // Some Ins[] entries become multiple ArgLoc[] entries.
3774 // Process them only once.
3775 if (index != lastInsIndex)
3776 {
3777 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3778 // FIXME: For now, all byval parameter objects are marked mutable.
3779 // This can be changed with more analysis.
3780 // In case of tail call optimization mark all arguments mutable.
3781 // Since they could be overwritten by lowering of arguments in case of
3782 // a tail call.
3783 if (Flags.isByVal()) {
3784 assert(Ins[index].isOrigArg() &&(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3785, __extension__ __PRETTY_FUNCTION__))
3785 "Byval arguments cannot be implicit")(static_cast <bool> (Ins[index].isOrigArg() && "Byval arguments cannot be implicit"
) ? void (0) : __assert_fail ("Ins[index].isOrigArg() && \"Byval arguments cannot be implicit\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3785, __extension__ __PRETTY_FUNCTION__))
;
3786 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3787
3788 int FrameIndex = StoreByValRegs(
3789 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3790 VA.getLocMemOffset(), Flags.getByValSize());
3791 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3792 CCInfo.nextInRegsParam();
3793 } else {
3794 unsigned FIOffset = VA.getLocMemOffset();
3795 int FI = MFI.CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3796 FIOffset, true);
3797
3798 // Create load nodes to retrieve arguments from the stack.
3799 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3800 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3801 MachinePointerInfo::getFixedStack(
3802 DAG.getMachineFunction(), FI)));
3803 }
3804 lastInsIndex = index;
3805 }
3806 }
3807 }
3808
3809 // varargs
3810 if (isVarArg && MFI.hasVAStart())
3811 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3812 CCInfo.getNextStackOffset(),
3813 TotalArgRegsSaveSize);
3814
3815 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3816
3817 return Chain;
3818}
3819
3820/// isFloatingPointZero - Return true if this is +0.0.
3821static bool isFloatingPointZero(SDValue Op) {
3822 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3823 return CFP->getValueAPF().isPosZero();
3824 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3825 // Maybe this has already been legalized into the constant pool?
3826 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3827 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3828 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3829 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3830 return CFP->getValueAPF().isPosZero();
3831 }
3832 } else if (Op->getOpcode() == ISD::BITCAST &&
3833 Op->getValueType(0) == MVT::f64) {
3834 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3835 // created by LowerConstantFP().
3836 SDValue BitcastOp = Op->getOperand(0);
3837 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3838 isNullConstant(BitcastOp->getOperand(0)))
3839 return true;
3840 }
3841 return false;
3842}
3843
3844/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3845/// the given operands.
3846SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3847 SDValue &ARMcc, SelectionDAG &DAG,
3848 const SDLoc &dl) const {
3849 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3850 unsigned C = RHSC->getZExtValue();
3851 if (!isLegalICmpImmediate(C)) {
3852 // Constant does not fit, try adjusting it by one?
3853 switch (CC) {
3854 default: break;
3855 case ISD::SETLT:
3856 case ISD::SETGE:
3857 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3858 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3859 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3860 }
3861 break;
3862 case ISD::SETULT:
3863 case ISD::SETUGE:
3864 if (C != 0 && isLegalICmpImmediate(C-1)) {
3865 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3866 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3867 }
3868 break;
3869 case ISD::SETLE:
3870 case ISD::SETGT:
3871 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3872 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3873 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3874 }
3875 break;
3876 case ISD::SETULE:
3877 case ISD::SETUGT:
3878 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3879 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3880 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3881 }
3882 break;
3883 }
3884 }
3885 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) &&
3886 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) {
3887 // In ARM and Thumb-2, the compare instructions can shift their second
3888 // operand.
3889 CC = ISD::getSetCCSwappedOperands(CC);
3890 std::swap(LHS, RHS);
3891 }
3892
3893 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3894 ARMISD::NodeType CompareType;
3895 switch (CondCode) {
3896 default:
3897 CompareType = ARMISD::CMP;
3898 break;
3899 case ARMCC::EQ:
3900 case ARMCC::NE:
3901 // Uses only Z Flag
3902 CompareType = ARMISD::CMPZ;
3903 break;
3904 }
3905 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3906 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3907}
3908
3909/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3910SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
3911 SelectionDAG &DAG, const SDLoc &dl,
3912 bool InvalidOnQNaN) const {
3913 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64)(static_cast <bool> (!Subtarget->isFPOnlySP() || RHS
.getValueType() != MVT::f64) ? void (0) : __assert_fail ("!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3913, __extension__ __PRETTY_FUNCTION__))
;
3914 SDValue Cmp;
3915 SDValue C = DAG.getConstant(InvalidOnQNaN, dl, MVT::i32);
3916 if (!isFloatingPointZero(RHS))
3917 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS, C);
3918 else
3919 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS, C);
3920 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3921}
3922
3923/// duplicateCmp - Glue values can have only one use, so this function
3924/// duplicates a comparison node.
3925SDValue
3926ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3927 unsigned Opc = Cmp.getOpcode();
3928 SDLoc DL(Cmp);
3929 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3930 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3931
3932 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation")(static_cast <bool> (Opc == ARMISD::FMSTAT && "unexpected comparison operation"
) ? void (0) : __assert_fail ("Opc == ARMISD::FMSTAT && \"unexpected comparison operation\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3932, __extension__ __PRETTY_FUNCTION__))
;
3933 Cmp = Cmp.getOperand(0);
3934 Opc = Cmp.getOpcode();
3935 if (Opc == ARMISD::CMPFP)
3936 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3937 Cmp.getOperand(1), Cmp.getOperand(2));
3938 else {
3939 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT")(static_cast <bool> (Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"
) ? void (0) : __assert_fail ("Opc == ARMISD::CMPFPw0 && \"unexpected operand of FMSTAT\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3939, __extension__ __PRETTY_FUNCTION__))
;
3940 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),
3941 Cmp.getOperand(1));
3942 }
3943 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3944}
3945
3946// This function returns three things: the arithmetic computation itself
3947// (Value), a comparison (OverflowCmp), and a condition code (ARMcc). The
3948// comparison and the condition code define the case in which the arithmetic
3949// computation *does not* overflow.
3950std::pair<SDValue, SDValue>
3951ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3952 SDValue &ARMcc) const {
3953 assert(Op.getValueType() == MVT::i32 && "Unsupported value type")(static_cast <bool> (Op.getValueType() == MVT::i32 &&
"Unsupported value type") ? void (0) : __assert_fail ("Op.getValueType() == MVT::i32 && \"Unsupported value type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3953, __extension__ __PRETTY_FUNCTION__))
;
3954
3955 SDValue Value, OverflowCmp;
3956 SDValue LHS = Op.getOperand(0);
3957 SDValue RHS = Op.getOperand(1);
3958 SDLoc dl(Op);
3959
3960 // FIXME: We are currently always generating CMPs because we don't support
3961 // generating CMN through the backend. This is not as good as the natural
3962 // CMP case because it causes a register dependency and cannot be folded
3963 // later.
3964
3965 switch (Op.getOpcode()) {
3966 default:
3967 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 3967)
;
3968 case ISD::SADDO:
3969 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3970 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3971 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3972 break;
3973 case ISD::UADDO:
3974 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3975 // We use ADDC here to correspond to its use in LowerUnsignedALUO.
3976 // We do not use it in the USUBO case as Value may not be used.
3977 Value = DAG.getNode(ARMISD::ADDC, dl,
3978 DAG.getVTList(Op.getValueType(), MVT::i32), LHS, RHS)
3979 .getValue(0);
3980 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3981 break;
3982 case ISD::SSUBO:
3983 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3984 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3985 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3986 break;
3987 case ISD::USUBO:
3988 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3989 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3990 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3991 break;
3992 case ISD::UMULO:
3993 // We generate a UMUL_LOHI and then check if the high word is 0.
3994 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
3995 Value = DAG.getNode(ISD::UMUL_LOHI, dl,
3996 DAG.getVTList(Op.getValueType(), Op.getValueType()),
3997 LHS, RHS);
3998 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
3999 DAG.getConstant(0, dl, MVT::i32));
4000 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4001 break;
4002 case ISD::SMULO:
4003 // We generate a SMUL_LOHI and then check if all the bits of the high word
4004 // are the same as the sign bit of the low word.
4005 ARMcc = DAG.getConstant(ARMCC::EQ, dl, MVT::i32);
4006 Value = DAG.getNode(ISD::SMUL_LOHI, dl,
4007 DAG.getVTList(Op.getValueType(), Op.getValueType()),
4008 LHS, RHS);
4009 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value.getValue(1),
4010 DAG.getNode(ISD::SRA, dl, Op.getValueType(),
4011 Value.getValue(0),
4012 DAG.getConstant(31, dl, MVT::i32)));
4013 Value = Value.getValue(0); // We only want the low 32 bits for the result.
4014 break;
4015 } // switch (...)
4016
4017 return std::make_pair(Value, OverflowCmp);
4018}
4019
4020SDValue
4021ARMTargetLowering::LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const {
4022 // Let legalize expand this if it isn't a legal type yet.
4023 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4024 return SDValue();
4025
4026 SDValue Value, OverflowCmp;
4027 SDValue ARMcc;
4028 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
4029 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4030 SDLoc dl(Op);
4031 // We use 0 and 1 as false and true values.
4032 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
4033 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
4034 EVT VT = Op.getValueType();
4035
4036 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
4037 ARMcc, CCR, OverflowCmp);
4038
4039 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
4040 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4041}
4042
4043static SDValue ConvertBooleanCarryToCarryFlag(SDValue BoolCarry,
4044 SelectionDAG &DAG) {
4045 SDLoc DL(BoolCarry);
4046 EVT CarryVT = BoolCarry.getValueType();
4047
4048 // This converts the boolean value carry into the carry flag by doing
4049 // ARMISD::SUBC Carry, 1
4050 return DAG.getNode(ARMISD::SUBC, DL, DAG.getVTList(CarryVT, MVT::i32),
4051 BoolCarry, DAG.getConstant(1, DL, CarryVT));
4052}
4053
4054static SDValue ConvertCarryFlagToBooleanCarry(SDValue Flags, EVT VT,
4055 SelectionDAG &DAG) {
4056 SDLoc DL(Flags);
4057
4058 // Now convert the carry flag into a boolean carry. We do this
4059 // using ARMISD:ADDE 0, 0, Carry
4060 return DAG.getNode(ARMISD::ADDE, DL, DAG.getVTList(VT, MVT::i32),
4061 DAG.getConstant(0, DL, MVT::i32),
4062 DAG.getConstant(0, DL, MVT::i32), Flags);
4063}
4064
4065SDValue ARMTargetLowering::LowerUnsignedALUO(SDValue Op,
4066 SelectionDAG &DAG) const {
4067 // Let legalize expand this if it isn't a legal type yet.
4068 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
4069 return SDValue();
4070
4071 SDValue LHS = Op.getOperand(0);
4072 SDValue RHS = Op.getOperand(1);
4073 SDLoc dl(Op);
4074
4075 EVT VT = Op.getValueType();
4076 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4077 SDValue Value;
4078 SDValue Overflow;
4079 switch (Op.getOpcode()) {
4080 default:
4081 llvm_unreachable("Unknown overflow instruction!")::llvm::llvm_unreachable_internal("Unknown overflow instruction!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4081)
;
4082 case ISD::UADDO:
4083 Value = DAG.getNode(ARMISD::ADDC, dl, VTs, LHS, RHS);
4084 // Convert the carry flag into a boolean value.
4085 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4086 break;
4087 case ISD::USUBO: {
4088 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS);
4089 // Convert the carry flag into a boolean value.
4090 Overflow = ConvertCarryFlagToBooleanCarry(Value.getValue(1), VT, DAG);
4091 // ARMISD::SUBC returns 0 when we have to borrow, so make it an overflow
4092 // value. So compute 1 - C.
4093 Overflow = DAG.getNode(ISD::SUB, dl, MVT::i32,
4094 DAG.getConstant(1, dl, MVT::i32), Overflow);
4095 break;
4096 }
4097 }
4098
4099 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
4100}
4101
4102SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
4103 SDValue Cond = Op.getOperand(0);
4104 SDValue SelectTrue = Op.getOperand(1);
4105 SDValue SelectFalse = Op.getOperand(2);
4106 SDLoc dl(Op);
4107 unsigned Opc = Cond.getOpcode();
4108
4109 if (Cond.getResNo() == 1 &&
1
Assuming the condition is false
4110 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4111 Opc == ISD::USUBO)) {
4112 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4113 return SDValue();
4114
4115 SDValue Value, OverflowCmp;
4116 SDValue ARMcc;
4117 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4118 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4119 EVT VT = Op.getValueType();
4120
4121 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
4122 OverflowCmp, DAG);
4123 }
4124
4125 // Convert:
4126 //
4127 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
4128 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
4129 //
4130 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2
Assuming the condition is true
3
Assuming the condition is true
4
Taking true branch
4131 const ConstantSDNode *CMOVTrue =
4132 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
4133 const ConstantSDNode *CMOVFalse =
4134 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
4135
4136 if (CMOVTrue && CMOVFalse) {
5
Assuming 'CMOVTrue' is non-null
6
Assuming 'CMOVFalse' is non-null
7
Taking true branch
4137 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
4138 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
4139
4140 SDValue True;
4141 SDValue False;
4142 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
8
Assuming 'CMOVTrueVal' is equal to 1
9
Assuming 'CMOVFalseVal' is equal to 0
10
Taking true branch
4143 True = SelectTrue;
4144 False = SelectFalse;
4145 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
4146 True = SelectFalse;
4147 False = SelectTrue;
4148 }
4149
4150 if (True.getNode() && False.getNode()) {
11
Assuming pointer value is null
4151 EVT VT = Op.getValueType();
4152 SDValue ARMcc = Cond.getOperand(2);
4153 SDValue CCR = Cond.getOperand(3);
4154 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
4155 assert(True.getValueType() == VT)(static_cast <bool> (True.getValueType() == VT) ? void (
0) : __assert_fail ("True.getValueType() == VT", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4155, __extension__ __PRETTY_FUNCTION__))
;
4156 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
4157 }
4158 }
4159 }
4160
4161 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
4162 // undefined bits before doing a full-word comparison with zero.
4163 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
4164 DAG.getConstant(1, dl, Cond.getValueType()));
4165
4166 return DAG.getSelectCC(dl, Cond,
12
Value assigned to 'True.Node'
13
Calling 'SelectionDAG::getSelectCC'
4167 DAG.getConstant(0, dl, Cond.getValueType()),
4168 SelectTrue, SelectFalse, ISD::SETNE);
4169}
4170
4171static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
4172 bool &swpCmpOps, bool &swpVselOps) {
4173 // Start by selecting the GE condition code for opcodes that return true for
4174 // 'equality'
4175 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
4176 CC == ISD::SETULE)
4177 CondCode = ARMCC::GE;
4178
4179 // and GT for opcodes that return false for 'equality'.
4180 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
4181 CC == ISD::SETULT)
4182 CondCode = ARMCC::GT;
4183
4184 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
4185 // to swap the compare operands.
4186 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
4187 CC == ISD::SETULT)
4188 swpCmpOps = true;
4189
4190 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
4191 // If we have an unordered opcode, we need to swap the operands to the VSEL
4192 // instruction (effectively negating the condition).
4193 //
4194 // This also has the effect of swapping which one of 'less' or 'greater'
4195 // returns true, so we also swap the compare operands. It also switches
4196 // whether we return true for 'equality', so we compensate by picking the
4197 // opposite condition code to our original choice.
4198 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
4199 CC == ISD::SETUGT) {
4200 swpCmpOps = !swpCmpOps;
4201 swpVselOps = !swpVselOps;
4202 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
4203 }
4204
4205 // 'ordered' is 'anything but unordered', so use the VS condition code and
4206 // swap the VSEL operands.
4207 if (CC == ISD::SETO) {
4208 CondCode = ARMCC::VS;
4209 swpVselOps = true;
4210 }
4211
4212 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
4213 // code and swap the VSEL operands.
4214 if (CC == ISD::SETUNE) {
4215 CondCode = ARMCC::EQ;
4216 swpVselOps = true;
4217 }
4218}
4219
4220SDValue ARMTargetLowering::getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal,
4221 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
4222 SDValue Cmp, SelectionDAG &DAG) const {
4223 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
4224 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4225 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
4226 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
4227 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
4228
4229 SDValue TrueLow = TrueVal.getValue(0);
4230 SDValue TrueHigh = TrueVal.getValue(1);
4231 SDValue FalseLow = FalseVal.getValue(0);
4232 SDValue FalseHigh = FalseVal.getValue(1);
4233
4234 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
4235 ARMcc, CCR, Cmp);
4236 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
4237 ARMcc, CCR, duplicateCmp(Cmp, DAG));
4238
4239 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
4240 } else {
4241 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
4242 Cmp);
4243 }
4244}
4245
4246static bool isGTorGE(ISD::CondCode CC) {
4247 return CC == ISD::SETGT || CC == ISD::SETGE;
4248}
4249
4250static bool isLTorLE(ISD::CondCode CC) {
4251 return CC == ISD::SETLT || CC == ISD::SETLE;
4252}
4253
4254// See if a conditional (LHS CC RHS ? TrueVal : FalseVal) is lower-saturating.
4255// All of these conditions (and their <= and >= counterparts) will do:
4256// x < k ? k : x
4257// x > k ? x : k
4258// k < x ? x : k
4259// k > x ? k : x
4260static bool isLowerSaturate(const SDValue LHS, const SDValue RHS,
4261 const SDValue TrueVal, const SDValue FalseVal,
4262 const ISD::CondCode CC, const SDValue K) {
4263 return (isGTorGE(CC) &&
4264 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal))) ||
4265 (isLTorLE(CC) &&
4266 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal)));
4267}
4268
4269// Similar to isLowerSaturate(), but checks for upper-saturating conditions.
4270static bool isUpperSaturate(const SDValue LHS, const SDValue RHS,
4271 const SDValue TrueVal, const SDValue FalseVal,
4272 const ISD::CondCode CC, const SDValue K) {
4273 return (isGTorGE(CC) &&
4274 ((K == RHS && K == TrueVal) || (K == LHS && K == FalseVal))) ||
4275 (isLTorLE(CC) &&
4276 ((K == LHS && K == TrueVal) || (K == RHS && K == FalseVal)));
4277}
4278
4279// Check if two chained conditionals could be converted into SSAT or USAT.
4280//
4281// SSAT can replace a set of two conditional selectors that bound a number to an
4282// interval of type [k, ~k] when k + 1 is a power of 2. Here are some examples:
4283//
4284// x < -k ? -k : (x > k ? k : x)
4285// x < -k ? -k : (x < k ? x : k)
4286// x > -k ? (x > k ? k : x) : -k
4287// x < k ? (x < -k ? -k : x) : k
4288// etc.
4289//
4290// USAT works similarily to SSAT but bounds on the interval [0, k] where k + 1 is
4291// a power of 2.
4292//
4293// It returns true if the conversion can be done, false otherwise.
4294// Additionally, the variable is returned in parameter V, the constant in K and
4295// usat is set to true if the conditional represents an unsigned saturation
4296static bool isSaturatingConditional(const SDValue &Op, SDValue &V,
4297 uint64_t &K, bool &usat) {
4298 SDValue LHS1 = Op.getOperand(0);
4299 SDValue RHS1 = Op.getOperand(1);
4300 SDValue TrueVal1 = Op.getOperand(2);
4301 SDValue FalseVal1 = Op.getOperand(3);
4302 ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4303
4304 const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
4305 if (Op2.getOpcode() != ISD::SELECT_CC)
4306 return false;
4307
4308 SDValue LHS2 = Op2.getOperand(0);
4309 SDValue RHS2 = Op2.getOperand(1);
4310 SDValue TrueVal2 = Op2.getOperand(2);
4311 SDValue FalseVal2 = Op2.getOperand(3);
4312 ISD::CondCode CC2 = cast<CondCodeSDNode>(Op2.getOperand(4))->get();
4313
4314 // Find out which are the constants and which are the variables
4315 // in each conditional
4316 SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
4317 ? &RHS1
4318 : nullptr;
4319 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
4320 ? &RHS2
4321 : nullptr;
4322 SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
4323 SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
4324 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
4325 SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
4326
4327 // We must detect cases where the original operations worked with 16- or
4328 // 8-bit values. In such case, V2Tmp != V2 because the comparison operations
4329 // must work with sign-extended values but the select operations return
4330 // the original non-extended value.
4331 SDValue V2TmpReg = V2Tmp;
4332 if (V2Tmp->getOpcode() == ISD::SIGN_EXTEND_INREG)
4333 V2TmpReg = V2Tmp->getOperand(0);
4334
4335 // Check that the registers and the constants have the correct values
4336 // in both conditionals
4337 if (!K1 || !K2 || *K1 == Op2 || *K2 != K2Tmp || V1Tmp != V2Tmp ||
4338 V2TmpReg != V2)
4339 return false;
4340
4341 // Figure out which conditional is saturating the lower/upper bound.
4342 const SDValue *LowerCheckOp =
4343 isLowerSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4344 ? &Op
4345 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4346 ? &Op2
4347 : nullptr;
4348 const SDValue *UpperCheckOp =
4349 isUpperSaturate(LHS1, RHS1, TrueVal1, FalseVal1, CC1, *K1)
4350 ? &Op
4351 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2)
4352 ? &Op2
4353 : nullptr;
4354
4355 if (!UpperCheckOp || !LowerCheckOp || LowerCheckOp == UpperCheckOp)
4356 return false;
4357
4358 // Check that the constant in the lower-bound check is
4359 // the opposite of the constant in the upper-bound check
4360 // in 1's complement.
4361 int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
4362 int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
4363 int64_t PosVal = std::max(Val1, Val2);
4364 int64_t NegVal = std::min(Val1, Val2);
4365
4366 if (((Val1 > Val2 && UpperCheckOp == &Op) ||
4367 (Val1 < Val2 && UpperCheckOp == &Op2)) &&
4368 isPowerOf2_64(PosVal + 1)) {
4369
4370 // Handle the difference between USAT (unsigned) and SSAT (signed) saturation
4371 if (Val1 == ~Val2)
4372 usat = false;
4373 else if (NegVal == 0)
4374 usat = true;
4375 else
4376 return false;
4377
4378 V = V2;
4379 K = (uint64_t)PosVal; // At this point, PosVal is guaranteed to be positive
4380
4381 return true;
4382 }
4383
4384 return false;
4385}
4386
4387SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4388 EVT VT = Op.getValueType();
4389 SDLoc dl(Op);
4390
4391 // Try to convert two saturating conditional selects into a single SSAT
4392 SDValue SatValue;
4393 uint64_t SatConstant;
4394 bool SatUSat;
4395 if (((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2()) &&
4396 isSaturatingConditional(Op, SatValue, SatConstant, SatUSat)) {
4397 if (SatUSat)
4398 return DAG.getNode(ARMISD::USAT, dl, VT, SatValue,
4399 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4400 else
4401 return DAG.getNode(ARMISD::SSAT, dl, VT, SatValue,
4402 DAG.getConstant(countTrailingOnes(SatConstant), dl, VT));
4403 }
4404
4405 SDValue LHS = Op.getOperand(0);
4406 SDValue RHS = Op.getOperand(1);
4407 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4408 SDValue TrueVal = Op.getOperand(2);
4409 SDValue FalseVal = Op.getOperand(3);
4410
4411 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4412 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4413 dl);
4414
4415 // If softenSetCCOperands only returned one value, we should compare it to
4416 // zero.
4417 if (!RHS.getNode()) {
4418 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4419 CC = ISD::SETNE;
4420 }
4421 }
4422
4423 if (LHS.getValueType() == MVT::i32) {
4424 // Try to generate VSEL on ARMv8.
4425 // The VSEL instruction can't use all the usual ARM condition
4426 // codes: it only has two bits to select the condition code, so it's
4427 // constrained to use only GE, GT, VS and EQ.
4428 //
4429 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
4430 // swap the operands of the previous compare instruction (effectively
4431 // inverting the compare condition, swapping 'less' and 'greater') and
4432 // sometimes need to swap the operands to the VSEL (which inverts the
4433 // condition in the sense of firing whenever the previous condition didn't)
4434 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4435 TrueVal.getValueType() == MVT::f64)) {
4436 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4437 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
4438 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
4439 CC = ISD::getSetCCInverse(CC, true);
4440 std::swap(TrueVal, FalseVal);
4441 }
4442 }
4443
4444 SDValue ARMcc;
4445 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4446 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4447 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4448 }
4449
4450 ARMCC::CondCodes CondCode, CondCode2;
4451 bool InvalidOnQNaN;
4452 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4453
4454 // Try to generate VMAXNM/VMINNM on ARMv8.
4455 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
4456 TrueVal.getValueType() == MVT::f64)) {
4457 bool swpCmpOps = false;
4458 bool swpVselOps = false;
4459 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
4460
4461 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
4462 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
4463 if (swpCmpOps)
4464 std::swap(LHS, RHS);
4465 if (swpVselOps)
4466 std::swap(TrueVal, FalseVal);
4467 }
4468 }
4469
4470 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4471 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4472 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4473 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
4474 if (CondCode2 != ARMCC::AL) {
4475 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
4476 // FIXME: Needs another CMP because flag can have but one use.
4477 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4478 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
4479 }
4480 return Result;
4481}
4482
4483/// canChangeToInt - Given the fp compare operand, return true if it is suitable
4484/// to morph to an integer compare sequence.
4485static bool canChangeToInt(SDValue Op, bool &SeenZero,
4486 const ARMSubtarget *Subtarget) {
4487 SDNode *N = Op.getNode();
4488 if (!N->hasOneUse())
4489 // Otherwise it requires moving the value from fp to integer registers.
4490 return false;
4491 if (!N->getNumValues())
4492 return false;
4493 EVT VT = Op.getValueType();
4494 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
4495 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
4496 // vmrs are very slow, e.g. cortex-a8.
4497 return false;
4498
4499 if (isFloatingPointZero(Op)) {
4500 SeenZero = true;
4501 return true;
4502 }
4503 return ISD::isNormalLoad(N);
4504}
4505
4506static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
4507 if (isFloatingPointZero(Op))
4508 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
4509
4510 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
4511 return DAG.getLoad(MVT::i32, SDLoc(Op), Ld->getChain(), Ld->getBasePtr(),
4512 Ld->getPointerInfo(), Ld->getAlignment(),
4513 Ld->getMemOperand()->getFlags());
4514
4515 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4515)
;
4516}
4517
4518static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
4519 SDValue &RetVal1, SDValue &RetVal2) {
4520 SDLoc dl(Op);
4521
4522 if (isFloatingPointZero(Op)) {
4523 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
4524 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
4525 return;
4526 }
4527
4528 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
4529 SDValue Ptr = Ld->getBasePtr();
4530 RetVal1 =
4531 DAG.getLoad(MVT::i32, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
4532 Ld->getAlignment(), Ld->getMemOperand()->getFlags());
4533
4534 EVT PtrType = Ptr.getValueType();
4535 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
4536 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
4537 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
4538 RetVal2 = DAG.getLoad(MVT::i32, dl, Ld->getChain(), NewPtr,
4539 Ld->getPointerInfo().getWithOffset(4), NewAlign,
4540 Ld->getMemOperand()->getFlags());
4541 return;
4542 }
4543
4544 llvm_unreachable("Unknown VFP cmp argument!")::llvm::llvm_unreachable_internal("Unknown VFP cmp argument!"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4544)
;
4545}
4546
4547/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
4548/// f32 and even f64 comparisons to integer ones.
4549SDValue
4550ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
4551 SDValue Chain = Op.getOperand(0);
4552 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4553 SDValue LHS = Op.getOperand(2);
4554 SDValue RHS = Op.getOperand(3);
4555 SDValue Dest = Op.getOperand(4);
4556 SDLoc dl(Op);
4557
4558 bool LHSSeenZero = false;
4559 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
4560 bool RHSSeenZero = false;
4561 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
4562 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
4563 // If unsafe fp math optimization is enabled and there are no other uses of
4564 // the CMP operands, and the condition code is EQ or NE, we can optimize it
4565 // to an integer comparison.
4566 if (CC == ISD::SETOEQ)
4567 CC = ISD::SETEQ;
4568 else if (CC == ISD::SETUNE)
4569 CC = ISD::SETNE;
4570
4571 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4572 SDValue ARMcc;
4573 if (LHS.getValueType() == MVT::f32) {
4574 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4575 bitcastf32Toi32(LHS, DAG), Mask);
4576 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
4577 bitcastf32Toi32(RHS, DAG), Mask);
4578 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4579 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4580 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4581 Chain, Dest, ARMcc, CCR, Cmp);
4582 }
4583
4584 SDValue LHS1, LHS2;
4585 SDValue RHS1, RHS2;
4586 expandf64Toi32(LHS, DAG, LHS1, LHS2);
4587 expandf64Toi32(RHS, DAG, RHS1, RHS2);
4588 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
4589 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
4590 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
4591 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4592 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4593 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
4594 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
4595 }
4596
4597 return SDValue();
4598}
4599
4600SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
4601 SDValue Chain = Op.getOperand(0);
4602 SDValue Cond = Op.getOperand(1);
4603 SDValue Dest = Op.getOperand(2);
4604 SDLoc dl(Op);
4605
4606 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4607 // instruction.
4608 unsigned Opc = Cond.getOpcode();
4609 if (Cond.getResNo() == 1 &&
4610 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4611 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
4612 // Only lower legal XALUO ops.
4613 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
4614 return SDValue();
4615
4616 // The actual operation with overflow check.
4617 SDValue Value, OverflowCmp;
4618 SDValue ARMcc;
4619 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
4620
4621 // Reverse the condition code.
4622 ARMCC::CondCodes CondCode =
4623 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4624 CondCode = ARMCC::getOppositeCondition(CondCode);
4625 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4626 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4627
4628 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4629 OverflowCmp);
4630 }
4631
4632 return SDValue();
4633}
4634
4635SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
4636 SDValue Chain = Op.getOperand(0);
4637 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
4638 SDValue LHS = Op.getOperand(2);
4639 SDValue RHS = Op.getOperand(3);
4640 SDValue Dest = Op.getOperand(4);
4641 SDLoc dl(Op);
4642
4643 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
4644 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
4645 dl);
4646
4647 // If softenSetCCOperands only returned one value, we should compare it to
4648 // zero.
4649 if (!RHS.getNode()) {
4650 RHS = DAG.getConstant(0, dl, LHS.getValueType());
4651 CC = ISD::SETNE;
4652 }
4653 }
4654
4655 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4656 // instruction.
4657 unsigned Opc = LHS.getOpcode();
4658 if (LHS.getResNo() == 1 && (isOneConstant(RHS) || isNullConstant(RHS)) &&
4659 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
4660 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO) &&
4661 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
4662 // Only lower legal XALUO ops.
4663 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
4664 return SDValue();
4665
4666 // The actual operation with overflow check.
4667 SDValue Value, OverflowCmp;
4668 SDValue ARMcc;
4669 std::tie(Value, OverflowCmp) = getARMXALUOOp(LHS.getValue(0), DAG, ARMcc);
4670
4671 if ((CC == ISD::SETNE) != isOneConstant(RHS)) {
4672 // Reverse the condition code.
4673 ARMCC::CondCodes CondCode =
4674 (ARMCC::CondCodes)cast<const ConstantSDNode>(ARMcc)->getZExtValue();
4675 CondCode = ARMCC::getOppositeCondition(CondCode);
4676 ARMcc = DAG.getConstant(CondCode, SDLoc(ARMcc), MVT::i32);
4677 }
4678 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4679
4680 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, CCR,
4681 OverflowCmp);
4682 }
4683
4684 if (LHS.getValueType() == MVT::i32) {
4685 SDValue ARMcc;
4686 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
4687 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4688 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
4689 Chain, Dest, ARMcc, CCR, Cmp);
4690 }
4691
4692 if (getTargetMachine().Options.UnsafeFPMath &&
4693 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
4694 CC == ISD::SETNE || CC == ISD::SETUNE)) {
4695 if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
4696 return Result;
4697 }
4698
4699 ARMCC::CondCodes CondCode, CondCode2;
4700 bool InvalidOnQNaN;
4701 FPCCToARMCC(CC, CondCode, CondCode2, InvalidOnQNaN);
4702
4703 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
4704 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl, InvalidOnQNaN);
4705 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4706 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
4707 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
4708 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4709 if (CondCode2 != ARMCC::AL) {
4710 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
4711 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
4712 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
4713 }
4714 return Res;
4715}
4716
4717SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
4718 SDValue Chain = Op.getOperand(0);
4719 SDValue Table = Op.getOperand(1);
4720 SDValue Index = Op.getOperand(2);
4721 SDLoc dl(Op);
4722
4723 EVT PTy = getPointerTy(DAG.getDataLayout());
4724 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
4725 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
4726 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
4727 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
4728 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Index);
4729 if (Subtarget->isThumb2() || (Subtarget->hasV8MBaselineOps() && Subtarget->isThumb())) {
4730 // Thumb2 and ARMv8-M use a two-level jump. That is, it jumps into the jump table
4731 // which does another jump to the destination. This also makes it easier
4732 // to translate it to TBB / TBH later (Thumb2 only).
4733 // FIXME: This might not work if the function is extremely large.
4734 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
4735 Addr, Op.getOperand(2), JTI);
4736 }
4737 if (isPositionIndependent() || Subtarget->isROPI()) {
4738 Addr =
4739 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
4740 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4741 Chain = Addr.getValue(1);
4742 Addr = DAG.getNode(ISD::ADD, dl, PTy, Table, Addr);
4743 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4744 } else {
4745 Addr =
4746 DAG.getLoad(PTy, dl, Chain, Addr,
4747 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()));
4748 Chain = Addr.getValue(1);
4749 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
4750 }
4751}
4752
4753static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
4754 EVT VT = Op.getValueType();
4755 SDLoc dl(Op);
4756
4757 if (Op.getValueType().getVectorElementType() == MVT::i32) {
4758 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
4759 return Op;
4760 return DAG.UnrollVectorOp(Op.getNode());
4761 }
4762
4763 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4764, __extension__ __PRETTY_FUNCTION__))
4764 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4f32 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4f32 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4764, __extension__ __PRETTY_FUNCTION__))
;
4765 if (VT != MVT::v4i16)
4766 return DAG.UnrollVectorOp(Op.getNode());
4767
4768 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
4769 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
4770}
4771
4772SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
4773 EVT VT = Op.getValueType();
4774 if (VT.isVector())
4775 return LowerVectorFP_TO_INT(Op, DAG);
4776 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
4777 RTLIB::Libcall LC;
4778 if (Op.getOpcode() == ISD::FP_TO_SINT)
4779 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
4780 Op.getValueType());
4781 else
4782 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
4783 Op.getValueType());
4784 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4785 /*isSigned*/ false, SDLoc(Op)).first;
4786 }
4787
4788 return Op;
4789}
4790
4791static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4792 EVT VT = Op.getValueType();
4793 SDLoc dl(Op);
4794
4795 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4796 if (VT.getVectorElementType() == MVT::f32)
4797 return Op;
4798 return DAG.UnrollVectorOp(Op.getNode());
4799 }
4800
4801 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4802, __extension__ __PRETTY_FUNCTION__))
4802 "Invalid type for custom lowering!")(static_cast <bool> (Op.getOperand(0).getValueType() ==
MVT::v4i16 && "Invalid type for custom lowering!") ?
void (0) : __assert_fail ("Op.getOperand(0).getValueType() == MVT::v4i16 && \"Invalid type for custom lowering!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4802, __extension__ __PRETTY_FUNCTION__))
;
4803 if (VT != MVT::v4f32)
4804 return DAG.UnrollVectorOp(Op.getNode());
4805
4806 unsigned CastOpc;
4807 unsigned Opc;
4808 switch (Op.getOpcode()) {
4809 default: llvm_unreachable("Invalid opcode!")::llvm::llvm_unreachable_internal("Invalid opcode!", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4809)
;
4810 case ISD::SINT_TO_FP:
4811 CastOpc = ISD::SIGN_EXTEND;
4812 Opc = ISD::SINT_TO_FP;
4813 break;
4814 case ISD::UINT_TO_FP:
4815 CastOpc = ISD::ZERO_EXTEND;
4816 Opc = ISD::UINT_TO_FP;
4817 break;
4818 }
4819
4820 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4821 return DAG.getNode(Opc, dl, VT, Op);
4822}
4823
4824SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4825 EVT VT = Op.getValueType();
4826 if (VT.isVector())
4827 return LowerVectorINT_TO_FP(Op, DAG);
4828 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4829 RTLIB::Libcall LC;
4830 if (Op.getOpcode() == ISD::SINT_TO_FP)
4831 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4832 Op.getValueType());
4833 else
4834 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4835 Op.getValueType());
4836 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4837 /*isSigned*/ false, SDLoc(Op)).first;
4838 }
4839
4840 return Op;
4841}
4842
4843SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4844 // Implement fcopysign with a fabs and a conditional fneg.
4845 SDValue Tmp0 = Op.getOperand(0);
4846 SDValue Tmp1 = Op.getOperand(1);
4847 SDLoc dl(Op);
4848 EVT VT = Op.getValueType();
4849 EVT SrcVT = Tmp1.getValueType();
4850 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4851 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4852 bool UseNEON = !InGPR && Subtarget->hasNEON();
4853
4854 if (UseNEON) {
4855 // Use VBSL to copy the sign bit.
4856 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4857 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4858 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4859 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4860 if (VT == MVT::f64)
4861 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4862 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4863 DAG.getConstant(32, dl, MVT::i32));
4864 else /*if (VT == MVT::f32)*/
4865 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4866 if (SrcVT == MVT::f32) {
4867 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4868 if (VT == MVT::f64)
4869 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4870 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4871 DAG.getConstant(32, dl, MVT::i32));
4872 } else if (VT == MVT::f32)
4873 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4874 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4875 DAG.getConstant(32, dl, MVT::i32));
4876 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4877 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4878
4879 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4880 dl, MVT::i32);
4881 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4882 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4883 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4884
4885 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4886 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4887 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4888 if (VT == MVT::f32) {
4889 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4890 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4891 DAG.getConstant(0, dl, MVT::i32));
4892 } else {
4893 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4894 }
4895
4896 return Res;
4897 }
4898
4899 // Bitcast operand 1 to i32.
4900 if (SrcVT == MVT::f64)
4901 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4902 Tmp1).getValue(1);
4903 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4904
4905 // Or in the signbit with integer operations.
4906 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4907 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4908 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4909 if (VT == MVT::f32) {
4910 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4911 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4912 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4913 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4914 }
4915
4916 // f64: Or the high part with signbit and then combine two parts.
4917 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4918 Tmp0);
4919 SDValue Lo = Tmp0.getValue(0);
4920 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4921 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4922 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4923}
4924
4925SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4926 MachineFunction &MF = DAG.getMachineFunction();
4927 MachineFrameInfo &MFI = MF.getFrameInfo();
4928 MFI.setReturnAddressIsTaken(true);
4929
4930 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4931 return SDValue();
4932
4933 EVT VT = Op.getValueType();
4934 SDLoc dl(Op);
4935 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4936 if (Depth) {
4937 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4938 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
4939 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4940 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4941 MachinePointerInfo());
4942 }
4943
4944 // Return LR, which contains the return address. Mark it an implicit live-in.
4945 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4946 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4947}
4948
4949SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4950 const ARMBaseRegisterInfo &ARI =
4951 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4952 MachineFunction &MF = DAG.getMachineFunction();
4953 MachineFrameInfo &MFI = MF.getFrameInfo();
4954 MFI.setFrameAddressIsTaken(true);
4955
4956 EVT VT = Op.getValueType();
4957 SDLoc dl(Op); // FIXME probably not meaningful
4958 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4959 unsigned FrameReg = ARI.getFrameRegister(MF);
4960 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4961 while (Depth--)
4962 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4963 MachinePointerInfo());
4964 return FrameAddr;
4965}
4966
4967// FIXME? Maybe this could be a TableGen attribute on some registers and
4968// this table could be generated automatically from RegInfo.
4969unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4970 SelectionDAG &DAG) const {
4971 unsigned Reg = StringSwitch<unsigned>(RegName)
4972 .Case("sp", ARM::SP)
4973 .Default(0);
4974 if (Reg)
4975 return Reg;
4976 report_fatal_error(Twine("Invalid register name \""
4977 + StringRef(RegName) + "\"."));
4978}
4979
4980// Result is 64 bit value so split into two 32 bit values and return as a
4981// pair of values.
4982static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
4983 SelectionDAG &DAG) {
4984 SDLoc DL(N);
4985
4986 // This function is only supposed to be called for i64 type destination.
4987 assert(N->getValueType(0) == MVT::i64(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4988, __extension__ __PRETTY_FUNCTION__))
4988 && "ExpandREAD_REGISTER called for non-i64 type result.")(static_cast <bool> (N->getValueType(0) == MVT::i64 &&
"ExpandREAD_REGISTER called for non-i64 type result.") ? void
(0) : __assert_fail ("N->getValueType(0) == MVT::i64 && \"ExpandREAD_REGISTER called for non-i64 type result.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 4988, __extension__ __PRETTY_FUNCTION__))
;
4989
4990 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
4991 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
4992 N->getOperand(0),
4993 N->getOperand(1));
4994
4995 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
4996 Read.getValue(1)));
4997 Results.push_back(Read.getOperand(0));
4998}
4999
5000/// \p BC is a bitcast that is about to be turned into a VMOVDRR.
5001/// When \p DstVT, the destination type of \p BC, is on the vector
5002/// register bank and the source of bitcast, \p Op, operates on the same bank,
5003/// it might be possible to combine them, such that everything stays on the
5004/// vector register bank.
5005/// \p return The node that would replace \p BT, if the combine
5006/// is possible.
5007static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
5008 SelectionDAG &DAG) {
5009 SDValue Op = BC->getOperand(0);
5010 EVT DstVT = BC->getValueType(0);
5011
5012 // The only vector instruction that can produce a scalar (remember,
5013 // since the bitcast was about to be turned into VMOVDRR, the source
5014 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
5015 // Moreover, we can do this combine only if there is one use.
5016 // Finally, if the destination type is not a vector, there is not
5017 // much point on forcing everything on the vector bank.
5018 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5019 !Op.hasOneUse())
5020 return SDValue();
5021
5022 // If the index is not constant, we will introduce an additional
5023 // multiply that will stick.
5024 // Give up in that case.
5025 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5026 if (!Index)
5027 return SDValue();
5028 unsigned DstNumElt = DstVT.getVectorNumElements();
5029
5030 // Compute the new index.
5031 const APInt &APIntIndex = Index->getAPIntValue();
5032 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
5033 NewIndex *= APIntIndex;
5034 // Check if the new constant index fits into i32.
5035 if (NewIndex.getBitWidth() > 32)
5036 return SDValue();
5037
5038 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
5039 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
5040 SDLoc dl(Op);
5041 SDValue ExtractSrc = Op.getOperand(0);
5042 EVT VecVT = EVT::getVectorVT(
5043 *DAG.getContext(), DstVT.getScalarType(),
5044 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
5045 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
5046 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
5047 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
5048}
5049
5050/// ExpandBITCAST - If the target supports VFP, this function is called to
5051/// expand a bit convert where either the source or destination type is i64 to
5052/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
5053/// operand type is illegal (e.g., v2f32 for a target that doesn't support
5054/// vectors), since the legalizer won't know what to do with that.
5055static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
5056 const ARMSubtarget *Subtarget) {
5057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5058 SDLoc dl(N);
5059 SDValue Op = N->getOperand(0);
5060
5061 // This function is only supposed to be called for i64 types, either as the
5062 // source or destination of the bit convert.
5063 EVT SrcVT = Op.getValueType();
5064 EVT DstVT = N->getValueType(0);
5065 const bool HasFullFP16 = Subtarget->hasFullFP16();
5066
5067 if (SrcVT == MVT::f32 && DstVT == MVT::i32) {
5068 // FullFP16: half values are passed in S-registers, and we don't
5069 // need any of the bitcast and moves:
5070 //
5071 // t2: f32,ch = CopyFromReg t0, Register:f32 %0
5072 // t5: i32 = bitcast t2
5073 // t18: f16 = ARMISD::VMOVhr t5
5074 if (Op.getOpcode() != ISD::CopyFromReg ||
5075 Op.getValueType() != MVT::f32)
5076 return SDValue();
5077
5078 auto Move = N->use_begin();
5079 if (Move->getOpcode() != ARMISD::VMOVhr)
5080 return SDValue();
5081
5082 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
5083 SDValue Copy = DAG.getNode(ISD::CopyFromReg, SDLoc(Op), MVT::f16, Ops);
5084 DAG.ReplaceAllUsesWith(*Move, &Copy);
5085 return Copy;
5086 }
5087
5088 if (SrcVT == MVT::i16 && DstVT == MVT::f16) {
5089 if (!HasFullFP16)
5090 return SDValue();
5091 // SoftFP: read half-precision arguments:
5092 //
5093 // t2: i32,ch = ...
5094 // t7: i16 = truncate t2 <~~~~ Op
5095 // t8: f16 = bitcast t7 <~~~~ N
5096 //
5097 if (Op.getOperand(0).getValueType() == MVT::i32)
5098 return DAG.getNode(ARMISD::VMOVhr, SDLoc(Op),
5099 MVT::f16, Op.getOperand(0));
5100
5101 return SDValue();
5102 }
5103
5104 // Half-precision return values
5105 if (SrcVT == MVT::f16 && DstVT == MVT::i16) {
5106 if (!HasFullFP16)
5107 return SDValue();
5108 //
5109 // t11: f16 = fadd t8, t10
5110 // t12: i16 = bitcast t11 <~~~ SDNode N
5111 // t13: i32 = zero_extend t12
5112 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t13
5113 // t17: ch = ARMISD::RET_FLAG t16, Register:i32 %r0, t16:1
5114 //
5115 // transform this into:
5116 //
5117 // t20: i32 = ARMISD::VMOVrh t11
5118 // t16: ch,glue = CopyToReg t0, Register:i32 %r0, t20
5119 //
5120 auto ZeroExtend = N->use_begin();
5121 if (N->use_size() != 1 || ZeroExtend->getOpcode() != ISD::ZERO_EXTEND ||
5122 ZeroExtend->getValueType(0) != MVT::i32)
5123 return SDValue();
5124
5125 auto Copy = ZeroExtend->use_begin();
5126 if (Copy->getOpcode() == ISD::CopyToReg &&
5127 Copy->use_begin()->getOpcode() == ARMISD::RET_FLAG) {
5128 SDValue Cvt = DAG.getNode(ARMISD::VMOVrh, SDLoc(Op), MVT::i32, Op);
5129 DAG.ReplaceAllUsesWith(*ZeroExtend, &Cvt);
5130 return Cvt;
5131 }
5132 return SDValue();
5133 }
5134
5135 if (!(SrcVT == MVT::i64 || DstVT == MVT::i64))
5136 return SDValue();
5137
5138 // Turn i64->f64 into VMOVDRR.
5139 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
5140 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
5141 // if we can combine the bitcast with its source.
5142 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
5143 return Val;
5144
5145 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5146 DAG.getConstant(0, dl, MVT::i32));
5147 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
5148 DAG.getConstant(1, dl, MVT::i32));
5149 return DAG.getNode(ISD::BITCAST, dl, DstVT,
5150 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
5151 }
5152
5153 // Turn f64->i64 into VMOVRRD.
5154 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
5155 SDValue Cvt;
5156 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
5157 SrcVT.getVectorNumElements() > 1)
5158 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5159 DAG.getVTList(MVT::i32, MVT::i32),
5160 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
5161 else
5162 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
5163 DAG.getVTList(MVT::i32, MVT::i32), Op);
5164 // Merge the pieces into a single i64 value.
5165 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
5166 }
5167
5168 return SDValue();
5169}
5170
5171/// getZeroVector - Returns a vector of specified type with all zero elements.
5172/// Zero vectors are used to represent vector negation and in those cases
5173/// will be implemented with the NEON VNEG instruction. However, VNEG does
5174/// not support i64 elements, so sometimes the zero vectors will need to be
5175/// explicitly constructed. Regardless, use a canonical VMOV to create the
5176/// zero vector.
5177static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, const SDLoc &dl) {
5178 assert(VT.isVector() && "Expected a vector type")(static_cast <bool> (VT.isVector() && "Expected a vector type"
) ? void (0) : __assert_fail ("VT.isVector() && \"Expected a vector type\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5178, __extension__ __PRETTY_FUNCTION__))
;
5179 // The canonical modified immediate encoding of a zero vector is....0!
5180 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
5181 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5182 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
5183 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5184}
5185
5186/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
5187/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5188SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
5189 SelectionDAG &DAG) const {
5190 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5190, __extension__ __PRETTY_FUNCTION__))
;
5191 EVT VT = Op.getValueType();
5192 unsigned VTBits = VT.getSizeInBits();
5193 SDLoc dl(Op);
5194 SDValue ShOpLo = Op.getOperand(0);
5195 SDValue ShOpHi = Op.getOperand(1);
5196 SDValue ShAmt = Op.getOperand(2);
5197 SDValue ARMcc;
5198 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5199 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
5200
5201 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SRA_PARTS ||
Op.getOpcode() == ISD::SRL_PARTS) ? void (0) : __assert_fail
("Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5201, __extension__ __PRETTY_FUNCTION__))
;
5202
5203 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5204 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5205 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
5206 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5207 DAG.getConstant(VTBits, dl, MVT::i32));
5208 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
5209 SDValue LoSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5210 SDValue LoBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
5211 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5212 ISD::SETGE, ARMcc, DAG, dl);
5213 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift,
5214 ARMcc, CCR, CmpLo);
5215
5216 SDValue HiSmallShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
5217 SDValue HiBigShift = Opc == ISD::SRA
5218 ? DAG.getNode(Opc, dl, VT, ShOpHi,
5219 DAG.getConstant(VTBits - 1, dl, VT))
5220 : DAG.getConstant(0, dl, VT);
5221 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5222 ISD::SETGE, ARMcc, DAG, dl);
5223 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5224 ARMcc, CCR, CmpHi);
5225
5226 SDValue Ops[2] = { Lo, Hi };
5227 return DAG.getMergeValues(Ops, dl);
5228}
5229
5230/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
5231/// i32 values and take a 2 x i32 value to shift plus a shift amount.
5232SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
5233 SelectionDAG &DAG) const {
5234 assert(Op.getNumOperands() == 3 && "Not a double-shift!")(static_cast <bool> (Op.getNumOperands() == 3 &&
"Not a double-shift!") ? void (0) : __assert_fail ("Op.getNumOperands() == 3 && \"Not a double-shift!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5234, __extension__ __PRETTY_FUNCTION__))
;
5235 EVT VT = Op.getValueType();
5236 unsigned VTBits = VT.getSizeInBits();
5237 SDLoc dl(Op);
5238 SDValue ShOpLo = Op.getOperand(0);
5239 SDValue ShOpHi = Op.getOperand(1);
5240 SDValue ShAmt = Op.getOperand(2);
5241 SDValue ARMcc;
5242 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5243
5244 assert(Op.getOpcode() == ISD::SHL_PARTS)(static_cast <bool> (Op.getOpcode() == ISD::SHL_PARTS) ?
void (0) : __assert_fail ("Op.getOpcode() == ISD::SHL_PARTS"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5244, __extension__ __PRETTY_FUNCTION__))
;
5245 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
5246 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
5247 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
5248 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
5249 SDValue HiSmallShift = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
5250
5251 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
5252 DAG.getConstant(VTBits, dl, MVT::i32));
5253 SDValue HiBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
5254 SDValue CmpHi = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5255 ISD::SETGE, ARMcc, DAG, dl);
5256 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift,
5257 ARMcc, CCR, CmpHi);
5258
5259 SDValue CmpLo = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
5260 ISD::SETGE, ARMcc, DAG, dl);
5261 SDValue LoSmallShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
5262 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift,
5263 DAG.getConstant(0, dl, VT), ARMcc, CCR, CmpLo);
5264
5265 SDValue Ops[2] = { Lo, Hi };
5266 return DAG.getMergeValues(Ops, dl);
5267}
5268
5269SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5270 SelectionDAG &DAG) const {
5271 // The rounding mode is in bits 23:22 of the FPSCR.
5272 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
5273 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
5274 // so that the shift + and get folded into a bitfield extract.
5275 SDLoc dl(Op);
5276 SDValue Ops[] = { DAG.getEntryNode(),
5277 DAG.getConstant(Intrinsic::arm_get_fpscr, dl, MVT::i32) };
5278
5279 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_W_CHAIN, dl, MVT::i32, Ops);
5280 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
5281 DAG.getConstant(1U << 22, dl, MVT::i32));
5282 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
5283 DAG.getConstant(22, dl, MVT::i32));
5284 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
5285 DAG.getConstant(3, dl, MVT::i32));
5286}
5287
5288static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
5289 const ARMSubtarget *ST) {
5290 SDLoc dl(N);
5291 EVT VT = N->getValueType(0);
5292 if (VT.isVector()) {
5293 assert(ST->hasNEON())(static_cast <bool> (ST->hasNEON()) ? void (0) : __assert_fail
("ST->hasNEON()", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5293, __extension__ __PRETTY_FUNCTION__))
;
5294
5295 // Compute the least significant set bit: LSB = X & -X
5296 SDValue X = N->getOperand(0);
5297 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
5298 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
5299
5300 EVT ElemTy = VT.getVectorElementType();
5301
5302 if (ElemTy == MVT::i8) {
5303 // Compute with: cttz(x) = ctpop(lsb - 1)
5304 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5305 DAG.getTargetConstant(1, dl, ElemTy));
5306 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5307 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
5308 }
5309
5310 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
5311 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
5312 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
5313 unsigned NumBits = ElemTy.getSizeInBits();
5314 SDValue WidthMinus1 =
5315 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5316 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
5317 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
5318 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
5319 }
5320
5321 // Compute with: cttz(x) = ctpop(lsb - 1)
5322
5323 // Since we can only compute the number of bits in a byte with vcnt.8, we
5324 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
5325 // and i64.
5326
5327 // Compute LSB - 1.
5328 SDValue Bits;
5329 if (ElemTy == MVT::i64) {
5330 // Load constant 0xffff'ffff'ffff'ffff to register.
5331 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5332 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
5333 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
5334 } else {
5335 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
5336 DAG.getTargetConstant(1, dl, ElemTy));
5337 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
5338 }
5339
5340 // Count #bits with vcnt.8.
5341 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5342 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
5343 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
5344
5345 // Gather the #bits with vpaddl (pairwise add.)
5346 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5347 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
5348 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5349 Cnt8);
5350 if (ElemTy == MVT::i16)
5351 return Cnt16;
5352
5353 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
5354 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
5355 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5356 Cnt16);
5357 if (ElemTy == MVT::i32)
5358 return Cnt32;
5359
5360 assert(ElemTy == MVT::i64)(static_cast <bool> (ElemTy == MVT::i64) ? void (0) : __assert_fail
("ElemTy == MVT::i64", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5360, __extension__ __PRETTY_FUNCTION__))
;
5361 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5362 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
5363 Cnt32);
5364 return Cnt64;
5365 }
5366
5367 if (!ST->hasV6T2Ops())
5368 return SDValue();
5369
5370 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
5371 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
5372}
5373
5374/// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
5375/// for each 16-bit element from operand, repeated. The basic idea is to
5376/// leverage vcnt to get the 8-bit counts, gather and add the results.
5377///
5378/// Trace for v4i16:
5379/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5380/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
5381/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
5382/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
5383/// [b0 b1 b2 b3 b4 b5 b6 b7]
5384/// +[b1 b0 b3 b2 b5 b4 b7 b6]
5385/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
5386/// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
5387static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
5388 EVT VT = N->getValueType(0);
5389 SDLoc DL(N);
5390
5391 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
5392 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
5393 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
5394 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
5395 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
5396 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
5397}
5398
5399/// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
5400/// bit-count for each 16-bit element from the operand. We need slightly
5401/// different sequencing for v4i16 and v8i16 to stay within NEON's available
5402/// 64/128-bit registers.
5403///
5404/// Trace for v4i16:
5405/// input = [v0 v1 v2 v3 ] (vi 16-bit element)
5406/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
5407/// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
5408/// v4i16:Extracted = [k0 k1 k2 k3 ]
5409static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
5410 EVT VT = N->getValueType(0);
5411 SDLoc DL(N);
5412
5413 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
5414 if (VT.is64BitVector()) {
5415 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
5416 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
5417 DAG.getIntPtrConstant(0, DL));
5418 } else {
5419 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
5420 BitCounts, DAG.getIntPtrConstant(0, DL));
5421 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
5422 }
5423}
5424
5425/// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
5426/// bit-count for each 32-bit element from the operand. The idea here is
5427/// to split the vector into 16-bit elements, leverage the 16-bit count
5428/// routine, and then combine the results.
5429///
5430/// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
5431/// input = [v0 v1 ] (vi: 32-bit elements)
5432/// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
5433/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
5434/// vrev: N0 = [k1 k0 k3 k2 ]
5435/// [k0 k1 k2 k3 ]
5436/// N1 =+[k1 k0 k3 k2 ]
5437/// [k0 k2 k1 k3 ]
5438/// N2 =+[k1 k3 k0 k2 ]
5439/// [k0 k2 k1 k3 ]
5440/// Extended =+[k1 k3 k0 k2 ]
5441/// [k0 k2 ]
5442/// Extracted=+[k1 k3 ]
5443///
5444static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
5445 EVT VT = N->getValueType(0);
5446 SDLoc DL(N);
5447
5448 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
5449
5450 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
5451 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
5452 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
5453 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
5454 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
5455
5456 if (VT.is64BitVector()) {
5457 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
5458 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
5459 DAG.getIntPtrConstant(0, DL));
5460 } else {
5461 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
5462 DAG.getIntPtrConstant(0, DL));
5463 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
5464 }
5465}
5466
5467static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
5468 const ARMSubtarget *ST) {
5469 EVT VT = N->getValueType(0);
5470
5471 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.")(static_cast <bool> (ST->hasNEON() && "Custom ctpop lowering requires NEON."
) ? void (0) : __assert_fail ("ST->hasNEON() && \"Custom ctpop lowering requires NEON.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5471, __extension__ __PRETTY_FUNCTION__))
;
5472 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5474, __extension__ __PRETTY_FUNCTION__))
5473 VT == MVT::v4i16 || VT == MVT::v8i16) &&(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5474, __extension__ __PRETTY_FUNCTION__))
5474 "Unexpected type for custom ctpop lowering")(static_cast <bool> ((VT == MVT::v2i32 || VT == MVT::v4i32
|| VT == MVT::v4i16 || VT == MVT::v8i16) && "Unexpected type for custom ctpop lowering"
) ? void (0) : __assert_fail ("(VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v4i16 || VT == MVT::v8i16) && \"Unexpected type for custom ctpop lowering\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5474, __extension__ __PRETTY_FUNCTION__))
;
5475
5476 if (VT.getVectorElementType() == MVT::i32)
5477 return lowerCTPOP32BitElements(N, DAG);
5478 else
5479 return lowerCTPOP16BitElements(N, DAG);
5480}
5481
5482static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
5483 const ARMSubtarget *ST) {
5484 EVT VT = N->getValueType(0);
5485 SDLoc dl(N);
5486
5487 if (!VT.isVector())
5488 return SDValue();
5489
5490 // Lower vector shifts on NEON to use VSHL.
5491 assert(ST->hasNEON() && "unexpected vector shift")(static_cast <bool> (ST->hasNEON() && "unexpected vector shift"
) ? void (0) : __assert_fail ("ST->hasNEON() && \"unexpected vector shift\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5491, __extension__ __PRETTY_FUNCTION__))
;
5492
5493 // Left shifts translate directly to the vshiftu intrinsic.
5494 if (N->getOpcode() == ISD::SHL)
5495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5496 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
5497 MVT::i32),
5498 N->getOperand(0), N->getOperand(1));
5499
5500 assert((N->getOpcode() == ISD::SRA ||(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5501, __extension__ __PRETTY_FUNCTION__))
5501 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode")(static_cast <bool> ((N->getOpcode() == ISD::SRA || N
->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) && \"unexpected vector shift opcode\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5501, __extension__ __PRETTY_FUNCTION__))
;
5502
5503 // NEON uses the same intrinsics for both left and right shifts. For
5504 // right shifts, the shift amounts are negative, so negate the vector of
5505 // shift amounts.
5506 EVT ShiftVT = N->getOperand(1).getValueType();
5507 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
5508 getZeroVector(ShiftVT, DAG, dl),
5509 N->getOperand(1));
5510 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
5511 Intrinsic::arm_neon_vshifts :
5512 Intrinsic::arm_neon_vshiftu);
5513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
5514 DAG.getConstant(vshiftInt, dl, MVT::i32),
5515 N->getOperand(0), NegatedCount);
5516}
5517
5518static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
5519 const ARMSubtarget *ST) {
5520 EVT VT = N->getValueType(0);
5521 SDLoc dl(N);
5522
5523 // We can get here for a node like i32 = ISD::SHL i32, i64
5524 if (VT != MVT::i64)
5525 return SDValue();
5526
5527 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5528, __extension__ __PRETTY_FUNCTION__))
5528 "Unknown shift to lower!")(static_cast <bool> ((N->getOpcode() == ISD::SRL || N
->getOpcode() == ISD::SRA) && "Unknown shift to lower!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && \"Unknown shift to lower!\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5528, __extension__ __PRETTY_FUNCTION__))
;
5529
5530 // We only lower SRA, SRL of 1 here, all others use generic lowering.
5531 if (!isOneConstant(N->getOperand(1)))
5532 return SDValue();
5533
5534 // If we are in thumb mode, we don't have RRX.
5535 if (ST->isThumb1Only()) return SDValue();
5536
5537 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
5538 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5539 DAG.getConstant(0, dl, MVT::i32));
5540 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
5541 DAG.getConstant(1, dl, MVT::i32));
5542
5543 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
5544 // captures the result into a carry flag.
5545 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
5546 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
5547
5548 // The low part is an ARMISD::RRX operand, which shifts the carry in.
5549 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
5550
5551 // Merge the pieces into a single i64 value.
5552 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5553}
5554
5555static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5556 SDValue TmpOp0, TmpOp1;
5557 bool Invert = false;
5558 bool Swap = false;
5559 unsigned Opc = 0;
5560
5561 SDValue Op0 = Op.getOperand(0);
5562 SDValue Op1 = Op.getOperand(1);
5563 SDValue CC = Op.getOperand(2);
5564 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
5565 EVT VT = Op.getValueType();
5566 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5567 SDLoc dl(Op);
5568
5569 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
5570 (SetCCOpcode == ISD::SETEQ || SetCCOpcode == ISD::SETNE)) {
5571 // Special-case integer 64-bit equality comparisons. They aren't legal,
5572 // but they can be lowered with a few vector instructions.
5573 unsigned CmpElements = CmpVT.getVectorNumElements() * 2;
5574 EVT SplitVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, CmpElements);
5575 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
5576 SDValue CastOp1 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op1);
5577 SDValue Cmp = DAG.getNode(ISD::SETCC, dl, SplitVT, CastOp0, CastOp1,
5578 DAG.getCondCode(ISD::SETEQ));
5579 SDValue Reversed = DAG.getNode(ARMISD::VREV64, dl, SplitVT, Cmp);
5580 SDValue Merged = DAG.getNode(ISD::AND, dl, SplitVT, Cmp, Reversed);
5581 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged);
5582 if (SetCCOpcode == ISD::SETNE)
5583 Merged = DAG.getNOT(dl, Merged, CmpVT);
5584 Merged = DAG.getSExtOrTrunc(Merged, dl, VT);
5585 return Merged;
5586 }
5587
5588 if (CmpVT.getVectorElementType() == MVT::i64)
5589 // 64-bit comparisons are not legal in general.
5590 return SDValue();
5591
5592 if (Op1.getValueType().isFloatingPoint()) {
5593 switch (SetCCOpcode) {
5594 default: llvm_unreachable("Illegal FP comparison")::llvm::llvm_unreachable_internal("Illegal FP comparison", "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5594)
;
5595 case ISD::SETUNE:
5596 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5597 case ISD::SETOEQ:
5598 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5599 case ISD::SETOLT:
5600 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5601 case ISD::SETOGT:
5602 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5603 case ISD::SETOLE:
5604 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5605 case ISD::SETOGE:
5606 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5607 case ISD::SETUGE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5608 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
5609 case ISD::SETUGT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5610 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
5611 case ISD::SETUEQ: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5612 case ISD::SETONE:
5613 // Expand this to (OLT | OGT).
5614 TmpOp0 = Op0;
5615 TmpOp1 = Op1;
5616 Opc = ISD::OR;
5617 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5618 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
5619 break;
5620 case ISD::SETUO:
5621 Invert = true;
5622 LLVM_FALLTHROUGH[[clang::fallthrough]];
5623 case ISD::SETO:
5624 // Expand this to (OLT | OGE).
5625 TmpOp0 = Op0;
5626 TmpOp1 = Op1;
5627 Opc = ISD::OR;
5628 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
5629 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
5630 break;
5631 }
5632 } else {
5633 // Integer comparisons.
5634 switch (SetCCOpcode) {
5635 default: llvm_unreachable("Illegal integer comparison")::llvm::llvm_unreachable_internal("Illegal integer comparison"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5635)
;
5636 case ISD::SETNE: Invert = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5637 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
5638 case ISD::SETLT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5639 case ISD::SETGT: Opc = ARMISD::VCGT; break;
5640 case ISD::SETLE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5641 case ISD::SETGE: Opc = ARMISD::VCGE; break;
5642 case ISD::SETULT: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5643 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
5644 case ISD::SETULE: Swap = true; LLVM_FALLTHROUGH[[clang::fallthrough]];
5645 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
5646 }
5647
5648 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
5649 if (Opc == ARMISD::VCEQ) {
5650 SDValue AndOp;
5651 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5652 AndOp = Op0;
5653 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
5654 AndOp = Op1;
5655
5656 // Ignore bitconvert.
5657 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
5658 AndOp = AndOp.getOperand(0);
5659
5660 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
5661 Opc = ARMISD::VTST;
5662 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
5663 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
5664 Invert = !Invert;
5665 }
5666 }
5667 }
5668
5669 if (Swap)
5670 std::swap(Op0, Op1);
5671
5672 // If one of the operands is a constant vector zero, attempt to fold the
5673 // comparison to a specialized compare-against-zero form.
5674 SDValue SingleOp;
5675 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
5676 SingleOp = Op0;
5677 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
5678 if (Opc == ARMISD::VCGE)
5679 Opc = ARMISD::VCLEZ;
5680 else if (Opc == ARMISD::VCGT)
5681 Opc = ARMISD::VCLTZ;
5682 SingleOp = Op1;
5683 }
5684
5685 SDValue Result;
5686 if (SingleOp.getNode()) {
5687 switch (Opc) {
5688 case ARMISD::VCEQ:
5689 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
5690 case ARMISD::VCGE:
5691 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
5692 case ARMISD::VCLEZ:
5693 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
5694 case ARMISD::VCGT:
5695 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
5696 case ARMISD::VCLTZ:
5697 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
5698 default:
5699 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5700 }
5701 } else {
5702 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
5703 }
5704
5705 Result = DAG.getSExtOrTrunc(Result, dl, VT);
5706
5707 if (Invert)
5708 Result = DAG.getNOT(dl, Result, VT);
5709
5710 return Result;
5711}
5712
5713static SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) {
5714 SDValue LHS = Op.getOperand(0);
5715 SDValue RHS = Op.getOperand(1);
5716 SDValue Carry = Op.getOperand(2);
5717 SDValue Cond = Op.getOperand(3);
5718 SDLoc DL(Op);
5719
5720 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.")(static_cast <bool> (LHS.getSimpleValueType().isInteger
() && "SETCCE is integer only.") ? void (0) : __assert_fail
("LHS.getSimpleValueType().isInteger() && \"SETCCE is integer only.\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5720, __extension__ __PRETTY_FUNCTION__))
;
5721
5722 assert(Carry.getOpcode() != ISD::CARRY_FALSE)(static_cast <bool> (Carry.getOpcode() != ISD::CARRY_FALSE
) ? void (0) : __assert_fail ("Carry.getOpcode() != ISD::CARRY_FALSE"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5722, __extension__ __PRETTY_FUNCTION__))
;
5723 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
5724 SDValue Cmp = DAG.getNode(ARMISD::SUBE, DL, VTs, LHS, RHS, Carry);
5725
5726 SDValue FVal = DAG.getConstant(0, DL, MVT::i32);
5727 SDValue TVal = DAG.getConstant(1, DL, MVT::i32);
5728 SDValue ARMcc = DAG.getConstant(
5729 IntCCToARMCC(cast<CondCodeSDNode>(Cond)->get()), DL, MVT::i32);
5730 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5731 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,
5732 Cmp.getValue(1), SDValue());
5733 return DAG.getNode(ARMISD::CMOV, DL, Op.getValueType(), FVal, TVal, ARMcc,
5734 CCR, Chain.getValue(1));
5735}
5736
5737/// isNEONModifiedImm - Check if the specified splat value corresponds to a
5738/// valid vector constant for a NEON instruction with a "modified immediate"
5739/// operand (e.g., VMOV). If so, return the encoded value.
5740static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
5741 unsigned SplatBitSize, SelectionDAG &DAG,
5742 const SDLoc &dl, EVT &VT, bool is128Bits,
5743 NEONModImmType type) {
5744 unsigned OpCmode, Imm;
5745
5746 // SplatBitSize is set to the smallest size that splats the vector, so a
5747 // zero vector will always have SplatBitSize == 8. However, NEON modified
5748 // immediate instructions others than VMOV do not support the 8-bit encoding
5749 // of a zero vector, and the default encoding of zero is supposed to be the
5750 // 32-bit version.
5751 if (SplatBits == 0)
5752 SplatBitSize = 32;
5753
5754 switch (SplatBitSize) {
5755 case 8:
5756 if (type != VMOVModImm)
5757 return SDValue();
5758 // Any 1-byte value is OK. Op=0, Cmode=1110.
5759 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big")(static_cast <bool> ((SplatBits & ~0xff) == 0 &&
"one byte splat value is too big") ? void (0) : __assert_fail
("(SplatBits & ~0xff) == 0 && \"one byte splat value is too big\""
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5759, __extension__ __PRETTY_FUNCTION__))
;
5760 OpCmode = 0xe;
5761 Imm = SplatBits;
5762 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
5763 break;
5764
5765 case 16:
5766 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
5767 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
5768 if ((SplatBits & ~0xff) == 0) {
5769 // Value = 0x00nn: Op=x, Cmode=100x.
5770 OpCmode = 0x8;
5771 Imm = SplatBits;
5772 break;
5773 }
5774 if ((SplatBits & ~0xff00) == 0) {
5775 // Value = 0xnn00: Op=x, Cmode=101x.
5776 OpCmode = 0xa;
5777 Imm = SplatBits >> 8;
5778 break;
5779 }
5780 return SDValue();
5781
5782 case 32:
5783 // NEON's 32-bit VMOV supports splat values where:
5784 // * only one byte is nonzero, or
5785 // * the least significant byte is 0xff and the second byte is nonzero, or
5786 // * the least significant 2 bytes are 0xff and the third is nonzero.
5787 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
5788 if ((SplatBits & ~0xff) == 0) {
5789 // Value = 0x000000nn: Op=x, Cmode=000x.
5790 OpCmode = 0;
5791 Imm = SplatBits;
5792 break;
5793 }
5794 if ((SplatBits & ~0xff00) == 0) {
5795 // Value = 0x0000nn00: Op=x, Cmode=001x.
5796 OpCmode = 0x2;
5797 Imm = SplatBits >> 8;
5798 break;
5799 }
5800 if ((SplatBits & ~0xff0000) == 0) {
5801 // Value = 0x00nn0000: Op=x, Cmode=010x.
5802 OpCmode = 0x4;
5803 Imm = SplatBits >> 16;
5804 break;
5805 }
5806 if ((SplatBits & ~0xff000000) == 0) {
5807 // Value = 0xnn000000: Op=x, Cmode=011x.
5808 OpCmode = 0x6;
5809 Imm = SplatBits >> 24;
5810 break;
5811 }
5812
5813 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
5814 if (type == OtherModImm) return SDValue();
5815
5816 if ((SplatBits & ~0xffff) == 0 &&
5817 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
5818 // Value = 0x0000nnff: Op=x, Cmode=1100.
5819 OpCmode = 0xc;
5820 Imm = SplatBits >> 8;
5821 break;
5822 }
5823
5824 if ((SplatBits & ~0xffffff) == 0 &&
5825 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
5826 // Value = 0x00nnffff: Op=x, Cmode=1101.
5827 OpCmode = 0xd;
5828 Imm = SplatBits >> 16;
5829 break;
5830 }
5831
5832 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
5833 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
5834 // VMOV.I32. A (very) minor optimization would be to replicate the value
5835 // and fall through here to test for a valid 64-bit splat. But, then the
5836 // caller would also need to check and handle the change in size.
5837 return SDValue();
5838
5839 case 64: {
5840 if (type != VMOVModImm)
5841 return SDValue();
5842 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
5843 uint64_t BitMask = 0xff;
5844 uint64_t Val = 0;
5845 unsigned ImmMask = 1;
5846 Imm = 0;
5847 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
5848 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
5849 Val |= BitMask;
5850 Imm |= ImmMask;
5851 } else if ((SplatBits & BitMask) != 0) {
5852 return SDValue();
5853 }
5854 BitMask <<= 8;
5855 ImmMask <<= 1;
5856 }
5857
5858 if (DAG.getDataLayout().isBigEndian())
5859 // swap higher and lower 32 bit word
5860 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
5861
5862 // Op=1, Cmode=1110.
5863 OpCmode = 0x1e;
5864 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
5865 break;
5866 }
5867
5868 default:
5869 llvm_unreachable("unexpected size for isNEONModifiedImm")::llvm::llvm_unreachable_internal("unexpected size for isNEONModifiedImm"
, "/build/llvm-toolchain-snapshot-7~svn326246/lib/Target/ARM/ARMISelLowering.cpp"
, 5869)
;
5870 }
5871
5872 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
5873 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
5874}
5875
5876SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
5877 const ARMSubtarget *ST) const {
5878 bool IsDouble = Op.getValueType() == MVT::f64;
5879 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
5880 const APFloat &FPVal = CFP->getValueAPF();
5881
5882 // Prevent floating-point constants from using literal loads
5883 // when execute-only is enabled.
5884 if (ST->genExecuteOnly()) {
5885 APInt INTVal = FPVal.bitcastToAPInt();
5886 SDLoc DL(CFP);
5887 if (IsDouble) {
5888 SDValue Lo = DAG.getConstant(INTVal.trunc(32), DL, MVT::i32);
5889 SDValue Hi = DAG.getConstant(INTVal.lshr(32).trunc(32), DL, MVT::i32);
5890 if (!ST->isLittle())
5891 std::swap(Lo, Hi);
5892 return DAG.getNode(ARMISD::VMOVDRR, DL, MVT::f64, Lo, Hi);
5893 } else {
5894 return DAG.getConstant(INTVal, DL, MVT::i32);
5895 }
5896 }
5897
5898 if (!ST->hasVFP3())
5899 return SDValue();
5900
5901 // Use the default (constant pool) lowering for double constants when we have
5902 // an SP-only FPU
5903 if (IsDouble && Subtarget->isFPOnlySP())
5904 return SDValue();
5905
5906 // Try splatting with a VMOV.f32...
5907 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
5908
5909 if (ImmVal != -1) {
5910 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
5911 // We have code in place to select a valid ConstantFP already, no need to
5912 // do any mangling.
5913 return Op;
5914 }
5915
5916 // It's a float and we are trying to use NEON operations where
5917 // possible. Lower it to a splat followed by an extract.
5918 SDLoc DL(Op);
5919 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
5920 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
5921 NewVal);
5922 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
5923 DAG.getConstant(0, DL, MVT::i32));
5924 }
5925
5926 // The rest of our options are NEON only, make sure that's allowed before
5927 // proceeding..
5928 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
5929 return SDValue();