Bug Summary

File:lib/IR/AutoUpgrade.cpp
Warning:line 918, column 32
Division by zero

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name AutoUpgrade.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/lib/IR -I /build/llvm-toolchain-snapshot-7~svn325118/lib/IR -I /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn325118/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn325118/build-llvm/lib/IR -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-14-150435-17243-1 -x c++ /build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp
1//===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the auto-upgrade helper functions.
11// This is where deprecated IR intrinsics and other IR features are updated to
12// current specifications.
13//
14//===----------------------------------------------------------------------===//
15
16#include "llvm/IR/AutoUpgrade.h"
17#include "llvm/ADT/StringSwitch.h"
18#include "llvm/IR/Constants.h"
19#include "llvm/IR/DIBuilder.h"
20#include "llvm/IR/DebugInfo.h"
21#include "llvm/IR/DiagnosticInfo.h"
22#include "llvm/IR/Function.h"
23#include "llvm/IR/IRBuilder.h"
24#include "llvm/IR/Instruction.h"
25#include "llvm/IR/IntrinsicInst.h"
26#include "llvm/IR/LLVMContext.h"
27#include "llvm/IR/Module.h"
28#include "llvm/IR/Verifier.h"
29#include "llvm/Support/ErrorHandling.h"
30#include "llvm/Support/Regex.h"
31#include <cstring>
32using namespace llvm;
33
34static void rename(GlobalValue *GV) { GV->setName(GV->getName() + ".old"); }
35
36// Upgrade the declarations of the SSE4.1 ptest intrinsics whose arguments have
37// changed their type from v4f32 to v2i64.
38static bool UpgradePTESTIntrinsic(Function* F, Intrinsic::ID IID,
39 Function *&NewFn) {
40 // Check whether this is an old version of the function, which received
41 // v4f32 arguments.
42 Type *Arg0Type = F->getFunctionType()->getParamType(0);
43 if (Arg0Type != VectorType::get(Type::getFloatTy(F->getContext()), 4))
44 return false;
45
46 // Yes, it's old, replace it with new version.
47 rename(F);
48 NewFn = Intrinsic::getDeclaration(F->getParent(), IID);
49 return true;
50}
51
52// Upgrade the declarations of intrinsic functions whose 8-bit immediate mask
53// arguments have changed their type from i32 to i8.
54static bool UpgradeX86IntrinsicsWith8BitMask(Function *F, Intrinsic::ID IID,
55 Function *&NewFn) {
56 // Check that the last argument is an i32.
57 Type *LastArgType = F->getFunctionType()->getParamType(
58 F->getFunctionType()->getNumParams() - 1);
59 if (!LastArgType->isIntegerTy(32))
60 return false;
61
62 // Move this function aside and map down.
63 rename(F);
64 NewFn = Intrinsic::getDeclaration(F->getParent(), IID);
65 return true;
66}
67
68// Upgrade the declaration of fp compare intrinsics that change return type
69// from scalar to vXi1 mask.
70static bool UpgradeX86MaskedFPCompare(Function *F, Intrinsic::ID IID,
71 Function *&NewFn) {
72 // Check if the return type is a vector.
73 if (F->getReturnType()->isVectorTy())
74 return false;
75
76 rename(F);
77 NewFn = Intrinsic::getDeclaration(F->getParent(), IID);
78 return true;
79}
80
81static bool ShouldUpgradeX86Intrinsic(Function *F, StringRef Name) {
82 // All of the intrinsics matches below should be marked with which llvm
83 // version started autoupgrading them. At some point in the future we would
84 // like to use this information to remove upgrade code for some older
85 // intrinsics. It is currently undecided how we will determine that future
86 // point.
87 if (Name=="ssse3.pabs.b.128" || // Added in 6.0
88 Name=="ssse3.pabs.w.128" || // Added in 6.0
89 Name=="ssse3.pabs.d.128" || // Added in 6.0
90 Name.startswith("avx512.mask.shuf.i") || // Added in 6.0
91 Name.startswith("avx512.mask.shuf.f") || // Added in 6.0
92 Name.startswith("avx512.kunpck") || //added in 6.0
93 Name.startswith("avx2.pabs.") || // Added in 6.0
94 Name.startswith("avx512.mask.pabs.") || // Added in 6.0
95 Name.startswith("avx512.broadcastm") || // Added in 6.0
96 Name.startswith("avx512.mask.pbroadcast") || // Added in 6.0
97 Name.startswith("sse2.pcmpeq.") || // Added in 3.1
98 Name.startswith("sse2.pcmpgt.") || // Added in 3.1
99 Name.startswith("avx2.pcmpeq.") || // Added in 3.1
100 Name.startswith("avx2.pcmpgt.") || // Added in 3.1
101 Name.startswith("avx512.mask.pcmpeq.") || // Added in 3.9
102 Name.startswith("avx512.mask.pcmpgt.") || // Added in 3.9
103 Name.startswith("avx.vperm2f128.") || // Added in 6.0
104 Name == "avx2.vperm2i128" || // Added in 6.0
105 Name == "sse.add.ss" || // Added in 4.0
106 Name == "sse2.add.sd" || // Added in 4.0
107 Name == "sse.sub.ss" || // Added in 4.0
108 Name == "sse2.sub.sd" || // Added in 4.0
109 Name == "sse.mul.ss" || // Added in 4.0
110 Name == "sse2.mul.sd" || // Added in 4.0
111 Name == "sse.div.ss" || // Added in 4.0
112 Name == "sse2.div.sd" || // Added in 4.0
113 Name == "sse41.pmaxsb" || // Added in 3.9
114 Name == "sse2.pmaxs.w" || // Added in 3.9
115 Name == "sse41.pmaxsd" || // Added in 3.9
116 Name == "sse2.pmaxu.b" || // Added in 3.9
117 Name == "sse41.pmaxuw" || // Added in 3.9
118 Name == "sse41.pmaxud" || // Added in 3.9
119 Name == "sse41.pminsb" || // Added in 3.9
120 Name == "sse2.pmins.w" || // Added in 3.9
121 Name == "sse41.pminsd" || // Added in 3.9
122 Name == "sse2.pminu.b" || // Added in 3.9
123 Name == "sse41.pminuw" || // Added in 3.9
124 Name == "sse41.pminud" || // Added in 3.9
125 Name == "avx512.kand.w" || // Added in 7.0
126 Name == "avx512.kandn.w" || // Added in 7.0
127 Name == "avx512.knot.w" || // Added in 7.0
128 Name == "avx512.kor.w" || // Added in 7.0
129 Name == "avx512.kxor.w" || // Added in 7.0
130 Name == "avx512.kxnor.w" || // Added in 7.0
131 Name == "avx512.kortestc.w" || // Added in 7.0
132 Name == "avx512.kortestz.w" || // Added in 7.0
133 Name.startswith("avx512.mask.pshuf.b.") || // Added in 4.0
134 Name.startswith("avx2.pmax") || // Added in 3.9
135 Name.startswith("avx2.pmin") || // Added in 3.9
136 Name.startswith("avx512.mask.pmax") || // Added in 4.0
137 Name.startswith("avx512.mask.pmin") || // Added in 4.0
138 Name.startswith("avx2.vbroadcast") || // Added in 3.8
139 Name.startswith("avx2.pbroadcast") || // Added in 3.8
140 Name.startswith("avx.vpermil.") || // Added in 3.1
141 Name.startswith("sse2.pshuf") || // Added in 3.9
142 Name.startswith("avx512.pbroadcast") || // Added in 3.9
143 Name.startswith("avx512.mask.broadcast.s") || // Added in 3.9
144 Name.startswith("avx512.mask.movddup") || // Added in 3.9
145 Name.startswith("avx512.mask.movshdup") || // Added in 3.9
146 Name.startswith("avx512.mask.movsldup") || // Added in 3.9
147 Name.startswith("avx512.mask.pshuf.d.") || // Added in 3.9
148 Name.startswith("avx512.mask.pshufl.w.") || // Added in 3.9
149 Name.startswith("avx512.mask.pshufh.w.") || // Added in 3.9
150 Name.startswith("avx512.mask.shuf.p") || // Added in 4.0
151 Name.startswith("avx512.mask.vpermil.p") || // Added in 3.9
152 Name.startswith("avx512.mask.perm.df.") || // Added in 3.9
153 Name.startswith("avx512.mask.perm.di.") || // Added in 3.9
154 Name.startswith("avx512.mask.punpckl") || // Added in 3.9
155 Name.startswith("avx512.mask.punpckh") || // Added in 3.9
156 Name.startswith("avx512.mask.unpckl.") || // Added in 3.9
157 Name.startswith("avx512.mask.unpckh.") || // Added in 3.9
158 Name.startswith("avx512.mask.pand.") || // Added in 3.9
159 Name.startswith("avx512.mask.pandn.") || // Added in 3.9
160 Name.startswith("avx512.mask.por.") || // Added in 3.9
161 Name.startswith("avx512.mask.pxor.") || // Added in 3.9
162 Name.startswith("avx512.mask.and.") || // Added in 3.9
163 Name.startswith("avx512.mask.andn.") || // Added in 3.9
164 Name.startswith("avx512.mask.or.") || // Added in 3.9
165 Name.startswith("avx512.mask.xor.") || // Added in 3.9
166 Name.startswith("avx512.mask.padd.") || // Added in 4.0
167 Name.startswith("avx512.mask.psub.") || // Added in 4.0
168 Name.startswith("avx512.mask.pmull.") || // Added in 4.0
169 Name.startswith("avx512.mask.cvtdq2pd.") || // Added in 4.0
170 Name.startswith("avx512.mask.cvtudq2pd.") || // Added in 4.0
171 Name.startswith("avx512.mask.pmul.dq.") || // Added in 4.0
172 Name.startswith("avx512.mask.pmulu.dq.") || // Added in 4.0
173 Name.startswith("avx512.mask.packsswb.") || // Added in 5.0
174 Name.startswith("avx512.mask.packssdw.") || // Added in 5.0
175 Name.startswith("avx512.mask.packuswb.") || // Added in 5.0
176 Name.startswith("avx512.mask.packusdw.") || // Added in 5.0
177 Name.startswith("avx512.mask.cmp.b") || // Added in 5.0
178 Name.startswith("avx512.mask.cmp.d") || // Added in 5.0
179 Name.startswith("avx512.mask.cmp.q") || // Added in 5.0
180 Name.startswith("avx512.mask.cmp.w") || // Added in 5.0
181 Name.startswith("avx512.mask.ucmp.") || // Added in 5.0
182 Name.startswith("avx512.cvtb2mask.") || // Added in 7.0
183 Name.startswith("avx512.cvtw2mask.") || // Added in 7.0
184 Name.startswith("avx512.cvtd2mask.") || // Added in 7.0
185 Name.startswith("avx512.cvtq2mask.") || // Added in 7.0
186 Name == "avx512.mask.add.pd.128" || // Added in 4.0
187 Name == "avx512.mask.add.pd.256" || // Added in 4.0
188 Name == "avx512.mask.add.ps.128" || // Added in 4.0
189 Name == "avx512.mask.add.ps.256" || // Added in 4.0
190 Name == "avx512.mask.div.pd.128" || // Added in 4.0
191 Name == "avx512.mask.div.pd.256" || // Added in 4.0
192 Name == "avx512.mask.div.ps.128" || // Added in 4.0
193 Name == "avx512.mask.div.ps.256" || // Added in 4.0
194 Name == "avx512.mask.mul.pd.128" || // Added in 4.0
195 Name == "avx512.mask.mul.pd.256" || // Added in 4.0
196 Name == "avx512.mask.mul.ps.128" || // Added in 4.0
197 Name == "avx512.mask.mul.ps.256" || // Added in 4.0
198 Name == "avx512.mask.sub.pd.128" || // Added in 4.0
199 Name == "avx512.mask.sub.pd.256" || // Added in 4.0
200 Name == "avx512.mask.sub.ps.128" || // Added in 4.0
201 Name == "avx512.mask.sub.ps.256" || // Added in 4.0
202 Name == "avx512.mask.max.pd.128" || // Added in 5.0
203 Name == "avx512.mask.max.pd.256" || // Added in 5.0
204 Name == "avx512.mask.max.ps.128" || // Added in 5.0
205 Name == "avx512.mask.max.ps.256" || // Added in 5.0
206 Name == "avx512.mask.min.pd.128" || // Added in 5.0
207 Name == "avx512.mask.min.pd.256" || // Added in 5.0
208 Name == "avx512.mask.min.ps.128" || // Added in 5.0
209 Name == "avx512.mask.min.ps.256" || // Added in 5.0
210 Name.startswith("avx512.mask.vpermilvar.") || // Added in 4.0
211 Name.startswith("avx512.mask.psll.d") || // Added in 4.0
212 Name.startswith("avx512.mask.psll.q") || // Added in 4.0
213 Name.startswith("avx512.mask.psll.w") || // Added in 4.0
214 Name.startswith("avx512.mask.psra.d") || // Added in 4.0
215 Name.startswith("avx512.mask.psra.q") || // Added in 4.0
216 Name.startswith("avx512.mask.psra.w") || // Added in 4.0
217 Name.startswith("avx512.mask.psrl.d") || // Added in 4.0
218 Name.startswith("avx512.mask.psrl.q") || // Added in 4.0
219 Name.startswith("avx512.mask.psrl.w") || // Added in 4.0
220 Name.startswith("avx512.mask.pslli") || // Added in 4.0
221 Name.startswith("avx512.mask.psrai") || // Added in 4.0
222 Name.startswith("avx512.mask.psrli") || // Added in 4.0
223 Name.startswith("avx512.mask.psllv") || // Added in 4.0
224 Name.startswith("avx512.mask.psrav") || // Added in 4.0
225 Name.startswith("avx512.mask.psrlv") || // Added in 4.0
226 Name.startswith("sse41.pmovsx") || // Added in 3.8
227 Name.startswith("sse41.pmovzx") || // Added in 3.9
228 Name.startswith("avx2.pmovsx") || // Added in 3.9
229 Name.startswith("avx2.pmovzx") || // Added in 3.9
230 Name.startswith("avx512.mask.pmovsx") || // Added in 4.0
231 Name.startswith("avx512.mask.pmovzx") || // Added in 4.0
232 Name.startswith("avx512.mask.lzcnt.") || // Added in 5.0
233 Name == "sse2.cvtdq2pd" || // Added in 3.9
234 Name == "sse2.cvtps2pd" || // Added in 3.9
235 Name == "avx.cvtdq2.pd.256" || // Added in 3.9
236 Name == "avx.cvt.ps2.pd.256" || // Added in 3.9
237 Name.startswith("avx.vinsertf128.") || // Added in 3.7
238 Name == "avx2.vinserti128" || // Added in 3.7
239 Name.startswith("avx512.mask.insert") || // Added in 4.0
240 Name.startswith("avx.vextractf128.") || // Added in 3.7
241 Name == "avx2.vextracti128" || // Added in 3.7
242 Name.startswith("avx512.mask.vextract") || // Added in 4.0
243 Name.startswith("sse4a.movnt.") || // Added in 3.9
244 Name.startswith("avx.movnt.") || // Added in 3.2
245 Name.startswith("avx512.storent.") || // Added in 3.9
246 Name == "sse41.movntdqa" || // Added in 5.0
247 Name == "avx2.movntdqa" || // Added in 5.0
248 Name == "avx512.movntdqa" || // Added in 5.0
249 Name == "sse2.storel.dq" || // Added in 3.9
250 Name.startswith("sse.storeu.") || // Added in 3.9
251 Name.startswith("sse2.storeu.") || // Added in 3.9
252 Name.startswith("avx.storeu.") || // Added in 3.9
253 Name.startswith("avx512.mask.storeu.") || // Added in 3.9
254 Name.startswith("avx512.mask.store.p") || // Added in 3.9
255 Name.startswith("avx512.mask.store.b.") || // Added in 3.9
256 Name.startswith("avx512.mask.store.w.") || // Added in 3.9
257 Name.startswith("avx512.mask.store.d.") || // Added in 3.9
258 Name.startswith("avx512.mask.store.q.") || // Added in 3.9
259 Name.startswith("avx512.mask.loadu.") || // Added in 3.9
260 Name.startswith("avx512.mask.load.") || // Added in 3.9
261 Name == "sse42.crc32.64.8" || // Added in 3.4
262 Name.startswith("avx.vbroadcast.s") || // Added in 3.5
263 Name.startswith("avx512.mask.palignr.") || // Added in 3.9
264 Name.startswith("avx512.mask.valign.") || // Added in 4.0
265 Name.startswith("sse2.psll.dq") || // Added in 3.7
266 Name.startswith("sse2.psrl.dq") || // Added in 3.7
267 Name.startswith("avx2.psll.dq") || // Added in 3.7
268 Name.startswith("avx2.psrl.dq") || // Added in 3.7
269 Name.startswith("avx512.psll.dq") || // Added in 3.9
270 Name.startswith("avx512.psrl.dq") || // Added in 3.9
271 Name == "sse41.pblendw" || // Added in 3.7
272 Name.startswith("sse41.blendp") || // Added in 3.7
273 Name.startswith("avx.blend.p") || // Added in 3.7
274 Name == "avx2.pblendw" || // Added in 3.7
275 Name.startswith("avx2.pblendd.") || // Added in 3.7
276 Name.startswith("avx.vbroadcastf128") || // Added in 4.0
277 Name == "avx2.vbroadcasti128" || // Added in 3.7
278 Name.startswith("avx512.mask.broadcastf") || // Added in 6.0
279 Name.startswith("avx512.mask.broadcasti") || // Added in 6.0
280 Name == "xop.vpcmov" || // Added in 3.8
281 Name == "xop.vpcmov.256" || // Added in 5.0
282 Name.startswith("avx512.mask.move.s") || // Added in 4.0
283 Name.startswith("avx512.cvtmask2") || // Added in 5.0
284 (Name.startswith("xop.vpcom") && // Added in 3.2
285 F->arg_size() == 2) ||
286 Name.startswith("avx512.ptestm") || //Added in 6.0
287 Name.startswith("avx512.ptestnm") || //Added in 6.0
288 Name.startswith("sse2.pavg") || // Added in 6.0
289 Name.startswith("avx2.pavg") || // Added in 6.0
290 Name.startswith("avx512.mask.pavg")) // Added in 6.0
291 return true;
292
293 return false;
294}
295
296static bool UpgradeX86IntrinsicFunction(Function *F, StringRef Name,
297 Function *&NewFn) {
298 // Only handle intrinsics that start with "x86.".
299 if (!Name.startswith("x86."))
300 return false;
301 // Remove "x86." prefix.
302 Name = Name.substr(4);
303
304 if (ShouldUpgradeX86Intrinsic(F, Name)) {
305 NewFn = nullptr;
306 return true;
307 }
308
309 // SSE4.1 ptest functions may have an old signature.
310 if (Name.startswith("sse41.ptest")) { // Added in 3.2
311 if (Name.substr(11) == "c")
312 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestc, NewFn);
313 if (Name.substr(11) == "z")
314 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestz, NewFn);
315 if (Name.substr(11) == "nzc")
316 return UpgradePTESTIntrinsic(F, Intrinsic::x86_sse41_ptestnzc, NewFn);
317 }
318 // Several blend and other instructions with masks used the wrong number of
319 // bits.
320 if (Name == "sse41.insertps") // Added in 3.6
321 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_insertps,
322 NewFn);
323 if (Name == "sse41.dppd") // Added in 3.6
324 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dppd,
325 NewFn);
326 if (Name == "sse41.dpps") // Added in 3.6
327 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_dpps,
328 NewFn);
329 if (Name == "sse41.mpsadbw") // Added in 3.6
330 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_sse41_mpsadbw,
331 NewFn);
332 if (Name == "avx.dp.ps.256") // Added in 3.6
333 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx_dp_ps_256,
334 NewFn);
335 if (Name == "avx2.mpsadbw") // Added in 3.6
336 return UpgradeX86IntrinsicsWith8BitMask(F, Intrinsic::x86_avx2_mpsadbw,
337 NewFn);
338 if (Name == "avx512.mask.cmp.pd.128") // Added in 7.0
339 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_128,
340 NewFn);
341 if (Name == "avx512.mask.cmp.pd.256") // Added in 7.0
342 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_256,
343 NewFn);
344 if (Name == "avx512.mask.cmp.pd.512") // Added in 7.0
345 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_pd_512,
346 NewFn);
347 if (Name == "avx512.mask.cmp.ps.128") // Added in 7.0
348 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_128,
349 NewFn);
350 if (Name == "avx512.mask.cmp.ps.256") // Added in 7.0
351 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_256,
352 NewFn);
353 if (Name == "avx512.mask.cmp.ps.512") // Added in 7.0
354 return UpgradeX86MaskedFPCompare(F, Intrinsic::x86_avx512_mask_cmp_ps_512,
355 NewFn);
356
357 // frcz.ss/sd may need to have an argument dropped. Added in 3.2
358 if (Name.startswith("xop.vfrcz.ss") && F->arg_size() == 2) {
359 rename(F);
360 NewFn = Intrinsic::getDeclaration(F->getParent(),
361 Intrinsic::x86_xop_vfrcz_ss);
362 return true;
363 }
364 if (Name.startswith("xop.vfrcz.sd") && F->arg_size() == 2) {
365 rename(F);
366 NewFn = Intrinsic::getDeclaration(F->getParent(),
367 Intrinsic::x86_xop_vfrcz_sd);
368 return true;
369 }
370 // Upgrade any XOP PERMIL2 index operand still using a float/double vector.
371 if (Name.startswith("xop.vpermil2")) { // Added in 3.9
372 auto Idx = F->getFunctionType()->getParamType(2);
373 if (Idx->isFPOrFPVectorTy()) {
374 rename(F);
375 unsigned IdxSize = Idx->getPrimitiveSizeInBits();
376 unsigned EltSize = Idx->getScalarSizeInBits();
377 Intrinsic::ID Permil2ID;
378 if (EltSize == 64 && IdxSize == 128)
379 Permil2ID = Intrinsic::x86_xop_vpermil2pd;
380 else if (EltSize == 32 && IdxSize == 128)
381 Permil2ID = Intrinsic::x86_xop_vpermil2ps;
382 else if (EltSize == 64 && IdxSize == 256)
383 Permil2ID = Intrinsic::x86_xop_vpermil2pd_256;
384 else
385 Permil2ID = Intrinsic::x86_xop_vpermil2ps_256;
386 NewFn = Intrinsic::getDeclaration(F->getParent(), Permil2ID);
387 return true;
388 }
389 }
390
391 return false;
392}
393
394static bool UpgradeIntrinsicFunction1(Function *F, Function *&NewFn) {
395 assert(F && "Illegal to upgrade a non-existent Function.")(static_cast <bool> (F && "Illegal to upgrade a non-existent Function."
) ? void (0) : __assert_fail ("F && \"Illegal to upgrade a non-existent Function.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 395, __extension__ __PRETTY_FUNCTION__))
;
396
397 // Quickly eliminate it, if it's not a candidate.
398 StringRef Name = F->getName();
399 if (Name.size() <= 8 || !Name.startswith("llvm."))
400 return false;
401 Name = Name.substr(5); // Strip off "llvm."
402
403 switch (Name[0]) {
404 default: break;
405 case 'a': {
406 if (Name.startswith("arm.rbit") || Name.startswith("aarch64.rbit")) {
407 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::bitreverse,
408 F->arg_begin()->getType());
409 return true;
410 }
411 if (Name.startswith("arm.neon.vclz")) {
412 Type* args[2] = {
413 F->arg_begin()->getType(),
414 Type::getInt1Ty(F->getContext())
415 };
416 // Can't use Intrinsic::getDeclaration here as it adds a ".i1" to
417 // the end of the name. Change name from llvm.arm.neon.vclz.* to
418 // llvm.ctlz.*
419 FunctionType* fType = FunctionType::get(F->getReturnType(), args, false);
420 NewFn = Function::Create(fType, F->getLinkage(),
421 "llvm.ctlz." + Name.substr(14), F->getParent());
422 return true;
423 }
424 if (Name.startswith("arm.neon.vcnt")) {
425 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop,
426 F->arg_begin()->getType());
427 return true;
428 }
429 Regex vldRegex("^arm\\.neon\\.vld([1234]|[234]lane)\\.v[a-z0-9]*$");
430 if (vldRegex.match(Name)) {
431 auto fArgs = F->getFunctionType()->params();
432 SmallVector<Type *, 4> Tys(fArgs.begin(), fArgs.end());
433 // Can't use Intrinsic::getDeclaration here as the return types might
434 // then only be structurally equal.
435 FunctionType* fType = FunctionType::get(F->getReturnType(), Tys, false);
436 NewFn = Function::Create(fType, F->getLinkage(),
437 "llvm." + Name + ".p0i8", F->getParent());
438 return true;
439 }
440 Regex vstRegex("^arm\\.neon\\.vst([1234]|[234]lane)\\.v[a-z0-9]*$");
441 if (vstRegex.match(Name)) {
442 static const Intrinsic::ID StoreInts[] = {Intrinsic::arm_neon_vst1,
443 Intrinsic::arm_neon_vst2,
444 Intrinsic::arm_neon_vst3,
445 Intrinsic::arm_neon_vst4};
446
447 static const Intrinsic::ID StoreLaneInts[] = {
448 Intrinsic::arm_neon_vst2lane, Intrinsic::arm_neon_vst3lane,
449 Intrinsic::arm_neon_vst4lane
450 };
451
452 auto fArgs = F->getFunctionType()->params();
453 Type *Tys[] = {fArgs[0], fArgs[1]};
454 if (Name.find("lane") == StringRef::npos)
455 NewFn = Intrinsic::getDeclaration(F->getParent(),
456 StoreInts[fArgs.size() - 3], Tys);
457 else
458 NewFn = Intrinsic::getDeclaration(F->getParent(),
459 StoreLaneInts[fArgs.size() - 5], Tys);
460 return true;
461 }
462 if (Name == "aarch64.thread.pointer" || Name == "arm.thread.pointer") {
463 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::thread_pointer);
464 return true;
465 }
466 break;
467 }
468
469 case 'c': {
470 if (Name.startswith("ctlz.") && F->arg_size() == 1) {
471 rename(F);
472 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz,
473 F->arg_begin()->getType());
474 return true;
475 }
476 if (Name.startswith("cttz.") && F->arg_size() == 1) {
477 rename(F);
478 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::cttz,
479 F->arg_begin()->getType());
480 return true;
481 }
482 break;
483 }
484 case 'd': {
485 if (Name == "dbg.value" && F->arg_size() == 4) {
486 rename(F);
487 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::dbg_value);
488 return true;
489 }
490 break;
491 }
492 case 'i':
493 case 'l': {
494 bool IsLifetimeStart = Name.startswith("lifetime.start");
495 if (IsLifetimeStart || Name.startswith("invariant.start")) {
496 Intrinsic::ID ID = IsLifetimeStart ?
497 Intrinsic::lifetime_start : Intrinsic::invariant_start;
498 auto Args = F->getFunctionType()->params();
499 Type* ObjectPtr[1] = {Args[1]};
500 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) {
501 rename(F);
502 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr);
503 return true;
504 }
505 }
506
507 bool IsLifetimeEnd = Name.startswith("lifetime.end");
508 if (IsLifetimeEnd || Name.startswith("invariant.end")) {
509 Intrinsic::ID ID = IsLifetimeEnd ?
510 Intrinsic::lifetime_end : Intrinsic::invariant_end;
511
512 auto Args = F->getFunctionType()->params();
513 Type* ObjectPtr[1] = {Args[IsLifetimeEnd ? 1 : 2]};
514 if (F->getName() != Intrinsic::getName(ID, ObjectPtr)) {
515 rename(F);
516 NewFn = Intrinsic::getDeclaration(F->getParent(), ID, ObjectPtr);
517 return true;
518 }
519 }
520 break;
521 }
522 case 'm': {
523 if (Name.startswith("masked.load.")) {
524 Type *Tys[] = { F->getReturnType(), F->arg_begin()->getType() };
525 if (F->getName() != Intrinsic::getName(Intrinsic::masked_load, Tys)) {
526 rename(F);
527 NewFn = Intrinsic::getDeclaration(F->getParent(),
528 Intrinsic::masked_load,
529 Tys);
530 return true;
531 }
532 }
533 if (Name.startswith("masked.store.")) {
534 auto Args = F->getFunctionType()->params();
535 Type *Tys[] = { Args[0], Args[1] };
536 if (F->getName() != Intrinsic::getName(Intrinsic::masked_store, Tys)) {
537 rename(F);
538 NewFn = Intrinsic::getDeclaration(F->getParent(),
539 Intrinsic::masked_store,
540 Tys);
541 return true;
542 }
543 }
544 // Renaming gather/scatter intrinsics with no address space overloading
545 // to the new overload which includes an address space
546 if (Name.startswith("masked.gather.")) {
547 Type *Tys[] = {F->getReturnType(), F->arg_begin()->getType()};
548 if (F->getName() != Intrinsic::getName(Intrinsic::masked_gather, Tys)) {
549 rename(F);
550 NewFn = Intrinsic::getDeclaration(F->getParent(),
551 Intrinsic::masked_gather, Tys);
552 return true;
553 }
554 }
555 if (Name.startswith("masked.scatter.")) {
556 auto Args = F->getFunctionType()->params();
557 Type *Tys[] = {Args[0], Args[1]};
558 if (F->getName() != Intrinsic::getName(Intrinsic::masked_scatter, Tys)) {
559 rename(F);
560 NewFn = Intrinsic::getDeclaration(F->getParent(),
561 Intrinsic::masked_scatter, Tys);
562 return true;
563 }
564 }
565 // Updating the memory intrinsics (memcpy/memmove/memset) that have an
566 // alignment parameter to embedding the alignment as an attribute of
567 // the pointer args.
568 if (Name.startswith("memcpy.") && F->arg_size() == 5) {
569 rename(F);
570 // Get the types of dest, src, and len
571 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3);
572 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memcpy,
573 ParamTypes);
574 return true;
575 }
576 if (Name.startswith("memmove.") && F->arg_size() == 5) {
577 rename(F);
578 // Get the types of dest, src, and len
579 ArrayRef<Type *> ParamTypes = F->getFunctionType()->params().slice(0, 3);
580 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memmove,
581 ParamTypes);
582 return true;
583 }
584 if (Name.startswith("memset.") && F->arg_size() == 5) {
585 rename(F);
586 // Get the types of dest, and len
587 const auto *FT = F->getFunctionType();
588 Type *ParamTypes[2] = {
589 FT->getParamType(0), // Dest
590 FT->getParamType(2) // len
591 };
592 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::memset,
593 ParamTypes);
594 return true;
595 }
596 break;
597 }
598 case 'n': {
599 if (Name.startswith("nvvm.")) {
600 Name = Name.substr(5);
601
602 // The following nvvm intrinsics correspond exactly to an LLVM intrinsic.
603 Intrinsic::ID IID = StringSwitch<Intrinsic::ID>(Name)
604 .Cases("brev32", "brev64", Intrinsic::bitreverse)
605 .Case("clz.i", Intrinsic::ctlz)
606 .Case("popc.i", Intrinsic::ctpop)
607 .Default(Intrinsic::not_intrinsic);
608 if (IID != Intrinsic::not_intrinsic && F->arg_size() == 1) {
609 NewFn = Intrinsic::getDeclaration(F->getParent(), IID,
610 {F->getReturnType()});
611 return true;
612 }
613
614 // The following nvvm intrinsics correspond exactly to an LLVM idiom, but
615 // not to an intrinsic alone. We expand them in UpgradeIntrinsicCall.
616 //
617 // TODO: We could add lohi.i2d.
618 bool Expand = StringSwitch<bool>(Name)
619 .Cases("abs.i", "abs.ll", true)
620 .Cases("clz.ll", "popc.ll", "h2f", true)
621 .Cases("max.i", "max.ll", "max.ui", "max.ull", true)
622 .Cases("min.i", "min.ll", "min.ui", "min.ull", true)
623 .Default(false);
624 if (Expand) {
625 NewFn = nullptr;
626 return true;
627 }
628 }
629 break;
630 }
631 case 'o':
632 // We only need to change the name to match the mangling including the
633 // address space.
634 if (Name.startswith("objectsize.")) {
635 Type *Tys[2] = { F->getReturnType(), F->arg_begin()->getType() };
636 if (F->arg_size() == 2 ||
637 F->getName() != Intrinsic::getName(Intrinsic::objectsize, Tys)) {
638 rename(F);
639 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::objectsize,
640 Tys);
641 return true;
642 }
643 }
644 break;
645
646 case 's':
647 if (Name == "stackprotectorcheck") {
648 NewFn = nullptr;
649 return true;
650 }
651 break;
652
653 case 'x':
654 if (UpgradeX86IntrinsicFunction(F, Name, NewFn))
655 return true;
656 }
657 // Remangle our intrinsic since we upgrade the mangling
658 auto Result = llvm::Intrinsic::remangleIntrinsicFunction(F);
659 if (Result != None) {
660 NewFn = Result.getValue();
661 return true;
662 }
663
664 // This may not belong here. This function is effectively being overloaded
665 // to both detect an intrinsic which needs upgrading, and to provide the
666 // upgraded form of the intrinsic. We should perhaps have two separate
667 // functions for this.
668 return false;
669}
670
671bool llvm::UpgradeIntrinsicFunction(Function *F, Function *&NewFn) {
672 NewFn = nullptr;
673 bool Upgraded = UpgradeIntrinsicFunction1(F, NewFn);
674 assert(F != NewFn && "Intrinsic function upgraded to the same function")(static_cast <bool> (F != NewFn && "Intrinsic function upgraded to the same function"
) ? void (0) : __assert_fail ("F != NewFn && \"Intrinsic function upgraded to the same function\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 674, __extension__ __PRETTY_FUNCTION__))
;
675
676 // Upgrade intrinsic attributes. This does not change the function.
677 if (NewFn)
678 F = NewFn;
679 if (Intrinsic::ID id = F->getIntrinsicID())
680 F->setAttributes(Intrinsic::getAttributes(F->getContext(), id));
681 return Upgraded;
682}
683
684bool llvm::UpgradeGlobalVariable(GlobalVariable *GV) {
685 // Nothing to do yet.
686 return false;
687}
688
689// Handles upgrading SSE2/AVX2/AVX512BW PSLLDQ intrinsics by converting them
690// to byte shuffles.
691static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder,
692 Value *Op, unsigned Shift) {
693 Type *ResultTy = Op->getType();
694 unsigned NumElts = ResultTy->getVectorNumElements() * 8;
695
696 // Bitcast from a 64-bit element type to a byte element type.
697 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts);
698 Op = Builder.CreateBitCast(Op, VecTy, "cast");
699
700 // We'll be shuffling in zeroes.
701 Value *Res = Constant::getNullValue(VecTy);
702
703 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
704 // we'll just return the zero vector.
705 if (Shift < 16) {
706 uint32_t Idxs[64];
707 // 256/512-bit version is split into 2/4 16-byte lanes.
708 for (unsigned l = 0; l != NumElts; l += 16)
709 for (unsigned i = 0; i != 16; ++i) {
710 unsigned Idx = NumElts + i - Shift;
711 if (Idx < NumElts)
712 Idx -= NumElts - 16; // end of lane, switch operand.
713 Idxs[l + i] = Idx + l;
714 }
715
716 Res = Builder.CreateShuffleVector(Res, Op, makeArrayRef(Idxs, NumElts));
717 }
718
719 // Bitcast back to a 64-bit element type.
720 return Builder.CreateBitCast(Res, ResultTy, "cast");
721}
722
723// Handles upgrading SSE2/AVX2/AVX512BW PSRLDQ intrinsics by converting them
724// to byte shuffles.
725static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op,
726 unsigned Shift) {
727 Type *ResultTy = Op->getType();
728 unsigned NumElts = ResultTy->getVectorNumElements() * 8;
729
730 // Bitcast from a 64-bit element type to a byte element type.
731 Type *VecTy = VectorType::get(Builder.getInt8Ty(), NumElts);
732 Op = Builder.CreateBitCast(Op, VecTy, "cast");
733
734 // We'll be shuffling in zeroes.
735 Value *Res = Constant::getNullValue(VecTy);
736
737 // If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
738 // we'll just return the zero vector.
739 if (Shift < 16) {
740 uint32_t Idxs[64];
741 // 256/512-bit version is split into 2/4 16-byte lanes.
742 for (unsigned l = 0; l != NumElts; l += 16)
743 for (unsigned i = 0; i != 16; ++i) {
744 unsigned Idx = i + Shift;
745 if (Idx >= 16)
746 Idx += NumElts - 16; // end of lane, switch operand.
747 Idxs[l + i] = Idx + l;
748 }
749
750 Res = Builder.CreateShuffleVector(Op, Res, makeArrayRef(Idxs, NumElts));
751 }
752
753 // Bitcast back to a 64-bit element type.
754 return Builder.CreateBitCast(Res, ResultTy, "cast");
755}
756
757static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask,
758 unsigned NumElts) {
759 llvm::VectorType *MaskTy = llvm::VectorType::get(Builder.getInt1Ty(),
760 cast<IntegerType>(Mask->getType())->getBitWidth());
761 Mask = Builder.CreateBitCast(Mask, MaskTy);
762
763 // If we have less than 8 elements, then the starting mask was an i8 and
764 // we need to extract down to the right number of elements.
765 if (NumElts < 8) {
766 uint32_t Indices[4];
767 for (unsigned i = 0; i != NumElts; ++i)
768 Indices[i] = i;
769 Mask = Builder.CreateShuffleVector(Mask, Mask,
770 makeArrayRef(Indices, NumElts),
771 "extract");
772 }
773
774 return Mask;
775}
776
777static Value *EmitX86Select(IRBuilder<> &Builder, Value *Mask,
778 Value *Op0, Value *Op1) {
779 // If the mask is all ones just emit the align operation.
780 if (const auto *C = dyn_cast<Constant>(Mask))
781 if (C->isAllOnesValue())
782 return Op0;
783
784 Mask = getX86MaskVec(Builder, Mask, Op0->getType()->getVectorNumElements());
785 return Builder.CreateSelect(Mask, Op0, Op1);
786}
787
788// Handle autoupgrade for masked PALIGNR and VALIGND/Q intrinsics.
789// PALIGNR handles large immediates by shifting while VALIGN masks the immediate
790// so we need to handle both cases. VALIGN also doesn't have 128-bit lanes.
791static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0,
792 Value *Op1, Value *Shift,
793 Value *Passthru, Value *Mask,
794 bool IsVALIGN) {
795 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue();
796
797 unsigned NumElts = Op0->getType()->getVectorNumElements();
798 assert((IsVALIGN || NumElts % 16 == 0) && "Illegal NumElts for PALIGNR!")(static_cast <bool> ((IsVALIGN || NumElts % 16 == 0) &&
"Illegal NumElts for PALIGNR!") ? void (0) : __assert_fail (
"(IsVALIGN || NumElts % 16 == 0) && \"Illegal NumElts for PALIGNR!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 798, __extension__ __PRETTY_FUNCTION__))
;
799 assert((!IsVALIGN || NumElts <= 16) && "NumElts too large for VALIGN!")(static_cast <bool> ((!IsVALIGN || NumElts <= 16) &&
"NumElts too large for VALIGN!") ? void (0) : __assert_fail (
"(!IsVALIGN || NumElts <= 16) && \"NumElts too large for VALIGN!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 799, __extension__ __PRETTY_FUNCTION__))
;
800 assert(isPowerOf2_32(NumElts) && "NumElts not a power of 2!")(static_cast <bool> (isPowerOf2_32(NumElts) && "NumElts not a power of 2!"
) ? void (0) : __assert_fail ("isPowerOf2_32(NumElts) && \"NumElts not a power of 2!\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 800, __extension__ __PRETTY_FUNCTION__))
;
801
802 // Mask the immediate for VALIGN.
803 if (IsVALIGN)
804 ShiftVal &= (NumElts - 1);
805
806 // If palignr is shifting the pair of vectors more than the size of two
807 // lanes, emit zero.
808 if (ShiftVal >= 32)
809 return llvm::Constant::getNullValue(Op0->getType());
810
811 // If palignr is shifting the pair of input vectors more than one lane,
812 // but less than two lanes, convert to shifting in zeroes.
813 if (ShiftVal > 16) {
814 ShiftVal -= 16;
815 Op1 = Op0;
816 Op0 = llvm::Constant::getNullValue(Op0->getType());
817 }
818
819 uint32_t Indices[64];
820 // 256-bit palignr operates on 128-bit lanes so we need to handle that
821 for (unsigned l = 0; l < NumElts; l += 16) {
822 for (unsigned i = 0; i != 16; ++i) {
823 unsigned Idx = ShiftVal + i;
824 if (!IsVALIGN && Idx >= 16) // Disable wrap for VALIGN.
825 Idx += NumElts - 16; // End of lane, switch operand.
826 Indices[l + i] = Idx + l;
827 }
828 }
829
830 Value *Align = Builder.CreateShuffleVector(Op1, Op0,
831 makeArrayRef(Indices, NumElts),
832 "palignr");
833
834 return EmitX86Select(Builder, Mask, Align, Passthru);
835}
836
837static Value *UpgradeMaskedStore(IRBuilder<> &Builder,
838 Value *Ptr, Value *Data, Value *Mask,
839 bool Aligned) {
840 // Cast the pointer to the right type.
841 Ptr = Builder.CreateBitCast(Ptr,
842 llvm::PointerType::getUnqual(Data->getType()));
843 unsigned Align =
844 Aligned ? cast<VectorType>(Data->getType())->getBitWidth() / 8 : 1;
845
846 // If the mask is all ones just emit a regular store.
847 if (const auto *C = dyn_cast<Constant>(Mask))
848 if (C->isAllOnesValue())
849 return Builder.CreateAlignedStore(Data, Ptr, Align);
850
851 // Convert the mask from an integer type to a vector of i1.
852 unsigned NumElts = Data->getType()->getVectorNumElements();
853 Mask = getX86MaskVec(Builder, Mask, NumElts);
854 return Builder.CreateMaskedStore(Data, Ptr, Align, Mask);
855}
856
857static Value *UpgradeMaskedLoad(IRBuilder<> &Builder,
858 Value *Ptr, Value *Passthru, Value *Mask,
859 bool Aligned) {
860 // Cast the pointer to the right type.
861 Ptr = Builder.CreateBitCast(Ptr,
862 llvm::PointerType::getUnqual(Passthru->getType()));
863 unsigned Align =
864 Aligned ? cast<VectorType>(Passthru->getType())->getBitWidth() / 8 : 1;
865
866 // If the mask is all ones just emit a regular store.
867 if (const auto *C = dyn_cast<Constant>(Mask))
868 if (C->isAllOnesValue())
869 return Builder.CreateAlignedLoad(Ptr, Align);
870
871 // Convert the mask from an integer type to a vector of i1.
872 unsigned NumElts = Passthru->getType()->getVectorNumElements();
873 Mask = getX86MaskVec(Builder, Mask, NumElts);
874 return Builder.CreateMaskedLoad(Ptr, Align, Mask, Passthru);
875}
876
877static Value *upgradeAbs(IRBuilder<> &Builder, CallInst &CI) {
878 Value *Op0 = CI.getArgOperand(0);
879 llvm::Type *Ty = Op0->getType();
880 Value *Zero = llvm::Constant::getNullValue(Ty);
881 Value *Cmp = Builder.CreateICmp(ICmpInst::ICMP_SGT, Op0, Zero);
882 Value *Neg = Builder.CreateNeg(Op0);
883 Value *Res = Builder.CreateSelect(Cmp, Op0, Neg);
884
885 if (CI.getNumArgOperands() == 3)
886 Res = EmitX86Select(Builder,CI.getArgOperand(2), Res, CI.getArgOperand(1));
887
888 return Res;
889}
890
891static Value *upgradeIntMinMax(IRBuilder<> &Builder, CallInst &CI,
892 ICmpInst::Predicate Pred) {
893 Value *Op0 = CI.getArgOperand(0);
894 Value *Op1 = CI.getArgOperand(1);
895 Value *Cmp = Builder.CreateICmp(Pred, Op0, Op1);
896 Value *Res = Builder.CreateSelect(Cmp, Op0, Op1);
897
898 if (CI.getNumArgOperands() == 4)
899 Res = EmitX86Select(Builder, CI.getArgOperand(3), Res, CI.getArgOperand(2));
900
901 return Res;
902}
903
904// Applying mask on vector of i1's and make sure result is at least 8 bits wide.
905static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder,Value *Vec, Value *Mask,
906 unsigned NumElts) {
907 if (Mask) {
11
Taking true branch
908 const auto *C = dyn_cast<Constant>(Mask);
909 if (!C || !C->isAllOnesValue())
12
Assuming 'C' is non-null
13
Assuming the condition is false
14
Taking false branch
910 Vec = Builder.CreateAnd(Vec, getX86MaskVec(Builder, Mask, NumElts));
911 }
912
913 if (NumElts < 8) {
15
Assuming 'NumElts' is < 8
16
Taking true branch
914 uint32_t Indices[8];
915 for (unsigned i = 0; i != NumElts; ++i)
17
Assuming 'i' is equal to 'NumElts'
18
Loop condition is false. Execution continues on line 917
916 Indices[i] = i;
917 for (unsigned i = NumElts; i != 8; ++i)
19
Loop condition is true. Entering loop body
918 Indices[i] = NumElts + i % NumElts;
20
Division by zero
919 Vec = Builder.CreateShuffleVector(Vec,
920 Constant::getNullValue(Vec->getType()),
921 Indices);
922 }
923 return Builder.CreateBitCast(Vec, Builder.getIntNTy(std::max(NumElts, 8U)));
924}
925
926static Value *upgradeMaskedCompare(IRBuilder<> &Builder, CallInst &CI,
927 unsigned CC, bool Signed) {
928 Value *Op0 = CI.getArgOperand(0);
929 unsigned NumElts = Op0->getType()->getVectorNumElements();
930
931 Value *Cmp;
932 if (CC == 3) {
1
Assuming 'CC' is not equal to 3
2
Taking false branch
933 Cmp = Constant::getNullValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts));
934 } else if (CC == 7) {
3
Assuming 'CC' is not equal to 7
4
Taking false branch
935 Cmp = Constant::getAllOnesValue(llvm::VectorType::get(Builder.getInt1Ty(), NumElts));
936 } else {
937 ICmpInst::Predicate Pred;
938 switch (CC) {
5
Control jumps to 'case 6:' at line 945
939 default: llvm_unreachable("Unknown condition code")::llvm::llvm_unreachable_internal("Unknown condition code", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 939)
;
940 case 0: Pred = ICmpInst::ICMP_EQ; break;
941 case 1: Pred = Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT; break;
942 case 2: Pred = Signed ? ICmpInst::ICMP_SLE : ICmpInst::ICMP_ULE; break;
943 case 4: Pred = ICmpInst::ICMP_NE; break;
944 case 5: Pred = Signed ? ICmpInst::ICMP_SGE : ICmpInst::ICMP_UGE; break;
945 case 6: Pred = Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT; break;
6
Assuming 'Signed' is 0
7
'?' condition is false
8
Execution continues on line 947
946 }
947 Cmp = Builder.CreateICmp(Pred, Op0, CI.getArgOperand(1));
948 }
949
950 Value *Mask = CI.getArgOperand(CI.getNumArgOperands() - 1);
951
952 return ApplyX86MaskOn1BitsVec(Builder, Cmp, Mask, NumElts);
9
Passing value via 4th parameter 'NumElts'
10
Calling 'ApplyX86MaskOn1BitsVec'
953}
954
955// Replace a masked intrinsic with an older unmasked intrinsic.
956static Value *UpgradeX86MaskedShift(IRBuilder<> &Builder, CallInst &CI,
957 Intrinsic::ID IID) {
958 Function *F = CI.getCalledFunction();
959 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID);
960 Value *Rep = Builder.CreateCall(Intrin,
961 { CI.getArgOperand(0), CI.getArgOperand(1) });
962 return EmitX86Select(Builder, CI.getArgOperand(3), Rep, CI.getArgOperand(2));
963}
964
965static Value* upgradeMaskedMove(IRBuilder<> &Builder, CallInst &CI) {
966 Value* A = CI.getArgOperand(0);
967 Value* B = CI.getArgOperand(1);
968 Value* Src = CI.getArgOperand(2);
969 Value* Mask = CI.getArgOperand(3);
970
971 Value* AndNode = Builder.CreateAnd(Mask, APInt(8, 1));
972 Value* Cmp = Builder.CreateIsNotNull(AndNode);
973 Value* Extract1 = Builder.CreateExtractElement(B, (uint64_t)0);
974 Value* Extract2 = Builder.CreateExtractElement(Src, (uint64_t)0);
975 Value* Select = Builder.CreateSelect(Cmp, Extract1, Extract2);
976 return Builder.CreateInsertElement(A, Select, (uint64_t)0);
977}
978
979
980static Value* UpgradeMaskToInt(IRBuilder<> &Builder, CallInst &CI) {
981 Value* Op = CI.getArgOperand(0);
982 Type* ReturnOp = CI.getType();
983 unsigned NumElts = CI.getType()->getVectorNumElements();
984 Value *Mask = getX86MaskVec(Builder, Op, NumElts);
985 return Builder.CreateSExt(Mask, ReturnOp, "vpmovm2");
986}
987
988/// Upgrade a call to an old intrinsic. All argument and return casting must be
989/// provided to seamlessly integrate with existing context.
990void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
991 Function *F = CI->getCalledFunction();
992 LLVMContext &C = CI->getContext();
993 IRBuilder<> Builder(C);
994 Builder.SetInsertPoint(CI->getParent(), CI->getIterator());
995
996 assert(F && "Intrinsic call is not direct?")(static_cast <bool> (F && "Intrinsic call is not direct?"
) ? void (0) : __assert_fail ("F && \"Intrinsic call is not direct?\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 996, __extension__ __PRETTY_FUNCTION__))
;
997
998 if (!NewFn) {
999 // Get the Function's name.
1000 StringRef Name = F->getName();
1001
1002 assert(Name.startswith("llvm.") && "Intrinsic doesn't start with 'llvm.'")(static_cast <bool> (Name.startswith("llvm.") &&
"Intrinsic doesn't start with 'llvm.'") ? void (0) : __assert_fail
("Name.startswith(\"llvm.\") && \"Intrinsic doesn't start with 'llvm.'\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1002, __extension__ __PRETTY_FUNCTION__))
;
1003 Name = Name.substr(5);
1004
1005 bool IsX86 = Name.startswith("x86.");
1006 if (IsX86)
1007 Name = Name.substr(4);
1008 bool IsNVVM = Name.startswith("nvvm.");
1009 if (IsNVVM)
1010 Name = Name.substr(5);
1011
1012 if (IsX86 && Name.startswith("sse4a.movnt.")) {
1013 Module *M = F->getParent();
1014 SmallVector<Metadata *, 1> Elts;
1015 Elts.push_back(
1016 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1)));
1017 MDNode *Node = MDNode::get(C, Elts);
1018
1019 Value *Arg0 = CI->getArgOperand(0);
1020 Value *Arg1 = CI->getArgOperand(1);
1021
1022 // Nontemporal (unaligned) store of the 0'th element of the float/double
1023 // vector.
1024 Type *SrcEltTy = cast<VectorType>(Arg1->getType())->getElementType();
1025 PointerType *EltPtrTy = PointerType::getUnqual(SrcEltTy);
1026 Value *Addr = Builder.CreateBitCast(Arg0, EltPtrTy, "cast");
1027 Value *Extract =
1028 Builder.CreateExtractElement(Arg1, (uint64_t)0, "extractelement");
1029
1030 StoreInst *SI = Builder.CreateAlignedStore(Extract, Addr, 1);
1031 SI->setMetadata(M->getMDKindID("nontemporal"), Node);
1032
1033 // Remove intrinsic.
1034 CI->eraseFromParent();
1035 return;
1036 }
1037
1038 if (IsX86 && (Name.startswith("avx.movnt.") ||
1039 Name.startswith("avx512.storent."))) {
1040 Module *M = F->getParent();
1041 SmallVector<Metadata *, 1> Elts;
1042 Elts.push_back(
1043 ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1)));
1044 MDNode *Node = MDNode::get(C, Elts);
1045
1046 Value *Arg0 = CI->getArgOperand(0);
1047 Value *Arg1 = CI->getArgOperand(1);
1048
1049 // Convert the type of the pointer to a pointer to the stored type.
1050 Value *BC = Builder.CreateBitCast(Arg0,
1051 PointerType::getUnqual(Arg1->getType()),
1052 "cast");
1053 VectorType *VTy = cast<VectorType>(Arg1->getType());
1054 StoreInst *SI = Builder.CreateAlignedStore(Arg1, BC,
1055 VTy->getBitWidth() / 8);
1056 SI->setMetadata(M->getMDKindID("nontemporal"), Node);
1057
1058 // Remove intrinsic.
1059 CI->eraseFromParent();
1060 return;
1061 }
1062
1063 if (IsX86 && Name == "sse2.storel.dq") {
1064 Value *Arg0 = CI->getArgOperand(0);
1065 Value *Arg1 = CI->getArgOperand(1);
1066
1067 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2);
1068 Value *BC0 = Builder.CreateBitCast(Arg1, NewVecTy, "cast");
1069 Value *Elt = Builder.CreateExtractElement(BC0, (uint64_t)0);
1070 Value *BC = Builder.CreateBitCast(Arg0,
1071 PointerType::getUnqual(Elt->getType()),
1072 "cast");
1073 Builder.CreateAlignedStore(Elt, BC, 1);
1074
1075 // Remove intrinsic.
1076 CI->eraseFromParent();
1077 return;
1078 }
1079
1080 if (IsX86 && (Name.startswith("sse.storeu.") ||
1081 Name.startswith("sse2.storeu.") ||
1082 Name.startswith("avx.storeu."))) {
1083 Value *Arg0 = CI->getArgOperand(0);
1084 Value *Arg1 = CI->getArgOperand(1);
1085
1086 Arg0 = Builder.CreateBitCast(Arg0,
1087 PointerType::getUnqual(Arg1->getType()),
1088 "cast");
1089 Builder.CreateAlignedStore(Arg1, Arg0, 1);
1090
1091 // Remove intrinsic.
1092 CI->eraseFromParent();
1093 return;
1094 }
1095
1096 if (IsX86 && (Name.startswith("avx512.mask.store"))) {
1097 // "avx512.mask.storeu." or "avx512.mask.store."
1098 bool Aligned = Name[17] != 'u'; // "avx512.mask.storeu".
1099 UpgradeMaskedStore(Builder, CI->getArgOperand(0), CI->getArgOperand(1),
1100 CI->getArgOperand(2), Aligned);
1101
1102 // Remove intrinsic.
1103 CI->eraseFromParent();
1104 return;
1105 }
1106
1107 Value *Rep;
1108 // Upgrade packed integer vector compare intrinsics to compare instructions.
1109 if (IsX86 && (Name.startswith("sse2.pcmp") ||
1110 Name.startswith("avx2.pcmp"))) {
1111 // "sse2.pcpmpeq." "sse2.pcmpgt." "avx2.pcmpeq." or "avx2.pcmpgt."
1112 bool CmpEq = Name[9] == 'e';
1113 Rep = Builder.CreateICmp(CmpEq ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_SGT,
1114 CI->getArgOperand(0), CI->getArgOperand(1));
1115 Rep = Builder.CreateSExt(Rep, CI->getType(), "");
1116 } else if (IsX86 && (Name.startswith("avx512.broadcastm"))) {
1117 Type *ExtTy = Type::getInt32Ty(C);
1118 if (CI->getOperand(0)->getType()->isIntegerTy(8))
1119 ExtTy = Type::getInt64Ty(C);
1120 unsigned NumElts = CI->getType()->getPrimitiveSizeInBits() /
1121 ExtTy->getPrimitiveSizeInBits();
1122 Rep = Builder.CreateZExt(CI->getArgOperand(0), ExtTy);
1123 Rep = Builder.CreateVectorSplat(NumElts, Rep);
1124 } else if (IsX86 && (Name.startswith("avx512.ptestm") ||
1125 Name.startswith("avx512.ptestnm"))) {
1126 Value *Op0 = CI->getArgOperand(0);
1127 Value *Op1 = CI->getArgOperand(1);
1128 Value *Mask = CI->getArgOperand(2);
1129 Rep = Builder.CreateAnd(Op0, Op1);
1130 llvm::Type *Ty = Op0->getType();
1131 Value *Zero = llvm::Constant::getNullValue(Ty);
1132 ICmpInst::Predicate Pred =
1133 Name.startswith("avx512.ptestm") ? ICmpInst::ICMP_NE : ICmpInst::ICMP_EQ;
1134 Rep = Builder.CreateICmp(Pred, Rep, Zero);
1135 unsigned NumElts = Op0->getType()->getVectorNumElements();
1136 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, Mask, NumElts);
1137 } else if (IsX86 && (Name.startswith("avx512.mask.pbroadcast"))){
1138 unsigned NumElts =
1139 CI->getArgOperand(1)->getType()->getVectorNumElements();
1140 Rep = Builder.CreateVectorSplat(NumElts, CI->getArgOperand(0));
1141 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1142 CI->getArgOperand(1));
1143 } else if (IsX86 && (Name.startswith("avx512.kunpck"))) {
1144 unsigned NumElts = CI->getType()->getScalarSizeInBits();
1145 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts);
1146 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts);
1147 uint32_t Indices[64];
1148 for (unsigned i = 0; i != NumElts; ++i)
1149 Indices[i] = i;
1150
1151 // First extract half of each vector. This gives better codegen than
1152 // doing it in a single shuffle.
1153 LHS = Builder.CreateShuffleVector(LHS, LHS,
1154 makeArrayRef(Indices, NumElts / 2));
1155 RHS = Builder.CreateShuffleVector(RHS, RHS,
1156 makeArrayRef(Indices, NumElts / 2));
1157 // Concat the vectors.
1158 // NOTE: Operands have to be swapped to match intrinsic definition.
1159 Rep = Builder.CreateShuffleVector(RHS, LHS,
1160 makeArrayRef(Indices, NumElts));
1161 Rep = Builder.CreateBitCast(Rep, CI->getType());
1162 } else if (IsX86 && Name == "avx512.kand.w") {
1163 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1164 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16);
1165 Rep = Builder.CreateAnd(LHS, RHS);
1166 Rep = Builder.CreateBitCast(Rep, CI->getType());
1167 } else if (IsX86 && Name == "avx512.kandn.w") {
1168 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1169 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16);
1170 LHS = Builder.CreateNot(LHS);
1171 Rep = Builder.CreateAnd(LHS, RHS);
1172 Rep = Builder.CreateBitCast(Rep, CI->getType());
1173 } else if (IsX86 && Name == "avx512.kor.w") {
1174 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1175 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16);
1176 Rep = Builder.CreateOr(LHS, RHS);
1177 Rep = Builder.CreateBitCast(Rep, CI->getType());
1178 } else if (IsX86 && Name == "avx512.kxor.w") {
1179 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1180 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16);
1181 Rep = Builder.CreateXor(LHS, RHS);
1182 Rep = Builder.CreateBitCast(Rep, CI->getType());
1183 } else if (IsX86 && Name == "avx512.kxnor.w") {
1184 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1185 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16);
1186 LHS = Builder.CreateNot(LHS);
1187 Rep = Builder.CreateXor(LHS, RHS);
1188 Rep = Builder.CreateBitCast(Rep, CI->getType());
1189 } else if (IsX86 && Name == "avx512.knot.w") {
1190 Rep = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1191 Rep = Builder.CreateNot(Rep);
1192 Rep = Builder.CreateBitCast(Rep, CI->getType());
1193 } else if (IsX86 &&
1194 (Name == "avx512.kortestz.w" || Name == "avx512.kortestc.w")) {
1195 Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), 16);
1196 Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), 16);
1197 Rep = Builder.CreateOr(LHS, RHS);
1198 Rep = Builder.CreateBitCast(Rep, Builder.getInt16Ty());
1199 Value *C;
1200 if (Name[14] == 'c')
1201 C = ConstantInt::getAllOnesValue(Builder.getInt16Ty());
1202 else
1203 C = ConstantInt::getNullValue(Builder.getInt16Ty());
1204 Rep = Builder.CreateICmpEQ(Rep, C);
1205 Rep = Builder.CreateZExt(Rep, Builder.getInt32Ty());
1206 } else if (IsX86 && (Name == "sse.add.ss" || Name == "sse2.add.sd")) {
1207 Type *I32Ty = Type::getInt32Ty(C);
1208 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0),
1209 ConstantInt::get(I32Ty, 0));
1210 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1),
1211 ConstantInt::get(I32Ty, 0));
1212 Rep = Builder.CreateInsertElement(CI->getArgOperand(0),
1213 Builder.CreateFAdd(Elt0, Elt1),
1214 ConstantInt::get(I32Ty, 0));
1215 } else if (IsX86 && (Name == "sse.sub.ss" || Name == "sse2.sub.sd")) {
1216 Type *I32Ty = Type::getInt32Ty(C);
1217 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0),
1218 ConstantInt::get(I32Ty, 0));
1219 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1),
1220 ConstantInt::get(I32Ty, 0));
1221 Rep = Builder.CreateInsertElement(CI->getArgOperand(0),
1222 Builder.CreateFSub(Elt0, Elt1),
1223 ConstantInt::get(I32Ty, 0));
1224 } else if (IsX86 && (Name == "sse.mul.ss" || Name == "sse2.mul.sd")) {
1225 Type *I32Ty = Type::getInt32Ty(C);
1226 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0),
1227 ConstantInt::get(I32Ty, 0));
1228 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1),
1229 ConstantInt::get(I32Ty, 0));
1230 Rep = Builder.CreateInsertElement(CI->getArgOperand(0),
1231 Builder.CreateFMul(Elt0, Elt1),
1232 ConstantInt::get(I32Ty, 0));
1233 } else if (IsX86 && (Name == "sse.div.ss" || Name == "sse2.div.sd")) {
1234 Type *I32Ty = Type::getInt32Ty(C);
1235 Value *Elt0 = Builder.CreateExtractElement(CI->getArgOperand(0),
1236 ConstantInt::get(I32Ty, 0));
1237 Value *Elt1 = Builder.CreateExtractElement(CI->getArgOperand(1),
1238 ConstantInt::get(I32Ty, 0));
1239 Rep = Builder.CreateInsertElement(CI->getArgOperand(0),
1240 Builder.CreateFDiv(Elt0, Elt1),
1241 ConstantInt::get(I32Ty, 0));
1242 } else if (IsX86 && Name.startswith("avx512.mask.pcmp")) {
1243 // "avx512.mask.pcmpeq." or "avx512.mask.pcmpgt."
1244 bool CmpEq = Name[16] == 'e';
1245 Rep = upgradeMaskedCompare(Builder, *CI, CmpEq ? 0 : 6, true);
1246 } else if (IsX86 && Name.startswith("avx512.mask.cmp")) {
1247 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1248 Rep = upgradeMaskedCompare(Builder, *CI, Imm, true);
1249 } else if (IsX86 && Name.startswith("avx512.mask.ucmp")) {
1250 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1251 Rep = upgradeMaskedCompare(Builder, *CI, Imm, false);
1252 } else if (IsX86 && (Name.startswith("avx512.cvtb2mask.") ||
1253 Name.startswith("avx512.cvtw2mask.") ||
1254 Name.startswith("avx512.cvtd2mask.") ||
1255 Name.startswith("avx512.cvtq2mask."))) {
1256 Value *Op = CI->getArgOperand(0);
1257 Value *Zero = llvm::Constant::getNullValue(Op->getType());
1258 Rep = Builder.CreateICmp(ICmpInst::ICMP_SLT, Op, Zero);
1259 Rep = ApplyX86MaskOn1BitsVec(Builder, Rep, nullptr,
1260 Op->getType()->getVectorNumElements());
1261 } else if(IsX86 && (Name == "ssse3.pabs.b.128" ||
1262 Name == "ssse3.pabs.w.128" ||
1263 Name == "ssse3.pabs.d.128" ||
1264 Name.startswith("avx2.pabs") ||
1265 Name.startswith("avx512.mask.pabs"))) {
1266 Rep = upgradeAbs(Builder, *CI);
1267 } else if (IsX86 && (Name == "sse41.pmaxsb" ||
1268 Name == "sse2.pmaxs.w" ||
1269 Name == "sse41.pmaxsd" ||
1270 Name.startswith("avx2.pmaxs") ||
1271 Name.startswith("avx512.mask.pmaxs"))) {
1272 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SGT);
1273 } else if (IsX86 && (Name == "sse2.pmaxu.b" ||
1274 Name == "sse41.pmaxuw" ||
1275 Name == "sse41.pmaxud" ||
1276 Name.startswith("avx2.pmaxu") ||
1277 Name.startswith("avx512.mask.pmaxu"))) {
1278 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_UGT);
1279 } else if (IsX86 && (Name == "sse41.pminsb" ||
1280 Name == "sse2.pmins.w" ||
1281 Name == "sse41.pminsd" ||
1282 Name.startswith("avx2.pmins") ||
1283 Name.startswith("avx512.mask.pmins"))) {
1284 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_SLT);
1285 } else if (IsX86 && (Name == "sse2.pminu.b" ||
1286 Name == "sse41.pminuw" ||
1287 Name == "sse41.pminud" ||
1288 Name.startswith("avx2.pminu") ||
1289 Name.startswith("avx512.mask.pminu"))) {
1290 Rep = upgradeIntMinMax(Builder, *CI, ICmpInst::ICMP_ULT);
1291 } else if (IsX86 && (Name == "sse2.cvtdq2pd" ||
1292 Name == "sse2.cvtps2pd" ||
1293 Name == "avx.cvtdq2.pd.256" ||
1294 Name == "avx.cvt.ps2.pd.256" ||
1295 Name.startswith("avx512.mask.cvtdq2pd.") ||
1296 Name.startswith("avx512.mask.cvtudq2pd."))) {
1297 // Lossless i32/float to double conversion.
1298 // Extract the bottom elements if necessary and convert to double vector.
1299 Value *Src = CI->getArgOperand(0);
1300 VectorType *SrcTy = cast<VectorType>(Src->getType());
1301 VectorType *DstTy = cast<VectorType>(CI->getType());
1302 Rep = CI->getArgOperand(0);
1303
1304 unsigned NumDstElts = DstTy->getNumElements();
1305 if (NumDstElts < SrcTy->getNumElements()) {
1306 assert(NumDstElts == 2 && "Unexpected vector size")(static_cast <bool> (NumDstElts == 2 && "Unexpected vector size"
) ? void (0) : __assert_fail ("NumDstElts == 2 && \"Unexpected vector size\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1306, __extension__ __PRETTY_FUNCTION__))
;
1307 uint32_t ShuffleMask[2] = { 0, 1 };
1308 Rep = Builder.CreateShuffleVector(Rep, UndefValue::get(SrcTy),
1309 ShuffleMask);
1310 }
1311
1312 bool SInt2Double = (StringRef::npos != Name.find("cvtdq2"));
1313 bool UInt2Double = (StringRef::npos != Name.find("cvtudq2"));
1314 if (SInt2Double)
1315 Rep = Builder.CreateSIToFP(Rep, DstTy, "cvtdq2pd");
1316 else if (UInt2Double)
1317 Rep = Builder.CreateUIToFP(Rep, DstTy, "cvtudq2pd");
1318 else
1319 Rep = Builder.CreateFPExt(Rep, DstTy, "cvtps2pd");
1320
1321 if (CI->getNumArgOperands() == 3)
1322 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1323 CI->getArgOperand(1));
1324 } else if (IsX86 && (Name.startswith("avx512.mask.loadu."))) {
1325 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0),
1326 CI->getArgOperand(1), CI->getArgOperand(2),
1327 /*Aligned*/false);
1328 } else if (IsX86 && (Name.startswith("avx512.mask.load."))) {
1329 Rep = UpgradeMaskedLoad(Builder, CI->getArgOperand(0),
1330 CI->getArgOperand(1),CI->getArgOperand(2),
1331 /*Aligned*/true);
1332 } else if (IsX86 && Name.startswith("xop.vpcom")) {
1333 Intrinsic::ID intID;
1334 if (Name.endswith("ub"))
1335 intID = Intrinsic::x86_xop_vpcomub;
1336 else if (Name.endswith("uw"))
1337 intID = Intrinsic::x86_xop_vpcomuw;
1338 else if (Name.endswith("ud"))
1339 intID = Intrinsic::x86_xop_vpcomud;
1340 else if (Name.endswith("uq"))
1341 intID = Intrinsic::x86_xop_vpcomuq;
1342 else if (Name.endswith("b"))
1343 intID = Intrinsic::x86_xop_vpcomb;
1344 else if (Name.endswith("w"))
1345 intID = Intrinsic::x86_xop_vpcomw;
1346 else if (Name.endswith("d"))
1347 intID = Intrinsic::x86_xop_vpcomd;
1348 else if (Name.endswith("q"))
1349 intID = Intrinsic::x86_xop_vpcomq;
1350 else
1351 llvm_unreachable("Unknown suffix")::llvm::llvm_unreachable_internal("Unknown suffix", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1351)
;
1352
1353 Name = Name.substr(9); // strip off "xop.vpcom"
1354 unsigned Imm;
1355 if (Name.startswith("lt"))
1356 Imm = 0;
1357 else if (Name.startswith("le"))
1358 Imm = 1;
1359 else if (Name.startswith("gt"))
1360 Imm = 2;
1361 else if (Name.startswith("ge"))
1362 Imm = 3;
1363 else if (Name.startswith("eq"))
1364 Imm = 4;
1365 else if (Name.startswith("ne"))
1366 Imm = 5;
1367 else if (Name.startswith("false"))
1368 Imm = 6;
1369 else if (Name.startswith("true"))
1370 Imm = 7;
1371 else
1372 llvm_unreachable("Unknown condition")::llvm::llvm_unreachable_internal("Unknown condition", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1372)
;
1373
1374 Function *VPCOM = Intrinsic::getDeclaration(F->getParent(), intID);
1375 Rep =
1376 Builder.CreateCall(VPCOM, {CI->getArgOperand(0), CI->getArgOperand(1),
1377 Builder.getInt8(Imm)});
1378 } else if (IsX86 && Name.startswith("xop.vpcmov")) {
1379 Value *Sel = CI->getArgOperand(2);
1380 Value *NotSel = Builder.CreateNot(Sel);
1381 Value *Sel0 = Builder.CreateAnd(CI->getArgOperand(0), Sel);
1382 Value *Sel1 = Builder.CreateAnd(CI->getArgOperand(1), NotSel);
1383 Rep = Builder.CreateOr(Sel0, Sel1);
1384 } else if (IsX86 && Name == "sse42.crc32.64.8") {
1385 Function *CRC32 = Intrinsic::getDeclaration(F->getParent(),
1386 Intrinsic::x86_sse42_crc32_32_8);
1387 Value *Trunc0 = Builder.CreateTrunc(CI->getArgOperand(0), Type::getInt32Ty(C));
1388 Rep = Builder.CreateCall(CRC32, {Trunc0, CI->getArgOperand(1)});
1389 Rep = Builder.CreateZExt(Rep, CI->getType(), "");
1390 } else if (IsX86 && Name.startswith("avx.vbroadcast.s")) {
1391 // Replace broadcasts with a series of insertelements.
1392 Type *VecTy = CI->getType();
1393 Type *EltTy = VecTy->getVectorElementType();
1394 unsigned EltNum = VecTy->getVectorNumElements();
1395 Value *Cast = Builder.CreateBitCast(CI->getArgOperand(0),
1396 EltTy->getPointerTo());
1397 Value *Load = Builder.CreateLoad(EltTy, Cast);
1398 Type *I32Ty = Type::getInt32Ty(C);
1399 Rep = UndefValue::get(VecTy);
1400 for (unsigned I = 0; I < EltNum; ++I)
1401 Rep = Builder.CreateInsertElement(Rep, Load,
1402 ConstantInt::get(I32Ty, I));
1403 } else if (IsX86 && (Name.startswith("sse41.pmovsx") ||
1404 Name.startswith("sse41.pmovzx") ||
1405 Name.startswith("avx2.pmovsx") ||
1406 Name.startswith("avx2.pmovzx") ||
1407 Name.startswith("avx512.mask.pmovsx") ||
1408 Name.startswith("avx512.mask.pmovzx"))) {
1409 VectorType *SrcTy = cast<VectorType>(CI->getArgOperand(0)->getType());
1410 VectorType *DstTy = cast<VectorType>(CI->getType());
1411 unsigned NumDstElts = DstTy->getNumElements();
1412
1413 // Extract a subvector of the first NumDstElts lanes and sign/zero extend.
1414 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts);
1415 for (unsigned i = 0; i != NumDstElts; ++i)
1416 ShuffleMask[i] = i;
1417
1418 Value *SV = Builder.CreateShuffleVector(
1419 CI->getArgOperand(0), UndefValue::get(SrcTy), ShuffleMask);
1420
1421 bool DoSext = (StringRef::npos != Name.find("pmovsx"));
1422 Rep = DoSext ? Builder.CreateSExt(SV, DstTy)
1423 : Builder.CreateZExt(SV, DstTy);
1424 // If there are 3 arguments, it's a masked intrinsic so we need a select.
1425 if (CI->getNumArgOperands() == 3)
1426 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1427 CI->getArgOperand(1));
1428 } else if (IsX86 && (Name.startswith("avx.vbroadcastf128") ||
1429 Name == "avx2.vbroadcasti128")) {
1430 // Replace vbroadcastf128/vbroadcasti128 with a vector load+shuffle.
1431 Type *EltTy = CI->getType()->getVectorElementType();
1432 unsigned NumSrcElts = 128 / EltTy->getPrimitiveSizeInBits();
1433 Type *VT = VectorType::get(EltTy, NumSrcElts);
1434 Value *Op = Builder.CreatePointerCast(CI->getArgOperand(0),
1435 PointerType::getUnqual(VT));
1436 Value *Load = Builder.CreateAlignedLoad(Op, 1);
1437 if (NumSrcElts == 2)
1438 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()),
1439 { 0, 1, 0, 1 });
1440 else
1441 Rep = Builder.CreateShuffleVector(Load, UndefValue::get(Load->getType()),
1442 { 0, 1, 2, 3, 0, 1, 2, 3 });
1443 } else if (IsX86 && (Name.startswith("avx512.mask.shuf.i") ||
1444 Name.startswith("avx512.mask.shuf.f"))) {
1445 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1446 Type *VT = CI->getType();
1447 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128;
1448 unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits();
1449 unsigned ControlBitsMask = NumLanes - 1;
1450 unsigned NumControlBits = NumLanes / 2;
1451 SmallVector<uint32_t, 8> ShuffleMask(0);
1452
1453 for (unsigned l = 0; l != NumLanes; ++l) {
1454 unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask;
1455 // We actually need the other source.
1456 if (l >= NumLanes / 2)
1457 LaneMask += NumLanes;
1458 for (unsigned i = 0; i != NumElementsInLane; ++i)
1459 ShuffleMask.push_back(LaneMask * NumElementsInLane + i);
1460 }
1461 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0),
1462 CI->getArgOperand(1), ShuffleMask);
1463 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep,
1464 CI->getArgOperand(3));
1465 }else if (IsX86 && (Name.startswith("avx512.mask.broadcastf") ||
1466 Name.startswith("avx512.mask.broadcasti"))) {
1467 unsigned NumSrcElts =
1468 CI->getArgOperand(0)->getType()->getVectorNumElements();
1469 unsigned NumDstElts = CI->getType()->getVectorNumElements();
1470
1471 SmallVector<uint32_t, 8> ShuffleMask(NumDstElts);
1472 for (unsigned i = 0; i != NumDstElts; ++i)
1473 ShuffleMask[i] = i % NumSrcElts;
1474
1475 Rep = Builder.CreateShuffleVector(CI->getArgOperand(0),
1476 CI->getArgOperand(0),
1477 ShuffleMask);
1478 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1479 CI->getArgOperand(1));
1480 } else if (IsX86 && (Name.startswith("avx2.pbroadcast") ||
1481 Name.startswith("avx2.vbroadcast") ||
1482 Name.startswith("avx512.pbroadcast") ||
1483 Name.startswith("avx512.mask.broadcast.s"))) {
1484 // Replace vp?broadcasts with a vector shuffle.
1485 Value *Op = CI->getArgOperand(0);
1486 unsigned NumElts = CI->getType()->getVectorNumElements();
1487 Type *MaskTy = VectorType::get(Type::getInt32Ty(C), NumElts);
1488 Rep = Builder.CreateShuffleVector(Op, UndefValue::get(Op->getType()),
1489 Constant::getNullValue(MaskTy));
1490
1491 if (CI->getNumArgOperands() == 3)
1492 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1493 CI->getArgOperand(1));
1494 } else if (IsX86 && Name.startswith("avx512.mask.palignr.")) {
1495 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0),
1496 CI->getArgOperand(1),
1497 CI->getArgOperand(2),
1498 CI->getArgOperand(3),
1499 CI->getArgOperand(4),
1500 false);
1501 } else if (IsX86 && Name.startswith("avx512.mask.valign.")) {
1502 Rep = UpgradeX86ALIGNIntrinsics(Builder, CI->getArgOperand(0),
1503 CI->getArgOperand(1),
1504 CI->getArgOperand(2),
1505 CI->getArgOperand(3),
1506 CI->getArgOperand(4),
1507 true);
1508 } else if (IsX86 && (Name == "sse2.psll.dq" ||
1509 Name == "avx2.psll.dq")) {
1510 // 128/256-bit shift left specified in bits.
1511 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1512 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0),
1513 Shift / 8); // Shift is in bits.
1514 } else if (IsX86 && (Name == "sse2.psrl.dq" ||
1515 Name == "avx2.psrl.dq")) {
1516 // 128/256-bit shift right specified in bits.
1517 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1518 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0),
1519 Shift / 8); // Shift is in bits.
1520 } else if (IsX86 && (Name == "sse2.psll.dq.bs" ||
1521 Name == "avx2.psll.dq.bs" ||
1522 Name == "avx512.psll.dq.512")) {
1523 // 128/256/512-bit shift left specified in bytes.
1524 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1525 Rep = UpgradeX86PSLLDQIntrinsics(Builder, CI->getArgOperand(0), Shift);
1526 } else if (IsX86 && (Name == "sse2.psrl.dq.bs" ||
1527 Name == "avx2.psrl.dq.bs" ||
1528 Name == "avx512.psrl.dq.512")) {
1529 // 128/256/512-bit shift right specified in bytes.
1530 unsigned Shift = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1531 Rep = UpgradeX86PSRLDQIntrinsics(Builder, CI->getArgOperand(0), Shift);
1532 } else if (IsX86 && (Name == "sse41.pblendw" ||
1533 Name.startswith("sse41.blendp") ||
1534 Name.startswith("avx.blend.p") ||
1535 Name == "avx2.pblendw" ||
1536 Name.startswith("avx2.pblendd."))) {
1537 Value *Op0 = CI->getArgOperand(0);
1538 Value *Op1 = CI->getArgOperand(1);
1539 unsigned Imm = cast <ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1540 VectorType *VecTy = cast<VectorType>(CI->getType());
1541 unsigned NumElts = VecTy->getNumElements();
1542
1543 SmallVector<uint32_t, 16> Idxs(NumElts);
1544 for (unsigned i = 0; i != NumElts; ++i)
1545 Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i;
1546
1547 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs);
1548 } else if (IsX86 && (Name.startswith("avx.vinsertf128.") ||
1549 Name == "avx2.vinserti128" ||
1550 Name.startswith("avx512.mask.insert"))) {
1551 Value *Op0 = CI->getArgOperand(0);
1552 Value *Op1 = CI->getArgOperand(1);
1553 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1554 unsigned DstNumElts = CI->getType()->getVectorNumElements();
1555 unsigned SrcNumElts = Op1->getType()->getVectorNumElements();
1556 unsigned Scale = DstNumElts / SrcNumElts;
1557
1558 // Mask off the high bits of the immediate value; hardware ignores those.
1559 Imm = Imm % Scale;
1560
1561 // Extend the second operand into a vector the size of the destination.
1562 Value *UndefV = UndefValue::get(Op1->getType());
1563 SmallVector<uint32_t, 8> Idxs(DstNumElts);
1564 for (unsigned i = 0; i != SrcNumElts; ++i)
1565 Idxs[i] = i;
1566 for (unsigned i = SrcNumElts; i != DstNumElts; ++i)
1567 Idxs[i] = SrcNumElts;
1568 Rep = Builder.CreateShuffleVector(Op1, UndefV, Idxs);
1569
1570 // Insert the second operand into the first operand.
1571
1572 // Note that there is no guarantee that instruction lowering will actually
1573 // produce a vinsertf128 instruction for the created shuffles. In
1574 // particular, the 0 immediate case involves no lane changes, so it can
1575 // be handled as a blend.
1576
1577 // Example of shuffle mask for 32-bit elements:
1578 // Imm = 1 <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
1579 // Imm = 0 <i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7 >
1580
1581 // First fill with identify mask.
1582 for (unsigned i = 0; i != DstNumElts; ++i)
1583 Idxs[i] = i;
1584 // Then replace the elements where we need to insert.
1585 for (unsigned i = 0; i != SrcNumElts; ++i)
1586 Idxs[i + Imm * SrcNumElts] = i + DstNumElts;
1587 Rep = Builder.CreateShuffleVector(Op0, Rep, Idxs);
1588
1589 // If the intrinsic has a mask operand, handle that.
1590 if (CI->getNumArgOperands() == 5)
1591 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep,
1592 CI->getArgOperand(3));
1593 } else if (IsX86 && (Name.startswith("avx.vextractf128.") ||
1594 Name == "avx2.vextracti128" ||
1595 Name.startswith("avx512.mask.vextract"))) {
1596 Value *Op0 = CI->getArgOperand(0);
1597 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1598 unsigned DstNumElts = CI->getType()->getVectorNumElements();
1599 unsigned SrcNumElts = Op0->getType()->getVectorNumElements();
1600 unsigned Scale = SrcNumElts / DstNumElts;
1601
1602 // Mask off the high bits of the immediate value; hardware ignores those.
1603 Imm = Imm % Scale;
1604
1605 // Get indexes for the subvector of the input vector.
1606 SmallVector<uint32_t, 8> Idxs(DstNumElts);
1607 for (unsigned i = 0; i != DstNumElts; ++i) {
1608 Idxs[i] = i + (Imm * DstNumElts);
1609 }
1610 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs);
1611
1612 // If the intrinsic has a mask operand, handle that.
1613 if (CI->getNumArgOperands() == 4)
1614 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1615 CI->getArgOperand(2));
1616 } else if (!IsX86 && Name == "stackprotectorcheck") {
1617 Rep = nullptr;
1618 } else if (IsX86 && (Name.startswith("avx512.mask.perm.df.") ||
1619 Name.startswith("avx512.mask.perm.di."))) {
1620 Value *Op0 = CI->getArgOperand(0);
1621 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1622 VectorType *VecTy = cast<VectorType>(CI->getType());
1623 unsigned NumElts = VecTy->getNumElements();
1624
1625 SmallVector<uint32_t, 8> Idxs(NumElts);
1626 for (unsigned i = 0; i != NumElts; ++i)
1627 Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3);
1628
1629 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs);
1630
1631 if (CI->getNumArgOperands() == 4)
1632 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1633 CI->getArgOperand(2));
1634 } else if (IsX86 && (Name.startswith("avx.vperm2f128.") ||
1635 Name == "avx2.vperm2i128")) {
1636 // The immediate permute control byte looks like this:
1637 // [1:0] - select 128 bits from sources for low half of destination
1638 // [2] - ignore
1639 // [3] - zero low half of destination
1640 // [5:4] - select 128 bits from sources for high half of destination
1641 // [6] - ignore
1642 // [7] - zero high half of destination
1643
1644 uint8_t Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1645
1646 unsigned NumElts = CI->getType()->getVectorNumElements();
1647 unsigned HalfSize = NumElts / 2;
1648 SmallVector<uint32_t, 8> ShuffleMask(NumElts);
1649
1650 // Determine which operand(s) are actually in use for this instruction.
1651 Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0);
1652 Value *V1 = (Imm & 0x20) ? CI->getArgOperand(1) : CI->getArgOperand(0);
1653
1654 // If needed, replace operands based on zero mask.
1655 V0 = (Imm & 0x08) ? ConstantAggregateZero::get(CI->getType()) : V0;
1656 V1 = (Imm & 0x80) ? ConstantAggregateZero::get(CI->getType()) : V1;
1657
1658 // Permute low half of result.
1659 unsigned StartIndex = (Imm & 0x01) ? HalfSize : 0;
1660 for (unsigned i = 0; i < HalfSize; ++i)
1661 ShuffleMask[i] = StartIndex + i;
1662
1663 // Permute high half of result.
1664 StartIndex = (Imm & 0x10) ? HalfSize : 0;
1665 for (unsigned i = 0; i < HalfSize; ++i)
1666 ShuffleMask[i + HalfSize] = NumElts + StartIndex + i;
1667
1668 Rep = Builder.CreateShuffleVector(V0, V1, ShuffleMask);
1669
1670 } else if (IsX86 && (Name.startswith("avx.vpermil.") ||
1671 Name == "sse2.pshuf.d" ||
1672 Name.startswith("avx512.mask.vpermil.p") ||
1673 Name.startswith("avx512.mask.pshuf.d."))) {
1674 Value *Op0 = CI->getArgOperand(0);
1675 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1676 VectorType *VecTy = cast<VectorType>(CI->getType());
1677 unsigned NumElts = VecTy->getNumElements();
1678 // Calculate the size of each index in the immediate.
1679 unsigned IdxSize = 64 / VecTy->getScalarSizeInBits();
1680 unsigned IdxMask = ((1 << IdxSize) - 1);
1681
1682 SmallVector<uint32_t, 8> Idxs(NumElts);
1683 // Lookup the bits for this element, wrapping around the immediate every
1684 // 8-bits. Elements are grouped into sets of 2 or 4 elements so we need
1685 // to offset by the first index of each group.
1686 for (unsigned i = 0; i != NumElts; ++i)
1687 Idxs[i] = ((Imm >> ((i * IdxSize) % 8)) & IdxMask) | (i & ~IdxMask);
1688
1689 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs);
1690
1691 if (CI->getNumArgOperands() == 4)
1692 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1693 CI->getArgOperand(2));
1694 } else if (IsX86 && (Name == "sse2.pshufl.w" ||
1695 Name.startswith("avx512.mask.pshufl.w."))) {
1696 Value *Op0 = CI->getArgOperand(0);
1697 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1698 unsigned NumElts = CI->getType()->getVectorNumElements();
1699
1700 SmallVector<uint32_t, 16> Idxs(NumElts);
1701 for (unsigned l = 0; l != NumElts; l += 8) {
1702 for (unsigned i = 0; i != 4; ++i)
1703 Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l;
1704 for (unsigned i = 4; i != 8; ++i)
1705 Idxs[i + l] = i + l;
1706 }
1707
1708 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs);
1709
1710 if (CI->getNumArgOperands() == 4)
1711 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1712 CI->getArgOperand(2));
1713 } else if (IsX86 && (Name == "sse2.pshufh.w" ||
1714 Name.startswith("avx512.mask.pshufh.w."))) {
1715 Value *Op0 = CI->getArgOperand(0);
1716 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
1717 unsigned NumElts = CI->getType()->getVectorNumElements();
1718
1719 SmallVector<uint32_t, 16> Idxs(NumElts);
1720 for (unsigned l = 0; l != NumElts; l += 8) {
1721 for (unsigned i = 0; i != 4; ++i)
1722 Idxs[i + l] = i + l;
1723 for (unsigned i = 0; i != 4; ++i)
1724 Idxs[i + l + 4] = ((Imm >> (2 * i)) & 0x3) + 4 + l;
1725 }
1726
1727 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs);
1728
1729 if (CI->getNumArgOperands() == 4)
1730 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1731 CI->getArgOperand(2));
1732 } else if (IsX86 && Name.startswith("avx512.mask.shuf.p")) {
1733 Value *Op0 = CI->getArgOperand(0);
1734 Value *Op1 = CI->getArgOperand(1);
1735 unsigned Imm = cast<ConstantInt>(CI->getArgOperand(2))->getZExtValue();
1736 unsigned NumElts = CI->getType()->getVectorNumElements();
1737
1738 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
1739 unsigned HalfLaneElts = NumLaneElts / 2;
1740
1741 SmallVector<uint32_t, 16> Idxs(NumElts);
1742 for (unsigned i = 0; i != NumElts; ++i) {
1743 // Base index is the starting element of the lane.
1744 Idxs[i] = i - (i % NumLaneElts);
1745 // If we are half way through the lane switch to the other source.
1746 if ((i % NumLaneElts) >= HalfLaneElts)
1747 Idxs[i] += NumElts;
1748 // Now select the specific element. By adding HalfLaneElts bits from
1749 // the immediate. Wrapping around the immediate every 8-bits.
1750 Idxs[i] += (Imm >> ((i * HalfLaneElts) % 8)) & ((1 << HalfLaneElts) - 1);
1751 }
1752
1753 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs);
1754
1755 Rep = EmitX86Select(Builder, CI->getArgOperand(4), Rep,
1756 CI->getArgOperand(3));
1757 } else if (IsX86 && (Name.startswith("avx512.mask.movddup") ||
1758 Name.startswith("avx512.mask.movshdup") ||
1759 Name.startswith("avx512.mask.movsldup"))) {
1760 Value *Op0 = CI->getArgOperand(0);
1761 unsigned NumElts = CI->getType()->getVectorNumElements();
1762 unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
1763
1764 unsigned Offset = 0;
1765 if (Name.startswith("avx512.mask.movshdup."))
1766 Offset = 1;
1767
1768 SmallVector<uint32_t, 16> Idxs(NumElts);
1769 for (unsigned l = 0; l != NumElts; l += NumLaneElts)
1770 for (unsigned i = 0; i != NumLaneElts; i += 2) {
1771 Idxs[i + l + 0] = i + l + Offset;
1772 Idxs[i + l + 1] = i + l + Offset;
1773 }
1774
1775 Rep = Builder.CreateShuffleVector(Op0, Op0, Idxs);
1776
1777 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1778 CI->getArgOperand(1));
1779 } else if (IsX86 && (Name.startswith("avx512.mask.punpckl") ||
1780 Name.startswith("avx512.mask.unpckl."))) {
1781 Value *Op0 = CI->getArgOperand(0);
1782 Value *Op1 = CI->getArgOperand(1);
1783 int NumElts = CI->getType()->getVectorNumElements();
1784 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
1785
1786 SmallVector<uint32_t, 64> Idxs(NumElts);
1787 for (int l = 0; l != NumElts; l += NumLaneElts)
1788 for (int i = 0; i != NumLaneElts; ++i)
1789 Idxs[i + l] = l + (i / 2) + NumElts * (i % 2);
1790
1791 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs);
1792
1793 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1794 CI->getArgOperand(2));
1795 } else if (IsX86 && (Name.startswith("avx512.mask.punpckh") ||
1796 Name.startswith("avx512.mask.unpckh."))) {
1797 Value *Op0 = CI->getArgOperand(0);
1798 Value *Op1 = CI->getArgOperand(1);
1799 int NumElts = CI->getType()->getVectorNumElements();
1800 int NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
1801
1802 SmallVector<uint32_t, 64> Idxs(NumElts);
1803 for (int l = 0; l != NumElts; l += NumLaneElts)
1804 for (int i = 0; i != NumLaneElts; ++i)
1805 Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2);
1806
1807 Rep = Builder.CreateShuffleVector(Op0, Op1, Idxs);
1808
1809 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1810 CI->getArgOperand(2));
1811 } else if (IsX86 && Name.startswith("avx512.mask.pand.")) {
1812 Rep = Builder.CreateAnd(CI->getArgOperand(0), CI->getArgOperand(1));
1813 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1814 CI->getArgOperand(2));
1815 } else if (IsX86 && Name.startswith("avx512.mask.pandn.")) {
1816 Rep = Builder.CreateAnd(Builder.CreateNot(CI->getArgOperand(0)),
1817 CI->getArgOperand(1));
1818 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1819 CI->getArgOperand(2));
1820 } else if (IsX86 && Name.startswith("avx512.mask.por.")) {
1821 Rep = Builder.CreateOr(CI->getArgOperand(0), CI->getArgOperand(1));
1822 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1823 CI->getArgOperand(2));
1824 } else if (IsX86 && Name.startswith("avx512.mask.pxor.")) {
1825 Rep = Builder.CreateXor(CI->getArgOperand(0), CI->getArgOperand(1));
1826 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1827 CI->getArgOperand(2));
1828 } else if (IsX86 && Name.startswith("avx512.mask.and.")) {
1829 VectorType *FTy = cast<VectorType>(CI->getType());
1830 VectorType *ITy = VectorType::getInteger(FTy);
1831 Rep = Builder.CreateAnd(Builder.CreateBitCast(CI->getArgOperand(0), ITy),
1832 Builder.CreateBitCast(CI->getArgOperand(1), ITy));
1833 Rep = Builder.CreateBitCast(Rep, FTy);
1834 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1835 CI->getArgOperand(2));
1836 } else if (IsX86 && Name.startswith("avx512.mask.andn.")) {
1837 VectorType *FTy = cast<VectorType>(CI->getType());
1838 VectorType *ITy = VectorType::getInteger(FTy);
1839 Rep = Builder.CreateNot(Builder.CreateBitCast(CI->getArgOperand(0), ITy));
1840 Rep = Builder.CreateAnd(Rep,
1841 Builder.CreateBitCast(CI->getArgOperand(1), ITy));
1842 Rep = Builder.CreateBitCast(Rep, FTy);
1843 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1844 CI->getArgOperand(2));
1845 } else if (IsX86 && Name.startswith("avx512.mask.or.")) {
1846 VectorType *FTy = cast<VectorType>(CI->getType());
1847 VectorType *ITy = VectorType::getInteger(FTy);
1848 Rep = Builder.CreateOr(Builder.CreateBitCast(CI->getArgOperand(0), ITy),
1849 Builder.CreateBitCast(CI->getArgOperand(1), ITy));
1850 Rep = Builder.CreateBitCast(Rep, FTy);
1851 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1852 CI->getArgOperand(2));
1853 } else if (IsX86 && Name.startswith("avx512.mask.xor.")) {
1854 VectorType *FTy = cast<VectorType>(CI->getType());
1855 VectorType *ITy = VectorType::getInteger(FTy);
1856 Rep = Builder.CreateXor(Builder.CreateBitCast(CI->getArgOperand(0), ITy),
1857 Builder.CreateBitCast(CI->getArgOperand(1), ITy));
1858 Rep = Builder.CreateBitCast(Rep, FTy);
1859 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1860 CI->getArgOperand(2));
1861 } else if (IsX86 && Name.startswith("avx512.mask.padd.")) {
1862 Rep = Builder.CreateAdd(CI->getArgOperand(0), CI->getArgOperand(1));
1863 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1864 CI->getArgOperand(2));
1865 } else if (IsX86 && Name.startswith("avx512.mask.psub.")) {
1866 Rep = Builder.CreateSub(CI->getArgOperand(0), CI->getArgOperand(1));
1867 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1868 CI->getArgOperand(2));
1869 } else if (IsX86 && Name.startswith("avx512.mask.pmull.")) {
1870 Rep = Builder.CreateMul(CI->getArgOperand(0), CI->getArgOperand(1));
1871 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1872 CI->getArgOperand(2));
1873 } else if (IsX86 && (Name.startswith("avx512.mask.add.p"))) {
1874 Rep = Builder.CreateFAdd(CI->getArgOperand(0), CI->getArgOperand(1));
1875 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1876 CI->getArgOperand(2));
1877 } else if (IsX86 && Name.startswith("avx512.mask.div.p")) {
1878 Rep = Builder.CreateFDiv(CI->getArgOperand(0), CI->getArgOperand(1));
1879 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1880 CI->getArgOperand(2));
1881 } else if (IsX86 && Name.startswith("avx512.mask.mul.p")) {
1882 Rep = Builder.CreateFMul(CI->getArgOperand(0), CI->getArgOperand(1));
1883 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1884 CI->getArgOperand(2));
1885 } else if (IsX86 && Name.startswith("avx512.mask.sub.p")) {
1886 Rep = Builder.CreateFSub(CI->getArgOperand(0), CI->getArgOperand(1));
1887 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1888 CI->getArgOperand(2));
1889 } else if (IsX86 && Name.startswith("avx512.mask.lzcnt.")) {
1890 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(),
1891 Intrinsic::ctlz,
1892 CI->getType()),
1893 { CI->getArgOperand(0), Builder.getInt1(false) });
1894 Rep = EmitX86Select(Builder, CI->getArgOperand(2), Rep,
1895 CI->getArgOperand(1));
1896 } else if (IsX86 && (Name.startswith("avx512.mask.max.p") ||
1897 Name.startswith("avx512.mask.min.p"))) {
1898 bool IsMin = Name[13] == 'i';
1899 VectorType *VecTy = cast<VectorType>(CI->getType());
1900 unsigned VecWidth = VecTy->getPrimitiveSizeInBits();
1901 unsigned EltWidth = VecTy->getScalarSizeInBits();
1902 Intrinsic::ID IID;
1903 if (!IsMin && VecWidth == 128 && EltWidth == 32)
1904 IID = Intrinsic::x86_sse_max_ps;
1905 else if (!IsMin && VecWidth == 128 && EltWidth == 64)
1906 IID = Intrinsic::x86_sse2_max_pd;
1907 else if (!IsMin && VecWidth == 256 && EltWidth == 32)
1908 IID = Intrinsic::x86_avx_max_ps_256;
1909 else if (!IsMin && VecWidth == 256 && EltWidth == 64)
1910 IID = Intrinsic::x86_avx_max_pd_256;
1911 else if (IsMin && VecWidth == 128 && EltWidth == 32)
1912 IID = Intrinsic::x86_sse_min_ps;
1913 else if (IsMin && VecWidth == 128 && EltWidth == 64)
1914 IID = Intrinsic::x86_sse2_min_pd;
1915 else if (IsMin && VecWidth == 256 && EltWidth == 32)
1916 IID = Intrinsic::x86_avx_min_ps_256;
1917 else if (IsMin && VecWidth == 256 && EltWidth == 64)
1918 IID = Intrinsic::x86_avx_min_pd_256;
1919 else
1920 llvm_unreachable("Unexpected intrinsic")::llvm::llvm_unreachable_internal("Unexpected intrinsic", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1920)
;
1921
1922 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
1923 { CI->getArgOperand(0), CI->getArgOperand(1) });
1924 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1925 CI->getArgOperand(2));
1926 } else if (IsX86 && Name.startswith("avx512.mask.pshuf.b.")) {
1927 VectorType *VecTy = cast<VectorType>(CI->getType());
1928 Intrinsic::ID IID;
1929 if (VecTy->getPrimitiveSizeInBits() == 128)
1930 IID = Intrinsic::x86_ssse3_pshuf_b_128;
1931 else if (VecTy->getPrimitiveSizeInBits() == 256)
1932 IID = Intrinsic::x86_avx2_pshuf_b;
1933 else if (VecTy->getPrimitiveSizeInBits() == 512)
1934 IID = Intrinsic::x86_avx512_pshuf_b_512;
1935 else
1936 llvm_unreachable("Unexpected intrinsic")::llvm::llvm_unreachable_internal("Unexpected intrinsic", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1936)
;
1937
1938 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
1939 { CI->getArgOperand(0), CI->getArgOperand(1) });
1940 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1941 CI->getArgOperand(2));
1942 } else if (IsX86 && (Name.startswith("avx512.mask.pmul.dq.") ||
1943 Name.startswith("avx512.mask.pmulu.dq."))) {
1944 bool IsUnsigned = Name[16] == 'u';
1945 VectorType *VecTy = cast<VectorType>(CI->getType());
1946 Intrinsic::ID IID;
1947 if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128)
1948 IID = Intrinsic::x86_sse41_pmuldq;
1949 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256)
1950 IID = Intrinsic::x86_avx2_pmul_dq;
1951 else if (!IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512)
1952 IID = Intrinsic::x86_avx512_pmul_dq_512;
1953 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 128)
1954 IID = Intrinsic::x86_sse2_pmulu_dq;
1955 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 256)
1956 IID = Intrinsic::x86_avx2_pmulu_dq;
1957 else if (IsUnsigned && VecTy->getPrimitiveSizeInBits() == 512)
1958 IID = Intrinsic::x86_avx512_pmulu_dq_512;
1959 else
1960 llvm_unreachable("Unexpected intrinsic")::llvm::llvm_unreachable_internal("Unexpected intrinsic", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1960)
;
1961
1962 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
1963 { CI->getArgOperand(0), CI->getArgOperand(1) });
1964 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
1965 CI->getArgOperand(2));
1966 } else if (IsX86 && Name.startswith("avx512.mask.pack")) {
1967 bool IsUnsigned = Name[16] == 'u';
1968 bool IsDW = Name[18] == 'd';
1969 VectorType *VecTy = cast<VectorType>(CI->getType());
1970 Intrinsic::ID IID;
1971 if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128)
1972 IID = Intrinsic::x86_sse2_packsswb_128;
1973 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256)
1974 IID = Intrinsic::x86_avx2_packsswb;
1975 else if (!IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512)
1976 IID = Intrinsic::x86_avx512_packsswb_512;
1977 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128)
1978 IID = Intrinsic::x86_sse2_packssdw_128;
1979 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256)
1980 IID = Intrinsic::x86_avx2_packssdw;
1981 else if (!IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512)
1982 IID = Intrinsic::x86_avx512_packssdw_512;
1983 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 128)
1984 IID = Intrinsic::x86_sse2_packuswb_128;
1985 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 256)
1986 IID = Intrinsic::x86_avx2_packuswb;
1987 else if (IsUnsigned && !IsDW && VecTy->getPrimitiveSizeInBits() == 512)
1988 IID = Intrinsic::x86_avx512_packuswb_512;
1989 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 128)
1990 IID = Intrinsic::x86_sse41_packusdw;
1991 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 256)
1992 IID = Intrinsic::x86_avx2_packusdw;
1993 else if (IsUnsigned && IsDW && VecTy->getPrimitiveSizeInBits() == 512)
1994 IID = Intrinsic::x86_avx512_packusdw_512;
1995 else
1996 llvm_unreachable("Unexpected intrinsic")::llvm::llvm_unreachable_internal("Unexpected intrinsic", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 1996)
;
1997
1998 Rep = Builder.CreateCall(Intrinsic::getDeclaration(F->getParent(), IID),
1999 { CI->getArgOperand(0), CI->getArgOperand(1) });
2000 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
2001 CI->getArgOperand(2));
2002 } else if (IsX86 && Name.startswith("avx512.mask.psll")) {
2003 bool IsImmediate = Name[16] == 'i' ||
2004 (Name.size() > 18 && Name[18] == 'i');
2005 bool IsVariable = Name[16] == 'v';
2006 char Size = Name[16] == '.' ? Name[17] :
2007 Name[17] == '.' ? Name[18] :
2008 Name[18] == '.' ? Name[19] :
2009 Name[20];
2010
2011 Intrinsic::ID IID;
2012 if (IsVariable && Name[17] != '.') {
2013 if (Size == 'd' && Name[17] == '2') // avx512.mask.psllv2.di
2014 IID = Intrinsic::x86_avx2_psllv_q;
2015 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psllv4.di
2016 IID = Intrinsic::x86_avx2_psllv_q_256;
2017 else if (Size == 's' && Name[17] == '4') // avx512.mask.psllv4.si
2018 IID = Intrinsic::x86_avx2_psllv_d;
2019 else if (Size == 's' && Name[17] == '8') // avx512.mask.psllv8.si
2020 IID = Intrinsic::x86_avx2_psllv_d_256;
2021 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psllv8.hi
2022 IID = Intrinsic::x86_avx512_psllv_w_128;
2023 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psllv16.hi
2024 IID = Intrinsic::x86_avx512_psllv_w_256;
2025 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psllv32hi
2026 IID = Intrinsic::x86_avx512_psllv_w_512;
2027 else
2028 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2028)
;
2029 } else if (Name.endswith(".128")) {
2030 if (Size == 'd') // avx512.mask.psll.d.128, avx512.mask.psll.di.128
2031 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_d
2032 : Intrinsic::x86_sse2_psll_d;
2033 else if (Size == 'q') // avx512.mask.psll.q.128, avx512.mask.psll.qi.128
2034 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_q
2035 : Intrinsic::x86_sse2_psll_q;
2036 else if (Size == 'w') // avx512.mask.psll.w.128, avx512.mask.psll.wi.128
2037 IID = IsImmediate ? Intrinsic::x86_sse2_pslli_w
2038 : Intrinsic::x86_sse2_psll_w;
2039 else
2040 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2040)
;
2041 } else if (Name.endswith(".256")) {
2042 if (Size == 'd') // avx512.mask.psll.d.256, avx512.mask.psll.di.256
2043 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_d
2044 : Intrinsic::x86_avx2_psll_d;
2045 else if (Size == 'q') // avx512.mask.psll.q.256, avx512.mask.psll.qi.256
2046 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_q
2047 : Intrinsic::x86_avx2_psll_q;
2048 else if (Size == 'w') // avx512.mask.psll.w.256, avx512.mask.psll.wi.256
2049 IID = IsImmediate ? Intrinsic::x86_avx2_pslli_w
2050 : Intrinsic::x86_avx2_psll_w;
2051 else
2052 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2052)
;
2053 } else {
2054 if (Size == 'd') // psll.di.512, pslli.d, psll.d, psllv.d.512
2055 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_d_512 :
2056 IsVariable ? Intrinsic::x86_avx512_psllv_d_512 :
2057 Intrinsic::x86_avx512_psll_d_512;
2058 else if (Size == 'q') // psll.qi.512, pslli.q, psll.q, psllv.q.512
2059 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_q_512 :
2060 IsVariable ? Intrinsic::x86_avx512_psllv_q_512 :
2061 Intrinsic::x86_avx512_psll_q_512;
2062 else if (Size == 'w') // psll.wi.512, pslli.w, psll.w
2063 IID = IsImmediate ? Intrinsic::x86_avx512_pslli_w_512
2064 : Intrinsic::x86_avx512_psll_w_512;
2065 else
2066 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2066)
;
2067 }
2068
2069 Rep = UpgradeX86MaskedShift(Builder, *CI, IID);
2070 } else if (IsX86 && Name.startswith("avx512.mask.psrl")) {
2071 bool IsImmediate = Name[16] == 'i' ||
2072 (Name.size() > 18 && Name[18] == 'i');
2073 bool IsVariable = Name[16] == 'v';
2074 char Size = Name[16] == '.' ? Name[17] :
2075 Name[17] == '.' ? Name[18] :
2076 Name[18] == '.' ? Name[19] :
2077 Name[20];
2078
2079 Intrinsic::ID IID;
2080 if (IsVariable && Name[17] != '.') {
2081 if (Size == 'd' && Name[17] == '2') // avx512.mask.psrlv2.di
2082 IID = Intrinsic::x86_avx2_psrlv_q;
2083 else if (Size == 'd' && Name[17] == '4') // avx512.mask.psrlv4.di
2084 IID = Intrinsic::x86_avx2_psrlv_q_256;
2085 else if (Size == 's' && Name[17] == '4') // avx512.mask.psrlv4.si
2086 IID = Intrinsic::x86_avx2_psrlv_d;
2087 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrlv8.si
2088 IID = Intrinsic::x86_avx2_psrlv_d_256;
2089 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrlv8.hi
2090 IID = Intrinsic::x86_avx512_psrlv_w_128;
2091 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrlv16.hi
2092 IID = Intrinsic::x86_avx512_psrlv_w_256;
2093 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrlv32hi
2094 IID = Intrinsic::x86_avx512_psrlv_w_512;
2095 else
2096 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2096)
;
2097 } else if (Name.endswith(".128")) {
2098 if (Size == 'd') // avx512.mask.psrl.d.128, avx512.mask.psrl.di.128
2099 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_d
2100 : Intrinsic::x86_sse2_psrl_d;
2101 else if (Size == 'q') // avx512.mask.psrl.q.128, avx512.mask.psrl.qi.128
2102 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_q
2103 : Intrinsic::x86_sse2_psrl_q;
2104 else if (Size == 'w') // avx512.mask.psrl.w.128, avx512.mask.psrl.wi.128
2105 IID = IsImmediate ? Intrinsic::x86_sse2_psrli_w
2106 : Intrinsic::x86_sse2_psrl_w;
2107 else
2108 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2108)
;
2109 } else if (Name.endswith(".256")) {
2110 if (Size == 'd') // avx512.mask.psrl.d.256, avx512.mask.psrl.di.256
2111 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_d
2112 : Intrinsic::x86_avx2_psrl_d;
2113 else if (Size == 'q') // avx512.mask.psrl.q.256, avx512.mask.psrl.qi.256
2114 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_q
2115 : Intrinsic::x86_avx2_psrl_q;
2116 else if (Size == 'w') // avx512.mask.psrl.w.256, avx512.mask.psrl.wi.256
2117 IID = IsImmediate ? Intrinsic::x86_avx2_psrli_w
2118 : Intrinsic::x86_avx2_psrl_w;
2119 else
2120 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2120)
;
2121 } else {
2122 if (Size == 'd') // psrl.di.512, psrli.d, psrl.d, psrl.d.512
2123 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_d_512 :
2124 IsVariable ? Intrinsic::x86_avx512_psrlv_d_512 :
2125 Intrinsic::x86_avx512_psrl_d_512;
2126 else if (Size == 'q') // psrl.qi.512, psrli.q, psrl.q, psrl.q.512
2127 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_q_512 :
2128 IsVariable ? Intrinsic::x86_avx512_psrlv_q_512 :
2129 Intrinsic::x86_avx512_psrl_q_512;
2130 else if (Size == 'w') // psrl.wi.512, psrli.w, psrl.w)
2131 IID = IsImmediate ? Intrinsic::x86_avx512_psrli_w_512
2132 : Intrinsic::x86_avx512_psrl_w_512;
2133 else
2134 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2134)
;
2135 }
2136
2137 Rep = UpgradeX86MaskedShift(Builder, *CI, IID);
2138 } else if (IsX86 && Name.startswith("avx512.mask.psra")) {
2139 bool IsImmediate = Name[16] == 'i' ||
2140 (Name.size() > 18 && Name[18] == 'i');
2141 bool IsVariable = Name[16] == 'v';
2142 char Size = Name[16] == '.' ? Name[17] :
2143 Name[17] == '.' ? Name[18] :
2144 Name[18] == '.' ? Name[19] :
2145 Name[20];
2146
2147 Intrinsic::ID IID;
2148 if (IsVariable && Name[17] != '.') {
2149 if (Size == 's' && Name[17] == '4') // avx512.mask.psrav4.si
2150 IID = Intrinsic::x86_avx2_psrav_d;
2151 else if (Size == 's' && Name[17] == '8') // avx512.mask.psrav8.si
2152 IID = Intrinsic::x86_avx2_psrav_d_256;
2153 else if (Size == 'h' && Name[17] == '8') // avx512.mask.psrav8.hi
2154 IID = Intrinsic::x86_avx512_psrav_w_128;
2155 else if (Size == 'h' && Name[17] == '1') // avx512.mask.psrav16.hi
2156 IID = Intrinsic::x86_avx512_psrav_w_256;
2157 else if (Name[17] == '3' && Name[18] == '2') // avx512.mask.psrav32hi
2158 IID = Intrinsic::x86_avx512_psrav_w_512;
2159 else
2160 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2160)
;
2161 } else if (Name.endswith(".128")) {
2162 if (Size == 'd') // avx512.mask.psra.d.128, avx512.mask.psra.di.128
2163 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_d
2164 : Intrinsic::x86_sse2_psra_d;
2165 else if (Size == 'q') // avx512.mask.psra.q.128, avx512.mask.psra.qi.128
2166 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_128 :
2167 IsVariable ? Intrinsic::x86_avx512_psrav_q_128 :
2168 Intrinsic::x86_avx512_psra_q_128;
2169 else if (Size == 'w') // avx512.mask.psra.w.128, avx512.mask.psra.wi.128
2170 IID = IsImmediate ? Intrinsic::x86_sse2_psrai_w
2171 : Intrinsic::x86_sse2_psra_w;
2172 else
2173 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2173)
;
2174 } else if (Name.endswith(".256")) {
2175 if (Size == 'd') // avx512.mask.psra.d.256, avx512.mask.psra.di.256
2176 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_d
2177 : Intrinsic::x86_avx2_psra_d;
2178 else if (Size == 'q') // avx512.mask.psra.q.256, avx512.mask.psra.qi.256
2179 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_256 :
2180 IsVariable ? Intrinsic::x86_avx512_psrav_q_256 :
2181 Intrinsic::x86_avx512_psra_q_256;
2182 else if (Size == 'w') // avx512.mask.psra.w.256, avx512.mask.psra.wi.256
2183 IID = IsImmediate ? Intrinsic::x86_avx2_psrai_w
2184 : Intrinsic::x86_avx2_psra_w;
2185 else
2186 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2186)
;
2187 } else {
2188 if (Size == 'd') // psra.di.512, psrai.d, psra.d, psrav.d.512
2189 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_d_512 :
2190 IsVariable ? Intrinsic::x86_avx512_psrav_d_512 :
2191 Intrinsic::x86_avx512_psra_d_512;
2192 else if (Size == 'q') // psra.qi.512, psrai.q, psra.q
2193 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_q_512 :
2194 IsVariable ? Intrinsic::x86_avx512_psrav_q_512 :
2195 Intrinsic::x86_avx512_psra_q_512;
2196 else if (Size == 'w') // psra.wi.512, psrai.w, psra.w
2197 IID = IsImmediate ? Intrinsic::x86_avx512_psrai_w_512
2198 : Intrinsic::x86_avx512_psra_w_512;
2199 else
2200 llvm_unreachable("Unexpected size")::llvm::llvm_unreachable_internal("Unexpected size", "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2200)
;
2201 }
2202
2203 Rep = UpgradeX86MaskedShift(Builder, *CI, IID);
2204 } else if (IsX86 && Name.startswith("avx512.mask.move.s")) {
2205 Rep = upgradeMaskedMove(Builder, *CI);
2206 } else if (IsX86 && Name.startswith("avx512.cvtmask2")) {
2207 Rep = UpgradeMaskToInt(Builder, *CI);
2208 } else if (IsX86 && Name.startswith("avx512.mask.vpermilvar.")) {
2209 Intrinsic::ID IID;
2210 if (Name.endswith("ps.128"))
2211 IID = Intrinsic::x86_avx_vpermilvar_ps;
2212 else if (Name.endswith("pd.128"))
2213 IID = Intrinsic::x86_avx_vpermilvar_pd;
2214 else if (Name.endswith("ps.256"))
2215 IID = Intrinsic::x86_avx_vpermilvar_ps_256;
2216 else if (Name.endswith("pd.256"))
2217 IID = Intrinsic::x86_avx_vpermilvar_pd_256;
2218 else if (Name.endswith("ps.512"))
2219 IID = Intrinsic::x86_avx512_vpermilvar_ps_512;
2220 else if (Name.endswith("pd.512"))
2221 IID = Intrinsic::x86_avx512_vpermilvar_pd_512;
2222 else
2223 llvm_unreachable("Unexpected vpermilvar intrinsic")::llvm::llvm_unreachable_internal("Unexpected vpermilvar intrinsic"
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2223)
;
2224
2225 Function *Intrin = Intrinsic::getDeclaration(F->getParent(), IID);
2226 Rep = Builder.CreateCall(Intrin,
2227 { CI->getArgOperand(0), CI->getArgOperand(1) });
2228 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
2229 CI->getArgOperand(2));
2230 } else if (IsX86 && Name.endswith(".movntdqa")) {
2231 Module *M = F->getParent();
2232 MDNode *Node = MDNode::get(
2233 C, ConstantAsMetadata::get(ConstantInt::get(Type::getInt32Ty(C), 1)));
2234
2235 Value *Ptr = CI->getArgOperand(0);
2236 VectorType *VTy = cast<VectorType>(CI->getType());
2237
2238 // Convert the type of the pointer to a pointer to the stored type.
2239 Value *BC =
2240 Builder.CreateBitCast(Ptr, PointerType::getUnqual(VTy), "cast");
2241 LoadInst *LI = Builder.CreateAlignedLoad(BC, VTy->getBitWidth() / 8);
2242 LI->setMetadata(M->getMDKindID("nontemporal"), Node);
2243 Rep = LI;
2244 } else if (IsX86 &&
2245 (Name.startswith("sse2.pavg") || Name.startswith("avx2.pavg") ||
2246 Name.startswith("avx512.mask.pavg"))) {
2247 // llvm.x86.sse2.pavg.b/w, llvm.x86.avx2.pavg.b/w,
2248 // llvm.x86.avx512.mask.pavg.b/w
2249 Value *A = CI->getArgOperand(0);
2250 Value *B = CI->getArgOperand(1);
2251 VectorType *ZextType = VectorType::getExtendedElementVectorType(
2252 cast<VectorType>(A->getType()));
2253 Value *ExtendedA = Builder.CreateZExt(A, ZextType);
2254 Value *ExtendedB = Builder.CreateZExt(B, ZextType);
2255 Value *Sum = Builder.CreateAdd(ExtendedA, ExtendedB);
2256 Value *AddOne = Builder.CreateAdd(Sum, ConstantInt::get(ZextType, 1));
2257 Value *ShiftR = Builder.CreateLShr(AddOne, ConstantInt::get(ZextType, 1));
2258 Rep = Builder.CreateTrunc(ShiftR, A->getType());
2259 if (CI->getNumArgOperands() > 2) {
2260 Rep = EmitX86Select(Builder, CI->getArgOperand(3), Rep,
2261 CI->getArgOperand(2));
2262 }
2263 } else if (IsNVVM && (Name == "abs.i" || Name == "abs.ll")) {
2264 Value *Arg = CI->getArgOperand(0);
2265 Value *Neg = Builder.CreateNeg(Arg, "neg");
2266 Value *Cmp = Builder.CreateICmpSGE(
2267 Arg, llvm::Constant::getNullValue(Arg->getType()), "abs.cond");
2268 Rep = Builder.CreateSelect(Cmp, Arg, Neg, "abs");
2269 } else if (IsNVVM && (Name == "max.i" || Name == "max.ll" ||
2270 Name == "max.ui" || Name == "max.ull")) {
2271 Value *Arg0 = CI->getArgOperand(0);
2272 Value *Arg1 = CI->getArgOperand(1);
2273 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull")
2274 ? Builder.CreateICmpUGE(Arg0, Arg1, "max.cond")
2275 : Builder.CreateICmpSGE(Arg0, Arg1, "max.cond");
2276 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "max");
2277 } else if (IsNVVM && (Name == "min.i" || Name == "min.ll" ||
2278 Name == "min.ui" || Name == "min.ull")) {
2279 Value *Arg0 = CI->getArgOperand(0);
2280 Value *Arg1 = CI->getArgOperand(1);
2281 Value *Cmp = Name.endswith(".ui") || Name.endswith(".ull")
2282 ? Builder.CreateICmpULE(Arg0, Arg1, "min.cond")
2283 : Builder.CreateICmpSLE(Arg0, Arg1, "min.cond");
2284 Rep = Builder.CreateSelect(Cmp, Arg0, Arg1, "min");
2285 } else if (IsNVVM && Name == "clz.ll") {
2286 // llvm.nvvm.clz.ll returns an i32, but llvm.ctlz.i64 and returns an i64.
2287 Value *Arg = CI->getArgOperand(0);
2288 Value *Ctlz = Builder.CreateCall(
2289 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz,
2290 {Arg->getType()}),
2291 {Arg, Builder.getFalse()}, "ctlz");
2292 Rep = Builder.CreateTrunc(Ctlz, Builder.getInt32Ty(), "ctlz.trunc");
2293 } else if (IsNVVM && Name == "popc.ll") {
2294 // llvm.nvvm.popc.ll returns an i32, but llvm.ctpop.i64 and returns an
2295 // i64.
2296 Value *Arg = CI->getArgOperand(0);
2297 Value *Popc = Builder.CreateCall(
2298 Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctpop,
2299 {Arg->getType()}),
2300 Arg, "ctpop");
2301 Rep = Builder.CreateTrunc(Popc, Builder.getInt32Ty(), "ctpop.trunc");
2302 } else if (IsNVVM && Name == "h2f") {
2303 Rep = Builder.CreateCall(Intrinsic::getDeclaration(
2304 F->getParent(), Intrinsic::convert_from_fp16,
2305 {Builder.getFloatTy()}),
2306 CI->getArgOperand(0), "h2f");
2307 } else {
2308 llvm_unreachable("Unknown function for CallInst upgrade.")::llvm::llvm_unreachable_internal("Unknown function for CallInst upgrade."
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2308)
;
2309 }
2310
2311 if (Rep)
2312 CI->replaceAllUsesWith(Rep);
2313 CI->eraseFromParent();
2314 return;
2315 }
2316
2317 const auto &DefaultCase = [&NewFn, &CI]() -> void {
2318 // Handle generic mangling change, but nothing else
2319 assert((static_cast <bool> ((CI->getCalledFunction()->getName
() != NewFn->getName()) && "Unknown function for CallInst upgrade and isn't just a name change"
) ? void (0) : __assert_fail ("(CI->getCalledFunction()->getName() != NewFn->getName()) && \"Unknown function for CallInst upgrade and isn't just a name change\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2321, __extension__ __PRETTY_FUNCTION__))
2320 (CI->getCalledFunction()->getName() != NewFn->getName()) &&(static_cast <bool> ((CI->getCalledFunction()->getName
() != NewFn->getName()) && "Unknown function for CallInst upgrade and isn't just a name change"
) ? void (0) : __assert_fail ("(CI->getCalledFunction()->getName() != NewFn->getName()) && \"Unknown function for CallInst upgrade and isn't just a name change\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2321, __extension__ __PRETTY_FUNCTION__))
2321 "Unknown function for CallInst upgrade and isn't just a name change")(static_cast <bool> ((CI->getCalledFunction()->getName
() != NewFn->getName()) && "Unknown function for CallInst upgrade and isn't just a name change"
) ? void (0) : __assert_fail ("(CI->getCalledFunction()->getName() != NewFn->getName()) && \"Unknown function for CallInst upgrade and isn't just a name change\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2321, __extension__ __PRETTY_FUNCTION__))
;
2322 CI->setCalledFunction(NewFn);
2323 };
2324 CallInst *NewCall = nullptr;
2325 switch (NewFn->getIntrinsicID()) {
2326 default: {
2327 DefaultCase();
2328 return;
2329 }
2330
2331 case Intrinsic::arm_neon_vld1:
2332 case Intrinsic::arm_neon_vld2:
2333 case Intrinsic::arm_neon_vld3:
2334 case Intrinsic::arm_neon_vld4:
2335 case Intrinsic::arm_neon_vld2lane:
2336 case Intrinsic::arm_neon_vld3lane:
2337 case Intrinsic::arm_neon_vld4lane:
2338 case Intrinsic::arm_neon_vst1:
2339 case Intrinsic::arm_neon_vst2:
2340 case Intrinsic::arm_neon_vst3:
2341 case Intrinsic::arm_neon_vst4:
2342 case Intrinsic::arm_neon_vst2lane:
2343 case Intrinsic::arm_neon_vst3lane:
2344 case Intrinsic::arm_neon_vst4lane: {
2345 SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
2346 CI->arg_operands().end());
2347 NewCall = Builder.CreateCall(NewFn, Args);
2348 break;
2349 }
2350
2351 case Intrinsic::bitreverse:
2352 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)});
2353 break;
2354
2355 case Intrinsic::ctlz:
2356 case Intrinsic::cttz:
2357 assert(CI->getNumArgOperands() == 1 &&(static_cast <bool> (CI->getNumArgOperands() == 1 &&
"Mismatch between function args and call args") ? void (0) :
__assert_fail ("CI->getNumArgOperands() == 1 && \"Mismatch between function args and call args\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2358, __extension__ __PRETTY_FUNCTION__))
2358 "Mismatch between function args and call args")(static_cast <bool> (CI->getNumArgOperands() == 1 &&
"Mismatch between function args and call args") ? void (0) :
__assert_fail ("CI->getNumArgOperands() == 1 && \"Mismatch between function args and call args\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2358, __extension__ __PRETTY_FUNCTION__))
;
2359 NewCall =
2360 Builder.CreateCall(NewFn, {CI->getArgOperand(0), Builder.getFalse()});
2361 break;
2362
2363 case Intrinsic::objectsize: {
2364 Value *NullIsUnknownSize = CI->getNumArgOperands() == 2
2365 ? Builder.getFalse()
2366 : CI->getArgOperand(2);
2367 NewCall = Builder.CreateCall(
2368 NewFn, {CI->getArgOperand(0), CI->getArgOperand(1), NullIsUnknownSize});
2369 break;
2370 }
2371
2372 case Intrinsic::ctpop:
2373 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)});
2374 break;
2375
2376 case Intrinsic::convert_from_fp16:
2377 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(0)});
2378 break;
2379
2380 case Intrinsic::dbg_value:
2381 // Upgrade from the old version that had an extra offset argument.
2382 assert(CI->getNumArgOperands() == 4)(static_cast <bool> (CI->getNumArgOperands() == 4) ?
void (0) : __assert_fail ("CI->getNumArgOperands() == 4",
"/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2382, __extension__ __PRETTY_FUNCTION__))
;
2383 // Drop nonzero offsets instead of attempting to upgrade them.
2384 if (auto *Offset = dyn_cast_or_null<Constant>(CI->getArgOperand(1)))
2385 if (Offset->isZeroValue()) {
2386 NewCall = Builder.CreateCall(
2387 NewFn,
2388 {CI->getArgOperand(0), CI->getArgOperand(2), CI->getArgOperand(3)});
2389 break;
2390 }
2391 CI->eraseFromParent();
2392 return;
2393
2394 case Intrinsic::x86_xop_vfrcz_ss:
2395 case Intrinsic::x86_xop_vfrcz_sd:
2396 NewCall = Builder.CreateCall(NewFn, {CI->getArgOperand(1)});
2397 break;
2398
2399 case Intrinsic::x86_xop_vpermil2pd:
2400 case Intrinsic::x86_xop_vpermil2ps:
2401 case Intrinsic::x86_xop_vpermil2pd_256:
2402 case Intrinsic::x86_xop_vpermil2ps_256: {
2403 SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
2404 CI->arg_operands().end());
2405 VectorType *FltIdxTy = cast<VectorType>(Args[2]->getType());
2406 VectorType *IntIdxTy = VectorType::getInteger(FltIdxTy);
2407 Args[2] = Builder.CreateBitCast(Args[2], IntIdxTy);
2408 NewCall = Builder.CreateCall(NewFn, Args);
2409 break;
2410 }
2411
2412 case Intrinsic::x86_sse41_ptestc:
2413 case Intrinsic::x86_sse41_ptestz:
2414 case Intrinsic::x86_sse41_ptestnzc: {
2415 // The arguments for these intrinsics used to be v4f32, and changed
2416 // to v2i64. This is purely a nop, since those are bitwise intrinsics.
2417 // So, the only thing required is a bitcast for both arguments.
2418 // First, check the arguments have the old type.
2419 Value *Arg0 = CI->getArgOperand(0);
2420 if (Arg0->getType() != VectorType::get(Type::getFloatTy(C), 4))
2421 return;
2422
2423 // Old intrinsic, add bitcasts
2424 Value *Arg1 = CI->getArgOperand(1);
2425
2426 Type *NewVecTy = VectorType::get(Type::getInt64Ty(C), 2);
2427
2428 Value *BC0 = Builder.CreateBitCast(Arg0, NewVecTy, "cast");
2429 Value *BC1 = Builder.CreateBitCast(Arg1, NewVecTy, "cast");
2430
2431 NewCall = Builder.CreateCall(NewFn, {BC0, BC1});
2432 break;
2433 }
2434
2435 case Intrinsic::x86_sse41_insertps:
2436 case Intrinsic::x86_sse41_dppd:
2437 case Intrinsic::x86_sse41_dpps:
2438 case Intrinsic::x86_sse41_mpsadbw:
2439 case Intrinsic::x86_avx_dp_ps_256:
2440 case Intrinsic::x86_avx2_mpsadbw: {
2441 // Need to truncate the last argument from i32 to i8 -- this argument models
2442 // an inherently 8-bit immediate operand to these x86 instructions.
2443 SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
2444 CI->arg_operands().end());
2445
2446 // Replace the last argument with a trunc.
2447 Args.back() = Builder.CreateTrunc(Args.back(), Type::getInt8Ty(C), "trunc");
2448 NewCall = Builder.CreateCall(NewFn, Args);
2449 break;
2450 }
2451
2452 case Intrinsic::x86_avx512_mask_cmp_pd_128:
2453 case Intrinsic::x86_avx512_mask_cmp_pd_256:
2454 case Intrinsic::x86_avx512_mask_cmp_pd_512:
2455 case Intrinsic::x86_avx512_mask_cmp_ps_128:
2456 case Intrinsic::x86_avx512_mask_cmp_ps_256:
2457 case Intrinsic::x86_avx512_mask_cmp_ps_512: {
2458 SmallVector<Value *, 4> Args;
2459 Args.push_back(CI->getArgOperand(0));
2460 Args.push_back(CI->getArgOperand(1));
2461 Args.push_back(CI->getArgOperand(2));
2462 if (CI->getNumArgOperands() == 5)
2463 Args.push_back(CI->getArgOperand(4));
2464
2465 NewCall = Builder.CreateCall(NewFn, Args);
2466 unsigned NumElts = Args[0]->getType()->getVectorNumElements();
2467 Value *Res = ApplyX86MaskOn1BitsVec(Builder, NewCall, CI->getArgOperand(3),
2468 NumElts);
2469
2470 std::string Name = CI->getName();
2471 if (!Name.empty()) {
2472 CI->setName(Name + ".old");
2473 NewCall->setName(Name);
2474 }
2475 CI->replaceAllUsesWith(Res);
2476 CI->eraseFromParent();
2477 return;
2478 }
2479
2480 case Intrinsic::thread_pointer: {
2481 NewCall = Builder.CreateCall(NewFn, {});
2482 break;
2483 }
2484
2485 case Intrinsic::invariant_start:
2486 case Intrinsic::invariant_end:
2487 case Intrinsic::masked_load:
2488 case Intrinsic::masked_store:
2489 case Intrinsic::masked_gather:
2490 case Intrinsic::masked_scatter: {
2491 SmallVector<Value *, 4> Args(CI->arg_operands().begin(),
2492 CI->arg_operands().end());
2493 NewCall = Builder.CreateCall(NewFn, Args);
2494 break;
2495 }
2496
2497 case Intrinsic::memcpy:
2498 case Intrinsic::memmove:
2499 case Intrinsic::memset: {
2500 // We have to make sure that the call signature is what we're expecting.
2501 // We only want to change the old signatures by removing the alignment arg:
2502 // @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i32, i1)
2503 // -> @llvm.mem[cpy|move]...(i8*, i8*, i[32|i64], i1)
2504 // @llvm.memset...(i8*, i8, i[32|64], i32, i1)
2505 // -> @llvm.memset...(i8*, i8, i[32|64], i1)
2506 // Note: i8*'s in the above can be any pointer type
2507 if (CI->getNumArgOperands() != 5) {
2508 DefaultCase();
2509 return;
2510 }
2511 // Remove alignment argument (3), and add alignment attributes to the
2512 // dest/src pointers.
2513 Value *Args[4] = {CI->getArgOperand(0), CI->getArgOperand(1),
2514 CI->getArgOperand(2), CI->getArgOperand(4)};
2515 NewCall = Builder.CreateCall(NewFn, Args);
2516 auto *MemCI = cast<MemIntrinsic>(NewCall);
2517 // All mem intrinsics support dest alignment.
2518 const ConstantInt *Align = cast<ConstantInt>(CI->getArgOperand(3));
2519 MemCI->setDestAlignment(Align->getZExtValue());
2520 // Memcpy/Memmove also support source alignment.
2521 if (auto *MTI = dyn_cast<MemTransferInst>(MemCI))
2522 MTI->setSourceAlignment(Align->getZExtValue());
2523 break;
2524 }
2525 }
2526 assert(NewCall && "Should have either set this variable or returned through "(static_cast <bool> (NewCall && "Should have either set this variable or returned through "
"the default case") ? void (0) : __assert_fail ("NewCall && \"Should have either set this variable or returned through \" \"the default case\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2527, __extension__ __PRETTY_FUNCTION__))
2527 "the default case")(static_cast <bool> (NewCall && "Should have either set this variable or returned through "
"the default case") ? void (0) : __assert_fail ("NewCall && \"Should have either set this variable or returned through \" \"the default case\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2527, __extension__ __PRETTY_FUNCTION__))
;
2528 std::string Name = CI->getName();
2529 if (!Name.empty()) {
2530 CI->setName(Name + ".old");
2531 NewCall->setName(Name);
2532 }
2533 CI->replaceAllUsesWith(NewCall);
2534 CI->eraseFromParent();
2535}
2536
2537void llvm::UpgradeCallsToIntrinsic(Function *F) {
2538 assert(F && "Illegal attempt to upgrade a non-existent intrinsic.")(static_cast <bool> (F && "Illegal attempt to upgrade a non-existent intrinsic."
) ? void (0) : __assert_fail ("F && \"Illegal attempt to upgrade a non-existent intrinsic.\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2538, __extension__ __PRETTY_FUNCTION__))
;
2539
2540 // Check if this function should be upgraded and get the replacement function
2541 // if there is one.
2542 Function *NewFn;
2543 if (UpgradeIntrinsicFunction(F, NewFn)) {
2544 // Replace all users of the old function with the new function or new
2545 // instructions. This is not a range loop because the call is deleted.
2546 for (auto UI = F->user_begin(), UE = F->user_end(); UI != UE; )
2547 if (CallInst *CI = dyn_cast<CallInst>(*UI++))
2548 UpgradeIntrinsicCall(CI, NewFn);
2549
2550 // Remove old function, no longer used, from the module.
2551 F->eraseFromParent();
2552 }
2553}
2554
2555MDNode *llvm::UpgradeTBAANode(MDNode &MD) {
2556 // Check if the tag uses struct-path aware TBAA format.
2557 if (isa<MDNode>(MD.getOperand(0)) && MD.getNumOperands() >= 3)
2558 return &MD;
2559
2560 auto &Context = MD.getContext();
2561 if (MD.getNumOperands() == 3) {
2562 Metadata *Elts[] = {MD.getOperand(0), MD.getOperand(1)};
2563 MDNode *ScalarType = MDNode::get(Context, Elts);
2564 // Create a MDNode <ScalarType, ScalarType, offset 0, const>
2565 Metadata *Elts2[] = {ScalarType, ScalarType,
2566 ConstantAsMetadata::get(
2567 Constant::getNullValue(Type::getInt64Ty(Context))),
2568 MD.getOperand(2)};
2569 return MDNode::get(Context, Elts2);
2570 }
2571 // Create a MDNode <MD, MD, offset 0>
2572 Metadata *Elts[] = {&MD, &MD, ConstantAsMetadata::get(Constant::getNullValue(
2573 Type::getInt64Ty(Context)))};
2574 return MDNode::get(Context, Elts);
2575}
2576
2577Instruction *llvm::UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
2578 Instruction *&Temp) {
2579 if (Opc != Instruction::BitCast)
2580 return nullptr;
2581
2582 Temp = nullptr;
2583 Type *SrcTy = V->getType();
2584 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() &&
2585 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) {
2586 LLVMContext &Context = V->getContext();
2587
2588 // We have no information about target data layout, so we assume that
2589 // the maximum pointer size is 64bit.
2590 Type *MidTy = Type::getInt64Ty(Context);
2591 Temp = CastInst::Create(Instruction::PtrToInt, V, MidTy);
2592
2593 return CastInst::Create(Instruction::IntToPtr, Temp, DestTy);
2594 }
2595
2596 return nullptr;
2597}
2598
2599Value *llvm::UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy) {
2600 if (Opc != Instruction::BitCast)
2601 return nullptr;
2602
2603 Type *SrcTy = C->getType();
2604 if (SrcTy->isPtrOrPtrVectorTy() && DestTy->isPtrOrPtrVectorTy() &&
2605 SrcTy->getPointerAddressSpace() != DestTy->getPointerAddressSpace()) {
2606 LLVMContext &Context = C->getContext();
2607
2608 // We have no information about target data layout, so we assume that
2609 // the maximum pointer size is 64bit.
2610 Type *MidTy = Type::getInt64Ty(Context);
2611
2612 return ConstantExpr::getIntToPtr(ConstantExpr::getPtrToInt(C, MidTy),
2613 DestTy);
2614 }
2615
2616 return nullptr;
2617}
2618
2619/// Check the debug info version number, if it is out-dated, drop the debug
2620/// info. Return true if module is modified.
2621bool llvm::UpgradeDebugInfo(Module &M) {
2622 unsigned Version = getDebugMetadataVersionFromModule(M);
2623 if (Version == DEBUG_METADATA_VERSION) {
2624 bool BrokenDebugInfo = false;
2625 if (verifyModule(M, &llvm::errs(), &BrokenDebugInfo))
2626 report_fatal_error("Broken module found, compilation aborted!");
2627 if (!BrokenDebugInfo)
2628 // Everything is ok.
2629 return false;
2630 else {
2631 // Diagnose malformed debug info.
2632 DiagnosticInfoIgnoringInvalidDebugMetadata Diag(M);
2633 M.getContext().diagnose(Diag);
2634 }
2635 }
2636 bool Modified = StripDebugInfo(M);
2637 if (Modified && Version != DEBUG_METADATA_VERSION) {
2638 // Diagnose a version mismatch.
2639 DiagnosticInfoDebugMetadataVersion DiagVersion(M, Version);
2640 M.getContext().diagnose(DiagVersion);
2641 }
2642 return Modified;
2643}
2644
2645bool llvm::UpgradeModuleFlags(Module &M) {
2646 NamedMDNode *ModFlags = M.getModuleFlagsMetadata();
2647 if (!ModFlags)
2648 return false;
2649
2650 bool HasObjCFlag = false, HasClassProperties = false, Changed = false;
2651 for (unsigned I = 0, E = ModFlags->getNumOperands(); I != E; ++I) {
2652 MDNode *Op = ModFlags->getOperand(I);
2653 if (Op->getNumOperands() != 3)
2654 continue;
2655 MDString *ID = dyn_cast_or_null<MDString>(Op->getOperand(1));
2656 if (!ID)
2657 continue;
2658 if (ID->getString() == "Objective-C Image Info Version")
2659 HasObjCFlag = true;
2660 if (ID->getString() == "Objective-C Class Properties")
2661 HasClassProperties = true;
2662 // Upgrade PIC/PIE Module Flags. The module flag behavior for these two
2663 // field was Error and now they are Max.
2664 if (ID->getString() == "PIC Level" || ID->getString() == "PIE Level") {
2665 if (auto *Behavior =
2666 mdconst::dyn_extract_or_null<ConstantInt>(Op->getOperand(0))) {
2667 if (Behavior->getLimitedValue() == Module::Error) {
2668 Type *Int32Ty = Type::getInt32Ty(M.getContext());
2669 Metadata *Ops[3] = {
2670 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, Module::Max)),
2671 MDString::get(M.getContext(), ID->getString()),
2672 Op->getOperand(2)};
2673 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops));
2674 Changed = true;
2675 }
2676 }
2677 }
2678 // Upgrade Objective-C Image Info Section. Removed the whitespce in the
2679 // section name so that llvm-lto will not complain about mismatching
2680 // module flags that is functionally the same.
2681 if (ID->getString() == "Objective-C Image Info Section") {
2682 if (auto *Value = dyn_cast_or_null<MDString>(Op->getOperand(2))) {
2683 SmallVector<StringRef, 4> ValueComp;
2684 Value->getString().split(ValueComp, " ");
2685 if (ValueComp.size() != 1) {
2686 std::string NewValue;
2687 for (auto &S : ValueComp)
2688 NewValue += S.str();
2689 Metadata *Ops[3] = {Op->getOperand(0), Op->getOperand(1),
2690 MDString::get(M.getContext(), NewValue)};
2691 ModFlags->setOperand(I, MDNode::get(M.getContext(), Ops));
2692 Changed = true;
2693 }
2694 }
2695 }
2696 }
2697
2698 // "Objective-C Class Properties" is recently added for Objective-C. We
2699 // upgrade ObjC bitcodes to contain a "Objective-C Class Properties" module
2700 // flag of value 0, so we can correclty downgrade this flag when trying to
2701 // link an ObjC bitcode without this module flag with an ObjC bitcode with
2702 // this module flag.
2703 if (HasObjCFlag && !HasClassProperties) {
2704 M.addModuleFlag(llvm::Module::Override, "Objective-C Class Properties",
2705 (uint32_t)0);
2706 Changed = true;
2707 }
2708
2709 return Changed;
2710}
2711
2712void llvm::UpgradeSectionAttributes(Module &M) {
2713 auto TrimSpaces = [](StringRef Section) -> std::string {
2714 SmallVector<StringRef, 5> Components;
2715 Section.split(Components, ',');
2716
2717 SmallString<32> Buffer;
2718 raw_svector_ostream OS(Buffer);
2719
2720 for (auto Component : Components)
2721 OS << ',' << Component.trim();
2722
2723 return OS.str().substr(1);
2724 };
2725
2726 for (auto &GV : M.globals()) {
2727 if (!GV.hasSection())
2728 continue;
2729
2730 StringRef Section = GV.getSection();
2731
2732 if (!Section.startswith("__DATA, __objc_catlist"))
2733 continue;
2734
2735 // __DATA, __objc_catlist, regular, no_dead_strip
2736 // __DATA,__objc_catlist,regular,no_dead_strip
2737 GV.setSection(TrimSpaces(Section));
2738 }
2739}
2740
2741static bool isOldLoopArgument(Metadata *MD) {
2742 auto *T = dyn_cast_or_null<MDTuple>(MD);
2743 if (!T)
2744 return false;
2745 if (T->getNumOperands() < 1)
2746 return false;
2747 auto *S = dyn_cast_or_null<MDString>(T->getOperand(0));
2748 if (!S)
2749 return false;
2750 return S->getString().startswith("llvm.vectorizer.");
2751}
2752
2753static MDString *upgradeLoopTag(LLVMContext &C, StringRef OldTag) {
2754 StringRef OldPrefix = "llvm.vectorizer.";
2755 assert(OldTag.startswith(OldPrefix) && "Expected old prefix")(static_cast <bool> (OldTag.startswith(OldPrefix) &&
"Expected old prefix") ? void (0) : __assert_fail ("OldTag.startswith(OldPrefix) && \"Expected old prefix\""
, "/build/llvm-toolchain-snapshot-7~svn325118/lib/IR/AutoUpgrade.cpp"
, 2755, __extension__ __PRETTY_FUNCTION__))
;
2756
2757 if (OldTag == "llvm.vectorizer.unroll")
2758 return MDString::get(C, "llvm.loop.interleave.count");
2759
2760 return MDString::get(
2761 C, (Twine("llvm.loop.vectorize.") + OldTag.drop_front(OldPrefix.size()))
2762 .str());
2763}
2764
2765static Metadata *upgradeLoopArgument(Metadata *MD) {
2766 auto *T = dyn_cast_or_null<MDTuple>(MD);
2767 if (!T)
2768 return MD;
2769 if (T->getNumOperands() < 1)
2770 return MD;
2771 auto *OldTag = dyn_cast_or_null<MDString>(T->getOperand(0));
2772 if (!OldTag)
2773 return MD;
2774 if (!OldTag->getString().startswith("llvm.vectorizer."))
2775 return MD;
2776
2777 // This has an old tag. Upgrade it.
2778 SmallVector<Metadata *, 8> Ops;
2779 Ops.reserve(T->getNumOperands());
2780 Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString()));
2781 for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I)
2782 Ops.push_back(T->getOperand(I));
2783
2784 return MDTuple::get(T->getContext(), Ops);
2785}
2786
2787MDNode *llvm::upgradeInstructionLoopAttachment(MDNode &N) {
2788 auto *T = dyn_cast<MDTuple>(&N);
2789 if (!T)
2790 return &N;
2791
2792 if (none_of(T->operands(), isOldLoopArgument))
2793 return &N;
2794
2795 SmallVector<Metadata *, 8> Ops;
2796 Ops.reserve(T->getNumOperands());
2797 for (Metadata *MD : T->operands())
2798 Ops.push_back(upgradeLoopArgument(MD));
2799
2800 return MDTuple::get(T->getContext(), Ops);
2801}