/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp

Bug Summary

File:	lib/CodeGen/CodeGenPrepare.cpp
Warning:	line 5826, column 3 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name CodeGenPrepare.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn373517/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn373517=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-02-234743-9763-1 -x c++ /build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp

/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp

→

1//===- CodeGenPrepare.cpp - Prepare a function for code generation --------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass munges the code in the input function to better prepare it for
10// SelectionDAG-based code generation. This works around limitations in it's
11// basic-block-at-a-time approach. It should eventually be removed.
12//
13//===----------------------------------------------------------------------===//

15#include "llvm/ADT/APInt.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/DenseMap.h"
18#include "llvm/ADT/MapVector.h"
19#include "llvm/ADT/PointerIntPair.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallPtrSet.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/ADT/Statistic.h"
24#include "llvm/Analysis/BlockFrequencyInfo.h"
25#include "llvm/Analysis/BranchProbabilityInfo.h"
26#include "llvm/Analysis/ConstantFolding.h"
27#include "llvm/Analysis/InstructionSimplify.h"
28#include "llvm/Analysis/LoopInfo.h"
29#include "llvm/Analysis/MemoryBuiltins.h"
30#include "llvm/Analysis/ProfileSummaryInfo.h"
31#include "llvm/Analysis/TargetLibraryInfo.h"
32#include "llvm/Analysis/TargetTransformInfo.h"
33#include "llvm/Transforms/Utils/Local.h"
34#include "llvm/Analysis/ValueTracking.h"
35#include "llvm/Analysis/VectorUtils.h"
36#include "llvm/CodeGen/Analysis.h"
37#include "llvm/CodeGen/ISDOpcodes.h"
38#include "llvm/CodeGen/SelectionDAGNodes.h"
39#include "llvm/CodeGen/TargetLowering.h"
40#include "llvm/CodeGen/TargetPassConfig.h"
41#include "llvm/CodeGen/TargetSubtargetInfo.h"
42#include "llvm/CodeGen/ValueTypes.h"
43#include "llvm/Config/llvm-config.h"
44#include "llvm/IR/Argument.h"
45#include "llvm/IR/Attributes.h"
46#include "llvm/IR/BasicBlock.h"
47#include "llvm/IR/CallSite.h"
48#include "llvm/IR/Constant.h"
49#include "llvm/IR/Constants.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DerivedTypes.h"
52#include "llvm/IR/Dominators.h"
53#include "llvm/IR/Function.h"
54#include "llvm/IR/GetElementPtrTypeIterator.h"
55#include "llvm/IR/GlobalValue.h"
56#include "llvm/IR/GlobalVariable.h"
57#include "llvm/IR/IRBuilder.h"
58#include "llvm/IR/InlineAsm.h"
59#include "llvm/IR/InstrTypes.h"
60#include "llvm/IR/Instruction.h"
61#include "llvm/IR/Instructions.h"
62#include "llvm/IR/IntrinsicInst.h"
63#include "llvm/IR/Intrinsics.h"
64#include "llvm/IR/LLVMContext.h"
65#include "llvm/IR/MDBuilder.h"
66#include "llvm/IR/Module.h"
67#include "llvm/IR/Operator.h"
68#include "llvm/IR/PatternMatch.h"
69#include "llvm/IR/Statepoint.h"
70#include "llvm/IR/Type.h"
71#include "llvm/IR/Use.h"
72#include "llvm/IR/User.h"
73#include "llvm/IR/Value.h"
74#include "llvm/IR/ValueHandle.h"
75#include "llvm/IR/ValueMap.h"
76#include "llvm/Pass.h"
77#include "llvm/Support/BlockFrequency.h"
78#include "llvm/Support/BranchProbability.h"
79#include "llvm/Support/Casting.h"
80#include "llvm/Support/CommandLine.h"
81#include "llvm/Support/Compiler.h"
82#include "llvm/Support/Debug.h"
83#include "llvm/Support/ErrorHandling.h"
84#include "llvm/Support/MachineValueType.h"
85#include "llvm/Support/MathExtras.h"
86#include "llvm/Support/raw_ostream.h"
87#include "llvm/Target/TargetMachine.h"
88#include "llvm/Target/TargetOptions.h"
89#include "llvm/Transforms/Utils/BasicBlockUtils.h"
90#include "llvm/Transforms/Utils/BypassSlowDivision.h"
91#include "llvm/Transforms/Utils/SimplifyLibCalls.h"
92#include <algorithm>
93#include <cassert>
94#include <cstdint>
95#include <iterator>
96#include <limits>
97#include <memory>
98#include <utility>
99#include <vector>

101using namespace llvm;
102using namespace llvm::PatternMatch;

104#define DEBUG_TYPE"codegenprepare" "codegenprepare"

106STATISTIC(NumBlocksElim, "Number of blocks eliminated")static llvm::Statistic NumBlocksElim = {"codegenprepare", "NumBlocksElim"
, "Number of blocks eliminated", {0}, {false}};
107STATISTIC(NumPHIsElim,   "Number of trivial PHIs eliminated")static llvm::Statistic NumPHIsElim = {"codegenprepare", "NumPHIsElim"
, "Number of trivial PHIs eliminated", {0}, {false}};
108STATISTIC(NumGEPsElim,   "Number of GEPs converted to casts")static llvm::Statistic NumGEPsElim = {"codegenprepare", "NumGEPsElim"
, "Number of GEPs converted to casts", {0}, {false}};
109STATISTIC(NumCmpUses, "Number of uses of Cmp expressions replaced with uses of "static llvm::Statistic NumCmpUses = {"codegenprepare", "NumCmpUses"
, "Number of uses of Cmp expressions replaced with uses of " "sunken Cmps"
, {0}, {false}}
                    "sunken Cmps")static llvm::Statistic NumCmpUses = {"codegenprepare", "NumCmpUses"
, "Number of uses of Cmp expressions replaced with uses of " "sunken Cmps"
, {0}, {false}};
111STATISTIC(NumCastUses, "Number of uses of Cast expressions replaced with uses "static llvm::Statistic NumCastUses = {"codegenprepare", "NumCastUses"
, "Number of uses of Cast expressions replaced with uses " "of sunken Casts"
, {0}, {false}}
                     "of sunken Casts")static llvm::Statistic NumCastUses = {"codegenprepare", "NumCastUses"
, "Number of uses of Cast expressions replaced with uses " "of sunken Casts"
, {0}, {false}};
113STATISTIC(NumMemoryInsts, "Number of memory instructions whose address "static llvm::Statistic NumMemoryInsts = {"codegenprepare", "NumMemoryInsts"
, "Number of memory instructions whose address " "computations were sunk"
, {0}, {false}}
                        "computations were sunk")static llvm::Statistic NumMemoryInsts = {"codegenprepare", "NumMemoryInsts"
, "Number of memory instructions whose address " "computations were sunk"
, {0}, {false}};
115STATISTIC(NumMemoryInstsPhiCreated,static llvm::Statistic NumMemoryInstsPhiCreated = {"codegenprepare"
, "NumMemoryInstsPhiCreated", "Number of phis created when address "
 "computations were sunk to memory instructions", {0}, {false
}}
        "Number of phis created when address "static llvm::Statistic NumMemoryInstsPhiCreated = {"codegenprepare"
, "NumMemoryInstsPhiCreated", "Number of phis created when address "
 "computations were sunk to memory instructions", {0}, {false
}}
        "computations were sunk to memory instructions")static llvm::Statistic NumMemoryInstsPhiCreated = {"codegenprepare"
, "NumMemoryInstsPhiCreated", "Number of phis created when address "
 "computations were sunk to memory instructions", {0}, {false
}};
118STATISTIC(NumMemoryInstsSelectCreated,static llvm::Statistic NumMemoryInstsSelectCreated = {"codegenprepare"
, "NumMemoryInstsSelectCreated", "Number of select created when address "
 "computations were sunk to memory instructions", {0}, {false
}}
        "Number of select created when address "static llvm::Statistic NumMemoryInstsSelectCreated = {"codegenprepare"
, "NumMemoryInstsSelectCreated", "Number of select created when address "
 "computations were sunk to memory instructions", {0}, {false
}}
        "computations were sunk to memory instructions")static llvm::Statistic NumMemoryInstsSelectCreated = {"codegenprepare"
, "NumMemoryInstsSelectCreated", "Number of select created when address "
 "computations were sunk to memory instructions", {0}, {false
}};
121STATISTIC(NumExtsMoved,  "Number of [s|z]ext instructions combined with loads")static llvm::Statistic NumExtsMoved = {"codegenprepare", "NumExtsMoved"
, "Number of [s|z]ext instructions combined with loads", {0},
 {false}};
122STATISTIC(NumExtUses,    "Number of uses of [s|z]ext instructions optimized")static llvm::Statistic NumExtUses = {"codegenprepare", "NumExtUses"
, "Number of uses of [s|z]ext instructions optimized", {0}, {
false}};
123STATISTIC(NumAndsAdded,static llvm::Statistic NumAndsAdded = {"codegenprepare", "NumAndsAdded"
, "Number of and mask instructions added to form ext loads", {
0}, {false}}
        "Number of and mask instructions added to form ext loads")static llvm::Statistic NumAndsAdded = {"codegenprepare", "NumAndsAdded"
, "Number of and mask instructions added to form ext loads", {
0}, {false}};
125STATISTIC(NumAndUses, "Number of uses of and mask instructions optimized")static llvm::Statistic NumAndUses = {"codegenprepare", "NumAndUses"
, "Number of uses of and mask instructions optimized", {0}, {
false}};
126STATISTIC(NumRetsDup,    "Number of return instructions duplicated")static llvm::Statistic NumRetsDup = {"codegenprepare", "NumRetsDup"
, "Number of return instructions duplicated", {0}, {false}};
127STATISTIC(NumDbgValueMoved, "Number of debug value instructions moved")static llvm::Statistic NumDbgValueMoved = {"codegenprepare", "NumDbgValueMoved"
, "Number of debug value instructions moved", {0}, {false}};
128STATISTIC(NumSelectsExpanded, "Number of selects turned into branches")static llvm::Statistic NumSelectsExpanded = {"codegenprepare"
, "NumSelectsExpanded", "Number of selects turned into branches"
, {0}, {false}};
129STATISTIC(NumStoreExtractExposed, "Number of store(extractelement) exposed")static llvm::Statistic NumStoreExtractExposed = {"codegenprepare"
, "NumStoreExtractExposed", "Number of store(extractelement) exposed"
, {0}, {false}};

131static cl::opt<bool> DisableBranchOpts(
"disable-cgp-branch-opts", cl::Hidden, cl::init(false),
cl::desc("Disable branch optimizations in CodeGenPrepare"));

135static cl::opt<bool>
  DisableGCOpts("disable-cgp-gc-opts", cl::Hidden, cl::init(false),
                cl::desc("Disable GC optimizations in CodeGenPrepare"));

139static cl::opt<bool> DisableSelectToBranch(
"disable-cgp-select2branch", cl::Hidden, cl::init(false),
cl::desc("Disable select to branch conversion."));

143static cl::opt<bool> AddrSinkUsingGEPs(
"addr-sink-using-gep", cl::Hidden, cl::init(true),
cl::desc("Address sinking in CGP using GEPs."));

147static cl::opt<bool> EnableAndCmpSinking(
 "enable-andcmp-sinking", cl::Hidden, cl::init(true),
 cl::desc("Enable sinkinig and/cmp into branches."));

151static cl::opt<bool> DisableStoreExtract(
  "disable-cgp-store-extract", cl::Hidden, cl::init(false),
  cl::desc("Disable store(extract) optimizations in CodeGenPrepare"));

155static cl::opt<bool> StressStoreExtract(
  "stress-cgp-store-extract", cl::Hidden, cl::init(false),
  cl::desc("Stress test store(extract) optimizations in CodeGenPrepare"));

159static cl::opt<bool> DisableExtLdPromotion(
  "disable-cgp-ext-ld-promotion", cl::Hidden, cl::init(false),
  cl::desc("Disable ext(promotable(ld)) -> promoted(ext(ld)) optimization in "
           "CodeGenPrepare"));

164static cl::opt<bool> StressExtLdPromotion(
  "stress-cgp-ext-ld-promotion", cl::Hidden, cl::init(false),
  cl::desc("Stress test ext(promotable(ld)) -> promoted(ext(ld)) "
           "optimization in CodeGenPrepare"));

169static cl::opt<bool> DisablePreheaderProtect(
  "disable-preheader-prot", cl::Hidden, cl::init(false),
  cl::desc("Disable protection against removing loop preheaders"));

173static cl::opt<bool> ProfileGuidedSectionPrefix(
  "profile-guided-section-prefix", cl::Hidden, cl::init(true), cl::ZeroOrMore,
  cl::desc("Use profile info to add section prefix for hot/cold functions"));

177static cl::opt<unsigned> FreqRatioToSkipMerge(
  "cgp-freq-ratio-to-skip-merge", cl::Hidden, cl::init(2),
  cl::desc("Skip merging empty blocks if (frequency of empty block) / "
           "(frequency of destination block) is greater than this ratio"));

182static cl::opt<bool> ForceSplitStore(
  "force-split-store", cl::Hidden, cl::init(false),
  cl::desc("Force store splitting no matter what the target query says."));

186static cl::opt<bool>
187EnableTypePromotionMerge("cgp-type-promotion-merge", cl::Hidden,
  cl::desc("Enable merging of redundant sexts when one is dominating"
  " the other."), cl::init(true));

191static cl::opt<bool> DisableComplexAddrModes(
  "disable-complex-addr-modes", cl::Hidden, cl::init(false),
  cl::desc("Disables combining addressing modes with different parts "
           "in optimizeMemoryInst."));

196static cl::opt<bool>
197AddrSinkNewPhis("addr-sink-new-phis", cl::Hidden, cl::init(false),
              cl::desc("Allow creation of Phis in Address sinking."));

200static cl::opt<bool>
201AddrSinkNewSelects("addr-sink-new-select", cl::Hidden, cl::init(true),
                 cl::desc("Allow creation of selects in Address sinking."));

204static cl::opt<bool> AddrSinkCombineBaseReg(
  "addr-sink-combine-base-reg", cl::Hidden, cl::init(true),
  cl::desc("Allow combining of BaseReg field in Address sinking."));

208static cl::opt<bool> AddrSinkCombineBaseGV(
  "addr-sink-combine-base-gv", cl::Hidden, cl::init(true),
  cl::desc("Allow combining of BaseGV field in Address sinking."));

212static cl::opt<bool> AddrSinkCombineBaseOffs(
  "addr-sink-combine-base-offs", cl::Hidden, cl::init(true),
  cl::desc("Allow combining of BaseOffs field in Address sinking."));

216static cl::opt<bool> AddrSinkCombineScaledReg(
  "addr-sink-combine-scaled-reg", cl::Hidden, cl::init(true),
  cl::desc("Allow combining of ScaledReg field in Address sinking."));

220static cl::opt<bool>
  EnableGEPOffsetSplit("cgp-split-large-offset-gep", cl::Hidden,
                       cl::init(true),
                       cl::desc("Enable splitting large offset of GEP."));

225namespace {

227enum ExtType {
ZeroExtension,   // Zero extension has been seen.
SignExtension,   // Sign extension has been seen.
BothExtension    // This extension type is used if we saw sext after
                 // ZeroExtension had been set, or if we saw zext after
                 // SignExtension had been set. It makes the type
                 // information of a promoted instruction invalid.
234};

236using SetOfInstrs = SmallPtrSet<Instruction *, 16>;
237using TypeIsSExt = PointerIntPair<Type *, 2, ExtType>;
238using InstrToOrigTy = DenseMap<Instruction *, TypeIsSExt>;
239using SExts = SmallVector<Instruction *, 16>;
240using ValueToSExts = DenseMap<Value *, SExts>;

242class TypePromotionTransaction;

class CodeGenPrepare : public FunctionPass {
  const TargetMachine *TM = nullptr;
  const TargetSubtargetInfo *SubtargetInfo;
  const TargetLowering *TLI = nullptr;
  const TargetRegisterInfo *TRI;
  const TargetTransformInfo *TTI = nullptr;
  const TargetLibraryInfo *TLInfo;
  const LoopInfo *LI;
  std::unique_ptr<BlockFrequencyInfo> BFI;
  std::unique_ptr<BranchProbabilityInfo> BPI;

  /// As we scan instructions optimizing them, this is the next instruction
  /// to optimize. Transforms that can invalidate this should update it.
  BasicBlock::iterator CurInstIterator;

  /// Keeps track of non-local addresses that have been sunk into a block.
  /// This allows us to avoid inserting duplicate code for blocks with
  /// multiple load/stores of the same address. The usage of WeakTrackingVH
  /// enables SunkAddrs to be treated as a cache whose entries can be
  /// invalidated if a sunken address computation has been erased.
  ValueMap<Value*, WeakTrackingVH> SunkAddrs;

  /// Keeps track of all instructions inserted for the current function.
  SetOfInstrs InsertedInsts;

  /// Keeps track of the type of the related instruction before their
  /// promotion for the current function.
  InstrToOrigTy PromotedInsts;

  /// Keep track of instructions removed during promotion.
  SetOfInstrs RemovedInsts;

  /// Keep track of sext chains based on their initial value.
  DenseMap<Value *, Instruction *> SeenChainsForSExt;

  /// Keep track of GEPs accessing the same data structures such as structs or
  /// arrays that are candidates to be split later because of their large
  /// size.
  MapVector<
      AssertingVH<Value>,
      SmallVector<std::pair<AssertingVH<GetElementPtrInst>, int64_t>, 32>>
      LargeOffsetGEPMap;

  /// Keep track of new GEP base after splitting the GEPs having large offset.
  SmallSet<AssertingVH<Value>, 2> NewGEPBases;

  /// Map serial numbers to Large offset GEPs.
  DenseMap<AssertingVH<GetElementPtrInst>, int> LargeOffsetGEPID;

  /// Keep track of SExt promoted.
  ValueToSExts ValToSExtendedUses;

  /// True if optimizing for size.
  bool OptSize;

  /// DataLayout for the Function being processed.
  const DataLayout *DL = nullptr;

  /// Building the dominator tree can be expensive, so we only build it
  /// lazily and update it when required.
  std::unique_ptr<DominatorTree> DT;

public:
  static char ID; // Pass identification, replacement for typeid

  CodeGenPrepare() : FunctionPass(ID) {
    initializeCodeGenPreparePass(*PassRegistry::getPassRegistry());
  }

  bool runOnFunction(Function &F) override;

  StringRef getPassName() const override { return "CodeGen Prepare"; }

  void getAnalysisUsage(AnalysisUsage &AU) const override {
    // FIXME: When we can selectively preserve passes, preserve the domtree.
    AU.addRequired<ProfileSummaryInfoWrapperPass>();
    AU.addRequired<TargetLibraryInfoWrapperPass>();
    AU.addRequired<TargetTransformInfoWrapperPass>();
    AU.addRequired<LoopInfoWrapperPass>();
  }

private:
  template <typename F>
  void resetIteratorIfInvalidatedWhileCalling(BasicBlock *BB, F f) {
    // Substituting can cause recursive simplifications, which can invalidate
    // our iterator.  Use a WeakTrackingVH to hold onto it in case this
    // happens.
    Value *CurValue = &*CurInstIterator;
    WeakTrackingVH IterHandle(CurValue);

    f();

    // If the iterator instruction was recursively deleted, start over at the
    // start of the block.
    if (IterHandle != CurValue) {
      CurInstIterator = BB->begin();
      SunkAddrs.clear();
    }
  }

  // Get the DominatorTree, building if necessary.
  DominatorTree &getDT(Function &F) {
    if (!DT)
      DT = std::make_unique<DominatorTree>(F);
    return *DT;
  }

  bool eliminateFallThrough(Function &F);
  bool eliminateMostlyEmptyBlocks(Function &F);
  BasicBlock *findDestBlockOfMergeableEmptyBlock(BasicBlock *BB);
  bool canMergeBlocks(const BasicBlock *BB, const BasicBlock *DestBB) const;
  void eliminateMostlyEmptyBlock(BasicBlock *BB);
  bool isMergingEmptyBlockProfitable(BasicBlock *BB, BasicBlock *DestBB,
                                     bool isPreheader);
  bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT);
  bool optimizeInst(Instruction *I, bool &ModifiedDT);
  bool optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
                          Type *AccessTy, unsigned AddrSpace);
  bool optimizeInlineAsmInst(CallInst *CS);
  bool optimizeCallInst(CallInst *CI, bool &ModifiedDT);
  bool optimizeExt(Instruction *&I);
  bool optimizeExtUses(Instruction *I);
  bool optimizeLoadExt(LoadInst *Load);
  bool optimizeShiftInst(BinaryOperator *BO);
  bool optimizeSelectInst(SelectInst *SI);
  bool optimizeShuffleVectorInst(ShuffleVectorInst *SVI);
  bool optimizeSwitchInst(SwitchInst *SI);
  bool optimizeExtractElementInst(Instruction *Inst);
  bool dupRetToEnableTailCallOpts(BasicBlock *BB, bool &ModifiedDT);
  bool placeDbgValues(Function &F);
  bool canFormExtLd(const SmallVectorImpl<Instruction *> &MovedExts,
                    LoadInst *&LI, Instruction *&Inst, bool HasPromoted);
  bool tryToPromoteExts(TypePromotionTransaction &TPT,
                        const SmallVectorImpl<Instruction *> &Exts,
                        SmallVectorImpl<Instruction *> &ProfitablyMovedExts,
                        unsigned CreatedInstsCost = 0);
  bool mergeSExts(Function &F);
  bool splitLargeGEPOffsets();
  bool performAddressTypePromotion(
      Instruction *&Inst,
      bool AllowPromotionWithoutCommonHeader,
      bool HasPromoted, TypePromotionTransaction &TPT,
      SmallVectorImpl<Instruction *> &SpeculativelyMovedExts);
  bool splitBranchCondition(Function &F, bool &ModifiedDT);
  bool simplifyOffsetableRelocate(Instruction &I);

  bool tryToSinkFreeOperands(Instruction *I);
  bool replaceMathCmpWithIntrinsic(BinaryOperator *BO, CmpInst *Cmp,
                                   Intrinsic::ID IID);
  bool optimizeCmp(CmpInst *Cmp, bool &ModifiedDT);
  bool combineToUSubWithOverflow(CmpInst *Cmp, bool &ModifiedDT);
  bool combineToUAddWithOverflow(CmpInst *Cmp, bool &ModifiedDT);
};

398} // end anonymous namespace

400char CodeGenPrepare::ID = 0;

402INITIALIZE_PASS_BEGIN(CodeGenPrepare, DEBUG_TYPE,static void *initializeCodeGenPreparePassOnce(PassRegistry &
Registry) {
                    "Optimize for code generation", false, false)static void *initializeCodeGenPreparePassOnce(PassRegistry &
Registry) {
404INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)initializeProfileSummaryInfoWrapperPassPass(Registry);
405INITIALIZE_PASS_END(CodeGenPrepare, DEBUG_TYPE,PassInfo *PI = new PassInfo( "Optimize for code generation", "codegenprepare"
, &CodeGenPrepare::ID, PassInfo::NormalCtor_t(callDefaultCtor
<CodeGenPrepare>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeCodeGenPreparePassFlag
; void llvm::initializeCodeGenPreparePass(PassRegistry &Registry
) { llvm::call_once(InitializeCodeGenPreparePassFlag, initializeCodeGenPreparePassOnce
, std::ref(Registry)); }
                  "Optimize for code generation", false, false)PassInfo *PI = new PassInfo( "Optimize for code generation", "codegenprepare"
, &CodeGenPrepare::ID, PassInfo::NormalCtor_t(callDefaultCtor
<CodeGenPrepare>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeCodeGenPreparePassFlag
; void llvm::initializeCodeGenPreparePass(PassRegistry &Registry
) { llvm::call_once(InitializeCodeGenPreparePassFlag, initializeCodeGenPreparePassOnce
, std::ref(Registry)); }

408FunctionPass *llvm::createCodeGenPreparePass() { return new CodeGenPrepare(); }

410bool CodeGenPrepare::runOnFunction(Function &F) {
if (skipFunction(F))
1
Assuming the condition is false→
2
←
Taking false branch→
  return false;

DL = &F.getParent()->getDataLayout();

bool EverMadeChange = false;
// Clear per function information.
InsertedInsts.clear();
PromotedInsts.clear();

if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>()) {
3
←
Assuming 'TPC' is null→
4
←
Taking false branch→
  TM = &TPC->getTM<TargetMachine>();
  SubtargetInfo = TM->getSubtargetImpl(F);
  TLI = SubtargetInfo->getTargetLowering();
  TRI = SubtargetInfo->getRegisterInfo();
}
TLInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
BPI.reset(new BranchProbabilityInfo(F, *LI));
BFI.reset(new BlockFrequencyInfo(F, *BPI, *LI));
OptSize = F.hasOptSize();

ProfileSummaryInfo *PSI =
    &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
if (ProfileGuidedSectionPrefix) {
5
←
Assuming the condition is false→
6
←
Taking false branch→
  if (PSI->isFunctionHotInCallGraph(&F, *BFI))
    F.setSectionPrefix(".hot");
  else if (PSI->isFunctionColdInCallGraph(&F, *BFI))
    F.setSectionPrefix(".unlikely");
}

/// This optimization identifies DIV instructions that can be
/// profitably bypassed and carried out with a shorter, faster divide.
if (!OptSize && !PSI->hasHugeWorkingSetSize() && TLI &&
7
←
Assuming field 'OptSize' is true→
    TLI->isSlowDivBypassed()) {
  const DenseMap<unsigned int, unsigned int> &BypassWidths =
     TLI->getBypassSlowDivWidths();
  BasicBlock* BB = &*F.begin();
  while (BB != nullptr) {
    // bypassSlowDivision may create new BBs, but we don't want to reapply the
    // optimization to those blocks.
    BasicBlock* Next = BB->getNextNode();
    EverMadeChange |= bypassSlowDivision(BB, BypassWidths);
    BB = Next;
  }
}

// Eliminate blocks that contain only PHI nodes and an
// unconditional branch.
EverMadeChange |= eliminateMostlyEmptyBlocks(F);

bool ModifiedDT = false;
if (!DisableBranchOpts)
8
←
Assuming the condition is false→
9
←
Taking false branch→
  EverMadeChange |= splitBranchCondition(F, ModifiedDT);

// Split some critical edges where one of the sources is an indirect branch,
// to help generate sane code for PHIs involving such edges.
EverMadeChange |= SplitIndirectBrCriticalEdges(F);

bool MadeChange = true;
while (MadeChange) {
10
←
Loop condition is true.  Entering loop body→
  MadeChange = false;
  DT.reset();
  for (Function::iterator I = F.begin(); I != F.end(); ) {
11
←
Loop condition is true.  Entering loop body→
    BasicBlock *BB = &*I++;
    bool ModifiedDTOnIteration = false;
    MadeChange |= optimizeBlock(*BB, ModifiedDTOnIteration);
12
←
Calling 'CodeGenPrepare::optimizeBlock'→

    // Restart BB iteration if the dominator tree of the Function was changed
    if (ModifiedDTOnIteration)
      break;
  }
  if (EnableTypePromotionMerge && !ValToSExtendedUses.empty())
    MadeChange |= mergeSExts(F);
  if (!LargeOffsetGEPMap.empty())
    MadeChange |= splitLargeGEPOffsets();

  // Really free removed instructions during promotion.
  for (Instruction *I : RemovedInsts)
    I->deleteValue();

  EverMadeChange |= MadeChange;
  SeenChainsForSExt.clear();
  ValToSExtendedUses.clear();
  RemovedInsts.clear();
  LargeOffsetGEPMap.clear();
  LargeOffsetGEPID.clear();
}

SunkAddrs.clear();

if (!DisableBranchOpts) {
  MadeChange = false;
  // Use a set vector to get deterministic iteration order. The order the
  // blocks are removed may affect whether or not PHI nodes in successors
  // are removed.
  SmallSetVector<BasicBlock*, 8> WorkList;
  for (BasicBlock &BB : F) {
    SmallVector<BasicBlock *, 2> Successors(succ_begin(&BB), succ_end(&BB));
    MadeChange |= ConstantFoldTerminator(&BB, true);
    if (!MadeChange) continue;

    for (SmallVectorImpl<BasicBlock*>::iterator
           II = Successors.begin(), IE = Successors.end(); II != IE; ++II)
      if (pred_begin(*II) == pred_end(*II))
        WorkList.insert(*II);
  }

  // Delete the dead blocks and any of their dead successors.
  MadeChange |= !WorkList.empty();
  while (!WorkList.empty()) {
    BasicBlock *BB = WorkList.pop_back_val();
    SmallVector<BasicBlock*, 2> Successors(succ_begin(BB), succ_end(BB));

    DeleteDeadBlock(BB);

    for (SmallVectorImpl<BasicBlock*>::iterator
           II = Successors.begin(), IE = Successors.end(); II != IE; ++II)
      if (pred_begin(*II) == pred_end(*II))
        WorkList.insert(*II);
  }

  // Merge pairs of basic blocks with unconditional branches, connected by
  // a single edge.
  if (EverMadeChange || MadeChange)
    MadeChange |= eliminateFallThrough(F);

  EverMadeChange |= MadeChange;
}

if (!DisableGCOpts) {
  SmallVector<Instruction *, 2> Statepoints;
  for (BasicBlock &BB : F)
    for (Instruction &I : BB)
      if (isStatepoint(I))
        Statepoints.push_back(&I);
  for (auto &I : Statepoints)
    EverMadeChange |= simplifyOffsetableRelocate(*I);
}

// Do this last to clean up use-before-def scenarios introduced by other
// preparatory transforms.
EverMadeChange |= placeDbgValues(F);

return EverMadeChange;
557}

559/// Merge basic blocks which are connected by a single edge, where one of the
560/// basic blocks has a single successor pointing to the other basic block,
561/// which has a single predecessor.
562bool CodeGenPrepare::eliminateFallThrough(Function &F) {
bool Changed = false;
// Scan all of the blocks in the function, except for the entry block.
// Use a temporary array to avoid iterator being invalidated when
// deleting blocks.
SmallVector<WeakTrackingVH, 16> Blocks;
for (auto &Block : llvm::make_range(std::next(F.begin()), F.end()))
  Blocks.push_back(&Block);

for (auto &Block : Blocks) {
  auto *BB = cast_or_null<BasicBlock>(Block);
  if (!BB)
    continue;
  // If the destination block has a single pred, then this is a trivial
  // edge, just collapse it.
  BasicBlock *SinglePred = BB->getSinglePredecessor();

  // Don't merge if BB's address is taken.
  if (!SinglePred || SinglePred == BB || BB->hasAddressTaken()) continue;

  BranchInst *Term = dyn_cast<BranchInst>(SinglePred->getTerminator());
  if (Term && !Term->isConditional()) {
    Changed = true;
    LLVM_DEBUG(dbgs() << "To merge:\n" << *BB << "\n\n\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "To merge:\n" << *
BB << "\n\n\n"; } } while (false);

    // Merge BB into SinglePred and delete it.
    MergeBlockIntoPredecessor(BB);
  }
}
return Changed;
592}

594/// Find a destination block from BB if BB is mergeable empty block.
595BasicBlock *CodeGenPrepare::findDestBlockOfMergeableEmptyBlock(BasicBlock *BB) {
// If this block doesn't end with an uncond branch, ignore it.
BranchInst *BI = dyn_cast<BranchInst>(BB->getTerminator());
if (!BI || !BI->isUnconditional())
  return nullptr;

// If the instruction before the branch (skipping debug info) isn't a phi
// node, then other stuff is happening here.
BasicBlock::iterator BBI = BI->getIterator();
if (BBI != BB->begin()) {
  --BBI;
  while (isa<DbgInfoIntrinsic>(BBI)) {
    if (BBI == BB->begin())
      break;
    --BBI;
  }
  if (!isa<DbgInfoIntrinsic>(BBI) && !isa<PHINode>(BBI))
    return nullptr;
}

// Do not break infinite loops.
BasicBlock *DestBB = BI->getSuccessor(0);
if (DestBB == BB)
  return nullptr;

if (!canMergeBlocks(BB, DestBB))
  DestBB = nullptr;

return DestBB;
624}

626/// Eliminate blocks that contain only PHI nodes, debug info directives, and an
627/// unconditional branch. Passes before isel (e.g. LSR/loopsimplify) often split
628/// edges in ways that are non-optimal for isel. Start by eliminating these
629/// blocks so we can split them the way we want them.
630bool CodeGenPrepare::eliminateMostlyEmptyBlocks(Function &F) {
SmallPtrSet<BasicBlock *, 16> Preheaders;
SmallVector<Loop *, 16> LoopList(LI->begin(), LI->end());
while (!LoopList.empty()) {
  Loop *L = LoopList.pop_back_val();
  LoopList.insert(LoopList.end(), L->begin(), L->end());
  if (BasicBlock *Preheader = L->getLoopPreheader())
    Preheaders.insert(Preheader);
}

bool MadeChange = false;
// Copy blocks into a temporary array to avoid iterator invalidation issues
// as we remove them.
// Note that this intentionally skips the entry block.
SmallVector<WeakTrackingVH, 16> Blocks;
for (auto &Block : llvm::make_range(std::next(F.begin()), F.end()))
  Blocks.push_back(&Block);

for (auto &Block : Blocks) {
  BasicBlock *BB = cast_or_null<BasicBlock>(Block);
  if (!BB)
    continue;
  BasicBlock *DestBB = findDestBlockOfMergeableEmptyBlock(BB);
  if (!DestBB ||
      !isMergingEmptyBlockProfitable(BB, DestBB, Preheaders.count(BB)))
    continue;

  eliminateMostlyEmptyBlock(BB);
  MadeChange = true;
}
return MadeChange;
661}

663bool CodeGenPrepare::isMergingEmptyBlockProfitable(BasicBlock *BB,
                                                 BasicBlock *DestBB,
                                                 bool isPreheader) {
// Do not delete loop preheaders if doing so would create a critical edge.
// Loop preheaders can be good locations to spill registers. If the
// preheader is deleted and we create a critical edge, registers may be
// spilled in the loop body instead.
if (!DisablePreheaderProtect && isPreheader &&
    !(BB->getSinglePredecessor() &&
      BB->getSinglePredecessor()->getSingleSuccessor()))
  return false;

// Skip merging if the block's successor is also a successor to any callbr
// that leads to this block.
// FIXME: Is this really needed? Is this a correctness issue?
for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI) {
  if (auto *CBI = dyn_cast<CallBrInst>((*PI)->getTerminator()))
    for (unsigned i = 0, e = CBI->getNumSuccessors(); i != e; ++i)
      if (DestBB == CBI->getSuccessor(i))
        return false;
}

// Try to skip merging if the unique predecessor of BB is terminated by a
// switch or indirect branch instruction, and BB is used as an incoming block
// of PHIs in DestBB. In such case, merging BB and DestBB would cause ISel to
// add COPY instructions in the predecessor of BB instead of BB (if it is not
// merged). Note that the critical edge created by merging such blocks wont be
// split in MachineSink because the jump table is not analyzable. By keeping
// such empty block (BB), ISel will place COPY instructions in BB, not in the
// predecessor of BB.
BasicBlock *Pred = BB->getUniquePredecessor();
if (!Pred ||
    !(isa<SwitchInst>(Pred->getTerminator()) ||
      isa<IndirectBrInst>(Pred->getTerminator())))
  return true;

if (BB->getTerminator() != BB->getFirstNonPHIOrDbg())
  return true;

// We use a simple cost heuristic which determine skipping merging is
// profitable if the cost of skipping merging is less than the cost of
// merging : Cost(skipping merging) < Cost(merging BB), where the
// Cost(skipping merging) is Freq(BB) * (Cost(Copy) + Cost(Branch)), and
// the Cost(merging BB) is Freq(Pred) * Cost(Copy).
// Assuming Cost(Copy) == Cost(Branch), we could simplify it to :
//   Freq(Pred) / Freq(BB) > 2.
// Note that if there are multiple empty blocks sharing the same incoming
// value for the PHIs in the DestBB, we consider them together. In such
// case, Cost(merging BB) will be the sum of their frequencies.

if (!isa<PHINode>(DestBB->begin()))
  return true;

SmallPtrSet<BasicBlock *, 16> SameIncomingValueBBs;

// Find all other incoming blocks from which incoming values of all PHIs in
// DestBB are the same as the ones from BB.
for (pred_iterator PI = pred_begin(DestBB), E = pred_end(DestBB); PI != E;
     ++PI) {
  BasicBlock *DestBBPred = *PI;
  if (DestBBPred == BB)
    continue;

  if (llvm::all_of(DestBB->phis(), [&](const PHINode &DestPN) {
        return DestPN.getIncomingValueForBlock(BB) ==
               DestPN.getIncomingValueForBlock(DestBBPred);
      }))
    SameIncomingValueBBs.insert(DestBBPred);
}

// See if all BB's incoming values are same as the value from Pred. In this
// case, no reason to skip merging because COPYs are expected to be place in
// Pred already.
if (SameIncomingValueBBs.count(Pred))
  return true;

BlockFrequency PredFreq = BFI->getBlockFreq(Pred);
BlockFrequency BBFreq = BFI->getBlockFreq(BB);

for (auto SameValueBB : SameIncomingValueBBs)
  if (SameValueBB->getUniquePredecessor() == Pred &&
      DestBB == findDestBlockOfMergeableEmptyBlock(SameValueBB))
    BBFreq += BFI->getBlockFreq(SameValueBB);

return PredFreq.getFrequency() <=
       BBFreq.getFrequency() * FreqRatioToSkipMerge;
749}

751/// Return true if we can merge BB into DestBB if there is a single
752/// unconditional branch between them, and BB contains no other non-phi
753/// instructions.
754bool CodeGenPrepare::canMergeBlocks(const BasicBlock *BB,
                                  const BasicBlock *DestBB) const {
// We only want to eliminate blocks whose phi nodes are used by phi nodes in
// the successor.  If there are more complex condition (e.g. preheaders),
// don't mess around with them.
for (const PHINode &PN : BB->phis()) {
  for (const User *U : PN.users()) {
    const Instruction *UI = cast<Instruction>(U);
    if (UI->getParent() != DestBB || !isa<PHINode>(UI))
      return false;
    // If User is inside DestBB block and it is a PHINode then check
    // incoming value. If incoming value is not from BB then this is
    // a complex condition (e.g. preheaders) we want to avoid here.
    if (UI->getParent() == DestBB) {
      if (const PHINode *UPN = dyn_cast<PHINode>(UI))
        for (unsigned I = 0, E = UPN->getNumIncomingValues(); I != E; ++I) {
          Instruction *Insn = dyn_cast<Instruction>(UPN->getIncomingValue(I));
          if (Insn && Insn->getParent() == BB &&
              Insn->getParent() != UPN->getIncomingBlock(I))
            return false;
        }
    }
  }
}

// If BB and DestBB contain any common predecessors, then the phi nodes in BB
// and DestBB may have conflicting incoming values for the block.  If so, we
// can't merge the block.
const PHINode *DestBBPN = dyn_cast<PHINode>(DestBB->begin());
if (!DestBBPN) return true;  // no conflict.

// Collect the preds of BB.
SmallPtrSet<const BasicBlock*, 16> BBPreds;
if (const PHINode *BBPN = dyn_cast<PHINode>(BB->begin())) {
  // It is faster to get preds from a PHI than with pred_iterator.
  for (unsigned i = 0, e = BBPN->getNumIncomingValues(); i != e; ++i)
    BBPreds.insert(BBPN->getIncomingBlock(i));
} else {
  BBPreds.insert(pred_begin(BB), pred_end(BB));
}

// Walk the preds of DestBB.
for (unsigned i = 0, e = DestBBPN->getNumIncomingValues(); i != e; ++i) {
  BasicBlock *Pred = DestBBPN->getIncomingBlock(i);
  if (BBPreds.count(Pred)) {   // Common predecessor?
    for (const PHINode &PN : DestBB->phis()) {
      const Value *V1 = PN.getIncomingValueForBlock(Pred);
      const Value *V2 = PN.getIncomingValueForBlock(BB);

      // If V2 is a phi node in BB, look up what the mapped value will be.
      if (const PHINode *V2PN = dyn_cast<PHINode>(V2))
        if (V2PN->getParent() == BB)
          V2 = V2PN->getIncomingValueForBlock(Pred);

      // If there is a conflict, bail out.
      if (V1 != V2) return false;
    }
  }
}

return true;
815}

817/// Eliminate a basic block that has only phi's and an unconditional branch in
818/// it.
819void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) {
BranchInst *BI = cast<BranchInst>(BB->getTerminator());
BasicBlock *DestBB = BI->getSuccessor(0);

LLVM_DEBUG(dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n"
 << *BB << *DestBB; } } while (false)
                  << *BB << *DestBB)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n"
 << *BB << *DestBB; } } while (false);

// If the destination block has a single pred, then this is a trivial edge,
// just collapse it.
if (BasicBlock *SinglePred = DestBB->getSinglePredecessor()) {
  if (SinglePred != DestBB) {
    assert(SinglePred == BB &&((SinglePred == BB && "Single predecessor not the same as predecessor"
) ? static_cast<void> (0) : __assert_fail ("SinglePred == BB && \"Single predecessor not the same as predecessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 831, __PRETTY_FUNCTION__))
           "Single predecessor not the same as predecessor")((SinglePred == BB && "Single predecessor not the same as predecessor"
) ? static_cast<void> (0) : __assert_fail ("SinglePred == BB && \"Single predecessor not the same as predecessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 831, __PRETTY_FUNCTION__));
    // Merge DestBB into SinglePred/BB and delete it.
    MergeBlockIntoPredecessor(DestBB);
    // Note: BB(=SinglePred) will not be deleted on this path.
    // DestBB(=its single successor) is the one that was deleted.
    LLVM_DEBUG(dbgs() << "AFTER:\n" << *SinglePred << "\n\n\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "AFTER:\n" << *SinglePred
 << "\n\n\n"; } } while (false);
    return;
  }
}

// Otherwise, we have multiple predecessors of BB.  Update the PHIs in DestBB
// to handle the new incoming edges it is about to have.
for (PHINode &PN : DestBB->phis()) {
  // Remove the incoming value for BB, and remember it.
  Value *InVal = PN.removeIncomingValue(BB, false);

  // Two options: either the InVal is a phi node defined in BB or it is some
  // value that dominates BB.
  PHINode *InValPhi = dyn_cast<PHINode>(InVal);
  if (InValPhi && InValPhi->getParent() == BB) {
    // Add all of the input values of the input PHI as inputs of this phi.
    for (unsigned i = 0, e = InValPhi->getNumIncomingValues(); i != e; ++i)
      PN.addIncoming(InValPhi->getIncomingValue(i),
                     InValPhi->getIncomingBlock(i));
  } else {
    // Otherwise, add one instance of the dominating value for each edge that
    // we will be adding.
    if (PHINode *BBPN = dyn_cast<PHINode>(BB->begin())) {
      for (unsigned i = 0, e = BBPN->getNumIncomingValues(); i != e; ++i)
        PN.addIncoming(InVal, BBPN->getIncomingBlock(i));
    } else {
      for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
        PN.addIncoming(InVal, *PI);
    }
  }
}

// The PHIs are now updated, change everything that refers to BB to use
// DestBB and remove BB.
BB->replaceAllUsesWith(DestBB);
BB->eraseFromParent();
++NumBlocksElim;

LLVM_DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "AFTER:\n" << *DestBB
 << "\n\n\n"; } } while (false);
875}

877// Computes a map of base pointer relocation instructions to corresponding
878// derived pointer relocation instructions given a vector of all relocate calls
879static void computeBaseDerivedRelocateMap(
  const SmallVectorImpl<GCRelocateInst *> &AllRelocateCalls,
  DenseMap<GCRelocateInst *, SmallVector<GCRelocateInst *, 2>>
      &RelocateInstMap) {
// Collect information in two maps: one primarily for locating the base object
// while filling the second map; the second map is the final structure holding
// a mapping between Base and corresponding Derived relocate calls
DenseMap<std::pair<unsigned, unsigned>, GCRelocateInst *> RelocateIdxMap;
for (auto *ThisRelocate : AllRelocateCalls) {
  auto K = std::make_pair(ThisRelocate->getBasePtrIndex(),
                          ThisRelocate->getDerivedPtrIndex());
  RelocateIdxMap.insert(std::make_pair(K, ThisRelocate));
}
for (auto &Item : RelocateIdxMap) {
  std::pair<unsigned, unsigned> Key = Item.first;
  if (Key.first == Key.second)
    // Base relocation: nothing to insert
    continue;

  GCRelocateInst *I = Item.second;
  auto BaseKey = std::make_pair(Key.first, Key.first);

  // We're iterating over RelocateIdxMap so we cannot modify it.
  auto MaybeBase = RelocateIdxMap.find(BaseKey);
  if (MaybeBase == RelocateIdxMap.end())
    // TODO: We might want to insert a new base object relocate and gep off
    // that, if there are enough derived object relocates.
    continue;

  RelocateInstMap[MaybeBase->second].push_back(I);
}
910}

912// Accepts a GEP and extracts the operands into a vector provided they're all
913// small integer constants
914static bool getGEPSmallConstantIntOffsetV(GetElementPtrInst *GEP,
                                        SmallVectorImpl<Value *> &OffsetV) {
for (unsigned i = 1; i < GEP->getNumOperands(); i++) {
  // Only accept small constant integer operands
  auto Op = dyn_cast<ConstantInt>(GEP->getOperand(i));
  if (!Op || Op->getZExtValue() > 20)
    return false;
}

for (unsigned i = 1; i < GEP->getNumOperands(); i++)
  OffsetV.push_back(GEP->getOperand(i));
return true;
926}

928// Takes a RelocatedBase (base pointer relocation instruction) and Targets to
929// replace, computes a replacement, and affects it.
930static bool
931simplifyRelocatesOffABase(GCRelocateInst *RelocatedBase,
                        const SmallVectorImpl<GCRelocateInst *> &Targets) {
bool MadeChange = false;
// We must ensure the relocation of derived pointer is defined after
// relocation of base pointer. If we find a relocation corresponding to base
// defined earlier than relocation of base then we move relocation of base
// right before found relocation. We consider only relocation in the same
// basic block as relocation of base. Relocations from other basic block will
// be skipped by optimization and we do not care about them.
for (auto R = RelocatedBase->getParent()->getFirstInsertionPt();
     &*R != RelocatedBase; ++R)
  if (auto RI = dyn_cast<GCRelocateInst>(R))
    if (RI->getStatepoint() == RelocatedBase->getStatepoint())
      if (RI->getBasePtrIndex() == RelocatedBase->getBasePtrIndex()) {
        RelocatedBase->moveBefore(RI);
        break;
      }

for (GCRelocateInst *ToReplace : Targets) {
  assert(ToReplace->getBasePtrIndex() == RelocatedBase->getBasePtrIndex() &&((ToReplace->getBasePtrIndex() == RelocatedBase->getBasePtrIndex
() && "Not relocating a derived object of the original base object"
) ? static_cast<void> (0) : __assert_fail ("ToReplace->getBasePtrIndex() == RelocatedBase->getBasePtrIndex() && \"Not relocating a derived object of the original base object\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 951, __PRETTY_FUNCTION__))
         "Not relocating a derived object of the original base object")((ToReplace->getBasePtrIndex() == RelocatedBase->getBasePtrIndex
() && "Not relocating a derived object of the original base object"
) ? static_cast<void> (0) : __assert_fail ("ToReplace->getBasePtrIndex() == RelocatedBase->getBasePtrIndex() && \"Not relocating a derived object of the original base object\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 951, __PRETTY_FUNCTION__));
  if (ToReplace->getBasePtrIndex() == ToReplace->getDerivedPtrIndex()) {
    // A duplicate relocate call. TODO: coalesce duplicates.
    continue;
  }

  if (RelocatedBase->getParent() != ToReplace->getParent()) {
    // Base and derived relocates are in different basic blocks.
    // In this case transform is only valid when base dominates derived
    // relocate. However it would be too expensive to check dominance
    // for each such relocate, so we skip the whole transformation.
    continue;
  }

  Value *Base = ToReplace->getBasePtr();
  auto Derived = dyn_cast<GetElementPtrInst>(ToReplace->getDerivedPtr());
  if (!Derived || Derived->getPointerOperand() != Base)
    continue;

  SmallVector<Value *, 2> OffsetV;
  if (!getGEPSmallConstantIntOffsetV(Derived, OffsetV))
    continue;

  // Create a Builder and replace the target callsite with a gep
  assert(RelocatedBase->getNextNode() &&((RelocatedBase->getNextNode() && "Should always have one since it's not a terminator"
) ? static_cast<void> (0) : __assert_fail ("RelocatedBase->getNextNode() && \"Should always have one since it's not a terminator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 976, __PRETTY_FUNCTION__))
         "Should always have one since it's not a terminator")((RelocatedBase->getNextNode() && "Should always have one since it's not a terminator"
) ? static_cast<void> (0) : __assert_fail ("RelocatedBase->getNextNode() && \"Should always have one since it's not a terminator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 976, __PRETTY_FUNCTION__));

  // Insert after RelocatedBase
  IRBuilder<> Builder(RelocatedBase->getNextNode());
  Builder.SetCurrentDebugLocation(ToReplace->getDebugLoc());

  // If gc_relocate does not match the actual type, cast it to the right type.
  // In theory, there must be a bitcast after gc_relocate if the type does not
  // match, and we should reuse it to get the derived pointer. But it could be
  // cases like this:
  // bb1:
  //  ...
  //  %g1 = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(...)
  //  br label %merge
  //
  // bb2:
  //  ...
  //  %g2 = call coldcc i8 addrspace(1)* @llvm.experimental.gc.relocate.p1i8(...)
  //  br label %merge
  //
  // merge:
  //  %p1 = phi i8 addrspace(1)* [ %g1, %bb1 ], [ %g2, %bb2 ]
  //  %cast = bitcast i8 addrspace(1)* %p1 in to i32 addrspace(1)*
  //
  // In this case, we can not find the bitcast any more. So we insert a new bitcast
  // no matter there is already one or not. In this way, we can handle all cases, and
  // the extra bitcast should be optimized away in later passes.
  Value *ActualRelocatedBase = RelocatedBase;
  if (RelocatedBase->getType() != Base->getType()) {
    ActualRelocatedBase =
        Builder.CreateBitCast(RelocatedBase, Base->getType());
  }
  Value *Replacement = Builder.CreateGEP(
      Derived->getSourceElementType(), ActualRelocatedBase, makeArrayRef(OffsetV));
  Replacement->takeName(ToReplace);
  // If the newly generated derived pointer's type does not match the original derived
  // pointer's type, cast the new derived pointer to match it. Same reasoning as above.
  Value *ActualReplacement = Replacement;
  if (Replacement->getType() != ToReplace->getType()) {
    ActualReplacement =
        Builder.CreateBitCast(Replacement, ToReplace->getType());
  }
  ToReplace->replaceAllUsesWith(ActualReplacement);
  ToReplace->eraseFromParent();

  MadeChange = true;
}
return MadeChange;
1024}

1026// Turns this:
1027//
1028// %base = ...
1029// %ptr = gep %base + 15
1030// %tok = statepoint (%fun, i32 0, i32 0, i32 0, %base, %ptr)
1031// %base' = relocate(%tok, i32 4, i32 4)
1032// %ptr' = relocate(%tok, i32 4, i32 5)
1033// %val = load %ptr'
1034//
1035// into this:
1036//
1037// %base = ...
1038// %ptr = gep %base + 15
1039// %tok = statepoint (%fun, i32 0, i32 0, i32 0, %base, %ptr)
1040// %base' = gc.relocate(%tok, i32 4, i32 4)
1041// %ptr' = gep %base' + 15
1042// %val = load %ptr'
1043bool CodeGenPrepare::simplifyOffsetableRelocate(Instruction &I) {
bool MadeChange = false;
SmallVector<GCRelocateInst *, 2> AllRelocateCalls;

for (auto *U : I.users())
  if (GCRelocateInst *Relocate = dyn_cast<GCRelocateInst>(U))
    // Collect all the relocate calls associated with a statepoint
    AllRelocateCalls.push_back(Relocate);

// We need atleast one base pointer relocation + one derived pointer
// relocation to mangle
if (AllRelocateCalls.size() < 2)
  return false;

// RelocateInstMap is a mapping from the base relocate instruction to the
// corresponding derived relocate instructions
DenseMap<GCRelocateInst *, SmallVector<GCRelocateInst *, 2>> RelocateInstMap;
computeBaseDerivedRelocateMap(AllRelocateCalls, RelocateInstMap);
if (RelocateInstMap.empty())
  return false;

for (auto &Item : RelocateInstMap)
  // Item.first is the RelocatedBase to offset against
  // Item.second is the vector of Targets to replace
  MadeChange = simplifyRelocatesOffABase(Item.first, Item.second);
return MadeChange;
1069}

1071/// Sink the specified cast instruction into its user blocks.
1072static bool SinkCast(CastInst *CI) {
BasicBlock *DefBB = CI->getParent();

/// InsertedCasts - Only insert a cast in each block once.
DenseMap<BasicBlock*, CastInst*> InsertedCasts;

bool MadeChange = false;
for (Value::user_iterator UI = CI->user_begin(), E = CI->user_end();
     UI != E; ) {
  Use &TheUse = UI.getUse();
  Instruction *User = cast<Instruction>(*UI);

  // Figure out which BB this cast is used in.  For PHI's this is the
  // appropriate predecessor block.
  BasicBlock *UserBB = User->getParent();
  if (PHINode *PN = dyn_cast<PHINode>(User)) {
    UserBB = PN->getIncomingBlock(TheUse);
  }

  // Preincrement use iterator so we don't invalidate it.
  ++UI;

  // The first insertion point of a block containing an EH pad is after the
  // pad.  If the pad is the user, we cannot sink the cast past the pad.
  if (User->isEHPad())
    continue;

  // If the block selected to receive the cast is an EH pad that does not
  // allow non-PHI instructions before the terminator, we can't sink the
  // cast.
  if (UserBB->getTerminator()->isEHPad())
    continue;

  // If this user is in the same block as the cast, don't change the cast.
  if (UserBB == DefBB) continue;

  // If we have already inserted a cast into this block, use it.
  CastInst *&InsertedCast = InsertedCasts[UserBB];

  if (!InsertedCast) {
    BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
    assert(InsertPt != UserBB->end())((InsertPt != UserBB->end()) ? static_cast<void> (0)
 : __assert_fail ("InsertPt != UserBB->end()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1113, __PRETTY_FUNCTION__));
    InsertedCast = CastInst::Create(CI->getOpcode(), CI->getOperand(0),
                                    CI->getType(), "", &*InsertPt);
    InsertedCast->setDebugLoc(CI->getDebugLoc());
  }

  // Replace a use of the cast with a use of the new cast.
  TheUse = InsertedCast;
  MadeChange = true;
  ++NumCastUses;
}

// If we removed all uses, nuke the cast.
if (CI->use_empty()) {
  salvageDebugInfo(*CI);
  CI->eraseFromParent();
  MadeChange = true;
}

return MadeChange;
1133}

1135/// If the specified cast instruction is a noop copy (e.g. it's casting from
1136/// one pointer type to another, i32->i8 on PPC), sink it into user blocks to
1137/// reduce the number of virtual registers that must be created and coalesced.
1138///
1139/// Return true if any changes are made.
1140static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI,
                                     const DataLayout &DL) {
// Sink only "cheap" (or nop) address-space casts.  This is a weaker condition
// than sinking only nop casts, but is helpful on some platforms.
if (auto *ASC = dyn_cast<AddrSpaceCastInst>(CI)) {
  if (!TLI.isFreeAddrSpaceCast(ASC->getSrcAddressSpace(),
                               ASC->getDestAddressSpace()))
    return false;
}

// If this is a noop copy,
EVT SrcVT = TLI.getValueType(DL, CI->getOperand(0)->getType());
EVT DstVT = TLI.getValueType(DL, CI->getType());

// This is an fp<->int conversion?
if (SrcVT.isInteger() != DstVT.isInteger())
  return false;

// If this is an extension, it will be a zero or sign extension, which
// isn't a noop.
if (SrcVT.bitsLT(DstVT)) return false;

// If these values will be promoted, find out what they will be promoted
// to.  This helps us consider truncates on PPC as noop copies when they
// are.
if (TLI.getTypeAction(CI->getContext(), SrcVT) ==
    TargetLowering::TypePromoteInteger)
  SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT);
if (TLI.getTypeAction(CI->getContext(), DstVT) ==
    TargetLowering::TypePromoteInteger)
  DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT);

// If, after promotion, these are the same types, this is a noop copy.
if (SrcVT != DstVT)
  return false;

return SinkCast(CI);
1177}

1179bool CodeGenPrepare::replaceMathCmpWithIntrinsic(BinaryOperator *BO,
                                               CmpInst *Cmp,
                                               Intrinsic::ID IID) {
if (BO->getParent() != Cmp->getParent()) {
  // We used to use a dominator tree here to allow multi-block optimization.
  // But that was problematic because:
  // 1. It could cause a perf regression by hoisting the math op into the
  //    critical path.
  // 2. It could cause a perf regression by creating a value that was live
  //    across multiple blocks and increasing register pressure.
  // 3. Use of a dominator tree could cause large compile-time regression.
  //    This is because we recompute the DT on every change in the main CGP
  //    run-loop. The recomputing is probably unnecessary in many cases, so if
  //    that was fixed, using a DT here would be ok.
  return false;
}

// We allow matching the canonical IR (add X, C) back to (usubo X, -C).
Value *Arg0 = BO->getOperand(0);
Value *Arg1 = BO->getOperand(1);
if (BO->getOpcode() == Instruction::Add &&
    IID == Intrinsic::usub_with_overflow) {
  assert(isa<Constant>(Arg1) && "Unexpected input for usubo")((isa<Constant>(Arg1) && "Unexpected input for usubo"
) ? static_cast<void> (0) : __assert_fail ("isa<Constant>(Arg1) && \"Unexpected input for usubo\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1201, __PRETTY_FUNCTION__));
  Arg1 = ConstantExpr::getNeg(cast<Constant>(Arg1));
}

// Insert at the first instruction of the pair.
Instruction *InsertPt = nullptr;
for (Instruction &Iter : *Cmp->getParent()) {
  if (&Iter == BO || &Iter == Cmp) {
    InsertPt = &Iter;
    break;
  }
}
assert(InsertPt != nullptr && "Parent block did not contain cmp or binop")((InsertPt != nullptr && "Parent block did not contain cmp or binop"
) ? static_cast<void> (0) : __assert_fail ("InsertPt != nullptr && \"Parent block did not contain cmp or binop\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1213, __PRETTY_FUNCTION__));

IRBuilder<> Builder(InsertPt);
Value *MathOV = Builder.CreateBinaryIntrinsic(IID, Arg0, Arg1);
Value *Math = Builder.CreateExtractValue(MathOV, 0, "math");
Value *OV = Builder.CreateExtractValue(MathOV, 1, "ov");
BO->replaceAllUsesWith(Math);
Cmp->replaceAllUsesWith(OV);
BO->eraseFromParent();
Cmp->eraseFromParent();
return true;
1224}

1226/// Match special-case patterns that check for unsigned add overflow.
1227static bool matchUAddWithOverflowConstantEdgeCases(CmpInst *Cmp,
                                                 BinaryOperator *&Add) {
// Add = add A, 1; Cmp = icmp eq A,-1 (overflow if A is max val)
// Add = add A,-1; Cmp = icmp ne A, 0 (overflow if A is non-zero)
Value *A = Cmp->getOperand(0), *B = Cmp->getOperand(1);

// We are not expecting non-canonical/degenerate code. Just bail out.
if (isa<Constant>(A))
  return false;

ICmpInst::Predicate Pred = Cmp->getPredicate();
if (Pred == ICmpInst::ICMP_EQ && match(B, m_AllOnes()))
  B = ConstantInt::get(B->getType(), 1);
else if (Pred == ICmpInst::ICMP_NE && match(B, m_ZeroInt()))
  B = ConstantInt::get(B->getType(), -1);
else
  return false;

// Check the users of the variable operand of the compare looking for an add
// with the adjusted constant.
for (User *U : A->users()) {
  if (match(U, m_Add(m_Specific(A), m_Specific(B)))) {
    Add = cast<BinaryOperator>(U);
    return true;
  }
}
return false;
1254}

1256/// Try to combine the compare into a call to the llvm.uadd.with.overflow
1257/// intrinsic. Return true if any changes were made.
1258bool CodeGenPrepare::combineToUAddWithOverflow(CmpInst *Cmp,
                                             bool &ModifiedDT) {
Value *A, *B;
BinaryOperator *Add;
if (!match(Cmp, m_UAddWithOverflow(m_Value(A), m_Value(B), m_BinOp(Add))))
  if (!matchUAddWithOverflowConstantEdgeCases(Cmp, Add))
    return false;

if (!TLI->shouldFormOverflowOp(ISD::UADDO,
                               TLI->getValueType(*DL, Add->getType())))
  return false;

// We don't want to move around uses of condition values this late, so we
// check if it is legal to create the call to the intrinsic in the basic
// block containing the icmp.
if (Add->getParent() != Cmp->getParent() && !Add->hasOneUse())
  return false;

if (!replaceMathCmpWithIntrinsic(Add, Cmp, Intrinsic::uadd_with_overflow))
  return false;

// Reset callers - do not crash by iterating over a dead instruction.
ModifiedDT = true;
return true;
1282}

1284bool CodeGenPrepare::combineToUSubWithOverflow(CmpInst *Cmp,
                                             bool &ModifiedDT) {
// We are not expecting non-canonical/degenerate code. Just bail out.
Value *A = Cmp->getOperand(0), *B = Cmp->getOperand(1);
if (isa<Constant>(A) && isa<Constant>(B))
  return false;

// Convert (A u> B) to (A u< B) to simplify pattern matching.
ICmpInst::Predicate Pred = Cmp->getPredicate();
if (Pred == ICmpInst::ICMP_UGT) {
  std::swap(A, B);
  Pred = ICmpInst::ICMP_ULT;
}
// Convert special-case: (A == 0) is the same as (A u< 1).
if (Pred == ICmpInst::ICMP_EQ && match(B, m_ZeroInt())) {
  B = ConstantInt::get(B->getType(), 1);
  Pred = ICmpInst::ICMP_ULT;
}
// Convert special-case: (A != 0) is the same as (0 u< A).
if (Pred == ICmpInst::ICMP_NE && match(B, m_ZeroInt())) {
  std::swap(A, B);
  Pred = ICmpInst::ICMP_ULT;
}
if (Pred != ICmpInst::ICMP_ULT)
  return false;

// Walk the users of a variable operand of a compare looking for a subtract or
// add with that same operand. Also match the 2nd operand of the compare to
// the add/sub, but that may be a negated constant operand of an add.
Value *CmpVariableOperand = isa<Constant>(A) ? B : A;
BinaryOperator *Sub = nullptr;
for (User *U : CmpVariableOperand->users()) {
  // A - B, A u< B --> usubo(A, B)
  if (match(U, m_Sub(m_Specific(A), m_Specific(B)))) {
    Sub = cast<BinaryOperator>(U);
    break;
  }

  // A + (-C), A u< C (canonicalized form of (sub A, C))
  const APInt *CmpC, *AddC;
  if (match(U, m_Add(m_Specific(A), m_APInt(AddC))) &&
      match(B, m_APInt(CmpC)) && *AddC == -(*CmpC)) {
    Sub = cast<BinaryOperator>(U);
    break;
  }
}
if (!Sub)
  return false;

if (!TLI->shouldFormOverflowOp(ISD::USUBO,
                               TLI->getValueType(*DL, Sub->getType())))
  return false;

if (!replaceMathCmpWithIntrinsic(Sub, Cmp, Intrinsic::usub_with_overflow))
  return false;

// Reset callers - do not crash by iterating over a dead instruction.
ModifiedDT = true;
return true;
1343}

1345/// Sink the given CmpInst into user blocks to reduce the number of virtual
1346/// registers that must be created and coalesced. This is a clear win except on
1347/// targets with multiple condition code registers (PowerPC), where it might
1348/// lose; some adjustment may be wanted there.
1349///
1350/// Return true if any changes are made.
1351static bool sinkCmpExpression(CmpInst *Cmp, const TargetLowering &TLI) {
if (TLI.hasMultipleConditionRegisters())
  return false;

// Avoid sinking soft-FP comparisons, since this can move them into a loop.
if (TLI.useSoftFloat() && isa<FCmpInst>(Cmp))
  return false;

// Only insert a cmp in each block once.
DenseMap<BasicBlock*, CmpInst*> InsertedCmps;

bool MadeChange = false;
for (Value::user_iterator UI = Cmp->user_begin(), E = Cmp->user_end();
     UI != E; ) {
  Use &TheUse = UI.getUse();
  Instruction *User = cast<Instruction>(*UI);

  // Preincrement use iterator so we don't invalidate it.
  ++UI;

  // Don't bother for PHI nodes.
  if (isa<PHINode>(User))
    continue;

  // Figure out which BB this cmp is used in.
  BasicBlock *UserBB = User->getParent();
  BasicBlock *DefBB = Cmp->getParent();

  // If this user is in the same block as the cmp, don't change the cmp.
  if (UserBB == DefBB) continue;

  // If we have already inserted a cmp into this block, use it.
  CmpInst *&InsertedCmp = InsertedCmps[UserBB];

  if (!InsertedCmp) {
    BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
    assert(InsertPt != UserBB->end())((InsertPt != UserBB->end()) ? static_cast<void> (0)
 : __assert_fail ("InsertPt != UserBB->end()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1387, __PRETTY_FUNCTION__));
    InsertedCmp =
        CmpInst::Create(Cmp->getOpcode(), Cmp->getPredicate(),
                        Cmp->getOperand(0), Cmp->getOperand(1), "",
                        &*InsertPt);
    // Propagate the debug info.
    InsertedCmp->setDebugLoc(Cmp->getDebugLoc());
  }

  // Replace a use of the cmp with a use of the new cmp.
  TheUse = InsertedCmp;
  MadeChange = true;
  ++NumCmpUses;
}

// If we removed all uses, nuke the cmp.
if (Cmp->use_empty()) {
  Cmp->eraseFromParent();
  MadeChange = true;
}

return MadeChange;
1409}

1411bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, bool &ModifiedDT) {
if (sinkCmpExpression(Cmp, *TLI))
  return true;

if (combineToUAddWithOverflow(Cmp, ModifiedDT))
  return true;

if (combineToUSubWithOverflow(Cmp, ModifiedDT))
  return true;

return false;
1422}

1424/// Duplicate and sink the given 'and' instruction into user blocks where it is
1425/// used in a compare to allow isel to generate better code for targets where
1426/// this operation can be combined.
1427///
1428/// Return true if any changes are made.
1429static bool sinkAndCmp0Expression(Instruction *AndI,
                                const TargetLowering &TLI,
                                SetOfInstrs &InsertedInsts) {
// Double-check that we're not trying to optimize an instruction that was
// already optimized by some other part of this pass.
assert(!InsertedInsts.count(AndI) &&((!InsertedInsts.count(AndI) && "Attempting to optimize already optimized and instruction"
) ? static_cast<void> (0) : __assert_fail ("!InsertedInsts.count(AndI) && \"Attempting to optimize already optimized and instruction\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1435, __PRETTY_FUNCTION__))
       "Attempting to optimize already optimized and instruction")((!InsertedInsts.count(AndI) && "Attempting to optimize already optimized and instruction"
) ? static_cast<void> (0) : __assert_fail ("!InsertedInsts.count(AndI) && \"Attempting to optimize already optimized and instruction\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1435, __PRETTY_FUNCTION__));
(void) InsertedInsts;

// Nothing to do for single use in same basic block.
if (AndI->hasOneUse() &&
    AndI->getParent() == cast<Instruction>(*AndI->user_begin())->getParent())
  return false;

// Try to avoid cases where sinking/duplicating is likely to increase register
// pressure.
if (!isa<ConstantInt>(AndI->getOperand(0)) &&
    !isa<ConstantInt>(AndI->getOperand(1)) &&
    AndI->getOperand(0)->hasOneUse() && AndI->getOperand(1)->hasOneUse())
  return false;

for (auto *U : AndI->users()) {
  Instruction *User = cast<Instruction>(U);

  // Only sink 'and' feeding icmp with 0.
  if (!isa<ICmpInst>(User))
    return false;

  auto *CmpC = dyn_cast<ConstantInt>(User->getOperand(1));
  if (!CmpC || !CmpC->isZero())
    return false;
}

if (!TLI.isMaskAndCmp0FoldingBeneficial(*AndI))
  return false;

LLVM_DEBUG(dbgs() << "found 'and' feeding only icmp 0;\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "found 'and' feeding only icmp 0;\n"
; } } while (false);
LLVM_DEBUG(AndI->getParent()->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { AndI->getParent()->dump(); } } while
 (false);

// Push the 'and' into the same block as the icmp 0.  There should only be
// one (icmp (and, 0)) in each block, since CSE/GVN should have removed any
// others, so we don't need to keep track of which BBs we insert into.
for (Value::user_iterator UI = AndI->user_begin(), E = AndI->user_end();
     UI != E; ) {
  Use &TheUse = UI.getUse();
  Instruction *User = cast<Instruction>(*UI);

  // Preincrement use iterator so we don't invalidate it.
  ++UI;

  LLVM_DEBUG(dbgs() << "sinking 'and' use: " << *User << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "sinking 'and' use: " <<
 *User << "\n"; } } while (false);

  // Keep the 'and' in the same place if the use is already in the same block.
  Instruction *InsertPt =
      User->getParent() == AndI->getParent() ? AndI : User;
  Instruction *InsertedAnd =
      BinaryOperator::Create(Instruction::And, AndI->getOperand(0),
                             AndI->getOperand(1), "", InsertPt);
  // Propagate the debug info.
  InsertedAnd->setDebugLoc(AndI->getDebugLoc());

  // Replace a use of the 'and' with a use of the new 'and'.
  TheUse = InsertedAnd;
  ++NumAndUses;
  LLVM_DEBUG(User->getParent()->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { User->getParent()->dump(); } } while
 (false);
}

// We removed all uses, nuke the and.
AndI->eraseFromParent();
return true;
1499}

1501/// Check if the candidates could be combined with a shift instruction, which
1502/// includes:
1503/// 1. Truncate instruction
1504/// 2. And instruction and the imm is a mask of the low bits:
1505/// imm & (imm+1) == 0
1506static bool isExtractBitsCandidateUse(Instruction *User) {
if (!isa<TruncInst>(User)) {
  if (User->getOpcode() != Instruction::And ||
      !isa<ConstantInt>(User->getOperand(1)))
    return false;

  const APInt &Cimm = cast<ConstantInt>(User->getOperand(1))->getValue();

  if ((Cimm & (Cimm + 1)).getBoolValue())
    return false;
}
return true;
1518}

1520/// Sink both shift and truncate instruction to the use of truncate's BB.
1521static bool
1522SinkShiftAndTruncate(BinaryOperator *ShiftI, Instruction *User, ConstantInt *CI,
                   DenseMap<BasicBlock *, BinaryOperator *> &InsertedShifts,
                   const TargetLowering &TLI, const DataLayout &DL) {
BasicBlock *UserBB = User->getParent();
DenseMap<BasicBlock *, CastInst *> InsertedTruncs;
TruncInst *TruncI = dyn_cast<TruncInst>(User);
bool MadeChange = false;

for (Value::user_iterator TruncUI = TruncI->user_begin(),
                          TruncE = TruncI->user_end();
     TruncUI != TruncE;) {

  Use &TruncTheUse = TruncUI.getUse();
  Instruction *TruncUser = cast<Instruction>(*TruncUI);
  // Preincrement use iterator so we don't invalidate it.

  ++TruncUI;

  int ISDOpcode = TLI.InstructionOpcodeToISD(TruncUser->getOpcode());
  if (!ISDOpcode)
    continue;

  // If the use is actually a legal node, there will not be an
  // implicit truncate.
  // FIXME: always querying the result type is just an
  // approximation; some nodes' legality is determined by the
  // operand or other means. There's no good way to find out though.
  if (TLI.isOperationLegalOrCustom(
          ISDOpcode, TLI.getValueType(DL, TruncUser->getType(), true)))
    continue;

  // Don't bother for PHI nodes.
  if (isa<PHINode>(TruncUser))
    continue;

  BasicBlock *TruncUserBB = TruncUser->getParent();

  if (UserBB == TruncUserBB)
    continue;

  BinaryOperator *&InsertedShift = InsertedShifts[TruncUserBB];
  CastInst *&InsertedTrunc = InsertedTruncs[TruncUserBB];

  if (!InsertedShift && !InsertedTrunc) {
    BasicBlock::iterator InsertPt = TruncUserBB->getFirstInsertionPt();
    assert(InsertPt != TruncUserBB->end())((InsertPt != TruncUserBB->end()) ? static_cast<void>
 (0) : __assert_fail ("InsertPt != TruncUserBB->end()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1567, __PRETTY_FUNCTION__));
    // Sink the shift
    if (ShiftI->getOpcode() == Instruction::AShr)
      InsertedShift = BinaryOperator::CreateAShr(ShiftI->getOperand(0), CI,
                                                 "", &*InsertPt);
    else
      InsertedShift = BinaryOperator::CreateLShr(ShiftI->getOperand(0), CI,
                                                 "", &*InsertPt);
    InsertedShift->setDebugLoc(ShiftI->getDebugLoc());

    // Sink the trunc
    BasicBlock::iterator TruncInsertPt = TruncUserBB->getFirstInsertionPt();
    TruncInsertPt++;
    assert(TruncInsertPt != TruncUserBB->end())((TruncInsertPt != TruncUserBB->end()) ? static_cast<void
> (0) : __assert_fail ("TruncInsertPt != TruncUserBB->end()"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1580, __PRETTY_FUNCTION__));

    InsertedTrunc = CastInst::Create(TruncI->getOpcode(), InsertedShift,
                                     TruncI->getType(), "", &*TruncInsertPt);
    InsertedTrunc->setDebugLoc(TruncI->getDebugLoc());

    MadeChange = true;

    TruncTheUse = InsertedTrunc;
  }
}
return MadeChange;
1592}

1594/// Sink the shift *right* instruction into user blocks if the uses could
1595/// potentially be combined with this shift instruction and generate BitExtract
1596/// instruction. It will only be applied if the architecture supports BitExtract
1597/// instruction. Here is an example:
1598/// BB1:
1599///   %x.extract.shift = lshr i64 %arg1, 32
1600/// BB2:
1601///   %x.extract.trunc = trunc i64 %x.extract.shift to i16
1602/// ==>
1603///
1604/// BB2:
1605///   %x.extract.shift.1 = lshr i64 %arg1, 32
1606///   %x.extract.trunc = trunc i64 %x.extract.shift.1 to i16
1607///
1608/// CodeGen will recognize the pattern in BB2 and generate BitExtract
1609/// instruction.
1610/// Return true if any changes are made.
1611static bool OptimizeExtractBits(BinaryOperator *ShiftI, ConstantInt *CI,
                              const TargetLowering &TLI,
                              const DataLayout &DL) {
BasicBlock *DefBB = ShiftI->getParent();

/// Only insert instructions in each block once.
DenseMap<BasicBlock *, BinaryOperator *> InsertedShifts;

bool shiftIsLegal = TLI.isTypeLegal(TLI.getValueType(DL, ShiftI->getType()));

bool MadeChange = false;
for (Value::user_iterator UI = ShiftI->user_begin(), E = ShiftI->user_end();
     UI != E;) {
  Use &TheUse = UI.getUse();
  Instruction *User = cast<Instruction>(*UI);
  // Preincrement use iterator so we don't invalidate it.
  ++UI;

  // Don't bother for PHI nodes.
  if (isa<PHINode>(User))
    continue;

  if (!isExtractBitsCandidateUse(User))
    continue;

  BasicBlock *UserBB = User->getParent();

  if (UserBB == DefBB) {
    // If the shift and truncate instruction are in the same BB. The use of
    // the truncate(TruncUse) may still introduce another truncate if not
    // legal. In this case, we would like to sink both shift and truncate
    // instruction to the BB of TruncUse.
    // for example:
    // BB1:
    // i64 shift.result = lshr i64 opnd, imm
    // trunc.result = trunc shift.result to i16
    //
    // BB2:
    //   ----> We will have an implicit truncate here if the architecture does
    //   not have i16 compare.
    // cmp i16 trunc.result, opnd2
    //
    if (isa<TruncInst>(User) && shiftIsLegal
        // If the type of the truncate is legal, no truncate will be
        // introduced in other basic blocks.
        &&
        (!TLI.isTypeLegal(TLI.getValueType(DL, User->getType()))))
      MadeChange =
          SinkShiftAndTruncate(ShiftI, User, CI, InsertedShifts, TLI, DL);

    continue;
  }
  // If we have already inserted a shift into this block, use it.
  BinaryOperator *&InsertedShift = InsertedShifts[UserBB];

  if (!InsertedShift) {
    BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
    assert(InsertPt != UserBB->end())((InsertPt != UserBB->end()) ? static_cast<void> (0)
 : __assert_fail ("InsertPt != UserBB->end()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 1668, __PRETTY_FUNCTION__));

    if (ShiftI->getOpcode() == Instruction::AShr)
      InsertedShift = BinaryOperator::CreateAShr(ShiftI->getOperand(0), CI,
                                                 "", &*InsertPt);
    else
      InsertedShift = BinaryOperator::CreateLShr(ShiftI->getOperand(0), CI,
                                                 "", &*InsertPt);
    InsertedShift->setDebugLoc(ShiftI->getDebugLoc());

    MadeChange = true;
  }

  // Replace a use of the shift with a use of the new shift.
  TheUse = InsertedShift;
}

// If we removed all uses, or there are none, nuke the shift.
if (ShiftI->use_empty()) {
  salvageDebugInfo(*ShiftI);
  ShiftI->eraseFromParent();
  MadeChange = true;
}

return MadeChange;
1693}

1695/// If counting leading or trailing zeros is an expensive operation and a zero
1696/// input is defined, add a check for zero to avoid calling the intrinsic.
1697///
1698/// We want to transform:
1699///     %z = call i64 @llvm.cttz.i64(i64 %A, i1 false)
1700///
1701/// into:
1702///   entry:
1703///     %cmpz = icmp eq i64 %A, 0
1704///     br i1 %cmpz, label %cond.end, label %cond.false
1705///   cond.false:
1706///     %z = call i64 @llvm.cttz.i64(i64 %A, i1 true)
1707///     br label %cond.end
1708///   cond.end:
1709///     %ctz = phi i64 [ 64, %entry ], [ %z, %cond.false ]
1710///
1711/// If the transform is performed, return true and set ModifiedDT to true.
1712static bool despeculateCountZeros(IntrinsicInst *CountZeros,
                                const TargetLowering *TLI,
                                const DataLayout *DL,
                                bool &ModifiedDT) {
if (!TLI || !DL)
  return false;

// If a zero input is undefined, it doesn't make sense to despeculate that.
if (match(CountZeros->getOperand(1), m_One()))
  return false;

// If it's cheap to speculate, there's nothing to do.
auto IntrinsicID = CountZeros->getIntrinsicID();
if ((IntrinsicID == Intrinsic::cttz && TLI->isCheapToSpeculateCttz()) ||
    (IntrinsicID == Intrinsic::ctlz && TLI->isCheapToSpeculateCtlz()))
  return false;

// Only handle legal scalar cases. Anything else requires too much work.
Type *Ty = CountZeros->getType();
unsigned SizeInBits = Ty->getPrimitiveSizeInBits();
if (Ty->isVectorTy() || SizeInBits > DL->getLargestLegalIntTypeSizeInBits())
  return false;

// The intrinsic will be sunk behind a compare against zero and branch.
BasicBlock *StartBlock = CountZeros->getParent();
BasicBlock *CallBlock = StartBlock->splitBasicBlock(CountZeros, "cond.false");

// Create another block after the count zero intrinsic. A PHI will be added
// in this block to select the result of the intrinsic or the bit-width
// constant if the input to the intrinsic is zero.
BasicBlock::iterator SplitPt = ++(BasicBlock::iterator(CountZeros));
BasicBlock *EndBlock = CallBlock->splitBasicBlock(SplitPt, "cond.end");

// Set up a builder to create a compare, conditional branch, and PHI.
IRBuilder<> Builder(CountZeros->getContext());
Builder.SetInsertPoint(StartBlock->getTerminator());
Builder.SetCurrentDebugLocation(CountZeros->getDebugLoc());

// Replace the unconditional branch that was created by the first split with
// a compare against zero and a conditional branch.
Value *Zero = Constant::getNullValue(Ty);
Value *Cmp = Builder.CreateICmpEQ(CountZeros->getOperand(0), Zero, "cmpz");
Builder.CreateCondBr(Cmp, EndBlock, CallBlock);
StartBlock->getTerminator()->eraseFromParent();

// Create a PHI in the end block to select either the output of the intrinsic
// or the bit width of the operand.
Builder.SetInsertPoint(&EndBlock->front());
PHINode *PN = Builder.CreatePHI(Ty, 2, "ctz");
CountZeros->replaceAllUsesWith(PN);
Value *BitWidth = Builder.getInt(APInt(SizeInBits, SizeInBits));
PN->addIncoming(BitWidth, StartBlock);
PN->addIncoming(CountZeros, CallBlock);

// We are explicitly handling the zero case, so we can set the intrinsic's
// undefined zero argument to 'true'. This will also prevent reprocessing the
// intrinsic; we only despeculate when a zero input is defined.
CountZeros->setArgOperand(1, Builder.getTrue());
ModifiedDT = true;
return true;
1772}

1774bool CodeGenPrepare::optimizeCallInst(CallInst *CI, bool &ModifiedDT) {
BasicBlock *BB = CI->getParent();

// Lower inline assembly if we can.
// If we found an inline asm expession, and if the target knows how to
// lower it to normal LLVM code, do so now.
if (TLI && isa<InlineAsm>(CI->getCalledValue())) {
  if (TLI->ExpandInlineAsm(CI)) {
    // Avoid invalidating the iterator.
    CurInstIterator = BB->begin();
    // Avoid processing instructions out of order, which could cause
    // reuse before a value is defined.
    SunkAddrs.clear();
    return true;
  }
  // Sink address computing for memory operands into the block.
  if (optimizeInlineAsmInst(CI))
    return true;
}

// Align the pointer arguments to this call if the target thinks it's a good
// idea
unsigned MinSize, PrefAlign;
if (TLI && TLI->shouldAlignPointerArgs(CI, MinSize, PrefAlign)) {
  for (auto &Arg : CI->arg_operands()) {
    // We want to align both objects whose address is used directly and
    // objects whose address is used in casts and GEPs, though it only makes
    // sense for GEPs if the offset is a multiple of the desired alignment and
    // if size - offset meets the size threshold.
    if (!Arg->getType()->isPointerTy())
      continue;
    APInt Offset(DL->getIndexSizeInBits(
                     cast<PointerType>(Arg->getType())->getAddressSpace()),
                 0);
    Value *Val = Arg->stripAndAccumulateInBoundsConstantOffsets(*DL, Offset);
    uint64_t Offset2 = Offset.getLimitedValue();
    if ((Offset2 & (PrefAlign-1)) != 0)
      continue;
    AllocaInst *AI;
    if ((AI = dyn_cast<AllocaInst>(Val)) && AI->getAlignment() < PrefAlign &&
        DL->getTypeAllocSize(AI->getAllocatedType()) >= MinSize + Offset2)
      AI->setAlignment(MaybeAlign(PrefAlign));
    // Global variables can only be aligned if they are defined in this
    // object (i.e. they are uniquely initialized in this object), and
    // over-aligning global variables that have an explicit section is
    // forbidden.
    GlobalVariable *GV;
    if ((GV = dyn_cast<GlobalVariable>(Val)) && GV->canIncreaseAlignment() &&
        GV->getPointerAlignment(*DL) < PrefAlign &&
        DL->getTypeAllocSize(GV->getValueType()) >=
            MinSize + Offset2)
      GV->setAlignment(PrefAlign);
  }
  // If this is a memcpy (or similar) then we may be able to improve the
  // alignment
  if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(CI)) {
    unsigned DestAlign = getKnownAlignment(MI->getDest(), *DL);
    if (DestAlign > MI->getDestAlignment())
      MI->setDestAlignment(DestAlign);
    if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(MI)) {
      unsigned SrcAlign = getKnownAlignment(MTI->getSource(), *DL);
      if (SrcAlign > MTI->getSourceAlignment())
        MTI->setSourceAlignment(SrcAlign);
    }
  }
}

// If we have a cold call site, try to sink addressing computation into the
// cold block.  This interacts with our handling for loads and stores to
// ensure that we can fold all uses of a potential addressing computation
// into their uses.  TODO: generalize this to work over profiling data
if (!OptSize && CI->hasFnAttr(Attribute::Cold))
  for (auto &Arg : CI->arg_operands()) {
    if (!Arg->getType()->isPointerTy())
      continue;
    unsigned AS = Arg->getType()->getPointerAddressSpace();
    return optimizeMemoryInst(CI, Arg, Arg->getType(), AS);
  }

IntrinsicInst *II = dyn_cast<IntrinsicInst>(CI);
if (II) {
  switch (II->getIntrinsicID()) {
  default: break;
  case Intrinsic::experimental_widenable_condition: {
    // Give up on future widening oppurtunties so that we can fold away dead
    // paths and merge blocks before going into block-local instruction
    // selection.   
    if (II->use_empty()) {
      II->eraseFromParent();
      return true;
    }
    Constant *RetVal = ConstantInt::getTrue(II->getContext());
    resetIteratorIfInvalidatedWhileCalling(BB, [&]() {
      replaceAndRecursivelySimplify(CI, RetVal, TLInfo, nullptr);
    });
    return true;
  }
  case Intrinsic::objectsize: {
    // Lower all uses of llvm.objectsize.*
    Value *RetVal =
        lowerObjectSizeCall(II, *DL, TLInfo, /*MustSucceed=*/true);

    resetIteratorIfInvalidatedWhileCalling(BB, [&]() {
      replaceAndRecursivelySimplify(CI, RetVal, TLInfo, nullptr);
    });
    return true;
  }
  case Intrinsic::is_constant: {
    // If is_constant hasn't folded away yet, lower it to false now.
    Constant *RetVal = ConstantInt::get(II->getType(), 0);
    resetIteratorIfInvalidatedWhileCalling(BB, [&]() {
      replaceAndRecursivelySimplify(CI, RetVal, TLInfo, nullptr);
    });
    return true;
  }
  case Intrinsic::aarch64_stlxr:
  case Intrinsic::aarch64_stxr: {
    ZExtInst *ExtVal = dyn_cast<ZExtInst>(CI->getArgOperand(0));
    if (!ExtVal || !ExtVal->hasOneUse() ||
        ExtVal->getParent() == CI->getParent())
      return false;
    // Sink a zext feeding stlxr/stxr before it, so it can be folded into it.
    ExtVal->moveBefore(CI);
    // Mark this instruction as "inserted by CGP", so that other
    // optimizations don't touch it.
    InsertedInsts.insert(ExtVal);
    return true;
  }

  case Intrinsic::launder_invariant_group:
  case Intrinsic::strip_invariant_group: {
    Value *ArgVal = II->getArgOperand(0);
    auto it = LargeOffsetGEPMap.find(II);
    if (it != LargeOffsetGEPMap.end()) {
        // Merge entries in LargeOffsetGEPMap to reflect the RAUW.
        // Make sure not to have to deal with iterator invalidation
        // after possibly adding ArgVal to LargeOffsetGEPMap.
        auto GEPs = std::move(it->second);
        LargeOffsetGEPMap[ArgVal].append(GEPs.begin(), GEPs.end());
        LargeOffsetGEPMap.erase(II);
    }

    II->replaceAllUsesWith(ArgVal);
    II->eraseFromParent();
    return true;
  }
  case Intrinsic::cttz:
  case Intrinsic::ctlz:
    // If counting zeros is expensive, try to avoid it.
    return despeculateCountZeros(II, TLI, DL, ModifiedDT);
  }

  if (TLI) {
    SmallVector<Value*, 2> PtrOps;
    Type *AccessTy;
    if (TLI->getAddrModeArguments(II, PtrOps, AccessTy))
      while (!PtrOps.empty()) {
        Value *PtrVal = PtrOps.pop_back_val();
        unsigned AS = PtrVal->getType()->getPointerAddressSpace();
        if (optimizeMemoryInst(II, PtrVal, AccessTy, AS))
          return true;
      }
  }
}

// From here on out we're working with named functions.
if (!CI->getCalledFunction()) return false;

// Lower all default uses of _chk calls.  This is very similar
// to what InstCombineCalls does, but here we are only lowering calls
// to fortified library functions (e.g. __memcpy_chk) that have the default
// "don't know" as the objectsize.  Anything else should be left alone.
FortifiedLibCallSimplifier Simplifier(TLInfo, true);
if (Value *V = Simplifier.optimizeCall(CI)) {
  CI->replaceAllUsesWith(V);
  CI->eraseFromParent();
  return true;
}

return false;
1954}

1956/// Look for opportunities to duplicate return instructions to the predecessor
1957/// to enable tail call optimizations. The case it is currently looking for is:
1958/// @code
1959/// bb0:
1960///   %tmp0 = tail call i32 @f0()
1961///   br label %return
1962/// bb1:
1963///   %tmp1 = tail call i32 @f1()
1964///   br label %return
1965/// bb2:
1966///   %tmp2 = tail call i32 @f2()
1967///   br label %return
1968/// return:
1969///   %retval = phi i32 [ %tmp0, %bb0 ], [ %tmp1, %bb1 ], [ %tmp2, %bb2 ]
1970///   ret i32 %retval
1971/// @endcode
1972///
1973/// =>
1974///
1975/// @code
1976/// bb0:
1977///   %tmp0 = tail call i32 @f0()
1978///   ret i32 %tmp0
1979/// bb1:
1980///   %tmp1 = tail call i32 @f1()
1981///   ret i32 %tmp1
1982/// bb2:
1983///   %tmp2 = tail call i32 @f2()
1984///   ret i32 %tmp2
1985/// @endcode
1986bool CodeGenPrepare::dupRetToEnableTailCallOpts(BasicBlock *BB, bool &ModifiedDT) {
if (!TLI)
  return false;

ReturnInst *RetI = dyn_cast<ReturnInst>(BB->getTerminator());
if (!RetI)
  return false;

PHINode *PN = nullptr;
BitCastInst *BCI = nullptr;
Value *V = RetI->getReturnValue();
if (V) {
  BCI = dyn_cast<BitCastInst>(V);
  if (BCI)
    V = BCI->getOperand(0);

  PN = dyn_cast<PHINode>(V);
  if (!PN)
    return false;
}

if (PN && PN->getParent() != BB)
  return false;

// Make sure there are no instructions between the PHI and return, or that the
// return is the first instruction in the block.
if (PN) {
  BasicBlock::iterator BI = BB->begin();
  // Skip over debug and the bitcast.
  do { ++BI; } while (isa<DbgInfoIntrinsic>(BI) || &*BI == BCI);
  if (&*BI != RetI)
    return false;
} else {
  BasicBlock::iterator BI = BB->begin();
  while (isa<DbgInfoIntrinsic>(BI)) ++BI;
  if (&*BI != RetI)
    return false;
}

/// Only dup the ReturnInst if the CallInst is likely to be emitted as a tail
/// call.
const Function *F = BB->getParent();
SmallVector<BasicBlock*, 4> TailCallBBs;
if (PN) {
  for (unsigned I = 0, E = PN->getNumIncomingValues(); I != E; ++I) {
    // Look through bitcasts.
    Value *IncomingVal = PN->getIncomingValue(I)->stripPointerCasts();
    CallInst *CI = dyn_cast<CallInst>(IncomingVal);
    BasicBlock *PredBB = PN->getIncomingBlock(I);
    // Make sure the phi value is indeed produced by the tail call.
    if (CI && CI->hasOneUse() && CI->getParent() == PredBB &&
        TLI->mayBeEmittedAsTailCall(CI) &&
        attributesPermitTailCall(F, CI, RetI, *TLI))
      TailCallBBs.push_back(PredBB);
  }
} else {
  SmallPtrSet<BasicBlock*, 4> VisitedBBs;
  for (pred_iterator PI = pred_begin(BB), PE = pred_end(BB); PI != PE; ++PI) {
    if (!VisitedBBs.insert(*PI).second)
      continue;

    BasicBlock::InstListType &InstList = (*PI)->getInstList();
    BasicBlock::InstListType::reverse_iterator RI = InstList.rbegin();
    BasicBlock::InstListType::reverse_iterator RE = InstList.rend();
    do { ++RI; } while (RI != RE && isa<DbgInfoIntrinsic>(&*RI));
    if (RI == RE)
      continue;

    CallInst *CI = dyn_cast<CallInst>(&*RI);
    if (CI && CI->use_empty() && TLI->mayBeEmittedAsTailCall(CI) &&
        attributesPermitTailCall(F, CI, RetI, *TLI))
      TailCallBBs.push_back(*PI);
  }
}

bool Changed = false;
for (auto const &TailCallBB : TailCallBBs) {
  // Make sure the call instruction is followed by an unconditional branch to
  // the return block.
  BranchInst *BI = dyn_cast<BranchInst>(TailCallBB->getTerminator());
  if (!BI || !BI->isUnconditional() || BI->getSuccessor(0) != BB)
    continue;

  // Duplicate the return into TailCallBB.
  (void)FoldReturnIntoUncondBranch(RetI, BB, TailCallBB);
  ModifiedDT = Changed = true;
  ++NumRetsDup;
}

// If we eliminated all predecessors of the block, delete the block now.
if (Changed && !BB->hasAddressTaken() && pred_begin(BB) == pred_end(BB))
  BB->eraseFromParent();

return Changed;
2080}

2082//===----------------------------------------------------------------------===//
2083// Memory Optimization
2084//===----------------------------------------------------------------------===//

2086namespace {

2088/// This is an extended version of TargetLowering::AddrMode
2089/// which holds actual Value*'s for register values.
2090struct ExtAddrMode : public TargetLowering::AddrMode {
Value *BaseReg = nullptr;
Value *ScaledReg = nullptr;
Value *OriginalValue = nullptr;
bool InBounds = true;

enum FieldName {
  NoField        = 0x00,
  BaseRegField   = 0x01,
  BaseGVField    = 0x02,
  BaseOffsField  = 0x04,
  ScaledRegField = 0x08,
  ScaleField     = 0x10,
  MultipleFields = 0xff
};


ExtAddrMode() = default;

void print(raw_ostream &OS) const;
void dump() const;

FieldName compare(const ExtAddrMode &other) {
  // First check that the types are the same on each field, as differing types
  // is something we can't cope with later on.
  if (BaseReg && other.BaseReg &&
      BaseReg->getType() != other.BaseReg->getType())
    return MultipleFields;
  if (BaseGV && other.BaseGV &&
      BaseGV->getType() != other.BaseGV->getType())
    return MultipleFields;
  if (ScaledReg && other.ScaledReg &&
      ScaledReg->getType() != other.ScaledReg->getType())
    return MultipleFields;

  // Conservatively reject 'inbounds' mismatches.
  if (InBounds != other.InBounds)
    return MultipleFields;

  // Check each field to see if it differs.
  unsigned Result = NoField;
  if (BaseReg != other.BaseReg)
    Result |= BaseRegField;
  if (BaseGV != other.BaseGV)
    Result |= BaseGVField;
  if (BaseOffs != other.BaseOffs)
    Result |= BaseOffsField;
  if (ScaledReg != other.ScaledReg)
    Result |= ScaledRegField;
  // Don't count 0 as being a different scale, because that actually means
  // unscaled (which will already be counted by having no ScaledReg).
  if (Scale && other.Scale && Scale != other.Scale)
    Result |= ScaleField;

  if (countPopulation(Result) > 1)
    return MultipleFields;
  else
    return static_cast<FieldName>(Result);
}

// An AddrMode is trivial if it involves no calculation i.e. it is just a base
// with no offset.
bool isTrivial() {
  // An AddrMode is (BaseGV + BaseReg + BaseOffs + ScaleReg * Scale) so it is
  // trivial if at most one of these terms is nonzero, except that BaseGV and
  // BaseReg both being zero actually means a null pointer value, which we
  // consider to be 'non-zero' here.
  return !BaseOffs && !Scale && !(BaseGV && BaseReg);
}

Value *GetFieldAsValue(FieldName Field, Type *IntPtrTy) {
  switch (Field) {
  default:
    return nullptr;
  case BaseRegField:
    return BaseReg;
  case BaseGVField:
    return BaseGV;
  case ScaledRegField:
    return ScaledReg;
  case BaseOffsField:
    return ConstantInt::get(IntPtrTy, BaseOffs);
  }
}

void SetCombinedField(FieldName Field, Value *V,
                      const SmallVectorImpl<ExtAddrMode> &AddrModes) {
  switch (Field) {
  default:
    llvm_unreachable("Unhandled fields are expected to be rejected earlier")::llvm::llvm_unreachable_internal("Unhandled fields are expected to be rejected earlier"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2179);
    break;
  case ExtAddrMode::BaseRegField:
    BaseReg = V;
    break;
  case ExtAddrMode::BaseGVField:
    // A combined BaseGV is an Instruction, not a GlobalValue, so it goes
    // in the BaseReg field.
    assert(BaseReg == nullptr)((BaseReg == nullptr) ? static_cast<void> (0) : __assert_fail
 ("BaseReg == nullptr", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2187, __PRETTY_FUNCTION__));
    BaseReg = V;
    BaseGV = nullptr;
    break;
  case ExtAddrMode::ScaledRegField:
    ScaledReg = V;
    // If we have a mix of scaled and unscaled addrmodes then we want scale
    // to be the scale and not zero.
    if (!Scale)
      for (const ExtAddrMode &AM : AddrModes)
        if (AM.Scale) {
          Scale = AM.Scale;
          break;
        }
    break;
  case ExtAddrMode::BaseOffsField:
    // The offset is no longer a constant, so it goes in ScaledReg with a
    // scale of 1.
    assert(ScaledReg == nullptr)((ScaledReg == nullptr) ? static_cast<void> (0) : __assert_fail
 ("ScaledReg == nullptr", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2205, __PRETTY_FUNCTION__));
    ScaledReg = V;
    Scale = 1;
    BaseOffs = 0;
    break;
  }
}
2212};

2214} // end anonymous namespace

2216#ifndef NDEBUG
2217static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) {
AM.print(OS);
return OS;
2220}
2221#endif

2223#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
2224void ExtAddrMode::print(raw_ostream &OS) const {
bool NeedPlus = false;
OS << "[";
if (InBounds)
  OS << "inbounds ";
if (BaseGV) {
  OS << (NeedPlus ? " + " : "")
     << "GV:";
  BaseGV->printAsOperand(OS, /*PrintType=*/false);
  NeedPlus = true;
}

if (BaseOffs) {
  OS << (NeedPlus ? " + " : "")
     << BaseOffs;
  NeedPlus = true;
}

if (BaseReg) {
  OS << (NeedPlus ? " + " : "")
     << "Base:";
  BaseReg->printAsOperand(OS, /*PrintType=*/false);
  NeedPlus = true;
}
if (Scale) {
  OS << (NeedPlus ? " + " : "")
     << Scale << "*";
  ScaledReg->printAsOperand(OS, /*PrintType=*/false);
}

OS << ']';
2255}

2257LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void ExtAddrMode::dump() const {
print(dbgs());
dbgs() << '\n';
2260}
2261#endif

2263namespace {

2265/// This class provides transaction based operation on the IR.
2266/// Every change made through this class is recorded in the internal state and
2267/// can be undone (rollback) until commit is called.
2268class TypePromotionTransaction {
/// This represents the common interface of the individual transaction.
/// Each class implements the logic for doing one specific modification on
/// the IR via the TypePromotionTransaction.
class TypePromotionAction {
protected:
  /// The Instruction modified.
  Instruction *Inst;

public:
  /// Constructor of the action.
  /// The constructor performs the related action on the IR.
  TypePromotionAction(Instruction *Inst) : Inst(Inst) {}

  virtual ~TypePromotionAction() = default;

  /// Undo the modification done by this action.
  /// When this method is called, the IR must be in the same state as it was
  /// before this action was applied.
  /// \pre Undoing the action works if and only if the IR is in the exact same
  /// state as it was directly after this action was applied.
  virtual void undo() = 0;

  /// Advocate every change made by this action.
  /// When the results on the IR of the action are to be kept, it is important
  /// to call this function, otherwise hidden information may be kept forever.
  virtual void commit() {
    // Nothing to be done, this action is not doing anything.
  }
};

/// Utility to remember the position of an instruction.
class InsertionHandler {
  /// Position of an instruction.
  /// Either an instruction:
  /// - Is the first in a basic block: BB is used.
  /// - Has a previous instruction: PrevInst is used.
  union {
    Instruction *PrevInst;
    BasicBlock *BB;
  } Point;

  /// Remember whether or not the instruction had a previous instruction.
  bool HasPrevInstruction;

public:
  /// Record the position of \p Inst.
  InsertionHandler(Instruction *Inst) {
    BasicBlock::iterator It = Inst->getIterator();
    HasPrevInstruction = (It != (Inst->getParent()->begin()));
    if (HasPrevInstruction)
      Point.PrevInst = &*--It;
    else
      Point.BB = Inst->getParent();
  }

  /// Insert \p Inst at the recorded position.
  void insert(Instruction *Inst) {
    if (HasPrevInstruction) {
      if (Inst->getParent())
        Inst->removeFromParent();
      Inst->insertAfter(Point.PrevInst);
    } else {
      Instruction *Position = &*Point.BB->getFirstInsertionPt();
      if (Inst->getParent())
        Inst->moveBefore(Position);
      else
        Inst->insertBefore(Position);
    }
  }
};

/// Move an instruction before another.
class InstructionMoveBefore : public TypePromotionAction {
  /// Original position of the instruction.
  InsertionHandler Position;

public:
  /// Move \p Inst before \p Before.
  InstructionMoveBefore(Instruction *Inst, Instruction *Before)
      : TypePromotionAction(Inst), Position(Inst) {
    LLVM_DEBUG(dbgs() << "Do: move: " << *Inst << "\nbefore: " << *Beforedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: move: " << *
Inst << "\nbefore: " << *Before << "\n"; } }
 while (false)
                      << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: move: " << *
Inst << "\nbefore: " << *Before << "\n"; } }
 while (false);
    Inst->moveBefore(Before);
  }

  /// Move the instruction back to its original position.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: moveBefore: " << *Inst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: moveBefore: " <<
 *Inst << "\n"; } } while (false);
    Position.insert(Inst);
  }
};

/// Set the operand of an instruction with a new value.
class OperandSetter : public TypePromotionAction {
  /// Original operand of the instruction.
  Value *Origin;

  /// Index of the modified instruction.
  unsigned Idx;

public:
  /// Set \p Idx operand of \p Inst with \p NewVal.
  OperandSetter(Instruction *Inst, unsigned Idx, Value *NewVal)
      : TypePromotionAction(Inst), Idx(Idx) {
    LLVM_DEBUG(dbgs() << "Do: setOperand: " << Idx << "\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: setOperand: " <<
 Idx << "\n" << "for:" << *Inst << "\n"
 << "with:" << *NewVal << "\n"; } } while (
false)
                      << "for:" << *Inst << "\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: setOperand: " <<
 Idx << "\n" << "for:" << *Inst << "\n"
 << "with:" << *NewVal << "\n"; } } while (
false)
                      << "with:" << *NewVal << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: setOperand: " <<
 Idx << "\n" << "for:" << *Inst << "\n"
 << "with:" << *NewVal << "\n"; } } while (
false);
    Origin = Inst->getOperand(Idx);
    Inst->setOperand(Idx, NewVal);
  }

  /// Restore the original value of the instruction.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: setOperand:" << Idx << "\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: setOperand:" <<
 Idx << "\n" << "for: " << *Inst << "\n"
 << "with: " << *Origin << "\n"; } } while (
false)
                      << "for: " << *Inst << "\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: setOperand:" <<
 Idx << "\n" << "for: " << *Inst << "\n"
 << "with: " << *Origin << "\n"; } } while (
false)
                      << "with: " << *Origin << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: setOperand:" <<
 Idx << "\n" << "for: " << *Inst << "\n"
 << "with: " << *Origin << "\n"; } } while (
false);
    Inst->setOperand(Idx, Origin);
  }
};

/// Hide the operands of an instruction.
/// Do as if this instruction was not using any of its operands.
class OperandsHider : public TypePromotionAction {
  /// The list of original operands.
  SmallVector<Value *, 4> OriginalValues;

public:
  /// Remove \p Inst from the uses of the operands of \p Inst.
  OperandsHider(Instruction *Inst) : TypePromotionAction(Inst) {
    LLVM_DEBUG(dbgs() << "Do: OperandsHider: " << *Inst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: OperandsHider: " <<
 *Inst << "\n"; } } while (false);
    unsigned NumOpnds = Inst->getNumOperands();
    OriginalValues.reserve(NumOpnds);
    for (unsigned It = 0; It < NumOpnds; ++It) {
      // Save the current operand.
      Value *Val = Inst->getOperand(It);
      OriginalValues.push_back(Val);
      // Set a dummy one.
      // We could use OperandSetter here, but that would imply an overhead
      // that we are not willing to pay.
      Inst->setOperand(It, UndefValue::get(Val->getType()));
    }
  }

  /// Restore the original list of uses.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: OperandsHider: " << *Inst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: OperandsHider: "
 << *Inst << "\n"; } } while (false);
    for (unsigned It = 0, EndIt = OriginalValues.size(); It != EndIt; ++It)
      Inst->setOperand(It, OriginalValues[It]);
  }
};

/// Build a truncate instruction.
class TruncBuilder : public TypePromotionAction {
  Value *Val;

public:
  /// Build a truncate instruction of \p Opnd producing a \p Ty
  /// result.
  /// trunc Opnd to Ty.
  TruncBuilder(Instruction *Opnd, Type *Ty) : TypePromotionAction(Opnd) {
    IRBuilder<> Builder(Opnd);
    Val = Builder.CreateTrunc(Opnd, Ty, "promoted");
    LLVM_DEBUG(dbgs() << "Do: TruncBuilder: " << *Val << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: TruncBuilder: " <<
 *Val << "\n"; } } while (false);
  }

  /// Get the built value.
  Value *getBuiltValue() { return Val; }

  /// Remove the built instruction.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: TruncBuilder: " << *Val << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: TruncBuilder: " <<
 *Val << "\n"; } } while (false);
    if (Instruction *IVal = dyn_cast<Instruction>(Val))
      IVal->eraseFromParent();
  }
};

/// Build a sign extension instruction.
class SExtBuilder : public TypePromotionAction {
  Value *Val;

public:
  /// Build a sign extension instruction of \p Opnd producing a \p Ty
  /// result.
  /// sext Opnd to Ty.
  SExtBuilder(Instruction *InsertPt, Value *Opnd, Type *Ty)
      : TypePromotionAction(InsertPt) {
    IRBuilder<> Builder(InsertPt);
    Val = Builder.CreateSExt(Opnd, Ty, "promoted");
    LLVM_DEBUG(dbgs() << "Do: SExtBuilder: " << *Val << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: SExtBuilder: " <<
 *Val << "\n"; } } while (false);
  }

  /// Get the built value.
  Value *getBuiltValue() { return Val; }

  /// Remove the built instruction.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: SExtBuilder: " << *Val << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: SExtBuilder: " <<
 *Val << "\n"; } } while (false);
    if (Instruction *IVal = dyn_cast<Instruction>(Val))
      IVal->eraseFromParent();
  }
};

/// Build a zero extension instruction.
class ZExtBuilder : public TypePromotionAction {
  Value *Val;

public:
  /// Build a zero extension instruction of \p Opnd producing a \p Ty
  /// result.
  /// zext Opnd to Ty.
  ZExtBuilder(Instruction *InsertPt, Value *Opnd, Type *Ty)
      : TypePromotionAction(InsertPt) {
    IRBuilder<> Builder(InsertPt);
    Val = Builder.CreateZExt(Opnd, Ty, "promoted");
    LLVM_DEBUG(dbgs() << "Do: ZExtBuilder: " << *Val << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: ZExtBuilder: " <<
 *Val << "\n"; } } while (false);
  }

  /// Get the built value.
  Value *getBuiltValue() { return Val; }

  /// Remove the built instruction.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: ZExtBuilder: " << *Val << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: ZExtBuilder: " <<
 *Val << "\n"; } } while (false);
    if (Instruction *IVal = dyn_cast<Instruction>(Val))
      IVal->eraseFromParent();
  }
};

/// Mutate an instruction to another type.
class TypeMutator : public TypePromotionAction {
  /// Record the original type.
  Type *OrigTy;

public:
  /// Mutate the type of \p Inst into \p NewTy.
  TypeMutator(Instruction *Inst, Type *NewTy)
      : TypePromotionAction(Inst), OrigTy(Inst->getType()) {
    LLVM_DEBUG(dbgs() << "Do: MutateType: " << *Inst << " with " << *NewTydo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: MutateType: " <<
 *Inst << " with " << *NewTy << "\n"; } } while
 (false)
                      << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: MutateType: " <<
 *Inst << " with " << *NewTy << "\n"; } } while
 (false);
    Inst->mutateType(NewTy);
  }

  /// Mutate the instruction back to its original type.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: MutateType: " << *Inst << " with " << *OrigTydo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: MutateType: " <<
 *Inst << " with " << *OrigTy << "\n"; } } while
 (false)
                      << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: MutateType: " <<
 *Inst << " with " << *OrigTy << "\n"; } } while
 (false);
    Inst->mutateType(OrigTy);
  }
};

/// Replace the uses of an instruction by another instruction.
class UsesReplacer : public TypePromotionAction {
  /// Helper structure to keep track of the replaced uses.
  struct InstructionAndIdx {
    /// The instruction using the instruction.
    Instruction *Inst;

    /// The index where this instruction is used for Inst.
    unsigned Idx;

    InstructionAndIdx(Instruction *Inst, unsigned Idx)
        : Inst(Inst), Idx(Idx) {}
  };

  /// Keep track of the original uses (pair Instruction, Index).
  SmallVector<InstructionAndIdx, 4> OriginalUses;
  /// Keep track of the debug users.
  SmallVector<DbgValueInst *, 1> DbgValues;

  using use_iterator = SmallVectorImpl<InstructionAndIdx>::iterator;

public:
  /// Replace all the use of \p Inst by \p New.
  UsesReplacer(Instruction *Inst, Value *New) : TypePromotionAction(Inst) {
    LLVM_DEBUG(dbgs() << "Do: UsersReplacer: " << *Inst << " with " << *Newdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: UsersReplacer: " <<
 *Inst << " with " << *New << "\n"; } } while
 (false)
                      << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: UsersReplacer: " <<
 *Inst << " with " << *New << "\n"; } } while
 (false);
    // Record the original uses.
    for (Use &U : Inst->uses()) {
      Instruction *UserI = cast<Instruction>(U.getUser());
      OriginalUses.push_back(InstructionAndIdx(UserI, U.getOperandNo()));
    }
    // Record the debug uses separately. They are not in the instruction's
    // use list, but they are replaced by RAUW.
    findDbgValues(DbgValues, Inst);

    // Now, we can replace the uses.
    Inst->replaceAllUsesWith(New);
  }

  /// Reassign the original uses of Inst to Inst.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: UsersReplacer: " << *Inst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: UsersReplacer: "
 << *Inst << "\n"; } } while (false);
    for (use_iterator UseIt = OriginalUses.begin(),
                      EndIt = OriginalUses.end();
         UseIt != EndIt; ++UseIt) {
      UseIt->Inst->setOperand(UseIt->Idx, Inst);
    }
    // RAUW has replaced all original uses with references to the new value,
    // including the debug uses. Since we are undoing the replacements,
    // the original debug uses must also be reinstated to maintain the
    // correctness and utility of debug value instructions.
    for (auto *DVI: DbgValues) {
      LLVMContext &Ctx = Inst->getType()->getContext();
      auto *MV = MetadataAsValue::get(Ctx, ValueAsMetadata::get(Inst));
      DVI->setOperand(0, MV);
    }
  }
};

/// Remove an instruction from the IR.
class InstructionRemover : public TypePromotionAction {
  /// Original position of the instruction.
  InsertionHandler Inserter;

  /// Helper structure to hide all the link to the instruction. In other
  /// words, this helps to do as if the instruction was removed.
  OperandsHider Hider;

  /// Keep track of the uses replaced, if any.
  UsesReplacer *Replacer = nullptr;

  /// Keep track of instructions removed.
  SetOfInstrs &RemovedInsts;

public:
  /// Remove all reference of \p Inst and optionally replace all its
  /// uses with New.
  /// \p RemovedInsts Keep track of the instructions removed by this Action.
  /// \pre If !Inst->use_empty(), then New != nullptr
  InstructionRemover(Instruction *Inst, SetOfInstrs &RemovedInsts,
                     Value *New = nullptr)
      : TypePromotionAction(Inst), Inserter(Inst), Hider(Inst),
        RemovedInsts(RemovedInsts) {
    if (New)
      Replacer = new UsesReplacer(Inst, New);
    LLVM_DEBUG(dbgs() << "Do: InstructionRemover: " << *Inst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Do: InstructionRemover: "
 << *Inst << "\n"; } } while (false);
    RemovedInsts.insert(Inst);
    /// The instructions removed here will be freed after completing
    /// optimizeBlock() for all blocks as we need to keep track of the
    /// removed instructions during promotion.
    Inst->removeFromParent();
  }

  ~InstructionRemover() override { delete Replacer; }

  /// Resurrect the instruction and reassign it to the proper uses if
  /// new value was provided when build this action.
  void undo() override {
    LLVM_DEBUG(dbgs() << "Undo: InstructionRemover: " << *Inst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Undo: InstructionRemover: "
 << *Inst << "\n"; } } while (false);
    Inserter.insert(Inst);
    if (Replacer)
      Replacer->undo();
    Hider.undo();
    RemovedInsts.erase(Inst);
  }
};

2626public:
/// Restoration point.
/// The restoration point is a pointer to an action instead of an iterator
/// because the iterator may be invalidated but not the pointer.
using ConstRestorationPt = const TypePromotionAction *;

TypePromotionTransaction(SetOfInstrs &RemovedInsts)
    : RemovedInsts(RemovedInsts) {}

/// Advocate every changes made in that transaction.
void commit();

/// Undo all the changes made after the given point.
void rollback(ConstRestorationPt Point);

/// Get the current restoration point.
ConstRestorationPt getRestorationPoint() const;

/// \name API for IR modification with state keeping to support rollback.
/// @{
/// Same as Instruction::setOperand.
void setOperand(Instruction *Inst, unsigned Idx, Value *NewVal);

/// Same as Instruction::eraseFromParent.
void eraseInstruction(Instruction *Inst, Value *NewVal = nullptr);

/// Same as Value::replaceAllUsesWith.
void replaceAllUsesWith(Instruction *Inst, Value *New);

/// Same as Value::mutateType.
void mutateType(Instruction *Inst, Type *NewTy);

/// Same as IRBuilder::createTrunc.
Value *createTrunc(Instruction *Opnd, Type *Ty);

/// Same as IRBuilder::createSExt.
Value *createSExt(Instruction *Inst, Value *Opnd, Type *Ty);

/// Same as IRBuilder::createZExt.
Value *createZExt(Instruction *Inst, Value *Opnd, Type *Ty);

/// Same as Instruction::moveBefore.
void moveBefore(Instruction *Inst, Instruction *Before);
/// @}

2671private:
/// The ordered list of actions made so far.
SmallVector<std::unique_ptr<TypePromotionAction>, 16> Actions;

using CommitPt = SmallVectorImpl<std::unique_ptr<TypePromotionAction>>::iterator;

SetOfInstrs &RemovedInsts;
2678};

2680} // end anonymous namespace

2682void TypePromotionTransaction::setOperand(Instruction *Inst, unsigned Idx,
                                        Value *NewVal) {
Actions.push_back(std::make_unique<TypePromotionTransaction::OperandSetter>(
    Inst, Idx, NewVal));
2686}

2688void TypePromotionTransaction::eraseInstruction(Instruction *Inst,
                                              Value *NewVal) {
Actions.push_back(
    std::make_unique<TypePromotionTransaction::InstructionRemover>(
        Inst, RemovedInsts, NewVal));
2693}

2695void TypePromotionTransaction::replaceAllUsesWith(Instruction *Inst,
                                                Value *New) {
Actions.push_back(
    std::make_unique<TypePromotionTransaction::UsesReplacer>(Inst, New));
2699}

2701void TypePromotionTransaction::mutateType(Instruction *Inst, Type *NewTy) {
Actions.push_back(
    std::make_unique<TypePromotionTransaction::TypeMutator>(Inst, NewTy));
2704}

2706Value *TypePromotionTransaction::createTrunc(Instruction *Opnd,
                                           Type *Ty) {
std::unique_ptr<TruncBuilder> Ptr(new TruncBuilder(Opnd, Ty));
Value *Val = Ptr->getBuiltValue();
Actions.push_back(std::move(Ptr));
return Val;
2712}

2714Value *TypePromotionTransaction::createSExt(Instruction *Inst,
                                          Value *Opnd, Type *Ty) {
std::unique_ptr<SExtBuilder> Ptr(new SExtBuilder(Inst, Opnd, Ty));
Value *Val = Ptr->getBuiltValue();
Actions.push_back(std::move(Ptr));
return Val;
2720}

2722Value *TypePromotionTransaction::createZExt(Instruction *Inst,
                                          Value *Opnd, Type *Ty) {
std::unique_ptr<ZExtBuilder> Ptr(new ZExtBuilder(Inst, Opnd, Ty));
Value *Val = Ptr->getBuiltValue();
Actions.push_back(std::move(Ptr));
return Val;
2728}

2730void TypePromotionTransaction::moveBefore(Instruction *Inst,
                                        Instruction *Before) {
Actions.push_back(
    std::make_unique<TypePromotionTransaction::InstructionMoveBefore>(
        Inst, Before));
2735}

2737TypePromotionTransaction::ConstRestorationPt
2738TypePromotionTransaction::getRestorationPoint() const {
return !Actions.empty() ? Actions.back().get() : nullptr;
2740}

2742void TypePromotionTransaction::commit() {
for (CommitPt It = Actions.begin(), EndIt = Actions.end(); It != EndIt;
     ++It)
  (*It)->commit();
Actions.clear();
2747}

2749void TypePromotionTransaction::rollback(
  TypePromotionTransaction::ConstRestorationPt Point) {
while (!Actions.empty() && Point != Actions.back().get()) {
  std::unique_ptr<TypePromotionAction> Curr = Actions.pop_back_val();
  Curr->undo();
}
2755}

2757namespace {

2759/// A helper class for matching addressing modes.
2760///
2761/// This encapsulates the logic for matching the target-legal addressing modes.
2762class AddressingModeMatcher {
SmallVectorImpl<Instruction*> &AddrModeInsts;
const TargetLowering &TLI;
const TargetRegisterInfo &TRI;
const DataLayout &DL;

/// AccessTy/MemoryInst - This is the type for the access (e.g. double) and
/// the memory instruction that we're computing this address for.
Type *AccessTy;
unsigned AddrSpace;
Instruction *MemoryInst;

/// This is the addressing mode that we're building up. This is
/// part of the return value of this addressing mode matching stuff.
ExtAddrMode &AddrMode;

/// The instructions inserted by other CodeGenPrepare optimizations.
const SetOfInstrs &InsertedInsts;

/// A map from the instructions to their type before promotion.
InstrToOrigTy &PromotedInsts;

/// The ongoing transaction where every action should be registered.
TypePromotionTransaction &TPT;

// A GEP which has too large offset to be folded into the addressing mode.
std::pair<AssertingVH<GetElementPtrInst>, int64_t> &LargeOffsetGEP;

/// This is set to true when we should not do profitability checks.
/// When true, IsProfitableToFoldIntoAddressingMode always returns true.
bool IgnoreProfitability;

AddressingModeMatcher(
    SmallVectorImpl<Instruction *> &AMI, const TargetLowering &TLI,
    const TargetRegisterInfo &TRI, Type *AT, unsigned AS, Instruction *MI,
    ExtAddrMode &AM, const SetOfInstrs &InsertedInsts,
    InstrToOrigTy &PromotedInsts, TypePromotionTransaction &TPT,
    std::pair<AssertingVH<GetElementPtrInst>, int64_t> &LargeOffsetGEP)
    : AddrModeInsts(AMI), TLI(TLI), TRI(TRI),
      DL(MI->getModule()->getDataLayout()), AccessTy(AT), AddrSpace(AS),
      MemoryInst(MI), AddrMode(AM), InsertedInsts(InsertedInsts),
      PromotedInsts(PromotedInsts), TPT(TPT), LargeOffsetGEP(LargeOffsetGEP) {
  IgnoreProfitability = false;
}

2807public:
/// Find the maximal addressing mode that a load/store of V can fold,
/// give an access type of AccessTy.  This returns a list of involved
/// instructions in AddrModeInsts.
/// \p InsertedInsts The instructions inserted by other CodeGenPrepare
/// optimizations.
/// \p PromotedInsts maps the instructions to their type before promotion.
/// \p The ongoing transaction where every action should be registered.
static ExtAddrMode
Match(Value *V, Type *AccessTy, unsigned AS, Instruction *MemoryInst,
      SmallVectorImpl<Instruction *> &AddrModeInsts,
      const TargetLowering &TLI, const TargetRegisterInfo &TRI,
      const SetOfInstrs &InsertedInsts, InstrToOrigTy &PromotedInsts,
      TypePromotionTransaction &TPT,
      std::pair<AssertingVH<GetElementPtrInst>, int64_t> &LargeOffsetGEP) {
  ExtAddrMode Result;

  bool Success = AddressingModeMatcher(AddrModeInsts, TLI, TRI, AccessTy, AS,
                                       MemoryInst, Result, InsertedInsts,
                                       PromotedInsts, TPT, LargeOffsetGEP)
                     .matchAddr(V, 0);
  (void)Success; assert(Success && "Couldn't select *anything*?")((Success && "Couldn't select *anything*?") ? static_cast
<void> (0) : __assert_fail ("Success && \"Couldn't select *anything*?\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2828, __PRETTY_FUNCTION__));
  return Result;
}

2832private:
bool matchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth);
bool matchAddr(Value *Addr, unsigned Depth);
bool matchOperationAddr(User *AddrInst, unsigned Opcode, unsigned Depth,
                        bool *MovedAway = nullptr);
bool isProfitableToFoldIntoAddressingMode(Instruction *I,
                                          ExtAddrMode &AMBefore,
                                          ExtAddrMode &AMAfter);
bool valueAlreadyLiveAtInst(Value *Val, Value *KnownLive1, Value *KnownLive2);
bool isPromotionProfitable(unsigned NewCost, unsigned OldCost,
                           Value *PromotedOperand) const;
2843};

2845class PhiNodeSet;

2847/// An iterator for PhiNodeSet.
2848class PhiNodeSetIterator {
PhiNodeSet * const Set;
size_t CurrentIndex = 0;

2852public:
/// The constructor. Start should point to either a valid element, or be equal
/// to the size of the underlying SmallVector of the PhiNodeSet.
PhiNodeSetIterator(PhiNodeSet * const Set, size_t Start);
PHINode * operator*() const;
PhiNodeSetIterator& operator++();
bool operator==(const PhiNodeSetIterator &RHS) const;
bool operator!=(const PhiNodeSetIterator &RHS) const;
2860};

2862/// Keeps a set of PHINodes.
2863///
2864/// This is a minimal set implementation for a specific use case:
2865/// It is very fast when there are very few elements, but also provides good
2866/// performance when there are many. It is similar to SmallPtrSet, but also
2867/// provides iteration by insertion order, which is deterministic and stable
2868/// across runs. It is also similar to SmallSetVector, but provides removing
2869/// elements in O(1) time. This is achieved by not actually removing the element
2870/// from the underlying vector, so comes at the cost of using more memory, but
2871/// that is fine, since PhiNodeSets are used as short lived objects.
2872class PhiNodeSet {
friend class PhiNodeSetIterator;

using MapType = SmallDenseMap<PHINode *, size_t, 32>;
using iterator =  PhiNodeSetIterator;

/// Keeps the elements in the order of their insertion in the underlying
/// vector. To achieve constant time removal, it never deletes any element.
SmallVector<PHINode *, 32> NodeList;

/// Keeps the elements in the underlying set implementation. This (and not the
/// NodeList defined above) is the source of truth on whether an element
/// is actually in the collection.
MapType NodeMap;

/// Points to the first valid (not deleted) element when the set is not empty
/// and the value is not zero. Equals to the size of the underlying vector
/// when the set is empty. When the value is 0, as in the beginning, the
/// first element may or may not be valid.
size_t FirstValidElement = 0;

2893public:
/// Inserts a new element to the collection.
/// \returns true if the element is actually added, i.e. was not in the
/// collection before the operation.
bool insert(PHINode *Ptr) {
  if (NodeMap.insert(std::make_pair(Ptr, NodeList.size())).second) {
    NodeList.push_back(Ptr);
    return true;
  }
  return false;
}

/// Removes the element from the collection.
/// \returns whether the element is actually removed, i.e. was in the
/// collection before the operation.
bool erase(PHINode *Ptr) {
  auto it = NodeMap.find(Ptr);
  if (it != NodeMap.end()) {
    NodeMap.erase(Ptr);
    SkipRemovedElements(FirstValidElement);
    return true;
  }
  return false;
}

/// Removes all elements and clears the collection.
void clear() {
  NodeMap.clear();
  NodeList.clear();
  FirstValidElement = 0;
}

/// \returns an iterator that will iterate the elements in the order of
/// insertion.
iterator begin() {
  if (FirstValidElement == 0)
    SkipRemovedElements(FirstValidElement);
  return PhiNodeSetIterator(this, FirstValidElement);
}

/// \returns an iterator that points to the end of the collection.
iterator end() { return PhiNodeSetIterator(this, NodeList.size()); }

/// Returns the number of elements in the collection.
size_t size() const {
  return NodeMap.size();
}

/// \returns 1 if the given element is in the collection, and 0 if otherwise.
size_t count(PHINode *Ptr) const {
  return NodeMap.count(Ptr);
}

2946private:
/// Updates the CurrentIndex so that it will point to a valid element.
///
/// If the element of NodeList at CurrentIndex is valid, it does not
/// change it. If there are no more valid elements, it updates CurrentIndex
/// to point to the end of the NodeList.
void SkipRemovedElements(size_t &CurrentIndex) {
  while (CurrentIndex < NodeList.size()) {
    auto it = NodeMap.find(NodeList[CurrentIndex]);
    // If the element has been deleted and added again later, NodeMap will
    // point to a different index, so CurrentIndex will still be invalid.
    if (it != NodeMap.end() && it->second == CurrentIndex)
      break;
    ++CurrentIndex;
  }
}
2962};

2964PhiNodeSetIterator::PhiNodeSetIterator(PhiNodeSet *const Set, size_t Start)
  : Set(Set), CurrentIndex(Start) {}

2967PHINode * PhiNodeSetIterator::operator*() const {
assert(CurrentIndex < Set->NodeList.size() &&((CurrentIndex < Set->NodeList.size() && "PhiNodeSet access out of range"
) ? static_cast<void> (0) : __assert_fail ("CurrentIndex < Set->NodeList.size() && \"PhiNodeSet access out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2969, __PRETTY_FUNCTION__))
       "PhiNodeSet access out of range")((CurrentIndex < Set->NodeList.size() && "PhiNodeSet access out of range"
) ? static_cast<void> (0) : __assert_fail ("CurrentIndex < Set->NodeList.size() && \"PhiNodeSet access out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2969, __PRETTY_FUNCTION__));
return Set->NodeList[CurrentIndex];
2971}

2973PhiNodeSetIterator& PhiNodeSetIterator::operator++() {
assert(CurrentIndex < Set->NodeList.size() &&((CurrentIndex < Set->NodeList.size() && "PhiNodeSet access out of range"
) ? static_cast<void> (0) : __assert_fail ("CurrentIndex < Set->NodeList.size() && \"PhiNodeSet access out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2975, __PRETTY_FUNCTION__))
       "PhiNodeSet access out of range")((CurrentIndex < Set->NodeList.size() && "PhiNodeSet access out of range"
) ? static_cast<void> (0) : __assert_fail ("CurrentIndex < Set->NodeList.size() && \"PhiNodeSet access out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 2975, __PRETTY_FUNCTION__));
++CurrentIndex;
Set->SkipRemovedElements(CurrentIndex);
return *this;
2979}

2981bool PhiNodeSetIterator::operator==(const PhiNodeSetIterator &RHS) const {
return CurrentIndex == RHS.CurrentIndex;
2983}

2985bool PhiNodeSetIterator::operator!=(const PhiNodeSetIterator &RHS) const {
return !((*this) == RHS);
2987}

2989/// Keep track of simplification of Phi nodes.
2990/// Accept the set of all phi nodes and erase phi node from this set
2991/// if it is simplified.
2992class SimplificationTracker {
DenseMap<Value *, Value *> Storage;
const SimplifyQuery &SQ;
// Tracks newly created Phi nodes. The elements are iterated by insertion
// order.
PhiNodeSet AllPhiNodes;
// Tracks newly created Select nodes.
SmallPtrSet<SelectInst *, 32> AllSelectNodes;

3001public:
SimplificationTracker(const SimplifyQuery &sq)
    : SQ(sq) {}

Value *Get(Value *V) {
  do {
    auto SV = Storage.find(V);
    if (SV == Storage.end())
      return V;
    V = SV->second;
  } while (true);
}

Value *Simplify(Value *Val) {
  SmallVector<Value *, 32> WorkList;
  SmallPtrSet<Value *, 32> Visited;
  WorkList.push_back(Val);
  while (!WorkList.empty()) {
    auto P = WorkList.pop_back_val();
    if (!Visited.insert(P).second)
      continue;
    if (auto *PI = dyn_cast<Instruction>(P))
      if (Value *V = SimplifyInstruction(cast<Instruction>(PI), SQ)) {
        for (auto *U : PI->users())
          WorkList.push_back(cast<Value>(U));
        Put(PI, V);
        PI->replaceAllUsesWith(V);
        if (auto *PHI = dyn_cast<PHINode>(PI))
          AllPhiNodes.erase(PHI);
        if (auto *Select = dyn_cast<SelectInst>(PI))
          AllSelectNodes.erase(Select);
        PI->eraseFromParent();
      }
  }
  return Get(Val);
}

void Put(Value *From, Value *To) {
  Storage.insert({ From, To });
}

void ReplacePhi(PHINode *From, PHINode *To) {
  Value* OldReplacement = Get(From);
  while (OldReplacement != From) {
    From = To;
    To = dyn_cast<PHINode>(OldReplacement);
    OldReplacement = Get(From);
  }
  assert(Get(To) == To && "Replacement PHI node is already replaced.")((Get(To) == To && "Replacement PHI node is already replaced."
) ? static_cast<void> (0) : __assert_fail ("Get(To) == To && \"Replacement PHI node is already replaced.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3049, __PRETTY_FUNCTION__));
  Put(From, To);
  From->replaceAllUsesWith(To);
  AllPhiNodes.erase(From);
  From->eraseFromParent();
}

PhiNodeSet& newPhiNodes() { return AllPhiNodes; }

void insertNewPhi(PHINode *PN) { AllPhiNodes.insert(PN); }

void insertNewSelect(SelectInst *SI) { AllSelectNodes.insert(SI); }

unsigned countNewPhiNodes() const { return AllPhiNodes.size(); }

unsigned countNewSelectNodes() const { return AllSelectNodes.size(); }

void destroyNewNodes(Type *CommonType) {
  // For safe erasing, replace the uses with dummy value first.
  auto Dummy = UndefValue::get(CommonType);
  for (auto I : AllPhiNodes) {
    I->replaceAllUsesWith(Dummy);
    I->eraseFromParent();
  }
  AllPhiNodes.clear();
  for (auto I : AllSelectNodes) {
    I->replaceAllUsesWith(Dummy);
    I->eraseFromParent();
  }
  AllSelectNodes.clear();
}
3080};

3082/// A helper class for combining addressing modes.
3083class AddressingModeCombiner {
typedef DenseMap<Value *, Value *> FoldAddrToValueMapping;
typedef std::pair<PHINode *, PHINode *> PHIPair;

3087private:
/// The addressing modes we've collected.
SmallVector<ExtAddrMode, 16> AddrModes;

/// The field in which the AddrModes differ, when we have more than one.
ExtAddrMode::FieldName DifferentField = ExtAddrMode::NoField;

/// Are the AddrModes that we have all just equal to their original values?
bool AllAddrModesTrivial = true;

/// Common Type for all different fields in addressing modes.
Type *CommonType;

/// SimplifyQuery for simplifyInstruction utility.
const SimplifyQuery &SQ;

/// Original Address.
Value *Original;

3106public:
AddressingModeCombiner(const SimplifyQuery &_SQ, Value *OriginalValue)
    : CommonType(nullptr), SQ(_SQ), Original(OriginalValue) {}

/// Get the combined AddrMode
const ExtAddrMode &getAddrMode() const {
  return AddrModes[0];
}

/// Add a new AddrMode if it's compatible with the AddrModes we already
/// have.
/// \return True iff we succeeded in doing so.
bool addNewAddrMode(ExtAddrMode &NewAddrMode) {
  // Take note of if we have any non-trivial AddrModes, as we need to detect
  // when all AddrModes are trivial as then we would introduce a phi or select
  // which just duplicates what's already there.
  AllAddrModesTrivial = AllAddrModesTrivial && NewAddrMode.isTrivial();

  // If this is the first addrmode then everything is fine.
  if (AddrModes.empty()) {
    AddrModes.emplace_back(NewAddrMode);
    return true;
  }

  // Figure out how different this is from the other address modes, which we
  // can do just by comparing against the first one given that we only care
  // about the cumulative difference.
  ExtAddrMode::FieldName ThisDifferentField =
    AddrModes[0].compare(NewAddrMode);
  if (DifferentField == ExtAddrMode::NoField)
    DifferentField = ThisDifferentField;
  else if (DifferentField != ThisDifferentField)
    DifferentField = ExtAddrMode::MultipleFields;

  // If NewAddrMode differs in more than one dimension we cannot handle it.
  bool CanHandle = DifferentField != ExtAddrMode::MultipleFields;

  // If Scale Field is different then we reject.
  CanHandle = CanHandle && DifferentField != ExtAddrMode::ScaleField;

  // We also must reject the case when base offset is different and
  // scale reg is not null, we cannot handle this case due to merge of
  // different offsets will be used as ScaleReg.
  CanHandle = CanHandle && (DifferentField != ExtAddrMode::BaseOffsField ||
                            !NewAddrMode.ScaledReg);

  // We also must reject the case when GV is different and BaseReg installed
  // due to we want to use base reg as a merge of GV values.
  CanHandle = CanHandle && (DifferentField != ExtAddrMode::BaseGVField ||
                            !NewAddrMode.HasBaseReg);

  // Even if NewAddMode is the same we still need to collect it due to
  // original value is different. And later we will need all original values
  // as anchors during finding the common Phi node.
  if (CanHandle)
    AddrModes.emplace_back(NewAddrMode);
  else
    AddrModes.clear();

  return CanHandle;
}

/// Combine the addressing modes we've collected into a single
/// addressing mode.
/// \return True iff we successfully combined them or we only had one so
/// didn't need to combine them anyway.
bool combineAddrModes() {
  // If we have no AddrModes then they can't be combined.
  if (AddrModes.size() == 0)
    return false;

  // A single AddrMode can trivially be combined.
  if (AddrModes.size() == 1 || DifferentField == ExtAddrMode::NoField)
    return true;

  // If the AddrModes we collected are all just equal to the value they are
  // derived from then combining them wouldn't do anything useful.
  if (AllAddrModesTrivial)
    return false;

  if (!addrModeCombiningAllowed())
    return false;

  // Build a map between <original value, basic block where we saw it> to
  // value of base register.
  // Bail out if there is no common type.
  FoldAddrToValueMapping Map;
  if (!initializeMap(Map))
    return false;

  Value *CommonValue = findCommon(Map);
  if (CommonValue)
    AddrModes[0].SetCombinedField(DifferentField, CommonValue, AddrModes);
  return CommonValue != nullptr;
}

3202private:
/// Initialize Map with anchor values. For address seen
/// we set the value of different field saw in this address.
/// At the same time we find a common type for different field we will
/// use to create new Phi/Select nodes. Keep it in CommonType field.
/// Return false if there is no common type found.
bool initializeMap(FoldAddrToValueMapping &Map) {
  // Keep track of keys where the value is null. We will need to replace it
  // with constant null when we know the common type.
  SmallVector<Value *, 2> NullValue;
  Type *IntPtrTy = SQ.DL.getIntPtrType(AddrModes[0].OriginalValue->getType());
  for (auto &AM : AddrModes) {
    Value *DV = AM.GetFieldAsValue(DifferentField, IntPtrTy);
    if (DV) {
      auto *Type = DV->getType();
      if (CommonType && CommonType != Type)
        return false;
      CommonType = Type;
      Map[AM.OriginalValue] = DV;
    } else {
      NullValue.push_back(AM.OriginalValue);
    }
  }
  assert(CommonType && "At least one non-null value must be!")((CommonType && "At least one non-null value must be!"
) ? static_cast<void> (0) : __assert_fail ("CommonType && \"At least one non-null value must be!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3225, __PRETTY_FUNCTION__));
  for (auto *V : NullValue)
    Map[V] = Constant::getNullValue(CommonType);
  return true;
}

/// We have mapping between value A and other value B where B was a field in
/// addressing mode represented by A. Also we have an original value C
/// representing an address we start with. Traversing from C through phi and
/// selects we ended up with A's in a map. This utility function tries to find
/// a value V which is a field in addressing mode C and traversing through phi
/// nodes and selects we will end up in corresponded values B in a map.
/// The utility will create a new Phi/Selects if needed.
// The simple example looks as follows:
// BB1:
//   p1 = b1 + 40
//   br cond BB2, BB3
// BB2:
//   p2 = b2 + 40
//   br BB3
// BB3:
//   p = phi [p1, BB1], [p2, BB2]
//   v = load p
// Map is
//   p1 -> b1
//   p2 -> b2
// Request is
//   p -> ?
// The function tries to find or build phi [b1, BB1], [b2, BB2] in BB3.
Value *findCommon(FoldAddrToValueMapping &Map) {
  // Tracks the simplification of newly created phi nodes. The reason we use
  // this mapping is because we will add new created Phi nodes in AddrToBase.
  // Simplification of Phi nodes is recursive, so some Phi node may
  // be simplified after we added it to AddrToBase. In reality this
  // simplification is possible only if original phi/selects were not
  // simplified yet.
  // Using this mapping we can find the current value in AddrToBase.
  SimplificationTracker ST(SQ);

  // First step, DFS to create PHI nodes for all intermediate blocks.
  // Also fill traverse order for the second step.
  SmallVector<Value *, 32> TraverseOrder;
  InsertPlaceholders(Map, TraverseOrder, ST);

  // Second Step, fill new nodes by merged values and simplify if possible.
  FillPlaceholders(Map, TraverseOrder, ST);

  if (!AddrSinkNewSelects && ST.countNewSelectNodes() > 0) {
    ST.destroyNewNodes(CommonType);
    return nullptr;
  }

  // Now we'd like to match New Phi nodes to existed ones.
  unsigned PhiNotMatchedCount = 0;
  if (!MatchPhiSet(ST, AddrSinkNewPhis, PhiNotMatchedCount)) {
    ST.destroyNewNodes(CommonType);
    return nullptr;
  }

  auto *Result = ST.Get(Map.find(Original)->second);
  if (Result) {
    NumMemoryInstsPhiCreated += ST.countNewPhiNodes() + PhiNotMatchedCount;
    NumMemoryInstsSelectCreated += ST.countNewSelectNodes();
  }
  return Result;
}

/// Try to match PHI node to Candidate.
/// Matcher tracks the matched Phi nodes.
bool MatchPhiNode(PHINode *PHI, PHINode *Candidate,
                  SmallSetVector<PHIPair, 8> &Matcher,
                  PhiNodeSet &PhiNodesToMatch) {
  SmallVector<PHIPair, 8> WorkList;
  Matcher.insert({ PHI, Candidate });
  SmallSet<PHINode *, 8> MatchedPHIs;
  MatchedPHIs.insert(PHI);
  WorkList.push_back({ PHI, Candidate });
  SmallSet<PHIPair, 8> Visited;
  while (!WorkList.empty()) {
    auto Item = WorkList.pop_back_val();
    if (!Visited.insert(Item).second)
      continue;
    // We iterate over all incoming values to Phi to compare them.
    // If values are different and both of them Phi and the first one is a
    // Phi we added (subject to match) and both of them is in the same basic
    // block then we can match our pair if values match. So we state that
    // these values match and add it to work list to verify that.
    for (auto B : Item.first->blocks()) {
      Value *FirstValue = Item.first->getIncomingValueForBlock(B);
      Value *SecondValue = Item.second->getIncomingValueForBlock(B);
      if (FirstValue == SecondValue)
        continue;

      PHINode *FirstPhi = dyn_cast<PHINode>(FirstValue);
      PHINode *SecondPhi = dyn_cast<PHINode>(SecondValue);

      // One of them is not Phi or
      // The first one is not Phi node from the set we'd like to match or
      // Phi nodes from different basic blocks then
      // we will not be able to match.
      if (!FirstPhi || !SecondPhi || !PhiNodesToMatch.count(FirstPhi) ||
          FirstPhi->getParent() != SecondPhi->getParent())
        return false;

      // If we already matched them then continue.
      if (Matcher.count({ FirstPhi, SecondPhi }))
        continue;
      // So the values are different and does not match. So we need them to
      // match. (But we register no more than one match per PHI node, so that
      // we won't later try to replace them twice.)
      if (MatchedPHIs.insert(FirstPhi).second)
        Matcher.insert({ FirstPhi, SecondPhi });
      // But me must check it.
      WorkList.push_back({ FirstPhi, SecondPhi });
    }
  }
  return true;
}

/// For the given set of PHI nodes (in the SimplificationTracker) try
/// to find their equivalents.
/// Returns false if this matching fails and creation of new Phi is disabled.
bool MatchPhiSet(SimplificationTracker &ST, bool AllowNewPhiNodes,
                 unsigned &PhiNotMatchedCount) {
  // Matched and PhiNodesToMatch iterate their elements in a deterministic
  // order, so the replacements (ReplacePhi) are also done in a deterministic
  // order.
  SmallSetVector<PHIPair, 8> Matched;
  SmallPtrSet<PHINode *, 8> WillNotMatch;
  PhiNodeSet &PhiNodesToMatch = ST.newPhiNodes();
  while (PhiNodesToMatch.size()) {
    PHINode *PHI = *PhiNodesToMatch.begin();

    // Add us, if no Phi nodes in the basic block we do not match.
    WillNotMatch.clear();
    WillNotMatch.insert(PHI);

    // Traverse all Phis until we found equivalent or fail to do that.
    bool IsMatched = false;
    for (auto &P : PHI->getParent()->phis()) {
      if (&P == PHI)
        continue;
      if ((IsMatched = MatchPhiNode(PHI, &P, Matched, PhiNodesToMatch)))
        break;
      // If it does not match, collect all Phi nodes from matcher.
      // if we end up with no match, them all these Phi nodes will not match
      // later.
      for (auto M : Matched)
        WillNotMatch.insert(M.first);
      Matched.clear();
    }
    if (IsMatched) {
      // Replace all matched values and erase them.
      for (auto MV : Matched)
        ST.ReplacePhi(MV.first, MV.second);
      Matched.clear();
      continue;
    }
    // If we are not allowed to create new nodes then bail out.
    if (!AllowNewPhiNodes)
      return false;
    // Just remove all seen values in matcher. They will not match anything.
    PhiNotMatchedCount += WillNotMatch.size();
    for (auto *P : WillNotMatch)
      PhiNodesToMatch.erase(P);
  }
  return true;
}
/// Fill the placeholders with values from predecessors and simplify them.
void FillPlaceholders(FoldAddrToValueMapping &Map,
                      SmallVectorImpl<Value *> &TraverseOrder,
                      SimplificationTracker &ST) {
  while (!TraverseOrder.empty()) {
    Value *Current = TraverseOrder.pop_back_val();
    assert(Map.find(Current) != Map.end() && "No node to fill!!!")((Map.find(Current) != Map.end() && "No node to fill!!!"
) ? static_cast<void> (0) : __assert_fail ("Map.find(Current) != Map.end() && \"No node to fill!!!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3399, __PRETTY_FUNCTION__));
    Value *V = Map[Current];

    if (SelectInst *Select = dyn_cast<SelectInst>(V)) {
      // CurrentValue also must be Select.
      auto *CurrentSelect = cast<SelectInst>(Current);
      auto *TrueValue = CurrentSelect->getTrueValue();
      assert(Map.find(TrueValue) != Map.end() && "No True Value!")((Map.find(TrueValue) != Map.end() && "No True Value!"
) ? static_cast<void> (0) : __assert_fail ("Map.find(TrueValue) != Map.end() && \"No True Value!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3406, __PRETTY_FUNCTION__));
      Select->setTrueValue(ST.Get(Map[TrueValue]));
      auto *FalseValue = CurrentSelect->getFalseValue();
      assert(Map.find(FalseValue) != Map.end() && "No False Value!")((Map.find(FalseValue) != Map.end() && "No False Value!"
) ? static_cast<void> (0) : __assert_fail ("Map.find(FalseValue) != Map.end() && \"No False Value!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3409, __PRETTY_FUNCTION__));
      Select->setFalseValue(ST.Get(Map[FalseValue]));
    } else {
      // Must be a Phi node then.
      PHINode *PHI = cast<PHINode>(V);
      auto *CurrentPhi = dyn_cast<PHINode>(Current);
      // Fill the Phi node with values from predecessors.
      for (auto B : predecessors(PHI->getParent())) {
        Value *PV = CurrentPhi->getIncomingValueForBlock(B);
        assert(Map.find(PV) != Map.end() && "No predecessor Value!")((Map.find(PV) != Map.end() && "No predecessor Value!"
) ? static_cast<void> (0) : __assert_fail ("Map.find(PV) != Map.end() && \"No predecessor Value!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3418, __PRETTY_FUNCTION__));
        PHI->addIncoming(ST.Get(Map[PV]), B);
      }
    }
    Map[Current] = ST.Simplify(V);
  }
}

/// Starting from original value recursively iterates over def-use chain up to
/// known ending values represented in a map. For each traversed phi/select
/// inserts a placeholder Phi or Select.
/// Reports all new created Phi/Select nodes by adding them to set.
/// Also reports and order in what values have been traversed.
void InsertPlaceholders(FoldAddrToValueMapping &Map,
                        SmallVectorImpl<Value *> &TraverseOrder,
                        SimplificationTracker &ST) {
  SmallVector<Value *, 32> Worklist;
  assert((isa<PHINode>(Original) || isa<SelectInst>(Original)) &&(((isa<PHINode>(Original) || isa<SelectInst>(Original
)) && "Address must be a Phi or Select node") ? static_cast
<void> (0) : __assert_fail ("(isa<PHINode>(Original) || isa<SelectInst>(Original)) && \"Address must be a Phi or Select node\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3436, __PRETTY_FUNCTION__))
         "Address must be a Phi or Select node")(((isa<PHINode>(Original) || isa<SelectInst>(Original
)) && "Address must be a Phi or Select node") ? static_cast
<void> (0) : __assert_fail ("(isa<PHINode>(Original) || isa<SelectInst>(Original)) && \"Address must be a Phi or Select node\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3436, __PRETTY_FUNCTION__));
  auto *Dummy = UndefValue::get(CommonType);
  Worklist.push_back(Original);
  while (!Worklist.empty()) {
    Value *Current = Worklist.pop_back_val();
    // if it is already visited or it is an ending value then skip it.
    if (Map.find(Current) != Map.end())
      continue;
    TraverseOrder.push_back(Current);

    // CurrentValue must be a Phi node or select. All others must be covered
    // by anchors.
    if (SelectInst *CurrentSelect = dyn_cast<SelectInst>(Current)) {
      // Is it OK to get metadata from OrigSelect?!
      // Create a Select placeholder with dummy value.
      SelectInst *Select = SelectInst::Create(
          CurrentSelect->getCondition(), Dummy, Dummy,
          CurrentSelect->getName(), CurrentSelect, CurrentSelect);
      Map[Current] = Select;
      ST.insertNewSelect(Select);
      // We are interested in True and False values.
      Worklist.push_back(CurrentSelect->getTrueValue());
      Worklist.push_back(CurrentSelect->getFalseValue());
    } else {
      // It must be a Phi node then.
      PHINode *CurrentPhi = cast<PHINode>(Current);
      unsigned PredCount = CurrentPhi->getNumIncomingValues();
      PHINode *PHI =
          PHINode::Create(CommonType, PredCount, "sunk_phi", CurrentPhi);
      Map[Current] = PHI;
      ST.insertNewPhi(PHI);
      for (Value *P : CurrentPhi->incoming_values())
        Worklist.push_back(P);
    }
  }
}

bool addrModeCombiningAllowed() {
  if (DisableComplexAddrModes)
    return false;
  switch (DifferentField) {
  default:
    return false;
  case ExtAddrMode::BaseRegField:
    return AddrSinkCombineBaseReg;
  case ExtAddrMode::BaseGVField:
    return AddrSinkCombineBaseGV;
  case ExtAddrMode::BaseOffsField:
    return AddrSinkCombineBaseOffs;
  case ExtAddrMode::ScaledRegField:
    return AddrSinkCombineScaledReg;
  }
}
3489};
3490} // end anonymous namespace

3492/// Try adding ScaleReg*Scale to the current addressing mode.
3493/// Return true and update AddrMode if this addr mode is legal for the target,
3494/// false if not.
3495bool AddressingModeMatcher::matchScaledValue(Value *ScaleReg, int64_t Scale,
                                           unsigned Depth) {
// If Scale is 1, then this is the same as adding ScaleReg to the addressing
// mode.  Just process that directly.
if (Scale == 1)
  return matchAddr(ScaleReg, Depth);

// If the scale is 0, it takes nothing to add this.
if (Scale == 0)
  return true;

// If we already have a scale of this value, we can add to it, otherwise, we
// need an available scale field.
if (AddrMode.Scale != 0 && AddrMode.ScaledReg != ScaleReg)
  return false;

ExtAddrMode TestAddrMode = AddrMode;

// Add scale to turn X*4+X*3 -> X*7.  This could also do things like
// [A+B + A*7] -> [B+A*8].
TestAddrMode.Scale += Scale;
TestAddrMode.ScaledReg = ScaleReg;

// If the new address isn't legal, bail out.
if (!TLI.isLegalAddressingMode(DL, TestAddrMode, AccessTy, AddrSpace))
  return false;

// It was legal, so commit it.
AddrMode = TestAddrMode;

// Okay, we decided that we can add ScaleReg+Scale to AddrMode.  Check now
// to see if ScaleReg is actually X+C.  If so, we can turn this into adding
// X*Scale + C*Scale to addr mode.
ConstantInt *CI = nullptr; Value *AddLHS = nullptr;
if (isa<Instruction>(ScaleReg) &&  // not a constant expr.
    match(ScaleReg, m_Add(m_Value(AddLHS), m_ConstantInt(CI)))) {
  TestAddrMode.InBounds = false;
  TestAddrMode.ScaledReg = AddLHS;
  TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale;

  // If this addressing mode is legal, commit it and remember that we folded
  // this instruction.
  if (TLI.isLegalAddressingMode(DL, TestAddrMode, AccessTy, AddrSpace)) {
    AddrModeInsts.push_back(cast<Instruction>(ScaleReg));
    AddrMode = TestAddrMode;
    return true;
  }
}

// Otherwise, not (x+c)*scale, just return what we have.
return true;
3546}

3548/// This is a little filter, which returns true if an addressing computation
3549/// involving I might be folded into a load/store accessing it.
3550/// This doesn't need to be perfect, but needs to accept at least
3551/// the set of instructions that MatchOperationAddr can.
3552static bool MightBeFoldableInst(Instruction *I) {
switch (I->getOpcode()) {
case Instruction::BitCast:
case Instruction::AddrSpaceCast:
  // Don't touch identity bitcasts.
  if (I->getType() == I->getOperand(0)->getType())
    return false;
  return I->getType()->isIntOrPtrTy();
case Instruction::PtrToInt:
  // PtrToInt is always a noop, as we know that the int type is pointer sized.
  return true;
case Instruction::IntToPtr:
  // We know the input is intptr_t, so this is foldable.
  return true;
case Instruction::Add:
  return true;
case Instruction::Mul:
case Instruction::Shl:
  // Can only handle X*C and X << C.
  return isa<ConstantInt>(I->getOperand(1));
case Instruction::GetElementPtr:
  return true;
default:
  return false;
}
3577}

3579/// Check whether or not \p Val is a legal instruction for \p TLI.
3580/// \note \p Val is assumed to be the product of some type promotion.
3581/// Therefore if \p Val has an undefined state in \p TLI, this is assumed
3582/// to be legal, as the non-promoted value would have had the same state.
3583static bool isPromotedInstructionLegal(const TargetLowering &TLI,
                                     const DataLayout &DL, Value *Val) {
Instruction *PromotedInst = dyn_cast<Instruction>(Val);
if (!PromotedInst)
  return false;
int ISDOpcode = TLI.InstructionOpcodeToISD(PromotedInst->getOpcode());
// If the ISDOpcode is undefined, it was undefined before the promotion.
if (!ISDOpcode)
  return true;
// Otherwise, check if the promoted instruction is legal or not.
return TLI.isOperationLegalOrCustom(
    ISDOpcode, TLI.getValueType(DL, PromotedInst->getType()));
3595}

3597namespace {

3599/// Hepler class to perform type promotion.
3600class TypePromotionHelper {
/// Utility function to add a promoted instruction \p ExtOpnd to
/// \p PromotedInsts and record the type of extension we have seen.
static void addPromotedInst(InstrToOrigTy &PromotedInsts,
                            Instruction *ExtOpnd,
                            bool IsSExt) {
  ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension;
  InstrToOrigTy::iterator It = PromotedInsts.find(ExtOpnd);
  if (It != PromotedInsts.end()) {
    // If the new extension is same as original, the information in
    // PromotedInsts[ExtOpnd] is still correct.
    if (It->second.getInt() == ExtTy)
      return;

    // Now the new extension is different from old extension, we make
    // the type information invalid by setting extension type to
    // BothExtension.
    ExtTy = BothExtension;
  }
  PromotedInsts[ExtOpnd] = TypeIsSExt(ExtOpnd->getType(), ExtTy);
}

/// Utility function to query the original type of instruction \p Opnd
/// with a matched extension type. If the extension doesn't match, we
/// cannot use the information we had on the original type.
/// BothExtension doesn't match any extension type.
static const Type *getOrigType(const InstrToOrigTy &PromotedInsts,
                               Instruction *Opnd,
                               bool IsSExt) {
  ExtType ExtTy = IsSExt ? SignExtension : ZeroExtension;
  InstrToOrigTy::const_iterator It = PromotedInsts.find(Opnd);
  if (It != PromotedInsts.end() && It->second.getInt() == ExtTy)
    return It->second.getPointer();
  return nullptr;
}

/// Utility function to check whether or not a sign or zero extension
/// of \p Inst with \p ConsideredExtType can be moved through \p Inst by
/// either using the operands of \p Inst or promoting \p Inst.
/// The type of the extension is defined by \p IsSExt.
/// In other words, check if:
/// ext (Ty Inst opnd1 opnd2 ... opndN) to ConsideredExtType.
/// #1 Promotion applies:
/// ConsideredExtType Inst (ext opnd1 to ConsideredExtType, ...).
/// #2 Operand reuses:
/// ext opnd1 to ConsideredExtType.
/// \p PromotedInsts maps the instructions to their type before promotion.
static bool canGetThrough(const Instruction *Inst, Type *ConsideredExtType,
                          const InstrToOrigTy &PromotedInsts, bool IsSExt);

/// Utility function to determine if \p OpIdx should be promoted when
/// promoting \p Inst.
static bool shouldExtOperand(const Instruction *Inst, int OpIdx) {
  return !(isa<SelectInst>(Inst) && OpIdx == 0);
}

/// Utility function to promote the operand of \p Ext when this
/// operand is a promotable trunc or sext or zext.
/// \p PromotedInsts maps the instructions to their type before promotion.
/// \p CreatedInstsCost[out] contains the cost of all instructions
/// created to promote the operand of Ext.
/// Newly added extensions are inserted in \p Exts.
/// Newly added truncates are inserted in \p Truncs.
/// Should never be called directly.
/// \return The promoted value which is used instead of Ext.
static Value *promoteOperandForTruncAndAnyExt(
    Instruction *Ext, TypePromotionTransaction &TPT,
    InstrToOrigTy &PromotedInsts, unsigned &CreatedInstsCost,
    SmallVectorImpl<Instruction *> *Exts,
    SmallVectorImpl<Instruction *> *Truncs, const TargetLowering &TLI);

/// Utility function to promote the operand of \p Ext when this
/// operand is promotable and is not a supported trunc or sext.
/// \p PromotedInsts maps the instructions to their type before promotion.
/// \p CreatedInstsCost[out] contains the cost of all the instructions
/// created to promote the operand of Ext.
/// Newly added extensions are inserted in \p Exts.
/// Newly added truncates are inserted in \p Truncs.
/// Should never be called directly.
/// \return The promoted value which is used instead of Ext.
static Value *promoteOperandForOther(Instruction *Ext,
                                     TypePromotionTransaction &TPT,
                                     InstrToOrigTy &PromotedInsts,
                                     unsigned &CreatedInstsCost,
                                     SmallVectorImpl<Instruction *> *Exts,
                                     SmallVectorImpl<Instruction *> *Truncs,
                                     const TargetLowering &TLI, bool IsSExt);

/// \see promoteOperandForOther.
static Value *signExtendOperandForOther(
    Instruction *Ext, TypePromotionTransaction &TPT,
    InstrToOrigTy &PromotedInsts, unsigned &CreatedInstsCost,
    SmallVectorImpl<Instruction *> *Exts,
    SmallVectorImpl<Instruction *> *Truncs, const TargetLowering &TLI) {
  return promoteOperandForOther(Ext, TPT, PromotedInsts, CreatedInstsCost,
                                Exts, Truncs, TLI, true);
}

/// \see promoteOperandForOther.
static Value *zeroExtendOperandForOther(
    Instruction *Ext, TypePromotionTransaction &TPT,
    InstrToOrigTy &PromotedInsts, unsigned &CreatedInstsCost,
    SmallVectorImpl<Instruction *> *Exts,
    SmallVectorImpl<Instruction *> *Truncs, const TargetLowering &TLI) {
  return promoteOperandForOther(Ext, TPT, PromotedInsts, CreatedInstsCost,
                                Exts, Truncs, TLI, false);
}

3708public:
/// Type for the utility function that promotes the operand of Ext.
using Action = Value *(*)(Instruction *Ext, TypePromotionTransaction &TPT,
                          InstrToOrigTy &PromotedInsts,
                          unsigned &CreatedInstsCost,
                          SmallVectorImpl<Instruction *> *Exts,
                          SmallVectorImpl<Instruction *> *Truncs,
                          const TargetLowering &TLI);

/// Given a sign/zero extend instruction \p Ext, return the appropriate
/// action to promote the operand of \p Ext instead of using Ext.
/// \return NULL if no promotable action is possible with the current
/// sign extension.
/// \p InsertedInsts keeps track of all the instructions inserted by the
/// other CodeGenPrepare optimizations. This information is important
/// because we do not want to promote these instructions as CodeGenPrepare
/// will reinsert them later. Thus creating an infinite loop: create/remove.
/// \p PromotedInsts maps the instructions to their type before promotion.
static Action getAction(Instruction *Ext, const SetOfInstrs &InsertedInsts,
                        const TargetLowering &TLI,
                        const InstrToOrigTy &PromotedInsts);
3729};

3731} // end anonymous namespace

3733bool TypePromotionHelper::canGetThrough(const Instruction *Inst,
                                      Type *ConsideredExtType,
                                      const InstrToOrigTy &PromotedInsts,
                                      bool IsSExt) {
// The promotion helper does not know how to deal with vector types yet.
// To be able to fix that, we would need to fix the places where we
// statically extend, e.g., constants and such.
if (Inst->getType()->isVectorTy())
  return false;

// We can always get through zext.
if (isa<ZExtInst>(Inst))
  return true;

// sext(sext) is ok too.
if (IsSExt && isa<SExtInst>(Inst))
  return true;

// We can get through binary operator, if it is legal. In other words, the
// binary operator must have a nuw or nsw flag.
const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
if (BinOp && isa<OverflowingBinaryOperator>(BinOp) &&
    ((!IsSExt && BinOp->hasNoUnsignedWrap()) ||
     (IsSExt && BinOp->hasNoSignedWrap())))
  return true;

// ext(and(opnd, cst)) --> and(ext(opnd), ext(cst))
if ((Inst->getOpcode() == Instruction::And ||
     Inst->getOpcode() == Instruction::Or))
  return true;

// ext(xor(opnd, cst)) --> xor(ext(opnd), ext(cst))
if (Inst->getOpcode() == Instruction::Xor) {
  const ConstantInt *Cst = dyn_cast<ConstantInt>(Inst->getOperand(1));
  // Make sure it is not a NOT.
  if (Cst && !Cst->getValue().isAllOnesValue())
    return true;
}

// zext(shrl(opnd, cst)) --> shrl(zext(opnd), zext(cst))
// It may change a poisoned value into a regular value, like
//     zext i32 (shrl i8 %val, 12)  -->  shrl i32 (zext i8 %val), 12
//          poisoned value                    regular value
// It should be OK since undef covers valid value.
if (Inst->getOpcode() == Instruction::LShr && !IsSExt)
  return true;

// and(ext(shl(opnd, cst)), cst) --> and(shl(ext(opnd), ext(cst)), cst)
// It may change a poisoned value into a regular value, like
//     zext i32 (shl i8 %val, 12)  -->  shl i32 (zext i8 %val), 12
//          poisoned value                    regular value
// It should be OK since undef covers valid value.
if (Inst->getOpcode() == Instruction::Shl && Inst->hasOneUse()) {
  const Instruction *ExtInst =
      dyn_cast<const Instruction>(*Inst->user_begin());
  if (ExtInst->hasOneUse()) {
    const Instruction *AndInst =
        dyn_cast<const Instruction>(*ExtInst->user_begin());
    if (AndInst && AndInst->getOpcode() == Instruction::And) {
      const ConstantInt *Cst = dyn_cast<ConstantInt>(AndInst->getOperand(1));
      if (Cst &&
          Cst->getValue().isIntN(Inst->getType()->getIntegerBitWidth()))
        return true;
    }
  }
}

// Check if we can do the following simplification.
// ext(trunc(opnd)) --> ext(opnd)
if (!isa<TruncInst>(Inst))
  return false;

Value *OpndVal = Inst->getOperand(0);
// Check if we can use this operand in the extension.
// If the type is larger than the result type of the extension, we cannot.
if (!OpndVal->getType()->isIntegerTy() ||
    OpndVal->getType()->getIntegerBitWidth() >
        ConsideredExtType->getIntegerBitWidth())
  return false;

// If the operand of the truncate is not an instruction, we will not have
// any information on the dropped bits.
// (Actually we could for constant but it is not worth the extra logic).
Instruction *Opnd = dyn_cast<Instruction>(OpndVal);
if (!Opnd)
  return false;

// Check if the source of the type is narrow enough.
// I.e., check that trunc just drops extended bits of the same kind of
// the extension.
// #1 get the type of the operand and check the kind of the extended bits.
const Type *OpndType = getOrigType(PromotedInsts, Opnd, IsSExt);
if (OpndType)
  ;
else if ((IsSExt && isa<SExtInst>(Opnd)) || (!IsSExt && isa<ZExtInst>(Opnd)))
  OpndType = Opnd->getOperand(0)->getType();
else
  return false;

// #2 check that the truncate just drops extended bits.
return Inst->getType()->getIntegerBitWidth() >=
       OpndType->getIntegerBitWidth();
3835}

3837TypePromotionHelper::Action TypePromotionHelper::getAction(
  Instruction *Ext, const SetOfInstrs &InsertedInsts,
  const TargetLowering &TLI, const InstrToOrigTy &PromotedInsts) {
assert((isa<SExtInst>(Ext) || isa<ZExtInst>(Ext)) &&(((isa<SExtInst>(Ext) || isa<ZExtInst>(Ext)) &&
 "Unexpected instruction type") ? static_cast<void> (0)
 : __assert_fail ("(isa<SExtInst>(Ext) || isa<ZExtInst>(Ext)) && \"Unexpected instruction type\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3841, __PRETTY_FUNCTION__))
       "Unexpected instruction type")(((isa<SExtInst>(Ext) || isa<ZExtInst>(Ext)) &&
 "Unexpected instruction type") ? static_cast<void> (0)
 : __assert_fail ("(isa<SExtInst>(Ext) || isa<ZExtInst>(Ext)) && \"Unexpected instruction type\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 3841, __PRETTY_FUNCTION__));
Instruction *ExtOpnd = dyn_cast<Instruction>(Ext->getOperand(0));
Type *ExtTy = Ext->getType();
bool IsSExt = isa<SExtInst>(Ext);
// If the operand of the extension is not an instruction, we cannot
// get through.
// If it, check we can get through.
if (!ExtOpnd || !canGetThrough(ExtOpnd, ExtTy, PromotedInsts, IsSExt))
  return nullptr;

// Do not promote if the operand has been added by codegenprepare.
// Otherwise, it means we are undoing an optimization that is likely to be
// redone, thus causing potential infinite loop.
if (isa<TruncInst>(ExtOpnd) && InsertedInsts.count(ExtOpnd))
  return nullptr;

// SExt or Trunc instructions.
// Return the related handler.
if (isa<SExtInst>(ExtOpnd) || isa<TruncInst>(ExtOpnd) ||
    isa<ZExtInst>(ExtOpnd))
  return promoteOperandForTruncAndAnyExt;

// Regular instruction.
// Abort early if we will have to insert non-free instructions.
if (!ExtOpnd->hasOneUse() && !TLI.isTruncateFree(ExtTy, ExtOpnd->getType()))
  return nullptr;
return IsSExt ? signExtendOperandForOther : zeroExtendOperandForOther;
3868}

3870Value *TypePromotionHelper::promoteOperandForTruncAndAnyExt(
  Instruction *SExt, TypePromotionTransaction &TPT,
  InstrToOrigTy &PromotedInsts, unsigned &CreatedInstsCost,
  SmallVectorImpl<Instruction *> *Exts,
  SmallVectorImpl<Instruction *> *Truncs, const TargetLowering &TLI) {
// By construction, the operand of SExt is an instruction. Otherwise we cannot
// get through it and this method should not be called.
Instruction *SExtOpnd = cast<Instruction>(SExt->getOperand(0));
Value *ExtVal = SExt;
bool HasMergedNonFreeExt = false;
if (isa<ZExtInst>(SExtOpnd)) {
  // Replace s|zext(zext(opnd))
  // => zext(opnd).
  HasMergedNonFreeExt = !TLI.isExtFree(SExtOpnd);
  Value *ZExt =
      TPT.createZExt(SExt, SExtOpnd->getOperand(0), SExt->getType());
  TPT.replaceAllUsesWith(SExt, ZExt);
  TPT.eraseInstruction(SExt);
  ExtVal = ZExt;
} else {
  // Replace z|sext(trunc(opnd)) or sext(sext(opnd))
  // => z|sext(opnd).
  TPT.setOperand(SExt, 0, SExtOpnd->getOperand(0));
}
CreatedInstsCost = 0;

// Remove dead code.
if (SExtOpnd->use_empty())
  TPT.eraseInstruction(SExtOpnd);

// Check if the extension is still needed.
Instruction *ExtInst = dyn_cast<Instruction>(ExtVal);
if (!ExtInst || ExtInst->getType() != ExtInst->getOperand(0)->getType()) {
  if (ExtInst) {
    if (Exts)
      Exts->push_back(ExtInst);
    CreatedInstsCost = !TLI.isExtFree(ExtInst) && !HasMergedNonFreeExt;
  }
  return ExtVal;
}

// At this point we have: ext ty opnd to ty.
// Reassign the uses of ExtInst to the opnd and remove ExtInst.
Value *NextVal = ExtInst->getOperand(0);
TPT.eraseInstruction(ExtInst, NextVal);
return NextVal;
3916}

3918Value *TypePromotionHelper::promoteOperandForOther(
  Instruction *Ext, TypePromotionTransaction &TPT,
  InstrToOrigTy &PromotedInsts, unsigned &CreatedInstsCost,
  SmallVectorImpl<Instruction *> *Exts,
  SmallVectorImpl<Instruction *> *Truncs, const TargetLowering &TLI,
  bool IsSExt) {
// By construction, the operand of Ext is an instruction. Otherwise we cannot
// get through it and this method should not be called.
Instruction *ExtOpnd = cast<Instruction>(Ext->getOperand(0));
CreatedInstsCost = 0;
if (!ExtOpnd->hasOneUse()) {
  // ExtOpnd will be promoted.
  // All its uses, but Ext, will need to use a truncated value of the
  // promoted version.
  // Create the truncate now.
  Value *Trunc = TPT.createTrunc(Ext, ExtOpnd->getType());
  if (Instruction *ITrunc = dyn_cast<Instruction>(Trunc)) {
    // Insert it just after the definition.
    ITrunc->moveAfter(ExtOpnd);
    if (Truncs)
      Truncs->push_back(ITrunc);
  }

  TPT.replaceAllUsesWith(ExtOpnd, Trunc);
  // Restore the operand of Ext (which has been replaced by the previous call
  // to replaceAllUsesWith) to avoid creating a cycle trunc <-> sext.
  TPT.setOperand(Ext, 0, ExtOpnd);
}

// Get through the Instruction:
// 1. Update its type.
// 2. Replace the uses of Ext by Inst.
// 3. Extend each operand that needs to be extended.

// Remember the original type of the instruction before promotion.
// This is useful to know that the high bits are sign extended bits.
addPromotedInst(PromotedInsts, ExtOpnd, IsSExt);
// Step #1.
TPT.mutateType(ExtOpnd, Ext->getType());
// Step #2.
TPT.replaceAllUsesWith(Ext, ExtOpnd);
// Step #3.
Instruction *ExtForOpnd = Ext;

LLVM_DEBUG(dbgs() << "Propagate Ext to operands\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Propagate Ext to operands\n"
; } } while (false);
for (int OpIdx = 0, EndOpIdx = ExtOpnd->getNumOperands(); OpIdx != EndOpIdx;
     ++OpIdx) {
  LLVM_DEBUG(dbgs() << "Operand:\n" << *(ExtOpnd->getOperand(OpIdx)) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Operand:\n" << *
(ExtOpnd->getOperand(OpIdx)) << '\n'; } } while (false
);
  if (ExtOpnd->getOperand(OpIdx)->getType() == Ext->getType() ||
      !shouldExtOperand(ExtOpnd, OpIdx)) {
    LLVM_DEBUG(dbgs() << "No need to propagate\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "No need to propagate\n"
; } } while (false);
    continue;
  }
  // Check if we can statically extend the operand.
  Value *Opnd = ExtOpnd->getOperand(OpIdx);
  if (const ConstantInt *Cst = dyn_cast<ConstantInt>(Opnd)) {
    LLVM_DEBUG(dbgs() << "Statically extend\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Statically extend\n"; }
 } while (false);
    unsigned BitWidth = Ext->getType()->getIntegerBitWidth();
    APInt CstVal = IsSExt ? Cst->getValue().sext(BitWidth)
                          : Cst->getValue().zext(BitWidth);
    TPT.setOperand(ExtOpnd, OpIdx, ConstantInt::get(Ext->getType(), CstVal));
    continue;
  }
  // UndefValue are typed, so we have to statically sign extend them.
  if (isa<UndefValue>(Opnd)) {
    LLVM_DEBUG(dbgs() << "Statically extend\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Statically extend\n"; }
 } while (false);
    TPT.setOperand(ExtOpnd, OpIdx, UndefValue::get(Ext->getType()));
    continue;
  }

  // Otherwise we have to explicitly sign extend the operand.
  // Check if Ext was reused to extend an operand.
  if (!ExtForOpnd) {
    // If yes, create a new one.
    LLVM_DEBUG(dbgs() << "More operands to ext\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "More operands to ext\n"
; } } while (false);
    Value *ValForExtOpnd = IsSExt ? TPT.createSExt(Ext, Opnd, Ext->getType())
      : TPT.createZExt(Ext, Opnd, Ext->getType());
    if (!isa<Instruction>(ValForExtOpnd)) {
      TPT.setOperand(ExtOpnd, OpIdx, ValForExtOpnd);
      continue;
    }
    ExtForOpnd = cast<Instruction>(ValForExtOpnd);
  }
  if (Exts)
    Exts->push_back(ExtForOpnd);
  TPT.setOperand(ExtForOpnd, 0, Opnd);

  // Move the sign extension before the insertion point.
  TPT.moveBefore(ExtForOpnd, ExtOpnd);
  TPT.setOperand(ExtOpnd, OpIdx, ExtForOpnd);
  CreatedInstsCost += !TLI.isExtFree(ExtForOpnd);
  // If more sext are required, new instructions will have to be created.
  ExtForOpnd = nullptr;
}
if (ExtForOpnd == Ext) {
  LLVM_DEBUG(dbgs() << "Extension is useless now\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Extension is useless now\n"
; } } while (false);
  TPT.eraseInstruction(Ext);
}
return ExtOpnd;
4017}

4019/// Check whether or not promoting an instruction to a wider type is profitable.
4020/// \p NewCost gives the cost of extension instructions created by the
4021/// promotion.
4022/// \p OldCost gives the cost of extension instructions before the promotion
4023/// plus the number of instructions that have been
4024/// matched in the addressing mode the promotion.
4025/// \p PromotedOperand is the value that has been promoted.
4026/// \return True if the promotion is profitable, false otherwise.
4027bool AddressingModeMatcher::isPromotionProfitable(
  unsigned NewCost, unsigned OldCost, Value *PromotedOperand) const {
LLVM_DEBUG(dbgs() << "OldCost: " << OldCost << "\tNewCost: " << NewCostdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "OldCost: " << OldCost
 << "\tNewCost: " << NewCost << '\n'; } } while
 (false)
                  << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "OldCost: " << OldCost
 << "\tNewCost: " << NewCost << '\n'; } } while
 (false);
// The cost of the new extensions is greater than the cost of the
// old extension plus what we folded.
// This is not profitable.
if (NewCost > OldCost)
  return false;
if (NewCost < OldCost)
  return true;
// The promotion is neutral but it may help folding the sign extension in
// loads for instance.
// Check that we did not create an illegal instruction.
return isPromotedInstructionLegal(TLI, DL, PromotedOperand);
4042}

4044/// Given an instruction or constant expr, see if we can fold the operation
4045/// into the addressing mode. If so, update the addressing mode and return
4046/// true, otherwise return false without modifying AddrMode.
4047/// If \p MovedAway is not NULL, it contains the information of whether or
4048/// not AddrInst has to be folded into the addressing mode on success.
4049/// If \p MovedAway == true, \p AddrInst will not be part of the addressing
4050/// because it has been moved away.
4051/// Thus AddrInst must not be added in the matched instructions.
4052/// This state can happen when AddrInst is a sext, since it may be moved away.
4053/// Therefore, AddrInst may not be valid when MovedAway is true and it must
4054/// not be referenced anymore.
4055bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode,
                                             unsigned Depth,
                                             bool *MovedAway) {
// Avoid exponential behavior on extremely deep expression trees.
if (Depth >= 5) return false;

// By default, all matched instructions stay in place.
if (MovedAway)
  *MovedAway = false;

switch (Opcode) {
case Instruction::PtrToInt:
  // PtrToInt is always a noop, as we know that the int type is pointer sized.
  return matchAddr(AddrInst->getOperand(0), Depth);
case Instruction::IntToPtr: {
  auto AS = AddrInst->getType()->getPointerAddressSpace();
  auto PtrTy = MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
  // This inttoptr is a no-op if the integer type is pointer sized.
  if (TLI.getValueType(DL, AddrInst->getOperand(0)->getType()) == PtrTy)
    return matchAddr(AddrInst->getOperand(0), Depth);
  return false;
}
case Instruction::BitCast:
  // BitCast is always a noop, and we can handle it as long as it is
  // int->int or pointer->pointer (we don't want int<->fp or something).
  if (AddrInst->getOperand(0)->getType()->isIntOrPtrTy() &&
      // Don't touch identity bitcasts.  These were probably put here by LSR,
      // and we don't want to mess around with them.  Assume it knows what it
      // is doing.
      AddrInst->getOperand(0)->getType() != AddrInst->getType())
    return matchAddr(AddrInst->getOperand(0), Depth);
  return false;
case Instruction::AddrSpaceCast: {
  unsigned SrcAS
    = AddrInst->getOperand(0)->getType()->getPointerAddressSpace();
  unsigned DestAS = AddrInst->getType()->getPointerAddressSpace();
  if (TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
    return matchAddr(AddrInst->getOperand(0), Depth);
  return false;
}
case Instruction::Add: {
  // Check to see if we can merge in the RHS then the LHS.  If so, we win.
  ExtAddrMode BackupAddrMode = AddrMode;
  unsigned OldSize = AddrModeInsts.size();
  // Start a transaction at this point.
  // The LHS may match but not the RHS.
  // Therefore, we need a higher level restoration point to undo partially
  // matched operation.
  TypePromotionTransaction::ConstRestorationPt LastKnownGood =
      TPT.getRestorationPoint();

  AddrMode.InBounds = false;
  if (matchAddr(AddrInst->getOperand(1), Depth+1) &&
      matchAddr(AddrInst->getOperand(0), Depth+1))
    return true;

  // Restore the old addr mode info.
  AddrMode = BackupAddrMode;
  AddrModeInsts.resize(OldSize);
  TPT.rollback(LastKnownGood);

  // Otherwise this was over-aggressive.  Try merging in the LHS then the RHS.
  if (matchAddr(AddrInst->getOperand(0), Depth+1) &&
      matchAddr(AddrInst->getOperand(1), Depth+1))
    return true;

  // Otherwise we definitely can't merge the ADD in.
  AddrMode = BackupAddrMode;
  AddrModeInsts.resize(OldSize);
  TPT.rollback(LastKnownGood);
  break;
}
//case Instruction::Or:
// TODO: We can handle "Or Val, Imm" iff this OR is equivalent to an ADD.
//break;
case Instruction::Mul:
case Instruction::Shl: {
  // Can only handle X*C and X << C.
  AddrMode.InBounds = false;
  ConstantInt *RHS = dyn_cast<ConstantInt>(AddrInst->getOperand(1));
  if (!RHS || RHS->getBitWidth() > 64)
    return false;
  int64_t Scale = RHS->getSExtValue();
  if (Opcode == Instruction::Shl)
    Scale = 1LL << Scale;

  return matchScaledValue(AddrInst->getOperand(0), Scale, Depth);
}
case Instruction::GetElementPtr: {
  // Scan the GEP.  We check it if it contains constant offsets and at most
  // one variable offset.
  int VariableOperand = -1;
  unsigned VariableScale = 0;

  int64_t ConstantOffset = 0;
  gep_type_iterator GTI = gep_type_begin(AddrInst);
  for (unsigned i = 1, e = AddrInst->getNumOperands(); i != e; ++i, ++GTI) {
    if (StructType *STy = GTI.getStructTypeOrNull()) {
      const StructLayout *SL = DL.getStructLayout(STy);
      unsigned Idx =
        cast<ConstantInt>(AddrInst->getOperand(i))->getZExtValue();
      ConstantOffset += SL->getElementOffset(Idx);
    } else {
      uint64_t TypeSize = DL.getTypeAllocSize(GTI.getIndexedType());
      if (ConstantInt *CI = dyn_cast<ConstantInt>(AddrInst->getOperand(i))) {
        const APInt &CVal = CI->getValue();
        if (CVal.getMinSignedBits() <= 64) {
          ConstantOffset += CVal.getSExtValue() * TypeSize;
          continue;
        }
      }
      if (TypeSize) {  // Scales of zero don't do anything.
        // We only allow one variable index at the moment.
        if (VariableOperand != -1)
          return false;

        // Remember the variable index.
        VariableOperand = i;
        VariableScale = TypeSize;
      }
    }
  }

  // A common case is for the GEP to only do a constant offset.  In this case,
  // just add it to the disp field and check validity.
  if (VariableOperand == -1) {
    AddrMode.BaseOffs += ConstantOffset;
    if (ConstantOffset == 0 ||
        TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace)) {
      // Check to see if we can fold the base pointer in too.
      if (matchAddr(AddrInst->getOperand(0), Depth+1)) {
        if (!cast<GEPOperator>(AddrInst)->isInBounds())
          AddrMode.InBounds = false;
        return true;
      }
    } else if (EnableGEPOffsetSplit && isa<GetElementPtrInst>(AddrInst) &&
               TLI.shouldConsiderGEPOffsetSplit() && Depth == 0 &&
               ConstantOffset > 0) {
      // Record GEPs with non-zero offsets as candidates for splitting in the
      // event that the offset cannot fit into the r+i addressing mode.
      // Simple and common case that only one GEP is used in calculating the
      // address for the memory access.
      Value *Base = AddrInst->getOperand(0);
      auto *BaseI = dyn_cast<Instruction>(Base);
      auto *GEP = cast<GetElementPtrInst>(AddrInst);
      if (isa<Argument>(Base) || isa<GlobalValue>(Base) ||
          (BaseI && !isa<CastInst>(BaseI) &&
           !isa<GetElementPtrInst>(BaseI))) {
        // Make sure the parent block allows inserting non-PHI instructions
        // before the terminator.
        BasicBlock *Parent =
            BaseI ? BaseI->getParent() : &GEP->getFunction()->getEntryBlock();
        if (!Parent->getTerminator()->isEHPad())
          LargeOffsetGEP = std::make_pair(GEP, ConstantOffset);
      }
    }
    AddrMode.BaseOffs -= ConstantOffset;
    return false;
  }

  // Save the valid addressing mode in case we can't match.
  ExtAddrMode BackupAddrMode = AddrMode;
  unsigned OldSize = AddrModeInsts.size();

  // See if the scale and offset amount is valid for this target.
  AddrMode.BaseOffs += ConstantOffset;
  if (!cast<GEPOperator>(AddrInst)->isInBounds())
    AddrMode.InBounds = false;

  // Match the base operand of the GEP.
  if (!matchAddr(AddrInst->getOperand(0), Depth+1)) {
    // If it couldn't be matched, just stuff the value in a register.
    if (AddrMode.HasBaseReg) {
      AddrMode = BackupAddrMode;
      AddrModeInsts.resize(OldSize);
      return false;
    }
    AddrMode.HasBaseReg = true;
    AddrMode.BaseReg = AddrInst->getOperand(0);
  }

  // Match the remaining variable portion of the GEP.
  if (!matchScaledValue(AddrInst->getOperand(VariableOperand), VariableScale,
                        Depth)) {
    // If it couldn't be matched, try stuffing the base into a register
    // instead of matching it, and retrying the match of the scale.
    AddrMode = BackupAddrMode;
    AddrModeInsts.resize(OldSize);
    if (AddrMode.HasBaseReg)
      return false;
    AddrMode.HasBaseReg = true;
    AddrMode.BaseReg = AddrInst->getOperand(0);
    AddrMode.BaseOffs += ConstantOffset;
    if (!matchScaledValue(AddrInst->getOperand(VariableOperand),
                          VariableScale, Depth)) {
      // If even that didn't work, bail.
      AddrMode = BackupAddrMode;
      AddrModeInsts.resize(OldSize);
      return false;
    }
  }

  return true;
}
case Instruction::SExt:
case Instruction::ZExt: {
  Instruction *Ext = dyn_cast<Instruction>(AddrInst);
  if (!Ext)
    return false;

  // Try to move this ext out of the way of the addressing mode.
  // Ask for a method for doing so.
  TypePromotionHelper::Action TPH =
      TypePromotionHelper::getAction(Ext, InsertedInsts, TLI, PromotedInsts);
  if (!TPH)
    return false;

  TypePromotionTransaction::ConstRestorationPt LastKnownGood =
      TPT.getRestorationPoint();
  unsigned CreatedInstsCost = 0;
  unsigned ExtCost = !TLI.isExtFree(Ext);
  Value *PromotedOperand =
      TPH(Ext, TPT, PromotedInsts, CreatedInstsCost, nullptr, nullptr, TLI);
  // SExt has been moved away.
  // Thus either it will be rematched later in the recursive calls or it is
  // gone. Anyway, we must not fold it into the addressing mode at this point.
  // E.g.,
  // op = add opnd, 1
  // idx = ext op
  // addr = gep base, idx
  // is now:
  // promotedOpnd = ext opnd            <- no match here
  // op = promoted_add promotedOpnd, 1  <- match (later in recursive calls)
  // addr = gep base, op                <- match
  if (MovedAway)
    *MovedAway = true;

  assert(PromotedOperand &&((PromotedOperand && "TypePromotionHelper should have filtered out those cases"
) ? static_cast<void> (0) : __assert_fail ("PromotedOperand && \"TypePromotionHelper should have filtered out those cases\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 4293, __PRETTY_FUNCTION__))
         "TypePromotionHelper should have filtered out those cases")((PromotedOperand && "TypePromotionHelper should have filtered out those cases"
) ? static_cast<void> (0) : __assert_fail ("PromotedOperand && \"TypePromotionHelper should have filtered out those cases\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 4293, __PRETTY_FUNCTION__));

  ExtAddrMode BackupAddrMode = AddrMode;
  unsigned OldSize = AddrModeInsts.size();

  if (!matchAddr(PromotedOperand, Depth) ||
      // The total of the new cost is equal to the cost of the created
      // instructions.
      // The total of the old cost is equal to the cost of the extension plus
      // what we have saved in the addressing mode.
      !isPromotionProfitable(CreatedInstsCost,
                             ExtCost + (AddrModeInsts.size() - OldSize),
                             PromotedOperand)) {
    AddrMode = BackupAddrMode;
    AddrModeInsts.resize(OldSize);
    LLVM_DEBUG(dbgs() << "Sign extension does not pay off: rollback\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Sign extension does not pay off: rollback\n"
; } } while (false);
    TPT.rollback(LastKnownGood);
    return false;
  }
  return true;
}
}
return false;
4316}

4318/// If we can, try to add the value of 'Addr' into the current addressing mode.
4319/// If Addr can't be added to AddrMode this returns false and leaves AddrMode
4320/// unmodified. This assumes that Addr is either a pointer type or intptr_t
4321/// for the target.
4322///
4323bool AddressingModeMatcher::matchAddr(Value *Addr, unsigned Depth) {
// Start a transaction at this point that we will rollback if the matching
// fails.
TypePromotionTransaction::ConstRestorationPt LastKnownGood =
    TPT.getRestorationPoint();
if (ConstantInt *CI = dyn_cast<ConstantInt>(Addr)) {
  // Fold in immediates if legal for the target.
  AddrMode.BaseOffs += CI->getSExtValue();
  if (TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace))
    return true;
  AddrMode.BaseOffs -= CI->getSExtValue();
} else if (GlobalValue *GV = dyn_cast<GlobalValue>(Addr)) {
  // If this is a global variable, try to fold it into the addressing mode.
  if (!AddrMode.BaseGV) {
    AddrMode.BaseGV = GV;
    if (TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace))
      return true;
    AddrMode.BaseGV = nullptr;
  }
} else if (Instruction *I = dyn_cast<Instruction>(Addr)) {
  ExtAddrMode BackupAddrMode = AddrMode;
  unsigned OldSize = AddrModeInsts.size();

  // Check to see if it is possible to fold this operation.
  bool MovedAway = false;
  if (matchOperationAddr(I, I->getOpcode(), Depth, &MovedAway)) {
    // This instruction may have been moved away. If so, there is nothing
    // to check here.
    if (MovedAway)
      return true;
    // Okay, it's possible to fold this.  Check to see if it is actually
    // *profitable* to do so.  We use a simple cost model to avoid increasing
    // register pressure too much.
    if (I->hasOneUse() ||
        isProfitableToFoldIntoAddressingMode(I, BackupAddrMode, AddrMode)) {
      AddrModeInsts.push_back(I);
      return true;
    }

    // It isn't profitable to do this, roll back.
    //cerr << "NOT FOLDING: " << *I;
    AddrMode = BackupAddrMode;
    AddrModeInsts.resize(OldSize);
    TPT.rollback(LastKnownGood);
  }
} else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Addr)) {
  if (matchOperationAddr(CE, CE->getOpcode(), Depth))
    return true;
  TPT.rollback(LastKnownGood);
} else if (isa<ConstantPointerNull>(Addr)) {
  // Null pointer gets folded without affecting the addressing mode.
  return true;
}

// Worse case, the target should support [reg] addressing modes. :)
if (!AddrMode.HasBaseReg) {
  AddrMode.HasBaseReg = true;
  AddrMode.BaseReg = Addr;
  // Still check for legality in case the target supports [imm] but not [i+r].
  if (TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace))
    return true;
  AddrMode.HasBaseReg = false;
  AddrMode.BaseReg = nullptr;
}

// If the base register is already taken, see if we can do [r+r].
if (AddrMode.Scale == 0) {
  AddrMode.Scale = 1;
  AddrMode.ScaledReg = Addr;
  if (TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace))
    return true;
  AddrMode.Scale = 0;
  AddrMode.ScaledReg = nullptr;
}
// Couldn't match.
TPT.rollback(LastKnownGood);
return false;
4400}

4402/// Check to see if all uses of OpVal by the specified inline asm call are due
4403/// to memory operands. If so, return true, otherwise return false.
4404static bool IsOperandAMemoryOperand(CallInst *CI, InlineAsm *IA, Value *OpVal,
                                  const TargetLowering &TLI,
                                  const TargetRegisterInfo &TRI) {
const Function *F = CI->getFunction();
TargetLowering::AsmOperandInfoVector TargetConstraints =
    TLI.ParseConstraints(F->getParent()->getDataLayout(), &TRI,
                          ImmutableCallSite(CI));

for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
  TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];

  // Compute the constraint code and ConstraintType to use.
  TLI.ComputeConstraintToUse(OpInfo, SDValue());

  // If this asm operand is our Value*, and if it isn't an indirect memory
  // operand, we can't fold it!
  if (OpInfo.CallOperandVal == OpVal &&
      (OpInfo.ConstraintType != TargetLowering::C_Memory ||
       !OpInfo.isIndirect))
    return false;
}

return true;
4427}

4429// Max number of memory uses to look at before aborting the search to conserve
4430// compile time.
4431static constexpr int MaxMemoryUsesToScan = 20;

4433/// Recursively walk all the uses of I until we find a memory use.
4434/// If we find an obviously non-foldable instruction, return true.
4435/// Add the ultimately found memory instructions to MemoryUses.
4436static bool FindAllMemoryUses(
  Instruction *I,
  SmallVectorImpl<std::pair<Instruction *, unsigned>> &MemoryUses,
  SmallPtrSetImpl<Instruction *> &ConsideredInsts, const TargetLowering &TLI,
  const TargetRegisterInfo &TRI, int SeenInsts = 0) {
// If we already considered this instruction, we're done.
if (!ConsideredInsts.insert(I).second)
  return false;

// If this is an obviously unfoldable instruction, bail out.
if (!MightBeFoldableInst(I))
  return true;

const bool OptSize = I->getFunction()->hasOptSize();

// Loop over all the uses, recursively processing them.
for (Use &U : I->uses()) {
  // Conservatively return true if we're seeing a large number or a deep chain
  // of users. This avoids excessive compilation times in pathological cases.
  if (SeenInsts++ >= MaxMemoryUsesToScan)
    return true;

  Instruction *UserI = cast<Instruction>(U.getUser());
  if (LoadInst *LI = dyn_cast<LoadInst>(UserI)) {
    MemoryUses.push_back(std::make_pair(LI, U.getOperandNo()));
    continue;
  }

  if (StoreInst *SI = dyn_cast<StoreInst>(UserI)) {
    unsigned opNo = U.getOperandNo();
    if (opNo != StoreInst::getPointerOperandIndex())
      return true; // Storing addr, not into addr.
    MemoryUses.push_back(std::make_pair(SI, opNo));
    continue;
  }

  if (AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(UserI)) {
    unsigned opNo = U.getOperandNo();
    if (opNo != AtomicRMWInst::getPointerOperandIndex())
      return true; // Storing addr, not into addr.
    MemoryUses.push_back(std::make_pair(RMW, opNo));
    continue;
  }

  if (AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(UserI)) {
    unsigned opNo = U.getOperandNo();
    if (opNo != AtomicCmpXchgInst::getPointerOperandIndex())
      return true; // Storing addr, not into addr.
    MemoryUses.push_back(std::make_pair(CmpX, opNo));
    continue;
  }

  if (CallInst *CI = dyn_cast<CallInst>(UserI)) {
    // If this is a cold call, we can sink the addressing calculation into
    // the cold path.  See optimizeCallInst
    if (!OptSize && CI->hasFnAttr(Attribute::Cold))
      continue;

    InlineAsm *IA = dyn_cast<InlineAsm>(CI->getCalledValue());
    if (!IA) return true;

    // If this is a memory operand, we're cool, otherwise bail out.
    if (!IsOperandAMemoryOperand(CI, IA, I, TLI, TRI))
      return true;
    continue;
  }

  if (FindAllMemoryUses(UserI, MemoryUses, ConsideredInsts, TLI, TRI,
                        SeenInsts))
    return true;
}

return false;
4509}

4511/// Return true if Val is already known to be live at the use site that we're
4512/// folding it into. If so, there is no cost to include it in the addressing
4513/// mode. KnownLive1 and KnownLive2 are two values that we know are live at the
4514/// instruction already.
4515bool AddressingModeMatcher::valueAlreadyLiveAtInst(Value *Val,Value *KnownLive1,
                                                 Value *KnownLive2) {
// If Val is either of the known-live values, we know it is live!
if (Val == nullptr || Val == KnownLive1 || Val == KnownLive2)
  return true;

// All values other than instructions and arguments (e.g. constants) are live.
if (!isa<Instruction>(Val) && !isa<Argument>(Val)) return true;

// If Val is a constant sized alloca in the entry block, it is live, this is
// true because it is just a reference to the stack/frame pointer, which is
// live for the whole function.
if (AllocaInst *AI = dyn_cast<AllocaInst>(Val))
  if (AI->isStaticAlloca())
    return true;

// Check to see if this value is already used in the memory instruction's
// block.  If so, it's already live into the block at the very least, so we
// can reasonably fold it.
return Val->isUsedInBasicBlock(MemoryInst->getParent());
4535}

4537/// It is possible for the addressing mode of the machine to fold the specified
4538/// instruction into a load or store that ultimately uses it.
4539/// However, the specified instruction has multiple uses.
4540/// Given this, it may actually increase register pressure to fold it
4541/// into the load. For example, consider this code:
4542///
4543///     X = ...
4544///     Y = X+1
4545///     use(Y)   -> nonload/store
4546///     Z = Y+1
4547///     load Z
4548///
4549/// In this case, Y has multiple uses, and can be folded into the load of Z
4550/// (yielding load [X+2]).  However, doing this will cause both "X" and "X+1" to
4551/// be live at the use(Y) line.  If we don't fold Y into load Z, we use one
4552/// fewer register.  Since Y can't be folded into "use(Y)" we don't increase the
4553/// number of computations either.
4554///
4555/// Note that this (like most of CodeGenPrepare) is just a rough heuristic.  If
4556/// X was live across 'load Z' for other reasons, we actually *would* want to
4557/// fold the addressing mode in the Z case.  This would make Y die earlier.
4558bool AddressingModeMatcher::
4559isProfitableToFoldIntoAddressingMode(Instruction *I, ExtAddrMode &AMBefore,
                                   ExtAddrMode &AMAfter) {
if (IgnoreProfitability) return true;

// AMBefore is the addressing mode before this instruction was folded into it,
// and AMAfter is the addressing mode after the instruction was folded.  Get
// the set of registers referenced by AMAfter and subtract out those
// referenced by AMBefore: this is the set of values which folding in this
// address extends the lifetime of.
//
// Note that there are only two potential values being referenced here,
// BaseReg and ScaleReg (global addresses are always available, as are any
// folded immediates).
Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg;

// If the BaseReg or ScaledReg was referenced by the previous addrmode, their
// lifetime wasn't extended by adding this instruction.
if (valueAlreadyLiveAtInst(BaseReg, AMBefore.BaseReg, AMBefore.ScaledReg))
  BaseReg = nullptr;
if (valueAlreadyLiveAtInst(ScaledReg, AMBefore.BaseReg, AMBefore.ScaledReg))
  ScaledReg = nullptr;

// If folding this instruction (and it's subexprs) didn't extend any live
// ranges, we're ok with it.
if (!BaseReg && !ScaledReg)
  return true;

// If all uses of this instruction can have the address mode sunk into them,
// we can remove the addressing mode and effectively trade one live register
// for another (at worst.)  In this context, folding an addressing mode into
// the use is just a particularly nice way of sinking it.
SmallVector<std::pair<Instruction*,unsigned>, 16> MemoryUses;
SmallPtrSet<Instruction*, 16> ConsideredInsts;
if (FindAllMemoryUses(I, MemoryUses, ConsideredInsts, TLI, TRI))
  return false;  // Has a non-memory, non-foldable use!

// Now that we know that all uses of this instruction are part of a chain of
// computation involving only operations that could theoretically be folded
// into a memory use, loop over each of these memory operation uses and see
// if they could  *actually* fold the instruction.  The assumption is that
// addressing modes are cheap and that duplicating the computation involved
// many times is worthwhile, even on a fastpath. For sinking candidates
// (i.e. cold call sites), this serves as a way to prevent excessive code
// growth since most architectures have some reasonable small and fast way to
// compute an effective address.  (i.e LEA on x86)
SmallVector<Instruction*, 32> MatchedAddrModeInsts;
for (unsigned i = 0, e = MemoryUses.size(); i != e; ++i) {
  Instruction *User = MemoryUses[i].first;
  unsigned OpNo = MemoryUses[i].second;

  // Get the access type of this use.  If the use isn't a pointer, we don't
  // know what it accesses.
  Value *Address = User->getOperand(OpNo);
  PointerType *AddrTy = dyn_cast<PointerType>(Address->getType());
  if (!AddrTy)
    return false;
  Type *AddressAccessTy = AddrTy->getElementType();
  unsigned AS = AddrTy->getAddressSpace();

  // Do a match against the root of this address, ignoring profitability. This
  // will tell us if the addressing mode for the memory operation will
  // *actually* cover the shared instruction.
  ExtAddrMode Result;
  std::pair<AssertingVH<GetElementPtrInst>, int64_t> LargeOffsetGEP(nullptr,
                                                                    0);
  TypePromotionTransaction::ConstRestorationPt LastKnownGood =
      TPT.getRestorationPoint();
  AddressingModeMatcher Matcher(
      MatchedAddrModeInsts, TLI, TRI, AddressAccessTy, AS, MemoryInst, Result,
      InsertedInsts, PromotedInsts, TPT, LargeOffsetGEP);
  Matcher.IgnoreProfitability = true;
  bool Success = Matcher.matchAddr(Address, 0);
  (void)Success; assert(Success && "Couldn't select *anything*?")((Success && "Couldn't select *anything*?") ? static_cast
<void> (0) : __assert_fail ("Success && \"Couldn't select *anything*?\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 4631, __PRETTY_FUNCTION__));

  // The match was to check the profitability, the changes made are not
  // part of the original matcher. Therefore, they should be dropped
  // otherwise the original matcher will not present the right state.
  TPT.rollback(LastKnownGood);

  // If the match didn't cover I, then it won't be shared by it.
  if (!is_contained(MatchedAddrModeInsts, I))
    return false;

  MatchedAddrModeInsts.clear();
}

return true;
4646}

4648/// Return true if the specified values are defined in a
4649/// different basic block than BB.
4650static bool IsNonLocalValue(Value *V, BasicBlock *BB) {
if (Instruction *I = dyn_cast<Instruction>(V))
  return I->getParent() != BB;
return false;
4654}

4656/// Sink addressing mode computation immediate before MemoryInst if doing so
4657/// can be done without increasing register pressure.  The need for the
4658/// register pressure constraint means this can end up being an all or nothing
4659/// decision for all uses of the same addressing computation.
4660///
4661/// Load and Store Instructions often have addressing modes that can do
4662/// significant amounts of computation. As such, instruction selection will try
4663/// to get the load or store to do as much computation as possible for the
4664/// program. The problem is that isel can only see within a single block. As
4665/// such, we sink as much legal addressing mode work into the block as possible.
4666///
4667/// This method is used to optimize both load/store and inline asms with memory
4668/// operands.  It's also used to sink addressing computations feeding into cold
4669/// call sites into their (cold) basic block.
4670///
4671/// The motivation for handling sinking into cold blocks is that doing so can
4672/// both enable other address mode sinking (by satisfying the register pressure
4673/// constraint above), and reduce register pressure globally (by removing the
4674/// addressing mode computation from the fast path entirely.).
4675bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
                                      Type *AccessTy, unsigned AddrSpace) {
Value *Repl = Addr;

// Try to collapse single-value PHI nodes.  This is necessary to undo
// unprofitable PRE transformations.
SmallVector<Value*, 8> worklist;
SmallPtrSet<Value*, 16> Visited;
worklist.push_back(Addr);

// Use a worklist to iteratively look through PHI and select nodes, and
// ensure that the addressing mode obtained from the non-PHI/select roots of
// the graph are compatible.
bool PhiOrSelectSeen = false;
SmallVector<Instruction*, 16> AddrModeInsts;
const SimplifyQuery SQ(*DL, TLInfo);
AddressingModeCombiner AddrModes(SQ, Addr);
TypePromotionTransaction TPT(RemovedInsts);
TypePromotionTransaction::ConstRestorationPt LastKnownGood =
    TPT.getRestorationPoint();
while (!worklist.empty()) {
  Value *V = worklist.back();
  worklist.pop_back();

  // We allow traversing cyclic Phi nodes.
  // In case of success after this loop we ensure that traversing through
  // Phi nodes ends up with all cases to compute address of the form
  //    BaseGV + Base + Scale * Index + Offset
  // where Scale and Offset are constans and BaseGV, Base and Index
  // are exactly the same Values in all cases.
  // It means that BaseGV, Scale and Offset dominate our memory instruction
  // and have the same value as they had in address computation represented
  // as Phi. So we can safely sink address computation to memory instruction.
  if (!Visited.insert(V).second)
    continue;

  // For a PHI node, push all of its incoming values.
  if (PHINode *P = dyn_cast<PHINode>(V)) {
    for (Value *IncValue : P->incoming_values())
      worklist.push_back(IncValue);
    PhiOrSelectSeen = true;
    continue;
  }
  // Similar for select.
  if (SelectInst *SI = dyn_cast<SelectInst>(V)) {
    worklist.push_back(SI->getFalseValue());
    worklist.push_back(SI->getTrueValue());
    PhiOrSelectSeen = true;
    continue;
  }

  // For non-PHIs, determine the addressing mode being computed.  Note that
  // the result may differ depending on what other uses our candidate
  // addressing instructions might have.
  AddrModeInsts.clear();
  std::pair<AssertingVH<GetElementPtrInst>, int64_t> LargeOffsetGEP(nullptr,
                                                                    0);
  ExtAddrMode NewAddrMode = AddressingModeMatcher::Match(
      V, AccessTy, AddrSpace, MemoryInst, AddrModeInsts, *TLI, *TRI,
      InsertedInsts, PromotedInsts, TPT, LargeOffsetGEP);

  GetElementPtrInst *GEP = LargeOffsetGEP.first;
  if (GEP && !NewGEPBases.count(GEP)) {
    // If splitting the underlying data structure can reduce the offset of a
    // GEP, collect the GEP.  Skip the GEPs that are the new bases of
    // previously split data structures.
    LargeOffsetGEPMap[GEP->getPointerOperand()].push_back(LargeOffsetGEP);
    if (LargeOffsetGEPID.find(GEP) == LargeOffsetGEPID.end())
      LargeOffsetGEPID[GEP] = LargeOffsetGEPID.size();
  }

  NewAddrMode.OriginalValue = V;
  if (!AddrModes.addNewAddrMode(NewAddrMode))
    break;
}

// Try to combine the AddrModes we've collected. If we couldn't collect any,
// or we have multiple but either couldn't combine them or combining them
// wouldn't do anything useful, bail out now.
if (!AddrModes.combineAddrModes()) {
  TPT.rollback(LastKnownGood);
  return false;
}
TPT.commit();

// Get the combined AddrMode (or the only AddrMode, if we only had one).
ExtAddrMode AddrMode = AddrModes.getAddrMode();

// If all the instructions matched are already in this BB, don't do anything.
// If we saw a Phi node then it is not local definitely, and if we saw a select
// then we want to push the address calculation past it even if it's already
// in this BB.
if (!PhiOrSelectSeen && none_of(AddrModeInsts, [&](Value *V) {
      return IsNonLocalValue(V, MemoryInst->getParent());
                })) {
  LLVM_DEBUG(dbgs() << "CGP: Found      local addrmode: " << AddrModedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: Found      local addrmode: "
 << AddrMode << "\n"; } } while (false)
                    << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: Found      local addrmode: "
 << AddrMode << "\n"; } } while (false);
  return false;
}

// Insert this computation right after this user.  Since our caller is
// scanning from the top of the BB to the bottom, reuse of the expr are
// guaranteed to happen later.
IRBuilder<> Builder(MemoryInst);

// Now that we determined the addressing expression we want to use and know
// that we have to sink it into this block.  Check to see if we have already
// done this for some other load/store instr in this block.  If so, reuse
// the computation.  Before attempting reuse, check if the address is valid
// as it may have been erased.

WeakTrackingVH SunkAddrVH = SunkAddrs[Addr];

Value * SunkAddr = SunkAddrVH.pointsToAliveValue() ? SunkAddrVH : nullptr;
if (SunkAddr) {
  LLVM_DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrModedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: Reusing nonlocal addrmode: "
 << AddrMode << " for " << *MemoryInst <<
 "\n"; } } while (false)
                    << " for " << *MemoryInst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: Reusing nonlocal addrmode: "
 << AddrMode << " for " << *MemoryInst <<
 "\n"; } } while (false);
  if (SunkAddr->getType() != Addr->getType())
    SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType());
} else if (AddrSinkUsingGEPs || (!AddrSinkUsingGEPs.getNumOccurrences() &&
                                 TM && SubtargetInfo->addrSinkUsingGEPs())) {
  // By default, we use the GEP-based method when AA is used later. This
  // prevents new inttoptr/ptrtoint pairs from degrading AA capabilities.
  LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrModedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: SINKING nonlocal addrmode: "
 << AddrMode << " for " << *MemoryInst <<
 "\n"; } } while (false)
                    << " for " << *MemoryInst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: SINKING nonlocal addrmode: "
 << AddrMode << " for " << *MemoryInst <<
 "\n"; } } while (false);
  Type *IntPtrTy = DL->getIntPtrType(Addr->getType());
  Value *ResultPtr = nullptr, *ResultIndex = nullptr;

  // First, find the pointer.
  if (AddrMode.BaseReg && AddrMode.BaseReg->getType()->isPointerTy()) {
    ResultPtr = AddrMode.BaseReg;
    AddrMode.BaseReg = nullptr;
  }

  if (AddrMode.Scale && AddrMode.ScaledReg->getType()->isPointerTy()) {
    // We can't add more than one pointer together, nor can we scale a
    // pointer (both of which seem meaningless).
    if (ResultPtr || AddrMode.Scale != 1)
      return false;

    ResultPtr = AddrMode.ScaledReg;
    AddrMode.Scale = 0;
  }

  // It is only safe to sign extend the BaseReg if we know that the math
  // required to create it did not overflow before we extend it. Since
  // the original IR value was tossed in favor of a constant back when
  // the AddrMode was created we need to bail out gracefully if widths
  // do not match instead of extending it.
  //
  // (See below for code to add the scale.)
  if (AddrMode.Scale) {
    Type *ScaledRegTy = AddrMode.ScaledReg->getType();
    if (cast<IntegerType>(IntPtrTy)->getBitWidth() >
        cast<IntegerType>(ScaledRegTy)->getBitWidth())
      return false;
  }

  if (AddrMode.BaseGV) {
    if (ResultPtr)
      return false;

    ResultPtr = AddrMode.BaseGV;
  }

  // If the real base value actually came from an inttoptr, then the matcher
  // will look through it and provide only the integer value. In that case,
  // use it here.
  if (!DL->isNonIntegralPointerType(Addr->getType())) {
    if (!ResultPtr && AddrMode.BaseReg) {
      ResultPtr = Builder.CreateIntToPtr(AddrMode.BaseReg, Addr->getType(),
                                         "sunkaddr");
      AddrMode.BaseReg = nullptr;
    } else if (!ResultPtr && AddrMode.Scale == 1) {
      ResultPtr = Builder.CreateIntToPtr(AddrMode.ScaledReg, Addr->getType(),
                                         "sunkaddr");
      AddrMode.Scale = 0;
    }
  }

  if (!ResultPtr &&
      !AddrMode.BaseReg && !AddrMode.Scale && !AddrMode.BaseOffs) {
    SunkAddr = Constant::getNullValue(Addr->getType());
  } else if (!ResultPtr) {
    return false;
  } else {
    Type *I8PtrTy =
        Builder.getInt8PtrTy(Addr->getType()->getPointerAddressSpace());
    Type *I8Ty = Builder.getInt8Ty();

    // Start with the base register. Do this first so that subsequent address
    // matching finds it last, which will prevent it from trying to match it
    // as the scaled value in case it happens to be a mul. That would be
    // problematic if we've sunk a different mul for the scale, because then
    // we'd end up sinking both muls.
    if (AddrMode.BaseReg) {
      Value *V = AddrMode.BaseReg;
      if (V->getType() != IntPtrTy)
        V = Builder.CreateIntCast(V, IntPtrTy, /*isSigned=*/true, "sunkaddr");

      ResultIndex = V;
    }

    // Add the scale value.
    if (AddrMode.Scale) {
      Value *V = AddrMode.ScaledReg;
      if (V->getType() == IntPtrTy) {
        // done.
      } else {
        assert(cast<IntegerType>(IntPtrTy)->getBitWidth() <((cast<IntegerType>(IntPtrTy)->getBitWidth() < cast
<IntegerType>(V->getType())->getBitWidth() &&
 "We can't transform if ScaledReg is too narrow") ? static_cast
<void> (0) : __assert_fail ("cast<IntegerType>(IntPtrTy)->getBitWidth() < cast<IntegerType>(V->getType())->getBitWidth() && \"We can't transform if ScaledReg is too narrow\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 4886, __PRETTY_FUNCTION__))
               cast<IntegerType>(V->getType())->getBitWidth() &&((cast<IntegerType>(IntPtrTy)->getBitWidth() < cast
<IntegerType>(V->getType())->getBitWidth() &&
 "We can't transform if ScaledReg is too narrow") ? static_cast
<void> (0) : __assert_fail ("cast<IntegerType>(IntPtrTy)->getBitWidth() < cast<IntegerType>(V->getType())->getBitWidth() && \"We can't transform if ScaledReg is too narrow\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 4886, __PRETTY_FUNCTION__))
               "We can't transform if ScaledReg is too narrow")((cast<IntegerType>(IntPtrTy)->getBitWidth() < cast
<IntegerType>(V->getType())->getBitWidth() &&
 "We can't transform if ScaledReg is too narrow") ? static_cast
<void> (0) : __assert_fail ("cast<IntegerType>(IntPtrTy)->getBitWidth() < cast<IntegerType>(V->getType())->getBitWidth() && \"We can't transform if ScaledReg is too narrow\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 4886, __PRETTY_FUNCTION__));
        V = Builder.CreateTrunc(V, IntPtrTy, "sunkaddr");
      }

      if (AddrMode.Scale != 1)
        V = Builder.CreateMul(V, ConstantInt::get(IntPtrTy, AddrMode.Scale),
                              "sunkaddr");
      if (ResultIndex)
        ResultIndex = Builder.CreateAdd(ResultIndex, V, "sunkaddr");
      else
        ResultIndex = V;
    }

    // Add in the Base Offset if present.
    if (AddrMode.BaseOffs) {
      Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
      if (ResultIndex) {
        // We need to add this separately from the scale above to help with
        // SDAG consecutive load/store merging.
        if (ResultPtr->getType() != I8PtrTy)
          ResultPtr = Builder.CreatePointerCast(ResultPtr, I8PtrTy);
        ResultPtr =
            AddrMode.InBounds
                ? Builder.CreateInBoundsGEP(I8Ty, ResultPtr, ResultIndex,
                                            "sunkaddr")
                : Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr");
      }

      ResultIndex = V;
    }

    if (!ResultIndex) {
      SunkAddr = ResultPtr;
    } else {
      if (ResultPtr->getType() != I8PtrTy)
        ResultPtr = Builder.CreatePointerCast(ResultPtr, I8PtrTy);
      SunkAddr =
          AddrMode.InBounds
              ? Builder.CreateInBoundsGEP(I8Ty, ResultPtr, ResultIndex,
                                          "sunkaddr")
              : Builder.CreateGEP(I8Ty, ResultPtr, ResultIndex, "sunkaddr");
    }

    if (SunkAddr->getType() != Addr->getType())
      SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType());
  }
} else {
  // We'd require a ptrtoint/inttoptr down the line, which we can't do for
  // non-integral pointers, so in that case bail out now.
  Type *BaseTy = AddrMode.BaseReg ? AddrMode.BaseReg->getType() : nullptr;
  Type *ScaleTy = AddrMode.Scale ? AddrMode.ScaledReg->getType() : nullptr;
  PointerType *BasePtrTy = dyn_cast_or_null<PointerType>(BaseTy);
  PointerType *ScalePtrTy = dyn_cast_or_null<PointerType>(ScaleTy);
  if (DL->isNonIntegralPointerType(Addr->getType()) ||
      (BasePtrTy && DL->isNonIntegralPointerType(BasePtrTy)) ||
      (ScalePtrTy && DL->isNonIntegralPointerType(ScalePtrTy)) ||
      (AddrMode.BaseGV &&
       DL->isNonIntegralPointerType(AddrMode.BaseGV->getType())))
    return false;

  LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrModedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: SINKING nonlocal addrmode: "
 << AddrMode << " for " << *MemoryInst <<
 "\n"; } } while (false)
                    << " for " << *MemoryInst << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "CGP: SINKING nonlocal addrmode: "
 << AddrMode << " for " << *MemoryInst <<
 "\n"; } } while (false);
  Type *IntPtrTy = DL->getIntPtrType(Addr->getType());
  Value *Result = nullptr;

  // Start with the base register. Do this first so that subsequent address
  // matching finds it last, which will prevent it from trying to match it
  // as the scaled value in case it happens to be a mul. That would be
  // problematic if we've sunk a different mul for the scale, because then
  // we'd end up sinking both muls.
  if (AddrMode.BaseReg) {
    Value *V = AddrMode.BaseReg;
    if (V->getType()->isPointerTy())
      V = Builder.CreatePtrToInt(V, IntPtrTy, "sunkaddr");
    if (V->getType() != IntPtrTy)
      V = Builder.CreateIntCast(V, IntPtrTy, /*isSigned=*/true, "sunkaddr");
    Result = V;
  }

  // Add the scale value.
  if (AddrMode.Scale) {
    Value *V = AddrMode.ScaledReg;
    if (V->getType() == IntPtrTy) {
      // done.
    } else if (V->getType()->isPointerTy()) {
      V = Builder.CreatePtrToInt(V, IntPtrTy, "sunkaddr");
    } else if (cast<IntegerType>(IntPtrTy)->getBitWidth() <
               cast<IntegerType>(V->getType())->getBitWidth()) {
      V = Builder.CreateTrunc(V, IntPtrTy, "sunkaddr");
    } else {
      // It is only safe to sign extend the BaseReg if we know that the math
      // required to create it did not overflow before we extend it. Since
      // the original IR value was tossed in favor of a constant back when
      // the AddrMode was created we need to bail out gracefully if widths
      // do not match instead of extending it.
      Instruction *I = dyn_cast_or_null<Instruction>(Result);
      if (I && (Result != AddrMode.BaseReg))
        I->eraseFromParent();
      return false;
    }
    if (AddrMode.Scale != 1)
      V = Builder.CreateMul(V, ConstantInt::get(IntPtrTy, AddrMode.Scale),
                            "sunkaddr");
    if (Result)
      Result = Builder.CreateAdd(Result, V, "sunkaddr");
    else
      Result = V;
  }

  // Add in the BaseGV if present.
  if (AddrMode.BaseGV) {
    Value *V = Builder.CreatePtrToInt(AddrMode.BaseGV, IntPtrTy, "sunkaddr");
    if (Result)
      Result = Builder.CreateAdd(Result, V, "sunkaddr");
    else
      Result = V;
  }

  // Add in the Base Offset if present.
  if (AddrMode.BaseOffs) {
    Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs);
    if (Result)
      Result = Builder.CreateAdd(Result, V, "sunkaddr");
    else
      Result = V;
  }

  if (!Result)
    SunkAddr = Constant::getNullValue(Addr->getType());
  else
    SunkAddr = Builder.CreateIntToPtr(Result, Addr->getType(), "sunkaddr");
}

MemoryInst->replaceUsesOfWith(Repl, SunkAddr);
// Store the newly computed address into the cache. In the case we reused a
// value, this should be idempotent.
SunkAddrs[Addr] = WeakTrackingVH(SunkAddr);

// If we have no uses, recursively delete the value and all dead instructions
// using it.
if (Repl->use_empty()) {
  // This can cause recursive deletion, which can invalidate our iterator.
  // Use a WeakTrackingVH to hold onto it in case this happens.
  Value *CurValue = &*CurInstIterator;
  WeakTrackingVH IterHandle(CurValue);
  BasicBlock *BB = CurInstIterator->getParent();

  RecursivelyDeleteTriviallyDeadInstructions(Repl, TLInfo);

  if (IterHandle != CurValue) {
    // If the iterator instruction was recursively deleted, start over at the
    // start of the block.
    CurInstIterator = BB->begin();
    SunkAddrs.clear();
  }
}
++NumMemoryInsts;
return true;
5044}

5046/// If there are any memory operands, use OptimizeMemoryInst to sink their
5047/// address computing into the block when possible / profitable.
5048bool CodeGenPrepare::optimizeInlineAsmInst(CallInst *CS) {
bool MadeChange = false;

const TargetRegisterInfo *TRI =
    TM->getSubtargetImpl(*CS->getFunction())->getRegisterInfo();
TargetLowering::AsmOperandInfoVector TargetConstraints =
    TLI->ParseConstraints(*DL, TRI, CS);
unsigned ArgNo = 0;
for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
  TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];

  // Compute the constraint code and ConstraintType to use.
  TLI->ComputeConstraintToUse(OpInfo, SDValue());

  if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
      OpInfo.isIndirect) {
    Value *OpVal = CS->getArgOperand(ArgNo++);
    MadeChange |= optimizeMemoryInst(CS, OpVal, OpVal->getType(), ~0u);
  } else if (OpInfo.Type == InlineAsm::isInput)
    ArgNo++;
}

return MadeChange;
5071}

5073/// Check if all the uses of \p Val are equivalent (or free) zero or
5074/// sign extensions.
5075static bool hasSameExtUse(Value *Val, const TargetLowering &TLI) {
assert(!Val->use_empty() && "Input must have at least one use")((!Val->use_empty() && "Input must have at least one use"
) ? static_cast<void> (0) : __assert_fail ("!Val->use_empty() && \"Input must have at least one use\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5076, __PRETTY_FUNCTION__));
const Instruction *FirstUser = cast<Instruction>(*Val->user_begin());
bool IsSExt = isa<SExtInst>(FirstUser);
Type *ExtTy = FirstUser->getType();
for (const User *U : Val->users()) {
  const Instruction *UI = cast<Instruction>(U);
  if ((IsSExt && !isa<SExtInst>(UI)) || (!IsSExt && !isa<ZExtInst>(UI)))
    return false;
  Type *CurTy = UI->getType();
  // Same input and output types: Same instruction after CSE.
  if (CurTy == ExtTy)
    continue;

  // If IsSExt is true, we are in this situation:
  // a = Val
  // b = sext ty1 a to ty2
  // c = sext ty1 a to ty3
  // Assuming ty2 is shorter than ty3, this could be turned into:
  // a = Val
  // b = sext ty1 a to ty2
  // c = sext ty2 b to ty3
  // However, the last sext is not free.
  if (IsSExt)
    return false;

  // This is a ZExt, maybe this is free to extend from one type to another.
  // In that case, we would not account for a different use.
  Type *NarrowTy;
  Type *LargeTy;
  if (ExtTy->getScalarType()->getIntegerBitWidth() >
      CurTy->getScalarType()->getIntegerBitWidth()) {
    NarrowTy = CurTy;
    LargeTy = ExtTy;
  } else {
    NarrowTy = ExtTy;
    LargeTy = CurTy;
  }

  if (!TLI.isZExtFree(NarrowTy, LargeTy))
    return false;
}
// All uses are the same or can be derived from one another for free.
return true;
5119}

5121/// Try to speculatively promote extensions in \p Exts and continue
5122/// promoting through newly promoted operands recursively as far as doing so is
5123/// profitable. Save extensions profitably moved up, in \p ProfitablyMovedExts.
5124/// When some promotion happened, \p TPT contains the proper state to revert
5125/// them.
5126///
5127/// \return true if some promotion happened, false otherwise.
5128bool CodeGenPrepare::tryToPromoteExts(
  TypePromotionTransaction &TPT, const SmallVectorImpl<Instruction *> &Exts,
  SmallVectorImpl<Instruction *> &ProfitablyMovedExts,
  unsigned CreatedInstsCost) {
bool Promoted = false;

// Iterate over all the extensions to try to promote them.
for (auto I : Exts) {
  // Early check if we directly have ext(load).
  if (isa<LoadInst>(I->getOperand(0))) {
    ProfitablyMovedExts.push_back(I);
    continue;
  }

  // Check whether or not we want to do any promotion.  The reason we have
  // this check inside the for loop is to catch the case where an extension
  // is directly fed by a load because in such case the extension can be moved
  // up without any promotion on its operands.
  if (!TLI || !TLI->enableExtLdPromotion() || DisableExtLdPromotion)
    return false;

  // Get the action to perform the promotion.
  TypePromotionHelper::Action TPH =
      TypePromotionHelper::getAction(I, InsertedInsts, *TLI, PromotedInsts);
  // Check if we can promote.
  if (!TPH) {
    // Save the current extension as we cannot move up through its operand.
    ProfitablyMovedExts.push_back(I);
    continue;
  }

  // Save the current state.
  TypePromotionTransaction::ConstRestorationPt LastKnownGood =
      TPT.getRestorationPoint();
  SmallVector<Instruction *, 4> NewExts;
  unsigned NewCreatedInstsCost = 0;
  unsigned ExtCost = !TLI->isExtFree(I);
  // Promote.
  Value *PromotedVal = TPH(I, TPT, PromotedInsts, NewCreatedInstsCost,
                           &NewExts, nullptr, *TLI);
  assert(PromotedVal &&((PromotedVal && "TypePromotionHelper should have filtered out those cases"
) ? static_cast<void> (0) : __assert_fail ("PromotedVal && \"TypePromotionHelper should have filtered out those cases\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5169, __PRETTY_FUNCTION__))
         "TypePromotionHelper should have filtered out those cases")((PromotedVal && "TypePromotionHelper should have filtered out those cases"
) ? static_cast<void> (0) : __assert_fail ("PromotedVal && \"TypePromotionHelper should have filtered out those cases\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5169, __PRETTY_FUNCTION__));

  // We would be able to merge only one extension in a load.
  // Therefore, if we have more than 1 new extension we heuristically
  // cut this search path, because it means we degrade the code quality.
  // With exactly 2, the transformation is neutral, because we will merge
  // one extension but leave one. However, we optimistically keep going,
  // because the new extension may be removed too.
  long long TotalCreatedInstsCost = CreatedInstsCost + NewCreatedInstsCost;
  // FIXME: It would be possible to propagate a negative value instead of
  // conservatively ceiling it to 0.
  TotalCreatedInstsCost =
      std::max((long long)0, (TotalCreatedInstsCost - ExtCost));
  if (!StressExtLdPromotion &&
      (TotalCreatedInstsCost > 1 ||
       !isPromotedInstructionLegal(*TLI, *DL, PromotedVal))) {
    // This promotion is not profitable, rollback to the previous state, and
    // save the current extension in ProfitablyMovedExts as the latest
    // speculative promotion turned out to be unprofitable.
    TPT.rollback(LastKnownGood);
    ProfitablyMovedExts.push_back(I);
    continue;
  }
  // Continue promoting NewExts as far as doing so is profitable.
  SmallVector<Instruction *, 2> NewlyMovedExts;
  (void)tryToPromoteExts(TPT, NewExts, NewlyMovedExts, TotalCreatedInstsCost);
  bool NewPromoted = false;
  for (auto ExtInst : NewlyMovedExts) {
    Instruction *MovedExt = cast<Instruction>(ExtInst);
    Value *ExtOperand = MovedExt->getOperand(0);
    // If we have reached to a load, we need this extra profitability check
    // as it could potentially be merged into an ext(load).
    if (isa<LoadInst>(ExtOperand) &&
        !(StressExtLdPromotion || NewCreatedInstsCost <= ExtCost ||
          (ExtOperand->hasOneUse() || hasSameExtUse(ExtOperand, *TLI))))
      continue;

    ProfitablyMovedExts.push_back(MovedExt);
    NewPromoted = true;
  }

  // If none of speculative promotions for NewExts is profitable, rollback
  // and save the current extension (I) as the last profitable extension.
  if (!NewPromoted) {
    TPT.rollback(LastKnownGood);
    ProfitablyMovedExts.push_back(I);
    continue;
  }
  // The promotion is profitable.
  Promoted = true;
}
return Promoted;
5221}

5223/// Merging redundant sexts when one is dominating the other.
5224bool CodeGenPrepare::mergeSExts(Function &F) {
bool Changed = false;
for (auto &Entry : ValToSExtendedUses) {
  SExts &Insts = Entry.second;
  SExts CurPts;
  for (Instruction *Inst : Insts) {
    if (RemovedInsts.count(Inst) || !isa<SExtInst>(Inst) ||
        Inst->getOperand(0) != Entry.first)
      continue;
    bool inserted = false;
    for (auto &Pt : CurPts) {
      if (getDT(F).dominates(Inst, Pt)) {
        Pt->replaceAllUsesWith(Inst);
        RemovedInsts.insert(Pt);
        Pt->removeFromParent();
        Pt = Inst;
        inserted = true;
        Changed = true;
        break;
      }
      if (!getDT(F).dominates(Pt, Inst))
        // Give up if we need to merge in a common dominator as the
        // experiments show it is not profitable.
        continue;
      Inst->replaceAllUsesWith(Pt);
      RemovedInsts.insert(Inst);
      Inst->removeFromParent();
      inserted = true;
      Changed = true;
      break;
    }
    if (!inserted)
      CurPts.push_back(Inst);
  }
}
return Changed;
5260}

5262// Spliting large data structures so that the GEPs accessing them can have
5263// smaller offsets so that they can be sunk to the same blocks as their users.
5264// For example, a large struct starting from %base is splitted into two parts
5265// where the second part starts from %new_base.
5266//
5267// Before:
5268// BB0:
5269//   %base     =
5270//
5271// BB1:
5272//   %gep0     = gep %base, off0
5273//   %gep1     = gep %base, off1
5274//   %gep2     = gep %base, off2
5275//
5276// BB2:
5277//   %load1    = load %gep0
5278//   %load2    = load %gep1
5279//   %load3    = load %gep2
5280//
5281// After:
5282// BB0:
5283//   %base     =
5284//   %new_base = gep %base, off0
5285//
5286// BB1:
5287//   %new_gep0 = %new_base
5288//   %new_gep1 = gep %new_base, off1 - off0
5289//   %new_gep2 = gep %new_base, off2 - off0
5290//
5291// BB2:
5292//   %load1    = load i32, i32* %new_gep0
5293//   %load2    = load i32, i32* %new_gep1
5294//   %load3    = load i32, i32* %new_gep2
5295//
5296// %new_gep1 and %new_gep2 can be sunk to BB2 now after the splitting because
5297// their offsets are smaller enough to fit into the addressing mode.
5298bool CodeGenPrepare::splitLargeGEPOffsets() {
bool Changed = false;
for (auto &Entry : LargeOffsetGEPMap) {
  Value *OldBase = Entry.first;
  SmallVectorImpl<std::pair<AssertingVH<GetElementPtrInst>, int64_t>>
      &LargeOffsetGEPs = Entry.second;
  auto compareGEPOffset =
      [&](const std::pair<GetElementPtrInst *, int64_t> &LHS,
          const std::pair<GetElementPtrInst *, int64_t> &RHS) {
        if (LHS.first == RHS.first)
          return false;
        if (LHS.second != RHS.second)
          return LHS.second < RHS.second;
        return LargeOffsetGEPID[LHS.first] < LargeOffsetGEPID[RHS.first];
      };
  // Sorting all the GEPs of the same data structures based on the offsets.
  llvm::sort(LargeOffsetGEPs, compareGEPOffset);
  LargeOffsetGEPs.erase(
      std::unique(LargeOffsetGEPs.begin(), LargeOffsetGEPs.end()),
      LargeOffsetGEPs.end());
  // Skip if all the GEPs have the same offsets.
  if (LargeOffsetGEPs.front().second == LargeOffsetGEPs.back().second)
    continue;
  GetElementPtrInst *BaseGEP = LargeOffsetGEPs.begin()->first;
  int64_t BaseOffset = LargeOffsetGEPs.begin()->second;
  Value *NewBaseGEP = nullptr;

  auto LargeOffsetGEP = LargeOffsetGEPs.begin();
  while (LargeOffsetGEP != LargeOffsetGEPs.end()) {
    GetElementPtrInst *GEP = LargeOffsetGEP->first;
    int64_t Offset = LargeOffsetGEP->second;
    if (Offset != BaseOffset) {
      TargetLowering::AddrMode AddrMode;
      AddrMode.BaseOffs = Offset - BaseOffset;
      // The result type of the GEP might not be the type of the memory
      // access.
      if (!TLI->isLegalAddressingMode(*DL, AddrMode,
                                      GEP->getResultElementType(),
                                      GEP->getAddressSpace())) {
        // We need to create a new base if the offset to the current base is
        // too large to fit into the addressing mode. So, a very large struct
        // may be splitted into several parts.
        BaseGEP = GEP;
        BaseOffset = Offset;
        NewBaseGEP = nullptr;
      }
    }

    // Generate a new GEP to replace the current one.
    LLVMContext &Ctx = GEP->getContext();
    Type *IntPtrTy = DL->getIntPtrType(GEP->getType());
    Type *I8PtrTy =
        Type::getInt8PtrTy(Ctx, GEP->getType()->getPointerAddressSpace());
    Type *I8Ty = Type::getInt8Ty(Ctx);

    if (!NewBaseGEP) {
      // Create a new base if we don't have one yet.  Find the insertion
      // pointer for the new base first.
      BasicBlock::iterator NewBaseInsertPt;
      BasicBlock *NewBaseInsertBB;
      if (auto *BaseI = dyn_cast<Instruction>(OldBase)) {
        // If the base of the struct is an instruction, the new base will be
        // inserted close to it.
        NewBaseInsertBB = BaseI->getParent();
        if (isa<PHINode>(BaseI))
          NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt();
        else if (InvokeInst *Invoke = dyn_cast<InvokeInst>(BaseI)) {
          NewBaseInsertBB =
              SplitEdge(NewBaseInsertBB, Invoke->getNormalDest());
          NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt();
        } else
          NewBaseInsertPt = std::next(BaseI->getIterator());
      } else {
        // If the current base is an argument or global value, the new base
        // will be inserted to the entry block.
        NewBaseInsertBB = &BaseGEP->getFunction()->getEntryBlock();
        NewBaseInsertPt = NewBaseInsertBB->getFirstInsertionPt();
      }
      IRBuilder<> NewBaseBuilder(NewBaseInsertBB, NewBaseInsertPt);
      // Create a new base.
      Value *BaseIndex = ConstantInt::get(IntPtrTy, BaseOffset);
      NewBaseGEP = OldBase;
      if (NewBaseGEP->getType() != I8PtrTy)
        NewBaseGEP = NewBaseBuilder.CreatePointerCast(NewBaseGEP, I8PtrTy);
      NewBaseGEP =
          NewBaseBuilder.CreateGEP(I8Ty, NewBaseGEP, BaseIndex, "splitgep");
      NewGEPBases.insert(NewBaseGEP);
    }

    IRBuilder<> Builder(GEP);
    Value *NewGEP = NewBaseGEP;
    if (Offset == BaseOffset) {
      if (GEP->getType() != I8PtrTy)
        NewGEP = Builder.CreatePointerCast(NewGEP, GEP->getType());
    } else {
      // Calculate the new offset for the new GEP.
      Value *Index = ConstantInt::get(IntPtrTy, Offset - BaseOffset);
      NewGEP = Builder.CreateGEP(I8Ty, NewBaseGEP, Index);

      if (GEP->getType() != I8PtrTy)
        NewGEP = Builder.CreatePointerCast(NewGEP, GEP->getType());
    }
    GEP->replaceAllUsesWith(NewGEP);
    LargeOffsetGEPID.erase(GEP);
    LargeOffsetGEP = LargeOffsetGEPs.erase(LargeOffsetGEP);
    GEP->eraseFromParent();
    Changed = true;
  }
}
return Changed;
5408}

5410/// Return true, if an ext(load) can be formed from an extension in
5411/// \p MovedExts.
5412bool CodeGenPrepare::canFormExtLd(
  const SmallVectorImpl<Instruction *> &MovedExts, LoadInst *&LI,
  Instruction *&Inst, bool HasPromoted) {
for (auto *MovedExtInst : MovedExts) {
  if (isa<LoadInst>(MovedExtInst->getOperand(0))) {
    LI = cast<LoadInst>(MovedExtInst->getOperand(0));
    Inst = MovedExtInst;
    break;
  }
}
if (!LI)
  return false;

// If they're already in the same block, there's nothing to do.
// Make the cheap checks first if we did not promote.
// If we promoted, we need to check if it is indeed profitable.
if (!HasPromoted && LI->getParent() == Inst->getParent())
  return false;

return TLI->isExtLoad(LI, Inst, *DL);
5432}

5434/// Move a zext or sext fed by a load into the same basic block as the load,
5435/// unless conditions are unfavorable. This allows SelectionDAG to fold the
5436/// extend into the load.
5437///
5438/// E.g.,
5439/// \code
5440/// %ld = load i32* %addr
5441/// %add = add nuw i32 %ld, 4
5442/// %zext = zext i32 %add to i64
5443// \endcode
5444/// =>
5445/// \code
5446/// %ld = load i32* %addr
5447/// %zext = zext i32 %ld to i64
5448/// %add = add nuw i64 %zext, 4
5449/// \encode
5450/// Note that the promotion in %add to i64 is done in tryToPromoteExts(), which
5451/// allow us to match zext(load i32*) to i64.
5452///
5453/// Also, try to promote the computations used to obtain a sign extended
5454/// value used into memory accesses.
5455/// E.g.,
5456/// \code
5457/// a = add nsw i32 b, 3
5458/// d = sext i32 a to i64
5459/// e = getelementptr ..., i64 d
5460/// \endcode
5461/// =>
5462/// \code
5463/// f = sext i32 b to i64
5464/// a = add nsw i64 f, 3
5465/// e = getelementptr ..., i64 a
5466/// \endcode
5467///
5468/// \p Inst[in/out] the extension may be modified during the process if some
5469/// promotions apply.
5470bool CodeGenPrepare::optimizeExt(Instruction *&Inst) {
// ExtLoad formation and address type promotion infrastructure requires TLI to
// be effective.
if (!TLI)
  return false;

bool AllowPromotionWithoutCommonHeader = false;
/// See if it is an interesting sext operations for the address type
/// promotion before trying to promote it, e.g., the ones with the right
/// type and used in memory accesses.
bool ATPConsiderable = TTI->shouldConsiderAddressTypePromotion(
    *Inst, AllowPromotionWithoutCommonHeader);
TypePromotionTransaction TPT(RemovedInsts);
TypePromotionTransaction::ConstRestorationPt LastKnownGood =
    TPT.getRestorationPoint();
SmallVector<Instruction *, 1> Exts;
SmallVector<Instruction *, 2> SpeculativelyMovedExts;
Exts.push_back(Inst);

bool HasPromoted = tryToPromoteExts(TPT, Exts, SpeculativelyMovedExts);

// Look for a load being extended.
LoadInst *LI = nullptr;
Instruction *ExtFedByLoad;

// Try to promote a chain of computation if it allows to form an extended
// load.
if (canFormExtLd(SpeculativelyMovedExts, LI, ExtFedByLoad, HasPromoted)) {
  assert(LI && ExtFedByLoad && "Expect a valid load and extension")((LI && ExtFedByLoad && "Expect a valid load and extension"
) ? static_cast<void> (0) : __assert_fail ("LI && ExtFedByLoad && \"Expect a valid load and extension\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5498, __PRETTY_FUNCTION__));
  TPT.commit();
  // Move the extend into the same block as the load
  ExtFedByLoad->moveAfter(LI);
  // CGP does not check if the zext would be speculatively executed when moved
  // to the same basic block as the load. Preserving its original location
  // would pessimize the debugging experience, as well as negatively impact
  // the quality of sample pgo. We don't want to use "line 0" as that has a
  // size cost in the line-table section and logically the zext can be seen as
  // part of the load. Therefore we conservatively reuse the same debug
  // location for the load and the zext.
  ExtFedByLoad->setDebugLoc(LI->getDebugLoc());
  ++NumExtsMoved;
  Inst = ExtFedByLoad;
  return true;
}

// Continue promoting SExts if known as considerable depending on targets.
if (ATPConsiderable &&
    performAddressTypePromotion(Inst, AllowPromotionWithoutCommonHeader,
                                HasPromoted, TPT, SpeculativelyMovedExts))
  return true;

TPT.rollback(LastKnownGood);
return false;
5523}

5525// Perform address type promotion if doing so is profitable.
5526// If AllowPromotionWithoutCommonHeader == false, we should find other sext
5527// instructions that sign extended the same initial value. However, if
5528// AllowPromotionWithoutCommonHeader == true, we expect promoting the
5529// extension is just profitable.
5530bool CodeGenPrepare::performAddressTypePromotion(
  Instruction *&Inst, bool AllowPromotionWithoutCommonHeader,
  bool HasPromoted, TypePromotionTransaction &TPT,
  SmallVectorImpl<Instruction *> &SpeculativelyMovedExts) {
bool Promoted = false;
SmallPtrSet<Instruction *, 1> UnhandledExts;
bool AllSeenFirst = true;
for (auto I : SpeculativelyMovedExts) {
  Value *HeadOfChain = I->getOperand(0);
  DenseMap<Value *, Instruction *>::iterator AlreadySeen =
      SeenChainsForSExt.find(HeadOfChain);
  // If there is an unhandled SExt which has the same header, try to promote
  // it as well.
  if (AlreadySeen != SeenChainsForSExt.end()) {
    if (AlreadySeen->second != nullptr)
      UnhandledExts.insert(AlreadySeen->second);
    AllSeenFirst = false;
  }
}

if (!AllSeenFirst || (AllowPromotionWithoutCommonHeader &&
                      SpeculativelyMovedExts.size() == 1)) {
  TPT.commit();
  if (HasPromoted)
    Promoted = true;
  for (auto I : SpeculativelyMovedExts) {
    Value *HeadOfChain = I->getOperand(0);
    SeenChainsForSExt[HeadOfChain] = nullptr;
    ValToSExtendedUses[HeadOfChain].push_back(I);
  }
  // Update Inst as promotion happen.
  Inst = SpeculativelyMovedExts.pop_back_val();
} else {
  // This is the first chain visited from the header, keep the current chain
  // as unhandled. Defer to promote this until we encounter another SExt
  // chain derived from the same header.
  for (auto I : SpeculativelyMovedExts) {
    Value *HeadOfChain = I->getOperand(0);
    SeenChainsForSExt[HeadOfChain] = Inst;
  }
  return false;
}

if (!AllSeenFirst && !UnhandledExts.empty())
  for (auto VisitedSExt : UnhandledExts) {
    if (RemovedInsts.count(VisitedSExt))
      continue;
    TypePromotionTransaction TPT(RemovedInsts);
    SmallVector<Instruction *, 1> Exts;
    SmallVector<Instruction *, 2> Chains;
    Exts.push_back(VisitedSExt);
    bool HasPromoted = tryToPromoteExts(TPT, Exts, Chains);
    TPT.commit();
    if (HasPromoted)
      Promoted = true;
    for (auto I : Chains) {
      Value *HeadOfChain = I->getOperand(0);
      // Mark this as handled.
      SeenChainsForSExt[HeadOfChain] = nullptr;
      ValToSExtendedUses[HeadOfChain].push_back(I);
    }
  }
return Promoted;
5593}

5595bool CodeGenPrepare::optimizeExtUses(Instruction *I) {
BasicBlock *DefBB = I->getParent();

// If the result of a {s|z}ext and its source are both live out, rewrite all
// other uses of the source with result of extension.
Value *Src = I->getOperand(0);
if (Src->hasOneUse())
  return false;

// Only do this xform if truncating is free.
if (TLI && !TLI->isTruncateFree(I->getType(), Src->getType()))
  return false;

// Only safe to perform the optimization if the source is also defined in
// this block.
if (!isa<Instruction>(Src) || DefBB != cast<Instruction>(Src)->getParent())
  return false;

bool DefIsLiveOut = false;
for (User *U : I->users()) {
  Instruction *UI = cast<Instruction>(U);

  // Figure out which BB this ext is used in.
  BasicBlock *UserBB = UI->getParent();
  if (UserBB == DefBB) continue;
  DefIsLiveOut = true;
  break;
}
if (!DefIsLiveOut)
  return false;

// Make sure none of the uses are PHI nodes.
for (User *U : Src->users()) {
  Instruction *UI = cast<Instruction>(U);
  BasicBlock *UserBB = UI->getParent();
  if (UserBB == DefBB) continue;
  // Be conservative. We don't want this xform to end up introducing
  // reloads just before load / store instructions.
  if (isa<PHINode>(UI) || isa<LoadInst>(UI) || isa<StoreInst>(UI))
    return false;
}

// InsertedTruncs - Only insert one trunc in each block once.
DenseMap<BasicBlock*, Instruction*> InsertedTruncs;

bool MadeChange = false;
for (Use &U : Src->uses()) {
  Instruction *User = cast<Instruction>(U.getUser());

  // Figure out which BB this ext is used in.
  BasicBlock *UserBB = User->getParent();
  if (UserBB == DefBB) continue;

  // Both src and def are live in this block. Rewrite the use.
  Instruction *&InsertedTrunc = InsertedTruncs[UserBB];

  if (!InsertedTrunc) {
    BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
    assert(InsertPt != UserBB->end())((InsertPt != UserBB->end()) ? static_cast<void> (0)
 : __assert_fail ("InsertPt != UserBB->end()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5653, __PRETTY_FUNCTION__));
    InsertedTrunc = new TruncInst(I, Src->getType(), "", &*InsertPt);
    InsertedInsts.insert(InsertedTrunc);
  }

  // Replace a use of the {s|z}ext source with a use of the result.
  U = InsertedTrunc;
  ++NumExtUses;
  MadeChange = true;
}

return MadeChange;
5665}

5667// Find loads whose uses only use some of the loaded value's bits.  Add an "and"
5668// just after the load if the target can fold this into one extload instruction,
5669// with the hope of eliminating some of the other later "and" instructions using
5670// the loaded value.  "and"s that are made trivially redundant by the insertion
5671// of the new "and" are removed by this function, while others (e.g. those whose
5672// path from the load goes through a phi) are left for isel to potentially
5673// remove.
5674//
5675// For example:
5676//
5677// b0:
5678//   x = load i32
5679//   ...
5680// b1:
5681//   y = and x, 0xff
5682//   z = use y
5683//
5684// becomes:
5685//
5686// b0:
5687//   x = load i32
5688//   x' = and x, 0xff
5689//   ...
5690// b1:
5691//   z = use x'
5692//
5693// whereas:
5694//
5695// b0:
5696//   x1 = load i32
5697//   ...
5698// b1:
5699//   x2 = load i32
5700//   ...
5701// b2:
5702//   x = phi x1, x2
5703//   y = and x, 0xff
5704//
5705// becomes (after a call to optimizeLoadExt for each load):
5706//
5707// b0:
5708//   x1 = load i32
5709//   x1' = and x1, 0xff
5710//   ...
5711// b1:
5712//   x2 = load i32
5713//   x2' = and x2, 0xff
5714//   ...
5715// b2:
5716//   x = phi x1', x2'
5717//   y = and x, 0xff
5718bool CodeGenPrepare::optimizeLoadExt(LoadInst *Load) {
if (!Load->isSimple() || !Load->getType()->isIntOrPtrTy())
50
←
Assuming the condition is false→
51
←
Assuming the condition is false→
52
←
Taking false branch→
  return false;

// Skip loads we've already transformed.
if (Load->hasOneUse() &&
53
←
Assuming the condition is false→
54
←
Taking false branch→
    InsertedInsts.count(cast<Instruction>(*Load->user_begin())))
  return false;

// Look at all uses of Load, looking through phis, to determine how many bits
// of the loaded value are needed.
SmallVector<Instruction *, 8> WorkList;
SmallPtrSet<Instruction *, 16> Visited;
SmallVector<Instruction *, 8> AndsToMaybeRemove;
for (auto *U : Load->users())
  WorkList.push_back(cast<Instruction>(U));

EVT LoadResultVT = TLI->getValueType(*DL, Load->getType());
unsigned BitWidth = LoadResultVT.getSizeInBits();
APInt DemandBits(BitWidth, 0);
APInt WidestAndBits(BitWidth, 0);

while (!WorkList.empty()) {
55
←
Calling 'SmallVectorBase::empty'→
58
←
Returning from 'SmallVectorBase::empty'→
59
←
Loop condition is false. Execution continues on line 5791→
  Instruction *I = WorkList.back();
  WorkList.pop_back();

  // Break use-def graph loops.
  if (!Visited.insert(I).second)
    continue;

  // For a PHI node, push all of its users.
  if (auto *Phi = dyn_cast<PHINode>(I)) {
    for (auto *U : Phi->users())
      WorkList.push_back(cast<Instruction>(U));
    continue;
  }

  switch (I->getOpcode()) {
  case Instruction::And: {
    auto *AndC = dyn_cast<ConstantInt>(I->getOperand(1));
    if (!AndC)
      return false;
    APInt AndBits = AndC->getValue();
    DemandBits |= AndBits;
    // Keep track of the widest and mask we see.
    if (AndBits.ugt(WidestAndBits))
      WidestAndBits = AndBits;
    if (AndBits == WidestAndBits && I->getOperand(0) == Load)
      AndsToMaybeRemove.push_back(I);
    break;
  }

  case Instruction::Shl: {
    auto *ShlC = dyn_cast<ConstantInt>(I->getOperand(1));
    if (!ShlC)
      return false;
    uint64_t ShiftAmt = ShlC->getLimitedValue(BitWidth - 1);
    DemandBits.setLowBits(BitWidth - ShiftAmt);
    break;
  }

  case Instruction::Trunc: {
    EVT TruncVT = TLI->getValueType(*DL, I->getType());
    unsigned TruncBitWidth = TruncVT.getSizeInBits();
    DemandBits.setLowBits(TruncBitWidth);
    break;
  }

  default:
    return false;
  }
}

uint32_t ActiveBits = DemandBits.getActiveBits();
// Avoid hoisting (and (load x) 1) since it is unlikely to be folded by the
// target even if isLoadExtLegal says an i1 EXTLOAD is valid.  For example,
// for the AArch64 target isLoadExtLegal(ZEXTLOAD, i32, i1) returns true, but
// (and (load x) 1) is not matched as a single instruction, rather as a LDR
// followed by an AND.
// TODO: Look into removing this restriction by fixing backends to either
// return false for isLoadExtLegal for i1 or have them select this pattern to
// a single instruction.
//
// Also avoid hoisting if we didn't see any ands with the exact DemandBits
// mask, since these are the only ands that will be removed by isel.
if (ActiveBits <= 1 || !DemandBits.isMask(ActiveBits) ||
60
←
Assuming 'ActiveBits' is > 1→
61
←
Assuming the condition is false→
66
←
Taking false branch→
    WidestAndBits != DemandBits)
62
←
Calling 'APInt::operator!='→
65
←
Returning from 'APInt::operator!='→
  return false;

LLVMContext &Ctx = Load->getType()->getContext();
Type *TruncTy = Type::getIntNTy(Ctx, ActiveBits);
EVT TruncVT = TLI->getValueType(*DL, TruncTy);

// Reject cases that won't be matched as extloads.
if (!LoadResultVT.bitsGT(TruncVT) || !TruncVT.isRound() ||
67
←
Assuming the condition is false→
68
←
Assuming the condition is false→
73
←
Taking false branch→
    !TLI->isLoadExtLegal(ISD::ZEXTLOAD, LoadResultVT, TruncVT))
69
←
Calling 'TargetLoweringBase::isLoadExtLegal'→
72
←
Returning from 'TargetLoweringBase::isLoadExtLegal'→
  return false;

IRBuilder<> Builder(Load->getNextNode());
auto *NewAnd = dyn_cast<Instruction>(
74
←
Assuming the object is not a 'Instruction'→
75
←
'NewAnd' initialized to a null pointer value→
    Builder.CreateAnd(Load, ConstantInt::get(Ctx, DemandBits)));
// Mark this instruction as "inserted by CGP", so that other
// optimizations don't touch it.
InsertedInsts.insert(NewAnd);

// Replace all uses of load with new and (except for the use of load in the
// new and itself).
Load->replaceAllUsesWith(NewAnd);
NewAnd->setOperand(0, Load);
76
←
Called C++ object pointer is null

// Remove any and instructions that are now redundant.
for (auto *And : AndsToMaybeRemove)
  // Check that the and mask is the same as the one we decided to put on the
  // new and.
  if (cast<ConstantInt>(And->getOperand(1))->getValue() == DemandBits) {
    And->replaceAllUsesWith(NewAnd);
    if (&*CurInstIterator == And)
      CurInstIterator = std::next(And->getIterator());
    And->eraseFromParent();
    ++NumAndUses;
  }

++NumAndsAdded;
return true;
5842}

5844/// Check if V (an operand of a select instruction) is an expensive instruction
5845/// that is only used once.
5846static bool sinkSelectOperand(const TargetTransformInfo *TTI, Value *V) {
auto *I = dyn_cast<Instruction>(V);
// If it's safe to speculatively execute, then it should not have side
// effects; therefore, it's safe to sink and possibly *not* execute.
return I && I->hasOneUse() && isSafeToSpeculativelyExecute(I) &&
       TTI->getUserCost(I) >= TargetTransformInfo::TCC_Expensive;
5852}

5854/// Returns true if a SelectInst should be turned into an explicit branch.
5855static bool isFormingBranchFromSelectProfitable(const TargetTransformInfo *TTI,
                                              const TargetLowering *TLI,
                                              SelectInst *SI) {
// If even a predictable select is cheap, then a branch can't be cheaper.
if (!TLI->isPredictableSelectExpensive())
  return false;

// FIXME: This should use the same heuristics as IfConversion to determine
// whether a select is better represented as a branch.

// If metadata tells us that the select condition is obviously predictable,
// then we want to replace the select with a branch.
uint64_t TrueWeight, FalseWeight;
if (SI->extractProfMetadata(TrueWeight, FalseWeight)) {
  uint64_t Max = std::max(TrueWeight, FalseWeight);
  uint64_t Sum = TrueWeight + FalseWeight;
  if (Sum != 0) {
    auto Probability = BranchProbability::getBranchProbability(Max, Sum);
    if (Probability > TLI->getPredictableBranchThreshold())
      return true;
  }
}

CmpInst *Cmp = dyn_cast<CmpInst>(SI->getCondition());

// If a branch is predictable, an out-of-order CPU can avoid blocking on its
// comparison condition. If the compare has more than one use, there's
// probably another cmov or setcc around, so it's not worth emitting a branch.
if (!Cmp || !Cmp->hasOneUse())
  return false;

// If either operand of the select is expensive and only needed on one side
// of the select, we should form a branch.
if (sinkSelectOperand(TTI, SI->getTrueValue()) ||
    sinkSelectOperand(TTI, SI->getFalseValue()))
  return true;

return false;
5893}

5895/// If \p isTrue is true, return the true value of \p SI, otherwise return
5896/// false value of \p SI. If the true/false value of \p SI is defined by any
5897/// select instructions in \p Selects, look through the defining select
5898/// instruction until the true/false value is not defined in \p Selects.
5899static Value *getTrueOrFalseValue(
  SelectInst *SI, bool isTrue,
  const SmallPtrSet<const Instruction *, 2> &Selects) {
Value *V = nullptr;

for (SelectInst *DefSI = SI; DefSI != nullptr && Selects.count(DefSI);
     DefSI = dyn_cast<SelectInst>(V)) {
  assert(DefSI->getCondition() == SI->getCondition() &&((DefSI->getCondition() == SI->getCondition() &&
 "The condition of DefSI does not match with SI") ? static_cast
<void> (0) : __assert_fail ("DefSI->getCondition() == SI->getCondition() && \"The condition of DefSI does not match with SI\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5907, __PRETTY_FUNCTION__))
         "The condition of DefSI does not match with SI")((DefSI->getCondition() == SI->getCondition() &&
 "The condition of DefSI does not match with SI") ? static_cast
<void> (0) : __assert_fail ("DefSI->getCondition() == SI->getCondition() && \"The condition of DefSI does not match with SI\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5907, __PRETTY_FUNCTION__));
  V = (isTrue ? DefSI->getTrueValue() : DefSI->getFalseValue());
}

assert(V && "Failed to get select true/false value")((V && "Failed to get select true/false value") ? static_cast
<void> (0) : __assert_fail ("V && \"Failed to get select true/false value\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5911, __PRETTY_FUNCTION__));
return V;
5913}

5915bool CodeGenPrepare::optimizeShiftInst(BinaryOperator *Shift) {
assert(Shift->isShift() && "Expected a shift")((Shift->isShift() && "Expected a shift") ? static_cast
<void> (0) : __assert_fail ("Shift->isShift() && \"Expected a shift\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 5916, __PRETTY_FUNCTION__));

// If this is (1) a vector shift, (2) shifts by scalars are cheaper than
// general vector shifts, and (3) the shift amount is a select-of-splatted
// values, hoist the shifts before the select:
//   shift Op0, (select Cond, TVal, FVal) -->
//   select Cond, (shift Op0, TVal), (shift Op0, FVal)
//
// This is inverting a generic IR transform when we know that the cost of a
// general vector shift is more than the cost of 2 shift-by-scalars.
// We can't do this effectively in SDAG because we may not be able to
// determine if the select operands are splats from within a basic block.
Type *Ty = Shift->getType();
if (!Ty->isVectorTy() || !TLI->isVectorShiftByScalarCheap(Ty))
  return false;
Value *Cond, *TVal, *FVal;
if (!match(Shift->getOperand(1),
           m_OneUse(m_Select(m_Value(Cond), m_Value(TVal), m_Value(FVal)))))
  return false;
if (!isSplatValue(TVal) || !isSplatValue(FVal))
  return false;

IRBuilder<> Builder(Shift);
BinaryOperator::BinaryOps Opcode = Shift->getOpcode();
Value *NewTVal = Builder.CreateBinOp(Opcode, Shift->getOperand(0), TVal);
Value *NewFVal = Builder.CreateBinOp(Opcode, Shift->getOperand(0), FVal);
Value *NewSel = Builder.CreateSelect(Cond, NewTVal, NewFVal);
Shift->replaceAllUsesWith(NewSel);
Shift->eraseFromParent();
return true;
5946}

5948/// If we have a SelectInst that will likely profit from branch prediction,
5949/// turn it into a branch.
5950bool CodeGenPrepare::optimizeSelectInst(SelectInst *SI) {
// If branch conversion isn't desirable, exit early.
if (DisableSelectToBranch || OptSize || !TLI)
  return false;

// Find all consecutive select instructions that share the same condition.
SmallVector<SelectInst *, 2> ASI;
ASI.push_back(SI);
for (BasicBlock::iterator It = ++BasicBlock::iterator(SI);
     It != SI->getParent()->end(); ++It) {
  SelectInst *I = dyn_cast<SelectInst>(&*It);
  if (I && SI->getCondition() == I->getCondition()) {
    ASI.push_back(I);
  } else {
    break;
  }
}

SelectInst *LastSI = ASI.back();
// Increment the current iterator to skip all the rest of select instructions
// because they will be either "not lowered" or "all lowered" to branch.
CurInstIterator = std::next(LastSI->getIterator());

bool VectorCond = !SI->getCondition()->getType()->isIntegerTy(1);

// Can we convert the 'select' to CF ?
if (VectorCond || SI->getMetadata(LLVMContext::MD_unpredictable))
  return false;

TargetLowering::SelectSupportKind SelectKind;
if (VectorCond)
  SelectKind = TargetLowering::VectorMaskSelect;
else if (SI->getType()->isVectorTy())
  SelectKind = TargetLowering::ScalarCondVectorVal;
else
  SelectKind = TargetLowering::ScalarValSelect;

if (TLI->isSelectSupported(SelectKind) &&
    !isFormingBranchFromSelectProfitable(TTI, TLI, SI))
  return false;

// The DominatorTree needs to be rebuilt by any consumers after this
// transformation. We simply reset here rather than setting the ModifiedDT
// flag to avoid restarting the function walk in runOnFunction for each
// select optimized.
DT.reset();

// Transform a sequence like this:
//    start:
//       %cmp = cmp uge i32 %a, %b
//       %sel = select i1 %cmp, i32 %c, i32 %d
//
// Into:
//    start:
//       %cmp = cmp uge i32 %a, %b
//       br i1 %cmp, label %select.true, label %select.false
//    select.true:
//       br label %select.end
//    select.false:
//       br label %select.end
//    select.end:
//       %sel = phi i32 [ %c, %select.true ], [ %d, %select.false ]
//
// In addition, we may sink instructions that produce %c or %d from
// the entry block into the destination(s) of the new branch.
// If the true or false blocks do not contain a sunken instruction, that
// block and its branch may be optimized away. In that case, one side of the
// first branch will point directly to select.end, and the corresponding PHI
// predecessor block will be the start block.

// First, we split the block containing the select into 2 blocks.
BasicBlock *StartBlock = SI->getParent();
BasicBlock::iterator SplitPt = ++(BasicBlock::iterator(LastSI));
BasicBlock *EndBlock = StartBlock->splitBasicBlock(SplitPt, "select.end");

// Delete the unconditional branch that was just created by the split.
StartBlock->getTerminator()->eraseFromParent();

// These are the new basic blocks for the conditional branch.
// At least one will become an actual new basic block.
BasicBlock *TrueBlock = nullptr;
BasicBlock *FalseBlock = nullptr;
BranchInst *TrueBranch = nullptr;
BranchInst *FalseBranch = nullptr;

// Sink expensive instructions into the conditional blocks to avoid executing
// them speculatively.
for (SelectInst *SI : ASI) {
  if (sinkSelectOperand(TTI, SI->getTrueValue())) {
    if (TrueBlock == nullptr) {
      TrueBlock = BasicBlock::Create(SI->getContext(), "select.true.sink",
                                     EndBlock->getParent(), EndBlock);
      TrueBranch = BranchInst::Create(EndBlock, TrueBlock);
      TrueBranch->setDebugLoc(SI->getDebugLoc());
    }
    auto *TrueInst = cast<Instruction>(SI->getTrueValue());
    TrueInst->moveBefore(TrueBranch);
  }
  if (sinkSelectOperand(TTI, SI->getFalseValue())) {
    if (FalseBlock == nullptr) {
      FalseBlock = BasicBlock::Create(SI->getContext(), "select.false.sink",
                                      EndBlock->getParent(), EndBlock);
      FalseBranch = BranchInst::Create(EndBlock, FalseBlock);
      FalseBranch->setDebugLoc(SI->getDebugLoc());
    }
    auto *FalseInst = cast<Instruction>(SI->getFalseValue());
    FalseInst->moveBefore(FalseBranch);
  }
}

// If there was nothing to sink, then arbitrarily choose the 'false' side
// for a new input value to the PHI.
if (TrueBlock == FalseBlock) {
  assert(TrueBlock == nullptr &&((TrueBlock == nullptr && "Unexpected basic block transform while optimizing select"
) ? static_cast<void> (0) : __assert_fail ("TrueBlock == nullptr && \"Unexpected basic block transform while optimizing select\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6064, __PRETTY_FUNCTION__))
         "Unexpected basic block transform while optimizing select")((TrueBlock == nullptr && "Unexpected basic block transform while optimizing select"
) ? static_cast<void> (0) : __assert_fail ("TrueBlock == nullptr && \"Unexpected basic block transform while optimizing select\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6064, __PRETTY_FUNCTION__));

  FalseBlock = BasicBlock::Create(SI->getContext(), "select.false",
                                  EndBlock->getParent(), EndBlock);
  auto *FalseBranch = BranchInst::Create(EndBlock, FalseBlock);
  FalseBranch->setDebugLoc(SI->getDebugLoc());
}

// Insert the real conditional branch based on the original condition.
// If we did not create a new block for one of the 'true' or 'false' paths
// of the condition, it means that side of the branch goes to the end block
// directly and the path originates from the start block from the point of
// view of the new PHI.
BasicBlock *TT, *FT;
if (TrueBlock == nullptr) {
  TT = EndBlock;
  FT = FalseBlock;
  TrueBlock = StartBlock;
} else if (FalseBlock == nullptr) {
  TT = TrueBlock;
  FT = EndBlock;
  FalseBlock = StartBlock;
} else {
  TT = TrueBlock;
  FT = FalseBlock;
}
IRBuilder<>(SI).CreateCondBr(SI->getCondition(), TT, FT, SI);

SmallPtrSet<const Instruction *, 2> INS;
INS.insert(ASI.begin(), ASI.end());
// Use reverse iterator because later select may use the value of the
// earlier select, and we need to propagate value through earlier select
// to get the PHI operand.
for (auto It = ASI.rbegin(); It != ASI.rend(); ++It) {
  SelectInst *SI = *It;
  // The select itself is replaced with a PHI Node.
  PHINode *PN = PHINode::Create(SI->getType(), 2, "", &EndBlock->front());
  PN->takeName(SI);
  PN->addIncoming(getTrueOrFalseValue(SI, true, INS), TrueBlock);
  PN->addIncoming(getTrueOrFalseValue(SI, false, INS), FalseBlock);
  PN->setDebugLoc(SI->getDebugLoc());

  SI->replaceAllUsesWith(PN);
  SI->eraseFromParent();
  INS.erase(SI);
  ++NumSelectsExpanded;
}

// Instruct OptimizeBlock to skip to the next block.
CurInstIterator = StartBlock->end();
return true;
6115}

6117static bool isBroadcastShuffle(ShuffleVectorInst *SVI) {
SmallVector<int, 16> Mask(SVI->getShuffleMask());
int SplatElem = -1;
for (unsigned i = 0; i < Mask.size(); ++i) {
  if (SplatElem != -1 && Mask[i] != -1 && Mask[i] != SplatElem)
    return false;
  SplatElem = Mask[i];
}

return true;
6127}

6129/// Some targets have expensive vector shifts if the lanes aren't all the same
6130/// (e.g. x86 only introduced "vpsllvd" and friends with AVX2). In these cases
6131/// it's often worth sinking a shufflevector splat down to its use so that
6132/// codegen can spot all lanes are identical.
6133bool CodeGenPrepare::optimizeShuffleVectorInst(ShuffleVectorInst *SVI) {
BasicBlock *DefBB = SVI->getParent();

// Only do this xform if variable vector shifts are particularly expensive.
if (!TLI || !TLI->isVectorShiftByScalarCheap(SVI->getType()))
  return false;

// We only expect better codegen by sinking a shuffle if we can recognise a
// constant splat.
if (!isBroadcastShuffle(SVI))
  return false;

// InsertedShuffles - Only insert a shuffle in each block once.
DenseMap<BasicBlock*, Instruction*> InsertedShuffles;

bool MadeChange = false;
for (User *U : SVI->users()) {
  Instruction *UI = cast<Instruction>(U);

  // Figure out which BB this ext is used in.
  BasicBlock *UserBB = UI->getParent();
  if (UserBB == DefBB) continue;

  // For now only apply this when the splat is used by a shift instruction.
  if (!UI->isShift()) continue;

  // Everything checks out, sink the shuffle if the user's block doesn't
  // already have a copy.
  Instruction *&InsertedShuffle = InsertedShuffles[UserBB];

  if (!InsertedShuffle) {
    BasicBlock::iterator InsertPt = UserBB->getFirstInsertionPt();
    assert(InsertPt != UserBB->end())((InsertPt != UserBB->end()) ? static_cast<void> (0)
 : __assert_fail ("InsertPt != UserBB->end()", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6165, __PRETTY_FUNCTION__));
    InsertedShuffle =
        new ShuffleVectorInst(SVI->getOperand(0), SVI->getOperand(1),
                              SVI->getOperand(2), "", &*InsertPt);
    InsertedShuffle->setDebugLoc(SVI->getDebugLoc());
  }

  UI->replaceUsesOfWith(SVI, InsertedShuffle);
  MadeChange = true;
}

// If we removed all uses, nuke the shuffle.
if (SVI->use_empty()) {
  SVI->eraseFromParent();
  MadeChange = true;
}

return MadeChange;
6183}

6185bool CodeGenPrepare::tryToSinkFreeOperands(Instruction *I) {
// If the operands of I can be folded into a target instruction together with
// I, duplicate and sink them.
SmallVector<Use *, 4> OpsToSink;
if (!TLI || !TLI->shouldSinkOperands(I, OpsToSink))
  return false;

// OpsToSink can contain multiple uses in a use chain (e.g.
// (%u1 with %u1 = shufflevector), (%u2 with %u2 = zext %u1)). The dominating
// uses must come first, so we process the ops in reverse order so as to not
// create invalid IR.
BasicBlock *TargetBB = I->getParent();
bool Changed = false;
SmallVector<Use *, 4> ToReplace;
for (Use *U : reverse(OpsToSink)) {
  auto *UI = cast<Instruction>(U->get());
  if (UI->getParent() == TargetBB || isa<PHINode>(UI))
    continue;
  ToReplace.push_back(U);
}

SetVector<Instruction *> MaybeDead;
DenseMap<Instruction *, Instruction *> NewInstructions;
Instruction *InsertPoint = I;
for (Use *U : ToReplace) {
  auto *UI = cast<Instruction>(U->get());
  Instruction *NI = UI->clone();
  NewInstructions[UI] = NI;
  MaybeDead.insert(UI);
  LLVM_DEBUG(dbgs() << "Sinking " << *UI << " to user " << *I << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Sinking " << *UI
 << " to user " << *I << "\n"; } } while (false
);
  NI->insertBefore(InsertPoint);
  InsertPoint = NI;
  InsertedInsts.insert(NI);

  // Update the use for the new instruction, making sure that we update the
  // sunk instruction uses, if it is part of a chain that has already been
  // sunk.
  Instruction *OldI = cast<Instruction>(U->getUser());
  if (NewInstructions.count(OldI))
    NewInstructions[OldI]->setOperand(U->getOperandNo(), NI);
  else
    U->set(NI);
  Changed = true;
}

// Remove instructions that are dead after sinking.
for (auto *I : MaybeDead) {
  if (!I->hasNUsesOrMore(1)) {
    LLVM_DEBUG(dbgs() << "Removing dead instruction: " << *I << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Removing dead instruction: "
 << *I << "\n"; } } while (false);
    I->eraseFromParent();
  }
}

return Changed;
6239}

6241bool CodeGenPrepare::optimizeSwitchInst(SwitchInst *SI) {
if (!TLI || !DL)
  return false;

Value *Cond = SI->getCondition();
Type *OldType = Cond->getType();
LLVMContext &Context = Cond->getContext();
MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType));
unsigned RegWidth = RegType.getSizeInBits();

if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth())
  return false;

// If the register width is greater than the type width, expand the condition
// of the switch instruction and each case constant to the width of the
// register. By widening the type of the switch condition, subsequent
// comparisons (for case comparisons) will not need to be extended to the
// preferred register width, so we will potentially eliminate N-1 extends,
// where N is the number of cases in the switch.
auto *NewType = Type::getIntNTy(Context, RegWidth);

// Zero-extend the switch condition and case constants unless the switch
// condition is a function argument that is already being sign-extended.
// In that case, we can avoid an unnecessary mask/extension by sign-extending
// everything instead.
Instruction::CastOps ExtType = Instruction::ZExt;
if (auto *Arg = dyn_cast<Argument>(Cond))
  if (Arg->hasSExtAttr())
    ExtType = Instruction::SExt;

auto *ExtInst = CastInst::Create(ExtType, Cond, NewType);
ExtInst->insertBefore(SI);
ExtInst->setDebugLoc(SI->getDebugLoc());
SI->setCondition(ExtInst);
for (auto Case : SI->cases()) {
  APInt NarrowConst = Case.getCaseValue()->getValue();
  APInt WideConst = (ExtType == Instruction::ZExt) ?
                    NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth);
  Case.setValue(ConstantInt::get(Context, WideConst));
}

return true;
6283}


6286namespace {

6288/// Helper class to promote a scalar operation to a vector one.
6289/// This class is used to move downward extractelement transition.
6290/// E.g.,
6291/// a = vector_op <2 x i32>
6292/// b = extractelement <2 x i32> a, i32 0
6293/// c = scalar_op b
6294/// store c
6295///
6296/// =>
6297/// a = vector_op <2 x i32>
6298/// c = vector_op a (equivalent to scalar_op on the related lane)
6299/// * d = extractelement <2 x i32> c, i32 0
6300/// * store d
6301/// Assuming both extractelement and store can be combine, we get rid of the
6302/// transition.
6303class VectorPromoteHelper {
/// DataLayout associated with the current module.
const DataLayout &DL;

/// Used to perform some checks on the legality of vector operations.
const TargetLowering &TLI;

/// Used to estimated the cost of the promoted chain.
const TargetTransformInfo &TTI;

/// The transition being moved downwards.
Instruction *Transition;

/// The sequence of instructions to be promoted.
SmallVector<Instruction *, 4> InstsToBePromoted;

/// Cost of combining a store and an extract.
unsigned StoreExtractCombineCost;

/// Instruction that will be combined with the transition.
Instruction *CombineInst = nullptr;

/// The instruction that represents the current end of the transition.
/// Since we are faking the promotion until we reach the end of the chain
/// of computation, we need a way to get the current end of the transition.
Instruction *getEndOfTransition() const {
  if (InstsToBePromoted.empty())
    return Transition;
  return InstsToBePromoted.back();
}

/// Return the index of the original value in the transition.
/// E.g., for "extractelement <2 x i32> c, i32 1" the original value,
/// c, is at index 0.
unsigned getTransitionOriginalValueIdx() const {
  assert(isa<ExtractElementInst>(Transition) &&((isa<ExtractElementInst>(Transition) && "Other kind of transitions are not supported yet"
) ? static_cast<void> (0) : __assert_fail ("isa<ExtractElementInst>(Transition) && \"Other kind of transitions are not supported yet\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6339, __PRETTY_FUNCTION__))
         "Other kind of transitions are not supported yet")((isa<ExtractElementInst>(Transition) && "Other kind of transitions are not supported yet"
) ? static_cast<void> (0) : __assert_fail ("isa<ExtractElementInst>(Transition) && \"Other kind of transitions are not supported yet\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6339, __PRETTY_FUNCTION__));
  return 0;
}

/// Return the index of the index in the transition.
/// E.g., for "extractelement <2 x i32> c, i32 0" the index
/// is at index 1.
unsigned getTransitionIdx() const {
  assert(isa<ExtractElementInst>(Transition) &&((isa<ExtractElementInst>(Transition) && "Other kind of transitions are not supported yet"
) ? static_cast<void> (0) : __assert_fail ("isa<ExtractElementInst>(Transition) && \"Other kind of transitions are not supported yet\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6348, __PRETTY_FUNCTION__))
         "Other kind of transitions are not supported yet")((isa<ExtractElementInst>(Transition) && "Other kind of transitions are not supported yet"
) ? static_cast<void> (0) : __assert_fail ("isa<ExtractElementInst>(Transition) && \"Other kind of transitions are not supported yet\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6348, __PRETTY_FUNCTION__));
  return 1;
}

/// Get the type of the transition.
/// This is the type of the original value.
/// E.g., for "extractelement <2 x i32> c, i32 1" the type of the
/// transition is <2 x i32>.
Type *getTransitionType() const {
  return Transition->getOperand(getTransitionOriginalValueIdx())->getType();
}

/// Promote \p ToBePromoted by moving \p Def downward through.
/// I.e., we have the following sequence:
/// Def = Transition <ty1> a to <ty2>
/// b = ToBePromoted <ty2> Def, ...
/// =>
/// b = ToBePromoted <ty1> a, ...
/// Def = Transition <ty1> ToBePromoted to <ty2>
void promoteImpl(Instruction *ToBePromoted);

/// Check whether or not it is profitable to promote all the
/// instructions enqueued to be promoted.
bool isProfitableToPromote() {
  Value *ValIdx = Transition->getOperand(getTransitionOriginalValueIdx());
  unsigned Index = isa<ConstantInt>(ValIdx)
                       ? cast<ConstantInt>(ValIdx)->getZExtValue()
                       : -1;
  Type *PromotedType = getTransitionType();

  StoreInst *ST = cast<StoreInst>(CombineInst);
  unsigned AS = ST->getPointerAddressSpace();
  unsigned Align = ST->getAlignment();
  // Check if this store is supported.
  if (!TLI.allowsMisalignedMemoryAccesses(
          TLI.getValueType(DL, ST->getValueOperand()->getType()), AS,
          Align)) {
    // If this is not supported, there is no way we can combine
    // the extract with the store.
    return false;
  }

  // The scalar chain of computation has to pay for the transition
  // scalar to vector.
  // The vector chain has to account for the combining cost.
  uint64_t ScalarCost =
      TTI.getVectorInstrCost(Transition->getOpcode(), PromotedType, Index);
  uint64_t VectorCost = StoreExtractCombineCost;
  for (const auto &Inst : InstsToBePromoted) {
    // Compute the cost.
    // By construction, all instructions being promoted are arithmetic ones.
    // Moreover, one argument is a constant that can be viewed as a splat
    // constant.
    Value *Arg0 = Inst->getOperand(0);
    bool IsArg0Constant = isa<UndefValue>(Arg0) || isa<ConstantInt>(Arg0) ||
                          isa<ConstantFP>(Arg0);
    TargetTransformInfo::OperandValueKind Arg0OVK =
        IsArg0Constant ? TargetTransformInfo::OK_UniformConstantValue
                       : TargetTransformInfo::OK_AnyValue;
    TargetTransformInfo::OperandValueKind Arg1OVK =
        !IsArg0Constant ? TargetTransformInfo::OK_UniformConstantValue
                        : TargetTransformInfo::OK_AnyValue;
    ScalarCost += TTI.getArithmeticInstrCost(
        Inst->getOpcode(), Inst->getType(), Arg0OVK, Arg1OVK);
    VectorCost += TTI.getArithmeticInstrCost(Inst->getOpcode(), PromotedType,
                                             Arg0OVK, Arg1OVK);
  }
  LLVM_DEBUG(do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Estimated cost of computation to be promoted:\nScalar: "
 << ScalarCost << "\nVector: " << VectorCost
 << '\n'; } } while (false)
      dbgs() << "Estimated cost of computation to be promoted:\nScalar: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Estimated cost of computation to be promoted:\nScalar: "
 << ScalarCost << "\nVector: " << VectorCost
 << '\n'; } } while (false)
             << ScalarCost << "\nVector: " << VectorCost << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Estimated cost of computation to be promoted:\nScalar: "
 << ScalarCost << "\nVector: " << VectorCost
 << '\n'; } } while (false);
  return ScalarCost > VectorCost;
}

/// Generate a constant vector with \p Val with the same
/// number of elements as the transition.
/// \p UseSplat defines whether or not \p Val should be replicated
/// across the whole vector.
/// In other words, if UseSplat == true, we generate <Val, Val, ..., Val>,
/// otherwise we generate a vector with as many undef as possible:
/// <undef, ..., undef, Val, undef, ..., undef> where \p Val is only
/// used at the index of the extract.
Value *getConstantVector(Constant *Val, bool UseSplat) const {
  unsigned ExtractIdx = std::numeric_limits<unsigned>::max();
  if (!UseSplat) {
    // If we cannot determine where the constant must be, we have to
    // use a splat constant.
    Value *ValExtractIdx = Transition->getOperand(getTransitionIdx());
    if (ConstantInt *CstVal = dyn_cast<ConstantInt>(ValExtractIdx))
      ExtractIdx = CstVal->getSExtValue();
    else
      UseSplat = true;
  }

  unsigned End = getTransitionType()->getVectorNumElements();
  if (UseSplat)
    return ConstantVector::getSplat(End, Val);

  SmallVector<Constant *, 4> ConstVec;
  UndefValue *UndefVal = UndefValue::get(Val->getType());
  for (unsigned Idx = 0; Idx != End; ++Idx) {
    if (Idx == ExtractIdx)
      ConstVec.push_back(Val);
    else
      ConstVec.push_back(UndefVal);
  }
  return ConstantVector::get(ConstVec);
}

/// Check if promoting to a vector type an operand at \p OperandIdx
/// in \p Use can trigger undefined behavior.
static bool canCauseUndefinedBehavior(const Instruction *Use,
                                      unsigned OperandIdx) {
  // This is not safe to introduce undef when the operand is on
  // the right hand side of a division-like instruction.
  if (OperandIdx != 1)
    return false;
  switch (Use->getOpcode()) {
  default:
    return false;
  case Instruction::SDiv:
  case Instruction::UDiv:
  case Instruction::SRem:
  case Instruction::URem:
    return true;
  case Instruction::FDiv:
  case Instruction::FRem:
    return !Use->hasNoNaNs();
  }
  llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6476);
}

6479public:
VectorPromoteHelper(const DataLayout &DL, const TargetLowering &TLI,
                    const TargetTransformInfo &TTI, Instruction *Transition,
                    unsigned CombineCost)
    : DL(DL), TLI(TLI), TTI(TTI), Transition(Transition),
      StoreExtractCombineCost(CombineCost) {
  assert(Transition && "Do not know how to promote null")((Transition && "Do not know how to promote null") ? static_cast
<void> (0) : __assert_fail ("Transition && \"Do not know how to promote null\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6485, __PRETTY_FUNCTION__));
}

/// Check if we can promote \p ToBePromoted to \p Type.
bool canPromote(const Instruction *ToBePromoted) const {
  // We could support CastInst too.
  return isa<BinaryOperator>(ToBePromoted);
}

/// Check if it is profitable to promote \p ToBePromoted
/// by moving downward the transition through.
bool shouldPromote(const Instruction *ToBePromoted) const {
  // Promote only if all the operands can be statically expanded.
  // Indeed, we do not want to introduce any new kind of transitions.
  for (const Use &U : ToBePromoted->operands()) {
    const Value *Val = U.get();
    if (Val == getEndOfTransition()) {
      // If the use is a division and the transition is on the rhs,
      // we cannot promote the operation, otherwise we may create a
      // division by zero.
      if (canCauseUndefinedBehavior(ToBePromoted, U.getOperandNo()))
        return false;
      continue;
    }
    if (!isa<ConstantInt>(Val) && !isa<UndefValue>(Val) &&
        !isa<ConstantFP>(Val))
      return false;
  }
  // Check that the resulting operation is legal.
  int ISDOpcode = TLI.InstructionOpcodeToISD(ToBePromoted->getOpcode());
  if (!ISDOpcode)
    return false;
  return StressStoreExtract ||
         TLI.isOperationLegalOrCustom(
             ISDOpcode, TLI.getValueType(DL, getTransitionType(), true));
}

/// Check whether or not \p Use can be combined
/// with the transition.
/// I.e., is it possible to do Use(Transition) => AnotherUse?
bool canCombine(const Instruction *Use) { return isa<StoreInst>(Use); }

/// Record \p ToBePromoted as part of the chain to be promoted.
void enqueueForPromotion(Instruction *ToBePromoted) {
  InstsToBePromoted.push_back(ToBePromoted);
}

/// Set the instruction that will be combined with the transition.
void recordCombineInstruction(Instruction *ToBeCombined) {
  assert(canCombine(ToBeCombined) && "Unsupported instruction to combine")((canCombine(ToBeCombined) && "Unsupported instruction to combine"
) ? static_cast<void> (0) : __assert_fail ("canCombine(ToBeCombined) && \"Unsupported instruction to combine\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6534, __PRETTY_FUNCTION__));
  CombineInst = ToBeCombined;
}

/// Promote all the instructions enqueued for promotion if it is
/// is profitable.
/// \return True if the promotion happened, false otherwise.
bool promote() {
  // Check if there is something to promote.
  // Right now, if we do not have anything to combine with,
  // we assume the promotion is not profitable.
  if (InstsToBePromoted.empty() || !CombineInst)
    return false;

  // Check cost.
  if (!StressStoreExtract && !isProfitableToPromote())
    return false;

  // Promote.
  for (auto &ToBePromoted : InstsToBePromoted)
    promoteImpl(ToBePromoted);
  InstsToBePromoted.clear();
  return true;
}
6558};

6560} // end anonymous namespace

6562void VectorPromoteHelper::promoteImpl(Instruction *ToBePromoted) {
// At this point, we know that all the operands of ToBePromoted but Def
// can be statically promoted.
// For Def, we need to use its parameter in ToBePromoted:
// b = ToBePromoted ty1 a
// Def = Transition ty1 b to ty2
// Move the transition down.
// 1. Replace all uses of the promoted operation by the transition.
// = ... b => = ... Def.
assert(ToBePromoted->getType() == Transition->getType() &&((ToBePromoted->getType() == Transition->getType() &&
 "The type of the result of the transition does not match " "the final type"
) ? static_cast<void> (0) : __assert_fail ("ToBePromoted->getType() == Transition->getType() && \"The type of the result of the transition does not match \" \"the final type\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6573, __PRETTY_FUNCTION__))
       "The type of the result of the transition does not match "((ToBePromoted->getType() == Transition->getType() &&
 "The type of the result of the transition does not match " "the final type"
) ? static_cast<void> (0) : __assert_fail ("ToBePromoted->getType() == Transition->getType() && \"The type of the result of the transition does not match \" \"the final type\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6573, __PRETTY_FUNCTION__))
       "the final type")((ToBePromoted->getType() == Transition->getType() &&
 "The type of the result of the transition does not match " "the final type"
) ? static_cast<void> (0) : __assert_fail ("ToBePromoted->getType() == Transition->getType() && \"The type of the result of the transition does not match \" \"the final type\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6573, __PRETTY_FUNCTION__));
ToBePromoted->replaceAllUsesWith(Transition);
// 2. Update the type of the uses.
// b = ToBePromoted ty2 Def => b = ToBePromoted ty1 Def.
Type *TransitionTy = getTransitionType();
ToBePromoted->mutateType(TransitionTy);
// 3. Update all the operands of the promoted operation with promoted
// operands.
// b = ToBePromoted ty1 Def => b = ToBePromoted ty1 a.
for (Use &U : ToBePromoted->operands()) {
  Value *Val = U.get();
  Value *NewVal = nullptr;
  if (Val == Transition)
    NewVal = Transition->getOperand(getTransitionOriginalValueIdx());
  else if (isa<UndefValue>(Val) || isa<ConstantInt>(Val) ||
           isa<ConstantFP>(Val)) {
    // Use a splat constant if it is not safe to use undef.
    NewVal = getConstantVector(
        cast<Constant>(Val),
        isa<UndefValue>(Val) ||
            canCauseUndefinedBehavior(ToBePromoted, U.getOperandNo()));
  } else
    llvm_unreachable("Did you modified shouldPromote and forgot to update "::llvm::llvm_unreachable_internal("Did you modified shouldPromote and forgot to update "
 "this?", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6596)
                     "this?")::llvm::llvm_unreachable_internal("Did you modified shouldPromote and forgot to update "
 "this?", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6596);
  ToBePromoted->setOperand(U.getOperandNo(), NewVal);
}
Transition->moveAfter(ToBePromoted);
Transition->setOperand(getTransitionOriginalValueIdx(), ToBePromoted);
6601}

6603/// Some targets can do store(extractelement) with one instruction.
6604/// Try to push the extractelement towards the stores when the target
6605/// has this feature and this is profitable.
6606bool CodeGenPrepare::optimizeExtractElementInst(Instruction *Inst) {
unsigned CombineCost = std::numeric_limits<unsigned>::max();
if (DisableStoreExtract || !TLI ||
    (!StressStoreExtract &&
     !TLI->canCombineStoreAndExtract(Inst->getOperand(0)->getType(),
                                     Inst->getOperand(1), CombineCost)))
  return false;

// At this point we know that Inst is a vector to scalar transition.
// Try to move it down the def-use chain, until:
// - We can combine the transition with its single use
//   => we got rid of the transition.
// - We escape the current basic block
//   => we would need to check that we are moving it at a cheaper place and
//      we do not do that for now.
BasicBlock *Parent = Inst->getParent();
LLVM_DEBUG(dbgs() << "Found an interesting transition: " << *Inst << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Found an interesting transition: "
 << *Inst << '\n'; } } while (false);
VectorPromoteHelper VPH(*DL, *TLI, *TTI, Inst, CombineCost);
// If the transition has more than one use, assume this is not going to be
// beneficial.
while (Inst->hasOneUse()) {
  Instruction *ToBePromoted = cast<Instruction>(*Inst->user_begin());
  LLVM_DEBUG(dbgs() << "Use: " << *ToBePromoted << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Use: " << *ToBePromoted
 << '\n'; } } while (false);

  if (ToBePromoted->getParent() != Parent) {
    LLVM_DEBUG(dbgs() << "Instruction to promote is in a different block ("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Instruction to promote is in a different block ("
 << ToBePromoted->getParent()->getName() <<
 ") than the transition (" << Parent->getName() <<
 ").\n"; } } while (false)
                      << ToBePromoted->getParent()->getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Instruction to promote is in a different block ("
 << ToBePromoted->getParent()->getName() <<
 ") than the transition (" << Parent->getName() <<
 ").\n"; } } while (false)
                      << ") than the transition (" << Parent->getName()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Instruction to promote is in a different block ("
 << ToBePromoted->getParent()->getName() <<
 ") than the transition (" << Parent->getName() <<
 ").\n"; } } while (false)
                      << ").\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Instruction to promote is in a different block ("
 << ToBePromoted->getParent()->getName() <<
 ") than the transition (" << Parent->getName() <<
 ").\n"; } } while (false);
    return false;
  }

  if (VPH.canCombine(ToBePromoted)) {
    LLVM_DEBUG(dbgs() << "Assume " << *Inst << '\n'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Assume " << *Inst
 << '\n' << "will be combined with: " << *ToBePromoted
 << '\n'; } } while (false)
                      << "will be combined with: " << *ToBePromoted << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Assume " << *Inst
 << '\n' << "will be combined with: " << *ToBePromoted
 << '\n'; } } while (false);
    VPH.recordCombineInstruction(ToBePromoted);
    bool Changed = VPH.promote();
    NumStoreExtractExposed += Changed;
    return Changed;
  }

  LLVM_DEBUG(dbgs() << "Try promoting.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Try promoting.\n"; } }
 while (false);
  if (!VPH.canPromote(ToBePromoted) || !VPH.shouldPromote(ToBePromoted))
    return false;

  LLVM_DEBUG(dbgs() << "Promoting is possible... Enqueue for promotion!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Promoting is possible... Enqueue for promotion!\n"
; } } while (false);

  VPH.enqueueForPromotion(ToBePromoted);
  Inst = ToBePromoted;
}
return false;
6657}

6659/// For the instruction sequence of store below, F and I values
6660/// are bundled together as an i64 value before being stored into memory.
6661/// Sometimes it is more efficient to generate separate stores for F and I,
6662/// which can remove the bitwise instructions or sink them to colder places.
6663///
6664///   (store (or (zext (bitcast F to i32) to i64),
6665///              (shl (zext I to i64), 32)), addr)  -->
6666///   (store F, addr) and (store I, addr+4)
6667///
6668/// Similarly, splitting for other merged store can also be beneficial, like:
6669/// For pair of {i32, i32}, i64 store --> two i32 stores.
6670/// For pair of {i32, i16}, i64 store --> two i32 stores.
6671/// For pair of {i16, i16}, i32 store --> two i16 stores.
6672/// For pair of {i16, i8},  i32 store --> two i16 stores.
6673/// For pair of {i8, i8},   i16 store --> two i8 stores.
6674///
6675/// We allow each target to determine specifically which kind of splitting is
6676/// supported.
6677///
6678/// The store patterns are commonly seen from the simple code snippet below
6679/// if only std::make_pair(...) is sroa transformed before inlined into hoo.
6680///   void goo(const std::pair<int, float> &);
6681///   hoo() {
6682///     ...
6683///     goo(std::make_pair(tmp, ftmp));
6684///     ...
6685///   }
6686///
6687/// Although we already have similar splitting in DAG Combine, we duplicate
6688/// it in CodeGenPrepare to catch the case in which pattern is across
6689/// multiple BBs. The logic in DAG Combine is kept to catch case generated
6690/// during code expansion.
6691static bool splitMergedValStore(StoreInst &SI, const DataLayout &DL,
                              const TargetLowering &TLI) {
// Handle simple but common cases only.
Type *StoreType = SI.getValueOperand()->getType();
if (!DL.typeSizeEqualsStoreSize(StoreType) ||
    DL.getTypeSizeInBits(StoreType) == 0)
  return false;

unsigned HalfValBitSize = DL.getTypeSizeInBits(StoreType) / 2;
Type *SplitStoreType = Type::getIntNTy(SI.getContext(), HalfValBitSize);
if (!DL.typeSizeEqualsStoreSize(SplitStoreType))
  return false;

// Don't split the store if it is volatile.
if (SI.isVolatile())
  return false;

// Match the following patterns:
// (store (or (zext LValue to i64),
//            (shl (zext HValue to i64), 32)), HalfValBitSize)
//  or
// (store (or (shl (zext HValue to i64), 32)), HalfValBitSize)
//            (zext LValue to i64),
// Expect both operands of OR and the first operand of SHL have only
// one use.
Value *LValue, *HValue;
if (!match(SI.getValueOperand(),
           m_c_Or(m_OneUse(m_ZExt(m_Value(LValue))),
                  m_OneUse(m_Shl(m_OneUse(m_ZExt(m_Value(HValue))),
                                 m_SpecificInt(HalfValBitSize))))))
  return false;

// Check LValue and HValue are int with size less or equal than 32.
if (!LValue->getType()->isIntegerTy() ||
    DL.getTypeSizeInBits(LValue->getType()) > HalfValBitSize ||
    !HValue->getType()->isIntegerTy() ||
    DL.getTypeSizeInBits(HValue->getType()) > HalfValBitSize)
  return false;

// If LValue/HValue is a bitcast instruction, use the EVT before bitcast
// as the input of target query.
auto *LBC = dyn_cast<BitCastInst>(LValue);
auto *HBC = dyn_cast<BitCastInst>(HValue);
EVT LowTy = LBC ? EVT::getEVT(LBC->getOperand(0)->getType())
                : EVT::getEVT(LValue->getType());
EVT HighTy = HBC ? EVT::getEVT(HBC->getOperand(0)->getType())
                 : EVT::getEVT(HValue->getType());
if (!ForceSplitStore && !TLI.isMultiStoresCheaperThanBitsMerge(LowTy, HighTy))
  return false;

// Start to split store.
IRBuilder<> Builder(SI.getContext());
Builder.SetInsertPoint(&SI);

// If LValue/HValue is a bitcast in another BB, create a new one in current
// BB so it may be merged with the splitted stores by dag combiner.
if (LBC && LBC->getParent() != SI.getParent())
  LValue = Builder.CreateBitCast(LBC->getOperand(0), LBC->getType());
if (HBC && HBC->getParent() != SI.getParent())
  HValue = Builder.CreateBitCast(HBC->getOperand(0), HBC->getType());

bool IsLE = SI.getModule()->getDataLayout().isLittleEndian();
auto CreateSplitStore = [&](Value *V, bool Upper) {
  V = Builder.CreateZExtOrBitCast(V, SplitStoreType);
  Value *Addr = Builder.CreateBitCast(
      SI.getOperand(1),
      SplitStoreType->getPointerTo(SI.getPointerAddressSpace()));
  if ((IsLE && Upper) || (!IsLE && !Upper))
    Addr = Builder.CreateGEP(
        SplitStoreType, Addr,
        ConstantInt::get(Type::getInt32Ty(SI.getContext()), 1));
  Builder.CreateAlignedStore(
      V, Addr, Upper ? SI.getAlignment() / 2 : SI.getAlignment());
};

CreateSplitStore(LValue, false);
CreateSplitStore(HValue, true);

// Delete the old store.
SI.eraseFromParent();
return true;
6772}

6774// Return true if the GEP has two operands, the first operand is of a sequential
6775// type, and the second operand is a constant.
6776static bool GEPSequentialConstIndexed(GetElementPtrInst *GEP) {
gep_type_iterator I = gep_type_begin(*GEP);
return GEP->getNumOperands() == 2 &&
    I.isSequential() &&
    isa<ConstantInt>(GEP->getOperand(1));
6781}

6783// Try unmerging GEPs to reduce liveness interference (register pressure) across
6784// IndirectBr edges. Since IndirectBr edges tend to touch on many blocks,
6785// reducing liveness interference across those edges benefits global register
6786// allocation. Currently handles only certain cases.
6787//
6788// For example, unmerge %GEPI and %UGEPI as below.
6789//
6790// ---------- BEFORE ----------
6791// SrcBlock:
6792//   ...
6793//   %GEPIOp = ...
6794//   ...
6795//   %GEPI = gep %GEPIOp, Idx
6796//   ...
6797//   indirectbr ... [ label %DstB0, label %DstB1, ... label %DstBi ... ]
6798//   (* %GEPI is alive on the indirectbr edges due to other uses ahead)
6799//   (* %GEPIOp is alive on the indirectbr edges only because of it's used by
6800//   %UGEPI)
6801//
6802// DstB0: ... (there may be a gep similar to %UGEPI to be unmerged)
6803// DstB1: ... (there may be a gep similar to %UGEPI to be unmerged)
6804// ...
6805//
6806// DstBi:
6807//   ...
6808//   %UGEPI = gep %GEPIOp, UIdx
6809// ...
6810// ---------------------------
6811//
6812// ---------- AFTER ----------
6813// SrcBlock:
6814//   ... (same as above)
6815//    (* %GEPI is still alive on the indirectbr edges)
6816//    (* %GEPIOp is no longer alive on the indirectbr edges as a result of the
6817//    unmerging)
6818// ...
6819//
6820// DstBi:
6821//   ...
6822//   %UGEPI = gep %GEPI, (UIdx-Idx)
6823//   ...
6824// ---------------------------
6825//
6826// The register pressure on the IndirectBr edges is reduced because %GEPIOp is
6827// no longer alive on them.
6828//
6829// We try to unmerge GEPs here in CodGenPrepare, as opposed to limiting merging
6830// of GEPs in the first place in InstCombiner::visitGetElementPtrInst() so as
6831// not to disable further simplications and optimizations as a result of GEP
6832// merging.
6833//
6834// Note this unmerging may increase the length of the data flow critical path
6835// (the path from %GEPIOp to %UGEPI would go through %GEPI), which is a tradeoff
6836// between the register pressure and the length of data-flow critical
6837// path. Restricting this to the uncommon IndirectBr case would minimize the
6838// impact of potentially longer critical path, if any, and the impact on compile
6839// time.
6840static bool tryUnmergingGEPsAcrossIndirectBr(GetElementPtrInst *GEPI,
                                           const TargetTransformInfo *TTI) {
BasicBlock *SrcBlock = GEPI->getParent();
// Check that SrcBlock ends with an IndirectBr. If not, give up. The common
// (non-IndirectBr) cases exit early here.
if (!isa<IndirectBrInst>(SrcBlock->getTerminator()))
  return false;
// Check that GEPI is a simple gep with a single constant index.
if (!GEPSequentialConstIndexed(GEPI))
  return false;
ConstantInt *GEPIIdx = cast<ConstantInt>(GEPI->getOperand(1));
// Check that GEPI is a cheap one.
if (TTI->getIntImmCost(GEPIIdx->getValue(), GEPIIdx->getType())
    > TargetTransformInfo::TCC_Basic)
  return false;
Value *GEPIOp = GEPI->getOperand(0);
// Check that GEPIOp is an instruction that's also defined in SrcBlock.
if (!isa<Instruction>(GEPIOp))
  return false;
auto *GEPIOpI = cast<Instruction>(GEPIOp);
if (GEPIOpI->getParent() != SrcBlock)
  return false;
// Check that GEP is used outside the block, meaning it's alive on the
// IndirectBr edge(s).
if (find_if(GEPI->users(), [&](User *Usr) {
      if (auto *I = dyn_cast<Instruction>(Usr)) {
        if (I->getParent() != SrcBlock) {
          return true;
        }
      }
      return false;
    }) == GEPI->users().end())
  return false;
// The second elements of the GEP chains to be unmerged.
std::vector<GetElementPtrInst *> UGEPIs;
// Check each user of GEPIOp to check if unmerging would make GEPIOp not alive
// on IndirectBr edges.
for (User *Usr : GEPIOp->users()) {
  if (Usr == GEPI) continue;
  // Check if Usr is an Instruction. If not, give up.
  if (!isa<Instruction>(Usr))
    return false;
  auto *UI = cast<Instruction>(Usr);
  // Check if Usr in the same block as GEPIOp, which is fine, skip.
  if (UI->getParent() == SrcBlock)
    continue;
  // Check if Usr is a GEP. If not, give up.
  if (!isa<GetElementPtrInst>(Usr))
    return false;
  auto *UGEPI = cast<GetElementPtrInst>(Usr);
  // Check if UGEPI is a simple gep with a single constant index and GEPIOp is
  // the pointer operand to it. If so, record it in the vector. If not, give
  // up.
  if (!GEPSequentialConstIndexed(UGEPI))
    return false;
  if (UGEPI->getOperand(0) != GEPIOp)
    return false;
  if (GEPIIdx->getType() !=
      cast<ConstantInt>(UGEPI->getOperand(1))->getType())
    return false;
  ConstantInt *UGEPIIdx = cast<ConstantInt>(UGEPI->getOperand(1));
  if (TTI->getIntImmCost(UGEPIIdx->getValue(), UGEPIIdx->getType())
      > TargetTransformInfo::TCC_Basic)
    return false;
  UGEPIs.push_back(UGEPI);
}
if (UGEPIs.size() == 0)
  return false;
// Check the materializing cost of (Uidx-Idx).
for (GetElementPtrInst *UGEPI : UGEPIs) {
  ConstantInt *UGEPIIdx = cast<ConstantInt>(UGEPI->getOperand(1));
  APInt NewIdx = UGEPIIdx->getValue() - GEPIIdx->getValue();
  unsigned ImmCost = TTI->getIntImmCost(NewIdx, GEPIIdx->getType());
  if (ImmCost > TargetTransformInfo::TCC_Basic)
    return false;
}
// Now unmerge between GEPI and UGEPIs.
for (GetElementPtrInst *UGEPI : UGEPIs) {
  UGEPI->setOperand(0, GEPI);
  ConstantInt *UGEPIIdx = cast<ConstantInt>(UGEPI->getOperand(1));
  Constant *NewUGEPIIdx =
      ConstantInt::get(GEPIIdx->getType(),
                       UGEPIIdx->getValue() - GEPIIdx->getValue());
  UGEPI->setOperand(1, NewUGEPIIdx);
  // If GEPI is not inbounds but UGEPI is inbounds, change UGEPI to not
  // inbounds to avoid UB.
  if (!GEPI->isInBounds()) {
    UGEPI->setIsInBounds(false);
  }
}
// After unmerging, verify that GEPIOp is actually only used in SrcBlock (not
// alive on IndirectBr edges).
assert(find_if(GEPIOp->users(), [&](User *Usr) {((find_if(GEPIOp->users(), [&](User *Usr) { return cast
<Instruction>(Usr)->getParent() != SrcBlock; }) == GEPIOp
->users().end() && "GEPIOp is used outside SrcBlock"
) ? static_cast<void> (0) : __assert_fail ("find_if(GEPIOp->users(), [&](User *Usr) { return cast<Instruction>(Usr)->getParent() != SrcBlock; }) == GEPIOp->users().end() && \"GEPIOp is used outside SrcBlock\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6934, __PRETTY_FUNCTION__))
      return cast<Instruction>(Usr)->getParent() != SrcBlock;((find_if(GEPIOp->users(), [&](User *Usr) { return cast
<Instruction>(Usr)->getParent() != SrcBlock; }) == GEPIOp
->users().end() && "GEPIOp is used outside SrcBlock"
) ? static_cast<void> (0) : __assert_fail ("find_if(GEPIOp->users(), [&](User *Usr) { return cast<Instruction>(Usr)->getParent() != SrcBlock; }) == GEPIOp->users().end() && \"GEPIOp is used outside SrcBlock\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6934, __PRETTY_FUNCTION__))
    }) == GEPIOp->users().end() && "GEPIOp is used outside SrcBlock")((find_if(GEPIOp->users(), [&](User *Usr) { return cast
<Instruction>(Usr)->getParent() != SrcBlock; }) == GEPIOp
->users().end() && "GEPIOp is used outside SrcBlock"
) ? static_cast<void> (0) : __assert_fail ("find_if(GEPIOp->users(), [&](User *Usr) { return cast<Instruction>(Usr)->getParent() != SrcBlock; }) == GEPIOp->users().end() && \"GEPIOp is used outside SrcBlock\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/CodeGenPrepare.cpp"
, 6934, __PRETTY_FUNCTION__));
return true;
6936}

6938bool CodeGenPrepare::optimizeInst(Instruction *I, bool &ModifiedDT) {
// Bail out if we inserted the instruction to prevent optimizations from
// stepping on each other's toes.
if (InsertedInsts.count(I))
15
←
Assuming the condition is false→
16
←
Taking false branch→
37
←
Assuming the condition is false→
38
←
Taking false branch→
  return false;

// TODO: Move into the switch on opcode below here.
if (PHINode *P17.1
'P' is null
1
'P' is null
1
'P' is null
1
'P' is null
1
'P' is null
1
'P' is null
1
'P' is null
1
'P' is null
 = dyn_cast<PHINode>(I)) {
17
←
Assuming 'I' is not a 'PHINode'→
18
←
Taking false branch→
39
←
Assuming 'I' is not a 'PHINode'→
40
←
Taking false branch→
  // It is possible for very late stage optimizations (such as SimplifyCFG)
  // to introduce PHI nodes too late to be cleaned up.  If we detect such a
  // trivial PHI, go ahead and zap it here.
  if (Value *V = SimplifyInstruction(P, {*DL, TLInfo})) {
    LargeOffsetGEPMap.erase(P);
    P->replaceAllUsesWith(V);
    P->eraseFromParent();
    ++NumPHIsElim;
    return true;
  }
  return false;
}

if (CastInst *CI19.1
'CI' is null
1
'CI' is null
1
'CI' is null
1
'CI' is null
1
'CI' is null
1
'CI' is null
1
'CI' is null
1
'CI' is null
 = dyn_cast<CastInst>(I)) {
19
←
Assuming 'I' is not a 'CastInst'→
20
←
Taking false branch→
41
←
Assuming 'I' is not a 'CastInst'→
42
←
Taking false branch→
  // If the source of the cast is a constant, then this should have
  // already been constant folded.  The only reason NOT to constant fold
  // it is if something (e.g. LSR) was careful to place the constant
  // evaluation in a block other than then one that uses it (e.g. to hoist
  // the address of globals out of a loop).  If this is the case, we don't
  // want to forward-subst the cast.
  if (isa<Constant>(CI->getOperand(0)))
    return false;

  if (TLI && OptimizeNoopCopyExpression(CI, *TLI, *DL))
    return true;

  if (isa<ZExtInst>(I) || isa<SExtInst>(I)) {
    /// Sink a zext or sext into its user blocks if the target type doesn't
    /// fit in one register
    if (TLI &&
        TLI->getTypeAction(CI->getContext(),
                           TLI->getValueType(*DL, CI->getType())) ==
            TargetLowering::TypeExpandInteger) {
      return SinkCast(CI);
    } else {
      bool MadeChange = optimizeExt(I);
      return MadeChange | optimizeExtUses(I);
    }
  }
  return false;
}

if (auto *Cmp21.1
'Cmp' is null
1
'Cmp' is null
1
'Cmp' is null
1
'Cmp' is null
1
'Cmp' is null
1
'Cmp' is null
1
'Cmp' is null
1
'Cmp' is null
 = dyn_cast<CmpInst>(I))
21
←
Assuming 'I' is not a 'CmpInst'→
22
←
Taking false branch→
43
←
Assuming 'I' is not a 'CmpInst'→
44
←
Taking false branch→
  if (TLI && optimizeCmp(Cmp, ModifiedDT))
    return true;

if (LoadInst *LI23.1
'LI' is null
1
'LI' is non-null
1
'LI' is null
1
'LI' is non-null
1
'LI' is null
1
'LI' is non-null
1
'LI' is null
1
'LI' is non-null
 = dyn_cast<LoadInst>(I)) {
23
←
Assuming 'I' is not a 'LoadInst'→
24
←
Taking false branch→
45
←
Assuming 'I' is a 'LoadInst'→
46
←
Taking true branch→
  LI->setMetadata(LLVMContext::MD_invariant_group, nullptr);
  if (TLI) {
47
←
Assuming field 'TLI' is non-null→
48
←
Taking true branch→
    bool Modified = optimizeLoadExt(LI);
49
←
Calling 'CodeGenPrepare::optimizeLoadExt'→
    unsigned AS = LI->getPointerAddressSpace();
    Modified |= optimizeMemoryInst(I, I->getOperand(0), LI->getType(), AS);
    return Modified;
  }
  return false;
}

if (StoreInst *SI25.1
'SI' is null
1
'SI' is null
1
'SI' is null
1
'SI' is null
 = dyn_cast<StoreInst>(I)) {
25
←
Assuming 'I' is not a 'StoreInst'→
26
←
Taking false branch→
  if (TLI && splitMergedValStore(*SI, *DL, *TLI))
    return true;
  SI->setMetadata(LLVMContext::MD_invariant_group, nullptr);
  if (TLI) {
    unsigned AS = SI->getPointerAddressSpace();
    return optimizeMemoryInst(I, SI->getOperand(1),
                              SI->getOperand(0)->getType(), AS);
  }
  return false;
}

if (AtomicRMWInst *RMW27.1
'RMW' is null
1
'RMW' is null
1
'RMW' is null
1
'RMW' is null
 = dyn_cast<AtomicRMWInst>(I)) {
27
←
Assuming 'I' is not a 'AtomicRMWInst'→
28
←
Taking false branch→
    unsigned AS = RMW->getPointerAddressSpace();
    return optimizeMemoryInst(I, RMW->getPointerOperand(),
                              RMW->getType(), AS);
}

if (AtomicCmpXchgInst *CmpX29.1
'CmpX' is null
1
'CmpX' is null
1
'CmpX' is null
1
'CmpX' is null
 = dyn_cast<AtomicCmpXchgInst>(I)) {
29
←
Assuming 'I' is not a 'AtomicCmpXchgInst'→
30
←
Taking false branch→
    unsigned AS = CmpX->getPointerAddressSpace();
    return optimizeMemoryInst(I, CmpX->getPointerOperand(),
                              CmpX->getCompareOperand()->getType(), AS);
}

BinaryOperator *BinOp = dyn_cast<BinaryOperator>(I);
31
←
Assuming 'I' is not a 'BinaryOperator'→

if (BinOp31.1
'BinOp' is null
1
'BinOp' is null
1
'BinOp' is null
1
'BinOp' is null
 && (BinOp->getOpcode() == Instruction::And) &&
    EnableAndCmpSinking && TLI)
  return sinkAndCmp0Expression(BinOp, *TLI, InsertedInsts);

// TODO: Move this into the switch on opcode - it handles shifts already.
if (BinOp31.2
'BinOp' is null
2
'BinOp' is null
2
'BinOp' is null
2
'BinOp' is null
 && (BinOp->getOpcode() == Instruction::AShr ||
              BinOp->getOpcode() == Instruction::LShr)) {
  ConstantInt *CI = dyn_cast<ConstantInt>(BinOp->getOperand(1));
  if (TLI && CI && TLI->hasExtractBitsInsn())
    if (OptimizeExtractBits(BinOp, CI, *TLI, *DL))
      return true;
}

if (GetElementPtrInst *GEPI32.1
'GEPI' is non-null
1
'GEPI' is non-null
1
'GEPI' is non-null
1
'GEPI' is non-null
 = dyn_cast<GetElementPtrInst>(I)) {
32
←
Assuming 'I' is a 'GetElementPtrInst'→
33
←
Taking true branch→
  if (GEPI->hasAllZeroIndices()) {
34
←
Assuming the condition is true→
35
←
Taking true branch→
    /// The GEP operand must be a pointer, so must its result -> BitCast
    Instruction *NC = new BitCastInst(GEPI->getOperand(0), GEPI->getType(),
                                      GEPI->getName(), GEPI);
    NC->setDebugLoc(GEPI->getDebugLoc());
    GEPI->replaceAllUsesWith(NC);
    GEPI->eraseFromParent();
    ++NumGEPsElim;
    optimizeInst(NC, ModifiedDT);
36
←
Calling 'CodeGenPrepare::optimizeInst'→
    return true;
  }
  if (tryUnmergingGEPsAcrossIndirectBr(GEPI, TTI)) {
    return true;
  }
  return false;
}

if (tryToSinkFreeOperands(I))
  return true;

switch (I->getOpcode()) {
case Instruction::Shl:
case Instruction::LShr:
case Instruction::AShr:
  return optimizeShiftInst(cast<BinaryOperator>(I));
case Instruction::Call:
  return optimizeCallInst(cast<CallInst>(I), ModifiedDT);
case Instruction::Select:
  return optimizeSelectInst(cast<SelectInst>(I));
case Instruction::ShuffleVector:
  return optimizeShuffleVectorInst(cast<ShuffleVectorInst>(I));
case Instruction::Switch:
  return optimizeSwitchInst(cast<SwitchInst>(I));
case Instruction::ExtractElement:
  return optimizeExtractElementInst(cast<ExtractElementInst>(I));
}

return false;
7081}

7083/// Given an OR instruction, check to see if this is a bitreverse
7084/// idiom. If so, insert the new intrinsic and return true.
7085static bool makeBitReverse(Instruction &I, const DataLayout &DL,
                         const TargetLowering &TLI) {
if (!I.getType()->isIntegerTy() ||
    !TLI.isOperationLegalOrCustom(ISD::BITREVERSE,
                                  TLI.getValueType(DL, I.getType(), true)))
  return false;

SmallVector<Instruction*, 4> Insts;
if (!recognizeBSwapOrBitReverseIdiom(&I, false, true, Insts))
  return false;
Instruction *LastInst = Insts.back();
I.replaceAllUsesWith(LastInst);
RecursivelyDeleteTriviallyDeadInstructions(&I);
return true;
7099}

7101// In this pass we look for GEP and cast instructions that are used
7102// across basic blocks and rewrite them to improve basic-block-at-a-time
7103// selection.
7104bool CodeGenPrepare::optimizeBlock(BasicBlock &BB, bool &ModifiedDT) {
SunkAddrs.clear();
bool MadeChange = false;

CurInstIterator = BB.begin();
while (CurInstIterator != BB.end()) {
13
←
Loop condition is true.  Entering loop body→
  MadeChange |= optimizeInst(&*CurInstIterator++, ModifiedDT);
14
←
Calling 'CodeGenPrepare::optimizeInst'→
  if (ModifiedDT)
    return true;
}

bool MadeBitReverse = true;
while (TLI && MadeBitReverse) {
  MadeBitReverse = false;
  for (auto &I : reverse(BB)) {
    if (makeBitReverse(I, *DL, *TLI)) {
      MadeBitReverse = MadeChange = true;
      break;
    }
  }
}
MadeChange |= dupRetToEnableTailCallOpts(&BB, ModifiedDT);

return MadeChange;
7128}

7130// llvm.dbg.value is far away from the value then iSel may not be able
7131// handle it properly. iSel will drop llvm.dbg.value if it can not
7132// find a node corresponding to the value.
7133bool CodeGenPrepare::placeDbgValues(Function &F) {
bool MadeChange = false;
for (BasicBlock &BB : F) {
  Instruction *PrevNonDbgInst = nullptr;
  for (BasicBlock::iterator BI = BB.begin(), BE = BB.end(); BI != BE;) {
    Instruction *Insn = &*BI++;
    DbgValueInst *DVI = dyn_cast<DbgValueInst>(Insn);
    // Leave dbg.values that refer to an alloca alone. These
    // intrinsics describe the address of a variable (= the alloca)
    // being taken.  They should not be moved next to the alloca
    // (and to the beginning of the scope), but rather stay close to
    // where said address is used.
    if (!DVI || (DVI->getValue() && isa<AllocaInst>(DVI->getValue()))) {
      PrevNonDbgInst = Insn;
      continue;
    }

    Instruction *VI = dyn_cast_or_null<Instruction>(DVI->getValue());
    if (VI && VI != PrevNonDbgInst && !VI->isTerminator()) {
      // If VI is a phi in a block with an EHPad terminator, we can't insert
      // after it.
      if (isa<PHINode>(VI) && VI->getParent()->getTerminator()->isEHPad())
        continue;
      LLVM_DEBUG(dbgs() << "Moving Debug Value before :\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Moving Debug Value before :\n"
 << *DVI << ' ' << *VI; } } while (false)
                        << *DVI << ' ' << *VI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Moving Debug Value before :\n"
 << *DVI << ' ' << *VI; } } while (false);
      DVI->removeFromParent();
      if (isa<PHINode>(VI))
        DVI->insertBefore(&*VI->getParent()->getFirstInsertionPt());
      else
        DVI->insertAfter(VI);
      MadeChange = true;
      ++NumDbgValueMoved;
    }
  }
}
return MadeChange;
7169}

7171/// Scale down both weights to fit into uint32_t.
7172static void scaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
uint32_t Scale = (NewMax / std::numeric_limits<uint32_t>::max()) + 1;
NewTrue = NewTrue / Scale;
NewFalse = NewFalse / Scale;
7177}

7179/// Some targets prefer to split a conditional branch like:
7180/// \code
7181///   %0 = icmp ne i32 %a, 0
7182///   %1 = icmp ne i32 %b, 0
7183///   %or.cond = or i1 %0, %1
7184///   br i1 %or.cond, label %TrueBB, label %FalseBB
7185/// \endcode
7186/// into multiple branch instructions like:
7187/// \code
7188///   bb1:
7189///     %0 = icmp ne i32 %a, 0
7190///     br i1 %0, label %TrueBB, label %bb2
7191///   bb2:
7192///     %1 = icmp ne i32 %b, 0
7193///     br i1 %1, label %TrueBB, label %FalseBB
7194/// \endcode
7195/// This usually allows instruction selection to do even further optimizations
7196/// and combine the compare with the branch instruction. Currently this is
7197/// applied for targets which have "cheap" jump instructions.
7198///
7199/// FIXME: Remove the (equivalent?) implementation in SelectionDAG.
7200///
7201bool CodeGenPrepare::splitBranchCondition(Function &F, bool &ModifiedDT) {
if (!TM || !TM->Options.EnableFastISel || !TLI || TLI->isJumpExpensive())
  return false;

bool MadeChange = false;
for (auto &BB : F) {
  // Does this BB end with the following?
  //   %cond1 = icmp|fcmp|binary instruction ...
  //   %cond2 = icmp|fcmp|binary instruction ...
  //   %cond.or = or|and i1 %cond1, cond2
  //   br i1 %cond.or label %dest1, label %dest2"
  BinaryOperator *LogicOp;
  BasicBlock *TBB, *FBB;
  if (!match(BB.getTerminator(), m_Br(m_OneUse(m_BinOp(LogicOp)), TBB, FBB)))
    continue;

  auto *Br1 = cast<BranchInst>(BB.getTerminator());
  if (Br1->getMetadata(LLVMContext::MD_unpredictable))
    continue;

  unsigned Opc;
  Value *Cond1, *Cond2;
  if (match(LogicOp, m_And(m_OneUse(m_Value(Cond1)),
                           m_OneUse(m_Value(Cond2)))))
    Opc = Instruction::And;
  else if (match(LogicOp, m_Or(m_OneUse(m_Value(Cond1)),
                               m_OneUse(m_Value(Cond2)))))
    Opc = Instruction::Or;
  else
    continue;

  if (!match(Cond1, m_CombineOr(m_Cmp(), m_BinOp())) ||
      !match(Cond2, m_CombineOr(m_Cmp(), m_BinOp()))   )
    continue;

  LLVM_DEBUG(dbgs() << "Before branch condition splitting\n"; BB.dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "Before branch condition splitting\n"
; BB.dump(); } } while (false);

  // Create a new BB.
  auto TmpBB =
      BasicBlock::Create(BB.getContext(), BB.getName() + ".cond.split",
                         BB.getParent(), BB.getNextNode());

  // Update original basic block by using the first condition directly by the
  // branch instruction and removing the no longer needed and/or instruction.
  Br1->setCondition(Cond1);
  LogicOp->eraseFromParent();

  // Depending on the condition we have to either replace the true or the
  // false successor of the original branch instruction.
  if (Opc == Instruction::And)
    Br1->setSuccessor(0, TmpBB);
  else
    Br1->setSuccessor(1, TmpBB);

  // Fill in the new basic block.
  auto *Br2 = IRBuilder<>(TmpBB).CreateCondBr(Cond2, TBB, FBB);
  if (auto *I = dyn_cast<Instruction>(Cond2)) {
    I->removeFromParent();
    I->insertBefore(Br2);
  }

  // Update PHI nodes in both successors. The original BB needs to be
  // replaced in one successor's PHI nodes, because the branch comes now from
  // the newly generated BB (NewBB). In the other successor we need to add one
  // incoming edge to the PHI nodes, because both branch instructions target
  // now the same successor. Depending on the original branch condition
  // (and/or) we have to swap the successors (TrueDest, FalseDest), so that
  // we perform the correct update for the PHI nodes.
  // This doesn't change the successor order of the just created branch
  // instruction (or any other instruction).
  if (Opc == Instruction::Or)
    std::swap(TBB, FBB);

  // Replace the old BB with the new BB.
  TBB->replacePhiUsesWith(&BB, TmpBB);

  // Add another incoming edge form the new BB.
  for (PHINode &PN : FBB->phis()) {
    auto *Val = PN.getIncomingValueForBlock(&BB);
    PN.addIncoming(Val, TmpBB);
  }

  // Update the branch weights (from SelectionDAGBuilder::
  // FindMergedConditions).
  if (Opc == Instruction::Or) {
    // Codegen X | Y as:
    // BB1:
    //   jmp_if_X TBB
    //   jmp TmpBB
    // TmpBB:
    //   jmp_if_Y TBB
    //   jmp FBB
    //

    // We have flexibility in setting Prob for BB1 and Prob for NewBB.
    // The requirement is that
    //   TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
    //     = TrueProb for original BB.
    // Assuming the original weights are A and B, one choice is to set BB1's
    // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
    // assumes that
    //   TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
    // Another choice is to assume TrueProb for BB1 equals to TrueProb for
    // TmpBB, but the math is more complicated.
    uint64_t TrueWeight, FalseWeight;
    if (Br1->extractProfMetadata(TrueWeight, FalseWeight)) {
      uint64_t NewTrueWeight = TrueWeight;
      uint64_t NewFalseWeight = TrueWeight + 2 * FalseWeight;
      scaleWeights(NewTrueWeight, NewFalseWeight);
      Br1->setMetadata(LLVMContext::MD_prof, MDBuilder(Br1->getContext())
                       .createBranchWeights(TrueWeight, FalseWeight));

      NewTrueWeight = TrueWeight;
      NewFalseWeight = 2 * FalseWeight;
      scaleWeights(NewTrueWeight, NewFalseWeight);
      Br2->setMetadata(LLVMContext::MD_prof, MDBuilder(Br2->getContext())
                       .createBranchWeights(TrueWeight, FalseWeight));
    }
  } else {
    // Codegen X & Y as:
    // BB1:
    //   jmp_if_X TmpBB
    //   jmp FBB
    // TmpBB:
    //   jmp_if_Y TBB
    //   jmp FBB
    //
    //  This requires creation of TmpBB after CurBB.

    // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
    // The requirement is that
    //   FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
    //     = FalseProb for original BB.
    // Assuming the original weights are A and B, one choice is to set BB1's
    // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
    // assumes that
    //   FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
    uint64_t TrueWeight, FalseWeight;
    if (Br1->extractProfMetadata(TrueWeight, FalseWeight)) {
      uint64_t NewTrueWeight = 2 * TrueWeight + FalseWeight;
      uint64_t NewFalseWeight = FalseWeight;
      scaleWeights(NewTrueWeight, NewFalseWeight);
      Br1->setMetadata(LLVMContext::MD_prof, MDBuilder(Br1->getContext())
                       .createBranchWeights(TrueWeight, FalseWeight));

      NewTrueWeight = 2 * TrueWeight;
      NewFalseWeight = FalseWeight;
      scaleWeights(NewTrueWeight, NewFalseWeight);
      Br2->setMetadata(LLVMContext::MD_prof, MDBuilder(Br2->getContext())
                       .createBranchWeights(TrueWeight, FalseWeight));
    }
  }

  ModifiedDT = true;
  MadeChange = true;

  LLVM_DEBUG(dbgs() << "After branch condition splitting\n"; BB.dump();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "After branch condition splitting\n"
; BB.dump(); TmpBB->dump(); } } while (false)
             TmpBB->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("codegenprepare")) { dbgs() << "After branch condition splitting\n"
; BB.dump(); TmpBB->dump(); } } while (false);
}
return MadeChange;
7361}

←

/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h

→

1//===- llvm/ADT/SmallVector.h - 'Normally small' vectors --------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the SmallVector class.
10//
11//===----------------------------------------------------------------------===//

13#ifndef LLVM_ADT_SMALLVECTOR_H
14#define LLVM_ADT_SMALLVECTOR_H

16#include "llvm/ADT/iterator_range.h"
17#include "llvm/Support/AlignOf.h"
18#include "llvm/Support/Compiler.h"
19#include "llvm/Support/MathExtras.h"
20#include "llvm/Support/MemAlloc.h"
21#include "llvm/Support/type_traits.h"
22#include "llvm/Support/ErrorHandling.h"
23#include <algorithm>
24#include <cassert>
25#include <cstddef>
26#include <cstdlib>
27#include <cstring>
28#include <initializer_list>
29#include <iterator>
30#include <memory>
31#include <new>
32#include <type_traits>
33#include <utility>

35namespace llvm {

37/// This is all the non-templated stuff common to all SmallVectors.
38class SmallVectorBase {
39protected:
void *BeginX;
unsigned Size = 0, Capacity;

SmallVectorBase() = delete;
SmallVectorBase(void *FirstEl, size_t TotalCapacity)
    : BeginX(FirstEl), Capacity(TotalCapacity) {}

/// This is an implementation of the grow() method which only works
/// on POD-like data types and is out of line to reduce code duplication.
void grow_pod(void *FirstEl, size_t MinCapacity, size_t TSize);

51public:
size_t size() const { return Size; }
size_t capacity() const { return Capacity; }

LLVM_NODISCARD[[clang::warn_unused_result]] bool empty() const { return !Size; }
56
←
Assuming field 'Size' is 0, which participates in a condition later→
57
←
Returning the value 1, which participates in a condition later→

/// Set the array size to \p N, which the current array must have enough
/// capacity for.
///
/// This does not construct or destroy any elements in the vector.
///
/// Clients can use this in conjunction with capacity() to write past the end
/// of the buffer when they know that more elements are available, and only
/// update the size later. This avoids the cost of value initializing elements
/// which will only be overwritten.
void set_size(size_t N) {
  assert(N <= capacity())((N <= capacity()) ? static_cast<void> (0) : __assert_fail
 ("N <= capacity()", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 67, __PRETTY_FUNCTION__));
  Size = N;
}
70};

72/// Figure out the offset of the first element.
73template <class T, typename = void> struct SmallVectorAlignmentAndSize {
AlignedCharArrayUnion<SmallVectorBase> Base;
AlignedCharArrayUnion<T> FirstEl;
76};

78/// This is the part of SmallVectorTemplateBase which does not depend on whether
79/// the type T is a POD. The extra dummy template argument is used by ArrayRef
80/// to avoid unnecessarily requiring T to be complete.
81template <typename T, typename = void>
82class SmallVectorTemplateCommon : public SmallVectorBase {
/// Find the address of the first element.  For this pointer math to be valid
/// with small-size of 0 for T with lots of alignment, it's important that
/// SmallVectorStorage is properly-aligned even for small-size of 0.
void *getFirstEl() const {
  return const_cast<void *>(reinterpret_cast<const void *>(
      reinterpret_cast<const char *>(this) +
      offsetof(SmallVectorAlignmentAndSize<T>, FirstEl)__builtin_offsetof(SmallVectorAlignmentAndSize<T>, FirstEl
)));
}
// Space after 'FirstEl' is clobbered, do not add any instance vars after it.

93protected:
SmallVectorTemplateCommon(size_t Size)
    : SmallVectorBase(getFirstEl(), Size) {}

void grow_pod(size_t MinCapacity, size_t TSize) {
  SmallVectorBase::grow_pod(getFirstEl(), MinCapacity, TSize);
}

/// Return true if this is a smallvector which has not had dynamic
/// memory allocated for it.
bool isSmall() const { return BeginX == getFirstEl(); }

/// Put this vector in a state of being small.
void resetToSmall() {
  BeginX = getFirstEl();
  Size = Capacity = 0; // FIXME: Setting Capacity to 0 is suspect.
}

111public:
using size_type = size_t;
using difference_type = ptrdiff_t;
using value_type = T;
using iterator = T *;
using const_iterator = const T *;

using const_reverse_iterator = std::reverse_iterator<const_iterator>;
using reverse_iterator = std::reverse_iterator<iterator>;

using reference = T &;
using const_reference = const T &;
using pointer = T *;
using const_pointer = const T *;

// forward iterator creation methods.
iterator begin() { return (iterator)this->BeginX; }
const_iterator begin() const { return (const_iterator)this->BeginX; }
iterator end() { return begin() + size(); }
const_iterator end() const { return begin() + size(); }

// reverse iterator creation methods.
reverse_iterator rbegin()            { return reverse_iterator(end()); }
const_reverse_iterator rbegin() const{ return const_reverse_iterator(end()); }
reverse_iterator rend()              { return reverse_iterator(begin()); }
const_reverse_iterator rend() const { return const_reverse_iterator(begin());}

size_type size_in_bytes() const { return size() * sizeof(T); }
size_type max_size() const { return size_type(-1) / sizeof(T); }

size_t capacity_in_bytes() const { return capacity() * sizeof(T); }

/// Return a pointer to the vector's buffer, even if empty().
pointer data() { return pointer(begin()); }
/// Return a pointer to the vector's buffer, even if empty().
const_pointer data() const { return const_pointer(begin()); }

reference operator[](size_type idx) {
  assert(idx < size())((idx < size()) ? static_cast<void> (0) : __assert_fail
 ("idx < size()", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 149, __PRETTY_FUNCTION__));
  return begin()[idx];
}
const_reference operator[](size_type idx) const {
  assert(idx < size())((idx < size()) ? static_cast<void> (0) : __assert_fail
 ("idx < size()", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 153, __PRETTY_FUNCTION__));
  return begin()[idx];
}

reference front() {
  assert(!empty())((!empty()) ? static_cast<void> (0) : __assert_fail ("!empty()"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 158, __PRETTY_FUNCTION__));
  return begin()[0];
}
const_reference front() const {
  assert(!empty())((!empty()) ? static_cast<void> (0) : __assert_fail ("!empty()"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 162, __PRETTY_FUNCTION__));
  return begin()[0];
}

reference back() {
  assert(!empty())((!empty()) ? static_cast<void> (0) : __assert_fail ("!empty()"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 167, __PRETTY_FUNCTION__));
  return end()[-1];
}
const_reference back() const {
  assert(!empty())((!empty()) ? static_cast<void> (0) : __assert_fail ("!empty()"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 171, __PRETTY_FUNCTION__));
  return end()[-1];
}
174};

176/// SmallVectorTemplateBase<TriviallyCopyable = false> - This is where we put method
177/// implementations that are designed to work with non-POD-like T's.
178template <typename T, bool = is_trivially_copyable<T>::value>
179class SmallVectorTemplateBase : public SmallVectorTemplateCommon<T> {
180protected:
SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}

static void destroy_range(T *S, T *E) {
  while (S != E) {
    --E;
    E->~T();
  }
}

/// Move the range [I, E) into the uninitialized memory starting with "Dest",
/// constructing elements as needed.
template<typename It1, typename It2>
static void uninitialized_move(It1 I, It1 E, It2 Dest) {
  std::uninitialized_copy(std::make_move_iterator(I),
                          std::make_move_iterator(E), Dest);
}

/// Copy the range [I, E) onto the uninitialized memory starting with "Dest",
/// constructing elements as needed.
template<typename It1, typename It2>
static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
  std::uninitialized_copy(I, E, Dest);
}

/// Grow the allocated memory (without initializing new elements), doubling
/// the size of the allocated memory. Guarantees space for at least one more
/// element, or MinSize more elements if specified.
void grow(size_t MinSize = 0);

210public:
void push_back(const T &Elt) {
  if (LLVM_UNLIKELY(this->size() >= this->capacity())__builtin_expect((bool)(this->size() >= this->capacity
()), false))
    this->grow();
  ::new ((void*) this->end()) T(Elt);
  this->set_size(this->size() + 1);
}

void push_back(T &&Elt) {
  if (LLVM_UNLIKELY(this->size() >= this->capacity())__builtin_expect((bool)(this->size() >= this->capacity
()), false))
    this->grow();
  ::new ((void*) this->end()) T(::std::move(Elt));
  this->set_size(this->size() + 1);
}

void pop_back() {
  this->set_size(this->size() - 1);
  this->end()->~T();
}
229};

231// Define this out-of-line to dissuade the C++ compiler from inlining it.
232template <typename T, bool TriviallyCopyable>
233void SmallVectorTemplateBase<T, TriviallyCopyable>::grow(size_t MinSize) {
if (MinSize > UINT32_MAX(4294967295U))
  report_bad_alloc_error("SmallVector capacity overflow during allocation");

// Always grow, even from zero.
size_t NewCapacity = size_t(NextPowerOf2(this->capacity() + 2));
NewCapacity = std::min(std::max(NewCapacity, MinSize), size_t(UINT32_MAX(4294967295U)));
T *NewElts = static_cast<T*>(llvm::safe_malloc(NewCapacity*sizeof(T)));

// Move the elements over.
this->uninitialized_move(this->begin(), this->end(), NewElts);

// Destroy the original elements.
destroy_range(this->begin(), this->end());

// If this wasn't grown from the inline copy, deallocate the old space.
if (!this->isSmall())
  free(this->begin());

this->BeginX = NewElts;
this->Capacity = NewCapacity;
254}

256/// SmallVectorTemplateBase<TriviallyCopyable = true> - This is where we put
257/// method implementations that are designed to work with POD-like T's.
258template <typename T>
259class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T> {
260protected:
SmallVectorTemplateBase(size_t Size) : SmallVectorTemplateCommon<T>(Size) {}

// No need to do a destroy loop for POD's.
static void destroy_range(T *, T *) {}

/// Move the range [I, E) onto the uninitialized memory
/// starting with "Dest", constructing elements into it as needed.
template<typename It1, typename It2>
static void uninitialized_move(It1 I, It1 E, It2 Dest) {
  // Just do a copy.
  uninitialized_copy(I, E, Dest);
}

/// Copy the range [I, E) onto the uninitialized memory
/// starting with "Dest", constructing elements into it as needed.
template<typename It1, typename It2>
static void uninitialized_copy(It1 I, It1 E, It2 Dest) {
  // Arbitrary iterator types; just use the basic implementation.
  std::uninitialized_copy(I, E, Dest);
}

/// Copy the range [I, E) onto the uninitialized memory
/// starting with "Dest", constructing elements into it as needed.
template <typename T1, typename T2>
static void uninitialized_copy(
    T1 *I, T1 *E, T2 *Dest,
    typename std::enable_if<std::is_same<typename std::remove_const<T1>::type,
                                         T2>::value>::type * = nullptr) {
  // Use memcpy for PODs iterated by pointers (which includes SmallVector
  // iterators): std::uninitialized_copy optimizes to memmove, but we can
  // use memcpy here. Note that I and E are iterators and thus might be
  // invalid for memcpy if they are equal.
  if (I != E)
    memcpy(reinterpret_cast<void *>(Dest), I, (E - I) * sizeof(T));
}

/// Double the size of the allocated memory, guaranteeing space for at
/// least one more element or MinSize if specified.
void grow(size_t MinSize = 0) { this->grow_pod(MinSize, sizeof(T)); }

301public:
void push_back(const T &Elt) {
  if (LLVM_UNLIKELY(this->size() >= this->capacity())__builtin_expect((bool)(this->size() >= this->capacity
()), false))
    this->grow();
  memcpy(reinterpret_cast<void *>(this->end()), &Elt, sizeof(T));
  this->set_size(this->size() + 1);
}

void pop_back() { this->set_size(this->size() - 1); }
310};

312/// This class consists of common code factored out of the SmallVector class to
313/// reduce code duplication based on the SmallVector 'N' template parameter.
314template <typename T>
315class SmallVectorImpl : public SmallVectorTemplateBase<T> {
using SuperClass = SmallVectorTemplateBase<T>;

318public:
using iterator = typename SuperClass::iterator;
using const_iterator = typename SuperClass::const_iterator;
using reference = typename SuperClass::reference;
using size_type = typename SuperClass::size_type;

324protected:
// Default ctor - Initialize to empty.
explicit SmallVectorImpl(unsigned N)
    : SmallVectorTemplateBase<T>(N) {}

329public:
SmallVectorImpl(const SmallVectorImpl &) = delete;

~SmallVectorImpl() {
  // Subclass has already destructed this vector's elements.
  // If this wasn't grown from the inline copy, deallocate the old space.
  if (!this->isSmall())
    free(this->begin());
}

void clear() {
  this->destroy_range(this->begin(), this->end());
  this->Size = 0;
}

void resize(size_type N) {
  if (N < this->size()) {
    this->destroy_range(this->begin()+N, this->end());
    this->set_size(N);
  } else if (N > this->size()) {
    if (this->capacity() < N)
      this->grow(N);
    for (auto I = this->end(), E = this->begin() + N; I != E; ++I)
      new (&*I) T();
    this->set_size(N);
  }
}

void resize(size_type N, const T &NV) {
  if (N < this->size()) {
    this->destroy_range(this->begin()+N, this->end());
    this->set_size(N);
  } else if (N > this->size()) {
    if (this->capacity() < N)
      this->grow(N);
    std::uninitialized_fill(this->end(), this->begin()+N, NV);
    this->set_size(N);
  }
}

void reserve(size_type N) {
  if (this->capacity() < N)
    this->grow(N);
}

LLVM_NODISCARD[[clang::warn_unused_result]] T pop_back_val() {
  T Result = ::std::move(this->back());
  this->pop_back();
  return Result;
}

void swap(SmallVectorImpl &RHS);

/// Add the specified range to the end of the SmallVector.
template <typename in_iter,
          typename = typename std::enable_if<std::is_convertible<
              typename std::iterator_traits<in_iter>::iterator_category,
              std::input_iterator_tag>::value>::type>
void append(in_iter in_start, in_iter in_end) {
  size_type NumInputs = std::distance(in_start, in_end);
  if (NumInputs > this->capacity() - this->size())
    this->grow(this->size()+NumInputs);

  this->uninitialized_copy(in_start, in_end, this->end());
  this->set_size(this->size() + NumInputs);
}

/// Append \p NumInputs copies of \p Elt to the end.
void append(size_type NumInputs, const T &Elt) {
  if (NumInputs > this->capacity() - this->size())
    this->grow(this->size()+NumInputs);

  std::uninitialized_fill_n(this->end(), NumInputs, Elt);
  this->set_size(this->size() + NumInputs);
}

void append(std::initializer_list<T> IL) {
  append(IL.begin(), IL.end());
}

// FIXME: Consider assigning over existing elements, rather than clearing &
// re-initializing them - for all assign(...) variants.

void assign(size_type NumElts, const T &Elt) {
  clear();
  if (this->capacity() < NumElts)
    this->grow(NumElts);
  this->set_size(NumElts);
  std::uninitialized_fill(this->begin(), this->end(), Elt);
}

template <typename in_iter,
          typename = typename std::enable_if<std::is_convertible<
              typename std::iterator_traits<in_iter>::iterator_category,
              std::input_iterator_tag>::value>::type>
void assign(in_iter in_start, in_iter in_end) {
  clear();
  append(in_start, in_end);
}

void assign(std::initializer_list<T> IL) {
  clear();
  append(IL);
}

iterator erase(const_iterator CI) {
  // Just cast away constness because this is a non-const member function.
  iterator I = const_cast<iterator>(CI);

  assert(I >= this->begin() && "Iterator to erase is out of bounds.")((I >= this->begin() && "Iterator to erase is out of bounds."
) ? static_cast<void> (0) : __assert_fail ("I >= this->begin() && \"Iterator to erase is out of bounds.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 438, __PRETTY_FUNCTION__));
  assert(I < this->end() && "Erasing at past-the-end iterator.")((I < this->end() && "Erasing at past-the-end iterator."
) ? static_cast<void> (0) : __assert_fail ("I < this->end() && \"Erasing at past-the-end iterator.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 439, __PRETTY_FUNCTION__));

  iterator N = I;
  // Shift all elts down one.
  std::move(I+1, this->end(), I);
  // Drop the last elt.
  this->pop_back();
  return(N);
}

iterator erase(const_iterator CS, const_iterator CE) {
  // Just cast away constness because this is a non-const member function.
  iterator S = const_cast<iterator>(CS);
  iterator E = const_cast<iterator>(CE);

  assert(S >= this->begin() && "Range to erase is out of bounds.")((S >= this->begin() && "Range to erase is out of bounds."
) ? static_cast<void> (0) : __assert_fail ("S >= this->begin() && \"Range to erase is out of bounds.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 454, __PRETTY_FUNCTION__));
  assert(S <= E && "Trying to erase invalid range.")((S <= E && "Trying to erase invalid range.") ? static_cast
<void> (0) : __assert_fail ("S <= E && \"Trying to erase invalid range.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 455, __PRETTY_FUNCTION__));
  assert(E <= this->end() && "Trying to erase past the end.")((E <= this->end() && "Trying to erase past the end."
) ? static_cast<void> (0) : __assert_fail ("E <= this->end() && \"Trying to erase past the end.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 456, __PRETTY_FUNCTION__));

  iterator N = S;
  // Shift all elts down.
  iterator I = std::move(E, this->end(), S);
  // Drop the last elts.
  this->destroy_range(I, this->end());
  this->set_size(I - this->begin());
  return(N);
}

iterator insert(iterator I, T &&Elt) {
  if (I == this->end()) {  // Important special case for empty vector.
    this->push_back(::std::move(Elt));
    return this->end()-1;
  }

  assert(I >= this->begin() && "Insertion iterator is out of bounds.")((I >= this->begin() && "Insertion iterator is out of bounds."
) ? static_cast<void> (0) : __assert_fail ("I >= this->begin() && \"Insertion iterator is out of bounds.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 473, __PRETTY_FUNCTION__));
  assert(I <= this->end() && "Inserting past the end of the vector.")((I <= this->end() && "Inserting past the end of the vector."
) ? static_cast<void> (0) : __assert_fail ("I <= this->end() && \"Inserting past the end of the vector.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 474, __PRETTY_FUNCTION__));

  if (this->size() >= this->capacity()) {
    size_t EltNo = I-this->begin();
    this->grow();
    I = this->begin()+EltNo;
  }

  ::new ((void*) this->end()) T(::std::move(this->back()));
  // Push everything else over.
  std::move_backward(I, this->end()-1, this->end());
  this->set_size(this->size() + 1);

  // If we just moved the element we're inserting, be sure to update
  // the reference.
  T *EltPtr = &Elt;
  if (I <= EltPtr && EltPtr < this->end())
    ++EltPtr;

  *I = ::std::move(*EltPtr);
  return I;
}

iterator insert(iterator I, const T &Elt) {
  if (I == this->end()) {  // Important special case for empty vector.
    this->push_back(Elt);
    return this->end()-1;
  }

  assert(I >= this->begin() && "Insertion iterator is out of bounds.")((I >= this->begin() && "Insertion iterator is out of bounds."
) ? static_cast<void> (0) : __assert_fail ("I >= this->begin() && \"Insertion iterator is out of bounds.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 503, __PRETTY_FUNCTION__));
  assert(I <= this->end() && "Inserting past the end of the vector.")((I <= this->end() && "Inserting past the end of the vector."
) ? static_cast<void> (0) : __assert_fail ("I <= this->end() && \"Inserting past the end of the vector.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 504, __PRETTY_FUNCTION__));

  if (this->size() >= this->capacity()) {
    size_t EltNo = I-this->begin();
    this->grow();
    I = this->begin()+EltNo;
  }
  ::new ((void*) this->end()) T(std::move(this->back()));
  // Push everything else over.
  std::move_backward(I, this->end()-1, this->end());
  this->set_size(this->size() + 1);

  // If we just moved the element we're inserting, be sure to update
  // the reference.
  const T *EltPtr = &Elt;
  if (I <= EltPtr && EltPtr < this->end())
    ++EltPtr;

  *I = *EltPtr;
  return I;
}

iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
  // Convert iterator to elt# to avoid invalidating iterator when we reserve()
  size_t InsertElt = I - this->begin();

  if (I == this->end()) {  // Important special case for empty vector.
    append(NumToInsert, Elt);
    return this->begin()+InsertElt;
  }

  assert(I >= this->begin() && "Insertion iterator is out of bounds.")((I >= this->begin() && "Insertion iterator is out of bounds."
) ? static_cast<void> (0) : __assert_fail ("I >= this->begin() && \"Insertion iterator is out of bounds.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 535, __PRETTY_FUNCTION__));
  assert(I <= this->end() && "Inserting past the end of the vector.")((I <= this->end() && "Inserting past the end of the vector."
) ? static_cast<void> (0) : __assert_fail ("I <= this->end() && \"Inserting past the end of the vector.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 536, __PRETTY_FUNCTION__));

  // Ensure there is enough space.
  reserve(this->size() + NumToInsert);

  // Uninvalidate the iterator.
  I = this->begin()+InsertElt;

  // If there are more elements between the insertion point and the end of the
  // range than there are being inserted, we can use a simple approach to
  // insertion.  Since we already reserved space, we know that this won't
  // reallocate the vector.
  if (size_t(this->end()-I) >= NumToInsert) {
    T *OldEnd = this->end();
    append(std::move_iterator<iterator>(this->end() - NumToInsert),
           std::move_iterator<iterator>(this->end()));

    // Copy the existing elements that get replaced.
    std::move_backward(I, OldEnd-NumToInsert, OldEnd);

    std::fill_n(I, NumToInsert, Elt);
    return I;
  }

  // Otherwise, we're inserting more elements than exist already, and we're
  // not inserting at the end.

  // Move over the elements that we're about to overwrite.
  T *OldEnd = this->end();
  this->set_size(this->size() + NumToInsert);
  size_t NumOverwritten = OldEnd-I;
  this->uninitialized_move(I, OldEnd, this->end()-NumOverwritten);

  // Replace the overwritten part.
  std::fill_n(I, NumOverwritten, Elt);

  // Insert the non-overwritten middle part.
  std::uninitialized_fill_n(OldEnd, NumToInsert-NumOverwritten, Elt);
  return I;
}

template <typename ItTy,
          typename = typename std::enable_if<std::is_convertible<
              typename std::iterator_traits<ItTy>::iterator_category,
              std::input_iterator_tag>::value>::type>
iterator insert(iterator I, ItTy From, ItTy To) {
  // Convert iterator to elt# to avoid invalidating iterator when we reserve()
  size_t InsertElt = I - this->begin();

  if (I == this->end()) {  // Important special case for empty vector.
    append(From, To);
    return this->begin()+InsertElt;
  }

  assert(I >= this->begin() && "Insertion iterator is out of bounds.")((I >= this->begin() && "Insertion iterator is out of bounds."
) ? static_cast<void> (0) : __assert_fail ("I >= this->begin() && \"Insertion iterator is out of bounds.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 590, __PRETTY_FUNCTION__));
  assert(I <= this->end() && "Inserting past the end of the vector.")((I <= this->end() && "Inserting past the end of the vector."
) ? static_cast<void> (0) : __assert_fail ("I <= this->end() && \"Inserting past the end of the vector.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/SmallVector.h"
, 591, __PRETTY_FUNCTION__));

  size_t NumToInsert = std::distance(From, To);

  // Ensure there is enough space.
  reserve(this->size() + NumToInsert);

  // Uninvalidate the iterator.
  I = this->begin()+InsertElt;

  // If there are more elements between the insertion point and the end of the
  // range than there are being inserted, we can use a simple approach to
  // insertion.  Since we already reserved space, we know that this won't
  // reallocate the vector.
  if (size_t(this->end()-I) >= NumToInsert) {
    T *OldEnd = this->end();
    append(std::move_iterator<iterator>(this->end() - NumToInsert),
           std::move_iterator<iterator>(this->end()));

    // Copy the existing elements that get replaced.
    std::move_backward(I, OldEnd-NumToInsert, OldEnd);

    std::copy(From, To, I);
    return I;
  }

  // Otherwise, we're inserting more elements than exist already, and we're
  // not inserting at the end.

  // Move over the elements that we're about to overwrite.
  T *OldEnd = this->end();
  this->set_size(this->size() + NumToInsert);
  size_t NumOverwritten = OldEnd-I;
  this->uninitialized_move(I, OldEnd, this->end()-NumOverwritten);

  // Replace the overwritten part.
  for (T *J = I; NumOverwritten > 0; --NumOverwritten) {
    *J = *From;
    ++J; ++From;
  }

  // Insert the non-overwritten middle part.
  this->uninitialized_copy(From, To, OldEnd);
  return I;
}

void insert(iterator I, std::initializer_list<T> IL) {
  insert(I, IL.begin(), IL.end());
}

template <typename... ArgTypes> reference emplace_back(ArgTypes &&... Args) {
  if (LLVM_UNLIKELY(this->size() >= this->capacity())__builtin_expect((bool)(this->size() >= this->capacity
()), false))
    this->grow();
  ::new ((void *)this->end()) T(std::forward<ArgTypes>(Args)...);
  this->set_size(this->size() + 1);
  return this->back();
}

SmallVectorImpl &operator=(const SmallVectorImpl &RHS);

SmallVectorImpl &operator=(SmallVectorImpl &&RHS);

bool operator==(const SmallVectorImpl &RHS) const {
  if (this->size() != RHS.size()) return false;
  return std::equal(this->begin(), this->end(), RHS.begin());
}
bool operator!=(const SmallVectorImpl &RHS) const {
  return !(*this == RHS);
}

bool operator<(const SmallVectorImpl &RHS) const {
  return std::lexicographical_compare(this->begin(), this->end(),
                                      RHS.begin(), RHS.end());
}
665};

667template <typename T>
668void SmallVectorImpl<T>::swap(SmallVectorImpl<T> &RHS) {
if (this == &RHS) return;

// We can only avoid copying elements if neither vector is small.
if (!this->isSmall() && !RHS.isSmall()) {
  std::swap(this->BeginX, RHS.BeginX);
  std::swap(this->Size, RHS.Size);
  std::swap(this->Capacity, RHS.Capacity);
  return;
}
if (RHS.size() > this->capacity())
  this->grow(RHS.size());
if (this->size() > RHS.capacity())
  RHS.grow(this->size());

// Swap the shared elements.
size_t NumShared = this->size();
if (NumShared > RHS.size()) NumShared = RHS.size();
for (size_type i = 0; i != NumShared; ++i)
  std::swap((*this)[i], RHS[i]);

// Copy over the extra elts.
if (this->size() > RHS.size()) {
  size_t EltDiff = this->size() - RHS.size();
  this->uninitialized_copy(this->begin()+NumShared, this->end(), RHS.end());
  RHS.set_size(RHS.size() + EltDiff);
  this->destroy_range(this->begin()+NumShared, this->end());
  this->set_size(NumShared);
} else if (RHS.size() > this->size()) {
  size_t EltDiff = RHS.size() - this->size();
  this->uninitialized_copy(RHS.begin()+NumShared, RHS.end(), this->end());
  this->set_size(this->size() + EltDiff);
  this->destroy_range(RHS.begin()+NumShared, RHS.end());
  RHS.set_size(NumShared);
}
703}

705template <typename T>
706SmallVectorImpl<T> &SmallVectorImpl<T>::
operator=(const SmallVectorImpl<T> &RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;

// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (CurSize >= RHSSize) {
  // Assign common elements.
  iterator NewEnd;
  if (RHSSize)
    NewEnd = std::copy(RHS.begin(), RHS.begin()+RHSSize, this->begin());
  else
    NewEnd = this->begin();

  // Destroy excess elements.
  this->destroy_range(NewEnd, this->end());

  // Trim.
  this->set_size(RHSSize);
  return *this;
}

// If we have to grow to have enough elements, destroy the current elements.
// This allows us to avoid copying them during the grow.
// FIXME: don't do this if they're efficiently moveable.
if (this->capacity() < RHSSize) {
  // Destroy current elements.
  this->destroy_range(this->begin(), this->end());
  this->set_size(0);
  CurSize = 0;
  this->grow(RHSSize);
} else if (CurSize) {
  // Otherwise, use assignment for the already-constructed elements.
  std::copy(RHS.begin(), RHS.begin()+CurSize, this->begin());
}

// Copy construct the new elements in place.
this->uninitialized_copy(RHS.begin()+CurSize, RHS.end(),
                         this->begin()+CurSize);

// Set end.
this->set_size(RHSSize);
return *this;
752}

754template <typename T>
755SmallVectorImpl<T> &SmallVectorImpl<T>::operator=(SmallVectorImpl<T> &&RHS) {
// Avoid self-assignment.
if (this == &RHS) return *this;

// If the RHS isn't small, clear this vector and then steal its buffer.
if (!RHS.isSmall()) {
  this->destroy_range(this->begin(), this->end());
  if (!this->isSmall()) free(this->begin());
  this->BeginX = RHS.BeginX;
  this->Size = RHS.Size;
  this->Capacity = RHS.Capacity;
  RHS.resetToSmall();
  return *this;
}

// If we already have sufficient space, assign the common elements, then
// destroy any excess.
size_t RHSSize = RHS.size();
size_t CurSize = this->size();
if (CurSize >= RHSSize) {
  // Assign common elements.
  iterator NewEnd = this->begin();
  if (RHSSize)
    NewEnd = std::move(RHS.begin(), RHS.end(), NewEnd);

  // Destroy excess elements and trim the bounds.
  this->destroy_range(NewEnd, this->end());
  this->set_size(RHSSize);

  // Clear the RHS.
  RHS.clear();

  return *this;
}

// If we have to grow to have enough elements, destroy the current elements.
// This allows us to avoid copying them during the grow.
// FIXME: this may not actually make any sense if we can efficiently move
// elements.
if (this->capacity() < RHSSize) {
  // Destroy current elements.
  this->destroy_range(this->begin(), this->end());
  this->set_size(0);
  CurSize = 0;
  this->grow(RHSSize);
} else if (CurSize) {
  // Otherwise, use assignment for the already-constructed elements.
  std::move(RHS.begin(), RHS.begin()+CurSize, this->begin());
}

// Move-construct the new elements in place.
this->uninitialized_move(RHS.begin()+CurSize, RHS.end(),
                         this->begin()+CurSize);

// Set end.
this->set_size(RHSSize);

RHS.clear();
return *this;
814}

816/// Storage for the SmallVector elements.  This is specialized for the N=0 case
817/// to avoid allocating unnecessary storage.
818template <typename T, unsigned N>
819struct SmallVectorStorage {
AlignedCharArrayUnion<T> InlineElts[N];
821};

823/// We need the storage to be properly aligned even for small-size of 0 so that
824/// the pointer math in \a SmallVectorTemplateCommon::getFirstEl() is
825/// well-defined.
826template <typename T> struct alignas(alignof(T)) SmallVectorStorage<T, 0> {};

828/// This is a 'vector' (really, a variable-sized array), optimized
829/// for the case when the array is small.  It contains some number of elements
830/// in-place, which allows it to avoid heap allocation when the actual number of
831/// elements is below that threshold.  This allows normal "small" cases to be
832/// fast without losing generality for large inputs.
833///
834/// Note that this does not attempt to be exception safe.
835///
836template <typename T, unsigned N>
837class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
838public:
SmallVector() : SmallVectorImpl<T>(N) {}

~SmallVector() {
  // Destroy the constructed elements in the vector.
  this->destroy_range(this->begin(), this->end());
}

explicit SmallVector(size_t Size, const T &Value = T())
  : SmallVectorImpl<T>(N) {
  this->assign(Size, Value);
}

template <typename ItTy,
          typename = typename std::enable_if<std::is_convertible<
              typename std::iterator_traits<ItTy>::iterator_category,
              std::input_iterator_tag>::value>::type>
SmallVector(ItTy S, ItTy E) : SmallVectorImpl<T>(N) {
  this->append(S, E);
}

template <typename RangeTy>
explicit SmallVector(const iterator_range<RangeTy> &R)
    : SmallVectorImpl<T>(N) {
  this->append(R.begin(), R.end());
}

SmallVector(std::initializer_list<T> IL) : SmallVectorImpl<T>(N) {
  this->assign(IL);
}

SmallVector(const SmallVector &RHS) : SmallVectorImpl<T>(N) {
  if (!RHS.empty())
    SmallVectorImpl<T>::operator=(RHS);
}

const SmallVector &operator=(const SmallVector &RHS) {
  SmallVectorImpl<T>::operator=(RHS);
  return *this;
}

SmallVector(SmallVector &&RHS) : SmallVectorImpl<T>(N) {
  if (!RHS.empty())
    SmallVectorImpl<T>::operator=(::std::move(RHS));
}

SmallVector(SmallVectorImpl<T> &&RHS) : SmallVectorImpl<T>(N) {
  if (!RHS.empty())
    SmallVectorImpl<T>::operator=(::std::move(RHS));
}

const SmallVector &operator=(SmallVector &&RHS) {
  SmallVectorImpl<T>::operator=(::std::move(RHS));
  return *this;
}

const SmallVector &operator=(SmallVectorImpl<T> &&RHS) {
  SmallVectorImpl<T>::operator=(::std::move(RHS));
  return *this;
}

const SmallVector &operator=(std::initializer_list<T> IL) {
  this->assign(IL);
  return *this;
}
903};

905template <typename T, unsigned N>
906inline size_t capacity_in_bytes(const SmallVector<T, N> &X) {
return X.capacity_in_bytes();
908}

910} // end namespace llvm

912namespace std {

/// Implement std::swap in terms of SmallVector swap.
template<typename T>
inline void
swap(llvm::SmallVectorImpl<T> &LHS, llvm::SmallVectorImpl<T> &RHS) {
  LHS.swap(RHS);
}

/// Implement std::swap in terms of SmallVector swap.
template<typename T, unsigned N>
inline void
swap(llvm::SmallVector<T, N> &LHS, llvm::SmallVector<T, N> &RHS) {
  LHS.swap(RHS);
}

928} // end namespace std

930#endif // LLVM_ADT_SMALLVECTOR_H

←

/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h

→

1//===-- llvm/ADT/APInt.h - For Arbitrary Precision Integer -----*- C++ -*--===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file implements a class to represent arbitrary precision
11/// integral constant values and operations on them.
12///
13//===----------------------------------------------------------------------===//

15#ifndef LLVM_ADT_APINT_H
16#define LLVM_ADT_APINT_H

18#include "llvm/Support/Compiler.h"
19#include "llvm/Support/MathExtras.h"
20#include <cassert>
21#include <climits>
22#include <cstring>
23#include <string>

25namespace llvm {
26class FoldingSetNodeID;
27class StringRef;
28class hash_code;
29class raw_ostream;

31template <typename T> class SmallVectorImpl;
32template <typename T> class ArrayRef;
33template <typename T> class Optional;

35class APInt;

37inline APInt operator-(APInt);

39//===----------------------------------------------------------------------===//
40//                              APInt Class
41//===----------------------------------------------------------------------===//

43/// Class for arbitrary precision integers.
44///
45/// APInt is a functional replacement for common case unsigned integer type like
46/// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-width
47/// integer sizes and large integer value types such as 3-bits, 15-bits, or more
48/// than 64-bits of precision. APInt provides a variety of arithmetic operators
49/// and methods to manipulate integer values of any bit-width. It supports both
50/// the typical integer arithmetic and comparison operations as well as bitwise
51/// manipulation.
52///
53/// The class has several invariants worth noting:
54///   * All bit, byte, and word positions are zero-based.
55///   * Once the bit width is set, it doesn't change except by the Truncate,
56///     SignExtend, or ZeroExtend operations.
57///   * All binary operators must be on APInt instances of the same bit width.
58///     Attempting to use these operators on instances with different bit
59///     widths will yield an assertion.
60///   * The value is stored canonically as an unsigned value. For operations
61///     where it makes a difference, there are both signed and unsigned variants
62///     of the operation. For example, sdiv and udiv. However, because the bit
63///     widths must be the same, operations such as Mul and Add produce the same
64///     results regardless of whether the values are interpreted as signed or
65///     not.
66///   * In general, the class tries to follow the style of computation that LLVM
67///     uses in its IR. This simplifies its use for LLVM.
68///
69class LLVM_NODISCARD[[clang::warn_unused_result]] APInt {
70public:
typedef uint64_t WordType;

/// This enum is used to hold the constants we needed for APInt.
enum : unsigned {
  /// Byte size of a word.
  APINT_WORD_SIZE = sizeof(WordType),
  /// Bits in a word.
  APINT_BITS_PER_WORD = APINT_WORD_SIZE * CHAR_BIT8
};

enum class Rounding {
  DOWN,
  TOWARD_ZERO,
  UP,
};

static const WordType WORDTYPE_MAX = ~WordType(0);

89private:
/// This union is used to store the integer value. When the
/// integer bit-width <= 64, it uses VAL, otherwise it uses pVal.
union {
  uint64_t VAL;   ///< Used to store the <= 64 bits integer value.
  uint64_t *pVal; ///< Used to store the >64 bits integer value.
} U;

unsigned BitWidth; ///< The number of bits in this APInt.

friend struct DenseMapAPIntKeyInfo;

friend class APSInt;

/// Fast internal constructor
///
/// This constructor is used only internally for speed of construction of
/// temporaries. It is unsafe for general use so it is not public.
APInt(uint64_t *val, unsigned bits) : BitWidth(bits) {
  U.pVal = val;
}

/// Determine if this APInt just has one word to store value.
///
/// \returns true if the number of bits <= 64, false otherwise.
bool isSingleWord() const { return BitWidth <= APINT_BITS_PER_WORD; }

/// Determine which word a bit is in.
///
/// \returns the word position for the specified bit position.
static unsigned whichWord(unsigned bitPosition) {
  return bitPosition / APINT_BITS_PER_WORD;
}

/// Determine which bit in a word a bit is in.
///
/// \returns the bit position in a word for the specified bit position
/// in the APInt.
static unsigned whichBit(unsigned bitPosition) {
  return bitPosition % APINT_BITS_PER_WORD;
}

/// Get a single bit mask.
///
/// \returns a uint64_t with only bit at "whichBit(bitPosition)" set
/// This method generates and returns a uint64_t (word) mask for a single
/// bit at a specific bit position. This is used to mask the bit in the
/// corresponding word.
static uint64_t maskBit(unsigned bitPosition) {
  return 1ULL << whichBit(bitPosition);
}

/// Clear unused high order bits
///
/// This method is used internally to clear the top "N" bits in the high order
/// word that are not used by the APInt. This is needed after the most
/// significant word is assigned a value to ensure that those bits are
/// zero'd out.
APInt &clearUnusedBits() {
  // Compute how many bits are used in the final word
  unsigned WordBits = ((BitWidth-1) % APINT_BITS_PER_WORD) + 1;

  // Mask out the high bits.
  uint64_t mask = WORDTYPE_MAX >> (APINT_BITS_PER_WORD - WordBits);
  if (isSingleWord())
    U.VAL &= mask;
  else
    U.pVal[getNumWords() - 1] &= mask;
  return *this;
}

/// Get the word corresponding to a bit position
/// \returns the corresponding word for the specified bit position.
uint64_t getWord(unsigned bitPosition) const {
  return isSingleWord() ? U.VAL : U.pVal[whichWord(bitPosition)];
}

/// Utility method to change the bit width of this APInt to new bit width,
/// allocating and/or deallocating as necessary. There is no guarantee on the
/// value of any bits upon return. Caller should populate the bits after.
void reallocate(unsigned NewBitWidth);

/// Convert a char array into an APInt
///
/// \param radix 2, 8, 10, 16, or 36
/// Converts a string into a number.  The string must be non-empty
/// and well-formed as a number of the given base. The bit-width
/// must be sufficient to hold the result.
///
/// This is used by the constructors that take string arguments.
///
/// StringRef::getAsInteger is superficially similar but (1) does
/// not assume that the string is well-formed and (2) grows the
/// result to hold the input.
void fromString(unsigned numBits, StringRef str, uint8_t radix);

/// An internal division function for dividing APInts.
///
/// This is used by the toString method to divide by the radix. It simply
/// provides a more convenient form of divide for internal use since KnuthDiv
/// has specific constraints on its inputs. If those constraints are not met
/// then it provides a simpler form of divide.
static void divide(const WordType *LHS, unsigned lhsWords,
                   const WordType *RHS, unsigned rhsWords, WordType *Quotient,
                   WordType *Remainder);

/// out-of-line slow case for inline constructor
void initSlowCase(uint64_t val, bool isSigned);

/// shared code between two array constructors
void initFromArray(ArrayRef<uint64_t> array);

/// out-of-line slow case for inline copy constructor
void initSlowCase(const APInt &that);

/// out-of-line slow case for shl
void shlSlowCase(unsigned ShiftAmt);

/// out-of-line slow case for lshr.
void lshrSlowCase(unsigned ShiftAmt);

/// out-of-line slow case for ashr.
void ashrSlowCase(unsigned ShiftAmt);

/// out-of-line slow case for operator=
void AssignSlowCase(const APInt &RHS);

/// out-of-line slow case for operator==
bool EqualSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for countLeadingZeros
unsigned countLeadingZerosSlowCase() const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for countLeadingOnes.
unsigned countLeadingOnesSlowCase() const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for countTrailingZeros.
unsigned countTrailingZerosSlowCase() const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for countTrailingOnes
unsigned countTrailingOnesSlowCase() const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for countPopulation
unsigned countPopulationSlowCase() const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for intersects.
bool intersectsSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for isSubsetOf.
bool isSubsetOfSlowCase(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));

/// out-of-line slow case for setBits.
void setBitsSlowCase(unsigned loBit, unsigned hiBit);

/// out-of-line slow case for flipAllBits.
void flipAllBitsSlowCase();

/// out-of-line slow case for operator&=.
void AndAssignSlowCase(const APInt& RHS);

/// out-of-line slow case for operator|=.
void OrAssignSlowCase(const APInt& RHS);

/// out-of-line slow case for operator^=.
void XorAssignSlowCase(const APInt& RHS);

/// Unsigned comparison. Returns -1, 0, or 1 if this APInt is less than, equal
/// to, or greater than RHS.
int compare(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));

/// Signed comparison. Returns -1, 0, or 1 if this APInt is less than, equal
/// to, or greater than RHS.
int compareSigned(const APInt &RHS) const LLVM_READONLY__attribute__((__pure__));

263public:
/// \name Constructors
/// @{

/// Create a new APInt of numBits width, initialized as val.
///
/// If isSigned is true then val is treated as if it were a signed value
/// (i.e. as an int64_t) and the appropriate sign extension to the bit width
/// will be done. Otherwise, no sign extension occurs (high order bits beyond
/// the range of val are zero filled).
///
/// \param numBits the bit width of the constructed APInt
/// \param val the initial value of the APInt
/// \param isSigned how to treat signedness of val
APInt(unsigned numBits, uint64_t val, bool isSigned = false)
    : BitWidth(numBits) {
  assert(BitWidth && "bitwidth too small")((BitWidth && "bitwidth too small") ? static_cast<
void> (0) : __assert_fail ("BitWidth && \"bitwidth too small\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 279, __PRETTY_FUNCTION__));
  if (isSingleWord()) {
    U.VAL = val;
    clearUnusedBits();
  } else {
    initSlowCase(val, isSigned);
  }
}

/// Construct an APInt of numBits width, initialized as bigVal[].
///
/// Note that bigVal.size() can be smaller or larger than the corresponding
/// bit width but any extraneous bits will be dropped.
///
/// \param numBits the bit width of the constructed APInt
/// \param bigVal a sequence of words to form the initial value of the APInt
APInt(unsigned numBits, ArrayRef<uint64_t> bigVal);

/// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), but
/// deprecated because this constructor is prone to ambiguity with the
/// APInt(unsigned, uint64_t, bool) constructor.
///
/// If this overload is ever deleted, care should be taken to prevent calls
/// from being incorrectly captured by the APInt(unsigned, uint64_t, bool)
/// constructor.
APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);

/// Construct an APInt from a string representation.
///
/// This constructor interprets the string \p str in the given radix. The
/// interpretation stops when the first character that is not suitable for the
/// radix is encountered, or the end of the string. Acceptable radix values
/// are 2, 8, 10, 16, and 36. It is an error for the value implied by the
/// string to require more bits than numBits.
///
/// \param numBits the bit width of the constructed APInt
/// \param str the string to be interpreted
/// \param radix the radix to use for the conversion
APInt(unsigned numBits, StringRef str, uint8_t radix);

/// Simply makes *this a copy of that.
/// Copy Constructor.
APInt(const APInt &that) : BitWidth(that.BitWidth) {
  if (isSingleWord())
    U.VAL = that.U.VAL;
  else
    initSlowCase(that);
}

/// Move Constructor.
APInt(APInt &&that) : BitWidth(that.BitWidth) {
  memcpy(&U, &that.U, sizeof(U));
  that.BitWidth = 0;
}

/// Destructor.
~APInt() {
  if (needsCleanup())
    delete[] U.pVal;
}

/// Default constructor that creates an uninteresting APInt
/// representing a 1-bit zero value.
///
/// This is useful for object deserialization (pair this with the static
///  method Read).
explicit APInt() : BitWidth(1) { U.VAL = 0; }

/// Returns whether this instance allocated memory.
bool needsCleanup() const { return !isSingleWord(); }

/// Used to insert APInt objects, or objects that contain APInt objects, into
///  FoldingSets.
void Profile(FoldingSetNodeID &id) const;

/// @}
/// \name Value Tests
/// @{

/// Determine sign of this APInt.
///
/// This tests the high bit of this APInt to determine if it is set.
///
/// \returns true if this APInt is negative, false otherwise
bool isNegative() const { return (*this)[BitWidth - 1]; }

/// Determine if this APInt Value is non-negative (>= 0)
///
/// This tests the high bit of the APInt to determine if it is unset.
bool isNonNegative() const { return !isNegative(); }

/// Determine if sign bit of this APInt is set.
///
/// This tests the high bit of this APInt to determine if it is set.
///
/// \returns true if this APInt has its sign bit set, false otherwise.
bool isSignBitSet() const { return (*this)[BitWidth-1]; }

/// Determine if sign bit of this APInt is clear.
///
/// This tests the high bit of this APInt to determine if it is clear.
///
/// \returns true if this APInt has its sign bit clear, false otherwise.
bool isSignBitClear() const { return !isSignBitSet(); }

/// Determine if this APInt Value is positive.
///
/// This tests if the value of this APInt is positive (> 0). Note
/// that 0 is not a positive value.
///
/// \returns true if this APInt is positive.
bool isStrictlyPositive() const { return isNonNegative() && !isNullValue(); }

/// Determine if all bits are set
///
/// This checks to see if the value has all bits of the APInt are set or not.
bool isAllOnesValue() const {
  if (isSingleWord())
    return U.VAL == WORDTYPE_MAX >> (APINT_BITS_PER_WORD - BitWidth);
  return countTrailingOnesSlowCase() == BitWidth;
}

/// Determine if all bits are clear
///
/// This checks to see if the value has all bits of the APInt are clear or
/// not.
bool isNullValue() const { return !*this; }

/// Determine if this is a value of 1.
///
/// This checks to see if the value of this APInt is one.
bool isOneValue() const {
  if (isSingleWord())
    return U.VAL == 1;
  return countLeadingZerosSlowCase() == BitWidth - 1;
}

/// Determine if this is the largest unsigned value.
///
/// This checks to see if the value of this APInt is the maximum unsigned
/// value for the APInt's bit width.
bool isMaxValue() const { return isAllOnesValue(); }

/// Determine if this is the largest signed value.
///
/// This checks to see if the value of this APInt is the maximum signed
/// value for the APInt's bit width.
bool isMaxSignedValue() const {
  if (isSingleWord())
    return U.VAL == ((WordType(1) << (BitWidth - 1)) - 1);
  return !isNegative() && countTrailingOnesSlowCase() == BitWidth - 1;
}

/// Determine if this is the smallest unsigned value.
///
/// This checks to see if the value of this APInt is the minimum unsigned
/// value for the APInt's bit width.
bool isMinValue() const { return isNullValue(); }

/// Determine if this is the smallest signed value.
///
/// This checks to see if the value of this APInt is the minimum signed
/// value for the APInt's bit width.
bool isMinSignedValue() const {
  if (isSingleWord())
    return U.VAL == (WordType(1) << (BitWidth - 1));
  return isNegative() && countTrailingZerosSlowCase() == BitWidth - 1;
}

/// Check if this APInt has an N-bits unsigned integer value.
bool isIntN(unsigned N) const {
  assert(N && "N == 0 ???")((N && "N == 0 ???") ? static_cast<void> (0) : __assert_fail
 ("N && \"N == 0 ???\"", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 450, __PRETTY_FUNCTION__));
  return getActiveBits() <= N;
}

/// Check if this APInt has an N-bits signed integer value.
bool isSignedIntN(unsigned N) const {
  assert(N && "N == 0 ???")((N && "N == 0 ???") ? static_cast<void> (0) : __assert_fail
 ("N && \"N == 0 ???\"", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 456, __PRETTY_FUNCTION__));
  return getMinSignedBits() <= N;
}

/// Check if this APInt's value is a power of two greater than zero.
///
/// \returns true if the argument APInt value is a power of two > 0.
bool isPowerOf2() const {
  if (isSingleWord())
    return isPowerOf2_64(U.VAL);
  return countPopulationSlowCase() == 1;
}

/// Check if the APInt's value is returned by getSignMask.
///
/// \returns true if this is the value returned by getSignMask.
bool isSignMask() const { return isMinSignedValue(); }

/// Convert APInt to a boolean value.
///
/// This converts the APInt to a boolean value as a test against zero.
bool getBoolValue() const { return !!*this; }

/// If this value is smaller than the specified limit, return it, otherwise
/// return the limit value.  This causes the value to saturate to the limit.
uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) const {
  return ugt(Limit) ? Limit : getZExtValue();
}

/// Check if the APInt consists of a repeated bit pattern.
///
/// e.g. 0x01010101 satisfies isSplat(8).
/// \param SplatSizeInBits The size of the pattern in bits. Must divide bit
/// width without remainder.
bool isSplat(unsigned SplatSizeInBits) const;

/// \returns true if this APInt value is a sequence of \param numBits ones
/// starting at the least significant bit with the remainder zero.
bool isMask(unsigned numBits) const {
  assert(numBits != 0 && "numBits must be non-zero")((numBits != 0 && "numBits must be non-zero") ? static_cast
<void> (0) : __assert_fail ("numBits != 0 && \"numBits must be non-zero\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 495, __PRETTY_FUNCTION__));
  assert(numBits <= BitWidth && "numBits out of range")((numBits <= BitWidth && "numBits out of range") ?
 static_cast<void> (0) : __assert_fail ("numBits <= BitWidth && \"numBits out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 496, __PRETTY_FUNCTION__));
  if (isSingleWord())
    return U.VAL == (WORDTYPE_MAX >> (APINT_BITS_PER_WORD - numBits));
  unsigned Ones = countTrailingOnesSlowCase();
  return (numBits == Ones) &&
         ((Ones + countLeadingZerosSlowCase()) == BitWidth);
}

/// \returns true if this APInt is a non-empty sequence of ones starting at
/// the least significant bit with the remainder zero.
/// Ex. isMask(0x0000FFFFU) == true.
bool isMask() const {
  if (isSingleWord())
    return isMask_64(U.VAL);
  unsigned Ones = countTrailingOnesSlowCase();
  return (Ones > 0) && ((Ones + countLeadingZerosSlowCase()) == BitWidth);
}

/// Return true if this APInt value contains a sequence of ones with
/// the remainder zero.
bool isShiftedMask() const {
  if (isSingleWord())
    return isShiftedMask_64(U.VAL);
  unsigned Ones = countPopulationSlowCase();
  unsigned LeadZ = countLeadingZerosSlowCase();
  return (Ones + LeadZ + countTrailingZeros()) == BitWidth;
}

/// @}
/// \name Value Generators
/// @{

/// Gets maximum unsigned value of APInt for specific bit width.
static APInt getMaxValue(unsigned numBits) {
  return getAllOnesValue(numBits);
}

/// Gets maximum signed value of APInt for a specific bit width.
static APInt getSignedMaxValue(unsigned numBits) {
  APInt API = getAllOnesValue(numBits);
  API.clearBit(numBits - 1);
  return API;
}

/// Gets minimum unsigned value of APInt for a specific bit width.
static APInt getMinValue(unsigned numBits) { return APInt(numBits, 0); }

/// Gets minimum signed value of APInt for a specific bit width.
static APInt getSignedMinValue(unsigned numBits) {
  APInt API(numBits, 0);
  API.setBit(numBits - 1);
  return API;
}

/// Get the SignMask for a specific bit width.
///
/// This is just a wrapper function of getSignedMinValue(), and it helps code
/// readability when we want to get a SignMask.
static APInt getSignMask(unsigned BitWidth) {
  return getSignedMinValue(BitWidth);
}

/// Get the all-ones value.
///
/// \returns the all-ones value for an APInt of the specified bit-width.
static APInt getAllOnesValue(unsigned numBits) {
  return APInt(numBits, WORDTYPE_MAX, true);
}

/// Get the '0' value.
///
/// \returns the '0' value for an APInt of the specified bit-width.
static APInt getNullValue(unsigned numBits) { return APInt(numBits, 0); }

/// Compute an APInt containing numBits highbits from this APInt.
///
/// Get an APInt with the same BitWidth as this APInt, just zero mask
/// the low bits and right shift to the least significant bit.
///
/// \returns the high "numBits" bits of this APInt.
APInt getHiBits(unsigned numBits) const;

/// Compute an APInt containing numBits lowbits from this APInt.
///
/// Get an APInt with the same BitWidth as this APInt, just zero mask
/// the high bits.
///
/// \returns the low "numBits" bits of this APInt.
APInt getLoBits(unsigned numBits) const;

/// Return an APInt with exactly one bit set in the result.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo) {
  APInt Res(numBits, 0);
  Res.setBit(BitNo);
  return Res;
}

/// Get a value with a block of bits set.
///
/// Constructs an APInt value that has a contiguous range of bits set. The
/// bits from loBit (inclusive) to hiBit (exclusive) will be set. All other
/// bits will be zero. For example, with parameters(32, 0, 16) you would get
/// 0x0000FFFF. If hiBit is less than loBit then the set bits "wrap". For
/// example, with parameters (32, 28, 4), you would get 0xF000000F.
///
/// \param numBits the intended bit width of the result
/// \param loBit the index of the lowest bit set.
/// \param hiBit the index of the highest bit set.
///
/// \returns An APInt value with the requested bits set.
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit) {
  APInt Res(numBits, 0);
  Res.setBits(loBit, hiBit);
  return Res;
}

/// Get a value with upper bits starting at loBit set.
///
/// Constructs an APInt value that has a contiguous range of bits set. The
/// bits from loBit (inclusive) to numBits (exclusive) will be set. All other
/// bits will be zero. For example, with parameters(32, 12) you would get
/// 0xFFFFF000.
///
/// \param numBits the intended bit width of the result
/// \param loBit the index of the lowest bit to set.
///
/// \returns An APInt value with the requested bits set.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit) {
  APInt Res(numBits, 0);
  Res.setBitsFrom(loBit);
  return Res;
}

/// Get a value with high bits set
///
/// Constructs an APInt value that has the top hiBitsSet bits set.
///
/// \param numBits the bitwidth of the result
/// \param hiBitsSet the number of high-order bits set in the result.
static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet) {
  APInt Res(numBits, 0);
  Res.setHighBits(hiBitsSet);
  return Res;
}

/// Get a value with low bits set
///
/// Constructs an APInt value that has the bottom loBitsSet bits set.
///
/// \param numBits the bitwidth of the result
/// \param loBitsSet the number of low-order bits set in the result.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {
  APInt Res(numBits, 0);
  Res.setLowBits(loBitsSet);
  return Res;
}

/// Return a value containing V broadcasted over NewLen bits.
static APInt getSplat(unsigned NewLen, const APInt &V);

/// Determine if two APInts have the same value, after zero-extending
/// one of them (if needed!) to ensure that the bit-widths match.
static bool isSameValue(const APInt &I1, const APInt &I2) {
  if (I1.getBitWidth() == I2.getBitWidth())
    return I1 == I2;

  if (I1.getBitWidth() > I2.getBitWidth())
    return I1 == I2.zext(I1.getBitWidth());

  return I1.zext(I2.getBitWidth()) == I2;
}

/// Overload to compute a hash_code for an APInt value.
friend hash_code hash_value(const APInt &Arg);

/// This function returns a pointer to the internal storage of the APInt.
/// This is useful for writing out the APInt in binary form without any
/// conversions.
const uint64_t *getRawData() const {
  if (isSingleWord())
    return &U.VAL;
  return &U.pVal[0];
}

/// @}
/// \name Unary Operators
/// @{

/// Postfix increment operator.
///
/// Increments *this by 1.
///
/// \returns a new APInt value representing the original value of *this.
const APInt operator++(int) {
  APInt API(*this);
  ++(*this);
  return API;
}

/// Prefix increment operator.
///
/// \returns *this incremented by one
APInt &operator++();

/// Postfix decrement operator.
///
/// Decrements *this by 1.
///
/// \returns a new APInt value representing the original value of *this.
const APInt operator--(int) {
  APInt API(*this);
  --(*this);
  return API;
}

/// Prefix decrement operator.
///
/// \returns *this decremented by one.
APInt &operator--();

/// Logical negation operator.
///
/// Performs logical negation operation on this APInt.
///
/// \returns true if *this is zero, false otherwise.
bool operator!() const {
  if (isSingleWord())
    return U.VAL == 0;
  return countLeadingZerosSlowCase() == BitWidth;
}

/// @}
/// \name Assignment Operators
/// @{

/// Copy assignment operator.
///
/// \returns *this after assignment of RHS.
APInt &operator=(const APInt &RHS) {
  // If the bitwidths are the same, we can avoid mucking with memory
  if (isSingleWord() && RHS.isSingleWord()) {
    U.VAL = RHS.U.VAL;
    BitWidth = RHS.BitWidth;
    return clearUnusedBits();
  }

  AssignSlowCase(RHS);
  return *this;
}

/// Move assignment operator.
APInt &operator=(APInt &&that) {
748#ifdef _MSC_VER
  // The MSVC std::shuffle implementation still does self-assignment.
  if (this == &that)
    return *this;
752#endif
  assert(this != &that && "Self-move not supported")((this != &that && "Self-move not supported") ? static_cast
<void> (0) : __assert_fail ("this != &that && \"Self-move not supported\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 753, __PRETTY_FUNCTION__));
  if (!isSingleWord())
    delete[] U.pVal;

  // Use memcpy so that type based alias analysis sees both VAL and pVal
  // as modified.
  memcpy(&U, &that.U, sizeof(U));

  BitWidth = that.BitWidth;
  that.BitWidth = 0;

  return *this;
}

/// Assignment operator.
///
/// The RHS value is assigned to *this. If the significant bits in RHS exceed
/// the bit width, the excess bits are truncated. If the bit width is larger
/// than 64, the value is zero filled in the unspecified high order bits.
///
/// \returns *this after assignment of RHS value.
APInt &operator=(uint64_t RHS) {
  if (isSingleWord()) {
    U.VAL = RHS;
    clearUnusedBits();
  } else {
    U.pVal[0] = RHS;
    memset(U.pVal+1, 0, (getNumWords() - 1) * APINT_WORD_SIZE);
  }
  return *this;
}

/// Bitwise AND assignment operator.
///
/// Performs a bitwise AND operation on this APInt and RHS. The result is
/// assigned to *this.
///
/// \returns *this after ANDing with RHS.
APInt &operator&=(const APInt &RHS) {
  assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 792, __PRETTY_FUNCTION__));
  if (isSingleWord())
    U.VAL &= RHS.U.VAL;
  else
    AndAssignSlowCase(RHS);
  return *this;
}

/// Bitwise AND assignment operator.
///
/// Performs a bitwise AND operation on this APInt and RHS. RHS is
/// logically zero-extended or truncated to match the bit-width of
/// the LHS.
APInt &operator&=(uint64_t RHS) {
  if (isSingleWord()) {
    U.VAL &= RHS;
    return *this;
  }
  U.pVal[0] &= RHS;
  memset(U.pVal+1, 0, (getNumWords() - 1) * APINT_WORD_SIZE);
  return *this;
}

/// Bitwise OR assignment operator.
///
/// Performs a bitwise OR operation on this APInt and RHS. The result is
/// assigned *this;
///
/// \returns *this after ORing with RHS.
APInt &operator|=(const APInt &RHS) {
  assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 822, __PRETTY_FUNCTION__));
  if (isSingleWord())
    U.VAL |= RHS.U.VAL;
  else
    OrAssignSlowCase(RHS);
  return *this;
}

/// Bitwise OR assignment operator.
///
/// Performs a bitwise OR operation on this APInt and RHS. RHS is
/// logically zero-extended or truncated to match the bit-width of
/// the LHS.
APInt &operator|=(uint64_t RHS) {
  if (isSingleWord()) {
    U.VAL |= RHS;
    clearUnusedBits();
  } else {
    U.pVal[0] |= RHS;
  }
  return *this;
}

/// Bitwise XOR assignment operator.
///
/// Performs a bitwise XOR operation on this APInt and RHS. The result is
/// assigned to *this.
///
/// \returns *this after XORing with RHS.
APInt &operator^=(const APInt &RHS) {
  assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 852, __PRETTY_FUNCTION__));
  if (isSingleWord())
    U.VAL ^= RHS.U.VAL;
  else
    XorAssignSlowCase(RHS);
  return *this;
}

/// Bitwise XOR assignment operator.
///
/// Performs a bitwise XOR operation on this APInt and RHS. RHS is
/// logically zero-extended or truncated to match the bit-width of
/// the LHS.
APInt &operator^=(uint64_t RHS) {
  if (isSingleWord()) {
    U.VAL ^= RHS;
    clearUnusedBits();
  } else {
    U.pVal[0] ^= RHS;
  }
  return *this;
}

/// Multiplication assignment operator.
///
/// Multiplies this APInt by RHS and assigns the result to *this.
///
/// \returns *this
APInt &operator*=(const APInt &RHS);
APInt &operator*=(uint64_t RHS);

/// Addition assignment operator.
///
/// Adds RHS to *this and assigns the result to *this.
///
/// \returns *this
APInt &operator+=(const APInt &RHS);
APInt &operator+=(uint64_t RHS);

/// Subtraction assignment operator.
///
/// Subtracts RHS from *this and assigns the result to *this.
///
/// \returns *this
APInt &operator-=(const APInt &RHS);
APInt &operator-=(uint64_t RHS);

/// Left-shift assignment function.
///
/// Shifts *this left by shiftAmt and assigns the result to *this.
///
/// \returns *this after shifting left by ShiftAmt
APInt &operator<<=(unsigned ShiftAmt) {
  assert(ShiftAmt <= BitWidth && "Invalid shift amount")((ShiftAmt <= BitWidth && "Invalid shift amount") ?
 static_cast<void> (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 905, __PRETTY_FUNCTION__));
  if (isSingleWord()) {
    if (ShiftAmt == BitWidth)
      U.VAL = 0;
    else
      U.VAL <<= ShiftAmt;
    return clearUnusedBits();
  }
  shlSlowCase(ShiftAmt);
  return *this;
}

/// Left-shift assignment function.
///
/// Shifts *this left by shiftAmt and assigns the result to *this.
///
/// \returns *this after shifting left by ShiftAmt
APInt &operator<<=(const APInt &ShiftAmt);

/// @}
/// \name Binary Operators
/// @{

/// Multiplication operator.
///
/// Multiplies this APInt by RHS and returns the result.
APInt operator*(const APInt &RHS) const;

/// Left logical shift operator.
///
/// Shifts this APInt left by \p Bits and returns the result.
APInt operator<<(unsigned Bits) const { return shl(Bits); }

/// Left logical shift operator.
///
/// Shifts this APInt left by \p Bits and returns the result.
APInt operator<<(const APInt &Bits) const { return shl(Bits); }

/// Arithmetic right-shift function.
///
/// Arithmetic right-shift this APInt by shiftAmt.
APInt ashr(unsigned ShiftAmt) const {
  APInt R(*this);
  R.ashrInPlace(ShiftAmt);
  return R;
}

/// Arithmetic right-shift this APInt by ShiftAmt in place.
void ashrInPlace(unsigned ShiftAmt) {
  assert(ShiftAmt <= BitWidth && "Invalid shift amount")((ShiftAmt <= BitWidth && "Invalid shift amount") ?
 static_cast<void> (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 954, __PRETTY_FUNCTION__));
  if (isSingleWord()) {
    int64_t SExtVAL = SignExtend64(U.VAL, BitWidth);
    if (ShiftAmt == BitWidth)
      U.VAL = SExtVAL >> (APINT_BITS_PER_WORD - 1); // Fill with sign bit.
    else
      U.VAL = SExtVAL >> ShiftAmt;
    clearUnusedBits();
    return;
  }
  ashrSlowCase(ShiftAmt);
}

/// Logical right-shift function.
///
/// Logical right-shift this APInt by shiftAmt.
APInt lshr(unsigned shiftAmt) const {
  APInt R(*this);
  R.lshrInPlace(shiftAmt);
  return R;
}

/// Logical right-shift this APInt by ShiftAmt in place.
void lshrInPlace(unsigned ShiftAmt) {
  assert(ShiftAmt <= BitWidth && "Invalid shift amount")((ShiftAmt <= BitWidth && "Invalid shift amount") ?
 static_cast<void> (0) : __assert_fail ("ShiftAmt <= BitWidth && \"Invalid shift amount\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 978, __PRETTY_FUNCTION__));
  if (isSingleWord()) {
    if (ShiftAmt == BitWidth)
      U.VAL = 0;
    else
      U.VAL >>= ShiftAmt;
    return;
  }
  lshrSlowCase(ShiftAmt);
}

/// Left-shift function.
///
/// Left-shift this APInt by shiftAmt.
APInt shl(unsigned shiftAmt) const {
  APInt R(*this);
  R <<= shiftAmt;
  return R;
}

/// Rotate left by rotateAmt.
APInt rotl(unsigned rotateAmt) const;

/// Rotate right by rotateAmt.
APInt rotr(unsigned rotateAmt) const;

/// Arithmetic right-shift function.
///
/// Arithmetic right-shift this APInt by shiftAmt.
APInt ashr(const APInt &ShiftAmt) const {
  APInt R(*this);
  R.ashrInPlace(ShiftAmt);
  return R;
}

/// Arithmetic right-shift this APInt by shiftAmt in place.
void ashrInPlace(const APInt &shiftAmt);

/// Logical right-shift function.
///
/// Logical right-shift this APInt by shiftAmt.
APInt lshr(const APInt &ShiftAmt) const {
  APInt R(*this);
  R.lshrInPlace(ShiftAmt);
  return R;
}

/// Logical right-shift this APInt by ShiftAmt in place.
void lshrInPlace(const APInt &ShiftAmt);

/// Left-shift function.
///
/// Left-shift this APInt by shiftAmt.
APInt shl(const APInt &ShiftAmt) const {
  APInt R(*this);
  R <<= ShiftAmt;
  return R;
}

/// Rotate left by rotateAmt.
APInt rotl(const APInt &rotateAmt) const;

/// Rotate right by rotateAmt.
APInt rotr(const APInt &rotateAmt) const;

/// Unsigned division operation.
///
/// Perform an unsigned divide operation on this APInt by RHS. Both this and
/// RHS are treated as unsigned quantities for purposes of this division.
///
/// \returns a new APInt value containing the division result, rounded towards
/// zero.
APInt udiv(const APInt &RHS) const;
APInt udiv(uint64_t RHS) const;

/// Signed division function for APInt.
///
/// Signed divide this APInt by APInt RHS.
///
/// The result is rounded towards zero.
APInt sdiv(const APInt &RHS) const;
APInt sdiv(int64_t RHS) const;

/// Unsigned remainder operation.
///
/// Perform an unsigned remainder operation on this APInt with RHS being the
/// divisor. Both this and RHS are treated as unsigned quantities for purposes
/// of this operation. Note that this is a true remainder operation and not a
/// modulo operation because the sign follows the sign of the dividend which
/// is *this.
///
/// \returns a new APInt value containing the remainder result
APInt urem(const APInt &RHS) const;
uint64_t urem(uint64_t RHS) const;

/// Function for signed remainder operation.
///
/// Signed remainder operation on APInt.
APInt srem(const APInt &RHS) const;
int64_t srem(int64_t RHS) const;

/// Dual division/remainder interface.
///
/// Sometimes it is convenient to divide two APInt values and obtain both the
/// quotient and remainder. This function does both operations in the same
/// computation making it a little more efficient. The pair of input arguments
/// may overlap with the pair of output arguments. It is safe to call
/// udivrem(X, Y, X, Y), for example.
static void udivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient,
                    APInt &Remainder);
static void udivrem(const APInt &LHS, uint64_t RHS, APInt &Quotient,
                    uint64_t &Remainder);

static void sdivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient,
                    APInt &Remainder);
static void sdivrem(const APInt &LHS, int64_t RHS, APInt &Quotient,
                    int64_t &Remainder);

// Operations that return overflow indicators.
APInt sadd_ov(const APInt &RHS, bool &Overflow) const;
APInt uadd_ov(const APInt &RHS, bool &Overflow) const;
APInt ssub_ov(const APInt &RHS, bool &Overflow) const;
APInt usub_ov(const APInt &RHS, bool &Overflow) const;
APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;
APInt smul_ov(const APInt &RHS, bool &Overflow) const;
APInt umul_ov(const APInt &RHS, bool &Overflow) const;
APInt sshl_ov(const APInt &Amt, bool &Overflow) const;
APInt ushl_ov(const APInt &Amt, bool &Overflow) const;

// Operations that saturate
APInt sadd_sat(const APInt &RHS) const;
APInt uadd_sat(const APInt &RHS) const;
APInt ssub_sat(const APInt &RHS) const;
APInt usub_sat(const APInt &RHS) const;

/// Array-indexing support.
///
/// \returns the bit value at bitPosition
bool operator[](unsigned bitPosition) const {
  assert(bitPosition < getBitWidth() && "Bit position out of bounds!")((bitPosition < getBitWidth() && "Bit position out of bounds!"
) ? static_cast<void> (0) : __assert_fail ("bitPosition < getBitWidth() && \"Bit position out of bounds!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1117, __PRETTY_FUNCTION__));
  return (maskBit(bitPosition) & getWord(bitPosition)) != 0;
}

/// @}
/// \name Comparison Operators
/// @{

/// Equality operator.
///
/// Compares this APInt with RHS for the validity of the equality
/// relationship.
bool operator==(const APInt &RHS) const {
  assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit widths")((BitWidth == RHS.BitWidth && "Comparison requires equal bit widths"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Comparison requires equal bit widths\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1130, __PRETTY_FUNCTION__));
  if (isSingleWord())
    return U.VAL == RHS.U.VAL;
  return EqualSlowCase(RHS);
}

/// Equality operator.
///
/// Compares this APInt with a uint64_t for the validity of the equality
/// relationship.
///
/// \returns true if *this == Val
bool operator==(uint64_t Val) const {
  return (isSingleWord() || getActiveBits() <= 64) && getZExtValue() == Val;
}

/// Equality comparison.
///
/// Compares this APInt with RHS for the validity of the equality
/// relationship.
///
/// \returns true if *this == Val
bool eq(const APInt &RHS) const { return (*this) == RHS; }

/// Inequality operator.
///
/// Compares this APInt with RHS for the validity of the inequality
/// relationship.
///
/// \returns true if *this != Val
bool operator!=(const APInt &RHS) const { return !((*this) == RHS); }
63
←
Assuming the condition is false→
64
←
Returning zero, which participates in a condition later→

/// Inequality operator.
///
/// Compares this APInt with a uint64_t for the validity of the inequality
/// relationship.
///
/// \returns true if *this != Val
bool operator!=(uint64_t Val) const { return !((*this) == Val); }

/// Inequality comparison
///
/// Compares this APInt with RHS for the validity of the inequality
/// relationship.
///
/// \returns true if *this != Val
bool ne(const APInt &RHS) const { return !((*this) == RHS); }

/// Unsigned less than comparison
///
/// Regards both *this and RHS as unsigned quantities and compares them for
/// the validity of the less-than relationship.
///
/// \returns true if *this < RHS when both are considered unsigned.
bool ult(const APInt &RHS) const { return compare(RHS) < 0; }

/// Unsigned less than comparison
///
/// Regards both *this as an unsigned quantity and compares it with RHS for
/// the validity of the less-than relationship.
///
/// \returns true if *this < RHS when considered unsigned.
bool ult(uint64_t RHS) const {
  // Only need to check active bits if not a single word.
  return (isSingleWord() || getActiveBits() <= 64) && getZExtValue() < RHS;
}

/// Signed less than comparison
///
/// Regards both *this and RHS as signed quantities and compares them for
/// validity of the less-than relationship.
///
/// \returns true if *this < RHS when both are considered signed.
bool slt(const APInt &RHS) const { return compareSigned(RHS) < 0; }

/// Signed less than comparison
///
/// Regards both *this as a signed quantity and compares it with RHS for
/// the validity of the less-than relationship.
///
/// \returns true if *this < RHS when considered signed.
bool slt(int64_t RHS) const {
  return (!isSingleWord() && getMinSignedBits() > 64) ? isNegative()
                                                      : getSExtValue() < RHS;
}

/// Unsigned less or equal comparison
///
/// Regards both *this and RHS as unsigned quantities and compares them for
/// validity of the less-or-equal relationship.
///
/// \returns true if *this <= RHS when both are considered unsigned.
bool ule(const APInt &RHS) const { return compare(RHS) <= 0; }

/// Unsigned less or equal comparison
///
/// Regards both *this as an unsigned quantity and compares it with RHS for
/// the validity of the less-or-equal relationship.
///
/// \returns true if *this <= RHS when considered unsigned.
bool ule(uint64_t RHS) const { return !ugt(RHS); }

/// Signed less or equal comparison
///
/// Regards both *this and RHS as signed quantities and compares them for
/// validity of the less-or-equal relationship.
///
/// \returns true if *this <= RHS when both are considered signed.
bool sle(const APInt &RHS) const { return compareSigned(RHS) <= 0; }

/// Signed less or equal comparison
///
/// Regards both *this as a signed quantity and compares it with RHS for the
/// validity of the less-or-equal relationship.
///
/// \returns true if *this <= RHS when considered signed.
bool sle(uint64_t RHS) const { return !sgt(RHS); }

/// Unsigned greather than comparison
///
/// Regards both *this and RHS as unsigned quantities and compares them for
/// the validity of the greater-than relationship.
///
/// \returns true if *this > RHS when both are considered unsigned.
bool ugt(const APInt &RHS) const { return !ule(RHS); }

/// Unsigned greater than comparison
///
/// Regards both *this as an unsigned quantity and compares it with RHS for
/// the validity of the greater-than relationship.
///
/// \returns true if *this > RHS when considered unsigned.
bool ugt(uint64_t RHS) const {
  // Only need to check active bits if not a single word.
  return (!isSingleWord() && getActiveBits() > 64) || getZExtValue() > RHS;
}

/// Signed greather than comparison
///
/// Regards both *this and RHS as signed quantities and compares them for the
/// validity of the greater-than relationship.
///
/// \returns true if *this > RHS when both are considered signed.
bool sgt(const APInt &RHS) const { return !sle(RHS); }

/// Signed greater than comparison
///
/// Regards both *this as a signed quantity and compares it with RHS for
/// the validity of the greater-than relationship.
///
/// \returns true if *this > RHS when considered signed.
bool sgt(int64_t RHS) const {
  return (!isSingleWord() && getMinSignedBits() > 64) ? !isNegative()
                                                      : getSExtValue() > RHS;
}

/// Unsigned greater or equal comparison
///
/// Regards both *this and RHS as unsigned quantities and compares them for
/// validity of the greater-or-equal relationship.
///
/// \returns true if *this >= RHS when both are considered unsigned.
bool uge(const APInt &RHS) const { return !ult(RHS); }

/// Unsigned greater or equal comparison
///
/// Regards both *this as an unsigned quantity and compares it with RHS for
/// the validity of the greater-or-equal relationship.
///
/// \returns true if *this >= RHS when considered unsigned.
bool uge(uint64_t RHS) const { return !ult(RHS); }

/// Signed greater or equal comparison
///
/// Regards both *this and RHS as signed quantities and compares them for
/// validity of the greater-or-equal relationship.
///
/// \returns true if *this >= RHS when both are considered signed.
bool sge(const APInt &RHS) const { return !slt(RHS); }

/// Signed greater or equal comparison
///
/// Regards both *this as a signed quantity and compares it with RHS for
/// the validity of the greater-or-equal relationship.
///
/// \returns true if *this >= RHS when considered signed.
bool sge(int64_t RHS) const { return !slt(RHS); }

/// This operation tests if there are any pairs of corresponding bits
/// between this APInt and RHS that are both set.
bool intersects(const APInt &RHS) const {
  assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1321, __PRETTY_FUNCTION__));
  if (isSingleWord())
    return (U.VAL & RHS.U.VAL) != 0;
  return intersectsSlowCase(RHS);
}

/// This operation checks that all bits set in this APInt are also set in RHS.
bool isSubsetOf(const APInt &RHS) const {
  assert(BitWidth == RHS.BitWidth && "Bit widths must be the same")((BitWidth == RHS.BitWidth && "Bit widths must be the same"
) ? static_cast<void> (0) : __assert_fail ("BitWidth == RHS.BitWidth && \"Bit widths must be the same\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1329, __PRETTY_FUNCTION__));
  if (isSingleWord())
    return (U.VAL & ~RHS.U.VAL) == 0;
  return isSubsetOfSlowCase(RHS);
}

/// @}
/// \name Resizing Operators
/// @{

/// Truncate to new width.
///
/// Truncate the APInt to a specified width. It is an error to specify a width
/// that is greater than or equal to the current width.
APInt trunc(unsigned width) const;

/// Sign extend to a new width.
///
/// This operation sign extends the APInt to a new width. If the high order
/// bit is set, the fill on the left will be done with 1 bits, otherwise zero.
/// It is an error to specify a width that is less than or equal to the
/// current width.
APInt sext(unsigned width) const;

/// Zero extend to a new width.
///
/// This operation zero extends the APInt to a new width. The high order bits
/// are filled with 0 bits.  It is an error to specify a width that is less
/// than or equal to the current width.
APInt zext(unsigned width) const;

/// Sign extend or truncate to width
///
/// Make this APInt have the bit width given by \p width. The value is sign
/// extended, truncated, or left alone to make it that width.
APInt sextOrTrunc(unsigned width) const;

/// Zero extend or truncate to width
///
/// Make this APInt have the bit width given by \p width. The value is zero
/// extended, truncated, or left alone to make it that width.
APInt zextOrTrunc(unsigned width) const;

/// Sign extend or truncate to width
///
/// Make this APInt have the bit width given by \p width. The value is sign
/// extended, or left alone to make it that width.
APInt sextOrSelf(unsigned width) const;

/// Zero extend or truncate to width
///
/// Make this APInt have the bit width given by \p width. The value is zero
/// extended, or left alone to make it that width.
APInt zextOrSelf(unsigned width) const;

/// @}
/// \name Bit Manipulation Operators
/// @{

/// Set every bit to 1.
void setAllBits() {
  if (isSingleWord())
    U.VAL = WORDTYPE_MAX;
  else
    // Set all the bits in all the words.
    memset(U.pVal, -1, getNumWords() * APINT_WORD_SIZE);
  // Clear the unused ones
  clearUnusedBits();
}

/// Set a given bit to 1.
///
/// Set the given bit to 1 whose position is given as "bitPosition".
void setBit(unsigned BitPosition) {
  assert(BitPosition < BitWidth && "BitPosition out of range")((BitPosition < BitWidth && "BitPosition out of range"
) ? static_cast<void> (0) : __assert_fail ("BitPosition < BitWidth && \"BitPosition out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1403, __PRETTY_FUNCTION__));
  WordType Mask = maskBit(BitPosition);
  if (isSingleWord())
    U.VAL |= Mask;
  else
    U.pVal[whichWord(BitPosition)] |= Mask;
}

/// Set the sign bit to 1.
void setSignBit() {
  setBit(BitWidth - 1);
}

/// Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
void setBits(unsigned loBit, unsigned hiBit) {
  assert(hiBit <= BitWidth && "hiBit out of range")((hiBit <= BitWidth && "hiBit out of range") ? static_cast
<void> (0) : __assert_fail ("hiBit <= BitWidth && \"hiBit out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1418, __PRETTY_FUNCTION__));
  assert(loBit <= BitWidth && "loBit out of range")((loBit <= BitWidth && "loBit out of range") ? static_cast
<void> (0) : __assert_fail ("loBit <= BitWidth && \"loBit out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1419, __PRETTY_FUNCTION__));
  assert(loBit <= hiBit && "loBit greater than hiBit")((loBit <= hiBit && "loBit greater than hiBit") ? static_cast
<void> (0) : __assert_fail ("loBit <= hiBit && \"loBit greater than hiBit\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1420, __PRETTY_FUNCTION__));
  if (loBit == hiBit)
    return;
  if (loBit < APINT_BITS_PER_WORD && hiBit <= APINT_BITS_PER_WORD) {
    uint64_t mask = WORDTYPE_MAX >> (APINT_BITS_PER_WORD - (hiBit - loBit));
    mask <<= loBit;
    if (isSingleWord())
      U.VAL |= mask;
    else
      U.pVal[0] |= mask;
  } else {
    setBitsSlowCase(loBit, hiBit);
  }
}

/// Set the top bits starting from loBit.
void setBitsFrom(unsigned loBit) {
  return setBits(loBit, BitWidth);
}

/// Set the bottom loBits bits.
void setLowBits(unsigned loBits) {
  return setBits(0, loBits);
}

/// Set the top hiBits bits.
void setHighBits(unsigned hiBits) {
  return setBits(BitWidth - hiBits, BitWidth);
}

/// Set every bit to 0.
void clearAllBits() {
  if (isSingleWord())
    U.VAL = 0;
  else
    memset(U.pVal, 0, getNumWords() * APINT_WORD_SIZE);
}

/// Set a given bit to 0.
///
/// Set the given bit to 0 whose position is given as "bitPosition".
void clearBit(unsigned BitPosition) {
  assert(BitPosition < BitWidth && "BitPosition out of range")((BitPosition < BitWidth && "BitPosition out of range"
) ? static_cast<void> (0) : __assert_fail ("BitPosition < BitWidth && \"BitPosition out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1462, __PRETTY_FUNCTION__));
  WordType Mask = ~maskBit(BitPosition);
  if (isSingleWord())
    U.VAL &= Mask;
  else
    U.pVal[whichWord(BitPosition)] &= Mask;
}

/// Set bottom loBits bits to 0.
void clearLowBits(unsigned loBits) {
  assert(loBits <= BitWidth && "More bits than bitwidth")((loBits <= BitWidth && "More bits than bitwidth")
 ? static_cast<void> (0) : __assert_fail ("loBits <= BitWidth && \"More bits than bitwidth\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1472, __PRETTY_FUNCTION__));
  APInt Keep = getHighBitsSet(BitWidth, BitWidth - loBits);
  *this &= Keep;
}

/// Set the sign bit to 0.
void clearSignBit() {
  clearBit(BitWidth - 1);
}

/// Toggle every bit to its opposite value.
void flipAllBits() {
  if (isSingleWord()) {
    U.VAL ^= WORDTYPE_MAX;
    clearUnusedBits();
  } else {
    flipAllBitsSlowCase();
  }
}

/// Toggles a given bit to its opposite value.
///
/// Toggle a given bit to its opposite value whose position is given
/// as "bitPosition".
void flipBit(unsigned bitPosition);

/// Negate this APInt in place.
void negate() {
  flipAllBits();
  ++(*this);
}

/// Insert the bits from a smaller APInt starting at bitPosition.
void insertBits(const APInt &SubBits, unsigned bitPosition);
void insertBits(uint64_t SubBits, unsigned bitPosition, unsigned numBits);

/// Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
APInt extractBits(unsigned numBits, unsigned bitPosition) const;
uint64_t extractBitsAsZExtValue(unsigned numBits, unsigned bitPosition) const;

/// @}
/// \name Value Characterization Functions
/// @{

/// Return the number of bits in the APInt.
unsigned getBitWidth() const { return BitWidth; }

/// Get the number of words.
///
/// Here one word's bitwidth equals to that of uint64_t.
///
/// \returns the number of words to hold the integer value of this APInt.
unsigned getNumWords() const { return getNumWords(BitWidth); }

/// Get the number of words.
///
/// *NOTE* Here one word's bitwidth equals to that of uint64_t.
///
/// \returns the number of words to hold the integer value with a given bit
/// width.
static unsigned getNumWords(unsigned BitWidth) {
  return ((uint64_t)BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD;
}

/// Compute the number of active bits in the value
///
/// This function returns the number of active bits which is defined as the
/// bit width minus the number of leading zeros. This is used in several
/// computations to see how "wide" the value is.
unsigned getActiveBits() const { return BitWidth - countLeadingZeros(); }

/// Compute the number of active words in the value of this APInt.
///
/// This is used in conjunction with getActiveData to extract the raw value of
/// the APInt.
unsigned getActiveWords() const {
  unsigned numActiveBits = getActiveBits();
  return numActiveBits ? whichWord(numActiveBits - 1) + 1 : 1;
}

/// Get the minimum bit size for this signed APInt
///
/// Computes the minimum bit width for this APInt while considering it to be a
/// signed (and probably negative) value. If the value is not negative, this
/// function returns the same value as getActiveBits()+1. Otherwise, it
/// returns the smallest bit width that will retain the negative value. For
/// example, -1 can be written as 0b1 or 0xFFFFFFFFFF. 0b1 is shorter and so
/// for -1, this function will always return 1.
unsigned getMinSignedBits() const {
  if (isNegative())
    return BitWidth - countLeadingOnes() + 1;
  return getActiveBits() + 1;
}

/// Get zero extended value
///
/// This method attempts to return the value of this APInt as a zero extended
/// uint64_t. The bitwidth must be <= 64 or the value must fit within a
/// uint64_t. Otherwise an assertion will result.
uint64_t getZExtValue() const {
  if (isSingleWord())
    return U.VAL;
  assert(getActiveBits() <= 64 && "Too many bits for uint64_t")((getActiveBits() <= 64 && "Too many bits for uint64_t"
) ? static_cast<void> (0) : __assert_fail ("getActiveBits() <= 64 && \"Too many bits for uint64_t\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1574, __PRETTY_FUNCTION__));
  return U.pVal[0];
}

/// Get sign extended value
///
/// This method attempts to return the value of this APInt as a sign extended
/// int64_t. The bit width must be <= 64 or the value must fit within an
/// int64_t. Otherwise an assertion will result.
int64_t getSExtValue() const {
  if (isSingleWord())
    return SignExtend64(U.VAL, BitWidth);
  assert(getMinSignedBits() <= 64 && "Too many bits for int64_t")((getMinSignedBits() <= 64 && "Too many bits for int64_t"
) ? static_cast<void> (0) : __assert_fail ("getMinSignedBits() <= 64 && \"Too many bits for int64_t\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/ADT/APInt.h"
, 1586, __PRETTY_FUNCTION__));
  return int64_t(U.pVal[0]);
}

/// Get bits required for string value.
///
/// This method determines how many bits are required to hold the APInt
/// equivalent of the string given by \p str.
static unsigned getBitsNeeded(StringRef str, uint8_t radix);

/// The APInt version of the countLeadingZeros functions in
///   MathExtras.h.
///
/// It counts the number of zeros from the most significant bit to the first
/// one bit.
///
/// \returns BitWidth if the value is zero, otherwise returns the number of
///   zeros from the most significant bit to the first one bits.
unsigned countLeadingZeros() const {
  if (isSingleWord()) {
    unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth;
    return llvm::countLeadingZeros(U.VAL) - unusedBits;
  }
  return countLeadingZerosSlowCase();
}

/// Count the number of leading one bits.
///
/// This function is an APInt version of the countLeadingOnes
/// functions in MathExtras.h. It counts the number of ones from the most
/// significant bit to the first zero bit.
///
/// \returns 0 if the high order bit is not set, otherwise returns the number
/// of 1 bits from the most significant to the least
unsigned countLeadingOnes() const {
  if (isSingleWord())
    return llvm::countLeadingOnes(U.VAL << (APINT_BITS_PER_WORD - BitWidth));
  return countLeadingOnesSlowCase();
}

/// Computes the number of leading bits of this APInt that are equal to its
/// sign bit.
unsigned getNumSignBits() const {
  return isNegative() ? countLeadingOnes() : countLeadingZeros();
}

/// Count the number of trailing zero bits.
///
/// This function is an APInt version of the countTrailingZeros
/// functions in MathExtras.h. It counts the number of zeros from the least
/// significant bit to the first set bit.
///
/// \returns BitWidth if the value is zero, otherwise returns the number of
/// zeros from the least significant bit to the first one bit.
unsigned countTrailingZeros() const {
  if (isSingleWord())
    return std::min(unsigned(llvm::countTrailingZeros(U.VAL)), BitWidth);
  return countTrailingZerosSlowCase();
}

/// Count the number of trailing one bits.
///
/// This function is an APInt version of the countTrailingOnes
/// functions in MathExtras.h. It counts the number of ones from the least
/// significant bit to the first zero bit.
///
/// \returns BitWidth if the value is all ones, otherwise returns the number
/// of ones from the least significant bit to the first zero bit.
unsigned countTrailingOnes() const {
  if (isSingleWord())
    return llvm::countTrailingOnes(U.VAL);
  return countTrailingOnesSlowCase();
}

/// Count the number of bits set.
///
/// This function is an APInt version of the countPopulation functions
/// in MathExtras.h. It counts the number of 1 bits in the APInt value.
///
/// \returns 0 if the value is zero, otherwise returns the number of set bits.
unsigned countPopulation() const {
  if (isSingleWord())
    return llvm::countPopulation(U.VAL);
  return countPopulationSlowCase();
}

/// @}
/// \name Conversion Functions
/// @{
void print(raw_ostream &OS, bool isSigned) const;

/// Converts an APInt to a string and append it to Str.  Str is commonly a
/// SmallString.
void toString(SmallVectorImpl<char> &Str, unsigned Radix, bool Signed,
              bool formatAsCLiteral = false) const;

/// Considers the APInt to be unsigned and converts it into a string in the
/// radix given. The radix can be 2, 8, 10 16, or 36.
void toStringUnsigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
  toString(Str, Radix, false, false);
}

/// Considers the APInt to be signed and converts it into a string in the
/// radix given. The radix can be 2, 8, 10, 16, or 36.
void toStringSigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
  toString(Str, Radix, true, false);
}

/// Return the APInt as a std::string.
///
/// Note that this is an inefficient method.  It is better to pass in a
/// SmallVector/SmallString to the methods above to avoid thrashing the heap
/// for the string.
std::string toString(unsigned Radix, bool Signed) const;

/// \returns a byte-swapped representation of this APInt Value.
APInt byteSwap() const;

/// \returns the value with the bit representation reversed of this APInt
/// Value.
APInt reverseBits() const;

/// Converts this APInt to a double value.
double roundToDouble(bool isSigned) const;

/// Converts this unsigned APInt to a double value.
double roundToDouble() const { return roundToDouble(false); }

/// Converts this signed APInt to a double value.
double signedRoundToDouble() const { return roundToDouble(true); }

/// Converts APInt bits to a double
///
/// The conversion does not do a translation from integer to double, it just
/// re-interprets the bits as a double. Note that it is valid to do this on
/// any bit width. Exactly 64 bits will be translated.
double bitsToDouble() const {
  return BitsToDouble(getWord(0));
}

/// Converts APInt bits to a double
///
/// The conversion does not do a translation from integer to float, it just
/// re-interprets the bits as a float. Note that it is valid to do this on
/// any bit width. Exactly 32 bits will be translated.
float bitsToFloat() const {
  return BitsToFloat(getWord(0));
}

/// Converts a double to APInt bits.
///
/// The conversion does not do a translation from double to integer, it just
/// re-interprets the bits of the double.
static APInt doubleToBits(double V) {
  return APInt(sizeof(double) * CHAR_BIT8, DoubleToBits(V));
}

/// Converts a float to APInt bits.
///
/// The conversion does not do a translation from float to integer, it just
/// re-interprets the bits of the float.
static APInt floatToBits(float V) {
  return APInt(sizeof(float) * CHAR_BIT8, FloatToBits(V));
}

/// @}
/// \name Mathematics Operations
/// @{

/// \returns the floor log base 2 of this APInt.
unsigned logBase2() const { return getActiveBits() -  1; }

/// \returns the ceil log base 2 of this APInt.
unsigned ceilLogBase2() const {
  APInt temp(*this);
  --temp;
  return temp.getActiveBits();
}

/// \returns the nearest log base 2 of this APInt. Ties round up.
///
/// NOTE: When we have a BitWidth of 1, we define:
///
///   log2(0) = UINT32_MAX
///   log2(1) = 0
///
/// to get around any mathematical concerns resulting from
/// referencing 2 in a space where 2 does no exist.
unsigned nearestLogBase2() const {
  // Special case when we have a bitwidth of 1. If VAL is 1, then we
  // get 0. If VAL is 0, we get WORDTYPE_MAX which gets truncated to
  // UINT32_MAX.
  if (BitWidth == 1)
    return U.VAL - 1;

  // Handle the zero case.
  if (isNullValue())
    return UINT32_MAX(4294967295U);

  // The non-zero case is handled by computing:
  //
  //   nearestLogBase2(x) = logBase2(x) + x[logBase2(x)-1].
  //
  // where x[i] is referring to the value of the ith bit of x.
  unsigned lg = logBase2();
  return lg + unsigned((*this)[lg - 1]);
}

/// \returns the log base 2 of this APInt if its an exact power of two, -1
/// otherwise
int32_t exactLogBase2() const {
  if (!isPowerOf2())
    return -1;
  return logBase2();
}

/// Compute the square root
APInt sqrt() const;

/// Get the absolute value;
///
/// If *this is < 0 then return -(*this), otherwise *this;
APInt abs() const {
  if (isNegative())
    return -(*this);
  return *this;
}

/// \returns the multiplicative inverse for a given modulo.
APInt multiplicativeInverse(const APInt &modulo) const;

/// @}
/// \name Support for division by constant
/// @{

/// Calculate the magic number for signed division by a constant.
struct ms;
ms magic() const;

/// Calculate the magic number for unsigned division by a constant.
struct mu;
mu magicu(unsigned LeadingZeros = 0) const;

/// @}
/// \name Building-block Operations for APInt and APFloat
/// @{

// These building block operations operate on a representation of arbitrary
// precision, two's-complement, bignum integer values. They should be
// sufficient to implement APInt and APFloat bignum requirements. Inputs are
// generally a pointer to the base of an array of integer parts, representing
// an unsigned bignum, and a count of how many parts there are.

/// Sets the least significant part of a bignum to the input value, and zeroes
/// out higher parts.
static void tcSet(WordType *, WordType, unsigned);

/// Assign one bignum to another.
static void tcAssign(WordType *, const WordType *, unsigned);

/// Returns true if a bignum is zero, false otherwise.
static bool tcIsZero(const WordType *, unsigned);

/// Extract the given bit of a bignum; returns 0 or 1.  Zero-based.
static int tcExtractBit(const WordType *, unsigned bit);

/// Copy the bit vector of width srcBITS from SRC, starting at bit srcLSB, to
/// DST, of dstCOUNT parts, such that the bit srcLSB becomes the least
/// significant bit of DST.  All high bits above srcBITS in DST are
/// zero-filled.
static void tcExtract(WordType *, unsigned dstCount,
                      const WordType *, unsigned srcBits,
                      unsigned srcLSB);

/// Set the given bit of a bignum.  Zero-based.
static void tcSetBit(WordType *, unsigned bit);

/// Clear the given bit of a bignum.  Zero-based.
static void tcClearBit(WordType *, unsigned bit);

/// Returns the bit number of the least or most significant set bit of a
/// number.  If the input number has no bits set -1U is returned.
static unsigned tcLSB(const WordType *, unsigned n);
static unsigned tcMSB(const WordType *parts, unsigned n);

/// Negate a bignum in-place.
static void tcNegate(WordType *, unsigned);

/// DST += RHS + CARRY where CARRY is zero or one.  Returns the carry flag.
static WordType tcAdd(WordType *, const WordType *,
                      WordType carry, unsigned);
/// DST += RHS.  Returns the carry flag.
static WordType tcAddPart(WordType *, WordType, unsigned);

/// DST -= RHS + CARRY where CARRY is zero or one. Returns the carry flag.
static WordType tcSubtract(WordType *, const WordType *,
                           WordType carry, unsigned);
/// DST -= RHS.  Returns the carry flag.
static WordType tcSubtractPart(WordType *, WordType, unsigned);

/// DST += SRC * MULTIPLIER + PART   if add is true
/// DST  = SRC * MULTIPLIER + PART   if add is false
///
/// Requires 0 <= DSTPARTS <= SRCPARTS + 1.  If DST overlaps SRC they must
/// start at the same point, i.e. DST == SRC.
///
/// If DSTPARTS == SRC_PARTS + 1 no overflow occurs and zero is returned.
/// Otherwise DST is filled with the least significant DSTPARTS parts of the
/// result, and if all of the omitted higher parts were zero return zero,
/// otherwise overflow occurred and return one.
static int tcMultiplyPart(WordType *dst, const WordType *src,
                          WordType multiplier, WordType carry,
                          unsigned srcParts, unsigned dstParts,
                          bool add);

/// DST = LHS * RHS, where DST has the same width as the operands and is
/// filled with the least significant parts of the result.  Returns one if
/// overflow occurred, otherwise zero.  DST must be disjoint from both
/// operands.
static int tcMultiply(WordType *, const WordType *, const WordType *,
                      unsigned);

/// DST = LHS * RHS, where DST has width the sum of the widths of the
/// operands. No overflow occurs. DST must be disjoint from both operands.
static void tcFullMultiply(WordType *, const WordType *,
                           const WordType *, unsigned, unsigned);

/// If RHS is zero LHS and REMAINDER are left unchanged, return one.
/// Otherwise set LHS to LHS / RHS with the fractional part discarded, set
/// REMAINDER to the remainder, return zero.  i.e.
///
///  OLD_LHS = RHS * LHS + REMAINDER
///
/// SCRATCH is a bignum of the same size as the operands and result for use by
/// the routine; its contents need not be initialized and are destroyed.  LHS,
/// REMAINDER and SCRATCH must be distinct.
static int tcDivide(WordType *lhs, const WordType *rhs,
                    WordType *remainder, WordType *scratch,
                    unsigned parts);

/// Shift a bignum left Count bits. Shifted in bits are zero. There are no
/// restrictions on Count.
static void tcShiftLeft(WordType *, unsigned Words, unsigned Count);

/// Shift a bignum right Count bits.  Shifted in bits are zero.  There are no
/// restrictions on Count.
static void tcShiftRight(WordType *, unsigned Words, unsigned Count);

/// The obvious AND, OR and XOR and complement operations.
static void tcAnd(WordType *, const WordType *, unsigned);
static void tcOr(WordType *, const WordType *, unsigned);
static void tcXor(WordType *, const WordType *, unsigned);
static void tcComplement(WordType *, unsigned);

/// Comparison (unsigned) of two bignums.
static int tcCompare(const WordType *, const WordType *, unsigned);

/// Increment a bignum in-place.  Return the carry flag.
static WordType tcIncrement(WordType *dst, unsigned parts) {
  return tcAddPart(dst, 1, parts);
}

/// Decrement a bignum in-place.  Return the borrow flag.
static WordType tcDecrement(WordType *dst, unsigned parts) {
  return tcSubtractPart(dst, 1, parts);
}

/// Set the least significant BITS and clear the rest.
static void tcSetLeastSignificantBits(WordType *, unsigned, unsigned bits);

/// debug method
void dump() const;

/// @}
1960};

1962/// Magic data for optimising signed division by a constant.
1963struct APInt::ms {
APInt m;    ///< magic number
unsigned s; ///< shift amount
1966};

1968/// Magic data for optimising unsigned division by a constant.
1969struct APInt::mu {
APInt m;    ///< magic number
bool a;     ///< add indicator
unsigned s; ///< shift amount
1973};

1975inline bool operator==(uint64_t V1, const APInt &V2) { return V2 == V1; }

1977inline bool operator!=(uint64_t V1, const APInt &V2) { return V2 != V1; }

1979/// Unary bitwise complement operator.
1980///
1981/// \returns an APInt that is the bitwise complement of \p v.
1982inline APInt operator~(APInt v) {
v.flipAllBits();
return v;
1985}

1987inline APInt operator&(APInt a, const APInt &b) {
a &= b;
return a;
1990}

1992inline APInt operator&(const APInt &a, APInt &&b) {
b &= a;
return std::move(b);
1995}

1997inline APInt operator&(APInt a, uint64_t RHS) {
a &= RHS;
return a;
2000}

2002inline APInt operator&(uint64_t LHS, APInt b) {
b &= LHS;
return b;
2005}

2007inline APInt operator|(APInt a, const APInt &b) {
a |= b;
return a;
2010}

2012inline APInt operator|(const APInt &a, APInt &&b) {
b |= a;
return std::move(b);
2015}

2017inline APInt operator|(APInt a, uint64_t RHS) {
a |= RHS;
return a;
2020}

2022inline APInt operator|(uint64_t LHS, APInt b) {
b |= LHS;
return b;
2025}

2027inline APInt operator^(APInt a, const APInt &b) {
a ^= b;
return a;
2030}

2032inline APInt operator^(const APInt &a, APInt &&b) {
b ^= a;
return std::move(b);
2035}

2037inline APInt operator^(APInt a, uint64_t RHS) {
a ^= RHS;
return a;
2040}

2042inline APInt operator^(uint64_t LHS, APInt b) {
b ^= LHS;
return b;
2045}

2047inline raw_ostream &operator<<(raw_ostream &OS, const APInt &I) {
I.print(OS, true);
return OS;
2050}

2052inline APInt operator-(APInt v) {
v.negate();
return v;
2055}

2057inline APInt operator+(APInt a, const APInt &b) {
a += b;
return a;
2060}

2062inline APInt operator+(const APInt &a, APInt &&b) {
b += a;
return std::move(b);
2065}

2067inline APInt operator+(APInt a, uint64_t RHS) {
a += RHS;
return a;
2070}

2072inline APInt operator+(uint64_t LHS, APInt b) {
b += LHS;
return b;
2075}

2077inline APInt operator-(APInt a, const APInt &b) {
a -= b;
return a;
2080}

2082inline APInt operator-(const APInt &a, APInt &&b) {
b.negate();
b += a;
return std::move(b);
2086}

2088inline APInt operator-(APInt a, uint64_t RHS) {
a -= RHS;
return a;
2091}

2093inline APInt operator-(uint64_t LHS, APInt b) {
b.negate();
b += LHS;
return b;
2097}

2099inline APInt operator*(APInt a, uint64_t RHS) {
a *= RHS;
return a;
2102}

2104inline APInt operator*(uint64_t LHS, APInt b) {
b *= LHS;
return b;
2107}


2110namespace APIntOps {

2112/// Determine the smaller of two APInts considered to be signed.
2113inline const APInt &smin(const APInt &A, const APInt &B) {
return A.slt(B) ? A : B;
2115}

2117/// Determine the larger of two APInts considered to be signed.
2118inline const APInt &smax(const APInt &A, const APInt &B) {
return A.sgt(B) ? A : B;
2120}

2122/// Determine the smaller of two APInts considered to be signed.
2123inline const APInt &umin(const APInt &A, const APInt &B) {
return A.ult(B) ? A : B;
2125}

2127/// Determine the larger of two APInts considered to be unsigned.
2128inline const APInt &umax(const APInt &A, const APInt &B) {
return A.ugt(B) ? A : B;
2130}

2132/// Compute GCD of two unsigned APInt values.
2133///
2134/// This function returns the greatest common divisor of the two APInt values
2135/// using Stein's algorithm.
2136///
2137/// \returns the greatest common divisor of A and B.
2138APInt GreatestCommonDivisor(APInt A, APInt B);

2140/// Converts the given APInt to a double value.
2141///
2142/// Treats the APInt as an unsigned value for conversion purposes.
2143inline double RoundAPIntToDouble(const APInt &APIVal) {
return APIVal.roundToDouble();
2145}

2147/// Converts the given APInt to a double value.
2148///
2149/// Treats the APInt as a signed value for conversion purposes.
2150inline double RoundSignedAPIntToDouble(const APInt &APIVal) {
return APIVal.signedRoundToDouble();
2152}

2154/// Converts the given APInt to a float vlalue.
2155inline float RoundAPIntToFloat(const APInt &APIVal) {
return float(RoundAPIntToDouble(APIVal));
2157}

2159/// Converts the given APInt to a float value.
2160///
2161/// Treast the APInt as a signed value for conversion purposes.
2162inline float RoundSignedAPIntToFloat(const APInt &APIVal) {
return float(APIVal.signedRoundToDouble());
2164}

2166/// Converts the given double value into a APInt.
2167///
2168/// This function convert a double value to an APInt value.
2169APInt RoundDoubleToAPInt(double Double, unsigned width);

2171/// Converts a float value into a APInt.
2172///
2173/// Converts a float value into an APInt value.
2174inline APInt RoundFloatToAPInt(float Float, unsigned width) {
return RoundDoubleToAPInt(double(Float), width);
2176}

2178/// Return A unsign-divided by B, rounded by the given rounding mode.
2179APInt RoundingUDiv(const APInt &A, const APInt &B, APInt::Rounding RM);

2181/// Return A sign-divided by B, rounded by the given rounding mode.
2182APInt RoundingSDiv(const APInt &A, const APInt &B, APInt::Rounding RM);

2184/// Let q(n) = An^2 + Bn + C, and BW = bit width of the value range
2185/// (e.g. 32 for i32).
2186/// This function finds the smallest number n, such that
2187/// (a) n >= 0 and q(n) = 0, or
2188/// (b) n >= 1 and q(n-1) and q(n), when evaluated in the set of all
2189///     integers, belong to two different intervals [Rk, Rk+R),
2190///     where R = 2^BW, and k is an integer.
2191/// The idea here is to find when q(n) "overflows" 2^BW, while at the
2192/// same time "allowing" subtraction. In unsigned modulo arithmetic a
2193/// subtraction (treated as addition of negated numbers) would always
2194/// count as an overflow, but here we want to allow values to decrease
2195/// and increase as long as they are within the same interval.
2196/// Specifically, adding of two negative numbers should not cause an
2197/// overflow (as long as the magnitude does not exceed the bith width).
2198/// On the other hand, given a positive number, adding a negative
2199/// number to it can give a negative result, which would cause the
2200/// value to go from [-2^BW, 0) to [0, 2^BW). In that sense, zero is
2201/// treated as a special case of an overflow.
2202///
2203/// This function returns None if after finding k that minimizes the
2204/// positive solution to q(n) = kR, both solutions are contained between
2205/// two consecutive integers.
2206///
2207/// There are cases where q(n) > T, and q(n+1) < T (assuming evaluation
2208/// in arithmetic modulo 2^BW, and treating the values as signed) by the
2209/// virtue of *signed* overflow. This function will *not* find such an n,
2210/// however it may find a value of n satisfying the inequalities due to
2211/// an *unsigned* overflow (if the values are treated as unsigned).
2212/// To find a solution for a signed overflow, treat it as a problem of
2213/// finding an unsigned overflow with a range with of BW-1.
2214///
2215/// The returned value may have a different bit width from the input
2216/// coefficients.
2217Optional<APInt> SolveQuadraticEquationWrap(APInt A, APInt B, APInt C,
                                         unsigned RangeWidth);
2219} // End of APIntOps namespace

2221// See friend declaration above. This additional declaration is required in
2222// order to compile LLVM with IBM xlC compiler.
2223hash_code hash_value(const APInt &Arg);

2225/// StoreIntToMemory - Fills the StoreBytes bytes of memory starting from Dst
2226/// with the integer held in IntVal.
2227void StoreIntToMemory(const APInt &IntVal, uint8_t *Dst, unsigned StoreBytes);

2229/// LoadIntFromMemory - Loads the integer stored in the LoadBytes bytes starting
2230/// from Src into IntVal, which is assumed to be wide enough and to hold zero.
2231void LoadIntFromMemory(APInt &IntVal, uint8_t *Src, unsigned LoadBytes);

2233} // namespace llvm

2235#endif

←

/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h

1//===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This file describes how to lower LLVM code to machine code.  This has two
11/// main components:
12///
13///  1. Which ValueTypes are natively supported by the target.
14///  2. Which operations are supported for supported ValueTypes.
15///  3. Cost thresholds for alternative implementations of certain operations.
16///
17/// In addition it has a few other components, like information about FP
18/// immediates.
19///
20//===----------------------------------------------------------------------===//

22#ifndef LLVM_CODEGEN_TARGETLOWERING_H
23#define LLVM_CODEGEN_TARGETLOWERING_H

25#include "llvm/ADT/APInt.h"
26#include "llvm/ADT/ArrayRef.h"
27#include "llvm/ADT/DenseMap.h"
28#include "llvm/ADT/STLExtras.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/StringRef.h"
31#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
32#include "llvm/CodeGen/DAGCombine.h"
33#include "llvm/CodeGen/ISDOpcodes.h"
34#include "llvm/CodeGen/RuntimeLibcalls.h"
35#include "llvm/CodeGen/SelectionDAG.h"
36#include "llvm/CodeGen/SelectionDAGNodes.h"
37#include "llvm/CodeGen/TargetCallingConv.h"
38#include "llvm/CodeGen/ValueTypes.h"
39#include "llvm/IR/Attributes.h"
40#include "llvm/IR/CallSite.h"
41#include "llvm/IR/CallingConv.h"
42#include "llvm/IR/DataLayout.h"
43#include "llvm/IR/DerivedTypes.h"
44#include "llvm/IR/Function.h"
45#include "llvm/IR/IRBuilder.h"
46#include "llvm/IR/InlineAsm.h"
47#include "llvm/IR/Instruction.h"
48#include "llvm/IR/Instructions.h"
49#include "llvm/IR/Type.h"
50#include "llvm/MC/MCRegisterInfo.h"
51#include "llvm/Support/Alignment.h"
52#include "llvm/Support/AtomicOrdering.h"
53#include "llvm/Support/Casting.h"
54#include "llvm/Support/ErrorHandling.h"
55#include "llvm/Support/MachineValueType.h"
56#include "llvm/Target/TargetMachine.h"
57#include <algorithm>
58#include <cassert>
59#include <climits>
60#include <cstdint>
61#include <iterator>
62#include <map>
63#include <string>
64#include <utility>
65#include <vector>

67namespace llvm {

69class BranchProbability;
70class CCState;
71class CCValAssign;
72class Constant;
73class FastISel;
74class FunctionLoweringInfo;
75class GlobalValue;
76class GISelKnownBits;
77class IntrinsicInst;
78struct KnownBits;
79class LLVMContext;
80class MachineBasicBlock;
81class MachineFunction;
82class MachineInstr;
83class MachineJumpTableInfo;
84class MachineLoop;
85class MachineRegisterInfo;
86class MCContext;
87class MCExpr;
88class Module;
89class TargetRegisterClass;
90class TargetLibraryInfo;
91class TargetRegisterInfo;
92class Value;

94namespace Sched {

enum Preference {
  None,             // No preference
  Source,           // Follow source order.
  RegPressure,      // Scheduling for lowest register pressure.
  Hybrid,           // Scheduling for both latency and register pressure.
  ILP,              // Scheduling for ILP in low register pressure mode.
  VLIW              // Scheduling for VLIW targets.
};

105} // end namespace Sched

107/// This base class for TargetLowering contains the SelectionDAG-independent
108/// parts that can be used from the rest of CodeGen.
109class TargetLoweringBase {
110public:
/// This enum indicates whether operations are valid for a target, and if not,
/// what action should be used to make them valid.
enum LegalizeAction : uint8_t {
  Legal,      // The target natively supports this operation.
  Promote,    // This operation should be executed in a larger type.
  Expand,     // Try to expand this to other ops, otherwise use a libcall.
  LibCall,    // Don't try to expand this to other ops, always use a libcall.
  Custom      // Use the LowerOperation hook to implement custom lowering.
};

/// This enum indicates whether a types are legal for a target, and if not,
/// what action should be used to make them valid.
enum LegalizeTypeAction : uint8_t {
  TypeLegal,           // The target natively supports this type.
  TypePromoteInteger,  // Replace this integer with a larger one.
  TypeExpandInteger,   // Split this integer into two of half the size.
  TypeSoftenFloat,     // Convert this float to a same size integer type.
  TypeExpandFloat,     // Split this float into two of half the size.
  TypeScalarizeVector, // Replace this one-element vector with its element.
  TypeSplitVector,     // Split this vector into two of half the size.
  TypeWidenVector,     // This vector should be widened into a larger vector.
  TypePromoteFloat     // Replace this float with a larger one.
};

/// LegalizeKind holds the legalization kind that needs to happen to EVT
/// in order to type-legalize it.
using LegalizeKind = std::pair<LegalizeTypeAction, EVT>;

/// Enum that describes how the target represents true/false values.
enum BooleanContent {
  UndefinedBooleanContent,    // Only bit 0 counts, the rest can hold garbage.
  ZeroOrOneBooleanContent,        // All bits zero except for bit 0.
  ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
};

/// Enum that describes what type of support for selects the target has.
enum SelectSupportKind {
  ScalarValSelect,      // The target supports scalar selects (ex: cmov).
  ScalarCondVectorVal,  // The target supports selects with a scalar condition
                        // and vector values (ex: cmov).
  VectorMaskSelect      // The target supports vector selects with a vector
                        // mask (ex: x86 blends).
};

/// Enum that specifies what an atomic load/AtomicRMWInst is expanded
/// to, if at all. Exists because different targets have different levels of
/// support for these atomic instructions, and also have different options
/// w.r.t. what they should expand to.
enum class AtomicExpansionKind {
  None,    // Don't expand the instruction.
  LLSC,    // Expand the instruction into loadlinked/storeconditional; used
           // by ARM/AArch64.
  LLOnly,  // Expand the (load) instruction into just a load-linked, which has
           // greater atomic guarantees than a normal load.
  CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
  MaskedIntrinsic, // Use a target-specific intrinsic for the LL/SC loop.
};

/// Enum that specifies when a multiplication should be expanded.
enum class MulExpansionKind {
  Always,            // Always expand the instruction.
  OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
                     // or custom.
};

class ArgListEntry {
public:
  Value *Val = nullptr;
  SDValue Node = SDValue();
  Type *Ty = nullptr;
  bool IsSExt : 1;
  bool IsZExt : 1;
  bool IsInReg : 1;
  bool IsSRet : 1;
  bool IsNest : 1;
  bool IsByVal : 1;
  bool IsInAlloca : 1;
  bool IsReturned : 1;
  bool IsSwiftSelf : 1;
  bool IsSwiftError : 1;
  uint16_t Alignment = 0;
  Type *ByValType = nullptr;

  ArgListEntry()
      : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
        IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
        IsSwiftSelf(false), IsSwiftError(false) {}

  void setAttributes(const CallBase *Call, unsigned ArgIdx);

  void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx) {
    return setAttributes(cast<CallBase>(CS->getInstruction()), ArgIdx);
  }
};
using ArgListTy = std::vector<ArgListEntry>;

virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
                                   ArgListTy &Args) const {};

static ISD::NodeType getExtendForContent(BooleanContent Content) {
  switch (Content) {
  case UndefinedBooleanContent:
    // Extend by adding rubbish bits.
    return ISD::ANY_EXTEND;
  case ZeroOrOneBooleanContent:
    // Extend by adding zero bits.
    return ISD::ZERO_EXTEND;
  case ZeroOrNegativeOneBooleanContent:
    // Extend by copying the sign bit.
    return ISD::SIGN_EXTEND;
  }
  llvm_unreachable("Invalid content kind")::llvm::llvm_unreachable_internal("Invalid content kind", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 222);
}

/// NOTE: The TargetMachine owns TLOF.
explicit TargetLoweringBase(const TargetMachine &TM);
TargetLoweringBase(const TargetLoweringBase &) = delete;
TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
virtual ~TargetLoweringBase() = default;

231protected:
/// Initialize all of the actions to default values.
void initActions();

235public:
const TargetMachine &getTargetMachine() const { return TM; }

virtual bool useSoftFloat() const { return false; }

/// Return the pointer type for the given address space, defaults to
/// the pointer type from the data layout.
/// FIXME: The default needs to be removed once all the code is updated.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
  return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
}

/// Return the in-memory pointer type for the given address space, defaults to
/// the pointer type from the data layout.  FIXME: The default needs to be
/// removed once all the code is updated.
MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const {
  return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
}

/// Return the type for frame index, which is determined by
/// the alloca address space specified through the data layout.
MVT getFrameIndexTy(const DataLayout &DL) const {
  return getPointerTy(DL, DL.getAllocaAddrSpace());
}

/// Return the type for operands of fence.
/// TODO: Let fence operands be of i32 type and remove this.
virtual MVT getFenceOperandTy(const DataLayout &DL) const {
  return getPointerTy(DL);
}

/// EVT is not used in-tree, but is used by out-of-tree target.
/// A documentation for this function would be nice...
virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;

EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL,
                     bool LegalTypes = true) const;

/// Returns the type to be used for the index operand of:
/// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
/// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
virtual MVT getVectorIdxTy(const DataLayout &DL) const {
  return getPointerTy(DL);
}

virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
  return true;
}

/// Return true if it is profitable to convert a select of FP constants into
/// a constant pool load whose address depends on the select condition. The
/// parameter may be used to differentiate a select with FP compare from
/// integer compare.
virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT) const {
  return true;
}

/// Return true if multiple condition registers are available.
bool hasMultipleConditionRegisters() const {
  return HasMultipleConditionRegisters;
}

/// Return true if the target has BitExtract instructions.
bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }

/// Return the preferred vector type legalization action.
virtual TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(MVT VT) const {
  // The default action for one element vectors is to scalarize
  if (VT.getVectorNumElements() == 1)
    return TypeScalarizeVector;
  // The default action for an odd-width vector is to widen.
  if (!VT.isPow2VectorType())
    return TypeWidenVector;
  // The default action for other vectors is to promote
  return TypePromoteInteger;
}

// There are two general methods for expanding a BUILD_VECTOR node:
//  1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
//     them together.
//  2. Build the vector on the stack and then load it.
// If this function returns true, then method (1) will be used, subject to
// the constraint that all of the necessary shuffles are legal (as determined
// by isShuffleMaskLegal). If this function returns false, then method (2) is
// always used. The vector type, and the number of defined values, are
// provided.
virtual bool
shouldExpandBuildVectorWithShuffles(EVT /* VT */,
                                    unsigned DefinedValues) const {
  return DefinedValues < 3;
}

/// Return true if integer divide is usually cheaper than a sequence of
/// several shifts, adds, and multiplies for this target.
/// The definition of "cheaper" may depend on whether we're optimizing
/// for speed or for size.
virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }

/// Return true if the target can handle a standalone remainder operation.
virtual bool hasStandaloneRem(EVT VT) const {
  return true;
}

/// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
  // Default behavior is to replace SQRT(X) with X*RSQRT(X).
  return false;
}

/// Reciprocal estimate status values used by the functions below.
enum ReciprocalEstimate : int {
  Unspecified = -1,
  Disabled = 0,
  Enabled = 1
};

/// Return a ReciprocalEstimate enum value for a square root of the given type
/// based on the function's attributes. If the operation is not overridden by
/// the function's attributes, "Unspecified" is returned and target defaults
/// are expected to be used for instruction selection.
int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;

/// Return a ReciprocalEstimate enum value for a division of the given type
/// based on the function's attributes. If the operation is not overridden by
/// the function's attributes, "Unspecified" is returned and target defaults
/// are expected to be used for instruction selection.
int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;

/// Return the refinement step count for a square root of the given type based
/// on the function's attributes. If the operation is not overridden by
/// the function's attributes, "Unspecified" is returned and target defaults
/// are expected to be used for instruction selection.
int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;

/// Return the refinement step count for a division of the given type based
/// on the function's attributes. If the operation is not overridden by
/// the function's attributes, "Unspecified" is returned and target defaults
/// are expected to be used for instruction selection.
int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;

/// Returns true if target has indicated at least one type should be bypassed.
bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }

/// Returns map of slow types for division or remainder with corresponding
/// fast types
const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
  return BypassSlowDivWidths;
}

/// Return true if Flow Control is an expensive operation that should be
/// avoided.
bool isJumpExpensive() const { return JumpIsExpensive; }

/// Return true if selects are only cheaper than branches if the branch is
/// unlikely to be predicted right.
bool isPredictableSelectExpensive() const {
  return PredictableSelectIsExpensive;
}

/// If a branch or a select condition is skewed in one direction by more than
/// this factor, it is very likely to be predicted correctly.
virtual BranchProbability getPredictableBranchThreshold() const;

/// Return true if the following transform is beneficial:
/// fold (conv (load x)) -> (load (conv*)x)
/// On architectures that don't natively support some vector loads
/// efficiently, casting the load to a smaller vector of larger types and
/// loading is more efficient, however, this can be undone by optimizations in
/// dag combiner.
virtual bool isLoadBitCastBeneficial(EVT LoadVT, EVT BitcastVT,
                                     const SelectionDAG &DAG,
                                     const MachineMemOperand &MMO) const {
  // Don't do if we could do an indexed load on the original type, but not on
  // the new one.
  if (!LoadVT.isSimple() || !BitcastVT.isSimple())
    return true;

  MVT LoadMVT = LoadVT.getSimpleVT();

  // Don't bother doing this if it's just going to be promoted again later, as
  // doing so might interfere with other combines.
  if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
      getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
    return false;

  bool Fast = false;
  return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT,
                            MMO, &Fast) && Fast;
}

/// Return true if the following transform is beneficial:
/// (store (y (conv x)), y*)) -> (store x, (x*))
virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT,
                                      const SelectionDAG &DAG,
                                      const MachineMemOperand &MMO) const {
  // Default to the same logic as loads.
  return isLoadBitCastBeneficial(StoreVT, BitcastVT, DAG, MMO);
}

/// Return true if it is expected to be cheaper to do a store of a non-zero
/// vector constant with the given size and type for the address space than to
/// store the individual scalar element constants.
virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
                                          unsigned NumElem,
                                          unsigned AddrSpace) const {
  return false;
}

/// Allow store merging for the specified type after legalization in addition
/// to before legalization. This may transform stores that do not exist
/// earlier (for example, stores created from intrinsics).
virtual bool mergeStoresAfterLegalization(EVT MemVT) const {
  return true;
}

/// Returns if it's reasonable to merge stores to MemVT size.
virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
                              const SelectionDAG &DAG) const {
  return true;
}

/// Return true if it is cheap to speculate a call to intrinsic cttz.
virtual bool isCheapToSpeculateCttz() const {
  return false;
}

/// Return true if it is cheap to speculate a call to intrinsic ctlz.
virtual bool isCheapToSpeculateCtlz() const {
  return false;
}

/// Return true if ctlz instruction is fast.
virtual bool isCtlzFast() const {
  return false;
}

/// Return true if it is safe to transform an integer-domain bitwise operation
/// into the equivalent floating-point operation. This should be set to true
/// if the target has IEEE-754-compliant fabs/fneg operations for the input
/// type.
virtual bool hasBitPreservingFPLogic(EVT VT) const {
  return false;
}

/// Return true if it is cheaper to split the store of a merged int val
/// from a pair of smaller values into multiple stores.
virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
  return false;
}

/// Return if the target supports combining a
/// chain like:
/// \code
///   %andResult = and %val1, #mask
///   %icmpResult = icmp %andResult, 0
/// \endcode
/// into a single machine instruction of a form like:
/// \code
///   cc = test %register, #mask
/// \endcode
virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
  return false;
}

/// Use bitwise logic to make pairs of compares more efficient. For example:
/// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
/// This should be true when it takes more than one instruction to lower
/// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
/// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
  return false;
}

/// Return the preferred operand type if the target has a quick way to compare
/// integer values of the given size. Assume that any legal integer type can
/// be compared efficiently. Targets may override this to allow illegal wide
/// types to return a vector type if there is support to compare that type.
virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
  MVT VT = MVT::getIntegerVT(NumBits);
  return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
}

/// Return true if the target should transform:
/// (X & Y) == Y ---> (~X & Y) == 0
/// (X & Y) != Y ---> (~X & Y) != 0
///
/// This may be profitable if the target has a bitwise and-not operation that
/// sets comparison flags. A target may want to limit the transformation based
/// on the type of Y or if Y is a constant.
///
/// Note that the transform will not occur if Y is known to be a power-of-2
/// because a mask and compare of a single bit can be handled by inverting the
/// predicate, for example:
/// (X & 8) == 8 ---> (X & 8) != 0
virtual bool hasAndNotCompare(SDValue Y) const {
  return false;
}

/// Return true if the target has a bitwise and-not operation:
/// X = ~A & B
/// This can be used to simplify select or other instructions.
virtual bool hasAndNot(SDValue X) const {
  // If the target has the more complex version of this operation, assume that
  // it has this operation too.
  return hasAndNotCompare(X);
}

/// Return true if the target has a bit-test instruction:
///   (X & (1 << Y)) ==/!= 0
/// This knowledge can be used to prevent breaking the pattern,
/// or creating it if it could be recognized.
virtual bool hasBitTest(SDValue X, SDValue Y) const { return false; }

/// There are two ways to clear extreme bits (either low or high):
/// Mask:    x &  (-1 << y)  (the instcombine canonical form)
/// Shifts:  x >> y << y
/// Return true if the variant with 2 variable shifts is preferred.
/// Return false if there is no preference.
virtual bool shouldFoldMaskToVariableShiftPair(SDValue X) const {
  // By default, let's assume that no one prefers shifts.
  return false;
}

/// Return true if it is profitable to fold a pair of shifts into a mask.
/// This is usually true on most targets. But some targets, like Thumb1,
/// have immediate shift instructions, but no immediate "and" instruction;
/// this makes the fold unprofitable.
virtual bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                               CombineLevel Level) const {
  return true;
}

/// Should we tranform the IR-optimal check for whether given truncation
/// down into KeptBits would be truncating or not:
///   (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
/// Into it's more traditional form:
///   ((%x << C) a>> C) dstcond %x
/// Return true if we should transform.
/// Return false if there is no preference.
virtual bool shouldTransformSignedTruncationCheck(EVT XVT,
                                                  unsigned KeptBits) const {
  // By default, let's assume that no one prefers shifts.
  return false;
}

/// Given the pattern
///   (X & (C l>>/<< Y)) ==/!= 0
/// return true if it should be transformed into:
///   ((X <</l>> Y) & C) ==/!= 0
/// WARNING: if 'X' is a constant, the fold may deadlock!
/// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
///        here because it can end up being not linked in.
virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
    SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y,
    unsigned OldShiftOpcode, unsigned NewShiftOpcode,
    SelectionDAG &DAG) const {
  if (hasBitTest(X, Y)) {
    // One interesting pattern that we'd want to form is 'bit test':
    //   ((1 << Y) & C) ==/!= 0
    // But we also need to be careful not to try to reverse that fold.

    // Is this '1 << Y' ?
    if (OldShiftOpcode == ISD::SHL && CC->isOne())
      return false; // Keep the 'bit test' pattern.

    // Will it be '1 << Y' after the transform ?
    if (XC && NewShiftOpcode == ISD::SHL && XC->isOne())
      return true; // Do form the 'bit test' pattern.
  }

  // If 'X' is a constant, and we transform, then we will immediately
  // try to undo the fold, thus causing endless combine loop.
  // So by default, let's assume everyone prefers the fold
  // iff 'X' is not a constant.
  return !XC;
}

/// These two forms are equivalent:
///   sub %y, (xor %x, -1)
///   add (add %x, 1), %y
/// The variant with two add's is IR-canonical.
/// Some targets may prefer one to the other.
virtual bool preferIncOfAddToSubOfNot(EVT VT) const {
  // By default, let's assume that everyone prefers the form with two add's.
  return true;
}

/// Return true if the target wants to use the optimization that
/// turns ext(promotableInst1(...(promotableInstN(load)))) into
/// promotedInst1(...(promotedInstN(ext(load)))).
bool enableExtLdPromotion() const { return EnableExtLdPromotion; }

/// Return true if the target can combine store(extractelement VectorTy,
/// Idx).
/// \p Cost[out] gives the cost of that transformation when this is true.
virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
                                       unsigned &Cost) const {
  return false;
}

/// Return true if inserting a scalar into a variable element of an undef
/// vector is more efficiently handled by splatting the scalar instead.
virtual bool shouldSplatInsEltVarIndex(EVT) const {
  return false;
}

/// Return true if target always beneficiates from combining into FMA for a
/// given value type. This must typically return false on targets where FMA
/// takes more cycles to execute than FADD.
virtual bool enableAggressiveFMAFusion(EVT VT) const {
  return false;
}

/// Return the ValueType of the result of SETCC operations.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                               EVT VT) const;

/// Return the ValueType for comparison libcalls. Comparions libcalls include
/// floating point comparion calls, and Ordered/Unordered check calls on
/// floating point numbers.
virtual
MVT::SimpleValueType getCmpLibcallReturnType() const;

/// For targets without i1 registers, this gives the nature of the high-bits
/// of boolean values held in types wider than i1.
///
/// "Boolean values" are special true/false values produced by nodes like
/// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
/// Not to be confused with general values promoted from i1.  Some cpus
/// distinguish between vectors of boolean and scalars; the isVec parameter
/// selects between the two kinds.  For example on X86 a scalar boolean should
/// be zero extended from i1, while the elements of a vector of booleans
/// should be sign extended from i1.
///
/// Some cpus also treat floating point types the same way as they treat
/// vectors instead of the way they treat scalars.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
  if (isVec)
    return BooleanVectorContents;
  return isFloat ? BooleanFloatContents : BooleanContents;
}

BooleanContent getBooleanContents(EVT Type) const {
  return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
}

/// Return target scheduling preference.
Sched::Preference getSchedulingPreference() const {
  return SchedPreferenceInfo;
}

/// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
/// for different nodes. This function returns the preference (or none) for
/// the given node.
virtual Sched::Preference getSchedulingPreference(SDNode *) const {
  return Sched::None;
}

/// Return the register class that should be used for the specified value
/// type.
virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
  (void)isDivergent;
  const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
  assert(RC && "This value type is not natively supported!")((RC && "This value type is not natively supported!")
 ? static_cast<void> (0) : __assert_fail ("RC && \"This value type is not natively supported!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 699, __PRETTY_FUNCTION__));
  return RC;
}

/// Allows target to decide about the register class of the
/// specific value that is live outside the defining block.
/// Returns true if the value needs uniform register class.
virtual bool requiresUniformRegister(MachineFunction &MF,
                                     const Value *) const {
  return false;
}

/// Return the 'representative' register class for the specified value
/// type.
///
/// The 'representative' register class is the largest legal super-reg
/// register class for the register class of the value type.  For example, on
/// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
/// register class is GR64 on x86_64.
virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
  const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
  return RC;
}

/// Return the cost of the 'representative' register class for the specified
/// value type.
virtual uint8_t getRepRegClassCostFor(MVT VT) const {
  return RepRegClassCostForVT[VT.SimpleTy];
}

/// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
/// instructions, and false if a library call is preferred (e.g for code-size
/// reasons).
virtual bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const {
  return true;
}

/// Return true if the target has native support for the specified value type.
/// This means that it has a register that directly holds it without
/// promotions or expansions.
bool isTypeLegal(EVT VT) const {
  assert(!VT.isSimple() ||((!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof
(RegClassForVT)) ? static_cast<void> (0) : __assert_fail
 ("!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 741, __PRETTY_FUNCTION__))
         (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT))((!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof
(RegClassForVT)) ? static_cast<void> (0) : __assert_fail
 ("!VT.isSimple() || (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 741, __PRETTY_FUNCTION__));
  return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
}

class ValueTypeActionImpl {
  /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
  /// that indicates how instruction selection should deal with the type.
  LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];

public:
  ValueTypeActionImpl() {
    std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
              TypeLegal);
  }

  LegalizeTypeAction getTypeAction(MVT VT) const {
    return ValueTypeActions[VT.SimpleTy];
  }

  void setTypeAction(MVT VT, LegalizeTypeAction Action) {
    ValueTypeActions[VT.SimpleTy] = Action;
  }
};

const ValueTypeActionImpl &getValueTypeActions() const {
  return ValueTypeActions;
}

/// Return how we should legalize values of this type, either it is already
/// legal (return 'Legal') or we need to promote it to a larger type (return
/// 'Promote'), or we need to expand it into multiple registers of smaller
/// integer type (return 'Expand').  'Custom' is not an option.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
  return getTypeConversion(Context, VT).first;
}
LegalizeTypeAction getTypeAction(MVT VT) const {
  return ValueTypeActions.getTypeAction(VT);
}

/// For types supported by the target, this is an identity function.  For
/// types that must be promoted to larger types, this returns the larger type
/// to promote to.  For integer types that are larger than the largest integer
/// register, this contains one step in the expansion to get to the smaller
/// register. For illegal floating point types, this returns the integer type
/// to transform to.
EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
  return getTypeConversion(Context, VT).second;
}

/// For types supported by the target, this is an identity function.  For
/// types that must be expanded (i.e. integer types that are larger than the
/// largest integer register or illegal floating point types), this returns
/// the largest legal type it will be expanded to.
EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
  assert(!VT.isVector())((!VT.isVector()) ? static_cast<void> (0) : __assert_fail
 ("!VT.isVector()", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 795, __PRETTY_FUNCTION__));
  while (true) {
    switch (getTypeAction(Context, VT)) {
    case TypeLegal:
      return VT;
    case TypeExpandInteger:
      VT = getTypeToTransformTo(Context, VT);
      break;
    default:
      llvm_unreachable("Type is not legal nor is it to be expanded!")::llvm::llvm_unreachable_internal("Type is not legal nor is it to be expanded!"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 804);
    }
  }
}

/// Vector types are broken down into some number of legal first class types.
/// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
/// promoted EVT::f64 values with the X86 FP stack.  Similarly, EVT::v2i64
/// turns into 4 EVT::i32 values with both PPC and X86.
///
/// This method returns the number of registers needed, and the VT for each
/// register.  It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
                                EVT &IntermediateVT,
                                unsigned &NumIntermediates,
                                MVT &RegisterVT) const;

/// Certain targets such as MIPS require that some types such as vectors are
/// always broken down into scalars in some contexts. This occurs even if the
/// vector type is legal.
virtual unsigned getVectorTypeBreakdownForCallingConv(
    LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
    unsigned &NumIntermediates, MVT &RegisterVT) const {
  return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
                                RegisterVT);
}

struct IntrinsicInfo {
  unsigned     opc = 0;          // target opcode
  EVT          memVT;            // memory VT

  // value representing memory location
  PointerUnion<const Value *, const PseudoSourceValue *> ptrVal;

  int          offset = 0;       // offset off of ptrVal
  uint64_t     size = 0;         // the size of the memory location
                                 // (taken from memVT if zero)
  MaybeAlign align = Align::None(); // alignment

  MachineMemOperand::Flags flags = MachineMemOperand::MONone;
  IntrinsicInfo() = default;
};

/// Given an intrinsic, checks if on the target the intrinsic will need to map
/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
/// true and store the intrinsic information into the IntrinsicInfo that was
/// passed to the function.
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
                                MachineFunction &,
                                unsigned /*Intrinsic*/) const {
  return false;
}

/// Returns true if the target can instruction select the specified FP
/// immediate natively. If false, the legalizer will materialize the FP
/// immediate as a load from a constant pool.
virtual bool isFPImmLegal(const APFloat & /*Imm*/, EVT /*VT*/,
                          bool ForCodeSize = false) const {
  return false;
}

/// Targets can use this to indicate that they only support *some*
/// VECTOR_SHUFFLE operations, those with specific masks.  By default, if a
/// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
/// legal.
virtual bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const {
  return true;
}

/// Returns true if the operation can trap for the value type.
///
/// VT must be a legal type. By default, we optimistically assume most
/// operations don't trap except for integer divide and remainder.
virtual bool canOpTrap(unsigned Op, EVT VT) const;

/// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
/// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
/// constant pool entry.
virtual bool isVectorClearMaskLegal(ArrayRef<int> /*Mask*/,
                                    EVT /*VT*/) const {
  return false;
}

/// Return how this operation should be treated: either it is legal, needs to
/// be promoted to a larger size, needs to be expanded to some other code
/// sequence, or the target has a custom expander for it.
LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
  if (VT.isExtended()) return Expand;
  // If a target-specific SDNode requires legalization, require the target
  // to provide custom legalization for it.
  if (Op >= array_lengthof(OpActions[0])) return Custom;
  return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
}

/// Custom method defined by each target to indicate if an operation which
/// may require a scale is supported natively by the target.
/// If not, the operation is illegal.
virtual bool isSupportedFixedPointOperation(unsigned Op, EVT VT,
                                            unsigned Scale) const {
  return false;
}

/// Some fixed point operations may be natively supported by the target but
/// only for specific scales. This method allows for checking
/// if the width is supported by the target for a given operation that may
/// depend on scale.
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT,
                                            unsigned Scale) const {
  auto Action = getOperationAction(Op, VT);
  if (Action != Legal)
    return Action;

  // This operation is supported in this type but may only work on specific
  // scales.
  bool Supported;
  switch (Op) {
  default:
    llvm_unreachable("Unexpected fixed point operation.")::llvm::llvm_unreachable_internal("Unexpected fixed point operation."
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 922);
  case ISD::SMULFIX:
  case ISD::SMULFIXSAT:
  case ISD::UMULFIX:
  case ISD::UMULFIXSAT:
    Supported = isSupportedFixedPointOperation(Op, VT, Scale);
    break;
  }

  return Supported ? Action : Expand;
}

// If Op is a strict floating-point operation, return the result
// of getOperationAction for the equivalent non-strict operation.
LegalizeAction getStrictFPOperationAction(unsigned Op, EVT VT) const {
  unsigned EqOpc;
  switch (Op) {
    default: llvm_unreachable("Unexpected FP pseudo-opcode")::llvm::llvm_unreachable_internal("Unexpected FP pseudo-opcode"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 939);
    case ISD::STRICT_FADD: EqOpc = ISD::FADD; break;
    case ISD::STRICT_FSUB: EqOpc = ISD::FSUB; break;
    case ISD::STRICT_FMUL: EqOpc = ISD::FMUL; break;
    case ISD::STRICT_FDIV: EqOpc = ISD::FDIV; break;
    case ISD::STRICT_FREM: EqOpc = ISD::FREM; break;
    case ISD::STRICT_FSQRT: EqOpc = ISD::FSQRT; break;
    case ISD::STRICT_FPOW: EqOpc = ISD::FPOW; break;
    case ISD::STRICT_FPOWI: EqOpc = ISD::FPOWI; break;
    case ISD::STRICT_FMA: EqOpc = ISD::FMA; break;
    case ISD::STRICT_FSIN: EqOpc = ISD::FSIN; break;
    case ISD::STRICT_FCOS: EqOpc = ISD::FCOS; break;
    case ISD::STRICT_FEXP: EqOpc = ISD::FEXP; break;
    case ISD::STRICT_FEXP2: EqOpc = ISD::FEXP2; break;
    case ISD::STRICT_FLOG: EqOpc = ISD::FLOG; break;
    case ISD::STRICT_FLOG10: EqOpc = ISD::FLOG10; break;
    case ISD::STRICT_FLOG2: EqOpc = ISD::FLOG2; break;
    case ISD::STRICT_FRINT: EqOpc = ISD::FRINT; break;
    case ISD::STRICT_FNEARBYINT: EqOpc = ISD::FNEARBYINT; break;
    case ISD::STRICT_FMAXNUM: EqOpc = ISD::FMAXNUM; break;
    case ISD::STRICT_FMINNUM: EqOpc = ISD::FMINNUM; break;
    case ISD::STRICT_FCEIL: EqOpc = ISD::FCEIL; break;
    case ISD::STRICT_FFLOOR: EqOpc = ISD::FFLOOR; break;
    case ISD::STRICT_FROUND: EqOpc = ISD::FROUND; break;
    case ISD::STRICT_FTRUNC: EqOpc = ISD::FTRUNC; break;
    case ISD::STRICT_FP_TO_SINT: EqOpc = ISD::FP_TO_SINT; break;
    case ISD::STRICT_FP_TO_UINT: EqOpc = ISD::FP_TO_UINT; break;
    case ISD::STRICT_FP_ROUND: EqOpc = ISD::FP_ROUND; break;
    case ISD::STRICT_FP_EXTEND: EqOpc = ISD::FP_EXTEND; break;
  }

  return getOperationAction(EqOpc, VT);
}

/// Return true if the specified operation is legal on this target or can be
/// made legal with custom lowering. This is used to help guide high-level
/// lowering decisions.
bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
  return (VT == MVT::Other || isTypeLegal(VT)) &&
    (getOperationAction(Op, VT) == Legal ||
     getOperationAction(Op, VT) == Custom);
}

/// Return true if the specified operation is legal on this target or can be
/// made legal using promotion. This is used to help guide high-level lowering
/// decisions.
bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
  return (VT == MVT::Other || isTypeLegal(VT)) &&
    (getOperationAction(Op, VT) == Legal ||
     getOperationAction(Op, VT) == Promote);
}

/// Return true if the specified operation is legal on this target or can be
/// made legal with custom lowering or using promotion. This is used to help
/// guide high-level lowering decisions.
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
  return (VT == MVT::Other || isTypeLegal(VT)) &&
    (getOperationAction(Op, VT) == Legal ||
     getOperationAction(Op, VT) == Custom ||
     getOperationAction(Op, VT) == Promote);
}

/// Return true if the operation uses custom lowering, regardless of whether
/// the type is legal or not.
bool isOperationCustom(unsigned Op, EVT VT) const {
  return getOperationAction(Op, VT) == Custom;
}

/// Return true if lowering to a jump table is allowed.
virtual bool areJTsAllowed(const Function *Fn) const {
  if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
    return false;

  return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
         isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
}

/// Check whether the range [Low,High] fits in a machine word.
bool rangeFitsInWord(const APInt &Low, const APInt &High,
                     const DataLayout &DL) const {
  // FIXME: Using the pointer type doesn't seem ideal.
  uint64_t BW = DL.getIndexSizeInBits(0u);
  uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX(18446744073709551615UL) - 1) + 1;
  return Range <= BW;
}

/// Return true if lowering to a jump table is suitable for a set of case
/// clusters which may contain \p NumCases cases, \p Range range of values.
virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
                                    uint64_t Range) const {
  // FIXME: This function check the maximum table size and density, but the
  // minimum size is not checked. It would be nice if the minimum size is
  // also combined within this function. Currently, the minimum size check is
  // performed in findJumpTable() in SelectionDAGBuiler and
  // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
  const bool OptForSize = SI->getParent()->getParent()->hasOptSize();
  const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
  const unsigned MaxJumpTableSize = getMaximumJumpTableSize();
  
  // Check whether the number of cases is small enough and
  // the range is dense enough for a jump table.
  if ((OptForSize || Range <= MaxJumpTableSize) &&
      (NumCases * 100 >= Range * MinDensity)) {
    return true;
  }
  return false;
}

/// Return true if lowering to a bit test is suitable for a set of case
/// clusters which contains \p NumDests unique destinations, \p Low and
/// \p High as its lowest and highest case values, and expects \p NumCmps
/// case value comparisons. Check if the number of destinations, comparison
/// metric, and range are all suitable.
bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
                           const APInt &Low, const APInt &High,
                           const DataLayout &DL) const {
  // FIXME: I don't think NumCmps is the correct metric: a single case and a
  // range of cases both require only one branch to lower. Just looking at the
  // number of clusters and destinations should be enough to decide whether to
  // build bit tests.

  // To lower a range with bit tests, the range must fit the bitwidth of a
  // machine word.
  if (!rangeFitsInWord(Low, High, DL))
    return false;

  // Decide whether it's profitable to lower this range with bit tests. Each
  // destination requires a bit test and branch, and there is an overall range
  // check branch. For a small number of clusters, separate comparisons might
  // be cheaper, and for many destinations, splitting the range might be
  // better.
  return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
         (NumDests == 3 && NumCmps >= 6);
}

/// Return true if the specified operation is illegal on this target or
/// unlikely to be made legal with custom lowering. This is used to help guide
/// high-level lowering decisions.
bool isOperationExpand(unsigned Op, EVT VT) const {
  return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
}

/// Return true if the specified operation is legal on this target.
bool isOperationLegal(unsigned Op, EVT VT) const {
  return (VT == MVT::Other || isTypeLegal(VT)) &&
         getOperationAction(Op, VT) == Legal;
}

/// Return how this load with extension should be treated: either it is legal,
/// needs to be promoted to a larger size, needs to be expanded to some other
/// code sequence, or the target has a custom expander for it.
LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
                                EVT MemVT) const {
  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&((ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT
::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
 "Table isn't big enough!") ? static_cast<void> (0) : __assert_fail
 ("ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1096, __PRETTY_FUNCTION__))
         MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!")((ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT
::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
 "Table isn't big enough!") ? static_cast<void> (0) : __assert_fail
 ("ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1096, __PRETTY_FUNCTION__));
  unsigned Shift = 4 * ExtType;
  return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
}

/// Return true if the specified load with extension is legal on this target.
bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
70
←
Assuming the condition is true→
71
←
Returning the value 1, which participates in a condition later→
}

/// Return true if the specified load with extension is legal or custom
/// on this target.
bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
  return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
         getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
}

/// Return how this store with truncation should be treated: either it is
/// legal, needs to be promoted to a larger size, needs to be expanded to some
/// other code sequence, or the target has a custom expander for it.
LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
  if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
  unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
  unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
  assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&((ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE
 && "Table isn't big enough!") ? static_cast<void>
 (0) : __assert_fail ("ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1121, __PRETTY_FUNCTION__))
         "Table isn't big enough!")((ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE
 && "Table isn't big enough!") ? static_cast<void>
 (0) : __assert_fail ("ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1121, __PRETTY_FUNCTION__));
  return TruncStoreActions[ValI][MemI];
}

/// Return true if the specified store with truncation is legal on this
/// target.
bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
  return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
}

/// Return true if the specified store with truncation has solution on this
/// target.
bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
  return isTypeLegal(ValVT) &&
    (getTruncStoreAction(ValVT, MemVT) == Legal ||
     getTruncStoreAction(ValVT, MemVT) == Custom);
}

/// Return how the indexed load should be treated: either it is legal, needs
/// to be promoted to a larger size, needs to be expanded to some other code
/// sequence, or the target has a custom expander for it.
LegalizeAction
getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
 && "Table isn't big enough!") ? static_cast<void>
 (0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1145, __PRETTY_FUNCTION__))
         "Table isn't big enough!")((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
 && "Table isn't big enough!") ? static_cast<void>
 (0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1145, __PRETTY_FUNCTION__));
  unsigned Ty = (unsigned)VT.SimpleTy;
  return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
}

/// Return true if the specified indexed load is legal on this target.
bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
  return VT.isSimple() &&
    (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
     getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
}

/// Return how the indexed store should be treated: either it is legal, needs
/// to be promoted to a larger size, needs to be expanded to some other code
/// sequence, or the target has a custom expander for it.
LegalizeAction
getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
  assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
 && "Table isn't big enough!") ? static_cast<void>
 (0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1163, __PRETTY_FUNCTION__))
         "Table isn't big enough!")((IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid()
 && "Table isn't big enough!") ? static_cast<void>
 (0) : __assert_fail ("IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1163, __PRETTY_FUNCTION__));
  unsigned Ty = (unsigned)VT.SimpleTy;
  return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
}

/// Return true if the specified indexed load is legal on this target.
bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
  return VT.isSimple() &&
    (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
     getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
}

/// Return how the condition code should be treated: either it is legal, needs
/// to be expanded to some other code sequence, or the target has a custom
/// expander for it.
LegalizeAction
getCondCodeAction(ISD::CondCode CC, MVT VT) const {
  assert((unsigned)CC < array_lengthof(CondCodeActions) &&(((unsigned)CC < array_lengthof(CondCodeActions) &&
 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions
[0]) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("(unsigned)CC < array_lengthof(CondCodeActions) && ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1182, __PRETTY_FUNCTION__))
         ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&(((unsigned)CC < array_lengthof(CondCodeActions) &&
 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions
[0]) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("(unsigned)CC < array_lengthof(CondCodeActions) && ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1182, __PRETTY_FUNCTION__))
         "Table isn't big enough!")(((unsigned)CC < array_lengthof(CondCodeActions) &&
 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions
[0]) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("(unsigned)CC < array_lengthof(CondCodeActions) && ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1182, __PRETTY_FUNCTION__));
  // See setCondCodeAction for how this is encoded.
  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
  uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
  LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
  assert(Action != Promote && "Can't promote condition code!")((Action != Promote && "Can't promote condition code!"
) ? static_cast<void> (0) : __assert_fail ("Action != Promote && \"Can't promote condition code!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1187, __PRETTY_FUNCTION__));
  return Action;
}

/// Return true if the specified condition code is legal on this target.
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
  return getCondCodeAction(CC, VT) == Legal;
}

/// Return true if the specified condition code is legal or custom on this
/// target.
bool isCondCodeLegalOrCustom(ISD::CondCode CC, MVT VT) const {
  return getCondCodeAction(CC, VT) == Legal ||
         getCondCodeAction(CC, VT) == Custom;
}

/// If the action for this operation is to promote, this method returns the
/// ValueType to promote to.
MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
  assert(getOperationAction(Op, VT) == Promote &&((getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"
) ? static_cast<void> (0) : __assert_fail ("getOperationAction(Op, VT) == Promote && \"This operation isn't promoted!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1207, __PRETTY_FUNCTION__))
         "This operation isn't promoted!")((getOperationAction(Op, VT) == Promote && "This operation isn't promoted!"
) ? static_cast<void> (0) : __assert_fail ("getOperationAction(Op, VT) == Promote && \"This operation isn't promoted!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1207, __PRETTY_FUNCTION__));

  // See if this has an explicit type specified.
  std::map<std::pair<unsigned, MVT::SimpleValueType>,
           MVT::SimpleValueType>::const_iterator PTTI =
    PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
  if (PTTI != PromoteToType.end()) return PTTI->second;

  assert((VT.isInteger() || VT.isFloatingPoint()) &&(((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."
) ? static_cast<void> (0) : __assert_fail ("(VT.isInteger() || VT.isFloatingPoint()) && \"Cannot autopromote this type, add it with AddPromotedToType.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1216, __PRETTY_FUNCTION__))
         "Cannot autopromote this type, add it with AddPromotedToType.")(((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromote this type, add it with AddPromotedToType."
) ? static_cast<void> (0) : __assert_fail ("(VT.isInteger() || VT.isFloatingPoint()) && \"Cannot autopromote this type, add it with AddPromotedToType.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1216, __PRETTY_FUNCTION__));

  MVT NVT = VT;
  do {
    NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
    assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&((NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid
 && "Didn't find type to promote to!") ? static_cast<
void> (0) : __assert_fail ("NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && \"Didn't find type to promote to!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1222, __PRETTY_FUNCTION__))
           "Didn't find type to promote to!")((NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid
 && "Didn't find type to promote to!") ? static_cast<
void> (0) : __assert_fail ("NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid && \"Didn't find type to promote to!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1222, __PRETTY_FUNCTION__));
  } while (!isTypeLegal(NVT) ||
            getOperationAction(Op, NVT) == Promote);
  return NVT;
}

/// Return the EVT corresponding to this LLVM type.  This is fixed by the LLVM
/// operations except for the pointer size.  If AllowUnknown is true, this
/// will return MVT::Other for types with no EVT counterpart (e.g. structs),
/// otherwise it will assert.
EVT getValueType(const DataLayout &DL, Type *Ty,
                 bool AllowUnknown = false) const {
  // Lower scalar pointers to native pointer types.
  if (auto *PTy = dyn_cast<PointerType>(Ty))
    return getPointerTy(DL, PTy->getAddressSpace());

  if (auto *VTy = dyn_cast<VectorType>(Ty)) {
    Type *EltTy = VTy->getElementType();
    // Lower vectors of pointers to native pointer types.
    if (auto *PTy = dyn_cast<PointerType>(EltTy)) {
      EVT PointerTy(getPointerTy(DL, PTy->getAddressSpace()));
      EltTy = PointerTy.getTypeForEVT(Ty->getContext());
    }
    return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(EltTy, false),
                            VTy->getElementCount());
  }

  return EVT::getEVT(Ty, AllowUnknown);
}

EVT getMemValueType(const DataLayout &DL, Type *Ty,
                    bool AllowUnknown = false) const {
  // Lower scalar pointers to native pointer types.
  if (PointerType *PTy = dyn_cast<PointerType>(Ty))
    return getPointerMemTy(DL, PTy->getAddressSpace());
  else if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
    Type *Elm = VTy->getElementType();
    if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
      EVT PointerTy(getPointerMemTy(DL, PT->getAddressSpace()));
      Elm = PointerTy.getTypeForEVT(Ty->getContext());
    }
    return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
                     VTy->getNumElements());
  }

  return getValueType(DL, Ty, AllowUnknown);
}


/// Return the MVT corresponding to this LLVM type. See getValueType.
MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
                       bool AllowUnknown = false) const {
  return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
}

/// Return the desired alignment for ByVal or InAlloca aggregate function
/// arguments in the caller parameter area.  This is the actual alignment, not
/// its logarithm.
virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;

/// Return the type of registers that this ValueType will eventually require.
MVT getRegisterType(MVT VT) const {
  assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT))(((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1284, __PRETTY_FUNCTION__));
  return RegisterTypeForVT[VT.SimpleTy];
}

/// Return the type of registers that this ValueType will eventually require.
MVT getRegisterType(LLVMContext &Context, EVT VT) const {
  if (VT.isSimple()) {
    assert((unsigned)VT.getSimpleVT().SimpleTy <(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1292, __PRETTY_FUNCTION__))
              array_lengthof(RegisterTypeForVT))(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegisterTypeForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1292, __PRETTY_FUNCTION__));
    return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
  }
  if (VT.isVector()) {
    EVT VT1;
    MVT RegisterVT;
    unsigned NumIntermediates;
    (void)getVectorTypeBreakdown(Context, VT, VT1,
                                 NumIntermediates, RegisterVT);
    return RegisterVT;
  }
  if (VT.isInteger()) {
    return getRegisterType(Context, getTypeToTransformTo(Context, VT));
  }
  llvm_unreachable("Unsupported extended type!")::llvm::llvm_unreachable_internal("Unsupported extended type!"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1306);
}

/// Return the number of registers that this ValueType will eventually
/// require.
///
/// This is one for any types promoted to live in larger registers, but may be
/// more than one for types (like i64) that are split into pieces.  For types
/// like i140, which are first promoted then expanded, it is the number of
/// registers needed to hold all the bits of the original type.  For an i140
/// on a 32 bit machine this means 5 registers.
unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
  if (VT.isSimple()) {
    assert((unsigned)VT.getSimpleVT().SimpleTy <(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1320, __PRETTY_FUNCTION__))
              array_lengthof(NumRegistersForVT))(((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT
)) ? static_cast<void> (0) : __assert_fail ("(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(NumRegistersForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1320, __PRETTY_FUNCTION__));
    return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
  }
  if (VT.isVector()) {
    EVT VT1;
    MVT VT2;
    unsigned NumIntermediates;
    return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
  }
  if (VT.isInteger()) {
    unsigned BitWidth = VT.getSizeInBits();
    unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
    return (BitWidth + RegWidth - 1) / RegWidth;
  }
  llvm_unreachable("Unsupported extended type!")::llvm::llvm_unreachable_internal("Unsupported extended type!"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1334);
}

/// Certain combinations of ABIs, Targets and features require that types
/// are legal for some operations and not for other operations.
/// For MIPS all vector types must be passed through the integer register set.
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
                                          CallingConv::ID CC, EVT VT) const {
  return getRegisterType(Context, VT);
}

/// Certain targets require unusual breakdowns of certain types. For MIPS,
/// this occurs when a vector type is used, as vector are passed through the
/// integer register set.
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
                                               CallingConv::ID CC,
                                               EVT VT) const {
  return getNumRegisters(Context, VT);
}

/// Certain targets have context senstive alignment requirements, where one
/// type has the alignment requirement of another type.
virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
                                               DataLayout DL) const {
  return DL.getABITypeAlignment(ArgTy);
}

/// If true, then instruction selection should seek to shrink the FP constant
/// of the specified type to a smaller type in order to save space and / or
/// reduce runtime.
virtual bool ShouldShrinkFPConstant(EVT) const { return true; }

/// Return true if it is profitable to reduce a load to a smaller type.
/// Example: (i16 (trunc (i32 (load x))) -> i16 load x
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
                                   EVT NewVT) const {
  // By default, assume that it is cheaper to extract a subvector from a wide
  // vector load rather than creating multiple narrow vector loads.
  if (NewVT.isVector() && !Load->hasOneUse())
    return false;

  return true;
}

/// When splitting a value of the specified type into parts, does the Lo
/// or Hi part come first?  This usually follows the endianness, except
/// for ppcf128, where the Hi part always comes first.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
  return DL.isBigEndian() || VT == MVT::ppcf128;
}

/// If true, the target has custom DAG combine transformations that it can
/// perform for the specified node.
bool hasTargetDAGCombine(ISD::NodeType NT) const {
  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray))((unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray
)) ? static_cast<void> (0) : __assert_fail ("unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1388, __PRETTY_FUNCTION__));
  return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
}

unsigned getGatherAllAliasesMaxDepth() const {
  return GatherAllAliasesMaxDepth;
}

/// Returns the size of the platform's va_list object.
virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
  return getPointerTy(DL).getSizeInBits();
}

/// Get maximum # of store operations permitted for llvm.memset
///
/// This function returns the maximum number of store operations permitted
/// to replace a call to llvm.memset. The value is set by the target at the
/// performance threshold for such a replacement. If OptSize is true,
/// return the limit for functions that have OptSize attribute.
unsigned getMaxStoresPerMemset(bool OptSize) const {
  return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
}

/// Get maximum # of store operations permitted for llvm.memcpy
///
/// This function returns the maximum number of store operations permitted
/// to replace a call to llvm.memcpy. The value is set by the target at the
/// performance threshold for such a replacement. If OptSize is true,
/// return the limit for functions that have OptSize attribute.
unsigned getMaxStoresPerMemcpy(bool OptSize) const {
  return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
}

/// \brief Get maximum # of store operations to be glued together
///
/// This function returns the maximum number of store operations permitted
/// to glue together during lowering of llvm.memcpy. The value is set by
//  the target at the performance threshold for such a replacement.
virtual unsigned getMaxGluedStoresPerMemcpy() const {
  return MaxGluedStoresPerMemcpy;
}

/// Get maximum # of load operations permitted for memcmp
///
/// This function returns the maximum number of load operations permitted
/// to replace a call to memcmp. The value is set by the target at the
/// performance threshold for such a replacement. If OptSize is true,
/// return the limit for functions that have OptSize attribute.
unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
  return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
}

/// Get maximum # of store operations permitted for llvm.memmove
///
/// This function returns the maximum number of store operations permitted
/// to replace a call to llvm.memmove. The value is set by the target at the
/// performance threshold for such a replacement. If OptSize is true,
/// return the limit for functions that have OptSize attribute.
unsigned getMaxStoresPerMemmove(bool OptSize) const {
  return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
}

/// Determine if the target supports unaligned memory accesses.
///
/// This function returns true if the target allows unaligned memory accesses
/// of the specified type in the given address space. If true, it also returns
/// whether the unaligned memory access is "fast" in the last argument by
/// reference. This is used, for example, in situations where an array
/// copy/move/set is converted to a sequence of store operations. Its use
/// helps to ensure that such replacements don't generate code that causes an
/// alignment error (trap) on the target machine.
virtual bool allowsMisalignedMemoryAccesses(
    EVT, unsigned AddrSpace = 0, unsigned Align = 1,
    MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
    bool * /*Fast*/ = nullptr) const {
  return false;
}

/// LLT handling variant.
virtual bool allowsMisalignedMemoryAccesses(
    LLT, unsigned AddrSpace = 0, unsigned Align = 1,
    MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
    bool * /*Fast*/ = nullptr) const {
  return false;
}

/// This function returns true if the memory access is aligned or if the
/// target allows this specific unaligned memory access. If the access is
/// allowed, the optional final parameter returns if the access is also fast
/// (as defined by the target).
bool allowsMemoryAccessForAlignment(
    LLVMContext &Context, const DataLayout &DL, EVT VT,
    unsigned AddrSpace = 0, unsigned Alignment = 1,
    MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
    bool *Fast = nullptr) const;

/// Return true if the memory access of this type is aligned or if the target
/// allows this specific unaligned access for the given MachineMemOperand.
/// If the access is allowed, the optional final parameter returns if the
/// access is also fast (as defined by the target).
bool allowsMemoryAccessForAlignment(LLVMContext &Context,
                                    const DataLayout &DL, EVT VT,
                                    const MachineMemOperand &MMO,
                                    bool *Fast = nullptr) const;

/// Return true if the target supports a memory access of this type for the
/// given address space and alignment. If the access is allowed, the optional
/// final parameter returns if the access is also fast (as defined by the
/// target).
virtual bool
allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
                   unsigned AddrSpace = 0, unsigned Alignment = 1,
                   MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
                   bool *Fast = nullptr) const;

/// Return true if the target supports a memory access of this type for the
/// given MachineMemOperand. If the access is allowed, the optional
/// final parameter returns if the access is also fast (as defined by the
/// target).
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
                        const MachineMemOperand &MMO,
                        bool *Fast = nullptr) const;

/// Returns the target specific optimal type for load and store operations as
/// a result of memset, memcpy, and memmove lowering.
///
/// If DstAlign is zero that means it's safe to destination alignment can
/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
/// a need to check it against alignment requirement, probably because the
/// source does not need to be loaded. If 'IsMemset' is true, that means it's
/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
/// does not need to be loaded.  It returns EVT::Other if the type should be
/// determined using generic target-independent logic.
virtual EVT
getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
                    unsigned /*SrcAlign*/, bool /*IsMemset*/,
                    bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
                    const AttributeList & /*FuncAttributes*/) const {
  return MVT::Other;
}


/// LLT returning variant.
virtual LLT
getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
                   unsigned /*SrcAlign*/, bool /*IsMemset*/,
                   bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
                   const AttributeList & /*FuncAttributes*/) const {
  return LLT();
}

/// Returns true if it's safe to use load / store of the specified type to
/// expand memcpy / memset inline.
///
/// This is mostly true for all types except for some special cases. For
/// example, on X86 targets without SSE2 f64 load / store are done with fldl /
/// fstpl which also does type conversion. Note the specified type doesn't
/// have to be legal as the hook is used before type legalization.
virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }

/// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
bool usesUnderscoreSetJmp() const {
  return UseUnderscoreSetJmp;
}

/// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
bool usesUnderscoreLongJmp() const {
  return UseUnderscoreLongJmp;
}

/// Return lower limit for number of blocks in a jump table.
virtual unsigned getMinimumJumpTableEntries() const;

/// Return lower limit of the density in a jump table.
unsigned getMinimumJumpTableDensity(bool OptForSize) const;

/// Return upper limit for number of entries in a jump table.
/// Zero if no limit.
unsigned getMaximumJumpTableSize() const;

virtual bool isJumpTableRelative() const {
  return TM.isPositionIndependent();
}

/// If a physical register, this specifies the register that
/// llvm.savestack/llvm.restorestack should save and restore.
unsigned getStackPointerRegisterToSaveRestore() const {
  return StackPointerRegisterToSaveRestore;
}

/// If a physical register, this returns the register that receives the
/// exception address on entry to an EH pad.
virtual unsigned
getExceptionPointerRegister(const Constant *PersonalityFn) const {
  // 0 is guaranteed to be the NoRegister value on all targets
  return 0;
}

/// If a physical register, this returns the register that receives the
/// exception typeid on entry to a landing pad.
virtual unsigned
getExceptionSelectorRegister(const Constant *PersonalityFn) const {
  // 0 is guaranteed to be the NoRegister value on all targets
  return 0;
}

virtual bool needsFixedCatchObjects() const {
  report_fatal_error("Funclet EH is not implemented for this target");
}

/// Return the minimum stack alignment of an argument.
Align getMinStackArgumentAlignment() const {
  return MinStackArgumentAlignment;
}

/// Return the minimum function alignment.
Align getMinFunctionAlignment() const { return MinFunctionAlignment; }

/// Return the preferred function alignment.
Align getPrefFunctionAlignment() const { return PrefFunctionAlignment; }

/// Return the preferred loop alignment.
virtual Align getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
  return PrefLoopAlignment;
}

/// Should loops be aligned even when the function is marked OptSize (but not
/// MinSize).
virtual bool alignLoopsWithOptSize() const {
  return false;
}

/// If the target has a standard location for the stack protector guard,
/// returns the address of that location. Otherwise, returns nullptr.
/// DEPRECATED: please override useLoadStackGuardNode and customize
///             LOAD_STACK_GUARD, or customize \@llvm.stackguard().
virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;

/// Inserts necessary declarations for SSP (stack protection) purpose.
/// Should be used only when getIRStackGuard returns nullptr.
virtual void insertSSPDeclarations(Module &M) const;

/// Return the variable that's previously inserted by insertSSPDeclarations,
/// if any, otherwise return nullptr. Should be used only when
/// getIRStackGuard returns nullptr.
virtual Value *getSDagStackGuard(const Module &M) const;

/// If this function returns true, stack protection checks should XOR the
/// frame pointer (or whichever pointer is used to address locals) into the
/// stack guard value before checking it. getIRStackGuard must return nullptr
/// if this returns true.
virtual bool useStackGuardXorFP() const { return false; }

/// If the target has a standard stack protection check function that
/// performs validation and error handling, returns the function. Otherwise,
/// returns nullptr. Must be previously inserted by insertSSPDeclarations.
/// Should be used only when getIRStackGuard returns nullptr.
virtual Function *getSSPStackGuardCheck(const Module &M) const;

1648protected:
Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
                                          bool UseTLS) const;

1652public:
/// Returns the target-specific address of the unsafe stack pointer.
virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;

/// Returns the name of the symbol used to emit stack probes or the empty
/// string if not applicable.
virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
  return "";
}

/// Returns true if a cast between SrcAS and DestAS is a noop.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
  return false;
}

/// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
/// are happy to sink it into basic blocks. A cast may be free, but not
/// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
  return isNoopAddrSpaceCast(SrcAS, DestAS);
}

/// Return true if the pointer arguments to CI should be aligned by aligning
/// the object whose address is being passed. If so then MinSize is set to the
/// minimum size the object must be to be aligned and PrefAlign is set to the
/// preferred alignment.
virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
                                    unsigned & /*PrefAlign*/) const {
  return false;
}

//===--------------------------------------------------------------------===//
/// \name Helpers for TargetTransformInfo implementations
/// @{

/// Get the ISD node that corresponds to the Instruction class opcode.
int InstructionOpcodeToISD(unsigned Opcode) const;

/// Estimate the cost of type-legalization and the legalized type.
std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
                                            Type *Ty) const;

/// @}

//===--------------------------------------------------------------------===//
/// \name Helpers for atomic expansion.
/// @{

/// Returns the maximum atomic operation size (in bits) supported by
/// the backend. Atomic operations greater than this size (as well
/// as ones that are not naturally aligned), will be expanded by
/// AtomicExpandPass into an __atomic_* library call.
unsigned getMaxAtomicSizeInBitsSupported() const {
  return MaxAtomicSizeInBitsSupported;
}

/// Returns the size of the smallest cmpxchg or ll/sc instruction
/// the backend supports.  Any smaller operations are widened in
/// AtomicExpandPass.
///
/// Note that *unlike* operations above the maximum size, atomic ops
/// are still natively supported below the minimum; they just
/// require a more complex expansion.
unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }

/// Whether the target supports unaligned atomic operations.
bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics; }

/// Whether AtomicExpandPass should automatically insert fences and reduce
/// ordering for this atomic. This should be true for most architectures with
/// weak memory ordering. Defaults to false.
virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
  return false;
}

/// Perform a load-linked operation on Addr, returning a "Value *" with the
/// corresponding pointee type. This may entail some non-trivial operations to
/// truncate or reconstruct types that will be illegal in the backend. See
/// ARMISelLowering for an example implementation.
virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
                              AtomicOrdering Ord) const {
  llvm_unreachable("Load linked unimplemented on this target")::llvm::llvm_unreachable_internal("Load linked unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1733);
}

/// Perform a store-conditional operation to Addr. Return the status of the
/// store. This should be 0 if the store succeeded, non-zero otherwise.
virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
                                    Value *Addr, AtomicOrdering Ord) const {
  llvm_unreachable("Store conditional unimplemented on this target")::llvm::llvm_unreachable_internal("Store conditional unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1740);
}

/// Perform a masked atomicrmw using a target-specific intrinsic. This
/// represents the core LL/SC loop which will be lowered at a late stage by
/// the backend.
virtual Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder,
                                            AtomicRMWInst *AI,
                                            Value *AlignedAddr, Value *Incr,
                                            Value *Mask, Value *ShiftAmt,
                                            AtomicOrdering Ord) const {
  llvm_unreachable("Masked atomicrmw expansion unimplemented on this target")::llvm::llvm_unreachable_internal("Masked atomicrmw expansion unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1751);
}

/// Perform a masked cmpxchg using a target-specific intrinsic. This
/// represents the core LL/SC loop which will be lowered at a late stage by
/// the backend.
virtual Value *emitMaskedAtomicCmpXchgIntrinsic(
    IRBuilder<> &Builder, AtomicCmpXchgInst *CI, Value *AlignedAddr,
    Value *CmpVal, Value *NewVal, Value *Mask, AtomicOrdering Ord) const {
  llvm_unreachable("Masked cmpxchg expansion unimplemented on this target")::llvm::llvm_unreachable_internal("Masked cmpxchg expansion unimplemented on this target"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 1760);
}

/// Inserts in the IR a target-specific intrinsic specifying a fence.
/// It is called by AtomicExpandPass before expanding an
///   AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
///   if shouldInsertFencesForAtomic returns true.
///
/// Inst is the original atomic instruction, prior to other expansions that
/// may be performed.
///
/// This function should either return a nullptr, or a pointer to an IR-level
///   Instruction*. Even complex fence sequences can be represented by a
///   single Instruction* through an intrinsic to be lowered later.
/// Backends should override this method to produce target-specific intrinsic
///   for their fences.
/// FIXME: Please note that the default implementation here in terms of
///   IR-level fences exists for historical/compatibility reasons and is
///   *unsound* ! Fences cannot, in general, be used to restore sequential
///   consistency. For example, consider the following example:
/// atomic<int> x = y = 0;
/// int r1, r2, r3, r4;
/// Thread 0:
///   x.store(1);
/// Thread 1:
///   y.store(1);
/// Thread 2:
///   r1 = x.load();
///   r2 = y.load();
/// Thread 3:
///   r3 = y.load();
///   r4 = x.load();
///  r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
///  seq_cst. But if they are lowered to monotonic accesses, no amount of
///  IR-level fences can prevent it.
/// @{
virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
                                      AtomicOrdering Ord) const {
  if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
    return Builder.CreateFence(Ord);
  else
    return nullptr;
}

virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
                                       Instruction *Inst,
                                       AtomicOrdering Ord) const {
  if (isAcquireOrStronger(Ord))
    return Builder.CreateFence(Ord);
  else
    return nullptr;
}
/// @}

// Emits code that executes when the comparison result in the ll/sc
// expansion of a cmpxchg instruction is such that the store-conditional will
// not execute.  This makes it possible to balance out the load-linked with
// a dedicated instruction, if desired.
// E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
// be unnecessarily held, except if clrex, inserted by this hook, is executed.
virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}

/// Returns true if the given (atomic) store should be expanded by the
/// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
  return false;
}

/// Returns true if arguments should be sign-extended in lib calls.
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
  return IsSigned;
}

/// Returns true if arguments should be extended in lib calls.
virtual bool shouldExtendTypeInLibCall(EVT Type) const {
  return true;
}

/// Returns how the given (atomic) load should be expanded by the
/// IR-level AtomicExpand pass.
virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
  return AtomicExpansionKind::None;
}

/// Returns how the given atomic cmpxchg should be expanded by the IR-level
/// AtomicExpand pass.
virtual AtomicExpansionKind
shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
  return AtomicExpansionKind::None;
}

/// Returns how the IR-level AtomicExpand pass should expand the given
/// AtomicRMW, if at all. Default is to never expand.
virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
  return RMW->isFloatingPointOperation() ?
    AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
}

/// On some platforms, an AtomicRMW that never actually modifies the value
/// (such as fetch_add of 0) can be turned into a fence followed by an
/// atomic load. This may sound useless, but it makes it possible for the
/// processor to keep the cacheline shared, dramatically improving
/// performance. And such idempotent RMWs are useful for implementing some
/// kinds of locks, see for example (justification + benchmarks):
/// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
/// This method tries doing that transformation, returning the atomic load if
/// it succeeds, and nullptr otherwise.
/// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
/// another round of expansion.
virtual LoadInst *
lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
  return nullptr;
}

/// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
/// SIGN_EXTEND, or ANY_EXTEND).
virtual ISD::NodeType getExtendForAtomicOps() const {
  return ISD::ZERO_EXTEND;
}

/// @}

/// Returns true if we should normalize
/// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
/// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
/// that it saves us from materializing N0 and N1 in an integer register.
/// Targets that are able to perform and/or on flags should return false here.
virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
                                             EVT VT) const {
  // If a target has multiple condition registers, then it likely has logical
  // operations on those registers.
  if (hasMultipleConditionRegisters())
    return false;
  // Only do the transform if the value won't be split into multiple
  // registers.
  LegalizeTypeAction Action = getTypeAction(Context, VT);
  return Action != TypeExpandInteger && Action != TypeExpandFloat &&
    Action != TypeSplitVector;
}

virtual bool isProfitableToCombineMinNumMaxNum(EVT VT) const { return true; }

/// Return true if a select of constants (select Cond, C1, C2) should be
/// transformed into simple math ops with the condition value. For example:
/// select Cond, C1, C1-1 --> add (zext Cond), C1-1
virtual bool convertSelectOfConstantsToMath(EVT VT) const {
  return false;
}

/// Return true if it is profitable to transform an integer
/// multiplication-by-constant into simpler operations like shifts and adds.
/// This may be true if the target does not directly support the
/// multiplication operation for the specified type or the sequence of simpler
/// ops is faster than the multiply.
virtual bool decomposeMulByConstant(LLVMContext &Context,
                                    EVT VT, SDValue C) const {
  return false;
}

/// Return true if it is more correct/profitable to use strict FP_TO_INT
/// conversion operations - canonicalizing the FP source value instead of
/// converting all cases and then selecting based on value.
/// This may be true if the target throws exceptions for out of bounds
/// conversions or has fast FP CMOV.
virtual bool shouldUseStrictFP_TO_INT(EVT FpVT, EVT IntVT,
                                      bool IsSigned) const {
  return false;
}

//===--------------------------------------------------------------------===//
// TargetLowering Configuration Methods - These methods should be invoked by
// the derived class constructor to configure this object for the target.
//
1933protected:
/// Specify how the target extends the result of integer and floating point
/// boolean values from i1 to a wider type.  See getBooleanContents.
void setBooleanContents(BooleanContent Ty) {
  BooleanContents = Ty;
  BooleanFloatContents = Ty;
}

/// Specify how the target extends the result of integer and floating point
/// boolean values from i1 to a wider type.  See getBooleanContents.
void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
  BooleanContents = IntTy;
  BooleanFloatContents = FloatTy;
}

/// Specify how the target extends the result of a vector boolean value from a
/// vector of i1 to a wider type.  See getBooleanContents.
void setBooleanVectorContents(BooleanContent Ty) {
  BooleanVectorContents = Ty;
}

/// Specify the target scheduling preference.
void setSchedulingPreference(Sched::Preference Pref) {
  SchedPreferenceInfo = Pref;
}

/// Indicate whether this target prefers to use _setjmp to implement
/// llvm.setjmp or the version without _.  Defaults to false.
void setUseUnderscoreSetJmp(bool Val) {
  UseUnderscoreSetJmp = Val;
}

/// Indicate whether this target prefers to use _longjmp to implement
/// llvm.longjmp or the version without _.  Defaults to false.
void setUseUnderscoreLongJmp(bool Val) {
  UseUnderscoreLongJmp = Val;
}

/// Indicate the minimum number of blocks to generate jump tables.
void setMinimumJumpTableEntries(unsigned Val);

/// Indicate the maximum number of entries in jump tables.
/// Set to zero to generate unlimited jump tables.
void setMaximumJumpTableSize(unsigned);

/// If set to a physical register, this specifies the register that
/// llvm.savestack/llvm.restorestack should save and restore.
void setStackPointerRegisterToSaveRestore(unsigned R) {
  StackPointerRegisterToSaveRestore = R;
}

/// Tells the code generator that the target has multiple (allocatable)
/// condition registers that can be used to store the results of comparisons
/// for use by selects and conditional branches. With multiple condition
/// registers, the code generator will not aggressively sink comparisons into
/// the blocks of their users.
void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
  HasMultipleConditionRegisters = hasManyRegs;
}

/// Tells the code generator that the target has BitExtract instructions.
/// The code generator will aggressively sink "shift"s into the blocks of
/// their users if the users will generate "and" instructions which can be
/// combined with "shift" to BitExtract instructions.
void setHasExtractBitsInsn(bool hasExtractInsn = true) {
  HasExtractBitsInsn = hasExtractInsn;
}

/// Tells the code generator not to expand logic operations on comparison
/// predicates into separate sequences that increase the amount of flow
/// control.
void setJumpIsExpensive(bool isExpensive = true);

/// Tells the code generator which bitwidths to bypass.
void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
  BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
}

/// Add the specified register class as an available regclass for the
/// specified value type. This indicates the selector can handle values of
/// that class natively.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
  assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT))(((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)) ?
 static_cast<void> (0) : __assert_fail ("(unsigned)VT.SimpleTy < array_lengthof(RegClassForVT)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2015, __PRETTY_FUNCTION__));
  RegClassForVT[VT.SimpleTy] = RC;
}

/// Return the largest legal super-reg register class of the register class
/// for the specified type and its associated "cost".
virtual std::pair<const TargetRegisterClass *, uint8_t>
findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;

/// Once all of the register classes are added, this allows us to compute
/// derived properties we expose.
void computeRegisterProperties(const TargetRegisterInfo *TRI);

/// Indicate that the specified operation does not work with the specified
/// type and indicate what to do about it. Note that VT may refer to either
/// the type of a result or that of an operand of Op.
void setOperationAction(unsigned Op, MVT VT,
                        LegalizeAction Action) {
  assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!")((Op < array_lengthof(OpActions[0]) && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("Op < array_lengthof(OpActions[0]) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2033, __PRETTY_FUNCTION__));
  OpActions[(unsigned)VT.SimpleTy][Op] = Action;
}

/// Indicate that the specified load with extension does not work with the
/// specified type and indicate what to do about it.
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
                      LegalizeAction Action) {
  assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&((ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid
() && MemVT.isValid() && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && MemVT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2042, __PRETTY_FUNCTION__))
         MemVT.isValid() && "Table isn't big enough!")((ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid
() && MemVT.isValid() && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && MemVT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2042, __PRETTY_FUNCTION__));
  assert((unsigned)Action < 0x10 && "too many bits for bitfield array")(((unsigned)Action < 0x10 && "too many bits for bitfield array"
) ? static_cast<void> (0) : __assert_fail ("(unsigned)Action < 0x10 && \"too many bits for bitfield array\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2043, __PRETTY_FUNCTION__));
  unsigned Shift = 4 * ExtType;
  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
  LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
}

/// Indicate that the specified truncating store does not work with the
/// specified type and indicate what to do about it.
void setTruncStoreAction(MVT ValVT, MVT MemVT,
                         LegalizeAction Action) {
  assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!")((ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("ValVT.isValid() && MemVT.isValid() && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2053, __PRETTY_FUNCTION__));
  TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
}

/// Indicate that the specified indexed load does or does not work with the
/// specified type and indicate what to do abort it.
///
/// NOTE: All indexed mode loads are initialized to Expand in
/// TargetLowering.cpp
void setIndexedLoadAction(unsigned IdxMode, MVT VT,
                          LegalizeAction Action) {
  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
 && (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2065, __PRETTY_FUNCTION__))
         (unsigned)Action < 0xf && "Table isn't big enough!")((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
 && (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2065, __PRETTY_FUNCTION__));
  // Load action are kept in the upper half.
  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
}

/// Indicate that the specified indexed store does or does not work with the
/// specified type and indicate what to do about it.
///
/// NOTE: All indexed mode stores are initialized to Expand in
/// TargetLowering.cpp
void setIndexedStoreAction(unsigned IdxMode, MVT VT,
                           LegalizeAction Action) {
  assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
 && (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2079, __PRETTY_FUNCTION__))
         (unsigned)Action < 0xf && "Table isn't big enough!")((VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE
 && (unsigned)Action < 0xf && "Table isn't big enough!"
) ? static_cast<void> (0) : __assert_fail ("VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE && (unsigned)Action < 0xf && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2079, __PRETTY_FUNCTION__));
  // Store action are kept in the lower half.
  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
  IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
}

/// Indicate that the specified condition code is or isn't supported on the
/// target and indicate what to do about it.
void setCondCodeAction(ISD::CondCode CC, MVT VT,
                       LegalizeAction Action) {
  assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&((VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions
) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2090, __PRETTY_FUNCTION__))
         "Table isn't big enough!")((VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions
) && "Table isn't big enough!") ? static_cast<void
> (0) : __assert_fail ("VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) && \"Table isn't big enough!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2090, __PRETTY_FUNCTION__));
  assert((unsigned)Action < 0x10 && "too many bits for bitfield array")(((unsigned)Action < 0x10 && "too many bits for bitfield array"
) ? static_cast<void> (0) : __assert_fail ("(unsigned)Action < 0x10 && \"too many bits for bitfield array\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2091, __PRETTY_FUNCTION__));
  /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
  /// value and the upper 29 bits index into the second dimension of the array
  /// to select what 32-bit value to use.
  uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
  CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
  CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
}

/// If Opc/OrigVT is specified as being promoted, the promotion code defaults
/// to trying a larger integer/fp until it can find one that works. If that
/// default is insufficient, this method can be used by the target to override
/// the default.
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
  PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
}

/// Convenience method to set an operation to Promote and specify the type
/// in a single call.
void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
  setOperationAction(Opc, OrigVT, Promote);
  AddPromotedToType(Opc, OrigVT, DestVT);
}

/// Targets should invoke this method for each target independent node that
/// they want to provide a custom DAG combiner for by implementing the
/// PerformDAGCombine virtual method.
void setTargetDAGCombine(ISD::NodeType NT) {
  assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray))((unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray
)) ? static_cast<void> (0) : __assert_fail ("unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray)"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2119, __PRETTY_FUNCTION__));
  TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
}

/// Set the target's minimum function alignment.
void setMinFunctionAlignment(Align Alignment) {
  MinFunctionAlignment = Alignment;
}

/// Set the target's preferred function alignment.  This should be set if
/// there is a performance benefit to higher-than-minimum alignment
void setPrefFunctionAlignment(Align Alignment) {
  PrefFunctionAlignment = Alignment;
}

/// Set the target's preferred loop alignment. Default alignment is one, it
/// means the target does not care about loop alignment. The target may also
/// override getPrefLoopAlignment to provide per-loop values.
void setPrefLoopAlignment(Align Alignment) { PrefLoopAlignment = Alignment; }

/// Set the minimum stack alignment of an argument.
void setMinStackArgumentAlignment(Align Alignment) {
  MinStackArgumentAlignment = Alignment;
}

/// Set the maximum atomic operation size supported by the
/// backend. Atomic operations greater than this size (as well as
/// ones that are not naturally aligned), will be expanded by
/// AtomicExpandPass into an __atomic_* library call.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
  MaxAtomicSizeInBitsSupported = SizeInBits;
}

/// Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
  MinCmpXchgSizeInBits = SizeInBits;
}

/// Sets whether unaligned atomic operations are supported.
void setSupportsUnalignedAtomics(bool UnalignedSupported) {
  SupportsUnalignedAtomics = UnalignedSupported;
}

2162public:
//===--------------------------------------------------------------------===//
// Addressing mode description hooks (used by LSR etc).
//

/// CodeGenPrepare sinks address calculations into the same BB as Load/Store
/// instructions reading the address. This allows as much computation as
/// possible to be done in the address mode for that operand. This hook lets
/// targets also pass back when this should be done on intrinsics which
/// load/store.
virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
                                  SmallVectorImpl<Value*> &/*Ops*/,
                                  Type *&/*AccessTy*/) const {
  return false;
}

/// This represents an addressing mode of:
///    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
/// If BaseGV is null,  there is no BaseGV.
/// If BaseOffs is zero, there is no base offset.
/// If HasBaseReg is false, there is no base register.
/// If Scale is zero, there is no ScaleReg.  Scale of 1 indicates a reg with
/// no scale.
struct AddrMode {
  GlobalValue *BaseGV = nullptr;
  int64_t      BaseOffs = 0;
  bool         HasBaseReg = false;
  int64_t      Scale = 0;
  AddrMode() = default;
};

/// Return true if the addressing mode represented by AM is legal for this
/// target, for a load/store of the specified type.
///
/// The type may be VoidTy, in which case only return true if the addressing
/// mode is legal for a load/store of any legal type.  TODO: Handle
/// pre/postinc as well.
///
/// If the address space cannot be determined, it will be -1.
///
/// TODO: Remove default argument
virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
                                   Type *Ty, unsigned AddrSpace,
                                   Instruction *I = nullptr) const;

/// Return the cost of the scaling factor used in the addressing mode
/// represented by AM for this target, for a load/store of the specified type.
///
/// If the AM is supported, the return value must be >= 0.
/// If the AM is not supported, it returns a negative value.
/// TODO: Handle pre/postinc as well.
/// TODO: Remove default argument
virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
                                 Type *Ty, unsigned AS = 0) const {
  // Default: assume that any scaling factor used in a legal AM is free.
  if (isLegalAddressingMode(DL, AM, Ty, AS))
    return 0;
  return -1;
}

/// Return true if the specified immediate is legal icmp immediate, that is
/// the target has icmp instructions which can compare a register against the
/// immediate without having to materialize the immediate into a register.
virtual bool isLegalICmpImmediate(int64_t) const {
  return true;
}

/// Return true if the specified immediate is legal add immediate, that is the
/// target has add instructions which can add a register with the immediate
/// without having to materialize the immediate into a register.
virtual bool isLegalAddImmediate(int64_t) const {
  return true;
}

/// Return true if the specified immediate is legal for the value input of a
/// store instruction.
virtual bool isLegalStoreImmediate(int64_t Value) const {
  // Default implementation assumes that at least 0 works since it is likely
  // that a zero register exists or a zero immediate is allowed.
  return Value == 0;
}

/// Return true if it's significantly cheaper to shift a vector by a uniform
/// scalar than by an amount which will vary across each lane. On x86, for
/// example, there is a "psllw" instruction for the former case, but no simple
/// instruction for a general "a << b" operation on vectors.
virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
  return false;
}

/// Returns true if the opcode is a commutative binary operation.
virtual bool isCommutativeBinOp(unsigned Opcode) const {
  // FIXME: This should get its info from the td file.
  switch (Opcode) {
  case ISD::ADD:
  case ISD::SMIN:
  case ISD::SMAX:
  case ISD::UMIN:
  case ISD::UMAX:
  case ISD::MUL:
  case ISD::MULHU:
  case ISD::MULHS:
  case ISD::SMUL_LOHI:
  case ISD::UMUL_LOHI:
  case ISD::FADD:
  case ISD::FMUL:
  case ISD::AND:
  case ISD::OR:
  case ISD::XOR:
  case ISD::SADDO:
  case ISD::UADDO:
  case ISD::ADDC:
  case ISD::ADDE:
  case ISD::SADDSAT:
  case ISD::UADDSAT:
  case ISD::FMINNUM:
  case ISD::FMAXNUM:
  case ISD::FMINNUM_IEEE:
  case ISD::FMAXNUM_IEEE:
  case ISD::FMINIMUM:
  case ISD::FMAXIMUM:
    return true;
  default: return false;
  }
}

/// Return true if the node is a math/logic binary operator.
virtual bool isBinOp(unsigned Opcode) const {
  // A commutative binop must be a binop.
  if (isCommutativeBinOp(Opcode))
    return true;
  // These are non-commutative binops.
  switch (Opcode) {
  case ISD::SUB:
  case ISD::SHL:
  case ISD::SRL:
  case ISD::SRA:
  case ISD::SDIV:
  case ISD::UDIV:
  case ISD::SREM:
  case ISD::UREM:
  case ISD::FSUB:
  case ISD::FDIV:
  case ISD::FREM:
    return true;
  default:
    return false;
  }
}

/// Return true if it's free to truncate a value of type FromTy to type
/// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
/// by referencing its sub-register AX.
/// Targets must return false when FromTy <= ToTy.
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
  return false;
}

/// Return true if a truncation from FromTy to ToTy is permitted when deciding
/// whether a call is in tail position. Typically this means that both results
/// would be assigned to the same register or stack slot, but it could mean
/// the target performs adequate checks of its own before proceeding with the
/// tail call.  Targets must return false when FromTy <= ToTy.
virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
  return false;
}

virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
  return false;
}

virtual bool isProfitableToHoist(Instruction *I) const { return true; }

/// Return true if the extension represented by \p I is free.
/// Unlikely the is[Z|FP]ExtFree family which is based on types,
/// this method can use the context provided by \p I to decide
/// whether or not \p I is free.
/// This method extends the behavior of the is[Z|FP]ExtFree family.
/// In other words, if is[Z|FP]Free returns true, then this method
/// returns true as well. The converse is not true.
/// The target can perform the adequate checks by overriding isExtFreeImpl.
/// \pre \p I must be a sign, zero, or fp extension.
bool isExtFree(const Instruction *I) const {
  switch (I->getOpcode()) {
  case Instruction::FPExt:
    if (isFPExtFree(EVT::getEVT(I->getType()),
                    EVT::getEVT(I->getOperand(0)->getType())))
      return true;
    break;
  case Instruction::ZExt:
    if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
      return true;
    break;
  case Instruction::SExt:
    break;
  default:
    llvm_unreachable("Instruction is not an extension")::llvm::llvm_unreachable_internal("Instruction is not an extension"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2358);
  }
  return isExtFreeImpl(I);
}

/// Return true if \p Load and \p Ext can form an ExtLoad.
/// For example, in AArch64
///   %L = load i8, i8* %ptr
///   %E = zext i8 %L to i32
/// can be lowered into one load instruction
///   ldrb w0, [x0]
bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
               const DataLayout &DL) const {
  EVT VT = getValueType(DL, Ext->getType());
  EVT LoadVT = getValueType(DL, Load->getType());

  // If the load has other users and the truncate is not free, the ext
  // probably isn't free.
  if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
      !isTruncateFree(Ext->getType(), Load->getType()))
    return false;

  // Check whether the target supports casts folded into loads.
  unsigned LType;
  if (isa<ZExtInst>(Ext))
    LType = ISD::ZEXTLOAD;
  else {
    assert(isa<SExtInst>(Ext) && "Unexpected ext type!")((isa<SExtInst>(Ext) && "Unexpected ext type!")
 ? static_cast<void> (0) : __assert_fail ("isa<SExtInst>(Ext) && \"Unexpected ext type!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2385, __PRETTY_FUNCTION__));
    LType = ISD::SEXTLOAD;
  }

  return isLoadExtLegal(LType, VT, LoadVT);
}

/// Return true if any actual instruction that defines a value of type FromTy
/// implicitly zero-extends the value to ToTy in the result register.
///
/// The function should return true when it is likely that the truncate can
/// be freely folded with an instruction defining a value of FromTy. If
/// the defining instruction is unknown (because you're looking at a
/// function argument, PHI, etc.) then the target may require an
/// explicit truncate, which is not necessarily free, but this function
/// does not deal with those cases.
/// Targets must return false when FromTy >= ToTy.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
  return false;
}

virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
  return false;
}

/// Return true if sign-extension from FromTy to ToTy is cheaper than
/// zero-extension.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
  return false;
}

/// Return true if sinking I's operands to the same basic block as I is
/// profitable, e.g. because the operands can be folded into a target
/// instruction during instruction selection. After calling the function
/// \p Ops contains the Uses to sink ordered by dominance (dominating users
/// come first).
virtual bool shouldSinkOperands(Instruction *I,
                                SmallVectorImpl<Use *> &Ops) const {
  return false;
}

/// Return true if the target supplies and combines to a paired load
/// two loaded values of type LoadedType next to each other in memory.
/// RequiredAlignment gives the minimal alignment constraints that must be met
/// to be able to select this paired load.
///
/// This information is *not* used to generate actual paired loads, but it is
/// used to generate a sequence of loads that is easier to combine into a
/// paired load.
/// For instance, something like this:
/// a = load i64* addr
/// b = trunc i64 a to i32
/// c = lshr i64 a, 32
/// d = trunc i64 c to i32
/// will be optimized into:
/// b = load i32* addr1
/// d = load i32* addr2
/// Where addr1 = addr2 +/- sizeof(i32).
///
/// In other words, unless the target performs a post-isel load combining,
/// this information should not be provided because it will generate more
/// loads.
virtual bool hasPairedLoad(EVT /*LoadedType*/,
                           unsigned & /*RequiredAlignment*/) const {
  return false;
}

/// Return true if the target has a vector blend instruction.
virtual bool hasVectorBlend() const { return false; }

/// Get the maximum supported factor for interleaved memory accesses.
/// Default to be the minimum interleave factor: 2.
virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }

/// Lower an interleaved load to target specific intrinsics. Return
/// true on success.
///
/// \p LI is the vector load instruction.
/// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
/// \p Indices is the corresponding indices for each shufflevector.
/// \p Factor is the interleave factor.
virtual bool lowerInterleavedLoad(LoadInst *LI,
                                  ArrayRef<ShuffleVectorInst *> Shuffles,
                                  ArrayRef<unsigned> Indices,
                                  unsigned Factor) const {
  return false;
}

/// Lower an interleaved store to target specific intrinsics. Return
/// true on success.
///
/// \p SI is the vector store instruction.
/// \p SVI is the shufflevector to RE-interleave the stored vector.
/// \p Factor is the interleave factor.
virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
                                   unsigned Factor) const {
  return false;
}

/// Return true if zero-extending the specific node Val to type VT2 is free
/// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
/// because it's folded such as X86 zero-extending loads).
virtual bool isZExtFree(SDValue Val, EVT VT2) const {
  return isZExtFree(Val.getValueType(), VT2);
}

/// Return true if an fpext operation is free (for instance, because
/// single-precision floating-point numbers are implicitly extended to
/// double-precision).
virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
  assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&((SrcVT.isFloatingPoint() && DestVT.isFloatingPoint()
 && "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2496, __PRETTY_FUNCTION__))
         "invalid fpext types")((SrcVT.isFloatingPoint() && DestVT.isFloatingPoint()
 && "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2496, __PRETTY_FUNCTION__));
  return false;
}

/// Return true if an fpext operation input to an \p Opcode operation is free
/// (for instance, because half-precision floating-point numbers are
/// implicitly extended to float-precision) for an FMA instruction.
virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
  assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&((DestVT.isFloatingPoint() && SrcVT.isFloatingPoint()
 && "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2505, __PRETTY_FUNCTION__))
         "invalid fpext types")((DestVT.isFloatingPoint() && SrcVT.isFloatingPoint()
 && "invalid fpext types") ? static_cast<void> (
0) : __assert_fail ("DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() && \"invalid fpext types\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2505, __PRETTY_FUNCTION__));
  return isFPExtFree(DestVT, SrcVT);
}

/// Return true if folding a vector load into ExtVal (a sign, zero, or any
/// extend node) is profitable.
virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }

/// Return true if an fneg operation is free to the point where it is never
/// worthwhile to replace it with a bitwise operation.
virtual bool isFNegFree(EVT VT) const {
  assert(VT.isFloatingPoint())((VT.isFloatingPoint()) ? static_cast<void> (0) : __assert_fail
 ("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2516, __PRETTY_FUNCTION__));
  return false;
}

/// Return true if an fabs operation is free to the point where it is never
/// worthwhile to replace it with a bitwise operation.
virtual bool isFAbsFree(EVT VT) const {
  assert(VT.isFloatingPoint())((VT.isFloatingPoint()) ? static_cast<void> (0) : __assert_fail
 ("VT.isFloatingPoint()", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2523, __PRETTY_FUNCTION__));
  return false;
}

/// Return true if an FMA operation is faster than a pair of fmul and fadd
/// instructions. fmuladd intrinsics will be expanded to FMAs when this method
/// returns true, otherwise fmuladd is expanded to fmul + fadd.
///
/// NOTE: This may be called before legalization on types for which FMAs are
/// not legal, but should return true if those types will eventually legalize
/// to types that support FMAs. After legalization, it will only be called on
/// types that support FMAs (via Legal or Custom actions)
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
  return false;
}

/// Return true if it's profitable to narrow operations of type VT1 to
/// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
/// i32 to i16.
virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
  return false;
}

/// Return true if it is beneficial to convert a load of a constant to
/// just the constant itself.
/// On some targets it might be more efficient to use a combination of
/// arithmetic instructions to materialize the constant instead of loading it
/// from a constant pool.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
                                               Type *Ty) const {
  return false;
}

/// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
/// from this source type with this index. This is needed because
/// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
/// the first element, and only the target knows which lowering is cheap.
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
                                     unsigned Index) const {
  return false;
}

/// Try to convert an extract element of a vector binary operation into an
/// extract element followed by a scalar operation.
virtual bool shouldScalarizeBinop(SDValue VecOp) const {
  return false;
}

/// Return true if extraction of a scalar element from the given vector type
/// at the given index is cheap. For example, if scalar operations occur on
/// the same register file as vector operations, then an extract element may
/// be a sub-register rename rather than an actual instruction.
virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
  return false;
}

/// Try to convert math with an overflow comparison into the corresponding DAG
/// node operation. Targets may want to override this independently of whether
/// the operation is legal/custom for the given type because it may obscure
/// matching of other patterns.
virtual bool shouldFormOverflowOp(unsigned Opcode, EVT VT) const {
  // TODO: The default logic is inherited from code in CodeGenPrepare.
  // The opcode should not make a difference by default?
  if (Opcode != ISD::UADDO)
    return false;

  // Allow the transform as long as we have an integer type that is not
  // obviously illegal and unsupported.
  if (VT.isVector())
    return false;
  return VT.isSimple() || !isOperationExpand(Opcode, VT);
}

// Return true if it is profitable to use a scalar input to a BUILD_VECTOR
// even if the vector itself has multiple uses.
virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
  return false;
}

// Return true if CodeGenPrepare should consider splitting large offset of a
// GEP to make the GEP fit into the addressing mode and can be sunk into the
// same blocks of its users.
virtual bool shouldConsiderGEPOffsetSplit() const { return false; }

//===--------------------------------------------------------------------===//
// Runtime Library hooks
//

/// Rename the default libcall routine name for the specified libcall.
void setLibcallName(RTLIB::Libcall Call, const char *Name) {
  LibcallRoutineNames[Call] = Name;
}

/// Get the libcall routine name for the specified libcall.
const char *getLibcallName(RTLIB::Libcall Call) const {
  return LibcallRoutineNames[Call];
}

/// Override the default CondCode to be used to test the result of the
/// comparison libcall against zero.
void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
  CmpLibcallCCs[Call] = CC;
}

/// Get the CondCode that's to be used to test the result of the comparison
/// libcall against zero.
ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
  return CmpLibcallCCs[Call];
}

/// Set the CallingConv that should be used for the specified libcall.
void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
  LibcallCallingConvs[Call] = CC;
}

/// Get the CallingConv that should be used for the specified libcall.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
  return LibcallCallingConvs[Call];
}

/// Execute target specific actions to finalize target lowering.
/// This is used to set extra flags in MachineFrameInformation and freezing
/// the set of reserved registers.
/// The default implementation just freezes the set of reserved registers.
virtual void finalizeLowering(MachineFunction &MF) const;

2649private:
const TargetMachine &TM;

/// Tells the code generator that the target has multiple (allocatable)
/// condition registers that can be used to store the results of comparisons
/// for use by selects and conditional branches. With multiple condition
/// registers, the code generator will not aggressively sink comparisons into
/// the blocks of their users.
bool HasMultipleConditionRegisters;

/// Tells the code generator that the target has BitExtract instructions.
/// The code generator will aggressively sink "shift"s into the blocks of
/// their users if the users will generate "and" instructions which can be
/// combined with "shift" to BitExtract instructions.
bool HasExtractBitsInsn;

/// Tells the code generator to bypass slow divide or remainder
/// instructions. For example, BypassSlowDivWidths[32,8] tells the code
/// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
/// div/rem when the operands are positive and less than 256.
DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;

/// Tells the code generator that it shouldn't generate extra flow control
/// instructions and should attempt to combine flow control instructions via
/// predication.
bool JumpIsExpensive;

/// This target prefers to use _setjmp to implement llvm.setjmp.
///
/// Defaults to false.
bool UseUnderscoreSetJmp;

/// This target prefers to use _longjmp to implement llvm.longjmp.
///
/// Defaults to false.
bool UseUnderscoreLongJmp;

/// Information about the contents of the high-bits in boolean values held in
/// a type wider than i1. See getBooleanContents.
BooleanContent BooleanContents;

/// Information about the contents of the high-bits in boolean values held in
/// a type wider than i1. See getBooleanContents.
BooleanContent BooleanFloatContents;

/// Information about the contents of the high-bits in boolean vector values
/// when the element type is wider than i1. See getBooleanContents.
BooleanContent BooleanVectorContents;

/// The target scheduling preference: shortest possible total cycles or lowest
/// register usage.
Sched::Preference SchedPreferenceInfo;

/// The minimum alignment that any argument on the stack needs to have.
Align MinStackArgumentAlignment;

/// The minimum function alignment (used when optimizing for size, and to
/// prevent explicitly provided alignment from leading to incorrect code).
Align MinFunctionAlignment;

/// The preferred function alignment (used when alignment unspecified and
/// optimizing for speed).
Align PrefFunctionAlignment;

/// The preferred loop alignment (in log2 bot in bytes).
Align PrefLoopAlignment;

/// Size in bits of the maximum atomics size the backend supports.
/// Accesses larger than this will be expanded by AtomicExpandPass.
unsigned MaxAtomicSizeInBitsSupported;

/// Size in bits of the minimum cmpxchg or ll/sc operation the
/// backend supports.
unsigned MinCmpXchgSizeInBits;

/// This indicates if the target supports unaligned atomic operations.
bool SupportsUnalignedAtomics;

/// If set to a physical register, this specifies the register that
/// llvm.savestack/llvm.restorestack should save and restore.
unsigned StackPointerRegisterToSaveRestore;

/// This indicates the default register class to use for each ValueType the
/// target supports natively.
const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];

/// This indicates the "representative" register class to use for each
/// ValueType the target supports natively. This information is used by the
/// scheduler to track register pressure. By default, the representative
/// register class is the largest legal super-reg register class of the
/// register class of the specified type. e.g. On x86, i8, i16, and i32's
/// representative class would be GR32.
const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];

/// This indicates the "cost" of the "representative" register class for each
/// ValueType. The cost is used by the scheduler to approximate register
/// pressure.
uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];

/// For any value types we are promoting or expanding, this contains the value
/// type that we are changing to.  For Expanded types, this contains one step
/// of the expand (e.g. i64 -> i32), even if there are multiple steps required
/// (e.g. i64 -> i16).  For types natively supported by the system, this holds
/// the same type (e.g. i32 -> i32).
MVT TransformToType[MVT::LAST_VALUETYPE];

/// For each operation and each value type, keep a LegalizeAction that
/// indicates how instruction selection should deal with the operation.  Most
/// operations are Legal (aka, supported natively by the target), but
/// operations that are not should be described.  Note that operations on
/// non-legal value types are not described here.
LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];

/// For each load extension type and each value type, keep a LegalizeAction
/// that indicates how instruction selection should deal with a load of a
/// specific value type and extension type. Uses 4-bits to store the action
/// for each of the 4 load ext types.
uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];

/// For each value type pair keep a LegalizeAction that indicates whether a
/// truncating store of a specific value type and truncating type is legal.
LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];

/// For each indexed mode and each value type, keep a pair of LegalizeAction
/// that indicates how instruction selection should deal with the load /
/// store.
///
/// The first dimension is the value_type for the reference. The second
/// dimension represents the various modes for load store.
uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];

/// For each condition code (ISD::CondCode) keep a LegalizeAction that
/// indicates how instruction selection should deal with the condition code.
///
/// Because each CC action takes up 4 bits, we need to have the array size be
/// large enough to fit all of the value types. This can be done by rounding
/// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];

ValueTypeActionImpl ValueTypeActions;

2792private:
LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;

/// Targets can specify ISD nodes that they would like PerformDAGCombine
/// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
/// array.
unsigned char
TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT8-1)/CHAR_BIT8];

/// For operations that must be promoted to a specific type, this holds the
/// destination type.  This map should be sparse, so don't hold it as an
/// array.
///
/// Targets add entries to this map with AddPromotedToType(..), clients access
/// this with getTypeToPromoteTo(..).
std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
  PromoteToType;

/// Stores the name each libcall.
const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL + 1];

/// The ISD::CondCode that should be used to test the result of each of the
/// comparison libcall against zero.
ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];

/// Stores the CallingConv that should be used for each libcall.
CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];

/// Set default libcall names and calling conventions.
void InitLibcalls(const Triple &TT);

2823protected:
/// Return true if the extension represented by \p I is free.
/// \pre \p I is a sign, zero, or fp extension and
///      is[Z|FP]ExtFree of the related types is not true.
virtual bool isExtFreeImpl(const Instruction *I) const { return false; }

/// Depth that GatherAllAliases should should continue looking for chain
/// dependencies when trying to find a more preferable chain. As an
/// approximation, this should be more than the number of consecutive stores
/// expected to be merged.
unsigned GatherAllAliasesMaxDepth;

/// \brief Specify maximum number of store instructions per memset call.
///
/// When lowering \@llvm.memset this field specifies the maximum number of
/// store operations that may be substituted for the call to memset. Targets
/// must set this value based on the cost threshold for that target. Targets
/// should assume that the memset will be done using as many of the largest
/// store operations first, followed by smaller ones, if necessary, per
/// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
/// with 16-bit alignment would result in four 2-byte stores and one 1-byte
/// store.  This only applies to setting a constant array of a constant size.
unsigned MaxStoresPerMemset;
/// Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemsetOptSize;

/// \brief Specify maximum number of store instructions per memcpy call.
///
/// When lowering \@llvm.memcpy this field specifies the maximum number of
/// store operations that may be substituted for a call to memcpy. Targets
/// must set this value based on the cost threshold for that target. Targets
/// should assume that the memcpy will be done using as many of the largest
/// store operations first, followed by smaller ones, if necessary, per
/// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
/// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
/// and one 1-byte store. This only applies to copying a constant array of
/// constant size.
unsigned MaxStoresPerMemcpy;
/// Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemcpyOptSize;
/// \brief Specify max number of store instructions to glue in inlined memcpy.
///
/// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
/// of store instructions to keep together. This helps in pairing and
//  vectorization later on.
unsigned MaxGluedStoresPerMemcpy = 0;

/// \brief Specify maximum number of load instructions per memcmp call.
///
/// When lowering \@llvm.memcmp this field specifies the maximum number of
/// pairs of load operations that may be substituted for a call to memcmp.
/// Targets must set this value based on the cost threshold for that target.
/// Targets should assume that the memcmp will be done using as many of the
/// largest load operations first, followed by smaller ones, if necessary, per
/// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
/// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
/// and one 1-byte load. This only applies to copying a constant array of
/// constant size.
unsigned MaxLoadsPerMemcmp;
/// Likewise for functions with the OptSize attribute.
unsigned MaxLoadsPerMemcmpOptSize;

/// \brief Specify maximum number of store instructions per memmove call.
///
/// When lowering \@llvm.memmove this field specifies the maximum number of
/// store instructions that may be substituted for a call to memmove. Targets
/// must set this value based on the cost threshold for that target. Targets
/// should assume that the memmove will be done using as many of the largest
/// store operations first, followed by smaller ones, if necessary, per
/// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
/// with 8-bit alignment would result in nine 1-byte stores.  This only
/// applies to copying a constant array of constant size.
unsigned MaxStoresPerMemmove;
/// Likewise for functions with the OptSize attribute.
unsigned MaxStoresPerMemmoveOptSize;

/// Tells the code generator that select is more expensive than a branch if
/// the branch is usually predicted right.
bool PredictableSelectIsExpensive;

/// \see enableExtLdPromotion.
bool EnableExtLdPromotion;

/// Return true if the value types that can be represented by the specified
/// register class are all legal.
bool isLegalRC(const TargetRegisterInfo &TRI,
               const TargetRegisterClass &RC) const;

/// Replace/modify any TargetFrameIndex operands with a targte-dependent
/// sequence of memory operands that is recognized by PrologEpilogInserter.
MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
                                  MachineBasicBlock *MBB) const;

/// Replace/modify the XRay custom event operands with target-dependent
/// details.
MachineBasicBlock *emitXRayCustomEvent(MachineInstr &MI,
                                       MachineBasicBlock *MBB) const;

/// Replace/modify the XRay typed event operands with target-dependent
/// details.
MachineBasicBlock *emitXRayTypedEvent(MachineInstr &MI,
                                      MachineBasicBlock *MBB) const;
2925};

2927/// This class defines information used to lower LLVM code to legal SelectionDAG
2928/// operators that the target instruction selector can accept natively.
2929///
2930/// This class also defines callbacks that targets must implement to lower
2931/// target-specific constructs to SelectionDAG operators.
2932class TargetLowering : public TargetLoweringBase {
2933public:
struct DAGCombinerInfo;
struct MakeLibCallOptions;

TargetLowering(const TargetLowering &) = delete;
TargetLowering &operator=(const TargetLowering &) = delete;

/// NOTE: The TargetMachine owns TLOF.
explicit TargetLowering(const TargetMachine &TM);

bool isPositionIndependent() const;

virtual bool isSDNodeSourceOfDivergence(const SDNode *N,
                                        FunctionLoweringInfo *FLI,
                                        LegacyDivergenceAnalysis *DA) const {
  return false;
}

virtual bool isSDNodeAlwaysUniform(const SDNode * N) const {
  return false;
}

/// Returns true by value, base pointer and offset pointer and addressing mode
/// by reference if the node's address can be legally represented as
/// pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
                                       SDValue &/*Offset*/,
                                       ISD::MemIndexedMode &/*AM*/,
                                       SelectionDAG &/*DAG*/) const {
  return false;
}

/// Returns true by value, base pointer and offset pointer and addressing mode
/// by reference if this node can be combined with a load / store to form a
/// post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
                                        SDValue &/*Base*/,
                                        SDValue &/*Offset*/,
                                        ISD::MemIndexedMode &/*AM*/,
                                        SelectionDAG &/*DAG*/) const {
  return false;
}

/// Returns true if the specified base+offset is a legal indexed addressing
/// mode for this target. \p MI is the load or store instruction that is being
/// considered for transformation.
virtual bool isIndexingLegal(MachineInstr &MI, Register Base, Register Offset,
                             bool IsPre, MachineRegisterInfo &MRI) const {
  return false;
}

/// Return the entry encoding for a jump table in the current function.  The
/// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
virtual unsigned getJumpTableEncoding() const;

virtual const MCExpr *
LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
                          const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
                          MCContext &/*Ctx*/) const {
  llvm_unreachable("Need to implement this hook if target has custom JTIs")::llvm::llvm_unreachable_internal("Need to implement this hook if target has custom JTIs"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 2992);
}

/// Returns relocation base for the given PIC jumptable.
virtual SDValue getPICJumpTableRelocBase(SDValue Table,
                                         SelectionDAG &DAG) const;

/// This returns the relocation base for the given PIC jumptable, the same as
/// getPICJumpTableRelocBase, but as an MCExpr.
virtual const MCExpr *
getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
                             unsigned JTI, MCContext &Ctx) const;

/// Return true if folding a constant offset with the given GlobalAddress is
/// legal.  It is frequently not legal in PIC relocation models.
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;

bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
                          SDValue &Chain) const;

void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
                         SDValue &NewRHS, ISD::CondCode &CCCode,
                         const SDLoc &DL, const SDValue OldLHS,
                         const SDValue OldRHS) const;

/// Returns a pair of (return value, chain).
/// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
                                        EVT RetVT, ArrayRef<SDValue> Ops,
                                        MakeLibCallOptions CallOptions,
                                        const SDLoc &dl) const;

/// Check whether parameters to a call that are passed in callee saved
/// registers are the same as from the calling function.  This needs to be
/// checked for tail call eligibility.
bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
    const uint32_t *CallerPreservedMask,
    const SmallVectorImpl<CCValAssign> &ArgLocs,
    const SmallVectorImpl<SDValue> &OutVals) const;

//===--------------------------------------------------------------------===//
// TargetLowering Optimization Methods
//

/// A convenience struct that encapsulates a DAG, and two SDValues for
/// returning information from TargetLowering to its clients that want to
/// combine.
struct TargetLoweringOpt {
  SelectionDAG &DAG;
  bool LegalTys;
  bool LegalOps;
  SDValue Old;
  SDValue New;

  explicit TargetLoweringOpt(SelectionDAG &InDAG,
                             bool LT, bool LO) :
    DAG(InDAG), LegalTys(LT), LegalOps(LO) {}

  bool LegalTypes() const { return LegalTys; }
  bool LegalOperations() const { return LegalOps; }

  bool CombineTo(SDValue O, SDValue N) {
    Old = O;
    New = N;
    return true;
  }
};

/// Determines the optimal series of memory ops to replace the memset / memcpy.
/// Return true if the number of memory ops is below the threshold (Limit).
/// It returns the types of the sequence of memory ops to perform
/// memset / memcpy by reference.
bool findOptimalMemOpLowering(std::vector<EVT> &MemOps,
                              unsigned Limit, uint64_t Size,
                              unsigned DstAlign, unsigned SrcAlign,
                              bool IsMemset,
                              bool ZeroMemset,
                              bool MemcpyStrSrc,
                              bool AllowOverlap,
                              unsigned DstAS, unsigned SrcAS,
                              const AttributeList &FuncAttributes) const;

/// Check to see if the specified operand of the specified instruction is a
/// constant integer.  If so, check to see if there are any bits set in the
/// constant that are not demanded.  If so, shrink the constant and return
/// true.
bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
                            TargetLoweringOpt &TLO) const;

// Target hook to do target-specific const optimization, which is called by
// ShrinkDemandedConstant. This function should return true if the target
// doesn't want ShrinkDemandedConstant to further optimize the constant.
virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
                                          TargetLoweringOpt &TLO) const {
  return false;
}

/// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.  This
/// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
/// generalized for targets with other types of implicit widening casts.
bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
                      TargetLoweringOpt &TLO) const;

/// Look at Op.  At this point, we know that only the DemandedBits bits of the
/// result of Op are ever used downstream.  If we can use this information to
/// simplify Op, create a new simplified DAG node and return true, returning
/// the original and new nodes in Old and New.  Otherwise, analyze the
/// expression and return a mask of KnownOne and KnownZero bits for the
/// expression (used to simplify the caller).  The KnownZero/One bits may only
/// be accurate for those bits in the Demanded masks.
/// \p AssumeSingleUse When this parameter is true, this function will
///    attempt to simplify \p Op even if there are multiple uses.
///    Callers are responsible for correctly updating the DAG based on the
///    results of this function, because simply replacing replacing TLO.Old
///    with TLO.New will be incorrect when this parameter is true and TLO.Old
///    has multiple uses.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
                          const APInt &DemandedElts, KnownBits &Known,
                          TargetLoweringOpt &TLO, unsigned Depth = 0,
                          bool AssumeSingleUse = false) const;

/// Helper wrapper around SimplifyDemandedBits, demanding all elements.
/// Adds Op back to the worklist upon success.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
                          KnownBits &Known, TargetLoweringOpt &TLO,
                          unsigned Depth = 0,
                          bool AssumeSingleUse = false) const;

/// Helper wrapper around SimplifyDemandedBits.
/// Adds Op back to the worklist upon success.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
                          DAGCombinerInfo &DCI) const;

/// More limited version of SimplifyDemandedBits that can be used to "look
/// through" ops that don't contribute to the DemandedBits/DemandedElts -
/// bitwise ops etc.
SDValue SimplifyMultipleUseDemandedBits(SDValue Op, const APInt &DemandedBits,
                                        const APInt &DemandedElts,
                                        SelectionDAG &DAG,
                                        unsigned Depth) const;

/// Look at Vector Op. At this point, we know that only the DemandedElts
/// elements of the result of Op are ever used downstream.  If we can use
/// this information to simplify Op, create a new simplified DAG node and
/// return true, storing the original and new nodes in TLO.
/// Otherwise, analyze the expression and return a mask of KnownUndef and
/// KnownZero elements for the expression (used to simplify the caller).
/// The KnownUndef/Zero elements may only be accurate for those bits
/// in the DemandedMask.
/// \p AssumeSingleUse When this parameter is true, this function will
///    attempt to simplify \p Op even if there are multiple uses.
///    Callers are responsible for correctly updating the DAG based on the
///    results of this function, because simply replacing replacing TLO.Old
///    with TLO.New will be incorrect when this parameter is true and TLO.Old
///    has multiple uses.
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
                                APInt &KnownUndef, APInt &KnownZero,
                                TargetLoweringOpt &TLO, unsigned Depth = 0,
                                bool AssumeSingleUse = false) const;

/// Helper wrapper around SimplifyDemandedVectorElts.
/// Adds Op back to the worklist upon success.
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
                                APInt &KnownUndef, APInt &KnownZero,
                                DAGCombinerInfo &DCI) const;

/// Determine which of the bits specified in Mask are known to be either zero
/// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
/// argument allows us to only collect the known bits that are shared by the
/// requested vector elements.
virtual void computeKnownBitsForTargetNode(const SDValue Op,
                                           KnownBits &Known,
                                           const APInt &DemandedElts,
                                           const SelectionDAG &DAG,
                                           unsigned Depth = 0) const;
/// Determine which of the bits specified in Mask are known to be either zero
/// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
/// argument allows us to only collect the known bits that are shared by the
/// requested vector elements. This is for GISel.
virtual void computeKnownBitsForTargetInstr(GISelKnownBits &Analysis,
                                            Register R, KnownBits &Known,
                                            const APInt &DemandedElts,
                                            const MachineRegisterInfo &MRI,
                                            unsigned Depth = 0) const;

/// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
/// Default implementation computes low bits based on alignment
/// information. This should preserve known bits passed into it.
virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
                                           KnownBits &Known,
                                           const APInt &DemandedElts,
                                           const SelectionDAG &DAG,
                                           unsigned Depth = 0) const;

/// This method can be implemented by targets that want to expose additional
/// information about sign bits to the DAG Combiner. The DemandedElts
/// argument allows us to only collect the minimum sign bits that are shared
/// by the requested vector elements.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
                                                 const APInt &DemandedElts,
                                                 const SelectionDAG &DAG,
                                                 unsigned Depth = 0) const;

/// Attempt to simplify any target nodes based on the demanded vector
/// elements, returning true on success. Otherwise, analyze the expression and
/// return a mask of KnownUndef and KnownZero elements for the expression
/// (used to simplify the caller). The KnownUndef/Zero elements may only be
/// accurate for those bits in the DemandedMask.
virtual bool SimplifyDemandedVectorEltsForTargetNode(
    SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
    APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;

/// Attempt to simplify any target nodes based on the demanded bits/elts,
/// returning true on success. Otherwise, analyze the
/// expression and return a mask of KnownOne and KnownZero bits for the
/// expression (used to simplify the caller).  The KnownZero/One bits may only
/// be accurate for those bits in the Demanded masks.
virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op,
                                               const APInt &DemandedBits,
                                               const APInt &DemandedElts,
                                               KnownBits &Known,
                                               TargetLoweringOpt &TLO,
                                               unsigned Depth = 0) const;

/// More limited version of SimplifyDemandedBits that can be used to "look
/// through" ops that don't contribute to the DemandedBits/DemandedElts -
/// bitwise ops etc.
virtual SDValue SimplifyMultipleUseDemandedBitsForTargetNode(
    SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts,
    SelectionDAG &DAG, unsigned Depth) const;

/// Tries to build a legal vector shuffle using the provided parameters
/// or equivalent variations. The Mask argument maybe be modified as the
/// function tries different variations.
/// Returns an empty SDValue if the operation fails.
SDValue buildLegalVectorShuffle(EVT VT, const SDLoc &DL, SDValue N0,
                                SDValue N1, MutableArrayRef<int> Mask,
                                SelectionDAG &DAG) const;

/// This method returns the constant pool value that will be loaded by LD.
/// NOTE: You must check for implicit extensions of the constant by LD.
virtual const Constant *getTargetConstantFromLoad(LoadSDNode *LD) const;

/// If \p SNaN is false, \returns true if \p Op is known to never be any
/// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
/// NaN.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
                                          const SelectionDAG &DAG,
                                          bool SNaN = false,
                                          unsigned Depth = 0) const;
struct DAGCombinerInfo {
  void *DC;  // The DAG Combiner object.
  CombineLevel Level;
  bool CalledByLegalizer;

public:
  SelectionDAG &DAG;

  DAGCombinerInfo(SelectionDAG &dag, CombineLevel level,  bool cl, void *dc)
    : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}

  bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
  bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
  bool isAfterLegalizeDAG() const {
    return Level == AfterLegalizeDAG;
  }
  CombineLevel getDAGCombineLevel() { return Level; }
  bool isCalledByLegalizer() const { return CalledByLegalizer; }

  void AddToWorklist(SDNode *N);
  SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
  SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
  SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);

  void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
};

/// Return if the N is a constant or constant vector equal to the true value
/// from getBooleanContents().
bool isConstTrueVal(const SDNode *N) const;

/// Return if the N is a constant or constant vector equal to the false value
/// from getBooleanContents().
bool isConstFalseVal(const SDNode *N) const;

/// Return if \p N is a True value when extended to \p VT.
bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;

/// Try to simplify a setcc built with the specified operands and cc. If it is
/// unable to simplify it, return a null SDValue.
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
                      bool foldBooleans, DAGCombinerInfo &DCI,
                      const SDLoc &dl) const;

// For targets which wrap address, unwrap for analysis.
virtual SDValue unwrapAddress(SDValue N) const { return N; }

/// Returns true (and the GlobalValue and the offset) if the node is a
/// GlobalAddress + offset.
virtual bool
isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;

/// This method will be invoked for all target nodes and for any
/// target-independent nodes that the target has registered with invoke it
/// for.
///
/// The semantics are as follows:
/// Return Value:
///   SDValue.Val == 0   - No change was made
///   SDValue.Val == N   - N was replaced, is dead, and is already handled.
///   otherwise          - N should be replaced by the returned Operand.
///
/// In addition, methods provided by DAGCombinerInfo may be used to perform
/// more complex transformations.
///
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;

/// Return true if it is profitable to move this shift by a constant amount
/// though its operand, adjusting any immediate operands as necessary to
/// preserve semantics. This transformation may not be desirable if it
/// disrupts a particularly auspicious target-specific tree (e.g. bitfield
/// extraction in AArch64). By default, it returns true.
///
/// @param N the shift node
/// @param Level the current DAGCombine legalization level.
virtual bool isDesirableToCommuteWithShift(const SDNode *N,
                                           CombineLevel Level) const {
  return true;
}

// Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
// to a shuffle and a truncate.
// Example of such a combine:
// v4i32 build_vector((extract_elt V, 1),
//                    (extract_elt V, 3),
//                    (extract_elt V, 5),
//                    (extract_elt V, 7))
//  -->
// v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
    ArrayRef<int> ShuffleMask, EVT SrcVT, EVT TruncVT) const {
  return false;
}

/// Return true if the target has native support for the specified value type
/// and it is 'desirable' to use the type for the given node type. e.g. On x86
/// i16 is legal, but undesirable since i16 instruction encodings are longer
/// and some i16 instructions are slow.
virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
  // By default, assume all legal types are desirable.
  return isTypeLegal(VT);
}

/// Return true if it is profitable for dag combiner to transform a floating
/// point op of specified opcode to a equivalent op of an integer
/// type. e.g. f32 load -> i32 load can be profitable on ARM.
virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
                                               EVT /*VT*/) const {
  return false;
}

/// This method query the target whether it is beneficial for dag combiner to
/// promote the specified node. If true, it should return the desired
/// promotion type by reference.
virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
  return false;
}

/// Return true if the target supports swifterror attribute. It optimizes
/// loads and stores to reading and writing a specific register.
virtual bool supportSwiftError() const {
  return false;
}

/// Return true if the target supports that a subset of CSRs for the given
/// machine function is handled explicitly via copies.
virtual bool supportSplitCSR(MachineFunction *MF) const {
  return false;
}

/// Perform necessary initialization to handle a subset of CSRs explicitly
/// via copies. This function is called at the beginning of instruction
/// selection.
virtual void initializeSplitCSR(MachineBasicBlock *Entry) const {
  llvm_unreachable("Not Implemented")::llvm::llvm_unreachable_internal("Not Implemented", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3376);
}

/// Insert explicit copies in entry and exit blocks. We copy a subset of
/// CSRs to virtual registers in the entry block, and copy them back to
/// physical registers in the exit blocks. This function is called at the end
/// of instruction selection.
virtual void insertCopiesSplitCSR(
    MachineBasicBlock *Entry,
    const SmallVectorImpl<MachineBasicBlock *> &Exits) const {
  llvm_unreachable("Not Implemented")::llvm::llvm_unreachable_internal("Not Implemented", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3386);
}

/// Return 1 if we can compute the negated form of the specified expression
/// for the same cost as the expression itself, or 2 if we can compute the
/// negated form more cheaply than the expression itself. Else return 0.
virtual char isNegatibleForFree(SDValue Op, SelectionDAG &DAG,
                                bool LegalOperations, bool ForCodeSize,
                                unsigned Depth = 0) const;

/// If isNegatibleForFree returns true, return the newly negated expression.
virtual SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG,
                                     bool LegalOperations, bool ForCodeSize,
                                     unsigned Depth = 0) const;

//===--------------------------------------------------------------------===//
// Lowering methods - These methods must be implemented by targets so that
// the SelectionDAGBuilder code knows how to lower these.
//

/// This hook must be implemented to lower the incoming (formal) arguments,
/// described by the Ins array, into the specified DAG. The implementation
/// should fill in the InVals array with legal-type argument values, and
/// return the resulting token chain value.
virtual SDValue LowerFormalArguments(
    SDValue /*Chain*/, CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
    const SmallVectorImpl<ISD::InputArg> & /*Ins*/, const SDLoc & /*dl*/,
    SelectionDAG & /*DAG*/, SmallVectorImpl<SDValue> & /*InVals*/) const {
  llvm_unreachable("Not Implemented")::llvm::llvm_unreachable_internal("Not Implemented", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3414);
}

/// This structure contains all information that is necessary for lowering
/// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
/// needs to lower a call, and targets will see this struct in their LowerCall
/// implementation.
struct CallLoweringInfo {
  SDValue Chain;
  Type *RetTy = nullptr;
  bool RetSExt           : 1;
  bool RetZExt           : 1;
  bool IsVarArg          : 1;
  bool IsInReg           : 1;
  bool DoesNotReturn     : 1;
  bool IsReturnValueUsed : 1;
  bool IsConvergent      : 1;
  bool IsPatchPoint      : 1;

  // IsTailCall should be modified by implementations of
  // TargetLowering::LowerCall that perform tail call conversions.
  bool IsTailCall = false;

  // Is Call lowering done post SelectionDAG type legalization.
  bool IsPostTypeLegalization = false;

  unsigned NumFixedArgs = -1;
  CallingConv::ID CallConv = CallingConv::C;
  SDValue Callee;
  ArgListTy Args;
  SelectionDAG &DAG;
  SDLoc DL;
  ImmutableCallSite CS;
  SmallVector<ISD::OutputArg, 32> Outs;
  SmallVector<SDValue, 32> OutVals;
  SmallVector<ISD::InputArg, 32> Ins;
  SmallVector<SDValue, 4> InVals;

  CallLoweringInfo(SelectionDAG &DAG)
      : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
        DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
        IsPatchPoint(false), DAG(DAG) {}

  CallLoweringInfo &setDebugLoc(const SDLoc &dl) {
    DL = dl;
    return *this;
  }

  CallLoweringInfo &setChain(SDValue InChain) {
    Chain = InChain;
    return *this;
  }

  // setCallee with target/module-specific attributes
  CallLoweringInfo &setLibCallee(CallingConv::ID CC, Type *ResultType,
                                 SDValue Target, ArgListTy &&ArgsList) {
    RetTy = ResultType;
    Callee = Target;
    CallConv = CC;
    NumFixedArgs = ArgsList.size();
    Args = std::move(ArgsList);

    DAG.getTargetLoweringInfo().markLibCallAttributes(
        &(DAG.getMachineFunction()), CC, Args);
    return *this;
  }

  CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
                              SDValue Target, ArgListTy &&ArgsList) {
    RetTy = ResultType;
    Callee = Target;
    CallConv = CC;
    NumFixedArgs = ArgsList.size();
    Args = std::move(ArgsList);
    return *this;
  }

  CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
                              SDValue Target, ArgListTy &&ArgsList,
                              ImmutableCallSite Call) {
    RetTy = ResultType;

    IsInReg = Call.hasRetAttr(Attribute::InReg);
    DoesNotReturn =
        Call.doesNotReturn() ||
        (!Call.isInvoke() &&
         isa<UnreachableInst>(Call.getInstruction()->getNextNode()));
    IsVarArg = FTy->isVarArg();
    IsReturnValueUsed = !Call.getInstruction()->use_empty();
    RetSExt = Call.hasRetAttr(Attribute::SExt);
    RetZExt = Call.hasRetAttr(Attribute::ZExt);

    Callee = Target;

    CallConv = Call.getCallingConv();
    NumFixedArgs = FTy->getNumParams();
    Args = std::move(ArgsList);

    CS = Call;

    return *this;
  }

  CallLoweringInfo &setInRegister(bool Value = true) {
    IsInReg = Value;
    return *this;
  }

  CallLoweringInfo &setNoReturn(bool Value = true) {
    DoesNotReturn = Value;
    return *this;
  }

  CallLoweringInfo &setVarArg(bool Value = true) {
    IsVarArg = Value;
    return *this;
  }

  CallLoweringInfo &setTailCall(bool Value = true) {
    IsTailCall = Value;
    return *this;
  }

  CallLoweringInfo &setDiscardResult(bool Value = true) {
    IsReturnValueUsed = !Value;
    return *this;
  }

  CallLoweringInfo &setConvergent(bool Value = true) {
    IsConvergent = Value;
    return *this;
  }

  CallLoweringInfo &setSExtResult(bool Value = true) {
    RetSExt = Value;
    return *this;
  }

  CallLoweringInfo &setZExtResult(bool Value = true) {
    RetZExt = Value;
    return *this;
  }

  CallLoweringInfo &setIsPatchPoint(bool Value = true) {
    IsPatchPoint = Value;
    return *this;
  }

  CallLoweringInfo &setIsPostTypeLegalization(bool Value=true) {
    IsPostTypeLegalization = Value;
    return *this;
  }

  ArgListTy &getArgs() {
    return Args;
  }
};

/// This structure is used to pass arguments to makeLibCall function.
struct MakeLibCallOptions {
  // By passing type list before soften to makeLibCall, the target hook
  // shouldExtendTypeInLibCall can get the original type before soften.
  ArrayRef<EVT> OpsVTBeforeSoften;
  EVT RetVTBeforeSoften;
  bool IsSExt : 1;
  bool DoesNotReturn : 1;
  bool IsReturnValueUsed : 1;
  bool IsPostTypeLegalization : 1;
  bool IsSoften : 1;

  MakeLibCallOptions()
      : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
        IsPostTypeLegalization(false), IsSoften(false) {}

  MakeLibCallOptions &setSExt(bool Value = true) {
    IsSExt = Value;
    return *this;
  }

  MakeLibCallOptions &setNoReturn(bool Value = true) {
    DoesNotReturn = Value;
    return *this;
  }

  MakeLibCallOptions &setDiscardResult(bool Value = true) {
    IsReturnValueUsed = !Value;
    return *this;
  }

  MakeLibCallOptions &setIsPostTypeLegalization(bool Value = true) {
    IsPostTypeLegalization = Value;
    return *this;
  }

  MakeLibCallOptions &setTypeListBeforeSoften(ArrayRef<EVT> OpsVT, EVT RetVT,
                                              bool Value = true) {
    OpsVTBeforeSoften = OpsVT;
    RetVTBeforeSoften = RetVT;
    IsSoften = Value;
    return *this;
  }
};

/// This function lowers an abstract call to a function into an actual call.
/// This returns a pair of operands.  The first element is the return value
/// for the function (if RetTy is not VoidTy).  The second element is the
/// outgoing token chain. It calls LowerCall to do the actual lowering.
std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;

/// This hook must be implemented to lower calls into the specified
/// DAG. The outgoing arguments to the call are described by the Outs array,
/// and the values to be returned by the call are described by the Ins
/// array. The implementation should fill in the InVals array with legal-type
/// return values from the call, and return the resulting token chain value.
virtual SDValue
  LowerCall(CallLoweringInfo &/*CLI*/,
            SmallVectorImpl<SDValue> &/*InVals*/) const {
  llvm_unreachable("Not Implemented")::llvm::llvm_unreachable_internal("Not Implemented", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3631);
}

/// Target-specific cleanup for formal ByVal parameters.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}

/// This hook should be implemented to check whether the return values
/// described by the Outs array can fit into the return registers.  If false
/// is returned, an sret-demotion is performed.
virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
                            MachineFunction &/*MF*/, bool /*isVarArg*/,
             const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
             LLVMContext &/*Context*/) const
{
  // Return true by default to get preexisting behavior.
  return true;
}

/// This hook must be implemented to lower outgoing return values, described
/// by the Outs array, into the specified DAG. The implementation should
/// return the resulting token chain value.
virtual SDValue LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
                            bool /*isVarArg*/,
                            const SmallVectorImpl<ISD::OutputArg> & /*Outs*/,
                            const SmallVectorImpl<SDValue> & /*OutVals*/,
                            const SDLoc & /*dl*/,
                            SelectionDAG & /*DAG*/) const {
  llvm_unreachable("Not Implemented")::llvm::llvm_unreachable_internal("Not Implemented", "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3658);
}

/// Return true if result of the specified node is used by a return node
/// only. It also compute and return the input chain for the tail call.
///
/// This is used to determine whether it is possible to codegen a libcall as
/// tail call at legalization time.
virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
  return false;
}

/// Return true if the target may be able emit the call instruction as a tail
/// call. This is used by optimization passes to determine if it's profitable
/// to duplicate return instructions to enable tailcall optimization.
virtual bool mayBeEmittedAsTailCall(const CallInst *) const {
  return false;
}

/// Return the builtin name for the __builtin___clear_cache intrinsic
/// Default is to invoke the clear cache library call
virtual const char * getClearCacheBuiltinName() const {
  return "__clear_cache";
}

/// Return the register ID of the name passed in. Used by named register
/// global variables extension. There is no target-independent behaviour
/// so the default action is to bail.
virtual Register getRegisterByName(const char* RegName, EVT VT,
                                   const MachineFunction &MF) const {
  report_fatal_error("Named registers not implemented for this target");
}

/// Return the type that should be used to zero or sign extend a
/// zeroext/signext integer return value.  FIXME: Some C calling conventions
/// require the return type to be promoted, but this is not true all the time,
/// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
/// conventions. The frontend should handle this and include all of the
/// necessary information.
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT,
                                     ISD::NodeType /*ExtendKind*/) const {
  EVT MinVT = getRegisterType(Context, MVT::i32);
  return VT.bitsLT(MinVT) ? MinVT : VT;
}

/// For some targets, an LLVM struct type must be broken down into multiple
/// simple types, but the calling convention specifies that the entire struct
/// must be passed in a block of consecutive registers.
virtual bool
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
                                          bool isVarArg) const {
  return false;
}

/// For most targets, an LLVM type must be broken down into multiple
/// smaller types. Usually the halves are ordered according to the endianness
/// but for some platform that would break. So this method will default to
/// matching the endianness but can be overridden.
virtual bool
shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout &DL) const {
  return DL.isLittleEndian();
}

/// Returns a 0 terminated array of registers that can be safely used as
/// scratch registers.
virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
  return nullptr;
}

/// This callback is used to prepare for a volatile or atomic load.
/// It takes a chain node as input and returns the chain for the load itself.
///
/// Having a callback like this is necessary for targets like SystemZ,
/// which allows a CPU to reuse the result of a previous load indefinitely,
/// even if a cache-coherent store is performed by another CPU.  The default
/// implementation does nothing.
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL,
                                            SelectionDAG &DAG) const {
  return Chain;
}

/// This callback is used to inspect load/store instructions and add
/// target-specific MachineMemOperand flags to them.  The default
/// implementation does nothing.
virtual MachineMemOperand::Flags getMMOFlags(const Instruction &I) const {
  return MachineMemOperand::MONone;
}

/// Should SelectionDAG lower an atomic store of the given kind as a normal
/// StoreSDNode (as opposed to an AtomicSDNode)?  NOTE: The intention is to
/// eventually migrate all targets to the using StoreSDNodes, but porting is
/// being done target at a time.  
virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst &SI) const {
  assert(SI.isAtomic() && "violated precondition")((SI.isAtomic() && "violated precondition") ? static_cast
<void> (0) : __assert_fail ("SI.isAtomic() && \"violated precondition\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3751, __PRETTY_FUNCTION__));
  return false;
}

/// Should SelectionDAG lower an atomic load of the given kind as a normal
/// LoadSDNode (as opposed to an AtomicSDNode)?  NOTE: The intention is to
/// eventually migrate all targets to the using LoadSDNodes, but porting is
/// being done target at a time.  
virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst &LI) const {
  assert(LI.isAtomic() && "violated precondition")((LI.isAtomic() && "violated precondition") ? static_cast
<void> (0) : __assert_fail ("LI.isAtomic() && \"violated precondition\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3760, __PRETTY_FUNCTION__));
  return false;
}


/// This callback is invoked by the type legalizer to legalize nodes with an
/// illegal operand type but legal result types.  It replaces the
/// LowerOperation callback in the type Legalizer.  The reason we can not do
/// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
/// use this callback.
///
/// TODO: Consider merging with ReplaceNodeResults.
///
/// The target places new result values for the node in Results (their number
/// and types must exactly match those of the original return values of
/// the node), or leaves Results empty, which indicates that the node is not
/// to be custom lowered after all.
/// The default implementation calls LowerOperation.
virtual void LowerOperationWrapper(SDNode *N,
                                   SmallVectorImpl<SDValue> &Results,
                                   SelectionDAG &DAG) const;

/// This callback is invoked for operations that are unsupported by the
/// target, which are registered to use 'custom' lowering, and whose defined
/// values are all legal.  If the target has no operations that require custom
/// lowering, it need not implement this.  The default implementation of this
/// aborts.
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;

/// This callback is invoked when a node result type is illegal for the
/// target, and the operation was registered to use 'custom' lowering for that
/// result type.  The target places new result values for the node in Results
/// (their number and types must exactly match those of the original return
/// values of the node), or leaves Results empty, which indicates that the
/// node is not to be custom lowered after all.
///
/// If the target has no operations that require custom lowering, it need not
/// implement this.  The default implementation aborts.
virtual void ReplaceNodeResults(SDNode * /*N*/,
                                SmallVectorImpl<SDValue> &/*Results*/,
                                SelectionDAG &/*DAG*/) const {
  llvm_unreachable("ReplaceNodeResults not implemented for this target!")::llvm::llvm_unreachable_internal("ReplaceNodeResults not implemented for this target!"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 3801);
}

/// This method returns the name of a target specific DAG node.
virtual const char *getTargetNodeName(unsigned Opcode) const;

/// This method returns a target specific FastISel object, or null if the
/// target does not support "fast" ISel.
virtual FastISel *createFastISel(FunctionLoweringInfo &,
                                 const TargetLibraryInfo *) const {
  return nullptr;
}

bool verifyReturnAddressArgumentIsConstant(SDValue Op,
                                           SelectionDAG &DAG) const;

//===--------------------------------------------------------------------===//
// Inline Asm Support hooks
//

/// This hook allows the target to expand an inline asm call to be explicit
/// llvm code if it wants to.  This is useful for turning simple inline asms
/// into LLVM intrinsics, which gives the compiler more information about the
/// behavior of the code.
virtual bool ExpandInlineAsm(CallInst *) const {
  return false;
}

enum ConstraintType {
  C_Register,            // Constraint represents specific register(s).
  C_RegisterClass,       // Constraint represents any of register(s) in class.
  C_Memory,              // Memory constraint.
  C_Immediate,           // Requires an immediate.
  C_Other,               // Something else.
  C_Unknown              // Unsupported constraint.
};

enum ConstraintWeight {
  // Generic weights.
  CW_Invalid  = -1,     // No match.
  CW_Okay     = 0,      // Acceptable.
  CW_Good     = 1,      // Good weight.
  CW_Better   = 2,      // Better weight.
  CW_Best     = 3,      // Best weight.

  // Well-known weights.
  CW_SpecificReg  = CW_Okay,    // Specific register operands.
  CW_Register     = CW_Good,    // Register operands.
  CW_Memory       = CW_Better,  // Memory operands.
  CW_Constant     = CW_Best,    // Constant operand.
  CW_Default      = CW_Okay     // Default or don't know type.
};

/// This contains information for each constraint that we are lowering.
struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
  /// This contains the actual string for the code, like "m".  TargetLowering
  /// picks the 'best' code from ConstraintInfo::Codes that most closely
  /// matches the operand.
  std::string ConstraintCode;

  /// Information about the constraint code, e.g. Register, RegisterClass,
  /// Memory, Other, Unknown.
  TargetLowering::ConstraintType ConstraintType = TargetLowering::C_Unknown;

  /// If this is the result output operand or a clobber, this is null,
  /// otherwise it is the incoming operand to the CallInst.  This gets
  /// modified as the asm is processed.
  Value *CallOperandVal = nullptr;

  /// The ValueType for the operand value.
  MVT ConstraintVT = MVT::Other;

  /// Copy constructor for copying from a ConstraintInfo.
  AsmOperandInfo(InlineAsm::ConstraintInfo Info)
      : InlineAsm::ConstraintInfo(std::move(Info)) {}

  /// Return true of this is an input operand that is a matching constraint
  /// like "4".
  bool isMatchingInputConstraint() const;

  /// If this is an input matching constraint, this method returns the output
  /// operand it matches.
  unsigned getMatchedOperand() const;
};

using AsmOperandInfoVector = std::vector<AsmOperandInfo>;

/// Split up the constraint string from the inline assembly value into the
/// specific constraints and their prefixes, and also tie in the associated
/// operand values.  If this returns an empty vector, and if the constraint
/// string itself isn't empty, there was an error parsing.
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
                                              const TargetRegisterInfo *TRI,
                                              ImmutableCallSite CS) const;

/// Examine constraint type and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
virtual ConstraintWeight getMultipleConstraintMatchWeight(
    AsmOperandInfo &info, int maIndex) const;

/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
virtual ConstraintWeight getSingleConstraintMatchWeight(
    AsmOperandInfo &info, const char *constraint) const;

/// Determines the constraint code and constraint type to use for the specific
/// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
/// If the actual operand being passed in is available, it can be passed in as
/// Op, otherwise an empty SDValue can be passed.
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
                                    SDValue Op,
                                    SelectionDAG *DAG = nullptr) const;

/// Given a constraint, return the type of constraint it is for this target.
virtual ConstraintType getConstraintType(StringRef Constraint) const;

/// Given a physical register constraint (e.g.  {edx}), return the register
/// number and the register class for the register.
///
/// Given a register class constraint, like 'r', if this corresponds directly
/// to an LLVM register class, return a register of 0 and the register class
/// pointer.
///
/// This should only be used for C_Register constraints.  On error, this
/// returns a register number of 0 and a null register class pointer.
virtual std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                             StringRef Constraint, MVT VT) const;

virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
  if (ConstraintCode == "i")
    return InlineAsm::Constraint_i;
  else if (ConstraintCode == "m")
    return InlineAsm::Constraint_m;
  return InlineAsm::Constraint_Unknown;
}

/// Try to replace an X constraint, which matches anything, with another that
/// has more specific requirements based on the type of the corresponding
/// operand.  This returns null if there is no replacement to make.
virtual const char *LowerXConstraint(EVT ConstraintVT) const;

/// Lower the specified operand into the Ops vector.  If it is invalid, don't
/// add anything to Ops.
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
                                          std::vector<SDValue> &Ops,
                                          SelectionDAG &DAG) const;

// Lower custom output constraints. If invalid, return SDValue().
virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Flag,
                                            SDLoc DL,
                                            const AsmOperandInfo &OpInfo,
                                            SelectionDAG &DAG) const;

//===--------------------------------------------------------------------===//
// Div utility functions
//
SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
                  SmallVectorImpl<SDNode *> &Created) const;
SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
                  SmallVectorImpl<SDNode *> &Created) const;

/// Targets may override this function to provide custom SDIV lowering for
/// power-of-2 denominators.  If the target returns an empty SDValue, LLVM
/// assumes SDIV is expensive and replaces it with a series of other integer
/// operations.
virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
                              SelectionDAG &DAG,
                              SmallVectorImpl<SDNode *> &Created) const;

/// Indicate whether this target prefers to combine FDIVs with the same
/// divisor. If the transform should never be done, return zero. If the
/// transform should be done, return the minimum number of divisor uses
/// that must exist.
virtual unsigned combineRepeatedFPDivisors() const {
  return 0;
}

/// Hooks for building estimates in place of slower divisions and square
/// roots.

/// Return either a square root or its reciprocal estimate value for the input
/// operand.
/// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
/// 'Enabled' as set by a potential default override attribute.
/// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
/// refinement iterations required to generate a sufficient (though not
/// necessarily IEEE-754 compliant) estimate is returned in that parameter.
/// The boolean UseOneConstNR output is used to select a Newton-Raphson
/// algorithm implementation that uses either one or two constants.
/// The boolean Reciprocal is used to select whether the estimate is for the
/// square root of the input operand or the reciprocal of its square root.
/// A target may choose to implement its own refinement within this function.
/// If that's true, then return '0' as the number of RefinementSteps to avoid
/// any further refinement of the estimate.
/// An empty SDValue return means no estimate sequence can be created.
virtual SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG,
                                int Enabled, int &RefinementSteps,
                                bool &UseOneConstNR, bool Reciprocal) const {
  return SDValue();
}

/// Return a reciprocal estimate value for the input operand.
/// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
/// 'Enabled' as set by a potential default override attribute.
/// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
/// refinement iterations required to generate a sufficient (though not
/// necessarily IEEE-754 compliant) estimate is returned in that parameter.
/// A target may choose to implement its own refinement within this function.
/// If that's true, then return '0' as the number of RefinementSteps to avoid
/// any further refinement of the estimate.
/// An empty SDValue return means no estimate sequence can be created.
virtual SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG,
                                 int Enabled, int &RefinementSteps) const {
  return SDValue();
}

//===--------------------------------------------------------------------===//
// Legalization utility functions
//

/// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
/// respectively, each computing an n/2-bit part of the result.
/// \param Result A vector that will be filled with the parts of the result
///        in little-endian order.
/// \param LL Low bits of the LHS of the MUL.  You can use this parameter
///        if you want to control how low bits are extracted from the LHS.
/// \param LH High bits of the LHS of the MUL.  See LL for meaning.
/// \param RL Low bits of the RHS of the MUL.  See LL for meaning
/// \param RH High bits of the RHS of the MUL.  See LL for meaning.
/// \returns true if the node has been expanded, false if it has not
bool expandMUL_LOHI(unsigned Opcode, EVT VT, SDLoc dl, SDValue LHS,
                    SDValue RHS, SmallVectorImpl<SDValue> &Result, EVT HiLoVT,
                    SelectionDAG &DAG, MulExpansionKind Kind,
                    SDValue LL = SDValue(), SDValue LH = SDValue(),
                    SDValue RL = SDValue(), SDValue RH = SDValue()) const;

/// Expand a MUL into two nodes.  One that computes the high bits of
/// the result and one that computes the low bits.
/// \param HiLoVT The value type to use for the Lo and Hi nodes.
/// \param LL Low bits of the LHS of the MUL.  You can use this parameter
///        if you want to control how low bits are extracted from the LHS.
/// \param LH High bits of the LHS of the MUL.  See LL for meaning.
/// \param RL Low bits of the RHS of the MUL.  See LL for meaning
/// \param RH High bits of the RHS of the MUL.  See LL for meaning.
/// \returns true if the node has been expanded. false if it has not
bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
               SelectionDAG &DAG, MulExpansionKind Kind,
               SDValue LL = SDValue(), SDValue LH = SDValue(),
               SDValue RL = SDValue(), SDValue RH = SDValue()) const;

/// Expand funnel shift.
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandFunnelShift(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand rotations.
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandROT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand float(f32) to SINT(i64) conversion
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand float to UINT conversion
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandFP_TO_UINT(SDNode *N, SDValue &Result, SDValue &Chain, SelectionDAG &DAG) const;

/// Expand UINT(i64) to double(f64) conversion
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandUINT_TO_FP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const;

/// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandCTPOP(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandCTLZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandCTTZ(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Expand ABS nodes. Expands vector/scalar ABS nodes,
/// vector nodes can only succeed if all operations are legal/custom.
/// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
/// \param N Node to expand
/// \param Result output after conversion
/// \returns True, if the expansion was successful, false otherwise
bool expandABS(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;

/// Turn load of vector type into a load of the individual elements.
/// \param LD load to expand
/// \returns MERGE_VALUEs of the scalar loads with their chains.
SDValue scalarizeVectorLoad(LoadSDNode *LD, SelectionDAG &DAG) const;

// Turn a store of a vector type into stores of the individual elements.
/// \param ST Store with a vector value type
/// \returns MERGE_VALUs of the individual store chains.
SDValue scalarizeVectorStore(StoreSDNode *ST, SelectionDAG &DAG) const;

/// Expands an unaligned load to 2 half-size loads for an integer, and
/// possibly more for vectors.
std::pair<SDValue, SDValue> expandUnalignedLoad(LoadSDNode *LD,
                                                SelectionDAG &DAG) const;

/// Expands an unaligned store to 2 half-size stores for integer values, and
/// possibly more for vectors.
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const;

/// Increments memory address \p Addr according to the type of the value
/// \p DataVT that should be stored. If the data is stored in compressed
/// form, the memory address should be incremented according to the number of
/// the stored elements. This number is equal to the number of '1's bits
/// in the \p Mask.
/// \p DataVT is a vector type. \p Mask is a vector value.
/// \p DataVT and \p Mask have the same number of vector elements.
SDValue IncrementMemoryAddress(SDValue Addr, SDValue Mask, const SDLoc &DL,
                               EVT DataVT, SelectionDAG &DAG,
                               bool IsCompressedMemory) const;

/// Get a pointer to vector element \p Idx located in memory for a vector of
/// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
/// bounds the returned pointer is unspecified, but will be within the vector
/// bounds.
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
                                SDValue Index) const;

/// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
/// method accepts integers as its arguments.
SDValue expandAddSubSat(SDNode *Node, SelectionDAG &DAG) const;

/// Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This
/// method accepts integers as its arguments.
SDValue expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const;

/// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
/// always suceeds and populates the Result and Overflow arguments.
void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
                    SelectionDAG &DAG) const;

/// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
/// always suceeds and populates the Result and Overflow arguments.
void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow,
                    SelectionDAG &DAG) const;

/// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
/// expansion was successful and populates the Result and Overflow arguments.
bool expandMULO(SDNode *Node, SDValue &Result, SDValue &Overflow,
                SelectionDAG &DAG) const;

/// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
/// only the first Count elements of the vector are used.
SDValue expandVecReduce(SDNode *Node, SelectionDAG &DAG) const;

//===--------------------------------------------------------------------===//
// Instruction Emitting Hooks
//

/// This method should be implemented by targets that mark instructions with
/// the 'usesCustomInserter' flag.  These instructions are special in various
/// ways, which require special support to insert.  The specified MachineInstr
/// is created but not inserted into any basic blocks, and this method is
/// called to expand it into a sequence of instructions, potentially also
/// creating new basic blocks and control flow.
/// As long as the returned basic block is different (i.e., we created a new
/// one), the custom inserter is free to modify the rest of \p MBB.
virtual MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *MBB) const;

/// This method should be implemented by targets that mark instructions with
/// the 'hasPostISelHook' flag. These instructions must be adjusted after
/// instruction selection by target hooks.  e.g. To fill in optional defs for
/// ARM 's' setting instructions.
virtual void AdjustInstrPostInstrSelection(MachineInstr &MI,
                                           SDNode *Node) const;

/// If this function returns true, SelectionDAGBuilder emits a
/// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
virtual bool useLoadStackGuardNode() const {
  return false;
}

virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val,
                                    const SDLoc &DL) const {
  llvm_unreachable("not implemented for this target")::llvm::llvm_unreachable_internal("not implemented for this target"
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/TargetLowering.h"
, 4208);
}

/// Lower TLS global address SDNode for target independent emulated TLS model.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
                                        SelectionDAG &DAG) const;

/// Expands target specific indirect branch for the case of JumpTable
/// expanasion.
virtual SDValue expandIndirectJTBranch(const SDLoc& dl, SDValue Value, SDValue Addr,
                                       SelectionDAG &DAG) const {
  return DAG.getNode(ISD::BRIND, dl, MVT::Other, Value, Addr);
}

// seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
// If we're comparing for equality to zero and isCtlzFast is true, expose the
// fact that this can be implemented as a ctlz/srl pair, so that the dag
// combiner can fold the new nodes.
SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const;

4228private:
SDValue foldSetCCWithAnd(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
                         const SDLoc &DL, DAGCombinerInfo &DCI) const;
SDValue foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
                           const SDLoc &DL, DAGCombinerInfo &DCI) const;

SDValue optimizeSetCCOfSignedTruncationCheck(EVT SCCVT, SDValue N0,
                                             SDValue N1, ISD::CondCode Cond,
                                             DAGCombinerInfo &DCI,
                                             const SDLoc &DL) const;

// (X & (C l>>/<< Y)) ==/!= 0  -->  ((X <</l>> Y) & C) ==/!= 0
SDValue optimizeSetCCByHoistingAndByConstFromLogicalShift(
    EVT SCCVT, SDValue N0, SDValue N1C, ISD::CondCode Cond,
    DAGCombinerInfo &DCI, const SDLoc &DL) const;

SDValue prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
                          SDValue CompTargetNode, ISD::CondCode Cond,
                          DAGCombinerInfo &DCI, const SDLoc &DL,
                          SmallVectorImpl<SDNode *> &Created) const;
SDValue buildUREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
                        ISD::CondCode Cond, DAGCombinerInfo &DCI,
                        const SDLoc &DL) const;

SDValue prepareSREMEqFold(EVT SETCCVT, SDValue REMNode,
                          SDValue CompTargetNode, ISD::CondCode Cond,
                          DAGCombinerInfo &DCI, const SDLoc &DL,
                          SmallVectorImpl<SDNode *> &Created) const;
SDValue buildSREMEqFold(EVT SETCCVT, SDValue REMNode, SDValue CompTargetNode,
                        ISD::CondCode Cond, DAGCombinerInfo &DCI,
                        const SDLoc &DL) const;
4259};

4261/// Given an LLVM IR type and return type attributes, compute the return value
4262/// EVTs and flags, and optionally also the offsets, if the return value is
4263/// being lowered to memory.
4264void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr,
                 SmallVectorImpl<ISD::OutputArg> &Outs,
                 const TargetLowering &TLI, const DataLayout &DL);

4268} // end namespace llvm

4270#endif // LLVM_CODEGEN_TARGETLOWERING_H