Bug Summary

File:lib/CodeGen/CriticalAntiDepBreaker.cpp
Warning:line 466, column 34
Called C++ object pointer is null

Annotated Source Code

1//===----- CriticalAntiDepBreaker.cpp - Anti-dep breaker -------- ---------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the CriticalAntiDepBreaker class, which
11// implements register anti-dependence breaking along a blocks
12// critical path during post-RA scheduler.
13//
14//===----------------------------------------------------------------------===//
15
16#include "CriticalAntiDepBreaker.h"
17#include "llvm/CodeGen/MachineBasicBlock.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/Support/Debug.h"
20#include "llvm/Support/ErrorHandling.h"
21#include "llvm/Support/raw_ostream.h"
22#include "llvm/Target/TargetInstrInfo.h"
23#include "llvm/Target/TargetRegisterInfo.h"
24#include "llvm/Target/TargetSubtargetInfo.h"
25
26using namespace llvm;
27
28#define DEBUG_TYPE"post-RA-sched" "post-RA-sched"
29
30CriticalAntiDepBreaker::CriticalAntiDepBreaker(MachineFunction &MFi,
31 const RegisterClassInfo &RCI)
32 : AntiDepBreaker(), MF(MFi), MRI(MF.getRegInfo()),
33 TII(MF.getSubtarget().getInstrInfo()),
34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
35 Classes(TRI->getNumRegs(), nullptr), KillIndices(TRI->getNumRegs(), 0),
36 DefIndices(TRI->getNumRegs(), 0), KeepRegs(TRI->getNumRegs(), false) {}
37
38CriticalAntiDepBreaker::~CriticalAntiDepBreaker() {
39}
40
41void CriticalAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
42 const unsigned BBSize = BB->size();
43 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
44 // Clear out the register class data.
45 Classes[i] = nullptr;
46
47 // Initialize the indices to indicate that no registers are live.
48 KillIndices[i] = ~0u;
49 DefIndices[i] = BBSize;
50 }
51
52 // Clear "do not change" set.
53 KeepRegs.reset();
54
55 bool IsReturnBlock = BB->isReturnBlock();
56
57 // Examine the live-in regs of all successors.
58 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
59 SE = BB->succ_end(); SI != SE; ++SI)
60 for (const auto &LI : (*SI)->liveins()) {
61 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
62 unsigned Reg = *AI;
63 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
64 KillIndices[Reg] = BBSize;
65 DefIndices[Reg] = ~0u;
66 }
67 }
68
69 // Mark live-out callee-saved registers. In a return block this is
70 // all callee-saved registers. In non-return this is any
71 // callee-saved register that is not saved in the prolog.
72 const MachineFrameInfo &MFI = MF.getFrameInfo();
73 BitVector Pristine = MFI.getPristineRegs(MF);
74 for (const MCPhysReg *I = MF.getRegInfo().getCalleeSavedRegs(); *I;
75 ++I) {
76 unsigned Reg = *I;
77 if (!IsReturnBlock && !(Pristine.test(Reg) || BB->isLiveIn(Reg)))
78 continue;
79 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
80 unsigned Reg = *AI;
81 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
82 KillIndices[Reg] = BBSize;
83 DefIndices[Reg] = ~0u;
84 }
85 }
86}
87
88void CriticalAntiDepBreaker::FinishBlock() {
89 RegRefs.clear();
90 KeepRegs.reset();
91}
92
93void CriticalAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
94 unsigned InsertPosIndex) {
95 // Kill instructions can define registers but are really nops, and there might
96 // be a real definition earlier that needs to be paired with uses dominated by
97 // this kill.
98
99 // FIXME: It may be possible to remove the isKill() restriction once PR18663
100 // has been properly fixed. There can be value in processing kills as seen in
101 // the AggressiveAntiDepBreaker class.
102 if (MI.isDebugValue() || MI.isKill())
103 return;
104 assert(Count < InsertPosIndex && "Instruction index out of expected range!")((Count < InsertPosIndex && "Instruction index out of expected range!"
) ? static_cast<void> (0) : __assert_fail ("Count < InsertPosIndex && \"Instruction index out of expected range!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 104, __PRETTY_FUNCTION__))
;
105
106 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
107 if (KillIndices[Reg] != ~0u) {
108 // If Reg is currently live, then mark that it can't be renamed as
109 // we don't know the extent of its live-range anymore (now that it
110 // has been scheduled).
111 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
112 KillIndices[Reg] = Count;
113 } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
114 // Any register which was defined within the previous scheduling region
115 // may have been rescheduled and its lifetime may overlap with registers
116 // in ways not reflected in our current liveness state. For each such
117 // register, adjust the liveness state to be conservatively correct.
118 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
119
120 // Move the def index to the end of the previous region, to reflect
121 // that the def could theoretically have been scheduled at the end.
122 DefIndices[Reg] = InsertPosIndex;
123 }
124 }
125
126 PrescanInstruction(MI);
127 ScanInstruction(MI, Count);
128}
129
130/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
131/// critical path.
132static const SDep *CriticalPathStep(const SUnit *SU) {
133 const SDep *Next = nullptr;
134 unsigned NextDepth = 0;
135 // Find the predecessor edge with the greatest depth.
136 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
137 P != PE; ++P) {
138 const SUnit *PredSU = P->getSUnit();
139 unsigned PredLatency = P->getLatency();
140 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
141 // In the case of a latency tie, prefer an anti-dependency edge over
142 // other types of edges.
143 if (NextDepth < PredTotalLatency ||
144 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
145 NextDepth = PredTotalLatency;
146 Next = &*P;
147 }
148 }
149 return Next;
150}
151
152void CriticalAntiDepBreaker::PrescanInstruction(MachineInstr &MI) {
153 // It's not safe to change register allocation for source operands of
154 // instructions that have special allocation requirements. Also assume all
155 // registers used in a call must not be changed (ABI).
156 // FIXME: The issue with predicated instruction is more complex. We are being
157 // conservative here because the kill markers cannot be trusted after
158 // if-conversion:
159 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
160 // ...
161 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
162 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
163 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
164 //
165 // The first R6 kill is not really a kill since it's killed by a predicated
166 // instruction which may not be executed. The second R6 def may or may not
167 // re-define R6 so it's not safe to change it since the last R6 use cannot be
168 // changed.
169 bool Special =
170 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI);
171
172 // Scan the register operands for this instruction and update
173 // Classes and RegRefs.
174 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
175 MachineOperand &MO = MI.getOperand(i);
176 if (!MO.isReg()) continue;
177 unsigned Reg = MO.getReg();
178 if (Reg == 0) continue;
179 const TargetRegisterClass *NewRC = nullptr;
180
181 if (i < MI.getDesc().getNumOperands())
182 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
183
184 // For now, only allow the register to be changed if its register
185 // class is consistent across all uses.
186 if (!Classes[Reg] && NewRC)
187 Classes[Reg] = NewRC;
188 else if (!NewRC || Classes[Reg] != NewRC)
189 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
190
191 // Now check for aliases.
192 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
193 // If an alias of the reg is used during the live range, give up.
194 // Note that this allows us to skip checking if AntiDepReg
195 // overlaps with any of the aliases, among other things.
196 unsigned AliasReg = *AI;
197 if (Classes[AliasReg]) {
198 Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
199 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
200 }
201 }
202
203 // If we're still willing to consider this register, note the reference.
204 if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
205 RegRefs.insert(std::make_pair(Reg, &MO));
206
207 // If this reg is tied and live (Classes[Reg] is set to -1), we can't change
208 // it or any of its sub or super regs. We need to use KeepRegs to mark the
209 // reg because not all uses of the same reg within an instruction are
210 // necessarily tagged as tied.
211 // Example: an x86 "xor %eax, %eax" will have one source operand tied to the
212 // def register but not the second (see PR20020 for details).
213 // FIXME: can this check be relaxed to account for undef uses
214 // of a register? In the above 'xor' example, the uses of %eax are undef, so
215 // earlier instructions could still replace %eax even though the 'xor'
216 // itself can't be changed.
217 if (MI.isRegTiedToUseOperand(i) &&
218 Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
219 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
220 SubRegs.isValid(); ++SubRegs) {
221 KeepRegs.set(*SubRegs);
222 }
223 for (MCSuperRegIterator SuperRegs(Reg, TRI);
224 SuperRegs.isValid(); ++SuperRegs) {
225 KeepRegs.set(*SuperRegs);
226 }
227 }
228
229 if (MO.isUse() && Special) {
230 if (!KeepRegs.test(Reg)) {
231 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
232 SubRegs.isValid(); ++SubRegs)
233 KeepRegs.set(*SubRegs);
234 }
235 }
236 }
237}
238
239void CriticalAntiDepBreaker::ScanInstruction(MachineInstr &MI, unsigned Count) {
240 // Update liveness.
241 // Proceeding upwards, registers that are defed but not used in this
242 // instruction are now dead.
243 assert(!MI.isKill() && "Attempting to scan a kill instruction")((!MI.isKill() && "Attempting to scan a kill instruction"
) ? static_cast<void> (0) : __assert_fail ("!MI.isKill() && \"Attempting to scan a kill instruction\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 243, __PRETTY_FUNCTION__))
;
244
245 if (!TII->isPredicated(MI)) {
246 // Predicated defs are modeled as read + write, i.e. similar to two
247 // address updates.
248 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
249 MachineOperand &MO = MI.getOperand(i);
250
251 if (MO.isRegMask())
252 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
253 if (MO.clobbersPhysReg(i)) {
254 DefIndices[i] = Count;
255 KillIndices[i] = ~0u;
256 KeepRegs.reset(i);
257 Classes[i] = nullptr;
258 RegRefs.erase(i);
259 }
260
261 if (!MO.isReg()) continue;
262 unsigned Reg = MO.getReg();
263 if (Reg == 0) continue;
264 if (!MO.isDef()) continue;
265
266 // Ignore two-addr defs.
267 if (MI.isRegTiedToUseOperand(i))
268 continue;
269
270 // If we've already marked this reg as unchangeable, don't remove
271 // it or any of its subregs from KeepRegs.
272 bool Keep = KeepRegs.test(Reg);
273
274 // For the reg itself and all subregs: update the def to current;
275 // reset the kill state, any restrictions, and references.
276 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) {
277 unsigned SubregReg = *SRI;
278 DefIndices[SubregReg] = Count;
279 KillIndices[SubregReg] = ~0u;
280 Classes[SubregReg] = nullptr;
281 RegRefs.erase(SubregReg);
282 if (!Keep)
283 KeepRegs.reset(SubregReg);
284 }
285 // Conservatively mark super-registers as unusable.
286 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR)
287 Classes[*SR] = reinterpret_cast<TargetRegisterClass *>(-1);
288 }
289 }
290 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
291 MachineOperand &MO = MI.getOperand(i);
292 if (!MO.isReg()) continue;
293 unsigned Reg = MO.getReg();
294 if (Reg == 0) continue;
295 if (!MO.isUse()) continue;
296
297 const TargetRegisterClass *NewRC = nullptr;
298 if (i < MI.getDesc().getNumOperands())
299 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
300
301 // For now, only allow the register to be changed if its register
302 // class is consistent across all uses.
303 if (!Classes[Reg] && NewRC)
304 Classes[Reg] = NewRC;
305 else if (!NewRC || Classes[Reg] != NewRC)
306 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
307
308 RegRefs.insert(std::make_pair(Reg, &MO));
309
310 // It wasn't previously live but now it is, this is a kill.
311 // Repeat for all aliases.
312 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
313 unsigned AliasReg = *AI;
314 if (KillIndices[AliasReg] == ~0u) {
315 KillIndices[AliasReg] = Count;
316 DefIndices[AliasReg] = ~0u;
317 }
318 }
319 }
320}
321
322// Check all machine operands that reference the antidependent register and must
323// be replaced by NewReg. Return true if any of their parent instructions may
324// clobber the new register.
325//
326// Note: AntiDepReg may be referenced by a two-address instruction such that
327// it's use operand is tied to a def operand. We guard against the case in which
328// the two-address instruction also defines NewReg, as may happen with
329// pre/postincrement loads. In this case, both the use and def operands are in
330// RegRefs because the def is inserted by PrescanInstruction and not erased
331// during ScanInstruction. So checking for an instruction with definitions of
332// both NewReg and AntiDepReg covers it.
333bool
334CriticalAntiDepBreaker::isNewRegClobberedByRefs(RegRefIter RegRefBegin,
335 RegRefIter RegRefEnd,
336 unsigned NewReg)
337{
338 for (RegRefIter I = RegRefBegin; I != RegRefEnd; ++I ) {
339 MachineOperand *RefOper = I->second;
340
341 // Don't allow the instruction defining AntiDepReg to earlyclobber its
342 // operands, in case they may be assigned to NewReg. In this case antidep
343 // breaking must fail, but it's too rare to bother optimizing.
344 if (RefOper->isDef() && RefOper->isEarlyClobber())
345 return true;
346
347 // Handle cases in which this instruction defines NewReg.
348 MachineInstr *MI = RefOper->getParent();
349 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
350 const MachineOperand &CheckOper = MI->getOperand(i);
351
352 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
353 return true;
354
355 if (!CheckOper.isReg() || !CheckOper.isDef() ||
356 CheckOper.getReg() != NewReg)
357 continue;
358
359 // Don't allow the instruction to define NewReg and AntiDepReg.
360 // When AntiDepReg is renamed it will be an illegal op.
361 if (RefOper->isDef())
362 return true;
363
364 // Don't allow an instruction using AntiDepReg to be earlyclobbered by
365 // NewReg.
366 if (CheckOper.isEarlyClobber())
367 return true;
368
369 // Don't allow inline asm to define NewReg at all. Who knows what it's
370 // doing with it.
371 if (MI->isInlineAsm())
372 return true;
373 }
374 }
375 return false;
376}
377
378unsigned CriticalAntiDepBreaker::
379findSuitableFreeRegister(RegRefIter RegRefBegin,
380 RegRefIter RegRefEnd,
381 unsigned AntiDepReg,
382 unsigned LastNewReg,
383 const TargetRegisterClass *RC,
384 SmallVectorImpl<unsigned> &Forbid)
385{
386 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
387 for (unsigned i = 0; i != Order.size(); ++i) {
388 unsigned NewReg = Order[i];
389 // Don't replace a register with itself.
390 if (NewReg == AntiDepReg) continue;
391 // Don't replace a register with one that was recently used to repair
392 // an anti-dependence with this AntiDepReg, because that would
393 // re-introduce that anti-dependence.
394 if (NewReg == LastNewReg) continue;
395 // If any instructions that define AntiDepReg also define the NewReg, it's
396 // not suitable. For example, Instruction with multiple definitions can
397 // result in this condition.
398 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
399 // If NewReg is dead and NewReg's most recent def is not before
400 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
401 assert(((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u))((((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg
] == ~0u)) && "Kill and Def maps aren't consistent for AntiDepReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && \"Kill and Def maps aren't consistent for AntiDepReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 402, __PRETTY_FUNCTION__))
402 && "Kill and Def maps aren't consistent for AntiDepReg!")((((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg
] == ~0u)) && "Kill and Def maps aren't consistent for AntiDepReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && \"Kill and Def maps aren't consistent for AntiDepReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 402, __PRETTY_FUNCTION__))
;
403 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))((((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u
)) && "Kill and Def maps aren't consistent for NewReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && \"Kill and Def maps aren't consistent for NewReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 404, __PRETTY_FUNCTION__))
404 && "Kill and Def maps aren't consistent for NewReg!")((((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u
)) && "Kill and Def maps aren't consistent for NewReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && \"Kill and Def maps aren't consistent for NewReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 404, __PRETTY_FUNCTION__))
;
405 if (KillIndices[NewReg] != ~0u ||
406 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
407 KillIndices[AntiDepReg] > DefIndices[NewReg])
408 continue;
409 // If NewReg overlaps any of the forbidden registers, we can't use it.
410 bool Forbidden = false;
411 for (SmallVectorImpl<unsigned>::iterator it = Forbid.begin(),
412 ite = Forbid.end(); it != ite; ++it)
413 if (TRI->regsOverlap(NewReg, *it)) {
414 Forbidden = true;
415 break;
416 }
417 if (Forbidden) continue;
418 return NewReg;
419 }
420
421 // No registers are free and available!
422 return 0;
423}
424
425unsigned CriticalAntiDepBreaker::
426BreakAntiDependencies(const std::vector<SUnit>& SUnits,
427 MachineBasicBlock::iterator Begin,
428 MachineBasicBlock::iterator End,
429 unsigned InsertPosIndex,
430 DbgValueVector &DbgValues) {
431 // The code below assumes that there is at least one instruction,
432 // so just duck out immediately if the block is empty.
433 if (SUnits.empty()) return 0;
1
Assuming the condition is false
2
Taking false branch
434
435 // Keep a map of the MachineInstr*'s back to the SUnit representing them.
436 // This is used for updating debug information.
437 //
438 // FIXME: Replace this with the existing map in ScheduleDAGInstrs::MISUnitMap
439 DenseMap<MachineInstr*,const SUnit*> MISUnitMap;
440
441 // Find the node at the bottom of the critical path.
442 const SUnit *Max = nullptr;
3
'Max' initialized to a null pointer value
443 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
4
Assuming 'i' is equal to 'e'
5
Loop condition is false. Execution continues on line 452
444 const SUnit *SU = &SUnits[i];
445 MISUnitMap[SU->getInstr()] = SU;
446 if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
447 Max = SU;
448 }
449
450#ifndef NDEBUG
451 {
452 DEBUG(dbgs() << "Critical path has total latency "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Critical path has total latency "
<< (Max->getDepth() + Max->Latency) << "\n"
; } } while (false)
453 << (Max->getDepth() + Max->Latency) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Critical path has total latency "
<< (Max->getDepth() + Max->Latency) << "\n"
; } } while (false)
;
454 DEBUG(dbgs() << "Available regs:")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Available regs:"; } } while
(false)
;
455 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
6
Assuming the condition is false
7
Loop condition is false. Execution continues on line 459
456 if (KillIndices[Reg] == ~0u)
457 DEBUG(dbgs() << " " << TRI->getName(Reg))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << " " << TRI->getName
(Reg); } } while (false)
;
458 }
459 DEBUG(dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << '\n'; } } while (false)
;
460 }
461#endif
462
463 // Track progress along the critical path through the SUnit graph as we walk
464 // the instructions.
465 const SUnit *CriticalPathSU = Max;
8
'CriticalPathSU' initialized to a null pointer value
466 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
9
Called C++ object pointer is null
467
468 // Consider this pattern:
469 // A = ...
470 // ... = A
471 // A = ...
472 // ... = A
473 // A = ...
474 // ... = A
475 // A = ...
476 // ... = A
477 // There are three anti-dependencies here, and without special care,
478 // we'd break all of them using the same register:
479 // A = ...
480 // ... = A
481 // B = ...
482 // ... = B
483 // B = ...
484 // ... = B
485 // B = ...
486 // ... = B
487 // because at each anti-dependence, B is the first register that
488 // isn't A which is free. This re-introduces anti-dependencies
489 // at all but one of the original anti-dependencies that we were
490 // trying to break. To avoid this, keep track of the most recent
491 // register that each register was replaced with, avoid
492 // using it to repair an anti-dependence on the same register.
493 // This lets us produce this:
494 // A = ...
495 // ... = A
496 // B = ...
497 // ... = B
498 // C = ...
499 // ... = C
500 // B = ...
501 // ... = B
502 // This still has an anti-dependence on B, but at least it isn't on the
503 // original critical path.
504 //
505 // TODO: If we tracked more than one register here, we could potentially
506 // fix that remaining critical edge too. This is a little more involved,
507 // because unlike the most recent register, less recent registers should
508 // still be considered, though only if no other registers are available.
509 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
510
511 // Attempt to break anti-dependence edges on the critical path. Walk the
512 // instructions from the bottom up, tracking information about liveness
513 // as we go to help determine which registers are available.
514 unsigned Broken = 0;
515 unsigned Count = InsertPosIndex - 1;
516 for (MachineBasicBlock::iterator I = End, E = Begin; I != E; --Count) {
517 MachineInstr &MI = *--I;
518 // Kill instructions can define registers but are really nops, and there
519 // might be a real definition earlier that needs to be paired with uses
520 // dominated by this kill.
521
522 // FIXME: It may be possible to remove the isKill() restriction once PR18663
523 // has been properly fixed. There can be value in processing kills as seen
524 // in the AggressiveAntiDepBreaker class.
525 if (MI.isDebugValue() || MI.isKill())
526 continue;
527
528 // Check if this instruction has a dependence on the critical path that
529 // is an anti-dependence that we may be able to break. If it is, set
530 // AntiDepReg to the non-zero register associated with the anti-dependence.
531 //
532 // We limit our attention to the critical path as a heuristic to avoid
533 // breaking anti-dependence edges that aren't going to significantly
534 // impact the overall schedule. There are a limited number of registers
535 // and we want to save them for the important edges.
536 //
537 // TODO: Instructions with multiple defs could have multiple
538 // anti-dependencies. The current code here only knows how to break one
539 // edge per instruction. Note that we'd have to be able to break all of
540 // the anti-dependencies in an instruction in order to be effective.
541 unsigned AntiDepReg = 0;
542 if (&MI == CriticalPathMI) {
543 if (const SDep *Edge = CriticalPathStep(CriticalPathSU)) {
544 const SUnit *NextSU = Edge->getSUnit();
545
546 // Only consider anti-dependence edges.
547 if (Edge->getKind() == SDep::Anti) {
548 AntiDepReg = Edge->getReg();
549 assert(AntiDepReg != 0 && "Anti-dependence on reg0?")((AntiDepReg != 0 && "Anti-dependence on reg0?") ? static_cast
<void> (0) : __assert_fail ("AntiDepReg != 0 && \"Anti-dependence on reg0?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 549, __PRETTY_FUNCTION__))
;
550 if (!MRI.isAllocatable(AntiDepReg))
551 // Don't break anti-dependencies on non-allocatable registers.
552 AntiDepReg = 0;
553 else if (KeepRegs.test(AntiDepReg))
554 // Don't break anti-dependencies if a use down below requires
555 // this exact register.
556 AntiDepReg = 0;
557 else {
558 // If the SUnit has other dependencies on the SUnit that it
559 // anti-depends on, don't bother breaking the anti-dependency
560 // since those edges would prevent such units from being
561 // scheduled past each other regardless.
562 //
563 // Also, if there are dependencies on other SUnits with the
564 // same register as the anti-dependency, don't attempt to
565 // break it.
566 for (SUnit::const_pred_iterator P = CriticalPathSU->Preds.begin(),
567 PE = CriticalPathSU->Preds.end(); P != PE; ++P)
568 if (P->getSUnit() == NextSU ?
569 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
570 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
571 AntiDepReg = 0;
572 break;
573 }
574 }
575 }
576 CriticalPathSU = NextSU;
577 CriticalPathMI = CriticalPathSU->getInstr();
578 } else {
579 // We've reached the end of the critical path.
580 CriticalPathSU = nullptr;
581 CriticalPathMI = nullptr;
582 }
583 }
584
585 PrescanInstruction(MI);
586
587 SmallVector<unsigned, 2> ForbidRegs;
588
589 // If MI's defs have a special allocation requirement, don't allow
590 // any def registers to be changed. Also assume all registers
591 // defined in a call must not be changed (ABI).
592 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI))
593 // If this instruction's defs have special allocation requirement, don't
594 // break this anti-dependency.
595 AntiDepReg = 0;
596 else if (AntiDepReg) {
597 // If this instruction has a use of AntiDepReg, breaking it
598 // is invalid. If the instruction defines other registers,
599 // save a list of them so that we don't pick a new register
600 // that overlaps any of them.
601 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
602 MachineOperand &MO = MI.getOperand(i);
603 if (!MO.isReg()) continue;
604 unsigned Reg = MO.getReg();
605 if (Reg == 0) continue;
606 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
607 AntiDepReg = 0;
608 break;
609 }
610 if (MO.isDef() && Reg != AntiDepReg)
611 ForbidRegs.push_back(Reg);
612 }
613 }
614
615 // Determine AntiDepReg's register class, if it is live and is
616 // consistently used within a single class.
617 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
618 : nullptr;
619 assert((AntiDepReg == 0 || RC != nullptr) &&(((AntiDepReg == 0 || RC != nullptr) && "Register should be live if it's causing an anti-dependence!"
) ? static_cast<void> (0) : __assert_fail ("(AntiDepReg == 0 || RC != nullptr) && \"Register should be live if it's causing an anti-dependence!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 620, __PRETTY_FUNCTION__))
620 "Register should be live if it's causing an anti-dependence!")(((AntiDepReg == 0 || RC != nullptr) && "Register should be live if it's causing an anti-dependence!"
) ? static_cast<void> (0) : __assert_fail ("(AntiDepReg == 0 || RC != nullptr) && \"Register should be live if it's causing an anti-dependence!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 620, __PRETTY_FUNCTION__))
;
621 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
622 AntiDepReg = 0;
623
624 // Look for a suitable register to use to break the anti-dependence.
625 //
626 // TODO: Instead of picking the first free register, consider which might
627 // be the best.
628 if (AntiDepReg != 0) {
629 std::pair<std::multimap<unsigned, MachineOperand *>::iterator,
630 std::multimap<unsigned, MachineOperand *>::iterator>
631 Range = RegRefs.equal_range(AntiDepReg);
632 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
633 AntiDepReg,
634 LastNewReg[AntiDepReg],
635 RC, ForbidRegs)) {
636 DEBUG(dbgs() << "Breaking anti-dependence edge on "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Breaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << " with " <<
RegRefs.count(AntiDepReg) << " references" << " using "
<< TRI->getName(NewReg) << "!\n"; } } while (
false)
637 << TRI->getName(AntiDepReg)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Breaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << " with " <<
RegRefs.count(AntiDepReg) << " references" << " using "
<< TRI->getName(NewReg) << "!\n"; } } while (
false)
638 << " with " << RegRefs.count(AntiDepReg) << " references"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Breaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << " with " <<
RegRefs.count(AntiDepReg) << " references" << " using "
<< TRI->getName(NewReg) << "!\n"; } } while (
false)
639 << " using " << TRI->getName(NewReg) << "!\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("post-RA-sched")) { dbgs() << "Breaking anti-dependence edge on "
<< TRI->getName(AntiDepReg) << " with " <<
RegRefs.count(AntiDepReg) << " references" << " using "
<< TRI->getName(NewReg) << "!\n"; } } while (
false)
;
640
641 // Update the references to the old register to refer to the new
642 // register.
643 for (std::multimap<unsigned, MachineOperand *>::iterator
644 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
645 Q->second->setReg(NewReg);
646 // If the SU for the instruction being updated has debug information
647 // related to the anti-dependency register, make sure to update that
648 // as well.
649 const SUnit *SU = MISUnitMap[Q->second->getParent()];
650 if (!SU) continue;
651 UpdateDbgValues(DbgValues, Q->second->getParent(),
652 AntiDepReg, NewReg);
653 }
654
655 // We just went back in time and modified history; the
656 // liveness information for the anti-dependence reg is now
657 // inconsistent. Set the state as if it were dead.
658 Classes[NewReg] = Classes[AntiDepReg];
659 DefIndices[NewReg] = DefIndices[AntiDepReg];
660 KillIndices[NewReg] = KillIndices[AntiDepReg];
661 assert(((KillIndices[NewReg] == ~0u) !=((((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u
)) && "Kill and Def maps aren't consistent for NewReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && \"Kill and Def maps aren't consistent for NewReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 663, __PRETTY_FUNCTION__))
662 (DefIndices[NewReg] == ~0u)) &&((((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u
)) && "Kill and Def maps aren't consistent for NewReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && \"Kill and Def maps aren't consistent for NewReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 663, __PRETTY_FUNCTION__))
663 "Kill and Def maps aren't consistent for NewReg!")((((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u
)) && "Kill and Def maps aren't consistent for NewReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u)) && \"Kill and Def maps aren't consistent for NewReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 663, __PRETTY_FUNCTION__))
;
664
665 Classes[AntiDepReg] = nullptr;
666 DefIndices[AntiDepReg] = KillIndices[AntiDepReg];
667 KillIndices[AntiDepReg] = ~0u;
668 assert(((KillIndices[AntiDepReg] == ~0u) !=((((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg
] == ~0u)) && "Kill and Def maps aren't consistent for AntiDepReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && \"Kill and Def maps aren't consistent for AntiDepReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 670, __PRETTY_FUNCTION__))
669 (DefIndices[AntiDepReg] == ~0u)) &&((((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg
] == ~0u)) && "Kill and Def maps aren't consistent for AntiDepReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && \"Kill and Def maps aren't consistent for AntiDepReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 670, __PRETTY_FUNCTION__))
670 "Kill and Def maps aren't consistent for AntiDepReg!")((((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg
] == ~0u)) && "Kill and Def maps aren't consistent for AntiDepReg!"
) ? static_cast<void> (0) : __assert_fail ("((KillIndices[AntiDepReg] == ~0u) != (DefIndices[AntiDepReg] == ~0u)) && \"Kill and Def maps aren't consistent for AntiDepReg!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/CriticalAntiDepBreaker.cpp"
, 670, __PRETTY_FUNCTION__))
;
671
672 RegRefs.erase(AntiDepReg);
673 LastNewReg[AntiDepReg] = NewReg;
674 ++Broken;
675 }
676 }
677
678 ScanInstruction(MI, Count);
679 }
680
681 return Broken;
682}