Bug Summary

File:include/llvm/ADT/APInt.h
Warning:line 983, column 15
Assigned value is garbage or undefined

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-9/lib/clang/9.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-9~svn361465/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-9~svn361465/build-llvm/include -I /build/llvm-toolchain-snapshot-9~svn361465/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/9.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-9/lib/clang/9.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-9~svn361465/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-9~svn361465=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2019-05-24-031927-21217-1 -x c++ /build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp -faddrsig

/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallBitVector.h"
28#include "llvm/ADT/SmallPtrSet.h"
29#include "llvm/ADT/SmallSet.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/Statistic.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/MemoryLocation.h"
34#include "llvm/CodeGen/DAGCombine.h"
35#include "llvm/CodeGen/ISDOpcodes.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/RuntimeLibcalls.h"
40#include "llvm/CodeGen/SelectionDAG.h"
41#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
42#include "llvm/CodeGen/SelectionDAGNodes.h"
43#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetRegisterInfo.h"
46#include "llvm/CodeGen/TargetSubtargetInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/IR/Attributes.h"
49#include "llvm/IR/Constant.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DerivedTypes.h"
52#include "llvm/IR/Function.h"
53#include "llvm/IR/LLVMContext.h"
54#include "llvm/IR/Metadata.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/CodeGen.h"
57#include "llvm/Support/CommandLine.h"
58#include "llvm/Support/Compiler.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/ErrorHandling.h"
61#include "llvm/Support/KnownBits.h"
62#include "llvm/Support/MachineValueType.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetMachine.h"
66#include "llvm/Target/TargetOptions.h"
67#include <algorithm>
68#include <cassert>
69#include <cstdint>
70#include <functional>
71#include <iterator>
72#include <string>
73#include <tuple>
74#include <utility>
75
76using namespace llvm;
77
78#define DEBUG_TYPE"dagcombine" "dagcombine"
79
80STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined", {0}, {false}}
;
81STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created", {0}, {false}}
;
82STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created", {0}, {false}}
;
83STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed", {0}, {false}}
;
84STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int", {0}, {false
}}
;
85STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced", {0}, {false}}
;
86STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops", {0}, {false}}
;
87
88static cl::opt<bool>
89CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
90 cl::desc("Enable DAG combiner's use of IR alias analysis"));
91
92static cl::opt<bool>
93UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
94 cl::desc("Enable DAG combiner's use of TBAA"));
95
96#ifndef NDEBUG
97static cl::opt<std::string>
98CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
99 cl::desc("Only use DAG-combiner alias analysis in this"
100 " function"));
101#endif
102
103/// Hidden option to stress test load slicing, i.e., when this option
104/// is enabled, load slicing bypasses most of its profitability guards.
105static cl::opt<bool>
106StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
107 cl::desc("Bypass the profitability model of load slicing"),
108 cl::init(false));
109
110static cl::opt<bool>
111 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
112 cl::desc("DAG combiner may split indexing from loads"));
113
114namespace {
115
116 class DAGCombiner {
117 SelectionDAG &DAG;
118 const TargetLowering &TLI;
119 CombineLevel Level;
120 CodeGenOpt::Level OptLevel;
121 bool LegalOperations = false;
122 bool LegalTypes = false;
123 bool ForCodeSize;
124
125 /// Worklist of all of the nodes that need to be simplified.
126 ///
127 /// This must behave as a stack -- new nodes to process are pushed onto the
128 /// back and when processing we pop off of the back.
129 ///
130 /// The worklist will not contain duplicates but may contain null entries
131 /// due to nodes being deleted from the underlying DAG.
132 SmallVector<SDNode *, 64> Worklist;
133
134 /// Mapping from an SDNode to its position on the worklist.
135 ///
136 /// This is used to find and remove nodes from the worklist (by nulling
137 /// them) when they are deleted from the underlying DAG. It relies on
138 /// stable indices of nodes within the worklist.
139 DenseMap<SDNode *, unsigned> WorklistMap;
140 /// This records all nodes attempted to add to the worklist since we
141 /// considered a new worklist entry. As we keep do not add duplicate nodes
142 /// in the worklist, this is different from the tail of the worklist.
143 SmallSetVector<SDNode *, 32> PruningList;
144
145 /// Set of nodes which have been combined (at least once).
146 ///
147 /// This is used to allow us to reliably add any operands of a DAG node
148 /// which have not yet been combined to the worklist.
149 SmallPtrSet<SDNode *, 32> CombinedNodes;
150
151 // AA - Used for DAG load/store alias analysis.
152 AliasAnalysis *AA;
153
154 /// When an instruction is simplified, add all users of the instruction to
155 /// the work lists because they might get more simplified now.
156 void AddUsersToWorklist(SDNode *N) {
157 for (SDNode *Node : N->uses())
158 AddToWorklist(Node);
159 }
160
161 // Prune potentially dangling nodes. This is called after
162 // any visit to a node, but should also be called during a visit after any
163 // failed combine which may have created a DAG node.
164 void clearAddedDanglingWorklistEntries() {
165 // Check any nodes added to the worklist to see if they are prunable.
166 while (!PruningList.empty()) {
167 auto *N = PruningList.pop_back_val();
168 if (N->use_empty())
169 recursivelyDeleteUnusedNodes(N);
170 }
171 }
172
173 SDNode *getNextWorklistEntry() {
174 // Before we do any work, remove nodes that are not in use.
175 clearAddedDanglingWorklistEntries();
176 SDNode *N = nullptr;
177 // The Worklist holds the SDNodes in order, but it may contain null
178 // entries.
179 while (!N && !Worklist.empty()) {
180 N = Worklist.pop_back_val();
181 }
182
183 if (N) {
184 bool GoodWorklistEntry = WorklistMap.erase(N);
185 (void)GoodWorklistEntry;
186 assert(GoodWorklistEntry &&((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 187, __PRETTY_FUNCTION__))
187 "Found a worklist entry without a corresponding map entry!")((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 187, __PRETTY_FUNCTION__))
;
188 }
189 return N;
190 }
191
192 /// Call the node-specific routine that folds each particular type of node.
193 SDValue visit(SDNode *N);
194
195 public:
196 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
197 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
198 OptLevel(OL), AA(AA) {
199 ForCodeSize = DAG.getMachineFunction().getFunction().hasOptSize();
200
201 MaximumLegalStoreInBits = 0;
202 for (MVT VT : MVT::all_valuetypes())
203 if (EVT(VT).isSimple() && VT != MVT::Other &&
204 TLI.isTypeLegal(EVT(VT)) &&
205 VT.getSizeInBits() >= MaximumLegalStoreInBits)
206 MaximumLegalStoreInBits = VT.getSizeInBits();
207 }
208
209 void ConsiderForPruning(SDNode *N) {
210 // Mark this for potential pruning.
211 PruningList.insert(N);
212 }
213
214 /// Add to the worklist making sure its instance is at the back (next to be
215 /// processed.)
216 void AddToWorklist(SDNode *N) {
217 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 218, __PRETTY_FUNCTION__))
218 "Deleted Node added to Worklist")((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 218, __PRETTY_FUNCTION__))
;
219
220 // Skip handle nodes as they can't usefully be combined and confuse the
221 // zero-use deletion strategy.
222 if (N->getOpcode() == ISD::HANDLENODE)
223 return;
224
225 ConsiderForPruning(N);
226
227 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
228 Worklist.push_back(N);
229 }
230
231 /// Remove all instances of N from the worklist.
232 void removeFromWorklist(SDNode *N) {
233 CombinedNodes.erase(N);
234 PruningList.remove(N);
235
236 auto It = WorklistMap.find(N);
237 if (It == WorklistMap.end())
238 return; // Not in the worklist.
239
240 // Null out the entry rather than erasing it to avoid a linear operation.
241 Worklist[It->second] = nullptr;
242 WorklistMap.erase(It);
243 }
244
245 void deleteAndRecombine(SDNode *N);
246 bool recursivelyDeleteUnusedNodes(SDNode *N);
247
248 /// Replaces all uses of the results of one DAG node with new values.
249 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
250 bool AddTo = true);
251
252 /// Replaces all uses of the results of one DAG node with new values.
253 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
254 return CombineTo(N, &Res, 1, AddTo);
255 }
256
257 /// Replaces all uses of the results of one DAG node with new values.
258 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
259 bool AddTo = true) {
260 SDValue To[] = { Res0, Res1 };
261 return CombineTo(N, To, 2, AddTo);
262 }
263
264 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
265
266 private:
267 unsigned MaximumLegalStoreInBits;
268
269 /// Check the specified integer node value to see if it can be simplified or
270 /// if things it uses can be simplified by bit propagation.
271 /// If so, return true.
272 bool SimplifyDemandedBits(SDValue Op) {
273 unsigned BitWidth = Op.getScalarValueSizeInBits();
274 APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
275 return SimplifyDemandedBits(Op, DemandedBits);
276 }
277
278 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
279 EVT VT = Op.getValueType();
280 unsigned NumElts = VT.isVector() ? VT.getVectorNumElements() : 1;
281 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
282 return SimplifyDemandedBits(Op, DemandedBits, DemandedElts);
283 }
284
285 /// Check the specified vector node value to see if it can be simplified or
286 /// if things it uses can be simplified as it only uses some of the
287 /// elements. If so, return true.
288 bool SimplifyDemandedVectorElts(SDValue Op) {
289 unsigned NumElts = Op.getValueType().getVectorNumElements();
290 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
291 return SimplifyDemandedVectorElts(Op, DemandedElts);
292 }
293
294 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
295 const APInt &DemandedElts);
296 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
297 bool AssumeSingleUse = false);
298
299 bool CombineToPreIndexedLoadStore(SDNode *N);
300 bool CombineToPostIndexedLoadStore(SDNode *N);
301 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
302 bool SliceUpLoad(SDNode *N);
303
304 // Scalars have size 0 to distinguish from singleton vectors.
305 SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
306 bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
307 bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);
308
309 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
310 /// load.
311 ///
312 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
313 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
314 /// \param EltNo index of the vector element to load.
315 /// \param OriginalLoad load that EVE came from to be replaced.
316 /// \returns EVE on success SDValue() on failure.
317 SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
318 SDValue EltNo,
319 LoadSDNode *OriginalLoad);
320 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
321 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
322 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
323 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
324 SDValue PromoteIntBinOp(SDValue Op);
325 SDValue PromoteIntShiftOp(SDValue Op);
326 SDValue PromoteExtend(SDValue Op);
327 bool PromoteLoad(SDValue Op);
328
329 /// Call the node-specific routine that knows how to fold each
330 /// particular type of node. If that doesn't do anything, try the
331 /// target-specific DAG combines.
332 SDValue combine(SDNode *N);
333
334 // Visitation implementation - Implement dag node combining for different
335 // node types. The semantics are as follows:
336 // Return Value:
337 // SDValue.getNode() == 0 - No change was made
338 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
339 // otherwise - N should be replaced by the returned Operand.
340 //
341 SDValue visitTokenFactor(SDNode *N);
342 SDValue visitMERGE_VALUES(SDNode *N);
343 SDValue visitADD(SDNode *N);
344 SDValue visitADDLike(SDNode *N);
345 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
346 SDValue visitSUB(SDNode *N);
347 SDValue visitADDSAT(SDNode *N);
348 SDValue visitSUBSAT(SDNode *N);
349 SDValue visitADDC(SDNode *N);
350 SDValue visitADDO(SDNode *N);
351 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
352 SDValue visitSUBC(SDNode *N);
353 SDValue visitSUBO(SDNode *N);
354 SDValue visitADDE(SDNode *N);
355 SDValue visitADDCARRY(SDNode *N);
356 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
357 SDValue visitSUBE(SDNode *N);
358 SDValue visitSUBCARRY(SDNode *N);
359 SDValue visitMUL(SDNode *N);
360 SDValue useDivRem(SDNode *N);
361 SDValue visitSDIV(SDNode *N);
362 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
363 SDValue visitUDIV(SDNode *N);
364 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
365 SDValue visitREM(SDNode *N);
366 SDValue visitMULHU(SDNode *N);
367 SDValue visitMULHS(SDNode *N);
368 SDValue visitSMUL_LOHI(SDNode *N);
369 SDValue visitUMUL_LOHI(SDNode *N);
370 SDValue visitMULO(SDNode *N);
371 SDValue visitIMINMAX(SDNode *N);
372 SDValue visitAND(SDNode *N);
373 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
374 SDValue visitOR(SDNode *N);
375 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
376 SDValue visitXOR(SDNode *N);
377 SDValue SimplifyVBinOp(SDNode *N);
378 SDValue visitSHL(SDNode *N);
379 SDValue visitSRA(SDNode *N);
380 SDValue visitSRL(SDNode *N);
381 SDValue visitFunnelShift(SDNode *N);
382 SDValue visitRotate(SDNode *N);
383 SDValue visitABS(SDNode *N);
384 SDValue visitBSWAP(SDNode *N);
385 SDValue visitBITREVERSE(SDNode *N);
386 SDValue visitCTLZ(SDNode *N);
387 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
388 SDValue visitCTTZ(SDNode *N);
389 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
390 SDValue visitCTPOP(SDNode *N);
391 SDValue visitSELECT(SDNode *N);
392 SDValue visitVSELECT(SDNode *N);
393 SDValue visitSELECT_CC(SDNode *N);
394 SDValue visitSETCC(SDNode *N);
395 SDValue visitSETCCCARRY(SDNode *N);
396 SDValue visitSIGN_EXTEND(SDNode *N);
397 SDValue visitZERO_EXTEND(SDNode *N);
398 SDValue visitANY_EXTEND(SDNode *N);
399 SDValue visitAssertExt(SDNode *N);
400 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
401 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
402 SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
403 SDValue visitTRUNCATE(SDNode *N);
404 SDValue visitBITCAST(SDNode *N);
405 SDValue visitBUILD_PAIR(SDNode *N);
406 SDValue visitFADD(SDNode *N);
407 SDValue visitFSUB(SDNode *N);
408 SDValue visitFMUL(SDNode *N);
409 SDValue visitFMA(SDNode *N);
410 SDValue visitFDIV(SDNode *N);
411 SDValue visitFREM(SDNode *N);
412 SDValue visitFSQRT(SDNode *N);
413 SDValue visitFCOPYSIGN(SDNode *N);
414 SDValue visitFPOW(SDNode *N);
415 SDValue visitSINT_TO_FP(SDNode *N);
416 SDValue visitUINT_TO_FP(SDNode *N);
417 SDValue visitFP_TO_SINT(SDNode *N);
418 SDValue visitFP_TO_UINT(SDNode *N);
419 SDValue visitFP_ROUND(SDNode *N);
420 SDValue visitFP_ROUND_INREG(SDNode *N);
421 SDValue visitFP_EXTEND(SDNode *N);
422 SDValue visitFNEG(SDNode *N);
423 SDValue visitFABS(SDNode *N);
424 SDValue visitFCEIL(SDNode *N);
425 SDValue visitFTRUNC(SDNode *N);
426 SDValue visitFFLOOR(SDNode *N);
427 SDValue visitFMINNUM(SDNode *N);
428 SDValue visitFMAXNUM(SDNode *N);
429 SDValue visitFMINIMUM(SDNode *N);
430 SDValue visitFMAXIMUM(SDNode *N);
431 SDValue visitBRCOND(SDNode *N);
432 SDValue visitBR_CC(SDNode *N);
433 SDValue visitLOAD(SDNode *N);
434
435 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
436 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
437
438 SDValue visitSTORE(SDNode *N);
439 SDValue visitLIFETIME_END(SDNode *N);
440 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
441 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
442 SDValue visitBUILD_VECTOR(SDNode *N);
443 SDValue visitCONCAT_VECTORS(SDNode *N);
444 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
445 SDValue visitVECTOR_SHUFFLE(SDNode *N);
446 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
447 SDValue visitINSERT_SUBVECTOR(SDNode *N);
448 SDValue visitMLOAD(SDNode *N);
449 SDValue visitMSTORE(SDNode *N);
450 SDValue visitMGATHER(SDNode *N);
451 SDValue visitMSCATTER(SDNode *N);
452 SDValue visitFP_TO_FP16(SDNode *N);
453 SDValue visitFP16_TO_FP(SDNode *N);
454 SDValue visitVECREDUCE(SDNode *N);
455
456 SDValue visitFADDForFMACombine(SDNode *N);
457 SDValue visitFSUBForFMACombine(SDNode *N);
458 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
459
460 SDValue XformToShuffleWithZero(SDNode *N);
461 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
462 SDValue N1);
463 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
464 SDValue N1, SDNodeFlags Flags);
465
466 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
467
468 SDValue foldSelectOfConstants(SDNode *N);
469 SDValue foldVSelectOfConstants(SDNode *N);
470 SDValue foldBinOpIntoSelect(SDNode *BO);
471 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
472 SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
473 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
474 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
475 SDValue N2, SDValue N3, ISD::CondCode CC,
476 bool NotExtCompare = false);
477 SDValue convertSelectOfFPConstantsToLoadOffset(
478 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
479 ISD::CondCode CC);
480 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
481 SDValue N2, SDValue N3, ISD::CondCode CC);
482 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
483 const SDLoc &DL);
484 SDValue unfoldMaskedMerge(SDNode *N);
485 SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
486 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
487 const SDLoc &DL, bool foldBooleans);
488 SDValue rebuildSetCC(SDValue N);
489
490 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
491 SDValue &CC) const;
492 bool isOneUseSetCC(SDValue N) const;
493
494 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
495 unsigned HiOp);
496 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
497 SDValue CombineExtLoad(SDNode *N);
498 SDValue CombineZExtLogicopShiftLoad(SDNode *N);
499 SDValue combineRepeatedFPDivisors(SDNode *N);
500 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
501 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
502 SDValue BuildSDIV(SDNode *N);
503 SDValue BuildSDIVPow2(SDNode *N);
504 SDValue BuildUDIV(SDNode *N);
505 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
506 SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags);
507 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
508 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
509 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
510 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
511 SDNodeFlags Flags, bool Reciprocal);
512 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
513 SDNodeFlags Flags, bool Reciprocal);
514 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
515 bool DemandHighBits = true);
516 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
517 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
518 SDValue InnerPos, SDValue InnerNeg,
519 unsigned PosOpcode, unsigned NegOpcode,
520 const SDLoc &DL);
521 SDNode *MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
522 SDValue MatchLoadCombine(SDNode *N);
523 SDValue ReduceLoadWidth(SDNode *N);
524 SDValue ReduceLoadOpStoreWidth(SDNode *N);
525 SDValue splitMergedValStore(StoreSDNode *ST);
526 SDValue TransformFPLoadStorePair(SDNode *N);
527 SDValue convertBuildVecZextToZext(SDNode *N);
528 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
529 SDValue reduceBuildVecToShuffle(SDNode *N);
530 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
531 ArrayRef<int> VectorMask, SDValue VecIn1,
532 SDValue VecIn2, unsigned LeftIdx,
533 bool DidSplitVec);
534 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
535
536 /// Walk up chain skipping non-aliasing memory nodes,
537 /// looking for aliasing nodes and adding them to the Aliases vector.
538 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
539 SmallVectorImpl<SDValue> &Aliases);
540
541 /// Return true if there is any possibility that the two addresses overlap.
542 bool isAlias(SDNode *Op0, SDNode *Op1) const;
543
544 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
545 /// chain (aliasing node.)
546 SDValue FindBetterChain(SDNode *N, SDValue Chain);
547
548 /// Try to replace a store and any possibly adjacent stores on
549 /// consecutive chains with better chains. Return true only if St is
550 /// replaced.
551 ///
552 /// Notice that other chains may still be replaced even if the function
553 /// returns false.
554 bool findBetterNeighborChains(StoreSDNode *St);
555
556 // Helper for findBetterNeighborChains. Walk up store chain add additional
557 // chained stores that do not overlap and can be parallelized.
558 bool parallelizeChainedStores(StoreSDNode *St);
559
560 /// Holds a pointer to an LSBaseSDNode as well as information on where it
561 /// is located in a sequence of memory operations connected by a chain.
562 struct MemOpLink {
563 // Ptr to the mem node.
564 LSBaseSDNode *MemNode;
565
566 // Offset from the base ptr.
567 int64_t OffsetFromBase;
568
569 MemOpLink(LSBaseSDNode *N, int64_t Offset)
570 : MemNode(N), OffsetFromBase(Offset) {}
571 };
572
573 /// This is a helper function for visitMUL to check the profitability
574 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
575 /// MulNode is the original multiply, AddNode is (add x, c1),
576 /// and ConstNode is c2.
577 bool isMulAddWithConstProfitable(SDNode *MulNode,
578 SDValue &AddNode,
579 SDValue &ConstNode);
580
581 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
582 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
583 /// the type of the loaded value to be extended.
584 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
585 EVT LoadResultTy, EVT &ExtVT);
586
587 /// Helper function to calculate whether the given Load/Store can have its
588 /// width reduced to ExtVT.
589 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
590 EVT &MemVT, unsigned ShAmt = 0);
591
592 /// Used by BackwardsPropagateMask to find suitable loads.
593 bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
594 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
595 ConstantSDNode *Mask, SDNode *&NodeToMask);
596 /// Attempt to propagate a given AND node back to load leaves so that they
597 /// can be combined into narrow loads.
598 bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
599
600 /// Helper function for MergeConsecutiveStores which merges the
601 /// component store chains.
602 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
603 unsigned NumStores);
604
605 /// This is a helper function for MergeConsecutiveStores. When the
606 /// source elements of the consecutive stores are all constants or
607 /// all extracted vector elements, try to merge them into one
608 /// larger store introducing bitcasts if necessary. \return True
609 /// if a merged store was created.
610 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
611 EVT MemVT, unsigned NumStores,
612 bool IsConstantSrc, bool UseVector,
613 bool UseTrunc);
614
615 /// This is a helper function for MergeConsecutiveStores. Stores
616 /// that potentially may be merged with St are placed in
617 /// StoreNodes. RootNode is a chain predecessor to all store
618 /// candidates.
619 void getStoreMergeCandidates(StoreSDNode *St,
620 SmallVectorImpl<MemOpLink> &StoreNodes,
621 SDNode *&Root);
622
623 /// Helper function for MergeConsecutiveStores. Checks if
624 /// candidate stores have indirect dependency through their
625 /// operands. RootNode is the predecessor to all stores calculated
626 /// by getStoreMergeCandidates and is used to prune the dependency check.
627 /// \return True if safe to merge.
628 bool checkMergeStoreCandidatesForDependencies(
629 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
630 SDNode *RootNode);
631
632 /// Merge consecutive store operations into a wide store.
633 /// This optimization uses wide integers or vectors when possible.
634 /// \return number of stores that were merged into a merged store (the
635 /// affected nodes are stored as a prefix in \p StoreNodes).
636 bool MergeConsecutiveStores(StoreSDNode *St);
637
638 /// Try to transform a truncation where C is a constant:
639 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
640 ///
641 /// \p N needs to be a truncation and its first operand an AND. Other
642 /// requirements are checked by the function (e.g. that trunc is
643 /// single-use) and if missed an empty SDValue is returned.
644 SDValue distributeTruncateThroughAnd(SDNode *N);
645
646 /// Helper function to determine whether the target supports operation
647 /// given by \p Opcode for type \p VT, that is, whether the operation
648 /// is legal or custom before legalizing operations, and whether is
649 /// legal (but not custom) after legalization.
650 bool hasOperation(unsigned Opcode, EVT VT) {
651 if (LegalOperations)
652 return TLI.isOperationLegal(Opcode, VT);
653 return TLI.isOperationLegalOrCustom(Opcode, VT);
654 }
655
656 public:
657 /// Runs the dag combiner on all nodes in the work list
658 void Run(CombineLevel AtLevel);
659
660 SelectionDAG &getDAG() const { return DAG; }
661
662 /// Returns a type large enough to hold any valid shift amount - before type
663 /// legalization these can be huge.
664 EVT getShiftAmountTy(EVT LHSTy) {
665 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")((LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? static_cast<void> (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 665, __PRETTY_FUNCTION__))
;
666 return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
667 }
668
669 /// This method returns true if we are running before type legalization or
670 /// if the specified VT is legal.
671 bool isTypeLegal(const EVT &VT) {
672 if (!LegalTypes) return true;
673 return TLI.isTypeLegal(VT);
674 }
675
676 /// Convenience wrapper around TargetLowering::getSetCCResultType
677 EVT getSetCCResultType(EVT VT) const {
678 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
679 }
680
681 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
682 SDValue OrigLoad, SDValue ExtLoad,
683 ISD::NodeType ExtType);
684 };
685
686/// This class is a DAGUpdateListener that removes any deleted
687/// nodes from the worklist.
688class WorklistRemover : public SelectionDAG::DAGUpdateListener {
689 DAGCombiner &DC;
690
691public:
692 explicit WorklistRemover(DAGCombiner &dc)
693 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
694
695 void NodeDeleted(SDNode *N, SDNode *E) override {
696 DC.removeFromWorklist(N);
697 }
698};
699
700class WorklistInserter : public SelectionDAG::DAGUpdateListener {
701 DAGCombiner &DC;
702
703public:
704 explicit WorklistInserter(DAGCombiner &dc)
705 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
706
707 // FIXME: Ideally we could add N to the worklist, but this causes exponential
708 // compile time costs in large DAGs, e.g. Halide.
709 void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
710};
711
712} // end anonymous namespace
713
714//===----------------------------------------------------------------------===//
715// TargetLowering::DAGCombinerInfo implementation
716//===----------------------------------------------------------------------===//
717
718void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
719 ((DAGCombiner*)DC)->AddToWorklist(N);
720}
721
722SDValue TargetLowering::DAGCombinerInfo::
723CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
724 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
725}
726
727SDValue TargetLowering::DAGCombinerInfo::
728CombineTo(SDNode *N, SDValue Res, bool AddTo) {
729 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
730}
731
732SDValue TargetLowering::DAGCombinerInfo::
733CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
734 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
735}
736
737void TargetLowering::DAGCombinerInfo::
738CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
739 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
740}
741
742//===----------------------------------------------------------------------===//
743// Helper Functions
744//===----------------------------------------------------------------------===//
745
746void DAGCombiner::deleteAndRecombine(SDNode *N) {
747 removeFromWorklist(N);
748
749 // If the operands of this node are only used by the node, they will now be
750 // dead. Make sure to re-visit them and recursively delete dead nodes.
751 for (const SDValue &Op : N->ops())
752 // For an operand generating multiple values, one of the values may
753 // become dead allowing further simplification (e.g. split index
754 // arithmetic from an indexed load).
755 if (Op->hasOneUse() || Op->getNumValues() > 1)
756 AddToWorklist(Op.getNode());
757
758 DAG.DeleteNode(N);
759}
760
761/// Return 1 if we can compute the negated form of the specified expression for
762/// the same cost as the expression itself, or 2 if we can compute the negated
763/// form more cheaply than the expression itself.
764static char isNegatibleForFree(SDValue Op, bool LegalOperations,
765 const TargetLowering &TLI,
766 const TargetOptions *Options,
767 bool ForCodeSize,
768 unsigned Depth = 0) {
769 // fneg is removable even if it has multiple uses.
770 if (Op.getOpcode() == ISD::FNEG) return 2;
771
772 // Don't allow anything with multiple uses unless we know it is free.
773 EVT VT = Op.getValueType();
774 const SDNodeFlags Flags = Op->getFlags();
775 if (!Op.hasOneUse())
776 if (!(Op.getOpcode() == ISD::FP_EXTEND &&
777 TLI.isFPExtFree(VT, Op.getOperand(0).getValueType())))
778 return 0;
779
780 // Don't recurse exponentially.
781 if (Depth > 6) return 0;
782
783 switch (Op.getOpcode()) {
784 default: return false;
785 case ISD::ConstantFP: {
786 if (!LegalOperations)
787 return 1;
788
789 // Don't invert constant FP values after legalization unless the target says
790 // the negated constant is legal.
791 return TLI.isOperationLegal(ISD::ConstantFP, VT) ||
792 TLI.isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT,
793 ForCodeSize);
794 }
795 case ISD::FADD:
796 if (!Options->UnsafeFPMath && !Flags.hasNoSignedZeros())
797 return 0;
798
799 // After operation legalization, it might not be legal to create new FSUBs.
800 if (LegalOperations && !TLI.isOperationLegalOrCustom(ISD::FSUB, VT))
801 return 0;
802
803 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
804 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
805 Options, ForCodeSize, Depth + 1))
806 return V;
807 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
808 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
809 ForCodeSize, Depth + 1);
810 case ISD::FSUB:
811 // We can't turn -(A-B) into B-A when we honor signed zeros.
812 if (!Options->NoSignedZerosFPMath &&
813 !Flags.hasNoSignedZeros())
814 return 0;
815
816 // fold (fneg (fsub A, B)) -> (fsub B, A)
817 return 1;
818
819 case ISD::FMUL:
820 case ISD::FDIV:
821 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
822 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
823 Options, ForCodeSize, Depth + 1))
824 return V;
825
826 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
827 ForCodeSize, Depth + 1);
828
829 case ISD::FP_EXTEND:
830 case ISD::FP_ROUND:
831 case ISD::FSIN:
832 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
833 ForCodeSize, Depth + 1);
834 }
835}
836
837/// If isNegatibleForFree returns true, return the newly negated expression.
838static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
839 bool LegalOperations, bool ForCodeSize,
840 unsigned Depth = 0) {
841 const TargetOptions &Options = DAG.getTarget().Options;
842 // fneg is removable even if it has multiple uses.
843 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
844
845 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree")((Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"
) ? static_cast<void> (0) : __assert_fail ("Depth <= 6 && \"GetNegatedExpression doesn't match isNegatibleForFree\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 845, __PRETTY_FUNCTION__))
;
846
847 const SDNodeFlags Flags = Op.getNode()->getFlags();
848
849 switch (Op.getOpcode()) {
850 default: llvm_unreachable("Unknown code")::llvm::llvm_unreachable_internal("Unknown code", "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 850)
;
851 case ISD::ConstantFP: {
852 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
853 V.changeSign();
854 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
855 }
856 case ISD::FADD:
857 assert(Options.UnsafeFPMath || Flags.hasNoSignedZeros())((Options.UnsafeFPMath || Flags.hasNoSignedZeros()) ? static_cast
<void> (0) : __assert_fail ("Options.UnsafeFPMath || Flags.hasNoSignedZeros()"
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 857, __PRETTY_FUNCTION__))
;
858
859 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
860 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
861 DAG.getTargetLoweringInfo(), &Options, ForCodeSize,
862 Depth+1))
863 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
864 GetNegatedExpression(Op.getOperand(0), DAG,
865 LegalOperations, ForCodeSize,
866 Depth+1),
867 Op.getOperand(1), Flags);
868 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
869 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
870 GetNegatedExpression(Op.getOperand(1), DAG,
871 LegalOperations, ForCodeSize,
872 Depth+1),
873 Op.getOperand(0), Flags);
874 case ISD::FSUB:
875 // fold (fneg (fsub 0, B)) -> B
876 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
877 if (N0CFP->isZero())
878 return Op.getOperand(1);
879
880 // fold (fneg (fsub A, B)) -> (fsub B, A)
881 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
882 Op.getOperand(1), Op.getOperand(0), Flags);
883
884 case ISD::FMUL:
885 case ISD::FDIV:
886 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
887 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
888 DAG.getTargetLoweringInfo(), &Options, ForCodeSize,
889 Depth+1))
890 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
891 GetNegatedExpression(Op.getOperand(0), DAG,
892 LegalOperations, ForCodeSize,
893 Depth+1),
894 Op.getOperand(1), Flags);
895
896 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
897 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
898 Op.getOperand(0),
899 GetNegatedExpression(Op.getOperand(1), DAG,
900 LegalOperations, ForCodeSize,
901 Depth+1), Flags);
902
903 case ISD::FP_EXTEND:
904 case ISD::FSIN:
905 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
906 GetNegatedExpression(Op.getOperand(0), DAG,
907 LegalOperations, ForCodeSize,
908 Depth+1));
909 case ISD::FP_ROUND:
910 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
911 GetNegatedExpression(Op.getOperand(0), DAG,
912 LegalOperations, ForCodeSize,
913 Depth+1),
914 Op.getOperand(1));
915 }
916}
917
918// APInts must be the same size for most operations, this helper
919// function zero extends the shorter of the pair so that they match.
920// We provide an Offset so that we can create bitwidths that won't overflow.
921static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
922 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
923 LHS = LHS.zextOrSelf(Bits);
924 RHS = RHS.zextOrSelf(Bits);
925}
926
927// Return true if this node is a setcc, or is a select_cc
928// that selects between the target values used for true and false, making it
929// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
930// the appropriate nodes based on the type of node we are checking. This
931// simplifies life a bit for the callers.
932bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
933 SDValue &CC) const {
934 if (N.getOpcode() == ISD::SETCC) {
935 LHS = N.getOperand(0);
936 RHS = N.getOperand(1);
937 CC = N.getOperand(2);
938 return true;
939 }
940
941 if (N.getOpcode() != ISD::SELECT_CC ||
942 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
943 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
944 return false;
945
946 if (TLI.getBooleanContents(N.getValueType()) ==
947 TargetLowering::UndefinedBooleanContent)
948 return false;
949
950 LHS = N.getOperand(0);
951 RHS = N.getOperand(1);
952 CC = N.getOperand(4);
953 return true;
954}
955
956/// Return true if this is a SetCC-equivalent operation with only one use.
957/// If this is true, it allows the users to invert the operation for free when
958/// it is profitable to do so.
959bool DAGCombiner::isOneUseSetCC(SDValue N) const {
960 SDValue N0, N1, N2;
961 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
962 return true;
963 return false;
964}
965
966// Returns the SDNode if it is a constant float BuildVector
967// or constant float.
968static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
969 if (isa<ConstantFPSDNode>(N))
970 return N.getNode();
971 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
972 return N.getNode();
973 return nullptr;
974}
975
976// Determines if it is a constant integer or a build vector of constant
977// integers (and undefs).
978// Do not permit build vector implicit truncation.
979static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
980 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
981 return !(Const->isOpaque() && NoOpaques);
982 if (N.getOpcode() != ISD::BUILD_VECTOR)
983 return false;
984 unsigned BitWidth = N.getScalarValueSizeInBits();
985 for (const SDValue &Op : N->op_values()) {
986 if (Op.isUndef())
987 continue;
988 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
989 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
990 (Const->isOpaque() && NoOpaques))
991 return false;
992 }
993 return true;
994}
995
996// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
997// undef's.
998static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
999 if (V.getOpcode() != ISD::BUILD_VECTOR)
1000 return false;
1001 return isConstantOrConstantVector(V, NoOpaques) ||
1002 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
1003}
1004
1005// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
1006// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
1007SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
1008 SDValue N0, SDValue N1) {
1009 EVT VT = N0.getValueType();
1010
1011 if (N0.getOpcode() != Opc)
1012 return SDValue();
1013
1014 // Don't reassociate reductions.
1015 if (N0->getFlags().hasVectorReduction())
1016 return SDValue();
1017
1018 if (SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
1019 if (SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
1020 // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
1021 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, C1, C2))
1022 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
1023 return SDValue();
1024 }
1025 if (N0.hasOneUse()) {
1026 // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
1027 // iff (op x, c1) has one use
1028 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
1029 if (!OpNode.getNode())
1030 return SDValue();
1031 AddToWorklist(OpNode.getNode());
1032 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
1033 }
1034 }
1035 return SDValue();
1036}
1037
1038// Try to reassociate commutative binops.
1039SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1040 SDValue N1, SDNodeFlags Flags) {
1041 assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")((TLI.isCommutativeBinOp(Opc) && "Operation not commutative."
) ? static_cast<void> (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1041, __PRETTY_FUNCTION__))
;
1042 // Don't reassociate reductions.
1043 if (Flags.hasVectorReduction())
1044 return SDValue();
1045
1046 // Floating-point reassociation is not allowed without loose FP math.
1047 if (N0.getValueType().isFloatingPoint() ||
1048 N1.getValueType().isFloatingPoint())
1049 if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
1050 return SDValue();
1051
1052 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
1053 return Combined;
1054 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
1055 return Combined;
1056 return SDValue();
1057}
1058
1059SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1060 bool AddTo) {
1061 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")((N->getNumValues() == NumTo && "Broken CombineTo call!"
) ? static_cast<void> (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1061, __PRETTY_FUNCTION__))
;
1062 ++NodesCombined;
1063 LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1064 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1065 dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
;
1066 for (unsigned i = 0, e = NumTo; i != e; ++i)
1067 assert((!To[i].getNode() ||(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1069, __PRETTY_FUNCTION__))
1068 N->getValueType(i) == To[i].getValueType()) &&(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1069, __PRETTY_FUNCTION__))
1069 "Cannot combine value to value of different type!")(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1069, __PRETTY_FUNCTION__))
;
1070
1071 WorklistRemover DeadNodes(*this);
1072 DAG.ReplaceAllUsesWith(N, To);
1073 if (AddTo) {
1074 // Push the new nodes and any users onto the worklist
1075 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1076 if (To[i].getNode()) {
1077 AddToWorklist(To[i].getNode());
1078 AddUsersToWorklist(To[i].getNode());
1079 }
1080 }
1081 }
1082
1083 // Finally, if the node is now dead, remove it from the graph. The node
1084 // may not be dead if the replacement process recursively simplified to
1085 // something else needing this node.
1086 if (N->use_empty())
1087 deleteAndRecombine(N);
1088 return SDValue(N, 0);
1089}
1090
1091void DAGCombiner::
1092CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1093 // Replace all uses. If any nodes become isomorphic to other nodes and
1094 // are deleted, make sure to remove them from our worklist.
1095 WorklistRemover DeadNodes(*this);
1096 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1097
1098 // Push the new node and any (possibly new) users onto the worklist.
1099 AddToWorklist(TLO.New.getNode());
1100 AddUsersToWorklist(TLO.New.getNode());
1101
1102 // Finally, if the node is now dead, remove it from the graph. The node
1103 // may not be dead if the replacement process recursively simplified to
1104 // something else needing this node.
1105 if (TLO.Old.getNode()->use_empty())
1106 deleteAndRecombine(TLO.Old.getNode());
1107}
1108
1109/// Check the specified integer node value to see if it can be simplified or if
1110/// things it uses can be simplified by bit propagation. If so, return true.
1111bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
1112 const APInt &DemandedElts) {
1113 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1114 KnownBits Known;
1115 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO))
1116 return false;
1117
1118 // Revisit the node.
1119 AddToWorklist(Op.getNode());
1120
1121 // Replace the old value with the new one.
1122 ++NodesCombined;
1123 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1124 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1125 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1126
1127 CommitTargetLoweringOpt(TLO);
1128 return true;
1129}
1130
1131/// Check the specified vector node value to see if it can be simplified or
1132/// if things it uses can be simplified as it only uses some of the elements.
1133/// If so, return true.
1134bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
1135 const APInt &DemandedElts,
1136 bool AssumeSingleUse) {
1137 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1138 APInt KnownUndef, KnownZero;
1139 if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
1140 TLO, 0, AssumeSingleUse))
1141 return false;
1142
1143 // Revisit the node.
1144 AddToWorklist(Op.getNode());
1145
1146 // Replace the old value with the new one.
1147 ++NodesCombined;
1148 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1149 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1150 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1151
1152 CommitTargetLoweringOpt(TLO);
1153 return true;
1154}
1155
1156void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1157 SDLoc DL(Load);
1158 EVT VT = Load->getValueType(0);
1159 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1160
1161 LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1162 Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1163 WorklistRemover DeadNodes(*this);
1164 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1165 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1166 deleteAndRecombine(Load);
1167 AddToWorklist(Trunc.getNode());
1168}
1169
1170SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1171 Replace = false;
1172 SDLoc DL(Op);
1173 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1174 LoadSDNode *LD = cast<LoadSDNode>(Op);
1175 EVT MemVT = LD->getMemoryVT();
1176 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1177 : LD->getExtensionType();
1178 Replace = true;
1179 return DAG.getExtLoad(ExtType, DL, PVT,
1180 LD->getChain(), LD->getBasePtr(),
1181 MemVT, LD->getMemOperand());
1182 }
1183
1184 unsigned Opc = Op.getOpcode();
1185 switch (Opc) {
1186 default: break;
1187 case ISD::AssertSext:
1188 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1189 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1190 break;
1191 case ISD::AssertZext:
1192 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1193 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1194 break;
1195 case ISD::Constant: {
1196 unsigned ExtOpc =
1197 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1198 return DAG.getNode(ExtOpc, DL, PVT, Op);
1199 }
1200 }
1201
1202 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1203 return SDValue();
1204 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1205}
1206
1207SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1208 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1209 return SDValue();
1210 EVT OldVT = Op.getValueType();
1211 SDLoc DL(Op);
1212 bool Replace = false;
1213 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1214 if (!NewOp.getNode())
1215 return SDValue();
1216 AddToWorklist(NewOp.getNode());
1217
1218 if (Replace)
1219 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1220 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1221 DAG.getValueType(OldVT));
1222}
1223
1224SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1225 EVT OldVT = Op.getValueType();
1226 SDLoc DL(Op);
1227 bool Replace = false;
1228 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1229 if (!NewOp.getNode())
1230 return SDValue();
1231 AddToWorklist(NewOp.getNode());
1232
1233 if (Replace)
1234 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1235 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1236}
1237
1238/// Promote the specified integer binary operation if the target indicates it is
1239/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1240/// i32 since i16 instructions are longer.
1241SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1242 if (!LegalOperations)
1243 return SDValue();
1244
1245 EVT VT = Op.getValueType();
1246 if (VT.isVector() || !VT.isInteger())
1247 return SDValue();
1248
1249 // If operation type is 'undesirable', e.g. i16 on x86, consider
1250 // promoting it.
1251 unsigned Opc = Op.getOpcode();
1252 if (TLI.isTypeDesirableForOp(Opc, VT))
1253 return SDValue();
1254
1255 EVT PVT = VT;
1256 // Consult target whether it is a good idea to promote this operation and
1257 // what's the right type to promote it to.
1258 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1259 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1259, __PRETTY_FUNCTION__))
;
1260
1261 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1262
1263 bool Replace0 = false;
1264 SDValue N0 = Op.getOperand(0);
1265 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1266
1267 bool Replace1 = false;
1268 SDValue N1 = Op.getOperand(1);
1269 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1270 SDLoc DL(Op);
1271
1272 SDValue RV =
1273 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1274
1275 // We are always replacing N0/N1's use in N and only need
1276 // additional replacements if there are additional uses.
1277 Replace0 &= !N0->hasOneUse();
1278 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1279
1280 // Combine Op here so it is preserved past replacements.
1281 CombineTo(Op.getNode(), RV);
1282
1283 // If operands have a use ordering, make sure we deal with
1284 // predecessor first.
1285 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1286 std::swap(N0, N1);
1287 std::swap(NN0, NN1);
1288 }
1289
1290 if (Replace0) {
1291 AddToWorklist(NN0.getNode());
1292 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1293 }
1294 if (Replace1) {
1295 AddToWorklist(NN1.getNode());
1296 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1297 }
1298 return Op;
1299 }
1300 return SDValue();
1301}
1302
1303/// Promote the specified integer shift operation if the target indicates it is
1304/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1305/// i32 since i16 instructions are longer.
1306SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1307 if (!LegalOperations)
1308 return SDValue();
1309
1310 EVT VT = Op.getValueType();
1311 if (VT.isVector() || !VT.isInteger())
1312 return SDValue();
1313
1314 // If operation type is 'undesirable', e.g. i16 on x86, consider
1315 // promoting it.
1316 unsigned Opc = Op.getOpcode();
1317 if (TLI.isTypeDesirableForOp(Opc, VT))
1318 return SDValue();
1319
1320 EVT PVT = VT;
1321 // Consult target whether it is a good idea to promote this operation and
1322 // what's the right type to promote it to.
1323 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1324 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1324, __PRETTY_FUNCTION__))
;
1325
1326 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1327
1328 bool Replace = false;
1329 SDValue N0 = Op.getOperand(0);
1330 SDValue N1 = Op.getOperand(1);
1331 if (Opc == ISD::SRA)
1332 N0 = SExtPromoteOperand(N0, PVT);
1333 else if (Opc == ISD::SRL)
1334 N0 = ZExtPromoteOperand(N0, PVT);
1335 else
1336 N0 = PromoteOperand(N0, PVT, Replace);
1337
1338 if (!N0.getNode())
1339 return SDValue();
1340
1341 SDLoc DL(Op);
1342 SDValue RV =
1343 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1344
1345 AddToWorklist(N0.getNode());
1346 if (Replace)
1347 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1348
1349 // Deal with Op being deleted.
1350 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1351 return RV;
1352 }
1353 return SDValue();
1354}
1355
1356SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1357 if (!LegalOperations)
1358 return SDValue();
1359
1360 EVT VT = Op.getValueType();
1361 if (VT.isVector() || !VT.isInteger())
1362 return SDValue();
1363
1364 // If operation type is 'undesirable', e.g. i16 on x86, consider
1365 // promoting it.
1366 unsigned Opc = Op.getOpcode();
1367 if (TLI.isTypeDesirableForOp(Opc, VT))
1368 return SDValue();
1369
1370 EVT PVT = VT;
1371 // Consult target whether it is a good idea to promote this operation and
1372 // what's the right type to promote it to.
1373 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1374 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1374, __PRETTY_FUNCTION__))
;
1375 // fold (aext (aext x)) -> (aext x)
1376 // fold (aext (zext x)) -> (zext x)
1377 // fold (aext (sext x)) -> (sext x)
1378 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1379 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1380 }
1381 return SDValue();
1382}
1383
1384bool DAGCombiner::PromoteLoad(SDValue Op) {
1385 if (!LegalOperations)
1386 return false;
1387
1388 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1389 return false;
1390
1391 EVT VT = Op.getValueType();
1392 if (VT.isVector() || !VT.isInteger())
1393 return false;
1394
1395 // If operation type is 'undesirable', e.g. i16 on x86, consider
1396 // promoting it.
1397 unsigned Opc = Op.getOpcode();
1398 if (TLI.isTypeDesirableForOp(Opc, VT))
1399 return false;
1400
1401 EVT PVT = VT;
1402 // Consult target whether it is a good idea to promote this operation and
1403 // what's the right type to promote it to.
1404 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1405 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1405, __PRETTY_FUNCTION__))
;
1406
1407 SDLoc DL(Op);
1408 SDNode *N = Op.getNode();
1409 LoadSDNode *LD = cast<LoadSDNode>(N);
1410 EVT MemVT = LD->getMemoryVT();
1411 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1412 : LD->getExtensionType();
1413 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1414 LD->getChain(), LD->getBasePtr(),
1415 MemVT, LD->getMemOperand());
1416 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1417
1418 LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1419 Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1420 WorklistRemover DeadNodes(*this);
1421 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1422 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1423 deleteAndRecombine(N);
1424 AddToWorklist(Result.getNode());
1425 return true;
1426 }
1427 return false;
1428}
1429
1430/// Recursively delete a node which has no uses and any operands for
1431/// which it is the only use.
1432///
1433/// Note that this both deletes the nodes and removes them from the worklist.
1434/// It also adds any nodes who have had a user deleted to the worklist as they
1435/// may now have only one use and subject to other combines.
1436bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1437 if (!N->use_empty())
1438 return false;
1439
1440 SmallSetVector<SDNode *, 16> Nodes;
1441 Nodes.insert(N);
1442 do {
1443 N = Nodes.pop_back_val();
1444 if (!N)
1445 continue;
1446
1447 if (N->use_empty()) {
1448 for (const SDValue &ChildN : N->op_values())
1449 Nodes.insert(ChildN.getNode());
1450
1451 removeFromWorklist(N);
1452 DAG.DeleteNode(N);
1453 } else {
1454 AddToWorklist(N);
1455 }
1456 } while (!Nodes.empty());
1457 return true;
1458}
1459
1460//===----------------------------------------------------------------------===//
1461// Main DAG Combiner implementation
1462//===----------------------------------------------------------------------===//
1463
1464void DAGCombiner::Run(CombineLevel AtLevel) {
1465 // set the instance variables, so that the various visit routines may use it.
1466 Level = AtLevel;
1467 LegalOperations = Level >= AfterLegalizeVectorOps;
1468 LegalTypes = Level >= AfterLegalizeTypes;
1469
1470 WorklistInserter AddNodes(*this);
1471
1472 // Add all the dag nodes to the worklist.
1473 for (SDNode &Node : DAG.allnodes())
1474 AddToWorklist(&Node);
1475
1476 // Create a dummy node (which is not added to allnodes), that adds a reference
1477 // to the root node, preventing it from being deleted, and tracking any
1478 // changes of the root.
1479 HandleSDNode Dummy(DAG.getRoot());
1480
1481 // While we have a valid worklist entry node, try to combine it.
1482 while (SDNode *N = getNextWorklistEntry()) {
1483 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1484 // N is deleted from the DAG, since they too may now be dead or may have a
1485 // reduced number of uses, allowing other xforms.
1486 if (recursivelyDeleteUnusedNodes(N))
1487 continue;
1488
1489 WorklistRemover DeadNodes(*this);
1490
1491 // If this combine is running after legalizing the DAG, re-legalize any
1492 // nodes pulled off the worklist.
1493 if (Level == AfterLegalizeDAG) {
1494 SmallSetVector<SDNode *, 16> UpdatedNodes;
1495 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1496
1497 for (SDNode *LN : UpdatedNodes) {
1498 AddToWorklist(LN);
1499 AddUsersToWorklist(LN);
1500 }
1501 if (!NIsValid)
1502 continue;
1503 }
1504
1505 LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1506
1507 // Add any operands of the new node which have not yet been combined to the
1508 // worklist as well. Because the worklist uniques things already, this
1509 // won't repeatedly process the same operand.
1510 CombinedNodes.insert(N);
1511 for (const SDValue &ChildN : N->op_values())
1512 if (!CombinedNodes.count(ChildN.getNode()))
1513 AddToWorklist(ChildN.getNode());
1514
1515 SDValue RV = combine(N);
1516
1517 if (!RV.getNode())
1518 continue;
1519
1520 ++NodesCombined;
1521
1522 // If we get back the same node we passed in, rather than a new node or
1523 // zero, we know that the node must have defined multiple values and
1524 // CombineTo was used. Since CombineTo takes care of the worklist
1525 // mechanics for us, we have no work to do in this case.
1526 if (RV.getNode() == N)
1527 continue;
1528
1529 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1531, __PRETTY_FUNCTION__))
1530 RV.getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1531, __PRETTY_FUNCTION__))
1531 "Node was deleted but visit returned new node!")((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1531, __PRETTY_FUNCTION__))
;
1532
1533 LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1534
1535 if (N->getNumValues() == RV.getNode()->getNumValues())
1536 DAG.ReplaceAllUsesWith(N, RV.getNode());
1537 else {
1538 assert(N->getValueType(0) == RV.getValueType() &&((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1539, __PRETTY_FUNCTION__))
1539 N->getNumValues() == 1 && "Type mismatch")((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1539, __PRETTY_FUNCTION__))
;
1540 DAG.ReplaceAllUsesWith(N, &RV);
1541 }
1542
1543 // Push the new node and any users onto the worklist
1544 AddToWorklist(RV.getNode());
1545 AddUsersToWorklist(RV.getNode());
1546
1547 // Finally, if the node is now dead, remove it from the graph. The node
1548 // may not be dead if the replacement process recursively simplified to
1549 // something else needing this node. This will also take care of adding any
1550 // operands which have lost a user to the worklist.
1551 recursivelyDeleteUnusedNodes(N);
1552 }
1553
1554 // If the root changed (e.g. it was a dead load, update the root).
1555 DAG.setRoot(Dummy.getValue());
1556 DAG.RemoveDeadNodes();
1557}
1558
1559SDValue DAGCombiner::visit(SDNode *N) {
1560 switch (N->getOpcode()) {
1561 default: break;
1562 case ISD::TokenFactor: return visitTokenFactor(N);
1563 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1564 case ISD::ADD: return visitADD(N);
1565 case ISD::SUB: return visitSUB(N);
1566 case ISD::SADDSAT:
1567 case ISD::UADDSAT: return visitADDSAT(N);
1568 case ISD::SSUBSAT:
1569 case ISD::USUBSAT: return visitSUBSAT(N);
1570 case ISD::ADDC: return visitADDC(N);
1571 case ISD::SADDO:
1572 case ISD::UADDO: return visitADDO(N);
1573 case ISD::SUBC: return visitSUBC(N);
1574 case ISD::SSUBO:
1575 case ISD::USUBO: return visitSUBO(N);
1576 case ISD::ADDE: return visitADDE(N);
1577 case ISD::ADDCARRY: return visitADDCARRY(N);
1578 case ISD::SUBE: return visitSUBE(N);
1579 case ISD::SUBCARRY: return visitSUBCARRY(N);
1580 case ISD::MUL: return visitMUL(N);
1581 case ISD::SDIV: return visitSDIV(N);
1582 case ISD::UDIV: return visitUDIV(N);
1583 case ISD::SREM:
1584 case ISD::UREM: return visitREM(N);
1585 case ISD::MULHU: return visitMULHU(N);
1586 case ISD::MULHS: return visitMULHS(N);
1587 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1588 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1589 case ISD::SMULO:
1590 case ISD::UMULO: return visitMULO(N);
1591 case ISD::SMIN:
1592 case ISD::SMAX:
1593 case ISD::UMIN:
1594 case ISD::UMAX: return visitIMINMAX(N);
1595 case ISD::AND: return visitAND(N);
1596 case ISD::OR: return visitOR(N);
1597 case ISD::XOR: return visitXOR(N);
1598 case ISD::SHL: return visitSHL(N);
1599 case ISD::SRA: return visitSRA(N);
1600 case ISD::SRL: return visitSRL(N);
1601 case ISD::ROTR:
1602 case ISD::ROTL: return visitRotate(N);
1603 case ISD::FSHL:
1604 case ISD::FSHR: return visitFunnelShift(N);
1605 case ISD::ABS: return visitABS(N);
1606 case ISD::BSWAP: return visitBSWAP(N);
1607 case ISD::BITREVERSE: return visitBITREVERSE(N);
1608 case ISD::CTLZ: return visitCTLZ(N);
1609 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1610 case ISD::CTTZ: return visitCTTZ(N);
1611 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1612 case ISD::CTPOP: return visitCTPOP(N);
1613 case ISD::SELECT: return visitSELECT(N);
1614 case ISD::VSELECT: return visitVSELECT(N);
1615 case ISD::SELECT_CC: return visitSELECT_CC(N);
1616 case ISD::SETCC: return visitSETCC(N);
1617 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1618 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1619 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1620 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1621 case ISD::AssertSext:
1622 case ISD::AssertZext: return visitAssertExt(N);
1623 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1624 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1625 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
1626 case ISD::TRUNCATE: return visitTRUNCATE(N);
1627 case ISD::BITCAST: return visitBITCAST(N);
1628 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1629 case ISD::FADD: return visitFADD(N);
1630 case ISD::FSUB: return visitFSUB(N);
1631 case ISD::FMUL: return visitFMUL(N);
1632 case ISD::FMA: return visitFMA(N);
1633 case ISD::FDIV: return visitFDIV(N);
1634 case ISD::FREM: return visitFREM(N);
1635 case ISD::FSQRT: return visitFSQRT(N);
1636 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1637 case ISD::FPOW: return visitFPOW(N);
1638 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1639 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1640 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1641 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1642 case ISD::FP_ROUND: return visitFP_ROUND(N);
1643 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1644 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1645 case ISD::FNEG: return visitFNEG(N);
1646 case ISD::FABS: return visitFABS(N);
1647 case ISD::FFLOOR: return visitFFLOOR(N);
1648 case ISD::FMINNUM: return visitFMINNUM(N);
1649 case ISD::FMAXNUM: return visitFMAXNUM(N);
1650 case ISD::FMINIMUM: return visitFMINIMUM(N);
1651 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
1652 case ISD::FCEIL: return visitFCEIL(N);
1653 case ISD::FTRUNC: return visitFTRUNC(N);
1654 case ISD::BRCOND: return visitBRCOND(N);
1655 case ISD::BR_CC: return visitBR_CC(N);
1656 case ISD::LOAD: return visitLOAD(N);
1657 case ISD::STORE: return visitSTORE(N);
1658 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1659 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1660 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1661 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1662 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1663 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1664 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1665 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1666 case ISD::MGATHER: return visitMGATHER(N);
1667 case ISD::MLOAD: return visitMLOAD(N);
1668 case ISD::MSCATTER: return visitMSCATTER(N);
1669 case ISD::MSTORE: return visitMSTORE(N);
1670 case ISD::LIFETIME_END: return visitLIFETIME_END(N);
1671 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1672 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1673 case ISD::VECREDUCE_FADD:
1674 case ISD::VECREDUCE_FMUL:
1675 case ISD::VECREDUCE_ADD:
1676 case ISD::VECREDUCE_MUL:
1677 case ISD::VECREDUCE_AND:
1678 case ISD::VECREDUCE_OR:
1679 case ISD::VECREDUCE_XOR:
1680 case ISD::VECREDUCE_SMAX:
1681 case ISD::VECREDUCE_SMIN:
1682 case ISD::VECREDUCE_UMAX:
1683 case ISD::VECREDUCE_UMIN:
1684 case ISD::VECREDUCE_FMAX:
1685 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
1686 }
1687 return SDValue();
1688}
1689
1690SDValue DAGCombiner::combine(SDNode *N) {
1691 SDValue RV = visit(N);
1692
1693 // If nothing happened, try a target-specific DAG combine.
1694 if (!RV.getNode()) {
1695 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1696, __PRETTY_FUNCTION__))
1696 "Node was deleted but visit returned NULL!")((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1696, __PRETTY_FUNCTION__))
;
1697
1698 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1699 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1700
1701 // Expose the DAG combiner to the target combiner impls.
1702 TargetLowering::DAGCombinerInfo
1703 DagCombineInfo(DAG, Level, false, this);
1704
1705 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1706 }
1707 }
1708
1709 // If nothing happened still, try promoting the operation.
1710 if (!RV.getNode()) {
1711 switch (N->getOpcode()) {
1712 default: break;
1713 case ISD::ADD:
1714 case ISD::SUB:
1715 case ISD::MUL:
1716 case ISD::AND:
1717 case ISD::OR:
1718 case ISD::XOR:
1719 RV = PromoteIntBinOp(SDValue(N, 0));
1720 break;
1721 case ISD::SHL:
1722 case ISD::SRA:
1723 case ISD::SRL:
1724 RV = PromoteIntShiftOp(SDValue(N, 0));
1725 break;
1726 case ISD::SIGN_EXTEND:
1727 case ISD::ZERO_EXTEND:
1728 case ISD::ANY_EXTEND:
1729 RV = PromoteExtend(SDValue(N, 0));
1730 break;
1731 case ISD::LOAD:
1732 if (PromoteLoad(SDValue(N, 0)))
1733 RV = SDValue(N, 0);
1734 break;
1735 }
1736 }
1737
1738 // If N is a commutative binary node, try to eliminate it if the commuted
1739 // version is already present in the DAG.
1740 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1741 N->getNumValues() == 1) {
1742 SDValue N0 = N->getOperand(0);
1743 SDValue N1 = N->getOperand(1);
1744
1745 // Constant operands are canonicalized to RHS.
1746 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1747 SDValue Ops[] = {N1, N0};
1748 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1749 N->getFlags());
1750 if (CSENode)
1751 return SDValue(CSENode, 0);
1752 }
1753 }
1754
1755 return RV;
1756}
1757
1758/// Given a node, return its input chain if it has one, otherwise return a null
1759/// sd operand.
1760static SDValue getInputChainForNode(SDNode *N) {
1761 if (unsigned NumOps = N->getNumOperands()) {
1762 if (N->getOperand(0).getValueType() == MVT::Other)
1763 return N->getOperand(0);
1764 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1765 return N->getOperand(NumOps-1);
1766 for (unsigned i = 1; i < NumOps-1; ++i)
1767 if (N->getOperand(i).getValueType() == MVT::Other)
1768 return N->getOperand(i);
1769 }
1770 return SDValue();
1771}
1772
1773SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1774 // If N has two operands, where one has an input chain equal to the other,
1775 // the 'other' chain is redundant.
1776 if (N->getNumOperands() == 2) {
1777 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1778 return N->getOperand(0);
1779 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1780 return N->getOperand(1);
1781 }
1782
1783 // Don't simplify token factors if optnone.
1784 if (OptLevel == CodeGenOpt::None)
1785 return SDValue();
1786
1787 // If the sole user is a token factor, we should make sure we have a
1788 // chance to merge them together. This prevents TF chains from inhibiting
1789 // optimizations.
1790 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1791 AddToWorklist(*(N->use_begin()));
1792
1793 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1794 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1795 SmallPtrSet<SDNode*, 16> SeenOps;
1796 bool Changed = false; // If we should replace this token factor.
1797
1798 // Start out with this token factor.
1799 TFs.push_back(N);
1800
1801 // Iterate through token factors. The TFs grows when new token factors are
1802 // encountered.
1803 for (unsigned i = 0; i < TFs.size(); ++i) {
1804 SDNode *TF = TFs[i];
1805
1806 // Check each of the operands.
1807 for (const SDValue &Op : TF->op_values()) {
1808 switch (Op.getOpcode()) {
1809 case ISD::EntryToken:
1810 // Entry tokens don't need to be added to the list. They are
1811 // redundant.
1812 Changed = true;
1813 break;
1814
1815 case ISD::TokenFactor:
1816 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1817 // Queue up for processing.
1818 TFs.push_back(Op.getNode());
1819 // Clean up in case the token factor is removed.
1820 AddToWorklist(Op.getNode());
1821 Changed = true;
1822 break;
1823 }
1824 LLVM_FALLTHROUGH[[clang::fallthrough]];
1825
1826 default:
1827 // Only add if it isn't already in the list.
1828 if (SeenOps.insert(Op.getNode()).second)
1829 Ops.push_back(Op);
1830 else
1831 Changed = true;
1832 break;
1833 }
1834 }
1835 }
1836
1837 // Remove Nodes that are chained to another node in the list. Do so
1838 // by walking up chains breath-first stopping when we've seen
1839 // another operand. In general we must climb to the EntryNode, but we can exit
1840 // early if we find all remaining work is associated with just one operand as
1841 // no further pruning is possible.
1842
1843 // List of nodes to search through and original Ops from which they originate.
1844 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1845 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1846 SmallPtrSet<SDNode *, 16> SeenChains;
1847 bool DidPruneOps = false;
1848
1849 unsigned NumLeftToConsider = 0;
1850 for (const SDValue &Op : Ops) {
1851 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1852 OpWorkCount.push_back(1);
1853 }
1854
1855 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1856 // If this is an Op, we can remove the op from the list. Remark any
1857 // search associated with it as from the current OpNumber.
1858 if (SeenOps.count(Op) != 0) {
1859 Changed = true;
1860 DidPruneOps = true;
1861 unsigned OrigOpNumber = 0;
1862 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1863 OrigOpNumber++;
1864 assert((OrigOpNumber != Ops.size()) &&(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1865, __PRETTY_FUNCTION__))
1865 "expected to find TokenFactor Operand")(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1865, __PRETTY_FUNCTION__))
;
1866 // Re-mark worklist from OrigOpNumber to OpNumber
1867 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1868 if (Worklist[i].second == OrigOpNumber) {
1869 Worklist[i].second = OpNumber;
1870 }
1871 }
1872 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1873 OpWorkCount[OrigOpNumber] = 0;
1874 NumLeftToConsider--;
1875 }
1876 // Add if it's a new chain
1877 if (SeenChains.insert(Op).second) {
1878 OpWorkCount[OpNumber]++;
1879 Worklist.push_back(std::make_pair(Op, OpNumber));
1880 }
1881 };
1882
1883 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1884 // We need at least be consider at least 2 Ops to prune.
1885 if (NumLeftToConsider <= 1)
1886 break;
1887 auto CurNode = Worklist[i].first;
1888 auto CurOpNumber = Worklist[i].second;
1889 assert((OpWorkCount[CurOpNumber] > 0) &&(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1890, __PRETTY_FUNCTION__))
1890 "Node should not appear in worklist")(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1890, __PRETTY_FUNCTION__))
;
1891 switch (CurNode->getOpcode()) {
1892 case ISD::EntryToken:
1893 // Hitting EntryToken is the only way for the search to terminate without
1894 // hitting
1895 // another operand's search. Prevent us from marking this operand
1896 // considered.
1897 NumLeftToConsider++;
1898 break;
1899 case ISD::TokenFactor:
1900 for (const SDValue &Op : CurNode->op_values())
1901 AddToWorklist(i, Op.getNode(), CurOpNumber);
1902 break;
1903 case ISD::LIFETIME_START:
1904 case ISD::LIFETIME_END:
1905 case ISD::CopyFromReg:
1906 case ISD::CopyToReg:
1907 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1908 break;
1909 default:
1910 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1911 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1912 break;
1913 }
1914 OpWorkCount[CurOpNumber]--;
1915 if (OpWorkCount[CurOpNumber] == 0)
1916 NumLeftToConsider--;
1917 }
1918
1919 // If we've changed things around then replace token factor.
1920 if (Changed) {
1921 SDValue Result;
1922 if (Ops.empty()) {
1923 // The entry token is the only possible outcome.
1924 Result = DAG.getEntryNode();
1925 } else {
1926 if (DidPruneOps) {
1927 SmallVector<SDValue, 8> PrunedOps;
1928 //
1929 for (const SDValue &Op : Ops) {
1930 if (SeenChains.count(Op.getNode()) == 0)
1931 PrunedOps.push_back(Op);
1932 }
1933 Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
1934 } else {
1935 Result = DAG.getTokenFactor(SDLoc(N), Ops);
1936 }
1937 }
1938 return Result;
1939 }
1940 return SDValue();
1941}
1942
1943/// MERGE_VALUES can always be eliminated.
1944SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1945 WorklistRemover DeadNodes(*this);
1946 // Replacing results may cause a different MERGE_VALUES to suddenly
1947 // be CSE'd with N, and carry its uses with it. Iterate until no
1948 // uses remain, to ensure that the node can be safely deleted.
1949 // First add the users of this node to the work list so that they
1950 // can be tried again once they have new operands.
1951 AddUsersToWorklist(N);
1952 do {
1953 // Do as a single replacement to avoid rewalking use lists.
1954 SmallVector<SDValue, 8> Ops;
1955 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1956 Ops.push_back(N->getOperand(i));
1957 DAG.ReplaceAllUsesWith(N, Ops.data());
1958 } while (!N->use_empty());
1959 deleteAndRecombine(N);
1960 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1961}
1962
1963/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
1964/// ConstantSDNode pointer else nullptr.
1965static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1966 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1967 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1968}
1969
1970SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
1971 assert(TLI.isBinOp(BO->getOpcode()) && "Unexpected binary operator")((TLI.isBinOp(BO->getOpcode()) && "Unexpected binary operator"
) ? static_cast<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1971, __PRETTY_FUNCTION__))
;
1972
1973 // Don't do this unless the old select is going away. We want to eliminate the
1974 // binary operator, not replace a binop with a select.
1975 // TODO: Handle ISD::SELECT_CC.
1976 unsigned SelOpNo = 0;
1977 SDValue Sel = BO->getOperand(0);
1978 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
1979 SelOpNo = 1;
1980 Sel = BO->getOperand(1);
1981 }
1982
1983 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
1984 return SDValue();
1985
1986 SDValue CT = Sel.getOperand(1);
1987 if (!isConstantOrConstantVector(CT, true) &&
1988 !isConstantFPBuildVectorOrConstantFP(CT))
1989 return SDValue();
1990
1991 SDValue CF = Sel.getOperand(2);
1992 if (!isConstantOrConstantVector(CF, true) &&
1993 !isConstantFPBuildVectorOrConstantFP(CF))
1994 return SDValue();
1995
1996 // Bail out if any constants are opaque because we can't constant fold those.
1997 // The exception is "and" and "or" with either 0 or -1 in which case we can
1998 // propagate non constant operands into select. I.e.:
1999 // and (select Cond, 0, -1), X --> select Cond, 0, X
2000 // or X, (select Cond, -1, 0) --> select Cond, -1, X
2001 auto BinOpcode = BO->getOpcode();
2002 bool CanFoldNonConst =
2003 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2004 (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
2005 (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));
2006
2007 SDValue CBO = BO->getOperand(SelOpNo ^ 1);
2008 if (!CanFoldNonConst &&
2009 !isConstantOrConstantVector(CBO, true) &&
2010 !isConstantFPBuildVectorOrConstantFP(CBO))
2011 return SDValue();
2012
2013 EVT VT = Sel.getValueType();
2014
2015 // In case of shift value and shift amount may have different VT. For instance
2016 // on x86 shift amount is i8 regardles of LHS type. Bail out if we have
2017 // swapped operands and value types do not match. NB: x86 is fine if operands
2018 // are not swapped with shift amount VT being not bigger than shifted value.
2019 // TODO: that is possible to check for a shift operation, correct VTs and
2020 // still perform optimization on x86 if needed.
2021 if (SelOpNo && VT != CBO.getValueType())
2022 return SDValue();
2023
2024 // We have a select-of-constants followed by a binary operator with a
2025 // constant. Eliminate the binop by pulling the constant math into the select.
2026 // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
2027 SDLoc DL(Sel);
2028 SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
2029 : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
2030 if (!CanFoldNonConst && !NewCT.isUndef() &&
2031 !isConstantOrConstantVector(NewCT, true) &&
2032 !isConstantFPBuildVectorOrConstantFP(NewCT))
2033 return SDValue();
2034
2035 SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
2036 : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
2037 if (!CanFoldNonConst && !NewCF.isUndef() &&
2038 !isConstantOrConstantVector(NewCF, true) &&
2039 !isConstantFPBuildVectorOrConstantFP(NewCF))
2040 return SDValue();
2041
2042 return DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
2043}
2044
2045static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
2046 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2047, __PRETTY_FUNCTION__))
2047 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2047, __PRETTY_FUNCTION__))
;
2048
2049 // Match a constant operand and a zext operand for the math instruction:
2050 // add Z, C
2051 // sub C, Z
2052 bool IsAdd = N->getOpcode() == ISD::ADD;
2053 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2054 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2055 auto *CN = dyn_cast<ConstantSDNode>(C);
2056 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2057 return SDValue();
2058
2059 // Match the zext operand as a setcc of a boolean.
2060 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2061 Z.getOperand(0).getValueType() != MVT::i1)
2062 return SDValue();
2063
2064 // Match the compare as: setcc (X & 1), 0, eq.
2065 SDValue SetCC = Z.getOperand(0);
2066 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2067 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2068 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2069 !isOneConstant(SetCC.getOperand(0).getOperand(1)))
2070 return SDValue();
2071
2072 // We are adding/subtracting a constant and an inverted low bit. Turn that
2073 // into a subtract/add of the low bit with incremented/decremented constant:
2074 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2075 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
2076 EVT VT = C.getValueType();
2077 SDLoc DL(N);
2078 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
2079 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2080 DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
2081 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2082}
2083
2084/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2085/// a shift and add with a different constant.
2086static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
2087 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2088, __PRETTY_FUNCTION__))
2088 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2088, __PRETTY_FUNCTION__))
;
2089
2090 // We need a constant operand for the add/sub, and the other operand is a
2091 // logical shift right: add (srl), C or sub C, (srl).
2092 bool IsAdd = N->getOpcode() == ISD::ADD;
2093 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2094 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2095 ConstantSDNode *C = isConstOrConstSplat(ConstantOp);
2096 if (!C || ShiftOp.getOpcode() != ISD::SRL)
2097 return SDValue();
2098
2099 // The shift must be of a 'not' value.
2100 SDValue Not = ShiftOp.getOperand(0);
2101 if (!Not.hasOneUse() || !isBitwiseNot(Not))
2102 return SDValue();
2103
2104 // The shift must be moving the sign bit to the least-significant-bit.
2105 EVT VT = ShiftOp.getValueType();
2106 SDValue ShAmt = ShiftOp.getOperand(1);
2107 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2108 if (!ShAmtC || ShAmtC->getZExtValue() != VT.getScalarSizeInBits() - 1)
2109 return SDValue();
2110
2111 // Eliminate the 'not' by adjusting the shift and add/sub constant:
2112 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2113 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2114 SDLoc DL(N);
2115 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2116 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
2117 APInt NewC = IsAdd ? C->getAPIntValue() + 1 : C->getAPIntValue() - 1;
2118 return DAG.getNode(ISD::ADD, DL, VT, NewShift, DAG.getConstant(NewC, DL, VT));
2119}
2120
2121/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2122/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2123/// are no common bits set in the operands).
2124SDValue DAGCombiner::visitADDLike(SDNode *N) {
2125 SDValue N0 = N->getOperand(0);
2126 SDValue N1 = N->getOperand(1);
2127 EVT VT = N0.getValueType();
2128 SDLoc DL(N);
2129
2130 // fold vector ops
2131 if (VT.isVector()) {
2132 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2133 return FoldedVOp;
2134
2135 // fold (add x, 0) -> x, vector edition
2136 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2137 return N0;
2138 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2139 return N1;
2140 }
2141
2142 // fold (add x, undef) -> undef
2143 if (N0.isUndef())
2144 return N0;
2145
2146 if (N1.isUndef())
2147 return N1;
2148
2149 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2150 // canonicalize constant to RHS
2151 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2152 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2153 // fold (add c1, c2) -> c1+c2
2154 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, N0.getNode(),
2155 N1.getNode());
2156 }
2157
2158 // fold (add x, 0) -> x
2159 if (isNullConstant(N1))
2160 return N0;
2161
2162 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
2163 // fold ((c1-A)+c2) -> (c1+c2)-A
2164 if (N0.getOpcode() == ISD::SUB &&
2165 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
2166 // FIXME: Adding 2 constants should be handled by FoldConstantArithmetic.
2167 return DAG.getNode(ISD::SUB, DL, VT,
2168 DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
2169 N0.getOperand(1));
2170 }
2171
2172 // add (sext i1 X), 1 -> zext (not i1 X)
2173 // We don't transform this pattern:
2174 // add (zext i1 X), -1 -> sext (not i1 X)
2175 // because most (?) targets generate better code for the zext form.
2176 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2177 isOneOrOneSplat(N1)) {
2178 SDValue X = N0.getOperand(0);
2179 if ((!LegalOperations ||
2180 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2181 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2182 X.getScalarValueSizeInBits() == 1) {
2183 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
2184 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2185 }
2186 }
2187
2188 // Undo the add -> or combine to merge constant offsets from a frame index.
2189 if (N0.getOpcode() == ISD::OR &&
2190 isa<FrameIndexSDNode>(N0.getOperand(0)) &&
2191 isa<ConstantSDNode>(N0.getOperand(1)) &&
2192 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2193 SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1));
2194 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
2195 }
2196 }
2197
2198 if (SDValue NewSel = foldBinOpIntoSelect(N))
2199 return NewSel;
2200
2201 // reassociate add
2202 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2203 return RADD;
2204
2205 // fold ((0-A) + B) -> B-A
2206 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2207 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2208
2209 // fold (A + (0-B)) -> A-B
2210 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2211 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2212
2213 // fold (A+(B-A)) -> B
2214 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2215 return N1.getOperand(0);
2216
2217 // fold ((B-A)+A) -> B
2218 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2219 return N0.getOperand(0);
2220
2221 // fold ((A-B)+(C-A)) -> (C-B)
2222 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2223 N0.getOperand(0) == N1.getOperand(1))
2224 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2225 N0.getOperand(1));
2226
2227 // fold ((A-B)+(B-C)) -> (A-C)
2228 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2229 N0.getOperand(1) == N1.getOperand(0))
2230 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2231 N1.getOperand(1));
2232
2233 // fold (A+(B-(A+C))) to (B-C)
2234 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2235 N0 == N1.getOperand(1).getOperand(0))
2236 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2237 N1.getOperand(1).getOperand(1));
2238
2239 // fold (A+(B-(C+A))) to (B-C)
2240 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2241 N0 == N1.getOperand(1).getOperand(1))
2242 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2243 N1.getOperand(1).getOperand(0));
2244
2245 // fold (A+((B-A)+or-C)) to (B+or-C)
2246 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2247 N1.getOperand(0).getOpcode() == ISD::SUB &&
2248 N0 == N1.getOperand(0).getOperand(1))
2249 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2250 N1.getOperand(1));
2251
2252 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2253 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2254 SDValue N00 = N0.getOperand(0);
2255 SDValue N01 = N0.getOperand(1);
2256 SDValue N10 = N1.getOperand(0);
2257 SDValue N11 = N1.getOperand(1);
2258
2259 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2260 return DAG.getNode(ISD::SUB, DL, VT,
2261 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2262 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2263 }
2264
2265 // fold (add (umax X, C), -C) --> (usubsat X, C)
2266 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2267 auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
2268 return (!Max && !Op) ||
2269 (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
2270 };
2271 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2272 /*AllowUndefs*/ true))
2273 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2274 N0.getOperand(1));
2275 }
2276
2277 if (SimplifyDemandedBits(SDValue(N, 0)))
2278 return SDValue(N, 0);
2279
2280 if (isOneOrOneSplat(N1)) {
2281 // fold (add (xor a, -1), 1) -> (sub 0, a)
2282 if (isBitwiseNot(N0))
2283 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2284 N0.getOperand(0));
2285
2286 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2287 if (N0.getOpcode() == ISD::ADD ||
2288 N0.getOpcode() == ISD::UADDO ||
2289 N0.getOpcode() == ISD::SADDO) {
2290 SDValue A, Xor;
2291
2292 if (isBitwiseNot(N0.getOperand(0))) {
2293 A = N0.getOperand(1);
2294 Xor = N0.getOperand(0);
2295 } else if (isBitwiseNot(N0.getOperand(1))) {
2296 A = N0.getOperand(0);
2297 Xor = N0.getOperand(1);
2298 }
2299
2300 if (Xor)
2301 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2302 }
2303 }
2304
2305 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2306 return Combined;
2307
2308 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2309 return Combined;
2310
2311 return SDValue();
2312}
2313
2314SDValue DAGCombiner::visitADD(SDNode *N) {
2315 SDValue N0 = N->getOperand(0);
2316 SDValue N1 = N->getOperand(1);
2317 EVT VT = N0.getValueType();
2318 SDLoc DL(N);
2319
2320 if (SDValue Combined = visitADDLike(N))
2321 return Combined;
2322
2323 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2324 return V;
2325
2326 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2327 return V;
2328
2329 // fold (a+b) -> (a|b) iff a and b share no bits.
2330 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2331 DAG.haveNoCommonBitsSet(N0, N1))
2332 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2333
2334 return SDValue();
2335}
2336
2337SDValue DAGCombiner::visitADDSAT(SDNode *N) {
2338 unsigned Opcode = N->getOpcode();
2339 SDValue N0 = N->getOperand(0);
2340 SDValue N1 = N->getOperand(1);
2341 EVT VT = N0.getValueType();
2342 SDLoc DL(N);
2343
2344 // fold vector ops
2345 if (VT.isVector()) {
2346 // TODO SimplifyVBinOp
2347
2348 // fold (add_sat x, 0) -> x, vector edition
2349 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2350 return N0;
2351 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2352 return N1;
2353 }
2354
2355 // fold (add_sat x, undef) -> -1
2356 if (N0.isUndef() || N1.isUndef())
2357 return DAG.getAllOnesConstant(DL, VT);
2358
2359 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2360 // canonicalize constant to RHS
2361 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2362 return DAG.getNode(Opcode, DL, VT, N1, N0);
2363 // fold (add_sat c1, c2) -> c3
2364 return DAG.FoldConstantArithmetic(Opcode, DL, VT, N0.getNode(),
2365 N1.getNode());
2366 }
2367
2368 // fold (add_sat x, 0) -> x
2369 if (isNullConstant(N1))
2370 return N0;
2371
2372 // If it cannot overflow, transform into an add.
2373 if (Opcode == ISD::UADDSAT)
2374 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2375 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
2376
2377 return SDValue();
2378}
2379
2380static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2381 bool Masked = false;
2382
2383 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2384 while (true) {
2385 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2386 V = V.getOperand(0);
2387 continue;
2388 }
2389
2390 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2391 Masked = true;
2392 V = V.getOperand(0);
2393 continue;
2394 }
2395
2396 break;
2397 }
2398
2399 // If this is not a carry, return.
2400 if (V.getResNo() != 1)
2401 return SDValue();
2402
2403 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2404 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2405 return SDValue();
2406
2407 EVT VT = V.getNode()->getValueType(0);
2408 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2409 return SDValue();
2410
2411 // If the result is masked, then no matter what kind of bool it is we can
2412 // return. If it isn't, then we need to make sure the bool type is either 0 or
2413 // 1 and not other values.
2414 if (Masked ||
2415 TLI.getBooleanContents(V.getValueType()) ==
2416 TargetLoweringBase::ZeroOrOneBooleanContent)
2417 return V;
2418
2419 return SDValue();
2420}
2421
2422/// Given the operands of an add/sub operation, see if the 2nd operand is a
2423/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2424/// the opcode and bypass the mask operation.
2425static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
2426 SelectionDAG &DAG, const SDLoc &DL) {
2427 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2428 return SDValue();
2429
2430 EVT VT = N0.getValueType();
2431 if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
2432 return SDValue();
2433
2434 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2435 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
2436 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2437}
2438
2439/// Helper for doing combines based on N0 and N1 being added to each other.
2440SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
2441 SDNode *LocReference) {
2442 EVT VT = N0.getValueType();
2443 SDLoc DL(LocReference);
2444
2445 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2446 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2447 isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
2448 return DAG.getNode(ISD::SUB, DL, VT, N0,
2449 DAG.getNode(ISD::SHL, DL, VT,
2450 N1.getOperand(0).getOperand(1),
2451 N1.getOperand(1)));
2452
2453 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
2454 return V;
2455
2456 // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
2457 // rather than 'add 0/-1' (the zext should get folded).
2458 // add (sext i1 Y), X --> sub X, (zext i1 Y)
2459 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2460 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
2461 TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
2462 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2463 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2464 }
2465
2466 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2467 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2468 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2469 if (TN->getVT() == MVT::i1) {
2470 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2471 DAG.getConstant(1, DL, VT));
2472 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2473 }
2474 }
2475
2476 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2477 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2478 N1.getResNo() == 0)
2479 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2480 N0, N1.getOperand(0), N1.getOperand(2));
2481
2482 // (add X, Carry) -> (addcarry X, 0, Carry)
2483 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2484 if (SDValue Carry = getAsCarry(TLI, N1))
2485 return DAG.getNode(ISD::ADDCARRY, DL,
2486 DAG.getVTList(VT, Carry.getValueType()), N0,
2487 DAG.getConstant(0, DL, VT), Carry);
2488
2489 return SDValue();
2490}
2491
2492SDValue DAGCombiner::visitADDC(SDNode *N) {
2493 SDValue N0 = N->getOperand(0);
2494 SDValue N1 = N->getOperand(1);
2495 EVT VT = N0.getValueType();
2496 SDLoc DL(N);
2497
2498 // If the flag result is dead, turn this into an ADD.
2499 if (!N->hasAnyUseOfValue(1))
2500 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2501 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2502
2503 // canonicalize constant to RHS.
2504 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2505 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2506 if (N0C && !N1C)
2507 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2508
2509 // fold (addc x, 0) -> x + no carry out
2510 if (isNullConstant(N1))
2511 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2512 DL, MVT::Glue));
2513
2514 // If it cannot overflow, transform into an add.
2515 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2516 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2517 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2518
2519 return SDValue();
2520}
2521
2522static SDValue flipBoolean(SDValue V, const SDLoc &DL,
2523 SelectionDAG &DAG, const TargetLowering &TLI) {
2524 EVT VT = V.getValueType();
2525
2526 SDValue Cst;
2527 switch (TLI.getBooleanContents(VT)) {
2528 case TargetLowering::ZeroOrOneBooleanContent:
2529 case TargetLowering::UndefinedBooleanContent:
2530 Cst = DAG.getConstant(1, DL, VT);
2531 break;
2532 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2533 Cst = DAG.getConstant(-1, DL, VT);
2534 break;
2535 }
2536
2537 return DAG.getNode(ISD::XOR, DL, VT, V, Cst);
2538}
2539
2540static SDValue extractBooleanFlip(SDValue V, const TargetLowering &TLI) {
2541 if (V.getOpcode() != ISD::XOR)
2542 return SDValue();
2543
2544 ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
2545 if (!Const)
2546 return SDValue();
2547
2548 EVT VT = V.getValueType();
2549
2550 bool IsFlip = false;
2551 switch(TLI.getBooleanContents(VT)) {
2552 case TargetLowering::ZeroOrOneBooleanContent:
2553 IsFlip = Const->isOne();
2554 break;
2555 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2556 IsFlip = Const->isAllOnesValue();
2557 break;
2558 case TargetLowering::UndefinedBooleanContent:
2559 IsFlip = (Const->getAPIntValue() & 0x01) == 1;
2560 break;
2561 }
2562
2563 if (IsFlip)
2564 return V.getOperand(0);
2565 return SDValue();
2566}
2567
2568SDValue DAGCombiner::visitADDO(SDNode *N) {
2569 SDValue N0 = N->getOperand(0);
2570 SDValue N1 = N->getOperand(1);
2571 EVT VT = N0.getValueType();
2572 bool IsSigned = (ISD::SADDO == N->getOpcode());
2573
2574 EVT CarryVT = N->getValueType(1);
2575 SDLoc DL(N);
2576
2577 // If the flag result is dead, turn this into an ADD.
2578 if (!N->hasAnyUseOfValue(1))
2579 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2580 DAG.getUNDEF(CarryVT));
2581
2582 // canonicalize constant to RHS.
2583 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2584 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2585 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2586
2587 // fold (addo x, 0) -> x + no carry out
2588 if (isNullOrNullSplat(N1))
2589 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2590
2591 if (!IsSigned) {
2592 // If it cannot overflow, transform into an add.
2593 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2594 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2595 DAG.getConstant(0, DL, CarryVT));
2596
2597 // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
2598 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
2599 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2600 DAG.getConstant(0, DL, VT), N0.getOperand(0));
2601 return CombineTo(N, Sub,
2602 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2603 }
2604
2605 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2606 return Combined;
2607
2608 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2609 return Combined;
2610 }
2611
2612 return SDValue();
2613}
2614
2615SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2616 EVT VT = N0.getValueType();
2617 if (VT.isVector())
2618 return SDValue();
2619
2620 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2621 // If Y + 1 cannot overflow.
2622 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2623 SDValue Y = N1.getOperand(0);
2624 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2625 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2626 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2627 N1.getOperand(2));
2628 }
2629
2630 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2631 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2632 if (SDValue Carry = getAsCarry(TLI, N1))
2633 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2634 DAG.getConstant(0, SDLoc(N), VT), Carry);
2635
2636 return SDValue();
2637}
2638
2639SDValue DAGCombiner::visitADDE(SDNode *N) {
2640 SDValue N0 = N->getOperand(0);
2641 SDValue N1 = N->getOperand(1);
2642 SDValue CarryIn = N->getOperand(2);
2643
2644 // canonicalize constant to RHS
2645 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2646 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2647 if (N0C && !N1C)
2648 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2649 N1, N0, CarryIn);
2650
2651 // fold (adde x, y, false) -> (addc x, y)
2652 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2653 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2654
2655 return SDValue();
2656}
2657
2658SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2659 SDValue N0 = N->getOperand(0);
2660 SDValue N1 = N->getOperand(1);
2661 SDValue CarryIn = N->getOperand(2);
2662 SDLoc DL(N);
2663
2664 // canonicalize constant to RHS
2665 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2666 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2667 if (N0C && !N1C)
2668 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2669
2670 // fold (addcarry x, y, false) -> (uaddo x, y)
2671 if (isNullConstant(CarryIn)) {
2672 if (!LegalOperations ||
2673 TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
2674 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2675 }
2676
2677 EVT CarryVT = CarryIn.getValueType();
2678
2679 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2680 if (isNullConstant(N0) && isNullConstant(N1)) {
2681 EVT VT = N0.getValueType();
2682 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2683 AddToWorklist(CarryExt.getNode());
2684 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2685 DAG.getConstant(1, DL, VT)),
2686 DAG.getConstant(0, DL, CarryVT));
2687 }
2688
2689 // fold (addcarry (xor a, -1), 0, !b) -> (subcarry 0, a, b) and flip carry.
2690 if (isBitwiseNot(N0) && isNullConstant(N1)) {
2691 if (SDValue B = extractBooleanFlip(CarryIn, TLI)) {
2692 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(),
2693 DAG.getConstant(0, DL, N0.getValueType()),
2694 N0.getOperand(0), B);
2695 return CombineTo(N, Sub,
2696 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2697 }
2698 }
2699
2700 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2701 return Combined;
2702
2703 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2704 return Combined;
2705
2706 return SDValue();
2707}
2708
2709SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
2710 SDNode *N) {
2711 // Iff the flag result is dead:
2712 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
2713 if ((N0.getOpcode() == ISD::ADD ||
2714 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0)) &&
2715 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
2716 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
2717 N0.getOperand(0), N0.getOperand(1), CarryIn);
2718
2719 /**
2720 * When one of the addcarry argument is itself a carry, we may be facing
2721 * a diamond carry propagation. In which case we try to transform the DAG
2722 * to ensure linear carry propagation if that is possible.
2723 *
2724 * We are trying to get:
2725 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2726 */
2727 if (auto Y = getAsCarry(TLI, N1)) {
2728 /**
2729 * (uaddo A, B)
2730 * / \
2731 * Carry Sum
2732 * | \
2733 * | (addcarry *, 0, Z)
2734 * | /
2735 * \ Carry
2736 * | /
2737 * (addcarry X, *, *)
2738 */
2739 if (Y.getOpcode() == ISD::UADDO &&
2740 CarryIn.getResNo() == 1 &&
2741 CarryIn.getOpcode() == ISD::ADDCARRY &&
2742 isNullConstant(CarryIn.getOperand(1)) &&
2743 CarryIn.getOperand(0) == Y.getValue(0)) {
2744 auto NewY = DAG.getNode(ISD::ADDCARRY, SDLoc(N), Y->getVTList(),
2745 Y.getOperand(0), Y.getOperand(1),
2746 CarryIn.getOperand(2));
2747 AddToWorklist(NewY.getNode());
2748 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2749 DAG.getConstant(0, SDLoc(N), N0.getValueType()),
2750 NewY.getValue(1));
2751 }
2752 }
2753
2754 return SDValue();
2755}
2756
2757// Since it may not be valid to emit a fold to zero for vector initializers
2758// check if we can before folding.
2759static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
2760 SelectionDAG &DAG, bool LegalOperations) {
2761 if (!VT.isVector())
2762 return DAG.getConstant(0, DL, VT);
2763 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
2764 return DAG.getConstant(0, DL, VT);
2765 return SDValue();
2766}
2767
2768SDValue DAGCombiner::visitSUB(SDNode *N) {
2769 SDValue N0 = N->getOperand(0);
2770 SDValue N1 = N->getOperand(1);
2771 EVT VT = N0.getValueType();
2772 SDLoc DL(N);
2773
2774 // fold vector ops
2775 if (VT.isVector()) {
2776 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2777 return FoldedVOp;
2778
2779 // fold (sub x, 0) -> x, vector edition
2780 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2781 return N0;
2782 }
2783
2784 // fold (sub x, x) -> 0
2785 // FIXME: Refactor this and xor and other similar operations together.
2786 if (N0 == N1)
2787 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
2788 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2789 DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
2790 // fold (sub c1, c2) -> c1-c2
2791 return DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2792 N1.getNode());
2793 }
2794
2795 if (SDValue NewSel = foldBinOpIntoSelect(N))
2796 return NewSel;
2797
2798 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
2799
2800 // fold (sub x, c) -> (add x, -c)
2801 if (N1C) {
2802 return DAG.getNode(ISD::ADD, DL, VT, N0,
2803 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
2804 }
2805
2806 if (isNullOrNullSplat(N0)) {
2807 unsigned BitWidth = VT.getScalarSizeInBits();
2808 // Right-shifting everything out but the sign bit followed by negation is
2809 // the same as flipping arithmetic/logical shift type without the negation:
2810 // -(X >>u 31) -> (X >>s 31)
2811 // -(X >>s 31) -> (X >>u 31)
2812 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2813 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
2814 if (ShiftAmt && ShiftAmt->getZExtValue() == BitWidth - 1) {
2815 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
2816 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
2817 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
2818 }
2819 }
2820
2821 // 0 - X --> 0 if the sub is NUW.
2822 if (N->getFlags().hasNoUnsignedWrap())
2823 return N0;
2824
2825 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
2826 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
2827 // N1 must be 0 because negating the minimum signed value is undefined.
2828 if (N->getFlags().hasNoSignedWrap())
2829 return N0;
2830
2831 // 0 - X --> X if X is 0 or the minimum signed value.
2832 return N1;
2833 }
2834 }
2835
2836 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
2837 if (isAllOnesOrAllOnesSplat(N0))
2838 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
2839
2840 // fold (A - (0-B)) -> A+B
2841 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2842 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
2843
2844 // fold A-(A-B) -> B
2845 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
2846 return N1.getOperand(1);
2847
2848 // fold (A+B)-A -> B
2849 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
2850 return N0.getOperand(1);
2851
2852 // fold (A+B)-B -> A
2853 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
2854 return N0.getOperand(0);
2855
2856 // fold C2-(A+C1) -> (C2-C1)-A
2857 if (N1.getOpcode() == ISD::ADD) {
2858 SDValue N11 = N1.getOperand(1);
2859 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
2860 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
2861 SDValue NewC = DAG.getNode(ISD::SUB, DL, VT, N0, N11);
2862 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
2863 }
2864 }
2865
2866 // fold ((A+(B+or-C))-B) -> A+or-C
2867 if (N0.getOpcode() == ISD::ADD &&
2868 (N0.getOperand(1).getOpcode() == ISD::SUB ||
2869 N0.getOperand(1).getOpcode() == ISD::ADD) &&
2870 N0.getOperand(1).getOperand(0) == N1)
2871 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
2872 N0.getOperand(1).getOperand(1));
2873
2874 // fold ((A+(C+B))-B) -> A+C
2875 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
2876 N0.getOperand(1).getOperand(1) == N1)
2877 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
2878 N0.getOperand(1).getOperand(0));
2879
2880 // fold ((A-(B-C))-C) -> A-B
2881 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
2882 N0.getOperand(1).getOperand(1) == N1)
2883 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2884 N0.getOperand(1).getOperand(0));
2885
2886 // fold (A-(B-C)) -> A+(C-B)
2887 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
2888 return DAG.getNode(ISD::ADD, DL, VT, N0,
2889 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
2890 N1.getOperand(0)));
2891
2892 // fold (X - (-Y * Z)) -> (X + (Y * Z))
2893 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
2894 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
2895 isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
2896 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
2897 N1.getOperand(0).getOperand(1),
2898 N1.getOperand(1));
2899 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
2900 }
2901 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
2902 isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
2903 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
2904 N1.getOperand(0),
2905 N1.getOperand(1).getOperand(1));
2906 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
2907 }
2908 }
2909
2910 // If either operand of a sub is undef, the result is undef
2911 if (N0.isUndef())
2912 return N0;
2913 if (N1.isUndef())
2914 return N1;
2915
2916 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2917 return V;
2918
2919 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2920 return V;
2921
2922 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
2923 return V;
2924
2925 // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
2926 // rather than 'sub 0/1' (the sext should get folded).
2927 // sub X, (zext i1 Y) --> add X, (sext i1 Y)
2928 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
2929 N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
2930 TLI.getBooleanContents(VT) ==
2931 TargetLowering::ZeroOrNegativeOneBooleanContent) {
2932 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
2933 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
2934 }
2935
2936 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
2937 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
2938 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
2939 SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
2940 SDValue S0 = N1.getOperand(0);
2941 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
2942 unsigned OpSizeInBits = VT.getScalarSizeInBits();
2943 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
2944 if (C->getAPIntValue() == (OpSizeInBits - 1))
2945 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
2946 }
2947 }
2948 }
2949
2950 // If the relocation model supports it, consider symbol offsets.
2951 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
2952 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
2953 // fold (sub Sym, c) -> Sym-c
2954 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
2955 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
2956 GA->getOffset() -
2957 (uint64_t)N1C->getSExtValue());
2958 // fold (sub Sym+c1, Sym+c2) -> c1-c2
2959 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
2960 if (GA->getGlobal() == GB->getGlobal())
2961 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
2962 DL, VT);
2963 }
2964
2965 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
2966 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2967 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2968 if (TN->getVT() == MVT::i1) {
2969 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2970 DAG.getConstant(1, DL, VT));
2971 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
2972 }
2973 }
2974
2975 // Prefer an add for more folding potential and possibly better codegen:
2976 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
2977 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
2978 SDValue ShAmt = N1.getOperand(1);
2979 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2980 if (ShAmtC && ShAmtC->getZExtValue() == N1.getScalarValueSizeInBits() - 1) {
2981 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
2982 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
2983 }
2984 }
2985
2986 return SDValue();
2987}
2988
2989SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
2990 SDValue N0 = N->getOperand(0);
2991 SDValue N1 = N->getOperand(1);
2992 EVT VT = N0.getValueType();
2993 SDLoc DL(N);
2994
2995 // fold vector ops
2996 if (VT.isVector()) {
2997 // TODO SimplifyVBinOp
2998
2999 // fold (sub_sat x, 0) -> x, vector edition
3000 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3001 return N0;
3002 }
3003
3004 // fold (sub_sat x, undef) -> 0
3005 if (N0.isUndef() || N1.isUndef())
3006 return DAG.getConstant(0, DL, VT);
3007
3008 // fold (sub_sat x, x) -> 0
3009 if (N0 == N1)
3010 return DAG.getConstant(0, DL, VT);
3011
3012 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3013 DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
3014 // fold (sub_sat c1, c2) -> c3
3015 return DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, N0.getNode(),
3016 N1.getNode());
3017 }
3018
3019 // fold (sub_sat x, 0) -> x
3020 if (isNullConstant(N1))
3021 return N0;
3022
3023 return SDValue();
3024}
3025
3026SDValue DAGCombiner::visitSUBC(SDNode *N) {
3027 SDValue N0 = N->getOperand(0);
3028 SDValue N1 = N->getOperand(1);
3029 EVT VT = N0.getValueType();
3030 SDLoc DL(N);
3031
3032 // If the flag result is dead, turn this into an SUB.
3033 if (!N->hasAnyUseOfValue(1))
3034 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3035 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3036
3037 // fold (subc x, x) -> 0 + no borrow
3038 if (N0 == N1)
3039 return CombineTo(N, DAG.getConstant(0, DL, VT),
3040 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3041
3042 // fold (subc x, 0) -> x + no borrow
3043 if (isNullConstant(N1))
3044 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3045
3046 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3047 if (isAllOnesConstant(N0))
3048 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3049 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3050
3051 return SDValue();
3052}
3053
3054SDValue DAGCombiner::visitSUBO(SDNode *N) {
3055 SDValue N0 = N->getOperand(0);
3056 SDValue N1 = N->getOperand(1);
3057 EVT VT = N0.getValueType();
3058 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3059
3060 EVT CarryVT = N->getValueType(1);
3061 SDLoc DL(N);
3062
3063 // If the flag result is dead, turn this into an SUB.
3064 if (!N->hasAnyUseOfValue(1))
3065 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3066 DAG.getUNDEF(CarryVT));
3067
3068 // fold (subo x, x) -> 0 + no borrow
3069 if (N0 == N1)
3070 return CombineTo(N, DAG.getConstant(0, DL, VT),
3071 DAG.getConstant(0, DL, CarryVT));
3072
3073 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3074
3075 // fold (subox, c) -> (addo x, -c)
3076 if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
3077 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3078 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3079 }
3080
3081 // fold (subo x, 0) -> x + no borrow
3082 if (isNullOrNullSplat(N1))
3083 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3084
3085 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3086 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
3087 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3088 DAG.getConstant(0, DL, CarryVT));
3089
3090 return SDValue();
3091}
3092
3093SDValue DAGCombiner::visitSUBE(SDNode *N) {
3094 SDValue N0 = N->getOperand(0);
3095 SDValue N1 = N->getOperand(1);
3096 SDValue CarryIn = N->getOperand(2);
3097
3098 // fold (sube x, y, false) -> (subc x, y)
3099 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3100 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3101
3102 return SDValue();
3103}
3104
3105SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
3106 SDValue N0 = N->getOperand(0);
3107 SDValue N1 = N->getOperand(1);
3108 SDValue CarryIn = N->getOperand(2);
3109
3110 // fold (subcarry x, y, false) -> (usubo x, y)
3111 if (isNullConstant(CarryIn)) {
3112 if (!LegalOperations ||
3113 TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
3114 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3115 }
3116
3117 return SDValue();
3118}
3119
3120SDValue DAGCombiner::visitMUL(SDNode *N) {
3121 SDValue N0 = N->getOperand(0);
3122 SDValue N1 = N->getOperand(1);
3123 EVT VT = N0.getValueType();
3124
3125 // fold (mul x, undef) -> 0
3126 if (N0.isUndef() || N1.isUndef())
3127 return DAG.getConstant(0, SDLoc(N), VT);
3128
3129 bool N0IsConst = false;
3130 bool N1IsConst = false;
3131 bool N1IsOpaqueConst = false;
3132 bool N0IsOpaqueConst = false;
3133 APInt ConstValue0, ConstValue1;
3134 // fold vector ops
3135 if (VT.isVector()) {
3136 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3137 return FoldedVOp;
3138
3139 N0IsConst = ISD::isConstantSplatVector(N0.getNode(), ConstValue0);
3140 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
3141 assert((!N0IsConst ||(((!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3143, __PRETTY_FUNCTION__))
3142 ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3143, __PRETTY_FUNCTION__))
3143 "Splat APInt should be element width")(((!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3143, __PRETTY_FUNCTION__))
;
3144 assert((!N1IsConst ||(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3146, __PRETTY_FUNCTION__))
3145 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3146, __PRETTY_FUNCTION__))
3146 "Splat APInt should be element width")(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3146, __PRETTY_FUNCTION__))
;
3147 } else {
3148 N0IsConst = isa<ConstantSDNode>(N0);
3149 if (N0IsConst) {
3150 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
3151 N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
3152 }
3153 N1IsConst = isa<ConstantSDNode>(N1);
3154 if (N1IsConst) {
3155 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
3156 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
3157 }
3158 }
3159
3160 // fold (mul c1, c2) -> c1*c2
3161 if (N0IsConst && N1IsConst && !N0IsOpaqueConst && !N1IsOpaqueConst)
3162 return DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT,
3163 N0.getNode(), N1.getNode());
3164
3165 // canonicalize constant to RHS (vector doesn't have to splat)
3166 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3167 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3168 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3169 // fold (mul x, 0) -> 0
3170 if (N1IsConst && ConstValue1.isNullValue())
3171 return N1;
3172 // fold (mul x, 1) -> x
3173 if (N1IsConst && ConstValue1.isOneValue())
3174 return N0;
3175
3176 if (SDValue NewSel = foldBinOpIntoSelect(N))
3177 return NewSel;
3178
3179 // fold (mul x, -1) -> 0-x
3180 if (N1IsConst && ConstValue1.isAllOnesValue()) {
3181 SDLoc DL(N);
3182 return DAG.getNode(ISD::SUB, DL, VT,
3183 DAG.getConstant(0, DL, VT), N0);
3184 }
3185 // fold (mul x, (1 << c)) -> x << c
3186 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3187 DAG.isKnownToBeAPowerOfTwo(N1) &&
3188 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
3189 SDLoc DL(N);
3190 SDValue LogBase2 = BuildLogBase2(N1, DL);
3191 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3192 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3193 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3194 }
3195 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
3196 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
3197 unsigned Log2Val = (-ConstValue1).logBase2();
3198 SDLoc DL(N);
3199 // FIXME: If the input is something that is easily negated (e.g. a
3200 // single-use add), we should put the negate there.
3201 return DAG.getNode(ISD::SUB, DL, VT,
3202 DAG.getConstant(0, DL, VT),
3203 DAG.getNode(ISD::SHL, DL, VT, N0,
3204 DAG.getConstant(Log2Val, DL,
3205 getShiftAmountTy(N0.getValueType()))));
3206 }
3207
3208 // Try to transform multiply-by-(power-of-2 +/- 1) into shift and add/sub.
3209 // mul x, (2^N + 1) --> add (shl x, N), x
3210 // mul x, (2^N - 1) --> sub (shl x, N), x
3211 // Examples: x * 33 --> (x << 5) + x
3212 // x * 15 --> (x << 4) - x
3213 // x * -33 --> -((x << 5) + x)
3214 // x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
3215 if (N1IsConst && TLI.decomposeMulByConstant(VT, N1)) {
3216 // TODO: We could handle more general decomposition of any constant by
3217 // having the target set a limit on number of ops and making a
3218 // callback to determine that sequence (similar to sqrt expansion).
3219 unsigned MathOp = ISD::DELETED_NODE;
3220 APInt MulC = ConstValue1.abs();
3221 if ((MulC - 1).isPowerOf2())
3222 MathOp = ISD::ADD;
3223 else if ((MulC + 1).isPowerOf2())
3224 MathOp = ISD::SUB;
3225
3226 if (MathOp != ISD::DELETED_NODE) {
3227 unsigned ShAmt = MathOp == ISD::ADD ? (MulC - 1).logBase2()
3228 : (MulC + 1).logBase2();
3229 assert(ShAmt > 0 && ShAmt < VT.getScalarSizeInBits() &&((ShAmt > 0 && ShAmt < VT.getScalarSizeInBits()
&& "Not expecting multiply-by-constant that could have simplified"
) ? static_cast<void> (0) : __assert_fail ("ShAmt > 0 && ShAmt < VT.getScalarSizeInBits() && \"Not expecting multiply-by-constant that could have simplified\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3230, __PRETTY_FUNCTION__))
3230 "Not expecting multiply-by-constant that could have simplified")((ShAmt > 0 && ShAmt < VT.getScalarSizeInBits()
&& "Not expecting multiply-by-constant that could have simplified"
) ? static_cast<void> (0) : __assert_fail ("ShAmt > 0 && ShAmt < VT.getScalarSizeInBits() && \"Not expecting multiply-by-constant that could have simplified\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3230, __PRETTY_FUNCTION__))
;
3231 SDLoc DL(N);
3232 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, N0,
3233 DAG.getConstant(ShAmt, DL, VT));
3234 SDValue R = DAG.getNode(MathOp, DL, VT, Shl, N0);
3235 if (ConstValue1.isNegative())
3236 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3237 return R;
3238 }
3239 }
3240
3241 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
3242 if (N0.getOpcode() == ISD::SHL &&
3243 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3244 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3245 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3246 if (isConstantOrConstantVector(C3))
3247 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3248 }
3249
3250 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
3251 // use.
3252 {
3253 SDValue Sh(nullptr, 0), Y(nullptr, 0);
3254
3255 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
3256 if (N0.getOpcode() == ISD::SHL &&
3257 isConstantOrConstantVector(N0.getOperand(1)) &&
3258 N0.getNode()->hasOneUse()) {
3259 Sh = N0; Y = N1;
3260 } else if (N1.getOpcode() == ISD::SHL &&
3261 isConstantOrConstantVector(N1.getOperand(1)) &&
3262 N1.getNode()->hasOneUse()) {
3263 Sh = N1; Y = N0;
3264 }
3265
3266 if (Sh.getNode()) {
3267 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3268 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3269 }
3270 }
3271
3272 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
3273 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
3274 N0.getOpcode() == ISD::ADD &&
3275 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
3276 isMulAddWithConstProfitable(N, N0, N1))
3277 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
3278 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
3279 N0.getOperand(0), N1),
3280 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
3281 N0.getOperand(1), N1));
3282
3283 // reassociate mul
3284 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3285 return RMUL;
3286
3287 return SDValue();
3288}
3289
3290/// Return true if divmod libcall is available.
3291static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
3292 const TargetLowering &TLI) {
3293 RTLIB::Libcall LC;
3294 EVT NodeType = Node->getValueType(0);
3295 if (!NodeType.isSimple())
3296 return false;
3297 switch (NodeType.getSimpleVT().SimpleTy) {
3298 default: return false; // No libcall for vector types.
3299 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
3300 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
3301 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
3302 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
3303 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
3304 }
3305
3306 return TLI.getLibcallName(LC) != nullptr;
3307}
3308
3309/// Issue divrem if both quotient and remainder are needed.
3310SDValue DAGCombiner::useDivRem(SDNode *Node) {
3311 if (Node->use_empty())
3312 return SDValue(); // This is a dead node, leave it alone.
3313
3314 unsigned Opcode = Node->getOpcode();
3315 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3316 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3317
3318 // DivMod lib calls can still work on non-legal types if using lib-calls.
3319 EVT VT = Node->getValueType(0);
3320 if (VT.isVector() || !VT.isInteger())
3321 return SDValue();
3322
3323 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
3324 return SDValue();
3325
3326 // If DIVREM is going to get expanded into a libcall,
3327 // but there is no libcall available, then don't combine.
3328 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
3329 !isDivRemLibcallAvailable(Node, isSigned, TLI))
3330 return SDValue();
3331
3332 // If div is legal, it's better to do the normal expansion
3333 unsigned OtherOpcode = 0;
3334 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3335 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3336 if (TLI.isOperationLegalOrCustom(Opcode, VT))
3337 return SDValue();
3338 } else {
3339 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3340 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
3341 return SDValue();
3342 }
3343
3344 SDValue Op0 = Node->getOperand(0);
3345 SDValue Op1 = Node->getOperand(1);
3346 SDValue combined;
3347 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
3348 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
3349 SDNode *User = *UI;
3350 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
3351 User->use_empty())
3352 continue;
3353 // Convert the other matching node(s), too;
3354 // otherwise, the DIVREM may get target-legalized into something
3355 // target-specific that we won't be able to recognize.
3356 unsigned UserOpc = User->getOpcode();
3357 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
3358 User->getOperand(0) == Op0 &&
3359 User->getOperand(1) == Op1) {
3360 if (!combined) {
3361 if (UserOpc == OtherOpcode) {
3362 SDVTList VTs = DAG.getVTList(VT, VT);
3363 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
3364 } else if (UserOpc == DivRemOpc) {
3365 combined = SDValue(User, 0);
3366 } else {
3367 assert(UserOpc == Opcode)((UserOpc == Opcode) ? static_cast<void> (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3367, __PRETTY_FUNCTION__))
;
3368 continue;
3369 }
3370 }
3371 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3372 CombineTo(User, combined);
3373 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3374 CombineTo(User, combined.getValue(1));
3375 }
3376 }
3377 return combined;
3378}
3379
3380static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
3381 SDValue N0 = N->getOperand(0);
3382 SDValue N1 = N->getOperand(1);
3383 EVT VT = N->getValueType(0);
3384 SDLoc DL(N);
3385
3386 unsigned Opc = N->getOpcode();
3387 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3388 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3389
3390 // X / undef -> undef
3391 // X % undef -> undef
3392 // X / 0 -> undef
3393 // X % 0 -> undef
3394 // NOTE: This includes vectors where any divisor element is zero/undef.
3395 if (DAG.isUndef(Opc, {N0, N1}))
3396 return DAG.getUNDEF(VT);
3397
3398 // undef / X -> 0
3399 // undef % X -> 0
3400 if (N0.isUndef())
3401 return DAG.getConstant(0, DL, VT);
3402
3403 // 0 / X -> 0
3404 // 0 % X -> 0
3405 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3406 if (N0C && N0C->isNullValue())
3407 return N0;
3408
3409 // X / X -> 1
3410 // X % X -> 0
3411 if (N0 == N1)
3412 return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);
3413
3414 // X / 1 -> X
3415 // X % 1 -> 0
3416 // If this is a boolean op (single-bit element type), we can't have
3417 // division-by-zero or remainder-by-zero, so assume the divisor is 1.
3418 // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
3419 // it's a 1.
3420 if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
3421 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
3422
3423 return SDValue();
3424}
3425
3426SDValue DAGCombiner::visitSDIV(SDNode *N) {
3427 SDValue N0 = N->getOperand(0);
3428 SDValue N1 = N->getOperand(1);
3429 EVT VT = N->getValueType(0);
3430 EVT CCVT = getSetCCResultType(VT);
3431
3432 // fold vector ops
3433 if (VT.isVector())
3434 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3435 return FoldedVOp;
3436
3437 SDLoc DL(N);
3438
3439 // fold (sdiv c1, c2) -> c1/c2
3440 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3441 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3442 if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
3443 return DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, N0C, N1C);
3444 // fold (sdiv X, -1) -> 0-X
3445 if (N1C && N1C->isAllOnesValue())
3446 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
3447 // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
3448 if (N1C && N1C->getAPIntValue().isMinSignedValue())
3449 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3450 DAG.getConstant(1, DL, VT),
3451 DAG.getConstant(0, DL, VT));
3452
3453 if (SDValue V = simplifyDivRem(N, DAG))
3454 return V;
3455
3456 if (SDValue NewSel = foldBinOpIntoSelect(N))
3457 return NewSel;
3458
3459 // If we know the sign bits of both operands are zero, strength reduce to a
3460 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
3461 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3462 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
3463
3464 if (SDValue V = visitSDIVLike(N0, N1, N)) {
3465 // If the corresponding remainder node exists, update its users with
3466 // (Dividend - (Quotient * Divisor).
3467 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
3468 { N0, N1 })) {
3469 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3470 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3471 AddToWorklist(Mul.getNode());
3472 AddToWorklist(Sub.getNode());
3473 CombineTo(RemNode, Sub);
3474 }
3475 return V;
3476 }
3477
3478 // sdiv, srem -> sdivrem
3479 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3480 // true. Otherwise, we break the simplification logic in visitREM().
3481 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3482 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3483 if (SDValue DivRem = useDivRem(N))
3484 return DivRem;
3485
3486 return SDValue();
3487}
3488
3489SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3490 SDLoc DL(N);
3491 EVT VT = N->getValueType(0);
3492 EVT CCVT = getSetCCResultType(VT);
3493 unsigned BitWidth = VT.getScalarSizeInBits();
3494
3495 // Helper for determining whether a value is a power-2 constant scalar or a
3496 // vector of such elements.
3497 auto IsPowerOfTwo = [](ConstantSDNode *C) {
3498 if (C->isNullValue() || C->isOpaque())
3499 return false;
3500 if (C->getAPIntValue().isPowerOf2())
3501 return true;
3502 if ((-C->getAPIntValue()).isPowerOf2())
3503 return true;
3504 return false;
3505 };
3506
3507 // fold (sdiv X, pow2) -> simple ops after legalize
3508 // FIXME: We check for the exact bit here because the generic lowering gives
3509 // better results in that case. The target-specific lowering should learn how
3510 // to handle exact sdivs efficiently.
3511 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
3512 // Target-specific implementation of sdiv x, pow2.
3513 if (SDValue Res = BuildSDIVPow2(N))
3514 return Res;
3515
3516 // Create constants that are functions of the shift amount value.
3517 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
3518 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
3519 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
3520 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
3521 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
3522 if (!isConstantOrConstantVector(Inexact))
3523 return SDValue();
3524
3525 // Splat the sign bit into the register
3526 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
3527 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
3528 AddToWorklist(Sign.getNode());
3529
3530 // Add (N0 < 0) ? abs2 - 1 : 0;
3531 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
3532 AddToWorklist(Srl.getNode());
3533 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
3534 AddToWorklist(Add.getNode());
3535 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
3536 AddToWorklist(Sra.getNode());
3537
3538 // Special case: (sdiv X, 1) -> X
3539 // Special Case: (sdiv X, -1) -> 0-X
3540 SDValue One = DAG.getConstant(1, DL, VT);
3541 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
3542 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
3543 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
3544 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
3545 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
3546
3547 // If dividing by a positive value, we're done. Otherwise, the result must
3548 // be negated.
3549 SDValue Zero = DAG.getConstant(0, DL, VT);
3550 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
3551
3552 // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
3553 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
3554 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
3555 return Res;
3556 }
3557
3558 // If integer divide is expensive and we satisfy the requirements, emit an
3559 // alternate sequence. Targets may check function attributes for size/speed
3560 // trade-offs.
3561 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3562 if (isConstantOrConstantVector(N1) &&
3563 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3564 if (SDValue Op = BuildSDIV(N))
3565 return Op;
3566
3567 return SDValue();
3568}
3569
3570SDValue DAGCombiner::visitUDIV(SDNode *N) {
3571 SDValue N0 = N->getOperand(0);
3572 SDValue N1 = N->getOperand(1);
3573 EVT VT = N->getValueType(0);
3574 EVT CCVT = getSetCCResultType(VT);
3575
3576 // fold vector ops
3577 if (VT.isVector())
3578 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3579 return FoldedVOp;
3580
3581 SDLoc DL(N);
3582
3583 // fold (udiv c1, c2) -> c1/c2
3584 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3585 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3586 if (N0C && N1C)
3587 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
3588 N0C, N1C))
3589 return Folded;
3590 // fold (udiv X, -1) -> select(X == -1, 1, 0)
3591 if (N1C && N1C->getAPIntValue().isAllOnesValue())
3592 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3593 DAG.getConstant(1, DL, VT),
3594 DAG.getConstant(0, DL, VT));
3595
3596 if (SDValue V = simplifyDivRem(N, DAG))
3597 return V;
3598
3599 if (SDValue NewSel = foldBinOpIntoSelect(N))
3600 return NewSel;
3601
3602 if (SDValue V = visitUDIVLike(N0, N1, N)) {
3603 // If the corresponding remainder node exists, update its users with
3604 // (Dividend - (Quotient * Divisor).
3605 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
3606 { N0, N1 })) {
3607 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3608 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3609 AddToWorklist(Mul.getNode());
3610 AddToWorklist(Sub.getNode());
3611 CombineTo(RemNode, Sub);
3612 }
3613 return V;
3614 }
3615
3616 // sdiv, srem -> sdivrem
3617 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3618 // true. Otherwise, we break the simplification logic in visitREM().
3619 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3620 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3621 if (SDValue DivRem = useDivRem(N))
3622 return DivRem;
3623
3624 return SDValue();
3625}
3626
3627SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3628 SDLoc DL(N);
3629 EVT VT = N->getValueType(0);
3630
3631 // fold (udiv x, (1 << c)) -> x >>u c
3632 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3633 DAG.isKnownToBeAPowerOfTwo(N1)) {
3634 SDValue LogBase2 = BuildLogBase2(N1, DL);
3635 AddToWorklist(LogBase2.getNode());
3636
3637 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3638 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3639 AddToWorklist(Trunc.getNode());
3640 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
3641 }
3642
3643 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
3644 if (N1.getOpcode() == ISD::SHL) {
3645 SDValue N10 = N1.getOperand(0);
3646 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
3647 DAG.isKnownToBeAPowerOfTwo(N10)) {
3648 SDValue LogBase2 = BuildLogBase2(N10, DL);
3649 AddToWorklist(LogBase2.getNode());
3650
3651 EVT ADDVT = N1.getOperand(1).getValueType();
3652 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
3653 AddToWorklist(Trunc.getNode());
3654 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
3655 AddToWorklist(Add.getNode());
3656 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
3657 }
3658 }
3659
3660 // fold (udiv x, c) -> alternate
3661 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3662 if (isConstantOrConstantVector(N1) &&
3663 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3664 if (SDValue Op = BuildUDIV(N))
3665 return Op;
3666
3667 return SDValue();
3668}
3669
3670// handles ISD::SREM and ISD::UREM
3671SDValue DAGCombiner::visitREM(SDNode *N) {
3672 unsigned Opcode = N->getOpcode();
3673 SDValue N0 = N->getOperand(0);
3674 SDValue N1 = N->getOperand(1);
3675 EVT VT = N->getValueType(0);
3676 EVT CCVT = getSetCCResultType(VT);
3677
3678 bool isSigned = (Opcode == ISD::SREM);
3679 SDLoc DL(N);
3680
3681 // fold (rem c1, c2) -> c1%c2
3682 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3683 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3684 if (N0C && N1C)
3685 if (SDValue Folded = DAG.FoldConstantArithmetic(Opcode, DL, VT, N0C, N1C))
3686 return Folded;
3687 // fold (urem X, -1) -> select(X == -1, 0, x)
3688 if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
3689 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3690 DAG.getConstant(0, DL, VT), N0);
3691
3692 if (SDValue V = simplifyDivRem(N, DAG))
3693 return V;
3694
3695 if (SDValue NewSel = foldBinOpIntoSelect(N))
3696 return NewSel;
3697
3698 if (isSigned) {
3699 // If we know the sign bits of both operands are zero, strength reduce to a
3700 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
3701 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3702 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
3703 } else {
3704 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
3705 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
3706 // fold (urem x, pow2) -> (and x, pow2-1)
3707 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
3708 AddToWorklist(Add.getNode());
3709 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3710 }
3711 if (N1.getOpcode() == ISD::SHL &&
3712 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
3713 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
3714 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
3715 AddToWorklist(Add.getNode());
3716 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3717 }
3718 }
3719
3720 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3721
3722 // If X/C can be simplified by the division-by-constant logic, lower
3723 // X%C to the equivalent of X-X/C*C.
3724 // Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
3725 // speculative DIV must not cause a DIVREM conversion. We guard against this
3726 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
3727 // combine will not return a DIVREM. Regardless, checking cheapness here
3728 // makes sense since the simplification results in fatter code.
3729 if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
3730 SDValue OptimizedDiv =
3731 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
3732 if (OptimizedDiv.getNode()) {
3733 // If the equivalent Div node also exists, update its users.
3734 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3735 if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
3736 { N0, N1 }))
3737 CombineTo(DivNode, OptimizedDiv);
3738 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
3739 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3740 AddToWorklist(OptimizedDiv.getNode());
3741 AddToWorklist(Mul.getNode());
3742 return Sub;
3743 }
3744 }
3745
3746 // sdiv, srem -> sdivrem
3747 if (SDValue DivRem = useDivRem(N))
3748 return DivRem.getValue(1);
3749
3750 return SDValue();
3751}
3752
3753SDValue DAGCombiner::visitMULHS(SDNode *N) {
3754 SDValue N0 = N->getOperand(0);
3755 SDValue N1 = N->getOperand(1);
3756 EVT VT = N->getValueType(0);
3757 SDLoc DL(N);
3758
3759 if (VT.isVector()) {
3760 // fold (mulhs x, 0) -> 0
3761 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3762 return N1;
3763 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3764 return N0;
3765 }
3766
3767 // fold (mulhs x, 0) -> 0
3768 if (isNullConstant(N1))
3769 return N1;
3770 // fold (mulhs x, 1) -> (sra x, size(x)-1)
3771 if (isOneConstant(N1))
3772 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
3773 DAG.getConstant(N0.getValueSizeInBits() - 1, DL,
3774 getShiftAmountTy(N0.getValueType())));
3775
3776 // fold (mulhs x, undef) -> 0
3777 if (N0.isUndef() || N1.isUndef())
3778 return DAG.getConstant(0, DL, VT);
3779
3780 // If the type twice as wide is legal, transform the mulhs to a wider multiply
3781 // plus a shift.
3782 if (VT.isSimple() && !VT.isVector()) {
3783 MVT Simple = VT.getSimpleVT();
3784 unsigned SimpleSize = Simple.getSizeInBits();
3785 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3786 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3787 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
3788 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
3789 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
3790 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
3791 DAG.getConstant(SimpleSize, DL,
3792 getShiftAmountTy(N1.getValueType())));
3793 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
3794 }
3795 }
3796
3797 return SDValue();
3798}
3799
3800SDValue DAGCombiner::visitMULHU(SDNode *N) {
3801 SDValue N0 = N->getOperand(0);
3802 SDValue N1 = N->getOperand(1);
3803 EVT VT = N->getValueType(0);
3804 SDLoc DL(N);
3805
3806 if (VT.isVector()) {
3807 // fold (mulhu x, 0) -> 0
3808 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3809 return N1;
3810 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3811 return N0;
3812 }
3813
3814 // fold (mulhu x, 0) -> 0
3815 if (isNullConstant(N1))
3816 return N1;
3817 // fold (mulhu x, 1) -> 0
3818 if (isOneConstant(N1))
3819 return DAG.getConstant(0, DL, N0.getValueType());
3820 // fold (mulhu x, undef) -> 0
3821 if (N0.isUndef() || N1.isUndef())
3822 return DAG.getConstant(0, DL, VT);
3823
3824 // fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
3825 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3826 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
3827 unsigned NumEltBits = VT.getScalarSizeInBits();
3828 SDValue LogBase2 = BuildLogBase2(N1, DL);
3829 SDValue SRLAmt = DAG.getNode(
3830 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
3831 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3832 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
3833 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
3834 }
3835
3836 // If the type twice as wide is legal, transform the mulhu to a wider multiply
3837 // plus a shift.
3838 if (VT.isSimple() && !VT.isVector()) {
3839 MVT Simple = VT.getSimpleVT();
3840 unsigned SimpleSize = Simple.getSizeInBits();
3841 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3842 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3843 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
3844 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
3845 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
3846 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
3847 DAG.getConstant(SimpleSize, DL,
3848 getShiftAmountTy(N1.getValueType())));
3849 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
3850 }
3851 }
3852
3853 return SDValue();
3854}
3855
3856/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
3857/// give the opcodes for the two computations that are being performed. Return
3858/// true if a simplification was made.
3859SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
3860 unsigned HiOp) {
3861 // If the high half is not needed, just compute the low half.
3862 bool HiExists = N->hasAnyUseOfValue(1);
3863 if (!HiExists && (!LegalOperations ||
3864 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
3865 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
3866 return CombineTo(N, Res, Res);
3867 }
3868
3869 // If the low half is not needed, just compute the high half.
3870 bool LoExists = N->hasAnyUseOfValue(0);
3871 if (!LoExists && (!LegalOperations ||
3872 TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
3873 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
3874 return CombineTo(N, Res, Res);
3875 }
3876
3877 // If both halves are used, return as it is.
3878 if (LoExists && HiExists)
3879 return SDValue();
3880
3881 // If the two computed results can be simplified separately, separate them.
3882 if (LoExists) {
3883 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
3884 AddToWorklist(Lo.getNode());
3885 SDValue LoOpt = combine(Lo.getNode());
3886 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
3887 (!LegalOperations ||
3888 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
3889 return CombineTo(N, LoOpt, LoOpt);
3890 }
3891
3892 if (HiExists) {
3893 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
3894 AddToWorklist(Hi.getNode());
3895 SDValue HiOpt = combine(Hi.getNode());
3896 if (HiOpt.getNode() && HiOpt != Hi &&
3897 (!LegalOperations ||
3898 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
3899 return CombineTo(N, HiOpt, HiOpt);
3900 }
3901
3902 return SDValue();
3903}
3904
3905SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
3906 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
3907 return Res;
3908
3909 EVT VT = N->getValueType(0);
3910 SDLoc DL(N);
3911
3912 // If the type is twice as wide is legal, transform the mulhu to a wider
3913 // multiply plus a shift.
3914 if (VT.isSimple() && !VT.isVector()) {
3915 MVT Simple = VT.getSimpleVT();
3916 unsigned SimpleSize = Simple.getSizeInBits();
3917 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3918 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3919 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
3920 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
3921 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
3922 // Compute the high part as N1.
3923 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
3924 DAG.getConstant(SimpleSize, DL,
3925 getShiftAmountTy(Lo.getValueType())));
3926 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
3927 // Compute the low part as N0.
3928 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
3929 return CombineTo(N, Lo, Hi);
3930 }
3931 }
3932
3933 return SDValue();
3934}
3935
3936SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
3937 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
3938 return Res;
3939
3940 EVT VT = N->getValueType(0);
3941 SDLoc DL(N);
3942
3943 // If the type is twice as wide is legal, transform the mulhu to a wider
3944 // multiply plus a shift.
3945 if (VT.isSimple() && !VT.isVector()) {
3946 MVT Simple = VT.getSimpleVT();
3947 unsigned SimpleSize = Simple.getSizeInBits();
3948 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3949 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3950 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
3951 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
3952 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
3953 // Compute the high part as N1.
3954 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
3955 DAG.getConstant(SimpleSize, DL,
3956 getShiftAmountTy(Lo.getValueType())));
3957 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
3958 // Compute the low part as N0.
3959 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
3960 return CombineTo(N, Lo, Hi);
3961 }
3962 }
3963
3964 return SDValue();
3965}
3966
3967SDValue DAGCombiner::visitMULO(SDNode *N) {
3968 bool IsSigned = (ISD::SMULO == N->getOpcode());
3969
3970 // (mulo x, 2) -> (addo x, x)
3971 if (ConstantSDNode *C2 = isConstOrConstSplat(N->getOperand(1)))
3972 if (C2->getAPIntValue() == 2)
3973 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, SDLoc(N),
3974 N->getVTList(), N->getOperand(0), N->getOperand(0));
3975
3976 return SDValue();
3977}
3978
3979SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
3980 SDValue N0 = N->getOperand(0);
3981 SDValue N1 = N->getOperand(1);
3982 EVT VT = N0.getValueType();
3983
3984 // fold vector ops
3985 if (VT.isVector())
3986 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3987 return FoldedVOp;
3988
3989 // fold operation with constant operands.
3990 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3991 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3992 if (N0C && N1C)
3993 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
3994
3995 // canonicalize constant to RHS
3996 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3997 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3998 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
3999
4000 // Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
4001 // Only do this if the current op isn't legal and the flipped is.
4002 unsigned Opcode = N->getOpcode();
4003 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4004 if (!TLI.isOperationLegal(Opcode, VT) &&
4005 (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
4006 (N1.isUndef() || DAG.SignBitIsZero(N1))) {
4007 unsigned AltOpcode;
4008 switch (Opcode) {
4009 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4010 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4011 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
4012 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
4013 default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4013)
;
4014 }
4015 if (TLI.isOperationLegal(AltOpcode, VT))
4016 return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
4017 }
4018
4019 return SDValue();
4020}
4021
4022/// If this is a bitwise logic instruction and both operands have the same
4023/// opcode, try to sink the other opcode after the logic instruction.
4024SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
4025 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4026 EVT VT = N0.getValueType();
4027 unsigned LogicOpcode = N->getOpcode();
4028 unsigned HandOpcode = N0.getOpcode();
4029 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4030, __PRETTY_FUNCTION__))
4030 LogicOpcode == ISD::XOR) && "Expected logic opcode")(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4030, __PRETTY_FUNCTION__))
;
4031 assert(HandOpcode == N1.getOpcode() && "Bad input!")((HandOpcode == N1.getOpcode() && "Bad input!") ? static_cast
<void> (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4031, __PRETTY_FUNCTION__))
;
4032
4033 // Bail early if none of these transforms apply.
4034 if (N0.getNumOperands() == 0)
4035 return SDValue();
4036
4037 // FIXME: We should check number of uses of the operands to not increase
4038 // the instruction count for all transforms.
4039
4040 // Handle size-changing casts.
4041 SDValue X = N0.getOperand(0);
4042 SDValue Y = N1.getOperand(0);
4043 EVT XVT = X.getValueType();
4044 SDLoc DL(N);
4045 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4046 HandOpcode == ISD::SIGN_EXTEND) {
4047 // If both operands have other uses, this transform would create extra
4048 // instructions without eliminating anything.
4049 if (!N0.hasOneUse() && !N1.hasOneUse())
4050 return SDValue();
4051 // We need matching integer source types.
4052 if (XVT != Y.getValueType())
4053 return SDValue();
4054 // Don't create an illegal op during or after legalization. Don't ever
4055 // create an unsupported vector op.
4056 if ((VT.isVector() || LegalOperations) &&
4057 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4058 return SDValue();
4059 // Avoid infinite looping with PromoteIntBinOp.
4060 // TODO: Should we apply desirable/legal constraints to all opcodes?
4061 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
4062 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4063 return SDValue();
4064 // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
4065 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4066 return DAG.getNode(HandOpcode, DL, VT, Logic);
4067 }
4068
4069 // logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
4070 if (HandOpcode == ISD::TRUNCATE) {
4071 // If both operands have other uses, this transform would create extra
4072 // instructions without eliminating anything.
4073 if (!N0.hasOneUse() && !N1.hasOneUse())
4074 return SDValue();
4075 // We need matching source types.
4076 if (XVT != Y.getValueType())
4077 return SDValue();
4078 // Don't create an illegal op during or after legalization.
4079 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4080 return SDValue();
4081 // Be extra careful sinking truncate. If it's free, there's no benefit in
4082 // widening a binop. Also, don't create a logic op on an illegal type.
4083 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
4084 return SDValue();
4085 if (!TLI.isTypeLegal(XVT))
4086 return SDValue();
4087 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4088 return DAG.getNode(HandOpcode, DL, VT, Logic);
4089 }
4090
4091 // For binops SHL/SRL/SRA/AND:
4092 // logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
4093 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4094 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4095 N0.getOperand(1) == N1.getOperand(1)) {
4096 // If either operand has other uses, this transform is not an improvement.
4097 if (!N0.hasOneUse() || !N1.hasOneUse())
4098 return SDValue();
4099 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4100 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
4101 }
4102
4103 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
4104 if (HandOpcode == ISD::BSWAP) {
4105 // If either operand has other uses, this transform is not an improvement.
4106 if (!N0.hasOneUse() || !N1.hasOneUse())
4107 return SDValue();
4108 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4109 return DAG.getNode(HandOpcode, DL, VT, Logic);
4110 }
4111
4112 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
4113 // Only perform this optimization up until type legalization, before
4114 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
4115 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
4116 // we don't want to undo this promotion.
4117 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4118 // on scalars.
4119 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
4120 Level <= AfterLegalizeTypes) {
4121 // Input types must be integer and the same.
4122 if (XVT.isInteger() && XVT == Y.getValueType()) {
4123 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4124 return DAG.getNode(HandOpcode, DL, VT, Logic);
4125 }
4126 }
4127
4128 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
4129 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
4130 // If both shuffles use the same mask, and both shuffle within a single
4131 // vector, then it is worthwhile to move the swizzle after the operation.
4132 // The type-legalizer generates this pattern when loading illegal
4133 // vector types from memory. In many cases this allows additional shuffle
4134 // optimizations.
4135 // There are other cases where moving the shuffle after the xor/and/or
4136 // is profitable even if shuffles don't perform a swizzle.
4137 // If both shuffles use the same mask, and both shuffles have the same first
4138 // or second operand, then it might still be profitable to move the shuffle
4139 // after the xor/and/or operation.
4140 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
4141 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
4142 auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
4143 assert(X.getValueType() == Y.getValueType() &&((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4144, __PRETTY_FUNCTION__))
4144 "Inputs to shuffles are not the same type")((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4144, __PRETTY_FUNCTION__))
;
4145
4146 // Check that both shuffles use the same mask. The masks are known to be of
4147 // the same length because the result vector type is the same.
4148 // Check also that shuffles have only one use to avoid introducing extra
4149 // instructions.
4150 if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
4151 !SVN0->getMask().equals(SVN1->getMask()))
4152 return SDValue();
4153
4154 // Don't try to fold this node if it requires introducing a
4155 // build vector of all zeros that might be illegal at this stage.
4156 SDValue ShOp = N0.getOperand(1);
4157 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4158 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4159
4160 // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
4161 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4162 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
4163 N0.getOperand(0), N1.getOperand(0));
4164 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4165 }
4166
4167 // Don't try to fold this node if it requires introducing a
4168 // build vector of all zeros that might be illegal at this stage.
4169 ShOp = N0.getOperand(0);
4170 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4171 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4172
4173 // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
4174 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4175 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
4176 N1.getOperand(1));
4177 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
4178 }
4179 }
4180
4181 return SDValue();
4182}
4183
4184/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4185SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
4186 const SDLoc &DL) {
4187 SDValue LL, LR, RL, RR, N0CC, N1CC;
4188 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
4189 !isSetCCEquivalent(N1, RL, RR, N1CC))
4190 return SDValue();
4191
4192 assert(N0.getValueType() == N1.getValueType() &&((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4193, __PRETTY_FUNCTION__))
4193 "Unexpected operand types for bitwise logic op")((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4193, __PRETTY_FUNCTION__))
;
4194 assert(LL.getValueType() == LR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4196, __PRETTY_FUNCTION__))
4195 RL.getValueType() == RR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4196, __PRETTY_FUNCTION__))
4196 "Unexpected operand types for setcc")((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4196, __PRETTY_FUNCTION__))
;
4197
4198 // If we're here post-legalization or the logic op type is not i1, the logic
4199 // op type must match a setcc result type. Also, all folds require new
4200 // operations on the left and right operands, so those types must match.
4201 EVT VT = N0.getValueType();
4202 EVT OpVT = LL.getValueType();
4203 if (LegalOperations || VT.getScalarType() != MVT::i1)
4204 if (VT != getSetCCResultType(OpVT))
4205 return SDValue();
4206 if (OpVT != RL.getValueType())
4207 return SDValue();
4208
4209 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
4210 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
4211 bool IsInteger = OpVT.isInteger();
4212 if (LR == RR && CC0 == CC1 && IsInteger) {
4213 bool IsZero = isNullOrNullSplat(LR);
4214 bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);
4215
4216 // All bits clear?
4217 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4218 // All sign bits clear?
4219 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4220 // Any bits set?
4221 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4222 // Any sign bits set?
4223 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4224
4225 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
4226 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
4227 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
4228 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
4229 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
4230 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
4231 AddToWorklist(Or.getNode());
4232 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4233 }
4234
4235 // All bits set?
4236 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4237 // All sign bits set?
4238 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4239 // Any bits clear?
4240 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
4241 // Any sign bits clear?
4242 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
4243
4244 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
4245 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
4246 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
4247 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
4248 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
4249 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
4250 AddToWorklist(And.getNode());
4251 return DAG.getSetCC(DL, VT, And, LR, CC1);
4252 }
4253 }
4254
4255 // TODO: What is the 'or' equivalent of this fold?
4256 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
4257 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
4258 IsInteger && CC0 == ISD::SETNE &&
4259 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
4260 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
4261 SDValue One = DAG.getConstant(1, DL, OpVT);
4262 SDValue Two = DAG.getConstant(2, DL, OpVT);
4263 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
4264 AddToWorklist(Add.getNode());
4265 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
4266 }
4267
4268 // Try more general transforms if the predicates match and the only user of
4269 // the compares is the 'and' or 'or'.
4270 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
4271 N0.hasOneUse() && N1.hasOneUse()) {
4272 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
4273 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
4274 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
4275 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
4276 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
4277 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
4278 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4279 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
4280 }
4281
4282 // Turn compare of constants whose difference is 1 bit into add+and+setcc.
4283 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
4284 // Match a shared variable operand and 2 non-opaque constant operands.
4285 ConstantSDNode *C0 = isConstOrConstSplat(LR);
4286 ConstantSDNode *C1 = isConstOrConstSplat(RR);
4287 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
4288 // Canonicalize larger constant as C0.
4289 if (C1->getAPIntValue().ugt(C0->getAPIntValue()))
4290 std::swap(C0, C1);
4291
4292 // The difference of the constants must be a single bit.
4293 const APInt &C0Val = C0->getAPIntValue();
4294 const APInt &C1Val = C1->getAPIntValue();
4295 if ((C0Val - C1Val).isPowerOf2()) {
4296 // and/or (setcc X, C0, ne), (setcc X, C1, ne/eq) -->
4297 // setcc ((add X, -C1), ~(C0 - C1)), 0, ne/eq
4298 SDValue OffsetC = DAG.getConstant(-C1Val, DL, OpVT);
4299 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LL, OffsetC);
4300 SDValue MaskC = DAG.getConstant(~(C0Val - C1Val), DL, OpVT);
4301 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
4302 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4303 return DAG.getSetCC(DL, VT, And, Zero, CC0);
4304 }
4305 }
4306 }
4307 }
4308
4309 // Canonicalize equivalent operands to LL == RL.
4310 if (LL == RR && LR == RL) {
4311 CC1 = ISD::getSetCCSwappedOperands(CC1);
4312 std::swap(RL, RR);
4313 }
4314
4315 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4316 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4317 if (LL == RL && LR == RR) {
4318 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, IsInteger)
4319 : ISD::getSetCCOrOperation(CC0, CC1, IsInteger);
4320 if (NewCC != ISD::SETCC_INVALID &&
4321 (!LegalOperations ||
4322 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
4323 TLI.isOperationLegal(ISD::SETCC, OpVT))))
4324 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
4325 }
4326
4327 return SDValue();
4328}
4329
4330/// This contains all DAGCombine rules which reduce two values combined by
4331/// an And operation to a single value. This makes them reusable in the context
4332/// of visitSELECT(). Rules involving constants are not included as
4333/// visitSELECT() already handles those cases.
4334SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
4335 EVT VT = N1.getValueType();
4336 SDLoc DL(N);
4337
4338 // fold (and x, undef) -> 0
4339 if (N0.isUndef() || N1.isUndef())
4340 return DAG.getConstant(0, DL, VT);
4341
4342 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
4343 return V;
4344
4345 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4346 VT.getSizeInBits() <= 64) {
4347 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4348 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
4349 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
4350 // immediate for an add, but it is legal if its top c2 bits are set,
4351 // transform the ADD so the immediate doesn't need to be materialized
4352 // in a register.
4353 APInt ADDC = ADDI->getAPIntValue();
4354 APInt SRLC = SRLI->getAPIntValue();
4355 if (ADDC.getMinSignedBits() <= 64 &&
4356 SRLC.ult(VT.getSizeInBits()) &&
4357 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4358 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
4359 SRLC.getZExtValue());
4360 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
4361 ADDC |= Mask;
4362 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4363 SDLoc DL0(N0);
4364 SDValue NewAdd =
4365 DAG.getNode(ISD::ADD, DL0, VT,
4366 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
4367 CombineTo(N0.getNode(), NewAdd);
4368 // Return N so it doesn't get rechecked!
4369 return SDValue(N, 0);
4370 }
4371 }
4372 }
4373 }
4374 }
4375 }
4376
4377 // Reduce bit extract of low half of an integer to the narrower type.
4378 // (and (srl i64:x, K), KMask) ->
4379 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
4380 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4381 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
4382 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4383 unsigned Size = VT.getSizeInBits();
4384 const APInt &AndMask = CAnd->getAPIntValue();
4385 unsigned ShiftBits = CShift->getZExtValue();
4386
4387 // Bail out, this node will probably disappear anyway.
4388 if (ShiftBits == 0)
4389 return SDValue();
4390
4391 unsigned MaskBits = AndMask.countTrailingOnes();
4392 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
4393
4394 if (AndMask.isMask() &&
4395 // Required bits must not span the two halves of the integer and
4396 // must fit in the half size type.
4397 (ShiftBits + MaskBits <= Size / 2) &&
4398 TLI.isNarrowingProfitable(VT, HalfVT) &&
4399 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
4400 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
4401 TLI.isTruncateFree(VT, HalfVT) &&
4402 TLI.isZExtFree(HalfVT, VT)) {
4403 // The isNarrowingProfitable is to avoid regressions on PPC and
4404 // AArch64 which match a few 64-bit bit insert / bit extract patterns
4405 // on downstream users of this. Those patterns could probably be
4406 // extended to handle extensions mixed in.
4407
4408 SDValue SL(N0);
4409 assert(MaskBits <= Size)((MaskBits <= Size) ? static_cast<void> (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4409, __PRETTY_FUNCTION__))
;
4410
4411 // Extracting the highest bit of the low half.
4412 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
4413 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
4414 N0.getOperand(0));
4415
4416 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
4417 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
4418 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
4419 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
4420 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
4421 }
4422 }
4423 }
4424 }
4425
4426 return SDValue();
4427}
4428
4429bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
4430 EVT LoadResultTy, EVT &ExtVT) {
4431 if (!AndC->getAPIntValue().isMask())
4432 return false;
4433
4434 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
4435
4436 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4437 EVT LoadedVT = LoadN->getMemoryVT();
4438
4439 if (ExtVT == LoadedVT &&
4440 (!LegalOperations ||
4441 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
4442 // ZEXTLOAD will match without needing to change the size of the value being
4443 // loaded.
4444 return true;
4445 }
4446
4447 // Do not change the width of a volatile load.
4448 if (LoadN->isVolatile())
4449 return false;
4450
4451 // Do not generate loads of non-round integer types since these can
4452 // be expensive (and would be wrong if the type is not byte sized).
4453 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
4454 return false;
4455
4456 if (LegalOperations &&
4457 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
4458 return false;
4459
4460 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
4461 return false;
4462
4463 return true;
4464}
4465
4466bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
4467 ISD::LoadExtType ExtType, EVT &MemVT,
4468 unsigned ShAmt) {
4469 if (!LDST)
4470 return false;
4471 // Only allow byte offsets.
4472 if (ShAmt % 8)
4473 return false;
4474
4475 // Do not generate loads of non-round integer types since these can
4476 // be expensive (and would be wrong if the type is not byte sized).
4477 if (!MemVT.isRound())
4478 return false;
4479
4480 // Don't change the width of a volatile load.
4481 if (LDST->isVolatile())
4482 return false;
4483
4484 // Verify that we are actually reducing a load width here.
4485 if (LDST->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits())
4486 return false;
4487
4488 // Ensure that this isn't going to produce an unsupported unaligned access.
4489 if (ShAmt &&
4490 !TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
4491 LDST->getAddressSpace(), ShAmt / 8))
4492 return false;
4493
4494 // It's not possible to generate a constant of extended or untyped type.
4495 EVT PtrType = LDST->getBasePtr().getValueType();
4496 if (PtrType == MVT::Untyped || PtrType.isExtended())
4497 return false;
4498
4499 if (isa<LoadSDNode>(LDST)) {
4500 LoadSDNode *Load = cast<LoadSDNode>(LDST);
4501 // Don't transform one with multiple uses, this would require adding a new
4502 // load.
4503 if (!SDValue(Load, 0).hasOneUse())
4504 return false;
4505
4506 if (LegalOperations &&
4507 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
4508 return false;
4509
4510 // For the transform to be legal, the load must produce only two values
4511 // (the value loaded and the chain). Don't transform a pre-increment
4512 // load, for example, which produces an extra value. Otherwise the
4513 // transformation is not equivalent, and the downstream logic to replace
4514 // uses gets things wrong.
4515 if (Load->getNumValues() > 2)
4516 return false;
4517
4518 // If the load that we're shrinking is an extload and we're not just
4519 // discarding the extension we can't simply shrink the load. Bail.
4520 // TODO: It would be possible to merge the extensions in some cases.
4521 if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
4522 Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4523 return false;
4524
4525 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
4526 return false;
4527 } else {
4528 assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")((isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode"
) ? static_cast<void> (0) : __assert_fail ("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4528, __PRETTY_FUNCTION__))
;
4529 StoreSDNode *Store = cast<StoreSDNode>(LDST);
4530 // Can't write outside the original store
4531 if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4532 return false;
4533
4534 if (LegalOperations &&
4535 !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
4536 return false;
4537 }
4538 return true;
4539}
4540
4541bool DAGCombiner::SearchForAndLoads(SDNode *N,
4542 SmallVectorImpl<LoadSDNode*> &Loads,
4543 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
4544 ConstantSDNode *Mask,
4545 SDNode *&NodeToMask) {
4546 // Recursively search for the operands, looking for loads which can be
4547 // narrowed.
4548 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) {
4549 SDValue Op = N->getOperand(i);
4550
4551 if (Op.getValueType().isVector())
4552 return false;
4553
4554 // Some constants may need fixing up later if they are too large.
4555 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
4556 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
4557 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
4558 NodesWithConsts.insert(N);
4559 continue;
4560 }
4561
4562 if (!Op.hasOneUse())
4563 return false;
4564
4565 switch(Op.getOpcode()) {
4566 case ISD::LOAD: {
4567 auto *Load = cast<LoadSDNode>(Op);
4568 EVT ExtVT;
4569 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
4570 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
4571
4572 // ZEXTLOAD is already small enough.
4573 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
4574 ExtVT.bitsGE(Load->getMemoryVT()))
4575 continue;
4576
4577 // Use LE to convert equal sized loads to zext.
4578 if (ExtVT.bitsLE(Load->getMemoryVT()))
4579 Loads.push_back(Load);
4580
4581 continue;
4582 }
4583 return false;
4584 }
4585 case ISD::ZERO_EXTEND:
4586 case ISD::AssertZext: {
4587 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
4588 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4589 EVT VT = Op.getOpcode() == ISD::AssertZext ?
4590 cast<VTSDNode>(Op.getOperand(1))->getVT() :
4591 Op.getOperand(0).getValueType();
4592
4593 // We can accept extending nodes if the mask is wider or an equal
4594 // width to the original type.
4595 if (ExtVT.bitsGE(VT))
4596 continue;
4597 break;
4598 }
4599 case ISD::OR:
4600 case ISD::XOR:
4601 case ISD::AND:
4602 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
4603 NodeToMask))
4604 return false;
4605 continue;
4606 }
4607
4608 // Allow one node which will masked along with any loads found.
4609 if (NodeToMask)
4610 return false;
4611
4612 // Also ensure that the node to be masked only produces one data result.
4613 NodeToMask = Op.getNode();
4614 if (NodeToMask->getNumValues() > 1) {
4615 bool HasValue = false;
4616 for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
4617 MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
4618 if (VT != MVT::Glue && VT != MVT::Other) {
4619 if (HasValue) {
4620 NodeToMask = nullptr;
4621 return false;
4622 }
4623 HasValue = true;
4624 }
4625 }
4626 assert(HasValue && "Node to be masked has no data result?")((HasValue && "Node to be masked has no data result?"
) ? static_cast<void> (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4626, __PRETTY_FUNCTION__))
;
4627 }
4628 }
4629 return true;
4630}
4631
4632bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
4633 auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
4634 if (!Mask)
4635 return false;
4636
4637 if (!Mask->getAPIntValue().isMask())
4638 return false;
4639
4640 // No need to do anything if the and directly uses a load.
4641 if (isa<LoadSDNode>(N->getOperand(0)))
4642 return false;
4643
4644 SmallVector<LoadSDNode*, 8> Loads;
4645 SmallPtrSet<SDNode*, 2> NodesWithConsts;
4646 SDNode *FixupNode = nullptr;
4647 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
4648 if (Loads.size() == 0)
4649 return false;
4650
4651 LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false)
;
4652 SDValue MaskOp = N->getOperand(1);
4653
4654 // If it exists, fixup the single node we allow in the tree that needs
4655 // masking.
4656 if (FixupNode) {
4657 LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false)
;
4658 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
4659 FixupNode->getValueType(0),
4660 SDValue(FixupNode, 0), MaskOp);
4661 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
4662 if (And.getOpcode() == ISD ::AND)
4663 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
4664 }
4665
4666 // Narrow any constants that need it.
4667 for (auto *LogicN : NodesWithConsts) {
4668 SDValue Op0 = LogicN->getOperand(0);
4669 SDValue Op1 = LogicN->getOperand(1);
4670
4671 if (isa<ConstantSDNode>(Op0))
4672 std::swap(Op0, Op1);
4673
4674 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
4675 Op1, MaskOp);
4676
4677 DAG.UpdateNodeOperands(LogicN, Op0, And);
4678 }
4679
4680 // Create narrow loads.
4681 for (auto *Load : Loads) {
4682 LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false)
;
4683 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
4684 SDValue(Load, 0), MaskOp);
4685 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
4686 if (And.getOpcode() == ISD ::AND)
4687 And = SDValue(
4688 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
4689 SDValue NewLoad = ReduceLoadWidth(And.getNode());
4690 assert(NewLoad &&((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4691, __PRETTY_FUNCTION__))
4691 "Shouldn't be masking the load if it can't be narrowed")((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4691, __PRETTY_FUNCTION__))
;
4692 CombineTo(Load, NewLoad, NewLoad.getValue(1));
4693 }
4694 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
4695 return true;
4696 }
4697 return false;
4698}
4699
4700// Unfold
4701// x & (-1 'logical shift' y)
4702// To
4703// (x 'opposite logical shift' y) 'logical shift' y
4704// if it is better for performance.
4705SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
4706 assert(N->getOpcode() == ISD::AND)((N->getOpcode() == ISD::AND) ? static_cast<void> (0
) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4706, __PRETTY_FUNCTION__))
;
4707
4708 SDValue N0 = N->getOperand(0);
4709 SDValue N1 = N->getOperand(1);
4710
4711 // Do we actually prefer shifts over mask?
4712 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
4713 return SDValue();
4714
4715 // Try to match (-1 '[outer] logical shift' y)
4716 unsigned OuterShift;
4717 unsigned InnerShift; // The opposite direction to the OuterShift.
4718 SDValue Y; // Shift amount.
4719 auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
4720 if (!M.hasOneUse())
4721 return false;
4722 OuterShift = M->getOpcode();
4723 if (OuterShift == ISD::SHL)
4724 InnerShift = ISD::SRL;
4725 else if (OuterShift == ISD::SRL)
4726 InnerShift = ISD::SHL;
4727 else
4728 return false;
4729 if (!isAllOnesConstant(M->getOperand(0)))
4730 return false;
4731 Y = M->getOperand(1);
4732 return true;
4733 };
4734
4735 SDValue X;
4736 if (matchMask(N1))
4737 X = N0;
4738 else if (matchMask(N0))
4739 X = N1;
4740 else
4741 return SDValue();
4742
4743 SDLoc DL(N);
4744 EVT VT = N->getValueType(0);
4745
4746 // tmp = x 'opposite logical shift' y
4747 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
4748 // ret = tmp 'logical shift' y
4749 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
4750
4751 return T1;
4752}
4753
4754SDValue DAGCombiner::visitAND(SDNode *N) {
4755 SDValue N0 = N->getOperand(0);
4756 SDValue N1 = N->getOperand(1);
4757 EVT VT = N1.getValueType();
4758
4759 // x & x --> x
4760 if (N0 == N1)
4761 return N0;
4762
4763 // fold vector ops
4764 if (VT.isVector()) {
4765 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4766 return FoldedVOp;
4767
4768 // fold (and x, 0) -> 0, vector edition
4769 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4770 // do not return N0, because undef node may exist in N0
4771 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
4772 SDLoc(N), N0.getValueType());
4773 if (ISD::isBuildVectorAllZeros(N1.getNode()))
4774 // do not return N1, because undef node may exist in N1
4775 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
4776 SDLoc(N), N1.getValueType());
4777
4778 // fold (and x, -1) -> x, vector edition
4779 if (ISD::isBuildVectorAllOnes(N0.getNode()))
4780 return N1;
4781 if (ISD::isBuildVectorAllOnes(N1.getNode()))
4782 return N0;
4783 }
4784
4785 // fold (and c1, c2) -> c1&c2
4786 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4787 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4788 if (N0C && N1C && !N1C->isOpaque())
4789 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
4790 // canonicalize constant to RHS
4791 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4792 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4793 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
4794 // fold (and x, -1) -> x
4795 if (isAllOnesConstant(N1))
4796 return N0;
4797 // if (and x, c) is known to be zero, return 0
4798 unsigned BitWidth = VT.getScalarSizeInBits();
4799 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4800 APInt::getAllOnesValue(BitWidth)))
4801 return DAG.getConstant(0, SDLoc(N), VT);
4802
4803 if (SDValue NewSel = foldBinOpIntoSelect(N))
4804 return NewSel;
4805
4806 // reassociate and
4807 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
4808 return RAND;
4809
4810 // Try to convert a constant mask AND into a shuffle clear mask.
4811 if (VT.isVector())
4812 if (SDValue Shuffle = XformToShuffleWithZero(N))
4813 return Shuffle;
4814
4815 // fold (and (or x, C), D) -> D if (C & D) == D
4816 auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
4817 return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
4818 };
4819 if (N0.getOpcode() == ISD::OR &&
4820 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
4821 return N1;
4822 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
4823 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4824 SDValue N0Op0 = N0.getOperand(0);
4825 APInt Mask = ~N1C->getAPIntValue();
4826 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
4827 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
4828 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4829 N0.getValueType(), N0Op0);
4830
4831 // Replace uses of the AND with uses of the Zero extend node.
4832 CombineTo(N, Zext);
4833
4834 // We actually want to replace all uses of the any_extend with the
4835 // zero_extend, to avoid duplicating things. This will later cause this
4836 // AND to be folded.
4837 CombineTo(N0.getNode(), Zext);
4838 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4839 }
4840 }
4841 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
4842 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
4843 // already be zero by virtue of the width of the base type of the load.
4844 //
4845 // the 'X' node here can either be nothing or an extract_vector_elt to catch
4846 // more cases.
4847 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4848 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
4849 N0.getOperand(0).getOpcode() == ISD::LOAD &&
4850 N0.getOperand(0).getResNo() == 0) ||
4851 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
4852 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
4853 N0 : N0.getOperand(0) );
4854
4855 // Get the constant (if applicable) the zero'th operand is being ANDed with.
4856 // This can be a pure constant or a vector splat, in which case we treat the
4857 // vector as a scalar and use the splat value.
4858 APInt Constant = APInt::getNullValue(1);
4859 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
4860 Constant = C->getAPIntValue();
4861 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
4862 APInt SplatValue, SplatUndef;
4863 unsigned SplatBitSize;
4864 bool HasAnyUndefs;
4865 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
4866 SplatBitSize, HasAnyUndefs);
4867 if (IsSplat) {
4868 // Undef bits can contribute to a possible optimisation if set, so
4869 // set them.
4870 SplatValue |= SplatUndef;
4871
4872 // The splat value may be something like "0x00FFFFFF", which means 0 for
4873 // the first vector value and FF for the rest, repeating. We need a mask
4874 // that will apply equally to all members of the vector, so AND all the
4875 // lanes of the constant together.
4876 EVT VT = Vector->getValueType(0);
4877 unsigned BitWidth = VT.getScalarSizeInBits();
4878
4879 // If the splat value has been compressed to a bitlength lower
4880 // than the size of the vector lane, we need to re-expand it to
4881 // the lane size.
4882 if (BitWidth > SplatBitSize)
4883 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
4884 SplatBitSize < BitWidth;
4885 SplatBitSize = SplatBitSize * 2)
4886 SplatValue |= SplatValue.shl(SplatBitSize);
4887
4888 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
4889 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
4890 if (SplatBitSize % BitWidth == 0) {
4891 Constant = APInt::getAllOnesValue(BitWidth);
4892 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
4893 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
4894 }
4895 }
4896 }
4897
4898 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
4899 // actually legal and isn't going to get expanded, else this is a false
4900 // optimisation.
4901 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
4902 Load->getValueType(0),
4903 Load->getMemoryVT());
4904
4905 // Resize the constant to the same size as the original memory access before
4906 // extension. If it is still the AllOnesValue then this AND is completely
4907 // unneeded.
4908 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
4909
4910 bool B;
4911 switch (Load->getExtensionType()) {
4912 default: B = false; break;
4913 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
4914 case ISD::ZEXTLOAD:
4915 case ISD::NON_EXTLOAD: B = true; break;
4916 }
4917
4918 if (B && Constant.isAllOnesValue()) {
4919 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
4920 // preserve semantics once we get rid of the AND.
4921 SDValue NewLoad(Load, 0);
4922
4923 // Fold the AND away. NewLoad may get replaced immediately.
4924 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
4925
4926 if (Load->getExtensionType() == ISD::EXTLOAD) {
4927 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
4928 Load->getValueType(0), SDLoc(Load),
4929 Load->getChain(), Load->getBasePtr(),
4930 Load->getOffset(), Load->getMemoryVT(),
4931 Load->getMemOperand());
4932 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
4933 if (Load->getNumValues() == 3) {
4934 // PRE/POST_INC loads have 3 values.
4935 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
4936 NewLoad.getValue(2) };
4937 CombineTo(Load, To, 3, true);
4938 } else {
4939 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
4940 }
4941 }
4942
4943 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4944 }
4945 }
4946
4947 // fold (and (load x), 255) -> (zextload x, i8)
4948 // fold (and (extload x, i16), 255) -> (zextload x, i8)
4949 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
4950 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
4951 (N0.getOpcode() == ISD::ANY_EXTEND &&
4952 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
4953 if (SDValue Res = ReduceLoadWidth(N)) {
4954 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
4955 ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
4956 AddToWorklist(N);
4957 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
4958 return SDValue(N, 0);
4959 }
4960 }
4961
4962 if (Level >= AfterLegalizeTypes) {
4963 // Attempt to propagate the AND back up to the leaves which, if they're
4964 // loads, can be combined to narrow loads and the AND node can be removed.
4965 // Perform after legalization so that extend nodes will already be
4966 // combined into the loads.
4967 if (BackwardsPropagateMask(N, DAG)) {
4968 return SDValue(N, 0);
4969 }
4970 }
4971
4972 if (SDValue Combined = visitANDLike(N0, N1, N))
4973 return Combined;
4974
4975 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
4976 if (N0.getOpcode() == N1.getOpcode())
4977 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
4978 return V;
4979
4980 // Masking the negated extension of a boolean is just the zero-extended
4981 // boolean:
4982 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
4983 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
4984 //
4985 // Note: the SimplifyDemandedBits fold below can make an information-losing
4986 // transform, and then we have no way to find this better fold.
4987 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
4988 if (isNullOrNullSplat(N0.getOperand(0))) {
4989 SDValue SubRHS = N0.getOperand(1);
4990 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
4991 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
4992 return SubRHS;
4993 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
4994 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
4995 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
4996 }
4997 }
4998
4999 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5000 // fold (and (sra)) -> (and (srl)) when possible.
5001 if (SimplifyDemandedBits(SDValue(N, 0)))
5002 return SDValue(N, 0);
5003
5004 // fold (zext_inreg (extload x)) -> (zextload x)
5005 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
5006 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5007 EVT MemVT = LN0->getMemoryVT();
5008 // If we zero all the possible extended bits, then we can turn this into
5009 // a zextload if we are running before legalize or the operation is legal.
5010 unsigned BitWidth = N1.getScalarValueSizeInBits();
5011 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
5012 BitWidth - MemVT.getScalarSizeInBits())) &&
5013 ((!LegalOperations && !LN0->isVolatile()) ||
5014 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5015 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
5016 LN0->getChain(), LN0->getBasePtr(),
5017 MemVT, LN0->getMemOperand());
5018 AddToWorklist(N);
5019 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5020 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5021 }
5022 }
5023 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
5024 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5025 N0.hasOneUse()) {
5026 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5027 EVT MemVT = LN0->getMemoryVT();
5028 // If we zero all the possible extended bits, then we can turn this into
5029 // a zextload if we are running before legalize or the operation is legal.
5030 unsigned BitWidth = N1.getScalarValueSizeInBits();
5031 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
5032 BitWidth - MemVT.getScalarSizeInBits())) &&
5033 ((!LegalOperations && !LN0->isVolatile()) ||
5034 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5035 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
5036 LN0->getChain(), LN0->getBasePtr(),
5037 MemVT, LN0->getMemOperand());
5038 AddToWorklist(N);
5039 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5040 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5041 }
5042 }
5043 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
5044 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5045 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5046 N0.getOperand(1), false))
5047 return BSwap;
5048 }
5049
5050 if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
5051 return Shifts;
5052
5053 return SDValue();
5054}
5055
5056/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5057SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
5058 bool DemandHighBits) {
5059 if (!LegalOperations)
5060 return SDValue();
5061
5062 EVT VT = N->getValueType(0);
5063 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5064 return SDValue();
5065 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5066 return SDValue();
5067
5068 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
5069 bool LookPassAnd0 = false;
5070 bool LookPassAnd1 = false;
5071 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5072 std::swap(N0, N1);
5073 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5074 std::swap(N0, N1);
5075 if (N0.getOpcode() == ISD::AND) {
5076 if (!N0.getNode()->hasOneUse())
5077 return SDValue();
5078 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5079 // Also handle 0xffff since the LHS is guaranteed to have zeros there.
5080 // This is needed for X86.
5081 if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
5082 N01C->getZExtValue() != 0xFFFF))
5083 return SDValue();
5084 N0 = N0.getOperand(0);
5085 LookPassAnd0 = true;
5086 }
5087
5088 if (N1.getOpcode() == ISD::AND) {
5089 if (!N1.getNode()->hasOneUse())
5090 return SDValue();
5091 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5092 if (!N11C || N11C->getZExtValue() != 0xFF)
5093 return SDValue();
5094 N1 = N1.getOperand(0);
5095 LookPassAnd1 = true;
5096 }
5097
5098 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5099 std::swap(N0, N1);
5100 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5101 return SDValue();
5102 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
5103 return SDValue();
5104
5105 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5106 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5107 if (!N01C || !N11C)
5108 return SDValue();
5109 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
5110 return SDValue();
5111
5112 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
5113 SDValue N00 = N0->getOperand(0);
5114 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5115 if (!N00.getNode()->hasOneUse())
5116 return SDValue();
5117 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
5118 if (!N001C || N001C->getZExtValue() != 0xFF)
5119 return SDValue();
5120 N00 = N00.getOperand(0);
5121 LookPassAnd0 = true;
5122 }
5123
5124 SDValue N10 = N1->getOperand(0);
5125 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5126 if (!N10.getNode()->hasOneUse())
5127 return SDValue();
5128 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
5129 // Also allow 0xFFFF since the bits will be shifted out. This is needed
5130 // for X86.
5131 if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
5132 N101C->getZExtValue() != 0xFFFF))
5133 return SDValue();
5134 N10 = N10.getOperand(0);
5135 LookPassAnd1 = true;
5136 }
5137
5138 if (N00 != N10)
5139 return SDValue();
5140
5141 // Make sure everything beyond the low halfword gets set to zero since the SRL
5142 // 16 will clear the top bits.
5143 unsigned OpSizeInBits = VT.getSizeInBits();
5144 if (DemandHighBits && OpSizeInBits > 16) {
5145 // If the left-shift isn't masked out then the only way this is a bswap is
5146 // if all bits beyond the low 8 are 0. In that case the entire pattern
5147 // reduces to a left shift anyway: leave it for other parts of the combiner.
5148 if (!LookPassAnd0)
5149 return SDValue();
5150
5151 // However, if the right shift isn't masked out then it might be because
5152 // it's not needed. See if we can spot that too.
5153 if (!LookPassAnd1 &&
5154 !DAG.MaskedValueIsZero(
5155 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
5156 return SDValue();
5157 }
5158
5159 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
5160 if (OpSizeInBits > 16) {
5161 SDLoc DL(N);
5162 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
5163 DAG.getConstant(OpSizeInBits - 16, DL,
5164 getShiftAmountTy(VT)));
5165 }
5166 return Res;
5167}
5168
5169/// Return true if the specified node is an element that makes up a 32-bit
5170/// packed halfword byteswap.
5171/// ((x & 0x000000ff) << 8) |
5172/// ((x & 0x0000ff00) >> 8) |
5173/// ((x & 0x00ff0000) << 8) |
5174/// ((x & 0xff000000) >> 8)
5175static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
5176 if (!N.getNode()->hasOneUse())
5177 return false;
5178
5179 unsigned Opc = N.getOpcode();
5180 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5181 return false;
5182
5183 SDValue N0 = N.getOperand(0);
5184 unsigned Opc0 = N0.getOpcode();
5185 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5186 return false;
5187
5188 ConstantSDNode *N1C = nullptr;
5189 // SHL or SRL: look upstream for AND mask operand
5190 if (Opc == ISD::AND)
5191 N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5192 else if (Opc0 == ISD::AND)
5193 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5194 if (!N1C)
5195 return false;
5196
5197 unsigned MaskByteOffset;
5198 switch (N1C->getZExtValue()) {
5199 default:
5200 return false;
5201 case 0xFF: MaskByteOffset = 0; break;
5202 case 0xFF00: MaskByteOffset = 1; break;
5203 case 0xFFFF:
5204 // In case demanded bits didn't clear the bits that will be shifted out.
5205 // This is needed for X86.
5206 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5207 MaskByteOffset = 1;
5208 break;
5209 }
5210 return false;
5211 case 0xFF0000: MaskByteOffset = 2; break;
5212 case 0xFF000000: MaskByteOffset = 3; break;
5213 }
5214
5215 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
5216 if (Opc == ISD::AND) {
5217 if (MaskByteOffset == 0 || MaskByteOffset == 2) {
5218 // (x >> 8) & 0xff
5219 // (x >> 8) & 0xff0000
5220 if (Opc0 != ISD::SRL)
5221 return false;
5222 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5223 if (!C || C->getZExtValue() != 8)
5224 return false;
5225 } else {
5226 // (x << 8) & 0xff00
5227 // (x << 8) & 0xff000000
5228 if (Opc0 != ISD::SHL)
5229 return false;
5230 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5231 if (!C || C->getZExtValue() != 8)
5232 return false;
5233 }
5234 } else if (Opc == ISD::SHL) {
5235 // (x & 0xff) << 8
5236 // (x & 0xff0000) << 8
5237 if (MaskByteOffset != 0 && MaskByteOffset != 2)
5238 return false;
5239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5240 if (!C || C->getZExtValue() != 8)
5241 return false;
5242 } else { // Opc == ISD::SRL
5243 // (x & 0xff00) >> 8
5244 // (x & 0xff000000) >> 8
5245 if (MaskByteOffset != 1 && MaskByteOffset != 3)
5246 return false;
5247 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5248 if (!C || C->getZExtValue() != 8)
5249 return false;
5250 }
5251
5252 if (Parts[MaskByteOffset])
5253 return false;
5254
5255 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
5256 return true;
5257}
5258
5259/// Match a 32-bit packed halfword bswap. That is
5260/// ((x & 0x000000ff) << 8) |
5261/// ((x & 0x0000ff00) >> 8) |
5262/// ((x & 0x00ff0000) << 8) |
5263/// ((x & 0xff000000) >> 8)
5264/// => (rotl (bswap x), 16)
5265SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
5266 if (!LegalOperations)
5267 return SDValue();
5268
5269 EVT VT = N->getValueType(0);
5270 if (VT != MVT::i32)
5271 return SDValue();
5272 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5273 return SDValue();
5274
5275 // Look for either
5276 // (or (or (and), (and)), (or (and), (and)))
5277 // (or (or (or (and), (and)), (and)), (and))
5278 if (N0.getOpcode() != ISD::OR)
5279 return SDValue();
5280 SDValue N00 = N0.getOperand(0);
5281 SDValue N01 = N0.getOperand(1);
5282 SDNode *Parts[4] = {};
5283
5284 if (N1.getOpcode() == ISD::OR &&
5285 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
5286 // (or (or (and), (and)), (or (and), (and)))
5287 if (!isBSwapHWordElement(N00, Parts))
5288 return SDValue();
5289
5290 if (!isBSwapHWordElement(N01, Parts))
5291 return SDValue();
5292 SDValue N10 = N1.getOperand(0);
5293 if (!isBSwapHWordElement(N10, Parts))
5294 return SDValue();
5295 SDValue N11 = N1.getOperand(1);
5296 if (!isBSwapHWordElement(N11, Parts))
5297 return SDValue();
5298 } else {
5299 // (or (or (or (and), (and)), (and)), (and))
5300 if (!isBSwapHWordElement(N1, Parts))
5301 return SDValue();
5302 if (!isBSwapHWordElement(N01, Parts))
5303 return SDValue();
5304 if (N00.getOpcode() != ISD::OR)
5305 return SDValue();
5306 SDValue N000 = N00.getOperand(0);
5307 if (!isBSwapHWordElement(N000, Parts))
5308 return SDValue();
5309 SDValue N001 = N00.getOperand(1);
5310 if (!isBSwapHWordElement(N001, Parts))
5311 return SDValue();
5312 }
5313
5314 // Make sure the parts are all coming from the same node.
5315 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
5316 return SDValue();
5317
5318 SDLoc DL(N);
5319 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
5320 SDValue(Parts[0], 0));
5321
5322 // Result of the bswap should be rotated by 16. If it's not legal, then
5323 // do (x << 16) | (x >> 16).
5324 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
5325 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
5326 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
5327 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5328 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5329 return DAG.getNode(ISD::OR, DL, VT,
5330 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
5331 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
5332}
5333
5334/// This contains all DAGCombine rules which reduce two values combined by
5335/// an Or operation to a single value \see visitANDLike().
5336SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
5337 EVT VT = N1.getValueType();
5338 SDLoc DL(N);
5339
5340 // fold (or x, undef) -> -1
5341 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
5342 return DAG.getAllOnesConstant(DL, VT);
5343
5344 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
5345 return V;
5346
5347 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
5348 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5349 // Don't increase # computations.
5350 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5351 // We can only do this xform if we know that bits from X that are set in C2
5352 // but not in C1 are already zero. Likewise for Y.
5353 if (const ConstantSDNode *N0O1C =
5354 getAsNonOpaqueConstant(N0.getOperand(1))) {
5355 if (const ConstantSDNode *N1O1C =
5356 getAsNonOpaqueConstant(N1.getOperand(1))) {
5357 // We can only do this xform if we know that bits from X that are set in
5358 // C2 but not in C1 are already zero. Likewise for Y.
5359 const APInt &LHSMask = N0O1C->getAPIntValue();
5360 const APInt &RHSMask = N1O1C->getAPIntValue();
5361
5362 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
5363 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
5364 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5365 N0.getOperand(0), N1.getOperand(0));
5366 return DAG.getNode(ISD::AND, DL, VT, X,
5367 DAG.getConstant(LHSMask | RHSMask, DL, VT));
5368 }
5369 }
5370 }
5371 }
5372
5373 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
5374 if (N0.getOpcode() == ISD::AND &&
5375 N1.getOpcode() == ISD::AND &&
5376 N0.getOperand(0) == N1.getOperand(0) &&
5377 // Don't increase # computations.
5378 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5379 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5380 N0.getOperand(1), N1.getOperand(1));
5381 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
5382 }
5383
5384 return SDValue();
5385}
5386
5387/// OR combines for which the commuted variant will be tried as well.
5388static SDValue visitORCommutative(
5389 SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) {
5390 EVT VT = N0.getValueType();
5391 if (N0.getOpcode() == ISD::AND) {
5392 // fold (or (and X, (xor Y, -1)), Y) -> (or X, Y)
5393 if (isBitwiseNot(N0.getOperand(1)) && N0.getOperand(1).getOperand(0) == N1)
5394 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
5395
5396 // fold (or (and (xor Y, -1), X), Y) -> (or X, Y)
5397 if (isBitwiseNot(N0.getOperand(0)) && N0.getOperand(0).getOperand(0) == N1)
5398 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(1), N1);
5399 }
5400
5401 return SDValue();
5402}
5403
5404SDValue DAGCombiner::visitOR(SDNode *N) {
5405 SDValue N0 = N->getOperand(0);
5406 SDValue N1 = N->getOperand(1);
5407 EVT VT = N1.getValueType();
5408
5409 // x | x --> x
5410 if (N0 == N1)
5411 return N0;
5412
5413 // fold vector ops
5414 if (VT.isVector()) {
5415 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5416 return FoldedVOp;
5417
5418 // fold (or x, 0) -> x, vector edition
5419 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5420 return N1;
5421 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5422 return N0;
5423
5424 // fold (or x, -1) -> -1, vector edition
5425 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5426 // do not return N0, because undef node may exist in N0
5427 return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
5428 if (ISD::isBuildVectorAllOnes(N1.getNode()))
5429 // do not return N1, because undef node may exist in N1
5430 return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
5431
5432 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
5433 // Do this only if the resulting shuffle is legal.
5434 if (isa<ShuffleVectorSDNode>(N0) &&
5435 isa<ShuffleVectorSDNode>(N1) &&
5436 // Avoid folding a node with illegal type.
5437 TLI.isTypeLegal(VT)) {
5438 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
5439 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
5440 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5441 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode());
5442 // Ensure both shuffles have a zero input.
5443 if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) {
5444 assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!")(((!ZeroN00 || !ZeroN01) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN00 || !ZeroN01) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5444, __PRETTY_FUNCTION__))
;
5445 assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!")(((!ZeroN10 || !ZeroN11) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN10 || !ZeroN11) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5445, __PRETTY_FUNCTION__))
;
5446 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
5447 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
5448 bool CanFold = true;
5449 int NumElts = VT.getVectorNumElements();
5450 SmallVector<int, 4> Mask(NumElts);
5451
5452 for (int i = 0; i != NumElts; ++i) {
5453 int M0 = SV0->getMaskElt(i);
5454 int M1 = SV1->getMaskElt(i);
5455
5456 // Determine if either index is pointing to a zero vector.
5457 bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts));
5458 bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts));
5459
5460 // If one element is zero and the otherside is undef, keep undef.
5461 // This also handles the case that both are undef.
5462 if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) {
5463 Mask[i] = -1;
5464 continue;
5465 }
5466
5467 // Make sure only one of the elements is zero.
5468 if (M0Zero == M1Zero) {
5469 CanFold = false;
5470 break;
5471 }
5472
5473 assert((M0 >= 0 || M1 >= 0) && "Undef index!")(((M0 >= 0 || M1 >= 0) && "Undef index!") ? static_cast
<void> (0) : __assert_fail ("(M0 >= 0 || M1 >= 0) && \"Undef index!\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5473, __PRETTY_FUNCTION__))
;
5474
5475 // We have a zero and non-zero element. If the non-zero came from
5476 // SV0 make the index a LHS index. If it came from SV1, make it
5477 // a RHS index. We need to mod by NumElts because we don't care
5478 // which operand it came from in the original shuffles.
5479 Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts;
5480 }
5481
5482 if (CanFold) {
5483 SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
5484 SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0);
5485
5486 bool LegalMask = TLI.isShuffleMaskLegal(Mask, VT);
5487 if (!LegalMask) {
5488 std::swap(NewLHS, NewRHS);
5489 ShuffleVectorSDNode::commuteMask(Mask);
5490 LegalMask = TLI.isShuffleMaskLegal(Mask, VT);
5491 }
5492
5493 if (LegalMask)
5494 return DAG.getVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS, Mask);
5495 }
5496 }
5497 }
5498 }
5499
5500 // fold (or c1, c2) -> c1|c2
5501 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
5502 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5503 if (N0C && N1C && !N1C->isOpaque())
5504 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
5505 // canonicalize constant to RHS
5506 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5507 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5508 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
5509 // fold (or x, 0) -> x
5510 if (isNullConstant(N1))
5511 return N0;
5512 // fold (or x, -1) -> -1
5513 if (isAllOnesConstant(N1))
5514 return N1;
5515
5516 if (SDValue NewSel = foldBinOpIntoSelect(N))
5517 return NewSel;
5518
5519 // fold (or x, c) -> c iff (x & ~c) == 0
5520 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
5521 return N1;
5522
5523 if (SDValue Combined = visitORLike(N0, N1, N))
5524 return Combined;
5525
5526 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
5527 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
5528 return BSwap;
5529 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
5530 return BSwap;
5531
5532 // reassociate or
5533 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
5534 return ROR;
5535
5536 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
5537 // iff (c1 & c2) != 0 or c1/c2 are undef.
5538 auto MatchIntersect = [](ConstantSDNode *C1, ConstantSDNode *C2) {
5539 return !C1 || !C2 || C1->getAPIntValue().intersects(C2->getAPIntValue());
5540 };
5541 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
5542 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) {
5543 if (SDValue COR = DAG.FoldConstantArithmetic(
5544 ISD::OR, SDLoc(N1), VT, N1.getNode(), N0.getOperand(1).getNode())) {
5545 SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
5546 AddToWorklist(IOR.getNode());
5547 return DAG.getNode(ISD::AND, SDLoc(N), VT, COR, IOR);
5548 }
5549 }
5550
5551 if (SDValue Combined = visitORCommutative(DAG, N0, N1, N))
5552 return Combined;
5553 if (SDValue Combined = visitORCommutative(DAG, N1, N0, N))
5554 return Combined;
5555
5556 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
5557 if (N0.getOpcode() == N1.getOpcode())
5558 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5559 return V;
5560
5561 // See if this is some rotate idiom.
5562 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
5563 return SDValue(Rot, 0);
5564
5565 if (SDValue Load = MatchLoadCombine(N))
5566 return Load;
5567
5568 // Simplify the operands using demanded-bits information.
5569 if (SimplifyDemandedBits(SDValue(N, 0)))
5570 return SDValue(N, 0);
5571
5572 // If OR can be rewritten into ADD, try combines based on ADD.
5573 if ((!LegalOperations || TLI.isOperationLegal(ISD::ADD, VT)) &&
5574 DAG.haveNoCommonBitsSet(N0, N1))
5575 if (SDValue Combined = visitADDLike(N))
5576 return Combined;
5577
5578 return SDValue();
5579}
5580
5581static SDValue stripConstantMask(SelectionDAG &DAG, SDValue Op, SDValue &Mask) {
5582 if (Op.getOpcode() == ISD::AND &&
5583 DAG.isConstantIntBuildVectorOrConstantInt(Op.getOperand(1))) {
5584 Mask = Op.getOperand(1);
5585 return Op.getOperand(0);
5586 }
5587 return Op;
5588}
5589
5590/// Match "(X shl/srl V1) & V2" where V2 may not be present.
5591static bool matchRotateHalf(SelectionDAG &DAG, SDValue Op, SDValue &Shift,
5592 SDValue &Mask) {
5593 Op = stripConstantMask(DAG, Op, Mask);
5594 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
5595 Shift = Op;
5596 return true;
5597 }
5598 return false;
5599}
5600
5601/// Helper function for visitOR to extract the needed side of a rotate idiom
5602/// from a shl/srl/mul/udiv. This is meant to handle cases where
5603/// InstCombine merged some outside op with one of the shifts from
5604/// the rotate pattern.
5605/// \returns An empty \c SDValue if the needed shift couldn't be extracted.
5606/// Otherwise, returns an expansion of \p ExtractFrom based on the following
5607/// patterns:
5608///
5609/// (or (mul v c0) (shrl (mul v c1) c2)):
5610/// expands (mul v c0) -> (shl (mul v c1) c3)
5611///
5612/// (or (udiv v c0) (shl (udiv v c1) c2)):
5613/// expands (udiv v c0) -> (shrl (udiv v c1) c3)
5614///
5615/// (or (shl v c0) (shrl (shl v c1) c2)):
5616/// expands (shl v c0) -> (shl (shl v c1) c3)
5617///
5618/// (or (shrl v c0) (shl (shrl v c1) c2)):
5619/// expands (shrl v c0) -> (shrl (shrl v c1) c3)
5620///
5621/// Such that in all cases, c3+c2==bitwidth(op v c1).
5622static SDValue extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift,
5623 SDValue ExtractFrom, SDValue &Mask,
5624 const SDLoc &DL) {
5625 assert(OppShift && ExtractFrom && "Empty SDValue")((OppShift && ExtractFrom && "Empty SDValue")
? static_cast<void> (0) : __assert_fail ("OppShift && ExtractFrom && \"Empty SDValue\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5625, __PRETTY_FUNCTION__))
;
5626 assert((((OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() ==
ISD::SRL) && "Existing shift must be valid as a rotate half"
) ? static_cast<void> (0) : __assert_fail ("(OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && \"Existing shift must be valid as a rotate half\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5628, __PRETTY_FUNCTION__))
5627 (OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) &&(((OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() ==
ISD::SRL) && "Existing shift must be valid as a rotate half"
) ? static_cast<void> (0) : __assert_fail ("(OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && \"Existing shift must be valid as a rotate half\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5628, __PRETTY_FUNCTION__))
5628 "Existing shift must be valid as a rotate half")(((OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() ==
ISD::SRL) && "Existing shift must be valid as a rotate half"
) ? static_cast<void> (0) : __assert_fail ("(OppShift.getOpcode() == ISD::SHL || OppShift.getOpcode() == ISD::SRL) && \"Existing shift must be valid as a rotate half\""
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5628, __PRETTY_FUNCTION__))
;
5629
5630 ExtractFrom = stripConstantMask(DAG, ExtractFrom, Mask);
5631 // Preconditions:
5632 // (or (op0 v c0) (shiftl/r (op0 v c1) c2))
5633 //
5634 // Find opcode of the needed shift to be extracted from (op0 v c0).
5635 unsigned Opcode = ISD::DELETED_NODE;
5636 bool IsMulOrDiv = false;
5637 // Set Opcode and IsMulOrDiv if the extract opcode matches the needed shift
5638 // opcode or its arithmetic (mul or udiv) variant.
5639 auto SelectOpcode = [&](unsigned NeededShift, unsigned MulOrDivVariant) {
5640 IsMulOrDiv = ExtractFrom.getOpcode() == MulOrDivVariant;
5641 if (!IsMulOrDiv && ExtractFrom.getOpcode() != NeededShift)
5642 return false;
5643 Opcode = NeededShift;
5644 return true;
5645 };
5646 // op0 must be either the needed shift opcode or the mul/udiv equivalent
5647 // that the needed shift can be extracted from.
5648 if ((OppShift.getOpcode() != ISD::SRL || !SelectOpcode(ISD::SHL, ISD::MUL)) &&
5649 (OppShift.getOpcode() != ISD::SHL || !SelectOpcode(ISD::SRL, ISD::UDIV)))
5650 return SDValue();
5651
5652 // op0 must be the same opcode on both sides, have the same LHS argument,
5653 // and produce the same value type.
5654 SDValue OppShiftLHS = OppShift.getOperand(0);
5655 EVT ShiftedVT = OppShiftLHS.getValueType();
5656 if (OppShiftLHS.getOpcode() != ExtractFrom.getOpcode() ||
5657 OppShiftLHS.getOperand(0) != ExtractFrom.getOperand(0) ||
5658 ShiftedVT != ExtractFrom.getValueType())
5659 return SDValue();
5660
5661 // Amount of the existing shift.
5662 ConstantSDNode *OppShiftCst = isConstOrConstSplat(OppShift.getOperand(1));
5663 // Constant mul/udiv/shift amount from the RHS of the shift's LHS op.
5664 ConstantSDNode *OppLHSCst = isConstOrConstSplat(OppShiftLHS.getOperand(1));
5665 // Constant mul/udiv/shift amount from the RHS of the ExtractFrom op.
5666 ConstantSDNode *ExtractFromCst =
5667 isConstOrConstSplat(ExtractFrom.getOperand(1));
5668 // TODO: We should be able to handle non-uniform constant vectors for these values
5669 // Check that we have constant values.
5670 if (!OppShiftCst || !OppShiftCst->getAPIntValue() ||
5671 !OppLHSCst || !OppLHSCst->getAPIntValue() ||
5672 !ExtractFromCst || !ExtractFromCst->getAPIntValue())
5673 return SDValue();
5674
5675 // Compute the shift amount we need to extract to complete the rotate.
5676 const unsigned VTWidth = ShiftedVT.getScalarSizeInBits();
5677 if (OppShiftCst->getAPIntValue().ugt(VTWidth))
5678 return SDValue();
5679 APInt NeededShiftAmt = VTWidth - OppShiftCst->getAPIntValue();
5680 // Normalize the bitwidth of the two mul/udiv/shift constant operands.
5681 APInt ExtractFromAmt = ExtractFromCst->getAPIntValue();
5682 APInt OppLHSAmt = OppLHSCst->getAPIntValue();
5683 zeroExtendToMatch(ExtractFromAmt, OppLHSAmt);
5684
5685 // Now try extract the needed shift from the ExtractFrom op and see if the
5686 // result matches up with the existing shift's LHS op.
5687 if (IsMulOrDiv) {
5688 // Op to extract from is a mul or udiv by a constant.
5689 // Check:
5690 // c2 / (1 << (bitwidth(op0 v c0) - c1)) == c0
5691 // c2 % (1 << (bitwidth(op0 v c0) - c1)) == 0
5692 const APInt ExtractDiv = APInt::getOneBitSet(ExtractFromAmt.getBitWidth(),
5693 NeededShiftAmt.getZExtValue());
5694 APInt ResultAmt;
5695 APInt Rem;
5696 APInt::udivrem(ExtractFromAmt, ExtractDiv, ResultAmt, Rem);
5697 if (Rem != 0 || ResultAmt != OppLHSAmt)
5698 return SDValue();
5699 } else {
5700 // Op to extract from is a shift by a constant.
5701 // Check:
5702 // c2 - (bitwidth(op0 v c0) - c1) == c0
5703 if (OppLHSAmt != ExtractFromAmt - NeededShiftAmt.zextOrTrunc(
5704 ExtractFromAmt.getBitWidth()))
5705 return SDValue();
5706 }
5707
5708 // Return the expanded shift op that should allow a rotate to be formed.
5709 EVT ShiftVT = OppShift.getOperand(1).getValueType();
5710 EVT ResVT = ExtractFrom.getValueType();
5711 SDValue NewShiftNode = DAG.getConstant(NeededShiftAmt, DL, ShiftVT);
5712 return DAG.getNode(Opcode, DL, ResVT, OppShiftLHS, NewShiftNode);
5713}
5714
5715// Return true if we can prove that, whenever Neg and Pos are both in the
5716// range [0, EltSize), Neg == (Pos == 0 ? 0 : EltSize - Pos). This means that
5717// for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
5718//
5719// (or (shift1 X, Neg), (shift2 X, Pos))
5720//
5721// reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
5722// in direction shift1 by Neg. The range [0, EltSize) means that we only need
5723// to consider shift amounts with defined behavior.
5724static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize,
5725 SelectionDAG &DAG) {
5726 // If EltSize is a power of 2 then:
5727 //
5728 // (a) (Pos == 0 ? 0 : EltSize - Pos) == (EltSize - Pos) & (EltSize - 1)
5729 // (b) Neg == Neg & (EltSize - 1) whenever Neg is in [0, EltSize).
5730 //
5731 // So if EltSize is a power of 2 and Neg is (and Neg', EltSize-1), we check
5732 // for the stronger condition:
5733 //
5734 // Neg & (EltSize - 1) == (EltSize - Pos) & (EltSize - 1) [A]
5735 //
5736 // for all Neg and Pos. Since Neg & (EltSize - 1) == Neg' & (EltSize - 1)
5737 // we can just replace Neg with Neg' for the rest of the function.
5738 //
5739 // In other cases we check for the even stronger condition:
5740 //
5741 // Neg == EltSize - Pos [B]
5742 //
5743 // for all Neg and Pos. Note that the (or ...) then invokes undefined
5744 // behavior if Pos == 0 (and consequently Neg == EltSize).
5745 //
5746 // We could actually use [A] whenever EltSize is a power of 2, but the
5747 // only extra cases that it would match are those uninteresting ones
5748 // where Neg and Pos are never in range at the same time. E.g. for
5749 // EltSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
5750 // as well as (sub 32, Pos), but:
5751 //
5752 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
5753 //
5754 // always invokes undefined behavior for 32-bit X.
5755 //
5756 // Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise.
5757 unsigned MaskLoBits = 0;
5758 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
5759 if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
5760 KnownBits Known = DAG.computeKnownBits(Neg.getOperand(0));
5761 unsigned Bits = Log2_64(EltSize);
5762 if (NegC->getAPIntValue().getActiveBits() <= Bits &&
5763 ((NegC->getAPIntValue() | Known.Zero).countTrailingOnes() >= Bits)) {
5764 Neg = Neg.getOperand(0);
5765 MaskLoBits = Bits;
5766 }
5767 }
5768 }
5769
5770 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
5771 if (Neg.getOpcode() != ISD::SUB)
5772 return false;
5773 ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0));
5774 if (!NegC)
5775 return false;
5776 SDValue NegOp1 = Neg.getOperand(1);
5777
5778 // On the RHS of [A], if Pos is Pos' & (EltSize - 1), just replace Pos with
5779 // Pos'. The truncation is redundant for the purpose of the equality.
5780 if (MaskLoBits && Pos.getOpcode() == ISD::AND) {
5781 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1))) {
5782 KnownBits Known = DAG.computeKnownBits(Pos.getOperand(0));
5783 if (PosC->getAPIntValue().getActiveBits() <= MaskLoBits &&
5784 ((PosC->getAPIntValue() | Known.Zero).countTrailingOnes() >=
5785 MaskLoBits))
5786 Pos = Pos.getOperand(0);
5787 }
5788 }
5789
5790 // The condition we need is now:
5791 //
5792 // (NegC - NegOp1) & Mask == (EltSize - Pos) & Mask
5793 //
5794 // If NegOp1 == Pos then we need:
5795 //
5796 // EltSize & Mask == NegC & Mask
5797 //
5798 // (because "x & Mask" is a truncation and distributes through subtraction).
5799 APInt Width;
5800 if (Pos == NegOp1)
5801 Width = NegC->getAPIntValue();
5802
5803 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
5804 // Then the condition we want to prove becomes:
5805 //
5806 // (NegC - NegOp1) & Mask == (EltSize - (NegOp1 + PosC)) & Mask
5807 //
5808 // which, again because "x & Mask" is a truncation, becomes:
5809 //
5810 // NegC & Mask == (EltSize - PosC) & Mask
5811 // EltSize & Mask == (NegC + PosC) & Mask
5812 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
5813 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
5814 Width = PosC->getAPIntValue() + NegC->getAPIntValue();
5815 else
5816 return false;
5817 } else
5818 return false;
5819
5820 // Now we just need to check that EltSize & Mask == Width & Mask.
5821 if (MaskLoBits)
5822 // EltSize & Mask is 0 since Mask is EltSize - 1.
5823 return Width.getLoBits(MaskLoBits) == 0;
5824 return Width == EltSize;
5825}
5826
5827// A subroutine of MatchRotate used once we have found an OR of two opposite
5828// shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
5829// to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
5830// former being preferred if supported. InnerPos and InnerNeg are Pos and
5831// Neg with outer conversions stripped away.
5832SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
5833 SDValue Neg, SDValue InnerPos,
5834 SDValue InnerNeg, unsigned PosOpcode,
5835 unsigned NegOpcode, const SDLoc &DL) {
5836 // fold (or (shl x, (*ext y)),
5837 // (srl x, (*ext (sub 32, y)))) ->
5838 // (rotl x, y) or (rotr x, (sub 32, y))
5839 //
5840 // fold (or (shl x, (*ext (sub 32, y))),
5841 // (srl x, (*ext y))) ->
5842 // (rotr x, y) or (rotl x, (sub 32, y))
5843 EVT VT = Shifted.getValueType();
5844 if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits(), DAG)) {
5845 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
5846 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
5847 HasPos ? Pos : Neg).getNode();
5848 }
5849
5850 return nullptr;
5851}
5852
5853// MatchRotate - Handle an 'or' of two operands. If this is one of the many
5854// idioms for rotate, and if the target supports rotation instructions, generate
5855// a rot[lr].
5856SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
5857 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
5858 EVT VT = LHS.getValueType();
5859 if (!TLI.isTypeLegal(VT)) return nullptr;
5860
5861 // The target must have at least one rotate flavor.
5862 bool HasROTL = hasOperation(ISD::ROTL, VT);
5863 bool HasROTR = hasOperation(ISD::ROTR, VT);
5864 if (!HasROTL && !HasROTR) return nullptr;
5865
5866 // Check for truncated rotate.
5867 if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE &&
5868 LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()) {
5869 assert(LHS.getValueType() == RHS.getValueType())((LHS.getValueType() == RHS.getValueType()) ? static_cast<
void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType()"
, "/build/llvm-toolchain-snapshot-9~svn361465/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5869, __PRETTY_FUNCTION__))
;
5870 if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
5871 return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(),
5872 SDValue(Rot, 0)).getNode();
5873 }
5874 }
5875
5876 // Match "(X shl/srl V1) & V2" where V2 may not be present.
5877 SDValue LHSShift; // The shift.
5878 SDValue LHSMask; // AND value if any.
5879 matchRotateHalf(DAG, LHS, LHSShift, LHSMask);
5880
5881 SDValue RHSShift; // The shift.
5882 SDValue RHSMask; // AND value if any.
5883 matchRotateHalf(DAG, RHS, RHSShift, RHSMask);
5884
5885 // If neither side matched a rotate half, bail
5886 if (!LHSShift && !RHSShift)
5887 return nullptr;
5888
5889 // InstCombine may have combined a constant shl, srl, mul, or udiv with one
5890 // side of the rotate, so try to handle that here. In all cases we need to
5891 // pass the matched shift from the opposite side to compute the opcode and
5892 // needed shift amount to extract. We still want to do this if both sides
5893 // matched a rotate half because one half may be a potential overshift that
5894 // can be broken down (ie if InstCombine merged two shl or srl ops into a
5895 // single one).
5896
5897 // Have LHS side of the rotate, try to extract the needed shift from the RHS.
5898 if (LHSShift)
5899 if (SDValue NewRHSShift =
5900 extractShiftForRotate(DAG, LHSShift, RHS, RHSMask, DL))
5901 RHSShift = NewRHSShift;
5902 // Have RHS side of the rotate, try to extract the needed shift from the LHS.
5903 if (RHSShift)
5904 if (SDValue NewLHSShift =
5905 extractShiftForRotate(DAG, RHSShift, LHS, LHSMask, DL))
5906 LHSShift = NewLHSShift;
5907
5908 // If a side is still missing, nothing else we can do.
5909 if (!RHSShift || !LHSShift)
5910 return nullptr;
5911
5912 // At this point we've matched or extracted a shift op on each side.
5913
5914 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
5915 return nullptr; // Not shifting the same value.
5916
5917 if (LHSShift.getOpcode() == RHSShift.getOpcode())
5918 return nullptr; // Shifts must disagree.
5919
5920 // Canonicalize shl to left side in a shl/srl pair.
5921 if (RHSShift.getOpcode() == ISD::SHL) {
5922 std::swap(LHS, RHS);
5923 std::swap(LHSShift, RHSShift);
5924 std::swap(LHSMask, RHSMask);
5925 }
5926
5927 unsigned EltSizeInBits = VT.getScalarSizeInBits();
5928 SDValue LHSShiftArg = LHSShift.getOperand(0);
5929 SDValue LHSShiftAmt = LHSShift.getOperand(1);
5930 SDValue RHSShiftArg = RHSShift.getOperand(0);
5931 SDValue RHSShiftAmt = RHSShift.getOperand(1);
5932
5933 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
5934 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
5935 auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS,
5936 ConstantSDNode *RHS) {
5937 return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits;
5938 };
5939 if (ISD::matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) {
5940 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
5941 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
5942
5943 // If there is an AND of either shifted operand, apply it to the result.
5944 if (LHSMask.getNode() || RHSMask.getNode()) {
5945 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
5946 SDValue Mask = AllOnes;
5947
5948 if (LHSMask.getNode()) {
5949 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt);
5950 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
5951 DAG.getNode(ISD::OR, DL, VT, LHSMask, RHSBits));
5952 }
5953 if (RHSMask.getNode()) {
5954 SDValue LHSBits = DAG.getNode(ISD::SHL, DL, VT, AllOnes, LHSShiftAmt);
5955 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
5956 DAG.getNode(ISD::OR, DL, VT, RHSMask, LHSBits));
5957 }
5958
5959 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, Mask);
5960 }
5961
5962 return Rot.getNode();
5963 }
5964
5965 // If there is a mask here, and we have a variable shift, we can't be sure
5966 // that we're masking out the right stuff.
5967 if (LHSMask.getNode() || RHSMask.getNode())
5968 return nullptr;
5969
5970 // If the shift amount is sign/zext/any-extended just peel it off.
5971 SDValue LExtOp0 = LHSShiftAmt;
5972 SDValue RExtOp0 = RHSShiftAmt;
5973 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
5974 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
5975 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
5976 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
5977 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
5978 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
5979 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
5980 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
5981 LExtOp0 = LHSShiftAmt.getOperand(0);
5982 RExtOp0 = RHSShiftAmt.getOperand(0);
5983 }
5984
5985 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
5986 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
5987 if (TryL)
5988 return TryL;
5989
5990 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
5991 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
5992 if (TryR)
5993 return TryR;
5994
5995 return nullptr;
5996}
5997
5998namespace {
5999
6000/// Represents known origin of an individual byte in load combine pattern. The
6001/// value of the byte is either constant zero or comes from memory.
6002struct ByteProvider {
6003 // For constant zero providers Load is set to nullptr. For memory providers
6004 // Load represents the node which loads the byte from memory.
6005 // ByteOffset is the offset of the byte in the value produced by the load.
6006 LoadSDNode *Load = nullptr;
6007 unsigned ByteOffset = 0;
6008
6009 ByteProvider() = default;
6010
6011 static ByteProvider getMemory(LoadSDNode *Load, unsigned ByteOffset) {
6012 return ByteProvider(Load, ByteOffset);
6013 }
6014
6015 static ByteProvider getConstantZero() { return ByteProvider(nullptr, 0); }
6016
6017 bool isConstantZero() const { return !Load; }
6018 bool isMemory() const { return Load; }
6019
6020 bool operator==(const ByteProvider &Other) const {
6021 return Other.Load == Load && Other.ByteOffset == ByteOffset;
6022 }
6023
6024private:
6025 ByteProvider(LoadSDNode *Load, unsigned ByteOffset)
6026 : Load(Load), ByteOffset(ByteOffset) {}
6027};
6028
6029} // end anonymous namespace
6030
6031/// Recursively traverses the expression calculating the origin of the requested
6032/// byte of the given value. Returns None if the provider can't be calculated.
6033///
6034/// For all the values except the root of the expression verifies that the value
6035/// has exactly one use and if it's not true return None. This way if the origin
6036/// of the byte is returned it's guaranteed that the values which contribute to
6037/// the byte are not used outside of this expression.
6038///
6039/// Because the parts of the expression are not allowed to have more than one
6040/// use this function iterates over trees, not DAGs. So it never visits the same
6041/// node more than once.
6042static const Optional<ByteProvider>
6043calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth,
6044 bool Root = false) {
6045 // Typical i64 by i8 pattern requi