Bug Summary

File:lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Warning:line 15378, column 1
Potential leak of memory pointed to by 'N1UsedElements.X'

Annotated Source Code

/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

</
1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11// both before and after the DAG is legalized.
12//
13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14// primarily intended to handle simplification opportunities that are implicit
15// in the LLVM IR and exposed by the various codegen lowering phases.
16//
17//===----------------------------------------------------------------------===//
18
19#include "llvm/ADT/APFloat.h"
20#include "llvm/ADT/APInt.h"
21#include "llvm/ADT/ArrayRef.h"
22#include "llvm/ADT/DenseMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallBitVector.h"
28#include "llvm/ADT/SmallPtrSet.h"
29#include "llvm/ADT/SmallSet.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/Statistic.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/MemoryLocation.h"
34#include "llvm/CodeGen/DAGCombine.h"
35#include "llvm/CodeGen/ISDOpcodes.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineValueType.h"
40#include "llvm/CodeGen/RuntimeLibcalls.h"
41#include "llvm/CodeGen/SelectionDAG.h"
42#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
43#include "llvm/CodeGen/SelectionDAGNodes.h"
44#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
45#include "llvm/CodeGen/TargetLowering.h"
46#include "llvm/CodeGen/TargetRegisterInfo.h"
47#include "llvm/CodeGen/TargetSubtargetInfo.h"
48#include "llvm/CodeGen/ValueTypes.h"
49#include "llvm/IR/Attributes.h"
50#include "llvm/IR/Constant.h"
51#include "llvm/IR/DataLayout.h"
52#include "llvm/IR/DerivedTypes.h"
53#include "llvm/IR/Function.h"
54#include "llvm/IR/LLVMContext.h"
55#include "llvm/IR/Metadata.h"
56#include "llvm/Support/Casting.h"
57#include "llvm/Support/CodeGen.h"
58#include "llvm/Support/CommandLine.h"
59#include "llvm/Support/Compiler.h"
60#include "llvm/Support/Debug.h"
61#include "llvm/Support/ErrorHandling.h"
62#include "llvm/Support/KnownBits.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetMachine.h"
66#include "llvm/Target/TargetOptions.h"
67#include <algorithm>
68#include <cassert>
69#include <cstdint>
70#include <functional>
71#include <iterator>
72#include <string>
73#include <tuple>
74#include <utility>
75#include <vector>
76
77using namespace llvm;
78
79#define DEBUG_TYPE"dagcombine" "dagcombine"
80
81STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined", {0}, false}
;
82STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created", {0}, false}
;
83STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created", {0}, false}
;
84STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed", {0}, false}
;
85STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int", {0}, false
}
;
86STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced", {0}, false}
;
87
88static cl::opt<bool>
89CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
90 cl::desc("Enable DAG combiner's use of IR alias analysis"));
91
92static cl::opt<bool>
93UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
94 cl::desc("Enable DAG combiner's use of TBAA"));
95
96#ifndef NDEBUG
97static cl::opt<std::string>
98CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
99 cl::desc("Only use DAG-combiner alias analysis in this"
100 " function"));
101#endif
102
103/// Hidden option to stress test load slicing, i.e., when this option
104/// is enabled, load slicing bypasses most of its profitability guards.
105static cl::opt<bool>
106StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
107 cl::desc("Bypass the profitability model of load slicing"),
108 cl::init(false));
109
110static cl::opt<bool>
111 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
112 cl::desc("DAG combiner may split indexing from loads"));
113
114namespace {
115
116 class DAGCombiner {
117 SelectionDAG &DAG;
118 const TargetLowering &TLI;
119 CombineLevel Level;
120 CodeGenOpt::Level OptLevel;
121 bool LegalOperations = false;
122 bool LegalTypes = false;
123 bool ForCodeSize;
124
125 /// \brief Worklist of all of the nodes that need to be simplified.
126 ///
127 /// This must behave as a stack -- new nodes to process are pushed onto the
128 /// back and when processing we pop off of the back.
129 ///
130 /// The worklist will not contain duplicates but may contain null entries
131 /// due to nodes being deleted from the underlying DAG.
132 SmallVector<SDNode *, 64> Worklist;
133
134 /// \brief Mapping from an SDNode to its position on the worklist.
135 ///
136 /// This is used to find and remove nodes from the worklist (by nulling
137 /// them) when they are deleted from the underlying DAG. It relies on
138 /// stable indices of nodes within the worklist.
139 DenseMap<SDNode *, unsigned> WorklistMap;
140
141 /// \brief Set of nodes which have been combined (at least once).
142 ///
143 /// This is used to allow us to reliably add any operands of a DAG node
144 /// which have not yet been combined to the worklist.
145 SmallPtrSet<SDNode *, 32> CombinedNodes;
146
147 // AA - Used for DAG load/store alias analysis.
148 AliasAnalysis *AA;
149
150 /// When an instruction is simplified, add all users of the instruction to
151 /// the work lists because they might get more simplified now.
152 void AddUsersToWorklist(SDNode *N) {
153 for (SDNode *Node : N->uses())
154 AddToWorklist(Node);
155 }
156
157 /// Call the node-specific routine that folds each particular type of node.
158 SDValue visit(SDNode *N);
159
160 public:
161 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
162 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
163 OptLevel(OL), AA(AA) {
164 ForCodeSize = DAG.getMachineFunction().getFunction()->optForSize();
165
166 MaximumLegalStoreInBits = 0;
167 for (MVT VT : MVT::all_valuetypes())
168 if (EVT(VT).isSimple() && VT != MVT::Other &&
169 TLI.isTypeLegal(EVT(VT)) &&
170 VT.getSizeInBits() >= MaximumLegalStoreInBits)
171 MaximumLegalStoreInBits = VT.getSizeInBits();
172 }
173
174 /// Add to the worklist making sure its instance is at the back (next to be
175 /// processed.)
176 void AddToWorklist(SDNode *N) {
177 assert(N->getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Deleted Node added to Worklist") ? void (0) : __assert_fail
("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 178, __extension__ __PRETTY_FUNCTION__))
178 "Deleted Node added to Worklist")(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Deleted Node added to Worklist") ? void (0) : __assert_fail
("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 178, __extension__ __PRETTY_FUNCTION__))
;
179
180 // Skip handle nodes as they can't usefully be combined and confuse the
181 // zero-use deletion strategy.
182 if (N->getOpcode() == ISD::HANDLENODE)
183 return;
184
185 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
186 Worklist.push_back(N);
187 }
188
189 /// Remove all instances of N from the worklist.
190 void removeFromWorklist(SDNode *N) {
191 CombinedNodes.erase(N);
192
193 auto It = WorklistMap.find(N);
194 if (It == WorklistMap.end())
195 return; // Not in the worklist.
196
197 // Null out the entry rather than erasing it to avoid a linear operation.
198 Worklist[It->second] = nullptr;
199 WorklistMap.erase(It);
200 }
201
202 void deleteAndRecombine(SDNode *N);
203 bool recursivelyDeleteUnusedNodes(SDNode *N);
204
205 /// Replaces all uses of the results of one DAG node with new values.
206 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
207 bool AddTo = true);
208
209 /// Replaces all uses of the results of one DAG node with new values.
210 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
211 return CombineTo(N, &Res, 1, AddTo);
212 }
213
214 /// Replaces all uses of the results of one DAG node with new values.
215 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
216 bool AddTo = true) {
217 SDValue To[] = { Res0, Res1 };
218 return CombineTo(N, To, 2, AddTo);
219 }
220
221 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
222
223 private:
224 unsigned MaximumLegalStoreInBits;
225
226 /// Check the specified integer node value to see if it can be simplified or
227 /// if things it uses can be simplified by bit propagation.
228 /// If so, return true.
229 bool SimplifyDemandedBits(SDValue Op) {
230 unsigned BitWidth = Op.getScalarValueSizeInBits();
231 APInt Demanded = APInt::getAllOnesValue(BitWidth);
232 return SimplifyDemandedBits(Op, Demanded);
233 }
234
235 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
236
237 bool CombineToPreIndexedLoadStore(SDNode *N);
238 bool CombineToPostIndexedLoadStore(SDNode *N);
239 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
240 bool SliceUpLoad(SDNode *N);
241
242 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
243 /// load.
244 ///
245 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
246 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
247 /// \param EltNo index of the vector element to load.
248 /// \param OriginalLoad load that EVE came from to be replaced.
249 /// \returns EVE on success SDValue() on failure.
250 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
251 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
252 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
253 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
254 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
255 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
256 SDValue PromoteIntBinOp(SDValue Op);
257 SDValue PromoteIntShiftOp(SDValue Op);
258 SDValue PromoteExtend(SDValue Op);
259 bool PromoteLoad(SDValue Op);
260
261 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs, SDValue Trunc,
262 SDValue ExtLoad, const SDLoc &DL,
263 ISD::NodeType ExtType);
264
265 /// Call the node-specific routine that knows how to fold each
266 /// particular type of node. If that doesn't do anything, try the
267 /// target-specific DAG combines.
268 SDValue combine(SDNode *N);
269
270 // Visitation implementation - Implement dag node combining for different
271 // node types. The semantics are as follows:
272 // Return Value:
273 // SDValue.getNode() == 0 - No change was made
274 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
275 // otherwise - N should be replaced by the returned Operand.
276 //
277 SDValue visitTokenFactor(SDNode *N);
278 SDValue visitMERGE_VALUES(SDNode *N);
279 SDValue visitADD(SDNode *N);
280 SDValue visitADDLike(SDValue N0, SDValue N1, SDNode *LocReference);
281 SDValue visitSUB(SDNode *N);
282 SDValue visitADDC(SDNode *N);
283 SDValue visitUADDO(SDNode *N);
284 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
285 SDValue visitSUBC(SDNode *N);
286 SDValue visitUSUBO(SDNode *N);
287 SDValue visitADDE(SDNode *N);
288 SDValue visitADDCARRY(SDNode *N);
289 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
290 SDValue visitSUBE(SDNode *N);
291 SDValue visitSUBCARRY(SDNode *N);
292 SDValue visitMUL(SDNode *N);
293 SDValue useDivRem(SDNode *N);
294 SDValue visitSDIV(SDNode *N);
295 SDValue visitUDIV(SDNode *N);
296 SDValue visitREM(SDNode *N);
297 SDValue visitMULHU(SDNode *N);
298 SDValue visitMULHS(SDNode *N);
299 SDValue visitSMUL_LOHI(SDNode *N);
300 SDValue visitUMUL_LOHI(SDNode *N);
301 SDValue visitSMULO(SDNode *N);
302 SDValue visitUMULO(SDNode *N);
303 SDValue visitIMINMAX(SDNode *N);
304 SDValue visitAND(SDNode *N);
305 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
306 SDValue visitOR(SDNode *N);
307 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
308 SDValue visitXOR(SDNode *N);
309 SDValue SimplifyVBinOp(SDNode *N);
310 SDValue visitSHL(SDNode *N);
311 SDValue visitSRA(SDNode *N);
312 SDValue visitSRL(SDNode *N);
313 SDValue visitRotate(SDNode *N);
314 SDValue visitABS(SDNode *N);
315 SDValue visitBSWAP(SDNode *N);
316 SDValue visitBITREVERSE(SDNode *N);
317 SDValue visitCTLZ(SDNode *N);
318 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
319 SDValue visitCTTZ(SDNode *N);
320 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
321 SDValue visitCTPOP(SDNode *N);
322 SDValue visitSELECT(SDNode *N);
323 SDValue visitVSELECT(SDNode *N);
324 SDValue visitSELECT_CC(SDNode *N);
325 SDValue visitSETCC(SDNode *N);
326 SDValue visitSETCCE(SDNode *N);
327 SDValue visitSETCCCARRY(SDNode *N);
328 SDValue visitSIGN_EXTEND(SDNode *N);
329 SDValue visitZERO_EXTEND(SDNode *N);
330 SDValue visitANY_EXTEND(SDNode *N);
331 SDValue visitAssertExt(SDNode *N);
332 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
333 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
334 SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
335 SDValue visitTRUNCATE(SDNode *N);
336 SDValue visitBITCAST(SDNode *N);
337 SDValue visitBUILD_PAIR(SDNode *N);
338 SDValue visitFADD(SDNode *N);
339 SDValue visitFSUB(SDNode *N);
340 SDValue visitFMUL(SDNode *N);
341 SDValue visitFMA(SDNode *N);
342 SDValue visitFDIV(SDNode *N);
343 SDValue visitFREM(SDNode *N);
344 SDValue visitFSQRT(SDNode *N);
345 SDValue visitFCOPYSIGN(SDNode *N);
346 SDValue visitSINT_TO_FP(SDNode *N);
347 SDValue visitUINT_TO_FP(SDNode *N);
348 SDValue visitFP_TO_SINT(SDNode *N);
349 SDValue visitFP_TO_UINT(SDNode *N);
350 SDValue visitFP_ROUND(SDNode *N);
351 SDValue visitFP_ROUND_INREG(SDNode *N);
352 SDValue visitFP_EXTEND(SDNode *N);
353 SDValue visitFNEG(SDNode *N);
354 SDValue visitFABS(SDNode *N);
355 SDValue visitFCEIL(SDNode *N);
356 SDValue visitFTRUNC(SDNode *N);
357 SDValue visitFFLOOR(SDNode *N);
358 SDValue visitFMINNUM(SDNode *N);
359 SDValue visitFMAXNUM(SDNode *N);
360 SDValue visitBRCOND(SDNode *N);
361 SDValue visitBR_CC(SDNode *N);
362 SDValue visitLOAD(SDNode *N);
363
364 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
365 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
366
367 SDValue visitSTORE(SDNode *N);
368 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
369 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
370 SDValue visitBUILD_VECTOR(SDNode *N);
371 SDValue visitCONCAT_VECTORS(SDNode *N);
372 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
373 SDValue visitVECTOR_SHUFFLE(SDNode *N);
374 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
375 SDValue visitINSERT_SUBVECTOR(SDNode *N);
376 SDValue visitMLOAD(SDNode *N);
377 SDValue visitMSTORE(SDNode *N);
378 SDValue visitMGATHER(SDNode *N);
379 SDValue visitMSCATTER(SDNode *N);
380 SDValue visitFP_TO_FP16(SDNode *N);
381 SDValue visitFP16_TO_FP(SDNode *N);
382
383 SDValue visitFADDForFMACombine(SDNode *N);
384 SDValue visitFSUBForFMACombine(SDNode *N);
385 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
386
387 SDValue XformToShuffleWithZero(SDNode *N);
388 SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS,
389 SDValue RHS);
390
391 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
392
393 SDValue foldSelectOfConstants(SDNode *N);
394 SDValue foldVSelectOfConstants(SDNode *N);
395 SDValue foldBinOpIntoSelect(SDNode *BO);
396 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
397 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
398 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
399 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
400 SDValue N2, SDValue N3, ISD::CondCode CC,
401 bool NotExtCompare = false);
402 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
403 SDValue N2, SDValue N3, ISD::CondCode CC);
404 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
405 const SDLoc &DL);
406 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
407 const SDLoc &DL, bool foldBooleans = true);
408
409 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
410 SDValue &CC) const;
411 bool isOneUseSetCC(SDValue N) const;
412
413 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
414 unsigned HiOp);
415 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
416 SDValue CombineExtLoad(SDNode *N);
417 SDValue combineRepeatedFPDivisors(SDNode *N);
418 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
419 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
420 SDValue BuildSDIV(SDNode *N);
421 SDValue BuildSDIVPow2(SDNode *N);
422 SDValue BuildUDIV(SDNode *N);
423 SDValue BuildLogBase2(SDValue Op, const SDLoc &DL);
424 SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags);
425 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
426 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
427 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
428 SDValue buildSqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations,
429 SDNodeFlags Flags, bool Reciprocal);
430 SDValue buildSqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations,
431 SDNodeFlags Flags, bool Reciprocal);
432 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
433 bool DemandHighBits = true);
434 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
435 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
436 SDValue InnerPos, SDValue InnerNeg,
437 unsigned PosOpcode, unsigned NegOpcode,
438 const SDLoc &DL);
439 SDNode *MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
440 SDValue MatchLoadCombine(SDNode *N);
441 SDValue ReduceLoadWidth(SDNode *N);
442 SDValue ReduceLoadOpStoreWidth(SDNode *N);
443 SDValue splitMergedValStore(StoreSDNode *ST);
444 SDValue TransformFPLoadStorePair(SDNode *N);
445 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
446 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
447 SDValue reduceBuildVecToShuffle(SDNode *N);
448 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
449 ArrayRef<int> VectorMask, SDValue VecIn1,
450 SDValue VecIn2, unsigned LeftIdx);
451 SDValue matchVSelectOpSizesWithSetCC(SDNode *N);
452
453 /// Walk up chain skipping non-aliasing memory nodes,
454 /// looking for aliasing nodes and adding them to the Aliases vector.
455 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
456 SmallVectorImpl<SDValue> &Aliases);
457
458 /// Return true if there is any possibility that the two addresses overlap.
459 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
460
461 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
462 /// chain (aliasing node.)
463 SDValue FindBetterChain(SDNode *N, SDValue Chain);
464
465 /// Try to replace a store and any possibly adjacent stores on
466 /// consecutive chains with better chains. Return true only if St is
467 /// replaced.
468 ///
469 /// Notice that other chains may still be replaced even if the function
470 /// returns false.
471 bool findBetterNeighborChains(StoreSDNode *St);
472
473 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
474 bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask);
475
476 /// Holds a pointer to an LSBaseSDNode as well as information on where it
477 /// is located in a sequence of memory operations connected by a chain.
478 struct MemOpLink {
479 // Ptr to the mem node.
480 LSBaseSDNode *MemNode;
481
482 // Offset from the base ptr.
483 int64_t OffsetFromBase;
484
485 MemOpLink(LSBaseSDNode *N, int64_t Offset)
486 : MemNode(N), OffsetFromBase(Offset) {}
487 };
488
489 /// This is a helper function for visitMUL to check the profitability
490 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
491 /// MulNode is the original multiply, AddNode is (add x, c1),
492 /// and ConstNode is c2.
493 bool isMulAddWithConstProfitable(SDNode *MulNode,
494 SDValue &AddNode,
495 SDValue &ConstNode);
496
497 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
498 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
499 /// the type of the loaded value to be extended. LoadedVT returns the type
500 /// of the original loaded value. NarrowLoad returns whether the load would
501 /// need to be narrowed in order to match.
502 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
503 EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT,
504 bool &NarrowLoad);
505
506 /// Helper function for MergeConsecutiveStores which merges the
507 /// component store chains.
508 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
509 unsigned NumStores);
510
511 /// This is a helper function for MergeConsecutiveStores. When the
512 /// source elements of the consecutive stores are all constants or
513 /// all extracted vector elements, try to merge them into one
514 /// larger store introducing bitcasts if necessary. \return True
515 /// if a merged store was created.
516 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
517 EVT MemVT, unsigned NumStores,
518 bool IsConstantSrc, bool UseVector,
519 bool UseTrunc);
520
521 /// This is a helper function for MergeConsecutiveStores. Stores
522 /// that potentially may be merged with St are placed in
523 /// StoreNodes.
524 void getStoreMergeCandidates(StoreSDNode *St,
525 SmallVectorImpl<MemOpLink> &StoreNodes);
526
527 /// Helper function for MergeConsecutiveStores. Checks if
528 /// candidate stores have indirect dependency through their
529 /// operands. \return True if safe to merge.
530 bool checkMergeStoreCandidatesForDependencies(
531 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores);
532
533 /// Merge consecutive store operations into a wide store.
534 /// This optimization uses wide integers or vectors when possible.
535 /// \return number of stores that were merged into a merged store (the
536 /// affected nodes are stored as a prefix in \p StoreNodes).
537 bool MergeConsecutiveStores(StoreSDNode *N);
538
539 /// \brief Try to transform a truncation where C is a constant:
540 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
541 ///
542 /// \p N needs to be a truncation and its first operand an AND. Other
543 /// requirements are checked by the function (e.g. that trunc is
544 /// single-use) and if missed an empty SDValue is returned.
545 SDValue distributeTruncateThroughAnd(SDNode *N);
546
547 public:
548 /// Runs the dag combiner on all nodes in the work list
549 void Run(CombineLevel AtLevel);
550
551 SelectionDAG &getDAG() const { return DAG; }
552
553 /// Returns a type large enough to hold any valid shift amount - before type
554 /// legalization these can be huge.
555 EVT getShiftAmountTy(EVT LHSTy) {
556 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")(static_cast <bool> (LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? void (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 556, __extension__ __PRETTY_FUNCTION__))
;
557 if (LHSTy.isVector())
558 return LHSTy;
559 auto &DL = DAG.getDataLayout();
560 return LegalTypes ? TLI.getScalarShiftAmountTy(DL, LHSTy)
561 : TLI.getPointerTy(DL);
562 }
563
564 /// This method returns true if we are running before type legalization or
565 /// if the specified VT is legal.
566 bool isTypeLegal(const EVT &VT) {
567 if (!LegalTypes) return true;
568 return TLI.isTypeLegal(VT);
569 }
570
571 /// Convenience wrapper around TargetLowering::getSetCCResultType
572 EVT getSetCCResultType(EVT VT) const {
573 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
574 }
575 };
576
577/// This class is a DAGUpdateListener that removes any deleted
578/// nodes from the worklist.
579class WorklistRemover : public SelectionDAG::DAGUpdateListener {
580 DAGCombiner &DC;
581
582public:
583 explicit WorklistRemover(DAGCombiner &dc)
584 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
585
586 void NodeDeleted(SDNode *N, SDNode *E) override {
587 DC.removeFromWorklist(N);
588 }
589};
590
591} // end anonymous namespace
592
593//===----------------------------------------------------------------------===//
594// TargetLowering::DAGCombinerInfo implementation
595//===----------------------------------------------------------------------===//
596
597void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
598 ((DAGCombiner*)DC)->AddToWorklist(N);
599}
600
601SDValue TargetLowering::DAGCombinerInfo::
602CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
603 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
604}
605
606SDValue TargetLowering::DAGCombinerInfo::
607CombineTo(SDNode *N, SDValue Res, bool AddTo) {
608 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
609}
610
611SDValue TargetLowering::DAGCombinerInfo::
612CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
613 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
614}
615
616void TargetLowering::DAGCombinerInfo::
617CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
618 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
619}
620
621//===----------------------------------------------------------------------===//
622// Helper Functions
623//===----------------------------------------------------------------------===//
624
625void DAGCombiner::deleteAndRecombine(SDNode *N) {
626 removeFromWorklist(N);
627
628 // If the operands of this node are only used by the node, they will now be
629 // dead. Make sure to re-visit them and recursively delete dead nodes.
630 for (const SDValue &Op : N->ops())
631 // For an operand generating multiple values, one of the values may
632 // become dead allowing further simplification (e.g. split index
633 // arithmetic from an indexed load).
634 if (Op->hasOneUse() || Op->getNumValues() > 1)
635 AddToWorklist(Op.getNode());
636
637 DAG.DeleteNode(N);
638}
639
640/// Return 1 if we can compute the negated form of the specified expression for
641/// the same cost as the expression itself, or 2 if we can compute the negated
642/// form more cheaply than the expression itself.
643static char isNegatibleForFree(SDValue Op, bool LegalOperations,
644 const TargetLowering &TLI,
645 const TargetOptions *Options,
646 unsigned Depth = 0) {
647 // fneg is removable even if it has multiple uses.
648 if (Op.getOpcode() == ISD::FNEG) return 2;
649
650 // Don't allow anything with multiple uses.
651 if (!Op.hasOneUse()) return 0;
652
653 // Don't recurse exponentially.
654 if (Depth > 6) return 0;
655
656 switch (Op.getOpcode()) {
657 default: return false;
658 case ISD::ConstantFP: {
659 if (!LegalOperations)
660 return 1;
661
662 // Don't invert constant FP values after legalization unless the target says
663 // the negated constant is legal.
664 EVT VT = Op.getValueType();
665 return TLI.isOperationLegal(ISD::ConstantFP, VT) ||
666 TLI.isFPImmLegal(neg(cast<ConstantFPSDNode>(Op)->getValueAPF()), VT);
667 }
668 case ISD::FADD:
669 // FIXME: determine better conditions for this xform.
670 if (!Options->UnsafeFPMath) return 0;
671
672 // After operation legalization, it might not be legal to create new FSUBs.
673 if (LegalOperations &&
674 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
675 return 0;
676
677 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
678 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
679 Options, Depth + 1))
680 return V;
681 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
682 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
683 Depth + 1);
684 case ISD::FSUB:
685 // We can't turn -(A-B) into B-A when we honor signed zeros.
686 if (!Options->NoSignedZerosFPMath &&
687 !Op.getNode()->getFlags().hasNoSignedZeros())
688 return 0;
689
690 // fold (fneg (fsub A, B)) -> (fsub B, A)
691 return 1;
692
693 case ISD::FMUL:
694 case ISD::FDIV:
695 if (Options->HonorSignDependentRoundingFPMath()) return 0;
696
697 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
698 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
699 Options, Depth + 1))
700 return V;
701
702 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
703 Depth + 1);
704
705 case ISD::FP_EXTEND:
706 case ISD::FP_ROUND:
707 case ISD::FSIN:
708 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
709 Depth + 1);
710 }
711}
712
713/// If isNegatibleForFree returns true, return the newly negated expression.
714static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
715 bool LegalOperations, unsigned Depth = 0) {
716 const TargetOptions &Options = DAG.getTarget().Options;
717 // fneg is removable even if it has multiple uses.
718 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
719
720 // Don't allow anything with multiple uses.
721 assert(Op.hasOneUse() && "Unknown reuse!")(static_cast <bool> (Op.hasOneUse() && "Unknown reuse!"
) ? void (0) : __assert_fail ("Op.hasOneUse() && \"Unknown reuse!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 721, __extension__ __PRETTY_FUNCTION__))
;
722
723 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree")(static_cast <bool> (Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"
) ? void (0) : __assert_fail ("Depth <= 6 && \"GetNegatedExpression doesn't match isNegatibleForFree\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 723, __extension__ __PRETTY_FUNCTION__))
;
724
725 const SDNodeFlags Flags = Op.getNode()->getFlags();
726
727 switch (Op.getOpcode()) {
728 default: llvm_unreachable("Unknown code")::llvm::llvm_unreachable_internal("Unknown code", "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 728)
;
729 case ISD::ConstantFP: {
730 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
731 V.changeSign();
732 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
733 }
734 case ISD::FADD:
735 // FIXME: determine better conditions for this xform.
736 assert(Options.UnsafeFPMath)(static_cast <bool> (Options.UnsafeFPMath) ? void (0) :
__assert_fail ("Options.UnsafeFPMath", "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 736, __extension__ __PRETTY_FUNCTION__))
;
737
738 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
739 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
740 DAG.getTargetLoweringInfo(), &Options, Depth+1))
741 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
742 GetNegatedExpression(Op.getOperand(0), DAG,
743 LegalOperations, Depth+1),
744 Op.getOperand(1), Flags);
745 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
746 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
747 GetNegatedExpression(Op.getOperand(1), DAG,
748 LegalOperations, Depth+1),
749 Op.getOperand(0), Flags);
750 case ISD::FSUB:
751 // fold (fneg (fsub 0, B)) -> B
752 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
753 if (N0CFP->isZero())
754 return Op.getOperand(1);
755
756 // fold (fneg (fsub A, B)) -> (fsub B, A)
757 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
758 Op.getOperand(1), Op.getOperand(0), Flags);
759
760 case ISD::FMUL:
761 case ISD::FDIV:
762 assert(!Options.HonorSignDependentRoundingFPMath())(static_cast <bool> (!Options.HonorSignDependentRoundingFPMath
()) ? void (0) : __assert_fail ("!Options.HonorSignDependentRoundingFPMath()"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 762, __extension__ __PRETTY_FUNCTION__))
;
763
764 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
765 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
766 DAG.getTargetLoweringInfo(), &Options, Depth+1))
767 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
768 GetNegatedExpression(Op.getOperand(0), DAG,
769 LegalOperations, Depth+1),
770 Op.getOperand(1), Flags);
771
772 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
773 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
774 Op.getOperand(0),
775 GetNegatedExpression(Op.getOperand(1), DAG,
776 LegalOperations, Depth+1), Flags);
777
778 case ISD::FP_EXTEND:
779 case ISD::FSIN:
780 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
781 GetNegatedExpression(Op.getOperand(0), DAG,
782 LegalOperations, Depth+1));
783 case ISD::FP_ROUND:
784 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
785 GetNegatedExpression(Op.getOperand(0), DAG,
786 LegalOperations, Depth+1),
787 Op.getOperand(1));
788 }
789}
790
791// APInts must be the same size for most operations, this helper
792// function zero extends the shorter of the pair so that they match.
793// We provide an Offset so that we can create bitwidths that won't overflow.
794static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
795 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
796 LHS = LHS.zextOrSelf(Bits);
797 RHS = RHS.zextOrSelf(Bits);
798}
799
800// Return true if this node is a setcc, or is a select_cc
801// that selects between the target values used for true and false, making it
802// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
803// the appropriate nodes based on the type of node we are checking. This
804// simplifies life a bit for the callers.
805bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
806 SDValue &CC) const {
807 if (N.getOpcode() == ISD::SETCC) {
808 LHS = N.getOperand(0);
809 RHS = N.getOperand(1);
810 CC = N.getOperand(2);
811 return true;
812 }
813
814 if (N.getOpcode() != ISD::SELECT_CC ||
815 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
816 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
817 return false;
818
819 if (TLI.getBooleanContents(N.getValueType()) ==
820 TargetLowering::UndefinedBooleanContent)
821 return false;
822
823 LHS = N.getOperand(0);
824 RHS = N.getOperand(1);
825 CC = N.getOperand(4);
826 return true;
827}
828
829/// Return true if this is a SetCC-equivalent operation with only one use.
830/// If this is true, it allows the users to invert the operation for free when
831/// it is profitable to do so.
832bool DAGCombiner::isOneUseSetCC(SDValue N) const {
833 SDValue N0, N1, N2;
834 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
835 return true;
836 return false;
837}
838
839// \brief Returns the SDNode if it is a constant float BuildVector
840// or constant float.
841static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
842 if (isa<ConstantFPSDNode>(N))
843 return N.getNode();
844 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
845 return N.getNode();
846 return nullptr;
847}
848
849// Determines if it is a constant integer or a build vector of constant
850// integers (and undefs).
851// Do not permit build vector implicit truncation.
852static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
853 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
854 return !(Const->isOpaque() && NoOpaques);
855 if (N.getOpcode() != ISD::BUILD_VECTOR)
856 return false;
857 unsigned BitWidth = N.getScalarValueSizeInBits();
858 for (const SDValue &Op : N->op_values()) {
859 if (Op.isUndef())
860 continue;
861 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
862 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
863 (Const->isOpaque() && NoOpaques))
864 return false;
865 }
866 return true;
867}
868
869// Determines if it is a constant null integer or a splatted vector of a
870// constant null integer (with no undefs).
871// Build vector implicit truncation is not an issue for null values.
872static bool isNullConstantOrNullSplatConstant(SDValue N) {
873 if (ConstantSDNode *Splat = isConstOrConstSplat(N))
874 return Splat->isNullValue();
875 return false;
876}
877
878// Determines if it is a constant integer of one or a splatted vector of a
879// constant integer of one (with no undefs).
880// Do not permit build vector implicit truncation.
881static bool isOneConstantOrOneSplatConstant(SDValue N) {
882 unsigned BitWidth = N.getScalarValueSizeInBits();
883 if (ConstantSDNode *Splat = isConstOrConstSplat(N))
884 return Splat->isOne() && Splat->getAPIntValue().getBitWidth() == BitWidth;
885 return false;
886}
887
888// Determines if it is a constant integer of all ones or a splatted vector of a
889// constant integer of all ones (with no undefs).
890// Do not permit build vector implicit truncation.
891static bool isAllOnesConstantOrAllOnesSplatConstant(SDValue N) {
892 unsigned BitWidth = N.getScalarValueSizeInBits();
893 if (ConstantSDNode *Splat = isConstOrConstSplat(N))
894 return Splat->isAllOnesValue() &&
895 Splat->getAPIntValue().getBitWidth() == BitWidth;
896 return false;
897}
898
899// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
900// undef's.
901static bool isAnyConstantBuildVector(const SDNode *N) {
902 return ISD::isBuildVectorOfConstantSDNodes(N) ||
903 ISD::isBuildVectorOfConstantFPSDNodes(N);
904}
905
906// Attempt to match a unary predicate against a scalar/splat constant or
907// every element of a constant BUILD_VECTOR.
908static bool matchUnaryPredicate(SDValue Op,
909 std::function<bool(ConstantSDNode *)> Match) {
910 if (auto *Cst = dyn_cast<ConstantSDNode>(Op))
911 return Match(Cst);
912
913 if (ISD::BUILD_VECTOR != Op.getOpcode())
914 return false;
915
916 EVT SVT = Op.getValueType().getScalarType();
917 for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
918 auto *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(i));
919 if (!Cst || Cst->getValueType(0) != SVT || !Match(Cst))
920 return false;
921 }
922 return true;
923}
924
925// Attempt to match a binary predicate against a pair of scalar/splat constants
926// or every element of a pair of constant BUILD_VECTORs.
927static bool matchBinaryPredicate(
928 SDValue LHS, SDValue RHS,
929 std::function<bool(ConstantSDNode *, ConstantSDNode *)> Match) {
930 if (LHS.getValueType() != RHS.getValueType())
931 return false;
932
933 if (auto *LHSCst = dyn_cast<ConstantSDNode>(LHS))
934 if (auto *RHSCst = dyn_cast<ConstantSDNode>(RHS))
935 return Match(LHSCst, RHSCst);
936
937 if (ISD::BUILD_VECTOR != LHS.getOpcode() ||
938 ISD::BUILD_VECTOR != RHS.getOpcode())
939 return false;
940
941 EVT SVT = LHS.getValueType().getScalarType();
942 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
943 auto *LHSCst = dyn_cast<ConstantSDNode>(LHS.getOperand(i));
944 auto *RHSCst = dyn_cast<ConstantSDNode>(RHS.getOperand(i));
945 if (!LHSCst || !RHSCst)
946 return false;
947 if (LHSCst->getValueType(0) != SVT ||
948 LHSCst->getValueType(0) != RHSCst->getValueType(0))
949 return false;
950 if (!Match(LHSCst, RHSCst))
951 return false;
952 }
953 return true;
954}
955
956SDValue DAGCombiner::ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
957 SDValue N1) {
958 EVT VT = N0.getValueType();
959 if (N0.getOpcode() == Opc) {
960 if (SDNode *L = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
961 if (SDNode *R = DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
962 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
963 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R))
964 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
965 return SDValue();
966 }
967 if (N0.hasOneUse()) {
968 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
969 // use
970 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
971 if (!OpNode.getNode())
972 return SDValue();
973 AddToWorklist(OpNode.getNode());
974 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
975 }
976 }
977 }
978
979 if (N1.getOpcode() == Opc) {
980 if (SDNode *R = DAG.isConstantIntBuildVectorOrConstantInt(N1.getOperand(1))) {
981 if (SDNode *L = DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
982 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
983 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, R, L))
984 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
985 return SDValue();
986 }
987 if (N1.hasOneUse()) {
988 // reassoc. (op x, (op y, c1)) -> (op (op x, y), c1) iff x+c1 has one
989 // use
990 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0, N1.getOperand(0));
991 if (!OpNode.getNode())
992 return SDValue();
993 AddToWorklist(OpNode.getNode());
994 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
995 }
996 }
997 }
998
999 return SDValue();
1000}
1001
1002SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1003 bool AddTo) {
1004 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")(static_cast <bool> (N->getNumValues() == NumTo &&
"Broken CombineTo call!") ? void (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1004, __extension__ __PRETTY_FUNCTION__))
;
1005 ++NodesCombined;
1006 DEBUG(dbgs() << "\nReplacing.1 ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo-1 <<
" other values\n"; } } while (false)
1007 N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo-1 <<
" other values\n"; } } while (false)
1008 dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo-1 <<
" other values\n"; } } while (false)
1009 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo-1 <<
" other values\n"; } } while (false)
1010 dbgs() << " and " << NumTo-1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo-1 <<
" other values\n"; } } while (false)
;
1011 for (unsigned i = 0, e = NumTo; i != e; ++i)
1012 assert((!To[i].getNode() ||(static_cast <bool> ((!To[i].getNode() || N->getValueType
(i) == To[i].getValueType()) && "Cannot combine value to value of different type!"
) ? void (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1014, __extension__ __PRETTY_FUNCTION__))
1013 N->getValueType(i) == To[i].getValueType()) &&(static_cast <bool> ((!To[i].getNode() || N->getValueType
(i) == To[i].getValueType()) && "Cannot combine value to value of different type!"
) ? void (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1014, __extension__ __PRETTY_FUNCTION__))
1014 "Cannot combine value to value of different type!")(static_cast <bool> ((!To[i].getNode() || N->getValueType
(i) == To[i].getValueType()) && "Cannot combine value to value of different type!"
) ? void (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1014, __extension__ __PRETTY_FUNCTION__))
;
1015
1016 WorklistRemover DeadNodes(*this);
1017 DAG.ReplaceAllUsesWith(N, To);
1018 if (AddTo) {
1019 // Push the new nodes and any users onto the worklist
1020 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1021 if (To[i].getNode()) {
1022 AddToWorklist(To[i].getNode());
1023 AddUsersToWorklist(To[i].getNode());
1024 }
1025 }
1026 }
1027
1028 // Finally, if the node is now dead, remove it from the graph. The node
1029 // may not be dead if the replacement process recursively simplified to
1030 // something else needing this node.
1031 if (N->use_empty())
1032 deleteAndRecombine(N);
1033 return SDValue(N, 0);
1034}
1035
1036void DAGCombiner::
1037CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1038 // Replace all uses. If any nodes become isomorphic to other nodes and
1039 // are deleted, make sure to remove them from our worklist.
1040 WorklistRemover DeadNodes(*this);
1041 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1042
1043 // Push the new node and any (possibly new) users onto the worklist.
1044 AddToWorklist(TLO.New.getNode());
1045 AddUsersToWorklist(TLO.New.getNode());
1046
1047 // Finally, if the node is now dead, remove it from the graph. The node
1048 // may not be dead if the replacement process recursively simplified to
1049 // something else needing this node.
1050 if (TLO.Old.getNode()->use_empty())
1051 deleteAndRecombine(TLO.Old.getNode());
1052}
1053
1054/// Check the specified integer node value to see if it can be simplified or if
1055/// things it uses can be simplified by bit propagation. If so, return true.
1056bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
1057 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1058 KnownBits Known;
1059 if (!TLI.SimplifyDemandedBits(Op, Demanded, Known, TLO))
1060 return false;
1061
1062 // Revisit the node.
1063 AddToWorklist(Op.getNode());
1064
1065 // Replace the old value with the new one.
1066 ++NodesCombined;
1067 DEBUG(dbgs() << "\nReplacing.2 ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1068 TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1069 dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1070 TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1071 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1072
1073 CommitTargetLoweringOpt(TLO);
1074 return true;
1075}
1076
1077void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1078 SDLoc DL(Load);
1079 EVT VT = Load->getValueType(0);
1080 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1081
1082 DEBUG(dbgs() << "\nReplacing.9 ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1083 Load->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1084 dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1085 Trunc.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1086 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1087 WorklistRemover DeadNodes(*this);
1088 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1089 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1090 deleteAndRecombine(Load);
1091 AddToWorklist(Trunc.getNode());
1092}
1093
1094SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1095 Replace = false;
1096 SDLoc DL(Op);
1097 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1098 LoadSDNode *LD = cast<LoadSDNode>(Op);
1099 EVT MemVT = LD->getMemoryVT();
1100 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1101 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1102 : ISD::EXTLOAD)
1103 : LD->getExtensionType();
1104 Replace = true;
1105 return DAG.getExtLoad(ExtType, DL, PVT,
1106 LD->getChain(), LD->getBasePtr(),
1107 MemVT, LD->getMemOperand());
1108 }
1109
1110 unsigned Opc = Op.getOpcode();
1111 switch (Opc) {
1112 default: break;
1113 case ISD::AssertSext:
1114 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1115 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1116 break;
1117 case ISD::AssertZext:
1118 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1119 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1120 break;
1121 case ISD::Constant: {
1122 unsigned ExtOpc =
1123 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1124 return DAG.getNode(ExtOpc, DL, PVT, Op);
1125 }
1126 }
1127
1128 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1129 return SDValue();
1130 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1131}
1132
1133SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1134 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1135 return SDValue();
1136 EVT OldVT = Op.getValueType();
1137 SDLoc DL(Op);
1138 bool Replace = false;
1139 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1140 if (!NewOp.getNode())
1141 return SDValue();
1142 AddToWorklist(NewOp.getNode());
1143
1144 if (Replace)
1145 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1146 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1147 DAG.getValueType(OldVT));
1148}
1149
1150SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1151 EVT OldVT = Op.getValueType();
1152 SDLoc DL(Op);
1153 bool Replace = false;
1154 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1155 if (!NewOp.getNode())
1156 return SDValue();
1157 AddToWorklist(NewOp.getNode());
1158
1159 if (Replace)
1160 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1161 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1162}
1163
1164/// Promote the specified integer binary operation if the target indicates it is
1165/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1166/// i32 since i16 instructions are longer.
1167SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1168 if (!LegalOperations)
1169 return SDValue();
1170
1171 EVT VT = Op.getValueType();
1172 if (VT.isVector() || !VT.isInteger())
1173 return SDValue();
1174
1175 // If operation type is 'undesirable', e.g. i16 on x86, consider
1176 // promoting it.
1177 unsigned Opc = Op.getOpcode();
1178 if (TLI.isTypeDesirableForOp(Opc, VT))
1179 return SDValue();
1180
1181 EVT PVT = VT;
1182 // Consult target whether it is a good idea to promote this operation and
1183 // what's the right type to promote it to.
1184 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1185 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1185, __extension__ __PRETTY_FUNCTION__))
;
1186
1187 DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1188
1189 bool Replace0 = false;
1190 SDValue N0 = Op.getOperand(0);
1191 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1192
1193 bool Replace1 = false;
1194 SDValue N1 = Op.getOperand(1);
1195 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1196 SDLoc DL(Op);
1197
1198 SDValue RV =
1199 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1200
1201 // We are always replacing N0/N1's use in N and only need
1202 // additional replacements if there are additional uses.
1203 Replace0 &= !N0->hasOneUse();
1204 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1205
1206 // Combine Op here so it is preserved past replacements.
1207 CombineTo(Op.getNode(), RV);
1208
1209 // If operands have a use ordering, make sure we deal with
1210 // predecessor first.
1211 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1212 std::swap(N0, N1);
1213 std::swap(NN0, NN1);
1214 }
1215
1216 if (Replace0) {
1217 AddToWorklist(NN0.getNode());
1218 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1219 }
1220 if (Replace1) {
1221 AddToWorklist(NN1.getNode());
1222 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1223 }
1224 return Op;
1225 }
1226 return SDValue();
1227}
1228
1229/// Promote the specified integer shift operation if the target indicates it is
1230/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1231/// i32 since i16 instructions are longer.
1232SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1233 if (!LegalOperations)
1234 return SDValue();
1235
1236 EVT VT = Op.getValueType();
1237 if (VT.isVector() || !VT.isInteger())
1238 return SDValue();
1239
1240 // If operation type is 'undesirable', e.g. i16 on x86, consider
1241 // promoting it.
1242 unsigned Opc = Op.getOpcode();
1243 if (TLI.isTypeDesirableForOp(Opc, VT))
1244 return SDValue();
1245
1246 EVT PVT = VT;
1247 // Consult target whether it is a good idea to promote this operation and
1248 // what's the right type to promote it to.
1249 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1250 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1250, __extension__ __PRETTY_FUNCTION__))
;
1251
1252 DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1253
1254 bool Replace = false;
1255 SDValue N0 = Op.getOperand(0);
1256 SDValue N1 = Op.getOperand(1);
1257 if (Opc == ISD::SRA)
1258 N0 = SExtPromoteOperand(N0, PVT);
1259 else if (Opc == ISD::SRL)
1260 N0 = ZExtPromoteOperand(N0, PVT);
1261 else
1262 N0 = PromoteOperand(N0, PVT, Replace);
1263
1264 if (!N0.getNode())
1265 return SDValue();
1266
1267 SDLoc DL(Op);
1268 SDValue RV =
1269 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1270
1271 AddToWorklist(N0.getNode());
1272 if (Replace)
1273 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1274
1275 // Deal with Op being deleted.
1276 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1277 return RV;
1278 }
1279 return SDValue();
1280}
1281
1282SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1283 if (!LegalOperations)
1284 return SDValue();
1285
1286 EVT VT = Op.getValueType();
1287 if (VT.isVector() || !VT.isInteger())
1288 return SDValue();
1289
1290 // If operation type is 'undesirable', e.g. i16 on x86, consider
1291 // promoting it.
1292 unsigned Opc = Op.getOpcode();
1293 if (TLI.isTypeDesirableForOp(Opc, VT))
1294 return SDValue();
1295
1296 EVT PVT = VT;
1297 // Consult target whether it is a good idea to promote this operation and
1298 // what's the right type to promote it to.
1299 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1300 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1300, __extension__ __PRETTY_FUNCTION__))
;
1301 // fold (aext (aext x)) -> (aext x)
1302 // fold (aext (zext x)) -> (zext x)
1303 // fold (aext (sext x)) -> (sext x)
1304 DEBUG(dbgs() << "\nPromoting ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
1305 Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1306 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1307 }
1308 return SDValue();
1309}
1310
1311bool DAGCombiner::PromoteLoad(SDValue Op) {
1312 if (!LegalOperations)
1313 return false;
1314
1315 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1316 return false;
1317
1318 EVT VT = Op.getValueType();
1319 if (VT.isVector() || !VT.isInteger())
1320 return false;
1321
1322 // If operation type is 'undesirable', e.g. i16 on x86, consider
1323 // promoting it.
1324 unsigned Opc = Op.getOpcode();
1325 if (TLI.isTypeDesirableForOp(Opc, VT))
1326 return false;
1327
1328 EVT PVT = VT;
1329 // Consult target whether it is a good idea to promote this operation and
1330 // what's the right type to promote it to.
1331 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1332 assert(PVT != VT && "Don't know what type to promote to!")(static_cast <bool> (PVT != VT && "Don't know what type to promote to!"
) ? void (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1332, __extension__ __PRETTY_FUNCTION__))
;
1333
1334 SDLoc DL(Op);
1335 SDNode *N = Op.getNode();
1336 LoadSDNode *LD = cast<LoadSDNode>(N);
1337 EVT MemVT = LD->getMemoryVT();
1338 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1339 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1340 : ISD::EXTLOAD)
1341 : LD->getExtensionType();
1342 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1343 LD->getChain(), LD->getBasePtr(),
1344 MemVT, LD->getMemOperand());
1345 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1346
1347 DEBUG(dbgs() << "\nPromoting ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1348 N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1349 dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1350 Result.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1351 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1352 WorklistRemover DeadNodes(*this);
1353 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1354 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1355 deleteAndRecombine(N);
1356 AddToWorklist(Result.getNode());
1357 return true;
1358 }
1359 return false;
1360}
1361
1362/// \brief Recursively delete a node which has no uses and any operands for
1363/// which it is the only use.
1364///
1365/// Note that this both deletes the nodes and removes them from the worklist.
1366/// It also adds any nodes who have had a user deleted to the worklist as they
1367/// may now have only one use and subject to other combines.
1368bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1369 if (!N->use_empty())
1370 return false;
1371
1372 SmallSetVector<SDNode *, 16> Nodes;
1373 Nodes.insert(N);
1374 do {
1375 N = Nodes.pop_back_val();
1376 if (!N)
1377 continue;
1378
1379 if (N->use_empty()) {
1380 for (const SDValue &ChildN : N->op_values())
1381 Nodes.insert(ChildN.getNode());
1382
1383 removeFromWorklist(N);
1384 DAG.DeleteNode(N);
1385 } else {
1386 AddToWorklist(N);
1387 }
1388 } while (!Nodes.empty());
1389 return true;
1390}
1391
1392//===----------------------------------------------------------------------===//
1393// Main DAG Combiner implementation
1394//===----------------------------------------------------------------------===//
1395
1396void DAGCombiner::Run(CombineLevel AtLevel) {
1397 // set the instance variables, so that the various visit routines may use it.
1398 Level = AtLevel;
1399 LegalOperations = Level >= AfterLegalizeVectorOps;
1400 LegalTypes = Level >= AfterLegalizeTypes;
1401
1402 // Add all the dag nodes to the worklist.
1403 for (SDNode &Node : DAG.allnodes())
1404 AddToWorklist(&Node);
1405
1406 // Create a dummy node (which is not added to allnodes), that adds a reference
1407 // to the root node, preventing it from being deleted, and tracking any
1408 // changes of the root.
1409 HandleSDNode Dummy(DAG.getRoot());
1410
1411 // While the worklist isn't empty, find a node and try to combine it.
1412 while (!WorklistMap.empty()) {
1413 SDNode *N;
1414 // The Worklist holds the SDNodes in order, but it may contain null entries.
1415 do {
1416 N = Worklist.pop_back_val();
1417 } while (!N);
1418
1419 bool GoodWorklistEntry = WorklistMap.erase(N);
1420 (void)GoodWorklistEntry;
1421 assert(GoodWorklistEntry &&(static_cast <bool> (GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? void (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1422, __extension__ __PRETTY_FUNCTION__))
1422 "Found a worklist entry without a corresponding map entry!")(static_cast <bool> (GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? void (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1422, __extension__ __PRETTY_FUNCTION__))
;
1423
1424 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1425 // N is deleted from the DAG, since they too may now be dead or may have a
1426 // reduced number of uses, allowing other xforms.
1427 if (recursivelyDeleteUnusedNodes(N))
1428 continue;
1429
1430 WorklistRemover DeadNodes(*this);
1431
1432 // If this combine is running after legalizing the DAG, re-legalize any
1433 // nodes pulled off the worklist.
1434 if (Level == AfterLegalizeDAG) {
1435 SmallSetVector<SDNode *, 16> UpdatedNodes;
1436 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1437
1438 for (SDNode *LN : UpdatedNodes) {
1439 AddToWorklist(LN);
1440 AddUsersToWorklist(LN);
1441 }
1442 if (!NIsValid)
1443 continue;
1444 }
1445
1446 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1447
1448 // Add any operands of the new node which have not yet been combined to the
1449 // worklist as well. Because the worklist uniques things already, this
1450 // won't repeatedly process the same operand.
1451 CombinedNodes.insert(N);
1452 for (const SDValue &ChildN : N->op_values())
1453 if (!CombinedNodes.count(ChildN.getNode()))
1454 AddToWorklist(ChildN.getNode());
1455
1456 SDValue RV = combine(N);
1457
1458 if (!RV.getNode())
1459 continue;
1460
1461 ++NodesCombined;
1462
1463 // If we get back the same node we passed in, rather than a new node or
1464 // zero, we know that the node must have defined multiple values and
1465 // CombineTo was used. Since CombineTo takes care of the worklist
1466 // mechanics for us, we have no work to do in this case.
1467 if (RV.getNode() == N)
1468 continue;
1469
1470 assert(N->getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? void (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1472, __extension__ __PRETTY_FUNCTION__))
1471 RV.getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? void (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1472, __extension__ __PRETTY_FUNCTION__))
1472 "Node was deleted but visit returned new node!")(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& RV.getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? void (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1472, __extension__ __PRETTY_FUNCTION__))
;
1473
1474 DEBUG(dbgs() << " ... into: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
1475 RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1476
1477 if (N->getNumValues() == RV.getNode()->getNumValues())
1478 DAG.ReplaceAllUsesWith(N, RV.getNode());
1479 else {
1480 assert(N->getValueType(0) == RV.getValueType() &&(static_cast <bool> (N->getValueType(0) == RV.getValueType
() && N->getNumValues() == 1 && "Type mismatch"
) ? void (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1481, __extension__ __PRETTY_FUNCTION__))
1481 N->getNumValues() == 1 && "Type mismatch")(static_cast <bool> (N->getValueType(0) == RV.getValueType
() && N->getNumValues() == 1 && "Type mismatch"
) ? void (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1481, __extension__ __PRETTY_FUNCTION__))
;
1482 DAG.ReplaceAllUsesWith(N, &RV);
1483 }
1484
1485 // Push the new node and any users onto the worklist
1486 AddToWorklist(RV.getNode());
1487 AddUsersToWorklist(RV.getNode());
1488
1489 // Finally, if the node is now dead, remove it from the graph. The node
1490 // may not be dead if the replacement process recursively simplified to
1491 // something else needing this node. This will also take care of adding any
1492 // operands which have lost a user to the worklist.
1493 recursivelyDeleteUnusedNodes(N);
1494 }
1495
1496 // If the root changed (e.g. it was a dead load, update the root).
1497 DAG.setRoot(Dummy.getValue());
1498 DAG.RemoveDeadNodes();
1499}
1500
1501SDValue DAGCombiner::visit(SDNode *N) {
1502 switch (N->getOpcode()) {
1503 default: break;
1504 case ISD::TokenFactor: return visitTokenFactor(N);
1505 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1506 case ISD::ADD: return visitADD(N);
1507 case ISD::SUB: return visitSUB(N);
1508 case ISD::ADDC: return visitADDC(N);
1509 case ISD::UADDO: return visitUADDO(N);
1510 case ISD::SUBC: return visitSUBC(N);
1511 case ISD::USUBO: return visitUSUBO(N);
1512 case ISD::ADDE: return visitADDE(N);
1513 case ISD::ADDCARRY: return visitADDCARRY(N);
1514 case ISD::SUBE: return visitSUBE(N);
1515 case ISD::SUBCARRY: return visitSUBCARRY(N);
1516 case ISD::MUL: return visitMUL(N);
1517 case ISD::SDIV: return visitSDIV(N);
1518 case ISD::UDIV: return visitUDIV(N);
1519 case ISD::SREM:
1520 case ISD::UREM: return visitREM(N);
1521 case ISD::MULHU: return visitMULHU(N);
1522 case ISD::MULHS: return visitMULHS(N);
1523 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1524 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1525 case ISD::SMULO: return visitSMULO(N);
1526 case ISD::UMULO: return visitUMULO(N);
1527 case ISD::SMIN:
1528 case ISD::SMAX:
1529 case ISD::UMIN:
1530 case ISD::UMAX: return visitIMINMAX(N);
1531 case ISD::AND: return visitAND(N);
1532 case ISD::OR: return visitOR(N);
1533 case ISD::XOR: return visitXOR(N);
1534 case ISD::SHL: return visitSHL(N);
1535 case ISD::SRA: return visitSRA(N);
1536 case ISD::SRL: return visitSRL(N);
1537 case ISD::ROTR:
1538 case ISD::ROTL: return visitRotate(N);
1539 case ISD::ABS: return visitABS(N);
1540 case ISD::BSWAP: return visitBSWAP(N);
1541 case ISD::BITREVERSE: return visitBITREVERSE(N);
1542 case ISD::CTLZ: return visitCTLZ(N);
1543 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1544 case ISD::CTTZ: return visitCTTZ(N);
1545 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1546 case ISD::CTPOP: return visitCTPOP(N);
1547 case ISD::SELECT: return visitSELECT(N);
1548 case ISD::VSELECT: return visitVSELECT(N);
1549 case ISD::SELECT_CC: return visitSELECT_CC(N);
1550 case ISD::SETCC: return visitSETCC(N);
1551 case ISD::SETCCE: return visitSETCCE(N);
1552 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1553 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1554 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1555 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1556 case ISD::AssertSext:
1557 case ISD::AssertZext: return visitAssertExt(N);
1558 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1559 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1560 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
1561 case ISD::TRUNCATE: return visitTRUNCATE(N);
1562 case ISD::BITCAST: return visitBITCAST(N);
1563 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1564 case ISD::FADD: return visitFADD(N);
1565 case ISD::FSUB: return visitFSUB(N);
1566 case ISD::FMUL: return visitFMUL(N);
1567 case ISD::FMA: return visitFMA(N);
1568 case ISD::FDIV: return visitFDIV(N);
1569 case ISD::FREM: return visitFREM(N);
1570 case ISD::FSQRT: return visitFSQRT(N);
1571 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1572 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1573 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1574 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1575 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1576 case ISD::FP_ROUND: return visitFP_ROUND(N);
1577 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1578 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1579 case ISD::FNEG: return visitFNEG(N);
1580 case ISD::FABS: return visitFABS(N);
1581 case ISD::FFLOOR: return visitFFLOOR(N);
1582 case ISD::FMINNUM: return visitFMINNUM(N);
1583 case ISD::FMAXNUM: return visitFMAXNUM(N);
1584 case ISD::FCEIL: return visitFCEIL(N);
1585 case ISD::FTRUNC: return visitFTRUNC(N);
1586 case ISD::BRCOND: return visitBRCOND(N);
1587 case ISD::BR_CC: return visitBR_CC(N);
1588 case ISD::LOAD: return visitLOAD(N);
1589 case ISD::STORE: return visitSTORE(N);
1590 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1591 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1592 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1593 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1594 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1595 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1596 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1597 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1598 case ISD::MGATHER: return visitMGATHER(N);
1599 case ISD::MLOAD: return visitMLOAD(N);
1600 case ISD::MSCATTER: return visitMSCATTER(N);
1601 case ISD::MSTORE: return visitMSTORE(N);
1602 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1603 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1604 }
1605 return SDValue();
1606}
1607
1608SDValue DAGCombiner::combine(SDNode *N) {
1609 SDValue RV = visit(N);
1610
1611 // If nothing happened, try a target-specific DAG combine.
1612 if (!RV.getNode()) {
1613 assert(N->getOpcode() != ISD::DELETED_NODE &&(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Node was deleted but visit returned NULL!") ? void
(0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1614, __extension__ __PRETTY_FUNCTION__))
1614 "Node was deleted but visit returned NULL!")(static_cast <bool> (N->getOpcode() != ISD::DELETED_NODE
&& "Node was deleted but visit returned NULL!") ? void
(0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1614, __extension__ __PRETTY_FUNCTION__))
;
1615
1616 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1617 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1618
1619 // Expose the DAG combiner to the target combiner impls.
1620 TargetLowering::DAGCombinerInfo
1621 DagCombineInfo(DAG, Level, false, this);
1622
1623 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1624 }
1625 }
1626
1627 // If nothing happened still, try promoting the operation.
1628 if (!RV.getNode()) {
1629 switch (N->getOpcode()) {
1630 default: break;
1631 case ISD::ADD:
1632 case ISD::SUB:
1633 case ISD::MUL:
1634 case ISD::AND:
1635 case ISD::OR:
1636 case ISD::XOR:
1637 RV = PromoteIntBinOp(SDValue(N, 0));
1638 break;
1639 case ISD::SHL:
1640 case ISD::SRA:
1641 case ISD::SRL:
1642 RV = PromoteIntShiftOp(SDValue(N, 0));
1643 break;
1644 case ISD::SIGN_EXTEND:
1645 case ISD::ZERO_EXTEND:
1646 case ISD::ANY_EXTEND:
1647 RV = PromoteExtend(SDValue(N, 0));
1648 break;
1649 case ISD::LOAD:
1650 if (PromoteLoad(SDValue(N, 0)))
1651 RV = SDValue(N, 0);
1652 break;
1653 }
1654 }
1655
1656 // If N is a commutative binary node, try eliminate it if the commuted
1657 // version is already present in the DAG.
1658 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1659 N->getNumValues() == 1) {
1660 SDValue N0 = N->getOperand(0);
1661 SDValue N1 = N->getOperand(1);
1662
1663 // Constant operands are canonicalized to RHS.
1664 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1665 SDValue Ops[] = {N1, N0};
1666 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1667 N->getFlags());
1668 if (CSENode)
1669 return SDValue(CSENode, 0);
1670 }
1671 }
1672
1673 return RV;
1674}
1675
1676/// Given a node, return its input chain if it has one, otherwise return a null
1677/// sd operand.
1678static SDValue getInputChainForNode(SDNode *N) {
1679 if (unsigned NumOps = N->getNumOperands()) {
1680 if (N->getOperand(0).getValueType() == MVT::Other)
1681 return N->getOperand(0);
1682 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1683 return N->getOperand(NumOps-1);
1684 for (unsigned i = 1; i < NumOps-1; ++i)
1685 if (N->getOperand(i).getValueType() == MVT::Other)
1686 return N->getOperand(i);
1687 }
1688 return SDValue();
1689}
1690
1691SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1692 // If N has two operands, where one has an input chain equal to the other,
1693 // the 'other' chain is redundant.
1694 if (N->getNumOperands() == 2) {
1695 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1696 return N->getOperand(0);
1697 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1698 return N->getOperand(1);
1699 }
1700
1701 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1702 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1703 SmallPtrSet<SDNode*, 16> SeenOps;
1704 bool Changed = false; // If we should replace this token factor.
1705
1706 // Start out with this token factor.
1707 TFs.push_back(N);
1708
1709 // Iterate through token factors. The TFs grows when new token factors are
1710 // encountered.
1711 for (unsigned i = 0; i < TFs.size(); ++i) {
1712 SDNode *TF = TFs[i];
1713
1714 // Check each of the operands.
1715 for (const SDValue &Op : TF->op_values()) {
1716 switch (Op.getOpcode()) {
1717 case ISD::EntryToken:
1718 // Entry tokens don't need to be added to the list. They are
1719 // redundant.
1720 Changed = true;
1721 break;
1722
1723 case ISD::TokenFactor:
1724 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1725 // Queue up for processing.
1726 TFs.push_back(Op.getNode());
1727 // Clean up in case the token factor is removed.
1728 AddToWorklist(Op.getNode());
1729 Changed = true;
1730 break;
1731 }
1732 LLVM_FALLTHROUGH[[clang::fallthrough]];
1733
1734 default:
1735 // Only add if it isn't already in the list.
1736 if (SeenOps.insert(Op.getNode()).second)
1737 Ops.push_back(Op);
1738 else
1739 Changed = true;
1740 break;
1741 }
1742 }
1743 }
1744
1745 // Remove Nodes that are chained to another node in the list. Do so
1746 // by walking up chains breath-first stopping when we've seen
1747 // another operand. In general we must climb to the EntryNode, but we can exit
1748 // early if we find all remaining work is associated with just one operand as
1749 // no further pruning is possible.
1750
1751 // List of nodes to search through and original Ops from which they originate.
1752 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1753 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1754 SmallPtrSet<SDNode *, 16> SeenChains;
1755 bool DidPruneOps = false;
1756
1757 unsigned NumLeftToConsider = 0;
1758 for (const SDValue &Op : Ops) {
1759 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1760 OpWorkCount.push_back(1);
1761 }
1762
1763 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1764 // If this is an Op, we can remove the op from the list. Remark any
1765 // search associated with it as from the current OpNumber.
1766 if (SeenOps.count(Op) != 0) {
1767 Changed = true;
1768 DidPruneOps = true;
1769 unsigned OrigOpNumber = 0;
1770 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1771 OrigOpNumber++;
1772 assert((OrigOpNumber != Ops.size()) &&(static_cast <bool> ((OrigOpNumber != Ops.size()) &&
"expected to find TokenFactor Operand") ? void (0) : __assert_fail
("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1773, __extension__ __PRETTY_FUNCTION__))
1773 "expected to find TokenFactor Operand")(static_cast <bool> ((OrigOpNumber != Ops.size()) &&
"expected to find TokenFactor Operand") ? void (0) : __assert_fail
("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1773, __extension__ __PRETTY_FUNCTION__))
;
1774 // Re-mark worklist from OrigOpNumber to OpNumber
1775 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1776 if (Worklist[i].second == OrigOpNumber) {
1777 Worklist[i].second = OpNumber;
1778 }
1779 }
1780 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1781 OpWorkCount[OrigOpNumber] = 0;
1782 NumLeftToConsider--;
1783 }
1784 // Add if it's a new chain
1785 if (SeenChains.insert(Op).second) {
1786 OpWorkCount[OpNumber]++;
1787 Worklist.push_back(std::make_pair(Op, OpNumber));
1788 }
1789 };
1790
1791 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1792 // We need at least be consider at least 2 Ops to prune.
1793 if (NumLeftToConsider <= 1)
1794 break;
1795 auto CurNode = Worklist[i].first;
1796 auto CurOpNumber = Worklist[i].second;
1797 assert((OpWorkCount[CurOpNumber] > 0) &&(static_cast <bool> ((OpWorkCount[CurOpNumber] > 0) &&
"Node should not appear in worklist") ? void (0) : __assert_fail
("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1798, __extension__ __PRETTY_FUNCTION__))
1798 "Node should not appear in worklist")(static_cast <bool> ((OpWorkCount[CurOpNumber] > 0) &&
"Node should not appear in worklist") ? void (0) : __assert_fail
("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1798, __extension__ __PRETTY_FUNCTION__))
;
1799 switch (CurNode->getOpcode()) {
1800 case ISD::EntryToken:
1801 // Hitting EntryToken is the only way for the search to terminate without
1802 // hitting
1803 // another operand's search. Prevent us from marking this operand
1804 // considered.
1805 NumLeftToConsider++;
1806 break;
1807 case ISD::TokenFactor:
1808 for (const SDValue &Op : CurNode->op_values())
1809 AddToWorklist(i, Op.getNode(), CurOpNumber);
1810 break;
1811 case ISD::CopyFromReg:
1812 case ISD::CopyToReg:
1813 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1814 break;
1815 default:
1816 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1817 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1818 break;
1819 }
1820 OpWorkCount[CurOpNumber]--;
1821 if (OpWorkCount[CurOpNumber] == 0)
1822 NumLeftToConsider--;
1823 }
1824
1825 // If we've changed things around then replace token factor.
1826 if (Changed) {
1827 SDValue Result;
1828 if (Ops.empty()) {
1829 // The entry token is the only possible outcome.
1830 Result = DAG.getEntryNode();
1831 } else {
1832 if (DidPruneOps) {
1833 SmallVector<SDValue, 8> PrunedOps;
1834 //
1835 for (const SDValue &Op : Ops) {
1836 if (SeenChains.count(Op.getNode()) == 0)
1837 PrunedOps.push_back(Op);
1838 }
1839 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, PrunedOps);
1840 } else {
1841 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1842 }
1843 }
1844 return Result;
1845 }
1846 return SDValue();
1847}
1848
1849/// MERGE_VALUES can always be eliminated.
1850SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1851 WorklistRemover DeadNodes(*this);
1852 // Replacing results may cause a different MERGE_VALUES to suddenly
1853 // be CSE'd with N, and carry its uses with it. Iterate until no
1854 // uses remain, to ensure that the node can be safely deleted.
1855 // First add the users of this node to the work list so that they
1856 // can be tried again once they have new operands.
1857 AddUsersToWorklist(N);
1858 do {
1859 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1860 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1861 } while (!N->use_empty());
1862 deleteAndRecombine(N);
1863 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1864}
1865
1866/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
1867/// ConstantSDNode pointer else nullptr.
1868static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1869 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1870 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1871}
1872
1873SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
1874 auto BinOpcode = BO->getOpcode();
1875 assert((BinOpcode == ISD::ADD || BinOpcode == ISD::SUB ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1876 BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1877 BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1878 BinOpcode == ISD::UREM || BinOpcode == ISD::AND ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1879 BinOpcode == ISD::OR || BinOpcode == ISD::XOR ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1880 BinOpcode == ISD::SHL || BinOpcode == ISD::SRL ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1881 BinOpcode == ISD::SRA || BinOpcode == ISD::FADD ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1882 BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL ||(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1883 BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) &&(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
1884 "Unexpected binary operator")(static_cast <bool> ((BinOpcode == ISD::ADD || BinOpcode
== ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV
|| BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode
== ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR
|| BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode
== ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD
|| BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode
== ISD::FDIV || BinOpcode == ISD::FREM) && "Unexpected binary operator"
) ? void (0) : __assert_fail ("(BinOpcode == ISD::ADD || BinOpcode == ISD::SUB || BinOpcode == ISD::MUL || BinOpcode == ISD::SDIV || BinOpcode == ISD::UDIV || BinOpcode == ISD::SREM || BinOpcode == ISD::UREM || BinOpcode == ISD::AND || BinOpcode == ISD::OR || BinOpcode == ISD::XOR || BinOpcode == ISD::SHL || BinOpcode == ISD::SRL || BinOpcode == ISD::SRA || BinOpcode == ISD::FADD || BinOpcode == ISD::FSUB || BinOpcode == ISD::FMUL || BinOpcode == ISD::FDIV || BinOpcode == ISD::FREM) && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1884, __extension__ __PRETTY_FUNCTION__))
;
1885
1886 // Bail out if any constants are opaque because we can't constant fold those.
1887 SDValue C1 = BO->getOperand(1);
1888 if (!isConstantOrConstantVector(C1, true) &&
1889 !isConstantFPBuildVectorOrConstantFP(C1))
1890 return SDValue();
1891
1892 // Don't do this unless the old select is going away. We want to eliminate the
1893 // binary operator, not replace a binop with a select.
1894 // TODO: Handle ISD::SELECT_CC.
1895 SDValue Sel = BO->getOperand(0);
1896 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
1897 return SDValue();
1898
1899 SDValue CT = Sel.getOperand(1);
1900 if (!isConstantOrConstantVector(CT, true) &&
1901 !isConstantFPBuildVectorOrConstantFP(CT))
1902 return SDValue();
1903
1904 SDValue CF = Sel.getOperand(2);
1905 if (!isConstantOrConstantVector(CF, true) &&
1906 !isConstantFPBuildVectorOrConstantFP(CF))
1907 return SDValue();
1908
1909 // We have a select-of-constants followed by a binary operator with a
1910 // constant. Eliminate the binop by pulling the constant math into the select.
1911 // Example: add (select Cond, CT, CF), C1 --> select Cond, CT + C1, CF + C1
1912 EVT VT = Sel.getValueType();
1913 SDLoc DL(Sel);
1914 SDValue NewCT = DAG.getNode(BinOpcode, DL, VT, CT, C1);
1915 assert((NewCT.isUndef() || isConstantOrConstantVector(NewCT) ||(static_cast <bool> ((NewCT.isUndef() || isConstantOrConstantVector
(NewCT) || isConstantFPBuildVectorOrConstantFP(NewCT)) &&
"Failed to constant fold a binop with constant operands") ? void
(0) : __assert_fail ("(NewCT.isUndef() || isConstantOrConstantVector(NewCT) || isConstantFPBuildVectorOrConstantFP(NewCT)) && \"Failed to constant fold a binop with constant operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1917, __extension__ __PRETTY_FUNCTION__))
1916 isConstantFPBuildVectorOrConstantFP(NewCT)) &&(static_cast <bool> ((NewCT.isUndef() || isConstantOrConstantVector
(NewCT) || isConstantFPBuildVectorOrConstantFP(NewCT)) &&
"Failed to constant fold a binop with constant operands") ? void
(0) : __assert_fail ("(NewCT.isUndef() || isConstantOrConstantVector(NewCT) || isConstantFPBuildVectorOrConstantFP(NewCT)) && \"Failed to constant fold a binop with constant operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1917, __extension__ __PRETTY_FUNCTION__))
1917 "Failed to constant fold a binop with constant operands")(static_cast <bool> ((NewCT.isUndef() || isConstantOrConstantVector
(NewCT) || isConstantFPBuildVectorOrConstantFP(NewCT)) &&
"Failed to constant fold a binop with constant operands") ? void
(0) : __assert_fail ("(NewCT.isUndef() || isConstantOrConstantVector(NewCT) || isConstantFPBuildVectorOrConstantFP(NewCT)) && \"Failed to constant fold a binop with constant operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1917, __extension__ __PRETTY_FUNCTION__))
;
1918
1919 SDValue NewCF = DAG.getNode(BinOpcode, DL, VT, CF, C1);
1920 assert((NewCF.isUndef() || isConstantOrConstantVector(NewCF) ||(static_cast <bool> ((NewCF.isUndef() || isConstantOrConstantVector
(NewCF) || isConstantFPBuildVectorOrConstantFP(NewCF)) &&
"Failed to constant fold a binop with constant operands") ? void
(0) : __assert_fail ("(NewCF.isUndef() || isConstantOrConstantVector(NewCF) || isConstantFPBuildVectorOrConstantFP(NewCF)) && \"Failed to constant fold a binop with constant operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1922, __extension__ __PRETTY_FUNCTION__))
1921 isConstantFPBuildVectorOrConstantFP(NewCF)) &&(static_cast <bool> ((NewCF.isUndef() || isConstantOrConstantVector
(NewCF) || isConstantFPBuildVectorOrConstantFP(NewCF)) &&
"Failed to constant fold a binop with constant operands") ? void
(0) : __assert_fail ("(NewCF.isUndef() || isConstantOrConstantVector(NewCF) || isConstantFPBuildVectorOrConstantFP(NewCF)) && \"Failed to constant fold a binop with constant operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1922, __extension__ __PRETTY_FUNCTION__))
1922 "Failed to constant fold a binop with constant operands")(static_cast <bool> ((NewCF.isUndef() || isConstantOrConstantVector
(NewCF) || isConstantFPBuildVectorOrConstantFP(NewCF)) &&
"Failed to constant fold a binop with constant operands") ? void
(0) : __assert_fail ("(NewCF.isUndef() || isConstantOrConstantVector(NewCF) || isConstantFPBuildVectorOrConstantFP(NewCF)) && \"Failed to constant fold a binop with constant operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1922, __extension__ __PRETTY_FUNCTION__))
;
1923
1924 return DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
1925}
1926
1927SDValue DAGCombiner::visitADD(SDNode *N) {
1928 SDValue N0 = N->getOperand(0);
1929 SDValue N1 = N->getOperand(1);
1930 EVT VT = N0.getValueType();
1931 SDLoc DL(N);
1932
1933 // fold vector ops
1934 if (VT.isVector()) {
1935 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1936 return FoldedVOp;
1937
1938 // fold (add x, 0) -> x, vector edition
1939 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1940 return N0;
1941 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1942 return N1;
1943 }
1944
1945 // fold (add x, undef) -> undef
1946 if (N0.isUndef())
1947 return N0;
1948
1949 if (N1.isUndef())
1950 return N1;
1951
1952 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
1953 // canonicalize constant to RHS
1954 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
1955 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
1956 // fold (add c1, c2) -> c1+c2
1957 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, N0.getNode(),
1958 N1.getNode());
1959 }
1960
1961 // fold (add x, 0) -> x
1962 if (isNullConstant(N1))
1963 return N0;
1964
1965 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
1966 // fold ((c1-A)+c2) -> (c1+c2)-A
1967 if (N0.getOpcode() == ISD::SUB &&
1968 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
1969 // FIXME: Adding 2 constants should be handled by FoldConstantArithmetic.
1970 return DAG.getNode(ISD::SUB, DL, VT,
1971 DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
1972 N0.getOperand(1));
1973 }
1974
1975 // add (sext i1 X), 1 -> zext (not i1 X)
1976 // We don't transform this pattern:
1977 // add (zext i1 X), -1 -> sext (not i1 X)
1978 // because most (?) targets generate better code for the zext form.
1979 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
1980 isOneConstantOrOneSplatConstant(N1)) {
1981 SDValue X = N0.getOperand(0);
1982 if ((!LegalOperations ||
1983 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
1984 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
1985 X.getScalarValueSizeInBits() == 1) {
1986 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
1987 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
1988 }
1989 }
1990
1991 // Undo the add -> or combine to merge constant offsets from a frame index.
1992 if (N0.getOpcode() == ISD::OR &&
1993 isa<FrameIndexSDNode>(N0.getOperand(0)) &&
1994 isa<ConstantSDNode>(N0.getOperand(1)) &&
1995 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
1996 SDValue Add0 = DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(1));
1997 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
1998 }
1999 }
2000
2001 if (SDValue NewSel = foldBinOpIntoSelect(N))
2002 return NewSel;
2003
2004 // reassociate add
2005 if (SDValue RADD = ReassociateOps(ISD::ADD, DL, N0, N1))
2006 return RADD;
2007
2008 // fold ((0-A) + B) -> B-A
2009 if (N0.getOpcode() == ISD::SUB &&
2010 isNullConstantOrNullSplatConstant(N0.getOperand(0)))
2011 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2012
2013 // fold (A + (0-B)) -> A-B
2014 if (N1.getOpcode() == ISD::SUB &&
2015 isNullConstantOrNullSplatConstant(N1.getOperand(0)))
2016 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2017
2018 // fold (A+(B-A)) -> B
2019 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2020 return N1.getOperand(0);
2021
2022 // fold ((B-A)+A) -> B
2023 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2024 return N0.getOperand(0);
2025
2026 // fold (A+(B-(A+C))) to (B-C)
2027 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2028 N0 == N1.getOperand(1).getOperand(0))
2029 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2030 N1.getOperand(1).getOperand(1));
2031
2032 // fold (A+(B-(C+A))) to (B-C)
2033 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2034 N0 == N1.getOperand(1).getOperand(1))
2035 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2036 N1.getOperand(1).getOperand(0));
2037
2038 // fold (A+((B-A)+or-C)) to (B+or-C)
2039 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2040 N1.getOperand(0).getOpcode() == ISD::SUB &&
2041 N0 == N1.getOperand(0).getOperand(1))
2042 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2043 N1.getOperand(1));
2044
2045 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2046 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2047 SDValue N00 = N0.getOperand(0);
2048 SDValue N01 = N0.getOperand(1);
2049 SDValue N10 = N1.getOperand(0);
2050 SDValue N11 = N1.getOperand(1);
2051
2052 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2053 return DAG.getNode(ISD::SUB, DL, VT,
2054 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2055 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2056 }
2057
2058 if (SimplifyDemandedBits(SDValue(N, 0)))
2059 return SDValue(N, 0);
2060
2061 // fold (a+b) -> (a|b) iff a and b share no bits.
2062 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2063 DAG.haveNoCommonBitsSet(N0, N1))
2064 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2065
2066 if (SDValue Combined = visitADDLike(N0, N1, N))
2067 return Combined;
2068
2069 if (SDValue Combined = visitADDLike(N1, N0, N))
2070 return Combined;
2071
2072 return SDValue();
2073}
2074
2075static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2076 bool Masked = false;
2077
2078 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2079 while (true) {
2080 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2081 V = V.getOperand(0);
2082 continue;
2083 }
2084
2085 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2086 Masked = true;
2087 V = V.getOperand(0);
2088 continue;
2089 }
2090
2091 break;
2092 }
2093
2094 // If this is not a carry, return.
2095 if (V.getResNo() != 1)
2096 return SDValue();
2097
2098 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2099 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2100 return SDValue();
2101
2102 // If the result is masked, then no matter what kind of bool it is we can
2103 // return. If it isn't, then we need to make sure the bool type is either 0 or
2104 // 1 and not other values.
2105 if (Masked ||
2106 TLI.getBooleanContents(V.getValueType()) ==
2107 TargetLoweringBase::ZeroOrOneBooleanContent)
2108 return V;
2109
2110 return SDValue();
2111}
2112
2113SDValue DAGCombiner::visitADDLike(SDValue N0, SDValue N1, SDNode *LocReference) {
2114 EVT VT = N0.getValueType();
2115 SDLoc DL(LocReference);
2116
2117 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2118 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2119 isNullConstantOrNullSplatConstant(N1.getOperand(0).getOperand(0)))
2120 return DAG.getNode(ISD::SUB, DL, VT, N0,
2121 DAG.getNode(ISD::SHL, DL, VT,
2122 N1.getOperand(0).getOperand(1),
2123 N1.getOperand(1)));
2124
2125 if (N1.getOpcode() == ISD::AND) {
2126 SDValue AndOp0 = N1.getOperand(0);
2127 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
2128 unsigned DestBits = VT.getScalarSizeInBits();
2129
2130 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
2131 // and similar xforms where the inner op is either ~0 or 0.
2132 if (NumSignBits == DestBits &&
2133 isOneConstantOrOneSplatConstant(N1->getOperand(1)))
2134 return DAG.getNode(ISD::SUB, DL, VT, N0, AndOp0);
2135 }
2136
2137 // add (sext i1), X -> sub X, (zext i1)
2138 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2139 N0.getOperand(0).getValueType() == MVT::i1 &&
2140 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
2141 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2142 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2143 }
2144
2145 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2146 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2147 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2148 if (TN->getVT() == MVT::i1) {
2149 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2150 DAG.getConstant(1, DL, VT));
2151 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2152 }
2153 }
2154
2155 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2156 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)))
2157 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2158 N0, N1.getOperand(0), N1.getOperand(2));
2159
2160 // (add X, Carry) -> (addcarry X, 0, Carry)
2161 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2162 if (SDValue Carry = getAsCarry(TLI, N1))
2163 return DAG.getNode(ISD::ADDCARRY, DL,
2164 DAG.getVTList(VT, Carry.getValueType()), N0,
2165 DAG.getConstant(0, DL, VT), Carry);
2166
2167 return SDValue();
2168}
2169
2170SDValue DAGCombiner::visitADDC(SDNode *N) {
2171 SDValue N0 = N->getOperand(0);
2172 SDValue N1 = N->getOperand(1);
2173 EVT VT = N0.getValueType();
2174 SDLoc DL(N);
2175
2176 // If the flag result is dead, turn this into an ADD.
2177 if (!N->hasAnyUseOfValue(1))
2178 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2179 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2180
2181 // canonicalize constant to RHS.
2182 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2183 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2184 if (N0C && !N1C)
2185 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2186
2187 // fold (addc x, 0) -> x + no carry out
2188 if (isNullConstant(N1))
2189 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2190 DL, MVT::Glue));
2191
2192 // If it cannot overflow, transform into an add.
2193 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2194 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2195 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2196
2197 return SDValue();
2198}
2199
2200SDValue DAGCombiner::visitUADDO(SDNode *N) {
2201 SDValue N0 = N->getOperand(0);
2202 SDValue N1 = N->getOperand(1);
2203 EVT VT = N0.getValueType();
2204 if (VT.isVector())
2205 return SDValue();
2206
2207 EVT CarryVT = N->getValueType(1);
2208 SDLoc DL(N);
2209
2210 // If the flag result is dead, turn this into an ADD.
2211 if (!N->hasAnyUseOfValue(1))
2212 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2213 DAG.getUNDEF(CarryVT));
2214
2215 // canonicalize constant to RHS.
2216 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2217 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2218 if (N0C && !N1C)
2219 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N1, N0);
2220
2221 // fold (uaddo x, 0) -> x + no carry out
2222 if (isNullConstant(N1))
2223 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2224
2225 // If it cannot overflow, transform into an add.
2226 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2227 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2228 DAG.getConstant(0, DL, CarryVT));
2229
2230 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2231 return Combined;
2232
2233 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2234 return Combined;
2235
2236 return SDValue();
2237}
2238
2239SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2240 auto VT = N0.getValueType();
2241
2242 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2243 // If Y + 1 cannot overflow.
2244 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2245 SDValue Y = N1.getOperand(0);
2246 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2247 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2248 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2249 N1.getOperand(2));
2250 }
2251
2252 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2253 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2254 if (SDValue Carry = getAsCarry(TLI, N1))
2255 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2256 DAG.getConstant(0, SDLoc(N), VT), Carry);
2257
2258 return SDValue();
2259}
2260
2261SDValue DAGCombiner::visitADDE(SDNode *N) {
2262 SDValue N0 = N->getOperand(0);
2263 SDValue N1 = N->getOperand(1);
2264 SDValue CarryIn = N->getOperand(2);
2265
2266 // canonicalize constant to RHS
2267 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2268 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2269 if (N0C && !N1C)
2270 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2271 N1, N0, CarryIn);
2272
2273 // fold (adde x, y, false) -> (addc x, y)
2274 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2275 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2276
2277 return SDValue();
2278}
2279
2280SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2281 SDValue N0 = N->getOperand(0);
2282 SDValue N1 = N->getOperand(1);
2283 SDValue CarryIn = N->getOperand(2);
2284 SDLoc DL(N);
2285
2286 // canonicalize constant to RHS
2287 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2288 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2289 if (N0C && !N1C)
2290 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2291
2292 // fold (addcarry x, y, false) -> (uaddo x, y)
2293 if (isNullConstant(CarryIn))
2294 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2295
2296 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2297 if (isNullConstant(N0) && isNullConstant(N1)) {
2298 EVT VT = N0.getValueType();
2299 EVT CarryVT = CarryIn.getValueType();
2300 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2301 AddToWorklist(CarryExt.getNode());
2302 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2303 DAG.getConstant(1, DL, VT)),
2304 DAG.getConstant(0, DL, CarryVT));
2305 }
2306
2307 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2308 return Combined;
2309
2310 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2311 return Combined;
2312
2313 return SDValue();
2314}
2315
2316SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
2317 SDNode *N) {
2318 // Iff the flag result is dead:
2319 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
2320 if ((N0.getOpcode() == ISD::ADD ||
2321 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0)) &&
2322 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
2323 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
2324 N0.getOperand(0), N0.getOperand(1), CarryIn);
2325
2326 /**
2327 * When one of the addcarry argument is itself a carry, we may be facing
2328 * a diamond carry propagation. In which case we try to transform the DAG
2329 * to ensure linear carry propagation if that is possible.
2330 *
2331 * We are trying to get:
2332 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2333 */
2334 if (auto Y = getAsCarry(TLI, N1)) {
2335 /**
2336 * (uaddo A, B)
2337 * / \
2338 * Carry Sum
2339 * | \
2340 * | (addcarry *, 0, Z)
2341 * | /
2342 * \ Carry
2343 * | /
2344 * (addcarry X, *, *)
2345 */
2346 if (Y.getOpcode() == ISD::UADDO &&
2347 CarryIn.getResNo() == 1 &&
2348 CarryIn.getOpcode() == ISD::ADDCARRY &&
2349 isNullConstant(CarryIn.getOperand(1)) &&
2350 CarryIn.getOperand(0) == Y.getValue(0)) {
2351 auto NewY = DAG.getNode(ISD::ADDCARRY, SDLoc(N), Y->getVTList(),
2352 Y.getOperand(0), Y.getOperand(1),
2353 CarryIn.getOperand(2));
2354 AddToWorklist(NewY.getNode());
2355 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2356 DAG.getConstant(0, SDLoc(N), N0.getValueType()),
2357 NewY.getValue(1));
2358 }
2359 }
2360
2361 return SDValue();
2362}
2363
2364// Since it may not be valid to emit a fold to zero for vector initializers
2365// check if we can before folding.
2366static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
2367 SelectionDAG &DAG, bool LegalOperations,
2368 bool LegalTypes) {
2369 if (!VT.isVector())
2370 return DAG.getConstant(0, DL, VT);
2371 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
2372 return DAG.getConstant(0, DL, VT);
2373 return SDValue();
2374}
2375
2376SDValue DAGCombiner::visitSUB(SDNode *N) {
2377 SDValue N0 = N->getOperand(0);
2378 SDValue N1 = N->getOperand(1);
2379 EVT VT = N0.getValueType();
2380 SDLoc DL(N);
2381
2382 // fold vector ops
2383 if (VT.isVector()) {
2384 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2385 return FoldedVOp;
2386
2387 // fold (sub x, 0) -> x, vector edition
2388 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2389 return N0;
2390 }
2391
2392 // fold (sub x, x) -> 0
2393 // FIXME: Refactor this and xor and other similar operations together.
2394 if (N0 == N1)
2395 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations, LegalTypes);
2396 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2397 DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
2398 // fold (sub c1, c2) -> c1-c2
2399 return DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, N0.getNode(),
2400 N1.getNode());
2401 }
2402
2403 if (SDValue NewSel = foldBinOpIntoSelect(N))
2404 return NewSel;
2405
2406 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
2407
2408 // fold (sub x, c) -> (add x, -c)
2409 if (N1C) {
2410 return DAG.getNode(ISD::ADD, DL, VT, N0,
2411 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
2412 }
2413
2414 if (isNullConstantOrNullSplatConstant(N0)) {
2415 unsigned BitWidth = VT.getScalarSizeInBits();
2416 // Right-shifting everything out but the sign bit followed by negation is
2417 // the same as flipping arithmetic/logical shift type without the negation:
2418 // -(X >>u 31) -> (X >>s 31)
2419 // -(X >>s 31) -> (X >>u 31)
2420 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
2421 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
2422 if (ShiftAmt && ShiftAmt->getZExtValue() == BitWidth - 1) {
2423 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
2424 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
2425 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
2426 }
2427 }
2428
2429 // 0 - X --> 0 if the sub is NUW.
2430 if (N->getFlags().hasNoUnsignedWrap())
2431 return N0;
2432
2433 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
2434 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
2435 // N1 must be 0 because negating the minimum signed value is undefined.
2436 if (N->getFlags().hasNoSignedWrap())
2437 return N0;
2438
2439 // 0 - X --> X if X is 0 or the minimum signed value.
2440 return N1;
2441 }
2442 }
2443
2444 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
2445 if (isAllOnesConstantOrAllOnesSplatConstant(N0))
2446 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
2447
2448 // fold A-(A-B) -> B
2449 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
2450 return N1.getOperand(1);
2451
2452 // fold (A+B)-A -> B
2453 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
2454 return N0.getOperand(1);
2455
2456 // fold (A+B)-B -> A
2457 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
2458 return N0.getOperand(0);
2459
2460 // fold C2-(A+C1) -> (C2-C1)-A
2461 if (N1.getOpcode() == ISD::ADD) {
2462 SDValue N11 = N1.getOperand(1);
2463 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
2464 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
2465 SDValue NewC = DAG.getNode(ISD::SUB, DL, VT, N0, N11);
2466 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
2467 }
2468 }
2469
2470 // fold ((A+(B+or-C))-B) -> A+or-C
2471 if (N0.getOpcode() == ISD::ADD &&
2472 (N0.getOperand(1).getOpcode() == ISD::SUB ||
2473 N0.getOperand(1).getOpcode() == ISD::ADD) &&
2474 N0.getOperand(1).getOperand(0) == N1)
2475 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
2476 N0.getOperand(1).getOperand(1));
2477
2478 // fold ((A+(C+B))-B) -> A+C
2479 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
2480 N0.getOperand(1).getOperand(1) == N1)
2481 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
2482 N0.getOperand(1).getOperand(0));
2483
2484 // fold ((A-(B-C))-C) -> A-B
2485 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
2486 N0.getOperand(1).getOperand(1) == N1)
2487 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2488 N0.getOperand(1).getOperand(0));
2489
2490 // If either operand of a sub is undef, the result is undef
2491 if (N0.isUndef())
2492 return N0;
2493 if (N1.isUndef())
2494 return N1;
2495
2496 // If the relocation model supports it, consider symbol offsets.
2497 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
2498 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
2499 // fold (sub Sym, c) -> Sym-c
2500 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
2501 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
2502 GA->getOffset() -
2503 (uint64_t)N1C->getSExtValue());
2504 // fold (sub Sym+c1, Sym+c2) -> c1-c2
2505 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
2506 if (GA->getGlobal() == GB->getGlobal())
2507 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
2508 DL, VT);
2509 }
2510
2511 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
2512 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2513 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2514 if (TN->getVT() == MVT::i1) {
2515 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2516 DAG.getConstant(1, DL, VT));
2517 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
2518 }
2519 }
2520
2521 return SDValue();
2522}
2523
2524SDValue DAGCombiner::visitSUBC(SDNode *N) {
2525 SDValue N0 = N->getOperand(0);
2526 SDValue N1 = N->getOperand(1);
2527 EVT VT = N0.getValueType();
2528 SDLoc DL(N);
2529
2530 // If the flag result is dead, turn this into an SUB.
2531 if (!N->hasAnyUseOfValue(1))
2532 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
2533 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2534
2535 // fold (subc x, x) -> 0 + no borrow
2536 if (N0 == N1)
2537 return CombineTo(N, DAG.getConstant(0, DL, VT),
2538 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2539
2540 // fold (subc x, 0) -> x + no borrow
2541 if (isNullConstant(N1))
2542 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2543
2544 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
2545 if (isAllOnesConstant(N0))
2546 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
2547 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2548
2549 return SDValue();
2550}
2551
2552SDValue DAGCombiner::visitUSUBO(SDNode *N) {
2553 SDValue N0 = N->getOperand(0);
2554 SDValue N1 = N->getOperand(1);
2555 EVT VT = N0.getValueType();
2556 if (VT.isVector())
2557 return SDValue();
2558
2559 EVT CarryVT = N->getValueType(1);
2560 SDLoc DL(N);
2561
2562 // If the flag result is dead, turn this into an SUB.
2563 if (!N->hasAnyUseOfValue(1))
2564 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
2565 DAG.getUNDEF(CarryVT));
2566
2567 // fold (usubo x, x) -> 0 + no borrow
2568 if (N0 == N1)
2569 return CombineTo(N, DAG.getConstant(0, DL, VT),
2570 DAG.getConstant(0, DL, CarryVT));
2571
2572 // fold (usubo x, 0) -> x + no borrow
2573 if (isNullConstant(N1))
2574 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2575
2576 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
2577 if (isAllOnesConstant(N0))
2578 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
2579 DAG.getConstant(0, DL, CarryVT));
2580
2581 return SDValue();
2582}
2583
2584SDValue DAGCombiner::visitSUBE(SDNode *N) {
2585 SDValue N0 = N->getOperand(0);
2586 SDValue N1 = N->getOperand(1);
2587 SDValue CarryIn = N->getOperand(2);
2588
2589 // fold (sube x, y, false) -> (subc x, y)
2590 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2591 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
2592
2593 return SDValue();
2594}
2595
2596SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
2597 SDValue N0 = N->getOperand(0);
2598 SDValue N1 = N->getOperand(1);
2599 SDValue CarryIn = N->getOperand(2);
2600
2601 // fold (subcarry x, y, false) -> (usubo x, y)
2602 if (isNullConstant(CarryIn))
2603 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
2604
2605 return SDValue();
2606}
2607
2608SDValue DAGCombiner::visitMUL(SDNode *N) {
2609 SDValue N0 = N->getOperand(0);
2610 SDValue N1 = N->getOperand(1);
2611 EVT VT = N0.getValueType();
2612
2613 // fold (mul x, undef) -> 0
2614 if (N0.isUndef() || N1.isUndef())
2615 return DAG.getConstant(0, SDLoc(N), VT);
2616
2617 bool N0IsConst = false;
2618 bool N1IsConst = false;
2619 bool N1IsOpaqueConst = false;
2620 bool N0IsOpaqueConst = false;
2621 APInt ConstValue0, ConstValue1;
2622 // fold vector ops
2623 if (VT.isVector()) {
2624 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2625 return FoldedVOp;
2626
2627 N0IsConst = ISD::isConstantSplatVector(N0.getNode(), ConstValue0);
2628 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
2629 assert((!N0IsConst ||(static_cast <bool> ((!N0IsConst || ConstValue0.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2631, __extension__ __PRETTY_FUNCTION__))
2630 ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) &&(static_cast <bool> ((!N0IsConst || ConstValue0.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2631, __extension__ __PRETTY_FUNCTION__))
2631 "Splat APInt should be element width")(static_cast <bool> ((!N0IsConst || ConstValue0.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N0IsConst || ConstValue0.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2631, __extension__ __PRETTY_FUNCTION__))
;
2632 assert((!N1IsConst ||(static_cast <bool> ((!N1IsConst || ConstValue1.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2634, __extension__ __PRETTY_FUNCTION__))
2633 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(static_cast <bool> ((!N1IsConst || ConstValue1.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2634, __extension__ __PRETTY_FUNCTION__))
2634 "Splat APInt should be element width")(static_cast <bool> ((!N1IsConst || ConstValue1.getBitWidth
() == VT.getScalarSizeInBits()) && "Splat APInt should be element width"
) ? void (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2634, __extension__ __PRETTY_FUNCTION__))
;
2635 } else {
2636 N0IsConst = isa<ConstantSDNode>(N0);
2637 if (N0IsConst) {
2638 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
2639 N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
2640 }
2641 N1IsConst = isa<ConstantSDNode>(N1);
2642 if (N1IsConst) {
2643 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
2644 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
2645 }
2646 }
2647
2648 // fold (mul c1, c2) -> c1*c2
2649 if (N0IsConst && N1IsConst && !N0IsOpaqueConst && !N1IsOpaqueConst)
2650 return DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT,
2651 N0.getNode(), N1.getNode());
2652
2653 // canonicalize constant to RHS (vector doesn't have to splat)
2654 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2655 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2656 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
2657 // fold (mul x, 0) -> 0
2658 if (N1IsConst && ConstValue1.isNullValue())
2659 return N1;
2660 // fold (mul x, 1) -> x
2661 if (N1IsConst && ConstValue1.isOneValue())
2662 return N0;
2663
2664 if (SDValue NewSel = foldBinOpIntoSelect(N))
2665 return NewSel;
2666
2667 // fold (mul x, -1) -> 0-x
2668 if (N1IsConst && ConstValue1.isAllOnesValue()) {
2669 SDLoc DL(N);
2670 return DAG.getNode(ISD::SUB, DL, VT,
2671 DAG.getConstant(0, DL, VT), N0);
2672 }
2673 // fold (mul x, (1 << c)) -> x << c
2674 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
2675 DAG.isKnownToBeAPowerOfTwo(N1)) {
2676 SDLoc DL(N);
2677 SDValue LogBase2 = BuildLogBase2(N1, DL);
2678 AddToWorklist(LogBase2.getNode());
2679
2680 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
2681 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
2682 AddToWorklist(Trunc.getNode());
2683 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
2684 }
2685 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
2686 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
2687 unsigned Log2Val = (-ConstValue1).logBase2();
2688 SDLoc DL(N);
2689 // FIXME: If the input is something that is easily negated (e.g. a
2690 // single-use add), we should put the negate there.
2691 return DAG.getNode(ISD::SUB, DL, VT,
2692 DAG.getConstant(0, DL, VT),
2693 DAG.getNode(ISD::SHL, DL, VT, N0,
2694 DAG.getConstant(Log2Val, DL,
2695 getShiftAmountTy(N0.getValueType()))));
2696 }
2697
2698 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2699 if (N0.getOpcode() == ISD::SHL &&
2700 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
2701 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
2702 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
2703 if (isConstantOrConstantVector(C3))
2704 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
2705 }
2706
2707 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2708 // use.
2709 {
2710 SDValue Sh(nullptr, 0), Y(nullptr, 0);
2711
2712 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2713 if (N0.getOpcode() == ISD::SHL &&
2714 isConstantOrConstantVector(N0.getOperand(1)) &&
2715 N0.getNode()->hasOneUse()) {
2716 Sh = N0; Y = N1;
2717 } else if (N1.getOpcode() == ISD::SHL &&
2718 isConstantOrConstantVector(N1.getOperand(1)) &&
2719 N1.getNode()->hasOneUse()) {
2720 Sh = N1; Y = N0;
2721 }
2722
2723 if (Sh.getNode()) {
2724 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
2725 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
2726 }
2727 }
2728
2729 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2730 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
2731 N0.getOpcode() == ISD::ADD &&
2732 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
2733 isMulAddWithConstProfitable(N, N0, N1))
2734 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2735 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2736 N0.getOperand(0), N1),
2737 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2738 N0.getOperand(1), N1));
2739
2740 // reassociate mul
2741 if (SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1))
2742 return RMUL;
2743
2744 return SDValue();
2745}
2746
2747/// Return true if divmod libcall is available.
2748static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2749 const TargetLowering &TLI) {
2750 RTLIB::Libcall LC;
2751 EVT NodeType = Node->getValueType(0);
2752 if (!NodeType.isSimple())
2753 return false;
2754 switch (NodeType.getSimpleVT().SimpleTy) {
2755 default: return false; // No libcall for vector types.
2756 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2757 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2758 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2759 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2760 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2761 }
2762
2763 return TLI.getLibcallName(LC) != nullptr;
2764}
2765
2766/// Issue divrem if both quotient and remainder are needed.
2767SDValue DAGCombiner::useDivRem(SDNode *Node) {
2768 if (Node->use_empty())
2769 return SDValue(); // This is a dead node, leave it alone.
2770
2771 unsigned Opcode = Node->getOpcode();
2772 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
2773 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2774
2775 // DivMod lib calls can still work on non-legal types if using lib-calls.
2776 EVT VT = Node->getValueType(0);
2777 if (VT.isVector() || !VT.isInteger())
2778 return SDValue();
2779
2780 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
2781 return SDValue();
2782
2783 // If DIVREM is going to get expanded into a libcall,
2784 // but there is no libcall available, then don't combine.
2785 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
2786 !isDivRemLibcallAvailable(Node, isSigned, TLI))
2787 return SDValue();
2788
2789 // If div is legal, it's better to do the normal expansion
2790 unsigned OtherOpcode = 0;
2791 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
2792 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
2793 if (TLI.isOperationLegalOrCustom(Opcode, VT))
2794 return SDValue();
2795 } else {
2796 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
2797 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
2798 return SDValue();
2799 }
2800
2801 SDValue Op0 = Node->getOperand(0);
2802 SDValue Op1 = Node->getOperand(1);
2803 SDValue combined;
2804 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2805 UE = Op0.getNode()->use_end(); UI != UE;) {
2806 SDNode *User = *UI++;
2807 if (User == Node || User->use_empty())
2808 continue;
2809 // Convert the other matching node(s), too;
2810 // otherwise, the DIVREM may get target-legalized into something
2811 // target-specific that we won't be able to recognize.
2812 unsigned UserOpc = User->getOpcode();
2813 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
2814 User->getOperand(0) == Op0 &&
2815 User->getOperand(1) == Op1) {
2816 if (!combined) {
2817 if (UserOpc == OtherOpcode) {
2818 SDVTList VTs = DAG.getVTList(VT, VT);
2819 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
2820 } else if (UserOpc == DivRemOpc) {
2821 combined = SDValue(User, 0);
2822 } else {
2823 assert(UserOpc == Opcode)(static_cast <bool> (UserOpc == Opcode) ? void (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2823, __extension__ __PRETTY_FUNCTION__))
;
2824 continue;
2825 }
2826 }
2827 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
2828 CombineTo(User, combined);
2829 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
2830 CombineTo(User, combined.getValue(1));
2831 }
2832 }
2833 return combined;
2834}
2835
2836static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
2837 SDValue N0 = N->getOperand(0);
2838 SDValue N1 = N->getOperand(1);
2839 EVT VT = N->getValueType(0);
2840 SDLoc DL(N);
2841
2842 if (DAG.isUndef(N->getOpcode(), {N0, N1}))
2843 return DAG.getUNDEF(VT);
2844
2845 // undef / X -> 0
2846 // undef % X -> 0
2847 if (N0.isUndef())
2848 return DAG.getConstant(0, DL, VT);
2849
2850 return SDValue();
2851}
2852
2853SDValue DAGCombiner::visitSDIV(SDNode *N) {
2854 SDValue N0 = N->getOperand(0);
2855 SDValue N1 = N->getOperand(1);
2856 EVT VT = N->getValueType(0);
2857
2858 // fold vector ops
2859 if (VT.isVector())
2860 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2861 return FoldedVOp;
2862
2863 SDLoc DL(N);
2864
2865 // fold (sdiv c1, c2) -> c1/c2
2866 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2867 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2868 if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
2869 return DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, N0C, N1C);
2870 // fold (sdiv X, 1) -> X
2871 if (N1C && N1C->isOne())
2872 return N0;
2873 // fold (sdiv X, -1) -> 0-X
2874 if (N1C && N1C->isAllOnesValue())
2875 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
2876
2877 if (SDValue V = simplifyDivRem(N, DAG))
2878 return V;
2879
2880 if (SDValue NewSel = foldBinOpIntoSelect(N))
2881 return NewSel;
2882
2883 // If we know the sign bits of both operands are zero, strength reduce to a
2884 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2885 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2886 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
2887
2888 // fold (sdiv X, pow2) -> simple ops after legalize
2889 // FIXME: We check for the exact bit here because the generic lowering gives
2890 // better results in that case. The target-specific lowering should learn how
2891 // to handle exact sdivs efficiently.
2892 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2893 !N->getFlags().hasExact() && (N1C->getAPIntValue().isPowerOf2() ||
2894 (-N1C->getAPIntValue()).isPowerOf2())) {
2895 // Target-specific implementation of sdiv x, pow2.
2896 if (SDValue Res = BuildSDIVPow2(N))
2897 return Res;
2898
2899 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2900
2901 // Splat the sign bit into the register
2902 SDValue SGN =
2903 DAG.getNode(ISD::SRA, DL, VT, N0,
2904 DAG.getConstant(VT.getScalarSizeInBits() - 1, DL,
2905 getShiftAmountTy(N0.getValueType())));
2906 AddToWorklist(SGN.getNode());
2907
2908 // Add (N0 < 0) ? abs2 - 1 : 0;
2909 SDValue SRL =
2910 DAG.getNode(ISD::SRL, DL, VT, SGN,
2911 DAG.getConstant(VT.getScalarSizeInBits() - lg2, DL,
2912 getShiftAmountTy(SGN.getValueType())));
2913 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL);
2914 AddToWorklist(SRL.getNode());
2915 AddToWorklist(ADD.getNode()); // Divide by pow2
2916 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD,
2917 DAG.getConstant(lg2, DL,
2918 getShiftAmountTy(ADD.getValueType())));
2919
2920 // If we're dividing by a positive value, we're done. Otherwise, we must
2921 // negate the result.
2922 if (N1C->getAPIntValue().isNonNegative())
2923 return SRA;
2924
2925 AddToWorklist(SRA.getNode());
2926 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
2927 }
2928
2929 // If integer divide is expensive and we satisfy the requirements, emit an
2930 // alternate sequence. Targets may check function attributes for size/speed
2931 // trade-offs.
2932 AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
2933 if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))
2934 if (SDValue Op = BuildSDIV(N))
2935 return Op;
2936
2937 // sdiv, srem -> sdivrem
2938 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
2939 // true. Otherwise, we break the simplification logic in visitREM().
2940 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
2941 if (SDValue DivRem = useDivRem(N))
2942 return DivRem;
2943
2944 return SDValue();
2945}
2946
2947SDValue DAGCombiner::visitUDIV(SDNode *N) {
2948 SDValue N0 = N->getOperand(0);
2949 SDValue N1 = N->getOperand(1);
2950 EVT VT = N->getValueType(0);
2951
2952 // fold vector ops
2953 if (VT.isVector())
2954 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2955 return FoldedVOp;
2956
2957 SDLoc DL(N);
2958
2959 // fold (udiv c1, c2) -> c1/c2
2960 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2961 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2962 if (N0C && N1C)
2963 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
2964 N0C, N1C))
2965 return Folded;
2966
2967 if (SDValue V = simplifyDivRem(N, DAG))
2968 return V;
2969
2970 if (SDValue NewSel = foldBinOpIntoSelect(N))
2971 return NewSel;
2972
2973 // fold (udiv x, (1 << c)) -> x >>u c
2974 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
2975 DAG.isKnownToBeAPowerOfTwo(N1)) {
2976 SDValue LogBase2 = BuildLogBase2(N1, DL);
2977 AddToWorklist(LogBase2.getNode());
2978
2979 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
2980 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
2981 AddToWorklist(Trunc.getNode());
2982 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
2983 }
2984
2985 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2986 if (N1.getOpcode() == ISD::SHL) {
2987 SDValue N10 = N1.getOperand(0);
2988 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
2989 DAG.isKnownToBeAPowerOfTwo(N10)) {
2990 SDValue LogBase2 = BuildLogBase2(N10, DL);
2991 AddToWorklist(LogBase2.getNode());
2992
2993 EVT ADDVT = N1.getOperand(1).getValueType();
2994 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
2995 AddToWorklist(Trunc.getNode());
2996 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
2997 AddToWorklist(Add.getNode());
2998 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
2999 }
3000 }
3001
3002 // fold (udiv x, c) -> alternate
3003 AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
3004 if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))
3005 if (SDValue Op = BuildUDIV(N))
3006 return Op;
3007
3008 // sdiv, srem -> sdivrem
3009 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3010 // true. Otherwise, we break the simplification logic in visitREM().
3011 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3012 if (SDValue DivRem = useDivRem(N))
3013 return DivRem;
3014
3015 return SDValue();
3016}
3017
3018// handles ISD::SREM and ISD::UREM
3019SDValue DAGCombiner::visitREM(SDNode *N) {
3020 unsigned Opcode = N->getOpcode();
3021 SDValue N0 = N->getOperand(0);
3022 SDValue N1 = N->getOperand(1);
3023 EVT VT = N->getValueType(0);
3024 bool isSigned = (Opcode == ISD::SREM);
3025 SDLoc DL(N);
3026
3027 // fold (rem c1, c2) -> c1%c2
3028 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3029 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3030 if (N0C && N1C)
3031 if (SDValue Folded = DAG.FoldConstantArithmetic(Opcode, DL, VT, N0C, N1C))
3032 return Folded;
3033
3034 if (SDValue V = simplifyDivRem(N, DAG))
3035 return V;
3036
3037 if (SDValue NewSel = foldBinOpIntoSelect(N))
3038 return NewSel;
3039
3040 if (isSigned) {
3041 // If we know the sign bits of both operands are zero, strength reduce to a
3042 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
3043 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3044 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
3045 } else {
3046 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
3047 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
3048 // fold (urem x, pow2) -> (and x, pow2-1)
3049 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
3050 AddToWorklist(Add.getNode());
3051 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3052 }
3053 if (N1.getOpcode() == ISD::SHL &&
3054 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
3055 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
3056 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
3057 AddToWorklist(Add.getNode());
3058 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
3059 }
3060 }
3061
3062 AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
3063
3064 // If X/C can be simplified by the division-by-constant logic, lower
3065 // X%C to the equivalent of X-X/C*C.
3066 // To avoid mangling nodes, this simplification requires that the combine()
3067 // call for the speculative DIV must not cause a DIVREM conversion. We guard
3068 // against this by skipping the simplification if isIntDivCheap(). When
3069 // div is not cheap, combine will not return a DIVREM. Regardless,
3070 // checking cheapness here makes sense since the simplification results in
3071 // fatter code.
3072 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap(VT, Attr)) {
3073 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3074 SDValue Div = DAG.getNode(DivOpcode, DL, VT, N0, N1);
3075 AddToWorklist(Div.getNode());
3076 SDValue OptimizedDiv = combine(Div.getNode());
3077 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
3078 assert((OptimizedDiv.getOpcode() != ISD::UDIVREM) &&(static_cast <bool> ((OptimizedDiv.getOpcode() != ISD::
UDIVREM) && (OptimizedDiv.getOpcode() != ISD::SDIVREM
)) ? void (0) : __assert_fail ("(OptimizedDiv.getOpcode() != ISD::UDIVREM) && (OptimizedDiv.getOpcode() != ISD::SDIVREM)"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3079, __extension__ __PRETTY_FUNCTION__))
3079 (OptimizedDiv.getOpcode() != ISD::SDIVREM))(static_cast <bool> ((OptimizedDiv.getOpcode() != ISD::
UDIVREM) && (OptimizedDiv.getOpcode() != ISD::SDIVREM
)) ? void (0) : __assert_fail ("(OptimizedDiv.getOpcode() != ISD::UDIVREM) && (OptimizedDiv.getOpcode() != ISD::SDIVREM)"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3079, __extension__ __PRETTY_FUNCTION__))
;
3080 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
3081 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3082 AddToWorklist(Mul.getNode());
3083 return Sub;
3084 }
3085 }
3086
3087 // sdiv, srem -> sdivrem
3088 if (SDValue DivRem = useDivRem(N))
3089 return DivRem.getValue(1);
3090
3091 return SDValue();
3092}
3093
3094SDValue DAGCombiner::visitMULHS(SDNode *N) {
3095 SDValue N0 = N->getOperand(0);
3096 SDValue N1 = N->getOperand(1);
3097 EVT VT = N->getValueType(0);
3098 SDLoc DL(N);
3099
3100 // fold (mulhs x, 0) -> 0
3101 if (isNullConstant(N1))
3102 return N1;
3103 // fold (mulhs x, 1) -> (sra x, size(x)-1)
3104 if (isOneConstant(N1)) {
3105 SDLoc DL(N);
3106 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
3107 DAG.getConstant(N0.getValueSizeInBits() - 1, DL,
3108 getShiftAmountTy(N0.getValueType())));
3109 }
3110 // fold (mulhs x, undef) -> 0
3111 if (N0.isUndef() || N1.isUndef())
3112 return DAG.getConstant(0, SDLoc(N), VT);
3113
3114 // If the type twice as wide is legal, transform the mulhs to a wider multiply
3115 // plus a shift.
3116 if (VT.isSimple() && !VT.isVector()) {
3117 MVT Simple = VT.getSimpleVT();
3118 unsigned SimpleSize = Simple.getSizeInBits();
3119 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3120 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3121 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
3122 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
3123 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
3124 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
3125 DAG.getConstant(SimpleSize, DL,
3126 getShiftAmountTy(N1.getValueType())));
3127 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
3128 }
3129 }
3130
3131 return SDValue();
3132}
3133
3134SDValue DAGCombiner::visitMULHU(SDNode *N) {
3135 SDValue N0 = N->getOperand(0);
3136 SDValue N1 = N->getOperand(1);
3137 EVT VT = N->getValueType(0);
3138 SDLoc DL(N);
3139
3140 // fold (mulhu x, 0) -> 0
3141 if (isNullConstant(N1))
3142 return N1;
3143 // fold (mulhu x, 1) -> 0
3144 if (isOneConstant(N1))
3145 return DAG.getConstant(0, DL, N0.getValueType());
3146 // fold (mulhu x, undef) -> 0
3147 if (N0.isUndef() || N1.isUndef())
3148 return DAG.getConstant(0, DL, VT);
3149
3150 // If the type twice as wide is legal, transform the mulhu to a wider multiply
3151 // plus a shift.
3152 if (VT.isSimple() && !VT.isVector()) {
3153 MVT Simple = VT.getSimpleVT();
3154 unsigned SimpleSize = Simple.getSizeInBits();
3155 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3156 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3157 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
3158 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
3159 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
3160 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
3161 DAG.getConstant(SimpleSize, DL,
3162 getShiftAmountTy(N1.getValueType())));
3163 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
3164 }
3165 }
3166
3167 return SDValue();
3168}
3169
3170/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
3171/// give the opcodes for the two computations that are being performed. Return
3172/// true if a simplification was made.
3173SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
3174 unsigned HiOp) {
3175 // If the high half is not needed, just compute the low half.
3176 bool HiExists = N->hasAnyUseOfValue(1);
3177 if (!HiExists &&
3178 (!LegalOperations ||
3179 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
3180 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
3181 return CombineTo(N, Res, Res);
3182 }
3183
3184 // If the low half is not needed, just compute the high half.
3185 bool LoExists = N->hasAnyUseOfValue(0);
3186 if (!LoExists &&
3187 (!LegalOperations ||
3188 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
3189 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
3190 return CombineTo(N, Res, Res);
3191 }
3192
3193 // If both halves are used, return as it is.
3194 if (LoExists && HiExists)
3195 return SDValue();
3196
3197 // If the two computed results can be simplified separately, separate them.
3198 if (LoExists) {
3199 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
3200 AddToWorklist(Lo.getNode());
3201 SDValue LoOpt = combine(Lo.getNode());
3202 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
3203 (!LegalOperations ||
3204 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
3205 return CombineTo(N, LoOpt, LoOpt);
3206 }
3207
3208 if (HiExists) {
3209 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
3210 AddToWorklist(Hi.getNode());
3211 SDValue HiOpt = combine(Hi.getNode());
3212 if (HiOpt.getNode() && HiOpt != Hi &&
3213 (!LegalOperations ||
3214 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
3215 return CombineTo(N, HiOpt, HiOpt);
3216 }
3217
3218 return SDValue();
3219}
3220
3221SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
3222 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
3223 return Res;
3224
3225 EVT VT = N->getValueType(0);
3226 SDLoc DL(N);
3227
3228 // If the type is twice as wide is legal, transform the mulhu to a wider
3229 // multiply plus a shift.
3230 if (VT.isSimple() && !VT.isVector()) {
3231 MVT Simple = VT.getSimpleVT();
3232 unsigned SimpleSize = Simple.getSizeInBits();
3233 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3234 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3235 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
3236 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
3237 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
3238 // Compute the high part as N1.
3239 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
3240 DAG.getConstant(SimpleSize, DL,
3241 getShiftAmountTy(Lo.getValueType())));
3242 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
3243 // Compute the low part as N0.
3244 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
3245 return CombineTo(N, Lo, Hi);
3246 }
3247 }
3248
3249 return SDValue();
3250}
3251
3252SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
3253 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
3254 return Res;
3255
3256 EVT VT = N->getValueType(0);
3257 SDLoc DL(N);
3258
3259 // If the type is twice as wide is legal, transform the mulhu to a wider
3260 // multiply plus a shift.
3261 if (VT.isSimple() && !VT.isVector()) {
3262 MVT Simple = VT.getSimpleVT();
3263 unsigned SimpleSize = Simple.getSizeInBits();
3264 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
3265 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
3266 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
3267 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
3268 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
3269 // Compute the high part as N1.
3270 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
3271 DAG.getConstant(SimpleSize, DL,
3272 getShiftAmountTy(Lo.getValueType())));
3273 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
3274 // Compute the low part as N0.
3275 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
3276 return CombineTo(N, Lo, Hi);
3277 }
3278 }
3279
3280 return SDValue();
3281}
3282
3283SDValue DAGCombiner::visitSMULO(SDNode *N) {
3284 // (smulo x, 2) -> (saddo x, x)
3285 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
3286 if (C2->getAPIntValue() == 2)
3287 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
3288 N->getOperand(0), N->getOperand(0));
3289
3290 return SDValue();
3291}
3292
3293SDValue DAGCombiner::visitUMULO(SDNode *N) {
3294 // (umulo x, 2) -> (uaddo x, x)
3295 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
3296 if (C2->getAPIntValue() == 2)
3297 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
3298 N->getOperand(0), N->getOperand(0));
3299
3300 return SDValue();
3301}
3302
3303SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
3304 SDValue N0 = N->getOperand(0);
3305 SDValue N1 = N->getOperand(1);
3306 EVT VT = N0.getValueType();
3307
3308 // fold vector ops
3309 if (VT.isVector())
3310 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3311 return FoldedVOp;
3312
3313 // fold operation with constant operands.
3314 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3315 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3316 if (N0C && N1C)
3317 return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
3318
3319 // canonicalize constant to RHS
3320 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3321 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3322 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
3323
3324 return SDValue();
3325}
3326
3327/// If this is a binary operator with two operands of the same opcode, try to
3328/// simplify it.
3329SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
3330 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3331 EVT VT = N0.getValueType();
3332 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!")(static_cast <bool> (N0.getOpcode() == N1.getOpcode() &&
"Bad input!") ? void (0) : __assert_fail ("N0.getOpcode() == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3332, __extension__ __PRETTY_FUNCTION__))
;
3333
3334 // Bail early if none of these transforms apply.
3335 if (N0.getNumOperands() == 0) return SDValue();
3336
3337 // For each of OP in AND/OR/XOR:
3338 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
3339 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
3340 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
3341 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
3342 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
3343 //
3344 // do not sink logical op inside of a vector extend, since it may combine
3345 // into a vsetcc.
3346 EVT Op0VT = N0.getOperand(0).getValueType();
3347 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
3348 N0.getOpcode() == ISD::SIGN_EXTEND ||
3349 N0.getOpcode() == ISD::BSWAP ||
3350 // Avoid infinite looping with PromoteIntBinOp.
3351 (N0.getOpcode() == ISD::ANY_EXTEND &&
3352 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
3353 (N0.getOpcode() == ISD::TRUNCATE &&
3354 (!TLI.isZExtFree(VT, Op0VT) ||
3355 !TLI.isTruncateFree(Op0VT, VT)) &&
3356 TLI.isTypeLegal(Op0VT))) &&
3357 !VT.isVector() &&
3358 Op0VT == N1.getOperand(0).getValueType() &&
3359 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
3360 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
3361 N0.getOperand(0).getValueType(),
3362 N0.getOperand(0), N1.getOperand(0));
3363 AddToWorklist(ORNode.getNode());
3364 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
3365 }
3366
3367 // For each of OP in SHL/SRL/SRA/AND...
3368 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
3369 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
3370 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
3371 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
3372 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
3373 N0.getOperand(1) == N1.getOperand(1)) {
3374 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
3375 N0.getOperand(0).getValueType(),
3376 N0.getOperand(0), N1.getOperand(0));
3377 AddToWorklist(ORNode.getNode());
3378 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
3379 ORNode, N0.getOperand(1));
3380 }
3381
3382 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
3383 // Only perform this optimization up until type legalization, before
3384 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
3385 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
3386 // we don't want to undo this promotion.
3387 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
3388 // on scalars.
3389 if ((N0.getOpcode() == ISD::BITCAST ||
3390 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
3391 Level <= AfterLegalizeTypes) {
3392 SDValue In0 = N0.getOperand(0);
3393 SDValue In1 = N1.getOperand(0);
3394 EVT In0Ty = In0.getValueType();
3395 EVT In1Ty = In1.getValueType();
3396 SDLoc DL(N);
3397 // If both incoming values are integers, and the original types are the
3398 // same.
3399 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
3400 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
3401 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
3402 AddToWorklist(Op.getNode());
3403 return BC;
3404 }
3405 }
3406
3407 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
3408 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
3409 // If both shuffles use the same mask, and both shuffle within a single
3410 // vector, then it is worthwhile to move the swizzle after the operation.
3411 // The type-legalizer generates this pattern when loading illegal
3412 // vector types from memory. In many cases this allows additional shuffle
3413 // optimizations.
3414 // There are other cases where moving the shuffle after the xor/and/or
3415 // is profitable even if shuffles don't perform a swizzle.
3416 // If both shuffles use the same mask, and both shuffles have the same first
3417 // or second operand, then it might still be profitable to move the shuffle
3418 // after the xor/and/or operation.
3419 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
3420 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
3421 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
3422
3423 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&(static_cast <bool> (N0.getOperand(0).getValueType() ==
N1.getOperand(0).getValueType() && "Inputs to shuffles are not the same type"
) ? void (0) : __assert_fail ("N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3424, __extension__ __PRETTY_FUNCTION__))
3424 "Inputs to shuffles are not the same type")(static_cast <bool> (N0.getOperand(0).getValueType() ==
N1.getOperand(0).getValueType() && "Inputs to shuffles are not the same type"
) ? void (0) : __assert_fail ("N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3424, __extension__ __PRETTY_FUNCTION__))
;
3425
3426 // Check that both shuffles use the same mask. The masks are known to be of
3427 // the same length because the result vector type is the same.
3428 // Check also that shuffles have only one use to avoid introducing extra
3429 // instructions.
3430 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
3431 SVN0->getMask().equals(SVN1->getMask())) {
3432 SDValue ShOp = N0->getOperand(1);
3433
3434 // Don't try to fold this node if it requires introducing a
3435 // build vector of all zeros that might be illegal at this stage.
3436 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) {
3437 if (!LegalTypes)
3438 ShOp = DAG.getConstant(0, SDLoc(N), VT);
3439 else
3440 ShOp = SDValue();
3441 }
3442
3443 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
3444 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
3445 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
3446 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
3447 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
3448 N0->getOperand(0), N1->getOperand(0));
3449 AddToWorklist(NewNode.getNode());
3450 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
3451 SVN0->getMask());
3452 }
3453
3454 // Don't try to fold this node if it requires introducing a
3455 // build vector of all zeros that might be illegal at this stage.
3456 ShOp = N0->getOperand(0);
3457 if (N->getOpcode() == ISD::XOR && !ShOp.isUndef()) {
3458 if (!LegalTypes)
3459 ShOp = DAG.getConstant(0, SDLoc(N), VT);
3460 else
3461 ShOp = SDValue();
3462 }
3463
3464 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
3465 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
3466 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
3467 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
3468 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
3469 N0->getOperand(1), N1->getOperand(1));
3470 AddToWorklist(NewNode.getNode());
3471 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
3472 SVN0->getMask());
3473 }
3474 }
3475 }
3476
3477 return SDValue();
3478}
3479
3480/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
3481SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
3482 const SDLoc &DL) {
3483 SDValue LL, LR, RL, RR, N0CC, N1CC;
3484 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
3485 !isSetCCEquivalent(N1, RL, RR, N1CC))
3486 return SDValue();
3487
3488 assert(N0.getValueType() == N1.getValueType() &&(static_cast <bool> (N0.getValueType() == N1.getValueType
() && "Unexpected operand types for bitwise logic op"
) ? void (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3489, __extension__ __PRETTY_FUNCTION__))
3489 "Unexpected operand types for bitwise logic op")(static_cast <bool> (N0.getValueType() == N1.getValueType
() && "Unexpected operand types for bitwise logic op"
) ? void (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3489, __extension__ __PRETTY_FUNCTION__))
;
3490 assert(LL.getValueType() == LR.getValueType() &&(static_cast <bool> (LL.getValueType() == LR.getValueType
() && RL.getValueType() == RR.getValueType() &&
"Unexpected operand types for setcc") ? void (0) : __assert_fail
("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3492, __extension__ __PRETTY_FUNCTION__))
3491 RL.getValueType() == RR.getValueType() &&(static_cast <bool> (LL.getValueType() == LR.getValueType
() && RL.getValueType() == RR.getValueType() &&
"Unexpected operand types for setcc") ? void (0) : __assert_fail
("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3492, __extension__ __PRETTY_FUNCTION__))
3492 "Unexpected operand types for setcc")(static_cast <bool> (LL.getValueType() == LR.getValueType
() && RL.getValueType() == RR.getValueType() &&
"Unexpected operand types for setcc") ? void (0) : __assert_fail
("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3492, __extension__ __PRETTY_FUNCTION__))
;
3493
3494 // If we're here post-legalization or the logic op type is not i1, the logic
3495 // op type must match a setcc result type. Also, all folds require new
3496 // operations on the left and right operands, so those types must match.
3497 EVT VT = N0.getValueType();
3498 EVT OpVT = LL.getValueType();
3499 if (LegalOperations || VT != MVT::i1)
3500 if (VT != getSetCCResultType(OpVT))
3501 return SDValue();
3502 if (OpVT != RL.getValueType())
3503 return SDValue();
3504
3505 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
3506 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
3507 bool IsInteger = OpVT.isInteger();
3508 if (LR == RR && CC0 == CC1 && IsInteger) {
3509 bool IsZero = isNullConstantOrNullSplatConstant(LR);
3510 bool IsNeg1 = isAllOnesConstantOrAllOnesSplatConstant(LR);
3511
3512 // All bits clear?
3513 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
3514 // All sign bits clear?
3515 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
3516 // Any bits set?
3517 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
3518 // Any sign bits set?
3519 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
3520
3521 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
3522 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
3523 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
3524 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
3525 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
3526 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
3527 AddToWorklist(Or.getNode());
3528 return DAG.getSetCC(DL, VT, Or, LR, CC1);
3529 }
3530
3531 // All bits set?
3532 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
3533 // All sign bits set?
3534 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
3535 // Any bits clear?
3536 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
3537 // Any sign bits clear?
3538 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
3539
3540 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
3541 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
3542 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
3543 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
3544 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
3545 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
3546 AddToWorklist(And.getNode());
3547 return DAG.getSetCC(DL, VT, And, LR, CC1);
3548 }
3549 }
3550
3551 // TODO: What is the 'or' equivalent of this fold?
3552 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
3553 if (IsAnd && LL == RL && CC0 == CC1 && IsInteger && CC0 == ISD::SETNE &&
3554 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
3555 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
3556 SDValue One = DAG.getConstant(1, DL, OpVT);
3557 SDValue Two = DAG.getConstant(2, DL, OpVT);
3558 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
3559 AddToWorklist(Add.getNode());
3560 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
3561 }
3562
3563 // Try more general transforms if the predicates match and the only user of
3564 // the compares is the 'and' or 'or'.
3565 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
3566 N0.hasOneUse() && N1.hasOneUse()) {
3567 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
3568 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
3569 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
3570 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
3571 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
3572 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
3573 SDValue Zero = DAG.getConstant(0, DL, OpVT);
3574 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
3575 }
3576 }
3577
3578 // Canonicalize equivalent operands to LL == RL.
3579 if (LL == RR && LR == RL) {
3580 CC1 = ISD::getSetCCSwappedOperands(CC1);
3581 std::swap(RL, RR);
3582 }
3583
3584 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
3585 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
3586 if (LL == RL && LR == RR) {
3587 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, IsInteger)
3588 : ISD::getSetCCOrOperation(CC0, CC1, IsInteger);
3589 if (NewCC != ISD::SETCC_INVALID &&
3590 (!LegalOperations ||
3591 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
3592 TLI.isOperationLegal(ISD::SETCC, OpVT))))
3593 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
3594 }
3595
3596 return SDValue();
3597}
3598
3599/// This contains all DAGCombine rules which reduce two values combined by
3600/// an And operation to a single value. This makes them reusable in the context
3601/// of visitSELECT(). Rules involving constants are not included as
3602/// visitSELECT() already handles those cases.
3603SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
3604 EVT VT = N1.getValueType();
3605 SDLoc DL(N);
3606
3607 // fold (and x, undef) -> 0
3608 if (N0.isUndef() || N1.isUndef())
3609 return DAG.getConstant(0, DL, VT);
3610
3611 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
3612 return V;
3613
3614 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3615 VT.getSizeInBits() <= 64) {
3616 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3617 APInt ADDC = ADDI->getAPIntValue();
3618 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3619 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
3620 // immediate for an add, but it is legal if its top c2 bits are set,
3621 // transform the ADD so the immediate doesn't need to be materialized
3622 // in a register.
3623 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
3624 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3625 SRLI->getZExtValue());
3626 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
3627 ADDC |= Mask;
3628 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3629 SDLoc DL0(N0);
3630 SDValue NewAdd =
3631 DAG.getNode(ISD::ADD, DL0, VT,
3632 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
3633 CombineTo(N0.getNode(), NewAdd);
3634 // Return N so it doesn't get rechecked!
3635 return SDValue(N, 0);
3636 }
3637 }
3638 }
3639 }
3640 }
3641 }
3642
3643 // Reduce bit extract of low half of an integer to the narrower type.
3644 // (and (srl i64:x, K), KMask) ->
3645 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
3646 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3647 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
3648 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3649 unsigned Size = VT.getSizeInBits();
3650 const APInt &AndMask = CAnd->getAPIntValue();
3651 unsigned ShiftBits = CShift->getZExtValue();
3652
3653 // Bail out, this node will probably disappear anyway.
3654 if (ShiftBits == 0)
3655 return SDValue();
3656
3657 unsigned MaskBits = AndMask.countTrailingOnes();
3658 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
3659
3660 if (AndMask.isMask() &&
3661 // Required bits must not span the two halves of the integer and
3662 // must fit in the half size type.
3663 (ShiftBits + MaskBits <= Size / 2) &&
3664 TLI.isNarrowingProfitable(VT, HalfVT) &&
3665 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
3666 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
3667 TLI.isTruncateFree(VT, HalfVT) &&
3668 TLI.isZExtFree(HalfVT, VT)) {
3669 // The isNarrowingProfitable is to avoid regressions on PPC and
3670 // AArch64 which match a few 64-bit bit insert / bit extract patterns
3671 // on downstream users of this. Those patterns could probably be
3672 // extended to handle extensions mixed in.
3673
3674 SDValue SL(N0);
3675 assert(MaskBits <= Size)(static_cast <bool> (MaskBits <= Size) ? void (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3675, __extension__ __PRETTY_FUNCTION__))
;
3676
3677 // Extracting the highest bit of the low half.
3678 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
3679 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
3680 N0.getOperand(0));
3681
3682 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
3683 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
3684 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
3685 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
3686 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
3687 }
3688 }
3689 }
3690 }
3691
3692 return SDValue();
3693}
3694
3695bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
3696 EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT,
3697 bool &NarrowLoad) {
3698 if (!AndC->getAPIntValue().isMask())
3699 return false;
3700
3701 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
3702
3703 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
3704 LoadedVT = LoadN->getMemoryVT();
3705
3706 if (ExtVT == LoadedVT &&
3707 (!LegalOperations ||
3708 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
3709 // ZEXTLOAD will match without needing to change the size of the value being
3710 // loaded.
3711 NarrowLoad = false;
3712 return true;
3713 }
3714
3715 // Do not change the width of a volatile load.
3716 if (LoadN->isVolatile())
3717 return false;
3718
3719 // Do not generate loads of non-round integer types since these can
3720 // be expensive (and would be wrong if the type is not byte sized).
3721 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
3722 return false;
3723
3724 if (LegalOperations &&
3725 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
3726 return false;
3727
3728 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
3729 return false;
3730
3731 NarrowLoad = true;
3732 return true;
3733}
3734
3735SDValue DAGCombiner::visitAND(SDNode *N) {
3736 SDValue N0 = N->getOperand(0);
3737 SDValue N1 = N->getOperand(1);
3738 EVT VT = N1.getValueType();
3739
3740 // x & x --> x
3741 if (N0 == N1)
3742 return N0;
3743
3744 // fold vector ops
3745 if (VT.isVector()) {
3746 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3747 return FoldedVOp;
3748
3749 // fold (and x, 0) -> 0, vector edition
3750 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3751 // do not return N0, because undef node may exist in N0
3752 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
3753 SDLoc(N), N0.getValueType());
3754 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3755 // do not return N1, because undef node may exist in N1
3756 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
3757 SDLoc(N), N1.getValueType());
3758
3759 // fold (and x, -1) -> x, vector edition
3760 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3761 return N1;
3762 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3763 return N0;
3764 }
3765
3766 // fold (and c1, c2) -> c1&c2
3767 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3768 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3769 if (N0C && N1C && !N1C->isOpaque())
3770 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
3771 // canonicalize constant to RHS
3772 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3773 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3774 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
3775 // fold (and x, -1) -> x
3776 if (isAllOnesConstant(N1))
3777 return N0;
3778 // if (and x, c) is known to be zero, return 0
3779 unsigned BitWidth = VT.getScalarSizeInBits();
3780 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3781 APInt::getAllOnesValue(BitWidth)))
3782 return DAG.getConstant(0, SDLoc(N), VT);
3783
3784 if (SDValue NewSel = foldBinOpIntoSelect(N))
3785 return NewSel;
3786
3787 // reassociate and
3788 if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1))
3789 return RAND;
3790 // fold (and (or x, C), D) -> D if (C & D) == D
3791 if (N1C && N0.getOpcode() == ISD::OR)
3792 if (ConstantSDNode *ORI = isConstOrConstSplat(N0.getOperand(1)))
3793 if (N1C->getAPIntValue().isSubsetOf(ORI->getAPIntValue()))
3794 return N1;
3795 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
3796 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3797 SDValue N0Op0 = N0.getOperand(0);
3798 APInt Mask = ~N1C->getAPIntValue();
3799 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
3800 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
3801 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
3802 N0.getValueType(), N0Op0);
3803
3804 // Replace uses of the AND with uses of the Zero extend node.
3805 CombineTo(N, Zext);
3806
3807 // We actually want to replace all uses of the any_extend with the
3808 // zero_extend, to avoid duplicating things. This will later cause this
3809 // AND to be folded.
3810 CombineTo(N0.getNode(), Zext);
3811 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3812 }
3813 }
3814 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
3815 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
3816 // already be zero by virtue of the width of the base type of the load.
3817 //
3818 // the 'X' node here can either be nothing or an extract_vector_elt to catch
3819 // more cases.
3820 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
3821 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
3822 N0.getOperand(0).getOpcode() == ISD::LOAD &&
3823 N0.getOperand(0).getResNo() == 0) ||
3824 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
3825 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
3826 N0 : N0.getOperand(0) );
3827
3828 // Get the constant (if applicable) the zero'th operand is being ANDed with.
3829 // This can be a pure constant or a vector splat, in which case we treat the
3830 // vector as a scalar and use the splat value.
3831 APInt Constant = APInt::getNullValue(1);
3832 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
3833 Constant = C->getAPIntValue();
3834 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
3835 APInt SplatValue, SplatUndef;
3836 unsigned SplatBitSize;
3837 bool HasAnyUndefs;
3838 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
3839 SplatBitSize, HasAnyUndefs);
3840 if (IsSplat) {
3841 // Undef bits can contribute to a possible optimisation if set, so
3842 // set them.
3843 SplatValue |= SplatUndef;
3844
3845 // The splat value may be something like "0x00FFFFFF", which means 0 for
3846 // the first vector value and FF for the rest, repeating. We need a mask
3847 // that will apply equally to all members of the vector, so AND all the
3848 // lanes of the constant together.
3849 EVT VT = Vector->getValueType(0);
3850 unsigned BitWidth = VT.getScalarSizeInBits();
3851
3852 // If the splat value has been compressed to a bitlength lower
3853 // than the size of the vector lane, we need to re-expand it to
3854 // the lane size.
3855 if (BitWidth > SplatBitSize)
3856 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
3857 SplatBitSize < BitWidth;
3858 SplatBitSize = SplatBitSize * 2)
3859 SplatValue |= SplatValue.shl(SplatBitSize);
3860
3861 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
3862 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
3863 if (SplatBitSize % BitWidth == 0) {
3864 Constant = APInt::getAllOnesValue(BitWidth);
3865 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
3866 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
3867 }
3868 }
3869 }
3870
3871 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
3872 // actually legal and isn't going to get expanded, else this is a false
3873 // optimisation.
3874 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
3875 Load->getValueType(0),
3876 Load->getMemoryVT());
3877
3878 // Resize the constant to the same size as the original memory access before
3879 // extension. If it is still the AllOnesValue then this AND is completely
3880 // unneeded.
3881 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
3882
3883 bool B;
3884 switch (Load->getExtensionType()) {
3885 default: B = false; break;
3886 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
3887 case ISD::ZEXTLOAD:
3888 case ISD::NON_EXTLOAD: B = true; break;
3889 }
3890
3891 if (B && Constant.isAllOnesValue()) {
3892 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
3893 // preserve semantics once we get rid of the AND.
3894 SDValue NewLoad(Load, 0);
3895
3896 // Fold the AND away. NewLoad may get replaced immediately.
3897 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
3898
3899 if (Load->getExtensionType() == ISD::EXTLOAD) {
3900 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
3901 Load->getValueType(0), SDLoc(Load),
3902 Load->getChain(), Load->getBasePtr(),
3903 Load->getOffset(), Load->getMemoryVT(),
3904 Load->getMemOperand());
3905 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
3906 if (Load->getNumValues() == 3) {
3907 // PRE/POST_INC loads have 3 values.
3908 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
3909 NewLoad.getValue(2) };
3910 CombineTo(Load, To, 3, true);
3911 } else {
3912 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
3913 }
3914 }
3915
3916 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3917 }
3918 }
3919
3920 // fold (and (load x), 255) -> (zextload x, i8)
3921 // fold (and (extload x, i16), 255) -> (zextload x, i8)
3922 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
3923 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
3924 (N0.getOpcode() == ISD::ANY_EXTEND &&
3925 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
3926 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
3927 LoadSDNode *LN0 = HasAnyExt
3928 ? cast<LoadSDNode>(N0.getOperand(0))
3929 : cast<LoadSDNode>(N0);
3930 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
3931 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
3932 auto NarrowLoad = false;
3933 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
3934 EVT ExtVT, LoadedVT;
3935 if (isAndLoadExtLoad(N1C, LN0, LoadResultTy, ExtVT, LoadedVT,
3936 NarrowLoad)) {
3937 if (!NarrowLoad) {
3938 SDValue NewLoad =
3939 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3940 LN0->getChain(), LN0->getBasePtr(), ExtVT,
3941 LN0->getMemOperand());
3942 AddToWorklist(N);
3943 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
3944 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3945 } else {
3946 EVT PtrType = LN0->getOperand(1).getValueType();
3947
3948 unsigned Alignment = LN0->getAlignment();
3949 SDValue NewPtr = LN0->getBasePtr();
3950
3951 // For big endian targets, we need to add an offset to the pointer
3952 // to load the correct bytes. For little endian systems, we merely
3953 // need to read fewer bytes from the same pointer.
3954 if (DAG.getDataLayout().isBigEndian()) {
3955 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3956 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3957 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3958 SDLoc DL(LN0);
3959 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType,
3960 NewPtr, DAG.getConstant(PtrOff, DL, PtrType));
3961 Alignment = MinAlign(Alignment, PtrOff);
3962 }
3963
3964 AddToWorklist(NewPtr.getNode());
3965
3966 SDValue Load = DAG.getExtLoad(
3967 ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, LN0->getChain(), NewPtr,
3968 LN0->getPointerInfo(), ExtVT, Alignment,
3969 LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
3970 AddToWorklist(N);
3971 CombineTo(LN0, Load, Load.getValue(1));
3972 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3973 }
3974 }
3975 }
3976 }
3977
3978 if (SDValue Combined = visitANDLike(N0, N1, N))
3979 return Combined;
3980
3981 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
3982 if (N0.getOpcode() == N1.getOpcode())
3983 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
3984 return Tmp;
3985
3986 // Masking the negated extension of a boolean is just the zero-extended
3987 // boolean:
3988 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
3989 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
3990 //
3991 // Note: the SimplifyDemandedBits fold below can make an information-losing
3992 // transform, and then we have no way to find this better fold.
3993 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
3994 if (isNullConstantOrNullSplatConstant(N0.getOperand(0))) {
3995 SDValue SubRHS = N0.getOperand(1);
3996 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
3997 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
3998 return SubRHS;
3999 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
4000 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
4001 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
4002 }
4003 }
4004
4005 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
4006 // fold (and (sra)) -> (and (srl)) when possible.
4007 if (SimplifyDemandedBits(SDValue(N, 0)))
4008 return SDValue(N, 0);
4009
4010 // fold (zext_inreg (extload x)) -> (zextload x)
4011 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
4012 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4013 EVT MemVT = LN0->getMemoryVT();
4014 // If we zero all the possible extended bits, then we can turn this into
4015 // a zextload if we are running before legalize or the operation is legal.
4016 unsigned BitWidth = N1.getScalarValueSizeInBits();
4017 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
4018 BitWidth - MemVT.getScalarSizeInBits())) &&
4019 ((!LegalOperations && !LN0->isVolatile()) ||
4020 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
4021 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
4022 LN0->getChain(), LN0->getBasePtr(),
4023 MemVT, LN0->getMemOperand());
4024 AddToWorklist(N);
4025 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4026 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4027 }
4028 }
4029 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
4030 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4031 N0.hasOneUse()) {
4032 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4033 EVT MemVT = LN0->getMemoryVT();
4034 // If we zero all the possible extended bits, then we can turn this into
4035 // a zextload if we are running before legalize or the operation is legal.
4036 unsigned BitWidth = N1.getScalarValueSizeInBits();
4037 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
4038 BitWidth - MemVT.getScalarSizeInBits())) &&
4039 ((!LegalOperations && !LN0->isVolatile()) ||
4040 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
4041 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
4042 LN0->getChain(), LN0->getBasePtr(),
4043 MemVT, LN0->getMemOperand());
4044 AddToWorklist(N);
4045 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4046 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4047 }
4048 }
4049 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
4050 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
4051 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4052 N0.getOperand(1), false))
4053 return BSwap;
4054 }
4055
4056 return SDValue();
4057}
4058
4059/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
4060SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
4061 bool DemandHighBits) {
4062 if (!LegalOperations)
4063 return SDValue();
4064
4065 EVT VT = N->getValueType(0);
4066 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
4067 return SDValue();
4068 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
4069 return SDValue();
4070
4071 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
4072 bool LookPassAnd0 = false;
4073 bool LookPassAnd1 = false;
4074 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
4075 std::swap(N0, N1);
4076 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
4077 std::swap(N0, N1);
4078 if (N0.getOpcode() == ISD::AND) {
4079 if (!N0.getNode()->hasOneUse())
4080 return SDValue();
4081 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4082 if (!N01C || N01C->getZExtValue() != 0xFF00)
4083 return SDValue();
4084 N0 = N0.getOperand(0);
4085 LookPassAnd0 = true;
4086 }
4087
4088 if (N1.getOpcode() == ISD::AND) {
4089 if (!N1.getNode()->hasOneUse())
4090 return SDValue();
4091 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4092 if (!N11C || N11C->getZExtValue() != 0xFF)
4093 return SDValue();
4094 N1 = N1.getOperand(0);
4095 LookPassAnd1 = true;
4096 }
4097
4098 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
4099 std::swap(N0, N1);
4100 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
4101 return SDValue();
4102 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
4103 return SDValue();
4104
4105 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4106 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4107 if (!N01C || !N11C)
4108 return SDValue();
4109 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
4110 return SDValue();
4111
4112 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
4113 SDValue N00 = N0->getOperand(0);
4114 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
4115 if (!N00.getNode()->hasOneUse())
4116 return SDValue();
4117 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
4118 if (!N001C || N001C->getZExtValue() != 0xFF)
4119 return SDValue();
4120 N00 = N00.getOperand(0);
4121 LookPassAnd0 = true;
4122 }
4123
4124 SDValue N10 = N1->getOperand(0);
4125 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
4126 if (!N10.getNode()->hasOneUse())
4127 return SDValue();
4128 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
4129 if (!N101C || N101C->getZExtValue() != 0xFF00)
4130 return SDValue();
4131 N10 = N10.getOperand(0);
4132 LookPassAnd1 = true;
4133 }
4134
4135 if (N00 != N10)
4136 return SDValue();
4137
4138 // Make sure everything beyond the low halfword gets set to zero since the SRL
4139 // 16 will clear the top bits.
4140 unsigned OpSizeInBits = VT.getSizeInBits();
4141 if (DemandHighBits && OpSizeInBits > 16) {
4142 // If the left-shift isn't masked out then the only way this is a bswap is
4143 // if all bits beyond the low 8 are 0. In that case the entire pattern
4144 // reduces to a left shift anyway: leave it for other parts of the combiner.
4145 if (!LookPassAnd0)
4146 return SDValue();
4147
4148 // However, if the right shift isn't masked out then it might be because
4149 // it's not needed. See if we can spot that too.
4150 if (!LookPassAnd1 &&
4151 !DAG.MaskedValueIsZero(
4152 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
4153 return SDValue();
4154 }
4155
4156 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
4157 if (OpSizeInBits > 16) {
4158 SDLoc DL(N);
4159 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
4160 DAG.getConstant(OpSizeInBits - 16, DL,
4161 getShiftAmountTy(VT)));
4162 }
4163 return Res;
4164}
4165
4166/// Return true if the specified node is an element that makes up a 32-bit
4167/// packed halfword byteswap.
4168/// ((x & 0x000000ff) << 8) |
4169/// ((x & 0x0000ff00) >> 8) |
4170/// ((x & 0x00ff0000) << 8) |
4171/// ((x & 0xff000000) >> 8)
4172static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
4173 if (!N.getNode()->hasOneUse())
4174 return false;
4175
4176 unsigned Opc = N.getOpcode();
4177 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
4178 return false;
4179
4180 SDValue N0 = N.getOperand(0);
4181 unsigned Opc0 = N0.getOpcode();
4182 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
4183 return false;
4184
4185 ConstantSDNode *N1C = nullptr;
4186 // SHL or SRL: look upstream for AND mask operand
4187 if (Opc == ISD::AND)
4188 N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
4189 else if (Opc0 == ISD::AND)
4190 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4191 if (!N1C)
4192 return false;
4193
4194 unsigned MaskByteOffset;
4195 switch (N1C->getZExtValue()) {
4196 default:
4197 return false;
4198 case 0xFF: MaskByteOffset = 0; break;
4199 case 0xFF00: MaskByteOffset = 1; break;
4200 case 0xFF0000: MaskByteOffset = 2; break;
4201 case 0xFF000000: MaskByteOffset = 3; break;
4202 }
4203
4204 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
4205 if (Opc == ISD::AND) {
4206 if (MaskByteOffset == 0 || MaskByteOffset == 2) {
4207 // (x >> 8) & 0xff
4208 // (x >> 8) & 0xff0000
4209 if (Opc0 != ISD::SRL)
4210 return false;
4211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4212 if (!C || C->getZExtValue() != 8)
4213 return false;
4214 } else {
4215 // (x << 8) & 0xff00
4216 // (x << 8) & 0xff000000
4217 if (Opc0 != ISD::SHL)
4218 return false;
4219 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4220 if (!C || C->getZExtValue() != 8)
4221 return false;
4222 }
4223 } else if (Opc == ISD::SHL) {
4224 // (x & 0xff) << 8
4225 // (x & 0xff0000) << 8
4226 if (MaskByteOffset != 0 && MaskByteOffset != 2)
4227 return false;
4228 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
4229 if (!C || C->getZExtValue() != 8)
4230 return false;
4231 } else { // Opc == ISD::SRL
4232 // (x & 0xff00) >> 8
4233 // (x & 0xff000000) >> 8
4234 if (MaskByteOffset != 1 && MaskByteOffset != 3)
4235 return false;
4236 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
4237 if (!C || C->getZExtValue() != 8)
4238 return false;
4239 }
4240
4241 if (Parts[MaskByteOffset])
4242 return false;
4243
4244 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
4245 return true;
4246}
4247
4248/// Match a 32-bit packed halfword bswap. That is
4249/// ((x & 0x000000ff) << 8) |
4250/// ((x & 0x0000ff00) >> 8) |
4251/// ((x & 0x00ff0000) << 8) |
4252/// ((x & 0xff000000) >> 8)
4253/// => (rotl (bswap x), 16)
4254SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
4255 if (!LegalOperations)
4256 return SDValue();
4257
4258 EVT VT = N->getValueType(0);
4259 if (VT != MVT::i32)
4260 return SDValue();
4261 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
4262 return SDValue();
4263
4264 // Look for either
4265 // (or (or (and), (and)), (or (and), (and)))
4266 // (or (or (or (and), (and)), (and)), (and))
4267 if (N0.getOpcode() != ISD::OR)
4268 return SDValue();
4269 SDValue N00 = N0.getOperand(0);
4270 SDValue N01 = N0.getOperand(1);
4271 SDNode *Parts[4] = {};
4272
4273 if (N1.getOpcode() == ISD::OR &&
4274 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
4275 // (or (or (and), (and)), (or (and), (and)))
4276 if (!isBSwapHWordElement(N00, Parts))
4277 return SDValue();
4278
4279 if (!isBSwapHWordElement(N01, Parts))
4280 return SDValue();
4281 SDValue N10 = N1.getOperand(0);
4282 if (!isBSwapHWordElement(N10, Parts))
4283 return SDValue();
4284 SDValue N11 = N1.getOperand(1);
4285 if (!isBSwapHWordElement(N11, Parts))
4286 return SDValue();
4287 } else {
4288 // (or (or (or (and), (and)), (and)), (and))
4289 if (!isBSwapHWordElement(N1, Parts))
4290 return SDValue();
4291 if (!isBSwapHWordElement(N01, Parts))
4292 return SDValue();
4293 if (N00.getOpcode() != ISD::OR)
4294 return SDValue();
4295 SDValue N000 = N00.getOperand(0);
4296 if (!isBSwapHWordElement(N000, Parts))
4297 return SDValue();
4298 SDValue N001 = N00.getOperand(1);
4299 if (!isBSwapHWordElement(N001, Parts))
4300 return SDValue();
4301 }
4302
4303 // Make sure the parts are all coming from the same node.
4304 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
4305 return SDValue();
4306
4307 SDLoc DL(N);
4308 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
4309 SDValue(Parts[0], 0));
4310
4311 // Result of the bswap should be rotated by 16. If it's not legal, then
4312 // do (x << 16) | (x >> 16).
4313 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
4314 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
4315 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
4316 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
4317 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
4318 return DAG.getNode(ISD::OR, DL, VT,
4319 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
4320 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
4321}
4322
4323/// This contains all DAGCombine rules which reduce two values combined by
4324/// an Or operation to a single value \see visitANDLike().
4325SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
4326 EVT VT = N1.getValueType();
4327 SDLoc DL(N);
4328
4329 // fold (or x, undef) -> -1
4330 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
4331 return DAG.getAllOnesConstant(DL, VT);
4332
4333 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
4334 return V;
4335
4336 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
4337 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
4338 // Don't increase # computations.
4339 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
4340 // We can only do this xform if we know that bits from X that are set in C2
4341 // but not in C1 are already zero. Likewise for Y.
4342 if (const ConstantSDNode *N0O1C =
4343 getAsNonOpaqueConstant(N0.getOperand(1))) {
4344 if (const ConstantSDNode *N1O1C =
4345 getAsNonOpaqueConstant(N1.getOperand(1))) {
4346 // We can only do this xform if we know that bits from X that are set in
4347 // C2 but not in C1 are already zero. Likewise for Y.
4348 const APInt &LHSMask = N0O1C->getAPIntValue();
4349 const APInt &RHSMask = N1O1C->getAPIntValue();
4350
4351 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
4352 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
4353 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
4354 N0.getOperand(0), N1.getOperand(0));
4355 return DAG.getNode(ISD::AND, DL, VT, X,
4356 DAG.getConstant(LHSMask | RHSMask, DL, VT));
4357 }
4358 }
4359 }
4360 }
4361
4362 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
4363 if (N0.getOpcode() == ISD::AND &&
4364 N1.getOpcode() == ISD::AND &&
4365 N0.getOperand(0) == N1.getOperand(0) &&
4366 // Don't increase # computations.
4367 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
4368 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
4369 N0.getOperand(1), N1.getOperand(1));
4370 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
4371 }
4372
4373 return SDValue();
4374}
4375
4376SDValue DAGCombiner::visitOR(SDNode *N) {
4377 SDValue N0 = N->getOperand(0);
4378 SDValue N1 = N->getOperand(1);
4379 EVT VT = N1.getValueType();
4380
4381 // x | x --> x
4382 if (N0 == N1)
4383 return N0;
4384
4385 // fold vector ops
4386 if (VT.isVector()) {
4387 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4388 return FoldedVOp;
4389
4390 // fold (or x, 0) -> x, vector edition
4391 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4392 return N1;
4393 if (ISD::isBuildVectorAllZeros(N1.getNode()))
4394 return N0;
4395
4396 // fold (or x, -1) -> -1, vector edition
4397 if (ISD::isBuildVectorAllOnes(N0.getNode()))
4398 // do not return N0, because undef node may exist in N0
4399 return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
4400 if (ISD::isBuildVectorAllOnes(N1.getNode()))
4401 // do not return N1, because undef node may exist in N1
4402 return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
4403
4404 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
4405 // Do this only if the resulting shuffle is legal.
4406 if (isa<ShuffleVectorSDNode>(N0) &&
4407 isa<ShuffleVectorSDNode>(N1) &&
4408 // Avoid folding a node with illegal type.
4409 TLI.isTypeLegal(VT)) {
4410 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
4411 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
4412 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4413 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode());
4414 // Ensure both shuffles have a zero input.
4415 if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) {
4416 assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!")(static_cast <bool> ((!ZeroN00 || !ZeroN01) && "Both inputs zero!"
) ? void (0) : __assert_fail ("(!ZeroN00 || !ZeroN01) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4416, __extension__ __PRETTY_FUNCTION__))
;
4417 assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!")(static_cast <bool> ((!ZeroN10 || !ZeroN11) && "Both inputs zero!"
) ? void (0) : __assert_fail ("(!ZeroN10 || !ZeroN11) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4417, __extension__ __PRETTY_FUNCTION__))
;
4418 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
4419 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
4420 bool CanFold = true;
4421 int NumElts = VT.getVectorNumElements();
4422 SmallVector<int, 4> Mask(NumElts);
4423
4424 for (int i = 0; i != NumElts; ++i) {
4425 int M0 = SV0->getMaskElt(i);
4426 int M1 = SV1->getMaskElt(i);
4427
4428 // Determine if either index is pointing to a zero vector.
4429 bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts));
4430 bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts));
4431
4432 // If one element is zero and the otherside is undef, keep undef.
4433 // This also handles the case that both are undef.
4434 if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) {
4435 Mask[i] = -1;
4436 continue;
4437 }
4438
4439 // Make sure only one of the elements is zero.
4440 if (M0Zero == M1Zero) {
4441 CanFold = false;
4442 break;
4443 }
4444
4445 assert((M0 >= 0 || M1 >= 0) && "Undef index!")(static_cast <bool> ((M0 >= 0 || M1 >= 0) &&
"Undef index!") ? void (0) : __assert_fail ("(M0 >= 0 || M1 >= 0) && \"Undef index!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4445, __extension__ __PRETTY_FUNCTION__))
;
4446
4447 // We have a zero and non-zero element. If the non-zero came from
4448 // SV0 make the index a LHS index. If it came from SV1, make it
4449 // a RHS index. We need to mod by NumElts because we don't care
4450 // which operand it came from in the original shuffles.
4451 Mask[i] = M1Zero ? M0 % NumElts : (M1 % NumElts) + NumElts;
4452 }
4453
4454 if (CanFold) {
4455 SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
4456 SDValue NewRHS = ZeroN10 ? N1.getOperand(1) : N1.getOperand(0);
4457
4458 bool LegalMask = TLI.isShuffleMaskLegal(Mask, VT);
4459 if (!LegalMask) {
4460 std::swap(NewLHS, NewRHS);
4461 ShuffleVectorSDNode::commuteMask(Mask);
4462 LegalMask = TLI.isShuffleMaskLegal(Mask, VT);
4463 }
4464
4465 if (LegalMask)
4466 return DAG.getVectorShuffle(VT, SDLoc(N), NewLHS, NewRHS, Mask);
4467 }
4468 }
4469 }
4470 }
4471
4472 // fold (or c1, c2) -> c1|c2
4473 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4474 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4475 if (N0C && N1C && !N1C->isOpaque())
4476 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
4477 // canonicalize constant to RHS
4478 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4479 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4480 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
4481 // fold (or x, 0) -> x
4482 if (isNullConstant(N1))
4483 return N0;
4484 // fold (or x, -1) -> -1
4485 if (isAllOnesConstant(N1))
4486 return N1;
4487
4488 if (SDValue NewSel = foldBinOpIntoSelect(N))
4489 return NewSel;
4490
4491 // fold (or x, c) -> c iff (x & ~c) == 0
4492 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
4493 return N1;
4494
4495 if (SDValue Combined = visitORLike(N0, N1, N))
4496 return Combined;
4497
4498 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
4499 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
4500 return BSwap;
4501 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
4502 return BSwap;
4503
4504 // reassociate or
4505 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1))
4506 return ROR;
4507
4508 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
4509 // iff (c1 & c2) != 0.
4510 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse()) {
4511 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4512 if (C1->getAPIntValue().intersects(N1C->getAPIntValue())) {
4513 if (SDValue COR =
4514 DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT, N1C, C1))
4515 return DAG.getNode(
4516 ISD::AND, SDLoc(N), VT,
4517 DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1), COR);
4518 return SDValue();
4519 }
4520 }
4521 }
4522
4523 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
4524 if (N0.getOpcode() == N1.getOpcode())
4525 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
4526 return Tmp;
4527
4528 // See if this is some rotate idiom.
4529 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
4530 return SDValue(Rot, 0);
4531
4532 if (SDValue Load = MatchLoadCombine(N))
4533 return Load;
4534
4535 // Simplify the operands using demanded-bits information.
4536 if (SimplifyDemandedBits(SDValue(N, 0)))
4537 return SDValue(N, 0);
4538
4539 return SDValue();
4540}
4541
4542/// Match "(X shl/srl V1) & V2" where V2 may not be present.
4543bool DAGCombiner::MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
4544 if (Op.getOpcode() == ISD::AND) {
4545 if (DAG.isConstantIntBuildVectorOrConstantInt(Op.getOperand(1))) {
4546 Mask = Op.getOperand(1);
4547 Op = Op.getOperand(0);
4548 } else {
4549 return false;
4550 }
4551 }
4552
4553 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
4554 Shift = Op;
4555 return true;
4556 }
4557
4558 return false;
4559}
4560
4561// Return true if we can prove that, whenever Neg and Pos are both in the
4562// range [0, EltSize), Neg == (Pos == 0 ? 0 : EltSize - Pos). This means that
4563// for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
4564//
4565// (or (shift1 X, Neg), (shift2 X, Pos))
4566//
4567// reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
4568// in direction shift1 by Neg. The range [0, EltSize) means that we only need
4569// to consider shift amounts with defined behavior.
4570static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize) {
4571 // If EltSize is a power of 2 then:
4572 //
4573 // (a) (Pos == 0 ? 0 : EltSize - Pos) == (EltSize - Pos) & (EltSize - 1)
4574 // (b) Neg == Neg & (EltSize - 1) whenever Neg is in [0, EltSize).
4575 //
4576 // So if EltSize is a power of 2 and Neg is (and Neg', EltSize-1), we check
4577 // for the stronger condition:
4578 //
4579 // Neg & (EltSize - 1) == (EltSize - Pos) & (EltSize - 1) [A]
4580 //
4581 // for all Neg and Pos. Since Neg & (EltSize - 1) == Neg' & (EltSize - 1)
4582 // we can just replace Neg with Neg' for the rest of the function.
4583 //
4584 // In other cases we check for the even stronger condition:
4585 //
4586 // Neg == EltSize - Pos [B]
4587 //
4588 // for all Neg and Pos. Note that the (or ...) then invokes undefined
4589 // behavior if Pos == 0 (and consequently Neg == EltSize).
4590 //
4591 // We could actually use [A] whenever EltSize is a power of 2, but the
4592 // only extra cases that it would match are those uninteresting ones
4593 // where Neg and Pos are never in range at the same time. E.g. for
4594 // EltSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
4595 // as well as (sub 32, Pos), but:
4596 //
4597 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
4598 //
4599 // always invokes undefined behavior for 32-bit X.
4600 //
4601 // Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise.
4602 unsigned MaskLoBits = 0;
4603 if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
4604 if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
4605 if (NegC->getAPIntValue() == EltSize - 1) {
4606 Neg = Neg.getOperand(0);
4607 MaskLoBits = Log2_64(EltSize);
4608 }
4609 }
4610 }
4611
4612 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
4613 if (Neg.getOpcode() != ISD::SUB)
4614 return false;
4615 ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0));
4616 if (!NegC)
4617 return false;
4618 SDValue NegOp1 = Neg.getOperand(1);
4619
4620 // On the RHS of [A], if Pos is Pos' & (EltSize - 1), just replace Pos with
4621 // Pos'. The truncation is redundant for the purpose of the equality.
4622 if (MaskLoBits && Pos.getOpcode() == ISD::AND)
4623 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
4624 if (PosC->getAPIntValue() == EltSize - 1)
4625 Pos = Pos.getOperand(0);
4626
4627 // The condition we need is now:
4628 //
4629 // (NegC - NegOp1) & Mask == (EltSize - Pos) & Mask
4630 //
4631 // If NegOp1 == Pos then we need:
4632 //
4633 // EltSize & Mask == NegC & Mask
4634 //
4635 // (because "x & Mask" is a truncation and distributes through subtraction).
4636 APInt Width;
4637 if (Pos == NegOp1)
4638 Width = NegC->getAPIntValue();
4639
4640 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
4641 // Then the condition we want to prove becomes:
4642 //
4643 // (NegC - NegOp1) & Mask == (EltSize - (NegOp1 + PosC)) & Mask
4644 //
4645 // which, again because "x & Mask" is a truncation, becomes:
4646 //
4647 // NegC & Mask == (EltSize - PosC) & Mask
4648 // EltSize & Mask == (NegC + PosC) & Mask
4649 else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
4650 if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
4651 Width = PosC->getAPIntValue() + NegC->getAPIntValue();
4652 else
4653 return false;
4654 } else
4655 return false;
4656
4657 // Now we just need to check that EltSize & Mask == Width & Mask.
4658 if (MaskLoBits)
4659 // EltSize & Mask is 0 since Mask is EltSize - 1.
4660 return Width.getLoBits(MaskLoBits) == 0;
4661 return Width == EltSize;
4662}
4663
4664// A subroutine of MatchRotate used once we have found an OR of two opposite
4665// shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
4666// to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
4667// former being preferred if supported. InnerPos and InnerNeg are Pos and
4668// Neg with outer conversions stripped away.
4669SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
4670 SDValue Neg, SDValue InnerPos,
4671 SDValue InnerNeg, unsigned PosOpcode,
4672 unsigned NegOpcode, const SDLoc &DL) {
4673 // fold (or (shl x, (*ext y)),
4674 // (srl x, (*ext (sub 32, y)))) ->
4675 // (rotl x, y) or (rotr x, (sub 32, y))
4676 //
4677 // fold (or (shl x, (*ext (sub 32, y))),
4678 // (srl x, (*ext y))) ->
4679 // (rotr x, y) or (rotl x, (sub 32, y))
4680 EVT VT = Shifted.getValueType();
4681 if (matchRotateSub(InnerPos, InnerNeg, VT.getScalarSizeInBits())) {
4682 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
4683 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
4684 HasPos ? Pos : Neg).getNode();
4685 }
4686
4687 return nullptr;
4688}
4689
4690// MatchRotate - Handle an 'or' of two operands. If this is one of the many
4691// idioms for rotate, and if the target supports rotation instructions, generate
4692// a rot[lr].
4693SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
4694 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
4695 EVT VT = LHS.getValueType();
4696 if (!TLI.isTypeLegal(VT)) return nullptr;
4697
4698 // The target must have at least one rotate flavor.
4699 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
4700 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
4701 if (!HasROTL && !HasROTR) return nullptr;
4702
4703 // Match "(X shl/srl V1) & V2" where V2 may not be present.
4704 SDValue LHSShift; // The shift.
4705 SDValue LHSMask; // AND value if any.
4706 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
4707 return nullptr; // Not part of a rotate.
4708
4709 SDValue RHSShift; // The shift.
4710 SDValue RHSMask; // AND value if any.
4711 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
4712 return nullptr; // Not part of a rotate.
4713
4714 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
4715 return nullptr; // Not shifting the same value.
4716
4717 if (LHSShift.getOpcode() == RHSShift.getOpcode())
4718 return nullptr; // Shifts must disagree.
4719
4720 // Canonicalize shl to left side in a shl/srl pair.
4721 if (RHSShift.getOpcode() == ISD::SHL) {
4722 std::swap(LHS, RHS);
4723 std::swap(LHSShift, RHSShift);
4724 std::swap(LHSMask, RHSMask);
4725 }
4726
4727 unsigned EltSizeInBits = VT.getScalarSizeInBits();
4728 SDValue LHSShiftArg = LHSShift.getOperand(0);
4729 SDValue LHSShiftAmt = LHSShift.getOperand(1);
4730 SDValue RHSShiftArg = RHSShift.getOperand(0);
4731 SDValue RHSShiftAmt = RHSShift.getOperand(1);
4732
4733 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
4734 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
4735 auto MatchRotateSum = [EltSizeInBits](ConstantSDNode *LHS,
4736 ConstantSDNode *RHS) {
4737 return (LHS->getAPIntValue() + RHS->getAPIntValue()) == EltSizeInBits;
4738 };
4739 if (matchBinaryPredicate(LHSShiftAmt, RHSShiftAmt, MatchRotateSum)) {
4740 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
4741 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
4742
4743 // If there is an AND of either shifted operand, apply it to the result.
4744 if (LHSMask.getNode() || RHSMask.getNode()) {
4745 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
4746 SDValue Mask = AllOnes;
4747
4748 if (LHSMask.getNode()) {
4749 SDValue RHSBits = DAG.getNode(ISD::SRL, DL, VT, AllOnes, RHSShiftAmt);
4750 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
4751 DAG.getNode(ISD::OR, DL, VT, LHSMask, RHSBits));
4752 }
4753 if (RHSMask.getNode()) {
4754 SDValue LHSBits = DAG.getNode(ISD::SHL, DL, VT, AllOnes, LHSShiftAmt);
4755 Mask = DAG.getNode(ISD::AND, DL, VT, Mask,
4756 DAG.getNode(ISD::OR, DL, VT, RHSMask, LHSBits));
4757 }
4758
4759 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, Mask);
4760 }
4761
4762 return Rot.getNode();
4763 }
4764
4765 // If there is a mask here, and we have a variable shift, we can't be sure
4766 // that we're masking out the right stuff.
4767 if (LHSMask.getNode() || RHSMask.getNode())
4768 return nullptr;
4769
4770 // If the shift amount is sign/zext/any-extended just peel it off.
4771 SDValue LExtOp0 = LHSShiftAmt;
4772 SDValue RExtOp0 = RHSShiftAmt;
4773 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
4774 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
4775 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
4776 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
4777 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
4778 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
4779 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
4780 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
4781 LExtOp0 = LHSShiftAmt.getOperand(0);
4782 RExtOp0 = RHSShiftAmt.getOperand(0);
4783 }
4784
4785 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
4786 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
4787 if (TryL)
4788 return TryL;
4789
4790 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
4791 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
4792 if (TryR)
4793 return TryR;
4794
4795 return nullptr;
4796}
4797
4798namespace {
4799
4800/// Represents known origin of an individual byte in load combine pattern. The
4801/// value of the byte is either constant zero or comes from memory.
4802struct ByteProvider {
4803 // For constant zero providers Load is set to nullptr. For memory providers
4804 // Load represents the node which loads the byte from memory.
4805 // ByteOffset is the offset of the byte in the value produced by the load.
4806 LoadSDNode *Load = nullptr;
4807 unsigned ByteOffset = 0;
4808
4809 ByteProvider() = default;
4810
4811 static ByteProvider getMemory(LoadSDNode *Load, unsigned ByteOffset) {
4812 return ByteProvider(Load, ByteOffset);
4813 }
4814
4815 static ByteProvider getConstantZero() { return ByteProvider(nullptr, 0); }
4816
4817 bool isConstantZero() const { return !Load; }
4818 bool isMemory() const { return Load; }
4819
4820 bool operator==(const ByteProvider &Other) const {
4821 return Other.Load == Load && Other.ByteOffset == ByteOffset;
4822 }
4823
4824private:
4825 ByteProvider(LoadSDNode *Load, unsigned ByteOffset)
4826 : Load(Load), ByteOffset(ByteOffset) {}
4827};
4828
4829} // end anonymous namespace
4830
4831/// Recursively traverses the expression calculating the origin of the requested
4832/// byte of the given value. Returns None if the provider can't be calculated.
4833///
4834/// For all the values except the root of the expression verifies that the value
4835/// has exactly one use and if it's not true return None. This way if the origin
4836/// of the byte is returned it's guaranteed that the values which contribute to
4837/// the byte are not used outside of this expression.
4838///
4839/// Because the parts of the expression are not allowed to have more than one
4840/// use this function iterates over trees, not DAGs. So it never visits the same
4841/// node more than once.
4842static const Optional<ByteProvider>
4843calculateByteProvider(SDValue Op, unsigned Index, unsigned Depth,
4844 bool Root = false) {
4845 // Typical i64 by i8 pattern requires recursion up to 8 calls depth
4846 if (Depth == 10)
4847 return None;
4848
4849 if (!Root && !Op.hasOneUse())
4850 return None;
4851
4852 assert(Op.getValueType().isScalarInteger() && "can't handle other types")(static_cast <bool> (Op.getValueType().isScalarInteger(
) && "can't handle other types") ? void (0) : __assert_fail
("Op.getValueType().isScalarInteger() && \"can't handle other types\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4852, __extension__ __PRETTY_FUNCTION__))
;
4853 unsigned BitWidth = Op.getValueSizeInBits();
4854 if (BitWidth % 8 != 0)
4855 return None;
4856 unsigned ByteWidth = BitWidth / 8;
4857 assert(Index < ByteWidth && "invalid index requested")(static_cast <bool> (Index < ByteWidth && "invalid index requested"
) ? void (0) : __assert_fail ("Index < ByteWidth && \"invalid index requested\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4857, __extension__ __PRETTY_FUNCTION__))
;
4858 (void) ByteWidth;
4859
4860 switch (Op.getOpcode()) {
4861 case ISD::OR: {
4862 auto LHS = calculateByteProvider(Op->getOperand(0), Index, Depth + 1);
4863 if (!LHS)
4864 return None;
4865 auto RHS = calculateByteProvider(Op->getOperand(1), Index, Depth + 1);
4866 if (!RHS)
4867 return None;
4868
4869 if (LHS->isConstantZero())
4870 return RHS;
4871 if (RHS->isConstantZero())
4872 return LHS;
4873 return None;
4874 }
4875 case ISD::SHL: {
4876 auto ShiftOp = dyn_cast<ConstantSDNode>(Op->getOperand(1));
4877 if (!ShiftOp)
4878 return None;
4879
4880 uint64_t BitShift = ShiftOp->getZExtValue();
4881 if (BitShift % 8 != 0)
4882 return None;
4883 uint64_t ByteShift = BitShift / 8;
4884
4885 return Index < ByteShift
4886 ? ByteProvider::getConstantZero()
4887 : calculateByteProvider(Op->getOperand(0), Index - ByteShift,
4888 Depth + 1);
4889 }
4890 case ISD::ANY_EXTEND:
4891 case ISD::SIGN_EXTEND:
4892 case ISD::ZERO_EXTEND: {
4893 SDValue NarrowOp = Op->getOperand(0);
4894 unsigned NarrowBitWidth = NarrowOp.getScalarValueSizeInBits();
4895 if (NarrowBitWidth % 8 != 0)
4896 return None;
4897 uint64_t NarrowByteWidth = NarrowBitWidth / 8;
4898
4899 if (Index >= NarrowByteWidth)
4900 return Op.getOpcode() == ISD::ZERO_EXTEND
4901 ? Optional<ByteProvider>(ByteProvider::getConstantZero())
4902 : None;
4903 return calculateByteProvider(NarrowOp, Index, Depth + 1);
4904 }
4905 case ISD::BSWAP:
4906 return calculateByteProvider(Op->getOperand(0), ByteWidth - Index - 1,
4907 Depth + 1);
4908 case ISD::LOAD: {
4909 auto L = cast<LoadSDNode>(Op.getNode());
4910 if (L->isVolatile() || L->isIndexed())
4911 return None;
4912
4913 unsigned NarrowBitWidth = L->getMemoryVT().getSizeInBits();
4914 if (NarrowBitWidth % 8 != 0)
4915 return None;
4916 uint64_t NarrowByteWidth = NarrowBitWidth / 8;
4917
4918 if (Index >= NarrowByteWidth)
4919 return L->getExtensionType() == ISD::ZEXTLOAD
4920 ? Optional<ByteProvider>(ByteProvider::getConstantZero())
4921 : None;
4922 return ByteProvider::getMemory(L, Index);
4923 }
4924 }
4925
4926 return None;
4927}
4928
4929/// Match a pattern where a wide type scalar value is loaded by several narrow
4930/// loads and combined by shifts and ors. Fold it into a single load or a load
4931/// and a BSWAP if the targets supports it.
4932///
4933/// Assuming little endian target:
4934/// i8 *a = ...
4935/// i32 val = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24)
4936/// =>
4937/// i32 val = *((i32)a)
4938///
4939/// i8 *a = ...
4940/// i32 val = (a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]
4941/// =>
4942/// i32 val = BSWAP(*((i32)a))
4943///
4944/// TODO: This rule matches complex patterns with OR node roots and doesn't
4945/// interact well with the worklist mechanism. When a part of the pattern is
4946/// updated (e.g. one of the loads) its direct users are put into the worklist,
4947/// but the root node of the pattern which triggers the load combine is not
4948/// necessarily a direct user of the changed node. For example, once the address
4949/// of t28 load is reassociated load combine won't be triggered:
4950/// t25: i32 = add t4, Constant:i32<2>
4951/// t26: i64 = sign_extend t25
4952/// t27: i64 = add t2, t26
4953/// t28: i8,ch = load<LD1[%tmp9]> t0, t27, undef:i64
4954/// t29: i32 = zero_extend t28
4955/// t32: i32 = shl t29, Constant:i8<8>
4956/// t33: i32 = or t23, t32
4957/// As a possible fix visitLoad can check if the load can be a part of a load
4958/// combine pattern and add corresponding OR roots to the worklist.
4959SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
4960 assert(N->getOpcode() == ISD::OR &&(static_cast <bool> (N->getOpcode() == ISD::OR &&
"Can only match load combining against OR nodes") ? void (0)
: __assert_fail ("N->getOpcode() == ISD::OR && \"Can only match load combining against OR nodes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4961, __extension__ __PRETTY_FUNCTION__))
4961 "Can only match load combining against OR nodes")(static_cast <bool> (N->getOpcode() == ISD::OR &&
"Can only match load combining against OR nodes") ? void (0)
: __assert_fail ("N->getOpcode() == ISD::OR && \"Can only match load combining against OR nodes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4961, __extension__ __PRETTY_FUNCTION__))
;
4962
4963 // Handles simple types only
4964 EVT VT = N->getValueType(0);
4965 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
4966 return SDValue();
4967 unsigned ByteWidth = VT.getSizeInBits() / 8;
4968
4969 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4970 // Before legalize we can introduce too wide illegal loads which will be later
4971 // split into legal sized loads. This enables us to combine i64 load by i8
4972 // patterns to a couple of i32 loads on 32 bit targets.
4973 if (LegalOperations && !TLI.isOperationLegal(ISD::LOAD, VT))
4974 return SDValue();
4975
4976 std::function<unsigned(unsigned, unsigned)> LittleEndianByteAt = [](
4977 unsigned BW, unsigned i) { return i; };
4978 std::function<unsigned(unsigned, unsigned)> BigEndianByteAt = [](
4979 unsigned BW, unsigned i) { return BW - i - 1; };
4980
4981 bool IsBigEndianTarget = DAG.getDataLayout().isBigEndian();
4982 auto MemoryByteOffset = [&] (ByteProvider P) {
4983 assert(P.isMemory() && "Must be a memory byte provider")(static_cast <bool> (P.isMemory() && "Must be a memory byte provider"
) ? void (0) : __assert_fail ("P.isMemory() && \"Must be a memory byte provider\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4983, __extension__ __PRETTY_FUNCTION__))
;
4984 unsigned LoadBitWidth = P.Load->getMemoryVT().getSizeInBits();
4985 assert(LoadBitWidth % 8 == 0 &&(static_cast <bool> (LoadBitWidth % 8 == 0 && "can only analyze providers for individual bytes not bit"
) ? void (0) : __assert_fail ("LoadBitWidth % 8 == 0 && \"can only analyze providers for individual bytes not bit\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4986, __extension__ __PRETTY_FUNCTION__))
4986 "can only analyze providers for individual bytes not bit")(static_cast <bool> (LoadBitWidth % 8 == 0 && "can only analyze providers for individual bytes not bit"
) ? void (0) : __assert_fail ("LoadBitWidth % 8 == 0 && \"can only analyze providers for individual bytes not bit\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4986, __extension__ __PRETTY_FUNCTION__))
;
4987 unsigned LoadByteWidth = LoadBitWidth / 8;
4988 return IsBigEndianTarget
4989 ? BigEndianByteAt(LoadByteWidth, P.ByteOffset)
4990 : LittleEndianByteAt(LoadByteWidth, P.ByteOffset);
4991 };
4992
4993 Optional<BaseIndexOffset> Base;
4994 SDValue Chain;
4995
4996 SmallSet<LoadSDNode *, 8> Loads;
4997 Optional<ByteProvider> FirstByteProvider;
4998 int64_t FirstOffset = INT64_MAX(9223372036854775807L);
4999
5000 // Check if all the bytes of the OR we are looking at are loaded from the same
5001 // base address. Collect bytes offsets from Base address in ByteOffsets.
5002 SmallVector<int64_t, 4> ByteOffsets(ByteWidth);
5003 for (unsigned i = 0; i < ByteWidth; i++) {
5004 auto P = calculateByteProvider(SDValue(N, 0), i, 0, /*Root=*/true);
5005 if (!P || !P->isMemory()) // All the bytes must be loaded from memory
5006 return SDValue();
5007
5008 LoadSDNode *L = P->Load;
5009 assert(L->hasNUsesOfValue(1, 0) && !L->isVolatile() && !L->isIndexed() &&(static_cast <bool> (L->hasNUsesOfValue(1, 0) &&
!L->isVolatile() && !L->isIndexed() &&
"Must be enforced by calculateByteProvider") ? void (0) : __assert_fail
("L->hasNUsesOfValue(1, 0) && !L->isVolatile() && !L->isIndexed() && \"Must be enforced by calculateByteProvider\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5010, __extension__ __PRETTY_FUNCTION__))
5010 "Must be enforced by calculateByteProvider")(static_cast <bool> (L->hasNUsesOfValue(1, 0) &&
!L->isVolatile() && !L->isIndexed() &&
"Must be enforced by calculateByteProvider") ? void (0) : __assert_fail
("L->hasNUsesOfValue(1, 0) && !L->isVolatile() && !L->isIndexed() && \"Must be enforced by calculateByteProvider\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5010, __extension__ __PRETTY_FUNCTION__))
;
5011 assert(L->getOffset().isUndef() && "Unindexed load must have undef offset")(static_cast <bool> (L->getOffset().isUndef() &&
"Unindexed load must have undef offset") ? void (0) : __assert_fail
("L->getOffset().isUndef() && \"Unindexed load must have undef offset\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5011, __extension__ __PRETTY_FUNCTION__))
;
5012
5013 // All loads must share the same chain
5014 SDValue LChain = L->getChain();
5015 if (!Chain)
5016 Chain = LChain;
5017 else if (Chain != LChain)
5018 return SDValue();
5019
5020 // Loads must share the same base address
5021 BaseIndexOffset Ptr = BaseIndexOffset::match(L->getBasePtr(), DAG);
5022 int64_t ByteOffsetFromBase = 0;
5023 if (!Base)
5024 Base = Ptr;
5025 else if (!Base->equalBaseIndex(Ptr, DAG, ByteOffsetFromBase))
5026 return SDValue();
5027
5028 // Calculate the offset of the current byte from the base address
5029 ByteOffsetFromBase += MemoryByteOffset(*P);
5030 ByteOffsets[i] = ByteOffsetFromBase;
5031
5032 // Remember the first byte load
5033 if (ByteOffsetFromBase < FirstOffset) {
5034 FirstByteProvider = P;
5035 FirstOffset = ByteOffsetFromBase;
5036 }
5037
5038 Loads.insert(L);
5039 }
5040 assert(!Loads.empty() && "All the bytes of the value must be loaded from "(static_cast <bool> (!Loads.empty() && "All the bytes of the value must be loaded from "
"memory, so there must be at least one load which produces the value"
) ? void (0) : __assert_fail ("!Loads.empty() && \"All the bytes of the value must be loaded from \" \"memory, so there must be at least one load which produces the value\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5041, __extension__ __PRETTY_FUNCTION__))
5041 "memory, so there must be at least one load which produces the value")(static_cast <bool> (!Loads.empty() && "All the bytes of the value must be loaded from "
"memory, so there must be at least one load which produces the value"
) ? void (0) : __assert_fail ("!Loads.empty() && \"All the bytes of the value must be loaded from \" \"memory, so there must be at least one load which produces the value\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5041, __extension__ __PRETTY_FUNCTION__))
;
5042 assert(Base && "Base address of the accessed memory location must be set")(static_cast <bool> (Base && "Base address of the accessed memory location must be set"
) ? void (0) : __assert_fail ("Base && \"Base address of the accessed memory location must be set\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5042, __extension__ __PRETTY_FUNCTION__))
;
5043 assert(FirstOffset != INT64_MAX && "First byte offset must be set")(static_cast <bool> (FirstOffset != (9223372036854775807L
) && "First byte offset must be set") ? void (0) : __assert_fail
("FirstOffset != INT64_MAX && \"First byte offset must be set\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5043, __extension__ __PRETTY_FUNCTION__))
;
5044
5045 // Check if the bytes of the OR we are looking at match with either big or
5046 // little endian value load
5047 bool BigEndian = true, LittleEndian = true;
5048 for (unsigned i = 0; i < ByteWidth; i++) {
5049 int64_t CurrentByteOffset = ByteOffsets[i] - FirstOffset;
5050 LittleEndian &= CurrentByteOffset == LittleEndianByteAt(ByteWidth, i);
5051 BigEndian &= CurrentByteOffset == BigEndianByteAt(ByteWidth, i);
5052 if (!BigEndian && !LittleEndian)
5053 return SDValue();
5054 }
5055 assert((BigEndian != LittleEndian) && "should be either or")(static_cast <bool> ((BigEndian != LittleEndian) &&
"should be either or") ? void (0) : __assert_fail ("(BigEndian != LittleEndian) && \"should be either or\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5055, __extension__ __PRETTY_FUNCTION__))
;
5056 assert(FirstByteProvider && "must be set")(static_cast <bool> (FirstByteProvider && "must be set"
) ? void (0) : __assert_fail ("FirstByteProvider && \"must be set\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5056, __extension__ __PRETTY_FUNCTION__))
;
5057
5058 // Ensure that the first byte is loaded from zero offset of the first load.
5059 // So the combined value can be loaded from the first load address.
5060 if (MemoryByteOffset(*FirstByteProvider) != 0)
5061 return SDValue();
5062 LoadSDNode *FirstLoad = FirstByteProvider->Load;
5063
5064 // The node we are looking at matches with the pattern, check if we can
5065 // replace it with a single load and bswap if needed.
5066
5067 // If the load needs byte swap check if the target supports it
5068 bool NeedsBswap = IsBigEndianTarget != BigEndian;
5069
5070 // Before legalize we can introduce illegal bswaps which will be later
5071 // converted to an explicit bswap sequence. This way we end up with a single
5072 // load and byte shuffling instead of several loads and byte shuffling.
5073 if (NeedsBswap && LegalOperations && !TLI.isOperationLegal(ISD::BSWAP, VT))
5074 return SDValue();
5075
5076 // Check that a load of the wide type is both allowed and fast on the target
5077 bool Fast = false;
5078 bool Allowed = TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
5079 VT, FirstLoad->getAddressSpace(),
5080 FirstLoad->getAlignment(), &Fast);
5081 if (!Allowed || !Fast)
5082 return SDValue();
5083
5084 SDValue NewLoad =
5085 DAG.getLoad(VT, SDLoc(N), Chain, FirstLoad->getBasePtr(),
5086 FirstLoad->getPointerInfo(), FirstLoad->getAlignment());
5087
5088 // Transfer chain users from old loads to the new load.
5089 for (LoadSDNode *L : Loads)
5090 DAG.ReplaceAllUsesOfValueWith(SDValue(L, 1), SDValue(NewLoad.getNode(), 1));
5091
5092 return NeedsBswap ? DAG.getNode(ISD::BSWAP, SDLoc(N), VT, NewLoad) : NewLoad;
5093}
5094
5095SDValue DAGCombiner::visitXOR(SDNode *N) {
5096 SDValue N0 = N->getOperand(0);
5097 SDValue N1 = N->getOperand(1);
5098 EVT VT = N0.getValueType();
5099
5100 // fold vector ops
5101 if (VT.isVector()) {
5102 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5103 return FoldedVOp;
5104
5105 // fold (xor x, 0) -> x, vector edition
5106 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5107 return N1;
5108 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5109 return N0;
5110 }
5111
5112 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
5113 if (N0.isUndef() && N1.isUndef())
5114 return DAG.getConstant(0, SDLoc(N), VT);
5115 // fold (xor x, undef) -> undef
5116 if (N0.isUndef())
5117 return N0;
5118 if (N1.isUndef())
5119 return N1;
5120 // fold (xor c1, c2) -> c1^c2
5121 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
5122 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
5123 if (N0C && N1C)
5124 return DAG.FoldConstantArithmetic(ISD::XOR, SDLoc(N), VT, N0C, N1C);
5125 // canonicalize constant to RHS
5126 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5127 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5128 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
5129 // fold (xor x, 0) -> x
5130 if (isNullConstant(N1))
5131 return N0;
5132
5133 if (SDValue NewSel = foldBinOpIntoSelect(N))
5134 return NewSel;
5135
5136 // reassociate xor
5137 if (SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1))
5138 return RXOR;
5139
5140 // fold !(x cc y) -> (x !cc y)
5141 SDValue LHS, RHS, CC;
5142 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
5143 bool isInt = LHS.getValueType().isInteger();
5144 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
5145 isInt);
5146
5147 if (!LegalOperations ||
5148 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
5149 switch (N0.getOpcode()) {
5150 default:
5151 llvm_unreachable("Unhandled SetCC Equivalent!")::llvm::llvm_unreachable_internal("Unhandled SetCC Equivalent!"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5151)
;
5152 case ISD::SETCC:
5153 return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC);
5154 case ISD::SELECT_CC:
5155 return DAG.getSelectCC(SDLoc(N0), LHS, RHS, N0.getOperand(2),
5156 N0.getOperand(3), NotCC);
5157 }
5158 }
5159 }
5160
5161 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
5162 if (isOneConstant(N1) && N0.getOpcode() == ISD::ZERO_EXTEND &&
5163 N0.getNode()->hasOneUse() &&
5164 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
5165 SDValue V = N0.getOperand(0);
5166 SDLoc DL(N0);
5167 V = DAG.getNode(ISD::XOR, DL, V.getValueType(), V,
5168 DAG.getConstant(1, DL, V.getValueType()));
5169 AddToWorklist(V.getNode());
5170 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
5171 }
5172
5173 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
5174 if (isOneConstant(N1) && VT == MVT::i1 &&
5175 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
5176 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5177 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
5178 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
5179 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
5180 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
5181 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
5182 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
5183 }
5184 }
5185 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
5186 if (isAllOnesConstant(N1) &&
5187 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
5188 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5189 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
5190 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
5191 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
5192 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
5193 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
5194 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
5195 }
5196 }
5197 // fold (xor (and x, y), y) -> (and (not x), y)
5198 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
5199 N0->getOperand(1) == N1) {
5200 SDValue X = N0->getOperand(0);
5201 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
5202 AddToWorklist(NotX.getNode());
5203 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
5204 }
5205 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
5206 if (N1C && N0.getOpcode() == ISD::XOR) {
5207 if (const ConstantSDNode *N00C = getAsNonOpaqueConstant(N0.getOperand(0))) {
5208 SDLoc DL(N);
5209 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
5210 DAG.getConstant(N1C->getAPIntValue() ^
5211 N00C->getAPIntValue(), DL, VT));
5212 }
5213 if (const ConstantSDNode *N01C = getAsNonOpaqueConstant(N0.getOperand(1))) {
5214 SDLoc DL(N);
5215 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
5216 DAG.getConstant(N1C->getAPIntValue() ^
5217 N01C->getAPIntValue(), DL, VT));
5218 }
5219 }
5220
5221 // fold Y = sra (X, size(X)-1); xor (add (X, Y), Y) -> (abs X)
5222 unsigned OpSizeInBits = VT.getScalarSizeInBits();
5223 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
5224 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0) &&
5225 TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
5226 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
5227 if (C->getAPIntValue() == (OpSizeInBits - 1))
5228 return DAG.getNode(ISD::ABS, SDLoc(N), VT, N0.getOperand(0));
5229 }
5230
5231 // fold (xor x, x) -> 0
5232 if (N0 == N1)
5233 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
5234
5235 // fold (xor (shl 1, x), -1) -> (rotl ~1, x)
5236 // Here is a concrete example of this equivalence:
5237 // i16 x == 14
5238 // i16 shl == 1 << 14 == 16384 == 0b0100000000000000
5239 // i16 xor == ~(1 << 14) == 49151 == 0b1011111111111111
5240 //
5241 // =>
5242 //
5243 // i16 ~1 == 0b1111111111111110
5244 // i16 rol(~1, 14) == 0b1011111111111111
5245 //
5246 // Some additional tips to help conceptualize this transform:
5247 // - Try to see the operation as placing a single zero in a value of all ones.
5248 // - There exists no value for x which would allow the result to contain zero.
5249 // - Values of x larger than the bitwidth are undefined and do not require a
5250 // consistent result.
5251 // - Pushing the zero left requires shifting one bits in from the right.
5252 // A rotate left of ~1 is a nice way of achieving the desired result.
5253 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL
5254 && isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) {
5255 SDLoc DL(N);
5256 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT),
5257 N0.getOperand(1));
5258 }
5259
5260 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
5261 if (N0.getOpcode() == N1.getOpcode())
5262 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
5263 return Tmp;
5264
5265 // Simplify the expression using non-local knowledge.
5266 if (SimplifyDemandedBits(SDValue(N, 0)))
5267 return SDValue(N, 0);
5268
5269 return SDValue();
5270}
5271
5272/// Handle transforms common to the three shifts, when the shift amount is a
5273/// constant.
5274SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
5275 SDNode *LHS = N->getOperand(0).getNode();
5276 if (!LHS->hasOneUse()) return SDValue();
5277
5278 // We want to pull some binops through shifts, so that we have (and (shift))
5279 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
5280 // thing happens with address calculations, so it's important to canonicalize
5281 // it.
5282 bool HighBitSet = false; // Can we transform this if the high bit is set?
5283
5284 switch (LHS->getOpcode()) {
5285 default: return SDValue();
5286 case ISD::OR:
5287 case ISD::XOR:
5288 HighBitSet = false; // We can only transform sra if the high bit is clear.
5289 break;
5290 case ISD::AND:
5291 HighBitSet = true; // We can only transform sra if the high bit is set.
5292 break;
5293 case ISD::ADD:
5294 if (N->getOpcode() != ISD::SHL)
5295 return SDValue(); // only shl(add) not sr[al](add).
5296 HighBitSet = false; // We can only transform sra if the high bit is clear.
5297 break;
5298 }
5299
5300 // We require the RHS of the binop to be a constant and not opaque as well.
5301 ConstantSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
5302 if (!BinOpCst) return SDValue();
5303
5304 // FIXME: disable this unless the input to the binop is a shift by a constant
5305 // or is copy/select.Enable this in other cases when figure out it's exactly profitable.
5306 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
5307 bool isShift = BinOpLHSVal->getOpcode() == ISD::SHL ||
5308 BinOpLHSVal->getOpcode() == ISD::SRA ||
5309 BinOpLHSVal->getOpcode() == ISD::SRL;
5310 bool isCopyOrSelect = BinOpLHSVal->getOpcode() == ISD::CopyFromReg ||
5311 BinOpLHSVal->getOpcode() == ISD::SELECT;
5312
5313 if ((!isShift || !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) &&
5314 !isCopyOrSelect)
5315 return SDValue();
5316
5317 if (isCopyOrSelect && N->hasOneUse())
5318 return SDValue();
5319
5320 EVT VT = N->getValueType(0);
5321
5322 // If this is a signed shift right, and the high bit is modified by the
5323 // logical operation, do not perform the transformation. The highBitSet
5324 // boolean indicates the value of the high bit of the constant which would
5325 // cause it to be modified for this operation.
5326 if (N->getOpcode() == ISD::SRA) {
5327 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
5328 if (BinOpRHSSignSet != HighBitSet)
5329 return SDValue();
5330 }
5331
5332 if (!TLI.isDesirableToCommuteWithShift(LHS))
5333 return SDValue();
5334
5335 // Fold the constants, shifting the binop RHS by the shift amount.
5336 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
5337 N->getValueType(0),
5338 LHS->getOperand(1), N->getOperand(1));
5339 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!")(static_cast <bool> (isa<ConstantSDNode>(NewRHS) &&
"Folding was not successful!") ? void (0) : __assert_fail ("isa<ConstantSDNode>(NewRHS) && \"Folding was not successful!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5339, __extension__ __PRETTY_FUNCTION__))
;
5340
5341 // Create the new shift.
5342 SDValue NewShift = DAG.getNode(N->getOpcode(),
5343 SDLoc(LHS->getOperand(0)),
5344 VT, LHS->getOperand(0), N->getOperand(1));
5345
5346 // Create the new binop.
5347 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
5348}
5349
5350SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
5351 assert(N->getOpcode() == ISD::TRUNCATE)(static_cast <bool> (N->getOpcode() == ISD::TRUNCATE
) ? void (0) : __assert_fail ("N->getOpcode() == ISD::TRUNCATE"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5351, __extension__ __PRETTY_FUNCTION__))
;
5352 assert(N->getOperand(0).getOpcode() == ISD::AND)(static_cast <bool> (N->getOperand(0).getOpcode() ==
ISD::AND) ? void (0) : __assert_fail ("N->getOperand(0).getOpcode() == ISD::AND"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5352, __extension__ __PRETTY_FUNCTION__))
;
5353
5354 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
5355 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
5356 SDValue N01 = N->getOperand(0).getOperand(1);
5357 if (isConstantOrConstantVector(N01, /* NoOpaques */ true)) {
5358 SDLoc DL(N);
5359 EVT TruncVT = N->getValueType(0);
5360 SDValue N00 = N->getOperand(0).getOperand(0);
5361 SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00);
5362 SDValue Trunc01 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N01);
5363 AddToWorklist(Trunc00.getNode());
5364 AddToWorklist(Trunc01.getNode());
5365 return DAG.getNode(ISD::AND, DL, TruncVT, Trunc00, Trunc01);
5366 }
5367 }
5368
5369 return SDValue();
5370}
5371
5372SDValue DAGCombiner::visitRotate(SDNode *N) {
5373 SDLoc dl(N);
5374 SDValue N0 = N->getOperand(0);
5375 SDValue N1 = N->getOperand(1);
5376 EVT VT = N->getValueType(0);
5377 unsigned Bitsize = VT.getScalarSizeInBits();
5378
5379 // fold (rot x, 0) -> x
5380 if (isNullConstantOrNullSplatConstant(N1))
5381 return N0;
5382
5383 // fold (rot x, c) -> (rot x, c % BitSize)
5384 if (ConstantSDNode *Cst = isConstOrConstSplat(N1)) {
5385 if (Cst->getAPIntValue().uge(Bitsize)) {
5386 uint64_t RotAmt = Cst->getAPIntValue().urem(Bitsize);
5387 return DAG.getNode(N->getOpcode(), dl, VT, N0,
5388 DAG.getConstant(RotAmt, dl, N1.getValueType()));
5389 }
5390 }
5391
5392 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
5393 if (N1.getOpcode() == ISD::TRUNCATE &&
5394 N1.getOperand(0).getOpcode() == ISD::AND) {
5395 if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
5396 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1);
5397 }
5398
5399 unsigned NextOp = N0.getOpcode();
5400 // fold (rot* (rot* x, c2), c1) -> (rot* x, c1 +- c2 % bitsize)
5401 if (NextOp == ISD::ROTL || NextOp == ISD::ROTR) {
5402 SDNode *C1 = DAG.isConstantIntBuildVectorOrConstantInt(N1);
5403 SDNode *C2 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1));
5404 if (C1 && C2 && C1->getValueType(0) == C2->getValueType(0)) {
5405 EVT ShiftVT = C1->getValueType(0);
5406 bool SameSide = (N->getOpcode() == NextOp);
5407 unsigned CombineOp = SameSide ? ISD::ADD : ISD::SUB;
5408 if (SDValue CombinedShift =
5409 DAG.FoldConstantArithmetic(CombineOp, dl, ShiftVT, C1, C2)) {
5410 SDValue BitsizeC = DAG.getConstant(Bitsize, dl, ShiftVT);
5411 SDValue CombinedShiftNorm = DAG.FoldConstantArithmetic(
5412 ISD::SREM, dl, ShiftVT, CombinedShift.getNode(),
5413 BitsizeC.getNode());
5414 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
5415 CombinedShiftNorm);
5416 }
5417 }
5418 }
5419 return SDValue();
5420}
5421
5422SDValue DAGCombiner::visitSHL(SDNode *N) {
5423 SDValue N0 = N->getOperand(0);
5424 SDValue N1 = N->getOperand(1);
5425 EVT VT = N0.getValueType();
5426 unsigned OpSizeInBits = VT.getScalarSizeInBits();
5427
5428 // fold vector ops
5429 if (VT.isVector()) {
5430 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5431 return FoldedVOp;
5432
5433 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
5434 // If setcc produces all-one true value then:
5435 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
5436 if (N1CV && N1CV->isConstant()) {
5437 if (N0.getOpcode() == ISD::AND) {
5438 SDValue N00 = N0->getOperand(0);
5439 SDValue N01 = N0->getOperand(1);
5440 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
5441
5442 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
5443 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
5444 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5445 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT,
5446 N01CV, N1CV))
5447 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
5448 }
5449 }
5450 }
5451 }
5452
5453 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5454
5455 // fold (shl c1, c2) -> c1<<c2
5456 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
5457 if (N0C && N1C && !N1C->isOpaque())
5458 return DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, N0C, N1C);
5459 // fold (shl 0, x) -> 0
5460 if (isNullConstantOrNullSplatConstant(N0))
5461 return N0;
5462 // fold (shl x, c >= size(x)) -> undef
5463 // NOTE: ALL vector elements must be too big to avoid partial UNDEFs.
5464 auto MatchShiftTooBig = [OpSizeInBits](ConstantSDNode *Val) {
5465 return Val->getAPIntValue().uge(OpSizeInBits);
5466 };
5467 if (matchUnaryPredicate(N1, MatchShiftTooBig))
5468 return DAG.getUNDEF(VT);
5469 // fold (shl x, 0) -> x
5470 if (N1C && N1C->isNullValue())
5471 return N0;
5472 // fold (shl undef, x) -> 0
5473 if (N0.isUndef())
5474 return DAG.getConstant(0, SDLoc(N), VT);
5475
5476 if (SDValue NewSel = foldBinOpIntoSelect(N))
5477 return NewSel;
5478
5479 // if (shl x, c) is known to be zero, return 0
5480 if (DAG.MaskedValueIsZero(SDValue(N, 0),
5481 APInt::getAllOnesValue(OpSizeInBits)))
5482 return DAG.getConstant(0, SDLoc(N), VT);
5483 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
5484 if (N1.getOpcode() == ISD::TRUNCATE &&
5485 N1.getOperand(0).getOpcode() == ISD::AND) {
5486 if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
5487 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
5488 }
5489
5490 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
5491 return SDValue(N, 0);
5492
5493 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
5494 if (N0.getOpcode() == ISD::SHL) {
5495 auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS,
5496 ConstantSDNode *RHS) {
5497 APInt c1 = LHS->getAPIntValue();
5498 APInt c2 = RHS->getAPIntValue();
5499 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5500 return (c1 + c2).uge(OpSizeInBits);
5501 };
5502 if (matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
5503 return DAG.getConstant(0, SDLoc(N), VT);
5504
5505 auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS,
5506 ConstantSDNode *RHS) {
5507 APInt c1 = LHS->getAPIntValue();
5508 APInt c2 = RHS->getAPIntValue();
5509 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5510 return (c1 + c2).ult(OpSizeInBits);
5511 };
5512 if (matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
5513 SDLoc DL(N);
5514 EVT ShiftVT = N1.getValueType();
5515 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
5516 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum);
5517 }
5518 }
5519
5520 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
5521 // For this to be valid, the second form must not preserve any of the bits
5522 // that are shifted out by the inner shift in the first form. This means
5523 // the outer shift size must be >= the number of bits added by the ext.
5524 // As a corollary, we don't care what kind of ext it is.
5525 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
5526 N0.getOpcode() == ISD::ANY_EXTEND ||
5527 N0.getOpcode() == ISD::SIGN_EXTEND) &&
5528 N0.getOperand(0).getOpcode() == ISD::SHL) {
5529 SDValue N0Op0 = N0.getOperand(0);
5530 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
5531 APInt c1 = N0Op0C1->getAPIntValue();
5532 APInt c2 = N1C->getAPIntValue();
5533 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5534
5535 EVT InnerShiftVT = N0Op0.getValueType();
5536 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
5537 if (c2.uge(OpSizeInBits - InnerShiftSize)) {
5538 SDLoc DL(N0);
5539 APInt Sum = c1 + c2;
5540 if (Sum.uge(OpSizeInBits))
5541 return DAG.getConstant(0, DL, VT);
5542
5543 return DAG.getNode(
5544 ISD::SHL, DL, VT,
5545 DAG.getNode(N0.getOpcode(), DL, VT, N0Op0->getOperand(0)),
5546 DAG.getConstant(Sum.getZExtValue(), DL, N1.getValueType()));
5547 }
5548 }
5549 }
5550
5551 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
5552 // Only fold this if the inner zext has no other uses to avoid increasing
5553 // the total number of instructions.
5554 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
5555 N0.getOperand(0).getOpcode() == ISD::SRL) {
5556 SDValue N0Op0 = N0.getOperand(0);
5557 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
5558 if (N0Op0C1->getAPIntValue().ult(VT.getScalarSizeInBits())) {
5559 uint64_t c1 = N0Op0C1->getZExtValue();
5560 uint64_t c2 = N1C->getZExtValue();
5561 if (c1 == c2) {
5562 SDValue NewOp0 = N0.getOperand(0);
5563 EVT CountVT = NewOp0.getOperand(1).getValueType();
5564 SDLoc DL(N);
5565 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, NewOp0.getValueType(),
5566 NewOp0,
5567 DAG.getConstant(c2, DL, CountVT));
5568 AddToWorklist(NewSHL.getNode());
5569 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
5570 }
5571 }
5572 }
5573 }
5574
5575 // fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
5576 // fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2
5577 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
5578 N0->getFlags().hasExact()) {
5579 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
5580 uint64_t C1 = N0C1->getZExtValue();
5581 uint64_t C2 = N1C->getZExtValue();
5582 SDLoc DL(N);
5583 if (C1 <= C2)
5584 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
5585 DAG.getConstant(C2 - C1, DL, N1.getValueType()));
5586 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0),
5587 DAG.getConstant(C1 - C2, DL, N1.getValueType()));
5588 }
5589 }
5590
5591 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
5592 // (and (srl x, (sub c1, c2), MASK)
5593 // Only fold this if the inner shift has no other uses -- if it does, folding
5594 // this will increase the total number of instructions.
5595 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5596 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
5597 uint64_t c1 = N0C1->getZExtValue();
5598 if (c1 < OpSizeInBits) {
5599 uint64_t c2 = N1C->getZExtValue();
5600 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
5601 SDValue Shift;
5602 if (c2 > c1) {
5603 Mask <<= c2 - c1;
5604 SDLoc DL(N);
5605 Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
5606 DAG.getConstant(c2 - c1, DL, N1.getValueType()));
5607 } else {
5608 Mask.lshrInPlace(c1 - c2);
5609 SDLoc DL(N);
5610 Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
5611 DAG.getConstant(c1 - c2, DL, N1.getValueType()));
5612 }
5613 SDLoc DL(N0);
5614 return DAG.getNode(ISD::AND, DL, VT, Shift,
5615 DAG.getConstant(Mask, DL, VT));
5616 }
5617 }
5618 }
5619
5620 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
5621 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
5622 isConstantOrConstantVector(N1, /* No Opaques */ true)) {
5623 SDLoc DL(N);
5624 SDValue AllBits = DAG.getAllOnesConstant(DL, VT);
5625 SDValue HiBitsMask = DAG.getNode(ISD::SHL, DL, VT, AllBits, N1);
5626 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask);
5627 }
5628
5629 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
5630 // fold (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)
5631 // Variant of version done on multiply, except mul by a power of 2 is turned
5632 // into a shift.
5633 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
5634 N0.getNode()->hasOneUse() &&
5635 isConstantOrConstantVector(N1, /* No Opaques */ true) &&
5636 isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true)) {
5637 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
5638 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
5639 AddToWorklist(Shl0.getNode());
5640 AddToWorklist(Shl1.getNode());
5641 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, Shl0, Shl1);
5642 }
5643
5644 // fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
5645 if (N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse() &&
5646 isConstantOrConstantVector(N1, /* No Opaques */ true) &&
5647 isConstantOrConstantVector(N0.getOperand(1), /* No Opaques */ true)) {
5648 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
5649 if (isConstantOrConstantVector(Shl))
5650 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Shl);
5651 }
5652
5653 if (N1C && !N1C->isOpaque())
5654 if (SDValue NewSHL = visitShiftByConstant(N, N1C))
5655 return NewSHL;
5656
5657 return SDValue();
5658}
5659
5660SDValue DAGCombiner::visitSRA(SDNode *N) {
5661 SDValue N0 = N->getOperand(0);
5662 SDValue N1 = N->getOperand(1);
5663 EVT VT = N0.getValueType();
5664 unsigned OpSizeInBits = VT.getScalarSizeInBits();
5665
5666 // Arithmetic shifting an all-sign-bit value is a no-op.
5667 // fold (sra 0, x) -> 0
5668 // fold (sra -1, x) -> -1
5669 if (DAG.ComputeNumSignBits(N0) == OpSizeInBits)
5670 return N0;
5671
5672 // fold vector ops
5673 if (VT.isVector())
5674 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5675 return FoldedVOp;
5676
5677 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5678
5679 // fold (sra c1, c2) -> (sra c1, c2)
5680 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
5681 if (N0C && N1C && !N1C->isOpaque())
5682 return DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, N0C, N1C);
5683 // fold (sra x, c >= size(x)) -> undef
5684 // NOTE: ALL vector elements must be too big to avoid partial UNDEFs.
5685 auto MatchShiftTooBig = [OpSizeInBits](ConstantSDNode *Val) {
5686 return Val->getAPIntValue().uge(OpSizeInBits);
5687 };
5688 if (matchUnaryPredicate(N1, MatchShiftTooBig))
5689 return DAG.getUNDEF(VT);
5690 // fold (sra x, 0) -> x
5691 if (N1C && N1C->isNullValue())
5692 return N0;
5693
5694 if (SDValue NewSel = foldBinOpIntoSelect(N))
5695 return NewSel;
5696
5697 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
5698 // sext_inreg.
5699 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
5700 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
5701 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
5702 if (VT.isVector())
5703 ExtVT = EVT::getVectorVT(*DAG.getContext(),
5704 ExtVT, VT.getVectorNumElements());
5705 if ((!LegalOperations ||
5706 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
5707 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5708 N0.getOperand(0), DAG.getValueType(ExtVT));
5709 }
5710
5711 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
5712 if (N0.getOpcode() == ISD::SRA) {
5713 SDLoc DL(N);
5714 EVT ShiftVT = N1.getValueType();
5715
5716 auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS,
5717 ConstantSDNode *RHS) {
5718 APInt c1 = LHS->getAPIntValue();
5719 APInt c2 = RHS->getAPIntValue();
5720 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5721 return (c1 + c2).uge(OpSizeInBits);
5722 };
5723 if (matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
5724 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
5725 DAG.getConstant(OpSizeInBits - 1, DL, ShiftVT));
5726
5727 auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS,
5728 ConstantSDNode *RHS) {
5729 APInt c1 = LHS->getAPIntValue();
5730 APInt c2 = RHS->getAPIntValue();
5731 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5732 return (c1 + c2).ult(OpSizeInBits);
5733 };
5734 if (matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
5735 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
5736 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), Sum);
5737 }
5738 }
5739
5740 // fold (sra (shl X, m), (sub result_size, n))
5741 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
5742 // result_size - n != m.
5743 // If truncate is free for the target sext(shl) is likely to result in better
5744 // code.
5745 if (N0.getOpcode() == ISD::SHL && N1C) {
5746 // Get the two constanst of the shifts, CN0 = m, CN = n.
5747 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
5748 if (N01C) {
5749 LLVMContext &Ctx = *DAG.getContext();
5750 // Determine what the truncate's result bitsize and type would be.
5751 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
5752
5753 if (VT.isVector())
5754 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
5755
5756 // Determine the residual right-shift amount.
5757 int ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
5758
5759 // If the shift is not a no-op (in which case this should be just a sign
5760 // extend already), the truncated to type is legal, sign_extend is legal
5761 // on that type, and the truncate to that type is both legal and free,
5762 // perform the transform.
5763 if ((ShiftAmt > 0) &&
5764 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
5765 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
5766 TLI.isTruncateFree(VT, TruncVT)) {
5767 SDLoc DL(N);
5768 SDValue Amt = DAG.getConstant(ShiftAmt, DL,
5769 getShiftAmountTy(N0.getOperand(0).getValueType()));
5770 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
5771 N0.getOperand(0), Amt);
5772 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT,
5773 Shift);
5774 return DAG.getNode(ISD::SIGN_EXTEND, DL,
5775 N->getValueType(0), Trunc);
5776 }
5777 }
5778 }
5779
5780 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
5781 if (N1.getOpcode() == ISD::TRUNCATE &&
5782 N1.getOperand(0).getOpcode() == ISD::AND) {
5783 if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
5784 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
5785 }
5786
5787 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
5788 // if c1 is equal to the number of bits the trunc removes
5789 if (N0.getOpcode() == ISD::TRUNCATE &&
5790 (N0.getOperand(0).getOpcode() == ISD::SRL ||
5791 N0.getOperand(0).getOpcode() == ISD::SRA) &&
5792 N0.getOperand(0).hasOneUse() &&
5793 N0.getOperand(0).getOperand(1).hasOneUse() &&
5794 N1C) {
5795 SDValue N0Op0 = N0.getOperand(0);
5796 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
5797 unsigned LargeShiftVal = LargeShift->getZExtValue();
5798 EVT LargeVT = N0Op0.getValueType();
5799
5800 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
5801 SDLoc DL(N);
5802 SDValue Amt =
5803 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(), DL,
5804 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
5805 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT,
5806 N0Op0.getOperand(0), Amt);
5807 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
5808 }
5809 }
5810 }
5811
5812 // Simplify, based on bits shifted out of the LHS.
5813 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
5814 return SDValue(N, 0);
5815
5816 // If the sign bit is known to be zero, switch this to a SRL.
5817 if (DAG.SignBitIsZero(N0))
5818 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
5819
5820 if (N1C && !N1C->isOpaque())
5821 if (SDValue NewSRA = visitShiftByConstant(N, N1C))
5822 return NewSRA;
5823
5824 return SDValue();
5825}
5826
5827SDValue DAGCombiner::visitSRL(SDNode *N) {
5828 SDValue N0 = N->getOperand(0);
5829 SDValue N1 = N->getOperand(1);
5830 EVT VT = N0.getValueType();
5831 unsigned OpSizeInBits = VT.getScalarSizeInBits();
5832
5833 // fold vector ops
5834 if (VT.isVector())
5835 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5836 return FoldedVOp;
5837
5838 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5839
5840 // fold (srl c1, c2) -> c1 >>u c2
5841 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
5842 if (N0C && N1C && !N1C->isOpaque())
5843 return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C);
5844 // fold (srl 0, x) -> 0
5845 if (isNullConstantOrNullSplatConstant(N0))
5846 return N0;
5847 // fold (srl x, c >= size(x)) -> undef
5848 // NOTE: ALL vector elements must be too big to avoid partial UNDEFs.
5849 auto MatchShiftTooBig = [OpSizeInBits](ConstantSDNode *Val) {
5850 return Val->getAPIntValue().uge(OpSizeInBits);
5851 };
5852 if (matchUnaryPredicate(N1, MatchShiftTooBig))
5853 return DAG.getUNDEF(VT);
5854 // fold (srl x, 0) -> x
5855 if (N1C && N1C->isNullValue())
5856 return N0;
5857
5858 if (SDValue NewSel = foldBinOpIntoSelect(N))
5859 return NewSel;
5860
5861 // if (srl x, c) is known to be zero, return 0
5862 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
5863 APInt::getAllOnesValue(OpSizeInBits)))
5864 return DAG.getConstant(0, SDLoc(N), VT);
5865
5866 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
5867 if (N0.getOpcode() == ISD::SRL) {
5868 auto MatchOutOfRange = [OpSizeInBits](ConstantSDNode *LHS,
5869 ConstantSDNode *RHS) {
5870 APInt c1 = LHS->getAPIntValue();
5871 APInt c2 = RHS->getAPIntValue();
5872 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5873 return (c1 + c2).uge(OpSizeInBits);
5874 };
5875 if (matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
5876 return DAG.getConstant(0, SDLoc(N), VT);
5877
5878 auto MatchInRange = [OpSizeInBits](ConstantSDNode *LHS,
5879 ConstantSDNode *RHS) {
5880 APInt c1 = LHS->getAPIntValue();
5881 APInt c2 = RHS->getAPIntValue();
5882 zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
5883 return (c1 + c2).ult(OpSizeInBits);
5884 };
5885 if (matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
5886 SDLoc DL(N);
5887 EVT ShiftVT = N1.getValueType();
5888 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
5889 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum);
5890 }
5891 }
5892
5893 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
5894 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
5895 N0.getOperand(0).getOpcode() == ISD::SRL) {
5896 if (auto N001C = isConstOrConstSplat(N0.getOperand(0).getOperand(1))) {
5897 uint64_t c1 = N001C->getZExtValue();
5898 uint64_t c2 = N1C->getZExtValue();
5899 EVT InnerShiftVT = N0.getOperand(0).getValueType();
5900 EVT ShiftCountVT = N0.getOperand(0).getOperand(1).getValueType();
5901 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
5902 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
5903 if (c1 + OpSizeInBits == InnerShiftSize) {
5904 SDLoc DL(N0);
5905 if (c1 + c2 >= InnerShiftSize)
5906 return DAG.getConstant(0, DL, VT);
5907 return DAG.getNode(ISD::TRUNCATE, DL, VT,
5908 DAG.getNode(ISD::SRL, DL, InnerShiftVT,
5909 N0.getOperand(0).getOperand(0),
5910 DAG.getConstant(c1 + c2, DL,
5911 ShiftCountVT)));
5912 }
5913 }
5914 }
5915
5916 // fold (srl (shl x, c), c) -> (and x, cst2)
5917 if (N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
5918 isConstantOrConstantVector(N1, /* NoOpaques */ true)) {
5919 SDLoc DL(N);
5920 SDValue Mask =
5921 DAG.getNode(ISD::SRL, DL, VT, DAG.getAllOnesConstant(DL, VT), N1);
5922 AddToWorklist(Mask.getNode());
5923 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), Mask);
5924 }
5925
5926 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
5927 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5928 // Shifting in all undef bits?
5929 EVT SmallVT = N0.getOperand(0).getValueType();
5930 unsigned BitSize = SmallVT.getScalarSizeInBits();
5931 if (N1C->getZExtValue() >= BitSize)
5932 return DAG.getUNDEF(VT);
5933
5934 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
5935 uint64_t ShiftAmt = N1C->getZExtValue();
5936 SDLoc DL0(N0);
5937 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT,
5938 N0.getOperand(0),
5939 DAG.getConstant(ShiftAmt, DL0,
5940 getShiftAmountTy(SmallVT)));
5941 AddToWorklist(SmallShift.getNode());
5942 APInt Mask = APInt::getLowBitsSet(OpSizeInBits, OpSizeInBits - ShiftAmt);
5943 SDLoc DL(N);
5944 return DAG.getNode(ISD::AND, DL, VT,
5945 DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift),
5946 DAG.getConstant(Mask, DL, VT));
5947 }
5948 }
5949
5950 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
5951 // bit, which is unmodified by sra.
5952 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
5953 if (N0.getOpcode() == ISD::SRA)
5954 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
5955 }
5956
5957 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
5958 if (N1C && N0.getOpcode() == ISD::CTLZ &&
5959 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
5960 KnownBits Known;
5961 DAG.computeKnownBits(N0.getOperand(0), Known);
5962
5963 // If any of the input bits are KnownOne, then the input couldn't be all
5964 // zeros, thus the result of the srl will always be zero.
5965 if (Known.One.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
5966
5967 // If all of the bits input the to ctlz node are known to be zero, then
5968 // the result of the ctlz is "32" and the result of the shift is one.
5969 APInt UnknownBits = ~Known.Zero;
5970 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
5971
5972 // Otherwise, check to see if there is exactly one bit input to the ctlz.
5973 if (UnknownBits.isPowerOf2()) {
5974 // Okay, we know that only that the single bit specified by UnknownBits
5975 // could be set on input to the CTLZ node. If this bit is set, the SRL
5976 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
5977 // to an SRL/XOR pair, which is likely to simplify more.
5978 unsigned ShAmt = UnknownBits.countTrailingZeros();
5979 SDValue Op = N0.getOperand(0);
5980
5981 if (ShAmt) {
5982 SDLoc DL(N0);
5983 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
5984 DAG.getConstant(ShAmt, DL,
5985 getShiftAmountTy(Op.getValueType())));
5986 AddToWorklist(Op.getNode());
5987 }
5988
5989 SDLoc DL(N);
5990 return DAG.getNode(ISD::XOR, DL, VT,
5991 Op, DAG.getConstant(1, DL, VT));
5992 }
5993 }
5994
5995 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
5996 if (N1.getOpcode() == ISD::TRUNCATE &&
5997 N1.getOperand(0).getOpcode() == ISD::AND) {
5998 if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
5999 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
6000 }
6001
6002 // fold operands of srl based on knowledge that the low bits are not
6003 // demanded.
6004 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
6005 return SDValue(N, 0);
6006
6007 if (N1C && !N1C->isOpaque())
6008 if (SDValue NewSRL = visitShiftByConstant(N, N1C))
6009 return NewSRL;
6010
6011 // Attempt to convert a srl of a load into a narrower zero-extending load.
6012 if (SDValue NarrowLoad = ReduceLoadWidth(N))
6013 return NarrowLoad;
6014
6015 // Here is a common situation. We want to optimize:
6016 //
6017 // %a = ...
6018 // %b = and i32 %a, 2
6019 // %c = srl i32 %b, 1
6020 // brcond i32 %c ...
6021 //
6022 // into
6023 //
6024 // %a = ...
6025 // %b = and %a, 2
6026 // %c = setcc eq %b, 0
6027 // brcond %c ...
6028 //
6029 // However when after the source operand of SRL is optimized into AND, the SRL
6030 // itself may not be optimized further. Look for it and add the BRCOND into
6031 // the worklist.
6032 if (N->hasOneUse()) {
6033 SDNode *Use = *N->use_begin();
6034 if (Use->getOpcode() == ISD::BRCOND)
6035 AddToWorklist(Use);
6036 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
6037 // Also look pass the truncate.
6038 Use = *Use->use_begin();
6039 if (Use->getOpcode() == ISD::BRCOND)
6040 AddToWorklist(Use);
6041 }
6042 }
6043
6044 return SDValue();
6045}
6046
6047SDValue DAGCombiner::visitABS(SDNode *N) {
6048 SDValue N0 = N->getOperand(0);
6049 EVT VT = N->getValueType(0);
6050
6051 // fold (abs c1) -> c2
6052 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6053 return DAG.getNode(ISD::ABS, SDLoc(N), VT, N0);
6054 // fold (abs (abs x)) -> (abs x)
6055 if (N0.getOpcode() == ISD::ABS)
6056 return N0;
6057 // fold (abs x) -> x iff not-negative
6058 if (DAG.SignBitIsZero(N0))
6059 return N0;
6060 return SDValue();
6061}
6062
6063SDValue DAGCombiner::visitBSWAP(SDNode *N) {
6064 SDValue N0 = N->getOperand(0);
6065 EVT VT = N->getValueType(0);
6066
6067 // fold (bswap c1) -> c2
6068 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6069 return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
6070 // fold (bswap (bswap x)) -> x
6071 if (N0.getOpcode() == ISD::BSWAP)
6072 return N0->getOperand(0);
6073 return SDValue();
6074}
6075
6076SDValue DAGCombiner::visitBITREVERSE(SDNode *N) {
6077 SDValue N0 = N->getOperand(0);
6078 EVT VT = N->getValueType(0);
6079
6080 // fold (bitreverse c1) -> c2
6081 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6082 return DAG.getNode(ISD::BITREVERSE, SDLoc(N), VT, N0);
6083 // fold (bitreverse (bitreverse x)) -> x
6084 if (N0.getOpcode() == ISD::BITREVERSE)
6085 return N0.getOperand(0);
6086 return SDValue();
6087}
6088
6089SDValue DAGCombiner::visitCTLZ(SDNode *N) {
6090 SDValue N0 = N->getOperand(0);
6091 EVT VT = N->getValueType(0);
6092
6093 // fold (ctlz c1) -> c2
6094 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6095 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
6096 return SDValue();
6097}
6098
6099SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
6100 SDValue N0 = N->getOperand(0);
6101 EVT VT = N->getValueType(0);
6102
6103 // fold (ctlz_zero_undef c1) -> c2
6104 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6105 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
6106 return SDValue();
6107}
6108
6109SDValue DAGCombiner::visitCTTZ(SDNode *N) {
6110 SDValue N0 = N->getOperand(0);
6111 EVT VT = N->getValueType(0);
6112
6113 // fold (cttz c1) -> c2
6114 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6115 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
6116 return SDValue();
6117}
6118
6119SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
6120 SDValue N0 = N->getOperand(0);
6121 EVT VT = N->getValueType(0);
6122
6123 // fold (cttz_zero_undef c1) -> c2
6124 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6125 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
6126 return SDValue();
6127}
6128
6129SDValue DAGCombiner::visitCTPOP(SDNode *N) {
6130 SDValue N0 = N->getOperand(0);
6131 EVT VT = N->getValueType(0);
6132
6133 // fold (ctpop c1) -> c2
6134 if (DAG.isConstantIntBuildVectorOrConstantInt(N0))
6135 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
6136 return SDValue();
6137}
6138
6139/// \brief Generate Min/Max node
6140static SDValue combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS,
6141 SDValue RHS, SDValue True, SDValue False,
6142 ISD::CondCode CC, const TargetLowering &TLI,
6143 SelectionDAG &DAG) {
6144 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
6145 return SDValue();
6146
6147 switch (CC) {
6148 case ISD::SETOLT:
6149 case ISD::SETOLE:
6150 case ISD::SETLT:
6151 case ISD::SETLE:
6152 case ISD::SETULT:
6153 case ISD::SETULE: {
6154 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
6155 if (TLI.isOperationLegal(Opcode, VT))
6156 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
6157 return SDValue();
6158 }
6159 case ISD::SETOGT:
6160 case ISD::SETOGE:
6161 case ISD::SETGT:
6162 case ISD::SETGE:
6163 case ISD::SETUGT:
6164 case ISD::SETUGE: {
6165 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
6166 if (TLI.isOperationLegal(Opcode, VT))
6167 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
6168 return SDValue();
6169 }
6170 default:
6171 return SDValue();
6172 }
6173}
6174
6175SDValue DAGCombiner::foldSelectOfConstants(SDNode *N) {
6176 SDValue Cond = N->getOperand(0);
6177 SDValue N1 = N->getOperand(1);
6178 SDValue N2 = N->getOperand(2);
6179 EVT VT = N->getValueType(0);
6180 EVT CondVT = Cond.getValueType();
6181 SDLoc DL(N);
6182
6183 if (!VT.isInteger())
6184 return SDValue();
6185
6186 auto *C1 = dyn_cast<ConstantSDNode>(N1);
6187 auto *C2 = dyn_cast<ConstantSDNode>(N2);
6188 if (!C1 || !C2)
6189 return SDValue();
6190
6191 // Only do this before legalization to avoid conflicting with target-specific
6192 // transforms in the other direction (create a select from a zext/sext). There
6193 // is also a target-independent combine here in DAGCombiner in the other
6194 // direction for (select Cond, -1, 0) when the condition is not i1.
6195 if (CondVT == MVT::i1 && !LegalOperations) {
6196 if (C1->isNullValue() && C2->isOne()) {
6197 // select Cond, 0, 1 --> zext (!Cond)
6198 SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1);
6199 if (VT != MVT::i1)
6200 NotCond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, NotCond);
6201 return NotCond;
6202 }
6203 if (C1->isNullValue() && C2->isAllOnesValue()) {
6204 // select Cond, 0, -1 --> sext (!Cond)
6205 SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1);
6206 if (VT != MVT::i1)
6207 NotCond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NotCond);
6208 return NotCond;
6209 }
6210 if (C1->isOne() && C2->isNullValue()) {
6211 // select Cond, 1, 0 --> zext (Cond)
6212 if (VT != MVT::i1)
6213 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
6214 return Cond;
6215 }
6216 if (C1->isAllOnesValue() && C2->isNullValue()) {
6217 // select Cond, -1, 0 --> sext (Cond)
6218 if (VT != MVT::i1)
6219 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
6220 return Cond;
6221 }
6222
6223 // For any constants that differ by 1, we can transform the select into an
6224 // extend and add. Use a target hook because some targets may prefer to
6225 // transform in the other direction.
6226 if (TLI.convertSelectOfConstantsToMath(VT)) {
6227 if (C1->getAPIntValue() - 1 == C2->getAPIntValue()) {
6228 // select Cond, C1, C1-1 --> add (zext Cond), C1-1
6229 if (VT != MVT::i1)
6230 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Cond);
6231 return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
6232 }
6233 if (C1->getAPIntValue() + 1 == C2->getAPIntValue()) {
6234 // select Cond, C1, C1+1 --> add (sext Cond), C1+1
6235 if (VT != MVT::i1)
6236 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Cond);
6237 return DAG.getNode(ISD::ADD, DL, VT, Cond, N2);
6238 }
6239 }
6240
6241 return SDValue();
6242 }
6243
6244 // fold (select Cond, 0, 1) -> (xor Cond, 1)
6245 // We can't do this reliably if integer based booleans have different contents
6246 // to floating point based booleans. This is because we can't tell whether we
6247 // have an integer-based boolean or a floating-point-based boolean unless we
6248 // can find the SETCC that produced it and inspect its operands. This is
6249 // fairly easy if C is the SETCC node, but it can potentially be
6250 // undiscoverable (or not reasonably discoverable). For example, it could be
6251 // in another basic block or it could require searching a complicated
6252 // expression.
6253 if (CondVT.isInteger() &&
6254 TLI.getBooleanContents(false, true) ==
6255 TargetLowering::ZeroOrOneBooleanContent &&
6256 TLI.getBooleanContents(false, false) ==
6257 TargetLowering::ZeroOrOneBooleanContent &&
6258 C1->isNullValue() && C2->isOne()) {
6259 SDValue NotCond =
6260 DAG.getNode(ISD::XOR, DL, CondVT, Cond, DAG.getConstant(1, DL, CondVT));
6261 if (VT.bitsEq(CondVT))
6262 return NotCond;
6263 return DAG.getZExtOrTrunc(NotCond, DL, VT);
6264 }
6265
6266 return SDValue();
6267}
6268
6269SDValue DAGCombiner::visitSELECT(SDNode *N) {
6270 SDValue N0 = N->getOperand(0);
6271 SDValue N1 = N->getOperand(1);
6272 SDValue N2 = N->getOperand(2);
6273 EVT VT = N->getValueType(0);
6274 EVT VT0 = N0.getValueType();
6275 SDLoc DL(N);
6276
6277 // fold (select C, X, X) -> X
6278 if (N1 == N2)
6279 return N1;
6280
6281 if (const ConstantSDNode *N0C = dyn_cast<const ConstantSDNode>(N0)) {
6282 // fold (select true, X, Y) -> X
6283 // fold (select false, X, Y) -> Y
6284 return !N0C->isNullValue() ? N1 : N2;
6285 }
6286
6287 // fold (select X, X, Y) -> (or X, Y)
6288 // fold (select X, 1, Y) -> (or C, Y)
6289 if (VT == VT0 && VT == MVT::i1 && (N0 == N1 || isOneConstant(N1)))
6290 return DAG.getNode(ISD::OR, DL, VT, N0, N2);
6291
6292 if (SDValue V = foldSelectOfConstants(N))
6293 return V;
6294
6295 // fold (select C, 0, X) -> (and (not C), X)
6296 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) {
6297 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
6298 AddToWorklist(NOTNode.getNode());
6299 return DAG.getNode(ISD::AND, DL, VT, NOTNode, N2);
6300 }
6301 // fold (select C, X, 1) -> (or (not C), X)
6302 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) {
6303 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
6304 AddToWorklist(NOTNode.getNode());
6305 return DAG.getNode(ISD::OR, DL, VT, NOTNode, N1);
6306 }
6307 // fold (select X, Y, X) -> (and X, Y)
6308 // fold (select X, Y, 0) -> (and X, Y)
6309 if (VT == VT0 && VT == MVT::i1 && (N0 == N2 || isNullConstant(N2)))
6310 return DAG.getNode(ISD::AND, DL, VT, N0, N1);
6311
6312 // If we can fold this based on the true/false value, do so.
6313 if (SimplifySelectOps(N, N1, N2))
6314 return SDValue(N, 0); // Don't revisit N.
6315
6316 if (VT0 == MVT::i1) {
6317 // The code in this block deals with the following 2 equivalences:
6318 // select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y))
6319 // select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y)
6320 // The target can specify its preferred form with the
6321 // shouldNormalizeToSelectSequence() callback. However we always transform
6322 // to the right anyway if we find the inner select exists in the DAG anyway
6323 // and we always transform to the left side if we know that we can further
6324 // optimize the combination of the conditions.
6325 bool normalizeToSequence =
6326 TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT);
6327 // select (and Cond0, Cond1), X, Y
6328 // -> select Cond0, (select Cond1, X, Y), Y
6329 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
6330 SDValue Cond0 = N0->getOperand(0);
6331 SDValue Cond1 = N0->getOperand(1);
6332 SDValue InnerSelect =
6333 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2);
6334 if (normalizeToSequence || !InnerSelect.use_empty())
6335 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0,
6336 InnerSelect, N2);
6337 }
6338 // select (or Cond0, Cond1), X, Y -> select Cond0, X, (select Cond1, X, Y)
6339 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
6340 SDValue Cond0 = N0->getOperand(0);
6341 SDValue Cond1 = N0->getOperand(1);
6342 SDValue InnerSelect =
6343 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2);
6344 if (normalizeToSequence || !InnerSelect.use_empty())
6345 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1,
6346 InnerSelect);
6347 }
6348
6349 // select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
6350 if (N1->getOpcode() == ISD::SELECT && N1->hasOneUse()) {
6351 SDValue N1_0 = N1->getOperand(0);
6352 SDValue N1_1 = N1->getOperand(1);
6353 SDValue N1_2 = N1->getOperand(2);
6354 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
6355 // Create the actual and node if we can generate good code for it.
6356 if (!normalizeToSequence) {
6357 SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0);
6358 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), And, N1_1, N2);
6359 }
6360 // Otherwise see if we can optimize the "and" to a better pattern.
6361 if (SDValue Combined = visitANDLike(N0, N1_0, N))
6362 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1_1,
6363 N2);
6364 }
6365 }
6366 // select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
6367 if (N2->getOpcode() == ISD::SELECT && N2->hasOneUse()) {
6368 SDValue N2_0 = N2->getOperand(0);
6369 SDValue N2_1 = N2->getOperand(1);
6370 SDValue N2_2 = N2->getOperand(2);
6371 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
6372 // Create the actual or node if we can generate good code for it.
6373 if (!normalizeToSequence) {
6374 SDValue Or = DAG.getNode(ISD::OR, DL, N0.getValueType(), N0, N2_0);
6375 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Or, N1, N2_2);
6376 }
6377 // Otherwise see if we can optimize to a better pattern.
6378 if (SDValue Combined = visitORLike(N0, N2_0, N))
6379 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Combined, N1,
6380 N2_2);
6381 }
6382 }
6383 }
6384
6385 // select (xor Cond, 1), X, Y -> select Cond, Y, X
6386 if (VT0 == MVT::i1) {
6387 if (N0->getOpcode() == ISD::XOR) {
6388 if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) {
6389 SDValue Cond0 = N0->getOperand(0);
6390 if (C->isOne())
6391 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N2, N1);
6392 }
6393 }
6394 }
6395
6396 // fold selects based on a setcc into other things, such as min/max/abs
6397 if (N0.getOpcode() == ISD::SETCC) {
6398 // select x, y (fcmp lt x, y) -> fminnum x, y
6399 // select x, y (fcmp gt x, y) -> fmaxnum x, y
6400 //
6401 // This is OK if we don't care about what happens if either operand is a
6402 // NaN.
6403 //
6404
6405 // FIXME: Instead of testing for UnsafeFPMath, this should be checking for
6406 // no signed zeros as well as no nans.
6407 const TargetOptions &Options = DAG.getTarget().Options;
6408 if (Options.UnsafeFPMath && VT.isFloatingPoint() && N0.hasOneUse() &&
6409 DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
6410 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
6411
6412 if (SDValue FMinMax = combineMinNumMaxNum(
6413 DL, VT, N0.getOperand(0), N0.getOperand(1), N1, N2, CC, TLI, DAG))
6414 return FMinMax;
6415 }
6416
6417 if ((!LegalOperations &&
6418 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
6419 TLI.isOperationLegal(ISD::SELECT_CC, VT))
6420 return DAG.getNode(ISD::SELECT_CC, DL, VT, N0.getOperand(0),
6421 N0.getOperand(1), N1, N2, N0.getOperand(2));
6422 return SimplifySelect(DL, N0, N1, N2);
6423 }
6424
6425 return SDValue();
6426}
6427
6428static
6429std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
6430 SDLoc DL(N);
6431 EVT LoVT, HiVT;
6432 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
6433
6434 // Split the inputs.
6435 SDValue Lo, Hi, LL, LH, RL, RH;
6436 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
6437 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
6438
6439 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
6440 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
6441
6442 return std::make_pair(Lo, Hi);
6443}
6444
6445// This function assumes all the vselect's arguments are CONCAT_VECTOR
6446// nodes and that the condition is a BV of ConstantSDNodes (or undefs).
6447static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
6448 SDLoc DL(N);
6449 SDValue Cond = N->getOperand(0);
6450 SDValue LHS = N->getOperand(1);
6451 SDValue RHS = N->getOperand(2);
6452 EVT VT = N->getValueType(0);
6453 int NumElems = VT.getVectorNumElements();
6454 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&(static_cast <bool> (LHS.getOpcode() == ISD::CONCAT_VECTORS
&& RHS.getOpcode() == ISD::CONCAT_VECTORS &&
Cond.getOpcode() == ISD::BUILD_VECTOR) ? void (0) : __assert_fail
("LHS.getOpcode() == ISD::CONCAT_VECTORS && RHS.getOpcode() == ISD::CONCAT_VECTORS && Cond.getOpcode() == ISD::BUILD_VECTOR"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6456, __extension__ __PRETTY_FUNCTION__))
6455 RHS.getOpcode() == ISD::CONCAT_VECTORS &&(static_cast <bool> (LHS.getOpcode() == ISD::CONCAT_VECTORS
&& RHS.getOpcode() == ISD::CONCAT_VECTORS &&
Cond.getOpcode() == ISD::BUILD_VECTOR) ? void (0) : __assert_fail
("LHS.getOpcode() == ISD::CONCAT_VECTORS && RHS.getOpcode() == ISD::CONCAT_VECTORS && Cond.getOpcode() == ISD::BUILD_VECTOR"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6456, __extension__ __PRETTY_FUNCTION__))
6456 Cond.getOpcode() == ISD::BUILD_VECTOR)(static_cast <bool> (LHS.getOpcode() == ISD::CONCAT_VECTORS
&& RHS.getOpcode() == ISD::CONCAT_VECTORS &&
Cond.getOpcode() == ISD::BUILD_VECTOR) ? void (0) : __assert_fail
("LHS.getOpcode() == ISD::CONCAT_VECTORS && RHS.getOpcode() == ISD::CONCAT_VECTORS && Cond.getOpcode() == ISD::BUILD_VECTOR"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6456, __extension__ __PRETTY_FUNCTION__))
;
6457
6458 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
6459 // binary ones here.
6460 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
6461 return SDValue();
6462
6463 // We're sure we have an even number of elements due to the
6464 // concat_vectors we have as arguments to vselect.
6465 // Skip BV elements until we find one that's not an UNDEF
6466 // After we find an UNDEF element, keep looping until we get to half the
6467 // length of the BV and see if all the non-undef nodes are the same.
6468 ConstantSDNode *BottomHalf = nullptr;
6469 for (int i = 0; i < NumElems / 2; ++i) {
6470 if (Cond->getOperand(i)->isUndef())
6471 continue;
6472
6473 if (BottomHalf == nullptr)
6474 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
6475 else if (Cond->getOperand(i).getNode() != BottomHalf)
6476 return SDValue();
6477 }
6478
6479 // Do the same for the second half of the BuildVector
6480 ConstantSDNode *TopHalf = nullptr;
6481 for (int i = NumElems / 2; i < NumElems; ++i) {
6482 if (Cond->getOperand(i)->isUndef())
6483 continue;
6484
6485 if (TopHalf == nullptr)
6486 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
6487 else if (Cond->getOperand(i).getNode() != TopHalf)
6488 return SDValue();
6489 }
6490
6491 assert(TopHalf && BottomHalf &&(static_cast <bool> (TopHalf && BottomHalf &&
"One half of the selector was all UNDEFs and the other was all the "
"same value. This should have been addressed before this function."
) ? void (0) : __assert_fail ("TopHalf && BottomHalf && \"One half of the selector was all UNDEFs and the other was all the \" \"same value. This should have been addressed before this function.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6493, __extension__ __PRETTY_FUNCTION__))
6492 "One half of the selector was all UNDEFs and the other was all the "(static_cast <bool> (TopHalf && BottomHalf &&
"One half of the selector was all UNDEFs and the other was all the "
"same value. This should have been addressed before this function."
) ? void (0) : __assert_fail ("TopHalf && BottomHalf && \"One half of the selector was all UNDEFs and the other was all the \" \"same value. This should have been addressed before this function.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6493, __extension__ __PRETTY_FUNCTION__))
6493 "same value. This should have been addressed before this function.")(static_cast <bool> (TopHalf && BottomHalf &&
"One half of the selector was all UNDEFs and the other was all the "
"same value. This should have been addressed before this function."
) ? void (0) : __assert_fail ("TopHalf && BottomHalf && \"One half of the selector was all UNDEFs and the other was all the \" \"same value. This should have been addressed before this function.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6493, __extension__ __PRETTY_FUNCTION__))
;
6494 return DAG.getNode(
6495 ISD::CONCAT_VECTORS, DL, VT,
6496 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
6497 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
6498}
6499
6500SDValue DAGCombiner::visitMSCATTER(SDNode *N) {
6501 if (Level >= AfterLegalizeTypes)
6502 return SDValue();
6503
6504 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
6505 SDValue Mask = MSC->getMask();
6506 SDValue Data = MSC->getValue();
6507 SDLoc DL(N);
6508
6509 // If the MSCATTER data type requires splitting and the mask is provided by a
6510 // SETCC, then split both nodes and its operands before legalization. This
6511 // prevents the type legalizer from unrolling SETCC into scalar comparisons
6512 // and enables future optimizations (e.g. min/max pattern matching on X86).
6513 if (Mask.getOpcode() != ISD::SETCC)
6514 return SDValue();
6515
6516 // Check if any splitting is required.
6517 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
6518 TargetLowering::TypeSplitVector)
6519 return SDValue();
6520 SDValue MaskLo, MaskHi, Lo, Hi;
6521 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
6522
6523 EVT LoVT, HiVT;
6524 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MSC->getValueType(0));
6525
6526 SDValue Chain = MSC->getChain();
6527
6528 EVT MemoryVT = MSC->getMemoryVT();
6529 unsigned Alignment = MSC->getOriginalAlignment();
6530
6531 EVT LoMemVT, HiMemVT;
6532 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
6533
6534 SDValue DataLo, DataHi;
6535 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
6536
6537 SDValue BasePtr = MSC->getBasePtr();
6538 SDValue IndexLo, IndexHi;
6539 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MSC->getIndex(), DL);
6540
6541 MachineMemOperand *MMO = DAG.getMachineFunction().
6542 getMachineMemOperand(MSC->getPointerInfo(),
6543 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
6544 Alignment, MSC->getAAInfo(), MSC->getRanges());
6545
6546 SDValue OpsLo[] = { Chain, DataLo, MaskLo, BasePtr, IndexLo };
6547 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
6548 DL, OpsLo, MMO);
6549
6550 SDValue OpsHi[] = {Chain, DataHi, MaskHi, BasePtr, IndexHi};
6551 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
6552 DL, OpsHi, MMO);
6553
6554 AddToWorklist(Lo.getNode());
6555 AddToWorklist(Hi.getNode());
6556
6557 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
6558}
6559
6560SDValue DAGCombiner::visitMSTORE(SDNode *N) {
6561 if (Level >= AfterLegalizeTypes)
6562 return SDValue();
6563
6564 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
6565 SDValue Mask = MST->getMask();
6566 SDValue Data = MST->getValue();
6567 EVT VT = Data.getValueType();
6568 SDLoc DL(N);
6569
6570 // If the MSTORE data type requires splitting and the mask is provided by a
6571 // SETCC, then split both nodes and its operands before legalization. This
6572 // prevents the type legalizer from unrolling SETCC into scalar comparisons
6573 // and enables future optimizations (e.g. min/max pattern matching on X86).
6574 if (Mask.getOpcode() == ISD::SETCC) {
6575 // Check if any splitting is required.
6576 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
6577 TargetLowering::TypeSplitVector)
6578 return SDValue();
6579
6580 SDValue MaskLo, MaskHi, Lo, Hi;
6581 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
6582
6583 SDValue Chain = MST->getChain();
6584 SDValue Ptr = MST->getBasePtr();
6585
6586 EVT MemoryVT = MST->getMemoryVT();
6587 unsigned Alignment = MST->getOriginalAlignment();
6588
6589 // if Alignment is equal to the vector size,
6590 // take the half of it for the second part
6591 unsigned SecondHalfAlignment =
6592 (Alignment == VT.getSizeInBits() / 8) ? Alignment / 2 : Alignment;
6593
6594 EVT LoMemVT, HiMemVT;
6595 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
6596
6597 SDValue DataLo, DataHi;
6598 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
6599
6600 MachineMemOperand *MMO = DAG.getMachineFunction().
6601 getMachineMemOperand(MST->getPointerInfo(),
6602 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
6603 Alignment, MST->getAAInfo(), MST->getRanges());
6604
6605 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
6606 MST->isTruncatingStore(),
6607 MST->isCompressingStore());
6608
6609 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
6610 MST->isCompressingStore());
6611
6612 MMO = DAG.getMachineFunction().
6613 getMachineMemOperand(MST->getPointerInfo(),
6614 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
6615 SecondHalfAlignment, MST->getAAInfo(),
6616 MST->getRanges());
6617
6618 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
6619 MST->isTruncatingStore(),
6620 MST->isCompressingStore());
6621
6622 AddToWorklist(Lo.getNode());
6623 AddToWorklist(Hi.getNode());
6624
6625 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
6626 }
6627 return SDValue();
6628}
6629
6630SDValue DAGCombiner::visitMGATHER(SDNode *N) {
6631 if (Level >= AfterLegalizeTypes)
6632 return SDValue();
6633
6634 MaskedGatherSDNode *MGT = cast<MaskedGatherSDNode>(N);
6635 SDValue Mask = MGT->getMask();
6636 SDLoc DL(N);
6637
6638 // If the MGATHER result requires splitting and the mask is provided by a
6639 // SETCC, then split both nodes and its operands before legalization. This
6640 // prevents the type legalizer from unrolling SETCC into scalar comparisons
6641 // and enables future optimizations (e.g. min/max pattern matching on X86).
6642
6643 if (Mask.getOpcode() != ISD::SETCC)
6644 return SDValue();
6645
6646 EVT VT = N->getValueType(0);
6647
6648 // Check if any splitting is required.
6649 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
6650 TargetLowering::TypeSplitVector)
6651 return SDValue();
6652
6653 SDValue MaskLo, MaskHi, Lo, Hi;
6654 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
6655
6656 SDValue Src0 = MGT->getValue();
6657 SDValue Src0Lo, Src0Hi;
6658 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
6659
6660 EVT LoVT, HiVT;
6661 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
6662
6663 SDValue Chain = MGT->getChain();
6664 EVT MemoryVT = MGT->getMemoryVT();
6665 unsigned Alignment = MGT->getOriginalAlignment();
6666
6667 EVT LoMemVT, HiMemVT;
6668 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
6669
6670 SDValue BasePtr = MGT->getBasePtr();
6671 SDValue Index = MGT->getIndex();
6672 SDValue IndexLo, IndexHi;
6673 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
6674
6675 MachineMemOperand *MMO = DAG.getMachineFunction().
6676 getMachineMemOperand(MGT->getPointerInfo(),
6677 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
6678 Alignment, MGT->getAAInfo(), MGT->getRanges());
6679
6680 SDValue OpsLo[] = { Chain, Src0Lo, MaskLo, BasePtr, IndexLo };
6681 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, DL, OpsLo,
6682 MMO);
6683
6684 SDValue OpsHi[] = {Chain, Src0Hi, MaskHi, BasePtr, IndexHi};
6685 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, DL, OpsHi,
6686 MMO);
6687
6688 AddToWorklist(Lo.getNode());
6689 AddToWorklist(Hi.getNode());
6690
6691 // Build a factor node to remember that this load is independent of the
6692 // other one.
6693 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
6694 Hi.getValue(1));
6695
6696 // Legalized the chain result - switch anything that used the old chain to
6697 // use the new one.
6698 DAG.ReplaceAllUsesOfValueWith(SDValue(MGT, 1), Chain);
6699
6700 SDValue GatherRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
6701
6702 SDValue RetOps[] = { GatherRes, Chain };
6703 return DAG.getMergeValues(RetOps, DL);
6704}
6705
6706SDValue DAGCombiner::visitMLOAD(SDNode *N) {
6707 if (Level >= AfterLegalizeTypes)
6708 return SDValue();
6709
6710 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
6711 SDValue Mask = MLD->getMask();
6712 SDLoc DL(N);
6713
6714 // If the MLOAD result requires splitting and the mask is provided by a
6715 // SETCC, then split both nodes and its operands before legalization. This
6716 // prevents the type legalizer from unrolling SETCC into scalar comparisons
6717 // and enables future optimizations (e.g. min/max pattern matching on X86).
6718 if (Mask.getOpcode() == ISD::SETCC) {
6719 EVT VT = N->getValueType(0);
6720
6721 // Check if any splitting is required.
6722 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
6723 TargetLowering::TypeSplitVector)
6724 return SDValue();
6725
6726 SDValue MaskLo, MaskHi, Lo, Hi;
6727 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
6728
6729 SDValue Src0 = MLD->getSrc0();
6730 SDValue Src0Lo, Src0Hi;
6731 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
6732
6733 EVT LoVT, HiVT;
6734 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
6735
6736 SDValue Chain = MLD->getChain();
6737 SDValue Ptr = MLD->getBasePtr();
6738 EVT MemoryVT = MLD->getMemoryVT();
6739 unsigned Alignment = MLD->getOriginalAlignment();
6740
6741 // if Alignment is equal to the vector size,
6742 // take the half of it for the second part
6743 unsigned SecondHalfAlignment =
6744 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
6745 Alignment/2 : Alignment;
6746
6747 EVT LoMemVT, HiMemVT;
6748 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
6749
6750 MachineMemOperand *MMO = DAG.getMachineFunction().
6751 getMachineMemOperand(MLD->getPointerInfo(),
6752 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
6753 Alignment, MLD->getAAInfo(), MLD->getRanges());
6754
6755 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
6756 ISD::NON_EXTLOAD, MLD->isExpandingLoad());
6757
6758 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
6759 MLD->isExpandingLoad());
6760
6761 MMO = DAG.getMachineFunction().
6762 getMachineMemOperand(MLD->getPointerInfo(),
6763 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
6764 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
6765
6766 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
6767 ISD::NON_EXTLOAD, MLD->isExpandingLoad());
6768
6769 AddToWorklist(Lo.getNode());
6770 AddToWorklist(Hi.getNode());
6771
6772 // Build a factor node to remember that this load is independent of the
6773 // other one.
6774 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
6775 Hi.getValue(1));
6776
6777 // Legalized the chain result - switch anything that used the old chain to
6778 // use the new one.
6779 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
6780
6781 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
6782
6783 SDValue RetOps[] = { LoadRes, Chain };
6784 return DAG.getMergeValues(RetOps, DL);
6785 }
6786 return SDValue();
6787}
6788
6789/// A vector select of 2 constant vectors can be simplified to math/logic to
6790/// avoid a variable select instruction and possibly avoid constant loads.
6791SDValue DAGCombiner::foldVSelectOfConstants(SDNode *N) {
6792 SDValue Cond = N->getOperand(0);
6793 SDValue N1 = N->getOperand(1);
6794 SDValue N2 = N->getOperand(2);
6795 EVT VT = N->getValueType(0);
6796 if (!Cond.hasOneUse() || Cond.getScalarValueSizeInBits() != 1 ||
6797 !TLI.convertSelectOfConstantsToMath(VT) ||
6798 !ISD::isBuildVectorOfConstantSDNodes(N1.getNode()) ||
6799 !ISD::isBuildVectorOfConstantSDNodes(N2.getNode()))
6800 return SDValue();
6801
6802 // Check if we can use the condition value to increment/decrement a single
6803 // constant value. This simplifies a select to an add and removes a constant
6804 // load/materialization from the general case.
6805 bool AllAddOne = true;
6806 bool AllSubOne = true;
6807 unsigned Elts = VT.getVectorNumElements();
6808 for (unsigned i = 0; i != Elts; ++i) {
6809 SDValue N1Elt = N1.getOperand(i);
6810 SDValue N2Elt = N2.getOperand(i);
6811 if (N1Elt.isUndef() || N2Elt.isUndef())
6812 continue;
6813
6814 const APInt &C1 = cast<ConstantSDNode>(N1Elt)->getAPIntValue();
6815 const APInt &C2 = cast<ConstantSDNode>(N2Elt)->getAPIntValue();
6816 if (C1 != C2 + 1)
6817 AllAddOne = false;
6818 if (C1 != C2 - 1)
6819 AllSubOne = false;
6820 }
6821
6822 // Further simplifications for the extra-special cases where the constants are
6823 // all 0 or all -1 should be implemented as folds of these patterns.
6824 SDLoc DL(N);
6825 if (AllAddOne || AllSubOne) {
6826 // vselect <N x i1> Cond, C+1, C --> add (zext Cond), C
6827 // vselect <N x i1> Cond, C-1, C --> add (sext Cond), C
6828 auto ExtendOpcode = AllAddOne ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
6829 SDValue ExtendedCond = DAG.getNode(ExtendOpcode, DL, VT, Cond);
6830 return DAG.getNode(ISD::ADD, DL, VT, ExtendedCond, N2);
6831 }
6832
6833 // The general case for select-of-constants:
6834 // vselect <N x i1> Cond, C1, C2 --> xor (and (sext Cond), (C1^C2)), C2
6835 // ...but that only makes sense if a vselect is slower than 2 logic ops, so
6836 // leave that to a machine-specific pass.
6837 return SDValue();
6838}
6839
6840SDValue DAGCombiner::visitVSELECT(SDNode *N) {
6841 SDValue N0 = N->getOperand(0);
6842 SDValue N1 = N->getOperand(1);
6843 SDValue N2 = N->getOperand(2);
6844 SDLoc DL(N);
6845
6846 // fold (vselect C, X, X) -> X
6847 if (N1 == N2)
6848 return N1;
6849
6850 // Canonicalize integer abs.
6851 // vselect (setg[te] X, 0), X, -X ->
6852 // vselect (setgt X, -1), X, -X ->
6853 // vselect (setl[te] X, 0), -X, X ->
6854 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6855 if (N0.getOpcode() == ISD::SETCC) {
6856 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
6857 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
6858 bool isAbs = false;
6859 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
6860
6861 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
6862 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
6863 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
6864 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
6865 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
6866 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
6867 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
6868
6869 if (isAbs) {
6870 EVT VT = LHS.getValueType();
6871 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT))
6872 return DAG.getNode(ISD::ABS, DL, VT, LHS);
6873
6874 SDValue Shift = DAG.getNode(
6875 ISD::SRA, DL, VT, LHS,
6876 DAG.getConstant(VT.getScalarSizeInBits() - 1, DL, VT));
6877 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
6878 AddToWorklist(Shift.getNode());
6879 AddToWorklist(Add.getNode());
6880 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
6881 }
6882 }
6883
6884 if (SimplifySelectOps(N, N1, N2))
6885 return SDValue(N, 0); // Don't revisit N.
6886
6887 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
6888 if (ISD::isBuildVectorAllOnes(N0.getNode()))
6889 return N1;
6890 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
6891 if (ISD::isBuildVectorAllZeros(N0.getNode()))
6892 return N2;
6893
6894 // The ConvertSelectToConcatVector function is assuming both the above
6895 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
6896 // and addressed.
6897 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
6898 N2.getOpcode() == ISD::CONCAT_VECTORS &&
6899 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6900 if (SDValue CV = ConvertSelectToConcatVector(N, DAG))
6901 return CV;
6902 }
6903
6904 if (SDValue V = foldVSelectOfConstants(N))
6905 return V;
6906
6907 return SDValue();
6908}
6909
6910SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
6911 SDValue N0 = N->getOperand(0);
6912 SDValue N1 = N->getOperand(1);
6913 SDValue N2 = N->getOperand(2);
6914 SDValue N3 = N->getOperand(3);
6915 SDValue N4 = N->getOperand(4);
6916 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
6917
6918 // fold select_cc lhs, rhs, x, x, cc -> x
6919 if (N2 == N3)
6920 return N2;
6921
6922 // Determine if the condition we're dealing with is constant
6923 if (SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), N0, N1,
6924 CC, SDLoc(N), false)) {
6925 AddToWorklist(SCC.getNode());
6926
6927 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
6928 if (!SCCC->isNullValue())
6929 return N2; // cond always true -> true val
6930 else
6931 return N3; // cond always false -> false val
6932 } else if (SCC->isUndef()) {
6933 // When the condition is UNDEF, just return the first operand. This is
6934 // coherent the DAG creation, no setcc node is created in this case
6935 return N2;
6936 } else if (SCC.getOpcode() == ISD::SETCC) {
6937 // Fold to a simpler select_cc
6938 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
6939 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
6940 SCC.getOperand(2));
6941 }
6942 }
6943
6944 // If we can fold this based on the true/false value, do so.
6945 if (SimplifySelectOps(N, N2, N3))
6946 return SDValue(N, 0); // Don't revisit N.
6947
6948 // fold select_cc into other things, such as min/max/abs
6949 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
6950}
6951
6952SDValue DAGCombiner::visitSETCC(SDNode *N) {
6953 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
6954 cast<CondCodeSDNode>(N->getOperand(2))->get(),
6955 SDLoc(N));
6956}
6957
6958SDValue DAGCombiner::visitSETCCE(SDNode *N) {
6959 SDValue LHS = N->getOperand(0);
6960 SDValue RHS = N->getOperand(1);
6961 SDValue Carry = N->getOperand(2);
6962 SDValue Cond = N->getOperand(3);
6963
6964 // If Carry is false, fold to a regular SETCC.
6965 if (Carry.getOpcode() == ISD::CARRY_FALSE)
6966 return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond);
6967
6968 return SDValue();
6969}
6970
6971SDValue DAGCombiner::visitSETCCCARRY(SDNode *N) {
6972 SDValue LHS = N->getOperand(0);
6973 SDValue RHS = N->getOperand(1);
6974 SDValue Carry = N->getOperand(2);
6975 SDValue Cond = N->getOperand(3);
6976
6977 // If Carry is false, fold to a regular SETCC.
6978 if (isNullConstant(Carry))
6979 return DAG.getNode(ISD::SETCC, SDLoc(N), N->getVTList(), LHS, RHS, Cond);
6980
6981 return SDValue();
6982}
6983
6984/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
6985/// a build_vector of constants.
6986/// This function is called by the DAGCombiner when visiting sext/zext/aext
6987/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
6988/// Vector extends are not folded if operations are legal; this is to
6989/// avoid introducing illegal build_vector dag nodes.
6990static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
6991 SelectionDAG &DAG, bool LegalTypes,
6992 bool LegalOperations) {
6993 unsigned Opcode = N->getOpcode();
6994 SDValue N0 = N->getOperand(0);
6995 EVT VT = N->getValueType(0);
6996
6997 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||(static_cast <bool> ((Opcode == ISD::SIGN_EXTEND || Opcode
== ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode ==
ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG
) && "Expected EXTEND dag node in input!") ? void (0)
: __assert_fail ("(Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) && \"Expected EXTEND dag node in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7000, __extension__ __PRETTY_FUNCTION__))
6998 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||(static_cast <bool> ((Opcode == ISD::SIGN_EXTEND || Opcode
== ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode ==
ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG
) && "Expected EXTEND dag node in input!") ? void (0)
: __assert_fail ("(Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) && \"Expected EXTEND dag node in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7000, __extension__ __PRETTY_FUNCTION__))
6999 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG)(static_cast <bool> ((Opcode == ISD::SIGN_EXTEND || Opcode
== ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode ==
ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG
) && "Expected EXTEND dag node in input!") ? void (0)
: __assert_fail ("(Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) && \"Expected EXTEND dag node in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7000, __extension__ __PRETTY_FUNCTION__))
7000 && "Expected EXTEND dag node in input!")(static_cast <bool> ((Opcode == ISD::SIGN_EXTEND || Opcode
== ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode ==
ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG
) && "Expected EXTEND dag node in input!") ? void (0)
: __assert_fail ("(Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND || Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) && \"Expected EXTEND dag node in input!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7000, __extension__ __PRETTY_FUNCTION__))
;
7001
7002 // fold (sext c1) -> c1
7003 // fold (zext c1) -> c1
7004 // fold (aext c1) -> c1
7005 if (isa<ConstantSDNode>(N0))
7006 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
7007
7008 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
7009 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
7010 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
7011 EVT SVT = VT.getScalarType();
7012 if (!(VT.isVector() &&
7013 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
7014 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
7015 return nullptr;
7016
7017 // We can fold this node into a build_vector.
7018 unsigned VTBits = SVT.getSizeInBits();
7019 unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits();
7020 SmallVector<SDValue, 8> Elts;
7021 unsigned NumElts = VT.getVectorNumElements();
7022 SDLoc DL(N);
7023
7024 for (unsigned i=0; i != NumElts; ++i) {
7025 SDValue Op = N0->getOperand(i);
7026 if (Op->isUndef()) {
7027 Elts.push_back(DAG.getUNDEF(SVT));
7028 continue;
7029 }
7030
7031 SDLoc DL(Op);
7032 // Get the constant value and if needed trunc it to the size of the type.
7033 // Nodes like build_vector might have constants wider than the scalar type.
7034 APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
7035 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
7036 Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
7037 else
7038 Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT));
7039 }
7040
7041 return DAG.getBuildVector(VT, DL, Elts).getNode();
7042}
7043
7044// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
7045// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
7046// transformation. Returns true if extension are possible and the above
7047// mentioned transformation is profitable.
7048static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
7049 unsigned ExtOpc,
7050 SmallVectorImpl<SDNode *> &ExtendNodes,
7051 const TargetLowering &TLI) {
7052 bool HasCopyToRegUses = false;
7053 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
7054 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
7055 UE = N0.getNode()->use_end();
7056 UI != UE; ++UI) {
7057 SDNode *User = *UI;
7058 if (User == N)
7059 continue;
7060 if (UI.getUse().getResNo() != N0.getResNo())
7061 continue;
7062 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
7063 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
7064 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
7065 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
7066 // Sign bits will be lost after a zext.
7067 return false;
7068 bool Add = false;
7069 for (unsigned i = 0; i != 2; ++i) {
7070 SDValue UseOp = User->getOperand(i);
7071 if (UseOp == N0)
7072 continue;
7073 if (!isa<ConstantSDNode>(UseOp))
7074 return false;
7075 Add = true;
7076 }
7077 if (Add)
7078 ExtendNodes.push_back(User);
7079 continue;
7080 }
7081 // If truncates aren't free and there are users we can't
7082 // extend, it isn't worthwhile.
7083 if (!isTruncFree)
7084 return false;
7085 // Remember if this value is live-out.
7086 if (User->getOpcode() == ISD::CopyToReg)
7087 HasCopyToRegUses = true;
7088 }
7089
7090 if (HasCopyToRegUses) {
7091 bool BothLiveOut = false;
7092 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7093 UI != UE; ++UI) {
7094 SDUse &Use = UI.getUse();
7095 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
7096 BothLiveOut = true;
7097 break;
7098 }
7099 }
7100 if (BothLiveOut)
7101 // Both unextended and extended values are live out. There had better be
7102 // a good reason for the transformation.
7103 return ExtendNodes.size();
7104 }
7105 return true;
7106}
7107
7108void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
7109 SDValue Trunc, SDValue ExtLoad,
7110 const SDLoc &DL, ISD::NodeType ExtType) {
7111 // Extend SetCC uses if necessary.
7112 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
7113 SDNode *SetCC = SetCCs[i];
7114 SmallVector<SDValue, 4> Ops;
7115
7116 for (unsigned j = 0; j != 2; ++j) {
7117 SDValue SOp = SetCC->getOperand(j);
7118 if (SOp == Trunc)
7119 Ops.push_back(ExtLoad);
7120 else
7121 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
7122 }
7123
7124 Ops.push_back(SetCC->getOperand(2));
7125 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
7126 }
7127}
7128
7129// FIXME: Bring more similar combines here, common to sext/zext (maybe aext?).
7130SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
7131 SDValue N0 = N->getOperand(0);
7132 EVT DstVT = N->getValueType(0);
7133 EVT SrcVT = N0.getValueType();
7134
7135 assert((N->getOpcode() == ISD::SIGN_EXTEND ||(static_cast <bool> ((N->getOpcode() == ISD::SIGN_EXTEND
|| N->getOpcode() == ISD::ZERO_EXTEND) && "Unexpected node type (not an extend)!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) && \"Unexpected node type (not an extend)!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7137, __extension__ __PRETTY_FUNCTION__))
7136 N->getOpcode() == ISD::ZERO_EXTEND) &&(static_cast <bool> ((N->getOpcode() == ISD::SIGN_EXTEND
|| N->getOpcode() == ISD::ZERO_EXTEND) && "Unexpected node type (not an extend)!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) && \"Unexpected node type (not an extend)!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7137, __extension__ __PRETTY_FUNCTION__))
7137 "Unexpected node type (not an extend)!")(static_cast <bool> ((N->getOpcode() == ISD::SIGN_EXTEND
|| N->getOpcode() == ISD::ZERO_EXTEND) && "Unexpected node type (not an extend)!"
) ? void (0) : __assert_fail ("(N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) && \"Unexpected node type (not an extend)!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7137, __extension__ __PRETTY_FUNCTION__))
;
7138
7139 // fold (sext (load x)) to multiple smaller sextloads; same for zext.
7140 // For example, on a target with legal v4i32, but illegal v8i32, turn:
7141 // (v8i32 (sext (v8i16 (load x))))
7142 // into:
7143 // (v8i32 (concat_vectors (v4i32 (sextload x)),
7144 // (v4i32 (sextload (x + 16)))))
7145 // Where uses of the original load, i.e.:
7146 // (v8i16 (load x))
7147 // are replaced with:
7148 // (v8i16 (truncate
7149 // (v8i32 (concat_vectors (v4i32 (sextload x)),
7150 // (v4i32 (sextload (x + 16)))))))
7151 //
7152 // This combine is only applicable to illegal, but splittable, vectors.
7153 // All legal types, and illegal non-vector types, are handled elsewhere.
7154 // This combine is controlled by TargetLowering::isVectorLoadExtDesirable.
7155 //
7156 if (N0->getOpcode() != ISD::LOAD)
7157 return SDValue();
7158
7159 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7160
7161 if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) ||
7162 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() ||
7163 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
7164 return SDValue();
7165
7166 SmallVector<SDNode *, 4> SetCCs;
7167 if (!ExtendUsesToFormExtLoad(N, N0, N->getOpcode(), SetCCs, TLI))
7168 return SDValue();
7169
7170 ISD::LoadExtType ExtType =
7171 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
7172
7173 // Try to split the vector types to get down to legal types.
7174 EVT SplitSrcVT = SrcVT;
7175 EVT SplitDstVT = DstVT;
7176 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) &&
7177 SplitSrcVT.getVectorNumElements() > 1) {
7178 SplitDstVT = DAG.GetSplitDestVTs(SplitDstVT).first;
7179 SplitSrcVT = DAG.GetSplitDestVTs(SplitSrcVT).first;
7180 }
7181
7182 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT))
7183 return SDValue();
7184
7185 SDLoc DL(N);
7186 const unsigned NumSplits =
7187 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements();
7188 const unsigned Stride = SplitSrcVT.getStoreSize();
7189 SmallVector<SDValue, 4> Loads;
7190 SmallVector<SDValue, 4> Chains;
7191
7192 SDValue BasePtr = LN0->getBasePtr();
7193 for (unsigned Idx = 0; Idx < NumSplits; Idx++) {
7194 const unsigned Offset = Idx * Stride;
7195 const unsigned Align = MinAlign(LN0->getAlignment(), Offset);
7196
7197 SDValue SplitLoad = DAG.getExtLoad(
7198 ExtType, DL, SplitDstVT, LN0->getChain(), BasePtr,
7199 LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT, Align,
7200 LN0->getMemOperand()->getFlags(), LN0->getAAInfo());
7201
7202 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
7203 DAG.getConstant(Stride, DL, BasePtr.getValueType()));
7204
7205 Loads.push_back(SplitLoad.getValue(0));
7206 Chains.push_back(SplitLoad.getValue(1));
7207 }
7208
7209 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
7210 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
7211
7212 // Simplify TF.
7213 AddToWorklist(NewChain.getNode());
7214
7215 CombineTo(N, NewValue);
7216
7217 // Replace uses of the original load (before extension)
7218 // with a truncate of the concatenated sextloaded vectors.
7219 SDValue Trunc =
7220 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
7221 CombineTo(N0.getNode(), Trunc, NewChain);
7222 ExtendSetCCUses(SetCCs, Trunc, NewValue, DL,
7223 (ISD::NodeType)N->getOpcode());
7224 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7225}
7226
7227/// If we're narrowing or widening the result of a vector select and the final
7228/// size is the same size as a setcc (compare) feeding the select, then try to
7229/// apply the cast operation to the select's operands because matching vector
7230/// sizes for a select condition and other operands should be more efficient.
7231SDValue DAGCombiner::matchVSelectOpSizesWithSetCC(SDNode *Cast) {
7232 unsigned CastOpcode = Cast->getOpcode();
7233 assert((CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND ||(static_cast <bool> ((CastOpcode == ISD::SIGN_EXTEND ||
CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE
|| CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND
) && "Unexpected opcode for vector select narrowing/widening"
) ? void (0) : __assert_fail ("(CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND) && \"Unexpected opcode for vector select narrowing/widening\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7236, __extension__ __PRETTY_FUNCTION__))
7234 CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND ||(static_cast <bool> ((CastOpcode == ISD::SIGN_EXTEND ||
CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE
|| CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND
) && "Unexpected opcode for vector select narrowing/widening"
) ? void (0) : __assert_fail ("(CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND) && \"Unexpected opcode for vector select narrowing/widening\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7236, __extension__ __PRETTY_FUNCTION__))
7235 CastOpcode == ISD::FP_ROUND) &&(static_cast <bool> ((CastOpcode == ISD::SIGN_EXTEND ||
CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE
|| CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND
) && "Unexpected opcode for vector select narrowing/widening"
) ? void (0) : __assert_fail ("(CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND) && \"Unexpected opcode for vector select narrowing/widening\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7236, __extension__ __PRETTY_FUNCTION__))
7236 "Unexpected opcode for vector select narrowing/widening")(static_cast <bool> ((CastOpcode == ISD::SIGN_EXTEND ||
CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE
|| CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND
) && "Unexpected opcode for vector select narrowing/widening"
) ? void (0) : __assert_fail ("(CastOpcode == ISD::SIGN_EXTEND || CastOpcode == ISD::ZERO_EXTEND || CastOpcode == ISD::TRUNCATE || CastOpcode == ISD::FP_EXTEND || CastOpcode == ISD::FP_ROUND) && \"Unexpected opcode for vector select narrowing/widening\""
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7236, __extension__ __PRETTY_FUNCTION__))
;
7237
7238 // We only do this transform before legal ops because the pattern may be
7239 // obfuscated by target-specific operations after legalization. Do not create
7240 // an illegal select op, however, because that may be difficult to lower.
7241 EVT VT = Cast->getValueType(0);
7242 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
7243 return SDValue();
7244
7245 SDValue VSel = Cast->getOperand(0);
7246 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() ||
7247 VSel.getOperand(0).getOpcode() != ISD::SETCC)
7248 return SDValue();
7249
7250 // Does the setcc have the same vector size as the casted select?
7251 SDValue SetCC = VSel.getOperand(0);
7252 EVT SetCCVT = getSetCCResultType(SetCC.getOperand(0).getValueType());
7253 if (SetCCVT.getSizeInBits() != VT.getSizeInBits())
7254 return SDValue();
7255
7256 // cast (vsel (setcc X), A, B) --> vsel (setcc X), (cast A), (cast B)
7257 SDValue A = VSel.getOperand(1);
7258 SDValue B = VSel.getOperand(2);
7259 SDValue CastA, CastB;
7260 SDLoc DL(Cast);
7261 if (CastOpcode == ISD::FP_ROUND) {
7262 // FP_ROUND (fptrunc) has an extra flag operand to pass along.
7263 CastA = DAG.getNode(CastOpcode, DL, VT, A, Cast->getOperand(1));
7264 CastB = DAG.getNode(CastOpcode, DL, VT, B, Cast->getOperand(1));
7265 } else {
7266 CastA = DAG.getNode(CastOpcode, DL, VT, A);
7267 CastB = DAG.getNode(CastOpcode, DL, VT, B);
7268 }
7269 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB);
7270}
7271
7272SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
7273 SDValue N0 = N->getOperand(0);
7274 EVT VT = N->getValueType(0);
7275 SDLoc DL(N);
7276
7277 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
7278 LegalOperations))
7279 return SDValue(Res, 0);
7280
7281 // fold (sext (sext x)) -> (sext x)
7282 // fold (sext (aext x)) -> (sext x)
7283 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
7284 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0));
7285
7286 if (N0.getOpcode() == ISD::TRUNCATE) {
7287 // fold (sext (truncate (load x))) -> (sext (smaller load x))
7288 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
7289 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
7290 SDNode *oye = N0.getOperand(0).getNode();
7291 if (NarrowLoad.getNode() != N0.getNode()) {
7292 CombineTo(N0.getNode(), NarrowLoad);
7293 // CombineTo deleted the truncate, if needed, but not what's under it.
7294 AddToWorklist(oye);
7295 }
7296 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7297 }
7298
7299 // See if the value being truncated is already sign extended. If so, just
7300 // eliminate the trunc/sext pair.
7301 SDValue Op = N0.getOperand(0);
7302 unsigned OpBits = Op.getScalarValueSizeInBits();
7303 unsigned MidBits = N0.getScalarValueSizeInBits();
7304 unsigned DestBits = VT.getScalarSizeInBits();
7305 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
7306
7307 if (OpBits == DestBits) {
7308 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
7309 // bits, it is already ready.
7310 if (NumSignBits > DestBits-MidBits)
7311 return Op;
7312 } else if (OpBits < DestBits) {
7313 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
7314 // bits, just sext from i32.
7315 if (NumSignBits > OpBits-MidBits)
7316 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op);
7317 } else {
7318 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
7319 // bits, just truncate to i32.
7320 if (NumSignBits > OpBits-MidBits)
7321 return DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
7322 }
7323
7324 // fold (sext (truncate x)) -> (sextinreg x).
7325 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
7326 N0.getValueType())) {
7327 if (OpBits < DestBits)
7328 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
7329 else if (OpBits > DestBits)
7330 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
7331 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Op,
7332 DAG.getValueType(N0.getValueType()));
7333 }
7334 }
7335
7336 // fold (sext (load x)) -> (sext (truncate (sextload x)))
7337 // Only generate vector extloads when 1) they're legal, and 2) they are
7338 // deemed desirable by the target.
7339 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
7340 ((!LegalOperations && !VT.isVector() &&
7341 !cast<LoadSDNode>(N0)->isVolatile()) ||
7342 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
7343 bool DoXform = true;
7344 SmallVector<SDNode*, 4> SetCCs;
7345 if (!N0.hasOneUse())
7346 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
7347 if (VT.isVector())
7348 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
7349 if (DoXform) {
7350 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7351 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
7352 LN0->getBasePtr(), N0.getValueType(),
7353 LN0->getMemOperand());
7354 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
7355 N0.getValueType(), ExtLoad);
7356 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
7357 // If the load value is used only by N, replace it via CombineTo N.
7358 bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse();
7359 CombineTo(N, ExtLoad);
7360 if (NoReplaceTrunc)
7361 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1));
7362 else
7363 CombineTo(LN0, Trunc, ExtLoad.getValue(1));
7364 return SDValue(N, 0);
7365 }
7366 }
7367
7368 // fold (sext (load x)) to multiple smaller sextloads.
7369 // Only on illegal but splittable vectors.
7370 if (SDValue ExtLoad = CombineExtLoad(N))
7371 return ExtLoad;
7372
7373 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
7374 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
7375 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
7376 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
7377 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7378 EVT MemVT = LN0->getMemoryVT();
7379 if ((!LegalOperations && !LN0->isVolatile()) ||
7380 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
7381 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, DL, VT, LN0->getChain(),
7382 LN0->getBasePtr(), MemVT,
7383 LN0->getMemOperand());
7384 CombineTo(N, ExtLoad);
7385 CombineTo(N0.getNode(),
7386 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
7387 N0.getValueType(), ExtLoad),
7388 ExtLoad.getValue(1));
7389 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7390 }
7391 }
7392
7393 // fold (sext (and/or/xor (load x), cst)) ->
7394 // (and/or/xor (sextload x), (sext cst))
7395 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
7396 N0.getOpcode() == ISD::XOR) &&
7397 isa<LoadSDNode>(N0.getOperand(0)) &&
7398 N0.getOperand(1).getOpcode() == ISD::Constant &&
7399 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
7400 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
7401 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
7402 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
7403 bool DoXform = true;
7404 SmallVector<SDNode*, 4> SetCCs;
7405 if (!N0.hasOneUse())
7406 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
7407 SetCCs, TLI);
7408 if (DoXform) {
7409 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
7410 LN0->getChain(), LN0->getBasePtr(),
7411 LN0->getMemoryVT(),
7412 LN0->getMemOperand());
7413 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
7414 Mask = Mask.sext(VT.getSizeInBits());
7415 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
7416 ExtLoad, DAG.getConstant(Mask, DL, VT));
7417 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
7418 SDLoc(N0.getOperand(0)),
7419 N0.getOperand(0).getValueType(), ExtLoad);
7420 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::SIGN_EXTEND);
7421 bool NoReplaceTruncAnd = !N0.hasOneUse();
7422 bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse();
7423 CombineTo(N, And);
7424 // If N0 has multiple uses, change other uses as well.
7425 if (NoReplaceTruncAnd) {
7426 SDValue TruncAnd =
7427 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And);
7428 CombineTo(N0.getNode(), TruncAnd);
7429 }
7430 if (NoReplaceTrunc)
7431 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1));
7432 else
7433 CombineTo(LN0, Trunc, ExtLoad.getValue(1));
7434 return SDValue(N,0); // Return N so it doesn't get rechecked!
7435 }
7436 }
7437 }
7438
7439 if (N0.getOpcode() == ISD::SETCC) {
7440 SDValue N00 = N0.getOperand(0);
7441 SDValue N01 = N0.getOperand(1);
7442 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
7443 EVT N00VT = N0.getOperand(0).getValueType();
7444
7445 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
7446 // Only do this before legalize for now.
7447 if (VT.isVector() && !LegalOperations &&
7448 TLI.getBooleanContents(N00VT) ==
7449 TargetLowering::ZeroOrNegativeOneBooleanContent) {
7450 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
7451 // of the same size as the compared operands. Only optimize sext(setcc())
7452 // if this is the case.
7453 EVT SVT = getSetCCResultType(N00VT);
7454
7455 // We know that the # elements of the results is the same as the
7456 // # elements of the compare (and the # elements of the compare result
7457 // for that matter). Check to see that they are the same size. If so,
7458 // we know that the element size of the sext'd result matches the
7459 // element size of the compare operands.
7460 if (VT.getSizeInBits() == SVT.getSizeInBits())
7461 return DAG.getSetCC(DL, VT, N00, N01, CC);
7462
7463 // If the desired elements are smaller or larger than the source
7464 // elements, we can use a matching integer vector type and then
7465 // truncate/sign extend.
7466 EVT MatchingVecType = N00VT.changeVectorElementTypeToInteger();
7467 if (SVT == MatchingVecType) {
7468 SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC);
7469 return DAG.getSExtOrTrunc(VsetCC, DL, VT);
7470 }
7471 }
7472
7473 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), T, 0)
7474 // Here, T can be 1 or -1, depending on the type of the setcc and
7475 // getBooleanContents().
7476 unsigned SetCCWidth = N0.getScalarValueSizeInBits();
7477
7478 // To determine the "true" side of the select, we need to know the high bit
7479 // of the value returned by the setcc if it evaluates to true.
7480 // If the type of the setcc is i1, then the true case of the select is just
7481 // sext(i1 1), that is, -1.
7482 // If the type of the setcc is larger (say, i8) then the value of the high
7483 // bit depends on getBooleanContents(), so ask TLI for a real "true" value
7484 // of the appropriate width.
7485 SDValue ExtTrueVal = (SetCCWidth == 1) ? DAG.getAllOnesConstant(DL, VT)
7486 : TLI.getConstTrueVal(DAG, VT, DL);
7487 SDValue Zero = DAG.getConstant(0, DL, VT);
7488 if (SDValue SCC =
7489 SimplifySelectCC(DL, N00, N01, ExtTrueVal, Zero, CC, true))
7490 return SCC;
7491
7492 if (!VT.isVector() && !TLI.convertSelectOfConstantsToMath(VT)) {
7493 EVT SetCCVT = getSetCCResultType(N00VT);
7494 // Don't do this transform for i1 because there's a select transform
7495 // that would reverse it.
7496 // TODO: We should not do this transform at all without a target hook
7497 // because a sext is likely cheaper than a select?
7498 if (SetCCVT.getScalarSizeInBits() != 1 &&
7499 (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, N00VT))) {
7500 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC);
7501 return DAG.getSelect(DL, VT, SetCC, ExtTrueVal, Zero);
7502 }
7503 }
7504 }
7505
7506 // fold (sext x) -> (zext x) if the sign bit is known zero.
7507 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
7508 DAG.SignBitIsZero(N0))
7509 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0);
7510
7511 if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N))
7512 return NewVSel;
7513
7514 return SDValue();
7515}
7516
7517// isTruncateOf - If N is a truncate of some other value, return true, record
7518// the value being truncated in Op and which of Op's bits are zero/one in Known.
7519// This function computes KnownBits to avoid a duplicated call to
7520// computeKnownBits in the caller.
7521static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
7522 KnownBits &Known) {
7523 if (N->getOpcode() == ISD::TRUNCATE) {
7524 Op = N->getOperand(0);
7525 DAG.computeKnownBits(Op, Known);
7526 return true;
7527 }
7528
7529 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
7530 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
7531 return false;
7532
7533 SDValue Op0 = N->getOperand(0);
7534 SDValue Op1 = N->getOperand(1);
7535 assert(Op0.getValueType() == Op1.getValueType())(static_cast <bool> (Op0.getValueType() == Op1.getValueType
()) ? void (0) : __assert_fail ("Op0.getValueType() == Op1.getValueType()"
, "/build/llvm-toolchain-snapshot-6.0~svn318801/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 7535, __extension__ __PRETTY_FUNCTION__))
;
7536
7537 if (isNullConstant(Op0))
7538 Op = Op1;
7539 else if (isNullConstant(Op1))
7540 Op = Op0;
7541 else
7542 return false;
7543
7544 DAG.computeKnownBits(Op, Known);
7545
7546 if (!(Known.Zero | 1).isAllOnesValue())
7547 return false;
7548
7549 return true;
7550}
7551
7552SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
7553 SDValue N0 = N->getOperand(0);
7554 EVT VT = N->getValueType(0);
7555
7556 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
7557 LegalOperations))
7558 return SDValue(Res, 0);
7559
7560 // fold (zext (zext x)) -> (zext x)
7561 // fold (zext (aext x)) -> (zext x)
7562 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
7563 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
7564 N0.getOperand(0));
7565
7566 // fold (zext (truncate x)) -> (zext x) or
7567 // (zext (truncate x)) -> (truncate x)
7568 // This is valid when the truncated bits of x are already zero.
7569 // FIXME: We should extend this to work for vectors too.
7570 SDValue Op;
7571 KnownBits Known;
7572 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, Known)) {
7573 APInt TruncatedBits =
7574 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
7575 APInt(Op.getValueSizeInBits(), 0) :
7576 APInt::getBitsSet(Op.getValueSizeInBits(),
7577 N0.getValueSizeInBits(),
7578 std::min(Op.getValueSizeInBits(),
7579 VT.getSizeInBits()));
7580 if (TruncatedBits.isSubsetOf(Known.Zero))
7581 return DAG.getZExtOrTrunc(Op, SDLoc(N), VT);
7582 }
7583
7584 // fold (zext (truncate x)) -> (and x, mask)
7585 if (N0.getOpcode() == ISD::TRUNCATE) {
7586 // fold (zext (truncate (load x))) -> (zext (smaller load x))
7587 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
7588 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
7589 SDNode *oye = N0.getOperand(0).getNode();
7590 if (NarrowLoad.getNode() != N0.getNode()) {
7591 CombineTo(N0.getNode(), NarrowLoad);
7592 // CombineTo deleted the truncate, if needed, but not what's under it.
7593 AddToWorklist(oye);
7594 }
7595 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7596 }
7597
7598 EVT SrcVT = N0.getOperand(0).getValueType();
7599 EVT MinVT = N0.getValueType();
7600
7601 // Try to mask before the extension to avoid having to generate a larger mask,
7602 // possibly over several sub-vectors.
7603 if (SrcVT.bitsLT(VT)) {
7604 if (!LegalOperations || (TLI.isOperationLegal(ISD::AND, SrcVT) &&
7605 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) {
7606 SDValue Op = N0.getOperand(0);
7607 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
7608 AddToWorklist(Op.getNode());
7609 return DAG.getZExtOrTrunc(Op, SDLoc(N), VT);
7610 }
7611 }
7612
7613 if (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) {
7614 SDValue Op = DAG.getAnyExtOrTrunc(N0.getOperand(0), SDLoc(N), VT);
7615 AddToWorklist(Op.getNode());
7616 SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType());
7617 // We may safely transfer the debug info describing the truncate node over
7618 // to the equivalent and operation.
7619 DAG.transferDbgValues(N0, And);
7620 return And;
7621 }
7622 }
7623
7624 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
7625 // if either of the casts is not free.
7626 if (N0.getOpcode() == ISD::AND &&
7627 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
7628 N0.getOperand(1).getOpcode() == ISD::Constant &&
7629 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
7630 N0.getValueType()) ||
7631 !TLI.isZExtFree(N0.getValueType(), VT))) {
7632 SDValue X = N0.getOperand(0).getOperand(0);
7633 X = DAG.getAnyExtOrTrunc(X, SDLoc(X), VT);
7634 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
7635 Mask = Mask.zext(VT.getSizeInBits());
7636 SDLoc DL(N);
7637 return DAG.getNode(ISD::AND, DL, VT,
7638 X, DAG.getConstant(Mask, DL, VT));
7639 }
7640
7641 // fold (zext (load x)) -> (zext (truncate (zextload x)))
7642 // Only generate vector extloads when 1) they're legal, and 2) they are
7643 // deemed desirable by the target.
7644 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
7645 ((!LegalOperations && !VT.isVector() &&
7646 !cast<LoadSDNode>(N0)->isVolatile()) ||
7647 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
7648 bool DoXform = true;
7649 SmallVector<SDNode*, 4> SetCCs;
7650 if (!N0.hasOneUse())
7651 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
7652 if (VT.isVector())
7653 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
7654 if (DoXform) {
7655 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7656 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
7657 LN0->getChain(),
7658 LN0->getBasePtr(), N0.getValueType(),
7659 LN0->getMemOperand());
7660
7661 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
7662 N0.getValueType(), ExtLoad);
7663 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), ISD::ZERO_EXTEND);
7664 // If the load value is used only by N, replace it via CombineTo N.
7665 bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse();
7666 CombineTo(N, ExtLoad);
7667 if (NoReplaceTrunc)
7668 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1));
7669 else
7670 CombineTo(LN0, Trunc, ExtLoad.getValue(1));
7671 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7672 }
7673 }
7674
7675 // fold (zext (load x)) to multiple smaller zextloads.
7676 // Only on illegal but splittable vectors.
7677 if (SDValue ExtLoad = CombineExtLoad(N))
7678 return ExtLoad;
7679
7680 // fold (zext (and/or/xor (load x), cst)) ->
7681 // (and/or/xor (zextload x), (zext cst))
7682 // Unless (and (load x) cst) will match as a zextload already and has
7683 // additional users.
7684 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
7685 N0.getOpcode() == ISD::XOR) &&
7686 isa<LoadSDNode>(N0.getOperand(0)) &&
7687 N0.getOperand(1).getOpcode() == ISD::Constant &&
7688 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
7689 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
7690 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
7691 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
7692 bool DoXform = true;
7693 SmallVector<SDNode*, 4> SetCCs;
7694 if (!N0.hasOneUse()) {
7695 if (N0.getOpcode() == ISD::AND) {
7696 auto *AndC = cast<ConstantSDNode>(N0.getOperand(1));
7697 auto NarrowLoad = false;
7698 EVT LoadResultTy = AndC->getValueType(0);
7699 EVT ExtVT, LoadedVT;
7700 if (isAndLoadExtLoad(AndC, LN0, LoadResultTy, ExtVT, LoadedVT,
7701 NarrowLoad))
7702 DoXform = false;
7703 }
7704 if (DoXform)
7705 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0),
7706 ISD::ZERO_EXTEND, SetCCs, TLI);
7707 }
7708 if (DoXform) {
7709 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
7710 LN0->getChain(), LN0->getBasePtr(),
7711 LN0->getMemoryVT(),
7712 LN0->getMemOperand());
7713 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
7714 Mask = Mask.zext(VT.getSizeInBits());
7715 SDLoc DL(N);
7716 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
7717 ExtLoad, DAG.getConstant(Mask, DL, VT));
7718 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
7719 SDLoc(N0.getOperand(0)),
7720 N0.getOperand(0).getValueType(), ExtLoad);
7721 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL, ISD::ZERO_EXTEND);
7722 bool NoReplaceTruncAnd = !N0.hasOneUse();
7723 bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse();
7724 CombineTo(N, And);
7725 // If N0 has multiple uses, change other uses as well.
7726 if (NoReplaceTruncAnd) {
7727 SDValue TruncAnd =
7728 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And);
7729 CombineTo(N0.getNode(), TruncAnd);
7730 }
7731 if (NoReplaceTrunc)
7732 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1));
7733 else
7734 CombineTo(LN0, Trunc, ExtLoad.getValue(1));
7735 return SDValue(N,0); // Return N so it doesn't get rechecked!
7736 }
7737 }
7738 }
7739
7740 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
7741 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
7742 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
7743 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
7744 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7745 EVT MemVT = LN0->getMemoryVT();
7746 if ((!LegalOperations && !LN0->isVolatile()) ||
7747 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
7748 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
7749 LN0->getChain(),
7750 LN0->getBasePtr(), MemVT,
7751 LN0->getMemOperand());
7752 CombineTo(N, ExtLoad);
7753 CombineTo(N0.getNode(),
7754 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
7755 ExtLoad),
7756 ExtLoad.getValue(1));
7757 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7758 }
7759 }
7760
7761 if (N0.getOpcode() == ISD::SETCC) {
7762 // Only do this before legalize for now.
7763 if (!LegalOperations && VT.isVector() &&
7764 N0.getValueType().getVectorElementType() == MVT::i1) {
7765 EVT N00VT = N0.getOperand(0).getValueType();
7766 if (getSetCCResultType(N00VT) == N0.getValueType())
7767 return SDValue();
7768
7769 // We know that the # elements of the results is the same as the #
7770 // elements of the compare (and the # elements of the compare result for
7771 // that matter). Check to see that they are the same size. If so, we know
7772 // that the element size of the sext'd result matches the element size of
7773 // the compare operands.
7774 SDLoc DL(N);
7775 SDValue VecOnes = DAG.getConstant(1, DL, VT);
7776 if (VT.getSizeInBits() == N00VT.getSizeInBits()) {
7777 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
7778 SDValue VSetCC = DAG.getNode(ISD::SETCC, DL, VT, N0.getOperand(0),
7779 N0.getOperand(1), N0.getOperand(2));
7780 return DAG.getNode(ISD::AND, DL, VT, VSetCC, VecOnes);
7781 }
7782
7783 // If the desired elements are smaller or larger than the source
7784 // elements we can use a matching integer vector type and then
7785 // truncate/sign extend.
7786 EVT MatchingElementType = EVT::getIntegerVT(
7787 *DAG.getContext(), N00VT.getScalarSizeInBits());
7788 EVT MatchingVectorType = EVT::getVectorVT(
7789 *DAG.getContext(), MatchingElementType, N00VT.getVectorNumElements());
7790 SDValue VsetCC =
7791 DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0),
7792 N0.getOperand(1), N0.getOperand(2));
7793 return DAG.getNode(ISD::AND, DL, VT, DAG.getSExtOrTrunc(VsetCC, DL, VT),
7794 VecOnes);
7795 }
7796
7797 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
7798 SDLoc DL(N);
7799 if (SDValue SCC = SimplifySelectCC(
7800 DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT),
7801 DAG.getConstant(0, DL, VT),
7802 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
7803 return SCC;
7804 }
7805
7806 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
7807 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
7808 isa<ConstantSDNode>(N0.getOperand(1)) &&
7809 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
7810 N0.hasOneUse()) {
7811 SDValue ShAmt = N0.getOperand(1);
7812 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
7813 if (N0.getOpcode() == ISD::SHL) {
7814 SDValue InnerZExt = N0.getOperand(0);
7815 // If the original shl may be shifting out bits, do not perform this
7816 // transformation.
7817 unsigned KnownZeroBits = InnerZExt.getValueSizeInBits() -
7818 InnerZExt.getOperand(0).getValueSizeInBits();
7819 if (ShAmtVal > KnownZeroBits)
7820 return SDValue();
7821 }
7822
7823 SDLoc DL(N);
7824
7825 // Ensure that the shift amount is wide enough for the shifted value.
7826 if (VT.getSizeInBits() >= 256)
7827 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
7828
7829 return DAG.getNode(N0.getOpcode(), DL, VT,
7830 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
7831 ShAmt);
7832 }