Bug Summary

File:llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Warning:line 16841, column 11
Value stored to 'StartAddress' during its initialization is never read

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-11-29-190409-37574-1 -x c++ /build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallBitVector.h"
28#include "llvm/ADT/SmallPtrSet.h"
29#include "llvm/ADT/SmallSet.h"
30#include "llvm/ADT/SmallVector.h"
31#include "llvm/ADT/Statistic.h"
32#include "llvm/Analysis/AliasAnalysis.h"
33#include "llvm/Analysis/MemoryLocation.h"
34#include "llvm/Analysis/VectorUtils.h"
35#include "llvm/CodeGen/DAGCombine.h"
36#include "llvm/CodeGen/ISDOpcodes.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineFunction.h"
39#include "llvm/CodeGen/MachineMemOperand.h"
40#include "llvm/CodeGen/RuntimeLibcalls.h"
41#include "llvm/CodeGen/SelectionDAG.h"
42#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
43#include "llvm/CodeGen/SelectionDAGNodes.h"
44#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
45#include "llvm/CodeGen/TargetLowering.h"
46#include "llvm/CodeGen/TargetRegisterInfo.h"
47#include "llvm/CodeGen/TargetSubtargetInfo.h"
48#include "llvm/CodeGen/ValueTypes.h"
49#include "llvm/IR/Attributes.h"
50#include "llvm/IR/Constant.h"
51#include "llvm/IR/DataLayout.h"
52#include "llvm/IR/DerivedTypes.h"
53#include "llvm/IR/Function.h"
54#include "llvm/IR/LLVMContext.h"
55#include "llvm/IR/Metadata.h"
56#include "llvm/Support/Casting.h"
57#include "llvm/Support/CodeGen.h"
58#include "llvm/Support/CommandLine.h"
59#include "llvm/Support/Compiler.h"
60#include "llvm/Support/Debug.h"
61#include "llvm/Support/ErrorHandling.h"
62#include "llvm/Support/KnownBits.h"
63#include "llvm/Support/MachineValueType.h"
64#include "llvm/Support/MathExtras.h"
65#include "llvm/Support/raw_ostream.h"
66#include "llvm/Target/TargetMachine.h"
67#include "llvm/Target/TargetOptions.h"
68#include <algorithm>
69#include <cassert>
70#include <cstdint>
71#include <functional>
72#include <iterator>
73#include <string>
74#include <tuple>
75#include <utility>
76
77using namespace llvm;
78
79#define DEBUG_TYPE"dagcombine" "dagcombine"
80
81STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined"}
;
82STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created"}
;
83STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created"}
;
84STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed"}
;
85STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int"}
;
86STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced"}
;
87STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops"}
;
88
89static cl::opt<bool>
90CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
91 cl::desc("Enable DAG combiner's use of IR alias analysis"));
92
93static cl::opt<bool>
94UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
95 cl::desc("Enable DAG combiner's use of TBAA"));
96
97#ifndef NDEBUG
98static cl::opt<std::string>
99CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
100 cl::desc("Only use DAG-combiner alias analysis in this"
101 " function"));
102#endif
103
104/// Hidden option to stress test load slicing, i.e., when this option
105/// is enabled, load slicing bypasses most of its profitability guards.
106static cl::opt<bool>
107StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
108 cl::desc("Bypass the profitability model of load slicing"),
109 cl::init(false));
110
111static cl::opt<bool>
112 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
113 cl::desc("DAG combiner may split indexing from loads"));
114
115static cl::opt<bool>
116 EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true),
117 cl::desc("DAG combiner enable merging multiple stores "
118 "into a wider store"));
119
120static cl::opt<unsigned> TokenFactorInlineLimit(
121 "combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048),
122 cl::desc("Limit the number of operands to inline for Token Factors"));
123
124static cl::opt<unsigned> StoreMergeDependenceLimit(
125 "combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10),
126 cl::desc("Limit the number of times for the same StoreNode and RootNode "
127 "to bail out in store merging dependence check"));
128
129static cl::opt<bool> EnableReduceLoadOpStoreWidth(
130 "combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true),
131 cl::desc("DAG cominber enable reducing the width of load/op/store "
132 "sequence"));
133
134static cl::opt<bool> EnableShrinkLoadReplaceStoreWithStore(
135 "combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true),
136 cl::desc("DAG cominber enable load/<replace bytes>/store with "
137 "a narrower store"));
138
139namespace {
140
141 class DAGCombiner {
142 SelectionDAG &DAG;
143 const TargetLowering &TLI;
144 const SelectionDAGTargetInfo *STI;
145 CombineLevel Level;
146 CodeGenOpt::Level OptLevel;
147 bool LegalDAG = false;
148 bool LegalOperations = false;
149 bool LegalTypes = false;
150 bool ForCodeSize;
151 bool DisableGenericCombines;
152
153 /// Worklist of all of the nodes that need to be simplified.
154 ///
155 /// This must behave as a stack -- new nodes to process are pushed onto the
156 /// back and when processing we pop off of the back.
157 ///
158 /// The worklist will not contain duplicates but may contain null entries
159 /// due to nodes being deleted from the underlying DAG.
160 SmallVector<SDNode *, 64> Worklist;
161
162 /// Mapping from an SDNode to its position on the worklist.
163 ///
164 /// This is used to find and remove nodes from the worklist (by nulling
165 /// them) when they are deleted from the underlying DAG. It relies on
166 /// stable indices of nodes within the worklist.
167 DenseMap<SDNode *, unsigned> WorklistMap;
168 /// This records all nodes attempted to add to the worklist since we
169 /// considered a new worklist entry. As we keep do not add duplicate nodes
170 /// in the worklist, this is different from the tail of the worklist.
171 SmallSetVector<SDNode *, 32> PruningList;
172
173 /// Set of nodes which have been combined (at least once).
174 ///
175 /// This is used to allow us to reliably add any operands of a DAG node
176 /// which have not yet been combined to the worklist.
177 SmallPtrSet<SDNode *, 32> CombinedNodes;
178
179 /// Map from candidate StoreNode to the pair of RootNode and count.
180 /// The count is used to track how many times we have seen the StoreNode
181 /// with the same RootNode bail out in dependence check. If we have seen
182 /// the bail out for the same pair many times over a limit, we won't
183 /// consider the StoreNode with the same RootNode as store merging
184 /// candidate again.
185 DenseMap<SDNode *, std::pair<SDNode *, unsigned>> StoreRootCountMap;
186
187 // AA - Used for DAG load/store alias analysis.
188 AliasAnalysis *AA;
189
190 /// When an instruction is simplified, add all users of the instruction to
191 /// the work lists because they might get more simplified now.
192 void AddUsersToWorklist(SDNode *N) {
193 for (SDNode *Node : N->uses())
194 AddToWorklist(Node);
195 }
196
197 /// Convenient shorthand to add a node and all of its user to the worklist.
198 void AddToWorklistWithUsers(SDNode *N) {
199 AddUsersToWorklist(N);
200 AddToWorklist(N);
201 }
202
203 // Prune potentially dangling nodes. This is called after
204 // any visit to a node, but should also be called during a visit after any
205 // failed combine which may have created a DAG node.
206 void clearAddedDanglingWorklistEntries() {
207 // Check any nodes added to the worklist to see if they are prunable.
208 while (!PruningList.empty()) {
209 auto *N = PruningList.pop_back_val();
210 if (N->use_empty())
211 recursivelyDeleteUnusedNodes(N);
212 }
213 }
214
215 SDNode *getNextWorklistEntry() {
216 // Before we do any work, remove nodes that are not in use.
217 clearAddedDanglingWorklistEntries();
218 SDNode *N = nullptr;
219 // The Worklist holds the SDNodes in order, but it may contain null
220 // entries.
221 while (!N && !Worklist.empty()) {
222 N = Worklist.pop_back_val();
223 }
224
225 if (N) {
226 bool GoodWorklistEntry = WorklistMap.erase(N);
227 (void)GoodWorklistEntry;
228 assert(GoodWorklistEntry &&((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 229, __PRETTY_FUNCTION__))
229 "Found a worklist entry without a corresponding map entry!")((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 229, __PRETTY_FUNCTION__))
;
230 }
231 return N;
232 }
233
234 /// Call the node-specific routine that folds each particular type of node.
235 SDValue visit(SDNode *N);
236
237 public:
238 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
239 : DAG(D), TLI(D.getTargetLoweringInfo()),
240 STI(D.getSubtarget().getSelectionDAGInfo()),
241 Level(BeforeLegalizeTypes), OptLevel(OL), AA(AA) {
242 ForCodeSize = DAG.shouldOptForSize();
243 DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel);
244
245 MaximumLegalStoreInBits = 0;
246 // We use the minimum store size here, since that's all we can guarantee
247 // for the scalable vector types.
248 for (MVT VT : MVT::all_valuetypes())
249 if (EVT(VT).isSimple() && VT != MVT::Other &&
250 TLI.isTypeLegal(EVT(VT)) &&
251 VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits)
252 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize();
253 }
254
255 void ConsiderForPruning(SDNode *N) {
256 // Mark this for potential pruning.
257 PruningList.insert(N);
258 }
259
260 /// Add to the worklist making sure its instance is at the back (next to be
261 /// processed.)
262 void AddToWorklist(SDNode *N) {
263 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 264, __PRETTY_FUNCTION__))
264 "Deleted Node added to Worklist")((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 264, __PRETTY_FUNCTION__))
;
265
266 // Skip handle nodes as they can't usefully be combined and confuse the
267 // zero-use deletion strategy.
268 if (N->getOpcode() == ISD::HANDLENODE)
269 return;
270
271 ConsiderForPruning(N);
272
273 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
274 Worklist.push_back(N);
275 }
276
277 /// Remove all instances of N from the worklist.
278 void removeFromWorklist(SDNode *N) {
279 CombinedNodes.erase(N);
280 PruningList.remove(N);
281 StoreRootCountMap.erase(N);
282
283 auto It = WorklistMap.find(N);
284 if (It == WorklistMap.end())
285 return; // Not in the worklist.
286
287 // Null out the entry rather than erasing it to avoid a linear operation.
288 Worklist[It->second] = nullptr;
289 WorklistMap.erase(It);
290 }
291
292 void deleteAndRecombine(SDNode *N);
293 bool recursivelyDeleteUnusedNodes(SDNode *N);
294
295 /// Replaces all uses of the results of one DAG node with new values.
296 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
297 bool AddTo = true);
298
299 /// Replaces all uses of the results of one DAG node with new values.
300 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
301 return CombineTo(N, &Res, 1, AddTo);
302 }
303
304 /// Replaces all uses of the results of one DAG node with new values.
305 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
306 bool AddTo = true) {
307 SDValue To[] = { Res0, Res1 };
308 return CombineTo(N, To, 2, AddTo);
309 }
310
311 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
312
313 private:
314 unsigned MaximumLegalStoreInBits;
315
316 /// Check the specified integer node value to see if it can be simplified or
317 /// if things it uses can be simplified by bit propagation.
318 /// If so, return true.
319 bool SimplifyDemandedBits(SDValue Op) {
320 unsigned BitWidth = Op.getScalarValueSizeInBits();
321 APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
322 return SimplifyDemandedBits(Op, DemandedBits);
323 }
324
325 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
326 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
327 KnownBits Known;
328 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, Known, TLO, 0, false))
329 return false;
330
331 // Revisit the node.
332 AddToWorklist(Op.getNode());
333
334 CommitTargetLoweringOpt(TLO);
335 return true;
336 }
337
338 /// Check the specified vector node value to see if it can be simplified or
339 /// if things it uses can be simplified as it only uses some of the
340 /// elements. If so, return true.
341 bool SimplifyDemandedVectorElts(SDValue Op) {
342 // TODO: For now just pretend it cannot be simplified.
343 if (Op.getValueType().isScalableVector())
344 return false;
345
346 unsigned NumElts = Op.getValueType().getVectorNumElements();
347 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
348 return SimplifyDemandedVectorElts(Op, DemandedElts);
349 }
350
351 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
352 const APInt &DemandedElts,
353 bool AssumeSingleUse = false);
354 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
355 bool AssumeSingleUse = false);
356
357 bool CombineToPreIndexedLoadStore(SDNode *N);
358 bool CombineToPostIndexedLoadStore(SDNode *N);
359 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
360 bool SliceUpLoad(SDNode *N);
361
362 // Scalars have size 0 to distinguish from singleton vectors.
363 SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
364 bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
365 bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);
366
367 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
368 /// load.
369 ///
370 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
371 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
372 /// \param EltNo index of the vector element to load.
373 /// \param OriginalLoad load that EVE came from to be replaced.
374 /// \returns EVE on success SDValue() on failure.
375 SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
376 SDValue EltNo,
377 LoadSDNode *OriginalLoad);
378 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
379 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
380 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
381 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
382 SDValue PromoteIntBinOp(SDValue Op);
383 SDValue PromoteIntShiftOp(SDValue Op);
384 SDValue PromoteExtend(SDValue Op);
385 bool PromoteLoad(SDValue Op);
386
387 /// Call the node-specific routine that knows how to fold each
388 /// particular type of node. If that doesn't do anything, try the
389 /// target-specific DAG combines.
390 SDValue combine(SDNode *N);
391
392 // Visitation implementation - Implement dag node combining for different
393 // node types. The semantics are as follows:
394 // Return Value:
395 // SDValue.getNode() == 0 - No change was made
396 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
397 // otherwise - N should be replaced by the returned Operand.
398 //
399 SDValue visitTokenFactor(SDNode *N);
400 SDValue visitMERGE_VALUES(SDNode *N);
401 SDValue visitADD(SDNode *N);
402 SDValue visitADDLike(SDNode *N);
403 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
404 SDValue visitSUB(SDNode *N);
405 SDValue visitADDSAT(SDNode *N);
406 SDValue visitSUBSAT(SDNode *N);
407 SDValue visitADDC(SDNode *N);
408 SDValue visitADDO(SDNode *N);
409 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
410 SDValue visitSUBC(SDNode *N);
411 SDValue visitSUBO(SDNode *N);
412 SDValue visitADDE(SDNode *N);
413 SDValue visitADDCARRY(SDNode *N);
414 SDValue visitSADDO_CARRY(SDNode *N);
415 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
416 SDValue visitSUBE(SDNode *N);
417 SDValue visitSUBCARRY(SDNode *N);
418 SDValue visitSSUBO_CARRY(SDNode *N);
419 SDValue visitMUL(SDNode *N);
420 SDValue visitMULFIX(SDNode *N);
421 SDValue useDivRem(SDNode *N);
422 SDValue visitSDIV(SDNode *N);
423 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
424 SDValue visitUDIV(SDNode *N);
425 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
426 SDValue visitREM(SDNode *N);
427 SDValue visitMULHU(SDNode *N);
428 SDValue visitMULHS(SDNode *N);
429 SDValue visitSMUL_LOHI(SDNode *N);
430 SDValue visitUMUL_LOHI(SDNode *N);
431 SDValue visitMULO(SDNode *N);
432 SDValue visitIMINMAX(SDNode *N);
433 SDValue visitAND(SDNode *N);
434 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
435 SDValue visitOR(SDNode *N);
436 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
437 SDValue visitXOR(SDNode *N);
438 SDValue SimplifyVBinOp(SDNode *N);
439 SDValue visitSHL(SDNode *N);
440 SDValue visitSRA(SDNode *N);
441 SDValue visitSRL(SDNode *N);
442 SDValue visitFunnelShift(SDNode *N);
443 SDValue visitRotate(SDNode *N);
444 SDValue visitABS(SDNode *N);
445 SDValue visitBSWAP(SDNode *N);
446 SDValue visitBITREVERSE(SDNode *N);
447 SDValue visitCTLZ(SDNode *N);
448 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
449 SDValue visitCTTZ(SDNode *N);
450 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
451 SDValue visitCTPOP(SDNode *N);
452 SDValue visitSELECT(SDNode *N);
453 SDValue visitVSELECT(SDNode *N);
454 SDValue visitSELECT_CC(SDNode *N);
455 SDValue visitSETCC(SDNode *N);
456 SDValue visitSETCCCARRY(SDNode *N);
457 SDValue visitSIGN_EXTEND(SDNode *N);
458 SDValue visitZERO_EXTEND(SDNode *N);
459 SDValue visitANY_EXTEND(SDNode *N);
460 SDValue visitAssertExt(SDNode *N);
461 SDValue visitAssertAlign(SDNode *N);
462 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
463 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
464 SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
465 SDValue visitTRUNCATE(SDNode *N);
466 SDValue visitBITCAST(SDNode *N);
467 SDValue visitFREEZE(SDNode *N);
468 SDValue visitBUILD_PAIR(SDNode *N);
469 SDValue visitFADD(SDNode *N);
470 SDValue visitSTRICT_FADD(SDNode *N);
471 SDValue visitFSUB(SDNode *N);
472 SDValue visitFMUL(SDNode *N);
473 SDValue visitFMA(SDNode *N);
474 SDValue visitFDIV(SDNode *N);
475 SDValue visitFREM(SDNode *N);
476 SDValue visitFSQRT(SDNode *N);
477 SDValue visitFCOPYSIGN(SDNode *N);
478 SDValue visitFPOW(SDNode *N);
479 SDValue visitSINT_TO_FP(SDNode *N);
480 SDValue visitUINT_TO_FP(SDNode *N);
481 SDValue visitFP_TO_SINT(SDNode *N);
482 SDValue visitFP_TO_UINT(SDNode *N);
483 SDValue visitFP_ROUND(SDNode *N);
484 SDValue visitFP_EXTEND(SDNode *N);
485 SDValue visitFNEG(SDNode *N);
486 SDValue visitFABS(SDNode *N);
487 SDValue visitFCEIL(SDNode *N);
488 SDValue visitFTRUNC(SDNode *N);
489 SDValue visitFFLOOR(SDNode *N);
490 SDValue visitFMINNUM(SDNode *N);
491 SDValue visitFMAXNUM(SDNode *N);
492 SDValue visitFMINIMUM(SDNode *N);
493 SDValue visitFMAXIMUM(SDNode *N);
494 SDValue visitBRCOND(SDNode *N);
495 SDValue visitBR_CC(SDNode *N);
496 SDValue visitLOAD(SDNode *N);
497
498 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
499 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
500
501 SDValue visitSTORE(SDNode *N);
502 SDValue visitLIFETIME_END(SDNode *N);
503 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
504 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
505 SDValue visitBUILD_VECTOR(SDNode *N);
506 SDValue visitCONCAT_VECTORS(SDNode *N);
507 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
508 SDValue visitVECTOR_SHUFFLE(SDNode *N);
509 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
510 SDValue visitINSERT_SUBVECTOR(SDNode *N);
511 SDValue visitMLOAD(SDNode *N);
512 SDValue visitMSTORE(SDNode *N);
513 SDValue visitMGATHER(SDNode *N);
514 SDValue visitMSCATTER(SDNode *N);
515 SDValue visitFP_TO_FP16(SDNode *N);
516 SDValue visitFP16_TO_FP(SDNode *N);
517 SDValue visitVECREDUCE(SDNode *N);
518
519 SDValue visitFADDForFMACombine(SDNode *N);
520 SDValue visitFSUBForFMACombine(SDNode *N);
521 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
522
523 SDValue XformToShuffleWithZero(SDNode *N);
524 bool reassociationCanBreakAddressingModePattern(unsigned Opc,
525 const SDLoc &DL, SDValue N0,
526 SDValue N1);
527 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
528 SDValue N1);
529 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
530 SDValue N1, SDNodeFlags Flags);
531
532 SDValue visitShiftByConstant(SDNode *N);
533
534 SDValue foldSelectOfConstants(SDNode *N);
535 SDValue foldVSelectOfConstants(SDNode *N);
536 SDValue foldBinOpIntoSelect(SDNode *BO);
537 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
538 SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
539 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
540 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
541 SDValue N2, SDValue N3, ISD::CondCode CC,
542 bool NotExtCompare = false);
543 SDValue convertSelectOfFPConstantsToLoadOffset(
544 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
545 ISD::CondCode CC);
546 SDValue foldSignChangeInBitcast(SDNode *N);
547 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
548 SDValue N2, SDValue N3, ISD::CondCode CC);
549 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
550 const SDLoc &DL);
551 SDValue unfoldMaskedMerge(SDNode *N);
552 SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
553 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
554 const SDLoc &DL, bool foldBooleans);
555 SDValue rebuildSetCC(SDValue N);
556
557 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
558 SDValue &CC, bool MatchStrict = false) const;
559 bool isOneUseSetCC(SDValue N) const;
560
561 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
562 unsigned HiOp);
563 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
564 SDValue CombineExtLoad(SDNode *N);
565 SDValue CombineZExtLogicopShiftLoad(SDNode *N);
566 SDValue combineRepeatedFPDivisors(SDNode *N);
567 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
568 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
569 SDValue BuildSDIV(SDNode *N);
570 SDValue BuildSDIVPow2(SDNode *N);
571 SDValue BuildUDIV(SDNode *N);
572 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
573 SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags);
574 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
575 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
576 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
577 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
578 SDNodeFlags Flags, bool Reciprocal);
579 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
580 SDNodeFlags Flags, bool Reciprocal);
581 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
582 bool DemandHighBits = true);
583 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
584 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
585 SDValue InnerPos, SDValue InnerNeg,
586 unsigned PosOpcode, unsigned NegOpcode,
587 const SDLoc &DL);
588 SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
589 SDValue InnerPos, SDValue InnerNeg,
590 unsigned PosOpcode, unsigned NegOpcode,
591 const SDLoc &DL);
592 SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
593 SDValue MatchLoadCombine(SDNode *N);
594 SDValue mergeTruncStores(StoreSDNode *N);
595 SDValue ReduceLoadWidth(SDNode *N);
596 SDValue ReduceLoadOpStoreWidth(SDNode *N);
597 SDValue splitMergedValStore(StoreSDNode *ST);
598 SDValue TransformFPLoadStorePair(SDNode *N);
599 SDValue convertBuildVecZextToZext(SDNode *N);
600 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
601 SDValue reduceBuildVecTruncToBitCast(SDNode *N);
602 SDValue reduceBuildVecToShuffle(SDNode *N);
603 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
604 ArrayRef<int> VectorMask, SDValue VecIn1,
605 SDValue VecIn2, unsigned LeftIdx,
606 bool DidSplitVec);
607 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
608
609 /// Walk up chain skipping non-aliasing memory nodes,
610 /// looking for aliasing nodes and adding them to the Aliases vector.
611 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
612 SmallVectorImpl<SDValue> &Aliases);
613
614 /// Return true if there is any possibility that the two addresses overlap.
615 bool isAlias(SDNode *Op0, SDNode *Op1) const;
616
617 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
618 /// chain (aliasing node.)
619 SDValue FindBetterChain(SDNode *N, SDValue Chain);
620
621 /// Try to replace a store and any possibly adjacent stores on
622 /// consecutive chains with better chains. Return true only if St is
623 /// replaced.
624 ///
625 /// Notice that other chains may still be replaced even if the function
626 /// returns false.
627 bool findBetterNeighborChains(StoreSDNode *St);
628
629 // Helper for findBetterNeighborChains. Walk up store chain add additional
630 // chained stores that do not overlap and can be parallelized.
631 bool parallelizeChainedStores(StoreSDNode *St);
632
633 /// Holds a pointer to an LSBaseSDNode as well as information on where it
634 /// is located in a sequence of memory operations connected by a chain.
635 struct MemOpLink {
636 // Ptr to the mem node.
637 LSBaseSDNode *MemNode;
638
639 // Offset from the base ptr.
640 int64_t OffsetFromBase;
641
642 MemOpLink(LSBaseSDNode *N, int64_t Offset)
643 : MemNode(N), OffsetFromBase(Offset) {}
644 };
645
646 // Classify the origin of a stored value.
647 enum class StoreSource { Unknown, Constant, Extract, Load };
648 StoreSource getStoreSource(SDValue StoreVal) {
649 switch (StoreVal.getOpcode()) {
650 case ISD::Constant:
651 case ISD::ConstantFP:
652 return StoreSource::Constant;
653 case ISD::EXTRACT_VECTOR_ELT:
654 case ISD::EXTRACT_SUBVECTOR:
655 return StoreSource::Extract;
656 case ISD::LOAD:
657 return StoreSource::Load;
658 default:
659 return StoreSource::Unknown;
660 }
661 }
662
663 /// This is a helper function for visitMUL to check the profitability
664 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
665 /// MulNode is the original multiply, AddNode is (add x, c1),
666 /// and ConstNode is c2.
667 bool isMulAddWithConstProfitable(SDNode *MulNode,
668 SDValue &AddNode,
669 SDValue &ConstNode);
670
671 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
672 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
673 /// the type of the loaded value to be extended.
674 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
675 EVT LoadResultTy, EVT &ExtVT);
676
677 /// Helper function to calculate whether the given Load/Store can have its
678 /// width reduced to ExtVT.
679 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
680 EVT &MemVT, unsigned ShAmt = 0);
681
682 /// Used by BackwardsPropagateMask to find suitable loads.
683 bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
684 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
685 ConstantSDNode *Mask, SDNode *&NodeToMask);
686 /// Attempt to propagate a given AND node back to load leaves so that they
687 /// can be combined into narrow loads.
688 bool BackwardsPropagateMask(SDNode *N);
689
690 /// Helper function for mergeConsecutiveStores which merges the component
691 /// store chains.
692 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
693 unsigned NumStores);
694
695 /// This is a helper function for mergeConsecutiveStores. When the source
696 /// elements of the consecutive stores are all constants or all extracted
697 /// vector elements, try to merge them into one larger store introducing
698 /// bitcasts if necessary. \return True if a merged store was created.
699 bool mergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
700 EVT MemVT, unsigned NumStores,
701 bool IsConstantSrc, bool UseVector,
702 bool UseTrunc);
703
704 /// This is a helper function for mergeConsecutiveStores. Stores that
705 /// potentially may be merged with St are placed in StoreNodes. RootNode is
706 /// a chain predecessor to all store candidates.
707 void getStoreMergeCandidates(StoreSDNode *St,
708 SmallVectorImpl<MemOpLink> &StoreNodes,
709 SDNode *&Root);
710
711 /// Helper function for mergeConsecutiveStores. Checks if candidate stores
712 /// have indirect dependency through their operands. RootNode is the
713 /// predecessor to all stores calculated by getStoreMergeCandidates and is
714 /// used to prune the dependency check. \return True if safe to merge.
715 bool checkMergeStoreCandidatesForDependencies(
716 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
717 SDNode *RootNode);
718
719 /// This is a helper function for mergeConsecutiveStores. Given a list of
720 /// store candidates, find the first N that are consecutive in memory.
721 /// Returns 0 if there are not at least 2 consecutive stores to try merging.
722 unsigned getConsecutiveStores(SmallVectorImpl<MemOpLink> &StoreNodes,
723 int64_t ElementSizeBytes) const;
724
725 /// This is a helper function for mergeConsecutiveStores. It is used for
726 /// store chains that are composed entirely of constant values.
727 bool tryStoreMergeOfConstants(SmallVectorImpl<MemOpLink> &StoreNodes,
728 unsigned NumConsecutiveStores,
729 EVT MemVT, SDNode *Root, bool AllowVectors);
730
731 /// This is a helper function for mergeConsecutiveStores. It is used for
732 /// store chains that are composed entirely of extracted vector elements.
733 /// When extracting multiple vector elements, try to store them in one
734 /// vector store rather than a sequence of scalar stores.
735 bool tryStoreMergeOfExtracts(SmallVectorImpl<MemOpLink> &StoreNodes,
736 unsigned NumConsecutiveStores, EVT MemVT,
737 SDNode *Root);
738
739 /// This is a helper function for mergeConsecutiveStores. It is used for
740 /// store chains that are composed entirely of loaded values.
741 bool tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
742 unsigned NumConsecutiveStores, EVT MemVT,
743 SDNode *Root, bool AllowVectors,
744 bool IsNonTemporalStore, bool IsNonTemporalLoad);
745
746 /// Merge consecutive store operations into a wide store.
747 /// This optimization uses wide integers or vectors when possible.
748 /// \return true if stores were merged.
749 bool mergeConsecutiveStores(StoreSDNode *St);
750
751 /// Try to transform a truncation where C is a constant:
752 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
753 ///
754 /// \p N needs to be a truncation and its first operand an AND. Other
755 /// requirements are checked by the function (e.g. that trunc is
756 /// single-use) and if missed an empty SDValue is returned.
757 SDValue distributeTruncateThroughAnd(SDNode *N);
758
759 /// Helper function to determine whether the target supports operation
760 /// given by \p Opcode for type \p VT, that is, whether the operation
761 /// is legal or custom before legalizing operations, and whether is
762 /// legal (but not custom) after legalization.
763 bool hasOperation(unsigned Opcode, EVT VT) {
764 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations);
765 }
766
767 public:
768 /// Runs the dag combiner on all nodes in the work list
769 void Run(CombineLevel AtLevel);
770
771 SelectionDAG &getDAG() const { return DAG; }
772
773 /// Returns a type large enough to hold any valid shift amount - before type
774 /// legalization these can be huge.
775 EVT getShiftAmountTy(EVT LHSTy) {
776 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")((LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? static_cast<void> (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 776, __PRETTY_FUNCTION__))
;
777 return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
778 }
779
780 /// This method returns true if we are running before type legalization or
781 /// if the specified VT is legal.
782 bool isTypeLegal(const EVT &VT) {
783 if (!LegalTypes) return true;
784 return TLI.isTypeLegal(VT);
785 }
786
787 /// Convenience wrapper around TargetLowering::getSetCCResultType
788 EVT getSetCCResultType(EVT VT) const {
789 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
790 }
791
792 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
793 SDValue OrigLoad, SDValue ExtLoad,
794 ISD::NodeType ExtType);
795 };
796
797/// This class is a DAGUpdateListener that removes any deleted
798/// nodes from the worklist.
799class WorklistRemover : public SelectionDAG::DAGUpdateListener {
800 DAGCombiner &DC;
801
802public:
803 explicit WorklistRemover(DAGCombiner &dc)
804 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
805
806 void NodeDeleted(SDNode *N, SDNode *E) override {
807 DC.removeFromWorklist(N);
808 }
809};
810
811class WorklistInserter : public SelectionDAG::DAGUpdateListener {
812 DAGCombiner &DC;
813
814public:
815 explicit WorklistInserter(DAGCombiner &dc)
816 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
817
818 // FIXME: Ideally we could add N to the worklist, but this causes exponential
819 // compile time costs in large DAGs, e.g. Halide.
820 void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
821};
822
823} // end anonymous namespace
824
825//===----------------------------------------------------------------------===//
826// TargetLowering::DAGCombinerInfo implementation
827//===----------------------------------------------------------------------===//
828
829void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
830 ((DAGCombiner*)DC)->AddToWorklist(N);
831}
832
833SDValue TargetLowering::DAGCombinerInfo::
834CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
835 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
836}
837
838SDValue TargetLowering::DAGCombinerInfo::
839CombineTo(SDNode *N, SDValue Res, bool AddTo) {
840 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
841}
842
843SDValue TargetLowering::DAGCombinerInfo::
844CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
845 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
846}
847
848bool TargetLowering::DAGCombinerInfo::
849recursivelyDeleteUnusedNodes(SDNode *N) {
850 return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N);
851}
852
853void TargetLowering::DAGCombinerInfo::
854CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
855 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
856}
857
858//===----------------------------------------------------------------------===//
859// Helper Functions
860//===----------------------------------------------------------------------===//
861
862void DAGCombiner::deleteAndRecombine(SDNode *N) {
863 removeFromWorklist(N);
864
865 // If the operands of this node are only used by the node, they will now be
866 // dead. Make sure to re-visit them and recursively delete dead nodes.
867 for (const SDValue &Op : N->ops())
868 // For an operand generating multiple values, one of the values may
869 // become dead allowing further simplification (e.g. split index
870 // arithmetic from an indexed load).
871 if (Op->hasOneUse() || Op->getNumValues() > 1)
872 AddToWorklist(Op.getNode());
873
874 DAG.DeleteNode(N);
875}
876
877// APInts must be the same size for most operations, this helper
878// function zero extends the shorter of the pair so that they match.
879// We provide an Offset so that we can create bitwidths that won't overflow.
880static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
881 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
882 LHS = LHS.zextOrSelf(Bits);
883 RHS = RHS.zextOrSelf(Bits);
884}
885
886// Return true if this node is a setcc, or is a select_cc
887// that selects between the target values used for true and false, making it
888// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
889// the appropriate nodes based on the type of node we are checking. This
890// simplifies life a bit for the callers.
891bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
892 SDValue &CC, bool MatchStrict) const {
893 if (N.getOpcode() == ISD::SETCC) {
894 LHS = N.getOperand(0);
895 RHS = N.getOperand(1);
896 CC = N.getOperand(2);
897 return true;
898 }
899
900 if (MatchStrict &&
901 (N.getOpcode() == ISD::STRICT_FSETCC ||
902 N.getOpcode() == ISD::STRICT_FSETCCS)) {
903 LHS = N.getOperand(1);
904 RHS = N.getOperand(2);
905 CC = N.getOperand(3);
906 return true;
907 }
908
909 if (N.getOpcode() != ISD::SELECT_CC ||
910 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
911 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
912 return false;
913
914 if (TLI.getBooleanContents(N.getValueType()) ==
915 TargetLowering::UndefinedBooleanContent)
916 return false;
917
918 LHS = N.getOperand(0);
919 RHS = N.getOperand(1);
920 CC = N.getOperand(4);
921 return true;
922}
923
924/// Return true if this is a SetCC-equivalent operation with only one use.
925/// If this is true, it allows the users to invert the operation for free when
926/// it is profitable to do so.
927bool DAGCombiner::isOneUseSetCC(SDValue N) const {
928 SDValue N0, N1, N2;
929 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
930 return true;
931 return false;
932}
933
934// Returns the SDNode if it is a constant float BuildVector
935// or constant float.
936static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
937 if (isa<ConstantFPSDNode>(N))
938 return N.getNode();
939 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
940 return N.getNode();
941 return nullptr;
942}
943
944// Determines if it is a constant integer or a build vector of constant
945// integers (and undefs).
946// Do not permit build vector implicit truncation.
947static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
948 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
949 return !(Const->isOpaque() && NoOpaques);
950 if (N.getOpcode() != ISD::BUILD_VECTOR)
951 return false;
952 unsigned BitWidth = N.getScalarValueSizeInBits();
953 for (const SDValue &Op : N->op_values()) {
954 if (Op.isUndef())
955 continue;
956 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
957 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
958 (Const->isOpaque() && NoOpaques))
959 return false;
960 }
961 return true;
962}
963
964// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
965// undef's.
966static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
967 if (V.getOpcode() != ISD::BUILD_VECTOR)
968 return false;
969 return isConstantOrConstantVector(V, NoOpaques) ||
970 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
971}
972
973// Determine if this an indexed load with an opaque target constant index.
974static bool canSplitIdx(LoadSDNode *LD) {
975 return MaySplitLoadIndex &&
976 (LD->getOperand(2).getOpcode() != ISD::TargetConstant ||
977 !cast<ConstantSDNode>(LD->getOperand(2))->isOpaque());
978}
979
980bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
981 const SDLoc &DL,
982 SDValue N0,
983 SDValue N1) {
984 // Currently this only tries to ensure we don't undo the GEP splits done by
985 // CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this,
986 // we check if the following transformation would be problematic:
987 // (load/store (add, (add, x, offset1), offset2)) ->
988 // (load/store (add, x, offset1+offset2)).
989
990 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD)
991 return false;
992
993 if (N0.hasOneUse())
994 return false;
995
996 auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
997 auto *C2 = dyn_cast<ConstantSDNode>(N1);
998 if (!C1 || !C2)
999 return false;
1000
1001 const APInt &C1APIntVal = C1->getAPIntValue();
1002 const APInt &C2APIntVal = C2->getAPIntValue();
1003 if (C1APIntVal.getBitWidth() > 64 || C2APIntVal.getBitWidth() > 64)
1004 return false;
1005
1006 const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal;
1007 if (CombinedValueIntVal.getBitWidth() > 64)
1008 return false;
1009 const int64_t CombinedValue = CombinedValueIntVal.getSExtValue();
1010
1011 for (SDNode *Node : N0->uses()) {
1012 auto LoadStore = dyn_cast<MemSDNode>(Node);
1013 if (LoadStore) {
1014 // Is x[offset2] already not a legal addressing mode? If so then
1015 // reassociating the constants breaks nothing (we test offset2 because
1016 // that's the one we hope to fold into the load or store).
1017 TargetLoweringBase::AddrMode AM;
1018 AM.HasBaseReg = true;
1019 AM.BaseOffs = C2APIntVal.getSExtValue();
1020 EVT VT = LoadStore->getMemoryVT();
1021 unsigned AS = LoadStore->getAddressSpace();
1022 Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
1023 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1024 continue;
1025
1026 // Would x[offset1+offset2] still be a legal addressing mode?
1027 AM.BaseOffs = CombinedValue;
1028 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1029 return true;
1030 }
1031 }
1032
1033 return false;
1034}
1035
1036// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
1037// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
1038SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
1039 SDValue N0, SDValue N1) {
1040 EVT VT = N0.getValueType();
1041
1042 if (N0.getOpcode() != Opc)
1043 return SDValue();
1044
1045 if (DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
1046 if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
1047 // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
1048 if (SDValue OpNode =
1049 DAG.FoldConstantArithmetic(Opc, DL, VT, {N0.getOperand(1), N1}))
1050 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
1051 return SDValue();
1052 }
1053 if (N0.hasOneUse()) {
1054 // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
1055 // iff (op x, c1) has one use
1056 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
1057 if (!OpNode.getNode())
1058 return SDValue();
1059 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
1060 }
1061 }
1062 return SDValue();
1063}
1064
1065// Try to reassociate commutative binops.
1066SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1067 SDValue N1, SDNodeFlags Flags) {
1068 assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")((TLI.isCommutativeBinOp(Opc) && "Operation not commutative."
) ? static_cast<void> (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1068, __PRETTY_FUNCTION__))
;
1069
1070 // Floating-point reassociation is not allowed without loose FP math.
1071 if (N0.getValueType().isFloatingPoint() ||
1072 N1.getValueType().isFloatingPoint())
1073 if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
1074 return SDValue();
1075
1076 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
1077 return Combined;
1078 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
1079 return Combined;
1080 return SDValue();
1081}
1082
1083SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1084 bool AddTo) {
1085 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")((N->getNumValues() == NumTo && "Broken CombineTo call!"
) ? static_cast<void> (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1085, __PRETTY_FUNCTION__))
;
1086 ++NodesCombined;
1087 LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1088 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1089 dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
;
1090 for (unsigned i = 0, e = NumTo; i != e; ++i)
1091 assert((!To[i].getNode() ||(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1093, __PRETTY_FUNCTION__))
1092 N->getValueType(i) == To[i].getValueType()) &&(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1093, __PRETTY_FUNCTION__))
1093 "Cannot combine value to value of different type!")(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1093, __PRETTY_FUNCTION__))
;
1094
1095 WorklistRemover DeadNodes(*this);
1096 DAG.ReplaceAllUsesWith(N, To);
1097 if (AddTo) {
1098 // Push the new nodes and any users onto the worklist
1099 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1100 if (To[i].getNode()) {
1101 AddToWorklist(To[i].getNode());
1102 AddUsersToWorklist(To[i].getNode());
1103 }
1104 }
1105 }
1106
1107 // Finally, if the node is now dead, remove it from the graph. The node
1108 // may not be dead if the replacement process recursively simplified to
1109 // something else needing this node.
1110 if (N->use_empty())
1111 deleteAndRecombine(N);
1112 return SDValue(N, 0);
1113}
1114
1115void DAGCombiner::
1116CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1117 // Replace the old value with the new one.
1118 ++NodesCombined;
1119 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1120 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1121 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1122
1123 // Replace all uses. If any nodes become isomorphic to other nodes and
1124 // are deleted, make sure to remove them from our worklist.
1125 WorklistRemover DeadNodes(*this);
1126 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1127
1128 // Push the new node and any (possibly new) users onto the worklist.
1129 AddToWorklistWithUsers(TLO.New.getNode());
1130
1131 // Finally, if the node is now dead, remove it from the graph. The node
1132 // may not be dead if the replacement process recursively simplified to
1133 // something else needing this node.
1134 if (TLO.Old.getNode()->use_empty())
1135 deleteAndRecombine(TLO.Old.getNode());
1136}
1137
1138/// Check the specified integer node value to see if it can be simplified or if
1139/// things it uses can be simplified by bit propagation. If so, return true.
1140bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
1141 const APInt &DemandedElts,
1142 bool AssumeSingleUse) {
1143 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1144 KnownBits Known;
1145 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0,
1146 AssumeSingleUse))
1147 return false;
1148
1149 // Revisit the node.
1150 AddToWorklist(Op.getNode());
1151
1152 CommitTargetLoweringOpt(TLO);
1153 return true;
1154}
1155
1156/// Check the specified vector node value to see if it can be simplified or
1157/// if things it uses can be simplified as it only uses some of the elements.
1158/// If so, return true.
1159bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
1160 const APInt &DemandedElts,
1161 bool AssumeSingleUse) {
1162 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1163 APInt KnownUndef, KnownZero;
1164 if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
1165 TLO, 0, AssumeSingleUse))
1166 return false;
1167
1168 // Revisit the node.
1169 AddToWorklist(Op.getNode());
1170
1171 CommitTargetLoweringOpt(TLO);
1172 return true;
1173}
1174
1175void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1176 SDLoc DL(Load);
1177 EVT VT = Load->getValueType(0);
1178 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1179
1180 LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1181 Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1182 WorklistRemover DeadNodes(*this);
1183 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1184 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1185 deleteAndRecombine(Load);
1186 AddToWorklist(Trunc.getNode());
1187}
1188
1189SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1190 Replace = false;
1191 SDLoc DL(Op);
1192 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1193 LoadSDNode *LD = cast<LoadSDNode>(Op);
1194 EVT MemVT = LD->getMemoryVT();
1195 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1196 : LD->getExtensionType();
1197 Replace = true;
1198 return DAG.getExtLoad(ExtType, DL, PVT,
1199 LD->getChain(), LD->getBasePtr(),
1200 MemVT, LD->getMemOperand());
1201 }
1202
1203 unsigned Opc = Op.getOpcode();
1204 switch (Opc) {
1205 default: break;
1206 case ISD::AssertSext:
1207 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1208 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1209 break;
1210 case ISD::AssertZext:
1211 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1212 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1213 break;
1214 case ISD::Constant: {
1215 unsigned ExtOpc =
1216 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1217 return DAG.getNode(ExtOpc, DL, PVT, Op);
1218 }
1219 }
1220
1221 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1222 return SDValue();
1223 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1224}
1225
1226SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1227 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1228 return SDValue();
1229 EVT OldVT = Op.getValueType();
1230 SDLoc DL(Op);
1231 bool Replace = false;
1232 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1233 if (!NewOp.getNode())
1234 return SDValue();
1235 AddToWorklist(NewOp.getNode());
1236
1237 if (Replace)
1238 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1239 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1240 DAG.getValueType(OldVT));
1241}
1242
1243SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1244 EVT OldVT = Op.getValueType();
1245 SDLoc DL(Op);
1246 bool Replace = false;
1247 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1248 if (!NewOp.getNode())
1249 return SDValue();
1250 AddToWorklist(NewOp.getNode());
1251
1252 if (Replace)
1253 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1254 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1255}
1256
1257/// Promote the specified integer binary operation if the target indicates it is
1258/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1259/// i32 since i16 instructions are longer.
1260SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1261 if (!LegalOperations)
1262 return SDValue();
1263
1264 EVT VT = Op.getValueType();
1265 if (VT.isVector() || !VT.isInteger())
1266 return SDValue();
1267
1268 // If operation type is 'undesirable', e.g. i16 on x86, consider
1269 // promoting it.
1270 unsigned Opc = Op.getOpcode();
1271 if (TLI.isTypeDesirableForOp(Opc, VT))
1272 return SDValue();
1273
1274 EVT PVT = VT;
1275 // Consult target whether it is a good idea to promote this operation and
1276 // what's the right type to promote it to.
1277 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1278 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1278, __PRETTY_FUNCTION__))
;
1279
1280 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1281
1282 bool Replace0 = false;
1283 SDValue N0 = Op.getOperand(0);
1284 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1285
1286 bool Replace1 = false;
1287 SDValue N1 = Op.getOperand(1);
1288 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1289 SDLoc DL(Op);
1290
1291 SDValue RV =
1292 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1293
1294 // We are always replacing N0/N1's use in N and only need additional
1295 // replacements if there are additional uses.
1296 // Note: We are checking uses of the *nodes* (SDNode) rather than values
1297 // (SDValue) here because the node may reference multiple values
1298 // (for example, the chain value of a load node).
1299 Replace0 &= !N0->hasOneUse();
1300 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1301
1302 // Combine Op here so it is preserved past replacements.
1303 CombineTo(Op.getNode(), RV);
1304
1305 // If operands have a use ordering, make sure we deal with
1306 // predecessor first.
1307 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1308 std::swap(N0, N1);
1309 std::swap(NN0, NN1);
1310 }
1311
1312 if (Replace0) {
1313 AddToWorklist(NN0.getNode());
1314 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1315 }
1316 if (Replace1) {
1317 AddToWorklist(NN1.getNode());
1318 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1319 }
1320 return Op;
1321 }
1322 return SDValue();
1323}
1324
1325/// Promote the specified integer shift operation if the target indicates it is
1326/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1327/// i32 since i16 instructions are longer.
1328SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1329 if (!LegalOperations)
1330 return SDValue();
1331
1332 EVT VT = Op.getValueType();
1333 if (VT.isVector() || !VT.isInteger())
1334 return SDValue();
1335
1336 // If operation type is 'undesirable', e.g. i16 on x86, consider
1337 // promoting it.
1338 unsigned Opc = Op.getOpcode();
1339 if (TLI.isTypeDesirableForOp(Opc, VT))
1340 return SDValue();
1341
1342 EVT PVT = VT;
1343 // Consult target whether it is a good idea to promote this operation and
1344 // what's the right type to promote it to.
1345 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1346 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1346, __PRETTY_FUNCTION__))
;
1347
1348 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1349
1350 bool Replace = false;
1351 SDValue N0 = Op.getOperand(0);
1352 SDValue N1 = Op.getOperand(1);
1353 if (Opc == ISD::SRA)
1354 N0 = SExtPromoteOperand(N0, PVT);
1355 else if (Opc == ISD::SRL)
1356 N0 = ZExtPromoteOperand(N0, PVT);
1357 else
1358 N0 = PromoteOperand(N0, PVT, Replace);
1359
1360 if (!N0.getNode())
1361 return SDValue();
1362
1363 SDLoc DL(Op);
1364 SDValue RV =
1365 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1366
1367 if (Replace)
1368 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1369
1370 // Deal with Op being deleted.
1371 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1372 return RV;
1373 }
1374 return SDValue();
1375}
1376
1377SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1378 if (!LegalOperations)
1379 return SDValue();
1380
1381 EVT VT = Op.getValueType();
1382 if (VT.isVector() || !VT.isInteger())
1383 return SDValue();
1384
1385 // If operation type is 'undesirable', e.g. i16 on x86, consider
1386 // promoting it.
1387 unsigned Opc = Op.getOpcode();
1388 if (TLI.isTypeDesirableForOp(Opc, VT))
1389 return SDValue();
1390
1391 EVT PVT = VT;
1392 // Consult target whether it is a good idea to promote this operation and
1393 // what's the right type to promote it to.
1394 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1395 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1395, __PRETTY_FUNCTION__))
;
1396 // fold (aext (aext x)) -> (aext x)
1397 // fold (aext (zext x)) -> (zext x)
1398 // fold (aext (sext x)) -> (sext x)
1399 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1400 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1401 }
1402 return SDValue();
1403}
1404
1405bool DAGCombiner::PromoteLoad(SDValue Op) {
1406 if (!LegalOperations)
1407 return false;
1408
1409 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1410 return false;
1411
1412 EVT VT = Op.getValueType();
1413 if (VT.isVector() || !VT.isInteger())
1414 return false;
1415
1416 // If operation type is 'undesirable', e.g. i16 on x86, consider
1417 // promoting it.
1418 unsigned Opc = Op.getOpcode();
1419 if (TLI.isTypeDesirableForOp(Opc, VT))
1420 return false;
1421
1422 EVT PVT = VT;
1423 // Consult target whether it is a good idea to promote this operation and
1424 // what's the right type to promote it to.
1425 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1426 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1426, __PRETTY_FUNCTION__))
;
1427
1428 SDLoc DL(Op);
1429 SDNode *N = Op.getNode();
1430 LoadSDNode *LD = cast<LoadSDNode>(N);
1431 EVT MemVT = LD->getMemoryVT();
1432 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1433 : LD->getExtensionType();
1434 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1435 LD->getChain(), LD->getBasePtr(),
1436 MemVT, LD->getMemOperand());
1437 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1438
1439 LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1440 Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1441 WorklistRemover DeadNodes(*this);
1442 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1443 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1444 deleteAndRecombine(N);
1445 AddToWorklist(Result.getNode());
1446 return true;
1447 }
1448 return false;
1449}
1450
1451/// Recursively delete a node which has no uses and any operands for
1452/// which it is the only use.
1453///
1454/// Note that this both deletes the nodes and removes them from the worklist.
1455/// It also adds any nodes who have had a user deleted to the worklist as they
1456/// may now have only one use and subject to other combines.
1457bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1458 if (!N->use_empty())
1459 return false;
1460
1461 SmallSetVector<SDNode *, 16> Nodes;
1462 Nodes.insert(N);
1463 do {
1464 N = Nodes.pop_back_val();
1465 if (!N)
1466 continue;
1467
1468 if (N->use_empty()) {
1469 for (const SDValue &ChildN : N->op_values())
1470 Nodes.insert(ChildN.getNode());
1471
1472 removeFromWorklist(N);
1473 DAG.DeleteNode(N);
1474 } else {
1475 AddToWorklist(N);
1476 }
1477 } while (!Nodes.empty());
1478 return true;
1479}
1480
1481//===----------------------------------------------------------------------===//
1482// Main DAG Combiner implementation
1483//===----------------------------------------------------------------------===//
1484
1485void DAGCombiner::Run(CombineLevel AtLevel) {
1486 // set the instance variables, so that the various visit routines may use it.
1487 Level = AtLevel;
1488 LegalDAG = Level >= AfterLegalizeDAG;
1489 LegalOperations = Level >= AfterLegalizeVectorOps;
1490 LegalTypes = Level >= AfterLegalizeTypes;
1491
1492 WorklistInserter AddNodes(*this);
1493
1494 // Add all the dag nodes to the worklist.
1495 for (SDNode &Node : DAG.allnodes())
1496 AddToWorklist(&Node);
1497
1498 // Create a dummy node (which is not added to allnodes), that adds a reference
1499 // to the root node, preventing it from being deleted, and tracking any
1500 // changes of the root.
1501 HandleSDNode Dummy(DAG.getRoot());
1502
1503 // While we have a valid worklist entry node, try to combine it.
1504 while (SDNode *N = getNextWorklistEntry()) {
1505 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1506 // N is deleted from the DAG, since they too may now be dead or may have a
1507 // reduced number of uses, allowing other xforms.
1508 if (recursivelyDeleteUnusedNodes(N))
1509 continue;
1510
1511 WorklistRemover DeadNodes(*this);
1512
1513 // If this combine is running after legalizing the DAG, re-legalize any
1514 // nodes pulled off the worklist.
1515 if (LegalDAG) {
1516 SmallSetVector<SDNode *, 16> UpdatedNodes;
1517 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1518
1519 for (SDNode *LN : UpdatedNodes)
1520 AddToWorklistWithUsers(LN);
1521
1522 if (!NIsValid)
1523 continue;
1524 }
1525
1526 LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1527
1528 // Add any operands of the new node which have not yet been combined to the
1529 // worklist as well. Because the worklist uniques things already, this
1530 // won't repeatedly process the same operand.
1531 CombinedNodes.insert(N);
1532 for (const SDValue &ChildN : N->op_values())
1533 if (!CombinedNodes.count(ChildN.getNode()))
1534 AddToWorklist(ChildN.getNode());
1535
1536 SDValue RV = combine(N);
1537
1538 if (!RV.getNode())
1539 continue;
1540
1541 ++NodesCombined;
1542
1543 // If we get back the same node we passed in, rather than a new node or
1544 // zero, we know that the node must have defined multiple values and
1545 // CombineTo was used. Since CombineTo takes care of the worklist
1546 // mechanics for us, we have no work to do in this case.
1547 if (RV.getNode() == N)
1548 continue;
1549
1550 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1552, __PRETTY_FUNCTION__))
1551 RV.getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1552, __PRETTY_FUNCTION__))
1552 "Node was deleted but visit returned new node!")((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1552, __PRETTY_FUNCTION__))
;
1553
1554 LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1555
1556 if (N->getNumValues() == RV.getNode()->getNumValues())
1557 DAG.ReplaceAllUsesWith(N, RV.getNode());
1558 else {
1559 assert(N->getValueType(0) == RV.getValueType() &&((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1560, __PRETTY_FUNCTION__))
1560 N->getNumValues() == 1 && "Type mismatch")((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1560, __PRETTY_FUNCTION__))
;
1561 DAG.ReplaceAllUsesWith(N, &RV);
1562 }
1563
1564 // Push the new node and any users onto the worklist. Omit this if the
1565 // new node is the EntryToken (e.g. if a store managed to get optimized
1566 // out), because re-visiting the EntryToken and its users will not uncover
1567 // any additional opportunities, but there may be a large number of such
1568 // users, potentially causing compile time explosion.
1569 if (RV.getOpcode() != ISD::EntryToken) {
1570 AddToWorklist(RV.getNode());
1571 AddUsersToWorklist(RV.getNode());
1572 }
1573
1574 // Finally, if the node is now dead, remove it from the graph. The node
1575 // may not be dead if the replacement process recursively simplified to
1576 // something else needing this node. This will also take care of adding any
1577 // operands which have lost a user to the worklist.
1578 recursivelyDeleteUnusedNodes(N);
1579 }
1580
1581 // If the root changed (e.g. it was a dead load, update the root).
1582 DAG.setRoot(Dummy.getValue());
1583 DAG.RemoveDeadNodes();
1584}
1585
1586SDValue DAGCombiner::visit(SDNode *N) {
1587 switch (N->getOpcode()) {
1588 default: break;
1589 case ISD::TokenFactor: return visitTokenFactor(N);
1590 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1591 case ISD::ADD: return visitADD(N);
1592 case ISD::SUB: return visitSUB(N);
1593 case ISD::SADDSAT:
1594 case ISD::UADDSAT: return visitADDSAT(N);
1595 case ISD::SSUBSAT:
1596 case ISD::USUBSAT: return visitSUBSAT(N);
1597 case ISD::ADDC: return visitADDC(N);
1598 case ISD::SADDO:
1599 case ISD::UADDO: return visitADDO(N);
1600 case ISD::SUBC: return visitSUBC(N);
1601 case ISD::SSUBO:
1602 case ISD::USUBO: return visitSUBO(N);
1603 case ISD::ADDE: return visitADDE(N);
1604 case ISD::ADDCARRY: return visitADDCARRY(N);
1605 case ISD::SADDO_CARRY: return visitSADDO_CARRY(N);
1606 case ISD::SUBE: return visitSUBE(N);
1607 case ISD::SUBCARRY: return visitSUBCARRY(N);
1608 case ISD::SSUBO_CARRY: return visitSSUBO_CARRY(N);
1609 case ISD::SMULFIX:
1610 case ISD::SMULFIXSAT:
1611 case ISD::UMULFIX:
1612 case ISD::UMULFIXSAT: return visitMULFIX(N);
1613 case ISD::MUL: return visitMUL(N);
1614 case ISD::SDIV: return visitSDIV(N);
1615 case ISD::UDIV: return visitUDIV(N);
1616 case ISD::SREM:
1617 case ISD::UREM: return visitREM(N);
1618 case ISD::MULHU: return visitMULHU(N);
1619 case ISD::MULHS: return visitMULHS(N);
1620 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1621 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1622 case ISD::SMULO:
1623 case ISD::UMULO: return visitMULO(N);
1624 case ISD::SMIN:
1625 case ISD::SMAX:
1626 case ISD::UMIN:
1627 case ISD::UMAX: return visitIMINMAX(N);
1628 case ISD::AND: return visitAND(N);
1629 case ISD::OR: return visitOR(N);
1630 case ISD::XOR: return visitXOR(N);
1631 case ISD::SHL: return visitSHL(N);
1632 case ISD::SRA: return visitSRA(N);
1633 case ISD::SRL: return visitSRL(N);
1634 case ISD::ROTR:
1635 case ISD::ROTL: return visitRotate(N);
1636 case ISD::FSHL:
1637 case ISD::FSHR: return visitFunnelShift(N);
1638 case ISD::ABS: return visitABS(N);
1639 case ISD::BSWAP: return visitBSWAP(N);
1640 case ISD::BITREVERSE: return visitBITREVERSE(N);
1641 case ISD::CTLZ: return visitCTLZ(N);
1642 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1643 case ISD::CTTZ: return visitCTTZ(N);
1644 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1645 case ISD::CTPOP: return visitCTPOP(N);
1646 case ISD::SELECT: return visitSELECT(N);
1647 case ISD::VSELECT: return visitVSELECT(N);
1648 case ISD::SELECT_CC: return visitSELECT_CC(N);
1649 case ISD::SETCC: return visitSETCC(N);
1650 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1651 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1652 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1653 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1654 case ISD::AssertSext:
1655 case ISD::AssertZext: return visitAssertExt(N);
1656 case ISD::AssertAlign: return visitAssertAlign(N);
1657 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1658 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1659 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
1660 case ISD::TRUNCATE: return visitTRUNCATE(N);
1661 case ISD::BITCAST: return visitBITCAST(N);
1662 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1663 case ISD::FADD: return visitFADD(N);
1664 case ISD::STRICT_FADD: return visitSTRICT_FADD(N);
1665 case ISD::FSUB: return visitFSUB(N);
1666 case ISD::FMUL: return visitFMUL(N);
1667 case ISD::FMA: return visitFMA(N);
1668 case ISD::FDIV: return visitFDIV(N);
1669 case ISD::FREM: return visitFREM(N);
1670 case ISD::FSQRT: return visitFSQRT(N);
1671 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1672 case ISD::FPOW: return visitFPOW(N);
1673 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1674 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1675 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1676 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1677 case ISD::FP_ROUND: return visitFP_ROUND(N);
1678 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1679 case ISD::FNEG: return visitFNEG(N);
1680 case ISD::FABS: return visitFABS(N);
1681 case ISD::FFLOOR: return visitFFLOOR(N);
1682 case ISD::FMINNUM: return visitFMINNUM(N);
1683 case ISD::FMAXNUM: return visitFMAXNUM(N);
1684 case ISD::FMINIMUM: return visitFMINIMUM(N);
1685 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
1686 case ISD::FCEIL: return visitFCEIL(N);
1687 case ISD::FTRUNC: return visitFTRUNC(N);
1688 case ISD::BRCOND: return visitBRCOND(N);
1689 case ISD::BR_CC: return visitBR_CC(N);
1690 case ISD::LOAD: return visitLOAD(N);
1691 case ISD::STORE: return visitSTORE(N);
1692 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1693 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1694 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1695 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1696 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1697 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1698 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1699 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1700 case ISD::MGATHER: return visitMGATHER(N);
1701 case ISD::MLOAD: return visitMLOAD(N);
1702 case ISD::MSCATTER: return visitMSCATTER(N);
1703 case ISD::MSTORE: return visitMSTORE(N);
1704 case ISD::LIFETIME_END: return visitLIFETIME_END(N);
1705 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1706 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1707 case ISD::FREEZE: return visitFREEZE(N);
1708 case ISD::VECREDUCE_FADD:
1709 case ISD::VECREDUCE_FMUL:
1710 case ISD::VECREDUCE_ADD:
1711 case ISD::VECREDUCE_MUL:
1712 case ISD::VECREDUCE_AND:
1713 case ISD::VECREDUCE_OR:
1714 case ISD::VECREDUCE_XOR:
1715 case ISD::VECREDUCE_SMAX:
1716 case ISD::VECREDUCE_SMIN:
1717 case ISD::VECREDUCE_UMAX:
1718 case ISD::VECREDUCE_UMIN:
1719 case ISD::VECREDUCE_FMAX:
1720 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
1721 }
1722 return SDValue();
1723}
1724
1725SDValue DAGCombiner::combine(SDNode *N) {
1726 SDValue RV;
1727 if (!DisableGenericCombines)
1728 RV = visit(N);
1729
1730 // If nothing happened, try a target-specific DAG combine.
1731 if (!RV.getNode()) {
1732 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1733, __PRETTY_FUNCTION__))
1733 "Node was deleted but visit returned NULL!")((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1733, __PRETTY_FUNCTION__))
;
1734
1735 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1736 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1737
1738 // Expose the DAG combiner to the target combiner impls.
1739 TargetLowering::DAGCombinerInfo
1740 DagCombineInfo(DAG, Level, false, this);
1741
1742 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1743 }
1744 }
1745
1746 // If nothing happened still, try promoting the operation.
1747 if (!RV.getNode()) {
1748 switch (N->getOpcode()) {
1749 default: break;
1750 case ISD::ADD:
1751 case ISD::SUB:
1752 case ISD::MUL:
1753 case ISD::AND:
1754 case ISD::OR:
1755 case ISD::XOR:
1756 RV = PromoteIntBinOp(SDValue(N, 0));
1757 break;
1758 case ISD::SHL:
1759 case ISD::SRA:
1760 case ISD::SRL:
1761 RV = PromoteIntShiftOp(SDValue(N, 0));
1762 break;
1763 case ISD::SIGN_EXTEND:
1764 case ISD::ZERO_EXTEND:
1765 case ISD::ANY_EXTEND:
1766 RV = PromoteExtend(SDValue(N, 0));
1767 break;
1768 case ISD::LOAD:
1769 if (PromoteLoad(SDValue(N, 0)))
1770 RV = SDValue(N, 0);
1771 break;
1772 }
1773 }
1774
1775 // If N is a commutative binary node, try to eliminate it if the commuted
1776 // version is already present in the DAG.
1777 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1778 N->getNumValues() == 1) {
1779 SDValue N0 = N->getOperand(0);
1780 SDValue N1 = N->getOperand(1);
1781
1782 // Constant operands are canonicalized to RHS.
1783 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1784 SDValue Ops[] = {N1, N0};
1785 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1786 N->getFlags());
1787 if (CSENode)
1788 return SDValue(CSENode, 0);
1789 }
1790 }
1791
1792 return RV;
1793}
1794
1795/// Given a node, return its input chain if it has one, otherwise return a null
1796/// sd operand.
1797static SDValue getInputChainForNode(SDNode *N) {
1798 if (unsigned NumOps = N->getNumOperands()) {
1799 if (N->getOperand(0).getValueType() == MVT::Other)
1800 return N->getOperand(0);
1801 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1802 return N->getOperand(NumOps-1);
1803 for (unsigned i = 1; i < NumOps-1; ++i)
1804 if (N->getOperand(i).getValueType() == MVT::Other)
1805 return N->getOperand(i);
1806 }
1807 return SDValue();
1808}
1809
1810SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1811 // If N has two operands, where one has an input chain equal to the other,
1812 // the 'other' chain is redundant.
1813 if (N->getNumOperands() == 2) {
1814 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1815 return N->getOperand(0);
1816 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1817 return N->getOperand(1);
1818 }
1819
1820 // Don't simplify token factors if optnone.
1821 if (OptLevel == CodeGenOpt::None)
1822 return SDValue();
1823
1824 // Don't simplify the token factor if the node itself has too many operands.
1825 if (N->getNumOperands() > TokenFactorInlineLimit)
1826 return SDValue();
1827
1828 // If the sole user is a token factor, we should make sure we have a
1829 // chance to merge them together. This prevents TF chains from inhibiting
1830 // optimizations.
1831 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1832 AddToWorklist(*(N->use_begin()));
1833
1834 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1835 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1836 SmallPtrSet<SDNode*, 16> SeenOps;
1837 bool Changed = false; // If we should replace this token factor.
1838
1839 // Start out with this token factor.
1840 TFs.push_back(N);
1841
1842 // Iterate through token factors. The TFs grows when new token factors are
1843 // encountered.
1844 for (unsigned i = 0; i < TFs.size(); ++i) {
1845 // Limit number of nodes to inline, to avoid quadratic compile times.
1846 // We have to add the outstanding Token Factors to Ops, otherwise we might
1847 // drop Ops from the resulting Token Factors.
1848 if (Ops.size() > TokenFactorInlineLimit) {
1849 for (unsigned j = i; j < TFs.size(); j++)
1850 Ops.emplace_back(TFs[j], 0);
1851 // Drop unprocessed Token Factors from TFs, so we do not add them to the
1852 // combiner worklist later.
1853 TFs.resize(i);
1854 break;
1855 }
1856
1857 SDNode *TF = TFs[i];
1858 // Check each of the operands.
1859 for (const SDValue &Op : TF->op_values()) {
1860 switch (Op.getOpcode()) {
1861 case ISD::EntryToken:
1862 // Entry tokens don't need to be added to the list. They are
1863 // redundant.
1864 Changed = true;
1865 break;
1866
1867 case ISD::TokenFactor:
1868 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1869 // Queue up for processing.
1870 TFs.push_back(Op.getNode());
1871 Changed = true;
1872 break;
1873 }
1874 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1875
1876 default:
1877 // Only add if it isn't already in the list.
1878 if (SeenOps.insert(Op.getNode()).second)
1879 Ops.push_back(Op);
1880 else
1881 Changed = true;
1882 break;
1883 }
1884 }
1885 }
1886
1887 // Re-visit inlined Token Factors, to clean them up in case they have been
1888 // removed. Skip the first Token Factor, as this is the current node.
1889 for (unsigned i = 1, e = TFs.size(); i < e; i++)
1890 AddToWorklist(TFs[i]);
1891
1892 // Remove Nodes that are chained to another node in the list. Do so
1893 // by walking up chains breath-first stopping when we've seen
1894 // another operand. In general we must climb to the EntryNode, but we can exit
1895 // early if we find all remaining work is associated with just one operand as
1896 // no further pruning is possible.
1897
1898 // List of nodes to search through and original Ops from which they originate.
1899 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1900 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1901 SmallPtrSet<SDNode *, 16> SeenChains;
1902 bool DidPruneOps = false;
1903
1904 unsigned NumLeftToConsider = 0;
1905 for (const SDValue &Op : Ops) {
1906 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1907 OpWorkCount.push_back(1);
1908 }
1909
1910 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1911 // If this is an Op, we can remove the op from the list. Remark any
1912 // search associated with it as from the current OpNumber.
1913 if (SeenOps.count(Op) != 0) {
1914 Changed = true;
1915 DidPruneOps = true;
1916 unsigned OrigOpNumber = 0;
1917 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1918 OrigOpNumber++;
1919 assert((OrigOpNumber != Ops.size()) &&(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1920, __PRETTY_FUNCTION__))
1920 "expected to find TokenFactor Operand")(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1920, __PRETTY_FUNCTION__))
;
1921 // Re-mark worklist from OrigOpNumber to OpNumber
1922 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1923 if (Worklist[i].second == OrigOpNumber) {
1924 Worklist[i].second = OpNumber;
1925 }
1926 }
1927 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1928 OpWorkCount[OrigOpNumber] = 0;
1929 NumLeftToConsider--;
1930 }
1931 // Add if it's a new chain
1932 if (SeenChains.insert(Op).second) {
1933 OpWorkCount[OpNumber]++;
1934 Worklist.push_back(std::make_pair(Op, OpNumber));
1935 }
1936 };
1937
1938 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1939 // We need at least be consider at least 2 Ops to prune.
1940 if (NumLeftToConsider <= 1)
1941 break;
1942 auto CurNode = Worklist[i].first;
1943 auto CurOpNumber = Worklist[i].second;
1944 assert((OpWorkCount[CurOpNumber] > 0) &&(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1945, __PRETTY_FUNCTION__))
1945 "Node should not appear in worklist")(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1945, __PRETTY_FUNCTION__))
;
1946 switch (CurNode->getOpcode()) {
1947 case ISD::EntryToken:
1948 // Hitting EntryToken is the only way for the search to terminate without
1949 // hitting
1950 // another operand's search. Prevent us from marking this operand
1951 // considered.
1952 NumLeftToConsider++;
1953 break;
1954 case ISD::TokenFactor:
1955 for (const SDValue &Op : CurNode->op_values())
1956 AddToWorklist(i, Op.getNode(), CurOpNumber);
1957 break;
1958 case ISD::LIFETIME_START:
1959 case ISD::LIFETIME_END:
1960 case ISD::CopyFromReg:
1961 case ISD::CopyToReg:
1962 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1963 break;
1964 default:
1965 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1966 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1967 break;
1968 }
1969 OpWorkCount[CurOpNumber]--;
1970 if (OpWorkCount[CurOpNumber] == 0)
1971 NumLeftToConsider--;
1972 }
1973
1974 // If we've changed things around then replace token factor.
1975 if (Changed) {
1976 SDValue Result;
1977 if (Ops.empty()) {
1978 // The entry token is the only possible outcome.
1979 Result = DAG.getEntryNode();
1980 } else {
1981 if (DidPruneOps) {
1982 SmallVector<SDValue, 8> PrunedOps;
1983 //
1984 for (const SDValue &Op : Ops) {
1985 if (SeenChains.count(Op.getNode()) == 0)
1986 PrunedOps.push_back(Op);
1987 }
1988 Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
1989 } else {
1990 Result = DAG.getTokenFactor(SDLoc(N), Ops);
1991 }
1992 }
1993 return Result;
1994 }
1995 return SDValue();
1996}
1997
1998/// MERGE_VALUES can always be eliminated.
1999SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
2000 WorklistRemover DeadNodes(*this);
2001 // Replacing results may cause a different MERGE_VALUES to suddenly
2002 // be CSE'd with N, and carry its uses with it. Iterate until no
2003 // uses remain, to ensure that the node can be safely deleted.
2004 // First add the users of this node to the work list so that they
2005 // can be tried again once they have new operands.
2006 AddUsersToWorklist(N);
2007 do {
2008 // Do as a single replacement to avoid rewalking use lists.
2009 SmallVector<SDValue, 8> Ops;
2010 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
2011 Ops.push_back(N->getOperand(i));
2012 DAG.ReplaceAllUsesWith(N, Ops.data());
2013 } while (!N->use_empty());
2014 deleteAndRecombine(N);
2015 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2016}
2017
2018/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
2019/// ConstantSDNode pointer else nullptr.
2020static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
2021 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
2022 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
2023}
2024
2025/// Return true if 'Use' is a load or a store that uses N as its base pointer
2026/// and that N may be folded in the load / store addressing mode.
2027static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG,
2028 const TargetLowering &TLI) {
2029 EVT VT;
2030 unsigned AS;
2031
2032 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
2033 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
2034 return false;
2035 VT = LD->getMemoryVT();
2036 AS = LD->getAddressSpace();
2037 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
2038 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
2039 return false;
2040 VT = ST->getMemoryVT();
2041 AS = ST->getAddressSpace();
2042 } else if (MaskedLoadSDNode *LD = dyn_cast<MaskedLoadSDNode>(Use)) {
2043 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
2044 return false;
2045 VT = LD->getMemoryVT();
2046 AS = LD->getAddressSpace();
2047 } else if (MaskedStoreSDNode *ST = dyn_cast<MaskedStoreSDNode>(Use)) {
2048 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
2049 return false;
2050 VT = ST->getMemoryVT();
2051 AS = ST->getAddressSpace();
2052 } else
2053 return false;
2054
2055 TargetLowering::AddrMode AM;
2056 if (N->getOpcode() == ISD::ADD) {
2057 AM.HasBaseReg = true;
2058 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2059 if (Offset)
2060 // [reg +/- imm]
2061 AM.BaseOffs = Offset->getSExtValue();
2062 else
2063 // [reg +/- reg]
2064 AM.Scale = 1;
2065 } else if (N->getOpcode() == ISD::SUB) {
2066 AM.HasBaseReg = true;
2067 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2068 if (Offset)
2069 // [reg +/- imm]
2070 AM.BaseOffs = -Offset->getSExtValue();
2071 else
2072 // [reg +/- reg]
2073 AM.Scale = 1;
2074 } else
2075 return false;
2076
2077 return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM,
2078 VT.getTypeForEVT(*DAG.getContext()), AS);
2079}
2080
2081SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
2082 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2083, __PRETTY_FUNCTION__))
2083 "Unexpected binary operator")((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2083, __PRETTY_FUNCTION__))
;
2084
2085 // Don't do this unless the old select is going away. We want to eliminate the
2086 // binary operator, not replace a binop with a select.
2087 // TODO: Handle ISD::SELECT_CC.
2088 unsigned SelOpNo = 0;
2089 SDValue Sel = BO->getOperand(0);
2090 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
2091 SelOpNo = 1;
2092 Sel = BO->getOperand(1);
2093 }
2094
2095 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2096 return SDValue();
2097
2098 SDValue CT = Sel.getOperand(1);
2099 if (!isConstantOrConstantVector(CT, true) &&
2100 !isConstantFPBuildVectorOrConstantFP(CT))
2101 return SDValue();
2102
2103 SDValue CF = Sel.getOperand(2);
2104 if (!isConstantOrConstantVector(CF, true) &&
2105 !isConstantFPBuildVectorOrConstantFP(CF))
2106 return SDValue();
2107
2108 // Bail out if any constants are opaque because we can't constant fold those.
2109 // The exception is "and" and "or" with either 0 or -1 in which case we can
2110 // propagate non constant operands into select. I.e.:
2111 // and (select Cond, 0, -1), X --> select Cond, 0, X
2112 // or X, (select Cond, -1, 0) --> select Cond, -1, X
2113 auto BinOpcode = BO->getOpcode();
2114 bool CanFoldNonConst =
2115 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2116 (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
2117 (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));
2118
2119 SDValue CBO = BO->getOperand(SelOpNo ^ 1);
2120 if (!CanFoldNonConst &&
2121 !isConstantOrConstantVector(CBO, true) &&
2122 !isConstantFPBuildVectorOrConstantFP(CBO))
2123 return SDValue();
2124
2125 EVT VT = Sel.getValueType();
2126
2127 // In case of shift value and shift amount may have different VT. For instance
2128 // on x86 shift amount is i8 regardles of LHS type. Bail out if we have
2129 // swapped operands and value types do not match. NB: x86 is fine if operands
2130 // are not swapped with shift amount VT being not bigger than shifted value.
2131 // TODO: that is possible to check for a shift operation, correct VTs and
2132 // still perform optimization on x86 if needed.
2133 if (SelOpNo && VT != CBO.getValueType())
2134 return SDValue();
2135
2136 // We have a select-of-constants followed by a binary operator with a
2137 // constant. Eliminate the binop by pulling the constant math into the select.
2138 // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
2139 SDLoc DL(Sel);
2140 SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
2141 : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
2142 if (!CanFoldNonConst && !NewCT.isUndef() &&
2143 !isConstantOrConstantVector(NewCT, true) &&
2144 !isConstantFPBuildVectorOrConstantFP(NewCT))
2145 return SDValue();
2146
2147 SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
2148 : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
2149 if (!CanFoldNonConst && !NewCF.isUndef() &&
2150 !isConstantOrConstantVector(NewCF, true) &&
2151 !isConstantFPBuildVectorOrConstantFP(NewCF))
2152 return SDValue();
2153
2154 SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
2155 SelectOp->setFlags(BO->getFlags());
2156 return SelectOp;
2157}
2158
2159static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
2160 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2161, __PRETTY_FUNCTION__))
2161 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2161, __PRETTY_FUNCTION__))
;
2162
2163 // Match a constant operand and a zext operand for the math instruction:
2164 // add Z, C
2165 // sub C, Z
2166 bool IsAdd = N->getOpcode() == ISD::ADD;
2167 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2168 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2169 auto *CN = dyn_cast<ConstantSDNode>(C);
2170 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2171 return SDValue();
2172
2173 // Match the zext operand as a setcc of a boolean.
2174 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2175 Z.getOperand(0).getValueType() != MVT::i1)
2176 return SDValue();
2177
2178 // Match the compare as: setcc (X & 1), 0, eq.
2179 SDValue SetCC = Z.getOperand(0);
2180 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2181 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2182 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2183 !isOneConstant(SetCC.getOperand(0).getOperand(1)))
2184 return SDValue();
2185
2186 // We are adding/subtracting a constant and an inverted low bit. Turn that
2187 // into a subtract/add of the low bit with incremented/decremented constant:
2188 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2189 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
2190 EVT VT = C.getValueType();
2191 SDLoc DL(N);
2192 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
2193 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2194 DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
2195 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2196}
2197
2198/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2199/// a shift and add with a different constant.
2200static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
2201 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2202, __PRETTY_FUNCTION__))
2202 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2202, __PRETTY_FUNCTION__))
;
2203
2204 // We need a constant operand for the add/sub, and the other operand is a
2205 // logical shift right: add (srl), C or sub C, (srl).
2206 bool IsAdd = N->getOpcode() == ISD::ADD;
2207 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2208 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2209 if (!DAG.isConstantIntBuildVectorOrConstantInt(ConstantOp) ||
2210 ShiftOp.getOpcode() != ISD::SRL)
2211 return SDValue();
2212
2213 // The shift must be of a 'not' value.
2214 SDValue Not = ShiftOp.getOperand(0);
2215 if (!Not.hasOneUse() || !isBitwiseNot(Not))
2216 return SDValue();
2217
2218 // The shift must be moving the sign bit to the least-significant-bit.
2219 EVT VT = ShiftOp.getValueType();
2220 SDValue ShAmt = ShiftOp.getOperand(1);
2221 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2222 if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
2223 return SDValue();
2224
2225 // Eliminate the 'not' by adjusting the shift and add/sub constant:
2226 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2227 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2228 SDLoc DL(N);
2229 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2230 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
2231 if (SDValue NewC =
2232 DAG.FoldConstantArithmetic(IsAdd ? ISD::ADD : ISD::SUB, DL, VT,
2233 {ConstantOp, DAG.getConstant(1, DL, VT)}))
2234 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC);
2235 return SDValue();
2236}
2237
2238/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2239/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2240/// are no common bits set in the operands).
2241SDValue DAGCombiner::visitADDLike(SDNode *N) {
2242 SDValue N0 = N->getOperand(0);
2243 SDValue N1 = N->getOperand(1);
2244 EVT VT = N0.getValueType();
2245 SDLoc DL(N);
2246
2247 // fold vector ops
2248 if (VT.isVector()) {
2249 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2250 return FoldedVOp;
2251
2252 // fold (add x, 0) -> x, vector edition
2253 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2254 return N0;
2255 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2256 return N1;
2257 }
2258
2259 // fold (add x, undef) -> undef
2260 if (N0.isUndef())
2261 return N0;
2262
2263 if (N1.isUndef())
2264 return N1;
2265
2266 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2267 // canonicalize constant to RHS
2268 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2269 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2270 // fold (add c1, c2) -> c1+c2
2271 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1});
2272 }
2273
2274 // fold (add x, 0) -> x
2275 if (isNullConstant(N1))
2276 return N0;
2277
2278 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
2279 // fold ((A-c1)+c2) -> (A+(c2-c1))
2280 if (N0.getOpcode() == ISD::SUB &&
2281 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2282 SDValue Sub =
2283 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N0.getOperand(1)});
2284 assert(Sub && "Constant folding failed")((Sub && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Sub && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2284, __PRETTY_FUNCTION__))
;
2285 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2286 }
2287
2288 // fold ((c1-A)+c2) -> (c1+c2)-A
2289 if (N0.getOpcode() == ISD::SUB &&
2290 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
2291 SDValue Add =
2292 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N0.getOperand(0)});
2293 assert(Add && "Constant folding failed")((Add && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Add && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2293, __PRETTY_FUNCTION__))
;
2294 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2295 }
2296
2297 // add (sext i1 X), 1 -> zext (not i1 X)
2298 // We don't transform this pattern:
2299 // add (zext i1 X), -1 -> sext (not i1 X)
2300 // because most (?) targets generate better code for the zext form.
2301 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2302 isOneOrOneSplat(N1)) {
2303 SDValue X = N0.getOperand(0);
2304 if ((!LegalOperations ||
2305 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2306 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2307 X.getScalarValueSizeInBits() == 1) {
2308 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
2309 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2310 }
2311 }
2312
2313 // Fold (add (or x, c0), c1) -> (add x, (c0 + c1)) if (or x, c0) is
2314 // equivalent to (add x, c0).
2315 if (N0.getOpcode() == ISD::OR &&
2316 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true) &&
2317 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2318 if (SDValue Add0 = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT,
2319 {N1, N0.getOperand(1)}))
2320 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
2321 }
2322 }
2323
2324 if (SDValue NewSel = foldBinOpIntoSelect(N))
2325 return NewSel;
2326
2327 // reassociate add
2328 if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N0, N1)) {
2329 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2330 return RADD;
2331 }
2332 // fold ((0-A) + B) -> B-A
2333 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2334 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2335
2336 // fold (A + (0-B)) -> A-B
2337 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2338 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2339
2340 // fold (A+(B-A)) -> B
2341 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2342 return N1.getOperand(0);
2343
2344 // fold ((B-A)+A) -> B
2345 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2346 return N0.getOperand(0);
2347
2348 // fold ((A-B)+(C-A)) -> (C-B)
2349 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2350 N0.getOperand(0) == N1.getOperand(1))
2351 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2352 N0.getOperand(1));
2353
2354 // fold ((A-B)+(B-C)) -> (A-C)
2355 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2356 N0.getOperand(1) == N1.getOperand(0))
2357 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2358 N1.getOperand(1));
2359
2360 // fold (A+(B-(A+C))) to (B-C)
2361 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2362 N0 == N1.getOperand(1).getOperand(0))
2363 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2364 N1.getOperand(1).getOperand(1));
2365
2366 // fold (A+(B-(C+A))) to (B-C)
2367 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2368 N0 == N1.getOperand(1).getOperand(1))
2369 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2370 N1.getOperand(1).getOperand(0));
2371
2372 // fold (A+((B-A)+or-C)) to (B+or-C)
2373 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2374 N1.getOperand(0).getOpcode() == ISD::SUB &&
2375 N0 == N1.getOperand(0).getOperand(1))
2376 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2377 N1.getOperand(1));
2378
2379 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2380 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2381 SDValue N00 = N0.getOperand(0);
2382 SDValue N01 = N0.getOperand(1);
2383 SDValue N10 = N1.getOperand(0);
2384 SDValue N11 = N1.getOperand(1);
2385
2386 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2387 return DAG.getNode(ISD::SUB, DL, VT,
2388 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2389 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2390 }
2391
2392 // fold (add (umax X, C), -C) --> (usubsat X, C)
2393 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2394 auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
2395 return (!Max && !Op) ||
2396 (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
2397 };
2398 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2399 /*AllowUndefs*/ true))
2400 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2401 N0.getOperand(1));
2402 }
2403
2404 if (SimplifyDemandedBits(SDValue(N, 0)))
2405 return SDValue(N, 0);
2406
2407 if (isOneOrOneSplat(N1)) {
2408 // fold (add (xor a, -1), 1) -> (sub 0, a)
2409 if (isBitwiseNot(N0))
2410 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2411 N0.getOperand(0));
2412
2413 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2414 if (N0.getOpcode() == ISD::ADD ||
2415 N0.getOpcode() == ISD::UADDO ||
2416 N0.getOpcode() == ISD::SADDO) {
2417 SDValue A, Xor;
2418
2419 if (isBitwiseNot(N0.getOperand(0))) {
2420 A = N0.getOperand(1);
2421 Xor = N0.getOperand(0);
2422 } else if (isBitwiseNot(N0.getOperand(1))) {
2423 A = N0.getOperand(0);
2424 Xor = N0.getOperand(1);
2425 }
2426
2427 if (Xor)
2428 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2429 }
2430
2431 // Look for:
2432 // add (add x, y), 1
2433 // And if the target does not like this form then turn into:
2434 // sub y, (xor x, -1)
2435 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2436 N0.getOpcode() == ISD::ADD) {
2437 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2438 DAG.getAllOnesConstant(DL, VT));
2439 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2440 }
2441 }
2442
2443 // (x - y) + -1 -> add (xor y, -1), x
2444 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2445 isAllOnesOrAllOnesSplat(N1)) {
2446 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1);
2447 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
2448 }
2449
2450 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2451 return Combined;
2452
2453 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2454 return Combined;
2455
2456 return SDValue();
2457}
2458
2459SDValue DAGCombiner::visitADD(SDNode *N) {
2460 SDValue N0 = N->getOperand(0);
2461 SDValue N1 = N->getOperand(1);
2462 EVT VT = N0.getValueType();
2463 SDLoc DL(N);
2464
2465 if (SDValue Combined = visitADDLike(N))
2466 return Combined;
2467
2468 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2469 return V;
2470
2471 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2472 return V;
2473
2474 // fold (a+b) -> (a|b) iff a and b share no bits.
2475 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2476 DAG.haveNoCommonBitsSet(N0, N1))
2477 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2478
2479 // Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
2480 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
2481 APInt C0 = N0->getConstantOperandAPInt(0);
2482 APInt C1 = N1->getConstantOperandAPInt(0);
2483 return DAG.getVScale(DL, VT, C0 + C1);
2484 }
2485
2486 // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
2487 if ((N0.getOpcode() == ISD::ADD) &&
2488 (N0.getOperand(1).getOpcode() == ISD::VSCALE) &&
2489 (N1.getOpcode() == ISD::VSCALE)) {
2490 auto VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
2491 auto VS1 = N1->getConstantOperandAPInt(0);
2492 auto VS = DAG.getVScale(DL, VT, VS0 + VS1);
2493 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
2494 }
2495
2496 return SDValue();
2497}
2498
2499SDValue DAGCombiner::visitADDSAT(SDNode *N) {
2500 unsigned Opcode = N->getOpcode();
2501 SDValue N0 = N->getOperand(0);
2502 SDValue N1 = N->getOperand(1);
2503 EVT VT = N0.getValueType();
2504 SDLoc DL(N);
2505
2506 // fold vector ops
2507 if (VT.isVector()) {
2508 // TODO SimplifyVBinOp
2509
2510 // fold (add_sat x, 0) -> x, vector edition
2511 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2512 return N0;
2513 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2514 return N1;
2515 }
2516
2517 // fold (add_sat x, undef) -> -1
2518 if (N0.isUndef() || N1.isUndef())
2519 return DAG.getAllOnesConstant(DL, VT);
2520
2521 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2522 // canonicalize constant to RHS
2523 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2524 return DAG.getNode(Opcode, DL, VT, N1, N0);
2525 // fold (add_sat c1, c2) -> c3
2526 return DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1});
2527 }
2528
2529 // fold (add_sat x, 0) -> x
2530 if (isNullConstant(N1))
2531 return N0;
2532
2533 // If it cannot overflow, transform into an add.
2534 if (Opcode == ISD::UADDSAT)
2535 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2536 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
2537
2538 return SDValue();
2539}
2540
2541static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2542 bool Masked = false;
2543
2544 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2545 while (true) {
2546 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2547 V = V.getOperand(0);
2548 continue;
2549 }
2550
2551 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2552 Masked = true;
2553 V = V.getOperand(0);
2554 continue;
2555 }
2556
2557 break;
2558 }
2559
2560 // If this is not a carry, return.
2561 if (V.getResNo() != 1)
2562 return SDValue();
2563
2564 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2565 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2566 return SDValue();
2567
2568 EVT VT = V.getNode()->getValueType(0);
2569 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2570 return SDValue();
2571
2572 // If the result is masked, then no matter what kind of bool it is we can
2573 // return. If it isn't, then we need to make sure the bool type is either 0 or
2574 // 1 and not other values.
2575 if (Masked ||
2576 TLI.getBooleanContents(V.getValueType()) ==
2577 TargetLoweringBase::ZeroOrOneBooleanContent)
2578 return V;
2579
2580 return SDValue();
2581}
2582
2583/// Given the operands of an add/sub operation, see if the 2nd operand is a
2584/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2585/// the opcode and bypass the mask operation.
2586static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
2587 SelectionDAG &DAG, const SDLoc &DL) {
2588 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2589 return SDValue();
2590
2591 EVT VT = N0.getValueType();
2592 if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
2593 return SDValue();
2594
2595 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2596 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
2597 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2598}
2599
2600/// Helper for doing combines based on N0 and N1 being added to each other.
2601SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
2602 SDNode *LocReference) {
2603 EVT VT = N0.getValueType();
2604 SDLoc DL(LocReference);
2605
2606 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2607 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2608 isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
2609 return DAG.getNode(ISD::SUB, DL, VT, N0,
2610 DAG.getNode(ISD::SHL, DL, VT,
2611 N1.getOperand(0).getOperand(1),
2612 N1.getOperand(1)));
2613
2614 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
2615 return V;
2616
2617 // Look for:
2618 // add (add x, 1), y
2619 // And if the target does not like this form then turn into:
2620 // sub y, (xor x, -1)
2621 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2622 N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) {
2623 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2624 DAG.getAllOnesConstant(DL, VT));
2625 return DAG.getNode(ISD::SUB, DL, VT, N1, Not);
2626 }
2627
2628 // Hoist one-use subtraction by non-opaque constant:
2629 // (x - C) + y -> (x + y) - C
2630 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
2631 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2632 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
2633 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
2634 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2635 }
2636 // Hoist one-use subtraction from non-opaque constant:
2637 // (C - x) + y -> (y - x) + C
2638 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2639 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
2640 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2641 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
2642 }
2643
2644 // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
2645 // rather than 'add 0/-1' (the zext should get folded).
2646 // add (sext i1 Y), X --> sub X, (zext i1 Y)
2647 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2648 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
2649 TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
2650 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2651 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2652 }
2653
2654 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2655 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2656 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2657 if (TN->getVT() == MVT::i1) {
2658 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2659 DAG.getConstant(1, DL, VT));
2660 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2661 }
2662 }
2663
2664 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2665 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2666 N1.getResNo() == 0)
2667 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2668 N0, N1.getOperand(0), N1.getOperand(2));
2669
2670 // (add X, Carry) -> (addcarry X, 0, Carry)
2671 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2672 if (SDValue Carry = getAsCarry(TLI, N1))
2673 return DAG.getNode(ISD::ADDCARRY, DL,
2674 DAG.getVTList(VT, Carry.getValueType()), N0,
2675 DAG.getConstant(0, DL, VT), Carry);
2676
2677 return SDValue();
2678}
2679
2680SDValue DAGCombiner::visitADDC(SDNode *N) {
2681 SDValue N0 = N->getOperand(0);
2682 SDValue N1 = N->getOperand(1);
2683 EVT VT = N0.getValueType();
2684 SDLoc DL(N);
2685
2686 // If the flag result is dead, turn this into an ADD.
2687 if (!N->hasAnyUseOfValue(1))
2688 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2689 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2690
2691 // canonicalize constant to RHS.
2692 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2693 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2694 if (N0C && !N1C)
2695 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2696
2697 // fold (addc x, 0) -> x + no carry out
2698 if (isNullConstant(N1))
2699 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2700 DL, MVT::Glue));
2701
2702 // If it cannot overflow, transform into an add.
2703 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2704 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2705 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2706
2707 return SDValue();
2708}
2709
2710static SDValue flipBoolean(SDValue V, const SDLoc &DL,
2711 SelectionDAG &DAG, const TargetLowering &TLI) {
2712 EVT VT = V.getValueType();
2713
2714 SDValue Cst;
2715 switch (TLI.getBooleanContents(VT)) {
2716 case TargetLowering::ZeroOrOneBooleanContent:
2717 case TargetLowering::UndefinedBooleanContent:
2718 Cst = DAG.getConstant(1, DL, VT);
2719 break;
2720 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2721 Cst = DAG.getAllOnesConstant(DL, VT);
2722 break;
2723 }
2724
2725 return DAG.getNode(ISD::XOR, DL, VT, V, Cst);
2726}
2727
2728/**
2729 * Flips a boolean if it is cheaper to compute. If the Force parameters is set,
2730 * then the flip also occurs if computing the inverse is the same cost.
2731 * This function returns an empty SDValue in case it cannot flip the boolean
2732 * without increasing the cost of the computation. If you want to flip a boolean
2733 * no matter what, use flipBoolean.
2734 */
2735static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
2736 const TargetLowering &TLI,
2737 bool Force) {
2738 if (Force && isa<ConstantSDNode>(V))
2739 return flipBoolean(V, SDLoc(V), DAG, TLI);
2740
2741 if (V.getOpcode() != ISD::XOR)
2742 return SDValue();
2743
2744 ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
2745 if (!Const)
2746 return SDValue();
2747
2748 EVT VT = V.getValueType();
2749
2750 bool IsFlip = false;
2751 switch(TLI.getBooleanContents(VT)) {
2752 case TargetLowering::ZeroOrOneBooleanContent:
2753 IsFlip = Const->isOne();
2754 break;
2755 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2756 IsFlip = Const->isAllOnesValue();
2757 break;
2758 case TargetLowering::UndefinedBooleanContent:
2759 IsFlip = (Const->getAPIntValue() & 0x01) == 1;
2760 break;
2761 }
2762
2763 if (IsFlip)
2764 return V.getOperand(0);
2765 if (Force)
2766 return flipBoolean(V, SDLoc(V), DAG, TLI);
2767 return SDValue();
2768}
2769
2770SDValue DAGCombiner::visitADDO(SDNode *N) {
2771 SDValue N0 = N->getOperand(0);
2772 SDValue N1 = N->getOperand(1);
2773 EVT VT = N0.getValueType();
2774 bool IsSigned = (ISD::SADDO == N->getOpcode());
2775
2776 EVT CarryVT = N->getValueType(1);
2777 SDLoc DL(N);
2778
2779 // If the flag result is dead, turn this into an ADD.
2780 if (!N->hasAnyUseOfValue(1))
2781 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2782 DAG.getUNDEF(CarryVT));
2783
2784 // canonicalize constant to RHS.
2785 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2786 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2787 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2788
2789 // fold (addo x, 0) -> x + no carry out
2790 if (isNullOrNullSplat(N1))
2791 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2792
2793 if (!IsSigned) {
2794 // If it cannot overflow, transform into an add.
2795 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2796 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2797 DAG.getConstant(0, DL, CarryVT));
2798
2799 // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
2800 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
2801 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2802 DAG.getConstant(0, DL, VT), N0.getOperand(0));
2803 return CombineTo(N, Sub,
2804 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2805 }
2806
2807 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2808 return Combined;
2809
2810 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2811 return Combined;
2812 }
2813
2814 return SDValue();
2815}
2816
2817SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2818 EVT VT = N0.getValueType();
2819 if (VT.isVector())
2820 return SDValue();
2821
2822 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2823 // If Y + 1 cannot overflow.
2824 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2825 SDValue Y = N1.getOperand(0);
2826 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2827 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2828 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2829 N1.getOperand(2));
2830 }
2831
2832 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2833 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2834 if (SDValue Carry = getAsCarry(TLI, N1))
2835 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2836 DAG.getConstant(0, SDLoc(N), VT), Carry);
2837
2838 return SDValue();
2839}
2840
2841SDValue DAGCombiner::visitADDE(SDNode *N) {
2842 SDValue N0 = N->getOperand(0);
2843 SDValue N1 = N->getOperand(1);
2844 SDValue CarryIn = N->getOperand(2);
2845
2846 // canonicalize constant to RHS
2847 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2848 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2849 if (N0C && !N1C)
2850 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2851 N1, N0, CarryIn);
2852
2853 // fold (adde x, y, false) -> (addc x, y)
2854 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2855 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2856
2857 return SDValue();
2858}
2859
2860SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2861 SDValue N0 = N->getOperand(0);
2862 SDValue N1 = N->getOperand(1);
2863 SDValue CarryIn = N->getOperand(2);
2864 SDLoc DL(N);
2865
2866 // canonicalize constant to RHS
2867 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2868 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2869 if (N0C && !N1C)
2870 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2871
2872 // fold (addcarry x, y, false) -> (uaddo x, y)
2873 if (isNullConstant(CarryIn)) {
2874 if (!LegalOperations ||
2875 TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
2876 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2877 }
2878
2879 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2880 if (isNullConstant(N0) && isNullConstant(N1)) {
2881 EVT VT = N0.getValueType();
2882 EVT CarryVT = CarryIn.getValueType();
2883 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2884 AddToWorklist(CarryExt.getNode());
2885 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2886 DAG.getConstant(1, DL, VT)),
2887 DAG.getConstant(0, DL, CarryVT));
2888 }
2889
2890 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2891 return Combined;
2892
2893 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2894 return Combined;
2895
2896 return SDValue();
2897}
2898
2899SDValue DAGCombiner::visitSADDO_CARRY(SDNode *N) {
2900 SDValue N0 = N->getOperand(0);
2901 SDValue N1 = N->getOperand(1);
2902 SDValue CarryIn = N->getOperand(2);
2903 SDLoc DL(N);
2904
2905 // canonicalize constant to RHS
2906 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2907 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2908 if (N0C && !N1C)
2909 return DAG.getNode(ISD::SADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
2910
2911 // fold (saddo_carry x, y, false) -> (saddo x, y)
2912 if (isNullConstant(CarryIn)) {
2913 if (!LegalOperations ||
2914 TLI.isOperationLegalOrCustom(ISD::SADDO, N->getValueType(0)))
2915 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1);
2916 }
2917
2918 return SDValue();
2919}
2920
2921/**
2922 * If we are facing some sort of diamond carry propapagtion pattern try to
2923 * break it up to generate something like:
2924 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2925 *
2926 * The end result is usually an increase in operation required, but because the
2927 * carry is now linearized, other tranforms can kick in and optimize the DAG.
2928 *
2929 * Patterns typically look something like
2930 * (uaddo A, B)
2931 * / \
2932 * Carry Sum
2933 * | \
2934 * | (addcarry *, 0, Z)
2935 * | /
2936 * \ Carry
2937 * | /
2938 * (addcarry X, *, *)
2939 *
2940 * But numerous variation exist. Our goal is to identify A, B, X and Z and
2941 * produce a combine with a single path for carry propagation.
2942 */
2943static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
2944 SDValue X, SDValue Carry0, SDValue Carry1,
2945 SDNode *N) {
2946 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1)
2947 return SDValue();
2948 if (Carry1.getOpcode() != ISD::UADDO)
2949 return SDValue();
2950
2951 SDValue Z;
2952
2953 /**
2954 * First look for a suitable Z. It will present itself in the form of
2955 * (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
2956 */
2957 if (Carry0.getOpcode() == ISD::ADDCARRY &&
2958 isNullConstant(Carry0.getOperand(1))) {
2959 Z = Carry0.getOperand(2);
2960 } else if (Carry0.getOpcode() == ISD::UADDO &&
2961 isOneConstant(Carry0.getOperand(1))) {
2962 EVT VT = Combiner.getSetCCResultType(Carry0.getValueType());
2963 Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT);
2964 } else {
2965 // We couldn't find a suitable Z.
2966 return SDValue();
2967 }
2968
2969
2970 auto cancelDiamond = [&](SDValue A,SDValue B) {
2971 SDLoc DL(N);
2972 SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
2973 Combiner.AddToWorklist(NewY.getNode());
2974 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
2975 DAG.getConstant(0, DL, X.getValueType()),
2976 NewY.getValue(1));
2977 };
2978
2979 /**
2980 * (uaddo A, B)
2981 * |
2982 * Sum
2983 * |
2984 * (addcarry *, 0, Z)
2985 */
2986 if (Carry0.getOperand(0) == Carry1.getValue(0)) {
2987 return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1));
2988 }
2989
2990 /**
2991 * (addcarry A, 0, Z)
2992 * |
2993 * Sum
2994 * |
2995 * (uaddo *, B)
2996 */
2997 if (Carry1.getOperand(0) == Carry0.getValue(0)) {
2998 return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1));
2999 }
3000
3001 if (Carry1.getOperand(1) == Carry0.getValue(0)) {
3002 return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0));
3003 }
3004
3005 return SDValue();
3006}
3007
3008// If we are facing some sort of diamond carry/borrow in/out pattern try to
3009// match patterns like:
3010//
3011// (uaddo A, B) CarryIn
3012// | \ |
3013// | \ |
3014// PartialSum PartialCarryOutX /
3015// | | /
3016// | ____|____________/
3017// | / |
3018// (uaddo *, *) \________
3019// | \ \
3020// | \ |
3021// | PartialCarryOutY |
3022// | \ |
3023// | \ /
3024// AddCarrySum | ______/
3025// | /
3026// CarryOut = (or *, *)
3027//
3028// And generate ADDCARRY (or SUBCARRY) with two result values:
3029//
3030// {AddCarrySum, CarryOut} = (addcarry A, B, CarryIn)
3031//
3032// Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
3033// a single path for carry/borrow out propagation:
3034static SDValue combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
3035 const TargetLowering &TLI, SDValue Carry0,
3036 SDValue Carry1, SDNode *N) {
3037 if (Carry0.getResNo() != 1 || Carry1.getResNo() != 1)
3038 return SDValue();
3039 unsigned Opcode = Carry0.getOpcode();
3040 if (Opcode != Carry1.getOpcode())
3041 return SDValue();
3042 if (Opcode != ISD::UADDO && Opcode != ISD::USUBO)
3043 return SDValue();
3044
3045 // Canonicalize the add/sub of A and B as Carry0 and the add/sub of the
3046 // carry/borrow in as Carry1. (The top and middle uaddo nodes respectively in
3047 // the above ASCII art.)
3048 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
3049 Carry1.getOperand(1) != Carry0.getValue(0))
3050 std::swap(Carry0, Carry1);
3051 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
3052 Carry1.getOperand(1) != Carry0.getValue(0))
3053 return SDValue();
3054
3055 // The carry in value must be on the righthand side for subtraction.
3056 unsigned CarryInOperandNum =
3057 Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0;
3058 if (Opcode == ISD::USUBO && CarryInOperandNum != 1)
3059 return SDValue();
3060 SDValue CarryIn = Carry1.getOperand(CarryInOperandNum);
3061
3062 unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
3063 if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType()))
3064 return SDValue();
3065
3066 // Verify that the carry/borrow in is plausibly a carry/borrow bit.
3067 // TODO: make getAsCarry() aware of how partial carries are merged.
3068 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND)
3069 return SDValue();
3070 CarryIn = CarryIn.getOperand(0);
3071 if (CarryIn.getValueType() != MVT::i1)
3072 return SDValue();
3073
3074 SDLoc DL(N);
3075 SDValue Merged =
3076 DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0),
3077 Carry0.getOperand(1), CarryIn);
3078
3079 // Please note that because we have proven that the result of the UADDO/USUBO
3080 // of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can
3081 // therefore prove that if the first UADDO/USUBO overflows, the second
3082 // UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the
3083 // maximum value.
3084 //
3085 // 0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry
3086 // 0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow)
3087 //
3088 // This is important because it means that OR and XOR can be used to merge
3089 // carry flags; and that AND can return a constant zero.
3090 //
3091 // TODO: match other operations that can merge flags (ADD, etc)
3092 DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0));
3093 if (N->getOpcode() == ISD::AND)
3094 return DAG.getConstant(0, DL, MVT::i1);
3095 return Merged.getValue(1);
3096}
3097
3098SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
3099 SDNode *N) {
3100 // fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
3101 if (isBitwiseNot(N0))
3102 if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) {
3103 SDLoc DL(N);
3104 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
3105 N0.getOperand(0), NotC);
3106 return CombineTo(N, Sub,
3107 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
3108 }
3109
3110 // Iff the flag result is dead:
3111 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
3112 // Don't do this if the Carry comes from the uaddo. It won't remove the uaddo
3113 // or the dependency between the instructions.
3114 if ((N0.getOpcode() == ISD::ADD ||
3115 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
3116 N0.getValue(1) != CarryIn)) &&
3117 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
3118 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
3119 N0.getOperand(0), N0.getOperand(1), CarryIn);
3120
3121 /**
3122 * When one of the addcarry argument is itself a carry, we may be facing
3123 * a diamond carry propagation. In which case we try to transform the DAG
3124 * to ensure linear carry propagation if that is possible.
3125 */
3126 if (auto Y = getAsCarry(TLI, N1)) {
3127 // Because both are carries, Y and Z can be swapped.
3128 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
3129 return R;
3130 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
3131 return R;
3132 }
3133
3134 return SDValue();
3135}
3136
3137// Since it may not be valid to emit a fold to zero for vector initializers
3138// check if we can before folding.
3139static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
3140 SelectionDAG &DAG, bool LegalOperations) {
3141 if (!VT.isVector())
3142 return DAG.getConstant(0, DL, VT);
3143 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
3144 return DAG.getConstant(0, DL, VT);
3145 return SDValue();
3146}
3147
3148SDValue DAGCombiner::visitSUB(SDNode *N) {
3149 SDValue N0 = N->getOperand(0);
3150 SDValue N1 = N->getOperand(1);
3151 EVT VT = N0.getValueType();
3152 SDLoc DL(N);
3153
3154 // fold vector ops
3155 if (VT.isVector()) {
3156 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3157 return FoldedVOp;
3158
3159 // fold (sub x, 0) -> x, vector edition
3160 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3161 return N0;
3162 }
3163
3164 // fold (sub x, x) -> 0
3165 // FIXME: Refactor this and xor and other similar operations together.
3166 if (N0 == N1)
3167 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
3168
3169 // fold (sub c1, c2) -> c3
3170 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
3171 return C;
3172
3173 if (SDValue NewSel = foldBinOpIntoSelect(N))
3174 return NewSel;
3175
3176 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3177
3178 // fold (sub x, c) -> (add x, -c)
3179 if (N1C) {
3180 return DAG.getNode(ISD::ADD, DL, VT, N0,
3181 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3182 }
3183
3184 if (isNullOrNullSplat(N0)) {
3185 unsigned BitWidth = VT.getScalarSizeInBits();
3186 // Right-shifting everything out but the sign bit followed by negation is
3187 // the same as flipping arithmetic/logical shift type without the negation:
3188 // -(X >>u 31) -> (X >>s 31)
3189 // -(X >>s 31) -> (X >>u 31)
3190 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3191 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
3192 if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) {
3193 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3194 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
3195 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
3196 }
3197 }
3198
3199 // 0 - X --> 0 if the sub is NUW.
3200 if (N->getFlags().hasNoUnsignedWrap())
3201 return N0;
3202
3203 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
3204 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
3205 // N1 must be 0 because negating the minimum signed value is undefined.
3206 if (N->getFlags().hasNoSignedWrap())
3207 return N0;
3208
3209 // 0 - X --> X if X is 0 or the minimum signed value.
3210 return N1;
3211 }
3212
3213 // Convert 0 - abs(x) -> Y = sra (X, size(X)-1); sub (Y, xor (X, Y)).
3214 if (N1->getOpcode() == ISD::ABS &&
3215 !TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3216 SDValue X = N1->getOperand(0);
3217 SDValue Shift =
3218 DAG.getNode(ISD::SRA, DL, VT, X,
3219 DAG.getConstant(BitWidth - 1, DL, getShiftAmountTy(VT)));
3220 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, X, Shift);
3221 AddToWorklist(Shift.getNode());
3222 AddToWorklist(Xor.getNode());
3223 return DAG.getNode(ISD::SUB, DL, VT, Shift, Xor);
3224 }
3225 }
3226
3227 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
3228 if (isAllOnesOrAllOnesSplat(N0))
3229 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
3230
3231 // fold (A - (0-B)) -> A+B
3232 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
3233 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
3234
3235 // fold A-(A-B) -> B
3236 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3237 return N1.getOperand(1);
3238
3239 // fold (A+B)-A -> B
3240 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3241 return N0.getOperand(1);
3242
3243 // fold (A+B)-B -> A
3244 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
3245 return N0.getOperand(0);
3246
3247 // fold (A+C1)-C2 -> A+(C1-C2)
3248 if (N0.getOpcode() == ISD::ADD &&
3249 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3250 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3251 SDValue NewC =
3252 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(1), N1});
3253 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3253, __PRETTY_FUNCTION__))
;
3254 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
3255 }
3256
3257 // fold C2-(A+C1) -> (C2-C1)-A
3258 if (N1.getOpcode() == ISD::ADD) {
3259 SDValue N11 = N1.getOperand(1);
3260 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
3261 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
3262 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11});
3263 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3263, __PRETTY_FUNCTION__))
;
3264 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
3265 }
3266 }
3267
3268 // fold (A-C1)-C2 -> A-(C1+C2)
3269 if (N0.getOpcode() == ISD::SUB &&
3270 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3271 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3272 SDValue NewC =
3273 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0.getOperand(1), N1});
3274 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3274, __PRETTY_FUNCTION__))
;
3275 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
3276 }
3277
3278 // fold (c1-A)-c2 -> (c1-c2)-A
3279 if (N0.getOpcode() == ISD::SUB &&
3280 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3281 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaques */ true)) {
3282 SDValue NewC =
3283 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(0), N1});
3284 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3284, __PRETTY_FUNCTION__))
;
3285 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
3286 }
3287
3288 // fold ((A+(B+or-C))-B) -> A+or-C
3289 if (N0.getOpcode() == ISD::ADD &&
3290 (N0.getOperand(1).getOpcode() == ISD::SUB ||
3291 N0.getOperand(1).getOpcode() == ISD::ADD) &&
3292 N0.getOperand(1).getOperand(0) == N1)
3293 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
3294 N0.getOperand(1).getOperand(1));
3295
3296 // fold ((A+(C+B))-B) -> A+C
3297 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
3298 N0.getOperand(1).getOperand(1) == N1)
3299 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
3300 N0.getOperand(1).getOperand(0));
3301
3302 // fold ((A-(B-C))-C) -> A-B
3303 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
3304 N0.getOperand(1).getOperand(1) == N1)
3305 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
3306 N0.getOperand(1).getOperand(0));
3307
3308 // fold (A-(B-C)) -> A+(C-B)
3309 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
3310 return DAG.getNode(ISD::ADD, DL, VT, N0,
3311 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
3312 N1.getOperand(0)));
3313
3314 // A - (A & B) -> A & (~B)
3315 if (N1.getOpcode() == ISD::AND) {
3316 SDValue A = N1.getOperand(0);
3317 SDValue B = N1.getOperand(1);
3318 if (A != N0)
3319 std::swap(A, B);
3320 if (A == N0 &&
3321 (N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) {
3322 SDValue InvB =
3323 DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT));
3324 return DAG.getNode(ISD::AND, DL, VT, A, InvB);
3325 }
3326 }
3327
3328 // fold (X - (-Y * Z)) -> (X + (Y * Z))
3329 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
3330 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
3331 isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
3332 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3333 N1.getOperand(0).getOperand(1),
3334 N1.getOperand(1));
3335 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3336 }
3337 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
3338 isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
3339 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3340 N1.getOperand(0),
3341 N1.getOperand(1).getOperand(1));
3342 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3343 }
3344 }
3345
3346 // If either operand of a sub is undef, the result is undef
3347 if (N0.isUndef())
3348 return N0;
3349 if (N1.isUndef())
3350 return N1;
3351
3352 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
3353 return V;
3354
3355 if (SDValue V = foldAddSubOfSignBit(N, DAG))
3356 return V;
3357
3358 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
3359 return V;
3360
3361 // (x - y) - 1 -> add (xor y, -1), x
3362 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3363 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
3364 DAG.getAllOnesConstant(DL, VT));
3365 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
3366 }
3367
3368 // Look for:
3369 // sub y, (xor x, -1)
3370 // And if the target does not like this form then turn into:
3371 // add (add x, y), 1
3372 if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) {
3373 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
3374 return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
3375 }
3376
3377 // Hoist one-use addition by non-opaque constant:
3378 // (x + C) - y -> (x - y) + C
3379 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
3380 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3381 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3382 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
3383 }
3384 // y - (x + C) -> (y - x) - C
3385 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
3386 isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) {
3387 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3388 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3389 }
3390 // (x - C) - y -> (x - y) - C
3391 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
3392 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3393 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3394 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3395 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3396 }
3397 // (C - x) - y -> C - (x + y)
3398 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3399 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3400 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
3401 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3402 }
3403
3404 // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
3405 // rather than 'sub 0/1' (the sext should get folded).
3406 // sub X, (zext i1 Y) --> add X, (sext i1 Y)
3407 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
3408 N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
3409 TLI.getBooleanContents(VT) ==
3410 TargetLowering::ZeroOrNegativeOneBooleanContent) {
3411 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3412 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
3413 }
3414
3415 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
3416 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3417 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3418 SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
3419 SDValue S0 = N1.getOperand(0);
3420 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3421 unsigned OpSizeInBits = VT.getScalarSizeInBits();
3422 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
3423 if (C->getAPIntValue() == (OpSizeInBits - 1))
3424 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
3425 }
3426 }
3427 }
3428
3429 // If the relocation model supports it, consider symbol offsets.
3430 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
3431 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
3432 // fold (sub Sym, c) -> Sym-c
3433 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
3434 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
3435 GA->getOffset() -
3436 (uint64_t)N1C->getSExtValue());
3437 // fold (sub Sym+c1, Sym+c2) -> c1-c2
3438 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
3439 if (GA->getGlobal() == GB->getGlobal())
3440 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
3441 DL, VT);
3442 }
3443
3444 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
3445 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3446 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
3447 if (TN->getVT() == MVT::i1) {
3448 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3449 DAG.getConstant(1, DL, VT));
3450 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
3451 }
3452 }
3453
3454 // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
3455 if (N1.getOpcode() == ISD::VSCALE) {
3456 APInt IntVal = N1.getConstantOperandAPInt(0);
3457 return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
3458 }
3459
3460 // Prefer an add for more folding potential and possibly better codegen:
3461 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
3462 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3463 SDValue ShAmt = N1.getOperand(1);
3464 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
3465 if (ShAmtC &&
3466 ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) {
3467 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3468 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
3469 }
3470 }
3471
3472 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
3473 // (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry)
3474 if (SDValue Carry = getAsCarry(TLI, N0)) {
3475 SDValue X = N1;
3476 SDValue Zero = DAG.getConstant(0, DL, VT);
3477 SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
3478 return DAG.getNode(ISD::ADDCARRY, DL,
3479 DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,
3480 Carry);
3481 }
3482 }
3483
3484 return SDValue();
3485}
3486
3487SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
3488 SDValue N0 = N->getOperand(0);
3489 SDValue N1 = N->getOperand(1);
3490 EVT VT = N0.getValueType();
3491 SDLoc DL(N);
3492
3493 // fold vector ops
3494 if (VT.isVector()) {
3495 // TODO SimplifyVBinOp
3496
3497 // fold (sub_sat x, 0) -> x, vector edition
3498 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3499 return N0;
3500 }
3501
3502 // fold (sub_sat x, undef) -> 0
3503 if (N0.isUndef() || N1.isUndef())
3504 return DAG.getConstant(0, DL, VT);
3505
3506 // fold (sub_sat x, x) -> 0
3507 if (N0 == N1)
3508 return DAG.getConstant(0, DL, VT);
3509
3510 // fold (sub_sat c1, c2) -> c3
3511 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
3512 return C;
3513
3514 // fold (sub_sat x, 0) -> x
3515 if (isNullConstant(N1))
3516 return N0;
3517
3518 return SDValue();
3519}
3520
3521SDValue DAGCombiner::visitSUBC(SDNode *N) {
3522 SDValue N0 = N->getOperand(0);
3523 SDValue N1 = N->getOperand(1);
3524 EVT VT = N0.getValueType();
3525 SDLoc DL(N);
3526
3527 // If the flag result is dead, turn this into an SUB.
3528 if (!N->hasAnyUseOfValue(1))
3529 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3530 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3531
3532 // fold (subc x, x) -> 0 + no borrow
3533 if (N0 == N1)
3534 return CombineTo(N, DAG.getConstant(0, DL, VT),
3535 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3536
3537 // fold (subc x, 0) -> x + no borrow
3538 if (isNullConstant(N1))
3539 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3540
3541 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3542 if (isAllOnesConstant(N0))
3543 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3544 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3545
3546 return SDValue();
3547}
3548
3549SDValue DAGCombiner::visitSUBO(SDNode *N) {
3550 SDValue N0 = N->getOperand(0);
3551 SDValue N1 = N->getOperand(1);
3552 EVT VT = N0.getValueType();
3553 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3554
3555 EVT CarryVT = N->getValueType(1);
3556 SDLoc DL(N);
3557
3558 // If the flag result is dead, turn this into an SUB.
3559 if (!N->hasAnyUseOfValue(1))
3560 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3561 DAG.getUNDEF(CarryVT));
3562
3563 // fold (subo x, x) -> 0 + no borrow
3564 if (N0 == N1)
3565 return CombineTo(N, DAG.getConstant(0, DL, VT),
3566 DAG.getConstant(0, DL, CarryVT));
3567
3568 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3569
3570 // fold (subox, c) -> (addo x, -c)
3571 if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
3572 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3573 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3574 }
3575
3576 // fold (subo x, 0) -> x + no borrow
3577 if (isNullOrNullSplat(N1))
3578 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3579
3580 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3581 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
3582 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3583 DAG.getConstant(0, DL, CarryVT));
3584
3585 return SDValue();
3586}
3587
3588SDValue DAGCombiner::visitSUBE(SDNode *N) {
3589 SDValue N0 = N->getOperand(0);
3590 SDValue N1 = N->getOperand(1);
3591 SDValue CarryIn = N->getOperand(2);
3592
3593 // fold (sube x, y, false) -> (subc x, y)
3594 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3595 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3596
3597 return SDValue();
3598}
3599
3600SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
3601 SDValue N0 = N->getOperand(0);
3602 SDValue N1 = N->getOperand(1);
3603 SDValue CarryIn = N->getOperand(2);
3604
3605 // fold (subcarry x, y, false) -> (usubo x, y)
3606 if (isNullConstant(CarryIn)) {
3607 if (!LegalOperations ||
3608 TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
3609 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3610 }
3611
3612 return SDValue();
3613}
3614
3615SDValue DAGCombiner::visitSSUBO_CARRY(SDNode *N) {
3616 SDValue N0 = N->getOperand(0);
3617 SDValue N1 = N->getOperand(1);
3618 SDValue CarryIn = N->getOperand(2);
3619
3620 // fold (ssubo_carry x, y, false) -> (ssubo x, y)
3621 if (isNullConstant(CarryIn)) {
3622 if (!LegalOperations ||
3623 TLI.isOperationLegalOrCustom(ISD::SSUBO, N->getValueType(0)))
3624 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1);
3625 }
3626
3627 return SDValue();
3628}
3629
3630// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and
3631// UMULFIXSAT here.
3632SDValue DAGCombiner::visitMULFIX(SDNode *N) {
3633 SDValue N0 = N->getOperand(0);
3634 SDValue N1 = N->getOperand(1);
3635 SDValue Scale = N->getOperand(2);
3636 EVT VT = N0.getValueType();
3637
3638 // fold (mulfix x, undef, scale) -> 0
3639 if (N0.isUndef() || N1.isUndef())
3640 return DAG.getConstant(0, SDLoc(N), VT);
3641
3642 // Canonicalize constant to RHS (vector doesn't have to splat)
3643 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3644 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3645 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
3646
3647 // fold (mulfix x, 0, scale) -> 0
3648 if (isNullConstant(N1))
3649 return DAG.getConstant(0, SDLoc(N), VT);
3650
3651 return SDValue();
3652}
3653
3654SDValue DAGCombiner::visitMUL(SDNode *N) {
3655 SDValue N0 = N->getOperand(0);
3656 SDValue N1 = N->getOperand(1);
3657 EVT VT = N0.getValueType();
3658
3659 // fold (mul x, undef) -> 0
3660 if (N0.isUndef() || N1.isUndef())
3661 return DAG.getConstant(0, SDLoc(N), VT);
3662
3663 bool N1IsConst = false;
3664 bool N1IsOpaqueConst = false;
3665 APInt ConstValue1;
3666
3667 // fold vector ops
3668 if (VT.isVector()) {
3669 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3670 return FoldedVOp;
3671
3672 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
3673 assert((!N1IsConst ||(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3675, __PRETTY_FUNCTION__))
3674 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3675, __PRETTY_FUNCTION__))
3675 "Splat APInt should be element width")(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3675, __PRETTY_FUNCTION__))
;
3676 } else {
3677 N1IsConst = isa<ConstantSDNode>(N1);
3678 if (N1IsConst) {
3679 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
3680 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
3681 }
3682 }
3683
3684 // fold (mul c1, c2) -> c1*c2
3685 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT, {N0, N1}))
3686 return C;
3687
3688 // canonicalize constant to RHS (vector doesn't have to splat)
3689 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3690 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3691 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3692
3693 // fold (mul x, 0) -> 0
3694 if (N1IsConst && ConstValue1.isNullValue())
3695 return N1;
3696
3697 // fold (mul x, 1) -> x
3698 if (N1IsConst && ConstValue1.isOneValue())
3699 return N0;
3700
3701 if (SDValue NewSel = foldBinOpIntoSelect(N))
3702 return NewSel;
3703
3704 // fold (mul x, -1) -> 0-x
3705 if (N1IsConst && ConstValue1.isAllOnesValue()) {
3706 SDLoc DL(N);
3707 return DAG.getNode(ISD::SUB, DL, VT,
3708 DAG.getConstant(0, DL, VT), N0);
3709 }
3710
3711 // fold (mul x, (1 << c)) -> x << c
3712 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3713 DAG.isKnownToBeAPowerOfTwo(N1) &&
3714 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
3715 SDLoc DL(N);
3716 SDValue LogBase2 = BuildLogBase2(N1, DL);
3717 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3718 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3719 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3720 }
3721
3722 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
3723 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
3724 unsigned Log2Val = (-ConstValue1).logBase2();
3725 SDLoc DL(N);
3726 // FIXME: If the input is something that is easily negated (e.g. a
3727 // single-use add), we should put the negate there.
3728 return DAG.getNode(ISD::SUB, DL, VT,
3729 DAG.getConstant(0, DL, VT),
3730 DAG.getNode(ISD::SHL, DL, VT, N0,
3731 DAG.getConstant(Log2Val, DL,
3732 getShiftAmountTy(N0.getValueType()))));
3733 }
3734
3735 // Try to transform:
3736 // (1) multiply-by-(power-of-2 +/- 1) into shift and add/sub.
3737 // mul x, (2^N + 1) --> add (shl x, N), x
3738 // mul x, (2^N - 1) --> sub (shl x, N), x
3739 // Examples: x * 33 --> (x << 5) + x
3740 // x * 15 --> (x << 4) - x
3741 // x * -33 --> -((x << 5) + x)
3742 // x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
3743 // (2) multiply-by-(power-of-2 +/- power-of-2) into shifts and add/sub.
3744 // mul x, (2^N + 2^M) --> (add (shl x, N), (shl x, M))
3745 // mul x, (2^N - 2^M) --> (sub (shl x, N), (shl x, M))
3746 // Examples: x * 0x8800 --> (x << 15) + (x << 11)
3747 // x * 0xf800 --> (x << 16) - (x << 11)
3748 // x * -0x8800 --> -((x << 15) + (x << 11))
3749 // x * -0xf800 --> -((x << 16) - (x << 11)) ; (x << 11) - (x << 16)
3750 if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) {
3751 // TODO: We could handle more general decomposition of any constant by
3752 // having the target set a limit on number of ops and making a
3753 // callback to determine that sequence (similar to sqrt expansion).
3754 unsigned MathOp = ISD::DELETED_NODE;
3755 APInt MulC = ConstValue1.abs();
3756 // The constant `2` should be treated as (2^0 + 1).
3757 unsigned TZeros = MulC == 2 ? 0 : MulC.countTrailingZeros();
3758 MulC.lshrInPlace(TZeros);
3759 if ((MulC - 1).isPowerOf2())
3760 MathOp = ISD::ADD;
3761 else if ((MulC + 1).isPowerOf2())
3762 MathOp = ISD::SUB;
3763
3764 if (MathOp != ISD::DELETED_NODE) {
3765 unsigned ShAmt =
3766 MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2();
3767 ShAmt += TZeros;
3768 assert(ShAmt < VT.getScalarSizeInBits() &&((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3769, __PRETTY_FUNCTION__))
3769 "multiply-by-constant generated out of bounds shift")((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3769, __PRETTY_FUNCTION__))
;
3770 SDLoc DL(N);
3771 SDValue Shl =
3772 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
3773 SDValue R =
3774 TZeros ? DAG.getNode(MathOp, DL, VT, Shl,
3775 DAG.getNode(ISD::SHL, DL, VT, N0,
3776 DAG.getConstant(TZeros, DL, VT)))
3777 : DAG.getNode(MathOp, DL, VT, Shl, N0);
3778 if (ConstValue1.isNegative())
3779 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3780 return R;
3781 }
3782 }
3783
3784 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
3785 if (N0.getOpcode() == ISD::SHL &&
3786 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3787 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3788 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3789 if (isConstantOrConstantVector(C3))
3790 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3791 }
3792
3793 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
3794 // use.
3795 {
3796 SDValue Sh(nullptr, 0), Y(nullptr, 0);
3797
3798 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
3799 if (N0.getOpcode() == ISD::SHL &&
3800 isConstantOrConstantVector(N0.getOperand(1)) &&
3801 N0.getNode()->hasOneUse()) {
3802 Sh = N0; Y = N1;
3803 } else if (N1.getOpcode() == ISD::SHL &&
3804 isConstantOrConstantVector(N1.getOperand(1)) &&
3805 N1.getNode()->hasOneUse()) {
3806 Sh = N1; Y = N0;
3807 }
3808
3809 if (Sh.getNode()) {
3810 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3811 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3812 }
3813 }
3814
3815 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
3816 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
3817 N0.getOpcode() == ISD::ADD &&
3818 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
3819 isMulAddWithConstProfitable(N, N0, N1))
3820 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
3821 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
3822 N0.getOperand(0), N1),
3823 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
3824 N0.getOperand(1), N1));
3825
3826 // Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
3827 if (N0.getOpcode() == ISD::VSCALE)
3828 if (ConstantSDNode *NC1 = isConstOrConstSplat(N1)) {
3829 APInt C0 = N0.getConstantOperandAPInt(0);
3830 APInt C1 = NC1->getAPIntValue();
3831 return DAG.getVScale(SDLoc(N), VT, C0 * C1);
3832 }
3833
3834 // Fold ((mul x, 0/undef) -> 0,
3835 // (mul x, 1) -> x) -> x)
3836 // -> and(x, mask)
3837 // We can replace vectors with '0' and '1' factors with a clearing mask.
3838 if (VT.isFixedLengthVector()) {
3839 unsigned NumElts = VT.getVectorNumElements();
3840 SmallBitVector ClearMask;
3841 ClearMask.reserve(NumElts);
3842 auto IsClearMask = [&ClearMask](ConstantSDNode *V) {
3843 if (!V || V->isNullValue()) {
3844 ClearMask.push_back(true);
3845 return true;
3846 }
3847 ClearMask.push_back(false);
3848 return V->isOne();
3849 };
3850 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::AND, VT)) &&
3851 ISD::matchUnaryPredicate(N1, IsClearMask, /*AllowUndefs*/ true)) {
3852 assert(N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector")((N1.getOpcode() == ISD::BUILD_VECTOR && "Unknown constant vector"
) ? static_cast<void> (0) : __assert_fail ("N1.getOpcode() == ISD::BUILD_VECTOR && \"Unknown constant vector\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3852, __PRETTY_FUNCTION__))
;
3853 SDLoc DL(N);
3854 EVT LegalSVT = N1.getOperand(0).getValueType();
3855 SDValue Zero = DAG.getConstant(0, DL, LegalSVT);
3856 SDValue AllOnes = DAG.getAllOnesConstant(DL, LegalSVT);
3857 SmallVector<SDValue, 16> Mask(NumElts, AllOnes);
3858 for (unsigned I = 0; I != NumElts; ++I)
3859 if (ClearMask[I])
3860 Mask[I] = Zero;
3861 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getBuildVector(VT, DL, Mask));
3862 }
3863 }
3864
3865 // reassociate mul
3866 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3867 return RMUL;
3868
3869 return SDValue();
3870}
3871
3872/// Return true if divmod libcall is available.
3873static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
3874 const TargetLowering &TLI) {
3875 RTLIB::Libcall LC;
3876 EVT NodeType = Node->getValueType(0);
3877 if (!NodeType.isSimple())
3878 return false;
3879 switch (NodeType.getSimpleVT().SimpleTy) {
3880 default: return false; // No libcall for vector types.
3881 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
3882 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
3883 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
3884 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
3885 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
3886 }
3887
3888 return TLI.getLibcallName(LC) != nullptr;
3889}
3890
3891/// Issue divrem if both quotient and remainder are needed.
3892SDValue DAGCombiner::useDivRem(SDNode *Node) {
3893 if (Node->use_empty())
3894 return SDValue(); // This is a dead node, leave it alone.
3895
3896 unsigned Opcode = Node->getOpcode();
3897 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3898 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3899
3900 // DivMod lib calls can still work on non-legal types if using lib-calls.
3901 EVT VT = Node->getValueType(0);
3902 if (VT.isVector() || !VT.isInteger())
3903 return SDValue();
3904
3905 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
3906 return SDValue();
3907
3908 // If DIVREM is going to get expanded into a libcall,
3909 // but there is no libcall available, then don't combine.
3910 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
3911 !isDivRemLibcallAvailable(Node, isSigned, TLI))
3912 return SDValue();
3913
3914 // If div is legal, it's better to do the normal expansion
3915 unsigned OtherOpcode = 0;
3916 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3917 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3918 if (TLI.isOperationLegalOrCustom(Opcode, VT))
3919 return SDValue();
3920 } else {
3921 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3922 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
3923 return SDValue();
3924 }
3925
3926 SDValue Op0 = Node->getOperand(0);
3927 SDValue Op1 = Node->getOperand(1);
3928 SDValue combined;
3929 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
3930 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
3931 SDNode *User = *UI;
3932 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
3933 User->use_empty())
3934 continue;
3935 // Convert the other matching node(s), too;
3936 // otherwise, the DIVREM may get target-legalized into something
3937 // target-specific that we won't be able to recognize.
3938 unsigned UserOpc = User->getOpcode();
3939 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
3940 User->getOperand(0) == Op0 &&
3941 User->getOperand(1) == Op1) {
3942 if (!combined) {
3943 if (UserOpc == OtherOpcode) {
3944 SDVTList VTs = DAG.getVTList(VT, VT);
3945 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
3946 } else if (UserOpc == DivRemOpc) {
3947 combined = SDValue(User, 0);
3948 } else {
3949 assert(UserOpc == Opcode)((UserOpc == Opcode) ? static_cast<void> (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3949, __PRETTY_FUNCTION__))
;
3950 continue;
3951 }
3952 }
3953 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3954 CombineTo(User, combined);
3955 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3956 CombineTo(User, combined.getValue(1));
3957 }
3958 }
3959 return combined;
3960}
3961
3962static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
3963 SDValue N0 = N->getOperand(0);
3964 SDValue N1 = N->getOperand(1);
3965 EVT VT = N->getValueType(0);
3966 SDLoc DL(N);
3967
3968 unsigned Opc = N->getOpcode();
3969 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3970 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3971
3972 // X / undef -> undef
3973 // X % undef -> undef
3974 // X / 0 -> undef
3975 // X % 0 -> undef
3976 // NOTE: This includes vectors where any divisor element is zero/undef.
3977 if (DAG.isUndef(Opc, {N0, N1}))
3978 return DAG.getUNDEF(VT);
3979
3980 // undef / X -> 0
3981 // undef % X -> 0
3982 if (N0.isUndef())
3983 return DAG.getConstant(0, DL, VT);
3984
3985 // 0 / X -> 0
3986 // 0 % X -> 0
3987 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3988 if (N0C && N0C->isNullValue())
3989 return N0;
3990
3991 // X / X -> 1
3992 // X % X -> 0
3993 if (N0 == N1)
3994 return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);
3995
3996 // X / 1 -> X
3997 // X % 1 -> 0
3998 // If this is a boolean op (single-bit element type), we can't have
3999 // division-by-zero or remainder-by-zero, so assume the divisor is 1.
4000 // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
4001 // it's a 1.
4002 if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
4003 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
4004
4005 return SDValue();
4006}
4007
4008SDValue DAGCombiner::visitSDIV(SDNode *N) {
4009 SDValue N0 = N->getOperand(0);
4010 SDValue N1 = N->getOperand(1);
4011 EVT VT = N->getValueType(0);
4012 EVT CCVT = getSetCCResultType(VT);
4013
4014 // fold vector ops
4015 if (VT.isVector())
4016 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4017 return FoldedVOp;
4018
4019 SDLoc DL(N);
4020
4021 // fold (sdiv c1, c2) -> c1/c2
4022 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4023 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
4024 return C;
4025
4026 // fold (sdiv X, -1) -> 0-X
4027 if (N1C && N1C->isAllOnesValue())
4028 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
4029
4030 // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
4031 if (N1C && N1C->getAPIntValue().isMinSignedValue())
4032 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4033 DAG.getConstant(1, DL, VT),
4034 DAG.getConstant(0, DL, VT));
4035
4036 if (SDValue V = simplifyDivRem(N, DAG))
4037 return V;
4038
4039 if (SDValue NewSel = foldBinOpIntoSelect(N))
4040 return NewSel;
4041
4042 // If we know the sign bits of both operands are zero, strength reduce to a
4043 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
4044 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4045 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
4046
4047 if (SDValue V = visitSDIVLike(N0, N1, N)) {
4048 // If the corresponding remainder node exists, update its users with
4049 // (Dividend - (Quotient * Divisor).
4050 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
4051 { N0, N1 })) {
4052 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
4053 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4054 AddToWorklist(Mul.getNode());
4055 AddToWorklist(Sub.getNode());
4056 CombineTo(RemNode, Sub);
4057 }
4058 return V;
4059 }
4060
4061 // sdiv, srem -> sdivrem
4062 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
4063 // true. Otherwise, we break the simplification logic in visitREM().
4064 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4065 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
4066 if (SDValue DivRem = useDivRem(N))
4067 return DivRem;
4068
4069 return SDValue();
4070}
4071
4072SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4073 SDLoc DL(N);
4074 EVT VT = N->getValueType(0);
4075 EVT CCVT = getSetCCResultType(VT);
4076 unsigned BitWidth = VT.getScalarSizeInBits();
4077
4078 // Helper for determining whether a value is a power-2 constant scalar or a
4079 // vector of such elements.
4080 auto IsPowerOfTwo = [](ConstantSDNode *C) {
4081 if (C->isNullValue() || C->isOpaque())
4082 return false;
4083 if (C->getAPIntValue().isPowerOf2())
4084 return true;
4085 if ((-C->getAPIntValue()).isPowerOf2())
4086 return true;
4087 return false;
4088 };
4089
4090 // fold (sdiv X, pow2) -> simple ops after legalize
4091 // FIXME: We check for the exact bit here because the generic lowering gives
4092 // better results in that case. The target-specific lowering should learn how
4093 // to handle exact sdivs efficiently.
4094 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
4095 // Target-specific implementation of sdiv x, pow2.
4096 if (SDValue Res = BuildSDIVPow2(N))
4097 return Res;
4098
4099 // Create constants that are functions of the shift amount value.
4100 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
4101 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
4102 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
4103 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
4104 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
4105 if (!isConstantOrConstantVector(Inexact))
4106 return SDValue();
4107
4108 // Splat the sign bit into the register
4109 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
4110 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
4111 AddToWorklist(Sign.getNode());
4112
4113 // Add (N0 < 0) ? abs2 - 1 : 0;
4114 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
4115 AddToWorklist(Srl.getNode());
4116 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
4117 AddToWorklist(Add.getNode());
4118 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
4119 AddToWorklist(Sra.getNode());
4120
4121 // Special case: (sdiv X, 1) -> X
4122 // Special Case: (sdiv X, -1) -> 0-X
4123 SDValue One = DAG.getConstant(1, DL, VT);
4124 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
4125 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
4126 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
4127 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
4128 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
4129
4130 // If dividing by a positive value, we're done. Otherwise, the result must
4131 // be negated.
4132 SDValue Zero = DAG.getConstant(0, DL, VT);
4133 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
4134
4135 // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
4136 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
4137 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
4138 return Res;
4139 }
4140
4141 // If integer divide is expensive and we satisfy the requirements, emit an
4142 // alternate sequence. Targets may check function attributes for size/speed
4143 // trade-offs.
4144 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4145 if (isConstantOrConstantVector(N1) &&
4146 !TLI.isIntDivCheap(N->getValueType(0), Attr))
4147 if (SDValue Op = BuildSDIV(N))
4148 return Op;
4149
4150 return SDValue();
4151}
4152
4153SDValue DAGCombiner::visitUDIV(SDNode *N) {
4154 SDValue N0 = N->getOperand(0);
4155 SDValue N1 = N->getOperand(1);
4156 EVT VT = N->getValueType(0);
4157 EVT CCVT = getSetCCResultType(VT);
4158
4159 // fold vector ops
4160 if (VT.isVector())
4161 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4162 return FoldedVOp;
4163
4164 SDLoc DL(N);
4165
4166 // fold (udiv c1, c2) -> c1/c2
4167 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4168 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
4169 return C;
4170
4171 // fold (udiv X, -1) -> select(X == -1, 1, 0)
4172 if (N1C && N1C->getAPIntValue().isAllOnesValue())
4173 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4174 DAG.getConstant(1, DL, VT),
4175 DAG.getConstant(0, DL, VT));
4176
4177 if (SDValue V = simplifyDivRem(N, DAG))
4178 return V;
4179
4180 if (SDValue NewSel = foldBinOpIntoSelect(N))
4181 return NewSel;
4182
4183 if (SDValue V = visitUDIVLike(N0, N1, N)) {
4184 // If the corresponding remainder node exists, update its users with
4185 // (Dividend - (Quotient * Divisor).
4186 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
4187 { N0, N1 })) {
4188 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
4189 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4190 AddToWorklist(Mul.getNode());
4191 AddToWorklist(Sub.getNode());
4192 CombineTo(RemNode, Sub);
4193 }
4194 return V;
4195 }
4196
4197 // sdiv, srem -> sdivrem
4198 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
4199 // true. Otherwise, we break the simplification logic in visitREM().
4200 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4201 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
4202 if (SDValue DivRem = useDivRem(N))
4203 return DivRem;
4204
4205 return SDValue();
4206}
4207
4208SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4209 SDLoc DL(N);
4210 EVT VT = N->getValueType(0);
4211
4212 // fold (udiv x, (1 << c)) -> x >>u c
4213 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4214 DAG.isKnownToBeAPowerOfTwo(N1)) {
4215 SDValue LogBase2 = BuildLogBase2(N1, DL);
4216 AddToWorklist(LogBase2.getNode());
4217
4218 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4219 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
4220 AddToWorklist(Trunc.getNode());
4221 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4222 }
4223
4224 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
4225 if (N1.getOpcode() == ISD::SHL) {
4226 SDValue N10 = N1.getOperand(0);
4227 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
4228 DAG.isKnownToBeAPowerOfTwo(N10)) {
4229 SDValue LogBase2 = BuildLogBase2(N10, DL);
4230 AddToWorklist(LogBase2.getNode());
4231
4232 EVT ADDVT = N1.getOperand(1).getValueType();
4233 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
4234 AddToWorklist(Trunc.getNode());
4235 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
4236 AddToWorklist(Add.getNode());
4237 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
4238 }
4239 }
4240
4241 // fold (udiv x, c) -> alternate
4242 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4243 if (isConstantOrConstantVector(N1) &&
4244 !TLI.isIntDivCheap(N->getValueType(0), Attr))
4245 if (SDValue Op = BuildUDIV(N))
4246 return Op;
4247
4248 return SDValue();
4249}
4250
4251// handles ISD::SREM and ISD::UREM
4252SDValue DAGCombiner::visitREM(SDNode *N) {
4253 unsigned Opcode = N->getOpcode();
4254 SDValue N0 = N->getOperand(0);
4255 SDValue N1 = N->getOperand(1);
4256 EVT VT = N->getValueType(0);
4257 EVT CCVT = getSetCCResultType(VT);
4258
4259 bool isSigned = (Opcode == ISD::SREM);
4260 SDLoc DL(N);
4261
4262 // fold (rem c1, c2) -> c1%c2
4263 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4264 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4265 return C;
4266
4267 // fold (urem X, -1) -> select(X == -1, 0, x)
4268 if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
4269 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4270 DAG.getConstant(0, DL, VT), N0);
4271
4272 if (SDValue V = simplifyDivRem(N, DAG))
4273 return V;
4274
4275 if (SDValue NewSel = foldBinOpIntoSelect(N))
4276 return NewSel;
4277
4278 if (isSigned) {
4279 // If we know the sign bits of both operands are zero, strength reduce to a
4280 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
4281 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4282 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
4283 } else {
4284 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
4285 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
4286 // fold (urem x, pow2) -> (and x, pow2-1)
4287 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4288 AddToWorklist(Add.getNode());
4289 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4290 }
4291 if (N1.getOpcode() == ISD::SHL &&
4292 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
4293 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
4294 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4295 AddToWorklist(Add.getNode());
4296 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4297 }
4298 }
4299
4300 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4301
4302 // If X/C can be simplified by the division-by-constant logic, lower
4303 // X%C to the equivalent of X-X/C*C.
4304 // Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
4305 // speculative DIV must not cause a DIVREM conversion. We guard against this
4306 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
4307 // combine will not return a DIVREM. Regardless, checking cheapness here
4308 // makes sense since the simplification results in fatter code.
4309 if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
4310 SDValue OptimizedDiv =
4311 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
4312 if (OptimizedDiv.getNode()) {
4313 // If the equivalent Div node also exists, update its users.
4314 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
4315 if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
4316 { N0, N1 }))
4317 CombineTo(DivNode, OptimizedDiv);
4318 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
4319 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4320 AddToWorklist(OptimizedDiv.getNode());
4321 AddToWorklist(Mul.getNode());
4322 return Sub;
4323 }
4324 }
4325
4326 // sdiv, srem -> sdivrem
4327 if (SDValue DivRem = useDivRem(N))
4328 return DivRem.getValue(1);
4329
4330 return SDValue();
4331}
4332
4333SDValue DAGCombiner::visitMULHS(SDNode *N) {
4334 SDValue N0 = N->getOperand(0);
4335 SDValue N1 = N->getOperand(1);
4336 EVT VT = N->getValueType(0);
4337 SDLoc DL(N);
4338
4339 if (VT.isVector()) {
4340 // fold (mulhs x, 0) -> 0
4341 // do not return N0/N1, because undef node may exist.
4342 if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
4343 ISD::isBuildVectorAllZeros(N1.getNode()))
4344 return DAG.getConstant(0, DL, VT);
4345 }
4346
4347 // fold (mulhs x, 0) -> 0
4348 if (isNullConstant(N1))
4349 return N1;
4350 // fold (mulhs x, 1) -> (sra x, size(x)-1)
4351 if (isOneConstant(N1))
4352 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
4353 DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL,
4354 getShiftAmountTy(N0.getValueType())));
4355
4356 // fold (mulhs x, undef) -> 0
4357 if (N0.isUndef() || N1.isUndef())
4358 return DAG.getConstant(0, DL, VT);
4359
4360 // If the type twice as wide is legal, transform the mulhs to a wider multiply
4361 // plus a shift.
4362 if (!TLI.isOperationLegalOrCustom(ISD::MULHS, VT) && VT.isSimple() &&
4363 !VT.isVector()) {
4364 MVT Simple = VT.getSimpleVT();
4365 unsigned SimpleSize = Simple.getSizeInBits();
4366 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4367 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4368 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
4369 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
4370 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4371 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4372 DAG.getConstant(SimpleSize, DL,
4373 getShiftAmountTy(N1.getValueType())));
4374 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4375 }
4376 }
4377
4378 return SDValue();
4379}
4380
4381SDValue DAGCombiner::visitMULHU(SDNode *N) {
4382 SDValue N0 = N->getOperand(0);
4383 SDValue N1 = N->getOperand(1);
4384 EVT VT = N->getValueType(0);
4385 SDLoc DL(N);
4386
4387 if (VT.isVector()) {
4388 // fold (mulhu x, 0) -> 0
4389 // do not return N0/N1, because undef node may exist.
4390 if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
4391 ISD::isBuildVectorAllZeros(N1.getNode()))
4392 return DAG.getConstant(0, DL, VT);
4393 }
4394
4395 // fold (mulhu x, 0) -> 0
4396 if (isNullConstant(N1))
4397 return N1;
4398 // fold (mulhu x, 1) -> 0
4399 if (isOneConstant(N1))
4400 return DAG.getConstant(0, DL, N0.getValueType());
4401 // fold (mulhu x, undef) -> 0
4402 if (N0.isUndef() || N1.isUndef())
4403 return DAG.getConstant(0, DL, VT);
4404
4405 // fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
4406 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4407 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
4408 unsigned NumEltBits = VT.getScalarSizeInBits();
4409 SDValue LogBase2 = BuildLogBase2(N1, DL);
4410 SDValue SRLAmt = DAG.getNode(
4411 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
4412 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4413 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
4414 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4415 }
4416
4417 // If the type twice as wide is legal, transform the mulhu to a wider multiply
4418 // plus a shift.
4419 if (!TLI.isOperationLegalOrCustom(ISD::MULHU, VT) && VT.isSimple() &&
4420 !VT.isVector()) {
4421 MVT Simple = VT.getSimpleVT();
4422 unsigned SimpleSize = Simple.getSizeInBits();
4423 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4424 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4425 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
4426 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
4427 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4428 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4429 DAG.getConstant(SimpleSize, DL,
4430 getShiftAmountTy(N1.getValueType())));
4431 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4432 }
4433 }
4434
4435 return SDValue();
4436}
4437
4438/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
4439/// give the opcodes for the two computations that are being performed. Return
4440/// true if a simplification was made.
4441SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
4442 unsigned HiOp) {
4443 // If the high half is not needed, just compute the low half.
4444 bool HiExists = N->hasAnyUseOfValue(1);
4445 if (!HiExists && (!LegalOperations ||
4446 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
4447 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4448 return CombineTo(N, Res, Res);
4449 }
4450
4451 // If the low half is not needed, just compute the high half.
4452 bool LoExists = N->hasAnyUseOfValue(0);
4453 if (!LoExists && (!LegalOperations ||
4454 TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
4455 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4456 return CombineTo(N, Res, Res);
4457 }
4458
4459 // If both halves are used, return as it is.
4460 if (LoExists && HiExists)
4461 return SDValue();
4462
4463 // If the two computed results can be simplified separately, separate them.
4464 if (LoExists) {
4465 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4466 AddToWorklist(Lo.getNode());
4467 SDValue LoOpt = combine(Lo.getNode());
4468 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
4469 (!LegalOperations ||
4470 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
4471 return CombineTo(N, LoOpt, LoOpt);
4472 }
4473
4474 if (HiExists) {
4475 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4476 AddToWorklist(Hi.getNode());
4477 SDValue HiOpt = combine(Hi.getNode());
4478 if (HiOpt.getNode() && HiOpt != Hi &&
4479 (!LegalOperations ||
4480 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
4481 return CombineTo(N, HiOpt, HiOpt);
4482 }
4483
4484 return SDValue();
4485}
4486
4487SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
4488 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
4489 return Res;
4490
4491 EVT VT = N->getValueType(0);
4492 SDLoc DL(N);
4493
4494 // If the type is twice as wide is legal, transform the mulhu to a wider
4495 // multiply plus a shift.
4496 if (VT.isSimple() && !VT.isVector()) {
4497 MVT Simple = VT.getSimpleVT();
4498 unsigned SimpleSize = Simple.getSizeInBits();
4499 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4500 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4501 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4502 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
4503 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4504 // Compute the high part as N1.
4505 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4506 DAG.getConstant(SimpleSize, DL,
4507 getShiftAmountTy(Lo.getValueType())));
4508 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4509 // Compute the low part as N0.
4510 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4511 return CombineTo(N, Lo, Hi);
4512 }
4513 }
4514
4515 return SDValue();
4516}
4517
4518SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
4519 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
4520 return Res;
4521
4522 EVT VT = N->getValueType(0);
4523 SDLoc DL(N);
4524
4525 // (umul_lohi N0, 0) -> (0, 0)
4526 if (isNullConstant(N->getOperand(1))) {
4527 SDValue Zero = DAG.getConstant(0, DL, VT);
4528 return CombineTo(N, Zero, Zero);
4529 }
4530
4531 // (umul_lohi N0, 1) -> (N0, 0)
4532 if (isOneConstant(N->getOperand(1))) {
4533 SDValue Zero = DAG.getConstant(0, DL, VT);
4534 return CombineTo(N, N->getOperand(0), Zero);
4535 }
4536
4537 // If the type is twice as wide is legal, transform the mulhu to a wider
4538 // multiply plus a shift.
4539 if (VT.isSimple() && !VT.isVector()) {
4540 MVT Simple = VT.getSimpleVT();
4541 unsigned SimpleSize = Simple.getSizeInBits();
4542 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4543 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4544 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
4545 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
4546 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4547 // Compute the high part as N1.
4548 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4549 DAG.getConstant(SimpleSize, DL,
4550 getShiftAmountTy(Lo.getValueType())));
4551 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4552 // Compute the low part as N0.
4553 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4554 return CombineTo(N, Lo, Hi);
4555 }
4556 }
4557
4558 return SDValue();
4559}
4560
4561SDValue DAGCombiner::visitMULO(SDNode *N) {
4562 SDValue N0 = N->getOperand(0);
4563 SDValue N1 = N->getOperand(1);
4564 EVT VT = N0.getValueType();
4565 bool IsSigned = (ISD::SMULO == N->getOpcode());
4566
4567 EVT CarryVT = N->getValueType(1);
4568 SDLoc DL(N);
4569
4570 // canonicalize constant to RHS.
4571 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4572 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4573 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
4574
4575 // fold (mulo x, 0) -> 0 + no carry out
4576 if (isNullOrNullSplat(N1))
4577 return CombineTo(N, DAG.getConstant(0, DL, VT),
4578 DAG.getConstant(0, DL, CarryVT));
4579
4580 // (mulo x, 2) -> (addo x, x)
4581 if (ConstantSDNode *C2 = isConstOrConstSplat(N1))
4582 if (C2->getAPIntValue() == 2)
4583 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
4584 N->getVTList(), N0, N0);
4585
4586 return SDValue();
4587}
4588
4589SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
4590 SDValue N0 = N->getOperand(0);
4591 SDValue N1 = N->getOperand(1);
4592 EVT VT = N0.getValueType();
4593 unsigned Opcode = N->getOpcode();
4594
4595 // fold vector ops
4596 if (VT.isVector())
4597 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4598 return FoldedVOp;
4599
4600 // fold operation with constant operands.
4601 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, SDLoc(N), VT, {N0, N1}))
4602 return C;
4603
4604 // canonicalize constant to RHS
4605 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4606 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4607 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
4608
4609 // Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
4610 // Only do this if the current op isn't legal and the flipped is.
4611 if (!TLI.isOperationLegal(Opcode, VT) &&
4612 (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
4613 (N1.isUndef() || DAG.SignBitIsZero(N1))) {
4614 unsigned AltOpcode;
4615 switch (Opcode) {
4616 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4617 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4618 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
4619 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
4620 default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4620)
;
4621 }
4622 if (TLI.isOperationLegal(AltOpcode, VT))
4623 return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
4624 }
4625
4626 return SDValue();
4627}
4628
4629/// If this is a bitwise logic instruction and both operands have the same
4630/// opcode, try to sink the other opcode after the logic instruction.
4631SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
4632 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4633 EVT VT = N0.getValueType();
4634 unsigned LogicOpcode = N->getOpcode();
4635 unsigned HandOpcode = N0.getOpcode();
4636 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4637, __PRETTY_FUNCTION__))
4637 LogicOpcode == ISD::XOR) && "Expected logic opcode")(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4637, __PRETTY_FUNCTION__))
;
4638 assert(HandOpcode == N1.getOpcode() && "Bad input!")((HandOpcode == N1.getOpcode() && "Bad input!") ? static_cast
<void> (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4638, __PRETTY_FUNCTION__))
;
4639
4640 // Bail early if none of these transforms apply.
4641 if (N0.getNumOperands() == 0)
4642 return SDValue();
4643
4644 // FIXME: We should check number of uses of the operands to not increase
4645 // the instruction count for all transforms.
4646
4647 // Handle size-changing casts.
4648 SDValue X = N0.getOperand(0);
4649 SDValue Y = N1.getOperand(0);
4650 EVT XVT = X.getValueType();
4651 SDLoc DL(N);
4652 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4653 HandOpcode == ISD::SIGN_EXTEND) {
4654 // If both operands have other uses, this transform would create extra
4655 // instructions without eliminating anything.
4656 if (!N0.hasOneUse() && !N1.hasOneUse())
4657 return SDValue();
4658 // We need matching integer source types.
4659 if (XVT != Y.getValueType())
4660 return SDValue();
4661 // Don't create an illegal op during or after legalization. Don't ever
4662 // create an unsupported vector op.
4663 if ((VT.isVector() || LegalOperations) &&
4664 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4665 return SDValue();
4666 // Avoid infinite looping with PromoteIntBinOp.
4667 // TODO: Should we apply desirable/legal constraints to all opcodes?
4668 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
4669 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4670 return SDValue();
4671 // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
4672 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4673 return DAG.getNode(HandOpcode, DL, VT, Logic);
4674 }
4675
4676 // logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
4677 if (HandOpcode == ISD::TRUNCATE) {
4678 // If both operands have other uses, this transform would create extra
4679 // instructions without eliminating anything.
4680 if (!N0.hasOneUse() && !N1.hasOneUse())
4681 return SDValue();
4682 // We need matching source types.
4683 if (XVT != Y.getValueType())
4684 return SDValue();
4685 // Don't create an illegal op during or after legalization.
4686 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4687 return SDValue();
4688 // Be extra careful sinking truncate. If it's free, there's no benefit in
4689 // widening a binop. Also, don't create a logic op on an illegal type.
4690 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
4691 return SDValue();
4692 if (!TLI.isTypeLegal(XVT))
4693 return SDValue();
4694 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4695 return DAG.getNode(HandOpcode, DL, VT, Logic);
4696 }
4697
4698 // For binops SHL/SRL/SRA/AND:
4699 // logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
4700 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4701 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4702 N0.getOperand(1) == N1.getOperand(1)) {
4703 // If either operand has other uses, this transform is not an improvement.
4704 if (!N0.hasOneUse() || !N1.hasOneUse())
4705 return SDValue();
4706 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4707 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
4708 }
4709
4710 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
4711 if (HandOpcode == ISD::BSWAP) {
4712 // If either operand has other uses, this transform is not an improvement.
4713 if (!N0.hasOneUse() || !N1.hasOneUse())
4714 return SDValue();
4715 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4716 return DAG.getNode(HandOpcode, DL, VT, Logic);
4717 }
4718
4719 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
4720 // Only perform this optimization up until type legalization, before
4721 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
4722 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
4723 // we don't want to undo this promotion.
4724 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4725 // on scalars.
4726 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
4727 Level <= AfterLegalizeTypes) {
4728 // Input types must be integer and the same.
4729 if (XVT.isInteger() && XVT == Y.getValueType() &&
4730 !(VT.isVector() && TLI.isTypeLegal(VT) &&
4731 !XVT.isVector() && !TLI.isTypeLegal(XVT))) {
4732 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4733 return DAG.getNode(HandOpcode, DL, VT, Logic);
4734 }
4735 }
4736
4737 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
4738 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
4739 // If both shuffles use the same mask, and both shuffle within a single
4740 // vector, then it is worthwhile to move the swizzle after the operation.
4741 // The type-legalizer generates this pattern when loading illegal
4742 // vector types from memory. In many cases this allows additional shuffle
4743 // optimizations.
4744 // There are other cases where moving the shuffle after the xor/and/or
4745 // is profitable even if shuffles don't perform a swizzle.
4746 // If both shuffles use the same mask, and both shuffles have the same first
4747 // or second operand, then it might still be profitable to move the shuffle
4748 // after the xor/and/or operation.
4749 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
4750 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
4751 auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
4752 assert(X.getValueType() == Y.getValueType() &&((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4753, __PRETTY_FUNCTION__))
4753 "Inputs to shuffles are not the same type")((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4753, __PRETTY_FUNCTION__))
;
4754
4755 // Check that both shuffles use the same mask. The masks are known to be of
4756 // the same length because the result vector type is the same.
4757 // Check also that shuffles have only one use to avoid introducing extra
4758 // instructions.
4759 if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
4760 !SVN0->getMask().equals(SVN1->getMask()))
4761 return SDValue();
4762
4763 // Don't try to fold this node if it requires introducing a
4764 // build vector of all zeros that might be illegal at this stage.
4765 SDValue ShOp = N0.getOperand(1);
4766 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4767 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4768
4769 // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
4770 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4771 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
4772 N0.getOperand(0), N1.getOperand(0));
4773 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4774 }
4775
4776 // Don't try to fold this node if it requires introducing a
4777 // build vector of all zeros that might be illegal at this stage.
4778 ShOp = N0.getOperand(0);
4779 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4780 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4781
4782 // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
4783 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4784 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
4785 N1.getOperand(1));
4786 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
4787 }
4788 }
4789
4790 return SDValue();
4791}
4792
4793/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4794SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
4795 const SDLoc &DL) {
4796 SDValue LL, LR, RL, RR, N0CC, N1CC;
4797 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
4798 !isSetCCEquivalent(N1, RL, RR, N1CC))
4799 return SDValue();
4800
4801 assert(N0.getValueType() == N1.getValueType() &&((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4802, __PRETTY_FUNCTION__))
4802 "Unexpected operand types for bitwise logic op")((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4802, __PRETTY_FUNCTION__))
;
4803 assert(LL.getValueType() == LR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4805, __PRETTY_FUNCTION__))
4804 RL.getValueType() == RR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4805, __PRETTY_FUNCTION__))
4805 "Unexpected operand types for setcc")((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4805, __PRETTY_FUNCTION__))
;
4806
4807 // If we're here post-legalization or the logic op type is not i1, the logic
4808 // op type must match a setcc result type. Also, all folds require new
4809 // operations on the left and right operands, so those types must match.
4810 EVT VT = N0.getValueType();
4811 EVT OpVT = LL.getValueType();
4812 if (LegalOperations || VT.getScalarType() != MVT::i1)
4813 if (VT != getSetCCResultType(OpVT))
4814 return SDValue();
4815 if (OpVT != RL.getValueType())
4816 return SDValue();
4817
4818 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
4819 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
4820 bool IsInteger = OpVT.isInteger();
4821 if (LR == RR && CC0 == CC1 && IsInteger) {
4822 bool IsZero = isNullOrNullSplat(LR);
4823 bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);
4824
4825 // All bits clear?
4826 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4827 // All sign bits clear?
4828 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4829 // Any bits set?
4830 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4831 // Any sign bits set?
4832 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4833
4834 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
4835 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
4836 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
4837 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
4838 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
4839 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
4840 AddToWorklist(Or.getNode());
4841 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4842 }
4843
4844 // All bits set?
4845 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4846 // All sign bits set?
4847 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4848 // Any bits clear?
4849 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
4850 // Any sign bits clear?
4851 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
4852
4853 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
4854 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
4855 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
4856 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
4857 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
4858 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
4859 AddToWorklist(And.getNode());
4860 return DAG.getSetCC(DL, VT, And, LR, CC1);
4861 }
4862 }
4863
4864 // TODO: What is the 'or' equivalent of this fold?
4865 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
4866 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
4867 IsInteger && CC0 == ISD::SETNE &&
4868 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
4869 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
4870 SDValue One = DAG.getConstant(1, DL, OpVT);
4871 SDValue Two = DAG.getConstant(2, DL, OpVT);
4872 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
4873 AddToWorklist(Add.getNode());
4874 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
4875 }
4876
4877 // Try more general transforms if the predicates match and the only user of
4878 // the compares is the 'and' or 'or'.
4879 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
4880 N0.hasOneUse() && N1.hasOneUse()) {
4881 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
4882 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
4883 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
4884 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
4885 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
4886 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
4887 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4888 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
4889 }
4890
4891 // Turn compare of constants whose difference is 1 bit into add+and+setcc.
4892 // TODO - support non-uniform vector amounts.
4893 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
4894 // Match a shared variable operand and 2 non-opaque constant operands.
4895 ConstantSDNode *C0 = isConstOrConstSplat(LR);
4896 ConstantSDNode *C1 = isConstOrConstSplat(RR);
4897 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
4898 // Canonicalize larger constant as C0.
4899 if (C1->getAPIntValue().ugt(C0->getAPIntValue()))
4900 std::swap(C0, C1);
4901
4902 // The difference of the constants must be a single bit.
4903 const APInt &C0Val = C0->getAPIntValue();
4904 const APInt &C1Val = C1->getAPIntValue();
4905 if ((C0Val - C1Val).isPowerOf2()) {
4906 // and/or (setcc X, C0, ne), (setcc X, C1, ne/eq) -->
4907 // setcc ((add X, -C1), ~(C0 - C1)), 0, ne/eq
4908 SDValue OffsetC = DAG.getConstant(-C1Val, DL, OpVT);
4909 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LL, OffsetC);
4910 SDValue MaskC = DAG.getConstant(~(C0Val - C1Val), DL, OpVT);
4911 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
4912 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4913 return DAG.getSetCC(DL, VT, And, Zero, CC0);
4914 }
4915 }
4916 }
4917 }
4918
4919 // Canonicalize equivalent operands to LL == RL.
4920 if (LL == RR && LR == RL) {
4921 CC1 = ISD::getSetCCSwappedOperands(CC1);
4922 std::swap(RL, RR);
4923 }
4924
4925 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4926 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4927 if (LL == RL && LR == RR) {
4928 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
4929 : ISD::getSetCCOrOperation(CC0, CC1, OpVT);
4930 if (NewCC != ISD::SETCC_INVALID &&
4931 (!LegalOperations ||
4932 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
4933 TLI.isOperationLegal(ISD::SETCC, OpVT))))
4934 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
4935 }
4936
4937 return SDValue();
4938}
4939
4940/// This contains all DAGCombine rules which reduce two values combined by
4941/// an And operation to a single value. This makes them reusable in the context
4942/// of visitSELECT(). Rules involving constants are not included as
4943/// visitSELECT() already handles those cases.
4944SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
4945 EVT VT = N1.getValueType();
4946 SDLoc DL(N);
4947
4948 // fold (and x, undef) -> 0
4949 if (N0.isUndef() || N1.isUndef())
4950 return DAG.getConstant(0, DL, VT);
4951
4952 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
4953 return V;
4954
4955 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4956 VT.getSizeInBits() <= 64) {
4957 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4958 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
4959 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
4960 // immediate for an add, but it is legal if its top c2 bits are set,
4961 // transform the ADD so the immediate doesn't need to be materialized
4962 // in a register.
4963 APInt ADDC = ADDI->getAPIntValue();
4964 APInt SRLC = SRLI->getAPIntValue();
4965 if (ADDC.getMinSignedBits() <= 64 &&
4966 SRLC.ult(VT.getSizeInBits()) &&
4967 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4968 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
4969 SRLC.getZExtValue());
4970 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
4971 ADDC |= Mask;
4972 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4973 SDLoc DL0(N0);
4974 SDValue NewAdd =
4975 DAG.getNode(ISD::ADD, DL0, VT,
4976 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
4977 CombineTo(N0.getNode(), NewAdd);
4978 // Return N so it doesn't get rechecked!
4979 return SDValue(N, 0);
4980 }
4981 }
4982 }
4983 }
4984 }
4985 }
4986
4987 // Reduce bit extract of low half of an integer to the narrower type.
4988 // (and (srl i64:x, K), KMask) ->
4989 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
4990 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4991 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
4992 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4993 unsigned Size = VT.getSizeInBits();
4994 const APInt &AndMask = CAnd->getAPIntValue();
4995 unsigned ShiftBits = CShift->getZExtValue();
4996
4997 // Bail out, this node will probably disappear anyway.
4998 if (ShiftBits == 0)
4999 return SDValue();
5000
5001 unsigned MaskBits = AndMask.countTrailingOnes();
5002 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
5003
5004 if (AndMask.isMask() &&
5005 // Required bits must not span the two halves of the integer and
5006 // must fit in the half size type.
5007 (ShiftBits + MaskBits <= Size / 2) &&
5008 TLI.isNarrowingProfitable(VT, HalfVT) &&
5009 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
5010 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
5011 TLI.isTruncateFree(VT, HalfVT) &&
5012 TLI.isZExtFree(HalfVT, VT)) {
5013 // The isNarrowingProfitable is to avoid regressions on PPC and
5014 // AArch64 which match a few 64-bit bit insert / bit extract patterns
5015 // on downstream users of this. Those patterns could probably be
5016 // extended to handle extensions mixed in.
5017
5018 SDValue SL(N0);
5019 assert(MaskBits <= Size)((MaskBits <= Size) ? static_cast<void> (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5019, __PRETTY_FUNCTION__))
;
5020
5021 // Extracting the highest bit of the low half.
5022 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
5023 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
5024 N0.getOperand(0));
5025
5026 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
5027 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
5028 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
5029 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
5030 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
5031 }
5032 }
5033 }
5034 }
5035
5036 return SDValue();
5037}
5038
5039bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
5040 EVT LoadResultTy, EVT &ExtVT) {
5041 if (!AndC->getAPIntValue().isMask())
5042 return false;
5043
5044 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
5045
5046 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
5047 EVT LoadedVT = LoadN->getMemoryVT();
5048
5049 if (ExtVT == LoadedVT &&
5050 (!LegalOperations ||
5051 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
5052 // ZEXTLOAD will match without needing to change the size of the value being
5053 // loaded.
5054 return true;
5055 }
5056
5057 // Do not change the width of a volatile or atomic loads.
5058 if (!LoadN->isSimple())
5059 return false;
5060
5061 // Do not generate loads of non-round integer types since these can
5062 // be expensive (and would be wrong if the type is not byte sized).
5063 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
5064 return false;
5065
5066 if (LegalOperations &&
5067 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
5068 return false;
5069
5070 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
5071 return false;
5072
5073 return true;
5074}
5075
5076bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
5077 ISD::LoadExtType ExtType, EVT &MemVT,
5078 unsigned ShAmt) {
5079 if (!LDST)
5080 return false;
5081 // Only allow byte offsets.
5082 if (ShAmt % 8)
5083 return false;
5084
5085 // Do not generate loads of non-round integer types since these can
5086 // be expensive (and would be wrong if the type is not byte sized).
5087 if (!MemVT.isRound())
5088 return false;
5089
5090 // Don't change the width of a volatile or atomic loads.
5091 if (!LDST->isSimple())
5092 return false;
5093
5094 EVT LdStMemVT = LDST->getMemoryVT();
5095
5096 // Bail out when changing the scalable property, since we can't be sure that
5097 // we're actually narrowing here.
5098 if (LdStMemVT.isScalableVector() != MemVT.isScalableVector())
5099 return false;
5100
5101 // Verify that we are actually reducing a load width here.
5102 if (LdStMemVT.bitsLT(MemVT))
5103 return false;
5104
5105 // Ensure that this isn't going to produce an unsupported memory access.
5106 if (ShAmt) {
5107 assert(ShAmt % 8 == 0 && "ShAmt is byte offset")((ShAmt % 8 == 0 && "ShAmt is byte offset") ? static_cast
<void> (0) : __assert_fail ("ShAmt % 8 == 0 && \"ShAmt is byte offset\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5107, __PRETTY_FUNCTION__))
;
5108 const unsigned ByteShAmt = ShAmt / 8;
5109 const Align LDSTAlign = LDST->getAlign();
5110 const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt);
5111 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
5112 LDST->getAddressSpace(), NarrowAlign,
5113 LDST->getMemOperand()->getFlags()))
5114 return false;
5115 }
5116
5117 // It's not possible to generate a constant of extended or untyped type.
5118 EVT PtrType = LDST->getBasePtr().getValueType();
5119 if (PtrType == MVT::Untyped || PtrType.isExtended())
5120 return false;
5121
5122 if (isa<LoadSDNode>(LDST)) {
5123 LoadSDNode *Load = cast<LoadSDNode>(LDST);
5124 // Don't transform one with multiple uses, this would require adding a new
5125 // load.
5126 if (!SDValue(Load, 0).hasOneUse())
5127 return false;
5128
5129 if (LegalOperations &&
5130 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
5131 return false;
5132
5133 // For the transform to be legal, the load must produce only two values
5134 // (the value loaded and the chain). Don't transform a pre-increment
5135 // load, for example, which produces an extra value. Otherwise the
5136 // transformation is not equivalent, and the downstream logic to replace
5137 // uses gets things wrong.
5138 if (Load->getNumValues() > 2)
5139 return false;
5140
5141 // If the load that we're shrinking is an extload and we're not just
5142 // discarding the extension we can't simply shrink the load. Bail.
5143 // TODO: It would be possible to merge the extensions in some cases.
5144 if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
5145 Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
5146 return false;
5147
5148 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
5149 return false;
5150 } else {
5151 assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")((isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode"
) ? static_cast<void> (0) : __assert_fail ("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5151, __PRETTY_FUNCTION__))
;
5152 StoreSDNode *Store = cast<StoreSDNode>(LDST);
5153 // Can't write outside the original store
5154 if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
5155 return false;
5156
5157 if (LegalOperations &&
5158 !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
5159 return false;
5160 }
5161 return true;
5162}
5163
5164bool DAGCombiner::SearchForAndLoads(SDNode *N,
5165 SmallVectorImpl<LoadSDNode*> &Loads,
5166 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
5167 ConstantSDNode *Mask,
5168 SDNode *&NodeToMask) {
5169 // Recursively search for the operands, looking for loads which can be
5170 // narrowed.
5171 for (SDValue Op : N->op_values()) {
5172 if (Op.getValueType().isVector())
5173 return false;
5174
5175 // Some constants may need fixing up later if they are too large.
5176 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
5177 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
5178 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
5179 NodesWithConsts.insert(N);
5180 continue;
5181 }
5182
5183 if (!Op.hasOneUse())
5184 return false;
5185
5186 switch(Op.getOpcode()) {
5187 case ISD::LOAD: {
5188 auto *Load = cast<LoadSDNode>(Op);
5189 EVT ExtVT;
5190 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
5191 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
5192
5193 // ZEXTLOAD is already small enough.
5194 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
5195 ExtVT.bitsGE(Load->getMemoryVT()))
5196 continue;
5197
5198 // Use LE to convert equal sized loads to zext.
5199 if (ExtVT.bitsLE(Load->getMemoryVT()))
5200 Loads.push_back(Load);
5201
5202 continue;
5203 }
5204 return false;
5205 }
5206 case ISD::ZERO_EXTEND:
5207 case ISD::AssertZext: {
5208 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
5209 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
5210 EVT VT = Op.getOpcode() == ISD::AssertZext ?
5211 cast<VTSDNode>(Op.getOperand(1))->getVT() :
5212 Op.getOperand(0).getValueType();
5213
5214 // We can accept extending nodes if the mask is wider or an equal
5215 // width to the original type.
5216 if (ExtVT.bitsGE(VT))
5217 continue;
5218 break;
5219 }
5220 case ISD::OR:
5221 case ISD::XOR:
5222 case ISD::AND:
5223 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
5224 NodeToMask))
5225 return false;
5226 continue;
5227 }
5228
5229 // Allow one node which will masked along with any loads found.
5230 if (NodeToMask)
5231 return false;
5232
5233 // Also ensure that the node to be masked only produces one data result.
5234 NodeToMask = Op.getNode();
5235 if (NodeToMask->getNumValues() > 1) {
5236 bool HasValue = false;
5237 for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
5238 MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
5239 if (VT != MVT::Glue && VT != MVT::Other) {
5240 if (HasValue) {
5241 NodeToMask = nullptr;
5242 return false;
5243 }
5244 HasValue = true;
5245 }
5246 }
5247 assert(HasValue && "Node to be masked has no data result?")((HasValue && "Node to be masked has no data result?"
) ? static_cast<void> (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5247, __PRETTY_FUNCTION__))
;
5248 }
5249 }
5250 return true;
5251}
5252
5253bool DAGCombiner::BackwardsPropagateMask(SDNode *N) {
5254 auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
5255 if (!Mask)
5256 return false;
5257
5258 if (!Mask->getAPIntValue().isMask())
5259 return false;
5260
5261 // No need to do anything if the and directly uses a load.
5262 if (isa<LoadSDNode>(N->getOperand(0)))
5263 return false;
5264
5265 SmallVector<LoadSDNode*, 8> Loads;
5266 SmallPtrSet<SDNode*, 2> NodesWithConsts;
5267 SDNode *FixupNode = nullptr;
5268 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
5269 if (Loads.size() == 0)
5270 return false;
5271
5272 LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false)
;
5273 SDValue MaskOp = N->getOperand(1);
5274
5275 // If it exists, fixup the single node we allow in the tree that needs
5276 // masking.
5277 if (FixupNode) {
5278 LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false)
;
5279 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
5280 FixupNode->getValueType(0),
5281 SDValue(FixupNode, 0), MaskOp);
5282 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
5283 if (And.getOpcode() == ISD ::AND)
5284 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
5285 }
5286
5287 // Narrow any constants that need it.
5288 for (auto *LogicN : NodesWithConsts) {
5289 SDValue Op0 = LogicN->getOperand(0);
5290 SDValue Op1 = LogicN->getOperand(1);
5291
5292 if (isa<ConstantSDNode>(Op0))
5293 std::swap(Op0, Op1);
5294
5295 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
5296 Op1, MaskOp);
5297
5298 DAG.UpdateNodeOperands(LogicN, Op0, And);
5299 }
5300
5301 // Create narrow loads.
5302 for (auto *Load : Loads) {
5303 LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false)
;
5304 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
5305 SDValue(Load, 0), MaskOp);
5306 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
5307 if (And.getOpcode() == ISD ::AND)
5308 And = SDValue(
5309 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
5310 SDValue NewLoad = ReduceLoadWidth(And.getNode());
5311 assert(NewLoad &&((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5312, __PRETTY_FUNCTION__))
5312 "Shouldn't be masking the load if it can't be narrowed")((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5312, __PRETTY_FUNCTION__))
;
5313 CombineTo(Load, NewLoad, NewLoad.getValue(1));
5314 }
5315 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
5316 return true;
5317 }
5318 return false;
5319}
5320
5321// Unfold
5322// x & (-1 'logical shift' y)
5323// To
5324// (x 'opposite logical shift' y) 'logical shift' y
5325// if it is better for performance.
5326SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
5327 assert(N->getOpcode() == ISD::AND)((N->getOpcode() == ISD::AND) ? static_cast<void> (0
) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5327, __PRETTY_FUNCTION__))
;
5328
5329 SDValue N0 = N->getOperand(0);
5330 SDValue N1 = N->getOperand(1);
5331
5332 // Do we actually prefer shifts over mask?
5333 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
5334 return SDValue();
5335
5336 // Try to match (-1 '[outer] logical shift' y)
5337 unsigned OuterShift;
5338 unsigned InnerShift; // The opposite direction to the OuterShift.
5339 SDValue Y; // Shift amount.
5340 auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
5341 if (!M.hasOneUse())
5342 return false;
5343 OuterShift = M->getOpcode();
5344 if (OuterShift == ISD::SHL)
5345 InnerShift = ISD::SRL;
5346 else if (OuterShift == ISD::SRL)
5347 InnerShift = ISD::SHL;
5348 else
5349 return false;
5350 if (!isAllOnesConstant(M->getOperand(0)))
5351 return false;
5352 Y = M->getOperand(1);
5353 return true;
5354 };
5355
5356 SDValue X;
5357 if (matchMask(N1))
5358 X = N0;
5359 else if (matchMask(N0))
5360 X = N1;
5361 else
5362 return SDValue();
5363
5364 SDLoc DL(N);
5365 EVT VT = N->getValueType(0);
5366
5367 // tmp = x 'opposite logical shift' y
5368 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
5369 // ret = tmp 'logical shift' y
5370 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
5371
5372 return T1;
5373}
5374
5375/// Try to replace shift/logic that tests if a bit is clear with mask + setcc.
5376/// For a target with a bit test, this is expected to become test + set and save
5377/// at least 1 instruction.
5378static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) {
5379 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op")((And->getOpcode() == ISD::AND && "Expected an 'and' op"
) ? static_cast<void> (0) : __assert_fail ("And->getOpcode() == ISD::AND && \"Expected an 'and' op\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5379, __PRETTY_FUNCTION__))
;
5380
5381 // This is probably not worthwhile without a supported type.
5382 EVT VT = And->getValueType(0);
5383 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5384 if (!TLI.isTypeLegal(VT))
5385 return SDValue();
5386
5387 // Look through an optional extension and find a 'not'.
5388 // TODO: Should we favor test+set even without the 'not' op?
5389 SDValue Not = And->getOperand(0), And1 = And->getOperand(1);
5390 if (Not.getOpcode() == ISD::ANY_EXTEND)
5391 Not = Not.getOperand(0);
5392 if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1))
5393 return SDValue();
5394
5395 // Look though an optional truncation. The source operand may not be the same
5396 // type as the original 'and', but that is ok because we are masking off
5397 // everything but the low bit.
5398 SDValue Srl = Not.getOperand(0);
5399 if (Srl.getOpcode() == ISD::TRUNCATE)
5400 Srl = Srl.getOperand(0);
5401
5402 // Match a shift-right by constant.
5403 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() ||
5404 !isa<ConstantSDNode>(Srl.getOperand(1)))
5405 return SDValue();
5406
5407 // We might have looked through casts that make this transform invalid.
5408 // TODO: If the source type is wider than the result type, do the mask and
5409 // compare in the source type.
5410 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1);
5411 unsigned VTBitWidth = VT.getSizeInBits();
5412 if (ShiftAmt.uge(VTBitWidth))
5413 return SDValue();
5414
5415 // Turn this into a bit-test pattern using mask op + setcc:
5416 // and (not (srl X, C)), 1 --> (and X, 1<<C) == 0
5417 SDLoc DL(And);
5418 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT);
5419 EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5420 SDValue Mask = DAG.getConstant(
5421 APInt::getOneBitSet(VTBitWidth, ShiftAmt.getZExtValue()), DL, VT);
5422 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, Mask);
5423 SDValue Zero = DAG.getConstant(0, DL, VT);
5424 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ);
5425 return DAG.getZExtOrTrunc(Setcc, DL, VT);
5426}
5427
5428SDValue DAGCombiner::visitAND(SDNode *N) {
5429 SDValue N0 = N->getOperand(0);
5430 SDValue N1 = N->getOperand(1);
5431 EVT VT = N1.getValueType();
5432
5433 // x & x --> x
5434 if (N0 == N1)
5435 return N0;
5436
5437 // fold vector ops
5438 if (VT.isVector()) {
5439 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5440 return FoldedVOp;
5441
5442 // fold (and x, 0) -> 0, vector edition
5443 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5444 // do not return N0, because undef node may exist in N0
5445 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
5446 SDLoc(N), N0.getValueType());
5447 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5448 // do not return N1, because undef node may exist in N1
5449 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
5450 SDLoc(N), N1.getValueType());
5451
5452 // fold (and x, -1) -> x, vector edition
5453 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5454 return N1;
5455 if (ISD::isBuildVectorAllOnes(N1.getNode()))
5456 return N0;
5457
5458 // fold (and (masked_load) (build_vec (x, ...))) to zext_masked_load
5459 auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
5460 auto *BVec = dyn_cast<BuildVectorSDNode>(N1);
5461 if (MLoad && BVec && MLoad->getExtensionType() == ISD::EXTLOAD &&
5462 N0.hasOneUse() && N1.hasOneUse()) {
5463 EVT LoadVT = MLoad->getMemoryVT();
5464 EVT ExtVT = VT;
5465 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) {
5466 // For this AND to be a zero extension of the masked load the elements
5467 // of the BuildVec must mask the bottom bits of the extended element
5468 // type
5469 if (ConstantSDNode *Splat = BVec->getConstantSplatNode()) {
5470 uint64_t ElementSize =
5471 LoadVT.getVectorElementType().getScalarSizeInBits();
5472 if (Splat->getAPIntValue().isMask(ElementSize)) {
5473 return DAG.getMaskedLoad(
5474 ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(),
5475 MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(),
5476 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(),
5477 ISD::ZEXTLOAD, MLoad->isExpandingLoad());
5478 }
5479 }
5480 }
5481 }
5482 }
5483
5484 // fold (and c1, c2) -> c1&c2
5485 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5486 if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1}))
5487 return C;
5488
5489 // canonicalize constant to RHS
5490 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5491 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5492 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
5493
5494 // fold (and x, -1) -> x
5495 if (isAllOnesConstant(N1))
5496 return N0;
5497
5498 // if (and x, c) is known to be zero, return 0
5499 unsigned BitWidth = VT.getScalarSizeInBits();
5500 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
5501 APInt::getAllOnesValue(BitWidth)))
5502 return DAG.getConstant(0, SDLoc(N), VT);
5503
5504 if (SDValue NewSel = foldBinOpIntoSelect(N))
5505 return NewSel;
5506
5507 // reassociate and
5508 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
5509 return RAND;
5510
5511 // Try to convert a constant mask AND into a shuffle clear mask.
5512 if (VT.isVector())
5513 if (SDValue Shuffle = XformToShuffleWithZero(N))
5514 return Shuffle;
5515
5516 if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
5517 return Combined;
5518
5519 // fold (and (or x, C), D) -> D if (C & D) == D
5520 auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
5521 return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
5522 };
5523 if (N0.getOpcode() == ISD::OR &&
5524 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
5525 return N1;
5526 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
5527 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5528 SDValue N0Op0 = N0.getOperand(0);
5529 APInt Mask = ~N1C->getAPIntValue();
5530 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
5531 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
5532 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
5533 N0.getValueType(), N0Op0);
5534
5535 // Replace uses of the AND with uses of the Zero extend node.
5536 CombineTo(N, Zext);
5537
5538 // We actually want to replace all uses of the any_extend with the
5539 // zero_extend, to avoid duplicating things. This will later cause this
5540 // AND to be folded.
5541 CombineTo(N0.getNode(), Zext);
5542 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5543 }
5544 }
5545
5546 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
5547 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
5548 // already be zero by virtue of the width of the base type of the load.
5549 //
5550 // the 'X' node here can either be nothing or an extract_vector_elt to catch
5551 // more cases.
5552 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5553 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
5554 N0.getOperand(0).getOpcode() == ISD::LOAD &&
5555 N0.getOperand(0).getResNo() == 0) ||
5556 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
5557 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
5558 N0 : N0.getOperand(0) );
5559
5560 // Get the constant (if applicable) the zero'th operand is being ANDed with.
5561 // This can be a pure constant or a vector splat, in which case we treat the
5562 // vector as a scalar and use the splat value.
5563 APInt Constant = APInt::getNullValue(1);
5564 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
5565 Constant = C->getAPIntValue();
5566 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
5567 APInt SplatValue, SplatUndef;
5568 unsigned SplatBitSize;
5569 bool HasAnyUndefs;
5570 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
5571 SplatBitSize, HasAnyUndefs);
5572 if (IsSplat) {
5573 // Undef bits can contribute to a possible optimisation if set, so
5574 // set them.
5575 SplatValue |= SplatUndef;
5576
5577 // The splat value may be something like "0x00FFFFFF", which means 0 for
5578 // the first vector value and FF for the rest, repeating. We need a mask
5579 // that will apply equally to all members of the vector, so AND all the
5580 // lanes of the constant together.
5581 unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits();
5582
5583 // If the splat value has been compressed to a bitlength lower
5584 // than the size of the vector lane, we need to re-expand it to
5585 // the lane size.
5586 if (EltBitWidth > SplatBitSize)
5587 for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth);
5588 SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2)
5589 SplatValue |= SplatValue.shl(SplatBitSize);
5590
5591 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
5592 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
5593 if ((SplatBitSize % EltBitWidth) == 0) {
5594 Constant = APInt::getAllOnesValue(EltBitWidth);
5595 for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i)
5596 Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth);
5597 }
5598 }
5599 }
5600
5601 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
5602 // actually legal and isn't going to get expanded, else this is a false
5603 // optimisation.
5604 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
5605 Load->getValueType(0),
5606 Load->getMemoryVT());
5607
5608 // Resize the constant to the same size as the original memory access before
5609 // extension. If it is still the AllOnesValue then this AND is completely
5610 // unneeded.
5611 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
5612
5613 bool B;
5614 switch (Load->getExtensionType()) {
5615 default: B = false; break;
5616 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
5617 case ISD::ZEXTLOAD:
5618 case ISD::NON_EXTLOAD: B = true; break;
5619 }
5620
5621 if (B && Constant.isAllOnesValue()) {
5622 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
5623 // preserve semantics once we get rid of the AND.
5624 SDValue NewLoad(Load, 0);
5625
5626 // Fold the AND away. NewLoad may get replaced immediately.
5627 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
5628
5629 if (Load->getExtensionType() == ISD::EXTLOAD) {
5630 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
5631 Load->getValueType(0), SDLoc(Load),
5632 Load->getChain(), Load->getBasePtr(),
5633 Load->getOffset(), Load->getMemoryVT(),
5634 Load->getMemOperand());
5635 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
5636 if (Load->getNumValues() == 3) {
5637 // PRE/POST_INC loads have 3 values.
5638 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
5639 NewLoad.getValue(2) };
5640 CombineTo(Load, To, 3, true);
5641 } else {
5642 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
5643 }
5644 }
5645
5646 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5647 }
5648 }
5649
5650 // fold (and (load x), 255) -> (zextload x, i8)
5651 // fold (and (extload x, i16), 255) -> (zextload x, i8)
5652 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
5653 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
5654 (N0.getOpcode() == ISD::ANY_EXTEND &&
5655 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
5656 if (SDValue Res = ReduceLoadWidth(N)) {
5657 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
5658 ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
5659 AddToWorklist(N);
5660 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
5661 return SDValue(N, 0);
5662 }
5663 }
5664
5665 if (LegalTypes) {
5666 // Attempt to propagate the AND back up to the leaves which, if they're
5667 // loads, can be combined to narrow loads and the AND node can be removed.
5668 // Perform after legalization so that extend nodes will already be
5669 // combined into the loads.
5670 if (BackwardsPropagateMask(N))
5671 return SDValue(N, 0);
5672 }
5673
5674 if (SDValue Combined = visitANDLike(N0, N1, N))
5675 return Combined;
5676
5677 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
5678 if (N0.getOpcode() == N1.getOpcode())
5679 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5680 return V;
5681
5682 // Masking the negated extension of a boolean is just the zero-extended
5683 // boolean:
5684 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
5685 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
5686 //
5687 // Note: the SimplifyDemandedBits fold below can make an information-losing
5688 // transform, and then we have no way to find this better fold.
5689 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
5690 if (isNullOrNullSplat(N0.getOperand(0))) {
5691 SDValue SubRHS = N0.getOperand(1);
5692 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5693 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5694 return SubRHS;
5695 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
5696 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5697 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
5698 }
5699 }
5700
5701 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5702 // fold (and (sra)) -> (and (srl)) when possible.
5703 if (SimplifyDemandedBits(SDValue(N, 0)))
5704 return SDValue(N, 0);
5705
5706 // fold (zext_inreg (extload x)) -> (zextload x)
5707 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
5708 if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
5709 (ISD::isEXTLoad(N0.getNode()) ||
5710 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
5711 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5712 EVT MemVT = LN0->getMemoryVT();
5713 // If we zero all the possible extended bits, then we can turn this into
5714 // a zextload if we are running before legalize or the operation is legal.
5715 unsigned ExtBitSize = N1.getScalarValueSizeInBits();
5716 unsigned MemBitSize = MemVT.getScalarSizeInBits();
5717 APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize);
5718 if (DAG.MaskedValueIsZero(N1, ExtBits) &&
5719 ((!LegalOperations && LN0->isSimple()) ||
5720 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5721 SDValue ExtLoad =
5722 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
5723 LN0->getBasePtr(), MemVT, LN0->getMemOperand());
5724 AddToWorklist(N);
5725 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5726 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5727 }
5728 }
5729
5730 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
5731 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5732 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5733 N0.getOperand(1), false))
5734 return BSwap;
5735 }
5736
5737 if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
5738 return Shifts;
5739
5740 if (TLI.hasBitTest(N0, N1))
5741 if (SDValue V = combineShiftAnd1ToBitTest(N, DAG))
5742 return V;
5743
5744 // Recognize the following pattern:
5745 //
5746 // AndVT = (and (sign_extend NarrowVT to AndVT) #bitmask)
5747 //
5748 // where bitmask is a mask that clears the upper bits of AndVT. The
5749 // number of bits in bitmask must be a power of two.
5750 auto IsAndZeroExtMask = [](SDValue LHS, SDValue RHS) {
5751 if (LHS->getOpcode() != ISD::SIGN_EXTEND)
5752 return false;
5753
5754 auto *C = dyn_cast<ConstantSDNode>(RHS);
5755 if (!C)
5756 return false;
5757
5758 if (!C->getAPIntValue().isMask(
5759 LHS.getOperand(0).getValueType().getFixedSizeInBits()))
5760 return false;
5761
5762 return true;
5763 };
5764
5765 // Replace (and (sign_extend ...) #bitmask) with (zero_extend ...).
5766 if (IsAndZeroExtMask(N0, N1))
5767 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0.getOperand(0));
5768
5769 return SDValue();
5770}
5771
5772/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5773SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
5774 bool DemandHighBits) {
5775 if (!LegalOperations)
5776 return SDValue();
5777
5778 EVT VT = N->getValueType(0);
5779 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5780 return SDValue();
5781 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5782 return SDValue();
5783
5784 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
5785 bool LookPassAnd0 = false;
5786 bool LookPassAnd1 = false;
5787 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5788 std::swap(N0, N1);
5789 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5790 std::swap(N0, N1);
5791 if (N0.getOpcode() == ISD::AND) {
5792 if (!N0.getNode()->hasOneUse())
5793 return SDValue();
5794 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5795 // Also handle 0xffff since the LHS is guaranteed to have zeros there.
5796 // This is needed for X86.
5797 if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
5798 N01C->getZExtValue() != 0xFFFF))
5799 return SDValue();
5800 N0 = N0.getOperand(0);
5801 LookPassAnd0 = true;
5802 }
5803
5804 if (N1.getOpcode() == ISD::AND) {
5805 if (!N1.getNode()->hasOneUse())
5806 return SDValue();
5807 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5808 if (!N11C || N11C->getZExtValue() != 0xFF)
5809 return SDValue();
5810 N1 = N1.getOperand(0);
5811 LookPassAnd1 = true;
5812 }
5813
5814 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5815 std::swap(N0, N1);
5816 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5817 return SDValue();
5818 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
5819 return SDValue();
5820
5821 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5822 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5823 if (!N01C || !N11C)
5824 return SDValue();
5825 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
5826 return SDValue();
5827
5828 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
5829 SDValue N00 = N0->getOperand(0);
5830 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5831 if (!N00.getNode()->hasOneUse())
5832 return SDValue();
5833 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
5834 if (!N001C || N001C->getZExtValue() != 0xFF)
5835 return SDValue();
5836 N00 = N00.getOperand(0);
5837 LookPassAnd0 = true;
5838 }
5839
5840 SDValue N10 = N1->getOperand(0);
5841 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5842 if (!N10.getNode()->hasOneUse())
5843 return SDValue();
5844 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
5845 // Also allow 0xFFFF since the bits will be shifted out. This is needed
5846 // for X86.
5847 if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
5848 N101C->getZExtValue() != 0xFFFF))
5849 return SDValue();
5850 N10 = N10.getOperand(0);
5851 LookPassAnd1 = true;
5852 }
5853
5854 if (N00 != N10)
5855 return SDValue();
5856
5857 // Make sure everything beyond the low halfword gets set to zero since the SRL
5858 // 16 will clear the top bits.
5859 unsigned OpSizeInBits = VT.getSizeInBits();
5860 if (DemandHighBits && OpSizeInBits > 16) {
5861 // If the left-shift isn't masked out then the only way this is a bswap is
5862 // if all bits beyond the low 8 are 0. In that case the entire pattern
5863 // reduces to a left shift anyway: leave it for other parts of the combiner.
5864 if (!LookPassAnd0)
5865 return SDValue();
5866
5867 // However, if the right shift isn't masked out then it might be because
5868 // it's not needed. See if we can spot that too.
5869 if (!LookPassAnd1 &&
5870 !DAG.MaskedValueIsZero(
5871 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
5872 return SDValue();
5873 }
5874
5875 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
5876 if (OpSizeInBits > 16) {
5877 SDLoc DL(N);
5878 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
5879 DAG.getConstant(OpSizeInBits - 16, DL,
5880 getShiftAmountTy(VT)));
5881 }
5882 return Res;
5883}
5884
5885/// Return true if the specified node is an element that makes up a 32-bit
5886/// packed halfword byteswap.
5887/// ((x & 0x000000ff) << 8) |
5888/// ((x & 0x0000ff00) >> 8) |
5889/// ((x & 0x00ff0000) << 8) |
5890/// ((x & 0xff000000) >> 8)
5891static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
5892 if (!N.getNode()->hasOneUse())
5893 return false;
5894
5895 unsigned Opc = N.getOpcode();
5896 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5897 return false;
5898
5899 SDValue N0 = N.getOperand(0);
5900 unsigned Opc0 = N0.getOpcode();
5901 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5902 return false;
5903
5904 ConstantSDNode *N1C = nullptr;
5905 // SHL or SRL: look upstream for AND mask operand
5906 if (Opc == ISD::AND)
5907 N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5908 else if (Opc0 == ISD::AND)
5909 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5910 if (!N1C)
5911 return false;
5912
5913 unsigned MaskByteOffset;
5914 switch (N1C->getZExtValue()) {
5915 default:
5916 return false;
5917 case 0xFF: MaskByteOffset = 0; break;
5918 case 0xFF00: MaskByteOffset = 1; break;
5919 case 0xFFFF:
5920 // In case demanded bits didn't clear the bits that will be shifted out.
5921 // This is needed for X86.
5922 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5923 MaskByteOffset = 1;
5924 break;
5925 }
5926 return false;
5927 case 0xFF0000: MaskByteOffset = 2; break;
5928 case 0xFF000000: MaskByteOffset = 3; break;
5929 }
5930
5931 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
5932 if (Opc == ISD::AND) {
5933 if (MaskByteOffset == 0 || MaskByteOffset == 2) {
5934 // (x >> 8) & 0xff
5935 // (x >> 8) & 0xff0000
5936 if (Opc0 != ISD::SRL)
5937 return false;
5938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5939 if (!C || C->getZExtValue() != 8)
5940 return false;
5941 } else {
5942 // (x << 8) & 0xff00
5943 // (x << 8) & 0xff000000
5944 if (Opc0 != ISD::SHL)
5945 return false;
5946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5947 if (!C || C->getZExtValue() != 8)
5948 return false;
5949 }
5950 } else if (Opc == ISD::SHL) {
5951 // (x & 0xff) << 8
5952 // (x & 0xff0000) << 8
5953 if (MaskByteOffset != 0 && MaskByteOffset != 2)
5954 return false;
5955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5956 if (!C || C->getZExtValue() != 8)
5957 return false;
5958 } else { // Opc == ISD::SRL
5959 // (x & 0xff00) >> 8
5960 // (x & 0xff000000) >> 8
5961 if (MaskByteOffset != 1 && MaskByteOffset != 3)
5962 return false;
5963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5964 if (!C || C->getZExtValue() != 8)
5965 return false;
5966 }
5967
5968 if (Parts[MaskByteOffset])
5969 return false;
5970
5971 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
5972 return true;
5973}
5974
5975// Match 2 elements of a packed halfword bswap.
5976static bool isBSwapHWordPair(SDValue N, MutableArrayRef<SDNode *> Parts) {
5977 if (N.getOpcode() == ISD::OR)
5978 return isBSwapHWordElement(N.getOperand(0), Parts) &&
5979 isBSwapHWordElement(N.getOperand(1), Parts);
5980
5981 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
5982 ConstantSDNode *C = isConstOrConstSplat(N.getOperand(1));
5983 if (!C || C->getAPIntValue() != 16)
5984 return false;
5985 Parts[0] = Parts[1] = N.getOperand(0).getOperand(0).getNode();
5986 return true;
5987 }
5988
5989 return false;
5990}
5991
5992// Match this pattern:
5993// (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff))
5994// And rewrite this to:
5995// (rotr (bswap A), 16)
5996static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI,
5997 SelectionDAG &DAG, SDNode *N, SDValue N0,
5998 SDValue N1, EVT VT, EVT ShiftAmountTy) {
5999 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
"MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6000, __PRETTY_FUNCTION__))
6000 "MatchBSwapHWordOrAndAnd: expecting i32")((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
"MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-12~++20201129111111+e987fbdd85d/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6000, __PRETTY_FUNCTION__))
;
6001 if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
6002 return SDValue();
6003 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
6004 return SDValue();
6005 // TODO: this is too restrictive; lifting this restriction requires more tests
6006 if (!N0->hasOneUse() || !N1->hasOneUse())
6007 return SDValue();
6008 ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
6009 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1));
6010 if (!Mask0 || !Mask1)
6011 return SDValue();
6012 if (Mask0->getAPIntValue() != 0xff00ff00 ||
6013 Mask1->getAPIntValue() != 0x00ff00ff)
6014 return SDValue();
6015 SDValue Shift0 = N0.getOperand(0);
6016 SDValue Shift1 = N1.getOperand(0);
6017 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
6018 return SDValue();
6019 ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1));
6020 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
6021 if (!ShiftAmt0 || !ShiftAmt1)
6022 return SDValue();
6023 if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8)
6024 return SDValue();
6025 if (Shift0.getOperand(0) != Shift1.getOperand(0))
6026 return SDValue();
6027
6028 SDLoc DL(N);
6029 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0));
6030 SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy);
6031 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
6032}
6033
6034/// Match a 32-bit packed halfword bswap. That is
6035/// ((x & 0x000000ff) << 8) |
6036/// ((x & 0x0000ff00) >> 8) |
6037/// ((x & 0x00ff0000) << 8) |
6038/// ((x & 0xff000000) >> 8)
6039/// => (rotl (bswap x), 16)
6040SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
6041 if (!LegalOperations)
6042 return SDValue();
6043
6044 EVT VT = N->getValueType(0);
6045 if (VT != MVT::i32)
6046 return SDValue();
6047 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
6048 return SDValue();
6049
6050 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT,
6051 getShiftAmountTy(VT)))
6052 return BSwap;
6053
6054 // Try again with commuted operands.
6055 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT,
6056 getShiftAmountTy(VT)))