Bug Summary

File:llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Warning:line 16654, column 11
Value stored to 'StartAddress' during its initialization is never read

Annotated Source Code

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clang -cc1 -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name DAGCombiner.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mframe-pointer=none -fmath-errno -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -fno-split-dwarf-inlining -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-12/lib/clang/12.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/include -I /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-12/lib/clang/12.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/build-llvm/lib/CodeGen/SelectionDAG -fdebug-prefix-map=/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b=. -ferror-limit 19 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2020-09-17-195756-12974-1 -x c++ /build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
1//===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10// both before and after the DAG is legalized.
11//
12// This pass is not a substitute for the LLVM IR instcombine pass. This pass is
13// primarily intended to handle simplification opportunities that are implicit
14// in the LLVM IR and exposed by the various codegen lowering phases.
15//
16//===----------------------------------------------------------------------===//
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/IntervalMap.h"
23#include "llvm/ADT/None.h"
24#include "llvm/ADT/Optional.h"
25#include "llvm/ADT/STLExtras.h"
26#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallPtrSet.h"
28#include "llvm/ADT/SmallSet.h"
29#include "llvm/ADT/SmallVector.h"
30#include "llvm/ADT/Statistic.h"
31#include "llvm/Analysis/AliasAnalysis.h"
32#include "llvm/Analysis/MemoryLocation.h"
33#include "llvm/Analysis/VectorUtils.h"
34#include "llvm/CodeGen/DAGCombine.h"
35#include "llvm/CodeGen/ISDOpcodes.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/CodeGen/MachineFunction.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/RuntimeLibcalls.h"
40#include "llvm/CodeGen/SelectionDAG.h"
41#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
42#include "llvm/CodeGen/SelectionDAGNodes.h"
43#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
44#include "llvm/CodeGen/TargetLowering.h"
45#include "llvm/CodeGen/TargetRegisterInfo.h"
46#include "llvm/CodeGen/TargetSubtargetInfo.h"
47#include "llvm/CodeGen/ValueTypes.h"
48#include "llvm/IR/Attributes.h"
49#include "llvm/IR/Constant.h"
50#include "llvm/IR/DataLayout.h"
51#include "llvm/IR/DerivedTypes.h"
52#include "llvm/IR/Function.h"
53#include "llvm/IR/LLVMContext.h"
54#include "llvm/IR/Metadata.h"
55#include "llvm/Support/Casting.h"
56#include "llvm/Support/CodeGen.h"
57#include "llvm/Support/CommandLine.h"
58#include "llvm/Support/Compiler.h"
59#include "llvm/Support/Debug.h"
60#include "llvm/Support/ErrorHandling.h"
61#include "llvm/Support/KnownBits.h"
62#include "llvm/Support/MachineValueType.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetMachine.h"
66#include "llvm/Target/TargetOptions.h"
67#include <algorithm>
68#include <cassert>
69#include <cstdint>
70#include <functional>
71#include <iterator>
72#include <string>
73#include <tuple>
74#include <utility>
75
76using namespace llvm;
77
78#define DEBUG_TYPE"dagcombine" "dagcombine"
79
80STATISTIC(NodesCombined , "Number of dag nodes combined")static llvm::Statistic NodesCombined = {"dagcombine", "NodesCombined"
, "Number of dag nodes combined"}
;
81STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created")static llvm::Statistic PreIndexedNodes = {"dagcombine", "PreIndexedNodes"
, "Number of pre-indexed nodes created"}
;
82STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created")static llvm::Statistic PostIndexedNodes = {"dagcombine", "PostIndexedNodes"
, "Number of post-indexed nodes created"}
;
83STATISTIC(OpsNarrowed , "Number of load/op/store narrowed")static llvm::Statistic OpsNarrowed = {"dagcombine", "OpsNarrowed"
, "Number of load/op/store narrowed"}
;
84STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int")static llvm::Statistic LdStFP2Int = {"dagcombine", "LdStFP2Int"
, "Number of fp load/store pairs transformed to int"}
;
85STATISTIC(SlicedLoads, "Number of load sliced")static llvm::Statistic SlicedLoads = {"dagcombine", "SlicedLoads"
, "Number of load sliced"}
;
86STATISTIC(NumFPLogicOpsConv, "Number of logic ops converted to fp ops")static llvm::Statistic NumFPLogicOpsConv = {"dagcombine", "NumFPLogicOpsConv"
, "Number of logic ops converted to fp ops"}
;
87
88static cl::opt<bool>
89CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
90 cl::desc("Enable DAG combiner's use of IR alias analysis"));
91
92static cl::opt<bool>
93UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
94 cl::desc("Enable DAG combiner's use of TBAA"));
95
96#ifndef NDEBUG
97static cl::opt<std::string>
98CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
99 cl::desc("Only use DAG-combiner alias analysis in this"
100 " function"));
101#endif
102
103/// Hidden option to stress test load slicing, i.e., when this option
104/// is enabled, load slicing bypasses most of its profitability guards.
105static cl::opt<bool>
106StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
107 cl::desc("Bypass the profitability model of load slicing"),
108 cl::init(false));
109
110static cl::opt<bool>
111 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
112 cl::desc("DAG combiner may split indexing from loads"));
113
114static cl::opt<bool>
115 EnableStoreMerging("combiner-store-merging", cl::Hidden, cl::init(true),
116 cl::desc("DAG combiner enable merging multiple stores "
117 "into a wider store"));
118
119static cl::opt<unsigned> TokenFactorInlineLimit(
120 "combiner-tokenfactor-inline-limit", cl::Hidden, cl::init(2048),
121 cl::desc("Limit the number of operands to inline for Token Factors"));
122
123static cl::opt<unsigned> StoreMergeDependenceLimit(
124 "combiner-store-merge-dependence-limit", cl::Hidden, cl::init(10),
125 cl::desc("Limit the number of times for the same StoreNode and RootNode "
126 "to bail out in store merging dependence check"));
127
128static cl::opt<bool> EnableReduceLoadOpStoreWidth(
129 "combiner-reduce-load-op-store-width", cl::Hidden, cl::init(true),
130 cl::desc("DAG cominber enable reducing the width of load/op/store "
131 "sequence"));
132
133static cl::opt<bool> EnableShrinkLoadReplaceStoreWithStore(
134 "combiner-shrink-load-replace-store-with-store", cl::Hidden, cl::init(true),
135 cl::desc("DAG cominber enable load/<replace bytes>/store with "
136 "a narrower store"));
137
138namespace {
139
140 class DAGCombiner {
141 SelectionDAG &DAG;
142 const TargetLowering &TLI;
143 const SelectionDAGTargetInfo *STI;
144 CombineLevel Level;
145 CodeGenOpt::Level OptLevel;
146 bool LegalDAG = false;
147 bool LegalOperations = false;
148 bool LegalTypes = false;
149 bool ForCodeSize;
150 bool DisableGenericCombines;
151
152 /// Worklist of all of the nodes that need to be simplified.
153 ///
154 /// This must behave as a stack -- new nodes to process are pushed onto the
155 /// back and when processing we pop off of the back.
156 ///
157 /// The worklist will not contain duplicates but may contain null entries
158 /// due to nodes being deleted from the underlying DAG.
159 SmallVector<SDNode *, 64> Worklist;
160
161 /// Mapping from an SDNode to its position on the worklist.
162 ///
163 /// This is used to find and remove nodes from the worklist (by nulling
164 /// them) when they are deleted from the underlying DAG. It relies on
165 /// stable indices of nodes within the worklist.
166 DenseMap<SDNode *, unsigned> WorklistMap;
167 /// This records all nodes attempted to add to the worklist since we
168 /// considered a new worklist entry. As we keep do not add duplicate nodes
169 /// in the worklist, this is different from the tail of the worklist.
170 SmallSetVector<SDNode *, 32> PruningList;
171
172 /// Set of nodes which have been combined (at least once).
173 ///
174 /// This is used to allow us to reliably add any operands of a DAG node
175 /// which have not yet been combined to the worklist.
176 SmallPtrSet<SDNode *, 32> CombinedNodes;
177
178 /// Map from candidate StoreNode to the pair of RootNode and count.
179 /// The count is used to track how many times we have seen the StoreNode
180 /// with the same RootNode bail out in dependence check. If we have seen
181 /// the bail out for the same pair many times over a limit, we won't
182 /// consider the StoreNode with the same RootNode as store merging
183 /// candidate again.
184 DenseMap<SDNode *, std::pair<SDNode *, unsigned>> StoreRootCountMap;
185
186 // AA - Used for DAG load/store alias analysis.
187 AliasAnalysis *AA;
188
189 /// When an instruction is simplified, add all users of the instruction to
190 /// the work lists because they might get more simplified now.
191 void AddUsersToWorklist(SDNode *N) {
192 for (SDNode *Node : N->uses())
193 AddToWorklist(Node);
194 }
195
196 /// Convenient shorthand to add a node and all of its user to the worklist.
197 void AddToWorklistWithUsers(SDNode *N) {
198 AddUsersToWorklist(N);
199 AddToWorklist(N);
200 }
201
202 // Prune potentially dangling nodes. This is called after
203 // any visit to a node, but should also be called during a visit after any
204 // failed combine which may have created a DAG node.
205 void clearAddedDanglingWorklistEntries() {
206 // Check any nodes added to the worklist to see if they are prunable.
207 while (!PruningList.empty()) {
208 auto *N = PruningList.pop_back_val();
209 if (N->use_empty())
210 recursivelyDeleteUnusedNodes(N);
211 }
212 }
213
214 SDNode *getNextWorklistEntry() {
215 // Before we do any work, remove nodes that are not in use.
216 clearAddedDanglingWorklistEntries();
217 SDNode *N = nullptr;
218 // The Worklist holds the SDNodes in order, but it may contain null
219 // entries.
220 while (!N && !Worklist.empty()) {
221 N = Worklist.pop_back_val();
222 }
223
224 if (N) {
225 bool GoodWorklistEntry = WorklistMap.erase(N);
226 (void)GoodWorklistEntry;
227 assert(GoodWorklistEntry &&((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 228, __PRETTY_FUNCTION__))
228 "Found a worklist entry without a corresponding map entry!")((GoodWorklistEntry && "Found a worklist entry without a corresponding map entry!"
) ? static_cast<void> (0) : __assert_fail ("GoodWorklistEntry && \"Found a worklist entry without a corresponding map entry!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 228, __PRETTY_FUNCTION__))
;
229 }
230 return N;
231 }
232
233 /// Call the node-specific routine that folds each particular type of node.
234 SDValue visit(SDNode *N);
235
236 public:
237 DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
238 : DAG(D), TLI(D.getTargetLoweringInfo()),
239 STI(D.getSubtarget().getSelectionDAGInfo()),
240 Level(BeforeLegalizeTypes), OptLevel(OL), AA(AA) {
241 ForCodeSize = DAG.shouldOptForSize();
242 DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel);
243
244 MaximumLegalStoreInBits = 0;
245 // We use the minimum store size here, since that's all we can guarantee
246 // for the scalable vector types.
247 for (MVT VT : MVT::all_valuetypes())
248 if (EVT(VT).isSimple() && VT != MVT::Other &&
249 TLI.isTypeLegal(EVT(VT)) &&
250 VT.getSizeInBits().getKnownMinSize() >= MaximumLegalStoreInBits)
251 MaximumLegalStoreInBits = VT.getSizeInBits().getKnownMinSize();
252 }
253
254 void ConsiderForPruning(SDNode *N) {
255 // Mark this for potential pruning.
256 PruningList.insert(N);
257 }
258
259 /// Add to the worklist making sure its instance is at the back (next to be
260 /// processed.)
261 void AddToWorklist(SDNode *N) {
262 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 263, __PRETTY_FUNCTION__))
263 "Deleted Node added to Worklist")((N->getOpcode() != ISD::DELETED_NODE && "Deleted Node added to Worklist"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Deleted Node added to Worklist\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 263, __PRETTY_FUNCTION__))
;
264
265 // Skip handle nodes as they can't usefully be combined and confuse the
266 // zero-use deletion strategy.
267 if (N->getOpcode() == ISD::HANDLENODE)
268 return;
269
270 ConsiderForPruning(N);
271
272 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
273 Worklist.push_back(N);
274 }
275
276 /// Remove all instances of N from the worklist.
277 void removeFromWorklist(SDNode *N) {
278 CombinedNodes.erase(N);
279 PruningList.remove(N);
280 StoreRootCountMap.erase(N);
281
282 auto It = WorklistMap.find(N);
283 if (It == WorklistMap.end())
284 return; // Not in the worklist.
285
286 // Null out the entry rather than erasing it to avoid a linear operation.
287 Worklist[It->second] = nullptr;
288 WorklistMap.erase(It);
289 }
290
291 void deleteAndRecombine(SDNode *N);
292 bool recursivelyDeleteUnusedNodes(SDNode *N);
293
294 /// Replaces all uses of the results of one DAG node with new values.
295 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
296 bool AddTo = true);
297
298 /// Replaces all uses of the results of one DAG node with new values.
299 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
300 return CombineTo(N, &Res, 1, AddTo);
301 }
302
303 /// Replaces all uses of the results of one DAG node with new values.
304 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
305 bool AddTo = true) {
306 SDValue To[] = { Res0, Res1 };
307 return CombineTo(N, To, 2, AddTo);
308 }
309
310 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
311
312 private:
313 unsigned MaximumLegalStoreInBits;
314
315 /// Check the specified integer node value to see if it can be simplified or
316 /// if things it uses can be simplified by bit propagation.
317 /// If so, return true.
318 bool SimplifyDemandedBits(SDValue Op) {
319 unsigned BitWidth = Op.getScalarValueSizeInBits();
320 APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
321 return SimplifyDemandedBits(Op, DemandedBits);
322 }
323
324 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) {
325 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
326 KnownBits Known;
327 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, Known, TLO, 0, false))
328 return false;
329
330 // Revisit the node.
331 AddToWorklist(Op.getNode());
332
333 CommitTargetLoweringOpt(TLO);
334 return true;
335 }
336
337 /// Check the specified vector node value to see if it can be simplified or
338 /// if things it uses can be simplified as it only uses some of the
339 /// elements. If so, return true.
340 bool SimplifyDemandedVectorElts(SDValue Op) {
341 // TODO: For now just pretend it cannot be simplified.
342 if (Op.getValueType().isScalableVector())
343 return false;
344
345 unsigned NumElts = Op.getValueType().getVectorNumElements();
346 APInt DemandedElts = APInt::getAllOnesValue(NumElts);
347 return SimplifyDemandedVectorElts(Op, DemandedElts);
348 }
349
350 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
351 const APInt &DemandedElts,
352 bool AssumeSingleUse = false);
353 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
354 bool AssumeSingleUse = false);
355
356 bool CombineToPreIndexedLoadStore(SDNode *N);
357 bool CombineToPostIndexedLoadStore(SDNode *N);
358 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
359 bool SliceUpLoad(SDNode *N);
360
361 // Scalars have size 0 to distinguish from singleton vectors.
362 SDValue ForwardStoreValueToDirectLoad(LoadSDNode *LD);
363 bool getTruncatedStoreValue(StoreSDNode *ST, SDValue &Val);
364 bool extendLoadedValueToExtension(LoadSDNode *LD, SDValue &Val);
365
366 /// Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
367 /// load.
368 ///
369 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
370 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
371 /// \param EltNo index of the vector element to load.
372 /// \param OriginalLoad load that EVE came from to be replaced.
373 /// \returns EVE on success SDValue() on failure.
374 SDValue scalarizeExtractedVectorLoad(SDNode *EVE, EVT InVecVT,
375 SDValue EltNo,
376 LoadSDNode *OriginalLoad);
377 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
378 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
379 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
380 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
381 SDValue PromoteIntBinOp(SDValue Op);
382 SDValue PromoteIntShiftOp(SDValue Op);
383 SDValue PromoteExtend(SDValue Op);
384 bool PromoteLoad(SDValue Op);
385
386 /// Call the node-specific routine that knows how to fold each
387 /// particular type of node. If that doesn't do anything, try the
388 /// target-specific DAG combines.
389 SDValue combine(SDNode *N);
390
391 // Visitation implementation - Implement dag node combining for different
392 // node types. The semantics are as follows:
393 // Return Value:
394 // SDValue.getNode() == 0 - No change was made
395 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
396 // otherwise - N should be replaced by the returned Operand.
397 //
398 SDValue visitTokenFactor(SDNode *N);
399 SDValue visitMERGE_VALUES(SDNode *N);
400 SDValue visitADD(SDNode *N);
401 SDValue visitADDLike(SDNode *N);
402 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
403 SDValue visitSUB(SDNode *N);
404 SDValue visitADDSAT(SDNode *N);
405 SDValue visitSUBSAT(SDNode *N);
406 SDValue visitADDC(SDNode *N);
407 SDValue visitADDO(SDNode *N);
408 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
409 SDValue visitSUBC(SDNode *N);
410 SDValue visitSUBO(SDNode *N);
411 SDValue visitADDE(SDNode *N);
412 SDValue visitADDCARRY(SDNode *N);
413 SDValue visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn, SDNode *N);
414 SDValue visitSUBE(SDNode *N);
415 SDValue visitSUBCARRY(SDNode *N);
416 SDValue visitMUL(SDNode *N);
417 SDValue visitMULFIX(SDNode *N);
418 SDValue useDivRem(SDNode *N);
419 SDValue visitSDIV(SDNode *N);
420 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
421 SDValue visitUDIV(SDNode *N);
422 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
423 SDValue visitREM(SDNode *N);
424 SDValue visitMULHU(SDNode *N);
425 SDValue visitMULHS(SDNode *N);
426 SDValue visitSMUL_LOHI(SDNode *N);
427 SDValue visitUMUL_LOHI(SDNode *N);
428 SDValue visitMULO(SDNode *N);
429 SDValue visitIMINMAX(SDNode *N);
430 SDValue visitAND(SDNode *N);
431 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
432 SDValue visitOR(SDNode *N);
433 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
434 SDValue visitXOR(SDNode *N);
435 SDValue SimplifyVBinOp(SDNode *N);
436 SDValue visitSHL(SDNode *N);
437 SDValue visitSRA(SDNode *N);
438 SDValue visitSRL(SDNode *N);
439 SDValue visitFunnelShift(SDNode *N);
440 SDValue visitRotate(SDNode *N);
441 SDValue visitABS(SDNode *N);
442 SDValue visitBSWAP(SDNode *N);
443 SDValue visitBITREVERSE(SDNode *N);
444 SDValue visitCTLZ(SDNode *N);
445 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
446 SDValue visitCTTZ(SDNode *N);
447 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
448 SDValue visitCTPOP(SDNode *N);
449 SDValue visitSELECT(SDNode *N);
450 SDValue visitVSELECT(SDNode *N);
451 SDValue visitSELECT_CC(SDNode *N);
452 SDValue visitSETCC(SDNode *N);
453 SDValue visitSETCCCARRY(SDNode *N);
454 SDValue visitSIGN_EXTEND(SDNode *N);
455 SDValue visitZERO_EXTEND(SDNode *N);
456 SDValue visitANY_EXTEND(SDNode *N);
457 SDValue visitAssertExt(SDNode *N);
458 SDValue visitAssertAlign(SDNode *N);
459 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
460 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
461 SDValue visitZERO_EXTEND_VECTOR_INREG(SDNode *N);
462 SDValue visitTRUNCATE(SDNode *N);
463 SDValue visitBITCAST(SDNode *N);
464 SDValue visitFREEZE(SDNode *N);
465 SDValue visitBUILD_PAIR(SDNode *N);
466 SDValue visitFADD(SDNode *N);
467 SDValue visitSTRICT_FADD(SDNode *N);
468 SDValue visitFSUB(SDNode *N);
469 SDValue visitFMUL(SDNode *N);
470 SDValue visitFMA(SDNode *N);
471 SDValue visitFDIV(SDNode *N);
472 SDValue visitFREM(SDNode *N);
473 SDValue visitFSQRT(SDNode *N);
474 SDValue visitFCOPYSIGN(SDNode *N);
475 SDValue visitFPOW(SDNode *N);
476 SDValue visitSINT_TO_FP(SDNode *N);
477 SDValue visitUINT_TO_FP(SDNode *N);
478 SDValue visitFP_TO_SINT(SDNode *N);
479 SDValue visitFP_TO_UINT(SDNode *N);
480 SDValue visitFP_ROUND(SDNode *N);
481 SDValue visitFP_EXTEND(SDNode *N);
482 SDValue visitFNEG(SDNode *N);
483 SDValue visitFABS(SDNode *N);
484 SDValue visitFCEIL(SDNode *N);
485 SDValue visitFTRUNC(SDNode *N);
486 SDValue visitFFLOOR(SDNode *N);
487 SDValue visitFMINNUM(SDNode *N);
488 SDValue visitFMAXNUM(SDNode *N);
489 SDValue visitFMINIMUM(SDNode *N);
490 SDValue visitFMAXIMUM(SDNode *N);
491 SDValue visitBRCOND(SDNode *N);
492 SDValue visitBR_CC(SDNode *N);
493 SDValue visitLOAD(SDNode *N);
494
495 SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
496 SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
497
498 SDValue visitSTORE(SDNode *N);
499 SDValue visitLIFETIME_END(SDNode *N);
500 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
501 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
502 SDValue visitBUILD_VECTOR(SDNode *N);
503 SDValue visitCONCAT_VECTORS(SDNode *N);
504 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
505 SDValue visitVECTOR_SHUFFLE(SDNode *N);
506 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
507 SDValue visitINSERT_SUBVECTOR(SDNode *N);
508 SDValue visitMLOAD(SDNode *N);
509 SDValue visitMSTORE(SDNode *N);
510 SDValue visitMGATHER(SDNode *N);
511 SDValue visitMSCATTER(SDNode *N);
512 SDValue visitFP_TO_FP16(SDNode *N);
513 SDValue visitFP16_TO_FP(SDNode *N);
514 SDValue visitVECREDUCE(SDNode *N);
515
516 SDValue visitFADDForFMACombine(SDNode *N);
517 SDValue visitFSUBForFMACombine(SDNode *N);
518 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
519
520 SDValue XformToShuffleWithZero(SDNode *N);
521 bool reassociationCanBreakAddressingModePattern(unsigned Opc,
522 const SDLoc &DL, SDValue N0,
523 SDValue N1);
524 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
525 SDValue N1);
526 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
527 SDValue N1, SDNodeFlags Flags);
528
529 SDValue visitShiftByConstant(SDNode *N);
530
531 SDValue foldSelectOfConstants(SDNode *N);
532 SDValue foldVSelectOfConstants(SDNode *N);
533 SDValue foldBinOpIntoSelect(SDNode *BO);
534 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
535 SDValue hoistLogicOpWithSameOpcodeHands(SDNode *N);
536 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
537 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
538 SDValue N2, SDValue N3, ISD::CondCode CC,
539 bool NotExtCompare = false);
540 SDValue convertSelectOfFPConstantsToLoadOffset(
541 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
542 ISD::CondCode CC);
543 SDValue foldSignChangeInBitcast(SDNode *N);
544 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
545 SDValue N2, SDValue N3, ISD::CondCode CC);
546 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
547 const SDLoc &DL);
548 SDValue unfoldMaskedMerge(SDNode *N);
549 SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
550 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
551 const SDLoc &DL, bool foldBooleans);
552 SDValue rebuildSetCC(SDValue N);
553
554 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
555 SDValue &CC, bool MatchStrict = false) const;
556 bool isOneUseSetCC(SDValue N) const;
557
558 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
559 unsigned HiOp);
560 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
561 SDValue CombineExtLoad(SDNode *N);
562 SDValue CombineZExtLogicopShiftLoad(SDNode *N);
563 SDValue combineRepeatedFPDivisors(SDNode *N);
564 SDValue combineInsertEltToShuffle(SDNode *N, unsigned InsIndex);
565 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
566 SDValue BuildSDIV(SDNode *N);
567 SDValue BuildSDIVPow2(SDNode *N);
568 SDValue BuildUDIV(SDNode *N);
569 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
570 SDValue BuildDivEstimate(SDValue N, SDValue Op, SDNodeFlags Flags);
571 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
572 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
573 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
574 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
575 SDNodeFlags Flags, bool Reciprocal);
576 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
577 SDNodeFlags Flags, bool Reciprocal);
578 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
579 bool DemandHighBits = true);
580 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
581 SDValue MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
582 SDValue InnerPos, SDValue InnerNeg,
583 unsigned PosOpcode, unsigned NegOpcode,
584 const SDLoc &DL);
585 SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
586 SDValue InnerPos, SDValue InnerNeg,
587 unsigned PosOpcode, unsigned NegOpcode,
588 const SDLoc &DL);
589 SDValue MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
590 SDValue MatchLoadCombine(SDNode *N);
591 SDValue mergeTruncStores(StoreSDNode *N);
592 SDValue ReduceLoadWidth(SDNode *N);
593 SDValue ReduceLoadOpStoreWidth(SDNode *N);
594 SDValue splitMergedValStore(StoreSDNode *ST);
595 SDValue TransformFPLoadStorePair(SDNode *N);
596 SDValue convertBuildVecZextToZext(SDNode *N);
597 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
598 SDValue reduceBuildVecTruncToBitCast(SDNode *N);
599 SDValue reduceBuildVecToShuffle(SDNode *N);
600 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
601 ArrayRef<int> VectorMask, SDValue VecIn1,
602 SDValue VecIn2, unsigned LeftIdx,
603 bool DidSplitVec);
604 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
605
606 /// Walk up chain skipping non-aliasing memory nodes,
607 /// looking for aliasing nodes and adding them to the Aliases vector.
608 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
609 SmallVectorImpl<SDValue> &Aliases);
610
611 /// Return true if there is any possibility that the two addresses overlap.
612 bool isAlias(SDNode *Op0, SDNode *Op1) const;
613
614 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
615 /// chain (aliasing node.)
616 SDValue FindBetterChain(SDNode *N, SDValue Chain);
617
618 /// Try to replace a store and any possibly adjacent stores on
619 /// consecutive chains with better chains. Return true only if St is
620 /// replaced.
621 ///
622 /// Notice that other chains may still be replaced even if the function
623 /// returns false.
624 bool findBetterNeighborChains(StoreSDNode *St);
625
626 // Helper for findBetterNeighborChains. Walk up store chain add additional
627 // chained stores that do not overlap and can be parallelized.
628 bool parallelizeChainedStores(StoreSDNode *St);
629
630 /// Holds a pointer to an LSBaseSDNode as well as information on where it
631 /// is located in a sequence of memory operations connected by a chain.
632 struct MemOpLink {
633 // Ptr to the mem node.
634 LSBaseSDNode *MemNode;
635
636 // Offset from the base ptr.
637 int64_t OffsetFromBase;
638
639 MemOpLink(LSBaseSDNode *N, int64_t Offset)
640 : MemNode(N), OffsetFromBase(Offset) {}
641 };
642
643 // Classify the origin of a stored value.
644 enum class StoreSource { Unknown, Constant, Extract, Load };
645 StoreSource getStoreSource(SDValue StoreVal) {
646 switch (StoreVal.getOpcode()) {
647 case ISD::Constant:
648 case ISD::ConstantFP:
649 return StoreSource::Constant;
650 case ISD::EXTRACT_VECTOR_ELT:
651 case ISD::EXTRACT_SUBVECTOR:
652 return StoreSource::Extract;
653 case ISD::LOAD:
654 return StoreSource::Load;
655 default:
656 return StoreSource::Unknown;
657 }
658 }
659
660 /// This is a helper function for visitMUL to check the profitability
661 /// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
662 /// MulNode is the original multiply, AddNode is (add x, c1),
663 /// and ConstNode is c2.
664 bool isMulAddWithConstProfitable(SDNode *MulNode,
665 SDValue &AddNode,
666 SDValue &ConstNode);
667
668 /// This is a helper function for visitAND and visitZERO_EXTEND. Returns
669 /// true if the (and (load x) c) pattern matches an extload. ExtVT returns
670 /// the type of the loaded value to be extended.
671 bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
672 EVT LoadResultTy, EVT &ExtVT);
673
674 /// Helper function to calculate whether the given Load/Store can have its
675 /// width reduced to ExtVT.
676 bool isLegalNarrowLdSt(LSBaseSDNode *LDSTN, ISD::LoadExtType ExtType,
677 EVT &MemVT, unsigned ShAmt = 0);
678
679 /// Used by BackwardsPropagateMask to find suitable loads.
680 bool SearchForAndLoads(SDNode *N, SmallVectorImpl<LoadSDNode*> &Loads,
681 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
682 ConstantSDNode *Mask, SDNode *&NodeToMask);
683 /// Attempt to propagate a given AND node back to load leaves so that they
684 /// can be combined into narrow loads.
685 bool BackwardsPropagateMask(SDNode *N);
686
687 /// Helper function for mergeConsecutiveStores which merges the component
688 /// store chains.
689 SDValue getMergeStoreChains(SmallVectorImpl<MemOpLink> &StoreNodes,
690 unsigned NumStores);
691
692 /// This is a helper function for mergeConsecutiveStores. When the source
693 /// elements of the consecutive stores are all constants or all extracted
694 /// vector elements, try to merge them into one larger store introducing
695 /// bitcasts if necessary. \return True if a merged store was created.
696 bool mergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
697 EVT MemVT, unsigned NumStores,
698 bool IsConstantSrc, bool UseVector,
699 bool UseTrunc);
700
701 /// This is a helper function for mergeConsecutiveStores. Stores that
702 /// potentially may be merged with St are placed in StoreNodes. RootNode is
703 /// a chain predecessor to all store candidates.
704 void getStoreMergeCandidates(StoreSDNode *St,
705 SmallVectorImpl<MemOpLink> &StoreNodes,
706 SDNode *&Root);
707
708 /// Helper function for mergeConsecutiveStores. Checks if candidate stores
709 /// have indirect dependency through their operands. RootNode is the
710 /// predecessor to all stores calculated by getStoreMergeCandidates and is
711 /// used to prune the dependency check. \return True if safe to merge.
712 bool checkMergeStoreCandidatesForDependencies(
713 SmallVectorImpl<MemOpLink> &StoreNodes, unsigned NumStores,
714 SDNode *RootNode);
715
716 /// This is a helper function for mergeConsecutiveStores. Given a list of
717 /// store candidates, find the first N that are consecutive in memory.
718 /// Returns 0 if there are not at least 2 consecutive stores to try merging.
719 unsigned getConsecutiveStores(SmallVectorImpl<MemOpLink> &StoreNodes,
720 int64_t ElementSizeBytes) const;
721
722 /// This is a helper function for mergeConsecutiveStores. It is used for
723 /// store chains that are composed entirely of constant values.
724 bool tryStoreMergeOfConstants(SmallVectorImpl<MemOpLink> &StoreNodes,
725 unsigned NumConsecutiveStores,
726 EVT MemVT, SDNode *Root, bool AllowVectors);
727
728 /// This is a helper function for mergeConsecutiveStores. It is used for
729 /// store chains that are composed entirely of extracted vector elements.
730 /// When extracting multiple vector elements, try to store them in one
731 /// vector store rather than a sequence of scalar stores.
732 bool tryStoreMergeOfExtracts(SmallVectorImpl<MemOpLink> &StoreNodes,
733 unsigned NumConsecutiveStores, EVT MemVT,
734 SDNode *Root);
735
736 /// This is a helper function for mergeConsecutiveStores. It is used for
737 /// store chains that are composed entirely of loaded values.
738 bool tryStoreMergeOfLoads(SmallVectorImpl<MemOpLink> &StoreNodes,
739 unsigned NumConsecutiveStores, EVT MemVT,
740 SDNode *Root, bool AllowVectors,
741 bool IsNonTemporalStore, bool IsNonTemporalLoad);
742
743 /// Merge consecutive store operations into a wide store.
744 /// This optimization uses wide integers or vectors when possible.
745 /// \return true if stores were merged.
746 bool mergeConsecutiveStores(StoreSDNode *St);
747
748 /// Try to transform a truncation where C is a constant:
749 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
750 ///
751 /// \p N needs to be a truncation and its first operand an AND. Other
752 /// requirements are checked by the function (e.g. that trunc is
753 /// single-use) and if missed an empty SDValue is returned.
754 SDValue distributeTruncateThroughAnd(SDNode *N);
755
756 /// Helper function to determine whether the target supports operation
757 /// given by \p Opcode for type \p VT, that is, whether the operation
758 /// is legal or custom before legalizing operations, and whether is
759 /// legal (but not custom) after legalization.
760 bool hasOperation(unsigned Opcode, EVT VT) {
761 return TLI.isOperationLegalOrCustom(Opcode, VT, LegalOperations);
762 }
763
764 public:
765 /// Runs the dag combiner on all nodes in the work list
766 void Run(CombineLevel AtLevel);
767
768 SelectionDAG &getDAG() const { return DAG; }
769
770 /// Returns a type large enough to hold any valid shift amount - before type
771 /// legalization these can be huge.
772 EVT getShiftAmountTy(EVT LHSTy) {
773 assert(LHSTy.isInteger() && "Shift amount is not an integer type!")((LHSTy.isInteger() && "Shift amount is not an integer type!"
) ? static_cast<void> (0) : __assert_fail ("LHSTy.isInteger() && \"Shift amount is not an integer type!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 773, __PRETTY_FUNCTION__))
;
774 return TLI.getShiftAmountTy(LHSTy, DAG.getDataLayout(), LegalTypes);
775 }
776
777 /// This method returns true if we are running before type legalization or
778 /// if the specified VT is legal.
779 bool isTypeLegal(const EVT &VT) {
780 if (!LegalTypes) return true;
781 return TLI.isTypeLegal(VT);
782 }
783
784 /// Convenience wrapper around TargetLowering::getSetCCResultType
785 EVT getSetCCResultType(EVT VT) const {
786 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
787 }
788
789 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
790 SDValue OrigLoad, SDValue ExtLoad,
791 ISD::NodeType ExtType);
792 };
793
794/// This class is a DAGUpdateListener that removes any deleted
795/// nodes from the worklist.
796class WorklistRemover : public SelectionDAG::DAGUpdateListener {
797 DAGCombiner &DC;
798
799public:
800 explicit WorklistRemover(DAGCombiner &dc)
801 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
802
803 void NodeDeleted(SDNode *N, SDNode *E) override {
804 DC.removeFromWorklist(N);
805 }
806};
807
808class WorklistInserter : public SelectionDAG::DAGUpdateListener {
809 DAGCombiner &DC;
810
811public:
812 explicit WorklistInserter(DAGCombiner &dc)
813 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
814
815 // FIXME: Ideally we could add N to the worklist, but this causes exponential
816 // compile time costs in large DAGs, e.g. Halide.
817 void NodeInserted(SDNode *N) override { DC.ConsiderForPruning(N); }
818};
819
820} // end anonymous namespace
821
822//===----------------------------------------------------------------------===//
823// TargetLowering::DAGCombinerInfo implementation
824//===----------------------------------------------------------------------===//
825
826void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
827 ((DAGCombiner*)DC)->AddToWorklist(N);
828}
829
830SDValue TargetLowering::DAGCombinerInfo::
831CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
832 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
833}
834
835SDValue TargetLowering::DAGCombinerInfo::
836CombineTo(SDNode *N, SDValue Res, bool AddTo) {
837 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
838}
839
840SDValue TargetLowering::DAGCombinerInfo::
841CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
842 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
843}
844
845bool TargetLowering::DAGCombinerInfo::
846recursivelyDeleteUnusedNodes(SDNode *N) {
847 return ((DAGCombiner*)DC)->recursivelyDeleteUnusedNodes(N);
848}
849
850void TargetLowering::DAGCombinerInfo::
851CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
852 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
853}
854
855//===----------------------------------------------------------------------===//
856// Helper Functions
857//===----------------------------------------------------------------------===//
858
859void DAGCombiner::deleteAndRecombine(SDNode *N) {
860 removeFromWorklist(N);
861
862 // If the operands of this node are only used by the node, they will now be
863 // dead. Make sure to re-visit them and recursively delete dead nodes.
864 for (const SDValue &Op : N->ops())
865 // For an operand generating multiple values, one of the values may
866 // become dead allowing further simplification (e.g. split index
867 // arithmetic from an indexed load).
868 if (Op->hasOneUse() || Op->getNumValues() > 1)
869 AddToWorklist(Op.getNode());
870
871 DAG.DeleteNode(N);
872}
873
874// APInts must be the same size for most operations, this helper
875// function zero extends the shorter of the pair so that they match.
876// We provide an Offset so that we can create bitwidths that won't overflow.
877static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
878 unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
879 LHS = LHS.zextOrSelf(Bits);
880 RHS = RHS.zextOrSelf(Bits);
881}
882
883// Return true if this node is a setcc, or is a select_cc
884// that selects between the target values used for true and false, making it
885// equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
886// the appropriate nodes based on the type of node we are checking. This
887// simplifies life a bit for the callers.
888bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
889 SDValue &CC, bool MatchStrict) const {
890 if (N.getOpcode() == ISD::SETCC) {
891 LHS = N.getOperand(0);
892 RHS = N.getOperand(1);
893 CC = N.getOperand(2);
894 return true;
895 }
896
897 if (MatchStrict &&
898 (N.getOpcode() == ISD::STRICT_FSETCC ||
899 N.getOpcode() == ISD::STRICT_FSETCCS)) {
900 LHS = N.getOperand(1);
901 RHS = N.getOperand(2);
902 CC = N.getOperand(3);
903 return true;
904 }
905
906 if (N.getOpcode() != ISD::SELECT_CC ||
907 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
908 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
909 return false;
910
911 if (TLI.getBooleanContents(N.getValueType()) ==
912 TargetLowering::UndefinedBooleanContent)
913 return false;
914
915 LHS = N.getOperand(0);
916 RHS = N.getOperand(1);
917 CC = N.getOperand(4);
918 return true;
919}
920
921/// Return true if this is a SetCC-equivalent operation with only one use.
922/// If this is true, it allows the users to invert the operation for free when
923/// it is profitable to do so.
924bool DAGCombiner::isOneUseSetCC(SDValue N) const {
925 SDValue N0, N1, N2;
926 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
927 return true;
928 return false;
929}
930
931// Returns the SDNode if it is a constant float BuildVector
932// or constant float.
933static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
934 if (isa<ConstantFPSDNode>(N))
935 return N.getNode();
936 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
937 return N.getNode();
938 return nullptr;
939}
940
941// Determines if it is a constant integer or a build vector of constant
942// integers (and undefs).
943// Do not permit build vector implicit truncation.
944static bool isConstantOrConstantVector(SDValue N, bool NoOpaques = false) {
945 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N))
946 return !(Const->isOpaque() && NoOpaques);
947 if (N.getOpcode() != ISD::BUILD_VECTOR)
948 return false;
949 unsigned BitWidth = N.getScalarValueSizeInBits();
950 for (const SDValue &Op : N->op_values()) {
951 if (Op.isUndef())
952 continue;
953 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Op);
954 if (!Const || Const->getAPIntValue().getBitWidth() != BitWidth ||
955 (Const->isOpaque() && NoOpaques))
956 return false;
957 }
958 return true;
959}
960
961// Determines if a BUILD_VECTOR is composed of all-constants possibly mixed with
962// undef's.
963static bool isAnyConstantBuildVector(SDValue V, bool NoOpaques = false) {
964 if (V.getOpcode() != ISD::BUILD_VECTOR)
965 return false;
966 return isConstantOrConstantVector(V, NoOpaques) ||
967 ISD::isBuildVectorOfConstantFPSDNodes(V.getNode());
968}
969
970// Determine if this an indexed load with an opaque target constant index.
971static bool canSplitIdx(LoadSDNode *LD) {
972 return MaySplitLoadIndex &&
973 (LD->getOperand(2).getOpcode() != ISD::TargetConstant ||
974 !cast<ConstantSDNode>(LD->getOperand(2))->isOpaque());
975}
976
977bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
978 const SDLoc &DL,
979 SDValue N0,
980 SDValue N1) {
981 // Currently this only tries to ensure we don't undo the GEP splits done by
982 // CodeGenPrepare when shouldConsiderGEPOffsetSplit is true. To ensure this,
983 // we check if the following transformation would be problematic:
984 // (load/store (add, (add, x, offset1), offset2)) ->
985 // (load/store (add, x, offset1+offset2)).
986
987 if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD)
988 return false;
989
990 if (N0.hasOneUse())
991 return false;
992
993 auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
994 auto *C2 = dyn_cast<ConstantSDNode>(N1);
995 if (!C1 || !C2)
996 return false;
997
998 const APInt &C1APIntVal = C1->getAPIntValue();
999 const APInt &C2APIntVal = C2->getAPIntValue();
1000 if (C1APIntVal.getBitWidth() > 64 || C2APIntVal.getBitWidth() > 64)
1001 return false;
1002
1003 const APInt CombinedValueIntVal = C1APIntVal + C2APIntVal;
1004 if (CombinedValueIntVal.getBitWidth() > 64)
1005 return false;
1006 const int64_t CombinedValue = CombinedValueIntVal.getSExtValue();
1007
1008 for (SDNode *Node : N0->uses()) {
1009 auto LoadStore = dyn_cast<MemSDNode>(Node);
1010 if (LoadStore) {
1011 // Is x[offset2] already not a legal addressing mode? If so then
1012 // reassociating the constants breaks nothing (we test offset2 because
1013 // that's the one we hope to fold into the load or store).
1014 TargetLoweringBase::AddrMode AM;
1015 AM.HasBaseReg = true;
1016 AM.BaseOffs = C2APIntVal.getSExtValue();
1017 EVT VT = LoadStore->getMemoryVT();
1018 unsigned AS = LoadStore->getAddressSpace();
1019 Type *AccessTy = VT.getTypeForEVT(*DAG.getContext());
1020 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1021 continue;
1022
1023 // Would x[offset1+offset2] still be a legal addressing mode?
1024 AM.BaseOffs = CombinedValue;
1025 if (!TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, AS))
1026 return true;
1027 }
1028 }
1029
1030 return false;
1031}
1032
1033// Helper for DAGCombiner::reassociateOps. Try to reassociate an expression
1034// such as (Opc N0, N1), if \p N0 is the same kind of operation as \p Opc.
1035SDValue DAGCombiner::reassociateOpsCommutative(unsigned Opc, const SDLoc &DL,
1036 SDValue N0, SDValue N1) {
1037 EVT VT = N0.getValueType();
1038
1039 if (N0.getOpcode() != Opc)
1040 return SDValue();
1041
1042 if (DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
1043 if (DAG.isConstantIntBuildVectorOrConstantInt(N1)) {
1044 // Reassociate: (op (op x, c1), c2) -> (op x, (op c1, c2))
1045 if (SDValue OpNode =
1046 DAG.FoldConstantArithmetic(Opc, DL, VT, {N0.getOperand(1), N1}))
1047 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
1048 return SDValue();
1049 }
1050 if (N0.hasOneUse()) {
1051 // Reassociate: (op (op x, c1), y) -> (op (op x, y), c1)
1052 // iff (op x, c1) has one use
1053 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
1054 if (!OpNode.getNode())
1055 return SDValue();
1056 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
1057 }
1058 }
1059 return SDValue();
1060}
1061
1062// Try to reassociate commutative binops.
1063SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1064 SDValue N1, SDNodeFlags Flags) {
1065 assert(TLI.isCommutativeBinOp(Opc) && "Operation not commutative.")((TLI.isCommutativeBinOp(Opc) && "Operation not commutative."
) ? static_cast<void> (0) : __assert_fail ("TLI.isCommutativeBinOp(Opc) && \"Operation not commutative.\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1065, __PRETTY_FUNCTION__))
;
1066
1067 // Floating-point reassociation is not allowed without loose FP math.
1068 if (N0.getValueType().isFloatingPoint() ||
1069 N1.getValueType().isFloatingPoint())
1070 if (!Flags.hasAllowReassociation() || !Flags.hasNoSignedZeros())
1071 return SDValue();
1072
1073 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1))
1074 return Combined;
1075 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0))
1076 return Combined;
1077 return SDValue();
1078}
1079
1080SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
1081 bool AddTo) {
1082 assert(N->getNumValues() == NumTo && "Broken CombineTo call!")((N->getNumValues() == NumTo && "Broken CombineTo call!"
) ? static_cast<void> (0) : __assert_fail ("N->getNumValues() == NumTo && \"Broken CombineTo call!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1082, __PRETTY_FUNCTION__))
;
1083 ++NodesCombined;
1084 LLVM_DEBUG(dbgs() << "\nReplacing.1 "; N->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1085 To[0].getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
1086 dbgs() << " and " << NumTo - 1 << " other values\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.1 "; N->dump
(&DAG); dbgs() << "\nWith: "; To[0].getNode()->dump
(&DAG); dbgs() << " and " << NumTo - 1 <<
" other values\n"; } } while (false)
;
1087 for (unsigned i = 0, e = NumTo; i != e; ++i)
1088 assert((!To[i].getNode() ||(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1090, __PRETTY_FUNCTION__))
1089 N->getValueType(i) == To[i].getValueType()) &&(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1090, __PRETTY_FUNCTION__))
1090 "Cannot combine value to value of different type!")(((!To[i].getNode() || N->getValueType(i) == To[i].getValueType
()) && "Cannot combine value to value of different type!"
) ? static_cast<void> (0) : __assert_fail ("(!To[i].getNode() || N->getValueType(i) == To[i].getValueType()) && \"Cannot combine value to value of different type!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1090, __PRETTY_FUNCTION__))
;
1091
1092 WorklistRemover DeadNodes(*this);
1093 DAG.ReplaceAllUsesWith(N, To);
1094 if (AddTo) {
1095 // Push the new nodes and any users onto the worklist
1096 for (unsigned i = 0, e = NumTo; i != e; ++i) {
1097 if (To[i].getNode()) {
1098 AddToWorklist(To[i].getNode());
1099 AddUsersToWorklist(To[i].getNode());
1100 }
1101 }
1102 }
1103
1104 // Finally, if the node is now dead, remove it from the graph. The node
1105 // may not be dead if the replacement process recursively simplified to
1106 // something else needing this node.
1107 if (N->use_empty())
1108 deleteAndRecombine(N);
1109 return SDValue(N, 0);
1110}
1111
1112void DAGCombiner::
1113CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
1114 // Replace the old value with the new one.
1115 ++NodesCombined;
1116 LLVM_DEBUG(dbgs() << "\nReplacing.2 "; TLO.Old.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1117 dbgs() << "\nWith: "; TLO.New.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
1118 dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.2 "; TLO.Old.getNode
()->dump(&DAG); dbgs() << "\nWith: "; TLO.New.getNode
()->dump(&DAG); dbgs() << '\n'; } } while (false
)
;
1119
1120 // Replace all uses. If any nodes become isomorphic to other nodes and
1121 // are deleted, make sure to remove them from our worklist.
1122 WorklistRemover DeadNodes(*this);
1123 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
1124
1125 // Push the new node and any (possibly new) users onto the worklist.
1126 AddToWorklistWithUsers(TLO.New.getNode());
1127
1128 // Finally, if the node is now dead, remove it from the graph. The node
1129 // may not be dead if the replacement process recursively simplified to
1130 // something else needing this node.
1131 if (TLO.Old.getNode()->use_empty())
1132 deleteAndRecombine(TLO.Old.getNode());
1133}
1134
1135/// Check the specified integer node value to see if it can be simplified or if
1136/// things it uses can be simplified by bit propagation. If so, return true.
1137bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits,
1138 const APInt &DemandedElts,
1139 bool AssumeSingleUse) {
1140 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1141 KnownBits Known;
1142 if (!TLI.SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, 0,
1143 AssumeSingleUse))
1144 return false;
1145
1146 // Revisit the node.
1147 AddToWorklist(Op.getNode());
1148
1149 CommitTargetLoweringOpt(TLO);
1150 return true;
1151}
1152
1153/// Check the specified vector node value to see if it can be simplified or
1154/// if things it uses can be simplified as it only uses some of the elements.
1155/// If so, return true.
1156bool DAGCombiner::SimplifyDemandedVectorElts(SDValue Op,
1157 const APInt &DemandedElts,
1158 bool AssumeSingleUse) {
1159 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
1160 APInt KnownUndef, KnownZero;
1161 if (!TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero,
1162 TLO, 0, AssumeSingleUse))
1163 return false;
1164
1165 // Revisit the node.
1166 AddToWorklist(Op.getNode());
1167
1168 CommitTargetLoweringOpt(TLO);
1169 return true;
1170}
1171
1172void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
1173 SDLoc DL(Load);
1174 EVT VT = Load->getValueType(0);
1175 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, SDValue(ExtLoad, 0));
1176
1177 LLVM_DEBUG(dbgs() << "\nReplacing.9 "; Load->dump(&DAG); dbgs() << "\nWith: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
1178 Trunc.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nReplacing.9 "; Load->
dump(&DAG); dbgs() << "\nWith: "; Trunc.getNode()->
dump(&DAG); dbgs() << '\n'; } } while (false)
;
1179 WorklistRemover DeadNodes(*this);
1180 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
1181 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
1182 deleteAndRecombine(Load);
1183 AddToWorklist(Trunc.getNode());
1184}
1185
1186SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
1187 Replace = false;
1188 SDLoc DL(Op);
1189 if (ISD::isUNINDEXEDLoad(Op.getNode())) {
1190 LoadSDNode *LD = cast<LoadSDNode>(Op);
1191 EVT MemVT = LD->getMemoryVT();
1192 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1193 : LD->getExtensionType();
1194 Replace = true;
1195 return DAG.getExtLoad(ExtType, DL, PVT,
1196 LD->getChain(), LD->getBasePtr(),
1197 MemVT, LD->getMemOperand());
1198 }
1199
1200 unsigned Opc = Op.getOpcode();
1201 switch (Opc) {
1202 default: break;
1203 case ISD::AssertSext:
1204 if (SDValue Op0 = SExtPromoteOperand(Op.getOperand(0), PVT))
1205 return DAG.getNode(ISD::AssertSext, DL, PVT, Op0, Op.getOperand(1));
1206 break;
1207 case ISD::AssertZext:
1208 if (SDValue Op0 = ZExtPromoteOperand(Op.getOperand(0), PVT))
1209 return DAG.getNode(ISD::AssertZext, DL, PVT, Op0, Op.getOperand(1));
1210 break;
1211 case ISD::Constant: {
1212 unsigned ExtOpc =
1213 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1214 return DAG.getNode(ExtOpc, DL, PVT, Op);
1215 }
1216 }
1217
1218 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
1219 return SDValue();
1220 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op);
1221}
1222
1223SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
1224 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
1225 return SDValue();
1226 EVT OldVT = Op.getValueType();
1227 SDLoc DL(Op);
1228 bool Replace = false;
1229 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1230 if (!NewOp.getNode())
1231 return SDValue();
1232 AddToWorklist(NewOp.getNode());
1233
1234 if (Replace)
1235 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1236 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, NewOp.getValueType(), NewOp,
1237 DAG.getValueType(OldVT));
1238}
1239
1240SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
1241 EVT OldVT = Op.getValueType();
1242 SDLoc DL(Op);
1243 bool Replace = false;
1244 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
1245 if (!NewOp.getNode())
1246 return SDValue();
1247 AddToWorklist(NewOp.getNode());
1248
1249 if (Replace)
1250 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
1251 return DAG.getZeroExtendInReg(NewOp, DL, OldVT);
1252}
1253
1254/// Promote the specified integer binary operation if the target indicates it is
1255/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1256/// i32 since i16 instructions are longer.
1257SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
1258 if (!LegalOperations)
1259 return SDValue();
1260
1261 EVT VT = Op.getValueType();
1262 if (VT.isVector() || !VT.isInteger())
1263 return SDValue();
1264
1265 // If operation type is 'undesirable', e.g. i16 on x86, consider
1266 // promoting it.
1267 unsigned Opc = Op.getOpcode();
1268 if (TLI.isTypeDesirableForOp(Opc, VT))
1269 return SDValue();
1270
1271 EVT PVT = VT;
1272 // Consult target whether it is a good idea to promote this operation and
1273 // what's the right type to promote it to.
1274 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1275 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1275, __PRETTY_FUNCTION__))
;
1276
1277 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1278
1279 bool Replace0 = false;
1280 SDValue N0 = Op.getOperand(0);
1281 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1282
1283 bool Replace1 = false;
1284 SDValue N1 = Op.getOperand(1);
1285 SDValue NN1 = PromoteOperand(N1, PVT, Replace1);
1286 SDLoc DL(Op);
1287
1288 SDValue RV =
1289 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, NN0, NN1));
1290
1291 // We are always replacing N0/N1's use in N and only need additional
1292 // replacements if there are additional uses.
1293 // Note: We are checking uses of the *nodes* (SDNode) rather than values
1294 // (SDValue) here because the node may reference multiple values
1295 // (for example, the chain value of a load node).
1296 Replace0 &= !N0->hasOneUse();
1297 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1298
1299 // Combine Op here so it is preserved past replacements.
1300 CombineTo(Op.getNode(), RV);
1301
1302 // If operands have a use ordering, make sure we deal with
1303 // predecessor first.
1304 if (Replace0 && Replace1 && N0.getNode()->isPredecessorOf(N1.getNode())) {
1305 std::swap(N0, N1);
1306 std::swap(NN0, NN1);
1307 }
1308
1309 if (Replace0) {
1310 AddToWorklist(NN0.getNode());
1311 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1312 }
1313 if (Replace1) {
1314 AddToWorklist(NN1.getNode());
1315 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1316 }
1317 return Op;
1318 }
1319 return SDValue();
1320}
1321
1322/// Promote the specified integer shift operation if the target indicates it is
1323/// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1324/// i32 since i16 instructions are longer.
1325SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1326 if (!LegalOperations)
1327 return SDValue();
1328
1329 EVT VT = Op.getValueType();
1330 if (VT.isVector() || !VT.isInteger())
1331 return SDValue();
1332
1333 // If operation type is 'undesirable', e.g. i16 on x86, consider
1334 // promoting it.
1335 unsigned Opc = Op.getOpcode();
1336 if (TLI.isTypeDesirableForOp(Opc, VT))
1337 return SDValue();
1338
1339 EVT PVT = VT;
1340 // Consult target whether it is a good idea to promote this operation and
1341 // what's the right type to promote it to.
1342 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1343 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1343, __PRETTY_FUNCTION__))
;
1344
1345 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1346
1347 bool Replace = false;
1348 SDValue N0 = Op.getOperand(0);
1349 SDValue N1 = Op.getOperand(1);
1350 if (Opc == ISD::SRA)
1351 N0 = SExtPromoteOperand(N0, PVT);
1352 else if (Opc == ISD::SRL)
1353 N0 = ZExtPromoteOperand(N0, PVT);
1354 else
1355 N0 = PromoteOperand(N0, PVT, Replace);
1356
1357 if (!N0.getNode())
1358 return SDValue();
1359
1360 SDLoc DL(Op);
1361 SDValue RV =
1362 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1363
1364 if (Replace)
1365 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1366
1367 // Deal with Op being deleted.
1368 if (Op && Op.getOpcode() != ISD::DELETED_NODE)
1369 return RV;
1370 }
1371 return SDValue();
1372}
1373
1374SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1375 if (!LegalOperations)
1376 return SDValue();
1377
1378 EVT VT = Op.getValueType();
1379 if (VT.isVector() || !VT.isInteger())
1380 return SDValue();
1381
1382 // If operation type is 'undesirable', e.g. i16 on x86, consider
1383 // promoting it.
1384 unsigned Opc = Op.getOpcode();
1385 if (TLI.isTypeDesirableForOp(Opc, VT))
1386 return SDValue();
1387
1388 EVT PVT = VT;
1389 // Consult target whether it is a good idea to promote this operation and
1390 // what's the right type to promote it to.
1391 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1392 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1392, __PRETTY_FUNCTION__))
;
1393 // fold (aext (aext x)) -> (aext x)
1394 // fold (aext (zext x)) -> (zext x)
1395 // fold (aext (sext x)) -> (sext x)
1396 LLVM_DEBUG(dbgs() << "\nPromoting "; Op.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; Op.getNode(
)->dump(&DAG); } } while (false)
;
1397 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1398 }
1399 return SDValue();
1400}
1401
1402bool DAGCombiner::PromoteLoad(SDValue Op) {
1403 if (!LegalOperations)
1404 return false;
1405
1406 if (!ISD::isUNINDEXEDLoad(Op.getNode()))
1407 return false;
1408
1409 EVT VT = Op.getValueType();
1410 if (VT.isVector() || !VT.isInteger())
1411 return false;
1412
1413 // If operation type is 'undesirable', e.g. i16 on x86, consider
1414 // promoting it.
1415 unsigned Opc = Op.getOpcode();
1416 if (TLI.isTypeDesirableForOp(Opc, VT))
1417 return false;
1418
1419 EVT PVT = VT;
1420 // Consult target whether it is a good idea to promote this operation and
1421 // what's the right type to promote it to.
1422 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1423 assert(PVT != VT && "Don't know what type to promote to!")((PVT != VT && "Don't know what type to promote to!")
? static_cast<void> (0) : __assert_fail ("PVT != VT && \"Don't know what type to promote to!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1423, __PRETTY_FUNCTION__))
;
1424
1425 SDLoc DL(Op);
1426 SDNode *N = Op.getNode();
1427 LoadSDNode *LD = cast<LoadSDNode>(N);
1428 EVT MemVT = LD->getMemoryVT();
1429 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) ? ISD::EXTLOAD
1430 : LD->getExtensionType();
1431 SDValue NewLD = DAG.getExtLoad(ExtType, DL, PVT,
1432 LD->getChain(), LD->getBasePtr(),
1433 MemVT, LD->getMemOperand());
1434 SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1435
1436 LLVM_DEBUG(dbgs() << "\nPromoting "; N->dump(&DAG); dbgs() << "\nTo: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
1437 Result.getNode()->dump(&DAG); dbgs() << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nPromoting "; N->dump(
&DAG); dbgs() << "\nTo: "; Result.getNode()->dump
(&DAG); dbgs() << '\n'; } } while (false)
;
1438 WorklistRemover DeadNodes(*this);
1439 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1440 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1441 deleteAndRecombine(N);
1442 AddToWorklist(Result.getNode());
1443 return true;
1444 }
1445 return false;
1446}
1447
1448/// Recursively delete a node which has no uses and any operands for
1449/// which it is the only use.
1450///
1451/// Note that this both deletes the nodes and removes them from the worklist.
1452/// It also adds any nodes who have had a user deleted to the worklist as they
1453/// may now have only one use and subject to other combines.
1454bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1455 if (!N->use_empty())
1456 return false;
1457
1458 SmallSetVector<SDNode *, 16> Nodes;
1459 Nodes.insert(N);
1460 do {
1461 N = Nodes.pop_back_val();
1462 if (!N)
1463 continue;
1464
1465 if (N->use_empty()) {
1466 for (const SDValue &ChildN : N->op_values())
1467 Nodes.insert(ChildN.getNode());
1468
1469 removeFromWorklist(N);
1470 DAG.DeleteNode(N);
1471 } else {
1472 AddToWorklist(N);
1473 }
1474 } while (!Nodes.empty());
1475 return true;
1476}
1477
1478//===----------------------------------------------------------------------===//
1479// Main DAG Combiner implementation
1480//===----------------------------------------------------------------------===//
1481
1482void DAGCombiner::Run(CombineLevel AtLevel) {
1483 // set the instance variables, so that the various visit routines may use it.
1484 Level = AtLevel;
1485 LegalDAG = Level >= AfterLegalizeDAG;
1486 LegalOperations = Level >= AfterLegalizeVectorOps;
1487 LegalTypes = Level >= AfterLegalizeTypes;
1488
1489 WorklistInserter AddNodes(*this);
1490
1491 // Add all the dag nodes to the worklist.
1492 for (SDNode &Node : DAG.allnodes())
1493 AddToWorklist(&Node);
1494
1495 // Create a dummy node (which is not added to allnodes), that adds a reference
1496 // to the root node, preventing it from being deleted, and tracking any
1497 // changes of the root.
1498 HandleSDNode Dummy(DAG.getRoot());
1499
1500 // While we have a valid worklist entry node, try to combine it.
1501 while (SDNode *N = getNextWorklistEntry()) {
1502 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1503 // N is deleted from the DAG, since they too may now be dead or may have a
1504 // reduced number of uses, allowing other xforms.
1505 if (recursivelyDeleteUnusedNodes(N))
1506 continue;
1507
1508 WorklistRemover DeadNodes(*this);
1509
1510 // If this combine is running after legalizing the DAG, re-legalize any
1511 // nodes pulled off the worklist.
1512 if (LegalDAG) {
1513 SmallSetVector<SDNode *, 16> UpdatedNodes;
1514 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1515
1516 for (SDNode *LN : UpdatedNodes)
1517 AddToWorklistWithUsers(LN);
1518
1519 if (!NIsValid)
1520 continue;
1521 }
1522
1523 LLVM_DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "\nCombining: "; N->dump
(&DAG); } } while (false)
;
1524
1525 // Add any operands of the new node which have not yet been combined to the
1526 // worklist as well. Because the worklist uniques things already, this
1527 // won't repeatedly process the same operand.
1528 CombinedNodes.insert(N);
1529 for (const SDValue &ChildN : N->op_values())
1530 if (!CombinedNodes.count(ChildN.getNode()))
1531 AddToWorklist(ChildN.getNode());
1532
1533 SDValue RV = combine(N);
1534
1535 if (!RV.getNode())
1536 continue;
1537
1538 ++NodesCombined;
1539
1540 // If we get back the same node we passed in, rather than a new node or
1541 // zero, we know that the node must have defined multiple values and
1542 // CombineTo was used. Since CombineTo takes care of the worklist
1543 // mechanics for us, we have no work to do in this case.
1544 if (RV.getNode() == N)
1545 continue;
1546
1547 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1549, __PRETTY_FUNCTION__))
1548 RV.getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1549, __PRETTY_FUNCTION__))
1549 "Node was deleted but visit returned new node!")((N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode
() != ISD::DELETED_NODE && "Node was deleted but visit returned new node!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && RV.getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned new node!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1549, __PRETTY_FUNCTION__))
;
1550
1551 LLVM_DEBUG(dbgs() << " ... into: "; RV.getNode()->dump(&DAG))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << " ... into: "; RV.getNode()
->dump(&DAG); } } while (false)
;
1552
1553 if (N->getNumValues() == RV.getNode()->getNumValues())
1554 DAG.ReplaceAllUsesWith(N, RV.getNode());
1555 else {
1556 assert(N->getValueType(0) == RV.getValueType() &&((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1557, __PRETTY_FUNCTION__))
1557 N->getNumValues() == 1 && "Type mismatch")((N->getValueType(0) == RV.getValueType() && N->
getNumValues() == 1 && "Type mismatch") ? static_cast
<void> (0) : __assert_fail ("N->getValueType(0) == RV.getValueType() && N->getNumValues() == 1 && \"Type mismatch\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1557, __PRETTY_FUNCTION__))
;
1558 DAG.ReplaceAllUsesWith(N, &RV);
1559 }
1560
1561 // Push the new node and any users onto the worklist. Omit this if the
1562 // new node is the EntryToken (e.g. if a store managed to get optimized
1563 // out), because re-visiting the EntryToken and its users will not uncover
1564 // any additional opportunities, but there may be a large number of such
1565 // users, potentially causing compile time explosion.
1566 if (RV.getOpcode() != ISD::EntryToken) {
1567 AddToWorklist(RV.getNode());
1568 AddUsersToWorklist(RV.getNode());
1569 }
1570
1571 // Finally, if the node is now dead, remove it from the graph. The node
1572 // may not be dead if the replacement process recursively simplified to
1573 // something else needing this node. This will also take care of adding any
1574 // operands which have lost a user to the worklist.
1575 recursivelyDeleteUnusedNodes(N);
1576 }
1577
1578 // If the root changed (e.g. it was a dead load, update the root).
1579 DAG.setRoot(Dummy.getValue());
1580 DAG.RemoveDeadNodes();
1581}
1582
1583SDValue DAGCombiner::visit(SDNode *N) {
1584 switch (N->getOpcode()) {
1585 default: break;
1586 case ISD::TokenFactor: return visitTokenFactor(N);
1587 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1588 case ISD::ADD: return visitADD(N);
1589 case ISD::SUB: return visitSUB(N);
1590 case ISD::SADDSAT:
1591 case ISD::UADDSAT: return visitADDSAT(N);
1592 case ISD::SSUBSAT:
1593 case ISD::USUBSAT: return visitSUBSAT(N);
1594 case ISD::ADDC: return visitADDC(N);
1595 case ISD::SADDO:
1596 case ISD::UADDO: return visitADDO(N);
1597 case ISD::SUBC: return visitSUBC(N);
1598 case ISD::SSUBO:
1599 case ISD::USUBO: return visitSUBO(N);
1600 case ISD::ADDE: return visitADDE(N);
1601 case ISD::ADDCARRY: return visitADDCARRY(N);
1602 case ISD::SUBE: return visitSUBE(N);
1603 case ISD::SUBCARRY: return visitSUBCARRY(N);
1604 case ISD::SMULFIX:
1605 case ISD::SMULFIXSAT:
1606 case ISD::UMULFIX:
1607 case ISD::UMULFIXSAT: return visitMULFIX(N);
1608 case ISD::MUL: return visitMUL(N);
1609 case ISD::SDIV: return visitSDIV(N);
1610 case ISD::UDIV: return visitUDIV(N);
1611 case ISD::SREM:
1612 case ISD::UREM: return visitREM(N);
1613 case ISD::MULHU: return visitMULHU(N);
1614 case ISD::MULHS: return visitMULHS(N);
1615 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1616 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1617 case ISD::SMULO:
1618 case ISD::UMULO: return visitMULO(N);
1619 case ISD::SMIN:
1620 case ISD::SMAX:
1621 case ISD::UMIN:
1622 case ISD::UMAX: return visitIMINMAX(N);
1623 case ISD::AND: return visitAND(N);
1624 case ISD::OR: return visitOR(N);
1625 case ISD::XOR: return visitXOR(N);
1626 case ISD::SHL: return visitSHL(N);
1627 case ISD::SRA: return visitSRA(N);
1628 case ISD::SRL: return visitSRL(N);
1629 case ISD::ROTR:
1630 case ISD::ROTL: return visitRotate(N);
1631 case ISD::FSHL:
1632 case ISD::FSHR: return visitFunnelShift(N);
1633 case ISD::ABS: return visitABS(N);
1634 case ISD::BSWAP: return visitBSWAP(N);
1635 case ISD::BITREVERSE: return visitBITREVERSE(N);
1636 case ISD::CTLZ: return visitCTLZ(N);
1637 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1638 case ISD::CTTZ: return visitCTTZ(N);
1639 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1640 case ISD::CTPOP: return visitCTPOP(N);
1641 case ISD::SELECT: return visitSELECT(N);
1642 case ISD::VSELECT: return visitVSELECT(N);
1643 case ISD::SELECT_CC: return visitSELECT_CC(N);
1644 case ISD::SETCC: return visitSETCC(N);
1645 case ISD::SETCCCARRY: return visitSETCCCARRY(N);
1646 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1647 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1648 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1649 case ISD::AssertSext:
1650 case ISD::AssertZext: return visitAssertExt(N);
1651 case ISD::AssertAlign: return visitAssertAlign(N);
1652 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1653 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1654 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N);
1655 case ISD::TRUNCATE: return visitTRUNCATE(N);
1656 case ISD::BITCAST: return visitBITCAST(N);
1657 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1658 case ISD::FADD: return visitFADD(N);
1659 case ISD::STRICT_FADD: return visitSTRICT_FADD(N);
1660 case ISD::FSUB: return visitFSUB(N);
1661 case ISD::FMUL: return visitFMUL(N);
1662 case ISD::FMA: return visitFMA(N);
1663 case ISD::FDIV: return visitFDIV(N);
1664 case ISD::FREM: return visitFREM(N);
1665 case ISD::FSQRT: return visitFSQRT(N);
1666 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1667 case ISD::FPOW: return visitFPOW(N);
1668 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1669 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1670 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1671 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1672 case ISD::FP_ROUND: return visitFP_ROUND(N);
1673 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1674 case ISD::FNEG: return visitFNEG(N);
1675 case ISD::FABS: return visitFABS(N);
1676 case ISD::FFLOOR: return visitFFLOOR(N);
1677 case ISD::FMINNUM: return visitFMINNUM(N);
1678 case ISD::FMAXNUM: return visitFMAXNUM(N);
1679 case ISD::FMINIMUM: return visitFMINIMUM(N);
1680 case ISD::FMAXIMUM: return visitFMAXIMUM(N);
1681 case ISD::FCEIL: return visitFCEIL(N);
1682 case ISD::FTRUNC: return visitFTRUNC(N);
1683 case ISD::BRCOND: return visitBRCOND(N);
1684 case ISD::BR_CC: return visitBR_CC(N);
1685 case ISD::LOAD: return visitLOAD(N);
1686 case ISD::STORE: return visitSTORE(N);
1687 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1688 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1689 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1690 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1691 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1692 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1693 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1694 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1695 case ISD::MGATHER: return visitMGATHER(N);
1696 case ISD::MLOAD: return visitMLOAD(N);
1697 case ISD::MSCATTER: return visitMSCATTER(N);
1698 case ISD::MSTORE: return visitMSTORE(N);
1699 case ISD::LIFETIME_END: return visitLIFETIME_END(N);
1700 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1701 case ISD::FP16_TO_FP: return visitFP16_TO_FP(N);
1702 case ISD::FREEZE: return visitFREEZE(N);
1703 case ISD::VECREDUCE_FADD:
1704 case ISD::VECREDUCE_FMUL:
1705 case ISD::VECREDUCE_ADD:
1706 case ISD::VECREDUCE_MUL:
1707 case ISD::VECREDUCE_AND:
1708 case ISD::VECREDUCE_OR:
1709 case ISD::VECREDUCE_XOR:
1710 case ISD::VECREDUCE_SMAX:
1711 case ISD::VECREDUCE_SMIN:
1712 case ISD::VECREDUCE_UMAX:
1713 case ISD::VECREDUCE_UMIN:
1714 case ISD::VECREDUCE_FMAX:
1715 case ISD::VECREDUCE_FMIN: return visitVECREDUCE(N);
1716 }
1717 return SDValue();
1718}
1719
1720SDValue DAGCombiner::combine(SDNode *N) {
1721 SDValue RV;
1722 if (!DisableGenericCombines)
1723 RV = visit(N);
1724
1725 // If nothing happened, try a target-specific DAG combine.
1726 if (!RV.getNode()) {
1727 assert(N->getOpcode() != ISD::DELETED_NODE &&((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1728, __PRETTY_FUNCTION__))
1728 "Node was deleted but visit returned NULL!")((N->getOpcode() != ISD::DELETED_NODE && "Node was deleted but visit returned NULL!"
) ? static_cast<void> (0) : __assert_fail ("N->getOpcode() != ISD::DELETED_NODE && \"Node was deleted but visit returned NULL!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1728, __PRETTY_FUNCTION__))
;
1729
1730 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1731 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1732
1733 // Expose the DAG combiner to the target combiner impls.
1734 TargetLowering::DAGCombinerInfo
1735 DagCombineInfo(DAG, Level, false, this);
1736
1737 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1738 }
1739 }
1740
1741 // If nothing happened still, try promoting the operation.
1742 if (!RV.getNode()) {
1743 switch (N->getOpcode()) {
1744 default: break;
1745 case ISD::ADD:
1746 case ISD::SUB:
1747 case ISD::MUL:
1748 case ISD::AND:
1749 case ISD::OR:
1750 case ISD::XOR:
1751 RV = PromoteIntBinOp(SDValue(N, 0));
1752 break;
1753 case ISD::SHL:
1754 case ISD::SRA:
1755 case ISD::SRL:
1756 RV = PromoteIntShiftOp(SDValue(N, 0));
1757 break;
1758 case ISD::SIGN_EXTEND:
1759 case ISD::ZERO_EXTEND:
1760 case ISD::ANY_EXTEND:
1761 RV = PromoteExtend(SDValue(N, 0));
1762 break;
1763 case ISD::LOAD:
1764 if (PromoteLoad(SDValue(N, 0)))
1765 RV = SDValue(N, 0);
1766 break;
1767 }
1768 }
1769
1770 // If N is a commutative binary node, try to eliminate it if the commuted
1771 // version is already present in the DAG.
1772 if (!RV.getNode() && TLI.isCommutativeBinOp(N->getOpcode()) &&
1773 N->getNumValues() == 1) {
1774 SDValue N0 = N->getOperand(0);
1775 SDValue N1 = N->getOperand(1);
1776
1777 // Constant operands are canonicalized to RHS.
1778 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
1779 SDValue Ops[] = {N1, N0};
1780 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1781 N->getFlags());
1782 if (CSENode)
1783 return SDValue(CSENode, 0);
1784 }
1785 }
1786
1787 return RV;
1788}
1789
1790/// Given a node, return its input chain if it has one, otherwise return a null
1791/// sd operand.
1792static SDValue getInputChainForNode(SDNode *N) {
1793 if (unsigned NumOps = N->getNumOperands()) {
1794 if (N->getOperand(0).getValueType() == MVT::Other)
1795 return N->getOperand(0);
1796 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1797 return N->getOperand(NumOps-1);
1798 for (unsigned i = 1; i < NumOps-1; ++i)
1799 if (N->getOperand(i).getValueType() == MVT::Other)
1800 return N->getOperand(i);
1801 }
1802 return SDValue();
1803}
1804
1805SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1806 // If N has two operands, where one has an input chain equal to the other,
1807 // the 'other' chain is redundant.
1808 if (N->getNumOperands() == 2) {
1809 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1810 return N->getOperand(0);
1811 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1812 return N->getOperand(1);
1813 }
1814
1815 // Don't simplify token factors if optnone.
1816 if (OptLevel == CodeGenOpt::None)
1817 return SDValue();
1818
1819 // Don't simplify the token factor if the node itself has too many operands.
1820 if (N->getNumOperands() > TokenFactorInlineLimit)
1821 return SDValue();
1822
1823 // If the sole user is a token factor, we should make sure we have a
1824 // chance to merge them together. This prevents TF chains from inhibiting
1825 // optimizations.
1826 if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
1827 AddToWorklist(*(N->use_begin()));
1828
1829 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1830 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1831 SmallPtrSet<SDNode*, 16> SeenOps;
1832 bool Changed = false; // If we should replace this token factor.
1833
1834 // Start out with this token factor.
1835 TFs.push_back(N);
1836
1837 // Iterate through token factors. The TFs grows when new token factors are
1838 // encountered.
1839 for (unsigned i = 0; i < TFs.size(); ++i) {
1840 // Limit number of nodes to inline, to avoid quadratic compile times.
1841 // We have to add the outstanding Token Factors to Ops, otherwise we might
1842 // drop Ops from the resulting Token Factors.
1843 if (Ops.size() > TokenFactorInlineLimit) {
1844 for (unsigned j = i; j < TFs.size(); j++)
1845 Ops.emplace_back(TFs[j], 0);
1846 // Drop unprocessed Token Factors from TFs, so we do not add them to the
1847 // combiner worklist later.
1848 TFs.resize(i);
1849 break;
1850 }
1851
1852 SDNode *TF = TFs[i];
1853 // Check each of the operands.
1854 for (const SDValue &Op : TF->op_values()) {
1855 switch (Op.getOpcode()) {
1856 case ISD::EntryToken:
1857 // Entry tokens don't need to be added to the list. They are
1858 // redundant.
1859 Changed = true;
1860 break;
1861
1862 case ISD::TokenFactor:
1863 if (Op.hasOneUse() && !is_contained(TFs, Op.getNode())) {
1864 // Queue up for processing.
1865 TFs.push_back(Op.getNode());
1866 Changed = true;
1867 break;
1868 }
1869 LLVM_FALLTHROUGH[[gnu::fallthrough]];
1870
1871 default:
1872 // Only add if it isn't already in the list.
1873 if (SeenOps.insert(Op.getNode()).second)
1874 Ops.push_back(Op);
1875 else
1876 Changed = true;
1877 break;
1878 }
1879 }
1880 }
1881
1882 // Re-visit inlined Token Factors, to clean them up in case they have been
1883 // removed. Skip the first Token Factor, as this is the current node.
1884 for (unsigned i = 1, e = TFs.size(); i < e; i++)
1885 AddToWorklist(TFs[i]);
1886
1887 // Remove Nodes that are chained to another node in the list. Do so
1888 // by walking up chains breath-first stopping when we've seen
1889 // another operand. In general we must climb to the EntryNode, but we can exit
1890 // early if we find all remaining work is associated with just one operand as
1891 // no further pruning is possible.
1892
1893 // List of nodes to search through and original Ops from which they originate.
1894 SmallVector<std::pair<SDNode *, unsigned>, 8> Worklist;
1895 SmallVector<unsigned, 8> OpWorkCount; // Count of work for each Op.
1896 SmallPtrSet<SDNode *, 16> SeenChains;
1897 bool DidPruneOps = false;
1898
1899 unsigned NumLeftToConsider = 0;
1900 for (const SDValue &Op : Ops) {
1901 Worklist.push_back(std::make_pair(Op.getNode(), NumLeftToConsider++));
1902 OpWorkCount.push_back(1);
1903 }
1904
1905 auto AddToWorklist = [&](unsigned CurIdx, SDNode *Op, unsigned OpNumber) {
1906 // If this is an Op, we can remove the op from the list. Remark any
1907 // search associated with it as from the current OpNumber.
1908 if (SeenOps.count(Op) != 0) {
1909 Changed = true;
1910 DidPruneOps = true;
1911 unsigned OrigOpNumber = 0;
1912 while (OrigOpNumber < Ops.size() && Ops[OrigOpNumber].getNode() != Op)
1913 OrigOpNumber++;
1914 assert((OrigOpNumber != Ops.size()) &&(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1915, __PRETTY_FUNCTION__))
1915 "expected to find TokenFactor Operand")(((OrigOpNumber != Ops.size()) && "expected to find TokenFactor Operand"
) ? static_cast<void> (0) : __assert_fail ("(OrigOpNumber != Ops.size()) && \"expected to find TokenFactor Operand\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1915, __PRETTY_FUNCTION__))
;
1916 // Re-mark worklist from OrigOpNumber to OpNumber
1917 for (unsigned i = CurIdx + 1; i < Worklist.size(); ++i) {
1918 if (Worklist[i].second == OrigOpNumber) {
1919 Worklist[i].second = OpNumber;
1920 }
1921 }
1922 OpWorkCount[OpNumber] += OpWorkCount[OrigOpNumber];
1923 OpWorkCount[OrigOpNumber] = 0;
1924 NumLeftToConsider--;
1925 }
1926 // Add if it's a new chain
1927 if (SeenChains.insert(Op).second) {
1928 OpWorkCount[OpNumber]++;
1929 Worklist.push_back(std::make_pair(Op, OpNumber));
1930 }
1931 };
1932
1933 for (unsigned i = 0; i < Worklist.size() && i < 1024; ++i) {
1934 // We need at least be consider at least 2 Ops to prune.
1935 if (NumLeftToConsider <= 1)
1936 break;
1937 auto CurNode = Worklist[i].first;
1938 auto CurOpNumber = Worklist[i].second;
1939 assert((OpWorkCount[CurOpNumber] > 0) &&(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1940, __PRETTY_FUNCTION__))
1940 "Node should not appear in worklist")(((OpWorkCount[CurOpNumber] > 0) && "Node should not appear in worklist"
) ? static_cast<void> (0) : __assert_fail ("(OpWorkCount[CurOpNumber] > 0) && \"Node should not appear in worklist\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 1940, __PRETTY_FUNCTION__))
;
1941 switch (CurNode->getOpcode()) {
1942 case ISD::EntryToken:
1943 // Hitting EntryToken is the only way for the search to terminate without
1944 // hitting
1945 // another operand's search. Prevent us from marking this operand
1946 // considered.
1947 NumLeftToConsider++;
1948 break;
1949 case ISD::TokenFactor:
1950 for (const SDValue &Op : CurNode->op_values())
1951 AddToWorklist(i, Op.getNode(), CurOpNumber);
1952 break;
1953 case ISD::LIFETIME_START:
1954 case ISD::LIFETIME_END:
1955 case ISD::CopyFromReg:
1956 case ISD::CopyToReg:
1957 AddToWorklist(i, CurNode->getOperand(0).getNode(), CurOpNumber);
1958 break;
1959 default:
1960 if (auto *MemNode = dyn_cast<MemSDNode>(CurNode))
1961 AddToWorklist(i, MemNode->getChain().getNode(), CurOpNumber);
1962 break;
1963 }
1964 OpWorkCount[CurOpNumber]--;
1965 if (OpWorkCount[CurOpNumber] == 0)
1966 NumLeftToConsider--;
1967 }
1968
1969 // If we've changed things around then replace token factor.
1970 if (Changed) {
1971 SDValue Result;
1972 if (Ops.empty()) {
1973 // The entry token is the only possible outcome.
1974 Result = DAG.getEntryNode();
1975 } else {
1976 if (DidPruneOps) {
1977 SmallVector<SDValue, 8> PrunedOps;
1978 //
1979 for (const SDValue &Op : Ops) {
1980 if (SeenChains.count(Op.getNode()) == 0)
1981 PrunedOps.push_back(Op);
1982 }
1983 Result = DAG.getTokenFactor(SDLoc(N), PrunedOps);
1984 } else {
1985 Result = DAG.getTokenFactor(SDLoc(N), Ops);
1986 }
1987 }
1988 return Result;
1989 }
1990 return SDValue();
1991}
1992
1993/// MERGE_VALUES can always be eliminated.
1994SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1995 WorklistRemover DeadNodes(*this);
1996 // Replacing results may cause a different MERGE_VALUES to suddenly
1997 // be CSE'd with N, and carry its uses with it. Iterate until no
1998 // uses remain, to ensure that the node can be safely deleted.
1999 // First add the users of this node to the work list so that they
2000 // can be tried again once they have new operands.
2001 AddUsersToWorklist(N);
2002 do {
2003 // Do as a single replacement to avoid rewalking use lists.
2004 SmallVector<SDValue, 8> Ops;
2005 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
2006 Ops.push_back(N->getOperand(i));
2007 DAG.ReplaceAllUsesWith(N, Ops.data());
2008 } while (!N->use_empty());
2009 deleteAndRecombine(N);
2010 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2011}
2012
2013/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
2014/// ConstantSDNode pointer else nullptr.
2015static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
2016 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
2017 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
2018}
2019
2020SDValue DAGCombiner::foldBinOpIntoSelect(SDNode *BO) {
2021 assert(TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 &&((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2022, __PRETTY_FUNCTION__))
2022 "Unexpected binary operator")((TLI.isBinOp(BO->getOpcode()) && BO->getNumValues
() == 1 && "Unexpected binary operator") ? static_cast
<void> (0) : __assert_fail ("TLI.isBinOp(BO->getOpcode()) && BO->getNumValues() == 1 && \"Unexpected binary operator\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2022, __PRETTY_FUNCTION__))
;
2023
2024 // Don't do this unless the old select is going away. We want to eliminate the
2025 // binary operator, not replace a binop with a select.
2026 // TODO: Handle ISD::SELECT_CC.
2027 unsigned SelOpNo = 0;
2028 SDValue Sel = BO->getOperand(0);
2029 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
2030 SelOpNo = 1;
2031 Sel = BO->getOperand(1);
2032 }
2033
2034 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
2035 return SDValue();
2036
2037 SDValue CT = Sel.getOperand(1);
2038 if (!isConstantOrConstantVector(CT, true) &&
2039 !isConstantFPBuildVectorOrConstantFP(CT))
2040 return SDValue();
2041
2042 SDValue CF = Sel.getOperand(2);
2043 if (!isConstantOrConstantVector(CF, true) &&
2044 !isConstantFPBuildVectorOrConstantFP(CF))
2045 return SDValue();
2046
2047 // Bail out if any constants are opaque because we can't constant fold those.
2048 // The exception is "and" and "or" with either 0 or -1 in which case we can
2049 // propagate non constant operands into select. I.e.:
2050 // and (select Cond, 0, -1), X --> select Cond, 0, X
2051 // or X, (select Cond, -1, 0) --> select Cond, -1, X
2052 auto BinOpcode = BO->getOpcode();
2053 bool CanFoldNonConst =
2054 (BinOpcode == ISD::AND || BinOpcode == ISD::OR) &&
2055 (isNullOrNullSplat(CT) || isAllOnesOrAllOnesSplat(CT)) &&
2056 (isNullOrNullSplat(CF) || isAllOnesOrAllOnesSplat(CF));
2057
2058 SDValue CBO = BO->getOperand(SelOpNo ^ 1);
2059 if (!CanFoldNonConst &&
2060 !isConstantOrConstantVector(CBO, true) &&
2061 !isConstantFPBuildVectorOrConstantFP(CBO))
2062 return SDValue();
2063
2064 EVT VT = Sel.getValueType();
2065
2066 // In case of shift value and shift amount may have different VT. For instance
2067 // on x86 shift amount is i8 regardles of LHS type. Bail out if we have
2068 // swapped operands and value types do not match. NB: x86 is fine if operands
2069 // are not swapped with shift amount VT being not bigger than shifted value.
2070 // TODO: that is possible to check for a shift operation, correct VTs and
2071 // still perform optimization on x86 if needed.
2072 if (SelOpNo && VT != CBO.getValueType())
2073 return SDValue();
2074
2075 // We have a select-of-constants followed by a binary operator with a
2076 // constant. Eliminate the binop by pulling the constant math into the select.
2077 // Example: add (select Cond, CT, CF), CBO --> select Cond, CT + CBO, CF + CBO
2078 SDLoc DL(Sel);
2079 SDValue NewCT = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CT)
2080 : DAG.getNode(BinOpcode, DL, VT, CT, CBO);
2081 if (!CanFoldNonConst && !NewCT.isUndef() &&
2082 !isConstantOrConstantVector(NewCT, true) &&
2083 !isConstantFPBuildVectorOrConstantFP(NewCT))
2084 return SDValue();
2085
2086 SDValue NewCF = SelOpNo ? DAG.getNode(BinOpcode, DL, VT, CBO, CF)
2087 : DAG.getNode(BinOpcode, DL, VT, CF, CBO);
2088 if (!CanFoldNonConst && !NewCF.isUndef() &&
2089 !isConstantOrConstantVector(NewCF, true) &&
2090 !isConstantFPBuildVectorOrConstantFP(NewCF))
2091 return SDValue();
2092
2093 SDValue SelectOp = DAG.getSelect(DL, VT, Sel.getOperand(0), NewCT, NewCF);
2094 SelectOp->setFlags(BO->getFlags());
2095 return SelectOp;
2096}
2097
2098static SDValue foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) {
2099 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2100, __PRETTY_FUNCTION__))
2100 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2100, __PRETTY_FUNCTION__))
;
2101
2102 // Match a constant operand and a zext operand for the math instruction:
2103 // add Z, C
2104 // sub C, Z
2105 bool IsAdd = N->getOpcode() == ISD::ADD;
2106 SDValue C = IsAdd ? N->getOperand(1) : N->getOperand(0);
2107 SDValue Z = IsAdd ? N->getOperand(0) : N->getOperand(1);
2108 auto *CN = dyn_cast<ConstantSDNode>(C);
2109 if (!CN || Z.getOpcode() != ISD::ZERO_EXTEND)
2110 return SDValue();
2111
2112 // Match the zext operand as a setcc of a boolean.
2113 if (Z.getOperand(0).getOpcode() != ISD::SETCC ||
2114 Z.getOperand(0).getValueType() != MVT::i1)
2115 return SDValue();
2116
2117 // Match the compare as: setcc (X & 1), 0, eq.
2118 SDValue SetCC = Z.getOperand(0);
2119 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC->getOperand(2))->get();
2120 if (CC != ISD::SETEQ || !isNullConstant(SetCC.getOperand(1)) ||
2121 SetCC.getOperand(0).getOpcode() != ISD::AND ||
2122 !isOneConstant(SetCC.getOperand(0).getOperand(1)))
2123 return SDValue();
2124
2125 // We are adding/subtracting a constant and an inverted low bit. Turn that
2126 // into a subtract/add of the low bit with incremented/decremented constant:
2127 // add (zext i1 (seteq (X & 1), 0)), C --> sub C+1, (zext (X & 1))
2128 // sub C, (zext i1 (seteq (X & 1), 0)) --> add C-1, (zext (X & 1))
2129 EVT VT = C.getValueType();
2130 SDLoc DL(N);
2131 SDValue LowBit = DAG.getZExtOrTrunc(SetCC.getOperand(0), DL, VT);
2132 SDValue C1 = IsAdd ? DAG.getConstant(CN->getAPIntValue() + 1, DL, VT) :
2133 DAG.getConstant(CN->getAPIntValue() - 1, DL, VT);
2134 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, C1, LowBit);
2135}
2136
2137/// Try to fold a 'not' shifted sign-bit with add/sub with constant operand into
2138/// a shift and add with a different constant.
2139static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
2140 assert((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2141, __PRETTY_FUNCTION__))
2141 "Expecting add or sub")(((N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::
SUB) && "Expecting add or sub") ? static_cast<void
> (0) : __assert_fail ("(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && \"Expecting add or sub\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2141, __PRETTY_FUNCTION__))
;
2142
2143 // We need a constant operand for the add/sub, and the other operand is a
2144 // logical shift right: add (srl), C or sub C, (srl).
2145 bool IsAdd = N->getOpcode() == ISD::ADD;
2146 SDValue ConstantOp = IsAdd ? N->getOperand(1) : N->getOperand(0);
2147 SDValue ShiftOp = IsAdd ? N->getOperand(0) : N->getOperand(1);
2148 if (!DAG.isConstantIntBuildVectorOrConstantInt(ConstantOp) ||
2149 ShiftOp.getOpcode() != ISD::SRL)
2150 return SDValue();
2151
2152 // The shift must be of a 'not' value.
2153 SDValue Not = ShiftOp.getOperand(0);
2154 if (!Not.hasOneUse() || !isBitwiseNot(Not))
2155 return SDValue();
2156
2157 // The shift must be moving the sign bit to the least-significant-bit.
2158 EVT VT = ShiftOp.getValueType();
2159 SDValue ShAmt = ShiftOp.getOperand(1);
2160 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
2161 if (!ShAmtC || ShAmtC->getAPIntValue() != (VT.getScalarSizeInBits() - 1))
2162 return SDValue();
2163
2164 // Eliminate the 'not' by adjusting the shift and add/sub constant:
2165 // add (srl (not X), 31), C --> add (sra X, 31), (C + 1)
2166 // sub C, (srl (not X), 31) --> add (srl X, 31), (C - 1)
2167 SDLoc DL(N);
2168 auto ShOpcode = IsAdd ? ISD::SRA : ISD::SRL;
2169 SDValue NewShift = DAG.getNode(ShOpcode, DL, VT, Not.getOperand(0), ShAmt);
2170 if (SDValue NewC =
2171 DAG.FoldConstantArithmetic(IsAdd ? ISD::ADD : ISD::SUB, DL, VT,
2172 {ConstantOp, DAG.getConstant(1, DL, VT)}))
2173 return DAG.getNode(ISD::ADD, DL, VT, NewShift, NewC);
2174 return SDValue();
2175}
2176
2177/// Try to fold a node that behaves like an ADD (note that N isn't necessarily
2178/// an ISD::ADD here, it could for example be an ISD::OR if we know that there
2179/// are no common bits set in the operands).
2180SDValue DAGCombiner::visitADDLike(SDNode *N) {
2181 SDValue N0 = N->getOperand(0);
2182 SDValue N1 = N->getOperand(1);
2183 EVT VT = N0.getValueType();
2184 SDLoc DL(N);
2185
2186 // fold vector ops
2187 if (VT.isVector()) {
2188 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2189 return FoldedVOp;
2190
2191 // fold (add x, 0) -> x, vector edition
2192 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2193 return N0;
2194 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2195 return N1;
2196 }
2197
2198 // fold (add x, undef) -> undef
2199 if (N0.isUndef())
2200 return N0;
2201
2202 if (N1.isUndef())
2203 return N1;
2204
2205 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2206 // canonicalize constant to RHS
2207 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2208 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2209 // fold (add c1, c2) -> c1+c2
2210 return DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1});
2211 }
2212
2213 // fold (add x, 0) -> x
2214 if (isNullConstant(N1))
2215 return N0;
2216
2217 if (isConstantOrConstantVector(N1, /* NoOpaque */ true)) {
2218 // fold ((A-c1)+c2) -> (A+(c2-c1))
2219 if (N0.getOpcode() == ISD::SUB &&
2220 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2221 SDValue Sub =
2222 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N1, N0.getOperand(1)});
2223 assert(Sub && "Constant folding failed")((Sub && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Sub && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2223, __PRETTY_FUNCTION__))
;
2224 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2225 }
2226
2227 // fold ((c1-A)+c2) -> (c1+c2)-A
2228 if (N0.getOpcode() == ISD::SUB &&
2229 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaque */ true)) {
2230 SDValue Add =
2231 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N0.getOperand(0)});
2232 assert(Add && "Constant folding failed")((Add && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("Add && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 2232, __PRETTY_FUNCTION__))
;
2233 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2234 }
2235
2236 // add (sext i1 X), 1 -> zext (not i1 X)
2237 // We don't transform this pattern:
2238 // add (zext i1 X), -1 -> sext (not i1 X)
2239 // because most (?) targets generate better code for the zext form.
2240 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2241 isOneOrOneSplat(N1)) {
2242 SDValue X = N0.getOperand(0);
2243 if ((!LegalOperations ||
2244 (TLI.isOperationLegal(ISD::XOR, X.getValueType()) &&
2245 TLI.isOperationLegal(ISD::ZERO_EXTEND, VT))) &&
2246 X.getScalarValueSizeInBits() == 1) {
2247 SDValue Not = DAG.getNOT(DL, X, X.getValueType());
2248 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Not);
2249 }
2250 }
2251
2252 // Fold (add (or x, c0), c1) -> (add x, (c0 + c1)) if (or x, c0) is
2253 // equivalent to (add x, c0).
2254 if (N0.getOpcode() == ISD::OR &&
2255 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true) &&
2256 DAG.haveNoCommonBitsSet(N0.getOperand(0), N0.getOperand(1))) {
2257 if (SDValue Add0 = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT,
2258 {N1, N0.getOperand(1)}))
2259 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add0);
2260 }
2261 }
2262
2263 if (SDValue NewSel = foldBinOpIntoSelect(N))
2264 return NewSel;
2265
2266 // reassociate add
2267 if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N0, N1)) {
2268 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2269 return RADD;
2270 }
2271 // fold ((0-A) + B) -> B-A
2272 if (N0.getOpcode() == ISD::SUB && isNullOrNullSplat(N0.getOperand(0)))
2273 return DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2274
2275 // fold (A + (0-B)) -> A-B
2276 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
2277 return DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(1));
2278
2279 // fold (A+(B-A)) -> B
2280 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
2281 return N1.getOperand(0);
2282
2283 // fold ((B-A)+A) -> B
2284 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
2285 return N0.getOperand(0);
2286
2287 // fold ((A-B)+(C-A)) -> (C-B)
2288 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2289 N0.getOperand(0) == N1.getOperand(1))
2290 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2291 N0.getOperand(1));
2292
2293 // fold ((A-B)+(B-C)) -> (A-C)
2294 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB &&
2295 N0.getOperand(1) == N1.getOperand(0))
2296 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
2297 N1.getOperand(1));
2298
2299 // fold (A+(B-(A+C))) to (B-C)
2300 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2301 N0 == N1.getOperand(1).getOperand(0))
2302 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2303 N1.getOperand(1).getOperand(1));
2304
2305 // fold (A+(B-(C+A))) to (B-C)
2306 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
2307 N0 == N1.getOperand(1).getOperand(1))
2308 return DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(0),
2309 N1.getOperand(1).getOperand(0));
2310
2311 // fold (A+((B-A)+or-C)) to (B+or-C)
2312 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
2313 N1.getOperand(0).getOpcode() == ISD::SUB &&
2314 N0 == N1.getOperand(0).getOperand(1))
2315 return DAG.getNode(N1.getOpcode(), DL, VT, N1.getOperand(0).getOperand(0),
2316 N1.getOperand(1));
2317
2318 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
2319 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
2320 SDValue N00 = N0.getOperand(0);
2321 SDValue N01 = N0.getOperand(1);
2322 SDValue N10 = N1.getOperand(0);
2323 SDValue N11 = N1.getOperand(1);
2324
2325 if (isConstantOrConstantVector(N00) || isConstantOrConstantVector(N10))
2326 return DAG.getNode(ISD::SUB, DL, VT,
2327 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
2328 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
2329 }
2330
2331 // fold (add (umax X, C), -C) --> (usubsat X, C)
2332 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2333 auto MatchUSUBSAT = [](ConstantSDNode *Max, ConstantSDNode *Op) {
2334 return (!Max && !Op) ||
2335 (Max && Op && Max->getAPIntValue() == (-Op->getAPIntValue()));
2336 };
2337 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2338 /*AllowUndefs*/ true))
2339 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2340 N0.getOperand(1));
2341 }
2342
2343 if (SimplifyDemandedBits(SDValue(N, 0)))
2344 return SDValue(N, 0);
2345
2346 if (isOneOrOneSplat(N1)) {
2347 // fold (add (xor a, -1), 1) -> (sub 0, a)
2348 if (isBitwiseNot(N0))
2349 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
2350 N0.getOperand(0));
2351
2352 // fold (add (add (xor a, -1), b), 1) -> (sub b, a)
2353 if (N0.getOpcode() == ISD::ADD ||
2354 N0.getOpcode() == ISD::UADDO ||
2355 N0.getOpcode() == ISD::SADDO) {
2356 SDValue A, Xor;
2357
2358 if (isBitwiseNot(N0.getOperand(0))) {
2359 A = N0.getOperand(1);
2360 Xor = N0.getOperand(0);
2361 } else if (isBitwiseNot(N0.getOperand(1))) {
2362 A = N0.getOperand(0);
2363 Xor = N0.getOperand(1);
2364 }
2365
2366 if (Xor)
2367 return DAG.getNode(ISD::SUB, DL, VT, A, Xor.getOperand(0));
2368 }
2369
2370 // Look for:
2371 // add (add x, y), 1
2372 // And if the target does not like this form then turn into:
2373 // sub y, (xor x, -1)
2374 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2375 N0.getOpcode() == ISD::ADD) {
2376 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2377 DAG.getAllOnesConstant(DL, VT));
2378 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2379 }
2380 }
2381
2382 // (x - y) + -1 -> add (xor y, -1), x
2383 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2384 isAllOnesOrAllOnesSplat(N1)) {
2385 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1), N1);
2386 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
2387 }
2388
2389 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2390 return Combined;
2391
2392 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2393 return Combined;
2394
2395 return SDValue();
2396}
2397
2398SDValue DAGCombiner::visitADD(SDNode *N) {
2399 SDValue N0 = N->getOperand(0);
2400 SDValue N1 = N->getOperand(1);
2401 EVT VT = N0.getValueType();
2402 SDLoc DL(N);
2403
2404 if (SDValue Combined = visitADDLike(N))
2405 return Combined;
2406
2407 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
2408 return V;
2409
2410 if (SDValue V = foldAddSubOfSignBit(N, DAG))
2411 return V;
2412
2413 // fold (a+b) -> (a|b) iff a and b share no bits.
2414 if ((!LegalOperations || TLI.isOperationLegal(ISD::OR, VT)) &&
2415 DAG.haveNoCommonBitsSet(N0, N1))
2416 return DAG.getNode(ISD::OR, DL, VT, N0, N1);
2417
2418 // Fold (add (vscale * C0), (vscale * C1)) to (vscale * (C0 + C1)).
2419 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
2420 APInt C0 = N0->getConstantOperandAPInt(0);
2421 APInt C1 = N1->getConstantOperandAPInt(0);
2422 return DAG.getVScale(DL, VT, C0 + C1);
2423 }
2424
2425 // fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
2426 if ((N0.getOpcode() == ISD::ADD) &&
2427 (N0.getOperand(1).getOpcode() == ISD::VSCALE) &&
2428 (N1.getOpcode() == ISD::VSCALE)) {
2429 auto VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
2430 auto VS1 = N1->getConstantOperandAPInt(0);
2431 auto VS = DAG.getVScale(DL, VT, VS0 + VS1);
2432 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
2433 }
2434
2435 return SDValue();
2436}
2437
2438SDValue DAGCombiner::visitADDSAT(SDNode *N) {
2439 unsigned Opcode = N->getOpcode();
2440 SDValue N0 = N->getOperand(0);
2441 SDValue N1 = N->getOperand(1);
2442 EVT VT = N0.getValueType();
2443 SDLoc DL(N);
2444
2445 // fold vector ops
2446 if (VT.isVector()) {
2447 // TODO SimplifyVBinOp
2448
2449 // fold (add_sat x, 0) -> x, vector edition
2450 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2451 return N0;
2452 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2453 return N1;
2454 }
2455
2456 // fold (add_sat x, undef) -> -1
2457 if (N0.isUndef() || N1.isUndef())
2458 return DAG.getAllOnesConstant(DL, VT);
2459
2460 if (DAG.isConstantIntBuildVectorOrConstantInt(N0)) {
2461 // canonicalize constant to RHS
2462 if (!DAG.isConstantIntBuildVectorOrConstantInt(N1))
2463 return DAG.getNode(Opcode, DL, VT, N1, N0);
2464 // fold (add_sat c1, c2) -> c3
2465 return DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1});
2466 }
2467
2468 // fold (add_sat x, 0) -> x
2469 if (isNullConstant(N1))
2470 return N0;
2471
2472 // If it cannot overflow, transform into an add.
2473 if (Opcode == ISD::UADDSAT)
2474 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2475 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
2476
2477 return SDValue();
2478}
2479
2480static SDValue getAsCarry(const TargetLowering &TLI, SDValue V) {
2481 bool Masked = false;
2482
2483 // First, peel away TRUNCATE/ZERO_EXTEND/AND nodes due to legalization.
2484 while (true) {
2485 if (V.getOpcode() == ISD::TRUNCATE || V.getOpcode() == ISD::ZERO_EXTEND) {
2486 V = V.getOperand(0);
2487 continue;
2488 }
2489
2490 if (V.getOpcode() == ISD::AND && isOneConstant(V.getOperand(1))) {
2491 Masked = true;
2492 V = V.getOperand(0);
2493 continue;
2494 }
2495
2496 break;
2497 }
2498
2499 // If this is not a carry, return.
2500 if (V.getResNo() != 1)
2501 return SDValue();
2502
2503 if (V.getOpcode() != ISD::ADDCARRY && V.getOpcode() != ISD::SUBCARRY &&
2504 V.getOpcode() != ISD::UADDO && V.getOpcode() != ISD::USUBO)
2505 return SDValue();
2506
2507 EVT VT = V.getNode()->getValueType(0);
2508 if (!TLI.isOperationLegalOrCustom(V.getOpcode(), VT))
2509 return SDValue();
2510
2511 // If the result is masked, then no matter what kind of bool it is we can
2512 // return. If it isn't, then we need to make sure the bool type is either 0 or
2513 // 1 and not other values.
2514 if (Masked ||
2515 TLI.getBooleanContents(V.getValueType()) ==
2516 TargetLoweringBase::ZeroOrOneBooleanContent)
2517 return V;
2518
2519 return SDValue();
2520}
2521
2522/// Given the operands of an add/sub operation, see if the 2nd operand is a
2523/// masked 0/1 whose source operand is actually known to be 0/-1. If so, invert
2524/// the opcode and bypass the mask operation.
2525static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
2526 SelectionDAG &DAG, const SDLoc &DL) {
2527 if (N1.getOpcode() != ISD::AND || !isOneOrOneSplat(N1->getOperand(1)))
2528 return SDValue();
2529
2530 EVT VT = N0.getValueType();
2531 if (DAG.ComputeNumSignBits(N1.getOperand(0)) != VT.getScalarSizeInBits())
2532 return SDValue();
2533
2534 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
2535 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
2536 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N1.getOperand(0));
2537}
2538
2539/// Helper for doing combines based on N0 and N1 being added to each other.
2540SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
2541 SDNode *LocReference) {
2542 EVT VT = N0.getValueType();
2543 SDLoc DL(LocReference);
2544
2545 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2546 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2547 isNullOrNullSplat(N1.getOperand(0).getOperand(0)))
2548 return DAG.getNode(ISD::SUB, DL, VT, N0,
2549 DAG.getNode(ISD::SHL, DL, VT,
2550 N1.getOperand(0).getOperand(1),
2551 N1.getOperand(1)));
2552
2553 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
2554 return V;
2555
2556 // Look for:
2557 // add (add x, 1), y
2558 // And if the target does not like this form then turn into:
2559 // sub y, (xor x, -1)
2560 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.hasOneUse() &&
2561 N0.getOpcode() == ISD::ADD && isOneOrOneSplat(N0.getOperand(1))) {
2562 SDValue Not = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
2563 DAG.getAllOnesConstant(DL, VT));
2564 return DAG.getNode(ISD::SUB, DL, VT, N1, Not);
2565 }
2566
2567 // Hoist one-use subtraction by non-opaque constant:
2568 // (x - C) + y -> (x + y) - C
2569 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
2570 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2571 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
2572 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
2573 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2574 }
2575 // Hoist one-use subtraction from non-opaque constant:
2576 // (C - x) + y -> (y - x) + C
2577 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
2578 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
2579 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
2580 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
2581 }
2582
2583 // If the target's bool is represented as 0/1, prefer to make this 'sub 0/1'
2584 // rather than 'add 0/-1' (the zext should get folded).
2585 // add (sext i1 Y), X --> sub X, (zext i1 Y)
2586 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
2587 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
2588 TLI.getBooleanContents(VT) == TargetLowering::ZeroOrOneBooleanContent) {
2589 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
2590 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
2591 }
2592
2593 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
2594 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
2595 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
2596 if (TN->getVT() == MVT::i1) {
2597 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
2598 DAG.getConstant(1, DL, VT));
2599 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
2600 }
2601 }
2602
2603 // (add X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2604 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1)) &&
2605 N1.getResNo() == 0)
2606 return DAG.getNode(ISD::ADDCARRY, DL, N1->getVTList(),
2607 N0, N1.getOperand(0), N1.getOperand(2));
2608
2609 // (add X, Carry) -> (addcarry X, 0, Carry)
2610 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2611 if (SDValue Carry = getAsCarry(TLI, N1))
2612 return DAG.getNode(ISD::ADDCARRY, DL,
2613 DAG.getVTList(VT, Carry.getValueType()), N0,
2614 DAG.getConstant(0, DL, VT), Carry);
2615
2616 return SDValue();
2617}
2618
2619SDValue DAGCombiner::visitADDC(SDNode *N) {
2620 SDValue N0 = N->getOperand(0);
2621 SDValue N1 = N->getOperand(1);
2622 EVT VT = N0.getValueType();
2623 SDLoc DL(N);
2624
2625 // If the flag result is dead, turn this into an ADD.
2626 if (!N->hasAnyUseOfValue(1))
2627 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2628 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2629
2630 // canonicalize constant to RHS.
2631 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2632 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2633 if (N0C && !N1C)
2634 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
2635
2636 // fold (addc x, 0) -> x + no carry out
2637 if (isNullConstant(N1))
2638 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
2639 DL, MVT::Glue));
2640
2641 // If it cannot overflow, transform into an add.
2642 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2643 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2644 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
2645
2646 return SDValue();
2647}
2648
2649static SDValue flipBoolean(SDValue V, const SDLoc &DL,
2650 SelectionDAG &DAG, const TargetLowering &TLI) {
2651 EVT VT = V.getValueType();
2652
2653 SDValue Cst;
2654 switch (TLI.getBooleanContents(VT)) {
2655 case TargetLowering::ZeroOrOneBooleanContent:
2656 case TargetLowering::UndefinedBooleanContent:
2657 Cst = DAG.getConstant(1, DL, VT);
2658 break;
2659 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2660 Cst = DAG.getAllOnesConstant(DL, VT);
2661 break;
2662 }
2663
2664 return DAG.getNode(ISD::XOR, DL, VT, V, Cst);
2665}
2666
2667/**
2668 * Flips a boolean if it is cheaper to compute. If the Force parameters is set,
2669 * then the flip also occurs if computing the inverse is the same cost.
2670 * This function returns an empty SDValue in case it cannot flip the boolean
2671 * without increasing the cost of the computation. If you want to flip a boolean
2672 * no matter what, use flipBoolean.
2673 */
2674static SDValue extractBooleanFlip(SDValue V, SelectionDAG &DAG,
2675 const TargetLowering &TLI,
2676 bool Force) {
2677 if (Force && isa<ConstantSDNode>(V))
2678 return flipBoolean(V, SDLoc(V), DAG, TLI);
2679
2680 if (V.getOpcode() != ISD::XOR)
2681 return SDValue();
2682
2683 ConstantSDNode *Const = isConstOrConstSplat(V.getOperand(1), false);
2684 if (!Const)
2685 return SDValue();
2686
2687 EVT VT = V.getValueType();
2688
2689 bool IsFlip = false;
2690 switch(TLI.getBooleanContents(VT)) {
2691 case TargetLowering::ZeroOrOneBooleanContent:
2692 IsFlip = Const->isOne();
2693 break;
2694 case TargetLowering::ZeroOrNegativeOneBooleanContent:
2695 IsFlip = Const->isAllOnesValue();
2696 break;
2697 case TargetLowering::UndefinedBooleanContent:
2698 IsFlip = (Const->getAPIntValue() & 0x01) == 1;
2699 break;
2700 }
2701
2702 if (IsFlip)
2703 return V.getOperand(0);
2704 if (Force)
2705 return flipBoolean(V, SDLoc(V), DAG, TLI);
2706 return SDValue();
2707}
2708
2709SDValue DAGCombiner::visitADDO(SDNode *N) {
2710 SDValue N0 = N->getOperand(0);
2711 SDValue N1 = N->getOperand(1);
2712 EVT VT = N0.getValueType();
2713 bool IsSigned = (ISD::SADDO == N->getOpcode());
2714
2715 EVT CarryVT = N->getValueType(1);
2716 SDLoc DL(N);
2717
2718 // If the flag result is dead, turn this into an ADD.
2719 if (!N->hasAnyUseOfValue(1))
2720 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2721 DAG.getUNDEF(CarryVT));
2722
2723 // canonicalize constant to RHS.
2724 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2725 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
2726 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
2727
2728 // fold (addo x, 0) -> x + no carry out
2729 if (isNullOrNullSplat(N1))
2730 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
2731
2732 if (!IsSigned) {
2733 // If it cannot overflow, transform into an add.
2734 if (DAG.computeOverflowKind(N0, N1) == SelectionDAG::OFK_Never)
2735 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
2736 DAG.getConstant(0, DL, CarryVT));
2737
2738 // fold (uaddo (xor a, -1), 1) -> (usub 0, a) and flip carry.
2739 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
2740 SDValue Sub = DAG.getNode(ISD::USUBO, DL, N->getVTList(),
2741 DAG.getConstant(0, DL, VT), N0.getOperand(0));
2742 return CombineTo(N, Sub,
2743 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
2744 }
2745
2746 if (SDValue Combined = visitUADDOLike(N0, N1, N))
2747 return Combined;
2748
2749 if (SDValue Combined = visitUADDOLike(N1, N0, N))
2750 return Combined;
2751 }
2752
2753 return SDValue();
2754}
2755
2756SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
2757 EVT VT = N0.getValueType();
2758 if (VT.isVector())
2759 return SDValue();
2760
2761 // (uaddo X, (addcarry Y, 0, Carry)) -> (addcarry X, Y, Carry)
2762 // If Y + 1 cannot overflow.
2763 if (N1.getOpcode() == ISD::ADDCARRY && isNullConstant(N1.getOperand(1))) {
2764 SDValue Y = N1.getOperand(0);
2765 SDValue One = DAG.getConstant(1, SDLoc(N), Y.getValueType());
2766 if (DAG.computeOverflowKind(Y, One) == SelectionDAG::OFK_Never)
2767 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0, Y,
2768 N1.getOperand(2));
2769 }
2770
2771 // (uaddo X, Carry) -> (addcarry X, 0, Carry)
2772 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT))
2773 if (SDValue Carry = getAsCarry(TLI, N1))
2774 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
2775 DAG.getConstant(0, SDLoc(N), VT), Carry);
2776
2777 return SDValue();
2778}
2779
2780SDValue DAGCombiner::visitADDE(SDNode *N) {
2781 SDValue N0 = N->getOperand(0);
2782 SDValue N1 = N->getOperand(1);
2783 SDValue CarryIn = N->getOperand(2);
2784
2785 // canonicalize constant to RHS
2786 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2787 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2788 if (N0C && !N1C)
2789 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
2790 N1, N0, CarryIn);
2791
2792 // fold (adde x, y, false) -> (addc x, y)
2793 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2794 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
2795
2796 return SDValue();
2797}
2798
2799SDValue DAGCombiner::visitADDCARRY(SDNode *N) {
2800 SDValue N0 = N->getOperand(0);
2801 SDValue N1 = N->getOperand(1);
2802 SDValue CarryIn = N->getOperand(2);
2803 SDLoc DL(N);
2804
2805 // canonicalize constant to RHS
2806 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2807 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2808 if (N0C && !N1C)
2809 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), N1, N0, CarryIn);
2810
2811 // fold (addcarry x, y, false) -> (uaddo x, y)
2812 if (isNullConstant(CarryIn)) {
2813 if (!LegalOperations ||
2814 TLI.isOperationLegalOrCustom(ISD::UADDO, N->getValueType(0)))
2815 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
2816 }
2817
2818 // fold (addcarry 0, 0, X) -> (and (ext/trunc X), 1) and no carry.
2819 if (isNullConstant(N0) && isNullConstant(N1)) {
2820 EVT VT = N0.getValueType();
2821 EVT CarryVT = CarryIn.getValueType();
2822 SDValue CarryExt = DAG.getBoolExtOrTrunc(CarryIn, DL, VT, CarryVT);
2823 AddToWorklist(CarryExt.getNode());
2824 return CombineTo(N, DAG.getNode(ISD::AND, DL, VT, CarryExt,
2825 DAG.getConstant(1, DL, VT)),
2826 DAG.getConstant(0, DL, CarryVT));
2827 }
2828
2829 if (SDValue Combined = visitADDCARRYLike(N0, N1, CarryIn, N))
2830 return Combined;
2831
2832 if (SDValue Combined = visitADDCARRYLike(N1, N0, CarryIn, N))
2833 return Combined;
2834
2835 return SDValue();
2836}
2837
2838/**
2839 * If we are facing some sort of diamond carry propapagtion pattern try to
2840 * break it up to generate something like:
2841 * (addcarry X, 0, (addcarry A, B, Z):Carry)
2842 *
2843 * The end result is usually an increase in operation required, but because the
2844 * carry is now linearized, other tranforms can kick in and optimize the DAG.
2845 *
2846 * Patterns typically look something like
2847 * (uaddo A, B)
2848 * / \
2849 * Carry Sum
2850 * | \
2851 * | (addcarry *, 0, Z)
2852 * | /
2853 * \ Carry
2854 * | /
2855 * (addcarry X, *, *)
2856 *
2857 * But numerous variation exist. Our goal is to identify A, B, X and Z and
2858 * produce a combine with a single path for carry propagation.
2859 */
2860static SDValue combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
2861 SDValue X, SDValue Carry0, SDValue Carry1,
2862 SDNode *N) {
2863 if (Carry1.getResNo() != 1 || Carry0.getResNo() != 1)
2864 return SDValue();
2865 if (Carry1.getOpcode() != ISD::UADDO)
2866 return SDValue();
2867
2868 SDValue Z;
2869
2870 /**
2871 * First look for a suitable Z. It will present itself in the form of
2872 * (addcarry Y, 0, Z) or its equivalent (uaddo Y, 1) for Z=true
2873 */
2874 if (Carry0.getOpcode() == ISD::ADDCARRY &&
2875 isNullConstant(Carry0.getOperand(1))) {
2876 Z = Carry0.getOperand(2);
2877 } else if (Carry0.getOpcode() == ISD::UADDO &&
2878 isOneConstant(Carry0.getOperand(1))) {
2879 EVT VT = Combiner.getSetCCResultType(Carry0.getValueType());
2880 Z = DAG.getConstant(1, SDLoc(Carry0.getOperand(1)), VT);
2881 } else {
2882 // We couldn't find a suitable Z.
2883 return SDValue();
2884 }
2885
2886
2887 auto cancelDiamond = [&](SDValue A,SDValue B) {
2888 SDLoc DL(N);
2889 SDValue NewY = DAG.getNode(ISD::ADDCARRY, DL, Carry0->getVTList(), A, B, Z);
2890 Combiner.AddToWorklist(NewY.getNode());
2891 return DAG.getNode(ISD::ADDCARRY, DL, N->getVTList(), X,
2892 DAG.getConstant(0, DL, X.getValueType()),
2893 NewY.getValue(1));
2894 };
2895
2896 /**
2897 * (uaddo A, B)
2898 * |
2899 * Sum
2900 * |
2901 * (addcarry *, 0, Z)
2902 */
2903 if (Carry0.getOperand(0) == Carry1.getValue(0)) {
2904 return cancelDiamond(Carry1.getOperand(0), Carry1.getOperand(1));
2905 }
2906
2907 /**
2908 * (addcarry A, 0, Z)
2909 * |
2910 * Sum
2911 * |
2912 * (uaddo *, B)
2913 */
2914 if (Carry1.getOperand(0) == Carry0.getValue(0)) {
2915 return cancelDiamond(Carry0.getOperand(0), Carry1.getOperand(1));
2916 }
2917
2918 if (Carry1.getOperand(1) == Carry0.getValue(0)) {
2919 return cancelDiamond(Carry1.getOperand(0), Carry0.getOperand(0));
2920 }
2921
2922 return SDValue();
2923}
2924
2925// If we are facing some sort of diamond carry/borrow in/out pattern try to
2926// match patterns like:
2927//
2928// (uaddo A, B) CarryIn
2929// | \ |
2930// | \ |
2931// PartialSum PartialCarryOutX /
2932// | | /
2933// | ____|____________/
2934// | / |
2935// (uaddo *, *) \________
2936// | \ \
2937// | \ |
2938// | PartialCarryOutY |
2939// | \ |
2940// | \ /
2941// AddCarrySum | ______/
2942// | /
2943// CarryOut = (or *, *)
2944//
2945// And generate ADDCARRY (or SUBCARRY) with two result values:
2946//
2947// {AddCarrySum, CarryOut} = (addcarry A, B, CarryIn)
2948//
2949// Our goal is to identify A, B, and CarryIn and produce ADDCARRY/SUBCARRY with
2950// a single path for carry/borrow out propagation:
2951static SDValue combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG,
2952 const TargetLowering &TLI, SDValue Carry0,
2953 SDValue Carry1, SDNode *N) {
2954 if (Carry0.getResNo() != 1 || Carry1.getResNo() != 1)
2955 return SDValue();
2956 unsigned Opcode = Carry0.getOpcode();
2957 if (Opcode != Carry1.getOpcode())
2958 return SDValue();
2959 if (Opcode != ISD::UADDO && Opcode != ISD::USUBO)
2960 return SDValue();
2961
2962 // Canonicalize the add/sub of A and B as Carry0 and the add/sub of the
2963 // carry/borrow in as Carry1. (The top and middle uaddo nodes respectively in
2964 // the above ASCII art.)
2965 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
2966 Carry1.getOperand(1) != Carry0.getValue(0))
2967 std::swap(Carry0, Carry1);
2968 if (Carry1.getOperand(0) != Carry0.getValue(0) &&
2969 Carry1.getOperand(1) != Carry0.getValue(0))
2970 return SDValue();
2971
2972 // The carry in value must be on the righthand side for subtraction.
2973 unsigned CarryInOperandNum =
2974 Carry1.getOperand(0) == Carry0.getValue(0) ? 1 : 0;
2975 if (Opcode == ISD::USUBO && CarryInOperandNum != 1)
2976 return SDValue();
2977 SDValue CarryIn = Carry1.getOperand(CarryInOperandNum);
2978
2979 unsigned NewOp = Opcode == ISD::UADDO ? ISD::ADDCARRY : ISD::SUBCARRY;
2980 if (!TLI.isOperationLegalOrCustom(NewOp, Carry0.getValue(0).getValueType()))
2981 return SDValue();
2982
2983 // Verify that the carry/borrow in is plausibly a carry/borrow bit.
2984 // TODO: make getAsCarry() aware of how partial carries are merged.
2985 if (CarryIn.getOpcode() != ISD::ZERO_EXTEND)
2986 return SDValue();
2987 CarryIn = CarryIn.getOperand(0);
2988 if (CarryIn.getValueType() != MVT::i1)
2989 return SDValue();
2990
2991 SDLoc DL(N);
2992 SDValue Merged =
2993 DAG.getNode(NewOp, DL, Carry1->getVTList(), Carry0.getOperand(0),
2994 Carry0.getOperand(1), CarryIn);
2995
2996 // Please note that because we have proven that the result of the UADDO/USUBO
2997 // of A and B feeds into the UADDO/USUBO that does the carry/borrow in, we can
2998 // therefore prove that if the first UADDO/USUBO overflows, the second
2999 // UADDO/USUBO cannot. For example consider 8-bit numbers where 0xFF is the
3000 // maximum value.
3001 //
3002 // 0xFF + 0xFF == 0xFE with carry but 0xFE + 1 does not carry
3003 // 0x00 - 0xFF == 1 with a carry/borrow but 1 - 1 == 0 (no carry/borrow)
3004 //
3005 // This is important because it means that OR and XOR can be used to merge
3006 // carry flags; and that AND can return a constant zero.
3007 //
3008 // TODO: match other operations that can merge flags (ADD, etc)
3009 DAG.ReplaceAllUsesOfValueWith(Carry1.getValue(0), Merged.getValue(0));
3010 if (N->getOpcode() == ISD::AND)
3011 return DAG.getConstant(0, DL, MVT::i1);
3012 return Merged.getValue(1);
3013}
3014
3015SDValue DAGCombiner::visitADDCARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
3016 SDNode *N) {
3017 // fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
3018 if (isBitwiseNot(N0))
3019 if (SDValue NotC = extractBooleanFlip(CarryIn, DAG, TLI, true)) {
3020 SDLoc DL(N);
3021 SDValue Sub = DAG.getNode(ISD::SUBCARRY, DL, N->getVTList(), N1,
3022 N0.getOperand(0), NotC);
3023 return CombineTo(N, Sub,
3024 flipBoolean(Sub.getValue(1), DL, DAG, TLI));
3025 }
3026
3027 // Iff the flag result is dead:
3028 // (addcarry (add|uaddo X, Y), 0, Carry) -> (addcarry X, Y, Carry)
3029 // Don't do this if the Carry comes from the uaddo. It won't remove the uaddo
3030 // or the dependency between the instructions.
3031 if ((N0.getOpcode() == ISD::ADD ||
3032 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
3033 N0.getValue(1) != CarryIn)) &&
3034 isNullConstant(N1) && !N->hasAnyUseOfValue(1))
3035 return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(),
3036 N0.getOperand(0), N0.getOperand(1), CarryIn);
3037
3038 /**
3039 * When one of the addcarry argument is itself a carry, we may be facing
3040 * a diamond carry propagation. In which case we try to transform the DAG
3041 * to ensure linear carry propagation if that is possible.
3042 */
3043 if (auto Y = getAsCarry(TLI, N1)) {
3044 // Because both are carries, Y and Z can be swapped.
3045 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
3046 return R;
3047 if (auto R = combineADDCARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
3048 return R;
3049 }
3050
3051 return SDValue();
3052}
3053
3054// Since it may not be valid to emit a fold to zero for vector initializers
3055// check if we can before folding.
3056static SDValue tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT,
3057 SelectionDAG &DAG, bool LegalOperations) {
3058 if (!VT.isVector())
3059 return DAG.getConstant(0, DL, VT);
3060 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
3061 return DAG.getConstant(0, DL, VT);
3062 return SDValue();
3063}
3064
3065SDValue DAGCombiner::visitSUB(SDNode *N) {
3066 SDValue N0 = N->getOperand(0);
3067 SDValue N1 = N->getOperand(1);
3068 EVT VT = N0.getValueType();
3069 SDLoc DL(N);
3070
3071 // fold vector ops
3072 if (VT.isVector()) {
3073 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3074 return FoldedVOp;
3075
3076 // fold (sub x, 0) -> x, vector edition
3077 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3078 return N0;
3079 }
3080
3081 // fold (sub x, x) -> 0
3082 // FIXME: Refactor this and xor and other similar operations together.
3083 if (N0 == N1)
3084 return tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
3085
3086 // fold (sub c1, c2) -> c3
3087 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
3088 return C;
3089
3090 if (SDValue NewSel = foldBinOpIntoSelect(N))
3091 return NewSel;
3092
3093 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3094
3095 // fold (sub x, c) -> (add x, -c)
3096 if (N1C) {
3097 return DAG.getNode(ISD::ADD, DL, VT, N0,
3098 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3099 }
3100
3101 if (isNullOrNullSplat(N0)) {
3102 unsigned BitWidth = VT.getScalarSizeInBits();
3103 // Right-shifting everything out but the sign bit followed by negation is
3104 // the same as flipping arithmetic/logical shift type without the negation:
3105 // -(X >>u 31) -> (X >>s 31)
3106 // -(X >>s 31) -> (X >>u 31)
3107 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3108 ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1));
3109 if (ShiftAmt && ShiftAmt->getAPIntValue() == (BitWidth - 1)) {
3110 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
3111 if (!LegalOperations || TLI.isOperationLegal(NewSh, VT))
3112 return DAG.getNode(NewSh, DL, VT, N1.getOperand(0), N1.getOperand(1));
3113 }
3114 }
3115
3116 // 0 - X --> 0 if the sub is NUW.
3117 if (N->getFlags().hasNoUnsignedWrap())
3118 return N0;
3119
3120 if (DAG.MaskedValueIsZero(N1, ~APInt::getSignMask(BitWidth))) {
3121 // N1 is either 0 or the minimum signed value. If the sub is NSW, then
3122 // N1 must be 0 because negating the minimum signed value is undefined.
3123 if (N->getFlags().hasNoSignedWrap())
3124 return N0;
3125
3126 // 0 - X --> X if X is 0 or the minimum signed value.
3127 return N1;
3128 }
3129 }
3130
3131 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
3132 if (isAllOnesOrAllOnesSplat(N0))
3133 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
3134
3135 // fold (A - (0-B)) -> A+B
3136 if (N1.getOpcode() == ISD::SUB && isNullOrNullSplat(N1.getOperand(0)))
3137 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
3138
3139 // fold A-(A-B) -> B
3140 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3141 return N1.getOperand(1);
3142
3143 // fold (A+B)-A -> B
3144 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3145 return N0.getOperand(1);
3146
3147 // fold (A+B)-B -> A
3148 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
3149 return N0.getOperand(0);
3150
3151 // fold (A+C1)-C2 -> A+(C1-C2)
3152 if (N0.getOpcode() == ISD::ADD &&
3153 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3154 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3155 SDValue NewC =
3156 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(1), N1});
3157 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3157, __PRETTY_FUNCTION__))
;
3158 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
3159 }
3160
3161 // fold C2-(A+C1) -> (C2-C1)-A
3162 if (N1.getOpcode() == ISD::ADD) {
3163 SDValue N11 = N1.getOperand(1);
3164 if (isConstantOrConstantVector(N0, /* NoOpaques */ true) &&
3165 isConstantOrConstantVector(N11, /* NoOpaques */ true)) {
3166 SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11});
3167 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3167, __PRETTY_FUNCTION__))
;
3168 return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
3169 }
3170 }
3171
3172 // fold (A-C1)-C2 -> A-(C1+C2)
3173 if (N0.getOpcode() == ISD::SUB &&
3174 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3175 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3176 SDValue NewC =
3177 DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0.getOperand(1), N1});
3178 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3178, __PRETTY_FUNCTION__))
;
3179 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
3180 }
3181
3182 // fold (c1-A)-c2 -> (c1-c2)-A
3183 if (N0.getOpcode() == ISD::SUB &&
3184 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3185 isConstantOrConstantVector(N0.getOperand(0), /* NoOpaques */ true)) {
3186 SDValue NewC =
3187 DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0.getOperand(0), N1});
3188 assert(NewC && "Constant folding failed")((NewC && "Constant folding failed") ? static_cast<
void> (0) : __assert_fail ("NewC && \"Constant folding failed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3188, __PRETTY_FUNCTION__))
;
3189 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
3190 }
3191
3192 // fold ((A+(B+or-C))-B) -> A+or-C
3193 if (N0.getOpcode() == ISD::ADD &&
3194 (N0.getOperand(1).getOpcode() == ISD::SUB ||
3195 N0.getOperand(1).getOpcode() == ISD::ADD) &&
3196 N0.getOperand(1).getOperand(0) == N1)
3197 return DAG.getNode(N0.getOperand(1).getOpcode(), DL, VT, N0.getOperand(0),
3198 N0.getOperand(1).getOperand(1));
3199
3200 // fold ((A+(C+B))-B) -> A+C
3201 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1).getOpcode() == ISD::ADD &&
3202 N0.getOperand(1).getOperand(1) == N1)
3203 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0),
3204 N0.getOperand(1).getOperand(0));
3205
3206 // fold ((A-(B-C))-C) -> A-B
3207 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1).getOpcode() == ISD::SUB &&
3208 N0.getOperand(1).getOperand(1) == N1)
3209 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0),
3210 N0.getOperand(1).getOperand(0));
3211
3212 // fold (A-(B-C)) -> A+(C-B)
3213 if (N1.getOpcode() == ISD::SUB && N1.hasOneUse())
3214 return DAG.getNode(ISD::ADD, DL, VT, N0,
3215 DAG.getNode(ISD::SUB, DL, VT, N1.getOperand(1),
3216 N1.getOperand(0)));
3217
3218 // A - (A & B) -> A & (~B)
3219 if (N1.getOpcode() == ISD::AND) {
3220 SDValue A = N1.getOperand(0);
3221 SDValue B = N1.getOperand(1);
3222 if (A != N0)
3223 std::swap(A, B);
3224 if (A == N0 &&
3225 (N1.hasOneUse() || isConstantOrConstantVector(B, /*NoOpaques=*/true))) {
3226 SDValue InvB =
3227 DAG.getNode(ISD::XOR, DL, VT, B, DAG.getAllOnesConstant(DL, VT));
3228 return DAG.getNode(ISD::AND, DL, VT, A, InvB);
3229 }
3230 }
3231
3232 // fold (X - (-Y * Z)) -> (X + (Y * Z))
3233 if (N1.getOpcode() == ISD::MUL && N1.hasOneUse()) {
3234 if (N1.getOperand(0).getOpcode() == ISD::SUB &&
3235 isNullOrNullSplat(N1.getOperand(0).getOperand(0))) {
3236 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3237 N1.getOperand(0).getOperand(1),
3238 N1.getOperand(1));
3239 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3240 }
3241 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
3242 isNullOrNullSplat(N1.getOperand(1).getOperand(0))) {
3243 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT,
3244 N1.getOperand(0),
3245 N1.getOperand(1).getOperand(1));
3246 return DAG.getNode(ISD::ADD, DL, VT, N0, Mul);
3247 }
3248 }
3249
3250 // If either operand of a sub is undef, the result is undef
3251 if (N0.isUndef())
3252 return N0;
3253 if (N1.isUndef())
3254 return N1;
3255
3256 if (SDValue V = foldAddSubBoolOfMaskedVal(N, DAG))
3257 return V;
3258
3259 if (SDValue V = foldAddSubOfSignBit(N, DAG))
3260 return V;
3261
3262 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, SDLoc(N)))
3263 return V;
3264
3265 // (x - y) - 1 -> add (xor y, -1), x
3266 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB && isOneOrOneSplat(N1)) {
3267 SDValue Xor = DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
3268 DAG.getAllOnesConstant(DL, VT));
3269 return DAG.getNode(ISD::ADD, DL, VT, Xor, N0.getOperand(0));
3270 }
3271
3272 // Look for:
3273 // sub y, (xor x, -1)
3274 // And if the target does not like this form then turn into:
3275 // add (add x, y), 1
3276 if (TLI.preferIncOfAddToSubOfNot(VT) && N1.hasOneUse() && isBitwiseNot(N1)) {
3277 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
3278 return DAG.getNode(ISD::ADD, DL, VT, Add, DAG.getConstant(1, DL, VT));
3279 }
3280
3281 // Hoist one-use addition by non-opaque constant:
3282 // (x + C) - y -> (x - y) + C
3283 if (N0.hasOneUse() && N0.getOpcode() == ISD::ADD &&
3284 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3285 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3286 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
3287 }
3288 // y - (x + C) -> (y - x) - C
3289 if (N1.hasOneUse() && N1.getOpcode() == ISD::ADD &&
3290 isConstantOrConstantVector(N1.getOperand(1), /*NoOpaques=*/true)) {
3291 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
3292 return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
3293 }
3294 // (x - C) - y -> (x - y) - C
3295 // This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
3296 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3297 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3298 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
3299 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
3300 }
3301 // (C - x) - y -> C - (x + y)
3302 if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
3303 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3304 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
3305 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
3306 }
3307
3308 // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
3309 // rather than 'sub 0/1' (the sext should get folded).
3310 // sub X, (zext i1 Y) --> add X, (sext i1 Y)
3311 if (N1.getOpcode() == ISD::ZERO_EXTEND &&
3312 N1.getOperand(0).getScalarValueSizeInBits() == 1 &&
3313 TLI.getBooleanContents(VT) ==
3314 TargetLowering::ZeroOrNegativeOneBooleanContent) {
3315 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0));
3316 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
3317 }
3318
3319 // fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
3320 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
3321 if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
3322 SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
3323 SDValue S0 = N1.getOperand(0);
3324 if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0)) {
3325 unsigned OpSizeInBits = VT.getScalarSizeInBits();
3326 if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
3327 if (C->getAPIntValue() == (OpSizeInBits - 1))
3328 return DAG.getNode(ISD::ABS, SDLoc(N), VT, S0);
3329 }
3330 }
3331 }
3332
3333 // If the relocation model supports it, consider symbol offsets.
3334 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
3335 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
3336 // fold (sub Sym, c) -> Sym-c
3337 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
3338 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
3339 GA->getOffset() -
3340 (uint64_t)N1C->getSExtValue());
3341 // fold (sub Sym+c1, Sym+c2) -> c1-c2
3342 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
3343 if (GA->getGlobal() == GB->getGlobal())
3344 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
3345 DL, VT);
3346 }
3347
3348 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
3349 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
3350 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
3351 if (TN->getVT() == MVT::i1) {
3352 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
3353 DAG.getConstant(1, DL, VT));
3354 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
3355 }
3356 }
3357
3358 // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
3359 if (N1.getOpcode() == ISD::VSCALE) {
3360 APInt IntVal = N1.getConstantOperandAPInt(0);
3361 return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
3362 }
3363
3364 // Prefer an add for more folding potential and possibly better codegen:
3365 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
3366 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
3367 SDValue ShAmt = N1.getOperand(1);
3368 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
3369 if (ShAmtC &&
3370 ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) {
3371 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
3372 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
3373 }
3374 }
3375
3376 if (TLI.isOperationLegalOrCustom(ISD::ADDCARRY, VT)) {
3377 // (sub Carry, X) -> (addcarry (sub 0, X), 0, Carry)
3378 if (SDValue Carry = getAsCarry(TLI, N0)) {
3379 SDValue X = N1;
3380 SDValue Zero = DAG.getConstant(0, DL, VT);
3381 SDValue NegX = DAG.getNode(ISD::SUB, DL, VT, Zero, X);
3382 return DAG.getNode(ISD::ADDCARRY, DL,
3383 DAG.getVTList(VT, Carry.getValueType()), NegX, Zero,
3384 Carry);
3385 }
3386 }
3387
3388 return SDValue();
3389}
3390
3391SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
3392 SDValue N0 = N->getOperand(0);
3393 SDValue N1 = N->getOperand(1);
3394 EVT VT = N0.getValueType();
3395 SDLoc DL(N);
3396
3397 // fold vector ops
3398 if (VT.isVector()) {
3399 // TODO SimplifyVBinOp
3400
3401 // fold (sub_sat x, 0) -> x, vector edition
3402 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3403 return N0;
3404 }
3405
3406 // fold (sub_sat x, undef) -> 0
3407 if (N0.isUndef() || N1.isUndef())
3408 return DAG.getConstant(0, DL, VT);
3409
3410 // fold (sub_sat x, x) -> 0
3411 if (N0 == N1)
3412 return DAG.getConstant(0, DL, VT);
3413
3414 // fold (sub_sat c1, c2) -> c3
3415 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
3416 return C;
3417
3418 // fold (sub_sat x, 0) -> x
3419 if (isNullConstant(N1))
3420 return N0;
3421
3422 return SDValue();
3423}
3424
3425SDValue DAGCombiner::visitSUBC(SDNode *N) {
3426 SDValue N0 = N->getOperand(0);
3427 SDValue N1 = N->getOperand(1);
3428 EVT VT = N0.getValueType();
3429 SDLoc DL(N);
3430
3431 // If the flag result is dead, turn this into an SUB.
3432 if (!N->hasAnyUseOfValue(1))
3433 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3434 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3435
3436 // fold (subc x, x) -> 0 + no borrow
3437 if (N0 == N1)
3438 return CombineTo(N, DAG.getConstant(0, DL, VT),
3439 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3440
3441 // fold (subc x, 0) -> x + no borrow
3442 if (isNullConstant(N1))
3443 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3444
3445 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3446 if (isAllOnesConstant(N0))
3447 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3448 DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
3449
3450 return SDValue();
3451}
3452
3453SDValue DAGCombiner::visitSUBO(SDNode *N) {
3454 SDValue N0 = N->getOperand(0);
3455 SDValue N1 = N->getOperand(1);
3456 EVT VT = N0.getValueType();
3457 bool IsSigned = (ISD::SSUBO == N->getOpcode());
3458
3459 EVT CarryVT = N->getValueType(1);
3460 SDLoc DL(N);
3461
3462 // If the flag result is dead, turn this into an SUB.
3463 if (!N->hasAnyUseOfValue(1))
3464 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
3465 DAG.getUNDEF(CarryVT));
3466
3467 // fold (subo x, x) -> 0 + no borrow
3468 if (N0 == N1)
3469 return CombineTo(N, DAG.getConstant(0, DL, VT),
3470 DAG.getConstant(0, DL, CarryVT));
3471
3472 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3473
3474 // fold (subox, c) -> (addo x, -c)
3475 if (IsSigned && N1C && !N1C->getAPIntValue().isMinSignedValue()) {
3476 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
3477 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
3478 }
3479
3480 // fold (subo x, 0) -> x + no borrow
3481 if (isNullOrNullSplat(N1))
3482 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3483
3484 // Canonicalize (usubo -1, x) -> ~x, i.e. (xor x, -1) + no borrow
3485 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
3486 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
3487 DAG.getConstant(0, DL, CarryVT));
3488
3489 return SDValue();
3490}
3491
3492SDValue DAGCombiner::visitSUBE(SDNode *N) {
3493 SDValue N0 = N->getOperand(0);
3494 SDValue N1 = N->getOperand(1);
3495 SDValue CarryIn = N->getOperand(2);
3496
3497 // fold (sube x, y, false) -> (subc x, y)
3498 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
3499 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
3500
3501 return SDValue();
3502}
3503
3504SDValue DAGCombiner::visitSUBCARRY(SDNode *N) {
3505 SDValue N0 = N->getOperand(0);
3506 SDValue N1 = N->getOperand(1);
3507 SDValue CarryIn = N->getOperand(2);
3508
3509 // fold (subcarry x, y, false) -> (usubo x, y)
3510 if (isNullConstant(CarryIn)) {
3511 if (!LegalOperations ||
3512 TLI.isOperationLegalOrCustom(ISD::USUBO, N->getValueType(0)))
3513 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
3514 }
3515
3516 return SDValue();
3517}
3518
3519// Notice that "mulfix" can be any of SMULFIX, SMULFIXSAT, UMULFIX and
3520// UMULFIXSAT here.
3521SDValue DAGCombiner::visitMULFIX(SDNode *N) {
3522 SDValue N0 = N->getOperand(0);
3523 SDValue N1 = N->getOperand(1);
3524 SDValue Scale = N->getOperand(2);
3525 EVT VT = N0.getValueType();
3526
3527 // fold (mulfix x, undef, scale) -> 0
3528 if (N0.isUndef() || N1.isUndef())
3529 return DAG.getConstant(0, SDLoc(N), VT);
3530
3531 // Canonicalize constant to RHS (vector doesn't have to splat)
3532 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3533 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3534 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
3535
3536 // fold (mulfix x, 0, scale) -> 0
3537 if (isNullConstant(N1))
3538 return DAG.getConstant(0, SDLoc(N), VT);
3539
3540 return SDValue();
3541}
3542
3543SDValue DAGCombiner::visitMUL(SDNode *N) {
3544 SDValue N0 = N->getOperand(0);
3545 SDValue N1 = N->getOperand(1);
3546 EVT VT = N0.getValueType();
3547
3548 // fold (mul x, undef) -> 0
3549 if (N0.isUndef() || N1.isUndef())
3550 return DAG.getConstant(0, SDLoc(N), VT);
3551
3552 bool N1IsConst = false;
3553 bool N1IsOpaqueConst = false;
3554 APInt ConstValue1;
3555
3556 // fold vector ops
3557 if (VT.isVector()) {
3558 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3559 return FoldedVOp;
3560
3561 N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
3562 assert((!N1IsConst ||(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3564, __PRETTY_FUNCTION__))
3563 ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) &&(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3564, __PRETTY_FUNCTION__))
3564 "Splat APInt should be element width")(((!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits
()) && "Splat APInt should be element width") ? static_cast
<void> (0) : __assert_fail ("(!N1IsConst || ConstValue1.getBitWidth() == VT.getScalarSizeInBits()) && \"Splat APInt should be element width\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3564, __PRETTY_FUNCTION__))
;
3565 } else {
3566 N1IsConst = isa<ConstantSDNode>(N1);
3567 if (N1IsConst) {
3568 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
3569 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
3570 }
3571 }
3572
3573 // fold (mul c1, c2) -> c1*c2
3574 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT, {N0, N1}))
3575 return C;
3576
3577 // canonicalize constant to RHS (vector doesn't have to splat)
3578 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3579 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
3580 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
3581
3582 // fold (mul x, 0) -> 0
3583 if (N1IsConst && ConstValue1.isNullValue())
3584 return N1;
3585
3586 // fold (mul x, 1) -> x
3587 if (N1IsConst && ConstValue1.isOneValue())
3588 return N0;
3589
3590 if (SDValue NewSel = foldBinOpIntoSelect(N))
3591 return NewSel;
3592
3593 // fold (mul x, -1) -> 0-x
3594 if (N1IsConst && ConstValue1.isAllOnesValue()) {
3595 SDLoc DL(N);
3596 return DAG.getNode(ISD::SUB, DL, VT,
3597 DAG.getConstant(0, DL, VT), N0);
3598 }
3599
3600 // fold (mul x, (1 << c)) -> x << c
3601 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
3602 DAG.isKnownToBeAPowerOfTwo(N1) &&
3603 (!VT.isVector() || Level <= AfterLegalizeVectorOps)) {
3604 SDLoc DL(N);
3605 SDValue LogBase2 = BuildLogBase2(N1, DL);
3606 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
3607 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
3608 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3609 }
3610
3611 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
3612 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2()) {
3613 unsigned Log2Val = (-ConstValue1).logBase2();
3614 SDLoc DL(N);
3615 // FIXME: If the input is something that is easily negated (e.g. a
3616 // single-use add), we should put the negate there.
3617 return DAG.getNode(ISD::SUB, DL, VT,
3618 DAG.getConstant(0, DL, VT),
3619 DAG.getNode(ISD::SHL, DL, VT, N0,
3620 DAG.getConstant(Log2Val, DL,
3621 getShiftAmountTy(N0.getValueType()))));
3622 }
3623
3624 // Try to transform multiply-by-(power-of-2 +/- 1) into shift and add/sub.
3625 // mul x, (2^N + 1) --> add (shl x, N), x
3626 // mul x, (2^N - 1) --> sub (shl x, N), x
3627 // Examples: x * 33 --> (x << 5) + x
3628 // x * 15 --> (x << 4) - x
3629 // x * -33 --> -((x << 5) + x)
3630 // x * -15 --> -((x << 4) - x) ; this reduces --> x - (x << 4)
3631 if (N1IsConst && TLI.decomposeMulByConstant(*DAG.getContext(), VT, N1)) {
3632 // TODO: We could handle more general decomposition of any constant by
3633 // having the target set a limit on number of ops and making a
3634 // callback to determine that sequence (similar to sqrt expansion).
3635 unsigned MathOp = ISD::DELETED_NODE;
3636 APInt MulC = ConstValue1.abs();
3637 if ((MulC - 1).isPowerOf2())
3638 MathOp = ISD::ADD;
3639 else if ((MulC + 1).isPowerOf2())
3640 MathOp = ISD::SUB;
3641
3642 if (MathOp != ISD::DELETED_NODE) {
3643 unsigned ShAmt =
3644 MathOp == ISD::ADD ? (MulC - 1).logBase2() : (MulC + 1).logBase2();
3645 assert(ShAmt < VT.getScalarSizeInBits() &&((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3646, __PRETTY_FUNCTION__))
3646 "multiply-by-constant generated out of bounds shift")((ShAmt < VT.getScalarSizeInBits() && "multiply-by-constant generated out of bounds shift"
) ? static_cast<void> (0) : __assert_fail ("ShAmt < VT.getScalarSizeInBits() && \"multiply-by-constant generated out of bounds shift\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3646, __PRETTY_FUNCTION__))
;
3647 SDLoc DL(N);
3648 SDValue Shl =
3649 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
3650 SDValue R = DAG.getNode(MathOp, DL, VT, Shl, N0);
3651 if (ConstValue1.isNegative())
3652 R = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), R);
3653 return R;
3654 }
3655 }
3656
3657 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
3658 if (N0.getOpcode() == ISD::SHL &&
3659 isConstantOrConstantVector(N1, /* NoOpaques */ true) &&
3660 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaques */ true)) {
3661 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
3662 if (isConstantOrConstantVector(C3))
3663 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
3664 }
3665
3666 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
3667 // use.
3668 {
3669 SDValue Sh(nullptr, 0), Y(nullptr, 0);
3670
3671 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
3672 if (N0.getOpcode() == ISD::SHL &&
3673 isConstantOrConstantVector(N0.getOperand(1)) &&
3674 N0.getNode()->hasOneUse()) {
3675 Sh = N0; Y = N1;
3676 } else if (N1.getOpcode() == ISD::SHL &&
3677 isConstantOrConstantVector(N1.getOperand(1)) &&
3678 N1.getNode()->hasOneUse()) {
3679 Sh = N1; Y = N0;
3680 }
3681
3682 if (Sh.getNode()) {
3683 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, Sh.getOperand(0), Y);
3684 return DAG.getNode(ISD::SHL, SDLoc(N), VT, Mul, Sh.getOperand(1));
3685 }
3686 }
3687
3688 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
3689 if (DAG.isConstantIntBuildVectorOrConstantInt(N1) &&
3690 N0.getOpcode() == ISD::ADD &&
3691 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
3692 isMulAddWithConstProfitable(N, N0, N1))
3693 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
3694 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
3695 N0.getOperand(0), N1),
3696 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
3697 N0.getOperand(1), N1));
3698
3699 // Fold (mul (vscale * C0), C1) to (vscale * (C0 * C1)).
3700 if (N0.getOpcode() == ISD::VSCALE)
3701 if (ConstantSDNode *NC1 = isConstOrConstSplat(N1)) {
3702 APInt C0 = N0.getConstantOperandAPInt(0);
3703 APInt C1 = NC1->getAPIntValue();
3704 return DAG.getVScale(SDLoc(N), VT, C0 * C1);
3705 }
3706
3707 // reassociate mul
3708 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3709 return RMUL;
3710
3711 return SDValue();
3712}
3713
3714/// Return true if divmod libcall is available.
3715static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
3716 const TargetLowering &TLI) {
3717 RTLIB::Libcall LC;
3718 EVT NodeType = Node->getValueType(0);
3719 if (!NodeType.isSimple())
3720 return false;
3721 switch (NodeType.getSimpleVT().SimpleTy) {
3722 default: return false; // No libcall for vector types.
3723 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
3724 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
3725 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
3726 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
3727 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
3728 }
3729
3730 return TLI.getLibcallName(LC) != nullptr;
3731}
3732
3733/// Issue divrem if both quotient and remainder are needed.
3734SDValue DAGCombiner::useDivRem(SDNode *Node) {
3735 if (Node->use_empty())
3736 return SDValue(); // This is a dead node, leave it alone.
3737
3738 unsigned Opcode = Node->getOpcode();
3739 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3740 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3741
3742 // DivMod lib calls can still work on non-legal types if using lib-calls.
3743 EVT VT = Node->getValueType(0);
3744 if (VT.isVector() || !VT.isInteger())
3745 return SDValue();
3746
3747 if (!TLI.isTypeLegal(VT) && !TLI.isOperationCustom(DivRemOpc, VT))
3748 return SDValue();
3749
3750 // If DIVREM is going to get expanded into a libcall,
3751 // but there is no libcall available, then don't combine.
3752 if (!TLI.isOperationLegalOrCustom(DivRemOpc, VT) &&
3753 !isDivRemLibcallAvailable(Node, isSigned, TLI))
3754 return SDValue();
3755
3756 // If div is legal, it's better to do the normal expansion
3757 unsigned OtherOpcode = 0;
3758 if ((Opcode == ISD::SDIV) || (Opcode == ISD::UDIV)) {
3759 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3760 if (TLI.isOperationLegalOrCustom(Opcode, VT))
3761 return SDValue();
3762 } else {
3763 OtherOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
3764 if (TLI.isOperationLegalOrCustom(OtherOpcode, VT))
3765 return SDValue();
3766 }
3767
3768 SDValue Op0 = Node->getOperand(0);
3769 SDValue Op1 = Node->getOperand(1);
3770 SDValue combined;
3771 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
3772 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
3773 SDNode *User = *UI;
3774 if (User == Node || User->getOpcode() == ISD::DELETED_NODE ||
3775 User->use_empty())
3776 continue;
3777 // Convert the other matching node(s), too;
3778 // otherwise, the DIVREM may get target-legalized into something
3779 // target-specific that we won't be able to recognize.
3780 unsigned UserOpc = User->getOpcode();
3781 if ((UserOpc == Opcode || UserOpc == OtherOpcode || UserOpc == DivRemOpc) &&
3782 User->getOperand(0) == Op0 &&
3783 User->getOperand(1) == Op1) {
3784 if (!combined) {
3785 if (UserOpc == OtherOpcode) {
3786 SDVTList VTs = DAG.getVTList(VT, VT);
3787 combined = DAG.getNode(DivRemOpc, SDLoc(Node), VTs, Op0, Op1);
3788 } else if (UserOpc == DivRemOpc) {
3789 combined = SDValue(User, 0);
3790 } else {
3791 assert(UserOpc == Opcode)((UserOpc == Opcode) ? static_cast<void> (0) : __assert_fail
("UserOpc == Opcode", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 3791, __PRETTY_FUNCTION__))
;
3792 continue;
3793 }
3794 }
3795 if (UserOpc == ISD::SDIV || UserOpc == ISD::UDIV)
3796 CombineTo(User, combined);
3797 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3798 CombineTo(User, combined.getValue(1));
3799 }
3800 }
3801 return combined;
3802}
3803
3804static SDValue simplifyDivRem(SDNode *N, SelectionDAG &DAG) {
3805 SDValue N0 = N->getOperand(0);
3806 SDValue N1 = N->getOperand(1);
3807 EVT VT = N->getValueType(0);
3808 SDLoc DL(N);
3809
3810 unsigned Opc = N->getOpcode();
3811 bool IsDiv = (ISD::SDIV == Opc) || (ISD::UDIV == Opc);
3812 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3813
3814 // X / undef -> undef
3815 // X % undef -> undef
3816 // X / 0 -> undef
3817 // X % 0 -> undef
3818 // NOTE: This includes vectors where any divisor element is zero/undef.
3819 if (DAG.isUndef(Opc, {N0, N1}))
3820 return DAG.getUNDEF(VT);
3821
3822 // undef / X -> 0
3823 // undef % X -> 0
3824 if (N0.isUndef())
3825 return DAG.getConstant(0, DL, VT);
3826
3827 // 0 / X -> 0
3828 // 0 % X -> 0
3829 ConstantSDNode *N0C = isConstOrConstSplat(N0);
3830 if (N0C && N0C->isNullValue())
3831 return N0;
3832
3833 // X / X -> 1
3834 // X % X -> 0
3835 if (N0 == N1)
3836 return DAG.getConstant(IsDiv ? 1 : 0, DL, VT);
3837
3838 // X / 1 -> X
3839 // X % 1 -> 0
3840 // If this is a boolean op (single-bit element type), we can't have
3841 // division-by-zero or remainder-by-zero, so assume the divisor is 1.
3842 // TODO: Similarly, if we're zero-extending a boolean divisor, then assume
3843 // it's a 1.
3844 if ((N1C && N1C->isOne()) || (VT.getScalarType() == MVT::i1))
3845 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
3846
3847 return SDValue();
3848}
3849
3850SDValue DAGCombiner::visitSDIV(SDNode *N) {
3851 SDValue N0 = N->getOperand(0);
3852 SDValue N1 = N->getOperand(1);
3853 EVT VT = N->getValueType(0);
3854 EVT CCVT = getSetCCResultType(VT);
3855
3856 // fold vector ops
3857 if (VT.isVector())
3858 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3859 return FoldedVOp;
3860
3861 SDLoc DL(N);
3862
3863 // fold (sdiv c1, c2) -> c1/c2
3864 ConstantSDNode *N1C = isConstOrConstSplat(N1);
3865 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
3866 return C;
3867
3868 // fold (sdiv X, -1) -> 0-X
3869 if (N1C && N1C->isAllOnesValue())
3870 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
3871
3872 // fold (sdiv X, MIN_SIGNED) -> select(X == MIN_SIGNED, 1, 0)
3873 if (N1C && N1C->getAPIntValue().isMinSignedValue())
3874 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
3875 DAG.getConstant(1, DL, VT),
3876 DAG.getConstant(0, DL, VT));
3877
3878 if (SDValue V = simplifyDivRem(N, DAG))
3879 return V;
3880
3881 if (SDValue NewSel = foldBinOpIntoSelect(N))
3882 return NewSel;
3883
3884 // If we know the sign bits of both operands are zero, strength reduce to a
3885 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
3886 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
3887 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
3888
3889 if (SDValue V = visitSDIVLike(N0, N1, N)) {
3890 // If the corresponding remainder node exists, update its users with
3891 // (Dividend - (Quotient * Divisor).
3892 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
3893 { N0, N1 })) {
3894 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
3895 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
3896 AddToWorklist(Mul.getNode());
3897 AddToWorklist(Sub.getNode());
3898 CombineTo(RemNode, Sub);
3899 }
3900 return V;
3901 }
3902
3903 // sdiv, srem -> sdivrem
3904 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
3905 // true. Otherwise, we break the simplification logic in visitREM().
3906 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3907 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
3908 if (SDValue DivRem = useDivRem(N))
3909 return DivRem;
3910
3911 return SDValue();
3912}
3913
3914SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
3915 SDLoc DL(N);
3916 EVT VT = N->getValueType(0);
3917 EVT CCVT = getSetCCResultType(VT);
3918 unsigned BitWidth = VT.getScalarSizeInBits();
3919
3920 // Helper for determining whether a value is a power-2 constant scalar or a
3921 // vector of such elements.
3922 auto IsPowerOfTwo = [](ConstantSDNode *C) {
3923 if (C->isNullValue() || C->isOpaque())
3924 return false;
3925 if (C->getAPIntValue().isPowerOf2())
3926 return true;
3927 if ((-C->getAPIntValue()).isPowerOf2())
3928 return true;
3929 return false;
3930 };
3931
3932 // fold (sdiv X, pow2) -> simple ops after legalize
3933 // FIXME: We check for the exact bit here because the generic lowering gives
3934 // better results in that case. The target-specific lowering should learn how
3935 // to handle exact sdivs efficiently.
3936 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
3937 // Target-specific implementation of sdiv x, pow2.
3938 if (SDValue Res = BuildSDIVPow2(N))
3939 return Res;
3940
3941 // Create constants that are functions of the shift amount value.
3942 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
3943 SDValue Bits = DAG.getConstant(BitWidth, DL, ShiftAmtTy);
3944 SDValue C1 = DAG.getNode(ISD::CTTZ, DL, VT, N1);
3945 C1 = DAG.getZExtOrTrunc(C1, DL, ShiftAmtTy);
3946 SDValue Inexact = DAG.getNode(ISD::SUB, DL, ShiftAmtTy, Bits, C1);
3947 if (!isConstantOrConstantVector(Inexact))
3948 return SDValue();
3949
3950 // Splat the sign bit into the register
3951 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
3952 DAG.getConstant(BitWidth - 1, DL, ShiftAmtTy));
3953 AddToWorklist(Sign.getNode());
3954
3955 // Add (N0 < 0) ? abs2 - 1 : 0;
3956 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact);
3957 AddToWorklist(Srl.getNode());
3958 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
3959 AddToWorklist(Add.getNode());
3960 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
3961 AddToWorklist(Sra.getNode());
3962
3963 // Special case: (sdiv X, 1) -> X
3964 // Special Case: (sdiv X, -1) -> 0-X
3965 SDValue One = DAG.getConstant(1, DL, VT);
3966 SDValue AllOnes = DAG.getAllOnesConstant(DL, VT);
3967 SDValue IsOne = DAG.getSetCC(DL, CCVT, N1, One, ISD::SETEQ);
3968 SDValue IsAllOnes = DAG.getSetCC(DL, CCVT, N1, AllOnes, ISD::SETEQ);
3969 SDValue IsOneOrAllOnes = DAG.getNode(ISD::OR, DL, CCVT, IsOne, IsAllOnes);
3970 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
3971
3972 // If dividing by a positive value, we're done. Otherwise, the result must
3973 // be negated.
3974 SDValue Zero = DAG.getConstant(0, DL, VT);
3975 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, Zero, Sra);
3976
3977 // FIXME: Use SELECT_CC once we improve SELECT_CC constant-folding.
3978 SDValue IsNeg = DAG.getSetCC(DL, CCVT, N1, Zero, ISD::SETLT);
3979 SDValue Res = DAG.getSelect(DL, VT, IsNeg, Sub, Sra);
3980 return Res;
3981 }
3982
3983 // If integer divide is expensive and we satisfy the requirements, emit an
3984 // alternate sequence. Targets may check function attributes for size/speed
3985 // trade-offs.
3986 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
3987 if (isConstantOrConstantVector(N1) &&
3988 !TLI.isIntDivCheap(N->getValueType(0), Attr))
3989 if (SDValue Op = BuildSDIV(N))
3990 return Op;
3991
3992 return SDValue();
3993}
3994
3995SDValue DAGCombiner::visitUDIV(SDNode *N) {
3996 SDValue N0 = N->getOperand(0);
3997 SDValue N1 = N->getOperand(1);
3998 EVT VT = N->getValueType(0);
3999 EVT CCVT = getSetCCResultType(VT);
4000
4001 // fold vector ops
4002 if (VT.isVector())
4003 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4004 return FoldedVOp;
4005
4006 SDLoc DL(N);
4007
4008 // fold (udiv c1, c2) -> c1/c2
4009 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4010 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
4011 return C;
4012
4013 // fold (udiv X, -1) -> select(X == -1, 1, 0)
4014 if (N1C && N1C->getAPIntValue().isAllOnesValue())
4015 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4016 DAG.getConstant(1, DL, VT),
4017 DAG.getConstant(0, DL, VT));
4018
4019 if (SDValue V = simplifyDivRem(N, DAG))
4020 return V;
4021
4022 if (SDValue NewSel = foldBinOpIntoSelect(N))
4023 return NewSel;
4024
4025 if (SDValue V = visitUDIVLike(N0, N1, N)) {
4026 // If the corresponding remainder node exists, update its users with
4027 // (Dividend - (Quotient * Divisor).
4028 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
4029 { N0, N1 })) {
4030 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, V, N1);
4031 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4032 AddToWorklist(Mul.getNode());
4033 AddToWorklist(Sub.getNode());
4034 CombineTo(RemNode, Sub);
4035 }
4036 return V;
4037 }
4038
4039 // sdiv, srem -> sdivrem
4040 // If the divisor is constant, then return DIVREM only if isIntDivCheap() is
4041 // true. Otherwise, we break the simplification logic in visitREM().
4042 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4043 if (!N1C || TLI.isIntDivCheap(N->getValueType(0), Attr))
4044 if (SDValue DivRem = useDivRem(N))
4045 return DivRem;
4046
4047 return SDValue();
4048}
4049
4050SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4051 SDLoc DL(N);
4052 EVT VT = N->getValueType(0);
4053
4054 // fold (udiv x, (1 << c)) -> x >>u c
4055 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4056 DAG.isKnownToBeAPowerOfTwo(N1)) {
4057 SDValue LogBase2 = BuildLogBase2(N1, DL);
4058 AddToWorklist(LogBase2.getNode());
4059
4060 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4061 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ShiftVT);
4062 AddToWorklist(Trunc.getNode());
4063 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4064 }
4065
4066 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
4067 if (N1.getOpcode() == ISD::SHL) {
4068 SDValue N10 = N1.getOperand(0);
4069 if (isConstantOrConstantVector(N10, /*NoOpaques*/ true) &&
4070 DAG.isKnownToBeAPowerOfTwo(N10)) {
4071 SDValue LogBase2 = BuildLogBase2(N10, DL);
4072 AddToWorklist(LogBase2.getNode());
4073
4074 EVT ADDVT = N1.getOperand(1).getValueType();
4075 SDValue Trunc = DAG.getZExtOrTrunc(LogBase2, DL, ADDVT);
4076 AddToWorklist(Trunc.getNode());
4077 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT, N1.getOperand(1), Trunc);
4078 AddToWorklist(Add.getNode());
4079 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
4080 }
4081 }
4082
4083 // fold (udiv x, c) -> alternate
4084 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4085 if (isConstantOrConstantVector(N1) &&
4086 !TLI.isIntDivCheap(N->getValueType(0), Attr))
4087 if (SDValue Op = BuildUDIV(N))
4088 return Op;
4089
4090 return SDValue();
4091}
4092
4093// handles ISD::SREM and ISD::UREM
4094SDValue DAGCombiner::visitREM(SDNode *N) {
4095 unsigned Opcode = N->getOpcode();
4096 SDValue N0 = N->getOperand(0);
4097 SDValue N1 = N->getOperand(1);
4098 EVT VT = N->getValueType(0);
4099 EVT CCVT = getSetCCResultType(VT);
4100
4101 bool isSigned = (Opcode == ISD::SREM);
4102 SDLoc DL(N);
4103
4104 // fold (rem c1, c2) -> c1%c2
4105 ConstantSDNode *N1C = isConstOrConstSplat(N1);
4106 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4107 return C;
4108
4109 // fold (urem X, -1) -> select(X == -1, 0, x)
4110 if (!isSigned && N1C && N1C->getAPIntValue().isAllOnesValue())
4111 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4112 DAG.getConstant(0, DL, VT), N0);
4113
4114 if (SDValue V = simplifyDivRem(N, DAG))
4115 return V;
4116
4117 if (SDValue NewSel = foldBinOpIntoSelect(N))
4118 return NewSel;
4119
4120 if (isSigned) {
4121 // If we know the sign bits of both operands are zero, strength reduce to a
4122 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
4123 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4124 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
4125 } else {
4126 SDValue NegOne = DAG.getAllOnesConstant(DL, VT);
4127 if (DAG.isKnownToBeAPowerOfTwo(N1)) {
4128 // fold (urem x, pow2) -> (and x, pow2-1)
4129 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4130 AddToWorklist(Add.getNode());
4131 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4132 }
4133 if (N1.getOpcode() == ISD::SHL &&
4134 DAG.isKnownToBeAPowerOfTwo(N1.getOperand(0))) {
4135 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
4136 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N1, NegOne);
4137 AddToWorklist(Add.getNode());
4138 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
4139 }
4140 }
4141
4142 AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
4143
4144 // If X/C can be simplified by the division-by-constant logic, lower
4145 // X%C to the equivalent of X-X/C*C.
4146 // Reuse the SDIVLike/UDIVLike combines - to avoid mangling nodes, the
4147 // speculative DIV must not cause a DIVREM conversion. We guard against this
4148 // by skipping the simplification if isIntDivCheap(). When div is not cheap,
4149 // combine will not return a DIVREM. Regardless, checking cheapness here
4150 // makes sense since the simplification results in fatter code.
4151 if (DAG.isKnownNeverZero(N1) && !TLI.isIntDivCheap(VT, Attr)) {
4152 SDValue OptimizedDiv =
4153 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
4154 if (OptimizedDiv.getNode()) {
4155 // If the equivalent Div node also exists, update its users.
4156 unsigned DivOpcode = isSigned ? ISD::SDIV : ISD::UDIV;
4157 if (SDNode *DivNode = DAG.getNodeIfExists(DivOpcode, N->getVTList(),
4158 { N0, N1 }))
4159 CombineTo(DivNode, OptimizedDiv);
4160 SDValue Mul = DAG.getNode(ISD::MUL, DL, VT, OptimizedDiv, N1);
4161 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4162 AddToWorklist(OptimizedDiv.getNode());
4163 AddToWorklist(Mul.getNode());
4164 return Sub;
4165 }
4166 }
4167
4168 // sdiv, srem -> sdivrem
4169 if (SDValue DivRem = useDivRem(N))
4170 return DivRem.getValue(1);
4171
4172 return SDValue();
4173}
4174
4175SDValue DAGCombiner::visitMULHS(SDNode *N) {
4176 SDValue N0 = N->getOperand(0);
4177 SDValue N1 = N->getOperand(1);
4178 EVT VT = N->getValueType(0);
4179 SDLoc DL(N);
4180
4181 if (VT.isVector()) {
4182 // fold (mulhs x, 0) -> 0
4183 // do not return N0/N1, because undef node may exist.
4184 if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
4185 ISD::isBuildVectorAllZeros(N1.getNode()))
4186 return DAG.getConstant(0, DL, VT);
4187 }
4188
4189 // fold (mulhs x, 0) -> 0
4190 if (isNullConstant(N1))
4191 return N1;
4192 // fold (mulhs x, 1) -> (sra x, size(x)-1)
4193 if (isOneConstant(N1))
4194 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
4195 DAG.getConstant(N0.getScalarValueSizeInBits() - 1, DL,
4196 getShiftAmountTy(N0.getValueType())));
4197
4198 // fold (mulhs x, undef) -> 0
4199 if (N0.isUndef() || N1.isUndef())
4200 return DAG.getConstant(0, DL, VT);
4201
4202 // If the type twice as wide is legal, transform the mulhs to a wider multiply
4203 // plus a shift.
4204 if (!TLI.isMulhCheaperThanMulShift(VT) && VT.isSimple() && !VT.isVector()) {
4205 MVT Simple = VT.getSimpleVT();
4206 unsigned SimpleSize = Simple.getSizeInBits();
4207 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4208 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4209 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
4210 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
4211 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4212 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4213 DAG.getConstant(SimpleSize, DL,
4214 getShiftAmountTy(N1.getValueType())));
4215 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4216 }
4217 }
4218
4219 return SDValue();
4220}
4221
4222SDValue DAGCombiner::visitMULHU(SDNode *N) {
4223 SDValue N0 = N->getOperand(0);
4224 SDValue N1 = N->getOperand(1);
4225 EVT VT = N->getValueType(0);
4226 SDLoc DL(N);
4227
4228 if (VT.isVector()) {
4229 // fold (mulhu x, 0) -> 0
4230 // do not return N0/N1, because undef node may exist.
4231 if (ISD::isBuildVectorAllZeros(N0.getNode()) ||
4232 ISD::isBuildVectorAllZeros(N1.getNode()))
4233 return DAG.getConstant(0, DL, VT);
4234 }
4235
4236 // fold (mulhu x, 0) -> 0
4237 if (isNullConstant(N1))
4238 return N1;
4239 // fold (mulhu x, 1) -> 0
4240 if (isOneConstant(N1))
4241 return DAG.getConstant(0, DL, N0.getValueType());
4242 // fold (mulhu x, undef) -> 0
4243 if (N0.isUndef() || N1.isUndef())
4244 return DAG.getConstant(0, DL, VT);
4245
4246 // fold (mulhu x, (1 << c)) -> x >> (bitwidth - c)
4247 if (isConstantOrConstantVector(N1, /*NoOpaques*/ true) &&
4248 DAG.isKnownToBeAPowerOfTwo(N1) && hasOperation(ISD::SRL, VT)) {
4249 unsigned NumEltBits = VT.getScalarSizeInBits();
4250 SDValue LogBase2 = BuildLogBase2(N1, DL);
4251 SDValue SRLAmt = DAG.getNode(
4252 ISD::SUB, DL, VT, DAG.getConstant(NumEltBits, DL, VT), LogBase2);
4253 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4254 SDValue Trunc = DAG.getZExtOrTrunc(SRLAmt, DL, ShiftVT);
4255 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
4256 }
4257
4258 // If the type twice as wide is legal, transform the mulhu to a wider multiply
4259 // plus a shift.
4260 if (!TLI.isMulhCheaperThanMulShift(VT) && VT.isSimple() && !VT.isVector()) {
4261 MVT Simple = VT.getSimpleVT();
4262 unsigned SimpleSize = Simple.getSizeInBits();
4263 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4264 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4265 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
4266 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
4267 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
4268 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
4269 DAG.getConstant(SimpleSize, DL,
4270 getShiftAmountTy(N1.getValueType())));
4271 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
4272 }
4273 }
4274
4275 return SDValue();
4276}
4277
4278/// Perform optimizations common to nodes that compute two values. LoOp and HiOp
4279/// give the opcodes for the two computations that are being performed. Return
4280/// true if a simplification was made.
4281SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
4282 unsigned HiOp) {
4283 // If the high half is not needed, just compute the low half.
4284 bool HiExists = N->hasAnyUseOfValue(1);
4285 if (!HiExists && (!LegalOperations ||
4286 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
4287 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4288 return CombineTo(N, Res, Res);
4289 }
4290
4291 // If the low half is not needed, just compute the high half.
4292 bool LoExists = N->hasAnyUseOfValue(0);
4293 if (!LoExists && (!LegalOperations ||
4294 TLI.isOperationLegalOrCustom(HiOp, N->getValueType(1)))) {
4295 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4296 return CombineTo(N, Res, Res);
4297 }
4298
4299 // If both halves are used, return as it is.
4300 if (LoExists && HiExists)
4301 return SDValue();
4302
4303 // If the two computed results can be simplified separately, separate them.
4304 if (LoExists) {
4305 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
4306 AddToWorklist(Lo.getNode());
4307 SDValue LoOpt = combine(Lo.getNode());
4308 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
4309 (!LegalOperations ||
4310 TLI.isOperationLegalOrCustom(LoOpt.getOpcode(), LoOpt.getValueType())))
4311 return CombineTo(N, LoOpt, LoOpt);
4312 }
4313
4314 if (HiExists) {
4315 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
4316 AddToWorklist(Hi.getNode());
4317 SDValue HiOpt = combine(Hi.getNode());
4318 if (HiOpt.getNode() && HiOpt != Hi &&
4319 (!LegalOperations ||
4320 TLI.isOperationLegalOrCustom(HiOpt.getOpcode(), HiOpt.getValueType())))
4321 return CombineTo(N, HiOpt, HiOpt);
4322 }
4323
4324 return SDValue();
4325}
4326
4327SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
4328 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
4329 return Res;
4330
4331 EVT VT = N->getValueType(0);
4332 SDLoc DL(N);
4333
4334 // If the type is twice as wide is legal, transform the mulhu to a wider
4335 // multiply plus a shift.
4336 if (VT.isSimple() && !VT.isVector()) {
4337 MVT Simple = VT.getSimpleVT();
4338 unsigned SimpleSize = Simple.getSizeInBits();
4339 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4340 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4341 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
4342 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
4343 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4344 // Compute the high part as N1.
4345 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4346 DAG.getConstant(SimpleSize, DL,
4347 getShiftAmountTy(Lo.getValueType())));
4348 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4349 // Compute the low part as N0.
4350 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4351 return CombineTo(N, Lo, Hi);
4352 }
4353 }
4354
4355 return SDValue();
4356}
4357
4358SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
4359 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
4360 return Res;
4361
4362 EVT VT = N->getValueType(0);
4363 SDLoc DL(N);
4364
4365 // (umul_lohi N0, 0) -> (0, 0)
4366 if (isNullConstant(N->getOperand(1))) {
4367 SDValue Zero = DAG.getConstant(0, DL, VT);
4368 return CombineTo(N, Zero, Zero);
4369 }
4370
4371 // (umul_lohi N0, 1) -> (N0, 0)
4372 if (isOneConstant(N->getOperand(1))) {
4373 SDValue Zero = DAG.getConstant(0, DL, VT);
4374 return CombineTo(N, N->getOperand(0), Zero);
4375 }
4376
4377 // If the type is twice as wide is legal, transform the mulhu to a wider
4378 // multiply plus a shift.
4379 if (VT.isSimple() && !VT.isVector()) {
4380 MVT Simple = VT.getSimpleVT();
4381 unsigned SimpleSize = Simple.getSizeInBits();
4382 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
4383 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
4384 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
4385 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
4386 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
4387 // Compute the high part as N1.
4388 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
4389 DAG.getConstant(SimpleSize, DL,
4390 getShiftAmountTy(Lo.getValueType())));
4391 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
4392 // Compute the low part as N0.
4393 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
4394 return CombineTo(N, Lo, Hi);
4395 }
4396 }
4397
4398 return SDValue();
4399}
4400
4401SDValue DAGCombiner::visitMULO(SDNode *N) {
4402 SDValue N0 = N->getOperand(0);
4403 SDValue N1 = N->getOperand(1);
4404 EVT VT = N0.getValueType();
4405 bool IsSigned = (ISD::SMULO == N->getOpcode());
4406
4407 EVT CarryVT = N->getValueType(1);
4408 SDLoc DL(N);
4409
4410 // canonicalize constant to RHS.
4411 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4412 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4413 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
4414
4415 // fold (mulo x, 0) -> 0 + no carry out
4416 if (isNullOrNullSplat(N1))
4417 return CombineTo(N, DAG.getConstant(0, DL, VT),
4418 DAG.getConstant(0, DL, CarryVT));
4419
4420 // (mulo x, 2) -> (addo x, x)
4421 if (ConstantSDNode *C2 = isConstOrConstSplat(N1))
4422 if (C2->getAPIntValue() == 2)
4423 return DAG.getNode(IsSigned ? ISD::SADDO : ISD::UADDO, DL,
4424 N->getVTList(), N0, N0);
4425
4426 return SDValue();
4427}
4428
4429SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
4430 SDValue N0 = N->getOperand(0);
4431 SDValue N1 = N->getOperand(1);
4432 EVT VT = N0.getValueType();
4433 unsigned Opcode = N->getOpcode();
4434
4435 // fold vector ops
4436 if (VT.isVector())
4437 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4438 return FoldedVOp;
4439
4440 // fold operation with constant operands.
4441 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, SDLoc(N), VT, {N0, N1}))
4442 return C;
4443
4444 // canonicalize constant to RHS
4445 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4446 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
4447 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
4448
4449 // Is sign bits are zero, flip between UMIN/UMAX and SMIN/SMAX.
4450 // Only do this if the current op isn't legal and the flipped is.
4451 if (!TLI.isOperationLegal(Opcode, VT) &&
4452 (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
4453 (N1.isUndef() || DAG.SignBitIsZero(N1))) {
4454 unsigned AltOpcode;
4455 switch (Opcode) {
4456 case ISD::SMIN: AltOpcode = ISD::UMIN; break;
4457 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4458 case ISD::UMIN: AltOpcode = ISD::SMIN; break;
4459 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
4460 default: llvm_unreachable("Unknown MINMAX opcode")::llvm::llvm_unreachable_internal("Unknown MINMAX opcode", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4460)
;
4461 }
4462 if (TLI.isOperationLegal(AltOpcode, VT))
4463 return DAG.getNode(AltOpcode, SDLoc(N), VT, N0, N1);
4464 }
4465
4466 return SDValue();
4467}
4468
4469/// If this is a bitwise logic instruction and both operands have the same
4470/// opcode, try to sink the other opcode after the logic instruction.
4471SDValue DAGCombiner::hoistLogicOpWithSameOpcodeHands(SDNode *N) {
4472 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4473 EVT VT = N0.getValueType();
4474 unsigned LogicOpcode = N->getOpcode();
4475 unsigned HandOpcode = N0.getOpcode();
4476 assert((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR ||(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4477, __PRETTY_FUNCTION__))
4477 LogicOpcode == ISD::XOR) && "Expected logic opcode")(((LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode
== ISD::XOR) && "Expected logic opcode") ? static_cast
<void> (0) : __assert_fail ("(LogicOpcode == ISD::AND || LogicOpcode == ISD::OR || LogicOpcode == ISD::XOR) && \"Expected logic opcode\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4477, __PRETTY_FUNCTION__))
;
4478 assert(HandOpcode == N1.getOpcode() && "Bad input!")((HandOpcode == N1.getOpcode() && "Bad input!") ? static_cast
<void> (0) : __assert_fail ("HandOpcode == N1.getOpcode() && \"Bad input!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4478, __PRETTY_FUNCTION__))
;
4479
4480 // Bail early if none of these transforms apply.
4481 if (N0.getNumOperands() == 0)
4482 return SDValue();
4483
4484 // FIXME: We should check number of uses of the operands to not increase
4485 // the instruction count for all transforms.
4486
4487 // Handle size-changing casts.
4488 SDValue X = N0.getOperand(0);
4489 SDValue Y = N1.getOperand(0);
4490 EVT XVT = X.getValueType();
4491 SDLoc DL(N);
4492 if (HandOpcode == ISD::ANY_EXTEND || HandOpcode == ISD::ZERO_EXTEND ||
4493 HandOpcode == ISD::SIGN_EXTEND) {
4494 // If both operands have other uses, this transform would create extra
4495 // instructions without eliminating anything.
4496 if (!N0.hasOneUse() && !N1.hasOneUse())
4497 return SDValue();
4498 // We need matching integer source types.
4499 if (XVT != Y.getValueType())
4500 return SDValue();
4501 // Don't create an illegal op during or after legalization. Don't ever
4502 // create an unsupported vector op.
4503 if ((VT.isVector() || LegalOperations) &&
4504 !TLI.isOperationLegalOrCustom(LogicOpcode, XVT))
4505 return SDValue();
4506 // Avoid infinite looping with PromoteIntBinOp.
4507 // TODO: Should we apply desirable/legal constraints to all opcodes?
4508 if (HandOpcode == ISD::ANY_EXTEND && LegalTypes &&
4509 !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
4510 return SDValue();
4511 // logic_op (hand_op X), (hand_op Y) --> hand_op (logic_op X, Y)
4512 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4513 return DAG.getNode(HandOpcode, DL, VT, Logic);
4514 }
4515
4516 // logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)
4517 if (HandOpcode == ISD::TRUNCATE) {
4518 // If both operands have other uses, this transform would create extra
4519 // instructions without eliminating anything.
4520 if (!N0.hasOneUse() && !N1.hasOneUse())
4521 return SDValue();
4522 // We need matching source types.
4523 if (XVT != Y.getValueType())
4524 return SDValue();
4525 // Don't create an illegal op during or after legalization.
4526 if (LegalOperations && !TLI.isOperationLegal(LogicOpcode, XVT))
4527 return SDValue();
4528 // Be extra careful sinking truncate. If it's free, there's no benefit in
4529 // widening a binop. Also, don't create a logic op on an illegal type.
4530 if (TLI.isZExtFree(VT, XVT) && TLI.isTruncateFree(XVT, VT))
4531 return SDValue();
4532 if (!TLI.isTypeLegal(XVT))
4533 return SDValue();
4534 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4535 return DAG.getNode(HandOpcode, DL, VT, Logic);
4536 }
4537
4538 // For binops SHL/SRL/SRA/AND:
4539 // logic_op (OP x, z), (OP y, z) --> OP (logic_op x, y), z
4540 if ((HandOpcode == ISD::SHL || HandOpcode == ISD::SRL ||
4541 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
4542 N0.getOperand(1) == N1.getOperand(1)) {
4543 // If either operand has other uses, this transform is not an improvement.
4544 if (!N0.hasOneUse() || !N1.hasOneUse())
4545 return SDValue();
4546 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4547 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
4548 }
4549
4550 // Unary ops: logic_op (bswap x), (bswap y) --> bswap (logic_op x, y)
4551 if (HandOpcode == ISD::BSWAP) {
4552 // If either operand has other uses, this transform is not an improvement.
4553 if (!N0.hasOneUse() || !N1.hasOneUse())
4554 return SDValue();
4555 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4556 return DAG.getNode(HandOpcode, DL, VT, Logic);
4557 }
4558
4559 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
4560 // Only perform this optimization up until type legalization, before
4561 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
4562 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
4563 // we don't want to undo this promotion.
4564 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
4565 // on scalars.
4566 if ((HandOpcode == ISD::BITCAST || HandOpcode == ISD::SCALAR_TO_VECTOR) &&
4567 Level <= AfterLegalizeTypes) {
4568 // Input types must be integer and the same.
4569 if (XVT.isInteger() && XVT == Y.getValueType() &&
4570 !(VT.isVector() && TLI.isTypeLegal(VT) &&
4571 !XVT.isVector() && !TLI.isTypeLegal(XVT))) {
4572 SDValue Logic = DAG.getNode(LogicOpcode, DL, XVT, X, Y);
4573 return DAG.getNode(HandOpcode, DL, VT, Logic);
4574 }
4575 }
4576
4577 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
4578 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
4579 // If both shuffles use the same mask, and both shuffle within a single
4580 // vector, then it is worthwhile to move the swizzle after the operation.
4581 // The type-legalizer generates this pattern when loading illegal
4582 // vector types from memory. In many cases this allows additional shuffle
4583 // optimizations.
4584 // There are other cases where moving the shuffle after the xor/and/or
4585 // is profitable even if shuffles don't perform a swizzle.
4586 // If both shuffles use the same mask, and both shuffles have the same first
4587 // or second operand, then it might still be profitable to move the shuffle
4588 // after the xor/and/or operation.
4589 if (HandOpcode == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
4590 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
4591 auto *SVN1 = cast<ShuffleVectorSDNode>(N1);
4592 assert(X.getValueType() == Y.getValueType() &&((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4593, __PRETTY_FUNCTION__))
4593 "Inputs to shuffles are not the same type")((X.getValueType() == Y.getValueType() && "Inputs to shuffles are not the same type"
) ? static_cast<void> (0) : __assert_fail ("X.getValueType() == Y.getValueType() && \"Inputs to shuffles are not the same type\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4593, __PRETTY_FUNCTION__))
;
4594
4595 // Check that both shuffles use the same mask. The masks are known to be of
4596 // the same length because the result vector type is the same.
4597 // Check also that shuffles have only one use to avoid introducing extra
4598 // instructions.
4599 if (!SVN0->hasOneUse() || !SVN1->hasOneUse() ||
4600 !SVN0->getMask().equals(SVN1->getMask()))
4601 return SDValue();
4602
4603 // Don't try to fold this node if it requires introducing a
4604 // build vector of all zeros that might be illegal at this stage.
4605 SDValue ShOp = N0.getOperand(1);
4606 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4607 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4608
4609 // (logic_op (shuf (A, C), shuf (B, C))) --> shuf (logic_op (A, B), C)
4610 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
4611 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT,
4612 N0.getOperand(0), N1.getOperand(0));
4613 return DAG.getVectorShuffle(VT, DL, Logic, ShOp, SVN0->getMask());
4614 }
4615
4616 // Don't try to fold this node if it requires introducing a
4617 // build vector of all zeros that might be illegal at this stage.
4618 ShOp = N0.getOperand(0);
4619 if (LogicOpcode == ISD::XOR && !ShOp.isUndef())
4620 ShOp = tryFoldToZero(DL, TLI, VT, DAG, LegalOperations);
4621
4622 // (logic_op (shuf (C, A), shuf (C, B))) --> shuf (C, logic_op (A, B))
4623 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
4624 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
4625 N1.getOperand(1));
4626 return DAG.getVectorShuffle(VT, DL, ShOp, Logic, SVN0->getMask());
4627 }
4628 }
4629
4630 return SDValue();
4631}
4632
4633/// Try to make (and/or setcc (LL, LR), setcc (RL, RR)) more efficient.
4634SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
4635 const SDLoc &DL) {
4636 SDValue LL, LR, RL, RR, N0CC, N1CC;
4637 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
4638 !isSetCCEquivalent(N1, RL, RR, N1CC))
4639 return SDValue();
4640
4641 assert(N0.getValueType() == N1.getValueType() &&((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4642, __PRETTY_FUNCTION__))
4642 "Unexpected operand types for bitwise logic op")((N0.getValueType() == N1.getValueType() && "Unexpected operand types for bitwise logic op"
) ? static_cast<void> (0) : __assert_fail ("N0.getValueType() == N1.getValueType() && \"Unexpected operand types for bitwise logic op\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4642, __PRETTY_FUNCTION__))
;
4643 assert(LL.getValueType() == LR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4645, __PRETTY_FUNCTION__))
4644 RL.getValueType() == RR.getValueType() &&((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4645, __PRETTY_FUNCTION__))
4645 "Unexpected operand types for setcc")((LL.getValueType() == LR.getValueType() && RL.getValueType
() == RR.getValueType() && "Unexpected operand types for setcc"
) ? static_cast<void> (0) : __assert_fail ("LL.getValueType() == LR.getValueType() && RL.getValueType() == RR.getValueType() && \"Unexpected operand types for setcc\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4645, __PRETTY_FUNCTION__))
;
4646
4647 // If we're here post-legalization or the logic op type is not i1, the logic
4648 // op type must match a setcc result type. Also, all folds require new
4649 // operations on the left and right operands, so those types must match.
4650 EVT VT = N0.getValueType();
4651 EVT OpVT = LL.getValueType();
4652 if (LegalOperations || VT.getScalarType() != MVT::i1)
4653 if (VT != getSetCCResultType(OpVT))
4654 return SDValue();
4655 if (OpVT != RL.getValueType())
4656 return SDValue();
4657
4658 ISD::CondCode CC0 = cast<CondCodeSDNode>(N0CC)->get();
4659 ISD::CondCode CC1 = cast<CondCodeSDNode>(N1CC)->get();
4660 bool IsInteger = OpVT.isInteger();
4661 if (LR == RR && CC0 == CC1 && IsInteger) {
4662 bool IsZero = isNullOrNullSplat(LR);
4663 bool IsNeg1 = isAllOnesOrAllOnesSplat(LR);
4664
4665 // All bits clear?
4666 bool AndEqZero = IsAnd && CC1 == ISD::SETEQ && IsZero;
4667 // All sign bits clear?
4668 bool AndGtNeg1 = IsAnd && CC1 == ISD::SETGT && IsNeg1;
4669 // Any bits set?
4670 bool OrNeZero = !IsAnd && CC1 == ISD::SETNE && IsZero;
4671 // Any sign bits set?
4672 bool OrLtZero = !IsAnd && CC1 == ISD::SETLT && IsZero;
4673
4674 // (and (seteq X, 0), (seteq Y, 0)) --> (seteq (or X, Y), 0)
4675 // (and (setgt X, -1), (setgt Y, -1)) --> (setgt (or X, Y), -1)
4676 // (or (setne X, 0), (setne Y, 0)) --> (setne (or X, Y), 0)
4677 // (or (setlt X, 0), (setlt Y, 0)) --> (setlt (or X, Y), 0)
4678 if (AndEqZero || AndGtNeg1 || OrNeZero || OrLtZero) {
4679 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
4680 AddToWorklist(Or.getNode());
4681 return DAG.getSetCC(DL, VT, Or, LR, CC1);
4682 }
4683
4684 // All bits set?
4685 bool AndEqNeg1 = IsAnd && CC1 == ISD::SETEQ && IsNeg1;
4686 // All sign bits set?
4687 bool AndLtZero = IsAnd && CC1 == ISD::SETLT && IsZero;
4688 // Any bits clear?
4689 bool OrNeNeg1 = !IsAnd && CC1 == ISD::SETNE && IsNeg1;
4690 // Any sign bits clear?
4691 bool OrGtNeg1 = !IsAnd && CC1 == ISD::SETGT && IsNeg1;
4692
4693 // (and (seteq X, -1), (seteq Y, -1)) --> (seteq (and X, Y), -1)
4694 // (and (setlt X, 0), (setlt Y, 0)) --> (setlt (and X, Y), 0)
4695 // (or (setne X, -1), (setne Y, -1)) --> (setne (and X, Y), -1)
4696 // (or (setgt X, -1), (setgt Y -1)) --> (setgt (and X, Y), -1)
4697 if (AndEqNeg1 || AndLtZero || OrNeNeg1 || OrGtNeg1) {
4698 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
4699 AddToWorklist(And.getNode());
4700 return DAG.getSetCC(DL, VT, And, LR, CC1);
4701 }
4702 }
4703
4704 // TODO: What is the 'or' equivalent of this fold?
4705 // (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2)
4706 if (IsAnd && LL == RL && CC0 == CC1 && OpVT.getScalarSizeInBits() > 1 &&
4707 IsInteger && CC0 == ISD::SETNE &&
4708 ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
4709 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
4710 SDValue One = DAG.getConstant(1, DL, OpVT);
4711 SDValue Two = DAG.getConstant(2, DL, OpVT);
4712 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
4713 AddToWorklist(Add.getNode());
4714 return DAG.getSetCC(DL, VT, Add, Two, ISD::SETUGE);
4715 }
4716
4717 // Try more general transforms if the predicates match and the only user of
4718 // the compares is the 'and' or 'or'.
4719 if (IsInteger && TLI.convertSetCCLogicToBitwiseLogic(OpVT) && CC0 == CC1 &&
4720 N0.hasOneUse() && N1.hasOneUse()) {
4721 // and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
4722 // or (setne A, B), (setne C, D) --> setne (or (xor A, B), (xor C, D)), 0
4723 if ((IsAnd && CC1 == ISD::SETEQ) || (!IsAnd && CC1 == ISD::SETNE)) {
4724 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
4725 SDValue XorR = DAG.getNode(ISD::XOR, SDLoc(N1), OpVT, RL, RR);
4726 SDValue Or = DAG.getNode(ISD::OR, DL, OpVT, XorL, XorR);
4727 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4728 return DAG.getSetCC(DL, VT, Or, Zero, CC1);
4729 }
4730
4731 // Turn compare of constants whose difference is 1 bit into add+and+setcc.
4732 // TODO - support non-uniform vector amounts.
4733 if ((IsAnd && CC1 == ISD::SETNE) || (!IsAnd && CC1 == ISD::SETEQ)) {
4734 // Match a shared variable operand and 2 non-opaque constant operands.
4735 ConstantSDNode *C0 = isConstOrConstSplat(LR);
4736 ConstantSDNode *C1 = isConstOrConstSplat(RR);
4737 if (LL == RL && C0 && C1 && !C0->isOpaque() && !C1->isOpaque()) {
4738 // Canonicalize larger constant as C0.
4739 if (C1->getAPIntValue().ugt(C0->getAPIntValue()))
4740 std::swap(C0, C1);
4741
4742 // The difference of the constants must be a single bit.
4743 const APInt &C0Val = C0->getAPIntValue();
4744 const APInt &C1Val = C1->getAPIntValue();
4745 if ((C0Val - C1Val).isPowerOf2()) {
4746 // and/or (setcc X, C0, ne), (setcc X, C1, ne/eq) -->
4747 // setcc ((add X, -C1), ~(C0 - C1)), 0, ne/eq
4748 SDValue OffsetC = DAG.getConstant(-C1Val, DL, OpVT);
4749 SDValue Add = DAG.getNode(ISD::ADD, DL, OpVT, LL, OffsetC);
4750 SDValue MaskC = DAG.getConstant(~(C0Val - C1Val), DL, OpVT);
4751 SDValue And = DAG.getNode(ISD::AND, DL, OpVT, Add, MaskC);
4752 SDValue Zero = DAG.getConstant(0, DL, OpVT);
4753 return DAG.getSetCC(DL, VT, And, Zero, CC0);
4754 }
4755 }
4756 }
4757 }
4758
4759 // Canonicalize equivalent operands to LL == RL.
4760 if (LL == RR && LR == RL) {
4761 CC1 = ISD::getSetCCSwappedOperands(CC1);
4762 std::swap(RL, RR);
4763 }
4764
4765 // (and (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4766 // (or (setcc X, Y, CC0), (setcc X, Y, CC1)) --> (setcc X, Y, NewCC)
4767 if (LL == RL && LR == RR) {
4768 ISD::CondCode NewCC = IsAnd ? ISD::getSetCCAndOperation(CC0, CC1, OpVT)
4769 : ISD::getSetCCOrOperation(CC0, CC1, OpVT);
4770 if (NewCC != ISD::SETCC_INVALID &&
4771 (!LegalOperations ||
4772 (TLI.isCondCodeLegal(NewCC, LL.getSimpleValueType()) &&
4773 TLI.isOperationLegal(ISD::SETCC, OpVT))))
4774 return DAG.getSetCC(DL, VT, LL, LR, NewCC);
4775 }
4776
4777 return SDValue();
4778}
4779
4780/// This contains all DAGCombine rules which reduce two values combined by
4781/// an And operation to a single value. This makes them reusable in the context
4782/// of visitSELECT(). Rules involving constants are not included as
4783/// visitSELECT() already handles those cases.
4784SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
4785 EVT VT = N1.getValueType();
4786 SDLoc DL(N);
4787
4788 // fold (and x, undef) -> 0
4789 if (N0.isUndef() || N1.isUndef())
4790 return DAG.getConstant(0, DL, VT);
4791
4792 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
4793 return V;
4794
4795 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
4796 VT.getSizeInBits() <= 64) {
4797 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4798 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
4799 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
4800 // immediate for an add, but it is legal if its top c2 bits are set,
4801 // transform the ADD so the immediate doesn't need to be materialized
4802 // in a register.
4803 APInt ADDC = ADDI->getAPIntValue();
4804 APInt SRLC = SRLI->getAPIntValue();
4805 if (ADDC.getMinSignedBits() <= 64 &&
4806 SRLC.ult(VT.getSizeInBits()) &&
4807 !TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4808 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
4809 SRLC.getZExtValue());
4810 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
4811 ADDC |= Mask;
4812 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
4813 SDLoc DL0(N0);
4814 SDValue NewAdd =
4815 DAG.getNode(ISD::ADD, DL0, VT,
4816 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
4817 CombineTo(N0.getNode(), NewAdd);
4818 // Return N so it doesn't get rechecked!
4819 return SDValue(N, 0);
4820 }
4821 }
4822 }
4823 }
4824 }
4825 }
4826
4827 // Reduce bit extract of low half of an integer to the narrower type.
4828 // (and (srl i64:x, K), KMask) ->
4829 // (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
4830 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4831 if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
4832 if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4833 unsigned Size = VT.getSizeInBits();
4834 const APInt &AndMask = CAnd->getAPIntValue();
4835 unsigned ShiftBits = CShift->getZExtValue();
4836
4837 // Bail out, this node will probably disappear anyway.
4838 if (ShiftBits == 0)
4839 return SDValue();
4840
4841 unsigned MaskBits = AndMask.countTrailingOnes();
4842 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), Size / 2);
4843
4844 if (AndMask.isMask() &&
4845 // Required bits must not span the two halves of the integer and
4846 // must fit in the half size type.
4847 (ShiftBits + MaskBits <= Size / 2) &&
4848 TLI.isNarrowingProfitable(VT, HalfVT) &&
4849 TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
4850 TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
4851 TLI.isTruncateFree(VT, HalfVT) &&
4852 TLI.isZExtFree(HalfVT, VT)) {
4853 // The isNarrowingProfitable is to avoid regressions on PPC and
4854 // AArch64 which match a few 64-bit bit insert / bit extract patterns
4855 // on downstream users of this. Those patterns could probably be
4856 // extended to handle extensions mixed in.
4857
4858 SDValue SL(N0);
4859 assert(MaskBits <= Size)((MaskBits <= Size) ? static_cast<void> (0) : __assert_fail
("MaskBits <= Size", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4859, __PRETTY_FUNCTION__))
;
4860
4861 // Extracting the highest bit of the low half.
4862 EVT ShiftVT = TLI.getShiftAmountTy(HalfVT, DAG.getDataLayout());
4863 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, HalfVT,
4864 N0.getOperand(0));
4865
4866 SDValue NewMask = DAG.getConstant(AndMask.trunc(Size / 2), SL, HalfVT);
4867 SDValue ShiftK = DAG.getConstant(ShiftBits, SL, ShiftVT);
4868 SDValue Shift = DAG.getNode(ISD::SRL, SL, HalfVT, Trunc, ShiftK);
4869 SDValue And = DAG.getNode(ISD::AND, SL, HalfVT, Shift, NewMask);
4870 return DAG.getNode(ISD::ZERO_EXTEND, SL, VT, And);
4871 }
4872 }
4873 }
4874 }
4875
4876 return SDValue();
4877}
4878
4879bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
4880 EVT LoadResultTy, EVT &ExtVT) {
4881 if (!AndC->getAPIntValue().isMask())
4882 return false;
4883
4884 unsigned ActiveBits = AndC->getAPIntValue().countTrailingOnes();
4885
4886 ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
4887 EVT LoadedVT = LoadN->getMemoryVT();
4888
4889 if (ExtVT == LoadedVT &&
4890 (!LegalOperations ||
4891 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
4892 // ZEXTLOAD will match without needing to change the size of the value being
4893 // loaded.
4894 return true;
4895 }
4896
4897 // Do not change the width of a volatile or atomic loads.
4898 if (!LoadN->isSimple())
4899 return false;
4900
4901 // Do not generate loads of non-round integer types since these can
4902 // be expensive (and would be wrong if the type is not byte sized).
4903 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound())
4904 return false;
4905
4906 if (LegalOperations &&
4907 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
4908 return false;
4909
4910 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
4911 return false;
4912
4913 return true;
4914}
4915
4916bool DAGCombiner::isLegalNarrowLdSt(LSBaseSDNode *LDST,
4917 ISD::LoadExtType ExtType, EVT &MemVT,
4918 unsigned ShAmt) {
4919 if (!LDST)
4920 return false;
4921 // Only allow byte offsets.
4922 if (ShAmt % 8)
4923 return false;
4924
4925 // Do not generate loads of non-round integer types since these can
4926 // be expensive (and would be wrong if the type is not byte sized).
4927 if (!MemVT.isRound())
4928 return false;
4929
4930 // Don't change the width of a volatile or atomic loads.
4931 if (!LDST->isSimple())
4932 return false;
4933
4934 // Verify that we are actually reducing a load width here.
4935 if (LDST->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits())
4936 return false;
4937
4938 // Ensure that this isn't going to produce an unsupported memory access.
4939 if (ShAmt) {
4940 assert(ShAmt % 8 == 0 && "ShAmt is byte offset")((ShAmt % 8 == 0 && "ShAmt is byte offset") ? static_cast
<void> (0) : __assert_fail ("ShAmt % 8 == 0 && \"ShAmt is byte offset\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4940, __PRETTY_FUNCTION__))
;
4941 const unsigned ByteShAmt = ShAmt / 8;
4942 const Align LDSTAlign = LDST->getAlign();
4943 const Align NarrowAlign = commonAlignment(LDSTAlign, ByteShAmt);
4944 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
4945 LDST->getAddressSpace(), NarrowAlign,
4946 LDST->getMemOperand()->getFlags()))
4947 return false;
4948 }
4949
4950 // It's not possible to generate a constant of extended or untyped type.
4951 EVT PtrType = LDST->getBasePtr().getValueType();
4952 if (PtrType == MVT::Untyped || PtrType.isExtended())
4953 return false;
4954
4955 if (isa<LoadSDNode>(LDST)) {
4956 LoadSDNode *Load = cast<LoadSDNode>(LDST);
4957 // Don't transform one with multiple uses, this would require adding a new
4958 // load.
4959 if (!SDValue(Load, 0).hasOneUse())
4960 return false;
4961
4962 if (LegalOperations &&
4963 !TLI.isLoadExtLegal(ExtType, Load->getValueType(0), MemVT))
4964 return false;
4965
4966 // For the transform to be legal, the load must produce only two values
4967 // (the value loaded and the chain). Don't transform a pre-increment
4968 // load, for example, which produces an extra value. Otherwise the
4969 // transformation is not equivalent, and the downstream logic to replace
4970 // uses gets things wrong.
4971 if (Load->getNumValues() > 2)
4972 return false;
4973
4974 // If the load that we're shrinking is an extload and we're not just
4975 // discarding the extension we can't simply shrink the load. Bail.
4976 // TODO: It would be possible to merge the extensions in some cases.
4977 if (Load->getExtensionType() != ISD::NON_EXTLOAD &&
4978 Load->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4979 return false;
4980
4981 if (!TLI.shouldReduceLoadWidth(Load, ExtType, MemVT))
4982 return false;
4983 } else {
4984 assert(isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode")((isa<StoreSDNode>(LDST) && "It is not a Load nor a Store SDNode"
) ? static_cast<void> (0) : __assert_fail ("isa<StoreSDNode>(LDST) && \"It is not a Load nor a Store SDNode\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 4984, __PRETTY_FUNCTION__))
;
4985 StoreSDNode *Store = cast<StoreSDNode>(LDST);
4986 // Can't write outside the original store
4987 if (Store->getMemoryVT().getSizeInBits() < MemVT.getSizeInBits() + ShAmt)
4988 return false;
4989
4990 if (LegalOperations &&
4991 !TLI.isTruncStoreLegal(Store->getValue().getValueType(), MemVT))
4992 return false;
4993 }
4994 return true;
4995}
4996
4997bool DAGCombiner::SearchForAndLoads(SDNode *N,
4998 SmallVectorImpl<LoadSDNode*> &Loads,
4999 SmallPtrSetImpl<SDNode*> &NodesWithConsts,
5000 ConstantSDNode *Mask,
5001 SDNode *&NodeToMask) {
5002 // Recursively search for the operands, looking for loads which can be
5003 // narrowed.
5004 for (SDValue Op : N->op_values()) {
5005 if (Op.getValueType().isVector())
5006 return false;
5007
5008 // Some constants may need fixing up later if they are too large.
5009 if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
5010 if ((N->getOpcode() == ISD::OR || N->getOpcode() == ISD::XOR) &&
5011 (Mask->getAPIntValue() & C->getAPIntValue()) != C->getAPIntValue())
5012 NodesWithConsts.insert(N);
5013 continue;
5014 }
5015
5016 if (!Op.hasOneUse())
5017 return false;
5018
5019 switch(Op.getOpcode()) {
5020 case ISD::LOAD: {
5021 auto *Load = cast<LoadSDNode>(Op);
5022 EVT ExtVT;
5023 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
5024 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
5025
5026 // ZEXTLOAD is already small enough.
5027 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
5028 ExtVT.bitsGE(Load->getMemoryVT()))
5029 continue;
5030
5031 // Use LE to convert equal sized loads to zext.
5032 if (ExtVT.bitsLE(Load->getMemoryVT()))
5033 Loads.push_back(Load);
5034
5035 continue;
5036 }
5037 return false;
5038 }
5039 case ISD::ZERO_EXTEND:
5040 case ISD::AssertZext: {
5041 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
5042 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
5043 EVT VT = Op.getOpcode() == ISD::AssertZext ?
5044 cast<VTSDNode>(Op.getOperand(1))->getVT() :
5045 Op.getOperand(0).getValueType();
5046
5047 // We can accept extending nodes if the mask is wider or an equal
5048 // width to the original type.
5049 if (ExtVT.bitsGE(VT))
5050 continue;
5051 break;
5052 }
5053 case ISD::OR:
5054 case ISD::XOR:
5055 case ISD::AND:
5056 if (!SearchForAndLoads(Op.getNode(), Loads, NodesWithConsts, Mask,
5057 NodeToMask))
5058 return false;
5059 continue;
5060 }
5061
5062 // Allow one node which will masked along with any loads found.
5063 if (NodeToMask)
5064 return false;
5065
5066 // Also ensure that the node to be masked only produces one data result.
5067 NodeToMask = Op.getNode();
5068 if (NodeToMask->getNumValues() > 1) {
5069 bool HasValue = false;
5070 for (unsigned i = 0, e = NodeToMask->getNumValues(); i < e; ++i) {
5071 MVT VT = SDValue(NodeToMask, i).getSimpleValueType();
5072 if (VT != MVT::Glue && VT != MVT::Other) {
5073 if (HasValue) {
5074 NodeToMask = nullptr;
5075 return false;
5076 }
5077 HasValue = true;
5078 }
5079 }
5080 assert(HasValue && "Node to be masked has no data result?")((HasValue && "Node to be masked has no data result?"
) ? static_cast<void> (0) : __assert_fail ("HasValue && \"Node to be masked has no data result?\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5080, __PRETTY_FUNCTION__))
;
5081 }
5082 }
5083 return true;
5084}
5085
5086bool DAGCombiner::BackwardsPropagateMask(SDNode *N) {
5087 auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
5088 if (!Mask)
5089 return false;
5090
5091 if (!Mask->getAPIntValue().isMask())
5092 return false;
5093
5094 // No need to do anything if the and directly uses a load.
5095 if (isa<LoadSDNode>(N->getOperand(0)))
5096 return false;
5097
5098 SmallVector<LoadSDNode*, 8> Loads;
5099 SmallPtrSet<SDNode*, 2> NodesWithConsts;
5100 SDNode *FixupNode = nullptr;
5101 if (SearchForAndLoads(N, Loads, NodesWithConsts, Mask, FixupNode)) {
5102 if (Loads.size() == 0)
5103 return false;
5104
5105 LLVM_DEBUG(dbgs() << "Backwards propagate AND: "; N->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Backwards propagate AND: "
; N->dump(); } } while (false)
;
5106 SDValue MaskOp = N->getOperand(1);
5107
5108 // If it exists, fixup the single node we allow in the tree that needs
5109 // masking.
5110 if (FixupNode) {
5111 LLVM_DEBUG(dbgs() << "First, need to fix up: "; FixupNode->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "First, need to fix up: "; FixupNode
->dump(); } } while (false)
;
5112 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
5113 FixupNode->getValueType(0),
5114 SDValue(FixupNode, 0), MaskOp);
5115 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
5116 if (And.getOpcode() == ISD ::AND)
5117 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0), MaskOp);
5118 }
5119
5120 // Narrow any constants that need it.
5121 for (auto *LogicN : NodesWithConsts) {
5122 SDValue Op0 = LogicN->getOperand(0);
5123 SDValue Op1 = LogicN->getOperand(1);
5124
5125 if (isa<ConstantSDNode>(Op0))
5126 std::swap(Op0, Op1);
5127
5128 SDValue And = DAG.getNode(ISD::AND, SDLoc(Op1), Op1.getValueType(),
5129 Op1, MaskOp);
5130
5131 DAG.UpdateNodeOperands(LogicN, Op0, And);
5132 }
5133
5134 // Create narrow loads.
5135 for (auto *Load : Loads) {
5136 LLVM_DEBUG(dbgs() << "Propagate AND back to: "; Load->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("dagcombine")) { dbgs() << "Propagate AND back to: "; Load
->dump(); } } while (false)
;
5137 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
5138 SDValue(Load, 0), MaskOp);
5139 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
5140 if (And.getOpcode() == ISD ::AND)
5141 And = SDValue(
5142 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp), 0);
5143 SDValue NewLoad = ReduceLoadWidth(And.getNode());
5144 assert(NewLoad &&((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5145, __PRETTY_FUNCTION__))
5145 "Shouldn't be masking the load if it can't be narrowed")((NewLoad && "Shouldn't be masking the load if it can't be narrowed"
) ? static_cast<void> (0) : __assert_fail ("NewLoad && \"Shouldn't be masking the load if it can't be narrowed\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5145, __PRETTY_FUNCTION__))
;
5146 CombineTo(Load, NewLoad, NewLoad.getValue(1));
5147 }
5148 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
5149 return true;
5150 }
5151 return false;
5152}
5153
5154// Unfold
5155// x & (-1 'logical shift' y)
5156// To
5157// (x 'opposite logical shift' y) 'logical shift' y
5158// if it is better for performance.
5159SDValue DAGCombiner::unfoldExtremeBitClearingToShifts(SDNode *N) {
5160 assert(N->getOpcode() == ISD::AND)((N->getOpcode() == ISD::AND) ? static_cast<void> (0
) : __assert_fail ("N->getOpcode() == ISD::AND", "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5160, __PRETTY_FUNCTION__))
;
5161
5162 SDValue N0 = N->getOperand(0);
5163 SDValue N1 = N->getOperand(1);
5164
5165 // Do we actually prefer shifts over mask?
5166 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
5167 return SDValue();
5168
5169 // Try to match (-1 '[outer] logical shift' y)
5170 unsigned OuterShift;
5171 unsigned InnerShift; // The opposite direction to the OuterShift.
5172 SDValue Y; // Shift amount.
5173 auto matchMask = [&OuterShift, &InnerShift, &Y](SDValue M) -> bool {
5174 if (!M.hasOneUse())
5175 return false;
5176 OuterShift = M->getOpcode();
5177 if (OuterShift == ISD::SHL)
5178 InnerShift = ISD::SRL;
5179 else if (OuterShift == ISD::SRL)
5180 InnerShift = ISD::SHL;
5181 else
5182 return false;
5183 if (!isAllOnesConstant(M->getOperand(0)))
5184 return false;
5185 Y = M->getOperand(1);
5186 return true;
5187 };
5188
5189 SDValue X;
5190 if (matchMask(N1))
5191 X = N0;
5192 else if (matchMask(N0))
5193 X = N1;
5194 else
5195 return SDValue();
5196
5197 SDLoc DL(N);
5198 EVT VT = N->getValueType(0);
5199
5200 // tmp = x 'opposite logical shift' y
5201 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
5202 // ret = tmp 'logical shift' y
5203 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
5204
5205 return T1;
5206}
5207
5208/// Try to replace shift/logic that tests if a bit is clear with mask + setcc.
5209/// For a target with a bit test, this is expected to become test + set and save
5210/// at least 1 instruction.
5211static SDValue combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) {
5212 assert(And->getOpcode() == ISD::AND && "Expected an 'and' op")((And->getOpcode() == ISD::AND && "Expected an 'and' op"
) ? static_cast<void> (0) : __assert_fail ("And->getOpcode() == ISD::AND && \"Expected an 'and' op\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5212, __PRETTY_FUNCTION__))
;
5213
5214 // This is probably not worthwhile without a supported type.
5215 EVT VT = And->getValueType(0);
5216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5217 if (!TLI.isTypeLegal(VT))
5218 return SDValue();
5219
5220 // Look through an optional extension and find a 'not'.
5221 // TODO: Should we favor test+set even without the 'not' op?
5222 SDValue Not = And->getOperand(0), And1 = And->getOperand(1);
5223 if (Not.getOpcode() == ISD::ANY_EXTEND)
5224 Not = Not.getOperand(0);
5225 if (!isBitwiseNot(Not) || !Not.hasOneUse() || !isOneConstant(And1))
5226 return SDValue();
5227
5228 // Look though an optional truncation. The source operand may not be the same
5229 // type as the original 'and', but that is ok because we are masking off
5230 // everything but the low bit.
5231 SDValue Srl = Not.getOperand(0);
5232 if (Srl.getOpcode() == ISD::TRUNCATE)
5233 Srl = Srl.getOperand(0);
5234
5235 // Match a shift-right by constant.
5236 if (Srl.getOpcode() != ISD::SRL || !Srl.hasOneUse() ||
5237 !isa<ConstantSDNode>(Srl.getOperand(1)))
5238 return SDValue();
5239
5240 // We might have looked through casts that make this transform invalid.
5241 // TODO: If the source type is wider than the result type, do the mask and
5242 // compare in the source type.
5243 const APInt &ShiftAmt = Srl.getConstantOperandAPInt(1);
5244 unsigned VTBitWidth = VT.getSizeInBits();
5245 if (ShiftAmt.uge(VTBitWidth))
5246 return SDValue();
5247
5248 // Turn this into a bit-test pattern using mask op + setcc:
5249 // and (not (srl X, C)), 1 --> (and X, 1<<C) == 0
5250 SDLoc DL(And);
5251 SDValue X = DAG.getZExtOrTrunc(Srl.getOperand(0), DL, VT);
5252 EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
5253 SDValue Mask = DAG.getConstant(
5254 APInt::getOneBitSet(VTBitWidth, ShiftAmt.getZExtValue()), DL, VT);
5255 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, Mask);
5256 SDValue Zero = DAG.getConstant(0, DL, VT);
5257 SDValue Setcc = DAG.getSetCC(DL, CCVT, NewAnd, Zero, ISD::SETEQ);
5258 return DAG.getZExtOrTrunc(Setcc, DL, VT);
5259}
5260
5261SDValue DAGCombiner::visitAND(SDNode *N) {
5262 SDValue N0 = N->getOperand(0);
5263 SDValue N1 = N->getOperand(1);
5264 EVT VT = N1.getValueType();
5265
5266 // x & x --> x
5267 if (N0 == N1)
5268 return N0;
5269
5270 // fold vector ops
5271 if (VT.isVector()) {
5272 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5273 return FoldedVOp;
5274
5275 // fold (and x, 0) -> 0, vector edition
5276 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5277 // do not return N0, because undef node may exist in N0
5278 return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()),
5279 SDLoc(N), N0.getValueType());
5280 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5281 // do not return N1, because undef node may exist in N1
5282 return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()),
5283 SDLoc(N), N1.getValueType());
5284
5285 // fold (and x, -1) -> x, vector edition
5286 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5287 return N1;
5288 if (ISD::isBuildVectorAllOnes(N1.getNode()))
5289 return N0;
5290
5291 // fold (and (masked_load) (build_vec (x, ...))) to zext_masked_load
5292 auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
5293 auto *BVec = dyn_cast<BuildVectorSDNode>(N1);
5294 if (MLoad && BVec && MLoad->getExtensionType() == ISD::EXTLOAD &&
5295 N0.hasOneUse() && N1.hasOneUse()) {
5296 EVT LoadVT = MLoad->getMemoryVT();
5297 EVT ExtVT = VT;
5298 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT, LoadVT)) {
5299 // For this AND to be a zero extension of the masked load the elements
5300 // of the BuildVec must mask the bottom bits of the extended element
5301 // type
5302 if (ConstantSDNode *Splat = BVec->getConstantSplatNode()) {
5303 TypeSize ElementSize =
5304 LoadVT.getVectorElementType().getScalarSizeInBits();
5305 if (Splat->getAPIntValue().isMask((uint64_t)ElementSize)) {
5306 return DAG.getMaskedLoad(
5307 ExtVT, SDLoc(N), MLoad->getChain(), MLoad->getBasePtr(),
5308 MLoad->getOffset(), MLoad->getMask(), MLoad->getPassThru(),
5309 LoadVT, MLoad->getMemOperand(), MLoad->getAddressingMode(),
5310 ISD::ZEXTLOAD, MLoad->isExpandingLoad());
5311 }
5312 }
5313 }
5314 }
5315 }
5316
5317 // fold (and c1, c2) -> c1&c2
5318 ConstantSDNode *N1C = isConstOrConstSplat(N1);
5319 if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, {N0, N1}))
5320 return C;
5321
5322 // canonicalize constant to RHS
5323 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5324 !DAG.isConstantIntBuildVectorOrConstantInt(N1))
5325 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
5326
5327 // fold (and x, -1) -> x
5328 if (isAllOnesConstant(N1))
5329 return N0;
5330
5331 // if (and x, c) is known to be zero, return 0
5332 unsigned BitWidth = VT.getScalarSizeInBits();
5333 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
5334 APInt::getAllOnesValue(BitWidth)))
5335 return DAG.getConstant(0, SDLoc(N), VT);
5336
5337 if (SDValue NewSel = foldBinOpIntoSelect(N))
5338 return NewSel;
5339
5340 // reassociate and
5341 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
5342 return RAND;
5343
5344 // Try to convert a constant mask AND into a shuffle clear mask.
5345 if (VT.isVector())
5346 if (SDValue Shuffle = XformToShuffleWithZero(N))
5347 return Shuffle;
5348
5349 if (SDValue Combined = combineCarryDiamond(*this, DAG, TLI, N0, N1, N))
5350 return Combined;
5351
5352 // fold (and (or x, C), D) -> D if (C & D) == D
5353 auto MatchSubset = [](ConstantSDNode *LHS, ConstantSDNode *RHS) {
5354 return RHS->getAPIntValue().isSubsetOf(LHS->getAPIntValue());
5355 };
5356 if (N0.getOpcode() == ISD::OR &&
5357 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
5358 return N1;
5359 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
5360 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
5361 SDValue N0Op0 = N0.getOperand(0);
5362 APInt Mask = ~N1C->getAPIntValue();
5363 Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
5364 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
5365 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
5366 N0.getValueType(), N0Op0);
5367
5368 // Replace uses of the AND with uses of the Zero extend node.
5369 CombineTo(N, Zext);
5370
5371 // We actually want to replace all uses of the any_extend with the
5372 // zero_extend, to avoid duplicating things. This will later cause this
5373 // AND to be folded.
5374 CombineTo(N0.getNode(), Zext);
5375 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5376 }
5377 }
5378
5379 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
5380 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
5381 // already be zero by virtue of the width of the base type of the load.
5382 //
5383 // the 'X' node here can either be nothing or an extract_vector_elt to catch
5384 // more cases.
5385 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5386 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
5387 N0.getOperand(0).getOpcode() == ISD::LOAD &&
5388 N0.getOperand(0).getResNo() == 0) ||
5389 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
5390 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
5391 N0 : N0.getOperand(0) );
5392
5393 // Get the constant (if applicable) the zero'th operand is being ANDed with.
5394 // This can be a pure constant or a vector splat, in which case we treat the
5395 // vector as a scalar and use the splat value.
5396 APInt Constant = APInt::getNullValue(1);
5397 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
5398 Constant = C->getAPIntValue();
5399 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
5400 APInt SplatValue, SplatUndef;
5401 unsigned SplatBitSize;
5402 bool HasAnyUndefs;
5403 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
5404 SplatBitSize, HasAnyUndefs);
5405 if (IsSplat) {
5406 // Undef bits can contribute to a possible optimisation if set, so
5407 // set them.
5408 SplatValue |= SplatUndef;
5409
5410 // The splat value may be something like "0x00FFFFFF", which means 0 for
5411 // the first vector value and FF for the rest, repeating. We need a mask
5412 // that will apply equally to all members of the vector, so AND all the
5413 // lanes of the constant together.
5414 unsigned EltBitWidth = Vector->getValueType(0).getScalarSizeInBits();
5415
5416 // If the splat value has been compressed to a bitlength lower
5417 // than the size of the vector lane, we need to re-expand it to
5418 // the lane size.
5419 if (EltBitWidth > SplatBitSize)
5420 for (SplatValue = SplatValue.zextOrTrunc(EltBitWidth);
5421 SplatBitSize < EltBitWidth; SplatBitSize = SplatBitSize * 2)
5422 SplatValue |= SplatValue.shl(SplatBitSize);
5423
5424 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
5425 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
5426 if ((SplatBitSize % EltBitWidth) == 0) {
5427 Constant = APInt::getAllOnesValue(EltBitWidth);
5428 for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i)
5429 Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth);
5430 }
5431 }
5432 }
5433
5434 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
5435 // actually legal and isn't going to get expanded, else this is a false
5436 // optimisation.
5437 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
5438 Load->getValueType(0),
5439 Load->getMemoryVT());
5440
5441 // Resize the constant to the same size as the original memory access before
5442 // extension. If it is still the AllOnesValue then this AND is completely
5443 // unneeded.
5444 Constant = Constant.zextOrTrunc(Load->getMemoryVT().getScalarSizeInBits());
5445
5446 bool B;
5447 switch (Load->getExtensionType()) {
5448 default: B = false; break;
5449 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
5450 case ISD::ZEXTLOAD:
5451 case ISD::NON_EXTLOAD: B = true; break;
5452 }
5453
5454 if (B && Constant.isAllOnesValue()) {
5455 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
5456 // preserve semantics once we get rid of the AND.
5457 SDValue NewLoad(Load, 0);
5458
5459 // Fold the AND away. NewLoad may get replaced immediately.
5460 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
5461
5462 if (Load->getExtensionType() == ISD::EXTLOAD) {
5463 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
5464 Load->getValueType(0), SDLoc(Load),
5465 Load->getChain(), Load->getBasePtr(),
5466 Load->getOffset(), Load->getMemoryVT(),
5467 Load->getMemOperand());
5468 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
5469 if (Load->getNumValues() == 3) {
5470 // PRE/POST_INC loads have 3 values.
5471 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
5472 NewLoad.getValue(2) };
5473 CombineTo(Load, To, 3, true);
5474 } else {
5475 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
5476 }
5477 }
5478
5479 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5480 }
5481 }
5482
5483 // fold (and (load x), 255) -> (zextload x, i8)
5484 // fold (and (extload x, i16), 255) -> (zextload x, i8)
5485 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
5486 if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
5487 (N0.getOpcode() == ISD::ANY_EXTEND &&
5488 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
5489 if (SDValue Res = ReduceLoadWidth(N)) {
5490 LoadSDNode *LN0 = N0->getOpcode() == ISD::ANY_EXTEND
5491 ? cast<LoadSDNode>(N0.getOperand(0)) : cast<LoadSDNode>(N0);
5492 AddToWorklist(N);
5493 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 0), Res);
5494 return SDValue(N, 0);
5495 }
5496 }
5497
5498 if (LegalTypes) {
5499 // Attempt to propagate the AND back up to the leaves which, if they're
5500 // loads, can be combined to narrow loads and the AND node can be removed.
5501 // Perform after legalization so that extend nodes will already be
5502 // combined into the loads.
5503 if (BackwardsPropagateMask(N))
5504 return SDValue(N, 0);
5505 }
5506
5507 if (SDValue Combined = visitANDLike(N0, N1, N))
5508 return Combined;
5509
5510 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
5511 if (N0.getOpcode() == N1.getOpcode())
5512 if (SDValue V = hoistLogicOpWithSameOpcodeHands(N))
5513 return V;
5514
5515 // Masking the negated extension of a boolean is just the zero-extended
5516 // boolean:
5517 // and (sub 0, zext(bool X)), 1 --> zext(bool X)
5518 // and (sub 0, sext(bool X)), 1 --> zext(bool X)
5519 //
5520 // Note: the SimplifyDemandedBits fold below can make an information-losing
5521 // transform, and then we have no way to find this better fold.
5522 if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
5523 if (isNullOrNullSplat(N0.getOperand(0))) {
5524 SDValue SubRHS = N0.getOperand(1);
5525 if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
5526 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5527 return SubRHS;
5528 if (SubRHS.getOpcode() == ISD::SIGN_EXTEND &&
5529 SubRHS.getOperand(0).getScalarValueSizeInBits() == 1)
5530 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, SubRHS.getOperand(0));
5531 }
5532 }
5533
5534 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
5535 // fold (and (sra)) -> (and (srl)) when possible.
5536 if (SimplifyDemandedBits(SDValue(N, 0)))
5537 return SDValue(N, 0);
5538
5539 // fold (zext_inreg (extload x)) -> (zextload x)
5540 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
5541 if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
5542 (ISD::isEXTLoad(N0.getNode()) ||
5543 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
5544 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5545 EVT MemVT = LN0->getMemoryVT();
5546 // If we zero all the possible extended bits, then we can turn this into
5547 // a zextload if we are running before legalize or the operation is legal.
5548 unsigned ExtBitSize = N1.getScalarValueSizeInBits();
5549 unsigned MemBitSize = MemVT.getScalarSizeInBits();
5550 APInt ExtBits = APInt::getHighBitsSet(ExtBitSize, ExtBitSize - MemBitSize);
5551 if (DAG.MaskedValueIsZero(N1, ExtBits) &&
5552 ((!LegalOperations && LN0->isSimple()) ||
5553 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5554 SDValue ExtLoad =
5555 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
5556 LN0->getBasePtr(), MemVT, LN0->getMemOperand());
5557 AddToWorklist(N);
5558 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5559 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5560 }
5561 }
5562
5563 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
5564 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
5565 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5566 N0.getOperand(1), false))
5567 return BSwap;
5568 }
5569
5570 if (SDValue Shifts = unfoldExtremeBitClearingToShifts(N))
5571 return Shifts;
5572
5573 if (TLI.hasBitTest(N0, N1))
5574 if (SDValue V = combineShiftAnd1ToBitTest(N, DAG))
5575 return V;
5576
5577 return SDValue();
5578}
5579
5580/// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
5581SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
5582 bool DemandHighBits) {
5583 if (!LegalOperations)
5584 return SDValue();
5585
5586 EVT VT = N->getValueType(0);
5587 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
5588 return SDValue();
5589 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5590 return SDValue();
5591
5592 // Recognize (and (shl a, 8), 0xff00), (and (srl a, 8), 0xff)
5593 bool LookPassAnd0 = false;
5594 bool LookPassAnd1 = false;
5595 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
5596 std::swap(N0, N1);
5597 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
5598 std::swap(N0, N1);
5599 if (N0.getOpcode() == ISD::AND) {
5600 if (!N0.getNode()->hasOneUse())
5601 return SDValue();
5602 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5603 // Also handle 0xffff since the LHS is guaranteed to have zeros there.
5604 // This is needed for X86.
5605 if (!N01C || (N01C->getZExtValue() != 0xFF00 &&
5606 N01C->getZExtValue() != 0xFFFF))
5607 return SDValue();
5608 N0 = N0.getOperand(0);
5609 LookPassAnd0 = true;
5610 }
5611
5612 if (N1.getOpcode() == ISD::AND) {
5613 if (!N1.getNode()->hasOneUse())
5614 return SDValue();
5615 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5616 if (!N11C || N11C->getZExtValue() != 0xFF)
5617 return SDValue();
5618 N1 = N1.getOperand(0);
5619 LookPassAnd1 = true;
5620 }
5621
5622 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
5623 std::swap(N0, N1);
5624 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
5625 return SDValue();
5626 if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
5627 return SDValue();
5628
5629 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5630 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5631 if (!N01C || !N11C)
5632 return SDValue();
5633 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
5634 return SDValue();
5635
5636 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
5637 SDValue N00 = N0->getOperand(0);
5638 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
5639 if (!N00.getNode()->hasOneUse())
5640 return SDValue();
5641 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
5642 if (!N001C || N001C->getZExtValue() != 0xFF)
5643 return SDValue();
5644 N00 = N00.getOperand(0);
5645 LookPassAnd0 = true;
5646 }
5647
5648 SDValue N10 = N1->getOperand(0);
5649 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
5650 if (!N10.getNode()->hasOneUse())
5651 return SDValue();
5652 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
5653 // Also allow 0xFFFF since the bits will be shifted out. This is needed
5654 // for X86.
5655 if (!N101C || (N101C->getZExtValue() != 0xFF00 &&
5656 N101C->getZExtValue() != 0xFFFF))
5657 return SDValue();
5658 N10 = N10.getOperand(0);
5659 LookPassAnd1 = true;
5660 }
5661
5662 if (N00 != N10)
5663 return SDValue();
5664
5665 // Make sure everything beyond the low halfword gets set to zero since the SRL
5666 // 16 will clear the top bits.
5667 unsigned OpSizeInBits = VT.getSizeInBits();
5668 if (DemandHighBits && OpSizeInBits > 16) {
5669 // If the left-shift isn't masked out then the only way this is a bswap is
5670 // if all bits beyond the low 8 are 0. In that case the entire pattern
5671 // reduces to a left shift anyway: leave it for other parts of the combiner.
5672 if (!LookPassAnd0)
5673 return SDValue();
5674
5675 // However, if the right shift isn't masked out then it might be because
5676 // it's not needed. See if we can spot that too.
5677 if (!LookPassAnd1 &&
5678 !DAG.MaskedValueIsZero(
5679 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
5680 return SDValue();
5681 }
5682
5683 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
5684 if (OpSizeInBits > 16) {
5685 SDLoc DL(N);
5686 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
5687 DAG.getConstant(OpSizeInBits - 16, DL,
5688 getShiftAmountTy(VT)));
5689 }
5690 return Res;
5691}
5692
5693/// Return true if the specified node is an element that makes up a 32-bit
5694/// packed halfword byteswap.
5695/// ((x & 0x000000ff) << 8) |
5696/// ((x & 0x0000ff00) >> 8) |
5697/// ((x & 0x00ff0000) << 8) |
5698/// ((x & 0xff000000) >> 8)
5699static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
5700 if (!N.getNode()->hasOneUse())
5701 return false;
5702
5703 unsigned Opc = N.getOpcode();
5704 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
5705 return false;
5706
5707 SDValue N0 = N.getOperand(0);
5708 unsigned Opc0 = N0.getOpcode();
5709 if (Opc0 != ISD::AND && Opc0 != ISD::SHL && Opc0 != ISD::SRL)
5710 return false;
5711
5712 ConstantSDNode *N1C = nullptr;
5713 // SHL or SRL: look upstream for AND mask operand
5714 if (Opc == ISD::AND)
5715 N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5716 else if (Opc0 == ISD::AND)
5717 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5718 if (!N1C)
5719 return false;
5720
5721 unsigned MaskByteOffset;
5722 switch (N1C->getZExtValue()) {
5723 default:
5724 return false;
5725 case 0xFF: MaskByteOffset = 0; break;
5726 case 0xFF00: MaskByteOffset = 1; break;
5727 case 0xFFFF:
5728 // In case demanded bits didn't clear the bits that will be shifted out.
5729 // This is needed for X86.
5730 if (Opc == ISD::SRL || (Opc == ISD::AND && Opc0 == ISD::SHL)) {
5731 MaskByteOffset = 1;
5732 break;
5733 }
5734 return false;
5735 case 0xFF0000: MaskByteOffset = 2; break;
5736 case 0xFF000000: MaskByteOffset = 3; break;
5737 }
5738
5739 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
5740 if (Opc == ISD::AND) {
5741 if (MaskByteOffset == 0 || MaskByteOffset == 2) {
5742 // (x >> 8) & 0xff
5743 // (x >> 8) & 0xff0000
5744 if (Opc0 != ISD::SRL)
5745 return false;
5746 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5747 if (!C || C->getZExtValue() != 8)
5748 return false;
5749 } else {
5750 // (x << 8) & 0xff00
5751 // (x << 8) & 0xff000000
5752 if (Opc0 != ISD::SHL)
5753 return false;
5754 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5755 if (!C || C->getZExtValue() != 8)
5756 return false;
5757 }
5758 } else if (Opc == ISD::SHL) {
5759 // (x & 0xff) << 8
5760 // (x & 0xff0000) << 8
5761 if (MaskByteOffset != 0 && MaskByteOffset != 2)
5762 return false;
5763 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5764 if (!C || C->getZExtValue() != 8)
5765 return false;
5766 } else { // Opc == ISD::SRL
5767 // (x & 0xff00) >> 8
5768 // (x & 0xff000000) >> 8
5769 if (MaskByteOffset != 1 && MaskByteOffset != 3)
5770 return false;
5771 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
5772 if (!C || C->getZExtValue() != 8)
5773 return false;
5774 }
5775
5776 if (Parts[MaskByteOffset])
5777 return false;
5778
5779 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
5780 return true;
5781}
5782
5783// Match 2 elements of a packed halfword bswap.
5784static bool isBSwapHWordPair(SDValue N, MutableArrayRef<SDNode *> Parts) {
5785 if (N.getOpcode() == ISD::OR)
5786 return isBSwapHWordElement(N.getOperand(0), Parts) &&
5787 isBSwapHWordElement(N.getOperand(1), Parts);
5788
5789 if (N.getOpcode() == ISD::SRL && N.getOperand(0).getOpcode() == ISD::BSWAP) {
5790 ConstantSDNode *C = isConstOrConstSplat(N.getOperand(1));
5791 if (!C || C->getAPIntValue() != 16)
5792 return false;
5793 Parts[0] = Parts[1] = N.getOperand(0).getOperand(0).getNode();
5794 return true;
5795 }
5796
5797 return false;
5798}
5799
5800// Match this pattern:
5801// (or (and (shl (A, 8)), 0xff00ff00), (and (srl (A, 8)), 0x00ff00ff))
5802// And rewrite this to:
5803// (rotr (bswap A), 16)
5804static SDValue matchBSwapHWordOrAndAnd(const TargetLowering &TLI,
5805 SelectionDAG &DAG, SDNode *N, SDValue N0,
5806 SDValue N1, EVT VT, EVT ShiftAmountTy) {
5807 assert(N->getOpcode() == ISD::OR && VT == MVT::i32 &&((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
"MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5808, __PRETTY_FUNCTION__))
5808 "MatchBSwapHWordOrAndAnd: expecting i32")((N->getOpcode() == ISD::OR && VT == MVT::i32 &&
"MatchBSwapHWordOrAndAnd: expecting i32") ? static_cast<void
> (0) : __assert_fail ("N->getOpcode() == ISD::OR && VT == MVT::i32 && \"MatchBSwapHWordOrAndAnd: expecting i32\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 5808, __PRETTY_FUNCTION__))
;
5809 if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5810 return SDValue();
5811 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
5812 return SDValue();
5813 // TODO: this is too restrictive; lifting this restriction requires more tests
5814 if (!N0->hasOneUse() || !N1->hasOneUse())
5815 return SDValue();
5816 ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
5817 ConstantSDNode *Mask1 = isConstOrConstSplat(N1.getOperand(1));
5818 if (!Mask0 || !Mask1)
5819 return SDValue();
5820 if (Mask0->getAPIntValue() != 0xff00ff00 ||
5821 Mask1->getAPIntValue() != 0x00ff00ff)
5822 return SDValue();
5823 SDValue Shift0 = N0.getOperand(0);
5824 SDValue Shift1 = N1.getOperand(0);
5825 if (Shift0.getOpcode() != ISD::SHL || Shift1.getOpcode() != ISD::SRL)
5826 return SDValue();
5827 ConstantSDNode *ShiftAmt0 = isConstOrConstSplat(Shift0.getOperand(1));
5828 ConstantSDNode *ShiftAmt1 = isConstOrConstSplat(Shift1.getOperand(1));
5829 if (!ShiftAmt0 || !ShiftAmt1)
5830 return SDValue();
5831 if (ShiftAmt0->getAPIntValue() != 8 || ShiftAmt1->getAPIntValue() != 8)
5832 return SDValue();
5833 if (Shift0.getOperand(0) != Shift1.getOperand(0))
5834 return SDValue();
5835
5836 SDLoc DL(N);
5837 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, Shift0.getOperand(0));
5838 SDValue ShAmt = DAG.getConstant(16, DL, ShiftAmountTy);
5839 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5840}
5841
5842/// Match a 32-bit packed halfword bswap. That is
5843/// ((x & 0x000000ff) << 8) |
5844/// ((x & 0x0000ff00) >> 8) |
5845/// ((x & 0x00ff0000) << 8) |
5846/// ((x & 0xff000000) >> 8)
5847/// => (rotl (bswap x), 16)
5848SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
5849 if (!LegalOperations)
5850 return SDValue();
5851
5852 EVT VT = N->getValueType(0);
5853 if (VT != MVT::i32)
5854 return SDValue();
5855 if (!TLI.isOperationLegalOrCustom(ISD::BSWAP, VT))
5856 return SDValue();
5857
5858 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT,
5859 getShiftAmountTy(VT)))
5860 return BSwap;
5861
5862 // Try again with commuted operands.
5863 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT,
5864 getShiftAmountTy(VT)))
5865 return BSwap;
5866
5867
5868 // Look for either
5869 // (or (bswaphpair), (bswaphpair))
5870 // (or (or (bswaphpair), (and)), (and))
5871 // (or (or (and), (bswaphpair)), (and))
5872 SDNode *Parts[4] = {};
5873
5874 if (isBSwapHWordPair(N0, Parts)) {
5875 // (or (or (and), (and)), (or (and), (and)))
5876 if (!isBSwapHWordPair(N1, Parts))
5877 return SDValue();
5878 } else if (N0.getOpcode() == ISD::OR) {
5879 // (or (or (or (and), (and)), (and)), (and))
5880 if (!isBSwapHWordElement(N1, Parts))
5881 return SDValue();
5882 SDValue N00 = N0.getOperand(0);
5883 SDValue N01 = N0.getOperand(1);
5884 if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) &&
5885 !(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts)))
5886 return SDValue();
5887 } else
5888 return SDValue();
5889
5890 // Make sure the parts are all coming from the same node.
5891 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
5892 return SDValue();
5893
5894 SDLoc DL(N);
5895 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
5896 SDValue(Parts[0], 0));
5897
5898 // Result of the bswap should be rotated by 16. If it's not legal, then
5899 // do (x << 16) | (x >> 16).
5900 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
5901 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
5902 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
5903 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
5904 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
5905 return DAG.getNode(ISD::OR, DL, VT,
5906 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
5907 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
5908}
5909
5910/// This contains all DAGCombine rules which reduce two values combined by
5911/// an Or operation to a single value \see visitANDLike().
5912SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *N) {
5913 EVT VT = N1.getValueType();
5914 SDLoc DL(N);
5915
5916 // fold (or x, undef) -> -1
5917 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
5918 return DAG.getAllOnesConstant(DL, VT);
5919
5920 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
5921 return V;
5922
5923 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
5924 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
5925 // Don't increase # computations.
5926 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5927 // We can only do this xform if we know that bits from X that are set in C2
5928 // but not in C1 are already zero. Likewise for Y.
5929 if (const ConstantSDNode *N0O1C =
5930 getAsNonOpaqueConstant(N0.getOperand(1))) {
5931 if (const ConstantSDNode *N1O1C =
5932 getAsNonOpaqueConstant(N1.getOperand(1))) {
5933 // We can only do this xform if we know that bits from X that are set in
5934 // C2 but not in C1 are already zero. Likewise for Y.
5935 const APInt &LHSMask = N0O1C->getAPIntValue();
5936 const APInt &RHSMask = N1O1C->getAPIntValue();
5937
5938 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
5939 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
5940 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5941 N0.getOperand(0), N1.getOperand(0));
5942 return DAG.getNode(ISD::AND, DL, VT, X,
5943 DAG.getConstant(LHSMask | RHSMask, DL, VT));
5944 }
5945 }
5946 }
5947 }
5948
5949 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
5950 if (N0.getOpcode() == ISD::AND &&
5951 N1.getOpcode() == ISD::AND &&
5952 N0.getOperand(0) == N1.getOperand(0) &&
5953 // Don't increase # computations.
5954 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
5955 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
5956 N0.getOperand(1), N1.getOperand(1));
5957 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
5958 }
5959
5960 return SDValue();
5961}
5962
5963/// OR combines for which the commuted variant will be tried as well.
5964static SDValue visitORCommutative(
5965 SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) {
5966 EVT VT = N0.getValueType();
5967 if (N0.getOpcode() == ISD::AND) {
5968 // fold (or (and X, (xor Y, -1)), Y) -> (or X, Y)
5969 if (isBitwiseNot(N0.getOperand(1)) && N0.getOperand(1).getOperand(0) == N1)
5970 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(0), N1);
5971
5972 // fold (or (and (xor Y, -1), X), Y) -> (or X, Y)
5973 if (isBitwiseNot(N0.getOperand(0)) && N0.getOperand(0).getOperand(0) == N1)
5974 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0.getOperand(1), N1);
5975 }
5976
5977 return SDValue();
5978}
5979
5980SDValue DAGCombiner::visitOR(SDNode *N) {
5981 SDValue N0 = N->getOperand(0);
5982 SDValue N1 = N->getOperand(1);
5983 EVT VT = N1.getValueType();
5984
5985 // x | x --> x
5986 if (N0 == N1)
5987 return N0;
5988
5989 // fold vector ops
5990 if (VT.isVector()) {
5991 if (SDValue FoldedVOp = SimplifyVBinOp(N))
5992 return FoldedVOp;
5993
5994 // fold (or x, 0) -> x, vector edition
5995 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5996 return N1;
5997 if (ISD::isBuildVectorAllZeros(N1.getNode()))
5998 return N0;
5999
6000 // fold (or x, -1) -> -1, vector edition
6001 if (ISD::isBuildVectorAllOnes(N0.getNode()))
6002 // do not return N0, because undef node may exist in N0
6003 return DAG.getAllOnesConstant(SDLoc(N), N0.getValueType());
6004 if (ISD::isBuildVectorAllOnes(N1.getNode()))
6005 // do not return N1, because undef node may exist in N1
6006 return DAG.getAllOnesConstant(SDLoc(N), N1.getValueType());
6007
6008 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask)
6009 // Do this only if the resulting shuffle is legal.
6010 if (isa<ShuffleVectorSDNode>(N0) &&
6011 isa<ShuffleVectorSDNode>(N1) &&
6012 // Avoid folding a node with illegal type.
6013 TLI.isTypeLegal(VT)) {
6014 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
6015 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
6016 bool ZeroN10 = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
6017 bool ZeroN11 = ISD::isBuildVectorAllZeros(N1.getOperand(1).getNode());
6018 // Ensure both shuffles have a zero input.
6019 if ((ZeroN00 != ZeroN01) && (ZeroN10 != ZeroN11)) {
6020 assert((!ZeroN00 || !ZeroN01) && "Both inputs zero!")(((!ZeroN00 || !ZeroN01) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN00 || !ZeroN01) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6020, __PRETTY_FUNCTION__))
;
6021 assert((!ZeroN10 || !ZeroN11) && "Both inputs zero!")(((!ZeroN10 || !ZeroN11) && "Both inputs zero!") ? static_cast
<void> (0) : __assert_fail ("(!ZeroN10 || !ZeroN11) && \"Both inputs zero!\""
, "/build/llvm-toolchain-snapshot-12~++20200917111122+b03c2b8395b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
, 6021, __PRETTY_FUNCTION__))
;
6022 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
6023 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
6024 bool CanFold = true;
6025 int NumElts = VT.getVectorNumElements();
6026 SmallVector<int, 4> Mask(NumElts);
6027
6028 for (int i = 0; i != NumElts; ++i) {
6029 int M0 = SV0->getMaskElt(i);
6030 int M1 = SV1->getMaskElt(i);
6031
6032 // Determine if either index is pointing to a zero vector.
6033 bool M0Zero = M0 < 0 || (ZeroN00 == (M0 < NumElts));
6034 bool M1Zero = M1 < 0 || (ZeroN10 == (M1 < NumElts));
6035
6036 // If one element is zero and the otherside is undef, keep undef.
6037 // This also handles the case that both are undef.
6038 if ((M0Zero && M1 < 0) || (M1Zero && M0 < 0)) {
6039 Mask[i] = -1;
6040 continue;
6041 }
6042
6043 // Make sure only one of the elements is zero.
6044 if (M0Zero == M1Zero) {
6045 CanFold = false;
6046 break;
6047 }
6048
6049 assert((M0 >= 0 || M1 >= 0) && "Undef index!")(((M0 >= 0 || M1 >= 0) && "Undef index!") ? static_cast
<void> (0) : __assert_fail ("(M0 >= 0 || M1 >= 0) && \"Undef index!\"