Bug Summary

File:lib/CodeGen/AsmPrinter/DwarfExpression.cpp
Location:line 230, column 7
Description:Value stored to 'ValidReg' is never read

Annotated Source Code

1//===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains support for writing dwarf debug info into asm files.
11//
12//===----------------------------------------------------------------------===//
13
14#include "DwarfExpression.h"
15#include "DwarfDebug.h"
16#include "llvm/ADT/SmallBitVector.h"
17#include "llvm/CodeGen/AsmPrinter.h"
18#include "llvm/Support/Dwarf.h"
19#include "llvm/Target/TargetMachine.h"
20#include "llvm/Target/TargetRegisterInfo.h"
21#include "llvm/Target/TargetSubtargetInfo.h"
22
23using namespace llvm;
24
25const TargetRegisterInfo *DwarfExpression::getTRI() const {
26 return AP.TM.getSubtargetImpl()->getRegisterInfo();
27}
28
29unsigned DwarfExpression::getDwarfVersion() const {
30 return AP.getDwarfDebug()->getDwarfVersion();
31}
32
33void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
34 assert(DwarfReg >= 0 && "invalid negative dwarf register number")((DwarfReg >= 0 && "invalid negative dwarf register number"
) ? static_cast<void> (0) : __assert_fail ("DwarfReg >= 0 && \"invalid negative dwarf register number\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227765/lib/CodeGen/AsmPrinter/DwarfExpression.cpp"
, 34, __PRETTY_FUNCTION__));
35 if (DwarfReg < 32) {
36 EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
37 } else {
38 EmitOp(dwarf::DW_OP_regx, Comment);
39 EmitUnsigned(DwarfReg);
40 }
41}
42
43void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
44 assert(DwarfReg >= 0 && "invalid negative dwarf register number")((DwarfReg >= 0 && "invalid negative dwarf register number"
) ? static_cast<void> (0) : __assert_fail ("DwarfReg >= 0 && \"invalid negative dwarf register number\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227765/lib/CodeGen/AsmPrinter/DwarfExpression.cpp"
, 44, __PRETTY_FUNCTION__));
45 if (DwarfReg < 32) {
46 EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
47 } else {
48 EmitOp(dwarf::DW_OP_bregx);
49 EmitUnsigned(DwarfReg);
50 }
51 EmitSigned(Offset);
52 if (Deref)
53 EmitOp(dwarf::DW_OP_deref);
54}
55
56void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
57 assert(SizeInBits > 0 && "piece has size zero")((SizeInBits > 0 && "piece has size zero") ? static_cast
<void> (0) : __assert_fail ("SizeInBits > 0 && \"piece has size zero\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227765/lib/CodeGen/AsmPrinter/DwarfExpression.cpp"
, 57, __PRETTY_FUNCTION__));
58 const unsigned SizeOfByte = 8;
59 if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
60 EmitOp(dwarf::DW_OP_bit_piece);
61 EmitUnsigned(SizeInBits);
62 EmitUnsigned(OffsetInBits);
63 } else {
64 EmitOp(dwarf::DW_OP_piece);
65 unsigned ByteSize = SizeInBits / SizeOfByte;
66 EmitUnsigned(ByteSize);
67 }
68}
69
70void DwarfExpression::AddShr(unsigned ShiftBy) {
71 EmitOp(dwarf::DW_OP_constu);
72 EmitUnsigned(ShiftBy);
73 EmitOp(dwarf::DW_OP_shr);
74}
75
76bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
77 int DwarfReg = getTRI()->getDwarfRegNum(MachineReg, false);
78 if (DwarfReg < 0)
79 return false;
80
81 if (isFrameRegister(MachineReg)) {
82 // If variable offset is based in frame register then use fbreg.
83 EmitOp(dwarf::DW_OP_fbreg);
84 EmitSigned(Offset);
85 } else {
86 AddRegIndirect(DwarfReg, Offset);
87 }
88 return true;
89}
90
91bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
92 unsigned PieceSizeInBits,
93 unsigned PieceOffsetInBits) {
94 const TargetRegisterInfo *TRI = getTRI();
95 if (!TRI->isPhysicalRegister(MachineReg))
96 return false;
97
98 int Reg = TRI->getDwarfRegNum(MachineReg, false);
99
100 // If this is a valid register number, emit it.
101 if (Reg >= 0) {
102 AddReg(Reg);
103 if (PieceSizeInBits)
104 AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
105 return true;
106 }
107
108 // Walk up the super-register chain until we find a valid number.
109 // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
110 for (MCSuperRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
111 Reg = TRI->getDwarfRegNum(*SR, false);
112 if (Reg >= 0) {
113 unsigned Idx = TRI->getSubRegIndex(*SR, MachineReg);
114 unsigned Size = TRI->getSubRegIdxSize(Idx);
115 unsigned RegOffset = TRI->getSubRegIdxOffset(Idx);
116 AddReg(Reg, "super-register");
117 if (PieceOffsetInBits == RegOffset) {
118 AddOpPiece(Size, RegOffset);
119 } else {
120 // If this is part of a variable in a sub-register at a
121 // non-zero offset, we need to manually shift the value into
122 // place, since the DW_OP_piece describes the part of the
123 // variable, not the position of the subregister.
124 if (RegOffset)
125 AddShr(RegOffset);
126 AddOpPiece(Size, PieceOffsetInBits);
127 }
128 return true;
129 }
130 }
131
132 // Otherwise, attempt to find a covering set of sub-register numbers.
133 // For example, Q0 on ARM is a composition of D0+D1.
134 //
135 // Keep track of the current position so we can emit the more
136 // efficient DW_OP_piece.
137 unsigned CurPos = PieceOffsetInBits;
138 // The size of the register in bits, assuming 8 bits per byte.
139 unsigned RegSize = TRI->getMinimalPhysRegClass(MachineReg)->getSize() * 8;
140 // Keep track of the bits in the register we already emitted, so we
141 // can avoid emitting redundant aliasing subregs.
142 SmallBitVector Coverage(RegSize, false);
143 for (MCSubRegIterator SR(MachineReg, TRI); SR.isValid(); ++SR) {
144 unsigned Idx = TRI->getSubRegIndex(MachineReg, *SR);
145 unsigned Size = TRI->getSubRegIdxSize(Idx);
146 unsigned Offset = TRI->getSubRegIdxOffset(Idx);
147 Reg = TRI->getDwarfRegNum(*SR, false);
148
149 // Intersection between the bits we already emitted and the bits
150 // covered by this subregister.
151 SmallBitVector Intersection(RegSize, false);
152 Intersection.set(Offset, Offset + Size);
153 Intersection ^= Coverage;
154
155 // If this sub-register has a DWARF number and we haven't covered
156 // its range, emit a DWARF piece for it.
157 if (Reg >= 0 && Intersection.any()) {
158 AddReg(Reg, "sub-register");
159 AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
160 CurPos = Offset + Size;
161
162 // Mark it as emitted.
163 Coverage.set(Offset, Offset + Size);
164 }
165 }
166
167 return CurPos > PieceOffsetInBits;
168}
169
170void DwarfExpression::AddSignedConstant(int Value) {
171 EmitOp(dwarf::DW_OP_consts);
172 EmitSigned(Value);
173 // The proper way to describe a constant value is
174 // DW_OP_constu <const>, DW_OP_stack_value.
175 // Unfortunately, DW_OP_stack_value was not available until DWARF-4,
176 // so we will continue to generate DW_OP_constu <const> for DWARF-2
177 // and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
178 // actually describes a value at a constant addess, not a constant value.
179 // However, in the past there was no better way to describe a constant
180 // value, so the producers and consumers started to rely on heuristics
181 // to disambiguate the value vs. location status of the expression.
182 // See PR21176 for more details.
183 if (getDwarfVersion() >= 4)
184 EmitOp(dwarf::DW_OP_stack_value);
185}
186
187void DwarfExpression::AddUnsignedConstant(unsigned Value) {
188 EmitOp(dwarf::DW_OP_constu);
189 EmitUnsigned(Value);
190 // cf. comment in DwarfExpression::AddSignedConstant().
191 if (getDwarfVersion() >= 4)
192 EmitOp(dwarf::DW_OP_stack_value);
193}
194
195static unsigned getOffsetOrZero(unsigned OffsetInBits,
196 unsigned PieceOffsetInBits) {
197 if (OffsetInBits == PieceOffsetInBits)
198 return 0;
199 assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces")((OffsetInBits >= PieceOffsetInBits && "overlapping pieces"
) ? static_cast<void> (0) : __assert_fail ("OffsetInBits >= PieceOffsetInBits && \"overlapping pieces\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227765/lib/CodeGen/AsmPrinter/DwarfExpression.cpp"
, 199, __PRETTY_FUNCTION__));
200 return OffsetInBits;
201}
202
203bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
204 unsigned MachineReg,
205 unsigned PieceOffsetInBits) {
206 auto I = Expr.begin();
207 // Pattern-match combinations for which more efficient representations exist
208 // first.
209 if (I == Expr.end())
210 return AddMachineRegPiece(MachineReg);
211
212 bool ValidReg = false;
213 switch (*I) {
214 case dwarf::DW_OP_piece: {
215 unsigned SizeOfByte = 8;
216 unsigned OffsetInBits = I->getArg(1) * SizeOfByte;
217 unsigned SizeInBits = I->getArg(2) * SizeOfByte;
218 // Piece always comes at the end of the expression.
219 return AddMachineRegPiece(MachineReg, SizeInBits,
220 getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
221 }
222 case dwarf::DW_OP_plus:
223 // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
224 if (I->getNext() == dwarf::DW_OP_deref) {
225 unsigned Offset = I->getArg(1);
226 ValidReg = AddMachineRegIndirect(MachineReg, Offset);
227 std::advance(I, 2);
228 break;
229 } else
230 ValidReg = AddMachineRegPiece(MachineReg);
Value stored to 'ValidReg' is never read
231 case dwarf::DW_OP_deref:
232 // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
233 ValidReg = AddMachineRegIndirect(MachineReg);
234 ++I;
235 break;
236 default:
237 llvm_unreachable("unsupported operand")::llvm::llvm_unreachable_internal("unsupported operand", "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227765/lib/CodeGen/AsmPrinter/DwarfExpression.cpp"
, 237);
238 }
239
240 if (!ValidReg)
241 return false;
242
243 // Emit remaining elements of the expression.
244 AddExpression(I, PieceOffsetInBits);
245 return true;
246}
247
248void DwarfExpression::AddExpression(DIExpression::iterator I,
249 unsigned PieceOffsetInBits) {
250 for (; I != DIExpression::iterator(); ++I) {
251 switch (*I) {
252 case dwarf::DW_OP_piece: {
253 unsigned SizeOfByte = 8;
254 unsigned OffsetInBits = I->getArg(1) * SizeOfByte;
255 unsigned SizeInBits = I->getArg(2) * SizeOfByte;
256 AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
257 break;
258 }
259 case dwarf::DW_OP_plus:
260 EmitOp(dwarf::DW_OP_plus_uconst);
261 EmitUnsigned(I->getArg(1));
262 break;
263 case dwarf::DW_OP_deref:
264 EmitOp(dwarf::DW_OP_deref);
265 break;
266 default:
267 llvm_unreachable("unhandled opcode found in DIExpression")::llvm::llvm_unreachable_internal("unhandled opcode found in DIExpression"
, "/tmp/buildd/llvm-toolchain-snapshot-3.7~svn227765/lib/CodeGen/AsmPrinter/DwarfExpression.cpp"
, 267);
268 }
269 }
270}