Bug Summary

File:lib/Target/Hexagon/HexagonConstPropagation.cpp
Warning:line 2740, column 24
3rd function call argument is an uninitialized value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonConstPropagation.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/Target/Hexagon -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp
1//===- HexagonConstPropagation.cpp ----------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE"hcp" "hcp"
11
12#include "HexagonInstrInfo.h"
13#include "HexagonRegisterInfo.h"
14#include "HexagonSubtarget.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/APInt.h"
17#include "llvm/ADT/PostOrderIterator.h"
18#include "llvm/ADT/SetVector.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/ADT/StringRef.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFunction.h"
23#include "llvm/CodeGen/MachineFunctionPass.h"
24#include "llvm/CodeGen/MachineInstr.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineOperand.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/TargetRegisterInfo.h"
29#include "llvm/CodeGen/TargetSubtargetInfo.h"
30#include "llvm/IR/Constants.h"
31#include "llvm/IR/Type.h"
32#include "llvm/Pass.h"
33#include "llvm/Support/Casting.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/MathExtras.h"
38#include "llvm/Support/raw_ostream.h"
39#include <cassert>
40#include <cstdint>
41#include <cstring>
42#include <iterator>
43#include <map>
44#include <queue>
45#include <set>
46#include <utility>
47#include <vector>
48
49using namespace llvm;
50
51namespace {
52
53 // Properties of a value that are tracked by the propagation.
54 // A property that is marked as present (i.e. bit is set) dentes that the
55 // value is known (proven) to have this property. Not all combinations
56 // of bits make sense, for example Zero and NonZero are mutually exclusive,
57 // but on the other hand, Zero implies Finite. In this case, whenever
58 // the Zero property is present, Finite should also be present.
59 class ConstantProperties {
60 public:
61 enum {
62 Unknown = 0x0000,
63 Zero = 0x0001,
64 NonZero = 0x0002,
65 Finite = 0x0004,
66 Infinity = 0x0008,
67 NaN = 0x0010,
68 SignedZero = 0x0020,
69 NumericProperties = (Zero|NonZero|Finite|Infinity|NaN|SignedZero),
70 PosOrZero = 0x0100,
71 NegOrZero = 0x0200,
72 SignProperties = (PosOrZero|NegOrZero),
73 Everything = (NumericProperties|SignProperties)
74 };
75
76 // For a given constant, deduce the set of trackable properties that this
77 // constant has.
78 static uint32_t deduce(const Constant *C);
79 };
80
81 // A representation of a register as it can appear in a MachineOperand,
82 // i.e. a pair register:subregister.
83 struct Register {
84 unsigned Reg, SubReg;
85
86 explicit Register(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
87 explicit Register(const MachineOperand &MO)
88 : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
89
90 void print(const TargetRegisterInfo *TRI = nullptr) const {
91 dbgs() << printReg(Reg, TRI, SubReg);
92 }
93
94 bool operator== (const Register &R) const {
95 return (Reg == R.Reg) && (SubReg == R.SubReg);
96 }
97 };
98
99 // Lattice cell, based on that was described in the W-Z paper on constant
100 // propagation.
101 // Latice cell will be allowed to hold multiple constant values. While
102 // multiple values would normally indicate "bottom", we can still derive
103 // some useful information from them. For example, comparison X > 0
104 // could be folded if all the values in the cell associated with X are
105 // positive.
106 class LatticeCell {
107 private:
108 enum { Normal, Top, Bottom };
109
110 static const unsigned MaxCellSize = 4;
111
112 unsigned Kind:2;
113 unsigned Size:3;
114 unsigned IsSpecial:1;
115 unsigned :0;
116
117 public:
118 union {
119 uint32_t Properties;
120 const Constant *Value;
121 const Constant *Values[MaxCellSize];
122 };
123
124 LatticeCell() : Kind(Top), Size(0), IsSpecial(false) {
125 for (unsigned i = 0; i < MaxCellSize; ++i)
126 Values[i] = nullptr;
127 }
128
129 bool meet(const LatticeCell &L);
130 bool add(const Constant *C);
131 bool add(uint32_t Property);
132 uint32_t properties() const;
133 unsigned size() const { return Size; }
134
135 LatticeCell &operator= (const LatticeCell &L) {
136 if (this != &L) {
137 // This memcpy also copies Properties (when L.Size == 0).
138 uint32_t N = L.IsSpecial ? sizeof L.Properties
139 : L.Size*sizeof(const Constant*);
140 memcpy(Values, L.Values, N);
141 Kind = L.Kind;
142 Size = L.Size;
143 IsSpecial = L.IsSpecial;
144 }
145 return *this;
146 }
147
148 bool isSingle() const { return size() == 1; }
149 bool isProperty() const { return IsSpecial; }
150 bool isTop() const { return Kind == Top; }
151 bool isBottom() const { return Kind == Bottom; }
152
153 bool setBottom() {
154 bool Changed = (Kind != Bottom);
155 Kind = Bottom;
156 Size = 0;
157 IsSpecial = false;
158 return Changed;
159 }
160
161 void print(raw_ostream &os) const;
162
163 private:
164 void setProperty() {
165 IsSpecial = true;
166 Size = 0;
167 Kind = Normal;
168 }
169
170 bool convertToProperty();
171 };
172
173#ifndef NDEBUG
174 raw_ostream &operator<< (raw_ostream &os, const LatticeCell &L) {
175 L.print(os);
176 return os;
177 }
178#endif
179
180 class MachineConstEvaluator;
181
182 class MachineConstPropagator {
183 public:
184 MachineConstPropagator(MachineConstEvaluator &E) : MCE(E) {
185 Bottom.setBottom();
186 }
187
188 // Mapping: vreg -> cell
189 // The keys are registers _without_ subregisters. This won't allow
190 // definitions in the form of "vreg:subreg = ...". Such definitions
191 // would be questionable from the point of view of SSA, since the "vreg"
192 // could not be initialized in its entirety (specifically, an instruction
193 // defining the "other part" of "vreg" would also count as a definition
194 // of "vreg", which would violate the SSA).
195 // If a value of a pair vreg:subreg needs to be obtained, the cell for
196 // "vreg" needs to be looked up, and then the value of subregister "subreg"
197 // needs to be evaluated.
198 class CellMap {
199 public:
200 CellMap() {
201 assert(Top.isTop())(static_cast <bool> (Top.isTop()) ? void (0) : __assert_fail
("Top.isTop()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 201, __extension__ __PRETTY_FUNCTION__))
;
202 Bottom.setBottom();
203 }
204
205 void clear() { Map.clear(); }
206
207 bool has(unsigned R) const {
208 // All non-virtual registers are considered "bottom".
209 if (!TargetRegisterInfo::isVirtualRegister(R))
210 return true;
211 MapType::const_iterator F = Map.find(R);
212 return F != Map.end();
213 }
214
215 const LatticeCell &get(unsigned R) const {
216 if (!TargetRegisterInfo::isVirtualRegister(R))
217 return Bottom;
218 MapType::const_iterator F = Map.find(R);
219 if (F != Map.end())
220 return F->second;
221 return Top;
222 }
223
224 // Invalidates any const references.
225 void update(unsigned R, const LatticeCell &L) {
226 Map[R] = L;
227 }
228
229 void print(raw_ostream &os, const TargetRegisterInfo &TRI) const;
230
231 private:
232 using MapType = std::map<unsigned, LatticeCell>;
233
234 MapType Map;
235 // To avoid creating "top" entries, return a const reference to
236 // this cell in "get". Also, have a "Bottom" cell to return from
237 // get when a value of a physical register is requested.
238 LatticeCell Top, Bottom;
239
240 public:
241 using const_iterator = MapType::const_iterator;
242
243 const_iterator begin() const { return Map.begin(); }
244 const_iterator end() const { return Map.end(); }
245 };
246
247 bool run(MachineFunction &MF);
248
249 private:
250 void visitPHI(const MachineInstr &PN);
251 void visitNonBranch(const MachineInstr &MI);
252 void visitBranchesFrom(const MachineInstr &BrI);
253 void visitUsesOf(unsigned R);
254 bool computeBlockSuccessors(const MachineBasicBlock *MB,
255 SetVector<const MachineBasicBlock*> &Targets);
256 void removeCFGEdge(MachineBasicBlock *From, MachineBasicBlock *To);
257
258 void propagate(MachineFunction &MF);
259 bool rewrite(MachineFunction &MF);
260
261 MachineRegisterInfo *MRI;
262 MachineConstEvaluator &MCE;
263
264 using CFGEdge = std::pair<unsigned, unsigned>;
265 using SetOfCFGEdge = std::set<CFGEdge>;
266 using SetOfInstr = std::set<const MachineInstr *>;
267 using QueueOfCFGEdge = std::queue<CFGEdge>;
268
269 LatticeCell Bottom;
270 CellMap Cells;
271 SetOfCFGEdge EdgeExec;
272 SetOfInstr InstrExec;
273 QueueOfCFGEdge FlowQ;
274 };
275
276 // The "evaluator/rewriter" of machine instructions. This is an abstract
277 // base class that provides the interface that the propagator will use,
278 // as well as some helper functions that are target-independent.
279 class MachineConstEvaluator {
280 public:
281 MachineConstEvaluator(MachineFunction &Fn)
282 : TRI(*Fn.getSubtarget().getRegisterInfo()),
283 MF(Fn), CX(Fn.getFunction().getContext()) {}
284 virtual ~MachineConstEvaluator() = default;
285
286 // The required interface:
287 // - A set of three "evaluate" functions. Each returns "true" if the
288 // computation succeeded, "false" otherwise.
289 // (1) Given an instruction MI, and the map with input values "Inputs",
290 // compute the set of output values "Outputs". An example of when
291 // the computation can "fail" is if MI is not an instruction that
292 // is recognized by the evaluator.
293 // (2) Given a register R (as reg:subreg), compute the cell that
294 // corresponds to the "subreg" part of the given register.
295 // (3) Given a branch instruction BrI, compute the set of target blocks.
296 // If the branch can fall-through, add null (0) to the list of
297 // possible targets.
298 // - A function "rewrite", that given the cell map after propagation,
299 // could rewrite instruction MI in a more beneficial form. Return
300 // "true" if a change has been made, "false" otherwise.
301 using CellMap = MachineConstPropagator::CellMap;
302 virtual bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
303 CellMap &Outputs) = 0;
304 virtual bool evaluate(const Register &R, const LatticeCell &SrcC,
305 LatticeCell &Result) = 0;
306 virtual bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
307 SetVector<const MachineBasicBlock*> &Targets,
308 bool &CanFallThru) = 0;
309 virtual bool rewrite(MachineInstr &MI, const CellMap &Inputs) = 0;
310
311 const TargetRegisterInfo &TRI;
312
313 protected:
314 MachineFunction &MF;
315 LLVMContext &CX;
316
317 struct Comparison {
318 enum {
319 Unk = 0x00,
320 EQ = 0x01,
321 NE = 0x02,
322 L = 0x04, // Less-than property.
323 G = 0x08, // Greater-than property.
324 U = 0x40, // Unsigned property.
325 LTs = L,
326 LEs = L | EQ,
327 GTs = G,
328 GEs = G | EQ,
329 LTu = L | U,
330 LEu = L | EQ | U,
331 GTu = G | U,
332 GEu = G | EQ | U
333 };
334
335 static uint32_t negate(uint32_t Cmp) {
336 if (Cmp == EQ)
337 return NE;
338 if (Cmp == NE)
339 return EQ;
340 assert((Cmp & (L|G)) != (L|G))(static_cast <bool> ((Cmp & (L|G)) != (L|G)) ? void
(0) : __assert_fail ("(Cmp & (L|G)) != (L|G)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 340, __extension__ __PRETTY_FUNCTION__))
;
341 return Cmp ^ (L|G);
342 }
343 };
344
345 // Helper functions.
346
347 bool getCell(const Register &R, const CellMap &Inputs, LatticeCell &RC);
348 bool constToInt(const Constant *C, APInt &Val) const;
349 bool constToFloat(const Constant *C, APFloat &Val) const;
350 const ConstantInt *intToConst(const APInt &Val) const;
351
352 // Compares.
353 bool evaluateCMPrr(uint32_t Cmp, const Register &R1, const Register &R2,
354 const CellMap &Inputs, bool &Result);
355 bool evaluateCMPri(uint32_t Cmp, const Register &R1, const APInt &A2,
356 const CellMap &Inputs, bool &Result);
357 bool evaluateCMPrp(uint32_t Cmp, const Register &R1, uint64_t Props2,
358 const CellMap &Inputs, bool &Result);
359 bool evaluateCMPii(uint32_t Cmp, const APInt &A1, const APInt &A2,
360 bool &Result);
361 bool evaluateCMPpi(uint32_t Cmp, uint32_t Props, const APInt &A2,
362 bool &Result);
363 bool evaluateCMPpp(uint32_t Cmp, uint32_t Props1, uint32_t Props2,
364 bool &Result);
365
366 bool evaluateCOPY(const Register &R1, const CellMap &Inputs,
367 LatticeCell &Result);
368
369 // Logical operations.
370 bool evaluateANDrr(const Register &R1, const Register &R2,
371 const CellMap &Inputs, LatticeCell &Result);
372 bool evaluateANDri(const Register &R1, const APInt &A2,
373 const CellMap &Inputs, LatticeCell &Result);
374 bool evaluateANDii(const APInt &A1, const APInt &A2, APInt &Result);
375 bool evaluateORrr(const Register &R1, const Register &R2,
376 const CellMap &Inputs, LatticeCell &Result);
377 bool evaluateORri(const Register &R1, const APInt &A2,
378 const CellMap &Inputs, LatticeCell &Result);
379 bool evaluateORii(const APInt &A1, const APInt &A2, APInt &Result);
380 bool evaluateXORrr(const Register &R1, const Register &R2,
381 const CellMap &Inputs, LatticeCell &Result);
382 bool evaluateXORri(const Register &R1, const APInt &A2,
383 const CellMap &Inputs, LatticeCell &Result);
384 bool evaluateXORii(const APInt &A1, const APInt &A2, APInt &Result);
385
386 // Extensions.
387 bool evaluateZEXTr(const Register &R1, unsigned Width, unsigned Bits,
388 const CellMap &Inputs, LatticeCell &Result);
389 bool evaluateZEXTi(const APInt &A1, unsigned Width, unsigned Bits,
390 APInt &Result);
391 bool evaluateSEXTr(const Register &R1, unsigned Width, unsigned Bits,
392 const CellMap &Inputs, LatticeCell &Result);
393 bool evaluateSEXTi(const APInt &A1, unsigned Width, unsigned Bits,
394 APInt &Result);
395
396 // Leading/trailing bits.
397 bool evaluateCLBr(const Register &R1, bool Zeros, bool Ones,
398 const CellMap &Inputs, LatticeCell &Result);
399 bool evaluateCLBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
400 bool evaluateCTBr(const Register &R1, bool Zeros, bool Ones,
401 const CellMap &Inputs, LatticeCell &Result);
402 bool evaluateCTBi(const APInt &A1, bool Zeros, bool Ones, APInt &Result);
403
404 // Bitfield extract.
405 bool evaluateEXTRACTr(const Register &R1, unsigned Width, unsigned Bits,
406 unsigned Offset, bool Signed, const CellMap &Inputs,
407 LatticeCell &Result);
408 bool evaluateEXTRACTi(const APInt &A1, unsigned Bits, unsigned Offset,
409 bool Signed, APInt &Result);
410 // Vector operations.
411 bool evaluateSplatr(const Register &R1, unsigned Bits, unsigned Count,
412 const CellMap &Inputs, LatticeCell &Result);
413 bool evaluateSplati(const APInt &A1, unsigned Bits, unsigned Count,
414 APInt &Result);
415 };
416
417} // end anonymous namespace
418
419uint32_t ConstantProperties::deduce(const Constant *C) {
420 if (isa<ConstantInt>(C)) {
421 const ConstantInt *CI = cast<ConstantInt>(C);
422 if (CI->isZero())
423 return Zero | PosOrZero | NegOrZero | Finite;
424 uint32_t Props = (NonZero | Finite);
425 if (CI->isNegative())
426 return Props | NegOrZero;
427 return Props | PosOrZero;
428 }
429
430 if (isa<ConstantFP>(C)) {
431 const ConstantFP *CF = cast<ConstantFP>(C);
432 uint32_t Props = CF->isNegative() ? (NegOrZero|NonZero)
433 : PosOrZero;
434 if (CF->isZero())
435 return (Props & ~NumericProperties) | (Zero|Finite);
436 Props = (Props & ~NumericProperties) | NonZero;
437 if (CF->isNaN())
438 return (Props & ~NumericProperties) | NaN;
439 const APFloat &Val = CF->getValueAPF();
440 if (Val.isInfinity())
441 return (Props & ~NumericProperties) | Infinity;
442 Props |= Finite;
443 return Props;
444 }
445
446 return Unknown;
447}
448
449// Convert a cell from a set of specific values to a cell that tracks
450// properties.
451bool LatticeCell::convertToProperty() {
452 if (isProperty())
453 return false;
454 // Corner case: converting a fresh (top) cell to "special".
455 // This can happen, when adding a property to a top cell.
456 uint32_t Everything = ConstantProperties::Everything;
457 uint32_t Ps = !isTop() ? properties()
458 : Everything;
459 if (Ps != ConstantProperties::Unknown) {
460 Properties = Ps;
461 setProperty();
462 } else {
463 setBottom();
464 }
465 return true;
466}
467
468#ifndef NDEBUG
469void LatticeCell::print(raw_ostream &os) const {
470 if (isProperty()) {
471 os << "{ ";
472 uint32_t Ps = properties();
473 if (Ps & ConstantProperties::Zero)
474 os << "zero ";
475 if (Ps & ConstantProperties::NonZero)
476 os << "nonzero ";
477 if (Ps & ConstantProperties::Finite)
478 os << "finite ";
479 if (Ps & ConstantProperties::Infinity)
480 os << "infinity ";
481 if (Ps & ConstantProperties::NaN)
482 os << "nan ";
483 if (Ps & ConstantProperties::PosOrZero)
484 os << "poz ";
485 if (Ps & ConstantProperties::NegOrZero)
486 os << "nez ";
487 os << '}';
488 return;
489 }
490
491 os << "{ ";
492 if (isBottom()) {
493 os << "bottom";
494 } else if (isTop()) {
495 os << "top";
496 } else {
497 for (unsigned i = 0; i < size(); ++i) {
498 const Constant *C = Values[i];
499 if (i != 0)
500 os << ", ";
501 C->print(os);
502 }
503 }
504 os << " }";
505}
506#endif
507
508// "Meet" operation on two cells. This is the key of the propagation
509// algorithm.
510bool LatticeCell::meet(const LatticeCell &L) {
511 bool Changed = false;
512 if (L.isBottom())
513 Changed = setBottom();
514 if (isBottom() || L.isTop())
515 return Changed;
516 if (isTop()) {
517 *this = L;
518 // L can be neither Top nor Bottom, so *this must have changed.
519 return true;
520 }
521
522 // Top/bottom cases covered. Need to integrate L's set into ours.
523 if (L.isProperty())
524 return add(L.properties());
525 for (unsigned i = 0; i < L.size(); ++i) {
526 const Constant *LC = L.Values[i];
527 Changed |= add(LC);
528 }
529 return Changed;
530}
531
532// Add a new constant to the cell. This is actually where the cell update
533// happens. If a cell has room for more constants, the new constant is added.
534// Otherwise, the cell is converted to a "property" cell (i.e. a cell that
535// will track properties of the associated values, and not the values
536// themselves. Care is taken to handle special cases, like "bottom", etc.
537bool LatticeCell::add(const Constant *LC) {
538 assert(LC)(static_cast <bool> (LC) ? void (0) : __assert_fail ("LC"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 538, __extension__ __PRETTY_FUNCTION__))
;
539 if (isBottom())
540 return false;
541
542 if (!isProperty()) {
543 // Cell is not special. Try to add the constant here first,
544 // if there is room.
545 unsigned Index = 0;
546 while (Index < Size) {
547 const Constant *C = Values[Index];
548 // If the constant is already here, no change is needed.
549 if (C == LC)
550 return false;
551 Index++;
552 }
553 if (Index < MaxCellSize) {
554 Values[Index] = LC;
555 Kind = Normal;
556 Size++;
557 return true;
558 }
559 }
560
561 bool Changed = false;
562
563 // This cell is special, or is not special, but is full. After this
564 // it will be special.
565 Changed = convertToProperty();
566 uint32_t Ps = properties();
567 uint32_t NewPs = Ps & ConstantProperties::deduce(LC);
568 if (NewPs == ConstantProperties::Unknown) {
569 setBottom();
570 return true;
571 }
572 if (Ps != NewPs) {
573 Properties = NewPs;
574 Changed = true;
575 }
576 return Changed;
577}
578
579// Add a property to the cell. This will force the cell to become a property-
580// tracking cell.
581bool LatticeCell::add(uint32_t Property) {
582 bool Changed = convertToProperty();
583 uint32_t Ps = properties();
584 if (Ps == (Ps & Property))
585 return Changed;
586 Properties = Property & Ps;
587 return true;
588}
589
590// Return the properties of the values in the cell. This is valid for any
591// cell, and does not alter the cell itself.
592uint32_t LatticeCell::properties() const {
593 if (isProperty())
594 return Properties;
595 assert(!isTop() && "Should not call this for a top cell")(static_cast <bool> (!isTop() && "Should not call this for a top cell"
) ? void (0) : __assert_fail ("!isTop() && \"Should not call this for a top cell\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 595, __extension__ __PRETTY_FUNCTION__))
;
596 if (isBottom())
597 return ConstantProperties::Unknown;
598
599 assert(size() > 0 && "Empty cell")(static_cast <bool> (size() > 0 && "Empty cell"
) ? void (0) : __assert_fail ("size() > 0 && \"Empty cell\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 599, __extension__ __PRETTY_FUNCTION__))
;
600 uint32_t Ps = ConstantProperties::deduce(Values[0]);
601 for (unsigned i = 1; i < size(); ++i) {
602 if (Ps == ConstantProperties::Unknown)
603 break;
604 Ps &= ConstantProperties::deduce(Values[i]);
605 }
606 return Ps;
607}
608
609#ifndef NDEBUG
610void MachineConstPropagator::CellMap::print(raw_ostream &os,
611 const TargetRegisterInfo &TRI) const {
612 for (auto &I : Map)
613 dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
614}
615#endif
616
617void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
618 const MachineBasicBlock *MB = PN.getParent();
619 unsigned MBN = MB->getNumber();
620 DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting FI(" << printMBBReference
(*MB) << "): " << PN; } } while (false)
;
621
622 const MachineOperand &MD = PN.getOperand(0);
623 Register DefR(MD);
624 assert(TargetRegisterInfo::isVirtualRegister(DefR.Reg))(static_cast <bool> (TargetRegisterInfo::isVirtualRegister
(DefR.Reg)) ? void (0) : __assert_fail ("TargetRegisterInfo::isVirtualRegister(DefR.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 624, __extension__ __PRETTY_FUNCTION__))
;
625
626 bool Changed = false;
627
628 // If the def has a sub-register, set the corresponding cell to "bottom".
629 if (DefR.SubReg) {
630Bottomize:
631 const LatticeCell &T = Cells.get(DefR.Reg);
632 Changed = !T.isBottom();
633 Cells.update(DefR.Reg, Bottom);
634 if (Changed)
635 visitUsesOf(DefR.Reg);
636 return;
637 }
638
639 LatticeCell DefC = Cells.get(DefR.Reg);
640
641 for (unsigned i = 1, n = PN.getNumOperands(); i < n; i += 2) {
642 const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB();
643 unsigned PBN = PB->getNumber();
644 if (!EdgeExec.count(CFGEdge(PBN, MBN))) {
645 DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " edge " << printMBBReference
(*PB) << "->" << printMBBReference(*MB) <<
" not executable\n"; } } while (false)
646 << printMBBReference(*MB) << " not executable\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " edge " << printMBBReference
(*PB) << "->" << printMBBReference(*MB) <<
" not executable\n"; } } while (false)
;
647 continue;
648 }
649 const MachineOperand &SO = PN.getOperand(i);
650 Register UseR(SO);
651 // If the input is not a virtual register, we don't really know what
652 // value it holds.
653 if (!TargetRegisterInfo::isVirtualRegister(UseR.Reg))
654 goto Bottomize;
655 // If there is no cell for an input register, it means top.
656 if (!Cells.has(UseR.Reg))
657 continue;
658
659 LatticeCell SrcC;
660 bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
661 DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " edge from " << printMBBReference
(*PB) << ": " << printReg(UseR.Reg, &MCE.TRI,
UseR.SubReg) << SrcC << '\n'; } } while (false)
662 << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " edge from " << printMBBReference
(*PB) << ": " << printReg(UseR.Reg, &MCE.TRI,
UseR.SubReg) << SrcC << '\n'; } } while (false)
;
663 Changed |= Eval ? DefC.meet(SrcC)
664 : DefC.setBottom();
665 Cells.update(DefR.Reg, DefC);
666 if (DefC.isBottom())
667 break;
668 }
669 if (Changed)
670 visitUsesOf(DefR.Reg);
671}
672
673void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
674 DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting MI(" << printMBBReference
(*MI.getParent()) << "): " << MI; } } while (false
)
675 << "): " << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting MI(" << printMBBReference
(*MI.getParent()) << "): " << MI; } } while (false
)
;
676 CellMap Outputs;
677 bool Eval = MCE.evaluate(MI, Cells, Outputs);
678 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
679 if (Eval) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
680 dbgs() << " outputs:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
681 for (auto &I : Outputs)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
682 dbgs() << ' ' << I.second;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
683 dbgs() << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
684 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
685 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (Eval) { dbgs() << " outputs:"; for (auto
&I : Outputs) dbgs() << ' ' << I.second; dbgs
() << '\n'; } }; } } while (false)
;
686
687 // Update outputs. If the value was not computed, set all the
688 // def cells to bottom.
689 for (const MachineOperand &MO : MI.operands()) {
690 if (!MO.isReg() || !MO.isDef())
691 continue;
692 Register DefR(MO);
693 // Only track virtual registers.
694 if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg))
695 continue;
696 bool Changed = false;
697 // If the evaluation failed, set cells for all output registers to bottom.
698 if (!Eval) {
699 const LatticeCell &T = Cells.get(DefR.Reg);
700 Changed = !T.isBottom();
701 Cells.update(DefR.Reg, Bottom);
702 } else {
703 // Find the corresponding cell in the computed outputs.
704 // If it's not there, go on to the next def.
705 if (!Outputs.has(DefR.Reg))
706 continue;
707 LatticeCell RC = Cells.get(DefR.Reg);
708 Changed = RC.meet(Outputs.get(DefR.Reg));
709 Cells.update(DefR.Reg, RC);
710 }
711 if (Changed)
712 visitUsesOf(DefR.Reg);
713 }
714}
715
716// \brief Starting at a given branch, visit remaining branches in the block.
717// Traverse over the subsequent branches for as long as the preceding one
718// can fall through. Add all the possible targets to the flow work queue,
719// including the potential fall-through to the layout-successor block.
720void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
721 const MachineBasicBlock &B = *BrI.getParent();
722 unsigned MBN = B.getNumber();
723 MachineBasicBlock::const_iterator It = BrI.getIterator();
724 MachineBasicBlock::const_iterator End = B.end();
725
726 SetVector<const MachineBasicBlock*> Targets;
727 bool EvalOk = true, FallsThru = true;
728 while (It != End) {
729 const MachineInstr &MI = *It;
730 InstrExec.insert(&MI);
731 DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "("do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting " << (EvalOk ? "BR"
: "br") << "(" << printMBBReference(B) << "): "
<< MI; } } while (false)
732 << printMBBReference(B) << "): " << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting " << (EvalOk ? "BR"
: "br") << "(" << printMBBReference(B) << "): "
<< MI; } } while (false)
;
733 // Do not evaluate subsequent branches if the evaluation of any of the
734 // previous branches failed. Keep iterating over the branches only
735 // to mark them as executable.
736 EvalOk = EvalOk && MCE.evaluate(MI, Cells, Targets, FallsThru);
737 if (!EvalOk)
738 FallsThru = true;
739 if (!FallsThru)
740 break;
741 ++It;
742 }
743
744 if (EvalOk) {
745 // Need to add all CFG successors that lead to EH landing pads.
746 // There won't be explicit branches to these blocks, but they must
747 // be processed.
748 for (const MachineBasicBlock *SB : B.successors()) {
749 if (SB->isEHPad())
750 Targets.insert(SB);
751 }
752 if (FallsThru) {
753 const MachineFunction &MF = *B.getParent();
754 MachineFunction::const_iterator BI = B.getIterator();
755 MachineFunction::const_iterator Next = std::next(BI);
756 if (Next != MF.end())
757 Targets.insert(&*Next);
758 }
759 } else {
760 // If the evaluation of the branches failed, make "Targets" to be the
761 // set of all successors of the block from the CFG.
762 // If the evaluation succeeded for all visited branches, then if the
763 // last one set "FallsThru", then add an edge to the layout successor
764 // to the targets.
765 Targets.clear();
766 DEBUG(dbgs() << " failed to evaluate a branch...adding all CFG "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " failed to evaluate a branch...adding all CFG "
"successors\n"; } } while (false)
767 "successors\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " failed to evaluate a branch...adding all CFG "
"successors\n"; } } while (false)
;
768 for (const MachineBasicBlock *SB : B.successors())
769 Targets.insert(SB);
770 }
771
772 for (const MachineBasicBlock *TB : Targets) {
773 unsigned TBN = TB->getNumber();
774 DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " pushing edge " << printMBBReference
(B) << " -> " << printMBBReference(*TB) <<
"\n"; } } while (false)
775 << printMBBReference(*TB) << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << " pushing edge " << printMBBReference
(B) << " -> " << printMBBReference(*TB) <<
"\n"; } } while (false)
;
776 FlowQ.push(CFGEdge(MBN, TBN));
777 }
778}
779
780void MachineConstPropagator::visitUsesOf(unsigned Reg) {
781 DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting uses of " << printReg
(Reg, &MCE.TRI) << Cells.get(Reg) << '\n'; } }
while (false)
782 << Cells.get(Reg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Visiting uses of " << printReg
(Reg, &MCE.TRI) << Cells.get(Reg) << '\n'; } }
while (false)
;
783 for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
784 // Do not process non-executable instructions. They can become exceutable
785 // later (via a flow-edge in the work queue). In such case, the instruc-
786 // tion will be visited at that time.
787 if (!InstrExec.count(&MI))
788 continue;
789 if (MI.isPHI())
790 visitPHI(MI);
791 else if (!MI.isBranch())
792 visitNonBranch(MI);
793 else
794 visitBranchesFrom(MI);
795 }
796}
797
798bool MachineConstPropagator::computeBlockSuccessors(const MachineBasicBlock *MB,
799 SetVector<const MachineBasicBlock*> &Targets) {
800 MachineBasicBlock::const_iterator FirstBr = MB->end();
801 for (const MachineInstr &MI : *MB) {
802 if (MI.isDebugValue())
803 continue;
804 if (MI.isBranch()) {
805 FirstBr = MI.getIterator();
806 break;
807 }
808 }
809
810 Targets.clear();
811 MachineBasicBlock::const_iterator End = MB->end();
812
813 bool DoNext = true;
814 for (MachineBasicBlock::const_iterator I = FirstBr; I != End; ++I) {
815 const MachineInstr &MI = *I;
816 // Can there be debug instructions between branches?
817 if (MI.isDebugValue())
818 continue;
819 if (!InstrExec.count(&MI))
820 continue;
821 bool Eval = MCE.evaluate(MI, Cells, Targets, DoNext);
822 if (!Eval)
823 return false;
824 if (!DoNext)
825 break;
826 }
827 // If the last branch could fall-through, add block's layout successor.
828 if (DoNext) {
829 MachineFunction::const_iterator BI = MB->getIterator();
830 MachineFunction::const_iterator NextI = std::next(BI);
831 if (NextI != MB->getParent()->end())
832 Targets.insert(&*NextI);
833 }
834
835 // Add all the EH landing pads.
836 for (const MachineBasicBlock *SB : MB->successors())
837 if (SB->isEHPad())
838 Targets.insert(SB);
839
840 return true;
841}
842
843void MachineConstPropagator::removeCFGEdge(MachineBasicBlock *From,
844 MachineBasicBlock *To) {
845 // First, remove the CFG successor/predecessor information.
846 From->removeSuccessor(To);
847 // Remove all corresponding PHI operands in the To block.
848 for (auto I = To->begin(), E = To->getFirstNonPHI(); I != E; ++I) {
849 MachineInstr *PN = &*I;
850 // reg0 = PHI reg1, bb2, reg3, bb4, ...
851 int N = PN->getNumOperands()-2;
852 while (N > 0) {
853 if (PN->getOperand(N+1).getMBB() == From) {
854 PN->RemoveOperand(N+1);
855 PN->RemoveOperand(N);
856 }
857 N -= 2;
858 }
859 }
860}
861
862void MachineConstPropagator::propagate(MachineFunction &MF) {
863 MachineBasicBlock *Entry = GraphTraits<MachineFunction*>::getEntryNode(&MF);
864 unsigned EntryNum = Entry->getNumber();
865
866 // Start with a fake edge, just to process the entry node.
867 FlowQ.push(CFGEdge(EntryNum, EntryNum));
868
869 while (!FlowQ.empty()) {
870 CFGEdge Edge = FlowQ.front();
871 FlowQ.pop();
872
873 DEBUG(dbgs() << "Picked edge "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Picked edge " << printMBBReference
(*MF.getBlockNumbered(Edge.first)) << "->" << printMBBReference
(*MF.getBlockNumbered(Edge.second)) << '\n'; } } while (
false)
874 << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Picked edge " << printMBBReference
(*MF.getBlockNumbered(Edge.first)) << "->" << printMBBReference
(*MF.getBlockNumbered(Edge.second)) << '\n'; } } while (
false)
875 << printMBBReference(*MF.getBlockNumbered(Edge.second))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Picked edge " << printMBBReference
(*MF.getBlockNumbered(Edge.first)) << "->" << printMBBReference
(*MF.getBlockNumbered(Edge.second)) << '\n'; } } while (
false)
876 << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Picked edge " << printMBBReference
(*MF.getBlockNumbered(Edge.first)) << "->" << printMBBReference
(*MF.getBlockNumbered(Edge.second)) << '\n'; } } while (
false)
;
877 if (Edge.first != EntryNum)
878 if (EdgeExec.count(Edge))
879 continue;
880 EdgeExec.insert(Edge);
881 MachineBasicBlock *SB = MF.getBlockNumbered(Edge.second);
882
883 // Process the block in three stages:
884 // - visit all PHI nodes,
885 // - visit all non-branch instructions,
886 // - visit block branches.
887 MachineBasicBlock::const_iterator It = SB->begin(), End = SB->end();
888
889 // Visit PHI nodes in the successor block.
890 while (It != End && It->isPHI()) {
891 InstrExec.insert(&*It);
892 visitPHI(*It);
893 ++It;
894 }
895
896 // If the successor block just became executable, visit all instructions.
897 // To see if this is the first time we're visiting it, check the first
898 // non-debug instruction to see if it is executable.
899 while (It != End && It->isDebugValue())
900 ++It;
901 assert(It == End || !It->isPHI())(static_cast <bool> (It == End || !It->isPHI()) ? void
(0) : __assert_fail ("It == End || !It->isPHI()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 901, __extension__ __PRETTY_FUNCTION__))
;
902 // If this block has been visited, go on to the next one.
903 if (It != End && InstrExec.count(&*It))
904 continue;
905 // For now, scan all non-branch instructions. Branches require different
906 // processing.
907 while (It != End && !It->isBranch()) {
908 if (!It->isDebugValue()) {
909 InstrExec.insert(&*It);
910 visitNonBranch(*It);
911 }
912 ++It;
913 }
914
915 // Time to process the end of the block. This is different from
916 // processing regular (non-branch) instructions, because there can
917 // be multiple branches in a block, and they can cause the block to
918 // terminate early.
919 if (It != End) {
920 visitBranchesFrom(*It);
921 } else {
922 // If the block didn't have a branch, add all successor edges to the
923 // work queue. (There should really be only one successor in such case.)
924 unsigned SBN = SB->getNumber();
925 for (const MachineBasicBlock *SSB : SB->successors())
926 FlowQ.push(CFGEdge(SBN, SSB->getNumber()));
927 }
928 } // while (FlowQ)
929
930 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
931 dbgs() << "Cells after propagation:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
932 Cells.print(dbgs(), MCE.TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
933 dbgs() << "Dead CFG edges:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
934 for (const MachineBasicBlock &B : MF) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
935 unsigned BN = B.getNumber();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
936 for (const MachineBasicBlock *SB : B.successors()) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
937 unsigned SN = SB->getNumber();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
938 if (!EdgeExec.count(CFGEdge(BN, SN)))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
939 dbgs() << " " << printMBBReference(B) << " -> "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
940 << printMBBReference(*SB) << '\n';do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
941 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
942 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
943 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "Cells after propagation:\n"; Cells
.print(dbgs(), MCE.TRI); dbgs() << "Dead CFG edges:\n";
for (const MachineBasicBlock &B : MF) { unsigned BN = B.
getNumber(); for (const MachineBasicBlock *SB : B.successors(
)) { unsigned SN = SB->getNumber(); if (!EdgeExec.count(CFGEdge
(BN, SN))) dbgs() << " " << printMBBReference(B)
<< " -> " << printMBBReference(*SB) << '\n'
; } } }; } } while (false)
;
944}
945
946bool MachineConstPropagator::rewrite(MachineFunction &MF) {
947 bool Changed = false;
948 // Rewrite all instructions based on the collected cell information.
949 //
950 // Traverse the instructions in a post-order, so that rewriting an
951 // instruction can make changes "downstream" in terms of control-flow
952 // without affecting the rewriting process. (We should not change
953 // instructions that have not yet been visited by the rewriter.)
954 // The reason for this is that the rewriter can introduce new vregs,
955 // and replace uses of old vregs (which had corresponding cells
956 // computed during propagation) with these new vregs (which at this
957 // point would not have any cells, and would appear to be "top").
958 // If an attempt was made to evaluate an instruction with a fresh
959 // "top" vreg, it would cause an error (abend) in the evaluator.
960
961 // Collect the post-order-traversal block ordering. The subsequent
962 // traversal/rewrite will update block successors, so it's safer
963 // if the visiting order it computed ahead of time.
964 std::vector<MachineBasicBlock*> POT;
965 for (MachineBasicBlock *B : post_order(&MF))
966 if (!B->empty())
967 POT.push_back(B);
968
969 for (MachineBasicBlock *B : POT) {
970 // Walk the block backwards (which usually begin with the branches).
971 // If any branch is rewritten, we may need to update the successor
972 // information for this block. Unless the block's successors can be
973 // precisely determined (which may not be the case for indirect
974 // branches), we cannot modify any branch.
975
976 // Compute the successor information.
977 SetVector<const MachineBasicBlock*> Targets;
978 bool HaveTargets = computeBlockSuccessors(B, Targets);
979 // Rewrite the executable instructions. Skip branches if we don't
980 // have block successor information.
981 for (auto I = B->rbegin(), E = B->rend(); I != E; ++I) {
982 MachineInstr &MI = *I;
983 if (InstrExec.count(&MI)) {
984 if (MI.isBranch() && !HaveTargets)
985 continue;
986 Changed |= MCE.rewrite(MI, Cells);
987 }
988 }
989 // The rewriting could rewrite PHI nodes to non-PHI nodes, causing
990 // regular instructions to appear in between PHI nodes. Bring all
991 // the PHI nodes to the beginning of the block.
992 for (auto I = B->begin(), E = B->end(); I != E; ++I) {
993 if (I->isPHI())
994 continue;
995 // I is not PHI. Find the next PHI node P.
996 auto P = I;
997 while (++P != E)
998 if (P->isPHI())
999 break;
1000 // Not found.
1001 if (P == E)
1002 break;
1003 // Splice P right before I.
1004 B->splice(I, B, P);
1005 // Reset I to point at the just spliced PHI node.
1006 --I;
1007 }
1008 // Update the block successor information: remove unnecessary successors.
1009 if (HaveTargets) {
1010 SmallVector<MachineBasicBlock*,2> ToRemove;
1011 for (MachineBasicBlock *SB : B->successors()) {
1012 if (!Targets.count(SB))
1013 ToRemove.push_back(const_cast<MachineBasicBlock*>(SB));
1014 Targets.remove(SB);
1015 }
1016 for (unsigned i = 0, n = ToRemove.size(); i < n; ++i)
1017 removeCFGEdge(B, ToRemove[i]);
1018 // If there are any blocks left in the computed targets, it means that
1019 // we think that the block could go somewhere, but the CFG does not.
1020 // This could legitimately happen in blocks that have non-returning
1021 // calls---we would think that the execution can continue, but the
1022 // CFG will not have a successor edge.
1023 }
1024 }
1025 // Need to do some final post-processing.
1026 // If a branch was not executable, it will not get rewritten, but should
1027 // be removed (or replaced with something equivalent to a A2_nop). We can't
1028 // erase instructions during rewriting, so this needs to be delayed until
1029 // now.
1030 for (MachineBasicBlock &B : MF) {
1031 MachineBasicBlock::iterator I = B.begin(), E = B.end();
1032 while (I != E) {
1033 auto Next = std::next(I);
1034 if (I->isBranch() && !InstrExec.count(&*I))
1035 B.erase(I);
1036 I = Next;
1037 }
1038 }
1039 return Changed;
1040}
1041
1042// This is the constant propagation algorithm as described by Wegman-Zadeck.
1043// Most of the terminology comes from there.
1044bool MachineConstPropagator::run(MachineFunction &MF) {
1045 DEBUG(MF.print(dbgs() << "Starting MachineConstPropagator\n", nullptr))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { MF.print(dbgs() << "Starting MachineConstPropagator\n"
, nullptr); } } while (false)
;
1046
1047 MRI = &MF.getRegInfo();
1048
1049 Cells.clear();
1050 EdgeExec.clear();
1051 InstrExec.clear();
1052 assert(FlowQ.empty())(static_cast <bool> (FlowQ.empty()) ? void (0) : __assert_fail
("FlowQ.empty()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1052, __extension__ __PRETTY_FUNCTION__))
;
1053
1054 propagate(MF);
1055 bool Changed = rewrite(MF);
1056
1057 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "End of MachineConstPropagator (Changed="
<< Changed << ")\n"; if (Changed) MF.print(dbgs(
), nullptr); }; } } while (false)
1058 dbgs() << "End of MachineConstPropagator (Changed=" << Changed << ")\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "End of MachineConstPropagator (Changed="
<< Changed << ")\n"; if (Changed) MF.print(dbgs(
), nullptr); }; } } while (false)
1059 if (Changed)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "End of MachineConstPropagator (Changed="
<< Changed << ")\n"; if (Changed) MF.print(dbgs(
), nullptr); }; } } while (false)
1060 MF.print(dbgs(), nullptr);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "End of MachineConstPropagator (Changed="
<< Changed << ")\n"; if (Changed) MF.print(dbgs(
), nullptr); }; } } while (false)
1061 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { dbgs() << "End of MachineConstPropagator (Changed="
<< Changed << ")\n"; if (Changed) MF.print(dbgs(
), nullptr); }; } } while (false)
;
1062 return Changed;
1063}
1064
1065// --------------------------------------------------------------------
1066// Machine const evaluator.
1067
1068bool MachineConstEvaluator::getCell(const Register &R, const CellMap &Inputs,
1069 LatticeCell &RC) {
1070 if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
1071 return false;
1072 const LatticeCell &L = Inputs.get(R.Reg);
1073 if (!R.SubReg) {
1074 RC = L;
1075 return !RC.isBottom();
1076 }
1077 bool Eval = evaluate(R, L, RC);
1078 return Eval && !RC.isBottom();
1079}
1080
1081bool MachineConstEvaluator::constToInt(const Constant *C,
1082 APInt &Val) const {
1083 const ConstantInt *CI = dyn_cast<ConstantInt>(C);
1084 if (!CI)
1085 return false;
1086 Val = CI->getValue();
1087 return true;
1088}
1089
1090const ConstantInt *MachineConstEvaluator::intToConst(const APInt &Val) const {
1091 return ConstantInt::get(CX, Val);
1092}
1093
1094bool MachineConstEvaluator::evaluateCMPrr(uint32_t Cmp, const Register &R1,
1095 const Register &R2, const CellMap &Inputs, bool &Result) {
1096 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg))(static_cast <bool> (Inputs.has(R1.Reg) && Inputs
.has(R2.Reg)) ? void (0) : __assert_fail ("Inputs.has(R1.Reg) && Inputs.has(R2.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1096, __extension__ __PRETTY_FUNCTION__))
;
1097 LatticeCell LS1, LS2;
1098 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
1099 return false;
1100
1101 bool IsProp1 = LS1.isProperty();
1102 bool IsProp2 = LS2.isProperty();
1103 if (IsProp1) {
1104 uint32_t Prop1 = LS1.properties();
1105 if (IsProp2)
1106 return evaluateCMPpp(Cmp, Prop1, LS2.properties(), Result);
1107 uint32_t NegCmp = Comparison::negate(Cmp);
1108 return evaluateCMPrp(NegCmp, R2, Prop1, Inputs, Result);
1109 }
1110 if (IsProp2) {
1111 uint32_t Prop2 = LS2.properties();
1112 return evaluateCMPrp(Cmp, R1, Prop2, Inputs, Result);
1113 }
1114
1115 APInt A;
1116 bool IsTrue = true, IsFalse = true;
1117 for (unsigned i = 0; i < LS2.size(); ++i) {
1118 bool Res;
1119 bool Computed = constToInt(LS2.Values[i], A) &&
1120 evaluateCMPri(Cmp, R1, A, Inputs, Res);
1121 if (!Computed)
1122 return false;
1123 IsTrue &= Res;
1124 IsFalse &= !Res;
1125 }
1126 assert(!IsTrue || !IsFalse)(static_cast <bool> (!IsTrue || !IsFalse) ? void (0) : __assert_fail
("!IsTrue || !IsFalse", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1126, __extension__ __PRETTY_FUNCTION__))
;
1127 // The actual logical value of the comparison is same as IsTrue.
1128 Result = IsTrue;
1129 // Return true if the result was proven to be true or proven to be false.
1130 return IsTrue || IsFalse;
1131}
1132
1133bool MachineConstEvaluator::evaluateCMPri(uint32_t Cmp, const Register &R1,
1134 const APInt &A2, const CellMap &Inputs, bool &Result) {
1135 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1135, __extension__ __PRETTY_FUNCTION__))
;
1136 LatticeCell LS;
1137 if (!getCell(R1, Inputs, LS))
1138 return false;
1139 if (LS.isProperty())
1140 return evaluateCMPpi(Cmp, LS.properties(), A2, Result);
1141
1142 APInt A;
1143 bool IsTrue = true, IsFalse = true;
1144 for (unsigned i = 0; i < LS.size(); ++i) {
1145 bool Res;
1146 bool Computed = constToInt(LS.Values[i], A) &&
1147 evaluateCMPii(Cmp, A, A2, Res);
1148 if (!Computed)
1149 return false;
1150 IsTrue &= Res;
1151 IsFalse &= !Res;
1152 }
1153 assert(!IsTrue || !IsFalse)(static_cast <bool> (!IsTrue || !IsFalse) ? void (0) : __assert_fail
("!IsTrue || !IsFalse", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1153, __extension__ __PRETTY_FUNCTION__))
;
1154 // The actual logical value of the comparison is same as IsTrue.
1155 Result = IsTrue;
1156 // Return true if the result was proven to be true or proven to be false.
1157 return IsTrue || IsFalse;
1158}
1159
1160bool MachineConstEvaluator::evaluateCMPrp(uint32_t Cmp, const Register &R1,
1161 uint64_t Props2, const CellMap &Inputs, bool &Result) {
1162 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1162, __extension__ __PRETTY_FUNCTION__))
;
1163 LatticeCell LS;
1164 if (!getCell(R1, Inputs, LS))
1165 return false;
1166 if (LS.isProperty())
1167 return evaluateCMPpp(Cmp, LS.properties(), Props2, Result);
1168
1169 APInt A;
1170 uint32_t NegCmp = Comparison::negate(Cmp);
1171 bool IsTrue = true, IsFalse = true;
1172 for (unsigned i = 0; i < LS.size(); ++i) {
1173 bool Res;
1174 bool Computed = constToInt(LS.Values[i], A) &&
1175 evaluateCMPpi(NegCmp, Props2, A, Res);
1176 if (!Computed)
1177 return false;
1178 IsTrue &= Res;
1179 IsFalse &= !Res;
1180 }
1181 assert(!IsTrue || !IsFalse)(static_cast <bool> (!IsTrue || !IsFalse) ? void (0) : __assert_fail
("!IsTrue || !IsFalse", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1181, __extension__ __PRETTY_FUNCTION__))
;
1182 Result = IsTrue;
1183 return IsTrue || IsFalse;
1184}
1185
1186bool MachineConstEvaluator::evaluateCMPii(uint32_t Cmp, const APInt &A1,
1187 const APInt &A2, bool &Result) {
1188 // NE is a special kind of comparison (not composed of smaller properties).
1189 if (Cmp == Comparison::NE) {
1190 Result = !APInt::isSameValue(A1, A2);
1191 return true;
1192 }
1193 if (Cmp == Comparison::EQ) {
1194 Result = APInt::isSameValue(A1, A2);
1195 return true;
1196 }
1197 if (Cmp & Comparison::EQ) {
1198 if (APInt::isSameValue(A1, A2))
1199 return (Result = true);
1200 }
1201 assert((Cmp & (Comparison::L | Comparison::G)) && "Malformed comparison")(static_cast <bool> ((Cmp & (Comparison::L | Comparison
::G)) && "Malformed comparison") ? void (0) : __assert_fail
("(Cmp & (Comparison::L | Comparison::G)) && \"Malformed comparison\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1201, __extension__ __PRETTY_FUNCTION__))
;
1202 Result = false;
1203
1204 unsigned W1 = A1.getBitWidth();
1205 unsigned W2 = A2.getBitWidth();
1206 unsigned MaxW = (W1 >= W2) ? W1 : W2;
1207 if (Cmp & Comparison::U) {
1208 const APInt Zx1 = A1.zextOrSelf(MaxW);
1209 const APInt Zx2 = A2.zextOrSelf(MaxW);
1210 if (Cmp & Comparison::L)
1211 Result = Zx1.ult(Zx2);
1212 else if (Cmp & Comparison::G)
1213 Result = Zx2.ult(Zx1);
1214 return true;
1215 }
1216
1217 // Signed comparison.
1218 const APInt Sx1 = A1.sextOrSelf(MaxW);
1219 const APInt Sx2 = A2.sextOrSelf(MaxW);
1220 if (Cmp & Comparison::L)
1221 Result = Sx1.slt(Sx2);
1222 else if (Cmp & Comparison::G)
1223 Result = Sx2.slt(Sx1);
1224 return true;
1225}
1226
1227bool MachineConstEvaluator::evaluateCMPpi(uint32_t Cmp, uint32_t Props,
1228 const APInt &A2, bool &Result) {
1229 if (Props == ConstantProperties::Unknown)
1230 return false;
1231
1232 // Should never see NaN here, but check for it for completeness.
1233 if (Props & ConstantProperties::NaN)
1234 return false;
1235 // Infinity could theoretically be compared to a number, but the
1236 // presence of infinity here would be very suspicious. If we don't
1237 // know for sure that the number is finite, bail out.
1238 if (!(Props & ConstantProperties::Finite))
1239 return false;
1240
1241 // Let X be a number that has properties Props.
1242
1243 if (Cmp & Comparison::U) {
1244 // In case of unsigned comparisons, we can only compare against 0.
1245 if (A2 == 0) {
1246 // Any x!=0 will be considered >0 in an unsigned comparison.
1247 if (Props & ConstantProperties::Zero)
1248 Result = (Cmp & Comparison::EQ);
1249 else if (Props & ConstantProperties::NonZero)
1250 Result = (Cmp & Comparison::G) || (Cmp == Comparison::NE);
1251 else
1252 return false;
1253 return true;
1254 }
1255 // A2 is not zero. The only handled case is if X = 0.
1256 if (Props & ConstantProperties::Zero) {
1257 Result = (Cmp & Comparison::L) || (Cmp == Comparison::NE);
1258 return true;
1259 }
1260 return false;
1261 }
1262
1263 // Signed comparisons are different.
1264 if (Props & ConstantProperties::Zero) {
1265 if (A2 == 0)
1266 Result = (Cmp & Comparison::EQ);
1267 else
1268 Result = (Cmp == Comparison::NE) ||
1269 ((Cmp & Comparison::L) && !A2.isNegative()) ||
1270 ((Cmp & Comparison::G) && A2.isNegative());
1271 return true;
1272 }
1273 if (Props & ConstantProperties::PosOrZero) {
1274 // X >= 0 and !(A2 < 0) => cannot compare
1275 if (!A2.isNegative())
1276 return false;
1277 // X >= 0 and A2 < 0
1278 Result = (Cmp & Comparison::G) || (Cmp == Comparison::NE);
1279 return true;
1280 }
1281 if (Props & ConstantProperties::NegOrZero) {
1282 // X <= 0 and Src1 < 0 => cannot compare
1283 if (A2 == 0 || A2.isNegative())
1284 return false;
1285 // X <= 0 and A2 > 0
1286 Result = (Cmp & Comparison::L) || (Cmp == Comparison::NE);
1287 return true;
1288 }
1289
1290 return false;
1291}
1292
1293bool MachineConstEvaluator::evaluateCMPpp(uint32_t Cmp, uint32_t Props1,
1294 uint32_t Props2, bool &Result) {
1295 using P = ConstantProperties;
1296
1297 if ((Props1 & P::NaN) && (Props2 & P::NaN))
1298 return false;
1299 if (!(Props1 & P::Finite) || !(Props2 & P::Finite))
1300 return false;
1301
1302 bool Zero1 = (Props1 & P::Zero), Zero2 = (Props2 & P::Zero);
1303 bool NonZero1 = (Props1 & P::NonZero), NonZero2 = (Props2 & P::NonZero);
1304 if (Zero1 && Zero2) {
1305 Result = (Cmp & Comparison::EQ);
1306 return true;
1307 }
1308 if (Cmp == Comparison::NE) {
1309 if ((Zero1 && NonZero2) || (NonZero1 && Zero2))
1310 return (Result = true);
1311 return false;
1312 }
1313
1314 if (Cmp & Comparison::U) {
1315 // In unsigned comparisons, we can only compare against a known zero,
1316 // or a known non-zero.
1317 if (Zero1 && NonZero2) {
1318 Result = (Cmp & Comparison::L);
1319 return true;
1320 }
1321 if (NonZero1 && Zero2) {
1322 Result = (Cmp & Comparison::G);
1323 return true;
1324 }
1325 return false;
1326 }
1327
1328 // Signed comparison. The comparison is not NE.
1329 bool Poz1 = (Props1 & P::PosOrZero), Poz2 = (Props2 & P::PosOrZero);
1330 bool Nez1 = (Props1 & P::NegOrZero), Nez2 = (Props2 & P::NegOrZero);
1331 if (Nez1 && Poz2) {
1332 if (NonZero1 || NonZero2) {
1333 Result = (Cmp & Comparison::L);
1334 return true;
1335 }
1336 // Either (or both) could be zero. Can only say that X <= Y.
1337 if ((Cmp & Comparison::EQ) && (Cmp & Comparison::L))
1338 return (Result = true);
1339 }
1340 if (Poz1 && Nez2) {
1341 if (NonZero1 || NonZero2) {
1342 Result = (Cmp & Comparison::G);
1343 return true;
1344 }
1345 // Either (or both) could be zero. Can only say that X >= Y.
1346 if ((Cmp & Comparison::EQ) && (Cmp & Comparison::G))
1347 return (Result = true);
1348 }
1349
1350 return false;
1351}
1352
1353bool MachineConstEvaluator::evaluateCOPY(const Register &R1,
1354 const CellMap &Inputs, LatticeCell &Result) {
1355 return getCell(R1, Inputs, Result);
1356}
1357
1358bool MachineConstEvaluator::evaluateANDrr(const Register &R1,
1359 const Register &R2, const CellMap &Inputs, LatticeCell &Result) {
1360 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg))(static_cast <bool> (Inputs.has(R1.Reg) && Inputs
.has(R2.Reg)) ? void (0) : __assert_fail ("Inputs.has(R1.Reg) && Inputs.has(R2.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1360, __extension__ __PRETTY_FUNCTION__))
;
1361 const LatticeCell &L1 = Inputs.get(R2.Reg);
1362 const LatticeCell &L2 = Inputs.get(R2.Reg);
1363 // If both sources are bottom, exit. Otherwise try to evaluate ANDri
1364 // with the non-bottom argument passed as the immediate. This is to
1365 // catch cases of ANDing with 0.
1366 if (L2.isBottom()) {
1367 if (L1.isBottom())
1368 return false;
1369 return evaluateANDrr(R2, R1, Inputs, Result);
1370 }
1371 LatticeCell LS2;
1372 if (!evaluate(R2, L2, LS2))
1373 return false;
1374 if (LS2.isBottom() || LS2.isProperty())
1375 return false;
1376
1377 APInt A;
1378 for (unsigned i = 0; i < LS2.size(); ++i) {
1379 LatticeCell RC;
1380 bool Eval = constToInt(LS2.Values[i], A) &&
1381 evaluateANDri(R1, A, Inputs, RC);
1382 if (!Eval)
1383 return false;
1384 Result.meet(RC);
1385 }
1386 return !Result.isBottom();
1387}
1388
1389bool MachineConstEvaluator::evaluateANDri(const Register &R1,
1390 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
1391 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1391, __extension__ __PRETTY_FUNCTION__))
;
1392 if (A2 == -1)
1393 return getCell(R1, Inputs, Result);
1394 if (A2 == 0) {
1395 LatticeCell RC;
1396 RC.add(intToConst(A2));
1397 // Overwrite Result.
1398 Result = RC;
1399 return true;
1400 }
1401 LatticeCell LS1;
1402 if (!getCell(R1, Inputs, LS1))
1403 return false;
1404 if (LS1.isBottom() || LS1.isProperty())
1405 return false;
1406
1407 APInt A, ResA;
1408 for (unsigned i = 0; i < LS1.size(); ++i) {
1409 bool Eval = constToInt(LS1.Values[i], A) &&
1410 evaluateANDii(A, A2, ResA);
1411 if (!Eval)
1412 return false;
1413 const Constant *C = intToConst(ResA);
1414 Result.add(C);
1415 }
1416 return !Result.isBottom();
1417}
1418
1419bool MachineConstEvaluator::evaluateANDii(const APInt &A1,
1420 const APInt &A2, APInt &Result) {
1421 Result = A1 & A2;
1422 return true;
1423}
1424
1425bool MachineConstEvaluator::evaluateORrr(const Register &R1,
1426 const Register &R2, const CellMap &Inputs, LatticeCell &Result) {
1427 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg))(static_cast <bool> (Inputs.has(R1.Reg) && Inputs
.has(R2.Reg)) ? void (0) : __assert_fail ("Inputs.has(R1.Reg) && Inputs.has(R2.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1427, __extension__ __PRETTY_FUNCTION__))
;
1428 const LatticeCell &L1 = Inputs.get(R2.Reg);
1429 const LatticeCell &L2 = Inputs.get(R2.Reg);
1430 // If both sources are bottom, exit. Otherwise try to evaluate ORri
1431 // with the non-bottom argument passed as the immediate. This is to
1432 // catch cases of ORing with -1.
1433 if (L2.isBottom()) {
1434 if (L1.isBottom())
1435 return false;
1436 return evaluateORrr(R2, R1, Inputs, Result);
1437 }
1438 LatticeCell LS2;
1439 if (!evaluate(R2, L2, LS2))
1440 return false;
1441 if (LS2.isBottom() || LS2.isProperty())
1442 return false;
1443
1444 APInt A;
1445 for (unsigned i = 0; i < LS2.size(); ++i) {
1446 LatticeCell RC;
1447 bool Eval = constToInt(LS2.Values[i], A) &&
1448 evaluateORri(R1, A, Inputs, RC);
1449 if (!Eval)
1450 return false;
1451 Result.meet(RC);
1452 }
1453 return !Result.isBottom();
1454}
1455
1456bool MachineConstEvaluator::evaluateORri(const Register &R1,
1457 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
1458 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1458, __extension__ __PRETTY_FUNCTION__))
;
1459 if (A2 == 0)
1460 return getCell(R1, Inputs, Result);
1461 if (A2 == -1) {
1462 LatticeCell RC;
1463 RC.add(intToConst(A2));
1464 // Overwrite Result.
1465 Result = RC;
1466 return true;
1467 }
1468 LatticeCell LS1;
1469 if (!getCell(R1, Inputs, LS1))
1470 return false;
1471 if (LS1.isBottom() || LS1.isProperty())
1472 return false;
1473
1474 APInt A, ResA;
1475 for (unsigned i = 0; i < LS1.size(); ++i) {
1476 bool Eval = constToInt(LS1.Values[i], A) &&
1477 evaluateORii(A, A2, ResA);
1478 if (!Eval)
1479 return false;
1480 const Constant *C = intToConst(ResA);
1481 Result.add(C);
1482 }
1483 return !Result.isBottom();
1484}
1485
1486bool MachineConstEvaluator::evaluateORii(const APInt &A1,
1487 const APInt &A2, APInt &Result) {
1488 Result = A1 | A2;
1489 return true;
1490}
1491
1492bool MachineConstEvaluator::evaluateXORrr(const Register &R1,
1493 const Register &R2, const CellMap &Inputs, LatticeCell &Result) {
1494 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg))(static_cast <bool> (Inputs.has(R1.Reg) && Inputs
.has(R2.Reg)) ? void (0) : __assert_fail ("Inputs.has(R1.Reg) && Inputs.has(R2.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1494, __extension__ __PRETTY_FUNCTION__))
;
1495 LatticeCell LS1, LS2;
1496 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2))
1497 return false;
1498 if (LS1.isProperty()) {
1499 if (LS1.properties() & ConstantProperties::Zero)
1500 return !(Result = LS2).isBottom();
1501 return false;
1502 }
1503 if (LS2.isProperty()) {
1504 if (LS2.properties() & ConstantProperties::Zero)
1505 return !(Result = LS1).isBottom();
1506 return false;
1507 }
1508
1509 APInt A;
1510 for (unsigned i = 0; i < LS2.size(); ++i) {
1511 LatticeCell RC;
1512 bool Eval = constToInt(LS2.Values[i], A) &&
1513 evaluateXORri(R1, A, Inputs, RC);
1514 if (!Eval)
1515 return false;
1516 Result.meet(RC);
1517 }
1518 return !Result.isBottom();
1519}
1520
1521bool MachineConstEvaluator::evaluateXORri(const Register &R1,
1522 const APInt &A2, const CellMap &Inputs, LatticeCell &Result) {
1523 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1523, __extension__ __PRETTY_FUNCTION__))
;
1524 LatticeCell LS1;
1525 if (!getCell(R1, Inputs, LS1))
1526 return false;
1527 if (LS1.isProperty()) {
1528 if (LS1.properties() & ConstantProperties::Zero) {
1529 const Constant *C = intToConst(A2);
1530 Result.add(C);
1531 return !Result.isBottom();
1532 }
1533 return false;
1534 }
1535
1536 APInt A, XA;
1537 for (unsigned i = 0; i < LS1.size(); ++i) {
1538 bool Eval = constToInt(LS1.Values[i], A) &&
1539 evaluateXORii(A, A2, XA);
1540 if (!Eval)
1541 return false;
1542 const Constant *C = intToConst(XA);
1543 Result.add(C);
1544 }
1545 return !Result.isBottom();
1546}
1547
1548bool MachineConstEvaluator::evaluateXORii(const APInt &A1,
1549 const APInt &A2, APInt &Result) {
1550 Result = A1 ^ A2;
1551 return true;
1552}
1553
1554bool MachineConstEvaluator::evaluateZEXTr(const Register &R1, unsigned Width,
1555 unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
1556 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1556, __extension__ __PRETTY_FUNCTION__))
;
1557 LatticeCell LS1;
1558 if (!getCell(R1, Inputs, LS1))
1559 return false;
1560 if (LS1.isProperty())
1561 return false;
1562
1563 APInt A, XA;
1564 for (unsigned i = 0; i < LS1.size(); ++i) {
1565 bool Eval = constToInt(LS1.Values[i], A) &&
1566 evaluateZEXTi(A, Width, Bits, XA);
1567 if (!Eval)
1568 return false;
1569 const Constant *C = intToConst(XA);
1570 Result.add(C);
1571 }
1572 return true;
1573}
1574
1575bool MachineConstEvaluator::evaluateZEXTi(const APInt &A1, unsigned Width,
1576 unsigned Bits, APInt &Result) {
1577 unsigned BW = A1.getBitWidth();
1578 (void)BW;
1579 assert(Width >= Bits && BW >= Bits)(static_cast <bool> (Width >= Bits && BW >=
Bits) ? void (0) : __assert_fail ("Width >= Bits && BW >= Bits"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1579, __extension__ __PRETTY_FUNCTION__))
;
1580 APInt Mask = APInt::getLowBitsSet(Width, Bits);
1581 Result = A1.zextOrTrunc(Width) & Mask;
1582 return true;
1583}
1584
1585bool MachineConstEvaluator::evaluateSEXTr(const Register &R1, unsigned Width,
1586 unsigned Bits, const CellMap &Inputs, LatticeCell &Result) {
1587 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1587, __extension__ __PRETTY_FUNCTION__))
;
1588 LatticeCell LS1;
1589 if (!getCell(R1, Inputs, LS1))
1590 return false;
1591 if (LS1.isBottom() || LS1.isProperty())
1592 return false;
1593
1594 APInt A, XA;
1595 for (unsigned i = 0; i < LS1.size(); ++i) {
1596 bool Eval = constToInt(LS1.Values[i], A) &&
1597 evaluateSEXTi(A, Width, Bits, XA);
1598 if (!Eval)
1599 return false;
1600 const Constant *C = intToConst(XA);
1601 Result.add(C);
1602 }
1603 return true;
1604}
1605
1606bool MachineConstEvaluator::evaluateSEXTi(const APInt &A1, unsigned Width,
1607 unsigned Bits, APInt &Result) {
1608 unsigned BW = A1.getBitWidth();
1609 assert(Width >= Bits && BW >= Bits)(static_cast <bool> (Width >= Bits && BW >=
Bits) ? void (0) : __assert_fail ("Width >= Bits && BW >= Bits"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1609, __extension__ __PRETTY_FUNCTION__))
;
1610 // Special case to make things faster for smaller source widths.
1611 // Sign extension of 0 bits generates 0 as a result. This is consistent
1612 // with what the HW does.
1613 if (Bits == 0) {
1614 Result = APInt(Width, 0);
1615 return true;
1616 }
1617 // In C, shifts by 64 invoke undefined behavior: handle that case in APInt.
1618 if (BW <= 64 && Bits != 0) {
1619 int64_t V = A1.getSExtValue();
1620 switch (Bits) {
1621 case 8:
1622 V = static_cast<int8_t>(V);
1623 break;
1624 case 16:
1625 V = static_cast<int16_t>(V);
1626 break;
1627 case 32:
1628 V = static_cast<int32_t>(V);
1629 break;
1630 default:
1631 // Shift left to lose all bits except lower "Bits" bits, then shift
1632 // the value back, replicating what was a sign bit after the first
1633 // shift.
1634 V = (V << (64-Bits)) >> (64-Bits);
1635 break;
1636 }
1637 // V is a 64-bit sign-extended value. Convert it to APInt of desired
1638 // width.
1639 Result = APInt(Width, V, true);
1640 return true;
1641 }
1642 // Slow case: the value doesn't fit in int64_t.
1643 if (Bits < BW)
1644 Result = A1.trunc(Bits).sext(Width);
1645 else // Bits == BW
1646 Result = A1.sext(Width);
1647 return true;
1648}
1649
1650bool MachineConstEvaluator::evaluateCLBr(const Register &R1, bool Zeros,
1651 bool Ones, const CellMap &Inputs, LatticeCell &Result) {
1652 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1652, __extension__ __PRETTY_FUNCTION__))
;
1653 LatticeCell LS1;
1654 if (!getCell(R1, Inputs, LS1))
1655 return false;
1656 if (LS1.isBottom() || LS1.isProperty())
1657 return false;
1658
1659 APInt A, CA;
1660 for (unsigned i = 0; i < LS1.size(); ++i) {
1661 bool Eval = constToInt(LS1.Values[i], A) &&
1662 evaluateCLBi(A, Zeros, Ones, CA);
1663 if (!Eval)
1664 return false;
1665 const Constant *C = intToConst(CA);
1666 Result.add(C);
1667 }
1668 return true;
1669}
1670
1671bool MachineConstEvaluator::evaluateCLBi(const APInt &A1, bool Zeros,
1672 bool Ones, APInt &Result) {
1673 unsigned BW = A1.getBitWidth();
1674 if (!Zeros && !Ones)
1675 return false;
1676 unsigned Count = 0;
1677 if (Zeros && (Count == 0))
1678 Count = A1.countLeadingZeros();
1679 if (Ones && (Count == 0))
1680 Count = A1.countLeadingOnes();
1681 Result = APInt(BW, static_cast<uint64_t>(Count), false);
1682 return true;
1683}
1684
1685bool MachineConstEvaluator::evaluateCTBr(const Register &R1, bool Zeros,
1686 bool Ones, const CellMap &Inputs, LatticeCell &Result) {
1687 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1687, __extension__ __PRETTY_FUNCTION__))
;
1688 LatticeCell LS1;
1689 if (!getCell(R1, Inputs, LS1))
1690 return false;
1691 if (LS1.isBottom() || LS1.isProperty())
1692 return false;
1693
1694 APInt A, CA;
1695 for (unsigned i = 0; i < LS1.size(); ++i) {
1696 bool Eval = constToInt(LS1.Values[i], A) &&
1697 evaluateCTBi(A, Zeros, Ones, CA);
1698 if (!Eval)
1699 return false;
1700 const Constant *C = intToConst(CA);
1701 Result.add(C);
1702 }
1703 return true;
1704}
1705
1706bool MachineConstEvaluator::evaluateCTBi(const APInt &A1, bool Zeros,
1707 bool Ones, APInt &Result) {
1708 unsigned BW = A1.getBitWidth();
1709 if (!Zeros && !Ones)
1710 return false;
1711 unsigned Count = 0;
1712 if (Zeros && (Count == 0))
1713 Count = A1.countTrailingZeros();
1714 if (Ones && (Count == 0))
1715 Count = A1.countTrailingOnes();
1716 Result = APInt(BW, static_cast<uint64_t>(Count), false);
1717 return true;
1718}
1719
1720bool MachineConstEvaluator::evaluateEXTRACTr(const Register &R1,
1721 unsigned Width, unsigned Bits, unsigned Offset, bool Signed,
1722 const CellMap &Inputs, LatticeCell &Result) {
1723 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1723, __extension__ __PRETTY_FUNCTION__))
;
1724 assert(Bits+Offset <= Width)(static_cast <bool> (Bits+Offset <= Width) ? void (0
) : __assert_fail ("Bits+Offset <= Width", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1724, __extension__ __PRETTY_FUNCTION__))
;
1725 LatticeCell LS1;
1726 if (!getCell(R1, Inputs, LS1))
1727 return false;
1728 if (LS1.isBottom())
1729 return false;
1730 if (LS1.isProperty()) {
1731 uint32_t Ps = LS1.properties();
1732 if (Ps & ConstantProperties::Zero) {
1733 const Constant *C = intToConst(APInt(Width, 0, false));
1734 Result.add(C);
1735 return true;
1736 }
1737 return false;
1738 }
1739
1740 APInt A, CA;
1741 for (unsigned i = 0; i < LS1.size(); ++i) {
1742 bool Eval = constToInt(LS1.Values[i], A) &&
1743 evaluateEXTRACTi(A, Bits, Offset, Signed, CA);
1744 if (!Eval)
1745 return false;
1746 const Constant *C = intToConst(CA);
1747 Result.add(C);
1748 }
1749 return true;
1750}
1751
1752bool MachineConstEvaluator::evaluateEXTRACTi(const APInt &A1, unsigned Bits,
1753 unsigned Offset, bool Signed, APInt &Result) {
1754 unsigned BW = A1.getBitWidth();
1755 assert(Bits+Offset <= BW)(static_cast <bool> (Bits+Offset <= BW) ? void (0) :
__assert_fail ("Bits+Offset <= BW", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1755, __extension__ __PRETTY_FUNCTION__))
;
1756 // Extracting 0 bits generates 0 as a result (as indicated by the HW people).
1757 if (Bits == 0) {
1758 Result = APInt(BW, 0);
1759 return true;
1760 }
1761 if (BW <= 64) {
1762 int64_t V = A1.getZExtValue();
1763 V <<= (64-Bits-Offset);
1764 if (Signed)
1765 V >>= (64-Bits);
1766 else
1767 V = static_cast<uint64_t>(V) >> (64-Bits);
1768 Result = APInt(BW, V, Signed);
1769 return true;
1770 }
1771 if (Signed)
1772 Result = A1.shl(BW-Bits-Offset).ashr(BW-Bits);
1773 else
1774 Result = A1.shl(BW-Bits-Offset).lshr(BW-Bits);
1775 return true;
1776}
1777
1778bool MachineConstEvaluator::evaluateSplatr(const Register &R1,
1779 unsigned Bits, unsigned Count, const CellMap &Inputs,
1780 LatticeCell &Result) {
1781 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1781, __extension__ __PRETTY_FUNCTION__))
;
1782 LatticeCell LS1;
1783 if (!getCell(R1, Inputs, LS1))
1784 return false;
1785 if (LS1.isBottom() || LS1.isProperty())
1786 return false;
1787
1788 APInt A, SA;
1789 for (unsigned i = 0; i < LS1.size(); ++i) {
1790 bool Eval = constToInt(LS1.Values[i], A) &&
1791 evaluateSplati(A, Bits, Count, SA);
1792 if (!Eval)
1793 return false;
1794 const Constant *C = intToConst(SA);
1795 Result.add(C);
1796 }
1797 return true;
1798}
1799
1800bool MachineConstEvaluator::evaluateSplati(const APInt &A1, unsigned Bits,
1801 unsigned Count, APInt &Result) {
1802 assert(Count > 0)(static_cast <bool> (Count > 0) ? void (0) : __assert_fail
("Count > 0", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1802, __extension__ __PRETTY_FUNCTION__))
;
1803 unsigned BW = A1.getBitWidth(), SW = Count*Bits;
1804 APInt LoBits = (Bits < BW) ? A1.trunc(Bits) : A1.zextOrSelf(Bits);
1805 if (Count > 1)
1806 LoBits = LoBits.zext(SW);
1807
1808 APInt Res(SW, 0, false);
1809 for (unsigned i = 0; i < Count; ++i) {
1810 Res <<= Bits;
1811 Res |= LoBits;
1812 }
1813 Result = Res;
1814 return true;
1815}
1816
1817// ----------------------------------------------------------------------
1818// Hexagon-specific code.
1819
1820namespace llvm {
1821
1822 FunctionPass *createHexagonConstPropagationPass();
1823 void initializeHexagonConstPropagationPass(PassRegistry &Registry);
1824
1825} // end namespace llvm
1826
1827namespace {
1828
1829 class HexagonConstEvaluator : public MachineConstEvaluator {
1830 public:
1831 HexagonConstEvaluator(MachineFunction &Fn);
1832
1833 bool evaluate(const MachineInstr &MI, const CellMap &Inputs,
1834 CellMap &Outputs) override;
1835 bool evaluate(const Register &R, const LatticeCell &SrcC,
1836 LatticeCell &Result) override;
1837 bool evaluate(const MachineInstr &BrI, const CellMap &Inputs,
1838 SetVector<const MachineBasicBlock*> &Targets, bool &FallsThru)
1839 override;
1840 bool rewrite(MachineInstr &MI, const CellMap &Inputs) override;
1841
1842 private:
1843 unsigned getRegBitWidth(unsigned Reg) const;
1844
1845 static uint32_t getCmp(unsigned Opc);
1846 static APInt getCmpImm(unsigned Opc, unsigned OpX,
1847 const MachineOperand &MO);
1848 void replaceWithNop(MachineInstr &MI);
1849
1850 bool evaluateHexRSEQ32(Register RL, Register RH, const CellMap &Inputs,
1851 LatticeCell &Result);
1852 bool evaluateHexCompare(const MachineInstr &MI, const CellMap &Inputs,
1853 CellMap &Outputs);
1854 // This is suitable to be called for compare-and-jump instructions.
1855 bool evaluateHexCompare2(uint32_t Cmp, const MachineOperand &Src1,
1856 const MachineOperand &Src2, const CellMap &Inputs, bool &Result);
1857 bool evaluateHexLogical(const MachineInstr &MI, const CellMap &Inputs,
1858 CellMap &Outputs);
1859 bool evaluateHexCondMove(const MachineInstr &MI, const CellMap &Inputs,
1860 CellMap &Outputs);
1861 bool evaluateHexExt(const MachineInstr &MI, const CellMap &Inputs,
1862 CellMap &Outputs);
1863 bool evaluateHexVector1(const MachineInstr &MI, const CellMap &Inputs,
1864 CellMap &Outputs);
1865 bool evaluateHexVector2(const MachineInstr &MI, const CellMap &Inputs,
1866 CellMap &Outputs);
1867
1868 void replaceAllRegUsesWith(unsigned FromReg, unsigned ToReg);
1869 bool rewriteHexBranch(MachineInstr &BrI, const CellMap &Inputs);
1870 bool rewriteHexConstDefs(MachineInstr &MI, const CellMap &Inputs,
1871 bool &AllDefs);
1872 bool rewriteHexConstUses(MachineInstr &MI, const CellMap &Inputs);
1873
1874 MachineRegisterInfo *MRI;
1875 const HexagonInstrInfo &HII;
1876 const HexagonRegisterInfo &HRI;
1877 };
1878
1879 class HexagonConstPropagation : public MachineFunctionPass {
1880 public:
1881 static char ID;
1882
1883 HexagonConstPropagation() : MachineFunctionPass(ID) {}
1884
1885 StringRef getPassName() const override {
1886 return "Hexagon Constant Propagation";
1887 }
1888
1889 bool runOnMachineFunction(MachineFunction &MF) override {
1890 const Function &F = MF.getFunction();
1891 if (skipFunction(F))
1892 return false;
1893
1894 HexagonConstEvaluator HCE(MF);
1895 return MachineConstPropagator(HCE).run(MF);
1896 }
1897 };
1898
1899} // end anonymous namespace
1900
1901char HexagonConstPropagation::ID = 0;
1902
1903INITIALIZE_PASS(HexagonConstPropagation, "hexagon-constp",static void *initializeHexagonConstPropagationPassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "Hexagon Constant Propagation"
, "hexagon-constp", &HexagonConstPropagation::ID, PassInfo
::NormalCtor_t(callDefaultCtor<HexagonConstPropagation>
), false, false); Registry.registerPass(*PI, true); return PI
; } static llvm::once_flag InitializeHexagonConstPropagationPassFlag
; void llvm::initializeHexagonConstPropagationPass(PassRegistry
&Registry) { llvm::call_once(InitializeHexagonConstPropagationPassFlag
, initializeHexagonConstPropagationPassOnce, std::ref(Registry
)); }
1904 "Hexagon Constant Propagation", false, false)static void *initializeHexagonConstPropagationPassOnce(PassRegistry
&Registry) { PassInfo *PI = new PassInfo( "Hexagon Constant Propagation"
, "hexagon-constp", &HexagonConstPropagation::ID, PassInfo
::NormalCtor_t(callDefaultCtor<HexagonConstPropagation>
), false, false); Registry.registerPass(*PI, true); return PI
; } static llvm::once_flag InitializeHexagonConstPropagationPassFlag
; void llvm::initializeHexagonConstPropagationPass(PassRegistry
&Registry) { llvm::call_once(InitializeHexagonConstPropagationPassFlag
, initializeHexagonConstPropagationPassOnce, std::ref(Registry
)); }
1905
1906HexagonConstEvaluator::HexagonConstEvaluator(MachineFunction &Fn)
1907 : MachineConstEvaluator(Fn),
1908 HII(*Fn.getSubtarget<HexagonSubtarget>().getInstrInfo()),
1909 HRI(*Fn.getSubtarget<HexagonSubtarget>().getRegisterInfo()) {
1910 MRI = &Fn.getRegInfo();
1911}
1912
1913bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
1914 const CellMap &Inputs, CellMap &Outputs) {
1915 if (MI.isCall())
1916 return false;
1917 if (MI.getNumOperands() == 0 || !MI.getOperand(0).isReg())
1918 return false;
1919 const MachineOperand &MD = MI.getOperand(0);
1920 if (!MD.isDef())
1921 return false;
1922
1923 unsigned Opc = MI.getOpcode();
1924 Register DefR(MD);
1925 assert(!DefR.SubReg)(static_cast <bool> (!DefR.SubReg) ? void (0) : __assert_fail
("!DefR.SubReg", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1925, __extension__ __PRETTY_FUNCTION__))
;
1926 if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg))
1927 return false;
1928
1929 if (MI.isCopy()) {
1930 LatticeCell RC;
1931 Register SrcR(MI.getOperand(1));
1932 bool Eval = evaluateCOPY(SrcR, Inputs, RC);
1933 if (!Eval)
1934 return false;
1935 Outputs.update(DefR.Reg, RC);
1936 return true;
1937 }
1938 if (MI.isRegSequence()) {
1939 unsigned Sub1 = MI.getOperand(2).getImm();
1940 unsigned Sub2 = MI.getOperand(4).getImm();
1941 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
1942 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo);
1943 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi);
1944 if (Sub1 != SubLo && Sub1 != SubHi)
1945 return false;
1946 if (Sub2 != SubLo && Sub2 != SubHi)
1947 return false;
1948 assert(Sub1 != Sub2)(static_cast <bool> (Sub1 != Sub2) ? void (0) : __assert_fail
("Sub1 != Sub2", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 1948, __extension__ __PRETTY_FUNCTION__))
;
1949 bool LoIs1 = (Sub1 == SubLo);
1950 const MachineOperand &OpLo = LoIs1 ? MI.getOperand(1) : MI.getOperand(3);
1951 const MachineOperand &OpHi = LoIs1 ? MI.getOperand(3) : MI.getOperand(1);
1952 LatticeCell RC;
1953 Register SrcRL(OpLo), SrcRH(OpHi);
1954 bool Eval = evaluateHexRSEQ32(SrcRL, SrcRH, Inputs, RC);
1955 if (!Eval)
1956 return false;
1957 Outputs.update(DefR.Reg, RC);
1958 return true;
1959 }
1960 if (MI.isCompare()) {
1961 bool Eval = evaluateHexCompare(MI, Inputs, Outputs);
1962 return Eval;
1963 }
1964
1965 switch (Opc) {
1966 default:
1967 return false;
1968 case Hexagon::A2_tfrsi:
1969 case Hexagon::A2_tfrpi:
1970 case Hexagon::CONST32:
1971 case Hexagon::CONST64:
1972 {
1973 const MachineOperand &VO = MI.getOperand(1);
1974 // The operand of CONST32 can be a blockaddress, e.g.
1975 // %0 = CONST32 <blockaddress(@eat, %l)>
1976 // Do this check for all instructions for safety.
1977 if (!VO.isImm())
1978 return false;
1979 int64_t V = MI.getOperand(1).getImm();
1980 unsigned W = getRegBitWidth(DefR.Reg);
1981 if (W != 32 && W != 64)
1982 return false;
1983 IntegerType *Ty = (W == 32) ? Type::getInt32Ty(CX)
1984 : Type::getInt64Ty(CX);
1985 const ConstantInt *CI = ConstantInt::get(Ty, V, true);
1986 LatticeCell RC = Outputs.get(DefR.Reg);
1987 RC.add(CI);
1988 Outputs.update(DefR.Reg, RC);
1989 break;
1990 }
1991
1992 case Hexagon::PS_true:
1993 case Hexagon::PS_false:
1994 {
1995 LatticeCell RC = Outputs.get(DefR.Reg);
1996 bool NonZero = (Opc == Hexagon::PS_true);
1997 uint32_t P = NonZero ? ConstantProperties::NonZero
1998 : ConstantProperties::Zero;
1999 RC.add(P);
2000 Outputs.update(DefR.Reg, RC);
2001 break;
2002 }
2003
2004 case Hexagon::A2_and:
2005 case Hexagon::A2_andir:
2006 case Hexagon::A2_andp:
2007 case Hexagon::A2_or:
2008 case Hexagon::A2_orir:
2009 case Hexagon::A2_orp:
2010 case Hexagon::A2_xor:
2011 case Hexagon::A2_xorp:
2012 {
2013 bool Eval = evaluateHexLogical(MI, Inputs, Outputs);
2014 if (!Eval)
2015 return false;
2016 break;
2017 }
2018
2019 case Hexagon::A2_combineii: // combine(#s8Ext, #s8)
2020 case Hexagon::A4_combineii: // combine(#s8, #u6Ext)
2021 {
2022 if (!MI.getOperand(1).isImm() || !MI.getOperand(2).isImm())
2023 return false;
2024 uint64_t Hi = MI.getOperand(1).getImm();
2025 uint64_t Lo = MI.getOperand(2).getImm();
2026 uint64_t Res = (Hi << 32) | (Lo & 0xFFFFFFFF);
2027 IntegerType *Ty = Type::getInt64Ty(CX);
2028 const ConstantInt *CI = ConstantInt::get(Ty, Res, false);
2029 LatticeCell RC = Outputs.get(DefR.Reg);
2030 RC.add(CI);
2031 Outputs.update(DefR.Reg, RC);
2032 break;
2033 }
2034
2035 case Hexagon::S2_setbit_i:
2036 {
2037 int64_t B = MI.getOperand(2).getImm();
2038 assert(B >=0 && B < 32)(static_cast <bool> (B >=0 && B < 32) ? void
(0) : __assert_fail ("B >=0 && B < 32", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2038, __extension__ __PRETTY_FUNCTION__))
;
2039 APInt A(32, (1ull << B), false);
2040 Register R(MI.getOperand(1));
2041 LatticeCell RC = Outputs.get(DefR.Reg);
2042 bool Eval = evaluateORri(R, A, Inputs, RC);
2043 if (!Eval)
2044 return false;
2045 Outputs.update(DefR.Reg, RC);
2046 break;
2047 }
2048
2049 case Hexagon::C2_mux:
2050 case Hexagon::C2_muxir:
2051 case Hexagon::C2_muxri:
2052 case Hexagon::C2_muxii:
2053 {
2054 bool Eval = evaluateHexCondMove(MI, Inputs, Outputs);
2055 if (!Eval)
2056 return false;
2057 break;
2058 }
2059
2060 case Hexagon::A2_sxtb:
2061 case Hexagon::A2_sxth:
2062 case Hexagon::A2_sxtw:
2063 case Hexagon::A2_zxtb:
2064 case Hexagon::A2_zxth:
2065 {
2066 bool Eval = evaluateHexExt(MI, Inputs, Outputs);
2067 if (!Eval)
2068 return false;
2069 break;
2070 }
2071
2072 case Hexagon::S2_ct0:
2073 case Hexagon::S2_ct0p:
2074 case Hexagon::S2_ct1:
2075 case Hexagon::S2_ct1p:
2076 {
2077 using namespace Hexagon;
2078
2079 bool Ones = (Opc == S2_ct1) || (Opc == S2_ct1p);
2080 Register R1(MI.getOperand(1));
2081 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2081, __extension__ __PRETTY_FUNCTION__))
;
2082 LatticeCell T;
2083 bool Eval = evaluateCTBr(R1, !Ones, Ones, Inputs, T);
2084 if (!Eval)
2085 return false;
2086 // All of these instructions return a 32-bit value. The evaluate
2087 // will generate the same type as the operand, so truncate the
2088 // result if necessary.
2089 APInt C;
2090 LatticeCell RC = Outputs.get(DefR.Reg);
2091 for (unsigned i = 0; i < T.size(); ++i) {
2092 const Constant *CI = T.Values[i];
2093 if (constToInt(CI, C) && C.getBitWidth() > 32)
2094 CI = intToConst(C.trunc(32));
2095 RC.add(CI);
2096 }
2097 Outputs.update(DefR.Reg, RC);
2098 break;
2099 }
2100
2101 case Hexagon::S2_cl0:
2102 case Hexagon::S2_cl0p:
2103 case Hexagon::S2_cl1:
2104 case Hexagon::S2_cl1p:
2105 case Hexagon::S2_clb:
2106 case Hexagon::S2_clbp:
2107 {
2108 using namespace Hexagon;
2109
2110 bool OnlyZeros = (Opc == S2_cl0) || (Opc == S2_cl0p);
2111 bool OnlyOnes = (Opc == S2_cl1) || (Opc == S2_cl1p);
2112 Register R1(MI.getOperand(1));
2113 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2113, __extension__ __PRETTY_FUNCTION__))
;
2114 LatticeCell T;
2115 bool Eval = evaluateCLBr(R1, !OnlyOnes, !OnlyZeros, Inputs, T);
2116 if (!Eval)
2117 return false;
2118 // All of these instructions return a 32-bit value. The evaluate
2119 // will generate the same type as the operand, so truncate the
2120 // result if necessary.
2121 APInt C;
2122 LatticeCell RC = Outputs.get(DefR.Reg);
2123 for (unsigned i = 0; i < T.size(); ++i) {
2124 const Constant *CI = T.Values[i];
2125 if (constToInt(CI, C) && C.getBitWidth() > 32)
2126 CI = intToConst(C.trunc(32));
2127 RC.add(CI);
2128 }
2129 Outputs.update(DefR.Reg, RC);
2130 break;
2131 }
2132
2133 case Hexagon::S4_extract:
2134 case Hexagon::S4_extractp:
2135 case Hexagon::S2_extractu:
2136 case Hexagon::S2_extractup:
2137 {
2138 bool Signed = (Opc == Hexagon::S4_extract) ||
2139 (Opc == Hexagon::S4_extractp);
2140 Register R1(MI.getOperand(1));
2141 unsigned BW = getRegBitWidth(R1.Reg);
2142 unsigned Bits = MI.getOperand(2).getImm();
2143 unsigned Offset = MI.getOperand(3).getImm();
2144 LatticeCell RC = Outputs.get(DefR.Reg);
2145 if (Offset >= BW) {
2146 APInt Zero(BW, 0, false);
2147 RC.add(intToConst(Zero));
2148 break;
2149 }
2150 if (Offset+Bits > BW) {
2151 // If the requested bitfield extends beyond the most significant bit,
2152 // the extra bits are treated as 0s. To emulate this behavior, reduce
2153 // the number of requested bits, and make the extract unsigned.
2154 Bits = BW-Offset;
2155 Signed = false;
2156 }
2157 bool Eval = evaluateEXTRACTr(R1, BW, Bits, Offset, Signed, Inputs, RC);
2158 if (!Eval)
2159 return false;
2160 Outputs.update(DefR.Reg, RC);
2161 break;
2162 }
2163
2164 case Hexagon::S2_vsplatrb:
2165 case Hexagon::S2_vsplatrh:
2166 // vabsh, vabsh:sat
2167 // vabsw, vabsw:sat
2168 // vconj:sat
2169 // vrndwh, vrndwh:sat
2170 // vsathb, vsathub, vsatwuh
2171 // vsxtbh, vsxthw
2172 // vtrunehb, vtrunohb
2173 // vzxtbh, vzxthw
2174 {
2175 bool Eval = evaluateHexVector1(MI, Inputs, Outputs);
2176 if (!Eval)
2177 return false;
2178 break;
2179 }
2180
2181 // TODO:
2182 // A2_vaddh
2183 // A2_vaddhs
2184 // A2_vaddw
2185 // A2_vaddws
2186 }
2187
2188 return true;
2189}
2190
2191bool HexagonConstEvaluator::evaluate(const Register &R,
2192 const LatticeCell &Input, LatticeCell &Result) {
2193 if (!R.SubReg) {
2194 Result = Input;
2195 return true;
2196 }
2197 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2198 if (RC != &Hexagon::DoubleRegsRegClass)
2199 return false;
2200 if (R.SubReg != Hexagon::isub_lo && R.SubReg != Hexagon::isub_hi)
2201 return false;
2202
2203 assert(!Input.isTop())(static_cast <bool> (!Input.isTop()) ? void (0) : __assert_fail
("!Input.isTop()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2203, __extension__ __PRETTY_FUNCTION__))
;
2204 if (Input.isBottom())
2205 return false;
2206
2207 using P = ConstantProperties;
2208
2209 if (Input.isProperty()) {
2210 uint32_t Ps = Input.properties();
2211 if (Ps & (P::Zero|P::NaN)) {
2212 uint32_t Ns = (Ps & (P::Zero|P::NaN|P::SignProperties));
2213 Result.add(Ns);
2214 return true;
2215 }
2216 if (R.SubReg == Hexagon::isub_hi) {
2217 uint32_t Ns = (Ps & P::SignProperties);
2218 Result.add(Ns);
2219 return true;
2220 }
2221 return false;
2222 }
2223
2224 // The Input cell contains some known values. Pick the word corresponding
2225 // to the subregister.
2226 APInt A;
2227 for (unsigned i = 0; i < Input.size(); ++i) {
2228 const Constant *C = Input.Values[i];
2229 if (!constToInt(C, A))
2230 return false;
2231 if (!A.isIntN(64))
2232 return false;
2233 uint64_t U = A.getZExtValue();
2234 if (R.SubReg == Hexagon::isub_hi)
2235 U >>= 32;
2236 U &= 0xFFFFFFFFULL;
2237 uint32_t U32 = Lo_32(U);
2238 int32_t V32;
2239 memcpy(&V32, &U32, sizeof V32);
2240 IntegerType *Ty = Type::getInt32Ty(CX);
2241 const ConstantInt *C32 = ConstantInt::get(Ty, static_cast<int64_t>(V32));
2242 Result.add(C32);
2243 }
2244 return true;
2245}
2246
2247bool HexagonConstEvaluator::evaluate(const MachineInstr &BrI,
2248 const CellMap &Inputs, SetVector<const MachineBasicBlock*> &Targets,
2249 bool &FallsThru) {
2250 // We need to evaluate one branch at a time. TII::analyzeBranch checks
2251 // all the branches in a basic block at once, so we cannot use it.
2252 unsigned Opc = BrI.getOpcode();
2253 bool SimpleBranch = false;
2254 bool Negated = false;
2255 switch (Opc) {
2256 case Hexagon::J2_jumpf:
2257 case Hexagon::J2_jumpfnew:
2258 case Hexagon::J2_jumpfnewpt:
2259 Negated = true;
2260 LLVM_FALLTHROUGH[[clang::fallthrough]];
2261 case Hexagon::J2_jumpt:
2262 case Hexagon::J2_jumptnew:
2263 case Hexagon::J2_jumptnewpt:
2264 // Simple branch: if([!]Pn) jump ...
2265 // i.e. Op0 = predicate, Op1 = branch target.
2266 SimpleBranch = true;
2267 break;
2268 case Hexagon::J2_jump:
2269 Targets.insert(BrI.getOperand(0).getMBB());
2270 FallsThru = false;
2271 return true;
2272 default:
2273Undetermined:
2274 // If the branch is of unknown type, assume that all successors are
2275 // executable.
2276 FallsThru = !BrI.isUnconditionalBranch();
2277 return false;
2278 }
2279
2280 if (SimpleBranch) {
2281 const MachineOperand &MD = BrI.getOperand(0);
2282 Register PR(MD);
2283 // If the condition operand has a subregister, this is not something
2284 // we currently recognize.
2285 if (PR.SubReg)
2286 goto Undetermined;
2287 assert(Inputs.has(PR.Reg))(static_cast <bool> (Inputs.has(PR.Reg)) ? void (0) : __assert_fail
("Inputs.has(PR.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2287, __extension__ __PRETTY_FUNCTION__))
;
2288 const LatticeCell &PredC = Inputs.get(PR.Reg);
2289 if (PredC.isBottom())
2290 goto Undetermined;
2291
2292 uint32_t Props = PredC.properties();
2293 bool CTrue = false, CFalse = false;
2294 if (Props & ConstantProperties::Zero)
2295 CFalse = true;
2296 else if (Props & ConstantProperties::NonZero)
2297 CTrue = true;
2298 // If the condition is not known to be either, bail out.
2299 if (!CTrue && !CFalse)
2300 goto Undetermined;
2301
2302 const MachineBasicBlock *BranchTarget = BrI.getOperand(1).getMBB();
2303
2304 FallsThru = false;
2305 if ((!Negated && CTrue) || (Negated && CFalse))
2306 Targets.insert(BranchTarget);
2307 else if ((!Negated && CFalse) || (Negated && CTrue))
2308 FallsThru = true;
2309 else
2310 goto Undetermined;
2311 }
2312
2313 return true;
2314}
2315
2316bool HexagonConstEvaluator::rewrite(MachineInstr &MI, const CellMap &Inputs) {
2317 if (MI.isBranch())
2318 return rewriteHexBranch(MI, Inputs);
2319
2320 unsigned Opc = MI.getOpcode();
2321 switch (Opc) {
2322 default:
2323 break;
2324 case Hexagon::A2_tfrsi:
2325 case Hexagon::A2_tfrpi:
2326 case Hexagon::CONST32:
2327 case Hexagon::CONST64:
2328 case Hexagon::PS_true:
2329 case Hexagon::PS_false:
2330 return false;
2331 }
2332
2333 unsigned NumOp = MI.getNumOperands();
2334 if (NumOp == 0)
2335 return false;
2336
2337 bool AllDefs, Changed;
2338 Changed = rewriteHexConstDefs(MI, Inputs, AllDefs);
2339 // If not all defs have been rewritten (i.e. the instruction defines
2340 // a register that is not compile-time constant), then try to rewrite
2341 // register operands that are known to be constant with immediates.
2342 if (!AllDefs)
2343 Changed |= rewriteHexConstUses(MI, Inputs);
2344
2345 return Changed;
2346}
2347
2348unsigned HexagonConstEvaluator::getRegBitWidth(unsigned Reg) const {
2349 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2350 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC))
2351 return 32;
2352 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC))
2353 return 64;
2354 if (Hexagon::PredRegsRegClass.hasSubClassEq(RC))
2355 return 8;
2356 llvm_unreachable("Invalid register")::llvm::llvm_unreachable_internal("Invalid register", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2356)
;
2357 return 0;
2358}
2359
2360uint32_t HexagonConstEvaluator::getCmp(unsigned Opc) {
2361 switch (Opc) {
2362 case Hexagon::C2_cmpeq:
2363 case Hexagon::C2_cmpeqp:
2364 case Hexagon::A4_cmpbeq:
2365 case Hexagon::A4_cmpheq:
2366 case Hexagon::A4_cmpbeqi:
2367 case Hexagon::A4_cmpheqi:
2368 case Hexagon::C2_cmpeqi:
2369 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
2370 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
2371 case Hexagon::J4_cmpeqi_t_jumpnv_nt:
2372 case Hexagon::J4_cmpeqi_t_jumpnv_t:
2373 case Hexagon::J4_cmpeq_t_jumpnv_nt:
2374 case Hexagon::J4_cmpeq_t_jumpnv_t:
2375 return Comparison::EQ;
2376
2377 case Hexagon::C4_cmpneq:
2378 case Hexagon::C4_cmpneqi:
2379 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
2380 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
2381 case Hexagon::J4_cmpeqi_f_jumpnv_nt:
2382 case Hexagon::J4_cmpeqi_f_jumpnv_t:
2383 case Hexagon::J4_cmpeq_f_jumpnv_nt:
2384 case Hexagon::J4_cmpeq_f_jumpnv_t:
2385 return Comparison::NE;
2386
2387 case Hexagon::C2_cmpgt:
2388 case Hexagon::C2_cmpgtp:
2389 case Hexagon::A4_cmpbgt:
2390 case Hexagon::A4_cmphgt:
2391 case Hexagon::A4_cmpbgti:
2392 case Hexagon::A4_cmphgti:
2393 case Hexagon::C2_cmpgti:
2394 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
2395 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
2396 case Hexagon::J4_cmpgti_t_jumpnv_nt:
2397 case Hexagon::J4_cmpgti_t_jumpnv_t:
2398 case Hexagon::J4_cmpgt_t_jumpnv_nt:
2399 case Hexagon::J4_cmpgt_t_jumpnv_t:
2400 return Comparison::GTs;
2401
2402 case Hexagon::C4_cmplte:
2403 case Hexagon::C4_cmpltei:
2404 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
2405 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
2406 case Hexagon::J4_cmpgti_f_jumpnv_nt:
2407 case Hexagon::J4_cmpgti_f_jumpnv_t:
2408 case Hexagon::J4_cmpgt_f_jumpnv_nt:
2409 case Hexagon::J4_cmpgt_f_jumpnv_t:
2410 return Comparison::LEs;
2411
2412 case Hexagon::C2_cmpgtu:
2413 case Hexagon::C2_cmpgtup:
2414 case Hexagon::A4_cmpbgtu:
2415 case Hexagon::A4_cmpbgtui:
2416 case Hexagon::A4_cmphgtu:
2417 case Hexagon::A4_cmphgtui:
2418 case Hexagon::C2_cmpgtui:
2419 case Hexagon::J4_cmpgtui_t_jumpnv_nt:
2420 case Hexagon::J4_cmpgtui_t_jumpnv_t:
2421 case Hexagon::J4_cmpgtu_t_jumpnv_nt:
2422 case Hexagon::J4_cmpgtu_t_jumpnv_t:
2423 return Comparison::GTu;
2424
2425 case Hexagon::J4_cmpltu_f_jumpnv_nt:
2426 case Hexagon::J4_cmpltu_f_jumpnv_t:
2427 return Comparison::GEu;
2428
2429 case Hexagon::J4_cmpltu_t_jumpnv_nt:
2430 case Hexagon::J4_cmpltu_t_jumpnv_t:
2431 return Comparison::LTu;
2432
2433 case Hexagon::J4_cmplt_f_jumpnv_nt:
2434 case Hexagon::J4_cmplt_f_jumpnv_t:
2435 return Comparison::GEs;
2436
2437 case Hexagon::C4_cmplteu:
2438 case Hexagon::C4_cmplteui:
2439 case Hexagon::J4_cmpgtui_f_jumpnv_nt:
2440 case Hexagon::J4_cmpgtui_f_jumpnv_t:
2441 case Hexagon::J4_cmpgtu_f_jumpnv_nt:
2442 case Hexagon::J4_cmpgtu_f_jumpnv_t:
2443 return Comparison::LEu;
2444
2445 case Hexagon::J4_cmplt_t_jumpnv_nt:
2446 case Hexagon::J4_cmplt_t_jumpnv_t:
2447 return Comparison::LTs;
2448
2449 default:
2450 break;
2451 }
2452 return Comparison::Unk;
2453}
2454
2455APInt HexagonConstEvaluator::getCmpImm(unsigned Opc, unsigned OpX,
2456 const MachineOperand &MO) {
2457 bool Signed = false;
2458 switch (Opc) {
2459 case Hexagon::A4_cmpbgtui: // u7
2460 case Hexagon::A4_cmphgtui: // u7
2461 break;
2462 case Hexagon::A4_cmpheqi: // s8
2463 case Hexagon::C4_cmpneqi: // s8
2464 Signed = true;
2465 case Hexagon::A4_cmpbeqi: // u8
2466 break;
2467 case Hexagon::C2_cmpgtui: // u9
2468 case Hexagon::C4_cmplteui: // u9
2469 break;
2470 case Hexagon::C2_cmpeqi: // s10
2471 case Hexagon::C2_cmpgti: // s10
2472 case Hexagon::C4_cmpltei: // s10
2473 Signed = true;
2474 break;
2475 case Hexagon::J4_cmpeqi_f_jumpnv_nt: // u5
2476 case Hexagon::J4_cmpeqi_f_jumpnv_t: // u5
2477 case Hexagon::J4_cmpeqi_t_jumpnv_nt: // u5
2478 case Hexagon::J4_cmpeqi_t_jumpnv_t: // u5
2479 case Hexagon::J4_cmpgti_f_jumpnv_nt: // u5
2480 case Hexagon::J4_cmpgti_f_jumpnv_t: // u5
2481 case Hexagon::J4_cmpgti_t_jumpnv_nt: // u5
2482 case Hexagon::J4_cmpgti_t_jumpnv_t: // u5
2483 case Hexagon::J4_cmpgtui_f_jumpnv_nt: // u5
2484 case Hexagon::J4_cmpgtui_f_jumpnv_t: // u5
2485 case Hexagon::J4_cmpgtui_t_jumpnv_nt: // u5
2486 case Hexagon::J4_cmpgtui_t_jumpnv_t: // u5
2487 break;
2488 default:
2489 llvm_unreachable("Unhandled instruction")::llvm::llvm_unreachable_internal("Unhandled instruction", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2489)
;
2490 break;
2491 }
2492
2493 uint64_t Val = MO.getImm();
2494 return APInt(32, Val, Signed);
2495}
2496
2497void HexagonConstEvaluator::replaceWithNop(MachineInstr &MI) {
2498 MI.setDesc(HII.get(Hexagon::A2_nop));
2499 while (MI.getNumOperands() > 0)
2500 MI.RemoveOperand(0);
2501}
2502
2503bool HexagonConstEvaluator::evaluateHexRSEQ32(Register RL, Register RH,
2504 const CellMap &Inputs, LatticeCell &Result) {
2505 assert(Inputs.has(RL.Reg) && Inputs.has(RH.Reg))(static_cast <bool> (Inputs.has(RL.Reg) && Inputs
.has(RH.Reg)) ? void (0) : __assert_fail ("Inputs.has(RL.Reg) && Inputs.has(RH.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2505, __extension__ __PRETTY_FUNCTION__))
;
2506 LatticeCell LSL, LSH;
2507 if (!getCell(RL, Inputs, LSL) || !getCell(RH, Inputs, LSH))
2508 return false;
2509 if (LSL.isProperty() || LSH.isProperty())
2510 return false;
2511
2512 unsigned LN = LSL.size(), HN = LSH.size();
2513 SmallVector<APInt,4> LoVs(LN), HiVs(HN);
2514 for (unsigned i = 0; i < LN; ++i) {
2515 bool Eval = constToInt(LSL.Values[i], LoVs[i]);
2516 if (!Eval)
2517 return false;
2518 assert(LoVs[i].getBitWidth() == 32)(static_cast <bool> (LoVs[i].getBitWidth() == 32) ? void
(0) : __assert_fail ("LoVs[i].getBitWidth() == 32", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2518, __extension__ __PRETTY_FUNCTION__))
;
2519 }
2520 for (unsigned i = 0; i < HN; ++i) {
2521 bool Eval = constToInt(LSH.Values[i], HiVs[i]);
2522 if (!Eval)
2523 return false;
2524 assert(HiVs[i].getBitWidth() == 32)(static_cast <bool> (HiVs[i].getBitWidth() == 32) ? void
(0) : __assert_fail ("HiVs[i].getBitWidth() == 32", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2524, __extension__ __PRETTY_FUNCTION__))
;
2525 }
2526
2527 for (unsigned i = 0; i < HiVs.size(); ++i) {
2528 APInt HV = HiVs[i].zextOrSelf(64) << 32;
2529 for (unsigned j = 0; j < LoVs.size(); ++j) {
2530 APInt LV = LoVs[j].zextOrSelf(64);
2531 const Constant *C = intToConst(HV | LV);
2532 Result.add(C);
2533 if (Result.isBottom())
2534 return false;
2535 }
2536 }
2537 return !Result.isBottom();
2538}
2539
2540bool HexagonConstEvaluator::evaluateHexCompare(const MachineInstr &MI,
2541 const CellMap &Inputs, CellMap &Outputs) {
2542 unsigned Opc = MI.getOpcode();
2543 bool Classic = false;
2544 switch (Opc) {
2545 case Hexagon::C2_cmpeq:
2546 case Hexagon::C2_cmpeqp:
2547 case Hexagon::C2_cmpgt:
2548 case Hexagon::C2_cmpgtp:
2549 case Hexagon::C2_cmpgtu:
2550 case Hexagon::C2_cmpgtup:
2551 case Hexagon::C2_cmpeqi:
2552 case Hexagon::C2_cmpgti:
2553 case Hexagon::C2_cmpgtui:
2554 // Classic compare: Dst0 = CMP Src1, Src2
2555 Classic = true;
2556 break;
2557 default:
2558 // Not handling other compare instructions now.
2559 return false;
2560 }
2561
2562 if (Classic) {
2563 const MachineOperand &Src1 = MI.getOperand(1);
2564 const MachineOperand &Src2 = MI.getOperand(2);
2565
2566 bool Result;
2567 unsigned Opc = MI.getOpcode();
2568 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result);
2569 if (Computed) {
2570 // Only create a zero/non-zero cell. At this time there isn't really
2571 // much need for specific values.
2572 Register DefR(MI.getOperand(0));
2573 LatticeCell L = Outputs.get(DefR.Reg);
2574 uint32_t P = Result ? ConstantProperties::NonZero
2575 : ConstantProperties::Zero;
2576 L.add(P);
2577 Outputs.update(DefR.Reg, L);
2578 return true;
2579 }
2580 }
2581
2582 return false;
2583}
2584
2585bool HexagonConstEvaluator::evaluateHexCompare2(unsigned Opc,
2586 const MachineOperand &Src1, const MachineOperand &Src2,
2587 const CellMap &Inputs, bool &Result) {
2588 uint32_t Cmp = getCmp(Opc);
2589 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
2590 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm();
2591 if (Reg1) {
2592 Register R1(Src1);
2593 if (Reg2) {
2594 Register R2(Src2);
2595 return evaluateCMPrr(Cmp, R1, R2, Inputs, Result);
2596 } else if (Imm2) {
2597 APInt A2 = getCmpImm(Opc, 2, Src2);
2598 return evaluateCMPri(Cmp, R1, A2, Inputs, Result);
2599 }
2600 } else if (Imm1) {
2601 APInt A1 = getCmpImm(Opc, 1, Src1);
2602 if (Reg2) {
2603 Register R2(Src2);
2604 uint32_t NegCmp = Comparison::negate(Cmp);
2605 return evaluateCMPri(NegCmp, R2, A1, Inputs, Result);
2606 } else if (Imm2) {
2607 APInt A2 = getCmpImm(Opc, 2, Src2);
2608 return evaluateCMPii(Cmp, A1, A2, Result);
2609 }
2610 }
2611 // Unknown kind of comparison.
2612 return false;
2613}
2614
2615bool HexagonConstEvaluator::evaluateHexLogical(const MachineInstr &MI,
2616 const CellMap &Inputs, CellMap &Outputs) {
2617 unsigned Opc = MI.getOpcode();
2618 if (MI.getNumOperands() != 3)
2619 return false;
2620 const MachineOperand &Src1 = MI.getOperand(1);
2621 const MachineOperand &Src2 = MI.getOperand(2);
2622 Register R1(Src1);
2623 bool Eval = false;
2624 LatticeCell RC;
2625 switch (Opc) {
2626 default:
2627 return false;
2628 case Hexagon::A2_and:
2629 case Hexagon::A2_andp:
2630 Eval = evaluateANDrr(R1, Register(Src2), Inputs, RC);
2631 break;
2632 case Hexagon::A2_andir: {
2633 if (!Src2.isImm())
2634 return false;
2635 APInt A(32, Src2.getImm(), true);
2636 Eval = evaluateANDri(R1, A, Inputs, RC);
2637 break;
2638 }
2639 case Hexagon::A2_or:
2640 case Hexagon::A2_orp:
2641 Eval = evaluateORrr(R1, Register(Src2), Inputs, RC);
2642 break;
2643 case Hexagon::A2_orir: {
2644 if (!Src2.isImm())
2645 return false;
2646 APInt A(32, Src2.getImm(), true);
2647 Eval = evaluateORri(R1, A, Inputs, RC);
2648 break;
2649 }
2650 case Hexagon::A2_xor:
2651 case Hexagon::A2_xorp:
2652 Eval = evaluateXORrr(R1, Register(Src2), Inputs, RC);
2653 break;
2654 }
2655 if (Eval) {
2656 Register DefR(MI.getOperand(0));
2657 Outputs.update(DefR.Reg, RC);
2658 }
2659 return Eval;
2660}
2661
2662bool HexagonConstEvaluator::evaluateHexCondMove(const MachineInstr &MI,
2663 const CellMap &Inputs, CellMap &Outputs) {
2664 // Dst0 = Cond1 ? Src2 : Src3
2665 Register CR(MI.getOperand(1));
2666 assert(Inputs.has(CR.Reg))(static_cast <bool> (Inputs.has(CR.Reg)) ? void (0) : __assert_fail
("Inputs.has(CR.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2666, __extension__ __PRETTY_FUNCTION__))
;
2667 LatticeCell LS;
2668 if (!getCell(CR, Inputs, LS))
2669 return false;
2670 uint32_t Ps = LS.properties();
2671 unsigned TakeOp;
2672 if (Ps & ConstantProperties::Zero)
2673 TakeOp = 3;
2674 else if (Ps & ConstantProperties::NonZero)
2675 TakeOp = 2;
2676 else
2677 return false;
2678
2679 const MachineOperand &ValOp = MI.getOperand(TakeOp);
2680 Register DefR(MI.getOperand(0));
2681 LatticeCell RC = Outputs.get(DefR.Reg);
2682
2683 if (ValOp.isImm()) {
2684 int64_t V = ValOp.getImm();
2685 unsigned W = getRegBitWidth(DefR.Reg);
2686 APInt A(W, V, true);
2687 const Constant *C = intToConst(A);
2688 RC.add(C);
2689 Outputs.update(DefR.Reg, RC);
2690 return true;
2691 }
2692 if (ValOp.isReg()) {
2693 Register R(ValOp);
2694 const LatticeCell &LR = Inputs.get(R.Reg);
2695 LatticeCell LSR;
2696 if (!evaluate(R, LR, LSR))
2697 return false;
2698 RC.meet(LSR);
2699 Outputs.update(DefR.Reg, RC);
2700 return true;
2701 }
2702 return false;
2703}
2704
2705bool HexagonConstEvaluator::evaluateHexExt(const MachineInstr &MI,
2706 const CellMap &Inputs, CellMap &Outputs) {
2707 // Dst0 = ext R1
2708 Register R1(MI.getOperand(1));
2709 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2709, __extension__ __PRETTY_FUNCTION__))
;
2710
2711 unsigned Opc = MI.getOpcode();
2712 unsigned Bits;
1
'Bits' declared without an initial value
2713 switch (Opc) {
2
'Default' branch taken. Execution continues on line 2727
2714 case Hexagon::A2_sxtb:
2715 case Hexagon::A2_zxtb:
2716 Bits = 8;
2717 break;
2718 case Hexagon::A2_sxth:
2719 case Hexagon::A2_zxth:
2720 Bits = 16;
2721 break;
2722 case Hexagon::A2_sxtw:
2723 Bits = 32;
2724 break;
2725 }
2726
2727 bool Signed = false;
2728 switch (Opc) {
3
'Default' branch taken. Execution continues on line 2736
2729 case Hexagon::A2_sxtb:
2730 case Hexagon::A2_sxth:
2731 case Hexagon::A2_sxtw:
2732 Signed = true;
2733 break;
2734 }
2735
2736 Register DefR(MI.getOperand(0));
2737 unsigned BW = getRegBitWidth(DefR.Reg);
2738 LatticeCell RC = Outputs.get(DefR.Reg);
2739 bool Eval = Signed ? evaluateSEXTr(R1, BW, Bits, Inputs, RC)
4
'?' condition is false
2740 : evaluateZEXTr(R1, BW, Bits, Inputs, RC);
5
3rd function call argument is an uninitialized value
2741 if (!Eval)
2742 return false;
2743 Outputs.update(DefR.Reg, RC);
2744 return true;
2745}
2746
2747bool HexagonConstEvaluator::evaluateHexVector1(const MachineInstr &MI,
2748 const CellMap &Inputs, CellMap &Outputs) {
2749 // DefR = op R1
2750 Register DefR(MI.getOperand(0));
2751 Register R1(MI.getOperand(1));
2752 assert(Inputs.has(R1.Reg))(static_cast <bool> (Inputs.has(R1.Reg)) ? void (0) : __assert_fail
("Inputs.has(R1.Reg)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2752, __extension__ __PRETTY_FUNCTION__))
;
2753 LatticeCell RC = Outputs.get(DefR.Reg);
2754 bool Eval;
2755
2756 unsigned Opc = MI.getOpcode();
2757 switch (Opc) {
2758 case Hexagon::S2_vsplatrb:
2759 // Rd = 4 times Rs:0..7
2760 Eval = evaluateSplatr(R1, 8, 4, Inputs, RC);
2761 break;
2762 case Hexagon::S2_vsplatrh:
2763 // Rdd = 4 times Rs:0..15
2764 Eval = evaluateSplatr(R1, 16, 4, Inputs, RC);
2765 break;
2766 default:
2767 return false;
2768 }
2769
2770 if (!Eval)
2771 return false;
2772 Outputs.update(DefR.Reg, RC);
2773 return true;
2774}
2775
2776bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
2777 const CellMap &Inputs, bool &AllDefs) {
2778 AllDefs = false;
2779
2780 // Some diagnostics.
2781 // DEBUG({...}) gets confused with all this code as an argument.
2782#ifndef NDEBUG
2783 bool Debugging = DebugFlag && isCurrentDebugType(DEBUG_TYPE"hcp");
2784 if (Debugging) {
2785 bool Const = true, HasUse = false;
2786 for (const MachineOperand &MO : MI.operands()) {
2787 if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
2788 continue;
2789 Register R(MO);
2790 if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
2791 continue;
2792 HasUse = true;
2793 // PHIs can legitimately have "top" cells after propagation.
2794 if (!MI.isPHI() && !Inputs.has(R.Reg)) {
2795 dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
2796 << " in MI: " << MI;
2797 continue;
2798 }
2799 const LatticeCell &L = Inputs.get(R.Reg);
2800 Const &= L.isSingle();
2801 if (!Const)
2802 break;
2803 }
2804 if (HasUse && Const) {
2805 if (!MI.isCopy()) {
2806 dbgs() << "CONST: " << MI;
2807 for (const MachineOperand &MO : MI.operands()) {
2808 if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
2809 continue;
2810 unsigned R = MO.getReg();
2811 dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
2812 }
2813 }
2814 }
2815 }
2816#endif
2817
2818 // Avoid generating TFRIs for register transfers---this will keep the
2819 // coalescing opportunities.
2820 if (MI.isCopy())
2821 return false;
2822
2823 // Collect all virtual register-def operands.
2824 SmallVector<unsigned,2> DefRegs;
2825 for (const MachineOperand &MO : MI.operands()) {
2826 if (!MO.isReg() || !MO.isDef())
2827 continue;
2828 unsigned R = MO.getReg();
2829 if (!TargetRegisterInfo::isVirtualRegister(R))
2830 continue;
2831 assert(!MO.getSubReg())(static_cast <bool> (!MO.getSubReg()) ? void (0) : __assert_fail
("!MO.getSubReg()", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2831, __extension__ __PRETTY_FUNCTION__))
;
2832 assert(Inputs.has(R))(static_cast <bool> (Inputs.has(R)) ? void (0) : __assert_fail
("Inputs.has(R)", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2832, __extension__ __PRETTY_FUNCTION__))
;
2833 DefRegs.push_back(R);
2834 }
2835
2836 MachineBasicBlock &B = *MI.getParent();
2837 const DebugLoc &DL = MI.getDebugLoc();
2838 unsigned ChangedNum = 0;
2839#ifndef NDEBUG
2840 SmallVector<const MachineInstr*,4> NewInstrs;
2841#endif
2842
2843 // For each defined register, if it is a constant, create an instruction
2844 // NewR = const
2845 // and replace all uses of the defined register with NewR.
2846 for (unsigned i = 0, n = DefRegs.size(); i < n; ++i) {
2847 unsigned R = DefRegs[i];
2848 const LatticeCell &L = Inputs.get(R);
2849 if (L.isBottom())
2850 continue;
2851 const TargetRegisterClass *RC = MRI->getRegClass(R);
2852 MachineBasicBlock::iterator At = MI.getIterator();
2853
2854 if (!L.isSingle()) {
2855 // If this a zero/non-zero cell, we can fold a definition
2856 // of a predicate register.
2857 using P = ConstantProperties;
2858
2859 uint64_t Ps = L.properties();
2860 if (!(Ps & (P::Zero|P::NonZero)))
2861 continue;
2862 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
2863 if (RC != PredRC)
2864 continue;
2865 const MCInstrDesc *NewD = (Ps & P::Zero) ?
2866 &HII.get(Hexagon::PS_false) :
2867 &HII.get(Hexagon::PS_true);
2868 unsigned NewR = MRI->createVirtualRegister(PredRC);
2869 const MachineInstrBuilder &MIB = BuildMI(B, At, DL, *NewD, NewR);
2870 (void)MIB;
2871#ifndef NDEBUG
2872 NewInstrs.push_back(&*MIB);
2873#endif
2874 replaceAllRegUsesWith(R, NewR);
2875 } else {
2876 // This cell has a single value.
2877 APInt A;
2878 if (!constToInt(L.Value, A) || !A.isSignedIntN(64))
2879 continue;
2880 const TargetRegisterClass *NewRC;
2881 const MCInstrDesc *NewD;
2882
2883 unsigned W = getRegBitWidth(R);
2884 int64_t V = A.getSExtValue();
2885 assert(W == 32 || W == 64)(static_cast <bool> (W == 32 || W == 64) ? void (0) : __assert_fail
("W == 32 || W == 64", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2885, __extension__ __PRETTY_FUNCTION__))
;
2886 if (W == 32)
2887 NewRC = &Hexagon::IntRegsRegClass;
2888 else
2889 NewRC = &Hexagon::DoubleRegsRegClass;
2890 unsigned NewR = MRI->createVirtualRegister(NewRC);
2891 const MachineInstr *NewMI;
2892
2893 if (W == 32) {
2894 NewD = &HII.get(Hexagon::A2_tfrsi);
2895 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2896 .addImm(V);
2897 } else {
2898 if (A.isSignedIntN(8)) {
2899 NewD = &HII.get(Hexagon::A2_tfrpi);
2900 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2901 .addImm(V);
2902 } else {
2903 int32_t Hi = V >> 32;
2904 int32_t Lo = V & 0xFFFFFFFFLL;
2905 if (isInt<8>(Hi) && isInt<8>(Lo)) {
2906 NewD = &HII.get(Hexagon::A2_combineii);
2907 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2908 .addImm(Hi)
2909 .addImm(Lo);
2910 } else {
2911 NewD = &HII.get(Hexagon::CONST64);
2912 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2913 .addImm(V);
2914 }
2915 }
2916 }
2917 (void)NewMI;
2918#ifndef NDEBUG
2919 NewInstrs.push_back(NewMI);
2920#endif
2921 replaceAllRegUsesWith(R, NewR);
2922 }
2923 ChangedNum++;
2924 }
2925
2926 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2927 if (!NewInstrs.empty()) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2928 MachineFunction &MF = *MI.getParent()->getParent();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2929 dbgs() << "In function: " << MF.getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2930 dbgs() << "Rewrite: for " << MI << " created " << *NewInstrs[0];do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2931 for (unsigned i = 1; i < NewInstrs.size(); ++i)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2932 dbgs() << " " << *NewInstrs[i];do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2933 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
2934 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (!NewInstrs.empty()) { MachineFunction &MF
= *MI.getParent()->getParent(); dbgs() << "In function: "
<< MF.getName() << "\n"; dbgs() << "Rewrite: for "
<< MI << " created " << *NewInstrs[0]; for
(unsigned i = 1; i < NewInstrs.size(); ++i) dbgs() <<
" " << *NewInstrs[i]; } }; } } while (false)
;
2935
2936 AllDefs = (ChangedNum == DefRegs.size());
2937 return ChangedNum > 0;
2938}
2939
2940bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
2941 const CellMap &Inputs) {
2942 bool Changed = false;
2943 unsigned Opc = MI.getOpcode();
2944 MachineBasicBlock &B = *MI.getParent();
2945 const DebugLoc &DL = MI.getDebugLoc();
2946 MachineBasicBlock::iterator At = MI.getIterator();
2947 MachineInstr *NewMI = nullptr;
2948
2949 switch (Opc) {
2950 case Hexagon::M2_maci:
2951 // Convert DefR += mpyi(R2, R3)
2952 // to DefR += mpyi(R, #imm),
2953 // or DefR -= mpyi(R, #imm).
2954 {
2955 Register DefR(MI.getOperand(0));
2956 assert(!DefR.SubReg)(static_cast <bool> (!DefR.SubReg) ? void (0) : __assert_fail
("!DefR.SubReg", "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2956, __extension__ __PRETTY_FUNCTION__))
;
2957 Register R2(MI.getOperand(2));
2958 Register R3(MI.getOperand(3));
2959 assert(Inputs.has(R2.Reg) && Inputs.has(R3.Reg))(static_cast <bool> (Inputs.has(R2.Reg) && Inputs
.has(R3.Reg)) ? void (0) : __assert_fail ("Inputs.has(R2.Reg) && Inputs.has(R3.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 2959, __extension__ __PRETTY_FUNCTION__))
;
2960 LatticeCell LS2, LS3;
2961 // It is enough to get one of the input cells, since we will only try
2962 // to replace one argument---whichever happens to be a single constant.
2963 bool HasC2 = getCell(R2, Inputs, LS2), HasC3 = getCell(R3, Inputs, LS3);
2964 if (!HasC2 && !HasC3)
2965 return false;
2966 bool Zero = ((HasC2 && (LS2.properties() & ConstantProperties::Zero)) ||
2967 (HasC3 && (LS3.properties() & ConstantProperties::Zero)));
2968 // If one of the operands is zero, eliminate the multiplication.
2969 if (Zero) {
2970 // DefR == R1 (tied operands).
2971 MachineOperand &Acc = MI.getOperand(1);
2972 Register R1(Acc);
2973 unsigned NewR = R1.Reg;
2974 if (R1.SubReg) {
2975 // Generate COPY. FIXME: Replace with the register:subregister.
2976 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
2977 NewR = MRI->createVirtualRegister(RC);
2978 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
2979 .addReg(R1.Reg, getRegState(Acc), R1.SubReg);
2980 }
2981 replaceAllRegUsesWith(DefR.Reg, NewR);
2982 MRI->clearKillFlags(NewR);
2983 Changed = true;
2984 break;
2985 }
2986
2987 bool Swap = false;
2988 if (!LS3.isSingle()) {
2989 if (!LS2.isSingle())
2990 return false;
2991 Swap = true;
2992 }
2993 const LatticeCell &LI = Swap ? LS2 : LS3;
2994 const MachineOperand &OpR2 = Swap ? MI.getOperand(3)
2995 : MI.getOperand(2);
2996 // LI is single here.
2997 APInt A;
2998 if (!constToInt(LI.Value, A) || !A.isSignedIntN(8))
2999 return false;
3000 int64_t V = A.getSExtValue();
3001 const MCInstrDesc &D = (V >= 0) ? HII.get(Hexagon::M2_macsip)
3002 : HII.get(Hexagon::M2_macsin);
3003 if (V < 0)
3004 V = -V;
3005 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3006 unsigned NewR = MRI->createVirtualRegister(RC);
3007 const MachineOperand &Src1 = MI.getOperand(1);
3008 NewMI = BuildMI(B, At, DL, D, NewR)
3009 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg())
3010 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg())
3011 .addImm(V);
3012 replaceAllRegUsesWith(DefR.Reg, NewR);
3013 Changed = true;
3014 break;
3015 }
3016
3017 case Hexagon::A2_and:
3018 {
3019 Register R1(MI.getOperand(1));
3020 Register R2(MI.getOperand(2));
3021 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg))(static_cast <bool> (Inputs.has(R1.Reg) && Inputs
.has(R2.Reg)) ? void (0) : __assert_fail ("Inputs.has(R1.Reg) && Inputs.has(R2.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 3021, __extension__ __PRETTY_FUNCTION__))
;
3022 LatticeCell LS1, LS2;
3023 unsigned CopyOf = 0;
3024 // Check if any of the operands is -1 (i.e. all bits set).
3025 if (getCell(R1, Inputs, LS1) && LS1.isSingle()) {
3026 APInt M1;
3027 if (constToInt(LS1.Value, M1) && !~M1)
3028 CopyOf = 2;
3029 }
3030 else if (getCell(R2, Inputs, LS2) && LS2.isSingle()) {
3031 APInt M1;
3032 if (constToInt(LS2.Value, M1) && !~M1)
3033 CopyOf = 1;
3034 }
3035 if (!CopyOf)
3036 return false;
3037 MachineOperand &SO = MI.getOperand(CopyOf);
3038 Register SR(SO);
3039 Register DefR(MI.getOperand(0));
3040 unsigned NewR = SR.Reg;
3041 if (SR.SubReg) {
3042 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3043 NewR = MRI->createVirtualRegister(RC);
3044 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3045 .addReg(SR.Reg, getRegState(SO), SR.SubReg);
3046 }
3047 replaceAllRegUsesWith(DefR.Reg, NewR);
3048 MRI->clearKillFlags(NewR);
3049 Changed = true;
3050 }
3051 break;
3052
3053 case Hexagon::A2_or:
3054 {
3055 Register R1(MI.getOperand(1));
3056 Register R2(MI.getOperand(2));
3057 assert(Inputs.has(R1.Reg) && Inputs.has(R2.Reg))(static_cast <bool> (Inputs.has(R1.Reg) && Inputs
.has(R2.Reg)) ? void (0) : __assert_fail ("Inputs.has(R1.Reg) && Inputs.has(R2.Reg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 3057, __extension__ __PRETTY_FUNCTION__))
;
3058 LatticeCell LS1, LS2;
3059 unsigned CopyOf = 0;
3060
3061 using P = ConstantProperties;
3062
3063 if (getCell(R1, Inputs, LS1) && (LS1.properties() & P::Zero))
3064 CopyOf = 2;
3065 else if (getCell(R2, Inputs, LS2) && (LS2.properties() & P::Zero))
3066 CopyOf = 1;
3067 if (!CopyOf)
3068 return false;
3069 MachineOperand &SO = MI.getOperand(CopyOf);
3070 Register SR(SO);
3071 Register DefR(MI.getOperand(0));
3072 unsigned NewR = SR.Reg;
3073 if (SR.SubReg) {
3074 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3075 NewR = MRI->createVirtualRegister(RC);
3076 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3077 .addReg(SR.Reg, getRegState(SO), SR.SubReg);
3078 }
3079 replaceAllRegUsesWith(DefR.Reg, NewR);
3080 MRI->clearKillFlags(NewR);
3081 Changed = true;
3082 }
3083 break;
3084 }
3085
3086 if (NewMI) {
3087 // clear all the kill flags of this new instruction.
3088 for (MachineOperand &MO : NewMI->operands())
3089 if (MO.isReg() && MO.isUse())
3090 MO.setIsKill(false);
3091 }
3092
3093 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3094 if (NewMI) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3095 dbgs() << "Rewrite: for " << MI;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3096 if (NewMI != &MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3097 dbgs() << " created " << *NewMI;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3098 elsedo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3099 dbgs() << " modified the instruction itself and created:" << *NewMI;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3100 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
3101 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { { if (NewMI) { dbgs() << "Rewrite: for " <<
MI; if (NewMI != &MI) dbgs() << " created " <<
*NewMI; else dbgs() << " modified the instruction itself and created:"
<< *NewMI; } }; } } while (false)
;
3102
3103 return Changed;
3104}
3105
3106void HexagonConstEvaluator::replaceAllRegUsesWith(unsigned FromReg,
3107 unsigned ToReg) {
3108 assert(TargetRegisterInfo::isVirtualRegister(FromReg))(static_cast <bool> (TargetRegisterInfo::isVirtualRegister
(FromReg)) ? void (0) : __assert_fail ("TargetRegisterInfo::isVirtualRegister(FromReg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 3108, __extension__ __PRETTY_FUNCTION__))
;
3109 assert(TargetRegisterInfo::isVirtualRegister(ToReg))(static_cast <bool> (TargetRegisterInfo::isVirtualRegister
(ToReg)) ? void (0) : __assert_fail ("TargetRegisterInfo::isVirtualRegister(ToReg)"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 3109, __extension__ __PRETTY_FUNCTION__))
;
3110 for (auto I = MRI->use_begin(FromReg), E = MRI->use_end(); I != E;) {
3111 MachineOperand &O = *I;
3112 ++I;
3113 O.setReg(ToReg);
3114 }
3115}
3116
3117bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,
3118 const CellMap &Inputs) {
3119 MachineBasicBlock &B = *BrI.getParent();
3120 unsigned NumOp = BrI.getNumOperands();
3121 if (!NumOp)
3122 return false;
3123
3124 bool FallsThru;
3125 SetVector<const MachineBasicBlock*> Targets;
3126 bool Eval = evaluate(BrI, Inputs, Targets, FallsThru);
3127 unsigned NumTargets = Targets.size();
3128 if (!Eval || NumTargets > 1 || (NumTargets == 1 && FallsThru))
3129 return false;
3130 if (BrI.getOpcode() == Hexagon::J2_jump)
3131 return false;
3132
3133 DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hcp")) { dbgs() << "Rewrite(" << printMBBReference
(B) << "):" << BrI; } } while (false)
;
3134 bool Rewritten = false;
3135 if (NumTargets > 0) {
3136 assert(!FallsThru && "This should have been checked before")(static_cast <bool> (!FallsThru && "This should have been checked before"
) ? void (0) : __assert_fail ("!FallsThru && \"This should have been checked before\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/Target/Hexagon/HexagonConstPropagation.cpp"
, 3136, __extension__ __PRETTY_FUNCTION__))
;
3137 // MIB.addMBB needs non-const pointer.
3138 MachineBasicBlock *TargetB = const_cast<MachineBasicBlock*>(Targets[0]);
3139 bool Moot = B.isLayoutSuccessor(TargetB);
3140 if (!Moot) {
3141 // If we build a branch here, we must make sure that it won't be
3142 // erased as "non-executable". We can't mark any new instructions
3143 // as executable here, so we need to overwrite the BrI, which we
3144 // know is executable.
3145 const MCInstrDesc &JD = HII.get(Hexagon::J2_jump);
3146 auto NI = BuildMI(B, BrI.getIterator(), BrI.getDebugLoc(), JD)
3147 .addMBB(TargetB);
3148 BrI.setDesc(JD);
3149 while (BrI.getNumOperands() > 0)
3150 BrI.RemoveOperand(0);
3151 // This ensures that all implicit operands (e.g. implicit-def %r31, etc)
3152 // are present in the rewritten branch.
3153 for (auto &Op : NI->operands())
3154 BrI.addOperand(Op);
3155 NI->eraseFromParent();
3156 Rewritten = true;
3157 }
3158 }
3159
3160 // Do not erase instructions. A newly created instruction could get
3161 // the same address as an instruction marked as executable during the
3162 // propagation.
3163 if (!Rewritten)
3164 replaceWithNop(BrI);
3165 return true;
3166}
3167
3168FunctionPass *llvm::createHexagonConstPropagationPass() {
3169 return new HexagonConstPropagation();
3170}