Bug Summary

File:lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
Warning:line 441, column 14
Forming reference to null pointer

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonDisassembler.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon/Disassembler -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler -I /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/Target/Hexagon/Disassembler -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp -faddrsig
1//===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE"hexagon-disassembler" "hexagon-disassembler"
11
12#include "MCTargetDesc/HexagonBaseInfo.h"
13#include "MCTargetDesc/HexagonMCChecker.h"
14#include "MCTargetDesc/HexagonMCInstrInfo.h"
15#include "MCTargetDesc/HexagonMCTargetDesc.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/STLExtras.h"
18#include "llvm/MC/MCContext.h"
19#include "llvm/MC/MCDisassembler/MCDisassembler.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCFixedLenDisassembler.h"
22#include "llvm/MC/MCInst.h"
23#include "llvm/MC/MCInstrInfo.h"
24#include "llvm/MC/MCRegisterInfo.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/Support/Endian.h"
27#include "llvm/Support/MathExtras.h"
28#include "llvm/Support/TargetRegistry.h"
29#include "llvm/Support/raw_ostream.h"
30#include <cassert>
31#include <cstddef>
32#include <cstdint>
33#include <memory>
34
35using namespace llvm;
36using namespace Hexagon;
37
38using DecodeStatus = MCDisassembler::DecodeStatus;
39
40namespace {
41
42/// Hexagon disassembler for all Hexagon platforms.
43class HexagonDisassembler : public MCDisassembler {
44public:
45 std::unique_ptr<MCInstrInfo const> const MCII;
46 std::unique_ptr<MCInst *> CurrentBundle;
47 mutable MCInst const *CurrentExtender;
48
49 HexagonDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
50 MCInstrInfo const *MCII)
51 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *),
52 CurrentExtender(nullptr) {}
53
54 DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
55 ArrayRef<uint8_t> Bytes, uint64_t Address,
56 raw_ostream &VStream, raw_ostream &CStream,
57 bool &Complete) const;
58 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
59 ArrayRef<uint8_t> Bytes, uint64_t Address,
60 raw_ostream &VStream,
61 raw_ostream &CStream) const override;
62 void remapInstruction(MCInst &Instr) const;
63};
64
65static uint64_t fullValue(HexagonDisassembler const &Disassembler, MCInst &MI,
66 int64_t Value) {
67 MCInstrInfo MCII = *Disassembler.MCII;
68 if (!Disassembler.CurrentExtender ||
69 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI))
70 return Value;
71 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
72 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
73 int64_t Bits;
74 bool Success =
75 Disassembler.CurrentExtender->getOperand(0).getExpr()->evaluateAsAbsolute(
76 Bits);
77 assert(Success)((Success) ? static_cast<void> (0) : __assert_fail ("Success"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp"
, 77, __PRETTY_FUNCTION__))
;
78 (void)Success;
79 uint64_t Upper26 = static_cast<uint64_t>(Bits);
80 uint64_t Operand = Upper26 | Lower6;
81 return Operand;
82}
83static HexagonDisassembler const &disassembler(void const *Decoder) {
84 return *static_cast<HexagonDisassembler const *>(Decoder);
85}
86template <size_t T>
87static void signedDecoder(MCInst &MI, unsigned tmp, const void *Decoder) {
88 HexagonDisassembler const &Disassembler = disassembler(Decoder);
89 int64_t FullValue = fullValue(Disassembler, MI, SignExtend64<T>(tmp));
90 int64_t Extended = SignExtend64<32>(FullValue);
91 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
92}
93}
94
95// Forward declare these because the auto-generated code will reference them.
96// Definitions are further down.
97
98static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
99 uint64_t Address,
100 const void *Decoder);
101static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
102 unsigned RegNo,
103 uint64_t Address,
104 const void *Decoder);
105static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
106 uint64_t Address,
107 const void *Decoder);
108static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
109 uint64_t Address,
110 const void *Decoder);
111static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
112 uint64_t Address,
113 const void *Decoder);
114static DecodeStatus
115DecodeGeneralDoubleLow8RegsRegisterClass(MCInst &Inst, unsigned RegNo,
116 uint64_t Address, const void *Decoder);
117static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
118 uint64_t Address,
119 const void *Decoder);
120static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
121 uint64_t Address,
122 const void *Decoder);
123static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
124 uint64_t Address,
125 const void *Decoder);
126static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
127 uint64_t Address,
128 const void *Decoder);
129static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
130 uint64_t Address,
131 const void *Decoder);
132static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
133 uint64_t Address,
134 const void *Decoder);
135static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
136 uint64_t Address,
137 const void *Decoder);
138static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
139 uint64_t Address,
140 const void *Decoder);
141
142static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
143 uint64_t Address, const void *Decoder);
144static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
145 uint64_t /*Address*/, const void *Decoder);
146static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
147 const void *Decoder);
148
149static DecodeStatus s4_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
150 const void *Decoder) {
151 signedDecoder<4>(MI, tmp, Decoder);
152 return MCDisassembler::Success;
153}
154static DecodeStatus s29_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
155 const void *Decoder) {
156 signedDecoder<14>(MI, tmp, Decoder);
157 return MCDisassembler::Success;
158}
159static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
160 const void *Decoder) {
161 signedDecoder<8>(MI, tmp, Decoder);
162 return MCDisassembler::Success;
163}
164static DecodeStatus s4_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
165 const void *Decoder) {
166 signedDecoder<7>(MI, tmp, Decoder);
167 return MCDisassembler::Success;
168}
169static DecodeStatus s31_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
170 const void *Decoder) {
171 signedDecoder<12>(MI, tmp, Decoder);
172 return MCDisassembler::Success;
173}
174static DecodeStatus s3_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
175 const void *Decoder) {
176 signedDecoder<3>(MI, tmp, Decoder);
177 return MCDisassembler::Success;
178}
179static DecodeStatus s30_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
180 const void *Decoder) {
181 signedDecoder<13>(MI, tmp, Decoder);
182 return MCDisassembler::Success;
183}
184static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
185 const void *Decoder) {
186 signedDecoder<6>(MI, tmp, Decoder);
187 return MCDisassembler::Success;
188}
189static DecodeStatus s6_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
190 const void *Decoder) {
191 signedDecoder<9>(MI, tmp, Decoder);
192 return MCDisassembler::Success;
193}
194static DecodeStatus s4_1ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
195 const void *Decoder) {
196 signedDecoder<5>(MI, tmp, Decoder);
197 return MCDisassembler::Success;
198}
199static DecodeStatus s4_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t,
200 const void *Decoder) {
201 signedDecoder<6>(MI, tmp, Decoder);
202 return MCDisassembler::Success;
203}
204#include "HexagonGenDisassemblerTables.inc"
205
206static MCDisassembler *createHexagonDisassembler(const Target &T,
207 const MCSubtargetInfo &STI,
208 MCContext &Ctx) {
209 return new HexagonDisassembler(STI, Ctx, T.createMCInstrInfo());
210}
211
212extern "C" void LLVMInitializeHexagonDisassembler() {
213 TargetRegistry::RegisterMCDisassembler(getTheHexagonTarget(),
214 createHexagonDisassembler);
215}
216
217DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
218 ArrayRef<uint8_t> Bytes,
219 uint64_t Address,
220 raw_ostream &os,
221 raw_ostream &cs) const {
222 DecodeStatus Result = DecodeStatus::Success;
223 bool Complete = false;
224 Size = 0;
225
226 *CurrentBundle = &MI;
227 MI.setOpcode(Hexagon::BUNDLE);
228 MI.addOperand(MCOperand::createImm(0));
229 while (Result == Success && !Complete) {
230 if (Bytes.size() < HEXAGON_INSTR_SIZE4)
231 return MCDisassembler::Fail;
232 MCInst *Inst = new (getContext()) MCInst;
233 Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
234 MI.addOperand(MCOperand::createInst(Inst));
235 Size += HEXAGON_INSTR_SIZE4;
236 Bytes = Bytes.slice(HEXAGON_INSTR_SIZE4);
237 }
238 if (Result == MCDisassembler::Fail)
239 return Result;
240 if (Size > HEXAGON_MAX_PACKET_SIZE(4 * 4))
241 return MCDisassembler::Fail;
242 HexagonMCChecker Checker(getContext(), *MCII, STI, MI,
243 *getContext().getRegisterInfo(), false);
244 if (!Checker.check())
245 return MCDisassembler::Fail;
246 remapInstruction(MI);
247 return MCDisassembler::Success;
248}
249
250void HexagonDisassembler::remapInstruction(MCInst &Instr) const {
251 for (auto I: HexagonMCInstrInfo::bundleInstructions(Instr)) {
252 auto &MI = const_cast<MCInst &>(*I.getInst());
253 switch (MI.getOpcode()) {
254 case Hexagon::S2_allocframe:
255 if (MI.getOperand(0).getReg() == Hexagon::R29) {
256 MI.setOpcode(Hexagon::S6_allocframe_to_raw);
257 MI.erase(MI.begin () + 1);
258 MI.erase(MI.begin ());
259 }
260 break;
261 case Hexagon::L2_deallocframe:
262 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
263 MI.getOperand(1).getReg() == Hexagon::R30) {
264 MI.setOpcode(L6_deallocframe_map_to_raw);
265 MI.erase(MI.begin () + 1);
266 MI.erase(MI.begin ());
267 }
268 break;
269 case Hexagon::L4_return:
270 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
271 MI.getOperand(1).getReg() == Hexagon::R30) {
272 MI.setOpcode(L6_return_map_to_raw);
273 MI.erase(MI.begin () + 1);
274 MI.erase(MI.begin ());
275 }
276 break;
277 case Hexagon::L4_return_t:
278 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
279 MI.getOperand(2).getReg() == Hexagon::R30) {
280 MI.setOpcode(L4_return_map_to_raw_t);
281 MI.erase(MI.begin () + 2);
282 MI.erase(MI.begin ());
283 }
284 break;
285 case Hexagon::L4_return_f:
286 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
287 MI.getOperand(2).getReg() == Hexagon::R30) {
288 MI.setOpcode(L4_return_map_to_raw_f);
289 MI.erase(MI.begin () + 2);
290 MI.erase(MI.begin ());
291 }
292 break;
293 case Hexagon::L4_return_tnew_pt:
294 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
295 MI.getOperand(2).getReg() == Hexagon::R30) {
296 MI.setOpcode(L4_return_map_to_raw_tnew_pt);
297 MI.erase(MI.begin () + 2);
298 MI.erase(MI.begin ());
299 }
300 break;
301 case Hexagon::L4_return_fnew_pt:
302 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
303 MI.getOperand(2).getReg() == Hexagon::R30) {
304 MI.setOpcode(L4_return_map_to_raw_fnew_pt);
305 MI.erase(MI.begin () + 2);
306 MI.erase(MI.begin ());
307 }
308 break;
309 case Hexagon::L4_return_tnew_pnt:
310 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
311 MI.getOperand(2).getReg() == Hexagon::R30) {
312 MI.setOpcode(L4_return_map_to_raw_tnew_pnt);
313 MI.erase(MI.begin () + 2);
314 MI.erase(MI.begin ());
315 }
316 break;
317 case Hexagon::L4_return_fnew_pnt:
318 if (MI.getOperand(0).getReg() == Hexagon::D15 &&
319 MI.getOperand(2).getReg() == Hexagon::R30) {
320 MI.setOpcode(L4_return_map_to_raw_fnew_pnt);
321 MI.erase(MI.begin () + 2);
322 MI.erase(MI.begin ());
323 }
324 break;
325 }
326 }
327}
328
329static void adjustDuplex(MCInst &MI, MCContext &Context) {
330 switch (MI.getOpcode()) {
331 case Hexagon::SA1_setin1:
332 MI.insert(MI.begin() + 1,
333 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
334 break;
335 case Hexagon::SA1_dec:
336 MI.insert(MI.begin() + 2,
337 MCOperand::createExpr(MCConstantExpr::create(-1, Context)));
338 break;
339 default:
340 break;
341 }
342}
343
344DecodeStatus HexagonDisassembler::getSingleInstruction(
345 MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
346 raw_ostream &os, raw_ostream &cs, bool &Complete) const {
347 assert(Bytes.size() >= HEXAGON_INSTR_SIZE)((Bytes.size() >= 4) ? static_cast<void> (0) : __assert_fail
("Bytes.size() >= HEXAGON_INSTR_SIZE", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp"
, 347, __PRETTY_FUNCTION__))
;
348
349 uint32_t Instruction = support::endian::read32le(Bytes.data());
350
351 auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
352 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
1
Assuming the condition is false
2
Taking false branch
353 HexagonII::INST_PARSE_LOOP_END) {
354 if (BundleSize == 0)
355 HexagonMCInstrInfo::setInnerLoop(MCB);
356 else if (BundleSize == 1)
357 HexagonMCInstrInfo::setOuterLoop(MCB);
358 else
359 return DecodeStatus::Fail;
360 }
361
362 CurrentExtender = HexagonMCInstrInfo::extenderForIndex(
363 MCB, HexagonMCInstrInfo::bundleSize(MCB));
364
365 DecodeStatus Result = DecodeStatus::Fail;
366 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
3
Assuming the condition is true
4
Taking true branch
367 HexagonII::INST_PARSE_DUPLEX) {
368 unsigned duplexIClass;
369 uint8_t const *DecodeLow, *DecodeHigh;
370 duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
371 switch (duplexIClass) {
5
Control jumps to 'case 12:' at line 422
372 default:
373 return MCDisassembler::Fail;
374 case 0:
375 DecodeLow = DecoderTableSUBINSN_L132;
376 DecodeHigh = DecoderTableSUBINSN_L132;
377 break;
378 case 1:
379 DecodeLow = DecoderTableSUBINSN_L232;
380 DecodeHigh = DecoderTableSUBINSN_L132;
381 break;
382 case 2:
383 DecodeLow = DecoderTableSUBINSN_L232;
384 DecodeHigh = DecoderTableSUBINSN_L232;
385 break;
386 case 3:
387 DecodeLow = DecoderTableSUBINSN_A32;
388 DecodeHigh = DecoderTableSUBINSN_A32;
389 break;
390 case 4:
391 DecodeLow = DecoderTableSUBINSN_L132;
392 DecodeHigh = DecoderTableSUBINSN_A32;
393 break;
394 case 5:
395 DecodeLow = DecoderTableSUBINSN_L232;
396 DecodeHigh = DecoderTableSUBINSN_A32;
397 break;
398 case 6:
399 DecodeLow = DecoderTableSUBINSN_S132;
400 DecodeHigh = DecoderTableSUBINSN_A32;
401 break;
402 case 7:
403 DecodeLow = DecoderTableSUBINSN_S232;
404 DecodeHigh = DecoderTableSUBINSN_A32;
405 break;
406 case 8:
407 DecodeLow = DecoderTableSUBINSN_S132;
408 DecodeHigh = DecoderTableSUBINSN_L132;
409 break;
410 case 9:
411 DecodeLow = DecoderTableSUBINSN_S132;
412 DecodeHigh = DecoderTableSUBINSN_L232;
413 break;
414 case 10:
415 DecodeLow = DecoderTableSUBINSN_S132;
416 DecodeHigh = DecoderTableSUBINSN_S132;
417 break;
418 case 11:
419 DecodeLow = DecoderTableSUBINSN_S232;
420 DecodeHigh = DecoderTableSUBINSN_S132;
421 break;
422 case 12:
423 DecodeLow = DecoderTableSUBINSN_S232;
424 DecodeHigh = DecoderTableSUBINSN_L132;
425 break;
6
Execution continues on line 435
426 case 13:
427 DecodeLow = DecoderTableSUBINSN_S232;
428 DecodeHigh = DecoderTableSUBINSN_L232;
429 break;
430 case 14:
431 DecodeLow = DecoderTableSUBINSN_S232;
432 DecodeHigh = DecoderTableSUBINSN_S232;
433 break;
434 }
435 MI.setOpcode(Hexagon::DuplexIClass0 + duplexIClass);
436 MCInst *MILow = new (getContext()) MCInst;
7
'MILow' initialized to a null pointer value
437 MCInst *MIHigh = new (getContext()) MCInst;
438 auto TmpExtender = CurrentExtender;
439 CurrentExtender =
440 nullptr; // constant extenders in duplex must always be in slot 1
441 Result = decodeInstruction(DecodeLow, *MILow, Instruction & 0x1fff, Address,
8
Forming reference to null pointer
442 this, STI);
443 CurrentExtender = TmpExtender;
444 if (Result != DecodeStatus::Success)
445 return DecodeStatus::Fail;
446 adjustDuplex(*MILow, getContext());
447 Result = decodeInstruction(
448 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
449 if (Result != DecodeStatus::Success)
450 return DecodeStatus::Fail;
451 adjustDuplex(*MIHigh, getContext());
452 MCOperand OPLow = MCOperand::createInst(MILow);
453 MCOperand OPHigh = MCOperand::createInst(MIHigh);
454 MI.addOperand(OPLow);
455 MI.addOperand(OPHigh);
456 Complete = true;
457 } else {
458 if ((Instruction & HexagonII::INST_PARSE_MASK) ==
459 HexagonII::INST_PARSE_PACKET_END)
460 Complete = true;
461
462 if (CurrentExtender != nullptr)
463 Result = decodeInstruction(DecoderTableMustExtend32, MI, Instruction,
464 Address, this, STI);
465
466 if (Result != MCDisassembler::Success)
467 Result = decodeInstruction(DecoderTable32, MI, Instruction, Address, this,
468 STI);
469
470 if (Result != MCDisassembler::Success &&
471 STI.getFeatureBits()[Hexagon::ExtensionHVX])
472 Result = decodeInstruction(DecoderTableEXT_mmvec32, MI, Instruction,
473 Address, this, STI);
474
475 }
476
477 switch (MI.getOpcode()) {
478 case Hexagon::J4_cmpeqn1_f_jumpnv_nt:
479 case Hexagon::J4_cmpeqn1_f_jumpnv_t:
480 case Hexagon::J4_cmpeqn1_fp0_jump_nt:
481 case Hexagon::J4_cmpeqn1_fp0_jump_t:
482 case Hexagon::J4_cmpeqn1_fp1_jump_nt:
483 case Hexagon::J4_cmpeqn1_fp1_jump_t:
484 case Hexagon::J4_cmpeqn1_t_jumpnv_nt:
485 case Hexagon::J4_cmpeqn1_t_jumpnv_t:
486 case Hexagon::J4_cmpeqn1_tp0_jump_nt:
487 case Hexagon::J4_cmpeqn1_tp0_jump_t:
488 case Hexagon::J4_cmpeqn1_tp1_jump_nt:
489 case Hexagon::J4_cmpeqn1_tp1_jump_t:
490 case Hexagon::J4_cmpgtn1_f_jumpnv_nt:
491 case Hexagon::J4_cmpgtn1_f_jumpnv_t:
492 case Hexagon::J4_cmpgtn1_fp0_jump_nt:
493 case Hexagon::J4_cmpgtn1_fp0_jump_t:
494 case Hexagon::J4_cmpgtn1_fp1_jump_nt:
495 case Hexagon::J4_cmpgtn1_fp1_jump_t:
496 case Hexagon::J4_cmpgtn1_t_jumpnv_nt:
497 case Hexagon::J4_cmpgtn1_t_jumpnv_t:
498 case Hexagon::J4_cmpgtn1_tp0_jump_nt:
499 case Hexagon::J4_cmpgtn1_tp0_jump_t:
500 case Hexagon::J4_cmpgtn1_tp1_jump_nt:
501 case Hexagon::J4_cmpgtn1_tp1_jump_t:
502 MI.insert(MI.begin() + 1,
503 MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
504 break;
505 default:
506 break;
507 }
508
509 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) {
510 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI);
511 MCOperand &MCO = MI.getOperand(OpIndex);
512 assert(MCO.isReg() && "New value consumers must be registers")((MCO.isReg() && "New value consumers must be registers"
) ? static_cast<void> (0) : __assert_fail ("MCO.isReg() && \"New value consumers must be registers\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp"
, 512, __PRETTY_FUNCTION__))
;
513 unsigned Register =
514 getContext().getRegisterInfo()->getEncodingValue(MCO.getReg());
515 if ((Register & 0x6) == 0)
516 // HexagonPRM 10.11 Bit 1-2 == 0 is reserved
517 return MCDisassembler::Fail;
518 unsigned Lookback = (Register & 0x6) >> 1;
519 unsigned Offset = 1;
520 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI);
521 bool PrevVector = false;
522 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
523 auto i = Instructions.end() - 1;
524 for (auto n = Instructions.begin() - 1;; --i, ++Offset) {
525 if (i == n)
526 // Couldn't find producer
527 return MCDisassembler::Fail;
528 bool CurrentVector = HexagonMCInstrInfo::isVector(*MCII, *i->getInst());
529 if (Vector && !CurrentVector)
530 // Skip scalars when calculating distances for vectors
531 ++Lookback;
532 if (HexagonMCInstrInfo::isImmext(*i->getInst()) && (Vector == PrevVector))
533 ++Lookback;
534 PrevVector = CurrentVector;
535 if (Offset == Lookback)
536 break;
537 }
538 auto const &Inst = *i->getInst();
539 bool SubregBit = (Register & 0x1) != 0;
540 if (HexagonMCInstrInfo::hasNewValue2(*MCII, Inst)) {
541 // If subreg bit is set we're selecting the second produced newvalue
542 unsigned Producer = SubregBit ?
543 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg() :
544 HexagonMCInstrInfo::getNewValueOperand2(*MCII, Inst).getReg();
545 assert(Producer != Hexagon::NoRegister)((Producer != Hexagon::NoRegister) ? static_cast<void> (
0) : __assert_fail ("Producer != Hexagon::NoRegister", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp"
, 545, __PRETTY_FUNCTION__))
;
546 MCO.setReg(Producer);
547 } else if (HexagonMCInstrInfo::hasNewValue(*MCII, Inst)) {
548 unsigned Producer =
549 HexagonMCInstrInfo::getNewValueOperand(*MCII, Inst).getReg();
550 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
551 Producer = ((Producer - Hexagon::W0) << 1) + SubregBit + Hexagon::V0;
552 else if (SubregBit)
553 // Hexagon PRM 10.11 New-value operands
554 // Nt[0] is reserved and should always be encoded as zero.
555 return MCDisassembler::Fail;
556 assert(Producer != Hexagon::NoRegister)((Producer != Hexagon::NoRegister) ? static_cast<void> (
0) : __assert_fail ("Producer != Hexagon::NoRegister", "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp"
, 556, __PRETTY_FUNCTION__))
;
557 MCO.setReg(Producer);
558 } else
559 return MCDisassembler::Fail;
560 }
561
562 if (CurrentExtender != nullptr) {
563 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI)
564 ? *MI.getOperand(1).getInst()
565 : MI;
566 if (!HexagonMCInstrInfo::isExtendable(*MCII, Inst) &&
567 !HexagonMCInstrInfo::isExtended(*MCII, Inst))
568 return MCDisassembler::Fail;
569 }
570 return Result;
571}
572
573static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
574 ArrayRef<MCPhysReg> Table) {
575 if (RegNo < Table.size()) {
576 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
577 return MCDisassembler::Success;
578 }
579
580 return MCDisassembler::Fail;
581}
582
583static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
584 uint64_t Address,
585 const void *Decoder) {
586 return DecodeIntRegsRegisterClass(Inst, RegNo, Address, Decoder);
587}
588
589static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
590 uint64_t Address,
591 const void *Decoder) {
592 static const MCPhysReg IntRegDecoderTable[] = {
593 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
594 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
595 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
596 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
597 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
598 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
599 Hexagon::R30, Hexagon::R31};
600
601 return DecodeRegisterClass(Inst, RegNo, IntRegDecoderTable);
602}
603
604static DecodeStatus DecodeGeneralSubRegsRegisterClass(MCInst &Inst,
605 unsigned RegNo,
606 uint64_t Address,
607 const void *Decoder) {
608 static const MCPhysReg GeneralSubRegDecoderTable[] = {
609 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3,
610 Hexagon::R4, Hexagon::R5, Hexagon::R6, Hexagon::R7,
611 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
612 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
613 };
614
615 return DecodeRegisterClass(Inst, RegNo, GeneralSubRegDecoderTable);
616}
617
618static DecodeStatus DecodeHvxVRRegisterClass(MCInst &Inst, unsigned RegNo,
619 uint64_t /*Address*/,
620 const void *Decoder) {
621 static const MCPhysReg HvxVRDecoderTable[] = {
622 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
623 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
624 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
625 Hexagon::V15, Hexagon::V16, Hexagon::V17, Hexagon::V18, Hexagon::V19,
626 Hexagon::V20, Hexagon::V21, Hexagon::V22, Hexagon::V23, Hexagon::V24,
627 Hexagon::V25, Hexagon::V26, Hexagon::V27, Hexagon::V28, Hexagon::V29,
628 Hexagon::V30, Hexagon::V31};
629
630 return DecodeRegisterClass(Inst, RegNo, HvxVRDecoderTable);
631}
632
633static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
634 uint64_t /*Address*/,
635 const void *Decoder) {
636 static const MCPhysReg DoubleRegDecoderTable[] = {
637 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
638 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
639 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
640 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
641
642 return DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable);
643}
644
645static DecodeStatus DecodeGeneralDoubleLow8RegsRegisterClass(
646 MCInst &Inst, unsigned RegNo, uint64_t /*Address*/, const void *Decoder) {
647 static const MCPhysReg GeneralDoubleLow8RegDecoderTable[] = {
648 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
649 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11};
650
651 return DecodeRegisterClass(Inst, RegNo, GeneralDoubleLow8RegDecoderTable);
652}
653
654static DecodeStatus DecodeHvxWRRegisterClass(MCInst &Inst, unsigned RegNo,
655 uint64_t /*Address*/,
656 const void *Decoder) {
657 static const MCPhysReg HvxWRDecoderTable[] = {
658 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3,
659 Hexagon::W4, Hexagon::W5, Hexagon::W6, Hexagon::W7,
660 Hexagon::W8, Hexagon::W9, Hexagon::W10, Hexagon::W11,
661 Hexagon::W12, Hexagon::W13, Hexagon::W14, Hexagon::W15};
662
663 return (DecodeRegisterClass(Inst, RegNo >> 1, HvxWRDecoderTable));
664}
665
666static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
667 uint64_t /*Address*/,
668 const void *Decoder) {
669 static const MCPhysReg PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
670 Hexagon::P2, Hexagon::P3};
671
672 return DecodeRegisterClass(Inst, RegNo, PredRegDecoderTable);
673}
674
675static DecodeStatus DecodeHvxQRRegisterClass(MCInst &Inst, unsigned RegNo,
676 uint64_t /*Address*/,
677 const void *Decoder) {
678 static const MCPhysReg HvxQRDecoderTable[] = {Hexagon::Q0, Hexagon::Q1,
679 Hexagon::Q2, Hexagon::Q3};
680
681 return DecodeRegisterClass(Inst, RegNo, HvxQRDecoderTable);
682}
683
684static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
685 uint64_t /*Address*/,
686 const void *Decoder) {
687 using namespace Hexagon;
688
689 static const MCPhysReg CtrlRegDecoderTable[] = {
690 /* 0 */ SA0, LC0, SA1, LC1,
691 /* 4 */ P3_0, C5, M0, M1,
692 /* 8 */ USR, PC, UGP, GP,
693 /* 12 */ CS0, CS1, UPCYCLELO, UPCYCLEHI,
694 /* 16 */ FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI,
695 /* 20 */ 0, 0, 0, 0,
696 /* 24 */ 0, 0, 0, 0,
697 /* 28 */ 0, 0, UTIMERLO, UTIMERHI
698 };
699
700 if (RegNo >= array_lengthof(CtrlRegDecoderTable))
701 return MCDisassembler::Fail;
702
703 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
704 if (CtrlRegDecoderTable[RegNo] == NoRegister)
705 return MCDisassembler::Fail;
706
707 unsigned Register = CtrlRegDecoderTable[RegNo];
708 Inst.addOperand(MCOperand::createReg(Register));
709 return MCDisassembler::Success;
710}
711
712static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
713 uint64_t /*Address*/,
714 const void *Decoder) {
715 using namespace Hexagon;
716
717 static const MCPhysReg CtrlReg64DecoderTable[] = {
718 /* 0 */ C1_0, 0, C3_2, 0,
719 /* 4 */ C5_4, 0, C7_6, 0,
720 /* 8 */ C9_8, 0, C11_10, 0,
721 /* 12 */ CS, 0, UPCYCLE, 0,
722 /* 16 */ C17_16, 0, PKTCOUNT, 0,
723 /* 20 */ 0, 0, 0, 0,
724 /* 24 */ 0, 0, 0, 0,
725 /* 28 */ 0, 0, UTIMER, 0
726 };
727
728 if (RegNo >= array_lengthof(CtrlReg64DecoderTable))
729 return MCDisassembler::Fail;
730
731 static_assert(NoRegister == 0, "Expecting NoRegister to be 0");
732 if (CtrlReg64DecoderTable[RegNo] == NoRegister)
733 return MCDisassembler::Fail;
734
735 unsigned Register = CtrlReg64DecoderTable[RegNo];
736 Inst.addOperand(MCOperand::createReg(Register));
737 return MCDisassembler::Success;
738}
739
740static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
741 uint64_t /*Address*/,
742 const void *Decoder) {
743 unsigned Register = 0;
744 switch (RegNo) {
745 case 0:
746 Register = Hexagon::M0;
747 break;
748 case 1:
749 Register = Hexagon::M1;
750 break;
751 default:
752 return MCDisassembler::Fail;
753 }
754 Inst.addOperand(MCOperand::createReg(Register));
755 return MCDisassembler::Success;
756}
757
758static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
759 uint64_t /*Address*/,
760 const void *Decoder) {
761 HexagonDisassembler const &Disassembler = disassembler(Decoder);
762 int64_t FullValue = fullValue(Disassembler, MI, tmp);
763 assert(FullValue >= 0 && "Negative in unsigned decoder")((FullValue >= 0 && "Negative in unsigned decoder"
) ? static_cast<void> (0) : __assert_fail ("FullValue >= 0 && \"Negative in unsigned decoder\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp"
, 763, __PRETTY_FUNCTION__))
;
764 HexagonMCInstrInfo::addConstant(MI, FullValue, Disassembler.getContext());
765 return MCDisassembler::Success;
766}
767
768static DecodeStatus s32_0ImmDecoder(MCInst &MI, unsigned tmp,
769 uint64_t /*Address*/, const void *Decoder) {
770 HexagonDisassembler const &Disassembler = disassembler(Decoder);
771 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
772 tmp = SignExtend64(tmp, Bits);
773 signedDecoder<32>(MI, tmp, Decoder);
774 return MCDisassembler::Success;
775}
776
777// custom decoder for various jump/call immediates
778static DecodeStatus brtargetDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
779 const void *Decoder) {
780 HexagonDisassembler const &Disassembler = disassembler(Decoder);
781 unsigned Bits = HexagonMCInstrInfo::getExtentBits(*Disassembler.MCII, MI);
782 // r13_2 is not extendable, so if there are no extent bits, it's r13_2
783 if (Bits == 0)
784 Bits = 15;
785 uint64_t FullValue = fullValue(Disassembler, MI, SignExtend64(tmp, Bits));
786 uint32_t Extended = FullValue + Address;
787 if (!Disassembler.tryAddingSymbolicOperand(MI, Extended, Address, true, 0, 4))
788 HexagonMCInstrInfo::addConstant(MI, Extended, Disassembler.getContext());
789 return MCDisassembler::Success;
790}
791
792static DecodeStatus DecodeGuestRegsRegisterClass(MCInst &Inst, unsigned RegNo,
793 uint64_t /*Address*/,
794 const void *Decoder) {
795 using namespace Hexagon;
796
797 static const MCPhysReg GuestRegDecoderTable[] = {
798 /* 0 */ GELR, GSR, GOSP, G3,
799 /* 4 */ G4, G5, G6, G7,
800 /* 8 */ G8, G9, G10, G11,
801 /* 12 */ G12, G13, G14, G15,
802 /* 16 */ GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7,
803 /* 20 */ G20, G21, G22, G23,
804 /* 24 */ GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1,
805 /* 28 */ GPMUCNT2, GPMUCNT3, G30, G31
806 };
807
808 if (RegNo >= array_lengthof(GuestRegDecoderTable))
809 return MCDisassembler::Fail;
810 if (GuestRegDecoderTable[RegNo] == Hexagon::NoRegister)
811 return MCDisassembler::Fail;
812
813 unsigned Register = GuestRegDecoderTable[RegNo];
814 Inst.addOperand(MCOperand::createReg(Register));
815 return MCDisassembler::Success;
816}
817
818static DecodeStatus DecodeGuestRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
819 uint64_t /*Address*/,
820 const void *Decoder) {
821 using namespace Hexagon;
822
823 static const MCPhysReg GuestReg64DecoderTable[] = {
824 /* 0 */ G1_0, 0, G3_2, 0,
825 /* 4 */ G5_4, 0, G7_6, 0,
826 /* 8 */ G9_8, 0, G11_10, 0,
827 /* 12 */ G13_12, 0, G15_14, 0,
828 /* 16 */ G17_16, 0, G19_18, 0,
829 /* 20 */ G21_20, 0, G23_22, 0,
830 /* 24 */ G25_24, 0, G27_26, 0,
831 /* 28 */ G29_28, 0, G31_30, 0
832 };
833
834 if (RegNo >= array_lengthof(GuestReg64DecoderTable))
835 return MCDisassembler::Fail;
836 if (GuestReg64DecoderTable[RegNo] == Hexagon::NoRegister)
837 return MCDisassembler::Fail;
838
839 unsigned Register = GuestReg64DecoderTable[RegNo];
840 Inst.addOperand(MCOperand::createReg(Register));
841 return MCDisassembler::Success;
842}