Bug Summary

File:lib/Target/Hexagon/HexagonISelLowering.cpp
Warning:line 2824, column 16
Value stored to 'Subreg' during its initialization is never read

Annotated Source Code

1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Hexagon uses to lower LLVM code
11// into a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "Hexagon.h"
16#include "HexagonISelLowering.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonRegisterInfo.h"
19#include "HexagonSubtarget.h"
20#include "HexagonTargetMachine.h"
21#include "HexagonTargetObjectFile.h"
22#include "llvm/ADT/APInt.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/CodeGen/CallingConvLower.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/RuntimeLibcalls.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAG.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/IR/BasicBlock.h"
34#include "llvm/IR/CallingConv.h"
35#include "llvm/IR/DataLayout.h"
36#include "llvm/IR/DerivedTypes.h"
37#include "llvm/IR/Function.h"
38#include "llvm/IR/GlobalValue.h"
39#include "llvm/IR/InlineAsm.h"
40#include "llvm/IR/Instructions.h"
41#include "llvm/IR/Intrinsics.h"
42#include "llvm/IR/Module.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include "llvm/MC/MCRegisterInfo.h"
46#include "llvm/Support/Casting.h"
47#include "llvm/Support/CodeGen.h"
48#include "llvm/Support/CommandLine.h"
49#include "llvm/Support/Debug.h"
50#include "llvm/Support/ErrorHandling.h"
51#include "llvm/Support/MathExtras.h"
52#include "llvm/Support/raw_ostream.h"
53#include "llvm/Target/TargetCallingConv.h"
54#include "llvm/Target/TargetMachine.h"
55#include <algorithm>
56#include <cassert>
57#include <cstddef>
58#include <cstdint>
59#include <limits>
60#include <utility>
61
62using namespace llvm;
63
64#define DEBUG_TYPE"hexagon-lowering" "hexagon-lowering"
65
66static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
67 cl::init(true), cl::Hidden,
68 cl::desc("Control jump table emission on Hexagon target"));
69
70static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
71 cl::Hidden, cl::ZeroOrMore, cl::init(false),
72 cl::desc("Enable Hexagon SDNode scheduling"));
73
74static cl::opt<bool> EnableFastMath("ffast-math",
75 cl::Hidden, cl::ZeroOrMore, cl::init(false),
76 cl::desc("Enable Fast Math processing"));
77
78static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
79 cl::Hidden, cl::ZeroOrMore, cl::init(5),
80 cl::desc("Set minimum jump tables"));
81
82static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
83 cl::Hidden, cl::ZeroOrMore, cl::init(6),
84 cl::desc("Max #stores to inline memcpy"));
85
86static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
87 cl::Hidden, cl::ZeroOrMore, cl::init(4),
88 cl::desc("Max #stores to inline memcpy"));
89
90static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
91 cl::Hidden, cl::ZeroOrMore, cl::init(6),
92 cl::desc("Max #stores to inline memmove"));
93
94static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
95 cl::Hidden, cl::ZeroOrMore, cl::init(4),
96 cl::desc("Max #stores to inline memmove"));
97
98static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
99 cl::Hidden, cl::ZeroOrMore, cl::init(8),
100 cl::desc("Max #stores to inline memset"));
101
102static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
103 cl::Hidden, cl::ZeroOrMore, cl::init(4),
104 cl::desc("Max #stores to inline memset"));
105
106
107namespace {
108
109 class HexagonCCState : public CCState {
110 unsigned NumNamedVarArgParams;
111
112 public:
113 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
114 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
115 int NumNamedVarArgParams)
116 : CCState(CC, isVarArg, MF, locs, C),
117 NumNamedVarArgParams(NumNamedVarArgParams) {}
118
119 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
120 };
121
122 enum StridedLoadKind {
123 Even = 0,
124 Odd,
125 NoPattern
126 };
127
128} // end anonymous namespace
129
130// Implement calling convention for Hexagon.
131
132static bool isHvxVectorType(MVT ty);
133
134static bool
135CC_Hexagon(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
138
139static bool
140CC_Hexagon32(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
143
144static bool
145CC_Hexagon64(unsigned ValNo, MVT ValVT,
146 MVT LocVT, CCValAssign::LocInfo LocInfo,
147 ISD::ArgFlagsTy ArgFlags, CCState &State);
148
149static bool
150CC_HexagonVector(unsigned ValNo, MVT ValVT,
151 MVT LocVT, CCValAssign::LocInfo LocInfo,
152 ISD::ArgFlagsTy ArgFlags, CCState &State);
153
154static bool
155RetCC_Hexagon(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, CCState &State);
158
159static bool
160RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
161 MVT LocVT, CCValAssign::LocInfo LocInfo,
162 ISD::ArgFlagsTy ArgFlags, CCState &State);
163
164static bool
165RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
166 MVT LocVT, CCValAssign::LocInfo LocInfo,
167 ISD::ArgFlagsTy ArgFlags, CCState &State);
168
169static bool
170RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
171 MVT LocVT, CCValAssign::LocInfo LocInfo,
172 ISD::ArgFlagsTy ArgFlags, CCState &State);
173
174static bool
175CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State) {
178 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
179
180 if (ValNo < HState.getNumNamedVarArgParams()) {
181 // Deal with named arguments.
182 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
183 }
184
185 // Deal with un-named arguments.
186 unsigned Offset;
187 if (ArgFlags.isByVal()) {
188 // If pass-by-value, the size allocated on stack is decided
189 // by ArgFlags.getByValSize(), not by the size of LocVT.
190 Offset = State.AllocateStack(ArgFlags.getByValSize(),
191 ArgFlags.getByValAlign());
192 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
193 return false;
194 }
195 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
196 LocVT = MVT::i32;
197 ValVT = MVT::i32;
198 if (ArgFlags.isSExt())
199 LocInfo = CCValAssign::SExt;
200 else if (ArgFlags.isZExt())
201 LocInfo = CCValAssign::ZExt;
202 else
203 LocInfo = CCValAssign::AExt;
204 }
205 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
206 Offset = State.AllocateStack(4, 4);
207 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
208 return false;
209 }
210 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
211 Offset = State.AllocateStack(8, 8);
212 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
213 return false;
214 }
215 if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
216 LocVT == MVT::v16i8) {
217 Offset = State.AllocateStack(16, 16);
218 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
219 return false;
220 }
221 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
222 LocVT == MVT::v32i8) {
223 Offset = State.AllocateStack(32, 32);
224 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
225 return false;
226 }
227 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
228 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
229 Offset = State.AllocateStack(64, 64);
230 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
231 return false;
232 }
233 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
234 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
235 Offset = State.AllocateStack(128, 128);
236 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
237 return false;
238 }
239 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
240 LocVT == MVT::v256i8) {
241 Offset = State.AllocateStack(256, 256);
242 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
243 return false;
244 }
245
246 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 246)
;
247}
248
249static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
250 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
251 if (ArgFlags.isByVal()) {
252 // Passed on stack.
253 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
254 ArgFlags.getByValAlign());
255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
256 return false;
257 }
258
259 if (LocVT == MVT::i1) {
260 LocVT = MVT::i32;
261 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
262 LocVT = MVT::i32;
263 ValVT = MVT::i32;
264 if (ArgFlags.isSExt())
265 LocInfo = CCValAssign::SExt;
266 else if (ArgFlags.isZExt())
267 LocInfo = CCValAssign::ZExt;
268 else
269 LocInfo = CCValAssign::AExt;
270 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
271 LocVT = MVT::i32;
272 LocInfo = CCValAssign::BCvt;
273 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
274 LocVT = MVT::i64;
275 LocInfo = CCValAssign::BCvt;
276 }
277
278 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
279 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
280 return false;
281 }
282
283 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
284 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
285 return false;
286 }
287
288 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
289 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
290 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
291 return false;
292 }
293
294 if (isHvxVectorType(LocVT)) {
295 if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
296 return false;
297 }
298
299 return true; // CC didn't match.
300}
301
302
303static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
304 MVT LocVT, CCValAssign::LocInfo LocInfo,
305 ISD::ArgFlagsTy ArgFlags, CCState &State) {
306 static const MCPhysReg RegList[] = {
307 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
308 Hexagon::R5
309 };
310 if (unsigned Reg = State.AllocateReg(RegList)) {
311 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
312 return false;
313 }
314
315 unsigned Offset = State.AllocateStack(4, 4);
316 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
317 return false;
318}
319
320static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
321 MVT LocVT, CCValAssign::LocInfo LocInfo,
322 ISD::ArgFlagsTy ArgFlags, CCState &State) {
323 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
324 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
325 return false;
326 }
327
328 static const MCPhysReg RegList1[] = {
329 Hexagon::D1, Hexagon::D2
330 };
331 static const MCPhysReg RegList2[] = {
332 Hexagon::R1, Hexagon::R3
333 };
334 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
335 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
336 return false;
337 }
338
339 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
340 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
341 return false;
342}
343
344static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
345 MVT LocVT, CCValAssign::LocInfo LocInfo,
346 ISD::ArgFlagsTy ArgFlags, CCState &State) {
347 static const MCPhysReg VecLstS[] = {
348 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
349 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
350 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
351 Hexagon::V15
352 };
353 static const MCPhysReg VecLstD[] = {
354 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
355 Hexagon::W5, Hexagon::W6, Hexagon::W7
356 };
357 auto &MF = State.getMachineFunction();
358 auto &HST = MF.getSubtarget<HexagonSubtarget>();
359 bool UseHVX = HST.useHVXOps();
360 bool UseHVXDbl = HST.useHVXDblOps();
361
362 if ((UseHVX && !UseHVXDbl) &&
363 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
364 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
365 if (unsigned Reg = State.AllocateReg(VecLstS)) {
366 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
367 return false;
368 }
369 unsigned Offset = State.AllocateStack(64, 64);
370 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
371 return false;
372 }
373 if ((UseHVX && !UseHVXDbl) &&
374 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
375 LocVT == MVT::v128i8)) {
376 if (unsigned Reg = State.AllocateReg(VecLstD)) {
377 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
378 return false;
379 }
380 unsigned Offset = State.AllocateStack(128, 128);
381 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
382 return false;
383 }
384 // 128B Mode
385 if ((UseHVX && UseHVXDbl) &&
386 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
387 LocVT == MVT::v256i8)) {
388 if (unsigned Reg = State.AllocateReg(VecLstD)) {
389 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
390 return false;
391 }
392 unsigned Offset = State.AllocateStack(256, 256);
393 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
394 return false;
395 }
396 if ((UseHVX && UseHVXDbl) &&
397 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
398 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
399 if (unsigned Reg = State.AllocateReg(VecLstS)) {
400 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
401 return false;
402 }
403 unsigned Offset = State.AllocateStack(128, 128);
404 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
405 return false;
406 }
407 return true;
408}
409
410static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
411 MVT LocVT, CCValAssign::LocInfo LocInfo,
412 ISD::ArgFlagsTy ArgFlags, CCState &State) {
413 auto &MF = State.getMachineFunction();
414 auto &HST = MF.getSubtarget<HexagonSubtarget>();
415 bool UseHVX = HST.useHVXOps();
416 bool UseHVXDbl = HST.useHVXDblOps();
417
418 if (LocVT == MVT::i1) {
419 // Return values of type MVT::i1 still need to be assigned to R0, but
420 // the value type needs to remain i1. LowerCallResult will deal with it,
421 // but it needs to recognize i1 as the value type.
422 LocVT = MVT::i32;
423 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
424 LocVT = MVT::i32;
425 ValVT = MVT::i32;
426 if (ArgFlags.isSExt())
427 LocInfo = CCValAssign::SExt;
428 else if (ArgFlags.isZExt())
429 LocInfo = CCValAssign::ZExt;
430 else
431 LocInfo = CCValAssign::AExt;
432 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
433 LocVT = MVT::i32;
434 LocInfo = CCValAssign::BCvt;
435 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
436 LocVT = MVT::i64;
437 LocInfo = CCValAssign::BCvt;
438 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
439 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
440 LocVT == MVT::v512i1) {
441 LocVT = MVT::v16i32;
442 ValVT = MVT::v16i32;
443 LocInfo = CCValAssign::Full;
444 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
445 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
446 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
447 LocVT = MVT::v32i32;
448 ValVT = MVT::v32i32;
449 LocInfo = CCValAssign::Full;
450 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
451 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
452 LocVT = MVT::v64i32;
453 ValVT = MVT::v64i32;
454 LocInfo = CCValAssign::Full;
455 }
456 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
457 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
458 return false;
459 }
460
461 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
462 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
463 return false;
464 }
465 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
466 if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
467 return false;
468 }
469 return true; // CC didn't match.
470}
471
472static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
473 MVT LocVT, CCValAssign::LocInfo LocInfo,
474 ISD::ArgFlagsTy ArgFlags, CCState &State) {
475 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
476 // Note that use of registers beyond R1 is not ABI compliant. However there
477 // are (experimental) IR passes which generate internal functions that
478 // return structs using these additional registers.
479 static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
480 Hexagon::R2, Hexagon::R3,
481 Hexagon::R4, Hexagon::R5 };
482 if (unsigned Reg = State.AllocateReg(RegList)) {
483 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
484 return false;
485 }
486 }
487
488 return true;
489}
490
491static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
492 MVT LocVT, CCValAssign::LocInfo LocInfo,
493 ISD::ArgFlagsTy ArgFlags, CCState &State) {
494 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
495 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
496 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
497 return false;
498 }
499 }
500
501 return true;
502}
503
504static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
505 MVT LocVT, CCValAssign::LocInfo LocInfo,
506 ISD::ArgFlagsTy ArgFlags, CCState &State) {
507 auto &MF = State.getMachineFunction();
508 auto &HST = MF.getSubtarget<HexagonSubtarget>();
509 bool UseHVX = HST.useHVXOps();
510 bool UseHVXDbl = HST.useHVXDblOps();
511
512 if (LocVT == MVT::v16i32) {
513 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
514 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
515 return false;
516 }
517 } else if (LocVT == MVT::v32i32) {
518 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
519 if (unsigned Reg = State.AllocateReg(Req)) {
520 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
521 return false;
522 }
523 } else if (LocVT == MVT::v64i32) {
524 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
525 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
526 return false;
527 }
528 }
529
530 return true;
531}
532
533void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
534 if (VT != PromotedLdStVT) {
535 setOperationAction(ISD::LOAD, VT, Promote);
536 AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
537
538 setOperationAction(ISD::STORE, VT, Promote);
539 AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
540 }
541}
542
543SDValue
544HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
545 const {
546 return SDValue();
547}
548
549/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
550/// by "Src" to address "Dst" of size "Size". Alignment information is
551/// specified by the specific parameter attribute. The copy will be passed as
552/// a byval function parameter. Sometimes what we are copying is the end of a
553/// larger object, the part that does not fit in registers.
554static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
555 SDValue Chain, ISD::ArgFlagsTy Flags,
556 SelectionDAG &DAG, const SDLoc &dl) {
557 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
558 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
559 /*isVolatile=*/false, /*AlwaysInline=*/false,
560 /*isTailCall=*/false,
561 MachinePointerInfo(), MachinePointerInfo());
562}
563
564static bool isHvxVectorType(MVT Ty) {
565 switch (Ty.SimpleTy) {
566 case MVT::v8i64:
567 case MVT::v16i32:
568 case MVT::v32i16:
569 case MVT::v64i8:
570 case MVT::v16i64:
571 case MVT::v32i32:
572 case MVT::v64i16:
573 case MVT::v128i8:
574 case MVT::v32i64:
575 case MVT::v64i32:
576 case MVT::v128i16:
577 case MVT::v256i8:
578 case MVT::v512i1:
579 case MVT::v1024i1:
580 return true;
581 default:
582 return false;
583 }
584}
585
586bool
587HexagonTargetLowering::CanLowerReturn(
588 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
589 const SmallVectorImpl<ISD::OutputArg> &Outs,
590 LLVMContext &Context) const {
591 SmallVector<CCValAssign, 16> RVLocs;
592 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
593 return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
594}
595
596// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
597// passed by value, the function prototype is modified to return void and
598// the value is stored in memory pointed by a pointer passed by caller.
599SDValue
600HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
601 bool isVarArg,
602 const SmallVectorImpl<ISD::OutputArg> &Outs,
603 const SmallVectorImpl<SDValue> &OutVals,
604 const SDLoc &dl, SelectionDAG &DAG) const {
605 // CCValAssign - represent the assignment of the return value to locations.
606 SmallVector<CCValAssign, 16> RVLocs;
607
608 // CCState - Info about the registers and stack slot.
609 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
610 *DAG.getContext());
611
612 // Analyze return values of ISD::RET
613 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
614
615 SDValue Flag;
616 SmallVector<SDValue, 4> RetOps(1, Chain);
617
618 // Copy the result values into the output registers.
619 for (unsigned i = 0; i != RVLocs.size(); ++i) {
620 CCValAssign &VA = RVLocs[i];
621
622 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
623
624 // Guarantee that all emitted copies are stuck together with flags.
625 Flag = Chain.getValue(1);
626 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
627 }
628
629 RetOps[0] = Chain; // Update chain.
630
631 // Add the flag if we have it.
632 if (Flag.getNode())
633 RetOps.push_back(Flag);
634
635 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
636}
637
638bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
639 // If either no tail call or told not to tail call at all, don't.
640 auto Attr =
641 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
642 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
643 return false;
644
645 return true;
646}
647
648/// LowerCallResult - Lower the result values of an ISD::CALL into the
649/// appropriate copies out of appropriate physical registers. This assumes that
650/// Chain/Glue are the input chain/glue to use, and that TheCall is the call
651/// being lowered. Returns a SDNode with the same number of values as the
652/// ISD::CALL.
653SDValue HexagonTargetLowering::LowerCallResult(
654 SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool isVarArg,
655 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
656 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
657 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
658 // Assign locations to each value returned by this call.
659 SmallVector<CCValAssign, 16> RVLocs;
660
661 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
662 *DAG.getContext());
663
664 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
665
666 // Copy all of the result registers out of their specified physreg.
667 for (unsigned i = 0; i != RVLocs.size(); ++i) {
668 SDValue RetVal;
669 if (RVLocs[i].getValVT() == MVT::i1) {
670 // Return values of type MVT::i1 require special handling. The reason
671 // is that MVT::i1 is associated with the PredRegs register class, but
672 // values of that type are still returned in R0. Generate an explicit
673 // copy into a predicate register from R0, and treat the value of the
674 // predicate register as the call result.
675 auto &MRI = DAG.getMachineFunction().getRegInfo();
676 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
677 MVT::i32, Glue);
678 // FR0 = (Value, Chain, Glue)
679 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
680 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
681 FR0.getValue(0), FR0.getValue(2));
682 // TPR = (Chain, Glue)
683 // Don't glue this CopyFromReg, because it copies from a virtual
684 // register. If it is glued to the call, InstrEmitter will add it
685 // as an implicit def to the call (EmitMachineNode).
686 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
687 Glue = TPR.getValue(1);
688 } else {
689 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
690 RVLocs[i].getValVT(), Glue);
691 Glue = RetVal.getValue(2);
692 }
693 InVals.push_back(RetVal.getValue(0));
694 Chain = RetVal.getValue(1);
695 }
696
697 return Chain;
698}
699
700/// LowerCall - Functions arguments are copied from virtual regs to
701/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
702SDValue
703HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
704 SmallVectorImpl<SDValue> &InVals) const {
705 SelectionDAG &DAG = CLI.DAG;
706 SDLoc &dl = CLI.DL;
707 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
708 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
709 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
710 SDValue Chain = CLI.Chain;
711 SDValue Callee = CLI.Callee;
712 bool &IsTailCall = CLI.IsTailCall;
713 CallingConv::ID CallConv = CLI.CallConv;
714 bool IsVarArg = CLI.IsVarArg;
715 bool DoesNotReturn = CLI.DoesNotReturn;
716
717 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
718 MachineFunction &MF = DAG.getMachineFunction();
719 auto PtrVT = getPointerTy(MF.getDataLayout());
720
721 // Check for varargs.
722 unsigned NumNamedVarArgParams = -1U;
723 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
724 const GlobalValue *GV = GAN->getGlobal();
725 Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
726 if (const Function* F = dyn_cast<Function>(GV)) {
727 // If a function has zero args and is a vararg function, that's
728 // disallowed so it must be an undeclared function. Do not assume
729 // varargs if the callee is undefined.
730 if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
731 NumNamedVarArgParams = F->getFunctionType()->getNumParams();
732 }
733 }
734
735 // Analyze operands of the call, assigning locations to each operand.
736 SmallVector<CCValAssign, 16> ArgLocs;
737 HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
738 *DAG.getContext(), NumNamedVarArgParams);
739
740 if (IsVarArg)
741 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
742 else
743 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
744
745 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
746 if (Attr.getValueAsString() == "true")
747 IsTailCall = false;
748
749 if (IsTailCall) {
750 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
751 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
752 IsVarArg, IsStructRet,
753 StructAttrFlag,
754 Outs, OutVals, Ins, DAG);
755 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
756 CCValAssign &VA = ArgLocs[i];
757 if (VA.isMemLoc()) {
758 IsTailCall = false;
759 break;
760 }
761 }
762 DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
763 : "Argument must be passed on stack. "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
764 "Not eligible for Tail Call\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
;
765 }
766 // Get a count of how many bytes are to be pushed on the stack.
767 unsigned NumBytes = CCInfo.getNextStackOffset();
768 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
769 SmallVector<SDValue, 8> MemOpChains;
770
771 auto &HRI = *Subtarget.getRegisterInfo();
772 SDValue StackPtr =
773 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
774
775 bool NeedsArgAlign = false;
776 unsigned LargestAlignSeen = 0;
777 // Walk the register/memloc assignments, inserting copies/loads.
778 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
779 CCValAssign &VA = ArgLocs[i];
780 SDValue Arg = OutVals[i];
781 ISD::ArgFlagsTy Flags = Outs[i].Flags;
782 // Record if we need > 8 byte alignment on an argument.
783 bool ArgAlign = isHvxVectorType(VA.getValVT());
784 NeedsArgAlign |= ArgAlign;
785
786 // Promote the value if needed.
787 switch (VA.getLocInfo()) {
788 default:
789 // Loc info must be one of Full, SExt, ZExt, or AExt.
790 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 790)
;
791 case CCValAssign::BCvt:
792 case CCValAssign::Full:
793 break;
794 case CCValAssign::SExt:
795 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
796 break;
797 case CCValAssign::ZExt:
798 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
799 break;
800 case CCValAssign::AExt:
801 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
802 break;
803 }
804
805 if (VA.isMemLoc()) {
806 unsigned LocMemOffset = VA.getLocMemOffset();
807 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
808 StackPtr.getValueType());
809 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
810 if (ArgAlign)
811 LargestAlignSeen = std::max(LargestAlignSeen,
812 VA.getLocVT().getStoreSizeInBits() >> 3);
813 if (Flags.isByVal()) {
814 // The argument is a struct passed by value. According to LLVM, "Arg"
815 // is is pointer.
816 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
817 Flags, DAG, dl));
818 } else {
819 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
820 DAG.getMachineFunction(), LocMemOffset);
821 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
822 MemOpChains.push_back(S);
823 }
824 continue;
825 }
826
827 // Arguments that can be passed on register must be kept at RegsToPass
828 // vector.
829 if (VA.isRegLoc())
830 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
831 }
832
833 if (NeedsArgAlign && Subtarget.hasV60TOps()) {
834 DEBUG(dbgs() << "Function needs byte stack align due to call args\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << "Function needs byte stack align due to call args\n"
; } } while (false)
;
835 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
836 // V6 vectors passed by value have 64 or 128 byte alignment depending
837 // on whether we are 64 byte vector mode or 128 byte.
838 bool UseHVXDbl = Subtarget.useHVXDblOps();
839 assert(Subtarget.useHVXOps())((Subtarget.useHVXOps()) ? static_cast<void> (0) : __assert_fail
("Subtarget.useHVXOps()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 839, __PRETTY_FUNCTION__))
;
840 const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
841 LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
842 MFI.ensureMaxAlignment(LargestAlignSeen);
843 }
844 // Transform all store nodes into one single node because all store
845 // nodes are independent of each other.
846 if (!MemOpChains.empty())
847 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
848
849 SDValue Glue;
850 if (!IsTailCall) {
851 SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
852 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
853 Glue = Chain.getValue(1);
854 }
855
856 // Build a sequence of copy-to-reg nodes chained together with token
857 // chain and flag operands which copy the outgoing args into registers.
858 // The Glue is necessary since all emitted instructions must be
859 // stuck together.
860 if (!IsTailCall) {
861 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
862 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
863 RegsToPass[i].second, Glue);
864 Glue = Chain.getValue(1);
865 }
866 } else {
867 // For tail calls lower the arguments to the 'real' stack slot.
868 //
869 // Force all the incoming stack arguments to be loaded from the stack
870 // before any new outgoing arguments are stored to the stack, because the
871 // outgoing stack slots may alias the incoming argument stack slots, and
872 // the alias isn't otherwise explicit. This is slightly more conservative
873 // than necessary, because it means that each store effectively depends
874 // on every argument instead of just those arguments it would clobber.
875 //
876 // Do not flag preceding copytoreg stuff together with the following stuff.
877 Glue = SDValue();
878 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
879 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
880 RegsToPass[i].second, Glue);
881 Glue = Chain.getValue(1);
882 }
883 Glue = SDValue();
884 }
885
886 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
887 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
888
889 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
890 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
891 // node so that legalize doesn't hack it.
892 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
893 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
894 } else if (ExternalSymbolSDNode *S =
895 dyn_cast<ExternalSymbolSDNode>(Callee)) {
896 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
897 }
898
899 // Returns a chain & a flag for retval copy to use.
900 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
901 SmallVector<SDValue, 8> Ops;
902 Ops.push_back(Chain);
903 Ops.push_back(Callee);
904
905 // Add argument registers to the end of the list so that they are
906 // known live into the call.
907 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
908 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
909 RegsToPass[i].second.getValueType()));
910 }
911
912 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
913 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 913, __PRETTY_FUNCTION__))
;
914 Ops.push_back(DAG.getRegisterMask(Mask));
915
916 if (Glue.getNode())
917 Ops.push_back(Glue);
918
919 if (IsTailCall) {
920 MF.getFrameInfo().setHasTailCall();
921 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
922 }
923
924 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
925 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
926 Glue = Chain.getValue(1);
927
928 // Create the CALLSEQ_END node.
929 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
930 DAG.getIntPtrConstant(0, dl, true), Glue, dl);
931 Glue = Chain.getValue(1);
932
933 // Handle result values, copying them out of physregs into vregs that we
934 // return.
935 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
936 InVals, OutVals, Callee);
937}
938
939static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
940 SDValue &Base, SDValue &Offset,
941 bool &IsInc, SelectionDAG &DAG) {
942 if (Ptr->getOpcode() != ISD::ADD)
943 return false;
944
945 auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
946 bool UseHVX = HST.useHVXOps();
947 bool UseHVXDbl = HST.useHVXDblOps();
948
949 bool ValidHVXDblType =
950 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
951 VT == MVT::v64i16 || VT == MVT::v128i8);
952 bool ValidHVXType =
953 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
954 VT == MVT::v32i16 || VT == MVT::v64i8);
955
956 if (ValidHVXDblType || ValidHVXType ||
957 VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
958 IsInc = (Ptr->getOpcode() == ISD::ADD);
959 Base = Ptr->getOperand(0);
960 Offset = Ptr->getOperand(1);
961 // Ensure that Offset is a constant.
962 return isa<ConstantSDNode>(Offset);
963 }
964
965 return false;
966}
967
968/// getPostIndexedAddressParts - returns true by value, base pointer and
969/// offset pointer and addressing mode by reference if this node can be
970/// combined with a load / store to form a post-indexed load / store.
971bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
972 SDValue &Base,
973 SDValue &Offset,
974 ISD::MemIndexedMode &AM,
975 SelectionDAG &DAG) const
976{
977 EVT VT;
978 SDValue Ptr;
979
980 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
981 VT = LD->getMemoryVT();
982 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
983 VT = ST->getMemoryVT();
984 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
985 return false;
986 } else {
987 return false;
988 }
989
990 bool IsInc = false;
991 bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
992 if (isLegal) {
993 auto &HII = *Subtarget.getInstrInfo();
994 int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
995 if (HII.isValidAutoIncImm(VT, OffsetVal)) {
996 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
997 return true;
998 }
999 }
1000
1001 return false;
1002}
1003
1004SDValue
1005HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
1006 SDNode *Node = Op.getNode();
1007 MachineFunction &MF = DAG.getMachineFunction();
1008 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1009 switch (Node->getOpcode()) {
1010 case ISD::INLINEASM: {
1011 unsigned NumOps = Node->getNumOperands();
1012 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1013 --NumOps; // Ignore the flag operand.
1014
1015 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1016 if (FuncInfo.hasClobberLR())
1017 break;
1018 unsigned Flags =
1019 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1020 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1021 ++i; // Skip the ID value.
1022
1023 switch (InlineAsm::getKind(Flags)) {
1024 default: llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1024)
;
1025 case InlineAsm::Kind_RegDef:
1026 case InlineAsm::Kind_RegUse:
1027 case InlineAsm::Kind_Imm:
1028 case InlineAsm::Kind_Clobber:
1029 case InlineAsm::Kind_Mem: {
1030 for (; NumVals; --NumVals, ++i) {}
1031 break;
1032 }
1033 case InlineAsm::Kind_RegDefEarlyClobber: {
1034 for (; NumVals; --NumVals, ++i) {
1035 unsigned Reg =
1036 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1037
1038 // Check it to be lr
1039 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
1040 if (Reg == QRI->getRARegister()) {
1041 FuncInfo.setHasClobberLR(true);
1042 break;
1043 }
1044 }
1045 break;
1046 }
1047 }
1048 }
1049 }
1050 } // Node->getOpcode
1051 return Op;
1052}
1053
1054// Need to transform ISD::PREFETCH into something that doesn't inherit
1055// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
1056// SDNPMayStore.
1057SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
1058 SelectionDAG &DAG) const {
1059 SDValue Chain = Op.getOperand(0);
1060 SDValue Addr = Op.getOperand(1);
1061 // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
1062 // if the "reg" is fed by an "add".
1063 SDLoc DL(Op);
1064 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1065 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1066}
1067
1068// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
1069// is marked as having side-effects, while the register read on Hexagon does
1070// not have any. TableGen refuses to accept the direct pattern from that node
1071// to the A4_tfrcpp.
1072SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
1073 SelectionDAG &DAG) const {
1074 SDValue Chain = Op.getOperand(0);
1075 SDLoc dl(Op);
1076 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1077 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
1078}
1079
1080SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1081 SelectionDAG &DAG) const {
1082 SDValue Chain = Op.getOperand(0);
1083 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1084 // Lower the hexagon_prefetch builtin to DCFETCH, as above.
1085 if (IntNo == Intrinsic::hexagon_prefetch) {
1086 SDValue Addr = Op.getOperand(2);
1087 SDLoc DL(Op);
1088 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1089 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1090 }
1091 return SDValue();
1092}
1093
1094SDValue
1095HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1096 SelectionDAG &DAG) const {
1097 SDValue Chain = Op.getOperand(0);
1098 SDValue Size = Op.getOperand(1);
1099 SDValue Align = Op.getOperand(2);
1100 SDLoc dl(Op);
1101
1102 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1103 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC")((AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC"
) ? static_cast<void> (0) : __assert_fail ("AlignConst && \"Non-constant Align in LowerDYNAMIC_STACKALLOC\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1103, __PRETTY_FUNCTION__))
;
1104
1105 unsigned A = AlignConst->getSExtValue();
1106 auto &HFI = *Subtarget.getFrameLowering();
1107 // "Zero" means natural stack alignment.
1108 if (A == 0)
1109 A = HFI.getStackAlignment();
1110
1111 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1112 dbgs () << __func__ << " Align: " << A << " Size: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1113 Size.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1114 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1115 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
;
1116
1117 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1118 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1119 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1120
1121 DAG.ReplaceAllUsesOfValueWith(Op, AA);
1122 return AA;
1123}
1124
1125SDValue HexagonTargetLowering::LowerFormalArguments(
1126 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1127 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1128 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1129 MachineFunction &MF = DAG.getMachineFunction();
1130 MachineFrameInfo &MFI = MF.getFrameInfo();
1131 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1132 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1133
1134 // Assign locations to all of the incoming arguments.
1135 SmallVector<CCValAssign, 16> ArgLocs;
1136 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1137 *DAG.getContext());
1138
1139 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1140
1141 // For LLVM, in the case when returning a struct by value (>8byte),
1142 // the first argument is a pointer that points to the location on caller's
1143 // stack where the return value will be stored. For Hexagon, the location on
1144 // caller's stack is passed only when the struct size is smaller than (and
1145 // equal to) 8 bytes. If not, no address will be passed into callee and
1146 // callee return the result direclty through R0/R1.
1147
1148 SmallVector<SDValue, 8> MemOps;
1149 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
1150
1151 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1152 CCValAssign &VA = ArgLocs[i];
1153 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1154 unsigned ObjSize;
1155 unsigned StackLocation;
1156 int FI;
1157
1158 if ( (VA.isRegLoc() && !Flags.isByVal())
1159 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1160 // Arguments passed in registers
1161 // 1. int, long long, ptr args that get allocated in register.
1162 // 2. Large struct that gets an register to put its address in.
1163 EVT RegVT = VA.getLocVT();
1164 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1165 RegVT == MVT::i32 || RegVT == MVT::f32) {
1166 unsigned VReg =
1167 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1168 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1169 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1170 // Treat values of type MVT::i1 specially: they are passed in
1171 // registers of type i32, but they need to remain as values of
1172 // type i1 for consistency of the argument lowering.
1173 if (VA.getValVT() == MVT::i1) {
1174 // Generate a copy into a predicate register and use the value
1175 // of the register as the "InVal".
1176 unsigned PReg =
1177 RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass);
1178 SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1179 Copy.getValue(0));
1180 Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0));
1181 Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1);
1182 }
1183 InVals.push_back(Copy);
1184 Chain = Copy.getValue(1);
1185 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1186 unsigned VReg =
1187 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1188 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1189 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1190
1191 // Single Vector
1192 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1193 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1194 unsigned VReg =
1195 RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
1196 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1197 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1198 } else if (UseHVX && UseHVXDbl &&
1199 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1200 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1201 unsigned VReg =
1202 RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
1203 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1204 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1205
1206 // Double Vector
1207 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1208 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1209 unsigned VReg =
1210 RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
1211 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1212 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1213 } else if (UseHVX && UseHVXDbl &&
1214 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1215 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1216 unsigned VReg =
1217 RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
1218 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1219 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1220 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1221 assert(0 && "need to support VecPred regs")((0 && "need to support VecPred regs") ? static_cast<
void> (0) : __assert_fail ("0 && \"need to support VecPred regs\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1221, __PRETTY_FUNCTION__))
;
1222 unsigned VReg =
1223 RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
1224 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1225 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1226 } else {
1227 assert (0)((0) ? static_cast<void> (0) : __assert_fail ("0", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1227, __PRETTY_FUNCTION__))
;
1228 }
1229 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1230 assert (0 && "ByValSize must be bigger than 8 bytes")((0 && "ByValSize must be bigger than 8 bytes") ? static_cast
<void> (0) : __assert_fail ("0 && \"ByValSize must be bigger than 8 bytes\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1230, __PRETTY_FUNCTION__))
;
1231 } else {
1232 // Sanity check.
1233 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1233, __PRETTY_FUNCTION__))
;
1234
1235 if (Flags.isByVal()) {
1236 // If it's a byval parameter, then we need to compute the
1237 // "real" size, not the size of the pointer.
1238 ObjSize = Flags.getByValSize();
1239 } else {
1240 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1241 }
1242
1243 StackLocation = HEXAGON_LRFP_SIZE8 + VA.getLocMemOffset();
1244 // Create the frame index object for this incoming parameter...
1245 FI = MFI.CreateFixedObject(ObjSize, StackLocation, true);
1246
1247 // Create the SelectionDAG nodes cordl, responding to a load
1248 // from this parameter.
1249 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1250
1251 if (Flags.isByVal()) {
1252 // If it's a pass-by-value aggregate, then do not dereference the stack
1253 // location. Instead, we should generate a reference to the stack
1254 // location.
1255 InVals.push_back(FIN);
1256 } else {
1257 InVals.push_back(
1258 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
1259 }
1260 }
1261 }
1262
1263 if (!MemOps.empty())
1264 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1265
1266 if (isVarArg) {
1267 // This will point to the next argument passed via stack.
1268 int FrameIndex = MFI.CreateFixedObject(Hexagon_PointerSize(4),
1269 HEXAGON_LRFP_SIZE8 +
1270 CCInfo.getNextStackOffset(),
1271 true);
1272 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1273 }
1274
1275 return Chain;
1276}
1277
1278SDValue
1279HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1280 // VASTART stores the address of the VarArgsFrameIndex slot into the
1281 // memory location argument.
1282 MachineFunction &MF = DAG.getMachineFunction();
1283 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
1284 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1285 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1286 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
1287 MachinePointerInfo(SV));
1288}
1289
1290// Creates a SPLAT instruction for a constant value VAL.
1291static SDValue createSplat(SelectionDAG &DAG, const SDLoc &dl, EVT VT,
1292 SDValue Val) {
1293 if (VT.getSimpleVT() == MVT::v4i8)
1294 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
1295
1296 if (VT.getSimpleVT() == MVT::v4i16)
1297 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
1298
1299 return SDValue();
1300}
1301
1302static bool isSExtFree(SDValue N) {
1303 // A sign-extend of a truncate of a sign-extend is free.
1304 if (N.getOpcode() == ISD::TRUNCATE &&
1305 N.getOperand(0).getOpcode() == ISD::AssertSext)
1306 return true;
1307 // We have sign-extended loads.
1308 if (N.getOpcode() == ISD::LOAD)
1309 return true;
1310 return false;
1311}
1312
1313SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1314 SDLoc dl(Op);
1315
1316 SDValue LHS = Op.getOperand(0);
1317 SDValue RHS = Op.getOperand(1);
1318 SDValue Cmp = Op.getOperand(2);
1319 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1320
1321 EVT VT = Op.getValueType();
1322 EVT LHSVT = LHS.getValueType();
1323 EVT RHSVT = RHS.getValueType();
1324
1325 if (LHSVT == MVT::v2i16) {
1326 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC))((ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)) ?
static_cast<void> (0) : __assert_fail ("ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1326, __PRETTY_FUNCTION__))
;
1327 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1328 : ISD::ZERO_EXTEND;
1329 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1330 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1331 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1332 return SC;
1333 }
1334
1335 // Treat all other vector types as legal.
1336 if (VT.isVector())
1337 return Op;
1338
1339 // Equals and not equals should use sign-extend, not zero-extend, since
1340 // we can represent small negative values in the compare instructions.
1341 // The LLVM default is to use zero-extend arbitrarily in these cases.
1342 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1343 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1344 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1345 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1346 if (C && C->getAPIntValue().isNegative()) {
1347 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1348 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1349 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1350 LHS, RHS, Op.getOperand(2));
1351 }
1352 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1353 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1354 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1355 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1356 LHS, RHS, Op.getOperand(2));
1357 }
1358 }
1359 return SDValue();
1360}
1361
1362SDValue
1363HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
1364 SDValue PredOp = Op.getOperand(0);
1365 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1366 EVT OpVT = Op1.getValueType();
1367 SDLoc DL(Op);
1368
1369 if (OpVT == MVT::v2i16) {
1370 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1371 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1372 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1373 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1374 return TR;
1375 }
1376
1377 return SDValue();
1378}
1379
1380// Handle only specific vector loads.
1381SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1382 EVT VT = Op.getValueType();
1383 SDLoc DL(Op);
1384 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1385 SDValue Chain = LoadNode->getChain();
1386 SDValue Ptr = Op.getOperand(1);
1387 SDValue LoweredLoad;
1388 SDValue Result;
1389 SDValue Base = LoadNode->getBasePtr();
1390 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1391 unsigned Alignment = LoadNode->getAlignment();
1392 SDValue LoadChain;
1393
1394 if(Ext == ISD::NON_EXTLOAD)
1395 Ext = ISD::ZEXTLOAD;
1396
1397 if (VT == MVT::v4i16) {
1398 if (Alignment == 2) {
1399 SDValue Loads[4];
1400 // Base load.
1401 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1402 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1403 LoadNode->getMemOperand()->getFlags());
1404 // Base+2 load.
1405 SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1406 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1407 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1408 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1409 LoadNode->getMemOperand()->getFlags());
1410 // SHL 16, then OR base and base+2.
1411 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1412 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1413 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1414 // Base + 4.
1415 Increment = DAG.getConstant(4, DL, MVT::i32);
1416 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1417 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1418 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1419 LoadNode->getMemOperand()->getFlags());
1420 // Base + 6.
1421 Increment = DAG.getConstant(6, DL, MVT::i32);
1422 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1423 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1424 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1425 LoadNode->getMemOperand()->getFlags());
1426 // SHL 16, then OR base+4 and base+6.
1427 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1428 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1429 // Combine to i64. This could be optimised out later if we can
1430 // affect reg allocation of this code.
1431 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1432 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1433 Loads[0].getValue(1), Loads[1].getValue(1),
1434 Loads[2].getValue(1), Loads[3].getValue(1));
1435 } else {
1436 // Perform default type expansion.
1437 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1438 LoadNode->getAlignment(),
1439 LoadNode->getMemOperand()->getFlags());
1440 LoadChain = Result.getValue(1);
1441 }
1442 } else
1443 llvm_unreachable("Custom lowering unsupported load")::llvm::llvm_unreachable_internal("Custom lowering unsupported load"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1443)
;
1444
1445 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1446 // Since we pretend to lower a load, we need the original chain
1447 // info attached to the result.
1448 SDValue Ops[] = { Result, LoadChain };
1449
1450 return DAG.getMergeValues(Ops, DL);
1451}
1452
1453SDValue
1454HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1455 EVT ValTy = Op.getValueType();
1456 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1457 unsigned Align = CPN->getAlignment();
1458 bool IsPositionIndependent = isPositionIndependent();
1459 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1460
1461 unsigned Offset = 0;
1462 SDValue T;
1463 if (CPN->isMachineConstantPoolEntry())
1464 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
1465 TF);
1466 else
1467 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
1468 TF);
1469
1470 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1471, __PRETTY_FUNCTION__))
1471 "Inconsistent target flag encountered")((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1471, __PRETTY_FUNCTION__))
;
1472
1473 if (IsPositionIndependent)
1474 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1475 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1476}
1477
1478SDValue
1479HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1480 EVT VT = Op.getValueType();
1481 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1482 if (isPositionIndependent()) {
1483 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1484 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1485 }
1486
1487 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1488 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1489}
1490
1491SDValue
1492HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1493 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1494 MachineFunction &MF = DAG.getMachineFunction();
1495 MachineFrameInfo &MFI = MF.getFrameInfo();
1496 MFI.setReturnAddressIsTaken(true);
1497
1498 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1499 return SDValue();
1500
1501 EVT VT = Op.getValueType();
1502 SDLoc dl(Op);
1503 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1504 if (Depth) {
1505 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1506 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1507 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1508 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1509 MachinePointerInfo());
1510 }
1511
1512 // Return LR, which contains the return address. Mark it an implicit live-in.
1513 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1514 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1515}
1516
1517SDValue
1518HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1519 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1520 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1521 MFI.setFrameAddressIsTaken(true);
1522
1523 EVT VT = Op.getValueType();
1524 SDLoc dl(Op);
1525 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1526 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1527 HRI.getFrameRegister(), VT);
1528 while (Depth--)
1529 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1530 MachinePointerInfo());
1531 return FrameAddr;
1532}
1533
1534SDValue
1535HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
1536 SDLoc dl(Op);
1537 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1538}
1539
1540SDValue
1541HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
1542 SDLoc dl(Op);
1543 auto *GAN = cast<GlobalAddressSDNode>(Op);
1544 auto PtrVT = getPointerTy(DAG.getDataLayout());
1545 auto *GV = GAN->getGlobal();
1546 int64_t Offset = GAN->getOffset();
1547
1548 auto &HLOF = *HTM.getObjFileLowering();
1549 Reloc::Model RM = HTM.getRelocationModel();
1550
1551 if (RM == Reloc::Static) {
1552 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1553 const GlobalObject *GO = GV->getBaseObject();
1554 if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1555 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1556 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1557 }
1558
1559 bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1560 if (UsePCRel) {
1561 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1562 HexagonII::MO_PCREL);
1563 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1564 }
1565
1566 // Use GOT index.
1567 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1568 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1569 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1570 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1571}
1572
1573// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1574SDValue
1575HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1576 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1577 SDLoc dl(Op);
1578 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1579
1580 Reloc::Model RM = HTM.getRelocationModel();
1581 if (RM == Reloc::Static) {
1582 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1583 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1584 }
1585
1586 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1587 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1588}
1589
1590SDValue
1591HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
1592 const {
1593 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1594 SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME"_GLOBAL_OFFSET_TABLE_", PtrVT,
1595 HexagonII::MO_PCREL);
1596 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1597}
1598
1599SDValue
1600HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
1601 GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1602 unsigned char OperandFlags) const {
1603 MachineFunction &MF = DAG.getMachineFunction();
1604 MachineFrameInfo &MFI = MF.getFrameInfo();
1605 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1606 SDLoc dl(GA);
1607 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1608 GA->getValueType(0),
1609 GA->getOffset(),
1610 OperandFlags);
1611 // Create Operands for the call.The Operands should have the following:
1612 // 1. Chain SDValue
1613 // 2. Callee which in this case is the Global address value.
1614 // 3. Registers live into the call.In this case its R0, as we
1615 // have just one argument to be passed.
1616 // 4. Glue.
1617 // Note: The order is important.
1618
1619 const auto &HRI = *Subtarget.getRegisterInfo();
1620 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1621 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1621, __PRETTY_FUNCTION__))
;
1622 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1623 DAG.getRegisterMask(Mask), Glue };
1624 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1625
1626 // Inform MFI that function has calls.
1627 MFI.setAdjustsStack(true);
1628
1629 Glue = Chain.getValue(1);
1630 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1631}
1632
1633//
1634// Lower using the intial executable model for TLS addresses
1635//
1636SDValue
1637HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
1638 SelectionDAG &DAG) const {
1639 SDLoc dl(GA);
1640 int64_t Offset = GA->getOffset();
1641 auto PtrVT = getPointerTy(DAG.getDataLayout());
1642
1643 // Get the thread pointer.
1644 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1645
1646 bool IsPositionIndependent = isPositionIndependent();
1647 unsigned char TF =
1648 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1649
1650 // First generate the TLS symbol address
1651 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1652 Offset, TF);
1653
1654 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1655
1656 if (IsPositionIndependent) {
1657 // Generate the GOT pointer in case of position independent code
1658 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1659
1660 // Add the TLS Symbol address to GOT pointer.This gives
1661 // GOT relative relocation for the symbol.
1662 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1663 }
1664
1665 // Load the offset value for TLS symbol.This offset is relative to
1666 // thread pointer.
1667 SDValue LoadOffset =
1668 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1669
1670 // Address of the thread local variable is the add of thread
1671 // pointer and the offset of the variable.
1672 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1673}
1674
1675//
1676// Lower using the local executable model for TLS addresses
1677//
1678SDValue
1679HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
1680 SelectionDAG &DAG) const {
1681 SDLoc dl(GA);
1682 int64_t Offset = GA->getOffset();
1683 auto PtrVT = getPointerTy(DAG.getDataLayout());
1684
1685 // Get the thread pointer.
1686 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1687 // Generate the TLS symbol address
1688 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1689 HexagonII::MO_TPREL);
1690 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1691
1692 // Address of the thread local variable is the add of thread
1693 // pointer and the offset of the variable.
1694 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1695}
1696
1697//
1698// Lower using the general dynamic model for TLS addresses
1699//
1700SDValue
1701HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1702 SelectionDAG &DAG) const {
1703 SDLoc dl(GA);
1704 int64_t Offset = GA->getOffset();
1705 auto PtrVT = getPointerTy(DAG.getDataLayout());
1706
1707 // First generate the TLS symbol address
1708 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1709 HexagonII::MO_GDGOT);
1710
1711 // Then, generate the GOT pointer
1712 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1713
1714 // Add the TLS symbol and the GOT pointer
1715 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1716 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1717
1718 // Copy over the argument to R0
1719 SDValue InFlag;
1720 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1721 InFlag = Chain.getValue(1);
1722
1723 return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1724 Hexagon::R0, HexagonII::MO_GDPLT);
1725}
1726
1727//
1728// Lower TLS addresses.
1729//
1730// For now for dynamic models, we only support the general dynamic model.
1731//
1732SDValue
1733HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1734 SelectionDAG &DAG) const {
1735 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1736
1737 switch (HTM.getTLSModel(GA->getGlobal())) {
1738 case TLSModel::GeneralDynamic:
1739 case TLSModel::LocalDynamic:
1740 return LowerToTLSGeneralDynamicModel(GA, DAG);
1741 case TLSModel::InitialExec:
1742 return LowerToTLSInitialExecModel(GA, DAG);
1743 case TLSModel::LocalExec:
1744 return LowerToTLSLocalExecModel(GA, DAG);
1745 }
1746 llvm_unreachable("Bogus TLS model")::llvm::llvm_unreachable_internal("Bogus TLS model", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1746)
;
1747}
1748
1749//===----------------------------------------------------------------------===//
1750// TargetLowering Implementation
1751//===----------------------------------------------------------------------===//
1752
1753HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1754 const HexagonSubtarget &ST)
1755 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1756 Subtarget(ST) {
1757 bool IsV4 = !Subtarget.hasV5TOps();
1758 auto &HRI = *Subtarget.getRegisterInfo();
1759 bool UseHVX = Subtarget.useHVXOps();
1760 bool UseHVXSgl = Subtarget.useHVXSglOps();
1761 bool UseHVXDbl = Subtarget.useHVXDblOps();
1762
1763 setPrefLoopAlignment(4);
1764 setPrefFunctionAlignment(4);
1765 setMinFunctionAlignment(2);
1766 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1767
1768 setMaxAtomicSizeInBitsSupported(64);
1769 setMinCmpXchgSizeInBits(32);
1770
1771 if (EnableHexSDNodeSched)
1772 setSchedulingPreference(Sched::VLIW);
1773 else
1774 setSchedulingPreference(Sched::Source);
1775
1776 // Limits for inline expansion of memcpy/memmove
1777 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1778 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1779 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1780 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1781 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1782 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1783
1784 //
1785 // Set up register classes.
1786 //
1787
1788 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1789 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1790 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1791 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1792 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1793 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1794 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1795 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1796 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1797 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1798 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1799
1800 if (Subtarget.hasV5TOps()) {
1801 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1802 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1803 }
1804
1805 if (Subtarget.hasV60TOps()) {
1806 if (Subtarget.useHVXSglOps()) {
1807 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass);
1808 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
1809 addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
1810 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass);
1811 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
1812 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
1813 addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
1814 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
1815 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
1816 } else if (Subtarget.useHVXDblOps()) {
1817 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass);
1818 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass);
1819 addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass);
1820 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass);
1821 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass);
1822 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
1823 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass);
1824 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
1825 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
1826 }
1827 }
1828
1829 //
1830 // Handling of scalar operations.
1831 //
1832 // All operations default to "legal", except:
1833 // - indexed loads and stores (pre-/post-incremented),
1834 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1835 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1836 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1837 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1838 // which default to "expand" for at least one type.
1839
1840 // Misc operations.
1841 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1842 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1843
1844 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1845 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1846 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1847 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1848 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1849 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1850 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1851 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1852 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1853 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1854 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1855 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1856
1857 // Custom legalize GlobalAddress nodes into CONST32.
1858 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1859 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1860 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1861
1862 // Hexagon needs to optimize cases with negative constants.
1863 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1864 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1865
1866 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1867 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1868 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1869 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1870
1871 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1872 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1873 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1874
1875 if (EmitJumpTables)
1876 setMinimumJumpTableEntries(MinimumJumpTables);
1877 else
1878 setMinimumJumpTableEntries(std::numeric_limits<int>::max());
1879 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1880
1881 // Hexagon has instructions for add/sub with carry. The problem with
1882 // modeling these instructions is that they produce 2 results: Rdd and Px.
1883 // To model the update of Px, we will have to use Defs[p0..p3] which will
1884 // cause any predicate live range to spill. So, we pretend we dont't have
1885 // these instructions.
1886 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1887 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1888 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1889 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1890 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1891 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1892 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1893 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1894 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1895 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1896 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1897 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1898 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1899 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1900 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1901 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1902
1903 // Only add and sub that detect overflow are the saturating ones.
1904 for (MVT VT : MVT::integer_valuetypes()) {
1905 setOperationAction(ISD::UADDO, VT, Expand);
1906 setOperationAction(ISD::SADDO, VT, Expand);
1907 setOperationAction(ISD::USUBO, VT, Expand);
1908 setOperationAction(ISD::SSUBO, VT, Expand);
1909 }
1910
1911 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1912 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1913 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1914 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1915
1916 // In V5, popcount can count # of 1s in i64 but returns i32.
1917 // On V4 it will be expanded (set later).
1918 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1919 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1920 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1921 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1922
1923 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1924 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
1925 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
1926 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
1927
1928 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1929 // operation. There is a pattern that will match i64 mul and transform it
1930 // to a series of instructions.
1931 setOperationAction(ISD::MUL, MVT::i64, Expand);
1932
1933 for (unsigned IntExpOp :
1934 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1935 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1936 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1937 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1938 setOperationAction(IntExpOp, MVT::i32, Expand);
1939 setOperationAction(IntExpOp, MVT::i64, Expand);
1940 }
1941
1942 for (unsigned FPExpOp :
1943 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1944 ISD::FPOW, ISD::FCOPYSIGN}) {
1945 setOperationAction(FPExpOp, MVT::f32, Expand);
1946 setOperationAction(FPExpOp, MVT::f64, Expand);
1947 }
1948
1949 // No extending loads from i32.
1950 for (MVT VT : MVT::integer_valuetypes()) {
1951 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1952 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1953 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1954 }
1955 // Turn FP truncstore into trunc + store.
1956 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1957 // Turn FP extload into load/fpextend.
1958 for (MVT VT : MVT::fp_valuetypes())
1959 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1960
1961 // Expand BR_CC and SELECT_CC for all integer and fp types.
1962 for (MVT VT : MVT::integer_valuetypes()) {
1963 setOperationAction(ISD::BR_CC, VT, Expand);
1964 setOperationAction(ISD::SELECT_CC, VT, Expand);
1965 }
1966 for (MVT VT : MVT::fp_valuetypes()) {
1967 setOperationAction(ISD::BR_CC, VT, Expand);
1968 setOperationAction(ISD::SELECT_CC, VT, Expand);
1969 }
1970 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1971
1972 //
1973 // Handling of vector operations.
1974 //
1975
1976 // Custom lower v4i16 load only. Let v4i16 store to be
1977 // promoted for now.
1978 promoteLdStType(MVT::v4i8, MVT::i32);
1979 promoteLdStType(MVT::v2i16, MVT::i32);
1980 promoteLdStType(MVT::v8i8, MVT::i64);
1981 promoteLdStType(MVT::v2i32, MVT::i64);
1982
1983 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1984 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1985 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1986 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1987
1988 // Set the action for vector operations to "expand", then override it with
1989 // either "custom" or "legal" for specific cases.
1990 static const unsigned VectExpOps[] = {
1991 // Integer arithmetic:
1992 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1993 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1994 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1995 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1996 // Logical/bit:
1997 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1998 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
1999 // Floating point arithmetic/math functions:
2000 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
2001 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
2002 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
2003 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
2004 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
2005 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
2006 // Misc:
2007 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
2008 // Vector:
2009 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
2010 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
2011 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
2012 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
2013 };
2014
2015 for (MVT VT : MVT::vector_valuetypes()) {
2016 for (unsigned VectExpOp : VectExpOps)
2017 setOperationAction(VectExpOp, VT, Expand);
2018
2019 // Expand all extending loads and truncating stores:
2020 for (MVT TargetVT : MVT::vector_valuetypes()) {
2021 if (TargetVT == VT)
2022 continue;
2023 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
2024 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
2025 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
2026 setTruncStoreAction(VT, TargetVT, Expand);
2027 }
2028
2029 // Normalize all inputs to SELECT to be vectors of i32.
2030 if (VT.getVectorElementType() != MVT::i32) {
2031 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
2032 setOperationAction(ISD::SELECT, VT, Promote);
2033 AddPromotedToType(ISD::SELECT, VT, VT32);
2034 }
2035 setOperationAction(ISD::SRA, VT, Custom);
2036 setOperationAction(ISD::SHL, VT, Custom);
2037 setOperationAction(ISD::SRL, VT, Custom);
2038 }
2039
2040 // Types natively supported:
2041 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
2042 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
2043 MVT::v2i32, MVT::v1i64}) {
2044 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
2045 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
2046 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
2047 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
2048 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
2049 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
2050
2051 setOperationAction(ISD::ADD, NativeVT, Legal);
2052 setOperationAction(ISD::SUB, NativeVT, Legal);
2053 setOperationAction(ISD::MUL, NativeVT, Legal);
2054 setOperationAction(ISD::AND, NativeVT, Legal);
2055 setOperationAction(ISD::OR, NativeVT, Legal);
2056 setOperationAction(ISD::XOR, NativeVT, Legal);
2057 }
2058
2059 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
2060 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
2061 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
2062 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
2063
2064 if (UseHVX) {
2065 if (UseHVXSgl) {
2066 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
2067 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
2068 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
2069 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
2070 // We try to generate the vpack{e/o} instructions. If we fail
2071 // we fall back upon ExpandOp.
2072 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
2073 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
2074 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
2075 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
2076 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
2077 } else if (UseHVXDbl) {
2078 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
2079 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
2080 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
2081 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
2082 // We try to generate the vpack{e/o} instructions. If we fail
2083 // we fall back upon ExpandOp.
2084 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom);
2085 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom);
2086 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
2087 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v128i8, Custom);
2088 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i16, Custom);
2089 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
2090 } else {
2091 llvm_unreachable("Unrecognized HVX mode")::llvm::llvm_unreachable_internal("Unrecognized HVX mode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2091)
;
2092 }
2093 }
2094 // Subtarget-specific operation actions.
2095 //
2096 if (Subtarget.hasV5TOps()) {
2097 setOperationAction(ISD::FMA, MVT::f64, Expand);
2098 setOperationAction(ISD::FADD, MVT::f64, Expand);
2099 setOperationAction(ISD::FSUB, MVT::f64, Expand);
2100 setOperationAction(ISD::FMUL, MVT::f64, Expand);
2101
2102 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
2103 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
2104
2105 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
2106 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
2107 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
2108 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
2109 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
2110 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
2111 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
2112 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
2113 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
2114 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
2115 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
2116 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
2117 } else { // V4
2118 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
2119 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
2120 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
2121 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
2122 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
2123 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
2124 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
2125 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
2126 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
2127
2128 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
2129 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
2130 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
2131 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
2132
2133 // Expand these operations for both f32 and f64:
2134 for (unsigned FPExpOpV4 :
2135 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
2136 setOperationAction(FPExpOpV4, MVT::f32, Expand);
2137 setOperationAction(FPExpOpV4, MVT::f64, Expand);
2138 }
2139
2140 for (ISD::CondCode FPExpCCV4 :
2141 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
2142 ISD::SETUO, ISD::SETO}) {
2143 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
2144 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
2145 }
2146 }
2147
2148 // Handling of indexed loads/stores: default is "expand".
2149 //
2150 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
2151 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2152 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2153 }
2154
2155 if (UseHVXSgl) {
2156 for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
2157 MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
2158 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2159 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2160 }
2161 } else if (UseHVXDbl) {
2162 for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
2163 MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
2164 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2165 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2166 }
2167 }
2168
2169 computeRegisterProperties(&HRI);
2170
2171 //
2172 // Library calls for unsupported operations
2173 //
2174 bool FastMath = EnableFastMath;
2175
2176 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
2177 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
2178 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
2179 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
2180 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
2181 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
2182 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
2183 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
2184
2185 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
2186 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
2187 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
2188 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
2189 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
2190 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
2191
2192 if (IsV4) {
2193 // Handle single-precision floating point operations on V4.
2194 if (FastMath) {
2195 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
2196 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
2197 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
2198 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
2199 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
2200 // Double-precision compares.
2201 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
2202 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
2203 } else {
2204 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
2205 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
2206 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
2207 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
2208 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
2209 // Double-precision compares.
2210 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
2211 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
2212 }
2213 }
2214
2215 // This is the only fast library function for sqrtd.
2216 if (FastMath)
2217 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
2218
2219 // Prefix is: nothing for "slow-math",
2220 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
2221 // (actually, keep fast-math and fast-math2 separate for now)
2222 if (FastMath) {
2223 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
2224 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
2225 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
2226 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
2227 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
2228 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
2229 } else {
2230 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
2231 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
2232 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
2233 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
2234 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
2235 }
2236
2237 if (Subtarget.hasV5TOps()) {
2238 if (FastMath)
2239 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
2240 else
2241 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
2242 } else {
2243 // V4
2244 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
2245 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
2246 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
2247 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
2248 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
2249 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
2250 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
2251 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
2252 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
2253 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
2254 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
2255 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
2256 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
2257 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
2258 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
2259 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
2260 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
2261 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
2262 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
2263 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
2264 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
2265 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
2266 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
2267 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
2268 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
2269 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
2270 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
2271 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
2272 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
2273 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
2274 }
2275
2276 // These cause problems when the shift amount is non-constant.
2277 setLibcallName(RTLIB::SHL_I128, nullptr);
2278 setLibcallName(RTLIB::SRL_I128, nullptr);
2279 setLibcallName(RTLIB::SRA_I128, nullptr);
2280}
2281
2282const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2283 switch ((HexagonISD::NodeType)Opcode) {
2284 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2285 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2286 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2287 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2288 case HexagonISD::CALL: return "HexagonISD::CALL";
2289 case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
2290 case HexagonISD::CALLR: return "HexagonISD::CALLR";
2291 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2292 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2293 case HexagonISD::CONST32: return "HexagonISD::CONST32";
2294 case HexagonISD::CP: return "HexagonISD::CP";
2295 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2296 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2297 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2298 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2299 case HexagonISD::INSERT: return "HexagonISD::INSERT";
2300 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2301 case HexagonISD::JT: return "HexagonISD::JT";
2302 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2303 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2304 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
2305 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
2306 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
2307 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
2308 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2309 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
2310 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
2311 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
2312 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
2313 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
2314 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
2315 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
2316 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
2317 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
2318 case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2319 case HexagonISD::VPACK: return "HexagonISD::VPACK";
2320 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
2321 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
2322 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
2323 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
2324 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
2325 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
2326 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
2327 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
2328 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
2329 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
2330 case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
2331 case HexagonISD::OP_END: break;
2332 }
2333 return nullptr;
2334}
2335
2336bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
2337 EVT MTy1 = EVT::getEVT(Ty1);
2338 EVT MTy2 = EVT::getEVT(Ty2);
2339 if (!MTy1.isSimple() || !MTy2.isSimple())
2340 return false;
2341 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2342}
2343
2344bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
2345 if (!VT1.isSimple() || !VT2.isSimple())
2346 return false;
2347 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2348}
2349
2350bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
2351 return isOperationLegalOrCustom(ISD::FMA, VT);
2352}
2353
2354// Should we expand the build vector with shuffles?
2355bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
2356 unsigned DefinedValues) const {
2357 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2358 EVT EltVT = VT.getVectorElementType();
2359 int EltBits = EltVT.getSizeInBits();
2360 if ((EltBits != 8) && (EltBits != 16))
2361 return false;
2362
2363 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2364}
2365
2366static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
2367 int even_start = -2;
2368 int odd_start = -1;
2369 size_t mask_len = Mask.size();
2370 for (auto idx : Mask) {
2371 if ((idx - even_start) == 2)
2372 even_start = idx;
2373 else
2374 break;
2375 }
2376 if (even_start == (int)(mask_len * 2) - 2)
2377 return StridedLoadKind::Even;
2378 for (auto idx : Mask) {
2379 if ((idx - odd_start) == 2)
2380 odd_start = idx;
2381 else
2382 break;
2383 }
2384 if (odd_start == (int)(mask_len * 2) - 1)
2385 return StridedLoadKind::Odd;
2386
2387 return StridedLoadKind::NoPattern;
2388}
2389
2390bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
2391 EVT VT) const {
2392 if (Subtarget.useHVXOps())
2393 return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
2394 return true;
2395}
2396
2397// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2398// to select data from, V3 is the permutation.
2399SDValue
2400HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
2401 const {
2402 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2403 SDValue V1 = Op.getOperand(0);
2404 SDValue V2 = Op.getOperand(1);
2405 SDLoc dl(Op);
2406 EVT VT = Op.getValueType();
2407 bool UseHVX = Subtarget.useHVXOps();
2408
2409 if (V2.isUndef())
2410 V2 = V1;
2411
2412 if (SVN->isSplat()) {
2413 int Lane = SVN->getSplatIndex();
2414 if (Lane == -1) Lane = 0;
2415
2416 // Test if V1 is a SCALAR_TO_VECTOR.
2417 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2418 return createSplat(DAG, dl, VT, V1.getOperand(0));
2419
2420 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2421 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2422 // reaches it).
2423 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2424 !isa<ConstantSDNode>(V1.getOperand(0))) {
2425 bool IsScalarToVector = true;
2426 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
2427 if (!V1.getOperand(i).isUndef()) {
2428 IsScalarToVector = false;
2429 break;
2430 }
2431 }
2432 if (IsScalarToVector)
2433 return createSplat(DAG, dl, VT, V1.getOperand(0));
2434 }
2435 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
2436 }
2437
2438 if (UseHVX) {
2439 ArrayRef<int> Mask = SVN->getMask();
2440 size_t MaskLen = Mask.size();
2441 int ElemSizeInBits = VT.getScalarSizeInBits();
2442 if ((Subtarget.useHVXSglOps() && (ElemSizeInBits * MaskLen) == 64 * 8) ||
2443 (Subtarget.useHVXDblOps() && (ElemSizeInBits * MaskLen) == 128 * 8)) {
2444 // Return 1 for odd and 2 of even
2445 StridedLoadKind Pattern = isStridedLoad(Mask);
2446
2447 if (Pattern == StridedLoadKind::NoPattern)
2448 return SDValue();
2449
2450 SDValue Vec0 = Op.getOperand(0);
2451 SDValue Vec1 = Op.getOperand(1);
2452 SDValue StridePattern = DAG.getConstant(Pattern, dl, MVT::i32);
2453 SDValue Ops[] = { Vec1, Vec0, StridePattern };
2454 return DAG.getNode(HexagonISD::VPACK, dl, VT, Ops);
2455 }
2456 // We used to assert in the "else" part here, but that is bad for Halide
2457 // Halide creates intermediate double registers by interleaving two
2458 // concatenated vector registers. The interleaving requires vector_shuffle
2459 // nodes and we shouldn't barf on a double register result of a
2460 // vector_shuffle because it is most likely an intermediate result.
2461 }
2462 // FIXME: We need to support more general vector shuffles. See
2463 // below the comment from the ARM backend that deals in the general
2464 // case with the vector shuffles. For now, let expand handle these.
2465 return SDValue();
2466
2467 // If the shuffle is not directly supported and it has 4 elements, use
2468 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2469}
2470
2471// If BUILD_VECTOR has same base element repeated several times,
2472// report true.
2473static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
2474 unsigned NElts = BVN->getNumOperands();
2475 SDValue V0 = BVN->getOperand(0);
2476
2477 for (unsigned i = 1, e = NElts; i != e; ++i) {
2478 if (BVN->getOperand(i) != V0)
2479 return false;
2480 }
2481 return true;
2482}
2483
2484// Lower a vector shift. Try to convert
2485// <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2486// <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
2487SDValue
2488HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
2489 BuildVectorSDNode *BVN = nullptr;
2490 SDValue V1 = Op.getOperand(0);
2491 SDValue V2 = Op.getOperand(1);
2492 SDValue V3;
2493 SDLoc dl(Op);
2494 EVT VT = Op.getValueType();
2495
2496 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2497 isCommonSplatElement(BVN))
2498 V3 = V2;
2499 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2500 isCommonSplatElement(BVN))
2501 V3 = V1;
2502 else
2503 return SDValue();
2504
2505 SDValue CommonSplat = BVN->getOperand(0);
2506 SDValue Result;
2507
2508 if (VT.getSimpleVT() == MVT::v4i16) {
2509 switch (Op.getOpcode()) {
2510 case ISD::SRA:
2511 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
2512 break;
2513 case ISD::SHL:
2514 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
2515 break;
2516 case ISD::SRL:
2517 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
2518 break;
2519 default:
2520 return SDValue();
2521 }
2522 } else if (VT.getSimpleVT() == MVT::v2i32) {
2523 switch (Op.getOpcode()) {
2524 case ISD::SRA:
2525 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
2526 break;
2527 case ISD::SHL:
2528 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
2529 break;
2530 case ISD::SRL:
2531 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
2532 break;
2533 default:
2534 return SDValue();
2535 }
2536 } else {
2537 return SDValue();
2538 }
2539
2540 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2541}
2542
2543SDValue
2544HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
2545 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2546 SDLoc dl(Op);
2547 EVT VT = Op.getValueType();
2548
2549 unsigned Size = VT.getSizeInBits();
2550
2551 // Only handle vectors of 64 bits or shorter.
2552 if (Size > 64)
2553 return SDValue();
2554
2555 APInt APSplatBits, APSplatUndef;
2556 unsigned SplatBitSize;
2557 bool HasAnyUndefs;
2558 unsigned NElts = BVN->getNumOperands();
2559
2560 // Try to generate a SPLAT instruction.
2561 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2562 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2563 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
2564 unsigned SplatBits = APSplatBits.getZExtValue();
2565 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2566 (32 - SplatBitSize));
2567 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
2568 }
2569
2570 // Try to generate COMBINE to build v2i32 vectors.
2571 if (VT.getSimpleVT() == MVT::v2i32) {
2572 SDValue V0 = BVN->getOperand(0);
2573 SDValue V1 = BVN->getOperand(1);
2574
2575 if (V0.isUndef())
2576 V0 = DAG.getConstant(0, dl, MVT::i32);
2577 if (V1.isUndef())
2578 V1 = DAG.getConstant(0, dl, MVT::i32);
2579
2580 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2581 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
2582 // If the element isn't a constant, it is in a register:
2583 // generate a COMBINE Register Register instruction.
2584 if (!C0 || !C1)
2585 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2586
2587 // If one of the operands is an 8 bit integer constant, generate
2588 // a COMBINE Immediate Immediate instruction.
2589 if (isInt<8>(C0->getSExtValue()) ||
2590 isInt<8>(C1->getSExtValue()))
2591 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2592 }
2593
2594 // Try to generate a S2_packhl to build v2i16 vectors.
2595 if (VT.getSimpleVT() == MVT::v2i16) {
2596 for (unsigned i = 0, e = NElts; i != e; ++i) {
2597 if (BVN->getOperand(i).isUndef())
2598 continue;
2599 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
2600 // If the element isn't a constant, it is in a register:
2601 // generate a S2_packhl instruction.
2602 if (!Cst) {
2603 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2604 BVN->getOperand(1), BVN->getOperand(0));
2605
2606 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
2607 pack);
2608 }
2609 }
2610 }
2611
2612 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2613 // and insert_vector_elt for all the other cases.
2614 uint64_t Res = 0;
2615 unsigned EltSize = Size / NElts;
2616 SDValue ConstVal;
2617 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2618 bool HasNonConstantElements = false;
2619
2620 for (unsigned i = 0, e = NElts; i != e; ++i) {
2621 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2622 // combine, const64, etc. are Big Endian.
2623 unsigned OpIdx = NElts - i - 1;
2624 SDValue Operand = BVN->getOperand(OpIdx);
2625 if (Operand.isUndef())
2626 continue;
2627
2628 int64_t Val = 0;
2629 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2630 Val = Cst->getSExtValue();
2631 else
2632 HasNonConstantElements = true;
2633
2634 Val &= Mask;
2635 Res = (Res << EltSize) | Val;
2636 }
2637
2638 if (Size > 64)
2639 return SDValue();
2640
2641 if (Size == 64)
2642 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2643 else
2644 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2645
2646 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2647 // ConstVal, the constant part of the vector.
2648 if (HasNonConstantElements) {
2649 EVT EltVT = VT.getVectorElementType();
2650 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2651 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2652 DAG.getConstant(32, dl, MVT::i64));
2653
2654 for (unsigned i = 0, e = NElts; i != e; ++i) {
2655 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2656 // is Big Endian.
2657 unsigned OpIdx = NElts - i - 1;
2658 SDValue Operand = BVN->getOperand(OpIdx);
2659 if (isa<ConstantSDNode>(Operand))
2660 // This operand is already in ConstVal.
2661 continue;
2662
2663 if (VT.getSizeInBits() == 64 &&
2664 Operand.getValueSizeInBits() == 32) {
2665 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2666 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2667 }
2668
2669 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2670 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2671 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2672 const SDValue Ops[] = {ConstVal, Operand, Combined};
2673
2674 if (VT.getSizeInBits() == 32)
2675 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2676 else
2677 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2678 }
2679 }
2680
2681 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2682}
2683
2684SDValue
2685HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2686 SelectionDAG &DAG) const {
2687 SDLoc dl(Op);
2688 bool UseHVX = Subtarget.useHVXOps();
2689 EVT VT = Op.getValueType();
2690 unsigned NElts = Op.getNumOperands();
2691 SDValue Vec0 = Op.getOperand(0);
2692 EVT VecVT = Vec0.getValueType();
2693 unsigned Width = VecVT.getSizeInBits();
2694
2695 if (NElts == 2) {
2696 MVT ST = VecVT.getSimpleVT();
2697 // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2698 // into a single v8i8.
2699 if (ST == MVT::v2i16 || ST == MVT::v4i8)
2700 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2701
2702 if (UseHVX) {
2703 assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||(((Width == 64*8 && Subtarget.useHVXSglOps()) || (Width
== 128*8 && Subtarget.useHVXDblOps())) ? static_cast
<void> (0) : __assert_fail ("(Width == 64*8 && Subtarget.useHVXSglOps()) || (Width == 128*8 && Subtarget.useHVXDblOps())"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2704, __PRETTY_FUNCTION__))
2704 (Width == 128*8 && Subtarget.useHVXDblOps()))(((Width == 64*8 && Subtarget.useHVXSglOps()) || (Width
== 128*8 && Subtarget.useHVXDblOps())) ? static_cast
<void> (0) : __assert_fail ("(Width == 64*8 && Subtarget.useHVXSglOps()) || (Width == 128*8 && Subtarget.useHVXDblOps())"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2704, __PRETTY_FUNCTION__))
;
2705 SDValue Vec1 = Op.getOperand(1);
2706 MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
2707 MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
2708 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2709 SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2710 SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2711 return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2712 }
2713 }
2714
2715 if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2716 return SDValue();
2717
2718 SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2719 SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2720 SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2721 // Create the "width" part of the argument to insert_rp/insertp_rp.
2722 SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2723 SDValue V = C0;
2724
2725 for (unsigned i = 0, e = NElts; i != e; ++i) {
2726 unsigned N = NElts-i-1;
2727 SDValue OpN = Op.getOperand(N);
2728
2729 if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
2730 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2731 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2732 }
2733 SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2734 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2735 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2736 if (VT.getSizeInBits() == 32)
2737 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2738 else if (VT.getSizeInBits() == 64)
2739 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2740 else
2741 return SDValue();
2742 }
2743
2744 return DAG.getNode(ISD::BITCAST, dl, VT, V);
2745}
2746
2747SDValue
2748HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
2749 SelectionDAG &DAG) const {
2750 EVT VT = Op.getOperand(0).getValueType();
2751 SDLoc dl(Op);
2752 bool UseHVX = Subtarget.useHVXOps();
2753 bool UseHVXSgl = Subtarget.useHVXSglOps();
2754 // Just in case...
2755
2756 if (!VT.isVector() || !UseHVX)
2757 return SDValue();
2758
2759 EVT ResVT = Op.getValueType();
2760 unsigned ResSize = ResVT.getSizeInBits();
2761 unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
2762 unsigned OpSize = VT.getSizeInBits();
2763
2764 // We deal only with cases where the result is the vector size
2765 // and the vector operand is a double register.
2766 if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
2767 !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
2768 return SDValue();
2769
2770 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2771 if (!Cst)
2772 return SDValue();
2773 unsigned Val = Cst->getZExtValue();
2774
2775 // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
2776 if (Val == 0) {
2777 SDValue Vec = Op.getOperand(0);
2778 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
2779 }
2780
2781 if (ResVT.getVectorNumElements() == Val) {
2782 SDValue Vec = Op.getOperand(0);
2783 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
2784 }
2785
2786 return SDValue();
2787}
2788
2789SDValue
2790HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2791 SelectionDAG &DAG) const {
2792 // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
2793 // be able to simplify it to an EXTRACT_SUBREG.
2794 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
2795 isHvxVectorType(Op.getValueType().getSimpleVT()))
2796 return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
2797
2798 EVT VT = Op.getValueType();
2799 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2800 SDLoc dl(Op);
2801 SDValue Idx = Op.getOperand(1);
2802 SDValue Vec = Op.getOperand(0);
2803 EVT VecVT = Vec.getValueType();
2804 EVT EltVT = VecVT.getVectorElementType();
2805 int EltSize = EltVT.getSizeInBits();
2806 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2807 EltSize : VTN * EltSize, dl, MVT::i64);
2808
2809 // Constant element number.
2810 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2811 uint64_t X = CI->getZExtValue();
2812 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2813 const SDValue Ops[] = {Vec, Width, Offset};
2814
2815 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2816 assert(CW && "Non constant width in LowerEXTRACT_VECTOR")((CW && "Non constant width in LowerEXTRACT_VECTOR") ?
static_cast<void> (0) : __assert_fail ("CW && \"Non constant width in LowerEXTRACT_VECTOR\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2816, __PRETTY_FUNCTION__))
;
2817
2818 SDValue N;
2819 MVT SVT = VecVT.getSimpleVT();
2820 uint64_t W = CW->getZExtValue();
2821
2822 if (W == 32) {
2823 // Translate this node into EXTRACT_SUBREG.
2824 unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
Value stored to 'Subreg' during its initialization is never read
2825
2826 if (X == 0)
2827 Subreg = Hexagon::isub_lo;
2828 else if (SVT == MVT::v2i32 && X == 1)
2829 Subreg = Hexagon::isub_hi;
2830 else if (SVT == MVT::v4i16 && X == 2)
2831 Subreg = Hexagon::isub_hi;
2832 else if (SVT == MVT::v8i8 && X == 4)
2833 Subreg = Hexagon::isub_hi;
2834 else
2835 llvm_unreachable("Bad offset")::llvm::llvm_unreachable_internal("Bad offset", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2835)
;
2836 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2837
2838 } else if (SVT.getSizeInBits() == 32) {
2839 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2840 } else if (SVT.getSizeInBits() == 64) {
2841 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2842 if (VT.getSizeInBits() == 32)
2843 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2844 } else
2845 return SDValue();
2846
2847 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2848 }
2849
2850 // Variable element number.
2851 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2852 DAG.getConstant(EltSize, dl, MVT::i32));
2853 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2854 DAG.getConstant(32, dl, MVT::i64));
2855 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2856
2857 const SDValue Ops[] = {Vec, Combined};
2858
2859 SDValue N;
2860 if (VecVT.getSizeInBits() == 32) {
2861 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2862 } else {
2863 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2864 if (VT.getSizeInBits() == 32)
2865 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2866 }
2867 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2868}
2869
2870SDValue
2871HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2872 SelectionDAG &DAG) const {
2873 EVT VT = Op.getValueType();
2874 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2875 SDLoc dl(Op);
2876 SDValue Vec = Op.getOperand(0);
2877 SDValue Val = Op.getOperand(1);
2878 SDValue Idx = Op.getOperand(2);
2879 EVT VecVT = Vec.getValueType();
2880 EVT EltVT = VecVT.getVectorElementType();
2881 int EltSize = EltVT.getSizeInBits();
2882 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2883 EltSize : VTN * EltSize, dl, MVT::i64);
2884
2885 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2886 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2887 const SDValue Ops[] = {Vec, Val, Width, Offset};
2888
2889 SDValue N;
2890 if (VT.getSizeInBits() == 32)
2891 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2892 else if (VT.getSizeInBits() == 64)
2893 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2894 else
2895 return SDValue();
2896
2897 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2898 }
2899
2900 // Variable element number.
2901 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2902 DAG.getConstant(EltSize, dl, MVT::i32));
2903 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2904 DAG.getConstant(32, dl, MVT::i64));
2905 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2906
2907 if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
2908 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2909 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2910 }
2911
2912 const SDValue Ops[] = {Vec, Val, Combined};
2913
2914 SDValue N;
2915 if (VT.getSizeInBits() == 32)
2916 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2917 else if (VT.getSizeInBits() == 64)
2918 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2919 else
2920 return SDValue();
2921
2922 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2923}
2924
2925bool
2926HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2927 // Assuming the caller does not have either a signext or zeroext modifier, and
2928 // only one value is accepted, any reasonable truncation is allowed.
2929 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2930 return false;
2931
2932 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2933 // fragile at the moment: any support for multiple value returns would be
2934 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2935 return Ty1->getPrimitiveSizeInBits() <= 32;
2936}
2937
2938SDValue
2939HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2940 SDValue Chain = Op.getOperand(0);
2941 SDValue Offset = Op.getOperand(1);
2942 SDValue Handler = Op.getOperand(2);
2943 SDLoc dl(Op);
2944 auto PtrVT = getPointerTy(DAG.getDataLayout());
2945
2946 // Mark function as containing a call to EH_RETURN.
2947 HexagonMachineFunctionInfo *FuncInfo =
2948 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2949 FuncInfo->setHasEHReturn();
2950
2951 unsigned OffsetReg = Hexagon::R28;
2952
2953 SDValue StoreAddr =
2954 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2955 DAG.getIntPtrConstant(4, dl));
2956 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2957 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2958
2959 // Not needed we already use it as explict input to EH_RETURN.
2960 // MF.getRegInfo().addLiveOut(OffsetReg);
2961
2962 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2963}
2964
2965SDValue
2966HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2967 unsigned Opc = Op.getOpcode();
2968 switch (Opc) {
2969 default:
2970#ifndef NDEBUG
2971 Op.getNode()->dumpr(&DAG);
2972 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2973 errs() << "Check for a non-legal type in this operation\n";
2974#endif
2975 llvm_unreachable("Should not custom lower this!")::llvm::llvm_unreachable_internal("Should not custom lower this!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2975)
;
2976 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2977 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2978 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2979 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2980 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2981 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2982 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2983 case ISD::SRA:
2984 case ISD::SHL:
2985 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2986 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2987 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2988 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2989 // Frame & Return address. Currently unimplemented.
2990 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2991 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2992 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2993 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2994 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2995 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2996 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2997 case ISD::VASTART: return LowerVASTART(Op, DAG);
2998 // Custom lower some vector loads.
2999 case ISD::LOAD: return LowerLOAD(Op, DAG);
3000 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3001 case ISD::SETCC: return LowerSETCC(Op, DAG);
3002 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3003 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3004 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3005 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
3006 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
3007 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
3008 }
3009}
3010
3011/// Returns relocation base for the given PIC jumptable.
3012SDValue
3013HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3014 SelectionDAG &DAG) const {
3015 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3016 EVT VT = Table.getValueType();
3017 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
3018 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
3019}
3020
3021//===----------------------------------------------------------------------===//
3022// Inline Assembly Support
3023//===----------------------------------------------------------------------===//
3024
3025TargetLowering::ConstraintType
3026HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
3027 if (Constraint.size() == 1) {
3028 switch (Constraint[0]) {
3029 case 'q':
3030 case 'v':
3031 if (Subtarget.useHVXOps())
3032 return C_Register;
3033 break;
3034 }
3035 }
3036 return TargetLowering::getConstraintType(Constraint);
3037}
3038
3039std::pair<unsigned, const TargetRegisterClass*>
3040HexagonTargetLowering::getRegForInlineAsmConstraint(
3041 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3042 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
3043
3044 if (Constraint.size() == 1) {
3045 switch (Constraint[0]) {
3046 case 'r': // R0-R31
3047 switch (VT.SimpleTy) {
3048 default:
3049 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type")::llvm::llvm_unreachable_internal("getRegForInlineAsmConstraint Unhandled data type"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3049)
;
3050 case MVT::i1:
3051 case MVT::i8:
3052 case MVT::i16:
3053 case MVT::i32:
3054 case MVT::f32:
3055 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
3056 case MVT::i64:
3057 case MVT::f64:
3058 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
3059 }
3060 case 'q': // q0-q3
3061 switch (VT.getSizeInBits()) {
3062 default:
3063 llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size")::llvm::llvm_unreachable_internal("getRegForInlineAsmConstraint Unhandled vector size"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3063)
;
3064 case 512:
3065 return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
3066 case 1024:
3067 return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass);
3068 }
3069 case 'v': // V0-V31
3070 switch (VT.getSizeInBits()) {
3071 default:
3072 llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size")::llvm::llvm_unreachable_internal("getRegForInlineAsmConstraint Unhandled vector size"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3072)
;
3073 case 512:
3074 return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
3075 case 1024:
3076 if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
3077 return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
3078 return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
3079 case 2048:
3080 return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
3081 }
3082
3083 default:
3084 llvm_unreachable("Unknown asm register class")::llvm::llvm_unreachable_internal("Unknown asm register class"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3084)
;
3085 }
3086 }
3087
3088 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3089}
3090
3091/// isFPImmLegal - Returns true if the target can instruction select the
3092/// specified FP immediate natively. If false, the legalizer will
3093/// materialize the FP immediate as a load from a constant pool.
3094bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3095 return Subtarget.hasV5TOps();
3096}
3097
3098/// isLegalAddressingMode - Return true if the addressing mode represented by
3099/// AM is legal for this target, for a load/store of the specified type.
3100bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3101 const AddrMode &AM, Type *Ty,
3102 unsigned AS) const {
3103 if (Ty->isSized()) {
3104 // When LSR detects uses of the same base address to access different
3105 // types (e.g. unions), it will assume a conservative type for these
3106 // uses:
3107 // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3108 // The type Ty passed here would then be "void". Skip the alignment
3109 // checks, but do not return false right away, since that confuses
3110 // LSR into crashing.
3111 unsigned A = DL.getABITypeAlignment(Ty);
3112 // The base offset must be a multiple of the alignment.
3113 if ((AM.BaseOffs % A) != 0)
3114 return false;
3115 // The shifted offset must fit in 11 bits.
3116 if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3117 return false;
3118 }
3119
3120 // No global is ever allowed as a base.
3121 if (AM.BaseGV)
3122 return false;
3123
3124 int Scale = AM.Scale;
3125 if (Scale < 0)
3126 Scale = -Scale;
3127 switch (Scale) {
3128 case 0: // No scale reg, "r+i", "r", or just "i".
3129 break;
3130 default: // No scaled addressing mode.
3131 return false;
3132 }
3133 return true;
3134}
3135
3136/// Return true if folding a constant offset with the given GlobalAddress is
3137/// legal. It is frequently not legal in PIC relocation models.
3138bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
3139 const {
3140 return HTM.getRelocationModel() == Reloc::Static;
3141}
3142
3143/// isLegalICmpImmediate - Return true if the specified immediate is legal
3144/// icmp immediate, that is the target has icmp instructions which can compare
3145/// a register against the immediate without having to materialize the
3146/// immediate into a register.
3147bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3148 return Imm >= -512 && Imm <= 511;
3149}
3150
3151/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3152/// for tail call optimization. Targets which want to do tail call
3153/// optimization should implement this function.
3154bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
3155 SDValue Callee,
3156 CallingConv::ID CalleeCC,
3157 bool isVarArg,
3158 bool isCalleeStructRet,
3159 bool isCallerStructRet,
3160 const SmallVectorImpl<ISD::OutputArg> &Outs,
3161 const SmallVectorImpl<SDValue> &OutVals,
3162 const SmallVectorImpl<ISD::InputArg> &Ins,
3163 SelectionDAG& DAG) const {
3164 const Function *CallerF = DAG.getMachineFunction().getFunction();
3165 CallingConv::ID CallerCC = CallerF->getCallingConv();
3166 bool CCMatch = CallerCC == CalleeCC;
3167
3168 // ***************************************************************************
3169 // Look for obvious safe cases to perform tail call optimization that do not
3170 // require ABI changes.
3171 // ***************************************************************************
3172
3173 // If this is a tail call via a function pointer, then don't do it!
3174 if (!isa<GlobalAddressSDNode>(Callee) &&
3175 !isa<ExternalSymbolSDNode>(Callee)) {
3176 return false;
3177 }
3178
3179 // Do not optimize if the calling conventions do not match and the conventions
3180 // used are not C or Fast.
3181 if (!CCMatch) {
3182 bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3183 bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3184 // If R & E, then ok.
3185 if (!R || !E)
3186 return false;
3187 }
3188
3189 // Do not tail call optimize vararg calls.
3190 if (isVarArg)
3191 return false;
3192
3193 // Also avoid tail call optimization if either caller or callee uses struct
3194 // return semantics.
3195 if (isCalleeStructRet || isCallerStructRet)
3196 return false;
3197
3198 // In addition to the cases above, we also disable Tail Call Optimization if
3199 // the calling convention code that at least one outgoing argument needs to
3200 // go on the stack. We cannot check that here because at this point that
3201 // information is not available.
3202 return true;
3203}
3204
3205/// Returns the target specific optimal type for load and store operations as
3206/// a result of memset, memcpy, and memmove lowering.
3207///
3208/// If DstAlign is zero that means it's safe to destination alignment can
3209/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3210/// a need to check it against alignment requirement, probably because the
3211/// source does not need to be loaded. If 'IsMemset' is true, that means it's
3212/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3213/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3214/// does not need to be loaded. It returns EVT::Other if the type should be
3215/// determined using generic target-independent logic.
3216EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size,
3217 unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3218 bool MemcpyStrSrc, MachineFunction &MF) const {
3219
3220 auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3221 return (GivenA % MinA) == 0;
3222 };
3223
3224 if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3225 return MVT::i64;
3226 if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3227 return MVT::i32;
3228 if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3229 return MVT::i16;
3230
3231 return MVT::Other;
3232}
3233
3234bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
3235 unsigned AS, unsigned Align, bool *Fast) const {
3236 if (Fast)
3237 *Fast = false;
3238
3239 switch (VT.getSimpleVT().SimpleTy) {
3240 default:
3241 return false;
3242 case MVT::v64i8:
3243 case MVT::v128i8:
3244 case MVT::v256i8:
3245 case MVT::v32i16:
3246 case MVT::v64i16:
3247 case MVT::v128i16:
3248 case MVT::v16i32:
3249 case MVT::v32i32:
3250 case MVT::v64i32:
3251 case MVT::v8i64:
3252 case MVT::v16i64:
3253 case MVT::v32i64:
3254 return true;
3255 }
3256 return false;
3257}
3258
3259std::pair<const TargetRegisterClass*, uint8_t>
3260HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3261 MVT VT) const {
3262 const TargetRegisterClass *RRC = nullptr;
3263
3264 uint8_t Cost = 1;
3265 switch (VT.SimpleTy) {
3266 default:
3267 return TargetLowering::findRepresentativeClass(TRI, VT);
3268 case MVT::v64i8:
3269 case MVT::v32i16:
3270 case MVT::v16i32:
3271 case MVT::v8i64:
3272 RRC = &Hexagon::VectorRegsRegClass;
3273 break;
3274 case MVT::v128i8:
3275 case MVT::v64i16:
3276 case MVT::v32i32:
3277 case MVT::v16i64:
3278 if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
3279 Subtarget.useHVXDblOps())
3280 RRC = &Hexagon::VectorRegs128BRegClass;
3281 else
3282 RRC = &Hexagon::VecDblRegsRegClass;
3283 break;
3284 case MVT::v256i8:
3285 case MVT::v128i16:
3286 case MVT::v64i32:
3287 case MVT::v32i64:
3288 RRC = &Hexagon::VecDblRegs128BRegClass;
3289 break;
3290 }
3291 return std::make_pair(RRC, Cost);
3292}
3293
3294Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
3295 AtomicOrdering Ord) const {
3296 BasicBlock *BB = Builder.GetInsertBlock();
3297 Module *M = BB->getParent()->getParent();
3298 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3299 unsigned SZ = Ty->getPrimitiveSizeInBits();
3300 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic loads supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3300, __PRETTY_FUNCTION__))
;
3301 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3302 : Intrinsic::hexagon_L4_loadd_locked;
3303 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3304 return Builder.CreateCall(Fn, Addr, "larx");
3305}
3306
3307/// Perform a store-conditional operation to Addr. Return the status of the
3308/// store. This should be 0 if the store succeeded, non-zero otherwise.
3309Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
3310 Value *Val, Value *Addr, AtomicOrdering Ord) const {
3311 BasicBlock *BB = Builder.GetInsertBlock();
3312 Module *M = BB->getParent()->getParent();
3313 Type *Ty = Val->getType();
3314 unsigned SZ = Ty->getPrimitiveSizeInBits();
3315 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic stores supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301235/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3315, __PRETTY_FUNCTION__))
;
3316 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3317 : Intrinsic::hexagon_S4_stored_locked;
3318 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3319 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3320 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3321 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3322 return Ext;
3323}
3324
3325TargetLowering::AtomicExpansionKind
3326HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
3327 // Do not expand loads and stores that don't exceed 64 bits.
3328 return LI->getType()->getPrimitiveSizeInBits() > 64
3329 ? AtomicExpansionKind::LLOnly
3330 : AtomicExpansionKind::None;
3331}
3332
3333bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
3334 // Do not expand loads and stores that don't exceed 64 bits.
3335 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3336}
3337
3338bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
3339 AtomicCmpXchgInst *AI) const {
3340 const DataLayout &DL = AI->getModule()->getDataLayout();
3341 unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3342 return Size >= 4 && Size <= 8;
3343}