Bug Summary

File:lib/Target/Hexagon/HexagonISelLowering.cpp
Warning:line 2823, column 16
Value stored to 'Subreg' during its initialization is never read

Annotated Source Code

1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Hexagon uses to lower LLVM code
11// into a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "Hexagon.h"
16#include "HexagonISelLowering.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonRegisterInfo.h"
19#include "HexagonSubtarget.h"
20#include "HexagonTargetMachine.h"
21#include "HexagonTargetObjectFile.h"
22#include "llvm/ADT/APInt.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/CodeGen/CallingConvLower.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/RuntimeLibcalls.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/SelectionDAG.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/IR/BasicBlock.h"
34#include "llvm/IR/CallingConv.h"
35#include "llvm/IR/DataLayout.h"
36#include "llvm/IR/DerivedTypes.h"
37#include "llvm/IR/Function.h"
38#include "llvm/IR/GlobalValue.h"
39#include "llvm/IR/InlineAsm.h"
40#include "llvm/IR/Instructions.h"
41#include "llvm/IR/Intrinsics.h"
42#include "llvm/IR/Module.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include "llvm/MC/MCRegisterInfo.h"
46#include "llvm/Support/Casting.h"
47#include "llvm/Support/CodeGen.h"
48#include "llvm/Support/CommandLine.h"
49#include "llvm/Support/Debug.h"
50#include "llvm/Support/ErrorHandling.h"
51#include "llvm/Support/MathExtras.h"
52#include "llvm/Support/raw_ostream.h"
53#include "llvm/Target/TargetCallingConv.h"
54#include "llvm/Target/TargetMachine.h"
55#include <algorithm>
56#include <cassert>
57#include <cstddef>
58#include <cstdint>
59#include <limits>
60#include <utility>
61
62using namespace llvm;
63
64#define DEBUG_TYPE"hexagon-lowering" "hexagon-lowering"
65
66static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
67 cl::init(true), cl::Hidden,
68 cl::desc("Control jump table emission on Hexagon target"));
69
70static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
71 cl::Hidden, cl::ZeroOrMore, cl::init(false),
72 cl::desc("Enable Hexagon SDNode scheduling"));
73
74static cl::opt<bool> EnableFastMath("ffast-math",
75 cl::Hidden, cl::ZeroOrMore, cl::init(false),
76 cl::desc("Enable Fast Math processing"));
77
78static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
79 cl::Hidden, cl::ZeroOrMore, cl::init(5),
80 cl::desc("Set minimum jump tables"));
81
82static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
83 cl::Hidden, cl::ZeroOrMore, cl::init(6),
84 cl::desc("Max #stores to inline memcpy"));
85
86static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
87 cl::Hidden, cl::ZeroOrMore, cl::init(4),
88 cl::desc("Max #stores to inline memcpy"));
89
90static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
91 cl::Hidden, cl::ZeroOrMore, cl::init(6),
92 cl::desc("Max #stores to inline memmove"));
93
94static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
95 cl::Hidden, cl::ZeroOrMore, cl::init(4),
96 cl::desc("Max #stores to inline memmove"));
97
98static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
99 cl::Hidden, cl::ZeroOrMore, cl::init(8),
100 cl::desc("Max #stores to inline memset"));
101
102static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
103 cl::Hidden, cl::ZeroOrMore, cl::init(4),
104 cl::desc("Max #stores to inline memset"));
105
106
107namespace {
108
109 class HexagonCCState : public CCState {
110 unsigned NumNamedVarArgParams;
111
112 public:
113 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
114 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
115 int NumNamedVarArgParams)
116 : CCState(CC, isVarArg, MF, locs, C),
117 NumNamedVarArgParams(NumNamedVarArgParams) {}
118
119 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
120 };
121
122 enum StridedLoadKind {
123 Even = 0,
124 Odd,
125 NoPattern
126 };
127
128} // end anonymous namespace
129
130// Implement calling convention for Hexagon.
131
132static bool isHvxVectorType(MVT ty);
133
134static bool
135CC_Hexagon(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
138
139static bool
140CC_Hexagon32(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
143
144static bool
145CC_Hexagon64(unsigned ValNo, MVT ValVT,
146 MVT LocVT, CCValAssign::LocInfo LocInfo,
147 ISD::ArgFlagsTy ArgFlags, CCState &State);
148
149static bool
150CC_HexagonVector(unsigned ValNo, MVT ValVT,
151 MVT LocVT, CCValAssign::LocInfo LocInfo,
152 ISD::ArgFlagsTy ArgFlags, CCState &State);
153
154static bool
155RetCC_Hexagon(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, CCState &State);
158
159static bool
160RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
161 MVT LocVT, CCValAssign::LocInfo LocInfo,
162 ISD::ArgFlagsTy ArgFlags, CCState &State);
163
164static bool
165RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
166 MVT LocVT, CCValAssign::LocInfo LocInfo,
167 ISD::ArgFlagsTy ArgFlags, CCState &State);
168
169static bool
170RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
171 MVT LocVT, CCValAssign::LocInfo LocInfo,
172 ISD::ArgFlagsTy ArgFlags, CCState &State);
173
174static bool
175CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State) {
178 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
179
180 if (ValNo < HState.getNumNamedVarArgParams()) {
181 // Deal with named arguments.
182 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
183 }
184
185 // Deal with un-named arguments.
186 unsigned Offset;
187 if (ArgFlags.isByVal()) {
188 // If pass-by-value, the size allocated on stack is decided
189 // by ArgFlags.getByValSize(), not by the size of LocVT.
190 Offset = State.AllocateStack(ArgFlags.getByValSize(),
191 ArgFlags.getByValAlign());
192 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
193 return false;
194 }
195 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
196 LocVT = MVT::i32;
197 ValVT = MVT::i32;
198 if (ArgFlags.isSExt())
199 LocInfo = CCValAssign::SExt;
200 else if (ArgFlags.isZExt())
201 LocInfo = CCValAssign::ZExt;
202 else
203 LocInfo = CCValAssign::AExt;
204 }
205 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
206 Offset = State.AllocateStack(4, 4);
207 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
208 return false;
209 }
210 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
211 Offset = State.AllocateStack(8, 8);
212 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
213 return false;
214 }
215 if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
216 LocVT == MVT::v16i8) {
217 Offset = State.AllocateStack(16, 16);
218 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
219 return false;
220 }
221 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
222 LocVT == MVT::v32i8) {
223 Offset = State.AllocateStack(32, 32);
224 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
225 return false;
226 }
227 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
228 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
229 Offset = State.AllocateStack(64, 64);
230 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
231 return false;
232 }
233 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
234 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
235 Offset = State.AllocateStack(128, 128);
236 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
237 return false;
238 }
239 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
240 LocVT == MVT::v256i8) {
241 Offset = State.AllocateStack(256, 256);
242 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
243 return false;
244 }
245
246 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 246)
;
247}
248
249static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
250 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
251 if (ArgFlags.isByVal()) {
252 // Passed on stack.
253 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
254 ArgFlags.getByValAlign());
255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
256 return false;
257 }
258
259 if (LocVT == MVT::i1) {
260 LocVT = MVT::i32;
261 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
262 LocVT = MVT::i32;
263 ValVT = MVT::i32;
264 if (ArgFlags.isSExt())
265 LocInfo = CCValAssign::SExt;
266 else if (ArgFlags.isZExt())
267 LocInfo = CCValAssign::ZExt;
268 else
269 LocInfo = CCValAssign::AExt;
270 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
271 LocVT = MVT::i32;
272 LocInfo = CCValAssign::BCvt;
273 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
274 LocVT = MVT::i64;
275 LocInfo = CCValAssign::BCvt;
276 }
277
278 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
279 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
280 return false;
281 }
282
283 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
284 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
285 return false;
286 }
287
288 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
289 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
290 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
291 return false;
292 }
293
294 if (isHvxVectorType(LocVT)) {
295 if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
296 return false;
297 }
298
299 return true; // CC didn't match.
300}
301
302
303static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
304 MVT LocVT, CCValAssign::LocInfo LocInfo,
305 ISD::ArgFlagsTy ArgFlags, CCState &State) {
306 static const MCPhysReg RegList[] = {
307 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
308 Hexagon::R5
309 };
310 if (unsigned Reg = State.AllocateReg(RegList)) {
311 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
312 return false;
313 }
314
315 unsigned Offset = State.AllocateStack(4, 4);
316 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
317 return false;
318}
319
320static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
321 MVT LocVT, CCValAssign::LocInfo LocInfo,
322 ISD::ArgFlagsTy ArgFlags, CCState &State) {
323 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
324 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
325 return false;
326 }
327
328 static const MCPhysReg RegList1[] = {
329 Hexagon::D1, Hexagon::D2
330 };
331 static const MCPhysReg RegList2[] = {
332 Hexagon::R1, Hexagon::R3
333 };
334 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
335 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
336 return false;
337 }
338
339 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
340 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
341 return false;
342}
343
344static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
345 MVT LocVT, CCValAssign::LocInfo LocInfo,
346 ISD::ArgFlagsTy ArgFlags, CCState &State) {
347 static const MCPhysReg VecLstS[] = {
348 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
349 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
350 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
351 Hexagon::V15
352 };
353 static const MCPhysReg VecLstD[] = {
354 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
355 Hexagon::W5, Hexagon::W6, Hexagon::W7
356 };
357 auto &MF = State.getMachineFunction();
358 auto &HST = MF.getSubtarget<HexagonSubtarget>();
359 bool UseHVX = HST.useHVXOps();
360 bool UseHVXDbl = HST.useHVXDblOps();
361
362 if ((UseHVX && !UseHVXDbl) &&
363 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
364 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
365 if (unsigned Reg = State.AllocateReg(VecLstS)) {
366 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
367 return false;
368 }
369 unsigned Offset = State.AllocateStack(64, 64);
370 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
371 return false;
372 }
373 if ((UseHVX && !UseHVXDbl) &&
374 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
375 LocVT == MVT::v128i8)) {
376 if (unsigned Reg = State.AllocateReg(VecLstD)) {
377 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
378 return false;
379 }
380 unsigned Offset = State.AllocateStack(128, 128);
381 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
382 return false;
383 }
384 // 128B Mode
385 if ((UseHVX && UseHVXDbl) &&
386 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
387 LocVT == MVT::v256i8)) {
388 if (unsigned Reg = State.AllocateReg(VecLstD)) {
389 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
390 return false;
391 }
392 unsigned Offset = State.AllocateStack(256, 256);
393 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
394 return false;
395 }
396 if ((UseHVX && UseHVXDbl) &&
397 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
398 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
399 if (unsigned Reg = State.AllocateReg(VecLstS)) {
400 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
401 return false;
402 }
403 unsigned Offset = State.AllocateStack(128, 128);
404 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
405 return false;
406 }
407 return true;
408}
409
410static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
411 MVT LocVT, CCValAssign::LocInfo LocInfo,
412 ISD::ArgFlagsTy ArgFlags, CCState &State) {
413 auto &MF = State.getMachineFunction();
414 auto &HST = MF.getSubtarget<HexagonSubtarget>();
415 bool UseHVX = HST.useHVXOps();
416 bool UseHVXDbl = HST.useHVXDblOps();
417
418 if (LocVT == MVT::i1) {
419 // Return values of type MVT::i1 still need to be assigned to R0, but
420 // the value type needs to remain i1. LowerCallResult will deal with it,
421 // but it needs to recognize i1 as the value type.
422 LocVT = MVT::i32;
423 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
424 LocVT = MVT::i32;
425 ValVT = MVT::i32;
426 if (ArgFlags.isSExt())
427 LocInfo = CCValAssign::SExt;
428 else if (ArgFlags.isZExt())
429 LocInfo = CCValAssign::ZExt;
430 else
431 LocInfo = CCValAssign::AExt;
432 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
433 LocVT = MVT::i32;
434 LocInfo = CCValAssign::BCvt;
435 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
436 LocVT = MVT::i64;
437 LocInfo = CCValAssign::BCvt;
438 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
439 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
440 LocVT == MVT::v512i1) {
441 LocVT = MVT::v16i32;
442 ValVT = MVT::v16i32;
443 LocInfo = CCValAssign::Full;
444 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
445 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
446 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
447 LocVT = MVT::v32i32;
448 ValVT = MVT::v32i32;
449 LocInfo = CCValAssign::Full;
450 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
451 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
452 LocVT = MVT::v64i32;
453 ValVT = MVT::v64i32;
454 LocInfo = CCValAssign::Full;
455 }
456 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
457 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
458 return false;
459 }
460
461 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
462 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
463 return false;
464 }
465 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
466 if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
467 return false;
468 }
469 return true; // CC didn't match.
470}
471
472static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
473 MVT LocVT, CCValAssign::LocInfo LocInfo,
474 ISD::ArgFlagsTy ArgFlags, CCState &State) {
475 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
476 // Note that use of registers beyond R1 is not ABI compliant. However there
477 // are (experimental) IR passes which generate internal functions that
478 // return structs using these additional registers.
479 static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
480 Hexagon::R2, Hexagon::R3,
481 Hexagon::R4, Hexagon::R5 };
482 if (unsigned Reg = State.AllocateReg(RegList)) {
483 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
484 return false;
485 }
486 }
487
488 unsigned Offset = State.AllocateStack(4, 4);
489 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
490 return false;
491}
492
493static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
494 MVT LocVT, CCValAssign::LocInfo LocInfo,
495 ISD::ArgFlagsTy ArgFlags, CCState &State) {
496 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
497 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
498 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
499 return false;
500 }
501 }
502
503 unsigned Offset = State.AllocateStack(8, 8);
504 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
505 return false;
506}
507
508static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
509 MVT LocVT, CCValAssign::LocInfo LocInfo,
510 ISD::ArgFlagsTy ArgFlags, CCState &State) {
511 auto &MF = State.getMachineFunction();
512 auto &HST = MF.getSubtarget<HexagonSubtarget>();
513 bool UseHVX = HST.useHVXOps();
514 bool UseHVXDbl = HST.useHVXDblOps();
515
516 unsigned OffSiz = 64;
517 if (LocVT == MVT::v16i32) {
518 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
519 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
520 return false;
521 }
522 } else if (LocVT == MVT::v32i32) {
523 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
524 if (unsigned Reg = State.AllocateReg(Req)) {
525 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
526 return false;
527 }
528 OffSiz = 128;
529 } else if (LocVT == MVT::v64i32) {
530 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
531 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
532 return false;
533 }
534 OffSiz = 256;
535 }
536
537 unsigned Offset = State.AllocateStack(OffSiz, OffSiz);
538 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
539 return false;
540}
541
542void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
543 if (VT != PromotedLdStVT) {
544 setOperationAction(ISD::LOAD, VT, Promote);
545 AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
546
547 setOperationAction(ISD::STORE, VT, Promote);
548 AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
549 }
550}
551
552SDValue
553HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
554 const {
555 return SDValue();
556}
557
558/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
559/// by "Src" to address "Dst" of size "Size". Alignment information is
560/// specified by the specific parameter attribute. The copy will be passed as
561/// a byval function parameter. Sometimes what we are copying is the end of a
562/// larger object, the part that does not fit in registers.
563static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
564 SDValue Chain, ISD::ArgFlagsTy Flags,
565 SelectionDAG &DAG, const SDLoc &dl) {
566 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
567 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
568 /*isVolatile=*/false, /*AlwaysInline=*/false,
569 /*isTailCall=*/false,
570 MachinePointerInfo(), MachinePointerInfo());
571}
572
573static bool isHvxVectorType(MVT Ty) {
574 switch (Ty.SimpleTy) {
575 case MVT::v8i64:
576 case MVT::v16i32:
577 case MVT::v32i16:
578 case MVT::v64i8:
579 case MVT::v16i64:
580 case MVT::v32i32:
581 case MVT::v64i16:
582 case MVT::v128i8:
583 case MVT::v32i64:
584 case MVT::v64i32:
585 case MVT::v128i16:
586 case MVT::v256i8:
587 case MVT::v512i1:
588 case MVT::v1024i1:
589 return true;
590 default:
591 return false;
592 }
593}
594
595// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
596// passed by value, the function prototype is modified to return void and
597// the value is stored in memory pointed by a pointer passed by caller.
598SDValue
599HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
600 bool isVarArg,
601 const SmallVectorImpl<ISD::OutputArg> &Outs,
602 const SmallVectorImpl<SDValue> &OutVals,
603 const SDLoc &dl, SelectionDAG &DAG) const {
604 // CCValAssign - represent the assignment of the return value to locations.
605 SmallVector<CCValAssign, 16> RVLocs;
606
607 // CCState - Info about the registers and stack slot.
608 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
609 *DAG.getContext());
610
611 // Analyze return values of ISD::RET
612 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
613
614 SDValue Flag;
615 SmallVector<SDValue, 4> RetOps(1, Chain);
616
617 // Copy the result values into the output registers.
618 for (unsigned i = 0; i != RVLocs.size(); ++i) {
619 CCValAssign &VA = RVLocs[i];
620
621 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
622
623 // Guarantee that all emitted copies are stuck together with flags.
624 Flag = Chain.getValue(1);
625 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
626 }
627
628 RetOps[0] = Chain; // Update chain.
629
630 // Add the flag if we have it.
631 if (Flag.getNode())
632 RetOps.push_back(Flag);
633
634 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
635}
636
637bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
638 // If either no tail call or told not to tail call at all, don't.
639 auto Attr =
640 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
641 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
642 return false;
643
644 return true;
645}
646
647/// LowerCallResult - Lower the result values of an ISD::CALL into the
648/// appropriate copies out of appropriate physical registers. This assumes that
649/// Chain/Glue are the input chain/glue to use, and that TheCall is the call
650/// being lowered. Returns a SDNode with the same number of values as the
651/// ISD::CALL.
652SDValue HexagonTargetLowering::LowerCallResult(
653 SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool isVarArg,
654 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
655 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
656 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
657 // Assign locations to each value returned by this call.
658 SmallVector<CCValAssign, 16> RVLocs;
659
660 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
661 *DAG.getContext());
662
663 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
664
665 // Copy all of the result registers out of their specified physreg.
666 for (unsigned i = 0; i != RVLocs.size(); ++i) {
667 SDValue RetVal;
668 if (RVLocs[i].getValVT() == MVT::i1) {
669 // Return values of type MVT::i1 require special handling. The reason
670 // is that MVT::i1 is associated with the PredRegs register class, but
671 // values of that type are still returned in R0. Generate an explicit
672 // copy into a predicate register from R0, and treat the value of the
673 // predicate register as the call result.
674 auto &MRI = DAG.getMachineFunction().getRegInfo();
675 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
676 MVT::i32, Glue);
677 // FR0 = (Value, Chain, Glue)
678 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
679 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
680 FR0.getValue(0), FR0.getValue(2));
681 // TPR = (Chain, Glue)
682 // Don't glue this CopyFromReg, because it copies from a virtual
683 // register. If it is glued to the call, InstrEmitter will add it
684 // as an implicit def to the call (EmitMachineNode).
685 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
686 Glue = TPR.getValue(1);
687 } else {
688 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
689 RVLocs[i].getValVT(), Glue);
690 Glue = RetVal.getValue(2);
691 }
692 InVals.push_back(RetVal.getValue(0));
693 Chain = RetVal.getValue(1);
694 }
695
696 return Chain;
697}
698
699/// LowerCall - Functions arguments are copied from virtual regs to
700/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
701SDValue
702HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
703 SmallVectorImpl<SDValue> &InVals) const {
704 SelectionDAG &DAG = CLI.DAG;
705 SDLoc &dl = CLI.DL;
706 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
707 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
708 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
709 SDValue Chain = CLI.Chain;
710 SDValue Callee = CLI.Callee;
711 bool &IsTailCall = CLI.IsTailCall;
712 CallingConv::ID CallConv = CLI.CallConv;
713 bool IsVarArg = CLI.IsVarArg;
714 bool DoesNotReturn = CLI.DoesNotReturn;
715
716 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
717 MachineFunction &MF = DAG.getMachineFunction();
718 auto PtrVT = getPointerTy(MF.getDataLayout());
719
720 // Check for varargs.
721 unsigned NumNamedVarArgParams = -1U;
722 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
723 const GlobalValue *GV = GAN->getGlobal();
724 Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
725 if (const Function* F = dyn_cast<Function>(GV)) {
726 // If a function has zero args and is a vararg function, that's
727 // disallowed so it must be an undeclared function. Do not assume
728 // varargs if the callee is undefined.
729 if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
730 NumNamedVarArgParams = F->getFunctionType()->getNumParams();
731 }
732 }
733
734 // Analyze operands of the call, assigning locations to each operand.
735 SmallVector<CCValAssign, 16> ArgLocs;
736 HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
737 *DAG.getContext(), NumNamedVarArgParams);
738
739 if (IsVarArg)
740 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
741 else
742 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
743
744 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
745 if (Attr.getValueAsString() == "true")
746 IsTailCall = false;
747
748 if (IsTailCall) {
749 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
750 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
751 IsVarArg, IsStructRet,
752 StructAttrFlag,
753 Outs, OutVals, Ins, DAG);
754 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
755 CCValAssign &VA = ArgLocs[i];
756 if (VA.isMemLoc()) {
757 IsTailCall = false;
758 break;
759 }
760 }
761 DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
762 : "Argument must be passed on stack. "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
763 "Not eligible for Tail Call\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
;
764 }
765 // Get a count of how many bytes are to be pushed on the stack.
766 unsigned NumBytes = CCInfo.getNextStackOffset();
767 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
768 SmallVector<SDValue, 8> MemOpChains;
769
770 auto &HRI = *Subtarget.getRegisterInfo();
771 SDValue StackPtr =
772 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
773
774 bool NeedsArgAlign = false;
775 unsigned LargestAlignSeen = 0;
776 // Walk the register/memloc assignments, inserting copies/loads.
777 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
778 CCValAssign &VA = ArgLocs[i];
779 SDValue Arg = OutVals[i];
780 ISD::ArgFlagsTy Flags = Outs[i].Flags;
781 // Record if we need > 8 byte alignment on an argument.
782 bool ArgAlign = isHvxVectorType(VA.getValVT());
783 NeedsArgAlign |= ArgAlign;
784
785 // Promote the value if needed.
786 switch (VA.getLocInfo()) {
787 default:
788 // Loc info must be one of Full, SExt, ZExt, or AExt.
789 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 789)
;
790 case CCValAssign::BCvt:
791 case CCValAssign::Full:
792 break;
793 case CCValAssign::SExt:
794 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
795 break;
796 case CCValAssign::ZExt:
797 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
798 break;
799 case CCValAssign::AExt:
800 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
801 break;
802 }
803
804 if (VA.isMemLoc()) {
805 unsigned LocMemOffset = VA.getLocMemOffset();
806 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
807 StackPtr.getValueType());
808 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
809 if (ArgAlign)
810 LargestAlignSeen = std::max(LargestAlignSeen,
811 VA.getLocVT().getStoreSizeInBits() >> 3);
812 if (Flags.isByVal()) {
813 // The argument is a struct passed by value. According to LLVM, "Arg"
814 // is is pointer.
815 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
816 Flags, DAG, dl));
817 } else {
818 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
819 DAG.getMachineFunction(), LocMemOffset);
820 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
821 MemOpChains.push_back(S);
822 }
823 continue;
824 }
825
826 // Arguments that can be passed on register must be kept at RegsToPass
827 // vector.
828 if (VA.isRegLoc())
829 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
830 }
831
832 if (NeedsArgAlign && Subtarget.hasV60TOps()) {
833 DEBUG(dbgs() << "Function needs byte stack align due to call args\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << "Function needs byte stack align due to call args\n"
; } } while (false)
;
834 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
835 // V6 vectors passed by value have 64 or 128 byte alignment depending
836 // on whether we are 64 byte vector mode or 128 byte.
837 bool UseHVXDbl = Subtarget.useHVXDblOps();
838 assert(Subtarget.useHVXOps())((Subtarget.useHVXOps()) ? static_cast<void> (0) : __assert_fail
("Subtarget.useHVXOps()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 838, __PRETTY_FUNCTION__))
;
839 const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
840 LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
841 MFI.ensureMaxAlignment(LargestAlignSeen);
842 }
843 // Transform all store nodes into one single node because all store
844 // nodes are independent of each other.
845 if (!MemOpChains.empty())
846 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
847
848 SDValue Glue;
849 if (!IsTailCall) {
850 SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
851 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
852 Glue = Chain.getValue(1);
853 }
854
855 // Build a sequence of copy-to-reg nodes chained together with token
856 // chain and flag operands which copy the outgoing args into registers.
857 // The Glue is necessary since all emitted instructions must be
858 // stuck together.
859 if (!IsTailCall) {
860 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
861 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
862 RegsToPass[i].second, Glue);
863 Glue = Chain.getValue(1);
864 }
865 } else {
866 // For tail calls lower the arguments to the 'real' stack slot.
867 //
868 // Force all the incoming stack arguments to be loaded from the stack
869 // before any new outgoing arguments are stored to the stack, because the
870 // outgoing stack slots may alias the incoming argument stack slots, and
871 // the alias isn't otherwise explicit. This is slightly more conservative
872 // than necessary, because it means that each store effectively depends
873 // on every argument instead of just those arguments it would clobber.
874 //
875 // Do not flag preceding copytoreg stuff together with the following stuff.
876 Glue = SDValue();
877 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
878 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
879 RegsToPass[i].second, Glue);
880 Glue = Chain.getValue(1);
881 }
882 Glue = SDValue();
883 }
884
885 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
886 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
887
888 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
889 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
890 // node so that legalize doesn't hack it.
891 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
892 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
893 } else if (ExternalSymbolSDNode *S =
894 dyn_cast<ExternalSymbolSDNode>(Callee)) {
895 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
896 }
897
898 // Returns a chain & a flag for retval copy to use.
899 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
900 SmallVector<SDValue, 8> Ops;
901 Ops.push_back(Chain);
902 Ops.push_back(Callee);
903
904 // Add argument registers to the end of the list so that they are
905 // known live into the call.
906 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
907 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
908 RegsToPass[i].second.getValueType()));
909 }
910
911 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
912 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 912, __PRETTY_FUNCTION__))
;
913 Ops.push_back(DAG.getRegisterMask(Mask));
914
915 if (Glue.getNode())
916 Ops.push_back(Glue);
917
918 if (IsTailCall) {
919 MF.getFrameInfo().setHasTailCall();
920 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
921 }
922
923 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
924 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
925 Glue = Chain.getValue(1);
926
927 // Create the CALLSEQ_END node.
928 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
929 DAG.getIntPtrConstant(0, dl, true), Glue, dl);
930 Glue = Chain.getValue(1);
931
932 // Handle result values, copying them out of physregs into vregs that we
933 // return.
934 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
935 InVals, OutVals, Callee);
936}
937
938static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
939 SDValue &Base, SDValue &Offset,
940 bool &IsInc, SelectionDAG &DAG) {
941 if (Ptr->getOpcode() != ISD::ADD)
942 return false;
943
944 auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
945 bool UseHVX = HST.useHVXOps();
946 bool UseHVXDbl = HST.useHVXDblOps();
947
948 bool ValidHVXDblType =
949 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
950 VT == MVT::v64i16 || VT == MVT::v128i8);
951 bool ValidHVXType =
952 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
953 VT == MVT::v32i16 || VT == MVT::v64i8);
954
955 if (ValidHVXDblType || ValidHVXType ||
956 VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
957 IsInc = (Ptr->getOpcode() == ISD::ADD);
958 Base = Ptr->getOperand(0);
959 Offset = Ptr->getOperand(1);
960 // Ensure that Offset is a constant.
961 return isa<ConstantSDNode>(Offset);
962 }
963
964 return false;
965}
966
967/// getPostIndexedAddressParts - returns true by value, base pointer and
968/// offset pointer and addressing mode by reference if this node can be
969/// combined with a load / store to form a post-indexed load / store.
970bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
971 SDValue &Base,
972 SDValue &Offset,
973 ISD::MemIndexedMode &AM,
974 SelectionDAG &DAG) const
975{
976 EVT VT;
977 SDValue Ptr;
978
979 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
980 VT = LD->getMemoryVT();
981 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
982 VT = ST->getMemoryVT();
983 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
984 return false;
985 } else {
986 return false;
987 }
988
989 bool IsInc = false;
990 bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
991 if (isLegal) {
992 auto &HII = *Subtarget.getInstrInfo();
993 int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
994 if (HII.isValidAutoIncImm(VT, OffsetVal)) {
995 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
996 return true;
997 }
998 }
999
1000 return false;
1001}
1002
1003SDValue
1004HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
1005 SDNode *Node = Op.getNode();
1006 MachineFunction &MF = DAG.getMachineFunction();
1007 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1008 switch (Node->getOpcode()) {
1009 case ISD::INLINEASM: {
1010 unsigned NumOps = Node->getNumOperands();
1011 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
1012 --NumOps; // Ignore the flag operand.
1013
1014 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1015 if (FuncInfo.hasClobberLR())
1016 break;
1017 unsigned Flags =
1018 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1019 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1020 ++i; // Skip the ID value.
1021
1022 switch (InlineAsm::getKind(Flags)) {
1023 default: llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1023)
;
1024 case InlineAsm::Kind_RegDef:
1025 case InlineAsm::Kind_RegUse:
1026 case InlineAsm::Kind_Imm:
1027 case InlineAsm::Kind_Clobber:
1028 case InlineAsm::Kind_Mem: {
1029 for (; NumVals; --NumVals, ++i) {}
1030 break;
1031 }
1032 case InlineAsm::Kind_RegDefEarlyClobber: {
1033 for (; NumVals; --NumVals, ++i) {
1034 unsigned Reg =
1035 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
1036
1037 // Check it to be lr
1038 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
1039 if (Reg == QRI->getRARegister()) {
1040 FuncInfo.setHasClobberLR(true);
1041 break;
1042 }
1043 }
1044 break;
1045 }
1046 }
1047 }
1048 }
1049 } // Node->getOpcode
1050 return Op;
1051}
1052
1053// Need to transform ISD::PREFETCH into something that doesn't inherit
1054// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
1055// SDNPMayStore.
1056SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
1057 SelectionDAG &DAG) const {
1058 SDValue Chain = Op.getOperand(0);
1059 SDValue Addr = Op.getOperand(1);
1060 // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
1061 // if the "reg" is fed by an "add".
1062 SDLoc DL(Op);
1063 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1064 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1065}
1066
1067// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
1068// is marked as having side-effects, while the register read on Hexagon does
1069// not have any. TableGen refuses to accept the direct pattern from that node
1070// to the A4_tfrcpp.
1071SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
1072 SelectionDAG &DAG) const {
1073 SDValue Chain = Op.getOperand(0);
1074 SDLoc dl(Op);
1075 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1076 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
1077}
1078
1079SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1080 SelectionDAG &DAG) const {
1081 SDValue Chain = Op.getOperand(0);
1082 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1083 // Lower the hexagon_prefetch builtin to DCFETCH, as above.
1084 if (IntNo == Intrinsic::hexagon_prefetch) {
1085 SDValue Addr = Op.getOperand(2);
1086 SDLoc DL(Op);
1087 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1088 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1089 }
1090 return SDValue();
1091}
1092
1093SDValue
1094HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1095 SelectionDAG &DAG) const {
1096 SDValue Chain = Op.getOperand(0);
1097 SDValue Size = Op.getOperand(1);
1098 SDValue Align = Op.getOperand(2);
1099 SDLoc dl(Op);
1100
1101 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1102 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC")((AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC"
) ? static_cast<void> (0) : __assert_fail ("AlignConst && \"Non-constant Align in LowerDYNAMIC_STACKALLOC\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1102, __PRETTY_FUNCTION__))
;
1103
1104 unsigned A = AlignConst->getSExtValue();
1105 auto &HFI = *Subtarget.getFrameLowering();
1106 // "Zero" means natural stack alignment.
1107 if (A == 0)
1108 A = HFI.getStackAlignment();
1109
1110 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1111 dbgs () << __func__ << " Align: " << A << " Size: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1112 Size.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1113 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1114 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
;
1115
1116 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1117 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1118 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1119
1120 DAG.ReplaceAllUsesOfValueWith(Op, AA);
1121 return AA;
1122}
1123
1124SDValue HexagonTargetLowering::LowerFormalArguments(
1125 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1126 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1127 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1128 MachineFunction &MF = DAG.getMachineFunction();
1129 MachineFrameInfo &MFI = MF.getFrameInfo();
1130 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1131 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1132
1133 // Assign locations to all of the incoming arguments.
1134 SmallVector<CCValAssign, 16> ArgLocs;
1135 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1136 *DAG.getContext());
1137
1138 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1139
1140 // For LLVM, in the case when returning a struct by value (>8byte),
1141 // the first argument is a pointer that points to the location on caller's
1142 // stack where the return value will be stored. For Hexagon, the location on
1143 // caller's stack is passed only when the struct size is smaller than (and
1144 // equal to) 8 bytes. If not, no address will be passed into callee and
1145 // callee return the result direclty through R0/R1.
1146
1147 SmallVector<SDValue, 8> MemOps;
1148 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
1149
1150 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1151 CCValAssign &VA = ArgLocs[i];
1152 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1153 unsigned ObjSize;
1154 unsigned StackLocation;
1155 int FI;
1156
1157 if ( (VA.isRegLoc() && !Flags.isByVal())
1158 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1159 // Arguments passed in registers
1160 // 1. int, long long, ptr args that get allocated in register.
1161 // 2. Large struct that gets an register to put its address in.
1162 EVT RegVT = VA.getLocVT();
1163 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1164 RegVT == MVT::i32 || RegVT == MVT::f32) {
1165 unsigned VReg =
1166 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1167 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1168 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1169 // Treat values of type MVT::i1 specially: they are passed in
1170 // registers of type i32, but they need to remain as values of
1171 // type i1 for consistency of the argument lowering.
1172 if (VA.getValVT() == MVT::i1) {
1173 // Generate a copy into a predicate register and use the value
1174 // of the register as the "InVal".
1175 unsigned PReg =
1176 RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass);
1177 SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1178 Copy.getValue(0));
1179 Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0));
1180 Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1);
1181 }
1182 InVals.push_back(Copy);
1183 Chain = Copy.getValue(1);
1184 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1185 unsigned VReg =
1186 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1187 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1188 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1189
1190 // Single Vector
1191 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1192 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1193 unsigned VReg =
1194 RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
1195 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1196 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1197 } else if (UseHVX && UseHVXDbl &&
1198 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1199 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1200 unsigned VReg =
1201 RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
1202 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1203 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1204
1205 // Double Vector
1206 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1207 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1208 unsigned VReg =
1209 RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
1210 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1211 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1212 } else if (UseHVX && UseHVXDbl &&
1213 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1214 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1215 unsigned VReg =
1216 RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
1217 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1218 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1219 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1220 assert(0 && "need to support VecPred regs")((0 && "need to support VecPred regs") ? static_cast<
void> (0) : __assert_fail ("0 && \"need to support VecPred regs\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1220, __PRETTY_FUNCTION__))
;
1221 unsigned VReg =
1222 RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
1223 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1224 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1225 } else {
1226 assert (0)((0) ? static_cast<void> (0) : __assert_fail ("0", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1226, __PRETTY_FUNCTION__))
;
1227 }
1228 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1229 assert (0 && "ByValSize must be bigger than 8 bytes")((0 && "ByValSize must be bigger than 8 bytes") ? static_cast
<void> (0) : __assert_fail ("0 && \"ByValSize must be bigger than 8 bytes\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1229, __PRETTY_FUNCTION__))
;
1230 } else {
1231 // Sanity check.
1232 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1232, __PRETTY_FUNCTION__))
;
1233
1234 if (Flags.isByVal()) {
1235 // If it's a byval parameter, then we need to compute the
1236 // "real" size, not the size of the pointer.
1237 ObjSize = Flags.getByValSize();
1238 } else {
1239 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1240 }
1241
1242 StackLocation = HEXAGON_LRFP_SIZE8 + VA.getLocMemOffset();
1243 // Create the frame index object for this incoming parameter...
1244 FI = MFI.CreateFixedObject(ObjSize, StackLocation, true);
1245
1246 // Create the SelectionDAG nodes cordl, responding to a load
1247 // from this parameter.
1248 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1249
1250 if (Flags.isByVal()) {
1251 // If it's a pass-by-value aggregate, then do not dereference the stack
1252 // location. Instead, we should generate a reference to the stack
1253 // location.
1254 InVals.push_back(FIN);
1255 } else {
1256 InVals.push_back(
1257 DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, MachinePointerInfo()));
1258 }
1259 }
1260 }
1261
1262 if (!MemOps.empty())
1263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1264
1265 if (isVarArg) {
1266 // This will point to the next argument passed via stack.
1267 int FrameIndex = MFI.CreateFixedObject(Hexagon_PointerSize(4),
1268 HEXAGON_LRFP_SIZE8 +
1269 CCInfo.getNextStackOffset(),
1270 true);
1271 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1272 }
1273
1274 return Chain;
1275}
1276
1277SDValue
1278HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1279 // VASTART stores the address of the VarArgsFrameIndex slot into the
1280 // memory location argument.
1281 MachineFunction &MF = DAG.getMachineFunction();
1282 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
1283 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1284 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1285 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
1286 MachinePointerInfo(SV));
1287}
1288
1289// Creates a SPLAT instruction for a constant value VAL.
1290static SDValue createSplat(SelectionDAG &DAG, const SDLoc &dl, EVT VT,
1291 SDValue Val) {
1292 if (VT.getSimpleVT() == MVT::v4i8)
1293 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
1294
1295 if (VT.getSimpleVT() == MVT::v4i16)
1296 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
1297
1298 return SDValue();
1299}
1300
1301static bool isSExtFree(SDValue N) {
1302 // A sign-extend of a truncate of a sign-extend is free.
1303 if (N.getOpcode() == ISD::TRUNCATE &&
1304 N.getOperand(0).getOpcode() == ISD::AssertSext)
1305 return true;
1306 // We have sign-extended loads.
1307 if (N.getOpcode() == ISD::LOAD)
1308 return true;
1309 return false;
1310}
1311
1312SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1313 SDLoc dl(Op);
1314
1315 SDValue LHS = Op.getOperand(0);
1316 SDValue RHS = Op.getOperand(1);
1317 SDValue Cmp = Op.getOperand(2);
1318 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1319
1320 EVT VT = Op.getValueType();
1321 EVT LHSVT = LHS.getValueType();
1322 EVT RHSVT = RHS.getValueType();
1323
1324 if (LHSVT == MVT::v2i16) {
1325 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC))((ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)) ?
static_cast<void> (0) : __assert_fail ("ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1325, __PRETTY_FUNCTION__))
;
1326 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1327 : ISD::ZERO_EXTEND;
1328 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1329 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1330 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1331 return SC;
1332 }
1333
1334 // Treat all other vector types as legal.
1335 if (VT.isVector())
1336 return Op;
1337
1338 // Equals and not equals should use sign-extend, not zero-extend, since
1339 // we can represent small negative values in the compare instructions.
1340 // The LLVM default is to use zero-extend arbitrarily in these cases.
1341 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1342 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1343 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1344 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1345 if (C && C->getAPIntValue().isNegative()) {
1346 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1347 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1348 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1349 LHS, RHS, Op.getOperand(2));
1350 }
1351 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1352 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1353 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1354 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1355 LHS, RHS, Op.getOperand(2));
1356 }
1357 }
1358 return SDValue();
1359}
1360
1361SDValue
1362HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
1363 SDValue PredOp = Op.getOperand(0);
1364 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1365 EVT OpVT = Op1.getValueType();
1366 SDLoc DL(Op);
1367
1368 if (OpVT == MVT::v2i16) {
1369 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1370 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1371 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1372 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1373 return TR;
1374 }
1375
1376 return SDValue();
1377}
1378
1379// Handle only specific vector loads.
1380SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1381 EVT VT = Op.getValueType();
1382 SDLoc DL(Op);
1383 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1384 SDValue Chain = LoadNode->getChain();
1385 SDValue Ptr = Op.getOperand(1);
1386 SDValue LoweredLoad;
1387 SDValue Result;
1388 SDValue Base = LoadNode->getBasePtr();
1389 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1390 unsigned Alignment = LoadNode->getAlignment();
1391 SDValue LoadChain;
1392
1393 if(Ext == ISD::NON_EXTLOAD)
1394 Ext = ISD::ZEXTLOAD;
1395
1396 if (VT == MVT::v4i16) {
1397 if (Alignment == 2) {
1398 SDValue Loads[4];
1399 // Base load.
1400 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1401 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1402 LoadNode->getMemOperand()->getFlags());
1403 // Base+2 load.
1404 SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1405 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1406 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1407 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1408 LoadNode->getMemOperand()->getFlags());
1409 // SHL 16, then OR base and base+2.
1410 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1411 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1412 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1413 // Base + 4.
1414 Increment = DAG.getConstant(4, DL, MVT::i32);
1415 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1416 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1417 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1418 LoadNode->getMemOperand()->getFlags());
1419 // Base + 6.
1420 Increment = DAG.getConstant(6, DL, MVT::i32);
1421 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1422 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1423 LoadNode->getPointerInfo(), MVT::i16, Alignment,
1424 LoadNode->getMemOperand()->getFlags());
1425 // SHL 16, then OR base+4 and base+6.
1426 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1427 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1428 // Combine to i64. This could be optimised out later if we can
1429 // affect reg allocation of this code.
1430 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1431 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1432 Loads[0].getValue(1), Loads[1].getValue(1),
1433 Loads[2].getValue(1), Loads[3].getValue(1));
1434 } else {
1435 // Perform default type expansion.
1436 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1437 LoadNode->getAlignment(),
1438 LoadNode->getMemOperand()->getFlags());
1439 LoadChain = Result.getValue(1);
1440 }
1441 } else
1442 llvm_unreachable("Custom lowering unsupported load")::llvm::llvm_unreachable_internal("Custom lowering unsupported load"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1442)
;
1443
1444 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1445 // Since we pretend to lower a load, we need the original chain
1446 // info attached to the result.
1447 SDValue Ops[] = { Result, LoadChain };
1448
1449 return DAG.getMergeValues(Ops, DL);
1450}
1451
1452SDValue
1453HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1454 EVT ValTy = Op.getValueType();
1455 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1456 unsigned Align = CPN->getAlignment();
1457 bool IsPositionIndependent = isPositionIndependent();
1458 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1459
1460 unsigned Offset = 0;
1461 SDValue T;
1462 if (CPN->isMachineConstantPoolEntry())
1463 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
1464 TF);
1465 else
1466 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
1467 TF);
1468
1469 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1470, __PRETTY_FUNCTION__))
1470 "Inconsistent target flag encountered")((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1470, __PRETTY_FUNCTION__))
;
1471
1472 if (IsPositionIndependent)
1473 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1474 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1475}
1476
1477SDValue
1478HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1479 EVT VT = Op.getValueType();
1480 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1481 if (isPositionIndependent()) {
1482 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1483 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1484 }
1485
1486 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1487 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1488}
1489
1490SDValue
1491HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1492 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1493 MachineFunction &MF = DAG.getMachineFunction();
1494 MachineFrameInfo &MFI = MF.getFrameInfo();
1495 MFI.setReturnAddressIsTaken(true);
1496
1497 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1498 return SDValue();
1499
1500 EVT VT = Op.getValueType();
1501 SDLoc dl(Op);
1502 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1503 if (Depth) {
1504 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1505 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1506 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1507 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1508 MachinePointerInfo());
1509 }
1510
1511 // Return LR, which contains the return address. Mark it an implicit live-in.
1512 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1513 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1514}
1515
1516SDValue
1517HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1518 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1519 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1520 MFI.setFrameAddressIsTaken(true);
1521
1522 EVT VT = Op.getValueType();
1523 SDLoc dl(Op);
1524 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1525 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1526 HRI.getFrameRegister(), VT);
1527 while (Depth--)
1528 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1529 MachinePointerInfo());
1530 return FrameAddr;
1531}
1532
1533SDValue
1534HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
1535 SDLoc dl(Op);
1536 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1537}
1538
1539SDValue
1540HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
1541 SDLoc dl(Op);
1542 auto *GAN = cast<GlobalAddressSDNode>(Op);
1543 auto PtrVT = getPointerTy(DAG.getDataLayout());
1544 auto *GV = GAN->getGlobal();
1545 int64_t Offset = GAN->getOffset();
1546
1547 auto &HLOF = *HTM.getObjFileLowering();
1548 Reloc::Model RM = HTM.getRelocationModel();
1549
1550 if (RM == Reloc::Static) {
1551 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1552 const GlobalObject *GO = GV->getBaseObject();
1553 if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1554 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1555 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1556 }
1557
1558 bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1559 if (UsePCRel) {
1560 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1561 HexagonII::MO_PCREL);
1562 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1563 }
1564
1565 // Use GOT index.
1566 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1567 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1568 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1569 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1570}
1571
1572// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1573SDValue
1574HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1575 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1576 SDLoc dl(Op);
1577 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1578
1579 Reloc::Model RM = HTM.getRelocationModel();
1580 if (RM == Reloc::Static) {
1581 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1582 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1583 }
1584
1585 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1586 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1587}
1588
1589SDValue
1590HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
1591 const {
1592 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1593 SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME"_GLOBAL_OFFSET_TABLE_", PtrVT,
1594 HexagonII::MO_PCREL);
1595 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1596}
1597
1598SDValue
1599HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
1600 GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1601 unsigned char OperandFlags) const {
1602 MachineFunction &MF = DAG.getMachineFunction();
1603 MachineFrameInfo &MFI = MF.getFrameInfo();
1604 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1605 SDLoc dl(GA);
1606 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1607 GA->getValueType(0),
1608 GA->getOffset(),
1609 OperandFlags);
1610 // Create Operands for the call.The Operands should have the following:
1611 // 1. Chain SDValue
1612 // 2. Callee which in this case is the Global address value.
1613 // 3. Registers live into the call.In this case its R0, as we
1614 // have just one argument to be passed.
1615 // 4. Glue.
1616 // Note: The order is important.
1617
1618 const auto &HRI = *Subtarget.getRegisterInfo();
1619 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1620 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1620, __PRETTY_FUNCTION__))
;
1621 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1622 DAG.getRegisterMask(Mask), Glue };
1623 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1624
1625 // Inform MFI that function has calls.
1626 MFI.setAdjustsStack(true);
1627
1628 Glue = Chain.getValue(1);
1629 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1630}
1631
1632//
1633// Lower using the intial executable model for TLS addresses
1634//
1635SDValue
1636HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
1637 SelectionDAG &DAG) const {
1638 SDLoc dl(GA);
1639 int64_t Offset = GA->getOffset();
1640 auto PtrVT = getPointerTy(DAG.getDataLayout());
1641
1642 // Get the thread pointer.
1643 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1644
1645 bool IsPositionIndependent = isPositionIndependent();
1646 unsigned char TF =
1647 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1648
1649 // First generate the TLS symbol address
1650 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1651 Offset, TF);
1652
1653 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1654
1655 if (IsPositionIndependent) {
1656 // Generate the GOT pointer in case of position independent code
1657 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1658
1659 // Add the TLS Symbol address to GOT pointer.This gives
1660 // GOT relative relocation for the symbol.
1661 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1662 }
1663
1664 // Load the offset value for TLS symbol.This offset is relative to
1665 // thread pointer.
1666 SDValue LoadOffset =
1667 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1668
1669 // Address of the thread local variable is the add of thread
1670 // pointer and the offset of the variable.
1671 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1672}
1673
1674//
1675// Lower using the local executable model for TLS addresses
1676//
1677SDValue
1678HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
1679 SelectionDAG &DAG) const {
1680 SDLoc dl(GA);
1681 int64_t Offset = GA->getOffset();
1682 auto PtrVT = getPointerTy(DAG.getDataLayout());
1683
1684 // Get the thread pointer.
1685 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1686 // Generate the TLS symbol address
1687 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1688 HexagonII::MO_TPREL);
1689 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1690
1691 // Address of the thread local variable is the add of thread
1692 // pointer and the offset of the variable.
1693 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1694}
1695
1696//
1697// Lower using the general dynamic model for TLS addresses
1698//
1699SDValue
1700HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1701 SelectionDAG &DAG) const {
1702 SDLoc dl(GA);
1703 int64_t Offset = GA->getOffset();
1704 auto PtrVT = getPointerTy(DAG.getDataLayout());
1705
1706 // First generate the TLS symbol address
1707 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1708 HexagonII::MO_GDGOT);
1709
1710 // Then, generate the GOT pointer
1711 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1712
1713 // Add the TLS symbol and the GOT pointer
1714 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1715 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1716
1717 // Copy over the argument to R0
1718 SDValue InFlag;
1719 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1720 InFlag = Chain.getValue(1);
1721
1722 return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1723 Hexagon::R0, HexagonII::MO_GDPLT);
1724}
1725
1726//
1727// Lower TLS addresses.
1728//
1729// For now for dynamic models, we only support the general dynamic model.
1730//
1731SDValue
1732HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1733 SelectionDAG &DAG) const {
1734 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1735
1736 switch (HTM.getTLSModel(GA->getGlobal())) {
1737 case TLSModel::GeneralDynamic:
1738 case TLSModel::LocalDynamic:
1739 return LowerToTLSGeneralDynamicModel(GA, DAG);
1740 case TLSModel::InitialExec:
1741 return LowerToTLSInitialExecModel(GA, DAG);
1742 case TLSModel::LocalExec:
1743 return LowerToTLSLocalExecModel(GA, DAG);
1744 }
1745 llvm_unreachable("Bogus TLS model")::llvm::llvm_unreachable_internal("Bogus TLS model", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1745)
;
1746}
1747
1748//===----------------------------------------------------------------------===//
1749// TargetLowering Implementation
1750//===----------------------------------------------------------------------===//
1751
1752HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1753 const HexagonSubtarget &ST)
1754 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1755 Subtarget(ST) {
1756 bool IsV4 = !Subtarget.hasV5TOps();
1757 auto &HRI = *Subtarget.getRegisterInfo();
1758 bool UseHVX = Subtarget.useHVXOps();
1759 bool UseHVXSgl = Subtarget.useHVXSglOps();
1760 bool UseHVXDbl = Subtarget.useHVXDblOps();
1761
1762 setPrefLoopAlignment(4);
1763 setPrefFunctionAlignment(4);
1764 setMinFunctionAlignment(2);
1765 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1766
1767 setMaxAtomicSizeInBitsSupported(64);
1768 setMinCmpXchgSizeInBits(32);
1769
1770 if (EnableHexSDNodeSched)
1771 setSchedulingPreference(Sched::VLIW);
1772 else
1773 setSchedulingPreference(Sched::Source);
1774
1775 // Limits for inline expansion of memcpy/memmove
1776 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1777 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1778 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1779 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1780 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1781 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1782
1783 //
1784 // Set up register classes.
1785 //
1786
1787 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1788 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1789 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1790 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1791 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1792 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1793 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1794 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1795 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1796 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1797 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1798
1799 if (Subtarget.hasV5TOps()) {
1800 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1801 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1802 }
1803
1804 if (Subtarget.hasV60TOps()) {
1805 if (Subtarget.useHVXSglOps()) {
1806 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass);
1807 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
1808 addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
1809 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass);
1810 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
1811 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
1812 addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
1813 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
1814 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
1815 } else if (Subtarget.useHVXDblOps()) {
1816 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass);
1817 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass);
1818 addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass);
1819 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass);
1820 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass);
1821 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
1822 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass);
1823 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
1824 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
1825 }
1826 }
1827
1828 //
1829 // Handling of scalar operations.
1830 //
1831 // All operations default to "legal", except:
1832 // - indexed loads and stores (pre-/post-incremented),
1833 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1834 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1835 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1836 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1837 // which default to "expand" for at least one type.
1838
1839 // Misc operations.
1840 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1841 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1842
1843 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1844 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1845 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1846 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1847 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1848 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1849 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1850 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1851 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1852 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1853 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1854 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1855
1856 // Custom legalize GlobalAddress nodes into CONST32.
1857 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1858 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1859 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1860
1861 // Hexagon needs to optimize cases with negative constants.
1862 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1863 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1864
1865 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1866 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1867 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1868 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1869
1870 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1871 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1872 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1873
1874 if (EmitJumpTables)
1875 setMinimumJumpTableEntries(MinimumJumpTables);
1876 else
1877 setMinimumJumpTableEntries(std::numeric_limits<int>::max());
1878 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1879
1880 // Hexagon has instructions for add/sub with carry. The problem with
1881 // modeling these instructions is that they produce 2 results: Rdd and Px.
1882 // To model the update of Px, we will have to use Defs[p0..p3] which will
1883 // cause any predicate live range to spill. So, we pretend we dont't have
1884 // these instructions.
1885 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1886 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1887 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1888 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1889 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1890 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1891 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1892 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1893 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1894 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1895 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1896 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1897 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1898 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1899 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1900 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1901
1902 // Only add and sub that detect overflow are the saturating ones.
1903 for (MVT VT : MVT::integer_valuetypes()) {
1904 setOperationAction(ISD::UADDO, VT, Expand);
1905 setOperationAction(ISD::SADDO, VT, Expand);
1906 setOperationAction(ISD::USUBO, VT, Expand);
1907 setOperationAction(ISD::SSUBO, VT, Expand);
1908 }
1909
1910 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1911 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1912 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1913 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1914
1915 // In V5, popcount can count # of 1s in i64 but returns i32.
1916 // On V4 it will be expanded (set later).
1917 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1918 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1919 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1920 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1921
1922 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1923 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
1924 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
1925 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
1926
1927 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1928 // operation. There is a pattern that will match i64 mul and transform it
1929 // to a series of instructions.
1930 setOperationAction(ISD::MUL, MVT::i64, Expand);
1931
1932 for (unsigned IntExpOp :
1933 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1934 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1935 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1936 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1937 setOperationAction(IntExpOp, MVT::i32, Expand);
1938 setOperationAction(IntExpOp, MVT::i64, Expand);
1939 }
1940
1941 for (unsigned FPExpOp :
1942 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1943 ISD::FPOW, ISD::FCOPYSIGN}) {
1944 setOperationAction(FPExpOp, MVT::f32, Expand);
1945 setOperationAction(FPExpOp, MVT::f64, Expand);
1946 }
1947
1948 // No extending loads from i32.
1949 for (MVT VT : MVT::integer_valuetypes()) {
1950 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1951 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1952 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1953 }
1954 // Turn FP truncstore into trunc + store.
1955 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1956 // Turn FP extload into load/fpextend.
1957 for (MVT VT : MVT::fp_valuetypes())
1958 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1959
1960 // Expand BR_CC and SELECT_CC for all integer and fp types.
1961 for (MVT VT : MVT::integer_valuetypes()) {
1962 setOperationAction(ISD::BR_CC, VT, Expand);
1963 setOperationAction(ISD::SELECT_CC, VT, Expand);
1964 }
1965 for (MVT VT : MVT::fp_valuetypes()) {
1966 setOperationAction(ISD::BR_CC, VT, Expand);
1967 setOperationAction(ISD::SELECT_CC, VT, Expand);
1968 }
1969 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1970
1971 //
1972 // Handling of vector operations.
1973 //
1974
1975 // Custom lower v4i16 load only. Let v4i16 store to be
1976 // promoted for now.
1977 promoteLdStType(MVT::v4i8, MVT::i32);
1978 promoteLdStType(MVT::v2i16, MVT::i32);
1979 promoteLdStType(MVT::v8i8, MVT::i64);
1980 promoteLdStType(MVT::v2i32, MVT::i64);
1981
1982 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1983 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1984 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1985 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1986
1987 // Set the action for vector operations to "expand", then override it with
1988 // either "custom" or "legal" for specific cases.
1989 static const unsigned VectExpOps[] = {
1990 // Integer arithmetic:
1991 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1992 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1993 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1994 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1995 // Logical/bit:
1996 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1997 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
1998 // Floating point arithmetic/math functions:
1999 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
2000 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
2001 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
2002 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
2003 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
2004 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
2005 // Misc:
2006 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
2007 // Vector:
2008 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
2009 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
2010 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
2011 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
2012 };
2013
2014 for (MVT VT : MVT::vector_valuetypes()) {
2015 for (unsigned VectExpOp : VectExpOps)
2016 setOperationAction(VectExpOp, VT, Expand);
2017
2018 // Expand all extending loads and truncating stores:
2019 for (MVT TargetVT : MVT::vector_valuetypes()) {
2020 if (TargetVT == VT)
2021 continue;
2022 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
2023 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
2024 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
2025 setTruncStoreAction(VT, TargetVT, Expand);
2026 }
2027
2028 // Normalize all inputs to SELECT to be vectors of i32.
2029 if (VT.getVectorElementType() != MVT::i32) {
2030 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
2031 setOperationAction(ISD::SELECT, VT, Promote);
2032 AddPromotedToType(ISD::SELECT, VT, VT32);
2033 }
2034 setOperationAction(ISD::SRA, VT, Custom);
2035 setOperationAction(ISD::SHL, VT, Custom);
2036 setOperationAction(ISD::SRL, VT, Custom);
2037 }
2038
2039 // Types natively supported:
2040 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
2041 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
2042 MVT::v2i32, MVT::v1i64}) {
2043 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
2044 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
2045 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
2046 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
2047 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
2048 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
2049
2050 setOperationAction(ISD::ADD, NativeVT, Legal);
2051 setOperationAction(ISD::SUB, NativeVT, Legal);
2052 setOperationAction(ISD::MUL, NativeVT, Legal);
2053 setOperationAction(ISD::AND, NativeVT, Legal);
2054 setOperationAction(ISD::OR, NativeVT, Legal);
2055 setOperationAction(ISD::XOR, NativeVT, Legal);
2056 }
2057
2058 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
2059 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
2060 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
2061 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
2062
2063 if (UseHVX) {
2064 if (UseHVXSgl) {
2065 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
2066 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
2067 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
2068 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
2069 // We try to generate the vpack{e/o} instructions. If we fail
2070 // we fall back upon ExpandOp.
2071 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
2072 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
2073 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
2074 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
2075 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
2076 } else if (UseHVXDbl) {
2077 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
2078 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
2079 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
2080 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
2081 // We try to generate the vpack{e/o} instructions. If we fail
2082 // we fall back upon ExpandOp.
2083 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom);
2084 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom);
2085 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
2086 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v128i8, Custom);
2087 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i16, Custom);
2088 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
2089 } else {
2090 llvm_unreachable("Unrecognized HVX mode")::llvm::llvm_unreachable_internal("Unrecognized HVX mode", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2090)
;
2091 }
2092 }
2093 // Subtarget-specific operation actions.
2094 //
2095 if (Subtarget.hasV5TOps()) {
2096 setOperationAction(ISD::FMA, MVT::f64, Expand);
2097 setOperationAction(ISD::FADD, MVT::f64, Expand);
2098 setOperationAction(ISD::FSUB, MVT::f64, Expand);
2099 setOperationAction(ISD::FMUL, MVT::f64, Expand);
2100
2101 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
2102 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
2103
2104 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
2105 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
2106 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
2107 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
2108 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
2109 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
2110 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
2111 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
2112 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
2113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
2114 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
2115 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
2116 } else { // V4
2117 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
2118 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
2119 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
2120 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
2121 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
2122 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
2123 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
2124 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
2125 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
2126
2127 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
2128 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
2129 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
2130 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
2131
2132 // Expand these operations for both f32 and f64:
2133 for (unsigned FPExpOpV4 :
2134 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
2135 setOperationAction(FPExpOpV4, MVT::f32, Expand);
2136 setOperationAction(FPExpOpV4, MVT::f64, Expand);
2137 }
2138
2139 for (ISD::CondCode FPExpCCV4 :
2140 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
2141 ISD::SETUO, ISD::SETO}) {
2142 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
2143 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
2144 }
2145 }
2146
2147 // Handling of indexed loads/stores: default is "expand".
2148 //
2149 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
2150 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2151 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2152 }
2153
2154 if (UseHVXSgl) {
2155 for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
2156 MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
2157 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2158 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2159 }
2160 } else if (UseHVXDbl) {
2161 for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
2162 MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
2163 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2164 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2165 }
2166 }
2167
2168 computeRegisterProperties(&HRI);
2169
2170 //
2171 // Library calls for unsupported operations
2172 //
2173 bool FastMath = EnableFastMath;
2174
2175 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
2176 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
2177 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
2178 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
2179 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
2180 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
2181 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
2182 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
2183
2184 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
2185 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
2186 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
2187 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
2188 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
2189 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
2190
2191 if (IsV4) {
2192 // Handle single-precision floating point operations on V4.
2193 if (FastMath) {
2194 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
2195 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
2196 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
2197 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
2198 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
2199 // Double-precision compares.
2200 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
2201 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
2202 } else {
2203 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
2204 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
2205 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
2206 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
2207 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
2208 // Double-precision compares.
2209 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
2210 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
2211 }
2212 }
2213
2214 // This is the only fast library function for sqrtd.
2215 if (FastMath)
2216 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
2217
2218 // Prefix is: nothing for "slow-math",
2219 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
2220 // (actually, keep fast-math and fast-math2 separate for now)
2221 if (FastMath) {
2222 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
2223 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
2224 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
2225 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
2226 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
2227 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
2228 } else {
2229 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
2230 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
2231 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
2232 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
2233 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
2234 }
2235
2236 if (Subtarget.hasV5TOps()) {
2237 if (FastMath)
2238 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
2239 else
2240 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
2241 } else {
2242 // V4
2243 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
2244 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
2245 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
2246 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
2247 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
2248 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
2249 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
2250 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
2251 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
2252 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
2253 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
2254 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
2255 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
2256 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
2257 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
2258 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
2259 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
2260 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
2261 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
2262 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
2263 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
2264 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
2265 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
2266 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
2267 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
2268 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
2269 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
2270 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
2271 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
2272 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
2273 }
2274
2275 // These cause problems when the shift amount is non-constant.
2276 setLibcallName(RTLIB::SHL_I128, nullptr);
2277 setLibcallName(RTLIB::SRL_I128, nullptr);
2278 setLibcallName(RTLIB::SRA_I128, nullptr);
2279}
2280
2281const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2282 switch ((HexagonISD::NodeType)Opcode) {
2283 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2284 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2285 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2286 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2287 case HexagonISD::CALL: return "HexagonISD::CALL";
2288 case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
2289 case HexagonISD::CALLR: return "HexagonISD::CALLR";
2290 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2291 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2292 case HexagonISD::CONST32: return "HexagonISD::CONST32";
2293 case HexagonISD::CP: return "HexagonISD::CP";
2294 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2295 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2296 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2297 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2298 case HexagonISD::INSERT: return "HexagonISD::INSERT";
2299 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2300 case HexagonISD::JT: return "HexagonISD::JT";
2301 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2302 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2303 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
2304 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
2305 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
2306 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
2307 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2308 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
2309 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
2310 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
2311 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
2312 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
2313 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
2314 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
2315 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
2316 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
2317 case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2318 case HexagonISD::VPACK: return "HexagonISD::VPACK";
2319 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
2320 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
2321 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
2322 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
2323 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
2324 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
2325 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
2326 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
2327 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
2328 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
2329 case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
2330 case HexagonISD::OP_END: break;
2331 }
2332 return nullptr;
2333}
2334
2335bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
2336 EVT MTy1 = EVT::getEVT(Ty1);
2337 EVT MTy2 = EVT::getEVT(Ty2);
2338 if (!MTy1.isSimple() || !MTy2.isSimple())
2339 return false;
2340 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2341}
2342
2343bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
2344 if (!VT1.isSimple() || !VT2.isSimple())
2345 return false;
2346 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2347}
2348
2349bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
2350 return isOperationLegalOrCustom(ISD::FMA, VT);
2351}
2352
2353// Should we expand the build vector with shuffles?
2354bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
2355 unsigned DefinedValues) const {
2356 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2357 EVT EltVT = VT.getVectorElementType();
2358 int EltBits = EltVT.getSizeInBits();
2359 if ((EltBits != 8) && (EltBits != 16))
2360 return false;
2361
2362 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2363}
2364
2365static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
2366 int even_start = -2;
2367 int odd_start = -1;
2368 size_t mask_len = Mask.size();
2369 for (auto idx : Mask) {
2370 if ((idx - even_start) == 2)
2371 even_start = idx;
2372 else
2373 break;
2374 }
2375 if (even_start == (int)(mask_len * 2) - 2)
2376 return StridedLoadKind::Even;
2377 for (auto idx : Mask) {
2378 if ((idx - odd_start) == 2)
2379 odd_start = idx;
2380 else
2381 break;
2382 }
2383 if (odd_start == (int)(mask_len * 2) - 1)
2384 return StridedLoadKind::Odd;
2385
2386 return StridedLoadKind::NoPattern;
2387}
2388
2389bool HexagonTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
2390 EVT VT) const {
2391 if (Subtarget.useHVXOps())
2392 return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
2393 return true;
2394}
2395
2396// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2397// to select data from, V3 is the permutation.
2398SDValue
2399HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
2400 const {
2401 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2402 SDValue V1 = Op.getOperand(0);
2403 SDValue V2 = Op.getOperand(1);
2404 SDLoc dl(Op);
2405 EVT VT = Op.getValueType();
2406 bool UseHVX = Subtarget.useHVXOps();
2407
2408 if (V2.isUndef())
2409 V2 = V1;
2410
2411 if (SVN->isSplat()) {
2412 int Lane = SVN->getSplatIndex();
2413 if (Lane == -1) Lane = 0;
2414
2415 // Test if V1 is a SCALAR_TO_VECTOR.
2416 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2417 return createSplat(DAG, dl, VT, V1.getOperand(0));
2418
2419 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2420 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2421 // reaches it).
2422 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2423 !isa<ConstantSDNode>(V1.getOperand(0))) {
2424 bool IsScalarToVector = true;
2425 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
2426 if (!V1.getOperand(i).isUndef()) {
2427 IsScalarToVector = false;
2428 break;
2429 }
2430 }
2431 if (IsScalarToVector)
2432 return createSplat(DAG, dl, VT, V1.getOperand(0));
2433 }
2434 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
2435 }
2436
2437 if (UseHVX) {
2438 ArrayRef<int> Mask = SVN->getMask();
2439 size_t MaskLen = Mask.size();
2440 int ElemSizeInBits = VT.getScalarSizeInBits();
2441 if ((Subtarget.useHVXSglOps() && (ElemSizeInBits * MaskLen) == 64 * 8) ||
2442 (Subtarget.useHVXDblOps() && (ElemSizeInBits * MaskLen) == 128 * 8)) {
2443 // Return 1 for odd and 2 of even
2444 StridedLoadKind Pattern = isStridedLoad(Mask);
2445
2446 if (Pattern == StridedLoadKind::NoPattern)
2447 return SDValue();
2448
2449 SDValue Vec0 = Op.getOperand(0);
2450 SDValue Vec1 = Op.getOperand(1);
2451 SDValue StridePattern = DAG.getConstant(Pattern, dl, MVT::i32);
2452 SDValue Ops[] = { Vec1, Vec0, StridePattern };
2453 return DAG.getNode(HexagonISD::VPACK, dl, VT, Ops);
2454 }
2455 // We used to assert in the "else" part here, but that is bad for Halide
2456 // Halide creates intermediate double registers by interleaving two
2457 // concatenated vector registers. The interleaving requires vector_shuffle
2458 // nodes and we shouldn't barf on a double register result of a
2459 // vector_shuffle because it is most likely an intermediate result.
2460 }
2461 // FIXME: We need to support more general vector shuffles. See
2462 // below the comment from the ARM backend that deals in the general
2463 // case with the vector shuffles. For now, let expand handle these.
2464 return SDValue();
2465
2466 // If the shuffle is not directly supported and it has 4 elements, use
2467 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2468}
2469
2470// If BUILD_VECTOR has same base element repeated several times,
2471// report true.
2472static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
2473 unsigned NElts = BVN->getNumOperands();
2474 SDValue V0 = BVN->getOperand(0);
2475
2476 for (unsigned i = 1, e = NElts; i != e; ++i) {
2477 if (BVN->getOperand(i) != V0)
2478 return false;
2479 }
2480 return true;
2481}
2482
2483// Lower a vector shift. Try to convert
2484// <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2485// <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
2486SDValue
2487HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
2488 BuildVectorSDNode *BVN = nullptr;
2489 SDValue V1 = Op.getOperand(0);
2490 SDValue V2 = Op.getOperand(1);
2491 SDValue V3;
2492 SDLoc dl(Op);
2493 EVT VT = Op.getValueType();
2494
2495 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2496 isCommonSplatElement(BVN))
2497 V3 = V2;
2498 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2499 isCommonSplatElement(BVN))
2500 V3 = V1;
2501 else
2502 return SDValue();
2503
2504 SDValue CommonSplat = BVN->getOperand(0);
2505 SDValue Result;
2506
2507 if (VT.getSimpleVT() == MVT::v4i16) {
2508 switch (Op.getOpcode()) {
2509 case ISD::SRA:
2510 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
2511 break;
2512 case ISD::SHL:
2513 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
2514 break;
2515 case ISD::SRL:
2516 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
2517 break;
2518 default:
2519 return SDValue();
2520 }
2521 } else if (VT.getSimpleVT() == MVT::v2i32) {
2522 switch (Op.getOpcode()) {
2523 case ISD::SRA:
2524 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
2525 break;
2526 case ISD::SHL:
2527 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
2528 break;
2529 case ISD::SRL:
2530 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
2531 break;
2532 default:
2533 return SDValue();
2534 }
2535 } else {
2536 return SDValue();
2537 }
2538
2539 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2540}
2541
2542SDValue
2543HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
2544 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2545 SDLoc dl(Op);
2546 EVT VT = Op.getValueType();
2547
2548 unsigned Size = VT.getSizeInBits();
2549
2550 // Only handle vectors of 64 bits or shorter.
2551 if (Size > 64)
2552 return SDValue();
2553
2554 APInt APSplatBits, APSplatUndef;
2555 unsigned SplatBitSize;
2556 bool HasAnyUndefs;
2557 unsigned NElts = BVN->getNumOperands();
2558
2559 // Try to generate a SPLAT instruction.
2560 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2561 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2562 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
2563 unsigned SplatBits = APSplatBits.getZExtValue();
2564 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2565 (32 - SplatBitSize));
2566 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
2567 }
2568
2569 // Try to generate COMBINE to build v2i32 vectors.
2570 if (VT.getSimpleVT() == MVT::v2i32) {
2571 SDValue V0 = BVN->getOperand(0);
2572 SDValue V1 = BVN->getOperand(1);
2573
2574 if (V0.isUndef())
2575 V0 = DAG.getConstant(0, dl, MVT::i32);
2576 if (V1.isUndef())
2577 V1 = DAG.getConstant(0, dl, MVT::i32);
2578
2579 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2580 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
2581 // If the element isn't a constant, it is in a register:
2582 // generate a COMBINE Register Register instruction.
2583 if (!C0 || !C1)
2584 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2585
2586 // If one of the operands is an 8 bit integer constant, generate
2587 // a COMBINE Immediate Immediate instruction.
2588 if (isInt<8>(C0->getSExtValue()) ||
2589 isInt<8>(C1->getSExtValue()))
2590 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2591 }
2592
2593 // Try to generate a S2_packhl to build v2i16 vectors.
2594 if (VT.getSimpleVT() == MVT::v2i16) {
2595 for (unsigned i = 0, e = NElts; i != e; ++i) {
2596 if (BVN->getOperand(i).isUndef())
2597 continue;
2598 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
2599 // If the element isn't a constant, it is in a register:
2600 // generate a S2_packhl instruction.
2601 if (!Cst) {
2602 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2603 BVN->getOperand(1), BVN->getOperand(0));
2604
2605 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
2606 pack);
2607 }
2608 }
2609 }
2610
2611 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2612 // and insert_vector_elt for all the other cases.
2613 uint64_t Res = 0;
2614 unsigned EltSize = Size / NElts;
2615 SDValue ConstVal;
2616 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2617 bool HasNonConstantElements = false;
2618
2619 for (unsigned i = 0, e = NElts; i != e; ++i) {
2620 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2621 // combine, const64, etc. are Big Endian.
2622 unsigned OpIdx = NElts - i - 1;
2623 SDValue Operand = BVN->getOperand(OpIdx);
2624 if (Operand.isUndef())
2625 continue;
2626
2627 int64_t Val = 0;
2628 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2629 Val = Cst->getSExtValue();
2630 else
2631 HasNonConstantElements = true;
2632
2633 Val &= Mask;
2634 Res = (Res << EltSize) | Val;
2635 }
2636
2637 if (Size > 64)
2638 return SDValue();
2639
2640 if (Size == 64)
2641 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2642 else
2643 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2644
2645 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2646 // ConstVal, the constant part of the vector.
2647 if (HasNonConstantElements) {
2648 EVT EltVT = VT.getVectorElementType();
2649 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2650 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2651 DAG.getConstant(32, dl, MVT::i64));
2652
2653 for (unsigned i = 0, e = NElts; i != e; ++i) {
2654 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2655 // is Big Endian.
2656 unsigned OpIdx = NElts - i - 1;
2657 SDValue Operand = BVN->getOperand(OpIdx);
2658 if (isa<ConstantSDNode>(Operand))
2659 // This operand is already in ConstVal.
2660 continue;
2661
2662 if (VT.getSizeInBits() == 64 &&
2663 Operand.getValueSizeInBits() == 32) {
2664 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2665 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2666 }
2667
2668 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2669 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2670 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2671 const SDValue Ops[] = {ConstVal, Operand, Combined};
2672
2673 if (VT.getSizeInBits() == 32)
2674 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2675 else
2676 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2677 }
2678 }
2679
2680 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2681}
2682
2683SDValue
2684HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2685 SelectionDAG &DAG) const {
2686 SDLoc dl(Op);
2687 bool UseHVX = Subtarget.useHVXOps();
2688 EVT VT = Op.getValueType();
2689 unsigned NElts = Op.getNumOperands();
2690 SDValue Vec0 = Op.getOperand(0);
2691 EVT VecVT = Vec0.getValueType();
2692 unsigned Width = VecVT.getSizeInBits();
2693
2694 if (NElts == 2) {
2695 MVT ST = VecVT.getSimpleVT();
2696 // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2697 // into a single v8i8.
2698 if (ST == MVT::v2i16 || ST == MVT::v4i8)
2699 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2700
2701 if (UseHVX) {
2702 assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||(((Width == 64*8 && Subtarget.useHVXSglOps()) || (Width
== 128*8 && Subtarget.useHVXDblOps())) ? static_cast
<void> (0) : __assert_fail ("(Width == 64*8 && Subtarget.useHVXSglOps()) || (Width == 128*8 && Subtarget.useHVXDblOps())"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2703, __PRETTY_FUNCTION__))
2703 (Width == 128*8 && Subtarget.useHVXDblOps()))(((Width == 64*8 && Subtarget.useHVXSglOps()) || (Width
== 128*8 && Subtarget.useHVXDblOps())) ? static_cast
<void> (0) : __assert_fail ("(Width == 64*8 && Subtarget.useHVXSglOps()) || (Width == 128*8 && Subtarget.useHVXDblOps())"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2703, __PRETTY_FUNCTION__))
;
2704 SDValue Vec1 = Op.getOperand(1);
2705 MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
2706 MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
2707 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2708 SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2709 SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2710 return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2711 }
2712 }
2713
2714 if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2715 return SDValue();
2716
2717 SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2718 SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2719 SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2720 // Create the "width" part of the argument to insert_rp/insertp_rp.
2721 SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2722 SDValue V = C0;
2723
2724 for (unsigned i = 0, e = NElts; i != e; ++i) {
2725 unsigned N = NElts-i-1;
2726 SDValue OpN = Op.getOperand(N);
2727
2728 if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
2729 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2730 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2731 }
2732 SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2733 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2734 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2735 if (VT.getSizeInBits() == 32)
2736 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2737 else if (VT.getSizeInBits() == 64)
2738 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2739 else
2740 return SDValue();
2741 }
2742
2743 return DAG.getNode(ISD::BITCAST, dl, VT, V);
2744}
2745
2746SDValue
2747HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
2748 SelectionDAG &DAG) const {
2749 EVT VT = Op.getOperand(0).getValueType();
2750 SDLoc dl(Op);
2751 bool UseHVX = Subtarget.useHVXOps();
2752 bool UseHVXSgl = Subtarget.useHVXSglOps();
2753 // Just in case...
2754
2755 if (!VT.isVector() || !UseHVX)
2756 return SDValue();
2757
2758 EVT ResVT = Op.getValueType();
2759 unsigned ResSize = ResVT.getSizeInBits();
2760 unsigned VectorSizeInBits = UseHVXSgl ? (64 * 8) : (128 * 8);
2761 unsigned OpSize = VT.getSizeInBits();
2762
2763 // We deal only with cases where the result is the vector size
2764 // and the vector operand is a double register.
2765 if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
2766 !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
2767 return SDValue();
2768
2769 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2770 if (!Cst)
2771 return SDValue();
2772 unsigned Val = Cst->getZExtValue();
2773
2774 // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
2775 if (Val == 0) {
2776 SDValue Vec = Op.getOperand(0);
2777 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
2778 }
2779
2780 if (ResVT.getVectorNumElements() == Val) {
2781 SDValue Vec = Op.getOperand(0);
2782 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
2783 }
2784
2785 return SDValue();
2786}
2787
2788SDValue
2789HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2790 SelectionDAG &DAG) const {
2791 // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
2792 // be able to simplify it to an EXTRACT_SUBREG.
2793 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
2794 isHvxVectorType(Op.getValueType().getSimpleVT()))
2795 return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
2796
2797 EVT VT = Op.getValueType();
2798 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2799 SDLoc dl(Op);
2800 SDValue Idx = Op.getOperand(1);
2801 SDValue Vec = Op.getOperand(0);
2802 EVT VecVT = Vec.getValueType();
2803 EVT EltVT = VecVT.getVectorElementType();
2804 int EltSize = EltVT.getSizeInBits();
2805 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2806 EltSize : VTN * EltSize, dl, MVT::i64);
2807
2808 // Constant element number.
2809 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2810 uint64_t X = CI->getZExtValue();
2811 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2812 const SDValue Ops[] = {Vec, Width, Offset};
2813
2814 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2815 assert(CW && "Non constant width in LowerEXTRACT_VECTOR")((CW && "Non constant width in LowerEXTRACT_VECTOR") ?
static_cast<void> (0) : __assert_fail ("CW && \"Non constant width in LowerEXTRACT_VECTOR\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2815, __PRETTY_FUNCTION__))
;
2816
2817 SDValue N;
2818 MVT SVT = VecVT.getSimpleVT();
2819 uint64_t W = CW->getZExtValue();
2820
2821 if (W == 32) {
2822 // Translate this node into EXTRACT_SUBREG.
2823 unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
Value stored to 'Subreg' during its initialization is never read
2824
2825 if (X == 0)
2826 Subreg = Hexagon::isub_lo;
2827 else if (SVT == MVT::v2i32 && X == 1)
2828 Subreg = Hexagon::isub_hi;
2829 else if (SVT == MVT::v4i16 && X == 2)
2830 Subreg = Hexagon::isub_hi;
2831 else if (SVT == MVT::v8i8 && X == 4)
2832 Subreg = Hexagon::isub_hi;
2833 else
2834 llvm_unreachable("Bad offset")::llvm::llvm_unreachable_internal("Bad offset", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2834)
;
2835 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2836
2837 } else if (SVT.getSizeInBits() == 32) {
2838 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2839 } else if (SVT.getSizeInBits() == 64) {
2840 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2841 if (VT.getSizeInBits() == 32)
2842 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2843 } else
2844 return SDValue();
2845
2846 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2847 }
2848
2849 // Variable element number.
2850 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2851 DAG.getConstant(EltSize, dl, MVT::i32));
2852 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2853 DAG.getConstant(32, dl, MVT::i64));
2854 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2855
2856 const SDValue Ops[] = {Vec, Combined};
2857
2858 SDValue N;
2859 if (VecVT.getSizeInBits() == 32) {
2860 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2861 } else {
2862 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2863 if (VT.getSizeInBits() == 32)
2864 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2865 }
2866 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2867}
2868
2869SDValue
2870HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2871 SelectionDAG &DAG) const {
2872 EVT VT = Op.getValueType();
2873 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2874 SDLoc dl(Op);
2875 SDValue Vec = Op.getOperand(0);
2876 SDValue Val = Op.getOperand(1);
2877 SDValue Idx = Op.getOperand(2);
2878 EVT VecVT = Vec.getValueType();
2879 EVT EltVT = VecVT.getVectorElementType();
2880 int EltSize = EltVT.getSizeInBits();
2881 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2882 EltSize : VTN * EltSize, dl, MVT::i64);
2883
2884 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2885 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2886 const SDValue Ops[] = {Vec, Val, Width, Offset};
2887
2888 SDValue N;
2889 if (VT.getSizeInBits() == 32)
2890 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2891 else if (VT.getSizeInBits() == 64)
2892 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2893 else
2894 return SDValue();
2895
2896 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2897 }
2898
2899 // Variable element number.
2900 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2901 DAG.getConstant(EltSize, dl, MVT::i32));
2902 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2903 DAG.getConstant(32, dl, MVT::i64));
2904 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2905
2906 if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
2907 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2908 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2909 }
2910
2911 const SDValue Ops[] = {Vec, Val, Combined};
2912
2913 SDValue N;
2914 if (VT.getSizeInBits() == 32)
2915 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2916 else if (VT.getSizeInBits() == 64)
2917 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2918 else
2919 return SDValue();
2920
2921 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2922}
2923
2924bool
2925HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2926 // Assuming the caller does not have either a signext or zeroext modifier, and
2927 // only one value is accepted, any reasonable truncation is allowed.
2928 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2929 return false;
2930
2931 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2932 // fragile at the moment: any support for multiple value returns would be
2933 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2934 return Ty1->getPrimitiveSizeInBits() <= 32;
2935}
2936
2937SDValue
2938HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2939 SDValue Chain = Op.getOperand(0);
2940 SDValue Offset = Op.getOperand(1);
2941 SDValue Handler = Op.getOperand(2);
2942 SDLoc dl(Op);
2943 auto PtrVT = getPointerTy(DAG.getDataLayout());
2944
2945 // Mark function as containing a call to EH_RETURN.
2946 HexagonMachineFunctionInfo *FuncInfo =
2947 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2948 FuncInfo->setHasEHReturn();
2949
2950 unsigned OffsetReg = Hexagon::R28;
2951
2952 SDValue StoreAddr =
2953 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2954 DAG.getIntPtrConstant(4, dl));
2955 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2956 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2957
2958 // Not needed we already use it as explict input to EH_RETURN.
2959 // MF.getRegInfo().addLiveOut(OffsetReg);
2960
2961 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2962}
2963
2964SDValue
2965HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2966 unsigned Opc = Op.getOpcode();
2967 switch (Opc) {
2968 default:
2969#ifndef NDEBUG
2970 Op.getNode()->dumpr(&DAG);
2971 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2972 errs() << "Check for a non-legal type in this operation\n";
2973#endif
2974 llvm_unreachable("Should not custom lower this!")::llvm::llvm_unreachable_internal("Should not custom lower this!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2974)
;
2975 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2976 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2977 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2978 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2979 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2980 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2981 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2982 case ISD::SRA:
2983 case ISD::SHL:
2984 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2985 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2986 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2987 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2988 // Frame & Return address. Currently unimplemented.
2989 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2990 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2991 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2992 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2993 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2994 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2995 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2996 case ISD::VASTART: return LowerVASTART(Op, DAG);
2997 // Custom lower some vector loads.
2998 case ISD::LOAD: return LowerLOAD(Op, DAG);
2999 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3000 case ISD::SETCC: return LowerSETCC(Op, DAG);
3001 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
3002 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3003 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
3004 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
3005 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
3006 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
3007 }
3008}
3009
3010/// Returns relocation base for the given PIC jumptable.
3011SDValue
3012HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
3013 SelectionDAG &DAG) const {
3014 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
3015 EVT VT = Table.getValueType();
3016 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
3017 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
3018}
3019
3020//===----------------------------------------------------------------------===//
3021// Inline Assembly Support
3022//===----------------------------------------------------------------------===//
3023
3024TargetLowering::ConstraintType
3025HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
3026 if (Constraint.size() == 1) {
3027 switch (Constraint[0]) {
3028 case 'q':
3029 case 'v':
3030 if (Subtarget.useHVXOps())
3031 return C_Register;
3032 break;
3033 }
3034 }
3035 return TargetLowering::getConstraintType(Constraint);
3036}
3037
3038std::pair<unsigned, const TargetRegisterClass*>
3039HexagonTargetLowering::getRegForInlineAsmConstraint(
3040 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3041 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
3042
3043 if (Constraint.size() == 1) {
3044 switch (Constraint[0]) {
3045 case 'r': // R0-R31
3046 switch (VT.SimpleTy) {
3047 default:
3048 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type")::llvm::llvm_unreachable_internal("getRegForInlineAsmConstraint Unhandled data type"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3048)
;
3049 case MVT::i1:
3050 case MVT::i8:
3051 case MVT::i16:
3052 case MVT::i32:
3053 case MVT::f32:
3054 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
3055 case MVT::i64:
3056 case MVT::f64:
3057 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
3058 }
3059 case 'q': // q0-q3
3060 switch (VT.getSizeInBits()) {
3061 default:
3062 llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size")::llvm::llvm_unreachable_internal("getRegForInlineAsmConstraint Unhandled vector size"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3062)
;
3063 case 512:
3064 return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
3065 case 1024:
3066 return std::make_pair(0U, &Hexagon::VecPredRegs128BRegClass);
3067 }
3068 case 'v': // V0-V31
3069 switch (VT.getSizeInBits()) {
3070 default:
3071 llvm_unreachable("getRegForInlineAsmConstraint Unhandled vector size")::llvm::llvm_unreachable_internal("getRegForInlineAsmConstraint Unhandled vector size"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3071)
;
3072 case 512:
3073 return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
3074 case 1024:
3075 if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
3076 return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
3077 return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
3078 case 2048:
3079 return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
3080 }
3081
3082 default:
3083 llvm_unreachable("Unknown asm register class")::llvm::llvm_unreachable_internal("Unknown asm register class"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3083)
;
3084 }
3085 }
3086
3087 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3088}
3089
3090/// isFPImmLegal - Returns true if the target can instruction select the
3091/// specified FP immediate natively. If false, the legalizer will
3092/// materialize the FP immediate as a load from a constant pool.
3093bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3094 return Subtarget.hasV5TOps();
3095}
3096
3097/// isLegalAddressingMode - Return true if the addressing mode represented by
3098/// AM is legal for this target, for a load/store of the specified type.
3099bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3100 const AddrMode &AM, Type *Ty,
3101 unsigned AS) const {
3102 if (Ty->isSized()) {
3103 // When LSR detects uses of the same base address to access different
3104 // types (e.g. unions), it will assume a conservative type for these
3105 // uses:
3106 // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3107 // The type Ty passed here would then be "void". Skip the alignment
3108 // checks, but do not return false right away, since that confuses
3109 // LSR into crashing.
3110 unsigned A = DL.getABITypeAlignment(Ty);
3111 // The base offset must be a multiple of the alignment.
3112 if ((AM.BaseOffs % A) != 0)
3113 return false;
3114 // The shifted offset must fit in 11 bits.
3115 if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3116 return false;
3117 }
3118
3119 // No global is ever allowed as a base.
3120 if (AM.BaseGV)
3121 return false;
3122
3123 int Scale = AM.Scale;
3124 if (Scale < 0)
3125 Scale = -Scale;
3126 switch (Scale) {
3127 case 0: // No scale reg, "r+i", "r", or just "i".
3128 break;
3129 default: // No scaled addressing mode.
3130 return false;
3131 }
3132 return true;
3133}
3134
3135/// Return true if folding a constant offset with the given GlobalAddress is
3136/// legal. It is frequently not legal in PIC relocation models.
3137bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
3138 const {
3139 return HTM.getRelocationModel() == Reloc::Static;
3140}
3141
3142/// isLegalICmpImmediate - Return true if the specified immediate is legal
3143/// icmp immediate, that is the target has icmp instructions which can compare
3144/// a register against the immediate without having to materialize the
3145/// immediate into a register.
3146bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3147 return Imm >= -512 && Imm <= 511;
3148}
3149
3150/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3151/// for tail call optimization. Targets which want to do tail call
3152/// optimization should implement this function.
3153bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
3154 SDValue Callee,
3155 CallingConv::ID CalleeCC,
3156 bool isVarArg,
3157 bool isCalleeStructRet,
3158 bool isCallerStructRet,
3159 const SmallVectorImpl<ISD::OutputArg> &Outs,
3160 const SmallVectorImpl<SDValue> &OutVals,
3161 const SmallVectorImpl<ISD::InputArg> &Ins,
3162 SelectionDAG& DAG) const {
3163 const Function *CallerF = DAG.getMachineFunction().getFunction();
3164 CallingConv::ID CallerCC = CallerF->getCallingConv();
3165 bool CCMatch = CallerCC == CalleeCC;
3166
3167 // ***************************************************************************
3168 // Look for obvious safe cases to perform tail call optimization that do not
3169 // require ABI changes.
3170 // ***************************************************************************
3171
3172 // If this is a tail call via a function pointer, then don't do it!
3173 if (!isa<GlobalAddressSDNode>(Callee) &&
3174 !isa<ExternalSymbolSDNode>(Callee)) {
3175 return false;
3176 }
3177
3178 // Do not optimize if the calling conventions do not match and the conventions
3179 // used are not C or Fast.
3180 if (!CCMatch) {
3181 bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3182 bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3183 // If R & E, then ok.
3184 if (!R || !E)
3185 return false;
3186 }
3187
3188 // Do not tail call optimize vararg calls.
3189 if (isVarArg)
3190 return false;
3191
3192 // Also avoid tail call optimization if either caller or callee uses struct
3193 // return semantics.
3194 if (isCalleeStructRet || isCallerStructRet)
3195 return false;
3196
3197 // In addition to the cases above, we also disable Tail Call Optimization if
3198 // the calling convention code that at least one outgoing argument needs to
3199 // go on the stack. We cannot check that here because at this point that
3200 // information is not available.
3201 return true;
3202}
3203
3204/// Returns the target specific optimal type for load and store operations as
3205/// a result of memset, memcpy, and memmove lowering.
3206///
3207/// If DstAlign is zero that means it's safe to destination alignment can
3208/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3209/// a need to check it against alignment requirement, probably because the
3210/// source does not need to be loaded. If 'IsMemset' is true, that means it's
3211/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3212/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3213/// does not need to be loaded. It returns EVT::Other if the type should be
3214/// determined using generic target-independent logic.
3215EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size,
3216 unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3217 bool MemcpyStrSrc, MachineFunction &MF) const {
3218
3219 auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3220 return (GivenA % MinA) == 0;
3221 };
3222
3223 if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3224 return MVT::i64;
3225 if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3226 return MVT::i32;
3227 if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3228 return MVT::i16;
3229
3230 return MVT::Other;
3231}
3232
3233bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
3234 unsigned AS, unsigned Align, bool *Fast) const {
3235 if (Fast)
3236 *Fast = false;
3237
3238 switch (VT.getSimpleVT().SimpleTy) {
3239 default:
3240 return false;
3241 case MVT::v64i8:
3242 case MVT::v128i8:
3243 case MVT::v256i8:
3244 case MVT::v32i16:
3245 case MVT::v64i16:
3246 case MVT::v128i16:
3247 case MVT::v16i32:
3248 case MVT::v32i32:
3249 case MVT::v64i32:
3250 case MVT::v8i64:
3251 case MVT::v16i64:
3252 case MVT::v32i64:
3253 return true;
3254 }
3255 return false;
3256}
3257
3258std::pair<const TargetRegisterClass*, uint8_t>
3259HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3260 MVT VT) const {
3261 const TargetRegisterClass *RRC = nullptr;
3262
3263 uint8_t Cost = 1;
3264 switch (VT.SimpleTy) {
3265 default:
3266 return TargetLowering::findRepresentativeClass(TRI, VT);
3267 case MVT::v64i8:
3268 case MVT::v32i16:
3269 case MVT::v16i32:
3270 case MVT::v8i64:
3271 RRC = &Hexagon::VectorRegsRegClass;
3272 break;
3273 case MVT::v128i8:
3274 case MVT::v64i16:
3275 case MVT::v32i32:
3276 case MVT::v16i64:
3277 if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
3278 Subtarget.useHVXDblOps())
3279 RRC = &Hexagon::VectorRegs128BRegClass;
3280 else
3281 RRC = &Hexagon::VecDblRegsRegClass;
3282 break;
3283 case MVT::v256i8:
3284 case MVT::v128i16:
3285 case MVT::v64i32:
3286 case MVT::v32i64:
3287 RRC = &Hexagon::VecDblRegs128BRegClass;
3288 break;
3289 }
3290 return std::make_pair(RRC, Cost);
3291}
3292
3293Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
3294 AtomicOrdering Ord) const {
3295 BasicBlock *BB = Builder.GetInsertBlock();
3296 Module *M = BB->getParent()->getParent();
3297 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3298 unsigned SZ = Ty->getPrimitiveSizeInBits();
3299 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic loads supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3299, __PRETTY_FUNCTION__))
;
3300 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3301 : Intrinsic::hexagon_L4_loadd_locked;
3302 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3303 return Builder.CreateCall(Fn, Addr, "larx");
3304}
3305
3306/// Perform a store-conditional operation to Addr. Return the status of the
3307/// store. This should be 0 if the store succeeded, non-zero otherwise.
3308Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
3309 Value *Val, Value *Addr, AtomicOrdering Ord) const {
3310 BasicBlock *BB = Builder.GetInsertBlock();
3311 Module *M = BB->getParent()->getParent();
3312 Type *Ty = Val->getType();
3313 unsigned SZ = Ty->getPrimitiveSizeInBits();
3314 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic stores supported\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn298304/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3314, __PRETTY_FUNCTION__))
;
3315 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3316 : Intrinsic::hexagon_S4_stored_locked;
3317 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3318 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3319 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3320 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3321 return Ext;
3322}
3323
3324TargetLowering::AtomicExpansionKind
3325HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
3326 // Do not expand loads and stores that don't exceed 64 bits.
3327 return LI->getType()->getPrimitiveSizeInBits() > 64
3328 ? AtomicExpansionKind::LLOnly
3329 : AtomicExpansionKind::None;
3330}
3331
3332bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
3333 // Do not expand loads and stores that don't exceed 64 bits.
3334 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3335}
3336
3337bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
3338 AtomicCmpXchgInst *AI) const {
3339 const DataLayout &DL = AI->getModule()->getDataLayout();
3340 unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3341 return Size >= 4 && Size <= 8;
3342}