Bug Summary

File:lib/Target/Hexagon/HexagonISelLowering.cpp
Warning:line 1045, column 10
Called C++ object pointer is null

Annotated Source Code

/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp

1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Hexagon uses to lower LLVM code
11// into a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "HexagonISelLowering.h"
16#include "Hexagon.h"
17#include "HexagonMachineFunctionInfo.h"
18#include "HexagonRegisterInfo.h"
19#include "HexagonSubtarget.h"
20#include "HexagonTargetMachine.h"
21#include "HexagonTargetObjectFile.h"
22#include "llvm/ADT/APInt.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/SmallVector.h"
25#include "llvm/CodeGen/CallingConvLower.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/RuntimeLibcalls.h"
31#include "llvm/CodeGen/SelectionDAG.h"
32#include "llvm/CodeGen/ValueTypes.h"
33#include "llvm/IR/BasicBlock.h"
34#include "llvm/IR/CallingConv.h"
35#include "llvm/IR/DataLayout.h"
36#include "llvm/IR/DerivedTypes.h"
37#include "llvm/IR/Function.h"
38#include "llvm/IR/GlobalValue.h"
39#include "llvm/IR/InlineAsm.h"
40#include "llvm/IR/Instructions.h"
41#include "llvm/IR/Intrinsics.h"
42#include "llvm/IR/Module.h"
43#include "llvm/IR/Type.h"
44#include "llvm/IR/Value.h"
45#include "llvm/MC/MCRegisterInfo.h"
46#include "llvm/Support/Casting.h"
47#include "llvm/Support/CodeGen.h"
48#include "llvm/Support/CommandLine.h"
49#include "llvm/Support/Debug.h"
50#include "llvm/Support/ErrorHandling.h"
51#include "llvm/Support/MathExtras.h"
52#include "llvm/Support/raw_ostream.h"
53#include "llvm/Target/TargetCallingConv.h"
54#include "llvm/Target/TargetMachine.h"
55#include <algorithm>
56#include <cassert>
57#include <cstddef>
58#include <cstdint>
59#include <limits>
60#include <utility>
61
62using namespace llvm;
63
64#define DEBUG_TYPE"hexagon-lowering" "hexagon-lowering"
65
66static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
67 cl::init(true), cl::Hidden,
68 cl::desc("Control jump table emission on Hexagon target"));
69
70static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
71 cl::Hidden, cl::ZeroOrMore, cl::init(false),
72 cl::desc("Enable Hexagon SDNode scheduling"));
73
74static cl::opt<bool> EnableFastMath("ffast-math",
75 cl::Hidden, cl::ZeroOrMore, cl::init(false),
76 cl::desc("Enable Fast Math processing"));
77
78static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
79 cl::Hidden, cl::ZeroOrMore, cl::init(5),
80 cl::desc("Set minimum jump tables"));
81
82static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
83 cl::Hidden, cl::ZeroOrMore, cl::init(6),
84 cl::desc("Max #stores to inline memcpy"));
85
86static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
87 cl::Hidden, cl::ZeroOrMore, cl::init(4),
88 cl::desc("Max #stores to inline memcpy"));
89
90static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
91 cl::Hidden, cl::ZeroOrMore, cl::init(6),
92 cl::desc("Max #stores to inline memmove"));
93
94static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
95 cl::Hidden, cl::ZeroOrMore, cl::init(4),
96 cl::desc("Max #stores to inline memmove"));
97
98static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
99 cl::Hidden, cl::ZeroOrMore, cl::init(8),
100 cl::desc("Max #stores to inline memset"));
101
102static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
103 cl::Hidden, cl::ZeroOrMore, cl::init(4),
104 cl::desc("Max #stores to inline memset"));
105
106
107namespace {
108
109 class HexagonCCState : public CCState {
110 unsigned NumNamedVarArgParams;
111
112 public:
113 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
114 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
115 int NumNamedVarArgParams)
116 : CCState(CC, isVarArg, MF, locs, C),
117 NumNamedVarArgParams(NumNamedVarArgParams) {}
118
119 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
120 };
121
122 enum StridedLoadKind {
123 Even = 0,
124 Odd,
125 NoPattern
126 };
127
128} // end anonymous namespace
129
130// Implement calling convention for Hexagon.
131
132static bool isHvxVectorType(MVT ty);
133
134static bool
135CC_Hexagon(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
138
139static bool
140CC_Hexagon32(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
143
144static bool
145CC_Hexagon64(unsigned ValNo, MVT ValVT,
146 MVT LocVT, CCValAssign::LocInfo LocInfo,
147 ISD::ArgFlagsTy ArgFlags, CCState &State);
148
149static bool
150CC_HexagonVector(unsigned ValNo, MVT ValVT,
151 MVT LocVT, CCValAssign::LocInfo LocInfo,
152 ISD::ArgFlagsTy ArgFlags, CCState &State);
153
154static bool
155RetCC_Hexagon(unsigned ValNo, MVT ValVT,
156 MVT LocVT, CCValAssign::LocInfo LocInfo,
157 ISD::ArgFlagsTy ArgFlags, CCState &State);
158
159static bool
160RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
161 MVT LocVT, CCValAssign::LocInfo LocInfo,
162 ISD::ArgFlagsTy ArgFlags, CCState &State);
163
164static bool
165RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
166 MVT LocVT, CCValAssign::LocInfo LocInfo,
167 ISD::ArgFlagsTy ArgFlags, CCState &State);
168
169static bool
170RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
171 MVT LocVT, CCValAssign::LocInfo LocInfo,
172 ISD::ArgFlagsTy ArgFlags, CCState &State);
173
174static bool
175CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
176 MVT LocVT, CCValAssign::LocInfo LocInfo,
177 ISD::ArgFlagsTy ArgFlags, CCState &State) {
178 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
179
180 if (ValNo < HState.getNumNamedVarArgParams()) {
181 // Deal with named arguments.
182 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
183 }
184
185 // Deal with un-named arguments.
186 unsigned Offset;
187 if (ArgFlags.isByVal()) {
188 // If pass-by-value, the size allocated on stack is decided
189 // by ArgFlags.getByValSize(), not by the size of LocVT.
190 Offset = State.AllocateStack(ArgFlags.getByValSize(),
191 ArgFlags.getByValAlign());
192 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
193 return false;
194 }
195 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
196 LocVT = MVT::i32;
197 ValVT = MVT::i32;
198 if (ArgFlags.isSExt())
199 LocInfo = CCValAssign::SExt;
200 else if (ArgFlags.isZExt())
201 LocInfo = CCValAssign::ZExt;
202 else
203 LocInfo = CCValAssign::AExt;
204 }
205 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
206 Offset = State.AllocateStack(4, 4);
207 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
208 return false;
209 }
210 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
211 Offset = State.AllocateStack(8, 8);
212 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
213 return false;
214 }
215 if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
216 LocVT == MVT::v16i8) {
217 Offset = State.AllocateStack(16, 16);
218 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
219 return false;
220 }
221 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
222 LocVT == MVT::v32i8) {
223 Offset = State.AllocateStack(32, 32);
224 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
225 return false;
226 }
227 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
228 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
229 Offset = State.AllocateStack(64, 64);
230 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
231 return false;
232 }
233 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
234 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
235 Offset = State.AllocateStack(128, 128);
236 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
237 return false;
238 }
239 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
240 LocVT == MVT::v256i8) {
241 Offset = State.AllocateStack(256, 256);
242 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
243 return false;
244 }
245
246 llvm_unreachable(nullptr)::llvm::llvm_unreachable_internal(nullptr, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 246)
;
247}
248
249static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
250 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
251 if (ArgFlags.isByVal()) {
252 // Passed on stack.
253 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
254 ArgFlags.getByValAlign());
255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
256 return false;
257 }
258
259 if (LocVT == MVT::i1) {
260 LocVT = MVT::i32;
261 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
262 LocVT = MVT::i32;
263 ValVT = MVT::i32;
264 if (ArgFlags.isSExt())
265 LocInfo = CCValAssign::SExt;
266 else if (ArgFlags.isZExt())
267 LocInfo = CCValAssign::ZExt;
268 else
269 LocInfo = CCValAssign::AExt;
270 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
271 LocVT = MVT::i32;
272 LocInfo = CCValAssign::BCvt;
273 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
274 LocVT = MVT::i64;
275 LocInfo = CCValAssign::BCvt;
276 }
277
278 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
279 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
280 return false;
281 }
282
283 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
284 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
285 return false;
286 }
287
288 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
289 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
290 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
291 return false;
292 }
293
294 if (isHvxVectorType(LocVT)) {
295 if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
296 return false;
297 }
298
299 return true; // CC didn't match.
300}
301
302
303static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
304 MVT LocVT, CCValAssign::LocInfo LocInfo,
305 ISD::ArgFlagsTy ArgFlags, CCState &State) {
306 static const MCPhysReg RegList[] = {
307 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
308 Hexagon::R5
309 };
310 if (unsigned Reg = State.AllocateReg(RegList)) {
311 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
312 return false;
313 }
314
315 unsigned Offset = State.AllocateStack(4, 4);
316 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
317 return false;
318}
319
320static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
321 MVT LocVT, CCValAssign::LocInfo LocInfo,
322 ISD::ArgFlagsTy ArgFlags, CCState &State) {
323 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
324 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
325 return false;
326 }
327
328 static const MCPhysReg RegList1[] = {
329 Hexagon::D1, Hexagon::D2
330 };
331 static const MCPhysReg RegList2[] = {
332 Hexagon::R1, Hexagon::R3
333 };
334 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
335 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
336 return false;
337 }
338
339 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
340 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
341 return false;
342}
343
344static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
345 MVT LocVT, CCValAssign::LocInfo LocInfo,
346 ISD::ArgFlagsTy ArgFlags, CCState &State) {
347 static const MCPhysReg VecLstS[] = {
348 Hexagon::V0, Hexagon::V1, Hexagon::V2, Hexagon::V3, Hexagon::V4,
349 Hexagon::V5, Hexagon::V6, Hexagon::V7, Hexagon::V8, Hexagon::V9,
350 Hexagon::V10, Hexagon::V11, Hexagon::V12, Hexagon::V13, Hexagon::V14,
351 Hexagon::V15
352 };
353 static const MCPhysReg VecLstD[] = {
354 Hexagon::W0, Hexagon::W1, Hexagon::W2, Hexagon::W3, Hexagon::W4,
355 Hexagon::W5, Hexagon::W6, Hexagon::W7
356 };
357 auto &MF = State.getMachineFunction();
358 auto &HST = MF.getSubtarget<HexagonSubtarget>();
359
360 if (HST.useHVX64BOps() &&
361 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
362 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
363 if (unsigned Reg = State.AllocateReg(VecLstS)) {
364 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
365 return false;
366 }
367 unsigned Offset = State.AllocateStack(64, 64);
368 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
369 return false;
370 }
371 if (HST.useHVX64BOps() && (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 ||
372 LocVT == MVT::v64i16 || LocVT == MVT::v128i8)) {
373 if (unsigned Reg = State.AllocateReg(VecLstD)) {
374 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
375 return false;
376 }
377 unsigned Offset = State.AllocateStack(128, 128);
378 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
379 return false;
380 }
381 // 128B Mode
382 if (HST.useHVX128BOps() && (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 ||
383 LocVT == MVT::v128i16 || LocVT == MVT::v256i8)) {
384 if (unsigned Reg = State.AllocateReg(VecLstD)) {
385 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
386 return false;
387 }
388 unsigned Offset = State.AllocateStack(256, 256);
389 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
390 return false;
391 }
392 if (HST.useHVX128BOps() &&
393 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
394 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
395 if (unsigned Reg = State.AllocateReg(VecLstS)) {
396 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
397 return false;
398 }
399 unsigned Offset = State.AllocateStack(128, 128);
400 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
401 return false;
402 }
403 return true;
404}
405
406static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
407 MVT LocVT, CCValAssign::LocInfo LocInfo,
408 ISD::ArgFlagsTy ArgFlags, CCState &State) {
409 auto &MF = State.getMachineFunction();
410 auto &HST = MF.getSubtarget<HexagonSubtarget>();
411
412 if (LocVT == MVT::i1) {
413 // Return values of type MVT::i1 still need to be assigned to R0, but
414 // the value type needs to remain i1. LowerCallResult will deal with it,
415 // but it needs to recognize i1 as the value type.
416 LocVT = MVT::i32;
417 } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
418 LocVT = MVT::i32;
419 ValVT = MVT::i32;
420 if (ArgFlags.isSExt())
421 LocInfo = CCValAssign::SExt;
422 else if (ArgFlags.isZExt())
423 LocInfo = CCValAssign::ZExt;
424 else
425 LocInfo = CCValAssign::AExt;
426 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
427 LocVT = MVT::i32;
428 LocInfo = CCValAssign::BCvt;
429 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
430 LocVT = MVT::i64;
431 LocInfo = CCValAssign::BCvt;
432 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
433 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
434 LocVT == MVT::v512i1) {
435 LocVT = MVT::v16i32;
436 ValVT = MVT::v16i32;
437 LocInfo = CCValAssign::Full;
438 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
439 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
440 (LocVT == MVT::v1024i1 && HST.useHVX128BOps())) {
441 LocVT = MVT::v32i32;
442 ValVT = MVT::v32i32;
443 LocInfo = CCValAssign::Full;
444 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
445 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
446 LocVT = MVT::v64i32;
447 ValVT = MVT::v64i32;
448 LocInfo = CCValAssign::Full;
449 }
450 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
451 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
452 return false;
453 }
454
455 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
456 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
457 return false;
458 }
459 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
460 if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
461 return false;
462 }
463 return true; // CC didn't match.
464}
465
466static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
467 MVT LocVT, CCValAssign::LocInfo LocInfo,
468 ISD::ArgFlagsTy ArgFlags, CCState &State) {
469 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
470 // Note that use of registers beyond R1 is not ABI compliant. However there
471 // are (experimental) IR passes which generate internal functions that
472 // return structs using these additional registers.
473 static const uint16_t RegList[] = { Hexagon::R0, Hexagon::R1,
474 Hexagon::R2, Hexagon::R3,
475 Hexagon::R4, Hexagon::R5 };
476 if (unsigned Reg = State.AllocateReg(RegList)) {
477 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
478 return false;
479 }
480 }
481
482 return true;
483}
484
485static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
486 MVT LocVT, CCValAssign::LocInfo LocInfo,
487 ISD::ArgFlagsTy ArgFlags, CCState &State) {
488 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
489 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
490 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
491 return false;
492 }
493 }
494
495 return true;
496}
497
498static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
499 MVT LocVT, CCValAssign::LocInfo LocInfo,
500 ISD::ArgFlagsTy ArgFlags, CCState &State) {
501 auto &MF = State.getMachineFunction();
502 auto &HST = MF.getSubtarget<HexagonSubtarget>();
503
504 if (LocVT == MVT::v16i32) {
505 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
506 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
507 return false;
508 }
509 } else if (LocVT == MVT::v32i32) {
510 unsigned Req = HST.useHVX128BOps() ? Hexagon::V0 : Hexagon::W0;
511 if (unsigned Reg = State.AllocateReg(Req)) {
512 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
513 return false;
514 }
515 } else if (LocVT == MVT::v64i32) {
516 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
517 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
518 return false;
519 }
520 }
521
522 return true;
523}
524
525void HexagonTargetLowering::promoteLdStType(MVT VT, MVT PromotedLdStVT) {
526 if (VT != PromotedLdStVT) {
527 setOperationAction(ISD::LOAD, VT, Promote);
528 AddPromotedToType(ISD::LOAD, VT, PromotedLdStVT);
529
530 setOperationAction(ISD::STORE, VT, Promote);
531 AddPromotedToType(ISD::STORE, VT, PromotedLdStVT);
532 }
533}
534
535SDValue
536HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
537 const {
538 return SDValue();
539}
540
541/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
542/// by "Src" to address "Dst" of size "Size". Alignment information is
543/// specified by the specific parameter attribute. The copy will be passed as
544/// a byval function parameter. Sometimes what we are copying is the end of a
545/// larger object, the part that does not fit in registers.
546static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
547 SDValue Chain, ISD::ArgFlagsTy Flags,
548 SelectionDAG &DAG, const SDLoc &dl) {
549 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
550 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
551 /*isVolatile=*/false, /*AlwaysInline=*/false,
552 /*isTailCall=*/false,
553 MachinePointerInfo(), MachinePointerInfo());
554}
555
556static bool isHvxVectorType(MVT Ty) {
557 switch (Ty.SimpleTy) {
558 case MVT::v8i64:
559 case MVT::v16i32:
560 case MVT::v32i16:
561 case MVT::v64i8:
562 case MVT::v16i64:
563 case MVT::v32i32:
564 case MVT::v64i16:
565 case MVT::v128i8:
566 case MVT::v32i64:
567 case MVT::v64i32:
568 case MVT::v128i16:
569 case MVT::v256i8:
570 case MVT::v512i1:
571 case MVT::v1024i1:
572 return true;
573 default:
574 return false;
575 }
576}
577
578bool
579HexagonTargetLowering::CanLowerReturn(
580 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
581 const SmallVectorImpl<ISD::OutputArg> &Outs,
582 LLVMContext &Context) const {
583 SmallVector<CCValAssign, 16> RVLocs;
584 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
585 return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
586}
587
588// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
589// passed by value, the function prototype is modified to return void and
590// the value is stored in memory pointed by a pointer passed by caller.
591SDValue
592HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
593 bool isVarArg,
594 const SmallVectorImpl<ISD::OutputArg> &Outs,
595 const SmallVectorImpl<SDValue> &OutVals,
596 const SDLoc &dl, SelectionDAG &DAG) const {
597 // CCValAssign - represent the assignment of the return value to locations.
598 SmallVector<CCValAssign, 16> RVLocs;
599
600 // CCState - Info about the registers and stack slot.
601 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
602 *DAG.getContext());
603
604 // Analyze return values of ISD::RET
605 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
606
607 SDValue Flag;
608 SmallVector<SDValue, 4> RetOps(1, Chain);
609
610 // Copy the result values into the output registers.
611 for (unsigned i = 0; i != RVLocs.size(); ++i) {
612 CCValAssign &VA = RVLocs[i];
613
614 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
615
616 // Guarantee that all emitted copies are stuck together with flags.
617 Flag = Chain.getValue(1);
618 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
619 }
620
621 RetOps[0] = Chain; // Update chain.
622
623 // Add the flag if we have it.
624 if (Flag.getNode())
625 RetOps.push_back(Flag);
626
627 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
628}
629
630bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
631 // If either no tail call or told not to tail call at all, don't.
632 auto Attr =
633 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
634 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
635 return false;
636
637 return true;
638}
639
640/// LowerCallResult - Lower the result values of an ISD::CALL into the
641/// appropriate copies out of appropriate physical registers. This assumes that
642/// Chain/Glue are the input chain/glue to use, and that TheCall is the call
643/// being lowered. Returns a SDNode with the same number of values as the
644/// ISD::CALL.
645SDValue HexagonTargetLowering::LowerCallResult(
646 SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool isVarArg,
647 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
648 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
649 const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
650 // Assign locations to each value returned by this call.
651 SmallVector<CCValAssign, 16> RVLocs;
652
653 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
654 *DAG.getContext());
655
656 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
657
658 // Copy all of the result registers out of their specified physreg.
659 for (unsigned i = 0; i != RVLocs.size(); ++i) {
27
Assuming the condition is true
28
Loop condition is true. Entering loop body
660 SDValue RetVal;
661 if (RVLocs[i].getValVT() == MVT::i1) {
29
Taking true branch
662 // Return values of type MVT::i1 require special handling. The reason
663 // is that MVT::i1 is associated with the PredRegs register class, but
664 // values of that type are still returned in R0. Generate an explicit
665 // copy into a predicate register from R0, and treat the value of the
666 // predicate register as the call result.
667 auto &MRI = DAG.getMachineFunction().getRegInfo();
668 SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
669 MVT::i32, Glue);
670 // FR0 = (Value, Chain, Glue)
671 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
672 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
30
Null pointer value stored to 'N.Node'
31
Calling 'SelectionDAG::getCopyToReg'
673 FR0.getValue(0), FR0.getValue(2));
674 // TPR = (Chain, Glue)
675 // Don't glue this CopyFromReg, because it copies from a virtual
676 // register. If it is glued to the call, InstrEmitter will add it
677 // as an implicit def to the call (EmitMachineNode).
678 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
679 Glue = TPR.getValue(1);
680 Chain = TPR.getValue(0);
681 } else {
682 RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
683 RVLocs[i].getValVT(), Glue);
684 Glue = RetVal.getValue(2);
685 Chain = RetVal.getValue(1);
686 }
687 InVals.push_back(RetVal.getValue(0));
688 }
689
690 return Chain;
691}
692
693/// LowerCall - Functions arguments are copied from virtual regs to
694/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
695SDValue
696HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
697 SmallVectorImpl<SDValue> &InVals) const {
698 SelectionDAG &DAG = CLI.DAG;
699 SDLoc &dl = CLI.DL;
700 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
701 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
702 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
703 SDValue Chain = CLI.Chain;
704 SDValue Callee = CLI.Callee;
705 bool &IsTailCall = CLI.IsTailCall;
706 CallingConv::ID CallConv = CLI.CallConv;
707 bool IsVarArg = CLI.IsVarArg;
708 bool DoesNotReturn = CLI.DoesNotReturn;
709
710 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1
'?' condition is false
711 MachineFunction &MF = DAG.getMachineFunction();
712 MachineFrameInfo &MFI = MF.getFrameInfo();
713 auto PtrVT = getPointerTy(MF.getDataLayout());
714
715 // Check for varargs.
716 unsigned NumNamedVarArgParams = -1U;
717 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
2
Taking false branch
718 const GlobalValue *GV = GAN->getGlobal();
719 Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
720 if (const Function* F = dyn_cast<Function>(GV)) {
721 // If a function has zero args and is a vararg function, that's
722 // disallowed so it must be an undeclared function. Do not assume
723 // varargs if the callee is undefined.
724 if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
725 NumNamedVarArgParams = F->getFunctionType()->getNumParams();
726 }
727 }
728
729 // Analyze operands of the call, assigning locations to each operand.
730 SmallVector<CCValAssign, 16> ArgLocs;
731 HexagonCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
732 *DAG.getContext(), NumNamedVarArgParams);
733
734 if (IsVarArg)
3
Assuming 'IsVarArg' is 0
4
Taking false branch
735 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
736 else
737 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
738
739 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
740 if (Attr.getValueAsString() == "true")
5
Assuming the condition is false
6
Taking false branch
741 IsTailCall = false;
742
743 if (IsTailCall) {
7
Assuming the condition is false
8
Taking false branch
744 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
745 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
746 IsVarArg, IsStructRet,
747 StructAttrFlag,
748 Outs, OutVals, Ins, DAG);
749 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
750 CCValAssign &VA = ArgLocs[i];
751 if (VA.isMemLoc()) {
752 IsTailCall = false;
753 break;
754 }
755 }
756 DEBUG(dbgs() << (IsTailCall ? "Eligible for Tail Call\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
757 : "Argument must be passed on stack. "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
758 "Not eligible for Tail Call\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (IsTailCall ? "Eligible for Tail Call\n"
: "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
;
759 }
760 // Get a count of how many bytes are to be pushed on the stack.
761 unsigned NumBytes = CCInfo.getNextStackOffset();
762 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
763 SmallVector<SDValue, 8> MemOpChains;
764
765 auto &HRI = *Subtarget.getRegisterInfo();
766 SDValue StackPtr =
767 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
768
769 bool NeedsArgAlign = false;
770 unsigned LargestAlignSeen = 0;
771 // Walk the register/memloc assignments, inserting copies/loads.
772 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
9
Assuming 'i' is equal to 'e'
10
Loop condition is false. Execution continues on line 827
773 CCValAssign &VA = ArgLocs[i];
774 SDValue Arg = OutVals[i];
775 ISD::ArgFlagsTy Flags = Outs[i].Flags;
776 // Record if we need > 8 byte alignment on an argument.
777 bool ArgAlign = isHvxVectorType(VA.getValVT());
778 NeedsArgAlign |= ArgAlign;
779
780 // Promote the value if needed.
781 switch (VA.getLocInfo()) {
782 default:
783 // Loc info must be one of Full, SExt, ZExt, or AExt.
784 llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 784)
;
785 case CCValAssign::BCvt:
786 case CCValAssign::Full:
787 break;
788 case CCValAssign::SExt:
789 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
790 break;
791 case CCValAssign::ZExt:
792 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
793 break;
794 case CCValAssign::AExt:
795 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
796 break;
797 }
798
799 if (VA.isMemLoc()) {
800 unsigned LocMemOffset = VA.getLocMemOffset();
801 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
802 StackPtr.getValueType());
803 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
804 if (ArgAlign)
805 LargestAlignSeen = std::max(LargestAlignSeen,
806 VA.getLocVT().getStoreSizeInBits() >> 3);
807 if (Flags.isByVal()) {
808 // The argument is a struct passed by value. According to LLVM, "Arg"
809 // is is pointer.
810 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
811 Flags, DAG, dl));
812 } else {
813 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
814 DAG.getMachineFunction(), LocMemOffset);
815 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
816 MemOpChains.push_back(S);
817 }
818 continue;
819 }
820
821 // Arguments that can be passed on register must be kept at RegsToPass
822 // vector.
823 if (VA.isRegLoc())
824 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
825 }
826
827 if (NeedsArgAlign && Subtarget.hasV60TOps()) {
828 DEBUG(dbgs() << "Function needs byte stack align due to call args\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << "Function needs byte stack align due to call args\n"
; } } while (false)
;
829 // V6 vectors passed by value have 64 or 128 byte alignment depending
830 // on whether we are 64 byte vector mode or 128 byte.
831 bool UseHVX128B = Subtarget.useHVX128BOps();
832 assert(Subtarget.useHVXOps())((Subtarget.useHVXOps()) ? static_cast<void> (0) : __assert_fail
("Subtarget.useHVXOps()", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 832, __PRETTY_FUNCTION__))
;
833 const unsigned ObjAlign = UseHVX128B ? 128 : 64;
834 LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
835 MFI.ensureMaxAlignment(LargestAlignSeen);
836 }
837 // Transform all store nodes into one single node because all store
838 // nodes are independent of each other.
839 if (!MemOpChains.empty())
11
Taking true branch
840 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
841
842 SDValue Glue;
843 if (!IsTailCall) {
12
Taking true branch
844 Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
845 Glue = Chain.getValue(1);
846 }
847
848 // Build a sequence of copy-to-reg nodes chained together with token
849 // chain and flag operands which copy the outgoing args into registers.
850 // The Glue is necessary since all emitted instructions must be
851 // stuck together.
852 if (!IsTailCall) {
13
Taking true branch
853 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
14
Assuming 'i' is equal to 'e'
15
Loop condition is false. Execution continues on line 878
854 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
855 RegsToPass[i].second, Glue);
856 Glue = Chain.getValue(1);
857 }
858 } else {
859 // For tail calls lower the arguments to the 'real' stack slot.
860 //
861 // Force all the incoming stack arguments to be loaded from the stack
862 // before any new outgoing arguments are stored to the stack, because the
863 // outgoing stack slots may alias the incoming argument stack slots, and
864 // the alias isn't otherwise explicit. This is slightly more conservative
865 // than necessary, because it means that each store effectively depends
866 // on every argument instead of just those arguments it would clobber.
867 //
868 // Do not flag preceding copytoreg stuff together with the following stuff.
869 Glue = SDValue();
870 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
871 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
872 RegsToPass[i].second, Glue);
873 Glue = Chain.getValue(1);
874 }
875 Glue = SDValue();
876 }
877
878 bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
879 unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;
16
Assuming 'LongCalls' is 0
17
'?' condition is false
880
881 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
882 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
883 // node so that legalize doesn't hack it.
884 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
18
Taking false branch
885 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
886 } else if (ExternalSymbolSDNode *S =
19
Taking false branch
887 dyn_cast<ExternalSymbolSDNode>(Callee)) {
888 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
889 }
890
891 // Returns a chain & a flag for retval copy to use.
892 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
893 SmallVector<SDValue, 8> Ops;
894 Ops.push_back(Chain);
895 Ops.push_back(Callee);
896
897 // Add argument registers to the end of the list so that they are
898 // known live into the call.
899 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
20
Assuming 'i' is equal to 'e'
21
Loop condition is false. Execution continues on line 904
900 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
901 RegsToPass[i].second.getValueType()));
902 }
903
904 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
905 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 905, __PRETTY_FUNCTION__))
;
906 Ops.push_back(DAG.getRegisterMask(Mask));
907
908 if (Glue.getNode())
22
Taking true branch
909 Ops.push_back(Glue);
910
911 if (IsTailCall) {
23
Taking false branch
912 MFI.setHasTailCall();
913 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
914 }
915
916 // Set this here because we need to know this for "hasFP" in frame lowering.
917 // The target-independent code calls getFrameRegister before setting it, and
918 // getFrameRegister uses hasFP to determine whether the function has FP.
919 MFI.setHasCalls(true);
920
921 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
24
Assuming 'DoesNotReturn' is 0
25
'?' condition is false
922 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
923 Glue = Chain.getValue(1);
924
925 // Create the CALLSEQ_END node.
926 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
927 DAG.getIntPtrConstant(0, dl, true), Glue, dl);
928 Glue = Chain.getValue(1);
929
930 // Handle result values, copying them out of physregs into vregs that we
931 // return.
932 return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
26
Calling 'HexagonTargetLowering::LowerCallResult'
933 InVals, OutVals, Callee);
934}
935
936static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
937 SDValue &Base, SDValue &Offset,
938 bool &IsInc, SelectionDAG &DAG) {
939 if (Ptr->getOpcode() != ISD::ADD)
940 return false;
941
942 auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
943
944 bool ValidHVX128BType =
945 HST.useHVX128BOps() && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
946 VT == MVT::v64i16 || VT == MVT::v128i8);
947 bool ValidHVXType =
948 HST.useHVX64BOps() && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
949 VT == MVT::v32i16 || VT == MVT::v64i8);
950
951 if (ValidHVX128BType || ValidHVXType || VT == MVT::i64 || VT == MVT::i32 ||
952 VT == MVT::i16 || VT == MVT::i8) {
953 IsInc = (Ptr->getOpcode() == ISD::ADD);
954 Base = Ptr->getOperand(0);
955 Offset = Ptr->getOperand(1);
956 // Ensure that Offset is a constant.
957 return isa<ConstantSDNode>(Offset);
958 }
959
960 return false;
961}
962
963/// getPostIndexedAddressParts - returns true by value, base pointer and
964/// offset pointer and addressing mode by reference if this node can be
965/// combined with a load / store to form a post-indexed load / store.
966bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
967 SDValue &Base,
968 SDValue &Offset,
969 ISD::MemIndexedMode &AM,
970 SelectionDAG &DAG) const
971{
972 EVT VT;
973
974 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
975 VT = LD->getMemoryVT();
976 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
977 VT = ST->getMemoryVT();
978 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore())
979 return false;
980 } else {
981 return false;
982 }
983
984 bool IsInc = false;
985 bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
986 if (isLegal) {
987 auto &HII = *Subtarget.getInstrInfo();
988 int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
989 if (HII.isValidAutoIncImm(VT, OffsetVal)) {
990 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
991 return true;
992 }
993 }
994
995 return false;
996}
997
998SDValue
999HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
1000 MachineFunction &MF = DAG.getMachineFunction();
1001 auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
1002 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1003 unsigned LR = HRI.getRARegister();
1004
1005 if (Op.getOpcode() != ISD::INLINEASM || HMFI.hasClobberLR())
1006 return Op;
1007
1008 unsigned NumOps = Op.getNumOperands();
1009 if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
1010 --NumOps; // Ignore the flag operand.
1011
1012 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1013 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
1014 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
1015 ++i; // Skip the ID value.
1016
1017 switch (InlineAsm::getKind(Flags)) {
1018 default:
1019 llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1019)
;
1020 case InlineAsm::Kind_RegUse:
1021 case InlineAsm::Kind_Imm:
1022 case InlineAsm::Kind_Mem:
1023 i += NumVals;
1024 break;
1025 case InlineAsm::Kind_Clobber:
1026 case InlineAsm::Kind_RegDef:
1027 case InlineAsm::Kind_RegDefEarlyClobber: {
1028 for (; NumVals; --NumVals, ++i) {
1029 unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
1030 if (Reg != LR)
1031 continue;
1032 HMFI.setHasClobberLR(true);
1033 return Op;
1034 }
1035 break;
1036 }
1037 }
1038 }
1039
1040 return Op;
1041}
1042
1043// Need to transform ISD::PREFETCH into something that doesn't inherit
1044// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
1045// SDNPMayStore.
1046SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
1047 SelectionDAG &DAG) const {
1048 SDValue Chain = Op.getOperand(0);
1049 SDValue Addr = Op.getOperand(1);
1050 // Lower it to DCFETCH($reg, #0). A "pat" will try to merge the offset in,
1051 // if the "reg" is fed by an "add".
1052 SDLoc DL(Op);
1053 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1054 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1055}
1056
1057// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
1058// is marked as having side-effects, while the register read on Hexagon does
1059// not have any. TableGen refuses to accept the direct pattern from that node
1060// to the A4_tfrcpp.
1061SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
1062 SelectionDAG &DAG) const {
1063 SDValue Chain = Op.getOperand(0);
1064 SDLoc dl(Op);
1065 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1066 return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
1067}
1068
1069SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1070 SelectionDAG &DAG) const {
1071 SDValue Chain = Op.getOperand(0);
1072 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1073 // Lower the hexagon_prefetch builtin to DCFETCH, as above.
1074 if (IntNo == Intrinsic::hexagon_prefetch) {
1075 SDValue Addr = Op.getOperand(2);
1076 SDLoc DL(Op);
1077 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
1078 return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
1079 }
1080 return SDValue();
1081}
1082
1083SDValue
1084HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1085 SelectionDAG &DAG) const {
1086 SDValue Chain = Op.getOperand(0);
1087 SDValue Size = Op.getOperand(1);
1088 SDValue Align = Op.getOperand(2);
1089 SDLoc dl(Op);
1090
1091 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1092 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC")((AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC"
) ? static_cast<void> (0) : __assert_fail ("AlignConst && \"Non-constant Align in LowerDYNAMIC_STACKALLOC\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1092, __PRETTY_FUNCTION__))
;
1093
1094 unsigned A = AlignConst->getSExtValue();
1095 auto &HFI = *Subtarget.getFrameLowering();
1096 // "Zero" means natural stack alignment.
1097 if (A == 0)
1098 A = HFI.getStackAlignment();
1099
1100 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1101 dbgs () << __func__ << " Align: " << A << " Size: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1102 Size.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1103 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
1104 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
<< A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
;
1105
1106 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1107 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1108 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1109
1110 DAG.ReplaceAllUsesOfValueWith(Op, AA);
1111 return AA;
1112}
1113
1114SDValue HexagonTargetLowering::LowerFormalArguments(
1115 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1116 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1117 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
1118 MachineFunction &MF = DAG.getMachineFunction();
1119 MachineFrameInfo &MFI = MF.getFrameInfo();
1120 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1121 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1122
1123 // Assign locations to all of the incoming arguments.
1124 SmallVector<CCValAssign, 16> ArgLocs;
1125 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1126 *DAG.getContext());
1127
1128 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1129
1130 // For LLVM, in the case when returning a struct by value (>8byte),
1131 // the first argument is a pointer that points to the location on caller's
1132 // stack where the return value will be stored. For Hexagon, the location on
1133 // caller's stack is passed only when the struct size is smaller than (and
1134 // equal to) 8 bytes. If not, no address will be passed into callee and
1135 // callee return the result direclty through R0/R1.
1136
1137 SmallVector<SDValue, 8> MemOps;
1138
1139 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1140 CCValAssign &VA = ArgLocs[i];
1141 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1142 unsigned ObjSize;
1143 unsigned StackLocation;
1144 int FI;
1145
1146 if ( (VA.isRegLoc() && !Flags.isByVal())
1147 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1148 // Arguments passed in registers
1149 // 1. int, long long, ptr args that get allocated in register.
1150 // 2. Large struct that gets an register to put its address in.
1151 EVT RegVT = VA.getLocVT();
1152 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1153 RegVT == MVT::i32 || RegVT == MVT::f32) {
1154 unsigned VReg =
1155 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1156 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1157 SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1158 // Treat values of type MVT::i1 specially: they are passed in
1159 // registers of type i32, but they need to remain as values of
1160 // type i1 for consistency of the argument lowering.
1161 if (VA.getValVT() == MVT::i1) {
1162 // Generate a copy into a predicate register and use the value
1163 // of the register as the "InVal".
1164 unsigned PReg =
1165 RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass);
1166 SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
1167 Copy.getValue(0));
1168 Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0));
1169 Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1);
1170 }
1171 InVals.push_back(Copy);
1172 Chain = Copy.getValue(1);
1173 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1174 unsigned VReg =
1175 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1176 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1177 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1178
1179 // Single Vector
1180 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1181 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1182 unsigned VReg =
1183 RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
1184 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1185 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1186 } else if (Subtarget.useHVX128BOps() &&
1187 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1188 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1189 unsigned VReg =
1190 RegInfo.createVirtualRegister(&Hexagon::HvxVRRegClass);
1191 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1192 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1193
1194 // Double Vector
1195 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1196 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1197 unsigned VReg =
1198 RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
1199 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1200 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1201 } else if (Subtarget.useHVX128BOps() &&
1202 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1203 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1204 unsigned VReg =
1205 RegInfo.createVirtualRegister(&Hexagon::HvxWRRegClass);
1206 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1207 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1208 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1209 assert(0 && "need to support VecPred regs")((0 && "need to support VecPred regs") ? static_cast<
void> (0) : __assert_fail ("0 && \"need to support VecPred regs\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1209, __PRETTY_FUNCTION__))
;
1210 unsigned VReg =
1211 RegInfo.createVirtualRegister(&Hexagon::HvxQRRegClass);
1212 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1213 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1214 } else {
1215 assert (0)((0) ? static_cast<void> (0) : __assert_fail ("0", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1215, __PRETTY_FUNCTION__))
;
1216 }
1217 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1218 assert (0 && "ByValSize must be bigger than 8 bytes")((0 && "ByValSize must be bigger than 8 bytes") ? static_cast
<void> (0) : __assert_fail ("0 && \"ByValSize must be bigger than 8 bytes\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1218, __PRETTY_FUNCTION__))
;
1219 } else {
1220 // Sanity check.
1221 assert(VA.isMemLoc())((VA.isMemLoc()) ? static_cast<void> (0) : __assert_fail
("VA.isMemLoc()", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1221, __PRETTY_FUNCTION__))
;
1222
1223 if (Flags.isByVal()) {
1224 // If it's a byval parameter, then we need to compute the
1225 // "real" size, not the size of the pointer.
1226 ObjSize = Flags.getByValSize();
1227 } else {
1228 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1229 }
1230
1231 StackLocation = HEXAGON_LRFP_SIZE8 + VA.getLocMemOffset();
1232 // Create the frame index object for this incoming parameter...
1233 FI = MFI.CreateFixedObject(ObjSize, StackLocation, true);
1234
1235 // Create the SelectionDAG nodes cordl, responding to a load
1236 // from this parameter.
1237 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1238
1239 if (Flags.isByVal()) {
1240 // If it's a pass-by-value aggregate, then do not dereference the stack
1241 // location. Instead, we should generate a reference to the stack
1242 // location.
1243 InVals.push_back(FIN);
1244 } else {
1245 InVals.push_back(
1246 DAG.getLoad(VA.getValVT(), dl, Chain, FIN, MachinePointerInfo()));
1247 }
1248 }
1249 }
1250
1251 if (!MemOps.empty())
1252 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1253
1254 if (isVarArg) {
1255 // This will point to the next argument passed via stack.
1256 int FrameIndex = MFI.CreateFixedObject(Hexagon_PointerSize(4),
1257 HEXAGON_LRFP_SIZE8 +
1258 CCInfo.getNextStackOffset(),
1259 true);
1260 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1261 }
1262
1263 return Chain;
1264}
1265
1266SDValue
1267HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1268 // VASTART stores the address of the VarArgsFrameIndex slot into the
1269 // memory location argument.
1270 MachineFunction &MF = DAG.getMachineFunction();
1271 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
1272 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1273 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1274 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
1275 MachinePointerInfo(SV));
1276}
1277
1278static bool isSExtFree(SDValue N) {
1279 // A sign-extend of a truncate of a sign-extend is free.
1280 if (N.getOpcode() == ISD::TRUNCATE &&
1281 N.getOperand(0).getOpcode() == ISD::AssertSext)
1282 return true;
1283 // We have sign-extended loads.
1284 if (N.getOpcode() == ISD::LOAD)
1285 return true;
1286 return false;
1287}
1288
1289SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1290 SDLoc dl(Op);
1291
1292 SDValue LHS = Op.getOperand(0);
1293 SDValue RHS = Op.getOperand(1);
1294 SDValue Cmp = Op.getOperand(2);
1295 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1296
1297 EVT VT = Op.getValueType();
1298 EVT LHSVT = LHS.getValueType();
1299 EVT RHSVT = RHS.getValueType();
1300
1301 if (LHSVT == MVT::v2i16) {
1302 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC))((ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)) ?
static_cast<void> (0) : __assert_fail ("ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC)"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1302, __PRETTY_FUNCTION__))
;
1303 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1304 : ISD::ZERO_EXTEND;
1305 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1306 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1307 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1308 return SC;
1309 }
1310
1311 // Treat all other vector types as legal.
1312 if (VT.isVector())
1313 return Op;
1314
1315 // Equals and not equals should use sign-extend, not zero-extend, since
1316 // we can represent small negative values in the compare instructions.
1317 // The LLVM default is to use zero-extend arbitrarily in these cases.
1318 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1319 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1320 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1321 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1322 if (C && C->getAPIntValue().isNegative()) {
1323 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1324 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1325 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1326 LHS, RHS, Op.getOperand(2));
1327 }
1328 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1329 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1330 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1331 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1332 LHS, RHS, Op.getOperand(2));
1333 }
1334 }
1335 return SDValue();
1336}
1337
1338SDValue
1339HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
1340 SDValue PredOp = Op.getOperand(0);
1341 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1342 EVT OpVT = Op1.getValueType();
1343 SDLoc DL(Op);
1344
1345 if (OpVT == MVT::v2i16) {
1346 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1347 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1348 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1349 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1350 return TR;
1351 }
1352
1353 return SDValue();
1354}
1355
1356static Constant *convert_i1_to_i8(const Constant *ConstVal) {
1357 SmallVector<Constant *, 128> NewConst;
1358 const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
1359 if (!CV)
1360 return nullptr;
1361
1362 LLVMContext &Ctx = ConstVal->getContext();
1363 IRBuilder<> IRB(Ctx);
1364 unsigned NumVectorElements = CV->getNumOperands();
1365 assert(isPowerOf2_32(NumVectorElements) &&((isPowerOf2_32(NumVectorElements) && "conversion only supported for pow2 VectorSize!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumVectorElements) && \"conversion only supported for pow2 VectorSize!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1366, __PRETTY_FUNCTION__))
1366 "conversion only supported for pow2 VectorSize!")((isPowerOf2_32(NumVectorElements) && "conversion only supported for pow2 VectorSize!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumVectorElements) && \"conversion only supported for pow2 VectorSize!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1366, __PRETTY_FUNCTION__))
;
1367
1368 for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
1369 uint8_t x = 0;
1370 for (unsigned j = 0; j < 8; ++j) {
1371 uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
1372 x |= y << (7 - j);
1373 }
1374 assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!")(((x == 0 || x == 255) && "Either all 0's or all 1's expected!"
) ? static_cast<void> (0) : __assert_fail ("(x == 0 || x == 255) && \"Either all 0's or all 1's expected!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1374, __PRETTY_FUNCTION__))
;
1375 NewConst.push_back(IRB.getInt8(x));
1376 }
1377 return ConstantVector::get(NewConst);
1378}
1379
1380SDValue
1381HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1382 EVT ValTy = Op.getValueType();
1383 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1384 Constant *CVal = nullptr;
1385 bool isVTi1Type = false;
1386 if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
1387 Type *CValTy = ConstVal->getType();
1388 if (CValTy->isVectorTy() &&
1389 CValTy->getVectorElementType()->isIntegerTy(1)) {
1390 CVal = convert_i1_to_i8(ConstVal);
1391 isVTi1Type = (CVal != nullptr);
1392 }
1393 }
1394 unsigned Align = CPN->getAlignment();
1395 bool IsPositionIndependent = isPositionIndependent();
1396 unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;
1397
1398 unsigned Offset = 0;
1399 SDValue T;
1400 if (CPN->isMachineConstantPoolEntry())
1401 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
1402 TF);
1403 else if (isVTi1Type)
1404 T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
1405 else
1406 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset,
1407 TF);
1408
1409 assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1410, __PRETTY_FUNCTION__))
1410 "Inconsistent target flag encountered")((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
&& "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1410, __PRETTY_FUNCTION__))
;
1411
1412 if (IsPositionIndependent)
1413 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1414 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1415}
1416
1417SDValue
1418HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1419 EVT VT = Op.getValueType();
1420 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1421 if (isPositionIndependent()) {
1422 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1423 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1424 }
1425
1426 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1427 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1428}
1429
1430SDValue
1431HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1432 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1433 MachineFunction &MF = DAG.getMachineFunction();
1434 MachineFrameInfo &MFI = MF.getFrameInfo();
1435 MFI.setReturnAddressIsTaken(true);
1436
1437 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1438 return SDValue();
1439
1440 EVT VT = Op.getValueType();
1441 SDLoc dl(Op);
1442 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1443 if (Depth) {
1444 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1445 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1446 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1447 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1448 MachinePointerInfo());
1449 }
1450
1451 // Return LR, which contains the return address. Mark it an implicit live-in.
1452 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1453 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1454}
1455
1456SDValue
1457HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1458 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1459 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1460 MFI.setFrameAddressIsTaken(true);
1461
1462 EVT VT = Op.getValueType();
1463 SDLoc dl(Op);
1464 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1465 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1466 HRI.getFrameRegister(), VT);
1467 while (Depth--)
1468 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1469 MachinePointerInfo());
1470 return FrameAddr;
1471}
1472
1473SDValue
1474HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
1475 SDLoc dl(Op);
1476 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1477}
1478
1479SDValue
1480HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
1481 SDLoc dl(Op);
1482 auto *GAN = cast<GlobalAddressSDNode>(Op);
1483 auto PtrVT = getPointerTy(DAG.getDataLayout());
1484 auto *GV = GAN->getGlobal();
1485 int64_t Offset = GAN->getOffset();
1486
1487 auto &HLOF = *HTM.getObjFileLowering();
1488 Reloc::Model RM = HTM.getRelocationModel();
1489
1490 if (RM == Reloc::Static) {
1491 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1492 const GlobalObject *GO = GV->getBaseObject();
1493 if (GO && HLOF.isGlobalInSmallSection(GO, HTM))
1494 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1495 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1496 }
1497
1498 bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1499 if (UsePCRel) {
1500 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1501 HexagonII::MO_PCREL);
1502 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1503 }
1504
1505 // Use GOT index.
1506 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1507 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1508 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1509 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1510}
1511
1512// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1513SDValue
1514HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1515 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1516 SDLoc dl(Op);
1517 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1518
1519 Reloc::Model RM = HTM.getRelocationModel();
1520 if (RM == Reloc::Static) {
1521 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1522 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1523 }
1524
1525 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1526 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1527}
1528
1529SDValue
1530HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
1531 const {
1532 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1533 SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME"_GLOBAL_OFFSET_TABLE_", PtrVT,
1534 HexagonII::MO_PCREL);
1535 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1536}
1537
1538SDValue
1539HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
1540 GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
1541 unsigned char OperandFlags) const {
1542 MachineFunction &MF = DAG.getMachineFunction();
1543 MachineFrameInfo &MFI = MF.getFrameInfo();
1544 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1545 SDLoc dl(GA);
1546 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
1547 GA->getValueType(0),
1548 GA->getOffset(),
1549 OperandFlags);
1550 // Create Operands for the call.The Operands should have the following:
1551 // 1. Chain SDValue
1552 // 2. Callee which in this case is the Global address value.
1553 // 3. Registers live into the call.In this case its R0, as we
1554 // have just one argument to be passed.
1555 // 4. Glue.
1556 // Note: The order is important.
1557
1558 const auto &HRI = *Subtarget.getRegisterInfo();
1559 const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
1560 assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1560, __PRETTY_FUNCTION__))
;
1561 SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
1562 DAG.getRegisterMask(Mask), Glue };
1563 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);
1564
1565 // Inform MFI that function has calls.
1566 MFI.setAdjustsStack(true);
1567
1568 Glue = Chain.getValue(1);
1569 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1570}
1571
1572//
1573// Lower using the intial executable model for TLS addresses
1574//
1575SDValue
1576HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
1577 SelectionDAG &DAG) const {
1578 SDLoc dl(GA);
1579 int64_t Offset = GA->getOffset();
1580 auto PtrVT = getPointerTy(DAG.getDataLayout());
1581
1582 // Get the thread pointer.
1583 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1584
1585 bool IsPositionIndependent = isPositionIndependent();
1586 unsigned char TF =
1587 IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;
1588
1589 // First generate the TLS symbol address
1590 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
1591 Offset, TF);
1592
1593 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1594
1595 if (IsPositionIndependent) {
1596 // Generate the GOT pointer in case of position independent code
1597 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);
1598
1599 // Add the TLS Symbol address to GOT pointer.This gives
1600 // GOT relative relocation for the symbol.
1601 Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1602 }
1603
1604 // Load the offset value for TLS symbol.This offset is relative to
1605 // thread pointer.
1606 SDValue LoadOffset =
1607 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());
1608
1609 // Address of the thread local variable is the add of thread
1610 // pointer and the offset of the variable.
1611 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1612}
1613
1614//
1615// Lower using the local executable model for TLS addresses
1616//
1617SDValue
1618HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
1619 SelectionDAG &DAG) const {
1620 SDLoc dl(GA);
1621 int64_t Offset = GA->getOffset();
1622 auto PtrVT = getPointerTy(DAG.getDataLayout());
1623
1624 // Get the thread pointer.
1625 SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
1626 // Generate the TLS symbol address
1627 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1628 HexagonII::MO_TPREL);
1629 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1630
1631 // Address of the thread local variable is the add of thread
1632 // pointer and the offset of the variable.
1633 return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1634}
1635
1636//
1637// Lower using the general dynamic model for TLS addresses
1638//
1639SDValue
1640HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1641 SelectionDAG &DAG) const {
1642 SDLoc dl(GA);
1643 int64_t Offset = GA->getOffset();
1644 auto PtrVT = getPointerTy(DAG.getDataLayout());
1645
1646 // First generate the TLS symbol address
1647 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
1648 HexagonII::MO_GDGOT);
1649
1650 // Then, generate the GOT pointer
1651 SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);
1652
1653 // Add the TLS symbol and the GOT pointer
1654 SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
1655 SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
1656
1657 // Copy over the argument to R0
1658 SDValue InFlag;
1659 Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
1660 InFlag = Chain.getValue(1);
1661
1662 unsigned Flags =
1663 static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
1664 ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended
1665 : HexagonII::MO_GDPLT;
1666
1667 return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
1668 Hexagon::R0, Flags);
1669}
1670
1671//
1672// Lower TLS addresses.
1673//
1674// For now for dynamic models, we only support the general dynamic model.
1675//
1676SDValue
1677HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1678 SelectionDAG &DAG) const {
1679 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1680
1681 switch (HTM.getTLSModel(GA->getGlobal())) {
1682 case TLSModel::GeneralDynamic:
1683 case TLSModel::LocalDynamic:
1684 return LowerToTLSGeneralDynamicModel(GA, DAG);
1685 case TLSModel::InitialExec:
1686 return LowerToTLSInitialExecModel(GA, DAG);
1687 case TLSModel::LocalExec:
1688 return LowerToTLSLocalExecModel(GA, DAG);
1689 }
1690 llvm_unreachable("Bogus TLS model")::llvm::llvm_unreachable_internal("Bogus TLS model", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1690)
;
1691}
1692
1693//===----------------------------------------------------------------------===//
1694// TargetLowering Implementation
1695//===----------------------------------------------------------------------===//
1696
1697HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1698 const HexagonSubtarget &ST)
1699 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1700 Subtarget(ST) {
1701 bool IsV4 = !Subtarget.hasV5TOps();
1702 auto &HRI = *Subtarget.getRegisterInfo();
1703
1704 setPrefLoopAlignment(4);
1705 setPrefFunctionAlignment(4);
1706 setMinFunctionAlignment(2);
1707 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1708
1709 setMaxAtomicSizeInBitsSupported(64);
1710 setMinCmpXchgSizeInBits(32);
1711
1712 if (EnableHexSDNodeSched)
1713 setSchedulingPreference(Sched::VLIW);
1714 else
1715 setSchedulingPreference(Sched::Source);
1716
1717 // Limits for inline expansion of memcpy/memmove
1718 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1719 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1720 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1721 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1722 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1723 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1724
1725 //
1726 // Set up register classes.
1727 //
1728
1729 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1730 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1731 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1732 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1733 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1734 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1735 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1736 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1737 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1738 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1739 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1740
1741 if (Subtarget.hasV5TOps()) {
1742 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1743 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1744 }
1745
1746 if (Subtarget.hasV60TOps()) {
1747 if (Subtarget.useHVX64BOps()) {
1748 addRegisterClass(MVT::v64i8, &Hexagon::HvxVRRegClass);
1749 addRegisterClass(MVT::v32i16, &Hexagon::HvxVRRegClass);
1750 addRegisterClass(MVT::v16i32, &Hexagon::HvxVRRegClass);
1751 addRegisterClass(MVT::v8i64, &Hexagon::HvxVRRegClass);
1752 addRegisterClass(MVT::v128i8, &Hexagon::HvxWRRegClass);
1753 addRegisterClass(MVT::v64i16, &Hexagon::HvxWRRegClass);
1754 addRegisterClass(MVT::v32i32, &Hexagon::HvxWRRegClass);
1755 addRegisterClass(MVT::v16i64, &Hexagon::HvxWRRegClass);
1756 addRegisterClass(MVT::v512i1, &Hexagon::HvxQRRegClass);
1757 } else if (Subtarget.useHVX128BOps()) {
1758 addRegisterClass(MVT::v128i8, &Hexagon::HvxVRRegClass);
1759 addRegisterClass(MVT::v64i16, &Hexagon::HvxVRRegClass);
1760 addRegisterClass(MVT::v32i32, &Hexagon::HvxVRRegClass);
1761 addRegisterClass(MVT::v16i64, &Hexagon::HvxVRRegClass);
1762 addRegisterClass(MVT::v256i8, &Hexagon::HvxWRRegClass);
1763 addRegisterClass(MVT::v128i16, &Hexagon::HvxWRRegClass);
1764 addRegisterClass(MVT::v64i32, &Hexagon::HvxWRRegClass);
1765 addRegisterClass(MVT::v32i64, &Hexagon::HvxWRRegClass);
1766 addRegisterClass(MVT::v1024i1, &Hexagon::HvxQRRegClass);
1767 }
1768 }
1769
1770 //
1771 // Handling of scalar operations.
1772 //
1773 // All operations default to "legal", except:
1774 // - indexed loads and stores (pre-/post-incremented),
1775 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1776 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1777 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1778 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1779 // which default to "expand" for at least one type.
1780
1781 // Misc operations.
1782 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1783 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1784
1785 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1786 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1787 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1788 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1789 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1790 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
1791 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1792 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1793 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1794 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1795 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
1796 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1797
1798 // Custom legalize GlobalAddress nodes into CONST32.
1799 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1800 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1801 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1802
1803 // Hexagon needs to optimize cases with negative constants.
1804 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1805 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1806
1807 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1808 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1809 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1810 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1811
1812 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1813 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1814 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1815
1816 if (EmitJumpTables)
1817 setMinimumJumpTableEntries(MinimumJumpTables);
1818 else
1819 setMinimumJumpTableEntries(std::numeric_limits<int>::max());
1820 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1821
1822 // Hexagon has instructions for add/sub with carry. The problem with
1823 // modeling these instructions is that they produce 2 results: Rdd and Px.
1824 // To model the update of Px, we will have to use Defs[p0..p3] which will
1825 // cause any predicate live range to spill. So, we pretend we dont't have
1826 // these instructions.
1827 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1828 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1829 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1830 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1831 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1832 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1833 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1834 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1835 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1836 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1837 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1838 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1839 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1840 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1841 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1842 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1843
1844 // Only add and sub that detect overflow are the saturating ones.
1845 for (MVT VT : MVT::integer_valuetypes()) {
1846 setOperationAction(ISD::UADDO, VT, Expand);
1847 setOperationAction(ISD::SADDO, VT, Expand);
1848 setOperationAction(ISD::USUBO, VT, Expand);
1849 setOperationAction(ISD::SSUBO, VT, Expand);
1850 }
1851
1852 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1853 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1854 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1855 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1856
1857 // In V5, popcount can count # of 1s in i64 but returns i32.
1858 // On V4 it will be expanded (set later).
1859 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1860 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1861 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1862 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
1863
1864 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
1865 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
1866 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
1867 setOperationAction(ISD::BSWAP, MVT::i64, Legal);
1868 setOperationAction(ISD::MUL, MVT::i64, Legal);
1869
1870 for (unsigned IntExpOp :
1871 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1872 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1873 ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1874 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1875 setOperationAction(IntExpOp, MVT::i32, Expand);
1876 setOperationAction(IntExpOp, MVT::i64, Expand);
1877 }
1878
1879 for (unsigned FPExpOp :
1880 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1881 ISD::FPOW, ISD::FCOPYSIGN}) {
1882 setOperationAction(FPExpOp, MVT::f32, Expand);
1883 setOperationAction(FPExpOp, MVT::f64, Expand);
1884 }
1885
1886 // No extending loads from i32.
1887 for (MVT VT : MVT::integer_valuetypes()) {
1888 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1889 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1891 }
1892 // Turn FP truncstore into trunc + store.
1893 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1894 // Turn FP extload into load/fpextend.
1895 for (MVT VT : MVT::fp_valuetypes())
1896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1897
1898 // Expand BR_CC and SELECT_CC for all integer and fp types.
1899 for (MVT VT : MVT::integer_valuetypes()) {
1900 setOperationAction(ISD::BR_CC, VT, Expand);
1901 setOperationAction(ISD::SELECT_CC, VT, Expand);
1902 }
1903 for (MVT VT : MVT::fp_valuetypes()) {
1904 setOperationAction(ISD::BR_CC, VT, Expand);
1905 setOperationAction(ISD::SELECT_CC, VT, Expand);
1906 }
1907 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1908
1909 //
1910 // Handling of vector operations.
1911 //
1912
1913 promoteLdStType(MVT::v4i8, MVT::i32);
1914 promoteLdStType(MVT::v2i16, MVT::i32);
1915 promoteLdStType(MVT::v8i8, MVT::i64);
1916 promoteLdStType(MVT::v4i16, MVT::i64);
1917 promoteLdStType(MVT::v2i32, MVT::i64);
1918
1919 // Set the action for vector operations to "expand", then override it with
1920 // either "custom" or "legal" for specific cases.
1921 static const unsigned VectExpOps[] = {
1922 // Integer arithmetic:
1923 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1924 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1925 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1926 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1927 // Logical/bit:
1928 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1929 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ,
1930 // Floating point arithmetic/math functions:
1931 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1932 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1933 ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1934 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1935 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1936 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1937 // Misc:
1938 ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
1939 // Vector:
1940 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1941 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1942 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1943 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1944 };
1945
1946 for (MVT VT : MVT::vector_valuetypes()) {
1947 for (unsigned VectExpOp : VectExpOps)
1948 setOperationAction(VectExpOp, VT, Expand);
1949
1950 // Expand all extending loads and truncating stores:
1951 for (MVT TargetVT : MVT::vector_valuetypes()) {
1952 if (TargetVT == VT)
1953 continue;
1954 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1955 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1956 setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
1957 setTruncStoreAction(VT, TargetVT, Expand);
1958 }
1959
1960 // Normalize all inputs to SELECT to be vectors of i32.
1961 if (VT.getVectorElementType() != MVT::i32) {
1962 MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
1963 setOperationAction(ISD::SELECT, VT, Promote);
1964 AddPromotedToType(ISD::SELECT, VT, VT32);
1965 }
1966 setOperationAction(ISD::SRA, VT, Custom);
1967 setOperationAction(ISD::SHL, VT, Custom);
1968 setOperationAction(ISD::SRL, VT, Custom);
1969 }
1970
1971 // Extending loads from (native) vectors of i8 into (native) vectors of i16
1972 // are legal.
1973 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1974 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1975 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1976 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1977 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
1979
1980 // Types natively supported:
1981 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
1982 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
1983 MVT::v2i32, MVT::v1i64}) {
1984 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1985 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1986 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1987 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1988 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1989 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1990
1991 setOperationAction(ISD::ADD, NativeVT, Legal);
1992 setOperationAction(ISD::SUB, NativeVT, Legal);
1993 setOperationAction(ISD::MUL, NativeVT, Legal);
1994 setOperationAction(ISD::AND, NativeVT, Legal);
1995 setOperationAction(ISD::OR, NativeVT, Legal);
1996 setOperationAction(ISD::XOR, NativeVT, Legal);
1997 }
1998
1999 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
2000 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
2001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
2002 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
2003
2004 if (Subtarget.useHVXOps()) {
2005 if (Subtarget.useHVX64BOps()) {
2006 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
2007 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
2008 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
2009 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
2010 // We try to generate the vpack{e/o} instructions. If we fail
2011 // we fall back upon ExpandOp.
2012 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
2013 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
2014 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i8, Custom);
2015 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i16, Custom);
2016 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v16i32, Custom);
2017 } else if (Subtarget.useHVX128BOps()) {
2018 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
2019 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
2020 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
2021 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
2022 // We try to generate the vpack{e/o} instructions. If we fail
2023 // we fall back upon ExpandOp.
2024 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v128i8, Custom);
2025 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i16, Custom);
2026 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
2027 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v128i8, Custom);
2028 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v64i16, Custom);
2029 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v32i32, Custom);
2030 } else {
2031 llvm_unreachable("Unrecognized HVX mode")::llvm::llvm_unreachable_internal("Unrecognized HVX mode", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2031)
;
2032 }
2033 }
2034 // Subtarget-specific operation actions.
2035 //
2036 if (Subtarget.hasV5TOps()) {
2037 setOperationAction(ISD::FMA, MVT::f64, Expand);
2038 setOperationAction(ISD::FADD, MVT::f64, Expand);
2039 setOperationAction(ISD::FSUB, MVT::f64, Expand);
2040 setOperationAction(ISD::FMUL, MVT::f64, Expand);
2041
2042 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
2043 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
2044
2045 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
2046 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
2047 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
2048 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
2049 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
2050 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
2051 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
2052 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
2053 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
2054 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
2055 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
2056 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
2057 } else { // V4
2058 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
2059 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
2060 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
2061 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
2062 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
2063 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
2064 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
2065 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
2066 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
2067
2068 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
2069 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
2070 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
2071 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
2072
2073 // Expand these operations for both f32 and f64:
2074 for (unsigned FPExpOpV4 :
2075 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
2076 setOperationAction(FPExpOpV4, MVT::f32, Expand);
2077 setOperationAction(FPExpOpV4, MVT::f64, Expand);
2078 }
2079
2080 for (ISD::CondCode FPExpCCV4 :
2081 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
2082 ISD::SETUO, ISD::SETO}) {
2083 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
2084 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
2085 }
2086 }
2087
2088 // Handling of indexed loads/stores: default is "expand".
2089 //
2090 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
2091 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2092 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2093 }
2094
2095 if (Subtarget.useHVX64BOps()) {
2096 for (MVT VT : {MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64,
2097 MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
2098 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2099 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2100 }
2101 } else if (Subtarget.useHVX128BOps()) {
2102 for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64,
2103 MVT::v256i8, MVT::v128i16, MVT::v64i32, MVT::v32i64}) {
2104 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
2105 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2106 }
2107 }
2108
2109 computeRegisterProperties(&HRI);
2110
2111 //
2112 // Library calls for unsupported operations
2113 //
2114 bool FastMath = EnableFastMath;
2115
2116 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
2117 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
2118 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
2119 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
2120 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
2121 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
2122 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
2123 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
2124
2125 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
2126 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
2127 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
2128 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
2129 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
2130 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
2131
2132 if (IsV4) {
2133 // Handle single-precision floating point operations on V4.
2134 if (FastMath) {
2135 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
2136 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
2137 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
2138 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
2139 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
2140 // Double-precision compares.
2141 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
2142 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
2143 } else {
2144 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
2145 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
2146 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
2147 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
2148 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
2149 // Double-precision compares.
2150 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
2151 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
2152 }
2153 }
2154
2155 // This is the only fast library function for sqrtd.
2156 if (FastMath)
2157 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
2158
2159 // Prefix is: nothing for "slow-math",
2160 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
2161 // (actually, keep fast-math and fast-math2 separate for now)
2162 if (FastMath) {
2163 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
2164 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
2165 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
2166 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
2167 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
2168 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
2169 } else {
2170 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
2171 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
2172 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
2173 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
2174 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
2175 }
2176
2177 if (Subtarget.hasV5TOps()) {
2178 if (FastMath)
2179 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
2180 else
2181 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
2182 } else {
2183 // V4
2184 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
2185 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
2186 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
2187 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
2188 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
2189 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
2190 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
2191 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
2192 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
2193 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
2194 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
2195 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
2196 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
2197 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
2198 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
2199 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
2200 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
2201 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
2202 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
2203 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
2204 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
2205 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
2206 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
2207 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
2208 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
2209 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
2210 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
2211 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
2212 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
2213 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
2214 }
2215
2216 // These cause problems when the shift amount is non-constant.
2217 setLibcallName(RTLIB::SHL_I128, nullptr);
2218 setLibcallName(RTLIB::SRL_I128, nullptr);
2219 setLibcallName(RTLIB::SRA_I128, nullptr);
2220}
2221
2222const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2223 switch ((HexagonISD::NodeType)Opcode) {
2224 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2225 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2226 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2227 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2228 case HexagonISD::CALL: return "HexagonISD::CALL";
2229 case HexagonISD::CALLnr: return "HexagonISD::CALLnr";
2230 case HexagonISD::CALLR: return "HexagonISD::CALLR";
2231 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2232 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2233 case HexagonISD::CONST32: return "HexagonISD::CONST32";
2234 case HexagonISD::CP: return "HexagonISD::CP";
2235 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2236 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2237 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2238 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2239 case HexagonISD::INSERT: return "HexagonISD::INSERT";
2240 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2241 case HexagonISD::JT: return "HexagonISD::JT";
2242 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2243 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2244 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2245 case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2246 case HexagonISD::VPACKE: return "HexagonISD::VPACKE";
2247 case HexagonISD::VPACKO: return "HexagonISD::VPACKO";
2248 case HexagonISD::VASL: return "HexagonISD::VASL";
2249 case HexagonISD::VASR: return "HexagonISD::VASR";
2250 case HexagonISD::VLSR: return "HexagonISD::VLSR";
2251 case HexagonISD::VSPLAT: return "HexagonISD::VSPLAT";
2252 case HexagonISD::READCYCLE: return "HexagonISD::READCYCLE";
2253 case HexagonISD::OP_END: break;
2254 }
2255 return nullptr;
2256}
2257
2258bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
2259 EVT MTy1 = EVT::getEVT(Ty1);
2260 EVT MTy2 = EVT::getEVT(Ty2);
2261 if (!MTy1.isSimple() || !MTy2.isSimple())
2262 return false;
2263 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2264}
2265
2266bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
2267 if (!VT1.isSimple() || !VT2.isSimple())
2268 return false;
2269 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2270}
2271
2272bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
2273 return isOperationLegalOrCustom(ISD::FMA, VT);
2274}
2275
2276// Should we expand the build vector with shuffles?
2277bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
2278 unsigned DefinedValues) const {
2279 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2280 EVT EltVT = VT.getVectorElementType();
2281 int EltBits = EltVT.getSizeInBits();
2282 if ((EltBits != 8) && (EltBits != 16))
2283 return false;
2284
2285 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2286}
2287
2288static StridedLoadKind isStridedLoad(const ArrayRef<int> &Mask) {
2289 int even_start = -2;
2290 int odd_start = -1;
2291 size_t mask_len = Mask.size();
2292 for (auto idx : Mask) {
2293 if ((idx - even_start) == 2)
2294 even_start = idx;
2295 else
2296 break;
2297 }
2298 if (even_start == (int)(mask_len * 2) - 2)
2299 return StridedLoadKind::Even;
2300 for (auto idx : Mask) {
2301 if ((idx - odd_start) == 2)
2302 odd_start = idx;
2303 else
2304 break;
2305 }
2306 if (odd_start == (int)(mask_len * 2) - 1)
2307 return StridedLoadKind::Odd;
2308
2309 return StridedLoadKind::NoPattern;
2310}
2311
2312bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
2313 EVT VT) const {
2314 if (Subtarget.useHVXOps())
2315 return isStridedLoad(Mask) != StridedLoadKind::NoPattern;
2316 return true;
2317}
2318
2319// Lower a vector shuffle (V1, V2, V3). V1 and V2 are the two vectors
2320// to select data from, V3 is the permutation.
2321SDValue
2322HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
2323 const {
2324 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2325 SDValue V1 = Op.getOperand(0);
2326 SDValue V2 = Op.getOperand(1);
2327 SDLoc dl(Op);
2328 EVT VT = Op.getValueType();
2329 bool UseHVX = Subtarget.useHVXOps();
2330
2331 if (V2.isUndef())
2332 V2 = V1;
2333
2334 if (SVN->isSplat()) {
2335 int Lane = SVN->getSplatIndex();
2336 if (Lane == -1) Lane = 0;
2337
2338 // Test if V1 is a SCALAR_TO_VECTOR.
2339 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2340 return DAG.getNode(HexagonISD::VSPLAT, dl, VT, V1.getOperand(0));
2341
2342 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2343 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2344 // reaches it).
2345 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2346 !isa<ConstantSDNode>(V1.getOperand(0))) {
2347 bool IsScalarToVector = true;
2348 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
2349 if (!V1.getOperand(i).isUndef()) {
2350 IsScalarToVector = false;
2351 break;
2352 }
2353 }
2354 if (IsScalarToVector)
2355 return DAG.getNode(HexagonISD::VSPLAT, dl, VT, V1.getOperand(0));
2356 }
2357 return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
2358 DAG.getConstant(Lane, dl, MVT::i32));
2359 }
2360
2361 if (UseHVX) {
2362 ArrayRef<int> Mask = SVN->getMask();
2363 size_t MaskLen = Mask.size();
2364 unsigned SizeInBits = VT.getScalarSizeInBits() * MaskLen;
2365
2366 if ((Subtarget.useHVX64BOps() && SizeInBits == 64 * 8) ||
2367 (Subtarget.useHVX128BOps() && SizeInBits == 128 * 8)) {
2368 StridedLoadKind Pattern = isStridedLoad(Mask);
2369 if (Pattern == StridedLoadKind::NoPattern)
2370 return SDValue();
2371
2372 unsigned Opc = Pattern == StridedLoadKind::Even ? HexagonISD::VPACKE
2373 : HexagonISD::VPACKO;
2374 return DAG.getNode(Opc, dl, VT, {Op.getOperand(1), Op.getOperand(0)});
2375 }
2376 // We used to assert in the "else" part here, but that is bad for Halide
2377 // Halide creates intermediate double registers by interleaving two
2378 // concatenated vector registers. The interleaving requires vector_shuffle
2379 // nodes and we shouldn't barf on a double register result of a
2380 // vector_shuffle because it is most likely an intermediate result.
2381 }
2382 // FIXME: We need to support more general vector shuffles. See
2383 // below the comment from the ARM backend that deals in the general
2384 // case with the vector shuffles. For now, let expand handle these.
2385 return SDValue();
2386
2387 // If the shuffle is not directly supported and it has 4 elements, use
2388 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2389}
2390
2391// If BUILD_VECTOR has same base element repeated several times,
2392// report true.
2393static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
2394 unsigned NElts = BVN->getNumOperands();
2395 SDValue V0 = BVN->getOperand(0);
2396
2397 for (unsigned i = 1, e = NElts; i != e; ++i) {
2398 if (BVN->getOperand(i) != V0)
2399 return false;
2400 }
2401 return true;
2402}
2403
2404// Lower a vector shift. Try to convert
2405// <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2406// <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
2407SDValue
2408HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
2409 BuildVectorSDNode *BVN = nullptr;
2410 SDValue V1 = Op.getOperand(0);
2411 SDValue V2 = Op.getOperand(1);
2412 SDValue V3;
2413 SDLoc dl(Op);
2414 EVT VT = Op.getValueType();
2415
2416 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2417 isCommonSplatElement(BVN))
2418 V3 = V2;
2419 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2420 isCommonSplatElement(BVN))
2421 V3 = V1;
2422 else
2423 return SDValue();
2424
2425 SDValue CommonSplat = BVN->getOperand(0);
2426 SDValue Result;
2427
2428 if (VT.getSimpleVT() == MVT::v4i16) {
2429 switch (Op.getOpcode()) {
2430 case ISD::SRA:
2431 Result = DAG.getNode(HexagonISD::VASR, dl, VT, V3, CommonSplat);
2432 break;
2433 case ISD::SHL:
2434 Result = DAG.getNode(HexagonISD::VASL, dl, VT, V3, CommonSplat);
2435 break;
2436 case ISD::SRL:
2437 Result = DAG.getNode(HexagonISD::VLSR, dl, VT, V3, CommonSplat);
2438 break;
2439 default:
2440 return SDValue();
2441 }
2442 } else if (VT.getSimpleVT() == MVT::v2i32) {
2443 switch (Op.getOpcode()) {
2444 case ISD::SRA:
2445 Result = DAG.getNode(HexagonISD::VASR, dl, VT, V3, CommonSplat);
2446 break;
2447 case ISD::SHL:
2448 Result = DAG.getNode(HexagonISD::VASL, dl, VT, V3, CommonSplat);
2449 break;
2450 case ISD::SRL:
2451 Result = DAG.getNode(HexagonISD::VLSR, dl, VT, V3, CommonSplat);
2452 break;
2453 default:
2454 return SDValue();
2455 }
2456 } else {
2457 return SDValue();
2458 }
2459
2460 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2461}
2462
2463SDValue
2464HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
2465 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2466 SDLoc dl(Op);
2467 EVT VT = Op.getValueType();
2468
2469 unsigned Size = VT.getSizeInBits();
2470
2471 // Only handle vectors of 64 bits or shorter.
2472 if (Size > 64)
2473 return SDValue();
2474
2475 unsigned NElts = BVN->getNumOperands();
2476
2477 // Try to generate a SPLAT instruction.
2478 if (VT == MVT::v4i8 || VT == MVT::v4i16 || VT == MVT::v2i32) {
2479 APInt APSplatBits, APSplatUndef;
2480 unsigned SplatBitSize;
2481 bool HasAnyUndefs;
2482 if (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2483 HasAnyUndefs, 0, false)) {
2484 if (SplatBitSize == VT.getVectorElementType().getSizeInBits()) {
2485 unsigned ZV = APSplatBits.getZExtValue();
2486 assert(SplatBitSize <= 32 && "Can only handle up to i32")((SplatBitSize <= 32 && "Can only handle up to i32"
) ? static_cast<void> (0) : __assert_fail ("SplatBitSize <= 32 && \"Can only handle up to i32\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2486, __PRETTY_FUNCTION__))
;
2487 // Sign-extend the splat value from SplatBitSize to 32.
2488 int32_t SV = SplatBitSize < 32
2489 ? int32_t(ZV << (32-SplatBitSize)) >> (32-SplatBitSize)
2490 : int32_t(ZV);
2491 return DAG.getNode(HexagonISD::VSPLAT, dl, VT,
2492 DAG.getConstant(SV, dl, MVT::i32));
2493 }
2494 }
2495 }
2496
2497 // Try to generate COMBINE to build v2i32 vectors.
2498 if (VT.getSimpleVT() == MVT::v2i32) {
2499 SDValue V0 = BVN->getOperand(0);
2500 SDValue V1 = BVN->getOperand(1);
2501
2502 if (V0.isUndef())
2503 V0 = DAG.getConstant(0, dl, MVT::i32);
2504 if (V1.isUndef())
2505 V1 = DAG.getConstant(0, dl, MVT::i32);
2506
2507 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2508 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
2509 // If the element isn't a constant, it is in a register:
2510 // generate a COMBINE Register Register instruction.
2511 if (!C0 || !C1)
2512 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2513
2514 // If one of the operands is an 8 bit integer constant, generate
2515 // a COMBINE Immediate Immediate instruction.
2516 if (isInt<8>(C0->getSExtValue()) ||
2517 isInt<8>(C1->getSExtValue()))
2518 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2519 }
2520
2521 // Try to generate a S2_packhl to build v2i16 vectors.
2522 if (VT.getSimpleVT() == MVT::v2i16) {
2523 for (unsigned i = 0, e = NElts; i != e; ++i) {
2524 if (BVN->getOperand(i).isUndef())
2525 continue;
2526 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
2527 // If the element isn't a constant, it is in a register:
2528 // generate a S2_packhl instruction.
2529 if (!Cst) {
2530 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2531 BVN->getOperand(1), BVN->getOperand(0));
2532
2533 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::v2i16,
2534 pack);
2535 }
2536 }
2537 }
2538
2539 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2540 // and insert_vector_elt for all the other cases.
2541 uint64_t Res = 0;
2542 unsigned EltSize = Size / NElts;
2543 SDValue ConstVal;
2544 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2545 bool HasNonConstantElements = false;
2546
2547 for (unsigned i = 0, e = NElts; i != e; ++i) {
2548 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2549 // combine, const64, etc. are Big Endian.
2550 unsigned OpIdx = NElts - i - 1;
2551 SDValue Operand = BVN->getOperand(OpIdx);
2552 if (Operand.isUndef())
2553 continue;
2554
2555 int64_t Val = 0;
2556 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2557 Val = Cst->getSExtValue();
2558 else
2559 HasNonConstantElements = true;
2560
2561 Val &= Mask;
2562 Res = (Res << EltSize) | Val;
2563 }
2564
2565 if (Size > 64)
2566 return SDValue();
2567
2568 if (Size == 64)
2569 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2570 else
2571 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2572
2573 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2574 // ConstVal, the constant part of the vector.
2575 if (HasNonConstantElements) {
2576 EVT EltVT = VT.getVectorElementType();
2577 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2578 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2579 DAG.getConstant(32, dl, MVT::i64));
2580
2581 for (unsigned i = 0, e = NElts; i != e; ++i) {
2582 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2583 // is Big Endian.
2584 unsigned OpIdx = NElts - i - 1;
2585 SDValue Operand = BVN->getOperand(OpIdx);
2586 if (isa<ConstantSDNode>(Operand))
2587 // This operand is already in ConstVal.
2588 continue;
2589
2590 if (VT.getSizeInBits() == 64 &&
2591 Operand.getValueSizeInBits() == 32) {
2592 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2593 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2594 }
2595
2596 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2597 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2598 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2599 const SDValue Ops[] = {ConstVal, Operand, Combined};
2600
2601 if (VT.getSizeInBits() == 32)
2602 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2603 else
2604 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2605 }
2606 }
2607
2608 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2609}
2610
2611SDValue
2612HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2613 SelectionDAG &DAG) const {
2614 SDLoc dl(Op);
2615 bool UseHVX = Subtarget.useHVXOps();
2616 EVT VT = Op.getValueType();
2617 unsigned NElts = Op.getNumOperands();
2618 SDValue Vec0 = Op.getOperand(0);
2619 EVT VecVT = Vec0.getValueType();
2620 unsigned Width = VecVT.getSizeInBits();
2621
2622 if (NElts == 2) {
2623 MVT ST = VecVT.getSimpleVT();
2624 // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2625 // into a single v8i8.
2626 if (ST == MVT::v2i16 || ST == MVT::v4i8)
2627 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2628
2629 if (UseHVX) {
2630 assert((Width == 64 * 8 && Subtarget.useHVX64BOps()) ||(((Width == 64 * 8 && Subtarget.useHVX64BOps()) || (Width
== 128 * 8 && Subtarget.useHVX128BOps())) ? static_cast
<void> (0) : __assert_fail ("(Width == 64 * 8 && Subtarget.useHVX64BOps()) || (Width == 128 * 8 && Subtarget.useHVX128BOps())"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2631, __PRETTY_FUNCTION__))
2631 (Width == 128 * 8 && Subtarget.useHVX128BOps()))(((Width == 64 * 8 && Subtarget.useHVX64BOps()) || (Width
== 128 * 8 && Subtarget.useHVX128BOps())) ? static_cast
<void> (0) : __assert_fail ("(Width == 64 * 8 && Subtarget.useHVX64BOps()) || (Width == 128 * 8 && Subtarget.useHVX128BOps())"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2631, __PRETTY_FUNCTION__))
;
2632 SDValue Vec1 = Op.getOperand(1);
2633 MVT OpTy = Subtarget.useHVX64BOps() ? MVT::v16i32 : MVT::v32i32;
2634 MVT ReTy = Subtarget.useHVX64BOps() ? MVT::v32i32 : MVT::v64i32;
2635 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2636 SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2637 SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2638 return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2639 }
2640 }
2641
2642 if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2643 return SDValue();
2644
2645 SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2646 SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2647 SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2648 // Create the "width" part of the argument to insert_rp/insertp_rp.
2649 SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2650 SDValue V = C0;
2651
2652 for (unsigned i = 0, e = NElts; i != e; ++i) {
2653 unsigned N = NElts-i-1;
2654 SDValue OpN = Op.getOperand(N);
2655
2656 if (VT.getSizeInBits() == 64 && OpN.getValueSizeInBits() == 32) {
2657 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2658 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2659 }
2660 SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2661 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2662 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2663 if (VT.getSizeInBits() == 32)
2664 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2665 else if (VT.getSizeInBits() == 64)
2666 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2667 else
2668 return SDValue();
2669 }
2670
2671 return DAG.getNode(ISD::BITCAST, dl, VT, V);
2672}
2673
2674SDValue
2675HexagonTargetLowering::LowerEXTRACT_SUBVECTOR_HVX(SDValue Op,
2676 SelectionDAG &DAG) const {
2677 EVT VT = Op.getOperand(0).getValueType();
2678 SDLoc dl(Op);
2679 bool UseHVX = Subtarget.useHVXOps();
2680 bool UseHVX64B = Subtarget.useHVX64BOps();
2681 // Just in case...
2682
2683 if (!VT.isVector() || !UseHVX)
2684 return SDValue();
2685
2686 EVT ResVT = Op.getValueType();
2687 unsigned ResSize = ResVT.getSizeInBits();
2688 unsigned VectorSizeInBits = UseHVX64B ? (64 * 8) : (128 * 8);
2689 unsigned OpSize = VT.getSizeInBits();
2690
2691 // We deal only with cases where the result is the vector size
2692 // and the vector operand is a double register.
2693 if (!(ResVT.isByteSized() && ResSize == VectorSizeInBits) ||
2694 !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
2695 return SDValue();
2696
2697 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2698 if (!Cst)
2699 return SDValue();
2700 unsigned Val = Cst->getZExtValue();
2701
2702 // These two will get lowered to an appropriate EXTRACT_SUBREG in ISel.
2703 if (Val == 0) {
2704 SDValue Vec = Op.getOperand(0);
2705 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResVT, Vec);
2706 }
2707
2708 if (ResVT.getVectorNumElements() == Val) {
2709 SDValue Vec = Op.getOperand(0);
2710 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResVT, Vec);
2711 }
2712
2713 return SDValue();
2714}
2715
2716SDValue
2717HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2718 SelectionDAG &DAG) const {
2719 // If we are dealing with EXTRACT_SUBVECTOR on a HVX type, we may
2720 // be able to simplify it to an EXTRACT_SUBREG.
2721 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR && Subtarget.useHVXOps() &&
2722 isHvxVectorType(Op.getValueType().getSimpleVT()))
2723 return LowerEXTRACT_SUBVECTOR_HVX(Op, DAG);
2724
2725 EVT VT = Op.getValueType();
2726 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2727 SDLoc dl(Op);
2728 SDValue Idx = Op.getOperand(1);
2729 SDValue Vec = Op.getOperand(0);
2730 EVT VecVT = Vec.getValueType();
2731 EVT EltVT = VecVT.getVectorElementType();
2732 int EltSize = EltVT.getSizeInBits();
2733 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2734 EltSize : VTN * EltSize, dl, MVT::i64);
2735
2736 // Constant element number.
2737 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2738 uint64_t X = CI->getZExtValue();
2739 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2740 const SDValue Ops[] = {Vec, Width, Offset};
2741
2742 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2743 assert(CW && "Non constant width in LowerEXTRACT_VECTOR")((CW && "Non constant width in LowerEXTRACT_VECTOR") ?
static_cast<void> (0) : __assert_fail ("CW && \"Non constant width in LowerEXTRACT_VECTOR\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2743, __PRETTY_FUNCTION__))
;
2744
2745 SDValue N;
2746 MVT SVT = VecVT.getSimpleVT();
2747 uint64_t W = CW->getZExtValue();
2748
2749 if (W == 1) {
2750 MVT LocVT = MVT::getIntegerVT(SVT.getSizeInBits());
2751 SDValue VecCast = DAG.getNode(ISD::BITCAST, dl, LocVT, Vec);
2752 SDValue Shifted = DAG.getNode(ISD::SRA, dl, LocVT, VecCast, Offset);
2753 return DAG.getNode(ISD::AND, dl, LocVT, Shifted,
2754 DAG.getConstant(1, dl, LocVT));
2755 } else if (W == 32) {
2756 // Translate this node into EXTRACT_SUBREG.
2757 unsigned Subreg = (X == 0) ? Hexagon::isub_lo : 0;
2758
2759 if (X == 0)
2760 Subreg = Hexagon::isub_lo;
2761 else if (SVT == MVT::v2i32 && X == 1)
2762 Subreg = Hexagon::isub_hi;
2763 else if (SVT == MVT::v4i16 && X == 2)
2764 Subreg = Hexagon::isub_hi;
2765 else if (SVT == MVT::v8i8 && X == 4)
2766 Subreg = Hexagon::isub_hi;
2767 else
2768 llvm_unreachable("Bad offset")::llvm::llvm_unreachable_internal("Bad offset", "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2768)
;
2769 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2770
2771 } else if (SVT.getSizeInBits() == 32) {
2772 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2773 } else if (SVT.getSizeInBits() == 64) {
2774 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2775 if (VT.getSizeInBits() == 32)
2776 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2777 } else
2778 return SDValue();
2779
2780 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2781 }
2782
2783 // Variable element number.
2784 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2785 DAG.getConstant(EltSize, dl, MVT::i32));
2786 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2787 DAG.getConstant(32, dl, MVT::i64));
2788 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2789
2790 const SDValue Ops[] = {Vec, Combined};
2791
2792 SDValue N;
2793 if (VecVT.getSizeInBits() == 32) {
2794 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2795 } else {
2796 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2797 if (VT.getSizeInBits() == 32)
2798 N = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, N);
2799 }
2800 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2801}
2802
2803SDValue
2804HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2805 SelectionDAG &DAG) const {
2806 EVT VT = Op.getValueType();
2807 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2808 SDLoc dl(Op);
2809 SDValue Vec = Op.getOperand(0);
2810 SDValue Val = Op.getOperand(1);
2811 SDValue Idx = Op.getOperand(2);
2812 EVT VecVT = Vec.getValueType();
2813 EVT EltVT = VecVT.getVectorElementType();
2814 int EltSize = EltVT.getSizeInBits();
2815 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2816 EltSize : VTN * EltSize, dl, MVT::i64);
2817
2818 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2819 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2820 const SDValue Ops[] = {Vec, Val, Width, Offset};
2821
2822 SDValue N;
2823 if (VT.getSizeInBits() == 32)
2824 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2825 else if (VT.getSizeInBits() == 64)
2826 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2827 else
2828 return SDValue();
2829
2830 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2831 }
2832
2833 // Variable element number.
2834 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2835 DAG.getConstant(EltSize, dl, MVT::i32));
2836 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2837 DAG.getConstant(32, dl, MVT::i64));
2838 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2839
2840 if (VT.getSizeInBits() == 64 && Val.getValueSizeInBits() == 32) {
2841 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2842 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2843 }
2844
2845 const SDValue Ops[] = {Vec, Val, Combined};
2846
2847 SDValue N;
2848 if (VT.getSizeInBits() == 32)
2849 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2850 else if (VT.getSizeInBits() == 64)
2851 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2852 else
2853 return SDValue();
2854
2855 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2856}
2857
2858bool
2859HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2860 // Assuming the caller does not have either a signext or zeroext modifier, and
2861 // only one value is accepted, any reasonable truncation is allowed.
2862 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2863 return false;
2864
2865 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2866 // fragile at the moment: any support for multiple value returns would be
2867 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2868 return Ty1->getPrimitiveSizeInBits() <= 32;
2869}
2870
2871SDValue
2872HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2873 SDValue Chain = Op.getOperand(0);
2874 SDValue Offset = Op.getOperand(1);
2875 SDValue Handler = Op.getOperand(2);
2876 SDLoc dl(Op);
2877 auto PtrVT = getPointerTy(DAG.getDataLayout());
2878
2879 // Mark function as containing a call to EH_RETURN.
2880 HexagonMachineFunctionInfo *FuncInfo =
2881 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2882 FuncInfo->setHasEHReturn();
2883
2884 unsigned OffsetReg = Hexagon::R28;
2885
2886 SDValue StoreAddr =
2887 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2888 DAG.getIntPtrConstant(4, dl));
2889 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
2890 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2891
2892 // Not needed we already use it as explict input to EH_RETURN.
2893 // MF.getRegInfo().addLiveOut(OffsetReg);
2894
2895 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2896}
2897
2898SDValue
2899HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2900 unsigned Opc = Op.getOpcode();
2901 switch (Opc) {
2902 default:
2903#ifndef NDEBUG
2904 Op.getNode()->dumpr(&DAG);
2905 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2906 errs() << "Check for a non-legal type in this operation\n";
2907#endif
2908 llvm_unreachable("Should not custom lower this!")::llvm::llvm_unreachable_internal("Should not custom lower this!"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2908)
;
2909 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2910 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2911 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2912 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2913 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2914 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2915 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2916 case ISD::SRA:
2917 case ISD::SHL:
2918 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2919 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2920 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2921 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2922 // Frame & Return address. Currently unimplemented.
2923 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2924 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2925 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2926 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2927 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2928 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2929 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2930 case ISD::VASTART: return LowerVASTART(Op, DAG);
2931 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2932 case ISD::SETCC: return LowerSETCC(Op, DAG);
2933 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2934 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2935 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
2936 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2937 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG);
2938 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
2939 }
2940}
2941
2942/// Returns relocation base for the given PIC jumptable.
2943SDValue
2944HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2945 SelectionDAG &DAG) const {
2946 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2947 EVT VT = Table.getValueType();
2948 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
2949 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2950}
2951
2952//===----------------------------------------------------------------------===//
2953// Inline Assembly Support
2954//===----------------------------------------------------------------------===//
2955
2956TargetLowering::ConstraintType
2957HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
2958 if (Constraint.size() == 1) {
2959 switch (Constraint[0]) {
2960 case 'q':
2961 case 'v':
2962 if (Subtarget.useHVXOps())
2963 return C_RegisterClass;
2964 break;
2965 case 'a':
2966 return C_RegisterClass;
2967 default:
2968 break;
2969 }
2970 }
2971 return TargetLowering::getConstraintType(Constraint);
2972}
2973
2974std::pair<unsigned, const TargetRegisterClass*>
2975HexagonTargetLowering::getRegForInlineAsmConstraint(
2976 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2977
2978 if (Constraint.size() == 1) {
2979 switch (Constraint[0]) {
2980 case 'r': // R0-R31
2981 switch (VT.SimpleTy) {
2982 default:
2983 return {0u, nullptr};
2984 case MVT::i1:
2985 case MVT::i8:
2986 case MVT::i16:
2987 case MVT::i32:
2988 case MVT::f32:
2989 return {0u, &Hexagon::IntRegsRegClass};
2990 case MVT::i64:
2991 case MVT::f64:
2992 return {0u, &Hexagon::DoubleRegsRegClass};
2993 }
2994 break;
2995 case 'a': // M0-M1
2996 if (VT != MVT::i32)
2997 return {0u, nullptr};
2998 return {0u, &Hexagon::ModRegsRegClass};
2999 case 'q': // q0-q3
3000 switch (VT.getSizeInBits()) {
3001 default:
3002 return {0u, nullptr};
3003 case 512:
3004 case 1024:
3005 return {0u, &Hexagon::HvxQRRegClass};
3006 }
3007 break;
3008 case 'v': // V0-V31
3009 switch (VT.getSizeInBits()) {
3010 default:
3011 return {0u, nullptr};
3012 case 512:
3013 return {0u, &Hexagon::HvxVRRegClass};
3014 case 1024:
3015 if (Subtarget.hasV60TOps() && Subtarget.useHVX128BOps())
3016 return {0u, &Hexagon::HvxVRRegClass};
3017 return {0u, &Hexagon::HvxWRRegClass};
3018 case 2048:
3019 return {0u, &Hexagon::HvxWRRegClass};
3020 }
3021 break;
3022 default:
3023 return {0u, nullptr};
3024 }
3025 }
3026
3027 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3028}
3029
3030/// isFPImmLegal - Returns true if the target can instruction select the
3031/// specified FP immediate natively. If false, the legalizer will
3032/// materialize the FP immediate as a load from a constant pool.
3033bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3034 return Subtarget.hasV5TOps();
3035}
3036
3037/// isLegalAddressingMode - Return true if the addressing mode represented by
3038/// AM is legal for this target, for a load/store of the specified type.
3039bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3040 const AddrMode &AM, Type *Ty,
3041 unsigned AS, Instruction *I) const {
3042 if (Ty->isSized()) {
3043 // When LSR detects uses of the same base address to access different
3044 // types (e.g. unions), it will assume a conservative type for these
3045 // uses:
3046 // LSR Use: Kind=Address of void in addrspace(4294967295), ...
3047 // The type Ty passed here would then be "void". Skip the alignment
3048 // checks, but do not return false right away, since that confuses
3049 // LSR into crashing.
3050 unsigned A = DL.getABITypeAlignment(Ty);
3051 // The base offset must be a multiple of the alignment.
3052 if ((AM.BaseOffs % A) != 0)
3053 return false;
3054 // The shifted offset must fit in 11 bits.
3055 if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
3056 return false;
3057 }
3058
3059 // No global is ever allowed as a base.
3060 if (AM.BaseGV)
3061 return false;
3062
3063 int Scale = AM.Scale;
3064 if (Scale < 0)
3065 Scale = -Scale;
3066 switch (Scale) {
3067 case 0: // No scale reg, "r+i", "r", or just "i".
3068 break;
3069 default: // No scaled addressing mode.
3070 return false;
3071 }
3072 return true;
3073}
3074
3075/// Return true if folding a constant offset with the given GlobalAddress is
3076/// legal. It is frequently not legal in PIC relocation models.
3077bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
3078 const {
3079 return HTM.getRelocationModel() == Reloc::Static;
3080}
3081
3082/// isLegalICmpImmediate - Return true if the specified immediate is legal
3083/// icmp immediate, that is the target has icmp instructions which can compare
3084/// a register against the immediate without having to materialize the
3085/// immediate into a register.
3086bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3087 return Imm >= -512 && Imm <= 511;
3088}
3089
3090/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3091/// for tail call optimization. Targets which want to do tail call
3092/// optimization should implement this function.
3093bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
3094 SDValue Callee,
3095 CallingConv::ID CalleeCC,
3096 bool isVarArg,
3097 bool isCalleeStructRet,
3098 bool isCallerStructRet,
3099 const SmallVectorImpl<ISD::OutputArg> &Outs,
3100 const SmallVectorImpl<SDValue> &OutVals,
3101 const SmallVectorImpl<ISD::InputArg> &Ins,
3102 SelectionDAG& DAG) const {
3103 const Function *CallerF = DAG.getMachineFunction().getFunction();
3104 CallingConv::ID CallerCC = CallerF->getCallingConv();
3105 bool CCMatch = CallerCC == CalleeCC;
3106
3107 // ***************************************************************************
3108 // Look for obvious safe cases to perform tail call optimization that do not
3109 // require ABI changes.
3110 // ***************************************************************************
3111
3112 // If this is a tail call via a function pointer, then don't do it!
3113 if (!isa<GlobalAddressSDNode>(Callee) &&
3114 !isa<ExternalSymbolSDNode>(Callee)) {
3115 return false;
3116 }
3117
3118 // Do not optimize if the calling conventions do not match and the conventions
3119 // used are not C or Fast.
3120 if (!CCMatch) {
3121 bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
3122 bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
3123 // If R & E, then ok.
3124 if (!R || !E)
3125 return false;
3126 }
3127
3128 // Do not tail call optimize vararg calls.
3129 if (isVarArg)
3130 return false;
3131
3132 // Also avoid tail call optimization if either caller or callee uses struct
3133 // return semantics.
3134 if (isCalleeStructRet || isCallerStructRet)
3135 return false;
3136
3137 // In addition to the cases above, we also disable Tail Call Optimization if
3138 // the calling convention code that at least one outgoing argument needs to
3139 // go on the stack. We cannot check that here because at this point that
3140 // information is not available.
3141 return true;
3142}
3143
3144/// Returns the target specific optimal type for load and store operations as
3145/// a result of memset, memcpy, and memmove lowering.
3146///
3147/// If DstAlign is zero that means it's safe to destination alignment can
3148/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3149/// a need to check it against alignment requirement, probably because the
3150/// source does not need to be loaded. If 'IsMemset' is true, that means it's
3151/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3152/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3153/// does not need to be loaded. It returns EVT::Other if the type should be
3154/// determined using generic target-independent logic.
3155EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size,
3156 unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
3157 bool MemcpyStrSrc, MachineFunction &MF) const {
3158
3159 auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
3160 return (GivenA % MinA) == 0;
3161 };
3162
3163 if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
3164 return MVT::i64;
3165 if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
3166 return MVT::i32;
3167 if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
3168 return MVT::i16;
3169
3170 return MVT::Other;
3171}
3172
3173bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
3174 unsigned AS, unsigned Align, bool *Fast) const {
3175 if (Fast)
3176 *Fast = false;
3177
3178 switch (VT.getSimpleVT().SimpleTy) {
3179 default:
3180 return false;
3181 case MVT::v64i8:
3182 case MVT::v128i8:
3183 case MVT::v256i8:
3184 case MVT::v32i16:
3185 case MVT::v64i16:
3186 case MVT::v128i16:
3187 case MVT::v16i32:
3188 case MVT::v32i32:
3189 case MVT::v64i32:
3190 case MVT::v8i64:
3191 case MVT::v16i64:
3192 case MVT::v32i64:
3193 return true;
3194 }
3195 return false;
3196}
3197
3198std::pair<const TargetRegisterClass*, uint8_t>
3199HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
3200 MVT VT) const {
3201 const TargetRegisterClass *RRC = nullptr;
3202
3203 uint8_t Cost = 1;
3204 switch (VT.SimpleTy) {
3205 default:
3206 return TargetLowering::findRepresentativeClass(TRI, VT);
3207 case MVT::v64i8:
3208 case MVT::v32i16:
3209 case MVT::v16i32:
3210 case MVT::v8i64:
3211 RRC = &Hexagon::HvxVRRegClass;
3212 break;
3213 case MVT::v128i8:
3214 case MVT::v64i16:
3215 case MVT::v32i32:
3216 case MVT::v16i64:
3217 if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
3218 Subtarget.useHVX128BOps())
3219 RRC = &Hexagon::HvxVRRegClass;
3220 else
3221 RRC = &Hexagon::HvxWRRegClass;
3222 break;
3223 case MVT::v256i8:
3224 case MVT::v128i16:
3225 case MVT::v64i32:
3226 case MVT::v32i64:
3227 RRC = &Hexagon::HvxWRRegClass;
3228 break;
3229 }
3230 return std::make_pair(RRC, Cost);
3231}
3232
3233Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
3234 AtomicOrdering Ord) const {
3235 BasicBlock *BB = Builder.GetInsertBlock();
3236 Module *M = BB->getParent()->getParent();
3237 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
3238 unsigned SZ = Ty->getPrimitiveSizeInBits();
3239 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic loads supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3239, __PRETTY_FUNCTION__))
;
3240 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3241 : Intrinsic::hexagon_L4_loadd_locked;
3242 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3243 return Builder.CreateCall(Fn, Addr, "larx");
3244}
3245
3246/// Perform a store-conditional operation to Addr. Return the status of the
3247/// store. This should be 0 if the store succeeded, non-zero otherwise.
3248Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
3249 Value *Val, Value *Addr, AtomicOrdering Ord) const {
3250 BasicBlock *BB = Builder.GetInsertBlock();
3251 Module *M = BB->getParent()->getParent();
3252 Type *Ty = Val->getType();
3253 unsigned SZ = Ty->getPrimitiveSizeInBits();
3254 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic stores supported\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3254, __PRETTY_FUNCTION__))
;
3255 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3256 : Intrinsic::hexagon_S4_stored_locked;
3257 Value *Fn = Intrinsic::getDeclaration(M, IntID);
3258 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
3259 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
3260 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
3261 return Ext;
3262}
3263
3264TargetLowering::AtomicExpansionKind
3265HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
3266 // Do not expand loads and stores that don't exceed 64 bits.
3267 return LI->getType()->getPrimitiveSizeInBits() > 64
3268 ? AtomicExpansionKind::LLOnly
3269 : AtomicExpansionKind::None;
3270}
3271
3272bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
3273 // Do not expand loads and stores that don't exceed 64 bits.
3274 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3275}
3276
3277bool HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
3278 AtomicCmpXchgInst *AI) const {
3279 const DataLayout &DL = AI->getModule()->getDataLayout();
3280 unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
3281 return Size >= 4 && Size <= 8;
3282}

/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h

1//===- llvm/CodeGen/SelectionDAG.h - InstSelection DAG ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the SelectionDAG class, and transitively defines the
11// SDNode class and subclasses.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_SELECTIONDAG_H
16#define LLVM_CODEGEN_SELECTIONDAG_H
17
18#include "llvm/ADT/APFloat.h"
19#include "llvm/ADT/APInt.h"
20#include "llvm/ADT/ArrayRef.h"
21#include "llvm/ADT/DenseMap.h"
22#include "llvm/ADT/DenseSet.h"
23#include "llvm/ADT/FoldingSet.h"
24#include "llvm/ADT/SetVector.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/StringMap.h"
27#include "llvm/ADT/ilist.h"
28#include "llvm/ADT/iterator.h"
29#include "llvm/ADT/iterator_range.h"
30#include "llvm/Analysis/AliasAnalysis.h"
31#include "llvm/CodeGen/DAGCombine.h"
32#include "llvm/CodeGen/ISDOpcodes.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineMemOperand.h"
35#include "llvm/CodeGen/MachineValueType.h"
36#include "llvm/CodeGen/SelectionDAGNodes.h"
37#include "llvm/CodeGen/ValueTypes.h"
38#include "llvm/IR/DebugLoc.h"
39#include "llvm/IR/Instructions.h"
40#include "llvm/IR/Metadata.h"
41#include "llvm/Support/Allocator.h"
42#include "llvm/Support/ArrayRecycler.h"
43#include "llvm/Support/AtomicOrdering.h"
44#include "llvm/Support/Casting.h"
45#include "llvm/Support/CodeGen.h"
46#include "llvm/Support/ErrorHandling.h"
47#include "llvm/Support/RecyclingAllocator.h"
48#include <algorithm>
49#include <cassert>
50#include <cstdint>
51#include <functional>
52#include <map>
53#include <string>
54#include <tuple>
55#include <utility>
56#include <vector>
57
58namespace llvm {
59
60class BlockAddress;
61class Constant;
62class ConstantFP;
63class ConstantInt;
64class DataLayout;
65struct fltSemantics;
66class GlobalValue;
67struct KnownBits;
68class LLVMContext;
69class MachineBasicBlock;
70class MachineConstantPoolValue;
71class MCSymbol;
72class OptimizationRemarkEmitter;
73class SDDbgValue;
74class SelectionDAG;
75class SelectionDAGTargetInfo;
76class TargetLowering;
77class TargetMachine;
78class TargetSubtargetInfo;
79class Value;
80
81class SDVTListNode : public FoldingSetNode {
82 friend struct FoldingSetTrait<SDVTListNode>;
83
84 /// A reference to an Interned FoldingSetNodeID for this node.
85 /// The Allocator in SelectionDAG holds the data.
86 /// SDVTList contains all types which are frequently accessed in SelectionDAG.
87 /// The size of this list is not expected to be big so it won't introduce
88 /// a memory penalty.
89 FoldingSetNodeIDRef FastID;
90 const EVT *VTs;
91 unsigned int NumVTs;
92 /// The hash value for SDVTList is fixed, so cache it to avoid
93 /// hash calculation.
94 unsigned HashValue;
95
96public:
97 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
98 FastID(ID), VTs(VT), NumVTs(Num) {
99 HashValue = ID.ComputeHash();
100 }
101
102 SDVTList getSDVTList() {
103 SDVTList result = {VTs, NumVTs};
104 return result;
105 }
106};
107
108/// Specialize FoldingSetTrait for SDVTListNode
109/// to avoid computing temp FoldingSetNodeID and hash value.
110template<> struct FoldingSetTrait<SDVTListNode> : DefaultFoldingSetTrait<SDVTListNode> {
111 static void Profile(const SDVTListNode &X, FoldingSetNodeID& ID) {
112 ID = X.FastID;
113 }
114
115 static bool Equals(const SDVTListNode &X, const FoldingSetNodeID &ID,
116 unsigned IDHash, FoldingSetNodeID &TempID) {
117 if (X.HashValue != IDHash)
118 return false;
119 return ID == X.FastID;
120 }
121
122 static unsigned ComputeHash(const SDVTListNode &X, FoldingSetNodeID &TempID) {
123 return X.HashValue;
124 }
125};
126
127template <> struct ilist_alloc_traits<SDNode> {
128 static void deleteNode(SDNode *) {
129 llvm_unreachable("ilist_traits<SDNode> shouldn't see a deleteNode call!")::llvm::llvm_unreachable_internal("ilist_traits<SDNode> shouldn't see a deleteNode call!"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 129)
;
130 }
131};
132
133/// Keeps track of dbg_value information through SDISel. We do
134/// not build SDNodes for these so as not to perturb the generated code;
135/// instead the info is kept off to the side in this structure. Each SDNode may
136/// have one or more associated dbg_value entries. This information is kept in
137/// DbgValMap.
138/// Byval parameters are handled separately because they don't use alloca's,
139/// which busts the normal mechanism. There is good reason for handling all
140/// parameters separately: they may not have code generated for them, they
141/// should always go at the beginning of the function regardless of other code
142/// motion, and debug info for them is potentially useful even if the parameter
143/// is unused. Right now only byval parameters are handled separately.
144class SDDbgInfo {
145 BumpPtrAllocator Alloc;
146 SmallVector<SDDbgValue*, 32> DbgValues;
147 SmallVector<SDDbgValue*, 32> ByvalParmDbgValues;
148 using DbgValMapType = DenseMap<const SDNode *, SmallVector<SDDbgValue *, 2>>;
149 DbgValMapType DbgValMap;
150
151public:
152 SDDbgInfo() = default;
153 SDDbgInfo(const SDDbgInfo &) = delete;
154 SDDbgInfo &operator=(const SDDbgInfo &) = delete;
155
156 void add(SDDbgValue *V, const SDNode *Node, bool isParameter) {
157 if (isParameter) {
158 ByvalParmDbgValues.push_back(V);
159 } else DbgValues.push_back(V);
160 if (Node)
161 DbgValMap[Node].push_back(V);
162 }
163
164 /// \brief Invalidate all DbgValues attached to the node and remove
165 /// it from the Node-to-DbgValues map.
166 void erase(const SDNode *Node);
167
168 void clear() {
169 DbgValMap.clear();
170 DbgValues.clear();
171 ByvalParmDbgValues.clear();
172 Alloc.Reset();
173 }
174
175 BumpPtrAllocator &getAlloc() { return Alloc; }
176
177 bool empty() const {
178 return DbgValues.empty() && ByvalParmDbgValues.empty();
179 }
180
181 ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) {
182 DbgValMapType::iterator I = DbgValMap.find(Node);
183 if (I != DbgValMap.end())
184 return I->second;
185 return ArrayRef<SDDbgValue*>();
186 }
187
188 using DbgIterator = SmallVectorImpl<SDDbgValue*>::iterator;
189
190 DbgIterator DbgBegin() { return DbgValues.begin(); }
191 DbgIterator DbgEnd() { return DbgValues.end(); }
192 DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }
193 DbgIterator ByvalParmDbgEnd() { return ByvalParmDbgValues.end(); }
194};
195
196void checkForCycles(const SelectionDAG *DAG, bool force = false);
197
198/// This is used to represent a portion of an LLVM function in a low-level
199/// Data Dependence DAG representation suitable for instruction selection.
200/// This DAG is constructed as the first step of instruction selection in order
201/// to allow implementation of machine specific optimizations
202/// and code simplifications.
203///
204/// The representation used by the SelectionDAG is a target-independent
205/// representation, which has some similarities to the GCC RTL representation,
206/// but is significantly more simple, powerful, and is a graph form instead of a
207/// linear form.
208///
209class SelectionDAG {
210 const TargetMachine &TM;
211 const SelectionDAGTargetInfo *TSI = nullptr;
212 const TargetLowering *TLI = nullptr;
213 MachineFunction *MF;
214 Pass *SDAGISelPass = nullptr;
215 LLVMContext *Context;
216 CodeGenOpt::Level OptLevel;
217
218 /// The function-level optimization remark emitter. Used to emit remarks
219 /// whenever manipulating the DAG.
220 OptimizationRemarkEmitter *ORE;
221
222 /// The starting token.
223 SDNode EntryNode;
224
225 /// The root of the entire DAG.
226 SDValue Root;
227
228 /// A linked list of nodes in the current DAG.
229 ilist<SDNode> AllNodes;
230
231 /// The AllocatorType for allocating SDNodes. We use
232 /// pool allocation with recycling.
233 using NodeAllocatorType = RecyclingAllocator<BumpPtrAllocator, SDNode,
234 sizeof(LargestSDNode),
235 alignof(MostAlignedSDNode)>;
236
237 /// Pool allocation for nodes.
238 NodeAllocatorType NodeAllocator;
239
240 /// This structure is used to memoize nodes, automatically performing
241 /// CSE with existing nodes when a duplicate is requested.
242 FoldingSet<SDNode> CSEMap;
243
244 /// Pool allocation for machine-opcode SDNode operands.
245 BumpPtrAllocator OperandAllocator;
246 ArrayRecycler<SDUse> OperandRecycler;
247
248 /// Pool allocation for misc. objects that are created once per SelectionDAG.
249 BumpPtrAllocator Allocator;
250
251 /// Tracks dbg_value information through SDISel.
252 SDDbgInfo *DbgInfo;
253
254 uint16_t NextPersistentId = 0;
255
256public:
257 /// Clients of various APIs that cause global effects on
258 /// the DAG can optionally implement this interface. This allows the clients
259 /// to handle the various sorts of updates that happen.
260 ///
261 /// A DAGUpdateListener automatically registers itself with DAG when it is
262 /// constructed, and removes itself when destroyed in RAII fashion.
263 struct DAGUpdateListener {
264 DAGUpdateListener *const Next;
265 SelectionDAG &DAG;
266
267 explicit DAGUpdateListener(SelectionDAG &D)
268 : Next(D.UpdateListeners), DAG(D) {
269 DAG.UpdateListeners = this;
270 }
271
272 virtual ~DAGUpdateListener() {
273 assert(DAG.UpdateListeners == this &&((DAG.UpdateListeners == this && "DAGUpdateListeners must be destroyed in LIFO order"
) ? static_cast<void> (0) : __assert_fail ("DAG.UpdateListeners == this && \"DAGUpdateListeners must be destroyed in LIFO order\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 274, __PRETTY_FUNCTION__))
274 "DAGUpdateListeners must be destroyed in LIFO order")((DAG.UpdateListeners == this && "DAGUpdateListeners must be destroyed in LIFO order"
) ? static_cast<void> (0) : __assert_fail ("DAG.UpdateListeners == this && \"DAGUpdateListeners must be destroyed in LIFO order\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 274, __PRETTY_FUNCTION__))
;
275 DAG.UpdateListeners = Next;
276 }
277
278 /// The node N that was deleted and, if E is not null, an
279 /// equivalent node E that replaced it.
280 virtual void NodeDeleted(SDNode *N, SDNode *E);
281
282 /// The node N that was updated.
283 virtual void NodeUpdated(SDNode *N);
284 };
285
286 struct DAGNodeDeletedListener : public DAGUpdateListener {
287 std::function<void(SDNode *, SDNode *)> Callback;
288
289 DAGNodeDeletedListener(SelectionDAG &DAG,
290 std::function<void(SDNode *, SDNode *)> Callback)
291 : DAGUpdateListener(DAG), Callback(std::move(Callback)) {}
292
293 void NodeDeleted(SDNode *N, SDNode *E) override { Callback(N, E); }
294 };
295
296 /// When true, additional steps are taken to
297 /// ensure that getConstant() and similar functions return DAG nodes that
298 /// have legal types. This is important after type legalization since
299 /// any illegally typed nodes generated after this point will not experience
300 /// type legalization.
301 bool NewNodesMustHaveLegalTypes = false;
302
303private:
304 /// DAGUpdateListener is a friend so it can manipulate the listener stack.
305 friend struct DAGUpdateListener;
306
307 /// Linked list of registered DAGUpdateListener instances.
308 /// This stack is maintained by DAGUpdateListener RAII.
309 DAGUpdateListener *UpdateListeners = nullptr;
310
311 /// Implementation of setSubgraphColor.
312 /// Return whether we had to truncate the search.
313 bool setSubgraphColorHelper(SDNode *N, const char *Color,
314 DenseSet<SDNode *> &visited,
315 int level, bool &printed);
316
317 template <typename SDNodeT, typename... ArgTypes>
318 SDNodeT *newSDNode(ArgTypes &&... Args) {
319 return new (NodeAllocator.template Allocate<SDNodeT>())
320 SDNodeT(std::forward<ArgTypes>(Args)...);
321 }
322
323 /// Build a synthetic SDNodeT with the given args and extract its subclass
324 /// data as an integer (e.g. for use in a folding set).
325 ///
326 /// The args to this function are the same as the args to SDNodeT's
327 /// constructor, except the second arg (assumed to be a const DebugLoc&) is
328 /// omitted.
329 template <typename SDNodeT, typename... ArgTypes>
330 static uint16_t getSyntheticNodeSubclassData(unsigned IROrder,
331 ArgTypes &&... Args) {
332 // The compiler can reduce this expression to a constant iff we pass an
333 // empty DebugLoc. Thankfully, the debug location doesn't have any bearing
334 // on the subclass data.
335 return SDNodeT(IROrder, DebugLoc(), std::forward<ArgTypes>(Args)...)
336 .getRawSubclassData();
337 }
338
339 template <typename SDNodeTy>
340 static uint16_t getSyntheticNodeSubclassData(unsigned Opc, unsigned Order,
341 SDVTList VTs, EVT MemoryVT,
342 MachineMemOperand *MMO) {
343 return SDNodeTy(Opc, Order, DebugLoc(), VTs, MemoryVT, MMO)
344 .getRawSubclassData();
345 }
346
347 void createOperands(SDNode *Node, ArrayRef<SDValue> Vals) {
348 assert(!Node->OperandList && "Node already has operands")((!Node->OperandList && "Node already has operands"
) ? static_cast<void> (0) : __assert_fail ("!Node->OperandList && \"Node already has operands\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 348, __PRETTY_FUNCTION__))
;
349 SDUse *Ops = OperandRecycler.allocate(
350 ArrayRecycler<SDUse>::Capacity::get(Vals.size()), OperandAllocator);
351
352 for (unsigned I = 0; I != Vals.size(); ++I) {
353 Ops[I].setUser(Node);
354 Ops[I].setInitial(Vals[I]);
355 }
356 Node->NumOperands = Vals.size();
357 Node->OperandList = Ops;
358 checkForCycles(Node);
359 }
360
361 void removeOperands(SDNode *Node) {
362 if (!Node->OperandList)
363 return;
364 OperandRecycler.deallocate(
365 ArrayRecycler<SDUse>::Capacity::get(Node->NumOperands),
366 Node->OperandList);
367 Node->NumOperands = 0;
368 Node->OperandList = nullptr;
369 }
370
371public:
372 explicit SelectionDAG(const TargetMachine &TM, CodeGenOpt::Level);
373 SelectionDAG(const SelectionDAG &) = delete;
374 SelectionDAG &operator=(const SelectionDAG &) = delete;
375 ~SelectionDAG();
376
377 /// Prepare this SelectionDAG to process code in the given MachineFunction.
378 void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
379 Pass *PassPtr);
380
381 /// Clear state and free memory necessary to make this
382 /// SelectionDAG ready to process a new block.
383 void clear();
384
385 MachineFunction &getMachineFunction() const { return *MF; }
386 const Pass *getPass() const { return SDAGISelPass; }
387
388 const DataLayout &getDataLayout() const { return MF->getDataLayout(); }
389 const TargetMachine &getTarget() const { return TM; }
390 const TargetSubtargetInfo &getSubtarget() const { return MF->getSubtarget(); }
391 const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
392 const SelectionDAGTargetInfo &getSelectionDAGInfo() const { return *TSI; }
393 LLVMContext *getContext() const {return Context; }
394 OptimizationRemarkEmitter &getORE() const { return *ORE; }
395
396 /// Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
397 void viewGraph(const std::string &Title);
398 void viewGraph();
399
400#ifndef NDEBUG
401 std::map<const SDNode *, std::string> NodeGraphAttrs;
402#endif
403
404 /// Clear all previously defined node graph attributes.
405 /// Intended to be used from a debugging tool (eg. gdb).
406 void clearGraphAttrs();
407
408 /// Set graph attributes for a node. (eg. "color=red".)
409 void setGraphAttrs(const SDNode *N, const char *Attrs);
410
411 /// Get graph attributes for a node. (eg. "color=red".)
412 /// Used from getNodeAttributes.
413 const std::string getGraphAttrs(const SDNode *N) const;
414
415 /// Convenience for setting node color attribute.
416 void setGraphColor(const SDNode *N, const char *Color);
417
418 /// Convenience for setting subgraph color attribute.
419 void setSubgraphColor(SDNode *N, const char *Color);
420
421 using allnodes_const_iterator = ilist<SDNode>::const_iterator;
422
423 allnodes_const_iterator allnodes_begin() const { return AllNodes.begin(); }
424 allnodes_const_iterator allnodes_end() const { return AllNodes.end(); }
425
426 using allnodes_iterator = ilist<SDNode>::iterator;
427
428 allnodes_iterator allnodes_begin() { return AllNodes.begin(); }
429 allnodes_iterator allnodes_end() { return AllNodes.end(); }
430
431 ilist<SDNode>::size_type allnodes_size() const {
432 return AllNodes.size();
433 }
434
435 iterator_range<allnodes_iterator> allnodes() {
436 return make_range(allnodes_begin(), allnodes_end());
437 }
438 iterator_range<allnodes_const_iterator> allnodes() const {
439 return make_range(allnodes_begin(), allnodes_end());
440 }
441
442 /// Return the root tag of the SelectionDAG.
443 const SDValue &getRoot() const { return Root; }
444
445 /// Return the token chain corresponding to the entry of the function.
446 SDValue getEntryNode() const {
447 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
448 }
449
450 /// Set the current root tag of the SelectionDAG.
451 ///
452 const SDValue &setRoot(SDValue N) {
453 assert((!N.getNode() || N.getValueType() == MVT::Other) &&(((!N.getNode() || N.getValueType() == MVT::Other) &&
"DAG root value is not a chain!") ? static_cast<void> (
0) : __assert_fail ("(!N.getNode() || N.getValueType() == MVT::Other) && \"DAG root value is not a chain!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 454, __PRETTY_FUNCTION__))
454 "DAG root value is not a chain!")(((!N.getNode() || N.getValueType() == MVT::Other) &&
"DAG root value is not a chain!") ? static_cast<void> (
0) : __assert_fail ("(!N.getNode() || N.getValueType() == MVT::Other) && \"DAG root value is not a chain!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 454, __PRETTY_FUNCTION__))
;
455 if (N.getNode())
456 checkForCycles(N.getNode(), this);
457 Root = N;
458 if (N.getNode())
459 checkForCycles(this);
460 return Root;
461 }
462
463 /// This iterates over the nodes in the SelectionDAG, folding
464 /// certain types of nodes together, or eliminating superfluous nodes. The
465 /// Level argument controls whether Combine is allowed to produce nodes and
466 /// types that are illegal on the target.
467 void Combine(CombineLevel Level, AliasAnalysis *AA,
468 CodeGenOpt::Level OptLevel);
469
470 /// This transforms the SelectionDAG into a SelectionDAG that
471 /// only uses types natively supported by the target.
472 /// Returns "true" if it made any changes.
473 ///
474 /// Note that this is an involved process that may invalidate pointers into
475 /// the graph.
476 bool LegalizeTypes();
477
478 /// This transforms the SelectionDAG into a SelectionDAG that is
479 /// compatible with the target instruction selector, as indicated by the
480 /// TargetLowering object.
481 ///
482 /// Note that this is an involved process that may invalidate pointers into
483 /// the graph.
484 void Legalize();
485
486 /// \brief Transforms a SelectionDAG node and any operands to it into a node
487 /// that is compatible with the target instruction selector, as indicated by
488 /// the TargetLowering object.
489 ///
490 /// \returns true if \c N is a valid, legal node after calling this.
491 ///
492 /// This essentially runs a single recursive walk of the \c Legalize process
493 /// over the given node (and its operands). This can be used to incrementally
494 /// legalize the DAG. All of the nodes which are directly replaced,
495 /// potentially including N, are added to the output parameter \c
496 /// UpdatedNodes so that the delta to the DAG can be understood by the
497 /// caller.
498 ///
499 /// When this returns false, N has been legalized in a way that make the
500 /// pointer passed in no longer valid. It may have even been deleted from the
501 /// DAG, and so it shouldn't be used further. When this returns true, the
502 /// N passed in is a legal node, and can be immediately processed as such.
503 /// This may still have done some work on the DAG, and will still populate
504 /// UpdatedNodes with any new nodes replacing those originally in the DAG.
505 bool LegalizeOp(SDNode *N, SmallSetVector<SDNode *, 16> &UpdatedNodes);
506
507 /// This transforms the SelectionDAG into a SelectionDAG
508 /// that only uses vector math operations supported by the target. This is
509 /// necessary as a separate step from Legalize because unrolling a vector
510 /// operation can introduce illegal types, which requires running
511 /// LegalizeTypes again.
512 ///
513 /// This returns true if it made any changes; in that case, LegalizeTypes
514 /// is called again before Legalize.
515 ///
516 /// Note that this is an involved process that may invalidate pointers into
517 /// the graph.
518 bool LegalizeVectors();
519
520 /// This method deletes all unreachable nodes in the SelectionDAG.
521 void RemoveDeadNodes();
522
523 /// Remove the specified node from the system. This node must
524 /// have no referrers.
525 void DeleteNode(SDNode *N);
526
527 /// Return an SDVTList that represents the list of values specified.
528 SDVTList getVTList(EVT VT);
529 SDVTList getVTList(EVT VT1, EVT VT2);
530 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
531 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
532 SDVTList getVTList(ArrayRef<EVT> VTs);
533
534 //===--------------------------------------------------------------------===//
535 // Node creation methods.
536
537 /// \brief Create a ConstantSDNode wrapping a constant value.
538 /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
539 ///
540 /// If only legal types can be produced, this does the necessary
541 /// transformations (e.g., if the vector element type is illegal).
542 /// @{
543 SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT,
544 bool isTarget = false, bool isOpaque = false);
545 SDValue getConstant(const APInt &Val, const SDLoc &DL, EVT VT,
546 bool isTarget = false, bool isOpaque = false);
547
548 SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false,
549 bool IsOpaque = false) {
550 return getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL,
551 VT, IsTarget, IsOpaque);
552 }
553
554 SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
555 bool isTarget = false, bool isOpaque = false);
556 SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
557 bool isTarget = false);
558 SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT,
559 bool isOpaque = false) {
560 return getConstant(Val, DL, VT, true, isOpaque);
561 }
562 SDValue getTargetConstant(const APInt &Val, const SDLoc &DL, EVT VT,
563 bool isOpaque = false) {
564 return getConstant(Val, DL, VT, true, isOpaque);
565 }
566 SDValue getTargetConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT,
567 bool isOpaque = false) {
568 return getConstant(Val, DL, VT, true, isOpaque);
569 }
570 /// @}
571
572 /// \brief Create a ConstantFPSDNode wrapping a constant value.
573 /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
574 ///
575 /// If only legal types can be produced, this does the necessary
576 /// transformations (e.g., if the vector element type is illegal).
577 /// The forms that take a double should only be used for simple constants
578 /// that can be exactly represented in VT. No checks are made.
579 /// @{
580 SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT,
581 bool isTarget = false);
582 SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
583 bool isTarget = false);
584 SDValue getConstantFP(const ConstantFP &CF, const SDLoc &DL, EVT VT,
585 bool isTarget = false);
586 SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
587 return getConstantFP(Val, DL, VT, true);
588 }
589 SDValue getTargetConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT) {
590 return getConstantFP(Val, DL, VT, true);
591 }
592 SDValue getTargetConstantFP(const ConstantFP &Val, const SDLoc &DL, EVT VT) {
593 return getConstantFP(Val, DL, VT, true);
594 }
595 /// @}
596
597 SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
598 int64_t offset = 0, bool isTargetGA = false,
599 unsigned char TargetFlags = 0);
600 SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT,
601 int64_t offset = 0,
602 unsigned char TargetFlags = 0) {
603 return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);
604 }
605 SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);
606 SDValue getTargetFrameIndex(int FI, EVT VT) {
607 return getFrameIndex(FI, VT, true);
608 }
609 SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false,
610 unsigned char TargetFlags = 0);
611 SDValue getTargetJumpTable(int JTI, EVT VT, unsigned char TargetFlags = 0) {
612 return getJumpTable(JTI, VT, true, TargetFlags);
613 }
614 SDValue getConstantPool(const Constant *C, EVT VT,
615 unsigned Align = 0, int Offs = 0, bool isT=false,
616 unsigned char TargetFlags = 0);
617 SDValue getTargetConstantPool(const Constant *C, EVT VT,
618 unsigned Align = 0, int Offset = 0,
619 unsigned char TargetFlags = 0) {
620 return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
621 }
622 SDValue getConstantPool(MachineConstantPoolValue *C, EVT VT,
623 unsigned Align = 0, int Offs = 0, bool isT=false,
624 unsigned char TargetFlags = 0);
625 SDValue getTargetConstantPool(MachineConstantPoolValue *C,
626 EVT VT, unsigned Align = 0,
627 int Offset = 0, unsigned char TargetFlags=0) {
628 return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
629 }
630 SDValue getTargetIndex(int Index, EVT VT, int64_t Offset = 0,
631 unsigned char TargetFlags = 0);
632 // When generating a branch to a BB, we don't in general know enough
633 // to provide debug info for the BB at that time, so keep this one around.
634 SDValue getBasicBlock(MachineBasicBlock *MBB);
635 SDValue getBasicBlock(MachineBasicBlock *MBB, SDLoc dl);
636 SDValue getExternalSymbol(const char *Sym, EVT VT);
637 SDValue getExternalSymbol(const char *Sym, const SDLoc &dl, EVT VT);
638 SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
639 unsigned char TargetFlags = 0);
640 SDValue getMCSymbol(MCSymbol *Sym, EVT VT);
641
642 SDValue getValueType(EVT);
643 SDValue getRegister(unsigned Reg, EVT VT);
644 SDValue getRegisterMask(const uint32_t *RegMask);
645 SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label);
646 SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root,
647 MCSymbol *Label);
648 SDValue getBlockAddress(const BlockAddress *BA, EVT VT,
649 int64_t Offset = 0, bool isTarget = false,
650 unsigned char TargetFlags = 0);
651 SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT,
652 int64_t Offset = 0,
653 unsigned char TargetFlags = 0) {
654 return getBlockAddress(BA, VT, Offset, true, TargetFlags);
655 }
656
657 SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
658 SDValue N) {
659 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
660 getRegister(Reg, N.getValueType()), N);
661 }
662
663 // This version of the getCopyToReg method takes an extra operand, which
664 // indicates that there is potentially an incoming glue value (if Glue is not
665 // null) and that there should be a glue result.
666 SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N,
667 SDValue Glue) {
668 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
669 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
32
Calling 'SDValue::getValueType'
670 return getNode(ISD::CopyToReg, dl, VTs,
671 makeArrayRef(Ops, Glue.getNode() ? 4 : 3));
672 }
673
674 // Similar to last getCopyToReg() except parameter Reg is a SDValue
675 SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, SDValue Reg, SDValue N,
676 SDValue Glue) {
677 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
678 SDValue Ops[] = { Chain, Reg, N, Glue };
679 return getNode(ISD::CopyToReg, dl, VTs,
680 makeArrayRef(Ops, Glue.getNode() ? 4 : 3));
681 }
682
683 SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) {
684 SDVTList VTs = getVTList(VT, MVT::Other);
685 SDValue Ops[] = { Chain, getRegister(Reg, VT) };
686 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
687 }
688
689 // This version of the getCopyFromReg method takes an extra operand, which
690 // indicates that there is potentially an incoming glue value (if Glue is not
691 // null) and that there should be a glue result.
692 SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT,
693 SDValue Glue) {
694 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
695 SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
696 return getNode(ISD::CopyFromReg, dl, VTs,
697 makeArrayRef(Ops, Glue.getNode() ? 3 : 2));
698 }
699
700 SDValue getCondCode(ISD::CondCode Cond);
701
702 /// Return an ISD::VECTOR_SHUFFLE node. The number of elements in VT,
703 /// which must be a vector type, must match the number of mask elements
704 /// NumElts. An integer mask element equal to -1 is treated as undefined.
705 SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2,
706 ArrayRef<int> Mask);
707
708 /// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
709 /// which must be a vector type, must match the number of operands in Ops.
710 /// The operands must have the same type as (or, for integers, a type wider
711 /// than) VT's element type.
712 SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDValue> Ops) {
713 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
714 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
715 }
716
717 /// Return an ISD::BUILD_VECTOR node. The number of elements in VT,
718 /// which must be a vector type, must match the number of operands in Ops.
719 /// The operands must have the same type as (or, for integers, a type wider
720 /// than) VT's element type.
721 SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef<SDUse> Ops) {
722 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
723 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
724 }
725
726 /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all
727 /// elements. VT must be a vector type. Op's type must be the same as (or,
728 /// for integers, a type wider than) VT's element type.
729 SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) {
730 // VerifySDNode (via InsertNode) checks BUILD_VECTOR later.
731 if (Op.getOpcode() == ISD::UNDEF) {
732 assert((VT.getVectorElementType() == Op.getValueType() ||(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger
() && VT.getVectorElementType().bitsLE(Op.getValueType
()))) && "A splatted value must have a width equal or (for integers) "
"greater than the vector element type!") ? static_cast<void
> (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 736, __PRETTY_FUNCTION__))
733 (VT.isInteger() &&(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger
() && VT.getVectorElementType().bitsLE(Op.getValueType
()))) && "A splatted value must have a width equal or (for integers) "
"greater than the vector element type!") ? static_cast<void
> (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 736, __PRETTY_FUNCTION__))
734 VT.getVectorElementType().bitsLE(Op.getValueType()))) &&(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger
() && VT.getVectorElementType().bitsLE(Op.getValueType
()))) && "A splatted value must have a width equal or (for integers) "
"greater than the vector element type!") ? static_cast<void
> (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 736, __PRETTY_FUNCTION__))
735 "A splatted value must have a width equal or (for integers) "(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger
() && VT.getVectorElementType().bitsLE(Op.getValueType
()))) && "A splatted value must have a width equal or (for integers) "
"greater than the vector element type!") ? static_cast<void
> (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 736, __PRETTY_FUNCTION__))
736 "greater than the vector element type!")(((VT.getVectorElementType() == Op.getValueType() || (VT.isInteger
() && VT.getVectorElementType().bitsLE(Op.getValueType
()))) && "A splatted value must have a width equal or (for integers) "
"greater than the vector element type!") ? static_cast<void
> (0) : __assert_fail ("(VT.getVectorElementType() == Op.getValueType() || (VT.isInteger() && VT.getVectorElementType().bitsLE(Op.getValueType()))) && \"A splatted value must have a width equal or (for integers) \" \"greater than the vector element type!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 736, __PRETTY_FUNCTION__))
;
737 return getNode(ISD::UNDEF, SDLoc(), VT);
738 }
739
740 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Op);
741 return getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
742 }
743
744 /// \brief Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to
745 /// the shuffle node in input but with swapped operands.
746 ///
747 /// Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
748 SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV);
749
750 /// Convert Op, which must be of float type, to the
751 /// float type VT, by either extending or rounding (by truncation).
752 SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT);
753
754 /// Convert Op, which must be of integer type, to the
755 /// integer type VT, by either any-extending or truncating it.
756 SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
757
758 /// Convert Op, which must be of integer type, to the
759 /// integer type VT, by either sign-extending or truncating it.
760 SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
761
762 /// Convert Op, which must be of integer type, to the
763 /// integer type VT, by either zero-extending or truncating it.
764 SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
765
766 /// Return the expression required to zero extend the Op
767 /// value assuming it was the smaller SrcTy value.
768 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);
769
770 /// Return an operation which will any-extend the low lanes of the operand
771 /// into the specified vector type. For example,
772 /// this can convert a v16i8 into a v4i32 by any-extending the low four
773 /// lanes of the operand from i8 to i32.
774 SDValue getAnyExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
775
776 /// Return an operation which will sign extend the low lanes of the operand
777 /// into the specified vector type. For example,
778 /// this can convert a v16i8 into a v4i32 by sign extending the low four
779 /// lanes of the operand from i8 to i32.
780 SDValue getSignExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
781
782 /// Return an operation which will zero extend the low lanes of the operand
783 /// into the specified vector type. For example,
784 /// this can convert a v16i8 into a v4i32 by zero extending the low four
785 /// lanes of the operand from i8 to i32.
786 SDValue getZeroExtendVectorInReg(SDValue Op, const SDLoc &DL, EVT VT);
787
788 /// Convert Op, which must be of integer type, to the integer type VT,
789 /// by using an extension appropriate for the target's
790 /// BooleanContent for type OpVT or truncating it.
791 SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT);
792
793 /// Create a bitwise NOT operation as (XOR Val, -1).
794 SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
795
796 /// \brief Create a logical NOT operation as (XOR Val, BooleanOne).
797 SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT);
798
799 /// Return a new CALLSEQ_START node, that starts new call frame, in which
800 /// InSize bytes are set up inside CALLSEQ_START..CALLSEQ_END sequence and
801 /// OutSize specifies part of the frame set up prior to the sequence.
802 SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize,
803 const SDLoc &DL) {
804 SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
805 SDValue Ops[] = { Chain,
806 getIntPtrConstant(InSize, DL, true),
807 getIntPtrConstant(OutSize, DL, true) };
808 return getNode(ISD::CALLSEQ_START, DL, VTs, Ops);
809 }
810
811 /// Return a new CALLSEQ_END node, which always must have a
812 /// glue result (to ensure it's not CSE'd).
813 /// CALLSEQ_END does not have a useful SDLoc.
814 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
815 SDValue InGlue, const SDLoc &DL) {
816 SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);
817 SmallVector<SDValue, 4> Ops;
818 Ops.push_back(Chain);
819 Ops.push_back(Op1);
820 Ops.push_back(Op2);
821 if (InGlue.getNode())
822 Ops.push_back(InGlue);
823 return getNode(ISD::CALLSEQ_END, DL, NodeTys, Ops);
824 }
825
826 /// Return true if the result of this operation is always undefined.
827 bool isUndef(unsigned Opcode, ArrayRef<SDValue> Ops);
828
829 /// Return an UNDEF node. UNDEF does not have a useful SDLoc.
830 SDValue getUNDEF(EVT VT) {
831 return getNode(ISD::UNDEF, SDLoc(), VT);
832 }
833
834 /// Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
835 SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
836 return getNode(ISD::GLOBAL_OFFSET_TABLE, SDLoc(), VT);
837 }
838
839 /// Gets or creates the specified node.
840 ///
841 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
842 ArrayRef<SDUse> Ops);
843 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
844 ArrayRef<SDValue> Ops, const SDNodeFlags Flags = SDNodeFlags());
845 SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef<EVT> ResultTys,
846 ArrayRef<SDValue> Ops);
847 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
848 ArrayRef<SDValue> Ops);
849
850 // Specialize based on number of operands.
851 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
852 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N,
853 const SDNodeFlags Flags = SDNodeFlags());
854 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
855 SDValue N2, const SDNodeFlags Flags = SDNodeFlags());
856 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
857 SDValue N2, SDValue N3);
858 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
859 SDValue N2, SDValue N3, SDValue N4);
860 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
861 SDValue N2, SDValue N3, SDValue N4, SDValue N5);
862
863 // Specialize again based on number of operands for nodes with a VTList
864 // rather than a single VT.
865 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs);
866 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N);
867 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
868 SDValue N2);
869 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
870 SDValue N2, SDValue N3);
871 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
872 SDValue N2, SDValue N3, SDValue N4);
873 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
874 SDValue N2, SDValue N3, SDValue N4, SDValue N5);
875
876 /// Compute a TokenFactor to force all the incoming stack arguments to be
877 /// loaded from the stack. This is used in tail call lowering to protect
878 /// stack arguments from being clobbered.
879 SDValue getStackArgumentTokenFactor(SDValue Chain);
880
881 SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
882 SDValue Size, unsigned Align, bool isVol, bool AlwaysInline,
883 bool isTailCall, MachinePointerInfo DstPtrInfo,
884 MachinePointerInfo SrcPtrInfo);
885
886 SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
887 SDValue Size, unsigned Align, bool isVol, bool isTailCall,
888 MachinePointerInfo DstPtrInfo,
889 MachinePointerInfo SrcPtrInfo);
890
891 SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
892 SDValue Size, unsigned Align, bool isVol, bool isTailCall,
893 MachinePointerInfo DstPtrInfo);
894
895 /// Helper function to make it easier to build SetCC's if you just
896 /// have an ISD::CondCode instead of an SDValue.
897 ///
898 SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS,
899 ISD::CondCode Cond) {
900 assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() &&((LHS.getValueType().isVector() == RHS.getValueType().isVector
() && "Cannot compare scalars to vectors") ? static_cast
<void> (0) : __assert_fail ("LHS.getValueType().isVector() == RHS.getValueType().isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 901, __PRETTY_FUNCTION__))
901 "Cannot compare scalars to vectors")((LHS.getValueType().isVector() == RHS.getValueType().isVector
() && "Cannot compare scalars to vectors") ? static_cast
<void> (0) : __assert_fail ("LHS.getValueType().isVector() == RHS.getValueType().isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 901, __PRETTY_FUNCTION__))
;
902 assert(LHS.getValueType().isVector() == VT.isVector() &&((LHS.getValueType().isVector() == VT.isVector() && "Cannot compare scalars to vectors"
) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType().isVector() == VT.isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 903, __PRETTY_FUNCTION__))
903 "Cannot compare scalars to vectors")((LHS.getValueType().isVector() == VT.isVector() && "Cannot compare scalars to vectors"
) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType().isVector() == VT.isVector() && \"Cannot compare scalars to vectors\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 903, __PRETTY_FUNCTION__))
;
904 assert(Cond != ISD::SETCC_INVALID &&((Cond != ISD::SETCC_INVALID && "Cannot create a setCC of an invalid node."
) ? static_cast<void> (0) : __assert_fail ("Cond != ISD::SETCC_INVALID && \"Cannot create a setCC of an invalid node.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 905, __PRETTY_FUNCTION__))
905 "Cannot create a setCC of an invalid node.")((Cond != ISD::SETCC_INVALID && "Cannot create a setCC of an invalid node."
) ? static_cast<void> (0) : __assert_fail ("Cond != ISD::SETCC_INVALID && \"Cannot create a setCC of an invalid node.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 905, __PRETTY_FUNCTION__))
;
906 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
907 }
908
909 /// Helper function to make it easier to build Select's if you just
910 /// have operands and don't want to check for vector.
911 SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS,
912 SDValue RHS) {
913 assert(LHS.getValueType() == RHS.getValueType() &&((LHS.getValueType() == RHS.getValueType() && "Cannot use select on differing types"
) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Cannot use select on differing types\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 914, __PRETTY_FUNCTION__))
914 "Cannot use select on differing types")((LHS.getValueType() == RHS.getValueType() && "Cannot use select on differing types"
) ? static_cast<void> (0) : __assert_fail ("LHS.getValueType() == RHS.getValueType() && \"Cannot use select on differing types\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 914, __PRETTY_FUNCTION__))
;
915 assert(VT.isVector() == LHS.getValueType().isVector() &&((VT.isVector() == LHS.getValueType().isVector() && "Cannot mix vectors and scalars"
) ? static_cast<void> (0) : __assert_fail ("VT.isVector() == LHS.getValueType().isVector() && \"Cannot mix vectors and scalars\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 916, __PRETTY_FUNCTION__))
916 "Cannot mix vectors and scalars")((VT.isVector() == LHS.getValueType().isVector() && "Cannot mix vectors and scalars"
) ? static_cast<void> (0) : __assert_fail ("VT.isVector() == LHS.getValueType().isVector() && \"Cannot mix vectors and scalars\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 916, __PRETTY_FUNCTION__))
;
917 return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
918 Cond, LHS, RHS);
919 }
920
921 /// Helper function to make it easier to build SelectCC's if you
922 /// just have an ISD::CondCode instead of an SDValue.
923 ///
924 SDValue getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True,
925 SDValue False, ISD::CondCode Cond) {
926 return getNode(ISD::SELECT_CC, DL, True.getValueType(),
927 LHS, RHS, True, False, getCondCode(Cond));
928 }
929
930 /// VAArg produces a result and token chain, and takes a pointer
931 /// and a source value as input.
932 SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
933 SDValue SV, unsigned Align);
934
935 /// Gets a node for an atomic cmpxchg op. There are two
936 /// valid Opcodes. ISD::ATOMIC_CMO_SWAP produces the value loaded and a
937 /// chain result. ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS produces the value loaded,
938 /// a success flag (initially i1), and a chain.
939 SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
940 SDVTList VTs, SDValue Chain, SDValue Ptr,
941 SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo,
942 unsigned Alignment, AtomicOrdering SuccessOrdering,
943 AtomicOrdering FailureOrdering,
944 SyncScope::ID SSID);
945 SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT,
946 SDVTList VTs, SDValue Chain, SDValue Ptr,
947 SDValue Cmp, SDValue Swp, MachineMemOperand *MMO);
948
949 /// Gets a node for an atomic op, produces result (if relevant)
950 /// and chain and takes 2 operands.
951 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
952 SDValue Ptr, SDValue Val, const Value *PtrVal,
953 unsigned Alignment, AtomicOrdering Ordering,
954 SyncScope::ID SSID);
955 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain,
956 SDValue Ptr, SDValue Val, MachineMemOperand *MMO);
957
958 /// Gets a node for an atomic op, produces result and chain and
959 /// takes 1 operand.
960 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, EVT VT,
961 SDValue Chain, SDValue Ptr, MachineMemOperand *MMO);
962
963 /// Gets a node for an atomic op, produces result and chain and takes N
964 /// operands.
965 SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT,
966 SDVTList VTList, ArrayRef<SDValue> Ops,
967 MachineMemOperand *MMO);
968
969 /// Creates a MemIntrinsicNode that may produce a
970 /// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
971 /// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
972 /// less than FIRST_TARGET_MEMORY_OPCODE.
973 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
974 ArrayRef<SDValue> Ops, EVT MemVT,
975 MachinePointerInfo PtrInfo, unsigned Align = 0,
976 bool Vol = false, bool ReadMem = true,
977 bool WriteMem = true, unsigned Size = 0);
978
979 SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
980 ArrayRef<SDValue> Ops, EVT MemVT,
981 MachineMemOperand *MMO);
982
983 /// Create a MERGE_VALUES node from the given operands.
984 SDValue getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl);
985
986 /// Loads are not normal binary operators: their result type is not
987 /// determined by their operands, and they produce a value AND a token chain.
988 ///
989 /// This function will set the MOLoad flag on MMOFlags, but you can set it if
990 /// you want. The MOStore flag must not be set.
991 SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
992 MachinePointerInfo PtrInfo, unsigned Alignment = 0,
993 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
994 const AAMDNodes &AAInfo = AAMDNodes(),
995 const MDNode *Ranges = nullptr);
996 SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
997 MachineMemOperand *MMO);
998 SDValue
999 getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain,
1000 SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT,
1001 unsigned Alignment = 0,
1002 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
1003 const AAMDNodes &AAInfo = AAMDNodes());
1004 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
1005 SDValue Chain, SDValue Ptr, EVT MemVT,
1006 MachineMemOperand *MMO);
1007 SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base,
1008 SDValue Offset, ISD::MemIndexedMode AM);
1009 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1010 const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
1011 MachinePointerInfo PtrInfo, EVT MemVT, unsigned Alignment = 0,
1012 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
1013 const AAMDNodes &AAInfo = AAMDNodes(),
1014 const MDNode *Ranges = nullptr);
1015 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
1016 const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset,
1017 EVT MemVT, MachineMemOperand *MMO);
1018
1019 /// Helper function to build ISD::STORE nodes.
1020 ///
1021 /// This function will set the MOStore flag on MMOFlags, but you can set it if
1022 /// you want. The MOLoad and MOInvariant flags must not be set.
1023 SDValue
1024 getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
1025 MachinePointerInfo PtrInfo, unsigned Alignment = 0,
1026 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
1027 const AAMDNodes &AAInfo = AAMDNodes());
1028 SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
1029 MachineMemOperand *MMO);
1030 SDValue
1031 getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
1032 MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment = 0,
1033 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
1034 const AAMDNodes &AAInfo = AAMDNodes());
1035 SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
1036 SDValue Ptr, EVT TVT, MachineMemOperand *MMO);
1037 SDValue getIndexedStore(SDValue OrigStoe, const SDLoc &dl, SDValue Base,
1038 SDValue Offset, ISD::MemIndexedMode AM);
1039
1040 /// Returns sum of the base pointer and offset.
1041 SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, const SDLoc &DL);
1042
1043 SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr,
1044 SDValue Mask, SDValue Src0, EVT MemVT,
1045 MachineMemOperand *MMO, ISD::LoadExtType,
1046 bool IsExpanding = false);
1047 SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val,
1048 SDValue Ptr, SDValue Mask, EVT MemVT,
1049 MachineMemOperand *MMO, bool IsTruncating = false,
1050 bool IsCompressing = false);
1051 SDValue getMaskedGather(SDVTList VTs, EVT VT, const SDLoc &dl,
1052 ArrayRef<SDValue> Ops, MachineMemOperand *MMO);
1053 SDValue getMaskedScatter(SDVTList VTs, EVT VT, const SDLoc &dl,
1054 ArrayRef<SDValue> Ops, MachineMemOperand *MMO);
1055
1056 /// Return (create a new or find existing) a target-specific node.
1057 /// TargetMemSDNode should be derived class from MemSDNode.
1058 template <class TargetMemSDNode>
1059 SDValue getTargetMemSDNode(SDVTList VTs, ArrayRef<SDValue> Ops,
1060 const SDLoc &dl, EVT MemVT,
1061 MachineMemOperand *MMO);
1062
1063 /// Construct a node to track a Value* through the backend.
1064 SDValue getSrcValue(const Value *v);
1065
1066 /// Return an MDNodeSDNode which holds an MDNode.
1067 SDValue getMDNode(const MDNode *MD);
1068
1069 /// Return a bitcast using the SDLoc of the value operand, and casting to the
1070 /// provided type. Use getNode to set a custom SDLoc.
1071 SDValue getBitcast(EVT VT, SDValue V);
1072
1073 /// Return an AddrSpaceCastSDNode.
1074 SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS,
1075 unsigned DestAS);
1076
1077 /// Return the specified value casted to
1078 /// the target's desired shift amount type.
1079 SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
1080
1081 /// Expand the specified \c ISD::VAARG node as the Legalize pass would.
1082 SDValue expandVAArg(SDNode *Node);
1083
1084 /// Expand the specified \c ISD::VACOPY node as the Legalize pass would.
1085 SDValue expandVACopy(SDNode *Node);
1086
1087 /// *Mutate* the specified node in-place to have the
1088 /// specified operands. If the resultant node already exists in the DAG,
1089 /// this does not modify the specified node, instead it returns the node that
1090 /// already exists. If the resultant node does not exist in the DAG, the
1091 /// input node is returned. As a degenerate case, if you specify the same
1092 /// input operands as the node already has, the input node is returned.
1093 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op);
1094 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
1095 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1096 SDValue Op3);
1097 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1098 SDValue Op3, SDValue Op4);
1099 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
1100 SDValue Op3, SDValue Op4, SDValue Op5);
1101 SDNode *UpdateNodeOperands(SDNode *N, ArrayRef<SDValue> Ops);
1102
1103 /// These are used for target selectors to *mutate* the
1104 /// specified node to have the specified return type, Target opcode, and
1105 /// operands. Note that target opcodes are stored as
1106 /// ~TargetOpcode in the node opcode field. The resultant node is returned.
1107 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT);
1108 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1);
1109 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
1110 SDValue Op1, SDValue Op2);
1111 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
1112 SDValue Op1, SDValue Op2, SDValue Op3);
1113 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
1114 ArrayRef<SDValue> Ops);
1115 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
1116 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1117 EVT VT2, ArrayRef<SDValue> Ops);
1118 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1119 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
1120 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1121 EVT VT2, SDValue Op1);
1122 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1123 EVT VT2, SDValue Op1, SDValue Op2);
1124 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
1125 ArrayRef<SDValue> Ops);
1126
1127 /// This *mutates* the specified node to have the specified
1128 /// return type, opcode, and operands.
1129 SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
1130 ArrayRef<SDValue> Ops);
1131
1132 /// Mutate the specified strict FP node to its non-strict equivalent,
1133 /// unlinking the node from its chain and dropping the metadata arguments.
1134 /// The node must be a strict FP node.
1135 SDNode *mutateStrictFPToFP(SDNode *Node);
1136
1137 /// These are used for target selectors to create a new node
1138 /// with specified return type(s), MachineInstr opcode, and operands.
1139 ///
1140 /// Note that getMachineNode returns the resultant node. If there is already
1141 /// a node of the specified opcode and operands, it returns that node instead
1142 /// of the current one.
1143 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT);
1144 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
1145 SDValue Op1);
1146 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
1147 SDValue Op1, SDValue Op2);
1148 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
1149 SDValue Op1, SDValue Op2, SDValue Op3);
1150 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT,
1151 ArrayRef<SDValue> Ops);
1152 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1153 EVT VT2, SDValue Op1, SDValue Op2);
1154 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1155 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3);
1156 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1157 EVT VT2, ArrayRef<SDValue> Ops);
1158 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1159 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2);
1160 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1161 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2,
1162 SDValue Op3);
1163 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1164 EVT VT2, EVT VT3, ArrayRef<SDValue> Ops);
1165 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl,
1166 ArrayRef<EVT> ResultTys, ArrayRef<SDValue> Ops);
1167 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, SDVTList VTs,
1168 ArrayRef<SDValue> Ops);
1169
1170 /// A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
1171 SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
1172 SDValue Operand);
1173
1174 /// A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
1175 SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
1176 SDValue Operand, SDValue Subreg);
1177
1178 /// Get the specified node if it's already available, or else return NULL.
1179 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs, ArrayRef<SDValue> Ops,
1180 const SDNodeFlags Flags = SDNodeFlags());
1181
1182 /// Creates a SDDbgValue node.
1183 SDDbgValue *getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N,
1184 unsigned R, bool IsIndirect, const DebugLoc &DL,
1185 unsigned O);
1186
1187 /// Creates a constant SDDbgValue node.
1188 SDDbgValue *getConstantDbgValue(DIVariable *Var, DIExpression *Expr,
1189 const Value *C, const DebugLoc &DL,
1190 unsigned O);
1191
1192 /// Creates a FrameIndex SDDbgValue node.
1193 SDDbgValue *getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr,
1194 unsigned FI, const DebugLoc &DL,
1195 unsigned O);
1196
1197 /// Transfer debug values from one node to another, while optionally
1198 /// generating fragment expressions for split-up values.
1199 void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits = 0,
1200 unsigned SizeInBits = 0);
1201
1202 /// Remove the specified node from the system. If any of its
1203 /// operands then becomes dead, remove them as well. Inform UpdateListener
1204 /// for each node deleted.
1205 void RemoveDeadNode(SDNode *N);
1206
1207 /// This method deletes the unreachable nodes in the
1208 /// given list, and any nodes that become unreachable as a result.
1209 void RemoveDeadNodes(SmallVectorImpl<SDNode *> &DeadNodes);
1210
1211 /// Modify anything using 'From' to use 'To' instead.
1212 /// This can cause recursive merging of nodes in the DAG. Use the first
1213 /// version if 'From' is known to have a single result, use the second
1214 /// if you have two nodes with identical results (or if 'To' has a superset
1215 /// of the results of 'From'), use the third otherwise.
1216 ///
1217 /// These methods all take an optional UpdateListener, which (if not null) is
1218 /// informed about nodes that are deleted and modified due to recursive
1219 /// changes in the dag.
1220 ///
1221 /// These functions only replace all existing uses. It's possible that as
1222 /// these replacements are being performed, CSE may cause the From node
1223 /// to be given new uses. These new uses of From are left in place, and
1224 /// not automatically transferred to To.
1225 ///
1226 void ReplaceAllUsesWith(SDValue From, SDValue Op);
1227 void ReplaceAllUsesWith(SDNode *From, SDNode *To);
1228 void ReplaceAllUsesWith(SDNode *From, const SDValue *To);
1229
1230 /// Replace any uses of From with To, leaving
1231 /// uses of other values produced by From.Val alone.
1232 void ReplaceAllUsesOfValueWith(SDValue From, SDValue To);
1233
1234 /// Like ReplaceAllUsesOfValueWith, but for multiple values at once.
1235 /// This correctly handles the case where
1236 /// there is an overlap between the From values and the To values.
1237 void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To,
1238 unsigned Num);
1239
1240 /// If an existing load has uses of its chain, create a token factor node with
1241 /// that chain and the new memory node's chain and update users of the old
1242 /// chain to the token factor. This ensures that the new memory node will have
1243 /// the same relative memory dependency position as the old load. Returns the
1244 /// new merged load chain.
1245 SDValue makeEquivalentMemoryOrdering(LoadSDNode *Old, SDValue New);
1246
1247 /// Topological-sort the AllNodes list and a
1248 /// assign a unique node id for each node in the DAG based on their
1249 /// topological order. Returns the number of nodes.
1250 unsigned AssignTopologicalOrder();
1251
1252 /// Move node N in the AllNodes list to be immediately
1253 /// before the given iterator Position. This may be used to update the
1254 /// topological ordering when the list of nodes is modified.
1255 void RepositionNode(allnodes_iterator Position, SDNode *N) {
1256 AllNodes.insert(Position, AllNodes.remove(N));
1257 }
1258
1259 /// Returns an APFloat semantics tag appropriate for the given type. If VT is
1260 /// a vector type, the element semantics are returned.
1261 static const fltSemantics &EVTToAPFloatSemantics(EVT VT) {
1262 switch (VT.getScalarType().getSimpleVT().SimpleTy) {
1263 default: llvm_unreachable("Unknown FP format")::llvm::llvm_unreachable_internal("Unknown FP format", "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAG.h"
, 1263)
;
1264 case MVT::f16: return APFloat::IEEEhalf();
1265 case MVT::f32: return APFloat::IEEEsingle();
1266 case MVT::f64: return APFloat::IEEEdouble();
1267 case MVT::f80: return APFloat::x87DoubleExtended();
1268 case MVT::f128: return APFloat::IEEEquad();
1269 case MVT::ppcf128: return APFloat::PPCDoubleDouble();
1270 }
1271 }
1272
1273 /// Add a dbg_value SDNode. If SD is non-null that means the
1274 /// value is produced by SD.
1275 void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter);
1276
1277 /// Get the debug values which reference the given SDNode.
1278 ArrayRef<SDDbgValue*> GetDbgValues(const SDNode* SD) {
1279 return DbgInfo->getSDDbgValues(SD);
1280 }
1281
1282private:
1283 /// Transfer SDDbgValues. Called via ReplaceAllUses{OfValue}?With
1284 void TransferDbgValues(SDValue From, SDValue To);
1285
1286public:
1287 /// Return true if there are any SDDbgValue nodes associated
1288 /// with this SelectionDAG.
1289 bool hasDebugValues() const { return !DbgInfo->empty(); }
1290
1291 SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
1292 SDDbgInfo::DbgIterator DbgEnd() { return DbgInfo->DbgEnd(); }
1293
1294 SDDbgInfo::DbgIterator ByvalParmDbgBegin() {
1295 return DbgInfo->ByvalParmDbgBegin();
1296 }
1297
1298 SDDbgInfo::DbgIterator ByvalParmDbgEnd() {
1299 return DbgInfo->ByvalParmDbgEnd();
1300 }
1301
1302 /// To be invoked on an SDNode that is slated to be erased. This
1303 /// function mirrors \c llvm::salvageDebugInfo.
1304 void salvageDebugInfo(SDNode &N);
1305
1306 void dump() const;
1307
1308 /// Create a stack temporary, suitable for holding the specified value type.
1309 /// If minAlign is specified, the slot size will have at least that alignment.
1310 SDValue CreateStackTemporary(EVT VT, unsigned minAlign = 1);
1311
1312 /// Create a stack temporary suitable for holding either of the specified
1313 /// value types.
1314 SDValue CreateStackTemporary(EVT VT1, EVT VT2);
1315
1316 SDValue FoldSymbolOffset(unsigned Opcode, EVT VT,
1317 const GlobalAddressSDNode *GA,
1318 const SDNode *N2);
1319
1320 SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
1321 SDNode *Cst1, SDNode *Cst2);
1322
1323 SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
1324 const ConstantSDNode *Cst1,
1325 const ConstantSDNode *Cst2);
1326
1327 SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
1328 ArrayRef<SDValue> Ops,
1329 const SDNodeFlags Flags = SDNodeFlags());
1330
1331 /// Constant fold a setcc to true or false.
1332 SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond,
1333 const SDLoc &dl);
1334
1335 /// See if the specified operand can be simplified with the knowledge that only
1336 /// the bits specified by Mask are used. If so, return the simpler operand,
1337 /// otherwise return a null SDValue.
1338 ///
1339 /// (This exists alongside SimplifyDemandedBits because GetDemandedBits can
1340 /// simplify nodes with multiple uses more aggressively.)
1341 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
1342
1343 /// Return true if the sign bit of Op is known to be zero.
1344 /// We use this predicate to simplify operations downstream.
1345 bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;
1346
1347 /// Return true if 'Op & Mask' is known to be zero. We
1348 /// use this predicate to simplify operations downstream. Op and Mask are
1349 /// known to be the same type.
1350 bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
1351 const;
1352
1353 /// Determine which bits of Op are known to be either zero or one and return
1354 /// them in Known. For vectors, the known bits are those that are shared by
1355 /// every vector element.
1356 /// Targets can implement the computeKnownBitsForTargetNode method in the
1357 /// TargetLowering class to allow target nodes to be understood.
1358 void computeKnownBits(SDValue Op, KnownBits &Known, unsigned Depth = 0) const;
1359
1360 /// Determine which bits of Op are known to be either zero or one and return
1361 /// them in Known. The DemandedElts argument allows us to only collect the
1362 /// known bits that are shared by the requested vector elements.
1363 /// Targets can implement the computeKnownBitsForTargetNode method in the
1364 /// TargetLowering class to allow target nodes to be understood.
1365 void computeKnownBits(SDValue Op, KnownBits &Known, const APInt &DemandedElts,
1366 unsigned Depth = 0) const;
1367
1368 /// Used to represent the possible overflow behavior of an operation.
1369 /// Never: the operation cannot overflow.
1370 /// Always: the operation will always overflow.
1371 /// Sometime: the operation may or may not overflow.
1372 enum OverflowKind {
1373 OFK_Never,
1374 OFK_Sometime,
1375 OFK_Always,
1376 };
1377
1378 /// Determine if the result of the addition of 2 node can overflow.
1379 OverflowKind computeOverflowKind(SDValue N0, SDValue N1) const;
1380
1381 /// Test if the given value is known to have exactly one bit set. This differs
1382 /// from computeKnownBits in that it doesn't necessarily determine which bit
1383 /// is set.
1384 bool isKnownToBeAPowerOfTwo(SDValue Val) const;
1385
1386 /// Return the number of times the sign bit of the register is replicated into
1387 /// the other bits. We know that at least 1 bit is always equal to the sign
1388 /// bit (itself), but other cases can give us information. For example,
1389 /// immediately after an "SRA X, 2", we know that the top 3 bits are all equal
1390 /// to each other, so we return 3. Targets can implement the
1391 /// ComputeNumSignBitsForTarget method in the TargetLowering class to allow
1392 /// target nodes to be understood.
1393 unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;
1394
1395 /// Return the number of times the sign bit of the register is replicated into
1396 /// the other bits. We know that at least 1 bit is always equal to the sign
1397 /// bit (itself), but other cases can give us information. For example,
1398 /// immediately after an "SRA X, 2", we know that the top 3 bits are all equal
1399 /// to each other, so we return 3. The DemandedElts argument allows
1400 /// us to only collect the minimum sign bits of the requested vector elements.
1401 /// Targets can implement the ComputeNumSignBitsForTarget method in the
1402 /// TargetLowering class to allow target nodes to be understood.
1403 unsigned ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
1404 unsigned Depth = 0) const;
1405
1406 /// Return true if the specified operand is an ISD::ADD with a ConstantSDNode
1407 /// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that
1408 /// is guaranteed to have the same semantics as an ADD. This handles the
1409 /// equivalence:
1410 /// X|Cst == X+Cst iff X&Cst = 0.
1411 bool isBaseWithConstantOffset(SDValue Op) const;
1412
1413 /// Test whether the given SDValue is known to never be NaN.
1414 bool isKnownNeverNaN(SDValue Op) const;
1415
1416 /// Test whether the given SDValue is known to never be positive or negative
1417 /// zero.
1418 bool isKnownNeverZero(SDValue Op) const;
1419
1420 /// Test whether two SDValues are known to compare equal. This
1421 /// is true if they are the same value, or if one is negative zero and the
1422 /// other positive zero.
1423 bool isEqualTo(SDValue A, SDValue B) const;
1424
1425 /// Return true if A and B have no common bits set. As an example, this can
1426 /// allow an 'add' to be transformed into an 'or'.
1427 bool haveNoCommonBitsSet(SDValue A, SDValue B) const;
1428
1429 /// Utility function used by legalize and lowering to
1430 /// "unroll" a vector operation by splitting out the scalars and operating
1431 /// on each element individually. If the ResNE is 0, fully unroll the vector
1432 /// op. If ResNE is less than the width of the vector op, unroll up to ResNE.
1433 /// If the ResNE is greater than the width of the vector op, unroll the
1434 /// vector op and fill the end of the resulting vector with UNDEFS.
1435 SDValue UnrollVectorOp(SDNode *N, unsigned ResNE = 0);
1436
1437 /// Return true if loads are next to each other and can be
1438 /// merged. Check that both are nonvolatile and if LD is loading
1439 /// 'Bytes' bytes from a location that is 'Dist' units away from the
1440 /// location that the 'Base' load is loading from.
1441 bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base,
1442 unsigned Bytes, int Dist) const;
1443
1444 /// Infer alignment of a load / store address. Return 0 if
1445 /// it cannot be inferred.
1446 unsigned InferPtrAlignment(SDValue Ptr) const;
1447
1448 /// Compute the VTs needed for the low/hi parts of a type
1449 /// which is split (or expanded) into two not necessarily identical pieces.
1450 std::pair<EVT, EVT> GetSplitDestVTs(const EVT &VT) const;
1451
1452 /// Split the vector with EXTRACT_SUBVECTOR using the provides
1453 /// VTs and return the low/high part.
1454 std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL,
1455 const EVT &LoVT, const EVT &HiVT);
1456
1457 /// Split the vector with EXTRACT_SUBVECTOR and return the low/high part.
1458 std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL) {
1459 EVT LoVT, HiVT;
1460 std::tie(LoVT, HiVT) = GetSplitDestVTs(N.getValueType());
1461 return SplitVector(N, DL, LoVT, HiVT);
1462 }
1463
1464 /// Split the node's operand with EXTRACT_SUBVECTOR and
1465 /// return the low/high part.
1466 std::pair<SDValue, SDValue> SplitVectorOperand(const SDNode *N, unsigned OpNo)
1467 {
1468 return SplitVector(N->getOperand(OpNo), SDLoc(N));
1469 }
1470
1471 /// Append the extracted elements from Start to Count out of the vector Op
1472 /// in Args. If Count is 0, all of the elements will be extracted.
1473 void ExtractVectorElements(SDValue Op, SmallVectorImpl<SDValue> &Args,
1474 unsigned Start = 0, unsigned Count = 0);
1475
1476 /// Compute the default alignment value for the given type.
1477 unsigned getEVTAlignment(EVT MemoryVT) const;
1478
1479 /// Test whether the given value is a constant int or similar node.
1480 SDNode *isConstantIntBuildVectorOrConstantInt(SDValue N);
1481
1482 /// Test whether the given value is a constant FP or similar node.
1483 SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N);
1484
1485 /// \returns true if \p N is any kind of constant or build_vector of
1486 /// constants, int or float. If a vector, it may not necessarily be a splat.
1487 inline bool isConstantValueOfAnyType(SDValue N) {
1488 return isConstantIntBuildVectorOrConstantInt(N) ||
1489 isConstantFPBuildVectorOrConstantFP(N);
1490 }
1491
1492private:
1493 void InsertNode(SDNode *N);
1494 bool RemoveNodeFromCSEMaps(SDNode *N);
1495 void AddModifiedNodeToCSEMaps(SDNode *N);
1496 SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);
1497 SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
1498 void *&InsertPos);
1499 SDNode *FindModifiedNodeSlot(SDNode *N, ArrayRef<SDValue> Ops,
1500 void *&InsertPos);
1501 SDNode *UpdateSDLocOnMergeSDNode(SDNode *N, const SDLoc &loc);
1502
1503 void DeleteNodeNotInCSEMaps(SDNode *N);
1504 void DeallocateNode(SDNode *N);
1505
1506 void allnodes_clear();
1507
1508 /// Look up the node specified by ID in CSEMap. If it exists, return it. If
1509 /// not, return the insertion token that will make insertion faster. This
1510 /// overload is for nodes other than Constant or ConstantFP, use the other one
1511 /// for those.
1512 SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, void *&InsertPos);
1513
1514 /// Look up the node specified by ID in CSEMap. If it exists, return it. If
1515 /// not, return the insertion token that will make insertion faster. Performs
1516 /// additional processing for constant nodes.
1517 SDNode *FindNodeOrInsertPos(const FoldingSetNodeID &ID, const SDLoc &DL,
1518 void *&InsertPos);
1519
1520 /// List of non-single value types.
1521 FoldingSet<SDVTListNode> VTListMap;
1522
1523 /// Maps to auto-CSE operations.
1524 std::vector<CondCodeSDNode*> CondCodeNodes;
1525
1526 std::vector<SDNode*> ValueTypeNodes;
1527 std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes;
1528 StringMap<SDNode*> ExternalSymbols;
1529
1530 std::map<std::pair<std::string, unsigned char>,SDNode*> TargetExternalSymbols;
1531 DenseMap<MCSymbol *, SDNode *> MCSymbols;
1532};
1533
1534template <> struct GraphTraits<SelectionDAG*> : public GraphTraits<SDNode*> {
1535 using nodes_iterator = pointer_iterator<SelectionDAG::allnodes_iterator>;
1536
1537 static nodes_iterator nodes_begin(SelectionDAG *G) {
1538 return nodes_iterator(G->allnodes_begin());
1539 }
1540
1541 static nodes_iterator nodes_end(SelectionDAG *G) {
1542 return nodes_iterator(G->allnodes_end());
1543 }
1544};
1545
1546template <class TargetMemSDNode>
1547SDValue SelectionDAG::getTargetMemSDNode(SDVTList VTs,
1548 ArrayRef<SDValue> Ops,
1549 const SDLoc &dl, EVT MemVT,
1550 MachineMemOperand *MMO) {
1551 /// Compose node ID and try to find an existing node.
1552 FoldingSetNodeID ID;
1553 unsigned Opcode =
1554 TargetMemSDNode(dl.getIROrder(), DebugLoc(), VTs, MemVT, MMO).getOpcode();
1555 ID.AddInteger(Opcode);
1556 ID.AddPointer(VTs.VTs);
1557 for (auto& Op : Ops) {
1558 ID.AddPointer(Op.getNode());
1559 ID.AddInteger(Op.getResNo());
1560 }
1561 ID.AddInteger(MemVT.getRawBits());
1562 ID.AddInteger(MMO->getPointerInfo().getAddrSpace());
1563 ID.AddInteger(getSyntheticNodeSubclassData<TargetMemSDNode>(
1564 dl.getIROrder(), VTs, MemVT, MMO));
1565
1566 void *IP = nullptr;
1567 if (SDNode *E = FindNodeOrInsertPos(ID, dl, IP)) {
1568 cast<TargetMemSDNode>(E)->refineAlignment(MMO);
1569 return SDValue(E, 0);
1570 }
1571
1572 /// Existing node was not found. Create a new one.
1573 auto *N = newSDNode<TargetMemSDNode>(dl.getIROrder(), dl.getDebugLoc(), VTs,
1574 MemVT, MMO);
1575 createOperands(N, Ops);
1576 CSEMap.InsertNode(N, IP);
1577 InsertNode(N);
1578 return SDValue(N, 0);
1579}
1580
1581} // end namespace llvm
1582
1583#endif // LLVM_CODEGEN_SELECTIONDAG_H

/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the SDNode class and derived classes, which are used to
11// represent the nodes and operations present in a SelectionDAG. These nodes
12// and operations are machine code level operations, with some similarities to
13// the GCC RTL representation.
14//
15// Clients should include the SelectionDAG.h file instead of this file directly.
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
20#define LLVM_CODEGEN_SELECTIONDAGNODES_H
21
22#include "llvm/ADT/APFloat.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/ADT/BitVector.h"
25#include "llvm/ADT/FoldingSet.h"
26#include "llvm/ADT/GraphTraits.h"
27#include "llvm/ADT/SmallPtrSet.h"
28#include "llvm/ADT/SmallVector.h"
29#include "llvm/ADT/ilist_node.h"
30#include "llvm/ADT/iterator.h"
31#include "llvm/ADT/iterator_range.h"
32#include "llvm/CodeGen/ISDOpcodes.h"
33#include "llvm/CodeGen/MachineMemOperand.h"
34#include "llvm/CodeGen/MachineValueType.h"
35#include "llvm/CodeGen/ValueTypes.h"
36#include "llvm/IR/Constants.h"
37#include "llvm/IR/DebugLoc.h"
38#include "llvm/IR/Instruction.h"
39#include "llvm/IR/Instructions.h"
40#include "llvm/IR/Metadata.h"
41#include "llvm/Support/AlignOf.h"
42#include "llvm/Support/AtomicOrdering.h"
43#include "llvm/Support/Casting.h"
44#include "llvm/Support/ErrorHandling.h"
45#include <algorithm>
46#include <cassert>
47#include <climits>
48#include <cstddef>
49#include <cstdint>
50#include <cstring>
51#include <iterator>
52#include <string>
53#include <tuple>
54
55namespace llvm {
56
57class APInt;
58class Constant;
59template <typename T> struct DenseMapInfo;
60class GlobalValue;
61class MachineBasicBlock;
62class MachineConstantPoolValue;
63class MCSymbol;
64class raw_ostream;
65class SDNode;
66class SelectionDAG;
67class Type;
68class Value;
69
70void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
71 bool force = false);
72
73/// This represents a list of ValueType's that has been intern'd by
74/// a SelectionDAG. Instances of this simple value class are returned by
75/// SelectionDAG::getVTList(...).
76///
77struct SDVTList {
78 const EVT *VTs;
79 unsigned int NumVTs;
80};
81
82namespace ISD {
83
84 /// Node predicates
85
86 /// If N is a BUILD_VECTOR node whose elements are all the same constant or
87 /// undefined, return true and return the constant value in \p SplatValue.
88 bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);
89
90 /// Return true if the specified node is a BUILD_VECTOR where all of the
91 /// elements are ~0 or undef.
92 bool isBuildVectorAllOnes(const SDNode *N);
93
94 /// Return true if the specified node is a BUILD_VECTOR where all of the
95 /// elements are 0 or undef.
96 bool isBuildVectorAllZeros(const SDNode *N);
97
98 /// Return true if the specified node is a BUILD_VECTOR node of all
99 /// ConstantSDNode or undef.
100 bool isBuildVectorOfConstantSDNodes(const SDNode *N);
101
102 /// Return true if the specified node is a BUILD_VECTOR node of all
103 /// ConstantFPSDNode or undef.
104 bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);
105
106 /// Return true if the node has at least one operand and all operands of the
107 /// specified node are ISD::UNDEF.
108 bool allOperandsUndef(const SDNode *N);
109
110} // end namespace ISD
111
112//===----------------------------------------------------------------------===//
113/// Unlike LLVM values, Selection DAG nodes may return multiple
114/// values as the result of a computation. Many nodes return multiple values,
115/// from loads (which define a token and a return value) to ADDC (which returns
116/// a result and a carry value), to calls (which may return an arbitrary number
117/// of values).
118///
119/// As such, each use of a SelectionDAG computation must indicate the node that
120/// computes it as well as which return value to use from that node. This pair
121/// of information is represented with the SDValue value type.
122///
123class SDValue {
124 friend struct DenseMapInfo<SDValue>;
125
126 SDNode *Node = nullptr; // The node defining the value we are using.
127 unsigned ResNo = 0; // Which return value of the node we are using.
128
129public:
130 SDValue() = default;
131 SDValue(SDNode *node, unsigned resno);
132
133 /// get the index which selects a specific result in the SDNode
134 unsigned getResNo() const { return ResNo; }
135
136 /// get the SDNode which holds the desired result
137 SDNode *getNode() const { return Node; }
138
139 /// set the SDNode
140 void setNode(SDNode *N) { Node = N; }
141
142 inline SDNode *operator->() const { return Node; }
143
144 bool operator==(const SDValue &O) const {
145 return Node == O.Node && ResNo == O.ResNo;
146 }
147 bool operator!=(const SDValue &O) const {
148 return !operator==(O);
149 }
150 bool operator<(const SDValue &O) const {
151 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
152 }
153 explicit operator bool() const {
154 return Node != nullptr;
155 }
156
157 SDValue getValue(unsigned R) const {
158 return SDValue(Node, R);
159 }
160
161 /// Return true if this node is an operand of N.
162 bool isOperandOf(const SDNode *N) const;
163
164 /// Return the ValueType of the referenced return value.
165 inline EVT getValueType() const;
166
167 /// Return the simple ValueType of the referenced return value.
168 MVT getSimpleValueType() const {
169 return getValueType().getSimpleVT();
170 }
171
172 /// Returns the size of the value in bits.
173 unsigned getValueSizeInBits() const {
174 return getValueType().getSizeInBits();
175 }
176
177 unsigned getScalarValueSizeInBits() const {
178 return getValueType().getScalarType().getSizeInBits();
179 }
180
181 // Forwarding methods - These forward to the corresponding methods in SDNode.
182 inline unsigned getOpcode() const;
183 inline unsigned getNumOperands() const;
184 inline const SDValue &getOperand(unsigned i) const;
185 inline uint64_t getConstantOperandVal(unsigned i) const;
186 inline bool isTargetMemoryOpcode() const;
187 inline bool isTargetOpcode() const;
188 inline bool isMachineOpcode() const;
189 inline bool isUndef() const;
190 inline unsigned getMachineOpcode() const;
191 inline const DebugLoc &getDebugLoc() const;
192 inline void dump() const;
193 inline void dumpr() const;
194
195 /// Return true if this operand (which must be a chain) reaches the
196 /// specified operand without crossing any side-effecting instructions.
197 /// In practice, this looks through token factors and non-volatile loads.
198 /// In order to remain efficient, this only
199 /// looks a couple of nodes in, it does not do an exhaustive search.
200 bool reachesChainWithoutSideEffects(SDValue Dest,
201 unsigned Depth = 2) const;
202
203 /// Return true if there are no nodes using value ResNo of Node.
204 inline bool use_empty() const;
205
206 /// Return true if there is exactly one node using value ResNo of Node.
207 inline bool hasOneUse() const;
208};
209
210template<> struct DenseMapInfo<SDValue> {
211 static inline SDValue getEmptyKey() {
212 SDValue V;
213 V.ResNo = -1U;
214 return V;
215 }
216
217 static inline SDValue getTombstoneKey() {
218 SDValue V;
219 V.ResNo = -2U;
220 return V;
221 }
222
223 static unsigned getHashValue(const SDValue &Val) {
224 return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
225 (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
226 }
227
228 static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
229 return LHS == RHS;
230 }
231};
232template <> struct isPodLike<SDValue> { static const bool value = true; };
233
234/// Allow casting operators to work directly on
235/// SDValues as if they were SDNode*'s.
236template<> struct simplify_type<SDValue> {
237 using SimpleType = SDNode *;
238
239 static SimpleType getSimplifiedValue(SDValue &Val) {
240 return Val.getNode();
241 }
242};
243template<> struct simplify_type<const SDValue> {
244 using SimpleType = /*const*/ SDNode *;
245
246 static SimpleType getSimplifiedValue(const SDValue &Val) {
247 return Val.getNode();
248 }
249};
250
251/// Represents a use of a SDNode. This class holds an SDValue,
252/// which records the SDNode being used and the result number, a
253/// pointer to the SDNode using the value, and Next and Prev pointers,
254/// which link together all the uses of an SDNode.
255///
256class SDUse {
257 /// Val - The value being used.
258 SDValue Val;
259 /// User - The user of this value.
260 SDNode *User = nullptr;
261 /// Prev, Next - Pointers to the uses list of the SDNode referred by
262 /// this operand.
263 SDUse **Prev = nullptr;
264 SDUse *Next = nullptr;
265
266public:
267 SDUse() = default;
268 SDUse(const SDUse &U) = delete;
269 SDUse &operator=(const SDUse &) = delete;
270
271 /// Normally SDUse will just implicitly convert to an SDValue that it holds.
272 operator const SDValue&() const { return Val; }
273
274 /// If implicit conversion to SDValue doesn't work, the get() method returns
275 /// the SDValue.
276 const SDValue &get() const { return Val; }
277
278 /// This returns the SDNode that contains this Use.
279 SDNode *getUser() { return User; }
280
281 /// Get the next SDUse in the use list.
282 SDUse *getNext() const { return Next; }
283
284 /// Convenience function for get().getNode().
285 SDNode *getNode() const { return Val.getNode(); }
286 /// Convenience function for get().getResNo().
287 unsigned getResNo() const { return Val.getResNo(); }
288 /// Convenience function for get().getValueType().
289 EVT getValueType() const { return Val.getValueType(); }
290
291 /// Convenience function for get().operator==
292 bool operator==(const SDValue &V) const {
293 return Val == V;
294 }
295
296 /// Convenience function for get().operator!=
297 bool operator!=(const SDValue &V) const {
298 return Val != V;
299 }
300
301 /// Convenience function for get().operator<
302 bool operator<(const SDValue &V) const {
303 return Val < V;
304 }
305
306private:
307 friend class SelectionDAG;
308 friend class SDNode;
309 // TODO: unfriend HandleSDNode once we fix its operand handling.
310 friend class HandleSDNode;
311
312 void setUser(SDNode *p) { User = p; }
313
314 /// Remove this use from its existing use list, assign it the
315 /// given value, and add it to the new value's node's use list.
316 inline void set(const SDValue &V);
317 /// Like set, but only supports initializing a newly-allocated
318 /// SDUse with a non-null value.
319 inline void setInitial(const SDValue &V);
320 /// Like set, but only sets the Node portion of the value,
321 /// leaving the ResNo portion unmodified.
322 inline void setNode(SDNode *N);
323
324 void addToList(SDUse **List) {
325 Next = *List;
326 if (Next) Next->Prev = &Next;
327 Prev = List;
328 *List = this;
329 }
330
331 void removeFromList() {
332 *Prev = Next;
333 if (Next) Next->Prev = Prev;
334 }
335};
336
337/// simplify_type specializations - Allow casting operators to work directly on
338/// SDValues as if they were SDNode*'s.
339template<> struct simplify_type<SDUse> {
340 using SimpleType = SDNode *;
341
342 static SimpleType getSimplifiedValue(SDUse &Val) {
343 return Val.getNode();
344 }
345};
346
347/// These are IR-level optimization flags that may be propagated to SDNodes.
348/// TODO: This data structure should be shared by the IR optimizer and the
349/// the backend.
350struct SDNodeFlags {
351private:
352 // This bit is used to determine if the flags are in a defined state.
353 // Flag bits can only be masked out during intersection if the masking flags
354 // are defined.
355 bool AnyDefined : 1;
356
357 bool NoUnsignedWrap : 1;
358 bool NoSignedWrap : 1;
359 bool Exact : 1;
360 bool UnsafeAlgebra : 1;
361 bool NoNaNs : 1;
362 bool NoInfs : 1;
363 bool NoSignedZeros : 1;
364 bool AllowReciprocal : 1;
365 bool VectorReduction : 1;
366 bool AllowContract : 1;
367
368public:
369 /// Default constructor turns off all optimization flags.
370 SDNodeFlags()
371 : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
372 Exact(false), UnsafeAlgebra(false), NoNaNs(false), NoInfs(false),
373 NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
374 AllowContract(false) {}
375
376 /// Sets the state of the flags to the defined state.
377 void setDefined() { AnyDefined = true; }
378 /// Returns true if the flags are in a defined state.
379 bool isDefined() const { return AnyDefined; }
380
381 // These are mutators for each flag.
382 void setNoUnsignedWrap(bool b) {
383 setDefined();
384 NoUnsignedWrap = b;
385 }
386 void setNoSignedWrap(bool b) {
387 setDefined();
388 NoSignedWrap = b;
389 }
390 void setExact(bool b) {
391 setDefined();
392 Exact = b;
393 }
394 void setUnsafeAlgebra(bool b) {
395 setDefined();
396 UnsafeAlgebra = b;
397 }
398 void setNoNaNs(bool b) {
399 setDefined();
400 NoNaNs = b;
401 }
402 void setNoInfs(bool b) {
403 setDefined();
404 NoInfs = b;
405 }
406 void setNoSignedZeros(bool b) {
407 setDefined();
408 NoSignedZeros = b;
409 }
410 void setAllowReciprocal(bool b) {
411 setDefined();
412 AllowReciprocal = b;
413 }
414 void setVectorReduction(bool b) {
415 setDefined();
416 VectorReduction = b;
417 }
418 void setAllowContract(bool b) {
419 setDefined();
420 AllowContract = b;
421 }
422
423 // These are accessors for each flag.
424 bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
425 bool hasNoSignedWrap() const { return NoSignedWrap; }
426 bool hasExact() const { return Exact; }
427 bool hasUnsafeAlgebra() const { return UnsafeAlgebra; }
428 bool hasNoNaNs() const { return NoNaNs; }
429 bool hasNoInfs() const { return NoInfs; }
430 bool hasNoSignedZeros() const { return NoSignedZeros; }
431 bool hasAllowReciprocal() const { return AllowReciprocal; }
432 bool hasVectorReduction() const { return VectorReduction; }
433 bool hasAllowContract() const { return AllowContract; }
434
435 /// Clear any flags in this flag set that aren't also set in Flags.
436 /// If the given Flags are undefined then don't do anything.
437 void intersectWith(const SDNodeFlags Flags) {
438 if (!Flags.isDefined())
439 return;
440 NoUnsignedWrap &= Flags.NoUnsignedWrap;
441 NoSignedWrap &= Flags.NoSignedWrap;
442 Exact &= Flags.Exact;
443 UnsafeAlgebra &= Flags.UnsafeAlgebra;
444 NoNaNs &= Flags.NoNaNs;
445 NoInfs &= Flags.NoInfs;
446 NoSignedZeros &= Flags.NoSignedZeros;
447 AllowReciprocal &= Flags.AllowReciprocal;
448 VectorReduction &= Flags.VectorReduction;
449 AllowContract &= Flags.AllowContract;
450 }
451};
452
453/// Represents one node in the SelectionDAG.
454///
455class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
456private:
457 /// The operation that this node performs.
458 int16_t NodeType;
459
460protected:
461 // We define a set of mini-helper classes to help us interpret the bits in our
462 // SubclassData. These are designed to fit within a uint16_t so they pack
463 // with NodeType.
464
465 class SDNodeBitfields {
466 friend class SDNode;
467 friend class MemIntrinsicSDNode;
468 friend class MemSDNode;
469
470 uint16_t HasDebugValue : 1;
471 uint16_t IsMemIntrinsic : 1;
472 };
473 enum { NumSDNodeBits = 2 };
474
475 class ConstantSDNodeBitfields {
476 friend class ConstantSDNode;
477
478 uint16_t : NumSDNodeBits;
479
480 uint16_t IsOpaque : 1;
481 };
482
483 class MemSDNodeBitfields {
484 friend class MemSDNode;
485 friend class MemIntrinsicSDNode;
486 friend class AtomicSDNode;
487
488 uint16_t : NumSDNodeBits;
489
490 uint16_t IsVolatile : 1;
491 uint16_t IsNonTemporal : 1;
492 uint16_t IsDereferenceable : 1;
493 uint16_t IsInvariant : 1;
494 };
495 enum { NumMemSDNodeBits = NumSDNodeBits + 4 };
496
497 class LSBaseSDNodeBitfields {
498 friend class LSBaseSDNode;
499
500 uint16_t : NumMemSDNodeBits;
501
502 uint16_t AddressingMode : 3; // enum ISD::MemIndexedMode
503 };
504 enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };
505
506 class LoadSDNodeBitfields {
507 friend class LoadSDNode;
508 friend class MaskedLoadSDNode;
509
510 uint16_t : NumLSBaseSDNodeBits;
511
512 uint16_t ExtTy : 2; // enum ISD::LoadExtType
513 uint16_t IsExpanding : 1;
514 };
515
516 class StoreSDNodeBitfields {
517 friend class StoreSDNode;
518 friend class MaskedStoreSDNode;
519
520 uint16_t : NumLSBaseSDNodeBits;
521
522 uint16_t IsTruncating : 1;
523 uint16_t IsCompressing : 1;
524 };
525
526 union {
527 char RawSDNodeBits[sizeof(uint16_t)];
528 SDNodeBitfields SDNodeBits;
529 ConstantSDNodeBitfields ConstantSDNodeBits;
530 MemSDNodeBitfields MemSDNodeBits;
531 LSBaseSDNodeBitfields LSBaseSDNodeBits;
532 LoadSDNodeBitfields LoadSDNodeBits;
533 StoreSDNodeBitfields StoreSDNodeBits;
534 };
535
536 // RawSDNodeBits must cover the entirety of the union. This means that all of
537 // the union's members must have size <= RawSDNodeBits. We write the RHS as
538 // "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
539 static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
540 static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
541 static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
542 static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
543 static_assert(sizeof(LoadSDNodeBitfields) <= 4, "field too wide");
544 static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");
545
546private:
547 friend class SelectionDAG;
548 // TODO: unfriend HandleSDNode once we fix its operand handling.
549 friend class HandleSDNode;
550
551 /// Unique id per SDNode in the DAG.
552 int NodeId = -1;
553
554 /// The values that are used by this operation.
555 SDUse *OperandList = nullptr;
556
557 /// The types of the values this node defines. SDNode's may
558 /// define multiple values simultaneously.
559 const EVT *ValueList;
560
561 /// List of uses for this SDNode.
562 SDUse *UseList = nullptr;
563
564 /// The number of entries in the Operand/Value list.
565 unsigned short NumOperands = 0;
566 unsigned short NumValues;
567
568 // The ordering of the SDNodes. It roughly corresponds to the ordering of the
569 // original LLVM instructions.
570 // This is used for turning off scheduling, because we'll forgo
571 // the normal scheduling algorithms and output the instructions according to
572 // this ordering.
573 unsigned IROrder;
574
575 /// Source line information.
576 DebugLoc debugLoc;
577
578 /// Return a pointer to the specified value type.
579 static const EVT *getValueTypeList(EVT VT);
580
581 SDNodeFlags Flags;
582
583public:
584 /// Unique and persistent id per SDNode in the DAG.
585 /// Used for debug printing.
586 uint16_t PersistentId;
587
588 //===--------------------------------------------------------------------===//
589 // Accessors
590 //
591
592 /// Return the SelectionDAG opcode value for this node. For
593 /// pre-isel nodes (those for which isMachineOpcode returns false), these
594 /// are the opcode values in the ISD and <target>ISD namespaces. For
595 /// post-isel opcodes, see getMachineOpcode.
596 unsigned getOpcode() const { return (unsigned short)NodeType; }
597
598 /// Test if this node has a target-specific opcode (in the
599 /// \<target\>ISD namespace).
600 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
601
602 /// Test if this node has a target-specific
603 /// memory-referencing opcode (in the \<target\>ISD namespace and
604 /// greater than FIRST_TARGET_MEMORY_OPCODE).
605 bool isTargetMemoryOpcode() const {
606 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
607 }
608
609 /// Return true if the type of the node type undefined.
610 bool isUndef() const { return NodeType == ISD::UNDEF; }
611
612 /// Test if this node is a memory intrinsic (with valid pointer information).
613 /// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
614 /// non-memory intrinsics (with chains) that are not really instances of
615 /// MemSDNode. For such nodes, we need some extra state to determine the
616 /// proper classof relationship.
617 bool isMemIntrinsic() const {
618 return (NodeType == ISD::INTRINSIC_W_CHAIN ||
619 NodeType == ISD::INTRINSIC_VOID) &&
620 SDNodeBits.IsMemIntrinsic;
621 }
622
623 /// Test if this node is a strict floating point pseudo-op.
624 bool isStrictFPOpcode() {
625 switch (NodeType) {
626 default:
627 return false;
628 case ISD::STRICT_FADD:
629 case ISD::STRICT_FSUB:
630 case ISD::STRICT_FMUL:
631 case ISD::STRICT_FDIV:
632 case ISD::STRICT_FREM:
633 case ISD::STRICT_FMA:
634 case ISD::STRICT_FSQRT:
635 case ISD::STRICT_FPOW:
636 case ISD::STRICT_FPOWI:
637 case ISD::STRICT_FSIN:
638 case ISD::STRICT_FCOS:
639 case ISD::STRICT_FEXP:
640 case ISD::STRICT_FEXP2:
641 case ISD::STRICT_FLOG:
642 case ISD::STRICT_FLOG10:
643 case ISD::STRICT_FLOG2:
644 case ISD::STRICT_FRINT:
645 case ISD::STRICT_FNEARBYINT:
646 return true;
647 }
648 }
649
650 /// Test if this node has a post-isel opcode, directly
651 /// corresponding to a MachineInstr opcode.
652 bool isMachineOpcode() const { return NodeType < 0; }
653
654 /// This may only be called if isMachineOpcode returns
655 /// true. It returns the MachineInstr opcode value that the node's opcode
656 /// corresponds to.
657 unsigned getMachineOpcode() const {
658 assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 658, __PRETTY_FUNCTION__))
;
659 return ~NodeType;
660 }
661
662 bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
663 void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }
664
665 /// Return true if there are no uses of this node.
666 bool use_empty() const { return UseList == nullptr; }
667
668 /// Return true if there is exactly one use of this node.
669 bool hasOneUse() const {
670 return !use_empty() && std::next(use_begin()) == use_end();
671 }
672
673 /// Return the number of uses of this node. This method takes
674 /// time proportional to the number of uses.
675 size_t use_size() const { return std::distance(use_begin(), use_end()); }
676
677 /// Return the unique node id.
678 int getNodeId() const { return NodeId; }
679
680 /// Set unique node id.
681 void setNodeId(int Id) { NodeId = Id; }
682
683 /// Return the node ordering.
684 unsigned getIROrder() const { return IROrder; }
685
686 /// Set the node ordering.
687 void setIROrder(unsigned Order) { IROrder = Order; }
688
689 /// Return the source location info.
690 const DebugLoc &getDebugLoc() const { return debugLoc; }
691
692 /// Set source location info. Try to avoid this, putting
693 /// it in the constructor is preferable.
694 void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }
695
696 /// This class provides iterator support for SDUse
697 /// operands that use a specific SDNode.
698 class use_iterator
699 : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
700 friend class SDNode;
701
702 SDUse *Op = nullptr;
703
704 explicit use_iterator(SDUse *op) : Op(op) {}
705
706 public:
707 using reference = std::iterator<std::forward_iterator_tag,
708 SDUse, ptrdiff_t>::reference;
709 using pointer = std::iterator<std::forward_iterator_tag,
710 SDUse, ptrdiff_t>::pointer;
711
712 use_iterator() = default;
713 use_iterator(const use_iterator &I) : Op(I.Op) {}
714
715 bool operator==(const use_iterator &x) const {
716 return Op == x.Op;
717 }
718 bool operator!=(const use_iterator &x) const {
719 return !operator==(x);
720 }
721
722 /// Return true if this iterator is at the end of uses list.
723 bool atEnd() const { return Op == nullptr; }
724
725 // Iterator traversal: forward iteration only.
726 use_iterator &operator++() { // Preincrement
727 assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 727, __PRETTY_FUNCTION__))
;
728 Op = Op->getNext();
729 return *this;
730 }
731
732 use_iterator operator++(int) { // Postincrement
733 use_iterator tmp = *this; ++*this; return tmp;
734 }
735
736 /// Retrieve a pointer to the current user node.
737 SDNode *operator*() const {
738 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 738, __PRETTY_FUNCTION__))
;
739 return Op->getUser();
740 }
741
742 SDNode *operator->() const { return operator*(); }
743
744 SDUse &getUse() const { return *Op; }
745
746 /// Retrieve the operand # of this use in its user.
747 unsigned getOperandNo() const {
748 assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 748, __PRETTY_FUNCTION__))
;
749 return (unsigned)(Op - Op->getUser()->OperandList);
750 }
751 };
752
753 /// Provide iteration support to walk over all uses of an SDNode.
754 use_iterator use_begin() const {
755 return use_iterator(UseList);
756 }
757
758 static use_iterator use_end() { return use_iterator(nullptr); }
759
760 inline iterator_range<use_iterator> uses() {
761 return make_range(use_begin(), use_end());
762 }
763 inline iterator_range<use_iterator> uses() const {
764 return make_range(use_begin(), use_end());
765 }
766
767 /// Return true if there are exactly NUSES uses of the indicated value.
768 /// This method ignores uses of other values defined by this operation.
769 bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;
770
771 /// Return true if there are any use of the indicated value.
772 /// This method ignores uses of other values defined by this operation.
773 bool hasAnyUseOfValue(unsigned Value) const;
774
775 /// Return true if this node is the only use of N.
776 bool isOnlyUserOf(const SDNode *N) const;
777
778 /// Return true if this node is an operand of N.
779 bool isOperandOf(const SDNode *N) const;
780
781 /// Return true if this node is a predecessor of N.
782 /// NOTE: Implemented on top of hasPredecessor and every bit as
783 /// expensive. Use carefully.
784 bool isPredecessorOf(const SDNode *N) const {
785 return N->hasPredecessor(this);
786 }
787
788 /// Return true if N is a predecessor of this node.
789 /// N is either an operand of this node, or can be reached by recursively
790 /// traversing up the operands.
791 /// NOTE: This is an expensive method. Use it carefully.
792 bool hasPredecessor(const SDNode *N) const;
793
794 /// Returns true if N is a predecessor of any node in Worklist. This
795 /// helper keeps Visited and Worklist sets externally to allow unions
796 /// searches to be performed in parallel, caching of results across
797 /// queries and incremental addition to Worklist. Stops early if N is
798 /// found but will resume. Remember to clear Visited and Worklists
799 /// if DAG changes.
800 static bool hasPredecessorHelper(const SDNode *N,
801 SmallPtrSetImpl<const SDNode *> &Visited,
802 SmallVectorImpl<const SDNode *> &Worklist,
803 unsigned int MaxSteps = 0) {
804 if (Visited.count(N))
805 return true;
806 while (!Worklist.empty()) {
807 const SDNode *M = Worklist.pop_back_val();
808 bool Found = false;
809 for (const SDValue &OpV : M->op_values()) {
810 SDNode *Op = OpV.getNode();
811 if (Visited.insert(Op).second)
812 Worklist.push_back(Op);
813 if (Op == N)
814 Found = true;
815 }
816 if (Found)
817 return true;
818 if (MaxSteps != 0 && Visited.size() >= MaxSteps)
819 return false;
820 }
821 return false;
822 }
823
824 /// Return true if all the users of N are contained in Nodes.
825 /// NOTE: Requires at least one match, but doesn't require them all.
826 static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);
827
828 /// Return the number of values used by this operation.
829 unsigned getNumOperands() const { return NumOperands; }
830
831 /// Helper method returns the integer value of a ConstantSDNode operand.
832 inline uint64_t getConstantOperandVal(unsigned Num) const;
833
834 const SDValue &getOperand(unsigned Num) const {
835 assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 835, __PRETTY_FUNCTION__))
;
836 return OperandList[Num];
837 }
838
839 using op_iterator = SDUse *;
840
841 op_iterator op_begin() const { return OperandList; }
842 op_iterator op_end() const { return OperandList+NumOperands; }
843 ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }
844
845 /// Iterator for directly iterating over the operand SDValue's.
846 struct value_op_iterator
847 : iterator_adaptor_base<value_op_iterator, op_iterator,
848 std::random_access_iterator_tag, SDValue,
849 ptrdiff_t, value_op_iterator *,
850 value_op_iterator *> {
851 explicit value_op_iterator(SDUse *U = nullptr)
852 : iterator_adaptor_base(U) {}
853
854 const SDValue &operator*() const { return I->get(); }
855 };
856
857 iterator_range<value_op_iterator> op_values() const {
858 return make_range(value_op_iterator(op_begin()),
859 value_op_iterator(op_end()));
860 }
861
862 SDVTList getVTList() const {
863 SDVTList X = { ValueList, NumValues };
864 return X;
865 }
866
867 /// If this node has a glue operand, return the node
868 /// to which the glue operand points. Otherwise return NULL.
869 SDNode *getGluedNode() const {
870 if (getNumOperands() != 0 &&
871 getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
872 return getOperand(getNumOperands()-1).getNode();
873 return nullptr;
874 }
875
876 /// If this node has a glue value with a user, return
877 /// the user (there is at most one). Otherwise return NULL.
878 SDNode *getGluedUser() const {
879 for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
880 if (UI.getUse().get().getValueType() == MVT::Glue)
881 return *UI;
882 return nullptr;
883 }
884
885 const SDNodeFlags getFlags() const { return Flags; }
886 void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
887
888 /// Clear any flags in this node that aren't also set in Flags.
889 /// If Flags is not in a defined state then this has no effect.
890 void intersectFlagsWith(const SDNodeFlags Flags);
891
892 /// Return the number of values defined/returned by this operator.
893 unsigned getNumValues() const { return NumValues; }
894
895 /// Return the type of a specified result.
896 EVT getValueType(unsigned ResNo) const {
897 assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 897, __PRETTY_FUNCTION__))
;
898 return ValueList[ResNo];
899 }
900
901 /// Return the type of a specified result as a simple type.
902 MVT getSimpleValueType(unsigned ResNo) const {
903 return getValueType(ResNo).getSimpleVT();
904 }
905
906 /// Returns MVT::getSizeInBits(getValueType(ResNo)).
907 unsigned getValueSizeInBits(unsigned ResNo) const {
908 return getValueType(ResNo).getSizeInBits();
909 }
910
911 using value_iterator = const EVT *;
912
913 value_iterator value_begin() const { return ValueList; }
914 value_iterator value_end() const { return ValueList+NumValues; }
915
916 /// Return the opcode of this operation for printing.
917 std::string getOperationName(const SelectionDAG *G = nullptr) const;
918 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
919 void print_types(raw_ostream &OS, const SelectionDAG *G) const;
920 void print_details(raw_ostream &OS, const SelectionDAG *G) const;
921 void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
922 void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
923
924 /// Print a SelectionDAG node and all children down to
925 /// the leaves. The given SelectionDAG allows target-specific nodes
926 /// to be printed in human-readable form. Unlike printr, this will
927 /// print the whole DAG, including children that appear multiple
928 /// times.
929 ///
930 void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;
931
932 /// Print a SelectionDAG node and children up to
933 /// depth "depth." The given SelectionDAG allows target-specific
934 /// nodes to be printed in human-readable form. Unlike printr, this
935 /// will print children that appear multiple times wherever they are
936 /// used.
937 ///
938 void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
939 unsigned depth = 100) const;
940
941 /// Dump this node, for debugging.
942 void dump() const;
943
944 /// Dump (recursively) this node and its use-def subgraph.
945 void dumpr() const;
946
947 /// Dump this node, for debugging.
948 /// The given SelectionDAG allows target-specific nodes to be printed
949 /// in human-readable form.
950 void dump(const SelectionDAG *G) const;
951
952 /// Dump (recursively) this node and its use-def subgraph.
953 /// The given SelectionDAG allows target-specific nodes to be printed
954 /// in human-readable form.
955 void dumpr(const SelectionDAG *G) const;
956
957 /// printrFull to dbgs(). The given SelectionDAG allows
958 /// target-specific nodes to be printed in human-readable form.
959 /// Unlike dumpr, this will print the whole DAG, including children
960 /// that appear multiple times.
961 void dumprFull(const SelectionDAG *G = nullptr) const;
962
963 /// printrWithDepth to dbgs(). The given
964 /// SelectionDAG allows target-specific nodes to be printed in
965 /// human-readable form. Unlike dumpr, this will print children
966 /// that appear multiple times wherever they are used.
967 ///
968 void dumprWithDepth(const SelectionDAG *G = nullptr,
969 unsigned depth = 100) const;
970
971 /// Gather unique data for the node.
972 void Profile(FoldingSetNodeID &ID) const;
973
974 /// This method should only be used by the SDUse class.
975 void addUse(SDUse &U) { U.addToList(&UseList); }
976
977protected:
978 static SDVTList getSDVTList(EVT VT) {
979 SDVTList Ret = { getValueTypeList(VT), 1 };
980 return Ret;
981 }
982
983 /// Create an SDNode.
984 ///
985 /// SDNodes are created without any operands, and never own the operand
986 /// storage. To add operands, see SelectionDAG::createOperands.
987 SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
988 : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
989 IROrder(Order), debugLoc(std::move(dl)) {
990 memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
991 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 991, __PRETTY_FUNCTION__))
;
992 assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 993, __PRETTY_FUNCTION__))
993 "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 993, __PRETTY_FUNCTION__))
;
994 }
995
996 /// Release the operands and set this node to have zero operands.
997 void DropOperands();
998};
999
1000/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1001/// into SDNode creation functions.
1002/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1003/// from the original Instruction, and IROrder is the ordinal position of
1004/// the instruction.
1005/// When an SDNode is created after the DAG is being built, both DebugLoc and
1006/// the IROrder are propagated from the original SDNode.
1007/// So SDLoc class provides two constructors besides the default one, one to
1008/// be used by the DAGBuilder, the other to be used by others.
1009class SDLoc {
1010private:
1011 DebugLoc DL;
1012 int IROrder = 0;
1013
1014public:
1015 SDLoc() = default;
1016 SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
1017 SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
1018 SDLoc(const Instruction *I, int Order) : IROrder(Order) {
1019 assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1019, __PRETTY_FUNCTION__))
;
1020 if (I)
1021 DL = I->getDebugLoc();
1022 }
1023
1024 unsigned getIROrder() const { return IROrder; }
1025 const DebugLoc &getDebugLoc() const { return DL; }
1026};
1027
1028// Define inline functions from the SDValue class.
1029
1030inline SDValue::SDValue(SDNode *node, unsigned resno)
1031 : Node(node), ResNo(resno) {
1032 // Explicitly check for !ResNo to avoid use-after-free, because there are
1033 // callers that use SDValue(N, 0) with a deleted N to indicate successful
1034 // combines.
1035 assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1036, __PRETTY_FUNCTION__))
1036 "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
"Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1036, __PRETTY_FUNCTION__))
;
1037 assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1037, __PRETTY_FUNCTION__))
;
1038}
1039
1040inline unsigned SDValue::getOpcode() const {
1041 return Node->getOpcode();
1042}
1043
1044inline EVT SDValue::getValueType() const {
1045 return Node->getValueType(ResNo);
33
Called C++ object pointer is null
1046}
1047
1048inline unsigned SDValue::getNumOperands() const {
1049 return Node->getNumOperands();
1050}
1051
1052inline const SDValue &SDValue::getOperand(unsigned i) const {
1053 return Node->getOperand(i);
1054}
1055
1056inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
1057 return Node->getConstantOperandVal(i);
1058}
1059
1060inline bool SDValue::isTargetOpcode() const {
1061 return Node->isTargetOpcode();
1062}
1063
1064inline bool SDValue::isTargetMemoryOpcode() const {
1065 return Node->isTargetMemoryOpcode();
1066}
1067
1068inline bool SDValue::isMachineOpcode() const {
1069 return Node->isMachineOpcode();
1070}
1071
1072inline unsigned SDValue::getMachineOpcode() const {
1073 return Node->getMachineOpcode();
1074}
1075
1076inline bool SDValue::isUndef() const {
1077 return Node->isUndef();
1078}
1079
1080inline bool SDValue::use_empty() const {
1081 return !Node->hasAnyUseOfValue(ResNo);
1082}
1083
1084inline bool SDValue::hasOneUse() const {
1085 return Node->hasNUsesOfValue(1, ResNo);
1086}
1087
1088inline const DebugLoc &SDValue::getDebugLoc() const {
1089 return Node->getDebugLoc();
1090}
1091
1092inline void SDValue::dump() const {
1093 return Node->dump();
1094}
1095
1096inline void SDValue::dumpr() const {
1097 return Node->dumpr();
1098}
1099
1100// Define inline functions from the SDUse class.
1101
1102inline void SDUse::set(const SDValue &V) {
1103 if (Val.getNode()) removeFromList();
1104 Val = V;
1105 if (V.getNode()) V.getNode()->addUse(*this);
1106}
1107
1108inline void SDUse::setInitial(const SDValue &V) {
1109 Val = V;
1110 V.getNode()->addUse(*this);
1111}
1112
1113inline void SDUse::setNode(SDNode *N) {
1114 if (Val.getNode()) removeFromList();
1115 Val.setNode(N);
1116 if (N) N->addUse(*this);
1117}
1118
1119/// This class is used to form a handle around another node that
1120/// is persistent and is updated across invocations of replaceAllUsesWith on its
1121/// operand. This node should be directly created by end-users and not added to
1122/// the AllNodes list.
1123class HandleSDNode : public SDNode {
1124 SDUse Op;
1125
1126public:
1127 explicit HandleSDNode(SDValue X)
1128 : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
1129 // HandleSDNodes are never inserted into the DAG, so they won't be
1130 // auto-numbered. Use ID 65535 as a sentinel.
1131 PersistentId = 0xffff;
1132
1133 // Manually set up the operand list. This node type is special in that it's
1134 // always stack allocated and SelectionDAG does not manage its operands.
1135 // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
1136 // be so special.
1137 Op.setUser(this);
1138 Op.setInitial(X);
1139 NumOperands = 1;
1140 OperandList = &Op;
1141 }
1142 ~HandleSDNode();
1143
1144 const SDValue &getValue() const { return Op; }
1145};
1146
1147class AddrSpaceCastSDNode : public SDNode {
1148private:
1149 unsigned SrcAddrSpace;
1150 unsigned DestAddrSpace;
1151
1152public:
1153 AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
1154 unsigned SrcAS, unsigned DestAS);
1155
1156 unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
1157 unsigned getDestAddressSpace() const { return DestAddrSpace; }
1158
1159 static bool classof(const SDNode *N) {
1160 return N->getOpcode() == ISD::ADDRSPACECAST;
1161 }
1162};
1163
1164/// This is an abstract virtual class for memory operations.
1165class MemSDNode : public SDNode {
1166private:
1167 // VT of in-memory value.
1168 EVT MemoryVT;
1169
1170protected:
1171 /// Memory reference information.
1172 MachineMemOperand *MMO;
1173
1174public:
1175 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1176 EVT MemoryVT, MachineMemOperand *MMO);
1177
1178 bool readMem() const { return MMO->isLoad(); }
1179 bool writeMem() const { return MMO->isStore(); }
1180
1181 /// Returns alignment and volatility of the memory access
1182 unsigned getOriginalAlignment() const {
1183 return MMO->getBaseAlignment();
1184 }
1185 unsigned getAlignment() const {
1186 return MMO->getAlignment();
1187 }
1188
1189 /// Return the SubclassData value, without HasDebugValue. This contains an
1190 /// encoding of the volatile flag, as well as bits used by subclasses. This
1191 /// function should only be used to compute a FoldingSetNodeID value.
1192 /// The HasDebugValue bit is masked out because CSE map needs to match
1193 /// nodes with debug info with nodes without debug info.
1194 unsigned getRawSubclassData() const {
1195 uint16_t Data;
1196 union {
1197 char RawSDNodeBits[sizeof(uint16_t)];
1198 SDNodeBitfields SDNodeBits;
1199 };
1200 memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
1201 SDNodeBits.HasDebugValue = 0;
1202 memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
1203 return Data;
1204 }
1205
1206 bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
1207 bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
1208 bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
1209 bool isInvariant() const { return MemSDNodeBits.IsInvariant; }
1210
1211 // Returns the offset from the location of the access.
1212 int64_t getSrcValueOffset() const { return MMO->getOffset(); }
1213
1214 /// Returns the AA info that describes the dereference.
1215 AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }
1216
1217 /// Returns the Ranges that describes the dereference.
1218 const MDNode *getRanges() const { return MMO->getRanges(); }
1219
1220 /// Returns the synchronization scope ID for this memory operation.
1221 SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }
1222
1223 /// Return the atomic ordering requirements for this memory operation. For
1224 /// cmpxchg atomic operations, return the atomic ordering requirements when
1225 /// store occurs.
1226 AtomicOrdering getOrdering() const { return MMO->getOrdering(); }
1227
1228 /// Return the type of the in-memory value.
1229 EVT getMemoryVT() const { return MemoryVT; }
1230
1231 /// Return a MachineMemOperand object describing the memory
1232 /// reference performed by operation.
1233 MachineMemOperand *getMemOperand() const { return MMO; }
1234
1235 const MachinePointerInfo &getPointerInfo() const {
1236 return MMO->getPointerInfo();
1237 }
1238
1239 /// Return the address space for the associated pointer
1240 unsigned getAddressSpace() const {
1241 return getPointerInfo().getAddrSpace();
1242 }
1243
1244 /// Update this MemSDNode's MachineMemOperand information
1245 /// to reflect the alignment of NewMMO, if it has a greater alignment.
1246 /// This must only be used when the new alignment applies to all users of
1247 /// this MachineMemOperand.
1248 void refineAlignment(const MachineMemOperand *NewMMO) {
1249 MMO->refineAlignment(NewMMO);
1250 }
1251
1252 const SDValue &getChain() const { return getOperand(0); }
1253 const SDValue &getBasePtr() const {
1254 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1255 }
1256
1257 // Methods to support isa and dyn_cast
1258 static bool classof(const SDNode *N) {
1259 // For some targets, we lower some target intrinsics to a MemIntrinsicNode
1260 // with either an intrinsic or a target opcode.
1261 return N->getOpcode() == ISD::LOAD ||
1262 N->getOpcode() == ISD::STORE ||
1263 N->getOpcode() == ISD::PREFETCH ||
1264 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1265 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1266 N->getOpcode() == ISD::ATOMIC_SWAP ||
1267 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1268 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1269 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1270 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1271 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1272 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1273 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1274 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1275 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1276 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1277 N->getOpcode() == ISD::ATOMIC_LOAD ||
1278 N->getOpcode() == ISD::ATOMIC_STORE ||
1279 N->getOpcode() == ISD::MLOAD ||
1280 N->getOpcode() == ISD::MSTORE ||
1281 N->getOpcode() == ISD::MGATHER ||
1282 N->getOpcode() == ISD::MSCATTER ||
1283 N->isMemIntrinsic() ||
1284 N->isTargetMemoryOpcode();
1285 }
1286};
1287
1288/// This is an SDNode representing atomic operations.
1289class AtomicSDNode : public MemSDNode {
1290public:
1291 AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
1292 EVT MemVT, MachineMemOperand *MMO)
1293 : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {}
1294
1295 const SDValue &getBasePtr() const { return getOperand(1); }
1296 const SDValue &getVal() const { return getOperand(2); }
1297
1298 /// Returns true if this SDNode represents cmpxchg atomic operation, false
1299 /// otherwise.
1300 bool isCompareAndSwap() const {
1301 unsigned Op = getOpcode();
1302 return Op == ISD::ATOMIC_CMP_SWAP ||
1303 Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
1304 }
1305
1306 /// For cmpxchg atomic operations, return the atomic ordering requirements
1307 /// when store does not occur.
1308 AtomicOrdering getFailureOrdering() const {
1309 assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1309, __PRETTY_FUNCTION__))
;
1310 return MMO->getFailureOrdering();
1311 }
1312
1313 // Methods to support isa and dyn_cast
1314 static bool classof(const SDNode *N) {
1315 return N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
1316 N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
1317 N->getOpcode() == ISD::ATOMIC_SWAP ||
1318 N->getOpcode() == ISD::ATOMIC_LOAD_ADD ||
1319 N->getOpcode() == ISD::ATOMIC_LOAD_SUB ||
1320 N->getOpcode() == ISD::ATOMIC_LOAD_AND ||
1321 N->getOpcode() == ISD::ATOMIC_LOAD_OR ||
1322 N->getOpcode() == ISD::ATOMIC_LOAD_XOR ||
1323 N->getOpcode() == ISD::ATOMIC_LOAD_NAND ||
1324 N->getOpcode() == ISD::ATOMIC_LOAD_MIN ||
1325 N->getOpcode() == ISD::ATOMIC_LOAD_MAX ||
1326 N->getOpcode() == ISD::ATOMIC_LOAD_UMIN ||
1327 N->getOpcode() == ISD::ATOMIC_LOAD_UMAX ||
1328 N->getOpcode() == ISD::ATOMIC_LOAD ||
1329 N->getOpcode() == ISD::ATOMIC_STORE;
1330 }
1331};
1332
1333/// This SDNode is used for target intrinsics that touch
1334/// memory and need an associated MachineMemOperand. Its opcode may be
1335/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1336/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1337class MemIntrinsicSDNode : public MemSDNode {
1338public:
1339 MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
1340 SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
1341 : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
1342 SDNodeBits.IsMemIntrinsic = true;
1343 }
1344
1345 // Methods to support isa and dyn_cast
1346 static bool classof(const SDNode *N) {
1347 // We lower some target intrinsics to their target opcode
1348 // early a node with a target opcode can be of this class
1349 return N->isMemIntrinsic() ||
1350 N->getOpcode() == ISD::PREFETCH ||
1351 N->isTargetMemoryOpcode();
1352 }
1353};
1354
1355/// This SDNode is used to implement the code generator
1356/// support for the llvm IR shufflevector instruction. It combines elements
1357/// from two input vectors into a new input vector, with the selection and
1358/// ordering of elements determined by an array of integers, referred to as
1359/// the shuffle mask. For input vectors of width N, mask indices of 0..N-1
1360/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1361/// An index of -1 is treated as undef, such that the code generator may put
1362/// any value in the corresponding element of the result.
1363class ShuffleVectorSDNode : public SDNode {
1364 // The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
1365 // is freed when the SelectionDAG object is destroyed.
1366 const int *Mask;
1367
1368protected:
1369 friend class SelectionDAG;
1370
1371 ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
1372 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1373
1374public:
1375 ArrayRef<int> getMask() const {
1376 EVT VT = getValueType(0);
1377 return makeArrayRef(Mask, VT.getVectorNumElements());
1378 }
1379
1380 int getMaskElt(unsigned Idx) const {
1381 assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1381, __PRETTY_FUNCTION__))
;
1382 return Mask[Idx];
1383 }
1384
1385 bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
1386
1387 int getSplatIndex() const {
1388 assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1388, __PRETTY_FUNCTION__))
;
1389 EVT VT = getValueType(0);
1390 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
1391 if (Mask[i] >= 0)
1392 return Mask[i];
1393 }
1394 llvm_unreachable("Splat with all undef indices?")::llvm::llvm_unreachable_internal("Splat with all undef indices?"
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1394)
;
1395 }
1396
1397 static bool isSplatMask(const int *Mask, EVT VT);
1398
1399 /// Change values in a shuffle permute mask assuming
1400 /// the two vector operands have swapped position.
1401 static void commuteMask(MutableArrayRef<int> Mask) {
1402 unsigned NumElems = Mask.size();
1403 for (unsigned i = 0; i != NumElems; ++i) {
1404 int idx = Mask[i];
1405 if (idx < 0)
1406 continue;
1407 else if (idx < (int)NumElems)
1408 Mask[i] = idx + NumElems;
1409 else
1410 Mask[i] = idx - NumElems;
1411 }
1412 }
1413
1414 static bool classof(const SDNode *N) {
1415 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
1416 }
1417};
1418
1419class ConstantSDNode : public SDNode {
1420 friend class SelectionDAG;
1421
1422 const ConstantInt *Value;
1423
1424 ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val,
1425 const DebugLoc &DL, EVT VT)
1426 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL,
1427 getSDVTList(VT)),
1428 Value(val) {
1429 ConstantSDNodeBits.IsOpaque = isOpaque;
1430 }
1431
1432public:
1433 const ConstantInt *getConstantIntValue() const { return Value; }
1434 const APInt &getAPIntValue() const { return Value->getValue(); }
1435 uint64_t getZExtValue() const { return Value->getZExtValue(); }
1436 int64_t getSExtValue() const { return Value->getSExtValue(); }
1437 uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
1438 return Value->getLimitedValue(Limit);
1439 }
1440
1441 bool isOne() const { return Value->isOne(); }
1442 bool isNullValue() const { return Value->isZero(); }
1443 bool isAllOnesValue() const { return Value->isMinusOne(); }
1444
1445 bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
1446
1447 static bool classof(const SDNode *N) {
1448 return N->getOpcode() == ISD::Constant ||
1449 N->getOpcode() == ISD::TargetConstant;
1450 }
1451};
1452
1453uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
1454 return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1455}
1456
1457class ConstantFPSDNode : public SDNode {
1458 friend class SelectionDAG;
1459
1460 const ConstantFP *Value;
1461
1462 ConstantFPSDNode(bool isTarget, const ConstantFP *val, const DebugLoc &DL,
1463 EVT VT)
1464 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, DL,
1465 getSDVTList(VT)),
1466 Value(val) {}
1467
1468public:
1469 const APFloat& getValueAPF() const { return Value->getValueAPF(); }
1470 const ConstantFP *getConstantFPValue() const { return Value; }
1471
1472 /// Return true if the value is positive or negative zero.
1473 bool isZero() const { return Value->isZero(); }
1474
1475 /// Return true if the value is a NaN.
1476 bool isNaN() const { return Value->isNaN(); }
1477
1478 /// Return true if the value is an infinity
1479 bool isInfinity() const { return Value->isInfinity(); }
1480
1481 /// Return true if the value is negative.
1482 bool isNegative() const { return Value->isNegative(); }
1483
1484 /// We don't rely on operator== working on double values, as
1485 /// it returns true for things that are clearly not equal, like -0.0 and 0.0.
1486 /// As such, this method can be used to do an exact bit-for-bit comparison of
1487 /// two floating point values.
1488
1489 /// We leave the version with the double argument here because it's just so
1490 /// convenient to write "2.0" and the like. Without this function we'd
1491 /// have to duplicate its logic everywhere it's called.
1492 bool isExactlyValue(double V) const {
1493 return Value->getValueAPF().isExactlyValue(V);
1494 }
1495 bool isExactlyValue(const APFloat& V) const;
1496
1497 static bool isValueValidForType(EVT VT, const APFloat& Val);
1498
1499 static bool classof(const SDNode *N) {
1500 return N->getOpcode() == ISD::ConstantFP ||
1501 N->getOpcode() == ISD::TargetConstantFP;
1502 }
1503};
1504
1505/// Returns true if \p V is a constant integer zero.
1506bool isNullConstant(SDValue V);
1507
1508/// Returns true if \p V is an FP constant with a value of positive zero.
1509bool isNullFPConstant(SDValue V);
1510
1511/// Returns true if \p V is an integer constant with all bits set.
1512bool isAllOnesConstant(SDValue V);
1513
1514/// Returns true if \p V is a constant integer one.
1515bool isOneConstant(SDValue V);
1516
1517/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1518/// constant is canonicalized to be operand 1.
1519bool isBitwiseNot(SDValue V);
1520
1521/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1522ConstantSDNode *isConstOrConstSplat(SDValue V);
1523
1524/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1525ConstantFPSDNode *isConstOrConstSplatFP(SDValue V);
1526
1527class GlobalAddressSDNode : public SDNode {
1528 friend class SelectionDAG;
1529
1530 const GlobalValue *TheGlobal;
1531 int64_t Offset;
1532 unsigned char TargetFlags;
1533
1534 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
1535 const GlobalValue *GA, EVT VT, int64_t o,
1536 unsigned char TargetFlags);
1537
1538public:
1539 const GlobalValue *getGlobal() const { return TheGlobal; }
1540 int64_t getOffset() const { return Offset; }
1541 unsigned char getTargetFlags() const { return TargetFlags; }
1542 // Return the address space this GlobalAddress belongs to.
1543 unsigned getAddressSpace() const;
1544
1545 static bool classof(const SDNode *N) {
1546 return N->getOpcode() == ISD::GlobalAddress ||
1547 N->getOpcode() == ISD::TargetGlobalAddress ||
1548 N->getOpcode() == ISD::GlobalTLSAddress ||
1549 N->getOpcode() == ISD::TargetGlobalTLSAddress;
1550 }
1551};
1552
1553class FrameIndexSDNode : public SDNode {
1554 friend class SelectionDAG;
1555
1556 int FI;
1557
1558 FrameIndexSDNode(int fi, EVT VT, bool isTarg)
1559 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
1560 0, DebugLoc(), getSDVTList(VT)), FI(fi) {
1561 }
1562
1563public:
1564 int getIndex() const { return FI; }
1565
1566 static bool classof(const SDNode *N) {
1567 return N->getOpcode() == ISD::FrameIndex ||
1568 N->getOpcode() == ISD::TargetFrameIndex;
1569 }
1570};
1571
1572class JumpTableSDNode : public SDNode {
1573 friend class SelectionDAG;
1574
1575 int JTI;
1576 unsigned char TargetFlags;
1577
1578 JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF)
1579 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
1580 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
1581 }
1582
1583public:
1584 int getIndex() const { return JTI; }
1585 unsigned char getTargetFlags() const { return TargetFlags; }
1586
1587 static bool classof(const SDNode *N) {
1588 return N->getOpcode() == ISD::JumpTable ||
1589 N->getOpcode() == ISD::TargetJumpTable;
1590 }
1591};
1592
1593class ConstantPoolSDNode : public SDNode {
1594 friend class SelectionDAG;
1595
1596 union {
1597 const Constant *ConstVal;
1598 MachineConstantPoolValue *MachineCPVal;
1599 } Val;
1600 int Offset; // It's a MachineConstantPoolValue if top bit is set.
1601 unsigned Alignment; // Minimum alignment requirement of CP (not log2 value).
1602 unsigned char TargetFlags;
1603
1604 ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
1605 unsigned Align, unsigned char TF)
1606 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1607 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1608 TargetFlags(TF) {
1609 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1609, __PRETTY_FUNCTION__))
;
1610 Val.ConstVal = c;
1611 }
1612
1613 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1614 EVT VT, int o, unsigned Align, unsigned char TF)
1615 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
1616 DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
1617 TargetFlags(TF) {
1618 assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1618, __PRETTY_FUNCTION__))
;
1619 Val.MachineCPVal = v;
1620 Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
1621 }
1622
1623public:
1624 bool isMachineConstantPoolEntry() const {
1625 return Offset < 0;
1626 }
1627
1628 const Constant *getConstVal() const {
1629 assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1629, __PRETTY_FUNCTION__))
;
1630 return Val.ConstVal;
1631 }
1632
1633 MachineConstantPoolValue *getMachineCPVal() const {
1634 assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1634, __PRETTY_FUNCTION__))
;
1635 return Val.MachineCPVal;
1636 }
1637
1638 int getOffset() const {
1639 return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
1640 }
1641
1642 // Return the alignment of this constant pool object, which is either 0 (for
1643 // default alignment) or the desired value.
1644 unsigned getAlignment() const { return Alignment; }
1645 unsigned char getTargetFlags() const { return TargetFlags; }
1646
1647 Type *getType() const;
1648
1649 static bool classof(const SDNode *N) {
1650 return N->getOpcode() == ISD::ConstantPool ||
1651 N->getOpcode() == ISD::TargetConstantPool;
1652 }
1653};
1654
1655/// Completely target-dependent object reference.
1656class TargetIndexSDNode : public SDNode {
1657 friend class SelectionDAG;
1658
1659 unsigned char TargetFlags;
1660 int Index;
1661 int64_t Offset;
1662
1663public:
1664 TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned char TF)
1665 : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
1666 TargetFlags(TF), Index(Idx), Offset(Ofs) {}
1667
1668 unsigned char getTargetFlags() const { return TargetFlags; }
1669 int getIndex() const { return Index; }
1670 int64_t getOffset() const { return Offset; }
1671
1672 static bool classof(const SDNode *N) {
1673 return N->getOpcode() == ISD::TargetIndex;
1674 }
1675};
1676
1677class BasicBlockSDNode : public SDNode {
1678 friend class SelectionDAG;
1679
1680 MachineBasicBlock *MBB;
1681
1682 /// Debug info is meaningful and potentially useful here, but we create
1683 /// blocks out of order when they're jumped to, which makes it a bit
1684 /// harder. Let's see if we need it first.
1685 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
1686 : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
1687 {}
1688
1689public:
1690 MachineBasicBlock *getBasicBlock() const { return MBB; }
1691
1692 static bool classof(const SDNode *N) {
1693 return N->getOpcode() == ISD::BasicBlock;
1694 }
1695};
1696
1697/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1698class BuildVectorSDNode : public SDNode {
1699public:
1700 // These are constructed as SDNodes and then cast to BuildVectorSDNodes.
1701 explicit BuildVectorSDNode() = delete;
1702
1703 /// Check if this is a constant splat, and if so, find the
1704 /// smallest element size that splats the vector. If MinSplatBits is
1705 /// nonzero, the element size must be at least that large. Note that the
1706 /// splat element may be the entire vector (i.e., a one element vector).
1707 /// Returns the splat element value in SplatValue. Any undefined bits in
1708 /// that value are zero, and the corresponding bits in the SplatUndef mask
1709 /// are set. The SplatBitSize value is set to the splat element size in
1710 /// bits. HasAnyUndefs is set to true if any bits in the vector are
1711 /// undefined. isBigEndian describes the endianness of the target.
1712 bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
1713 unsigned &SplatBitSize, bool &HasAnyUndefs,
1714 unsigned MinSplatBits = 0,
1715 bool isBigEndian = false) const;
1716
1717 /// \brief Returns the splatted value or a null value if this is not a splat.
1718 ///
1719 /// If passed a non-null UndefElements bitvector, it will resize it to match
1720 /// the vector width and set the bits where elements are undef.
1721 SDValue getSplatValue(BitVector *UndefElements = nullptr) const;
1722
1723 /// \brief Returns the splatted constant or null if this is not a constant
1724 /// splat.
1725 ///
1726 /// If passed a non-null UndefElements bitvector, it will resize it to match
1727 /// the vector width and set the bits where elements are undef.
1728 ConstantSDNode *
1729 getConstantSplatNode(BitVector *UndefElements = nullptr) const;
1730
1731 /// \brief Returns the splatted constant FP or null if this is not a constant
1732 /// FP splat.
1733 ///
1734 /// If passed a non-null UndefElements bitvector, it will resize it to match
1735 /// the vector width and set the bits where elements are undef.
1736 ConstantFPSDNode *
1737 getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;
1738
1739 /// \brief If this is a constant FP splat and the splatted constant FP is an
1740 /// exact power or 2, return the log base 2 integer value. Otherwise,
1741 /// return -1.
1742 ///
1743 /// The BitWidth specifies the necessary bit precision.
1744 int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
1745 uint32_t BitWidth) const;
1746
1747 bool isConstant() const;
1748
1749 static bool classof(const SDNode *N) {
1750 return N->getOpcode() == ISD::BUILD_VECTOR;
1751 }
1752};
1753
1754/// An SDNode that holds an arbitrary LLVM IR Value. This is
1755/// used when the SelectionDAG needs to make a simple reference to something
1756/// in the LLVM IR representation.
1757///
1758class SrcValueSDNode : public SDNode {
1759 friend class SelectionDAG;
1760
1761 const Value *V;
1762
1763 /// Create a SrcValue for a general value.
1764 explicit SrcValueSDNode(const Value *v)
1765 : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}
1766
1767public:
1768 /// Return the contained Value.
1769 const Value *getValue() const { return V; }
1770
1771 static bool classof(const SDNode *N) {
1772 return N->getOpcode() == ISD::SRCVALUE;
1773 }
1774};
1775
1776class MDNodeSDNode : public SDNode {
1777 friend class SelectionDAG;
1778
1779 const MDNode *MD;
1780
1781 explicit MDNodeSDNode(const MDNode *md)
1782 : SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
1783 {}
1784
1785public:
1786 const MDNode *getMD() const { return MD; }
1787
1788 static bool classof(const SDNode *N) {
1789 return N->getOpcode() == ISD::MDNODE_SDNODE;
1790 }
1791};
1792
1793class RegisterSDNode : public SDNode {
1794 friend class SelectionDAG;
1795
1796 unsigned Reg;
1797
1798 RegisterSDNode(unsigned reg, EVT VT)
1799 : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}
1800
1801public:
1802 unsigned getReg() const { return Reg; }
1803
1804 static bool classof(const SDNode *N) {
1805 return N->getOpcode() == ISD::Register;
1806 }
1807};
1808
1809class RegisterMaskSDNode : public SDNode {
1810 friend class SelectionDAG;
1811
1812 // The memory for RegMask is not owned by the node.
1813 const uint32_t *RegMask;
1814
1815 RegisterMaskSDNode(const uint32_t *mask)
1816 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
1817 RegMask(mask) {}
1818
1819public:
1820 const uint32_t *getRegMask() const { return RegMask; }
1821
1822 static bool classof(const SDNode *N) {
1823 return N->getOpcode() == ISD::RegisterMask;
1824 }
1825};
1826
1827class BlockAddressSDNode : public SDNode {
1828 friend class SelectionDAG;
1829
1830 const BlockAddress *BA;
1831 int64_t Offset;
1832 unsigned char TargetFlags;
1833
1834 BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
1835 int64_t o, unsigned char Flags)
1836 : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
1837 BA(ba), Offset(o), TargetFlags(Flags) {}
1838
1839public:
1840 const BlockAddress *getBlockAddress() const { return BA; }
1841 int64_t getOffset() const { return Offset; }
1842 unsigned char getTargetFlags() const { return TargetFlags; }
1843
1844 static bool classof(const SDNode *N) {
1845 return N->getOpcode() == ISD::BlockAddress ||
1846 N->getOpcode() == ISD::TargetBlockAddress;
1847 }
1848};
1849
1850class LabelSDNode : public SDNode {
1851 friend class SelectionDAG;
1852
1853 MCSymbol *Label;
1854
1855 LabelSDNode(unsigned Order, const DebugLoc &dl, MCSymbol *L)
1856 : SDNode(ISD::EH_LABEL, Order, dl, getSDVTList(MVT::Other)), Label(L) {}
1857
1858public:
1859 MCSymbol *getLabel() const { return Label; }
1860
1861 static bool classof(const SDNode *N) {
1862 return N->getOpcode() == ISD::EH_LABEL ||
1863 N->getOpcode() == ISD::ANNOTATION_LABEL;
1864 }
1865};
1866
1867class ExternalSymbolSDNode : public SDNode {
1868 friend class SelectionDAG;
1869
1870 const char *Symbol;
1871 unsigned char TargetFlags;
1872
1873 ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EVT VT)
1874 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
1875 0, DebugLoc(), getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) {}
1876
1877public:
1878 const char *getSymbol() const { return Symbol; }
1879 unsigned char getTargetFlags() const { return TargetFlags; }
1880
1881 static bool classof(const SDNode *N) {
1882 return N->getOpcode() == ISD::ExternalSymbol ||
1883 N->getOpcode() == ISD::TargetExternalSymbol;
1884 }
1885};
1886
1887class MCSymbolSDNode : public SDNode {
1888 friend class SelectionDAG;
1889
1890 MCSymbol *Symbol;
1891
1892 MCSymbolSDNode(MCSymbol *Symbol, EVT VT)
1893 : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {}
1894
1895public:
1896 MCSymbol *getMCSymbol() const { return Symbol; }
1897
1898 static bool classof(const SDNode *N) {
1899 return N->getOpcode() == ISD::MCSymbol;
1900 }
1901};
1902
1903class CondCodeSDNode : public SDNode {
1904 friend class SelectionDAG;
1905
1906 ISD::CondCode Condition;
1907
1908 explicit CondCodeSDNode(ISD::CondCode Cond)
1909 : SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
1910 Condition(Cond) {}
1911
1912public:
1913 ISD::CondCode get() const { return Condition; }
1914
1915 static bool classof(const SDNode *N) {
1916 return N->getOpcode() == ISD::CONDCODE;
1917 }
1918};
1919
1920/// This class is used to represent EVT's, which are used
1921/// to parameterize some operations.
1922class VTSDNode : public SDNode {
1923 friend class SelectionDAG;
1924
1925 EVT ValueType;
1926
1927 explicit VTSDNode(EVT VT)
1928 : SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
1929 ValueType(VT) {}
1930
1931public:
1932 EVT getVT() const { return ValueType; }
1933
1934 static bool classof(const SDNode *N) {
1935 return N->getOpcode() == ISD::VALUETYPE;
1936 }
1937};
1938
1939/// Base class for LoadSDNode and StoreSDNode
1940class LSBaseSDNode : public MemSDNode {
1941public:
1942 LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, const DebugLoc &dl,
1943 SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
1944 MachineMemOperand *MMO)
1945 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
1946 LSBaseSDNodeBits.AddressingMode = AM;
1947 assert(getAddressingMode() == AM && "Value truncated")((getAddressingMode() == AM && "Value truncated") ? static_cast
<void> (0) : __assert_fail ("getAddressingMode() == AM && \"Value truncated\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1947, __PRETTY_FUNCTION__))
;
1948 }
1949
1950 const SDValue &getOffset() const {
1951 return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
1952 }
1953
1954 /// Return the addressing mode for this load or store:
1955 /// unindexed, pre-inc, pre-dec, post-inc, or post-dec.
1956 ISD::MemIndexedMode getAddressingMode() const {
1957 return static_cast<ISD::MemIndexedMode>(LSBaseSDNodeBits.AddressingMode);
1958 }
1959
1960 /// Return true if this is a pre/post inc/dec load/store.
1961 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1962
1963 /// Return true if this is NOT a pre/post inc/dec load/store.
1964 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
1965
1966 static bool classof(const SDNode *N) {
1967 return N->getOpcode() == ISD::LOAD ||
1968 N->getOpcode() == ISD::STORE;
1969 }
1970};
1971
1972/// This class is used to represent ISD::LOAD nodes.
1973class LoadSDNode : public LSBaseSDNode {
1974 friend class SelectionDAG;
1975
1976 LoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
1977 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
1978 MachineMemOperand *MMO)
1979 : LSBaseSDNode(ISD::LOAD, Order, dl, VTs, AM, MemVT, MMO) {
1980 LoadSDNodeBits.ExtTy = ETy;
1981 assert(readMem() && "Load MachineMemOperand is not a load!")((readMem() && "Load MachineMemOperand is not a load!"
) ? static_cast<void> (0) : __assert_fail ("readMem() && \"Load MachineMemOperand is not a load!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1981, __PRETTY_FUNCTION__))
;
1982 assert(!writeMem() && "Load MachineMemOperand is a store!")((!writeMem() && "Load MachineMemOperand is a store!"
) ? static_cast<void> (0) : __assert_fail ("!writeMem() && \"Load MachineMemOperand is a store!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1982, __PRETTY_FUNCTION__))
;
1983 }
1984
1985public:
1986 /// Return whether this is a plain node,
1987 /// or one of the varieties of value-extending loads.
1988 ISD::LoadExtType getExtensionType() const {
1989 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
1990 }
1991
1992 const SDValue &getBasePtr() const { return getOperand(1); }
1993 const SDValue &getOffset() const { return getOperand(2); }
1994
1995 static bool classof(const SDNode *N) {
1996 return N->getOpcode() == ISD::LOAD;
1997 }
1998};
1999
2000/// This class is used to represent ISD::STORE nodes.
2001class StoreSDNode : public LSBaseSDNode {
2002 friend class SelectionDAG;
2003
2004 StoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2005 ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,
2006 MachineMemOperand *MMO)
2007 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2008 StoreSDNodeBits.IsTruncating = isTrunc;
2009 assert(!readMem() && "Store MachineMemOperand is a load!")((!readMem() && "Store MachineMemOperand is a load!")
? static_cast<void> (0) : __assert_fail ("!readMem() && \"Store MachineMemOperand is a load!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2009, __PRETTY_FUNCTION__))
;
2010 assert(writeMem() && "Store MachineMemOperand is not a store!")((writeMem() && "Store MachineMemOperand is not a store!"
) ? static_cast<void> (0) : __assert_fail ("writeMem() && \"Store MachineMemOperand is not a store!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2010, __PRETTY_FUNCTION__))
;
2011 }
2012
2013public:
2014 /// Return true if the op does a truncation before store.
2015 /// For integers this is the same as doing a TRUNCATE and storing the result.
2016 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2017 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2018
2019 const SDValue &getValue() const { return getOperand(1); }
2020 const SDValue &getBasePtr() const { return getOperand(2); }
2021 const SDValue &getOffset() const { return getOperand(3); }
2022
2023 static bool classof(const SDNode *N) {
2024 return N->getOpcode() == ISD::STORE;
2025 }
2026};
2027
2028/// This base class is used to represent MLOAD and MSTORE nodes
2029class MaskedLoadStoreSDNode : public MemSDNode {
2030public:
2031 friend class SelectionDAG;
2032
2033 MaskedLoadStoreSDNode(ISD::NodeType NodeTy, unsigned Order,
2034 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2035 MachineMemOperand *MMO)
2036 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
2037
2038 // In the both nodes address is Op1, mask is Op2:
2039 // MaskedLoadSDNode (Chain, ptr, mask, src0), src0 is a passthru value
2040 // MaskedStoreSDNode (Chain, ptr, mask, data)
2041 // Mask is a vector of i1 elements
2042 const SDValue &getBasePtr() const { return getOperand(1); }
2043 const SDValue &getMask() const { return getOperand(2); }
2044
2045 static bool classof(const SDNode *N) {
2046 return N->getOpcode() == ISD::MLOAD ||
2047 N->getOpcode() == ISD::MSTORE;
2048 }
2049};
2050
2051/// This class is used to represent an MLOAD node
2052class MaskedLoadSDNode : public MaskedLoadStoreSDNode {
2053public:
2054 friend class SelectionDAG;
2055
2056 MaskedLoadSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2057 ISD::LoadExtType ETy, bool IsExpanding, EVT MemVT,
2058 MachineMemOperand *MMO)
2059 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, MemVT, MMO) {
2060 LoadSDNodeBits.ExtTy = ETy;
2061 LoadSDNodeBits.IsExpanding = IsExpanding;
2062 }
2063
2064 ISD::LoadExtType getExtensionType() const {
2065 return static_cast<ISD::LoadExtType>(LoadSDNodeBits.ExtTy);
2066 }
2067
2068 const SDValue &getSrc0() const { return getOperand(3); }
2069 static bool classof(const SDNode *N) {
2070 return N->getOpcode() == ISD::MLOAD;
2071 }
2072
2073 bool isExpandingLoad() const { return LoadSDNodeBits.IsExpanding; }
2074};
2075
2076/// This class is used to represent an MSTORE node
2077class MaskedStoreSDNode : public MaskedLoadStoreSDNode {
2078public:
2079 friend class SelectionDAG;
2080
2081 MaskedStoreSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2082 bool isTrunc, bool isCompressing, EVT MemVT,
2083 MachineMemOperand *MMO)
2084 : MaskedLoadStoreSDNode(ISD::MSTORE, Order, dl, VTs, MemVT, MMO) {
2085 StoreSDNodeBits.IsTruncating = isTrunc;
2086 StoreSDNodeBits.IsCompressing = isCompressing;
2087 }
2088
2089 /// Return true if the op does a truncation before store.
2090 /// For integers this is the same as doing a TRUNCATE and storing the result.
2091 /// For floats, it is the same as doing an FP_ROUND and storing the result.
2092 bool isTruncatingStore() const { return StoreSDNodeBits.IsTruncating; }
2093
2094 /// Returns true if the op does a compression to the vector before storing.
2095 /// The node contiguously stores the active elements (integers or floats)
2096 /// in src (those with their respective bit set in writemask k) to unaligned
2097 /// memory at base_addr.
2098 bool isCompressingStore() const { return StoreSDNodeBits.IsCompressing; }
2099
2100 const SDValue &getValue() const { return getOperand(3); }
2101
2102 static bool classof(const SDNode *N) {
2103 return N->getOpcode() == ISD::MSTORE;
2104 }
2105};
2106
2107/// This is a base class used to represent
2108/// MGATHER and MSCATTER nodes
2109///
2110class MaskedGatherScatterSDNode : public MemSDNode {
2111public:
2112 friend class SelectionDAG;
2113
2114 MaskedGatherScatterSDNode(ISD::NodeType NodeTy, unsigned Order,
2115 const DebugLoc &dl, SDVTList VTs, EVT MemVT,
2116 MachineMemOperand *MMO)
2117 : MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {}
2118
2119 // In the both nodes address is Op1, mask is Op2:
2120 // MaskedGatherSDNode (Chain, src0, mask, base, index), src0 is a passthru value
2121 // MaskedScatterSDNode (Chain, value, mask, base, index)
2122 // Mask is a vector of i1 elements
2123 const SDValue &getBasePtr() const { return getOperand(3); }
2124 const SDValue &getIndex() const { return getOperand(4); }
2125 const SDValue &getMask() const { return getOperand(2); }
2126 const SDValue &getValue() const { return getOperand(1); }
2127
2128 static bool classof(const SDNode *N) {
2129 return N->getOpcode() == ISD::MGATHER ||
2130 N->getOpcode() == ISD::MSCATTER;
2131 }
2132};
2133
2134/// This class is used to represent an MGATHER node
2135///
2136class MaskedGatherSDNode : public MaskedGatherScatterSDNode {
2137public:
2138 friend class SelectionDAG;
2139
2140 MaskedGatherSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2141 EVT MemVT, MachineMemOperand *MMO)
2142 : MaskedGatherScatterSDNode(ISD::MGATHER, Order, dl, VTs, MemVT, MMO) {}
2143
2144 static bool classof(const SDNode *N) {
2145 return N->getOpcode() == ISD::MGATHER;
2146 }
2147};
2148
2149/// This class is used to represent an MSCATTER node
2150///
2151class MaskedScatterSDNode : public MaskedGatherScatterSDNode {
2152public:
2153 friend class SelectionDAG;
2154
2155 MaskedScatterSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs,
2156 EVT MemVT, MachineMemOperand *MMO)
2157 : MaskedGatherScatterSDNode(ISD::MSCATTER, Order, dl, VTs, MemVT, MMO) {}
2158
2159 static bool classof(const SDNode *N) {
2160 return N->getOpcode() == ISD::MSCATTER;
2161 }
2162};
2163
2164/// An SDNode that represents everything that will be needed
2165/// to construct a MachineInstr. These nodes are created during the
2166/// instruction selection proper phase.
2167class MachineSDNode : public SDNode {
2168public:
2169 using mmo_iterator = MachineMemOperand **;
2170
2171private:
2172 friend class SelectionDAG;
2173
2174 MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, SDVTList VTs)
2175 : SDNode(Opc, Order, DL, VTs) {}
2176
2177 /// Memory reference descriptions for this instruction.
2178 mmo_iterator MemRefs = nullptr;
2179 mmo_iterator MemRefsEnd = nullptr;
2180
2181public:
2182 mmo_iterator memoperands_begin() const { return MemRefs; }
2183 mmo_iterator memoperands_end() const { return MemRefsEnd; }
2184 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
2185
2186 /// Assign this MachineSDNodes's memory reference descriptor
2187 /// list. This does not transfer ownership.
2188 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
2189 for (mmo_iterator MMI = NewMemRefs, MME = NewMemRefsEnd; MMI != MME; ++MMI)
2190 assert(*MMI && "Null mem ref detected!")((*MMI && "Null mem ref detected!") ? static_cast<
void> (0) : __assert_fail ("*MMI && \"Null mem ref detected!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2190, __PRETTY_FUNCTION__))
;
2191 MemRefs = NewMemRefs;
2192 MemRefsEnd = NewMemRefsEnd;
2193 }
2194
2195 static bool classof(const SDNode *N) {
2196 return N->isMachineOpcode();
2197 }
2198};
2199
2200class SDNodeIterator : public std::iterator<std::forward_iterator_tag,
2201 SDNode, ptrdiff_t> {
2202 const SDNode *Node;
2203 unsigned Operand;
2204
2205 SDNodeIterator(const SDNode *N, unsigned Op) : Node(N), Operand(Op) {}
2206
2207public:
2208 bool operator==(const SDNodeIterator& x) const {
2209 return Operand == x.Operand;
2210 }
2211 bool operator!=(const SDNodeIterator& x) const { return !operator==(x); }
2212
2213 pointer operator*() const {
2214 return Node->getOperand(Operand).getNode();
2215 }
2216 pointer operator->() const { return operator*(); }
2217
2218 SDNodeIterator& operator++() { // Preincrement
2219 ++Operand;
2220 return *this;
2221 }
2222 SDNodeIterator operator++(int) { // Postincrement
2223 SDNodeIterator tmp = *this; ++*this; return tmp;
2224 }
2225 size_t operator-(SDNodeIterator Other) const {
2226 assert(Node == Other.Node &&((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2227, __PRETTY_FUNCTION__))
2227 "Cannot compare iterators of two different nodes!")((Node == Other.Node && "Cannot compare iterators of two different nodes!"
) ? static_cast<void> (0) : __assert_fail ("Node == Other.Node && \"Cannot compare iterators of two different nodes!\""
, "/build/llvm-toolchain-snapshot-6.0~svn318211/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2227, __PRETTY_FUNCTION__))
;
2228 return Operand - Other.Operand;
2229 }
2230
2231 static SDNodeIterator begin(const SDNode *N) { return SDNodeIterator(N, 0); }
2232 static SDNodeIterator end (const SDNode *N) {
2233 return SDNodeIterator(N, N->getNumOperands());
2234 }
2235
2236 unsigned getOperand() const { return Operand; }
2237 const SDNode *getNode() const { return Node; }
2238};
2239
2240template <> struct GraphTraits<SDNode*> {
2241 using NodeRef = SDNode *;
2242 using ChildIteratorType = SDNodeIterator;
2243
2244 static NodeRef getEntryNode(SDNode *N) { return N; }
2245
2246 static ChildIteratorType child_begin(NodeRef N) {
2247 return SDNodeIterator::begin(N);
2248 }
2249
2250 static ChildIteratorType child_end(NodeRef N) {
2251 return SDNodeIterator::end(N);
2252 }
2253};
2254
2255/// A representation of the largest SDNode, for use in sizeof().
2256///
2257/// This needs to be a union because the largest node differs on 32 bit systems
2258/// with 4 and 8 byte pointer alignment, respectively.
2259using LargestSDNode = AlignedCharArrayUnion<AtomicSDNode, TargetIndexSDNode,
2260 BlockAddressSDNode,
2261 GlobalAddressSDNode>;
2262
2263/// The SDNode class with the greatest alignment requirement.
2264using MostAlignedSDNode = GlobalAddressSDNode;
2265
2266namespace ISD {
2267
2268 /// Returns true if the specified node is a non-extending and unindexed load.
2269 inline bool isNormalLoad(const SDNode *N) {
2270 const LoadSDNode *Ld = dyn_cast<LoadSDNode>(N);
2271 return Ld && Ld->getExtensionType() == ISD::NON_EXTLOAD &&
2272 Ld->getAddressingMode() == ISD::UNINDEXED;
2273 }
2274
2275 /// Returns true if the specified node is a non-extending load.
2276 inline bool isNON_EXTLoad(const SDNode *N) {
2277 return isa<LoadSDNode>(N) &&
2278 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
2279 }
2280
2281 /// Returns true if the specified node is a EXTLOAD.
2282 inline bool isEXTLoad(const SDNode *N) {
2283 return isa<LoadSDNode>(N) &&
2284 cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
2285 }
2286
2287 /// Returns true if the specified node is a SEXTLOAD.
2288 inline bool isSEXTLoad(const SDNode *N) {
2289 return isa<LoadSDNode>(N) &&
2290 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
2291 }
2292
2293 /// Returns true if the specified node is a ZEXTLOAD.
2294 inline bool isZEXTLoad(const SDNode *N) {
2295 return isa<LoadSDNode>(N) &&
2296 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
2297 }
2298
2299 /// Returns true if the specified node is an unindexed load.
2300 inline bool isUNINDEXEDLoad(const SDNode *N) {
2301 return isa<LoadSDNode>(N) &&
2302 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2303 }
2304
2305 /// Returns true if the specified node is a non-truncating
2306 /// and unindexed store.
2307 inline bool isNormalStore(const SDNode *N) {
2308 const StoreSDNode *St = dyn_cast<StoreSDNode>(N);
2309 return St && !St->isTruncatingStore() &&
2310 St->getAddressingMode() == ISD::UNINDEXED;
2311 }
2312
2313 /// Returns true if the specified node is a non-truncating store.
2314 inline bool isNON_TRUNCStore(const SDNode *N) {
2315 return isa<StoreSDNode>(N) && !cast<StoreSDNode>(N)->isTruncatingStore();
2316 }
2317
2318 /// Returns true if the specified node is a truncating store.
2319 inline bool isTRUNCStore(const SDNode *N) {
2320 return isa<StoreSDNode>(N) && cast<StoreSDNode>(N)->isTruncatingStore();
2321 }
2322
2323 /// Returns true if the specified node is an unindexed store.
2324 inline bool isUNINDEXEDStore(const SDNode *N) {
2325 return isa<StoreSDNode>(N) &&
2326 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2327 }
2328
2329} // end namespace ISD
2330
2331} // end namespace llvm
2332
2333#endif // LLVM_CODEGEN_SELECTIONDAGNODES_H