/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h

Bug Summary

File:	include/llvm/CodeGen/SelectionDAGNodes.h
Warning:	line 1163, column 10 Called C++ object pointer is null

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonISelLowering.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn374814/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-10~svn374814/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn374814/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn374814/build-llvm/lib/Target/Hexagon -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn374814=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-15-035155-28452-1 -x c++ /build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp

/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp

→

1//===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements the interfaces that Hexagon uses to lower LLVM code
10// into a selection DAG.
11//
12//===----------------------------------------------------------------------===//

14#include "HexagonISelLowering.h"
15#include "Hexagon.h"
16#include "HexagonMachineFunctionInfo.h"
17#include "HexagonRegisterInfo.h"
18#include "HexagonSubtarget.h"
19#include "HexagonTargetMachine.h"
20#include "HexagonTargetObjectFile.h"
21#include "llvm/ADT/APInt.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/ADT/StringSwitch.h"
25#include "llvm/CodeGen/CallingConvLower.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineMemOperand.h"
29#include "llvm/CodeGen/MachineRegisterInfo.h"
30#include "llvm/CodeGen/RuntimeLibcalls.h"
31#include "llvm/CodeGen/SelectionDAG.h"
32#include "llvm/CodeGen/TargetCallingConv.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/BasicBlock.h"
35#include "llvm/IR/CallingConv.h"
36#include "llvm/IR/DataLayout.h"
37#include "llvm/IR/DerivedTypes.h"
38#include "llvm/IR/Function.h"
39#include "llvm/IR/GlobalValue.h"
40#include "llvm/IR/InlineAsm.h"
41#include "llvm/IR/Instructions.h"
42#include "llvm/IR/Intrinsics.h"
43#include "llvm/IR/IntrinsicInst.h"
44#include "llvm/IR/Module.h"
45#include "llvm/IR/Type.h"
46#include "llvm/IR/Value.h"
47#include "llvm/MC/MCRegisterInfo.h"
48#include "llvm/Support/Casting.h"
49#include "llvm/Support/CodeGen.h"
50#include "llvm/Support/CommandLine.h"
51#include "llvm/Support/Debug.h"
52#include "llvm/Support/ErrorHandling.h"
53#include "llvm/Support/MathExtras.h"
54#include "llvm/Support/raw_ostream.h"
55#include "llvm/Target/TargetMachine.h"
56#include <algorithm>
57#include <cassert>
58#include <cstddef>
59#include <cstdint>
60#include <limits>
61#include <utility>

63using namespace llvm;

65#define DEBUG_TYPE"hexagon-lowering" "hexagon-lowering"

67static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
cl::init(true), cl::Hidden,
cl::desc("Control jump table emission on Hexagon target"));

71static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Enable Hexagon SDNode scheduling"));

75static cl::opt<bool> EnableFastMath("ffast-math",
cl::Hidden, cl::ZeroOrMore, cl::init(false),
cl::desc("Enable Fast Math processing"));

79static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
cl::Hidden, cl::ZeroOrMore, cl::init(5),
cl::desc("Set minimum jump tables"));

83static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
cl::Hidden, cl::ZeroOrMore, cl::init(6),
cl::desc("Max #stores to inline memcpy"));

87static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
cl::Hidden, cl::ZeroOrMore, cl::init(4),
cl::desc("Max #stores to inline memcpy"));

91static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
cl::Hidden, cl::ZeroOrMore, cl::init(6),
cl::desc("Max #stores to inline memmove"));

95static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
cl::Hidden, cl::ZeroOrMore, cl::init(4),
cl::desc("Max #stores to inline memmove"));

99static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
cl::Hidden, cl::ZeroOrMore, cl::init(8),
cl::desc("Max #stores to inline memset"));

103static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
cl::Hidden, cl::ZeroOrMore, cl::init(4),
cl::desc("Max #stores to inline memset"));

107static cl::opt<bool> AlignLoads("hexagon-align-loads",
cl::Hidden, cl::init(false),
cl::desc("Rewrite unaligned loads as a pair of aligned loads"));


112namespace {

class HexagonCCState : public CCState {
  unsigned NumNamedVarArgParams = 0;

public:
  HexagonCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF,
                 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
                 unsigned NumNamedArgs)
      : CCState(CC, IsVarArg, MF, locs, C),
        NumNamedVarArgParams(NumNamedArgs) {}
  unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
};

126} // end anonymous namespace


129// Implement calling convention for Hexagon.

131static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
                     CCValAssign::LocInfo &LocInfo,
                     ISD::ArgFlagsTy &ArgFlags, CCState &State) {
static const MCPhysReg ArgRegs[] = {
  Hexagon::R0, Hexagon::R1, Hexagon::R2,
  Hexagon::R3, Hexagon::R4, Hexagon::R5
};
const unsigned NumArgRegs = array_lengthof(ArgRegs);
unsigned RegNum = State.getFirstUnallocated(ArgRegs);

// RegNum is an index into ArgRegs: skip a register if RegNum is odd.
if (RegNum != NumArgRegs && RegNum % 2 == 1)
  State.AllocateReg(ArgRegs[RegNum]);

// Always return false here, as this function only makes sure that the first
// unallocated register has an even register number and does not actually
// allocate a register for the current argument.
return false;
149}

151#include "HexagonGenCallingConv.inc"


154SDValue
155HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
    const {
return SDValue();
158}

160/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
161/// by "Src" to address "Dst" of size "Size".  Alignment information is
162/// specified by the specific parameter attribute. The copy will be passed as
163/// a byval function parameter.  Sometimes what we are copying is the end of a
164/// larger object, the part that does not fit in registers.
165static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst,
                                       SDValue Chain, ISD::ArgFlagsTy Flags,
                                       SelectionDAG &DAG, const SDLoc &dl) {
SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
                     /*isVolatile=*/false, /*AlwaysInline=*/false,
                     /*isTailCall=*/false,
                     MachinePointerInfo(), MachinePointerInfo());
173}

175bool
176HexagonTargetLowering::CanLowerReturn(
  CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
  const SmallVectorImpl<ISD::OutputArg> &Outs,
  LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);

if (MF.getSubtarget<HexagonSubtarget>().useHVXOps())
  return CCInfo.CheckReturn(Outs, RetCC_Hexagon_HVX);
return CCInfo.CheckReturn(Outs, RetCC_Hexagon);
186}

188// LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
189// passed by value, the function prototype is modified to return void and
190// the value is stored in memory pointed by a pointer passed by caller.
191SDValue
192HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                 bool IsVarArg,
                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
                                 const SmallVectorImpl<SDValue> &OutVals,
                                 const SDLoc &dl, SelectionDAG &DAG) const {
// CCValAssign - represent the assignment of the return value to locations.
SmallVector<CCValAssign, 16> RVLocs;

// CCState - Info about the registers and stack slot.
CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
               *DAG.getContext());

// Analyze return values of ISD::RET
if (Subtarget.useHVXOps())
  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon_HVX);
else
  CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);

SDValue Flag;
SmallVector<SDValue, 4> RetOps(1, Chain);

// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
  CCValAssign &VA = RVLocs[i];

  Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);

  // Guarantee that all emitted copies are stuck together with flags.
  Flag = Chain.getValue(1);
  RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
}

RetOps[0] = Chain;  // Update chain.

// Add the flag if we have it.
if (Flag.getNode())
  RetOps.push_back(Flag);

return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
231}

233bool HexagonTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
// If either no tail call or told not to tail call at all, don't.
auto Attr =
    CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
if (!CI->isTailCall() || Attr.getValueAsString() == "true")
  return false;

return true;
241}

243Register HexagonTargetLowering::getRegisterByName(const char* RegName, EVT VT,
                                                const MachineFunction &) const {
// Just support r19, the linux kernel uses it.
Register Reg = StringSwitch<Register>(RegName)
                   .Case("r19", Hexagon::R19)
                   .Default(Register());
if (Reg)
  return Reg;

report_fatal_error("Invalid register name global variable");
253}

255/// LowerCallResult - Lower the result values of an ISD::CALL into the
256/// appropriate copies out of appropriate physical registers.  This assumes that
257/// Chain/Glue are the input chain/glue to use, and that TheCall is the call
258/// being lowered. Returns a SDNode with the same number of values as the
259/// ISD::CALL.
260SDValue HexagonTargetLowering::LowerCallResult(
  SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg,
  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
  const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const {
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;

CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
               *DAG.getContext());

if (Subtarget.useHVXOps())
  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon_HVX);
else
  CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);

// Copy all of the result registers out of their specified physreg.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
  SDValue RetVal;
  if (RVLocs[i].getValVT() == MVT::i1) {
    // Return values of type MVT::i1 require special handling. The reason
    // is that MVT::i1 is associated with the PredRegs register class, but
    // values of that type are still returned in R0. Generate an explicit
    // copy into a predicate register from R0, and treat the value of the
    // predicate register as the call result.
    auto &MRI = DAG.getMachineFunction().getRegInfo();
    SDValue FR0 = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
                                     MVT::i32, Glue);
    // FR0 = (Value, Chain, Glue)
    Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
    SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR,
                                   FR0.getValue(0), FR0.getValue(2));
    // TPR = (Chain, Glue)
    // Don't glue this CopyFromReg, because it copies from a virtual
    // register. If it is glued to the call, InstrEmitter will add it
    // as an implicit def to the call (EmitMachineNode).
    RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1);
    Glue = TPR.getValue(1);
    Chain = TPR.getValue(0);
  } else {
    RetVal = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
                                RVLocs[i].getValVT(), Glue);
    Glue = RetVal.getValue(2);
    Chain = RetVal.getValue(1);
  }
  InVals.push_back(RetVal.getValue(0));
}

return Chain;
309}

311/// LowerCall - Functions arguments are copied from virtual regs to
312/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
313SDValue
314HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
                               SmallVectorImpl<SDValue> &InVals) const {
SelectionDAG &DAG                     = CLI.DAG;
SDLoc &dl                             = CLI.DL;
SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
SDValue Chain                         = CLI.Chain;
SDValue Callee                        = CLI.Callee;
CallingConv::ID CallConv              = CLI.CallConv;
bool IsVarArg                         = CLI.IsVarArg;
bool DoesNotReturn                    = CLI.DoesNotReturn;

bool IsStructRet    = Outs.empty() ? false : Outs[0].Flags.isSRet();
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
auto PtrVT = getPointerTy(MF.getDataLayout());

unsigned NumParams = CLI.CS.getInstruction()
                      ? CLI.CS.getFunctionType()->getNumParams()
                      : 0;
if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee))
  Callee = DAG.getTargetGlobalAddress(GAN->getGlobal(), dl, MVT::i32);

// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
                      NumParams);

if (Subtarget.useHVXOps())
  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_HVX);
else
  CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);

auto Attr = MF.getFunction().getFnAttribute("disable-tail-calls");
if (Attr.getValueAsString() == "true")
  CLI.IsTailCall = false;

if (CLI.IsTailCall) {
  bool StructAttrFlag = MF.getFunction().hasStructRetAttr();
  CLI.IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
                      IsVarArg, IsStructRet, StructAttrFlag, Outs,
                      OutVals, Ins, DAG);
  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
    CCValAssign &VA = ArgLocs[i];
    if (VA.isMemLoc()) {
      CLI.IsTailCall = false;
      break;
    }
  }
  LLVM_DEBUG(dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
 : "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
                                       : "Argument must be passed on stack. "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
 : "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false)
                                         "Not eligible for Tail Call\n"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << (CLI.IsTailCall ? "Eligible for Tail Call\n"
 : "Argument must be passed on stack. " "Not eligible for Tail Call\n"
); } } while (false);
}
// Get a count of how many bytes are to be pushed on the stack.
unsigned NumBytes = CCInfo.getNextStackOffset();
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
SmallVector<SDValue, 8> MemOpChains;

const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
SDValue StackPtr =
    DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);

bool NeedsArgAlign = false;
unsigned LargestAlignSeen = 0;
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
  CCValAssign &VA = ArgLocs[i];
  SDValue Arg = OutVals[i];
  ISD::ArgFlagsTy Flags = Outs[i].Flags;
  // Record if we need > 8 byte alignment on an argument.
  bool ArgAlign = Subtarget.isHVXVectorType(VA.getValVT());
  NeedsArgAlign |= ArgAlign;

  // Promote the value if needed.
  switch (VA.getLocInfo()) {
    default:
      // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
      llvm_unreachable("Unknown loc info!")::llvm::llvm_unreachable_internal("Unknown loc info!", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 392);
    case CCValAssign::Full:
      break;
    case CCValAssign::BCvt:
      Arg = DAG.getBitcast(VA.getLocVT(), Arg);
      break;
    case CCValAssign::SExt:
      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
      break;
    case CCValAssign::ZExt:
      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
      break;
    case CCValAssign::AExt:
      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
      break;
  }

  if (VA.isMemLoc()) {
    unsigned LocMemOffset = VA.getLocMemOffset();
    SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
                                      StackPtr.getValueType());
    MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
    if (ArgAlign)
      LargestAlignSeen = std::max(LargestAlignSeen,
                                  VA.getLocVT().getStoreSizeInBits() >> 3);
    if (Flags.isByVal()) {
      // The argument is a struct passed by value. According to LLVM, "Arg"
      // is a pointer.
      MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
                                                      Flags, DAG, dl));
    } else {
      MachinePointerInfo LocPI = MachinePointerInfo::getStack(
          DAG.getMachineFunction(), LocMemOffset);
      SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI);
      MemOpChains.push_back(S);
    }
    continue;
  }

  // Arguments that can be passed on register must be kept at RegsToPass
  // vector.
  if (VA.isRegLoc())
    RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
}

if (NeedsArgAlign && Subtarget.hasV60Ops()) {
  LLVM_DEBUG(dbgs() << "Function needs byte stack align due to call args\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { dbgs() << "Function needs byte stack align due to call args\n"
; } } while (false);
  unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
  LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
  MFI.ensureMaxAlignment(LargestAlignSeen);
}
// Transform all store nodes into one single node because all store
// nodes are independent of each other.
if (!MemOpChains.empty())
  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);

SDValue Glue;
if (!CLI.IsTailCall) {
  Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, dl);
  Glue = Chain.getValue(1);
}

// Build a sequence of copy-to-reg nodes chained together with token
// chain and flag operands which copy the outgoing args into registers.
// The Glue is necessary since all emitted instructions must be
// stuck together.
if (!CLI.IsTailCall) {
  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
                             RegsToPass[i].second, Glue);
    Glue = Chain.getValue(1);
  }
} else {
  // For tail calls lower the arguments to the 'real' stack slot.
  //
  // Force all the incoming stack arguments to be loaded from the stack
  // before any new outgoing arguments are stored to the stack, because the
  // outgoing stack slots may alias the incoming argument stack slots, and
  // the alias isn't otherwise explicit. This is slightly more conservative
  // than necessary, because it means that each store effectively depends
  // on every argument instead of just those arguments it would clobber.
  //
  // Do not flag preceding copytoreg stuff together with the following stuff.
  Glue = SDValue();
  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
                             RegsToPass[i].second, Glue);
    Glue = Chain.getValue(1);
  }
  Glue = SDValue();
}

bool LongCalls = MF.getSubtarget<HexagonSubtarget>().useLongCalls();
unsigned Flags = LongCalls ? HexagonII::HMOTF_ConstExtended : 0;

// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
  Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT, 0, Flags);
} else if (ExternalSymbolSDNode *S =
           dyn_cast<ExternalSymbolSDNode>(Callee)) {
  Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, Flags);
}

// Returns a chain & a flag for retval copy to use.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SmallVector<SDValue, 8> Ops;
Ops.push_back(Chain);
Ops.push_back(Callee);

// Add argument registers to the end of the list so that they are
// known live into the call.
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
  Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                RegsToPass[i].second.getValueType()));
}

const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallConv);
assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 511, __PRETTY_FUNCTION__));
Ops.push_back(DAG.getRegisterMask(Mask));

if (Glue.getNode())
  Ops.push_back(Glue);

if (CLI.IsTailCall) {
  MFI.setHasTailCall();
  return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
}

// Set this here because we need to know this for "hasFP" in frame lowering.
// The target-independent code calls getFrameRegister before setting it, and
// getFrameRegister uses hasFP to determine whether the function has FP.
MFI.setHasCalls(true);

unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
Glue = Chain.getValue(1);

// Create the CALLSEQ_END node.
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
                           DAG.getIntPtrConstant(0, dl, true), Glue, dl);
Glue = Chain.getValue(1);

// Handle result values, copying them out of physregs into vregs that we
// return.
return LowerCallResult(Chain, Glue, CallConv, IsVarArg, Ins, dl, DAG,
                       InVals, OutVals, Callee);
540}

542/// Returns true by value, base pointer and offset pointer and addressing
543/// mode by reference if this node can be combined with a load / store to
544/// form a post-indexed load / store.
545bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
    SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM,
    SelectionDAG &DAG) const {
LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(N);
if (!LSN)
  return false;
EVT VT = LSN->getMemoryVT();
if (!VT.isSimple())
  return false;
bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
                   VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
                   VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
                   VT == MVT::v4i16 || VT == MVT::v8i8 ||
                   Subtarget.isHVXVectorType(VT.getSimpleVT());
if (!IsLegalType)
  return false;

if (Op->getOpcode() != ISD::ADD)
  return false;
Base = Op->getOperand(0);
Offset = Op->getOperand(1);
if (!isa<ConstantSDNode>(Offset.getNode()))
  return false;
AM = ISD::POST_INC;

int32_t V = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
572}

574SDValue
575HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
unsigned LR = HRI.getRARegister();

if ((Op.getOpcode() != ISD::INLINEASM &&
     Op.getOpcode() != ISD::INLINEASM_BR) || HMFI.hasClobberLR())
  return Op;

unsigned NumOps = Op.getNumOperands();
if (Op.getOperand(NumOps-1).getValueType() == MVT::Glue)
  --NumOps;  // Ignore the flag operand.

for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
  unsigned Flags = cast<ConstantSDNode>(Op.getOperand(i))->getZExtValue();
  unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
  ++i;  // Skip the ID value.

  switch (InlineAsm::getKind(Flags)) {
    default:
      llvm_unreachable("Bad flags!")::llvm::llvm_unreachable_internal("Bad flags!", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 596);
    case InlineAsm::Kind_RegUse:
    case InlineAsm::Kind_Imm:
    case InlineAsm::Kind_Mem:
      i += NumVals;
      break;
    case InlineAsm::Kind_Clobber:
    case InlineAsm::Kind_RegDef:
    case InlineAsm::Kind_RegDefEarlyClobber: {
      for (; NumVals; --NumVals, ++i) {
        unsigned Reg = cast<RegisterSDNode>(Op.getOperand(i))->getReg();
        if (Reg != LR)
          continue;
        HMFI.setHasClobberLR(true);
        return Op;
      }
      break;
    }
  }
}

return Op;
618}

620// Need to transform ISD::PREFETCH into something that doesn't inherit
621// all of the properties of ISD::PREFETCH, specifically SDNPMayLoad and
622// SDNPMayStore.
623SDValue HexagonTargetLowering::LowerPREFETCH(SDValue Op,
                                           SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDValue Addr = Op.getOperand(1);
// Lower it to DCFETCH($reg, #0).  A "pat" will try to merge the offset in,
// if the "reg" is fed by an "add".
SDLoc DL(Op);
SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
632}

634// Custom-handle ISD::READCYCLECOUNTER because the target-independent SDNode
635// is marked as having side-effects, while the register read on Hexagon does
636// not have any. TableGen refuses to accept the direct pattern from that node
637// to the A4_tfrcpp.
638SDValue HexagonTargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
                                                   SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDLoc dl(Op);
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
return DAG.getNode(HexagonISD::READCYCLE, dl, VTs, Chain);
644}

646SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
    SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
// Lower the hexagon_prefetch builtin to DCFETCH, as above.
if (IntNo == Intrinsic::hexagon_prefetch) {
  SDValue Addr = Op.getOperand(2);
  SDLoc DL(Op);
  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
  return DAG.getNode(HexagonISD::DCFETCH, DL, MVT::Other, Chain, Addr, Zero);
}
return SDValue();
658}

660SDValue
661HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
                                             SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDValue Size = Op.getOperand(1);
SDValue Align = Op.getOperand(2);
SDLoc dl(Op);

ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC")((AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC"
) ? static_cast<void> (0) : __assert_fail ("AlignConst && \"Non-constant Align in LowerDYNAMIC_STACKALLOC\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 669, __PRETTY_FUNCTION__));

unsigned A = AlignConst->getSExtValue();
auto &HFI = *Subtarget.getFrameLowering();
// "Zero" means natural stack alignment.
if (A == 0)
  A = HFI.getStackAlignment();

LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
 << A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
  dbgs () << __func__ << " Align: " << A << " Size: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
 << A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
  Size.getNode()->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
 << A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
  dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
 << A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false)
})do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-lowering")) { { dbgs () << __func__ << " Align: "
 << A << " Size: "; Size.getNode()->dump(&
DAG); dbgs() << "\n"; }; } } while (false);

SDValue AC = DAG.getConstant(A, dl, MVT::i32);
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);

DAG.ReplaceAllUsesOfValueWith(Op, AA);
return AA;
689}

691SDValue HexagonTargetLowering::LowerFormalArguments(
  SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
  const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
  SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();

// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
HexagonCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext(),
                      MF.getFunction().getFunctionType()->getNumParams());

if (Subtarget.useHVXOps())
  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon_HVX);
else
  CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);

// For LLVM, in the case when returning a struct by value (>8byte),
// the first argument is a pointer that points to the location on caller's
// stack where the return value will be stored. For Hexagon, the location on
// caller's stack is passed only when the struct size is smaller than (and
// equal to) 8 bytes. If not, no address will be passed into callee and
// callee return the result direclty through R0/R1.

auto &HMFI = *MF.getInfo<HexagonMachineFunctionInfo>();

for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
  CCValAssign &VA = ArgLocs[i];
  ISD::ArgFlagsTy Flags = Ins[i].Flags;
  bool ByVal = Flags.isByVal();

  // Arguments passed in registers:
  // 1. 32- and 64-bit values and HVX vectors are passed directly,
  // 2. Large structs are passed via an address, and the address is
  //    passed in a register.
  if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8)
    llvm_unreachable("ByValSize must be bigger than 8 bytes")::llvm::llvm_unreachable_internal("ByValSize must be bigger than 8 bytes"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 728);

  bool InReg = VA.isRegLoc() &&
               (!ByVal || (ByVal && Flags.getByValSize() > 8));

  if (InReg) {
    MVT RegVT = VA.getLocVT();
    if (VA.getLocInfo() == CCValAssign::BCvt)
      RegVT = VA.getValVT();

    const TargetRegisterClass *RC = getRegClassFor(RegVT);
    Register VReg = MRI.createVirtualRegister(RC);
    SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);

    // Treat values of type MVT::i1 specially: they are passed in
    // registers of type i32, but they need to remain as values of
    // type i1 for consistency of the argument lowering.
    if (VA.getValVT() == MVT::i1) {
      assert(RegVT.getSizeInBits() <= 32)((RegVT.getSizeInBits() <= 32) ? static_cast<void> (
0) : __assert_fail ("RegVT.getSizeInBits() <= 32", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 746, __PRETTY_FUNCTION__));
      SDValue T = DAG.getNode(ISD::AND, dl, RegVT,
                              Copy, DAG.getConstant(1, dl, RegVT));
      Copy = DAG.getSetCC(dl, MVT::i1, T, DAG.getConstant(0, dl, RegVT),
                          ISD::SETNE);
    } else {
752#ifndef NDEBUG
      unsigned RegSize = RegVT.getSizeInBits();
      assert(RegSize == 32 || RegSize == 64 ||((RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType
(RegVT)) ? static_cast<void> (0) : __assert_fail ("RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType(RegVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 755, __PRETTY_FUNCTION__))
             Subtarget.isHVXVectorType(RegVT))((RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType
(RegVT)) ? static_cast<void> (0) : __assert_fail ("RegSize == 32 || RegSize == 64 || Subtarget.isHVXVectorType(RegVT)"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 755, __PRETTY_FUNCTION__));
756#endif
    }
    InVals.push_back(Copy);
    MRI.addLiveIn(VA.getLocReg(), VReg);
  } else {
    assert(VA.isMemLoc() && "Argument should be passed in memory")((VA.isMemLoc() && "Argument should be passed in memory"
) ? static_cast<void> (0) : __assert_fail ("VA.isMemLoc() && \"Argument should be passed in memory\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 761, __PRETTY_FUNCTION__));

    // If it's a byval parameter, then we need to compute the
    // "real" size, not the size of the pointer.
    unsigned ObjSize = Flags.isByVal()
                          ? Flags.getByValSize()
                          : VA.getLocVT().getStoreSizeInBits() / 8;

    // Create the frame index object for this incoming parameter.
    int Offset = HEXAGON_LRFP_SIZE8 + VA.getLocMemOffset();
    int FI = MFI.CreateFixedObject(ObjSize, Offset, true);
    SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);

    if (Flags.isByVal()) {
      // If it's a pass-by-value aggregate, then do not dereference the stack
      // location. Instead, we should generate a reference to the stack
      // location.
      InVals.push_back(FIN);
    } else {
      SDValue L = DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
                              MachinePointerInfo::getFixedStack(MF, FI, 0));
      InVals.push_back(L);
    }
  }
}


if (IsVarArg) {
  // This will point to the next argument passed via stack.
  int Offset = HEXAGON_LRFP_SIZE8 + CCInfo.getNextStackOffset();
  int FI = MFI.CreateFixedObject(Hexagon_PointerSize(4), Offset, true);
  HMFI.setVarArgsFrameIndex(FI);
}

return Chain;
796}

798SDValue
799HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
// VASTART stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
MachineFunction &MF = DAG.getMachineFunction();
HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, Op.getOperand(1),
                    MachinePointerInfo(SV));
808}

810SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
const SDLoc &dl(Op);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
MVT ResTy = ty(Op);
MVT OpTy = ty(LHS);

if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
  MVT ElemTy = OpTy.getVectorElementType();
  assert(ElemTy.isScalarInteger())((ElemTy.isScalarInteger()) ? static_cast<void> (0) : __assert_fail
 ("ElemTy.isScalarInteger()", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 820, __PRETTY_FUNCTION__));
  MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
                                OpTy.getVectorNumElements());
  return DAG.getSetCC(dl, ResTy,
                      DAG.getSExtOrTrunc(LHS, SDLoc(LHS), WideTy),
                      DAG.getSExtOrTrunc(RHS, SDLoc(RHS), WideTy), CC);
}

// Treat all other vector types as legal.
if (ResTy.isVector())
  return Op;

// Comparisons of short integers should use sign-extend, not zero-extend,
// since we can represent small negative values in the compare instructions.
// The LLVM default is to use zero-extend arbitrarily in these cases.
auto isSExtFree = [this](SDValue N) {
  switch (N.getOpcode()) {
    case ISD::TRUNCATE: {
      // A sign-extend of a truncate of a sign-extend is free.
      SDValue Op = N.getOperand(0);
      if (Op.getOpcode() != ISD::AssertSext)
        return false;
      EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT();
      unsigned ThisBW = ty(N).getSizeInBits();
      unsigned OrigBW = OrigTy.getSizeInBits();
      // The type that was sign-extended to get the AssertSext must be
      // narrower than the type of N (so that N has still the same value
      // as the original).
      return ThisBW >= OrigBW;
    }
    case ISD::LOAD:
      // We have sign-extended loads.
      return true;
  }
  return false;
};

if (OpTy == MVT::i8 || OpTy == MVT::i16) {
  ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
  bool IsNegative = C && C->getAPIntValue().isNegative();
  if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
    return DAG.getSetCC(dl, ResTy,
                        DAG.getSExtOrTrunc(LHS, SDLoc(LHS), MVT::i32),
                        DAG.getSExtOrTrunc(RHS, SDLoc(RHS), MVT::i32), CC);
}

return SDValue();
867}

869SDValue
870HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue PredOp = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
MVT OpTy = ty(Op1);
const SDLoc &dl(Op);

if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
  MVT ElemTy = OpTy.getVectorElementType();
  assert(ElemTy.isScalarInteger())((ElemTy.isScalarInteger()) ? static_cast<void> (0) : __assert_fail
 ("ElemTy.isScalarInteger()", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 878, __PRETTY_FUNCTION__));
  MVT WideTy = MVT::getVectorVT(MVT::getIntegerVT(2*ElemTy.getSizeInBits()),
                                OpTy.getVectorNumElements());
  // Generate (trunc (select (_, sext, sext))).
  return DAG.getSExtOrTrunc(
            DAG.getSelect(dl, WideTy, PredOp,
                          DAG.getSExtOrTrunc(Op1, dl, WideTy),
                          DAG.getSExtOrTrunc(Op2, dl, WideTy)),
            dl, OpTy);
}

return SDValue();
890}

892static Constant *convert_i1_to_i8(const Constant *ConstVal) {
SmallVector<Constant *, 128> NewConst;
const ConstantVector *CV = dyn_cast<ConstantVector>(ConstVal);
if (!CV)
  return nullptr;

LLVMContext &Ctx = ConstVal->getContext();
IRBuilder<> IRB(Ctx);
unsigned NumVectorElements = CV->getNumOperands();
assert(isPowerOf2_32(NumVectorElements) &&((isPowerOf2_32(NumVectorElements) && "conversion only supported for pow2 VectorSize!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumVectorElements) && \"conversion only supported for pow2 VectorSize!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 902, __PRETTY_FUNCTION__))
       "conversion only supported for pow2 VectorSize!")((isPowerOf2_32(NumVectorElements) && "conversion only supported for pow2 VectorSize!"
) ? static_cast<void> (0) : __assert_fail ("isPowerOf2_32(NumVectorElements) && \"conversion only supported for pow2 VectorSize!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 902, __PRETTY_FUNCTION__));

for (unsigned i = 0; i < NumVectorElements / 8; ++i) {
  uint8_t x = 0;
  for (unsigned j = 0; j < 8; ++j) {
    uint8_t y = CV->getOperand(i * 8 + j)->getUniqueInteger().getZExtValue();
    x |= y << (7 - j);
  }
  assert((x == 0 || x == 255) && "Either all 0's or all 1's expected!")(((x == 0 || x == 255) && "Either all 0's or all 1's expected!"
) ? static_cast<void> (0) : __assert_fail ("(x == 0 || x == 255) && \"Either all 0's or all 1's expected!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 910, __PRETTY_FUNCTION__));
  NewConst.push_back(IRB.getInt8(x));
}
return ConstantVector::get(NewConst);
914}

916SDValue
917HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
EVT ValTy = Op.getValueType();
ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
Constant *CVal = nullptr;
bool isVTi1Type = false;
if (const Constant *ConstVal = dyn_cast<Constant>(CPN->getConstVal())) {
  Type *CValTy = ConstVal->getType();
  if (CValTy->isVectorTy() &&
      CValTy->getVectorElementType()->isIntegerTy(1)) {
    CVal = convert_i1_to_i8(ConstVal);
    isVTi1Type = (CVal != nullptr);
  }
}
unsigned Align = CPN->getAlignment();
bool IsPositionIndependent = isPositionIndependent();
unsigned char TF = IsPositionIndependent ? HexagonII::MO_PCREL : 0;

unsigned Offset = 0;
SDValue T;
if (CPN->isMachineConstantPoolEntry())
  T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, Offset,
                                TF);
else if (isVTi1Type)
  T = DAG.getTargetConstantPool(CVal, ValTy, Align, Offset, TF);
else
  T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, Offset, TF);

assert(cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF &&((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
 && "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 945, __PRETTY_FUNCTION__))
       "Inconsistent target flag encountered")((cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF
 && "Inconsistent target flag encountered") ? static_cast
<void> (0) : __assert_fail ("cast<ConstantPoolSDNode>(T)->getTargetFlags() == TF && \"Inconsistent target flag encountered\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 945, __PRETTY_FUNCTION__));

if (IsPositionIndependent)
  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
950}

952SDValue
953HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
EVT VT = Op.getValueType();
int Idx = cast<JumpTableSDNode>(Op)->getIndex();
if (isPositionIndependent()) {
  SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
  return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
}

SDValue T = DAG.getTargetJumpTable(Idx, VT);
return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
963}

965SDValue
966HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
MFI.setReturnAddressIsTaken(true);

if (verifyReturnAddressArgumentIsConstant(Op, DAG))
  return SDValue();

EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
if (Depth) {
  SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
  SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
  return DAG.getLoad(VT, dl, DAG.getEntryNode(),
                     DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
                     MachinePointerInfo());
}

// Return LR, which contains the return address. Mark it an implicit live-in.
unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
989}

991SDValue
992HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
MFI.setFrameAddressIsTaken(true);

EVT VT = Op.getValueType();
SDLoc dl(Op);
unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
                                       HRI.getFrameRegister(), VT);
while (Depth--)
  FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
                          MachinePointerInfo());
return FrameAddr;
1006}

1008SDValue
1009HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
SDLoc dl(Op);
return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1012}

1014SDValue
1015HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
auto *GAN = cast<GlobalAddressSDNode>(Op);
auto PtrVT = getPointerTy(DAG.getDataLayout());
auto *GV = GAN->getGlobal();
int64_t Offset = GAN->getOffset();

auto &HLOF = *HTM.getObjFileLowering();
Reloc::Model RM = HTM.getRelocationModel();

if (RM == Reloc::Static) {
  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
  const GlobalObject *GO = GV->getBaseObject();
  if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
    return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
  return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
}

bool UsePCRel = getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
if (UsePCRel) {
  SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
                                          HexagonII::MO_PCREL);
  return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
}

// Use GOT index.
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1045}

1047// Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1048SDValue
1049HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
SDLoc dl(Op);
EVT PtrVT = getPointerTy(DAG.getDataLayout());

Reloc::Model RM = HTM.getRelocationModel();
if (RM == Reloc::Static) {
  SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
  return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
}

SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1062}

1064SDValue
1065HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
    const {
EVT PtrVT = getPointerTy(DAG.getDataLayout());
SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME"_GLOBAL_OFFSET_TABLE_", PtrVT,
                                             HexagonII::MO_PCREL);
return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1071}

1073SDValue
1074HexagonTargetLowering::GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
    GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg,
    unsigned char OperandFlags) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
SDLoc dl(GA);
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
                                         GA->getValueType(0),
                                         GA->getOffset(),
                                         OperandFlags);
// Create Operands for the call.The Operands should have the following:
// 1. Chain SDValue
// 2. Callee which in this case is the Global address value.
// 3. Registers live into the call.In this case its R0, as we
//    have just one argument to be passed.
// 4. Glue.
// Note: The order is important.

const auto &HRI = *Subtarget.getRegisterInfo();
const uint32_t *Mask = HRI.getCallPreservedMask(MF, CallingConv::C);
assert(Mask && "Missing call preserved mask for calling convention")((Mask && "Missing call preserved mask for calling convention"
) ? static_cast<void> (0) : __assert_fail ("Mask && \"Missing call preserved mask for calling convention\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1095, __PRETTY_FUNCTION__));
SDValue Ops[] = { Chain, TGA, DAG.getRegister(Hexagon::R0, PtrVT),
                  DAG.getRegisterMask(Mask), Glue };
Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, Ops);

// Inform MFI that function has calls.
MFI.setAdjustsStack(true);

Glue = Chain.getValue(1);
return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Glue);
1105}

1107//
1108// Lower using the intial executable model for TLS addresses
1109//
1110SDValue
1111HexagonTargetLowering::LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
    SelectionDAG &DAG) const {
SDLoc dl(GA);
int64_t Offset = GA->getOffset();
auto PtrVT = getPointerTy(DAG.getDataLayout());

// Get the thread pointer.
SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);

bool IsPositionIndependent = isPositionIndependent();
unsigned char TF =
    IsPositionIndependent ? HexagonII::MO_IEGOT : HexagonII::MO_IE;

// First generate the TLS symbol address
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT,
                                         Offset, TF);

SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);

if (IsPositionIndependent) {
  // Generate the GOT pointer in case of position independent code
  SDValue GOT = LowerGLOBAL_OFFSET_TABLE(Sym, DAG);

  // Add the TLS Symbol address to GOT pointer.This gives
  // GOT relative relocation for the symbol.
  Sym = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);
}

// Load the offset value for TLS symbol.This offset is relative to
// thread pointer.
SDValue LoadOffset =
    DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Sym, MachinePointerInfo());

// Address of the thread local variable is the add of thread
// pointer and the offset of the variable.
return DAG.getNode(ISD::ADD, dl, PtrVT, TP, LoadOffset);
1147}

1149//
1150// Lower using the local executable model for TLS addresses
1151//
1152SDValue
1153HexagonTargetLowering::LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
    SelectionDAG &DAG) const {
SDLoc dl(GA);
int64_t Offset = GA->getOffset();
auto PtrVT = getPointerTy(DAG.getDataLayout());

// Get the thread pointer.
SDValue TP = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Hexagon::UGP, PtrVT);
// Generate the TLS symbol address
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
                                         HexagonII::MO_TPREL);
SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);

// Address of the thread local variable is the add of thread
// pointer and the offset of the variable.
return DAG.getNode(ISD::ADD, dl, PtrVT, TP, Sym);
1169}

1171//
1172// Lower using the general dynamic model for TLS addresses
1173//
1174SDValue
1175HexagonTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
    SelectionDAG &DAG) const {
SDLoc dl(GA);
int64_t Offset = GA->getOffset();
auto PtrVT = getPointerTy(DAG.getDataLayout());

// First generate the TLS symbol address
SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, PtrVT, Offset,
                                         HexagonII::MO_GDGOT);

// Then, generate the GOT pointer
SDValue GOT = LowerGLOBAL_OFFSET_TABLE(TGA, DAG);

// Add the TLS symbol and the GOT pointer
SDValue Sym = DAG.getNode(HexagonISD::CONST32, dl, PtrVT, TGA);
SDValue Chain = DAG.getNode(ISD::ADD, dl, PtrVT, GOT, Sym);

// Copy over the argument to R0
SDValue InFlag;
Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, Hexagon::R0, Chain, InFlag);
InFlag = Chain.getValue(1);

unsigned Flags =
    static_cast<const HexagonSubtarget &>(DAG.getSubtarget()).useLongCalls()
        ? HexagonII::MO_GDPLT | HexagonII::HMOTF_ConstExtended
        : HexagonII::MO_GDPLT;

return GetDynamicTLSAddr(DAG, Chain, GA, InFlag, PtrVT,
                         Hexagon::R0, Flags);
1204}

1206//
1207// Lower TLS addresses.
1208//
1209// For now for dynamic models, we only support the general dynamic model.
1210//
1211SDValue
1212HexagonTargetLowering::LowerGlobalTLSAddress(SDValue Op,
    SelectionDAG &DAG) const {
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);

switch (HTM.getTLSModel(GA->getGlobal())) {
  case TLSModel::GeneralDynamic:
  case TLSModel::LocalDynamic:
    return LowerToTLSGeneralDynamicModel(GA, DAG);
  case TLSModel::InitialExec:
    return LowerToTLSInitialExecModel(GA, DAG);
  case TLSModel::LocalExec:
    return LowerToTLSLocalExecModel(GA, DAG);
}
llvm_unreachable("Bogus TLS model")::llvm::llvm_unreachable_internal("Bogus TLS model", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1225);
1226}

1228//===----------------------------------------------------------------------===//
1229// TargetLowering Implementation
1230//===----------------------------------------------------------------------===//

1232HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
                                           const HexagonSubtarget &ST)
  : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
    Subtarget(ST) {
auto &HRI = *Subtarget.getRegisterInfo();

setPrefLoopAlignment(Align(16));
setMinFunctionAlignment(Align(4));
setPrefFunctionAlignment(Align(16));
setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
setBooleanContents(TargetLoweringBase::UndefinedBooleanContent);
setBooleanVectorContents(TargetLoweringBase::UndefinedBooleanContent);

setMaxAtomicSizeInBitsSupported(64);
setMinCmpXchgSizeInBits(32);

if (EnableHexSDNodeSched)
  setSchedulingPreference(Sched::VLIW);
else
  setSchedulingPreference(Sched::Source);

// Limits for inline expansion of memcpy/memmove
MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
MaxStoresPerMemset = MaxStoresPerMemsetCL;
MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;

//
// Set up register classes.
//

addRegisterClass(MVT::i1,    &Hexagon::PredRegsRegClass);
addRegisterClass(MVT::v2i1,  &Hexagon::PredRegsRegClass);  // bbbbaaaa
addRegisterClass(MVT::v4i1,  &Hexagon::PredRegsRegClass);  // ddccbbaa
addRegisterClass(MVT::v8i1,  &Hexagon::PredRegsRegClass);  // hgfedcba
addRegisterClass(MVT::i32,   &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::v4i8,  &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::i64,   &Hexagon::DoubleRegsRegClass);
addRegisterClass(MVT::v8i8,  &Hexagon::DoubleRegsRegClass);
addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);

addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);

//
// Handling of scalar operations.
//
// All operations default to "legal", except:
// - indexed loads and stores (pre-/post-incremented),
// - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
//   ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
//   FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
//   FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
// which default to "expand" for at least one type.

// Misc operations.
setOperationAction(ISD::ConstantFP,           MVT::f32,   Legal);
setOperationAction(ISD::ConstantFP,           MVT::f64,   Legal);
setOperationAction(ISD::TRAP,                 MVT::Other, Legal);
setOperationAction(ISD::ConstantPool,         MVT::i32,   Custom);
setOperationAction(ISD::JumpTable,            MVT::i32,   Custom);
setOperationAction(ISD::BUILD_PAIR,           MVT::i64,   Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG,    MVT::i1,    Expand);
setOperationAction(ISD::INLINEASM,            MVT::Other, Custom);
setOperationAction(ISD::INLINEASM_BR,         MVT::Other, Custom);
setOperationAction(ISD::PREFETCH,             MVT::Other, Custom);
setOperationAction(ISD::READCYCLECOUNTER,     MVT::i64,   Custom);
setOperationAction(ISD::INTRINSIC_VOID,       MVT::Other, Custom);
setOperationAction(ISD::EH_RETURN,            MVT::Other, Custom);
setOperationAction(ISD::GLOBAL_OFFSET_TABLE,  MVT::i32,   Custom);
setOperationAction(ISD::GlobalTLSAddress,     MVT::i32,   Custom);
setOperationAction(ISD::ATOMIC_FENCE,         MVT::Other, Custom);

// Custom legalize GlobalAddress nodes into CONST32.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::GlobalAddress, MVT::i8,  Custom);
setOperationAction(ISD::BlockAddress,  MVT::i32, Custom);

// Hexagon needs to optimize cases with negative constants.
setOperationAction(ISD::SETCC, MVT::i8,    Custom);
setOperationAction(ISD::SETCC, MVT::i16,   Custom);
setOperationAction(ISD::SETCC, MVT::v4i8,  Custom);
setOperationAction(ISD::SETCC, MVT::v2i16, Custom);

// VASTART needs to be custom lowered to use the VarArgsFrameIndex.
setOperationAction(ISD::VASTART, MVT::Other, Custom);
setOperationAction(ISD::VAEND,   MVT::Other, Expand);
setOperationAction(ISD::VAARG,   MVT::Other, Expand);
setOperationAction(ISD::VACOPY,  MVT::Other, Expand);

setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);

if (EmitJumpTables)
  setMinimumJumpTableEntries(MinimumJumpTables);
else
  setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max());
setOperationAction(ISD::BR_JT, MVT::Other, Expand);

setOperationAction(ISD::ABS, MVT::i32, Legal);
setOperationAction(ISD::ABS, MVT::i64, Legal);

// Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
// but they only operate on i64.
for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::UADDO,    VT, Custom);
  setOperationAction(ISD::USUBO,    VT, Custom);
  setOperationAction(ISD::SADDO,    VT, Expand);
  setOperationAction(ISD::SSUBO,    VT, Expand);
  setOperationAction(ISD::ADDCARRY, VT, Expand);
  setOperationAction(ISD::SUBCARRY, VT, Expand);
}
setOperationAction(ISD::ADDCARRY, MVT::i64, Custom);
setOperationAction(ISD::SUBCARRY, MVT::i64, Custom);

setOperationAction(ISD::CTLZ, MVT::i8,  Promote);
setOperationAction(ISD::CTLZ, MVT::i16, Promote);
setOperationAction(ISD::CTTZ, MVT::i8,  Promote);
setOperationAction(ISD::CTTZ, MVT::i16, Promote);

// Popcount can count # of 1s in i64 but returns i32.
setOperationAction(ISD::CTPOP, MVT::i8,  Promote);
setOperationAction(ISD::CTPOP, MVT::i16, Promote);
setOperationAction(ISD::CTPOP, MVT::i32, Promote);
setOperationAction(ISD::CTPOP, MVT::i64, Legal);

setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
setOperationAction(ISD::BSWAP, MVT::i32, Legal);
setOperationAction(ISD::BSWAP, MVT::i64, Legal);

setOperationAction(ISD::FSHL, MVT::i32, Legal);
setOperationAction(ISD::FSHL, MVT::i64, Legal);
setOperationAction(ISD::FSHR, MVT::i32, Legal);
setOperationAction(ISD::FSHR, MVT::i64, Legal);

for (unsigned IntExpOp :
     {ISD::SDIV,      ISD::UDIV,      ISD::SREM,      ISD::UREM,
      ISD::SDIVREM,   ISD::UDIVREM,   ISD::ROTL,      ISD::ROTR,
      ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
      ISD::SMUL_LOHI, ISD::UMUL_LOHI}) {
  for (MVT VT : MVT::integer_valuetypes())
    setOperationAction(IntExpOp, VT, Expand);
}

for (unsigned FPExpOp :
     {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
      ISD::FPOW, ISD::FCOPYSIGN}) {
  for (MVT VT : MVT::fp_valuetypes())
    setOperationAction(FPExpOp, VT, Expand);
}

// No extending loads from i32.
for (MVT VT : MVT::integer_valuetypes()) {
  setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
  setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
  setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i32, Expand);
}
// Turn FP truncstore into trunc + store.
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
// Turn FP extload into load/fpextend.
for (MVT VT : MVT::fp_valuetypes())
  setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);

// Expand BR_CC and SELECT_CC for all integer and fp types.
for (MVT VT : MVT::integer_valuetypes()) {
  setOperationAction(ISD::BR_CC,     VT, Expand);
  setOperationAction(ISD::SELECT_CC, VT, Expand);
}
for (MVT VT : MVT::fp_valuetypes()) {
  setOperationAction(ISD::BR_CC,     VT, Expand);
  setOperationAction(ISD::SELECT_CC, VT, Expand);
}
setOperationAction(ISD::BR_CC, MVT::Other, Expand);

//
// Handling of vector operations.
//

// Set the action for vector operations to "expand", then override it with
// either "custom" or "legal" for specific cases.
static const unsigned VectExpOps[] = {
  // Integer arithmetic:
  ISD::ADD,     ISD::SUB,     ISD::MUL,     ISD::SDIV,      ISD::UDIV,
  ISD::SREM,    ISD::UREM,    ISD::SDIVREM, ISD::UDIVREM,   ISD::SADDO,
  ISD::UADDO,   ISD::SSUBO,   ISD::USUBO,   ISD::SMUL_LOHI, ISD::UMUL_LOHI,
  // Logical/bit:
  ISD::AND,     ISD::OR,      ISD::XOR,     ISD::ROTL,    ISD::ROTR,
  ISD::CTPOP,   ISD::CTLZ,    ISD::CTTZ,
  // Floating point arithmetic/math functions:
  ISD::FADD,    ISD::FSUB,    ISD::FMUL,    ISD::FMA,     ISD::FDIV,
  ISD::FREM,    ISD::FNEG,    ISD::FABS,    ISD::FSQRT,   ISD::FSIN,
  ISD::FCOS,    ISD::FPOW,    ISD::FLOG,    ISD::FLOG2,
  ISD::FLOG10,  ISD::FEXP,    ISD::FEXP2,   ISD::FCEIL,   ISD::FTRUNC,
  ISD::FRINT,   ISD::FNEARBYINT,            ISD::FROUND,  ISD::FFLOOR,
  ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
  // Misc:
  ISD::BR_CC,   ISD::SELECT_CC,             ISD::ConstantPool,
  // Vector:
  ISD::BUILD_VECTOR,          ISD::SCALAR_TO_VECTOR,
  ISD::EXTRACT_VECTOR_ELT,    ISD::INSERT_VECTOR_ELT,
  ISD::EXTRACT_SUBVECTOR,     ISD::INSERT_SUBVECTOR,
  ISD::CONCAT_VECTORS,        ISD::VECTOR_SHUFFLE
};

for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
  for (unsigned VectExpOp : VectExpOps)
    setOperationAction(VectExpOp, VT, Expand);

  // Expand all extending loads and truncating stores:
  for (MVT TargetVT : MVT::fixedlen_vector_valuetypes()) {
    if (TargetVT == VT)
      continue;
    setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
    setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
    setLoadExtAction(ISD::SEXTLOAD, TargetVT, VT, Expand);
    setTruncStoreAction(VT, TargetVT, Expand);
  }

  // Normalize all inputs to SELECT to be vectors of i32.
  if (VT.getVectorElementType() != MVT::i32) {
    MVT VT32 = MVT::getVectorVT(MVT::i32, VT.getSizeInBits()/32);
    setOperationAction(ISD::SELECT, VT, Promote);
    AddPromotedToType(ISD::SELECT, VT, VT32);
  }
  setOperationAction(ISD::SRA, VT, Custom);
  setOperationAction(ISD::SHL, VT, Custom);
  setOperationAction(ISD::SRL, VT, Custom);
}

// Extending loads from (native) vectors of i8 into (native) vectors of i16
// are legal.
setLoadExtAction(ISD::EXTLOAD,  MVT::v2i16, MVT::v2i8, Legal);
setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
setLoadExtAction(ISD::EXTLOAD,  MVT::v4i16, MVT::v4i8, Legal);
setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);

// Types natively supported:
for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
                     MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
  setOperationAction(ISD::BUILD_VECTOR,       NativeVT, Custom);
  setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
  setOperationAction(ISD::INSERT_VECTOR_ELT,  NativeVT, Custom);
  setOperationAction(ISD::EXTRACT_SUBVECTOR,  NativeVT, Custom);
  setOperationAction(ISD::INSERT_SUBVECTOR,   NativeVT, Custom);
  setOperationAction(ISD::CONCAT_VECTORS,     NativeVT, Custom);

  setOperationAction(ISD::ADD, NativeVT, Legal);
  setOperationAction(ISD::SUB, NativeVT, Legal);
  setOperationAction(ISD::MUL, NativeVT, Legal);
  setOperationAction(ISD::AND, NativeVT, Legal);
  setOperationAction(ISD::OR,  NativeVT, Legal);
  setOperationAction(ISD::XOR, NativeVT, Legal);
}

// Custom lower unaligned loads.
// Also, for both loads and stores, verify the alignment of the address
// in case it is a compile-time constant. This is a usability feature to
// provide a meaningful error message to users.
for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
               MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
  setOperationAction(ISD::LOAD,  VT, Custom);
  setOperationAction(ISD::STORE, VT, Custom);
}

for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
               MVT::v2i32}) {
  setCondCodeAction(ISD::SETNE,  VT, Expand);
  setCondCodeAction(ISD::SETLE,  VT, Expand);
  setCondCodeAction(ISD::SETGE,  VT, Expand);
  setCondCodeAction(ISD::SETLT,  VT, Expand);
  setCondCodeAction(ISD::SETULE, VT, Expand);
  setCondCodeAction(ISD::SETUGE, VT, Expand);
  setCondCodeAction(ISD::SETULT, VT, Expand);
}

// Custom-lower bitcasts from i8 to v8i1.
setOperationAction(ISD::BITCAST,        MVT::i8,    Custom);
setOperationAction(ISD::SETCC,          MVT::v2i16, Custom);
setOperationAction(ISD::VSELECT,        MVT::v4i8,  Custom);
setOperationAction(ISD::VSELECT,        MVT::v2i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8,  Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8,  Custom);

// V5+.
setOperationAction(ISD::FMA,  MVT::f64, Expand);
setOperationAction(ISD::FADD, MVT::f64, Expand);
setOperationAction(ISD::FSUB, MVT::f64, Expand);
setOperationAction(ISD::FMUL, MVT::f64, Expand);

setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);

setOperationAction(ISD::FP_TO_UINT, MVT::i1,  Promote);
setOperationAction(ISD::FP_TO_UINT, MVT::i8,  Promote);
setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
setOperationAction(ISD::FP_TO_SINT, MVT::i1,  Promote);
setOperationAction(ISD::FP_TO_SINT, MVT::i8,  Promote);
setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
setOperationAction(ISD::UINT_TO_FP, MVT::i1,  Promote);
setOperationAction(ISD::UINT_TO_FP, MVT::i8,  Promote);
setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
setOperationAction(ISD::SINT_TO_FP, MVT::i1,  Promote);
setOperationAction(ISD::SINT_TO_FP, MVT::i8,  Promote);
setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);

// Handling of indexed loads/stores: default is "expand".
//
for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
               MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
  setIndexedLoadAction(ISD::POST_INC, VT, Legal);
  setIndexedStoreAction(ISD::POST_INC, VT, Legal);
}

// Subtarget-specific operation actions.
//
if (Subtarget.hasV60Ops()) {
  setOperationAction(ISD::ROTL, MVT::i32, Legal);
  setOperationAction(ISD::ROTL, MVT::i64, Legal);
  setOperationAction(ISD::ROTR, MVT::i32, Legal);
  setOperationAction(ISD::ROTR, MVT::i64, Legal);
}
if (Subtarget.hasV66Ops()) {
  setOperationAction(ISD::FADD, MVT::f64, Legal);
  setOperationAction(ISD::FSUB, MVT::f64, Legal);
}

setTargetDAGCombine(ISD::VSELECT);

if (Subtarget.useHVXOps())
  initializeHVXLowering();

computeRegisterProperties(&HRI);

//
// Library calls for unsupported operations
//
bool FastMath  = EnableFastMath;

setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");

setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");

// This is the only fast library function for sqrtd.
if (FastMath)
  setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");

// Prefix is: nothing  for "slow-math",
//            "fast2_" for V5+ fast-math double-precision
// (actually, keep fast-math and fast-math2 separate for now)
if (FastMath) {
  setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
  setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
  setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
  setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
  setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
} else {
  setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
  setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
  setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
  setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
  setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
}

if (FastMath)
  setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
else
  setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");

// These cause problems when the shift amount is non-constant.
setLibcallName(RTLIB::SHL_I128, nullptr);
setLibcallName(RTLIB::SRL_I128, nullptr);
setLibcallName(RTLIB::SRA_I128, nullptr);
1625}

1627const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
switch ((HexagonISD::NodeType)Opcode) {
case HexagonISD::ADDC:          return "HexagonISD::ADDC";
case HexagonISD::SUBC:          return "HexagonISD::SUBC";
case HexagonISD::ALLOCA:        return "HexagonISD::ALLOCA";
case HexagonISD::AT_GOT:        return "HexagonISD::AT_GOT";
case HexagonISD::AT_PCREL:      return "HexagonISD::AT_PCREL";
case HexagonISD::BARRIER:       return "HexagonISD::BARRIER";
case HexagonISD::CALL:          return "HexagonISD::CALL";
case HexagonISD::CALLnr:        return "HexagonISD::CALLnr";
case HexagonISD::CALLR:         return "HexagonISD::CALLR";
case HexagonISD::COMBINE:       return "HexagonISD::COMBINE";
case HexagonISD::CONST32_GP:    return "HexagonISD::CONST32_GP";
case HexagonISD::CONST32:       return "HexagonISD::CONST32";
case HexagonISD::CP:            return "HexagonISD::CP";
case HexagonISD::DCFETCH:       return "HexagonISD::DCFETCH";
case HexagonISD::EH_RETURN:     return "HexagonISD::EH_RETURN";
case HexagonISD::TSTBIT:        return "HexagonISD::TSTBIT";
case HexagonISD::EXTRACTU:      return "HexagonISD::EXTRACTU";
case HexagonISD::INSERT:        return "HexagonISD::INSERT";
case HexagonISD::JT:            return "HexagonISD::JT";
case HexagonISD::RET_FLAG:      return "HexagonISD::RET_FLAG";
case HexagonISD::TC_RETURN:     return "HexagonISD::TC_RETURN";
case HexagonISD::VASL:          return "HexagonISD::VASL";
case HexagonISD::VASR:          return "HexagonISD::VASR";
case HexagonISD::VLSR:          return "HexagonISD::VLSR";
case HexagonISD::VSPLAT:        return "HexagonISD::VSPLAT";
case HexagonISD::VEXTRACTW:     return "HexagonISD::VEXTRACTW";
case HexagonISD::VINSERTW0:     return "HexagonISD::VINSERTW0";
case HexagonISD::VROR:          return "HexagonISD::VROR";
case HexagonISD::READCYCLE:     return "HexagonISD::READCYCLE";
case HexagonISD::PTRUE:         return "HexagonISD::PTRUE";
case HexagonISD::PFALSE:        return "HexagonISD::PFALSE";
case HexagonISD::VZERO:         return "HexagonISD::VZERO";
case HexagonISD::VSPLATW:       return "HexagonISD::VSPLATW";
case HexagonISD::D2P:           return "HexagonISD::D2P";
case HexagonISD::P2D:           return "HexagonISD::P2D";
case HexagonISD::V2Q:           return "HexagonISD::V2Q";
case HexagonISD::Q2V:           return "HexagonISD::Q2V";
case HexagonISD::QCAT:          return "HexagonISD::QCAT";
case HexagonISD::QTRUE:         return "HexagonISD::QTRUE";
case HexagonISD::QFALSE:        return "HexagonISD::QFALSE";
case HexagonISD::TYPECAST:      return "HexagonISD::TYPECAST";
case HexagonISD::VALIGN:        return "HexagonISD::VALIGN";
case HexagonISD::VALIGNADDR:    return "HexagonISD::VALIGNADDR";
case HexagonISD::OP_END:        break;
}
return nullptr;
1675}

1677void
1678HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
    unsigned NeedAlign) const {
auto *CA = dyn_cast<ConstantSDNode>(Ptr);
if (!CA)
  return;
unsigned Addr = CA->getZExtValue();
unsigned HaveAlign = Addr != 0 ? 1u << countTrailingZeros(Addr) : NeedAlign;
if (HaveAlign < NeedAlign) {
  std::string ErrMsg;
  raw_string_ostream O(ErrMsg);
  O << "Misaligned constant address: " << format_hex(Addr, 10)
    << " has alignment " << HaveAlign
    << ", but the memory access requires " << NeedAlign;
  if (DebugLoc DL = dl.getDebugLoc())
    DL.print(O << ", at ");
  report_fatal_error(O.str());
}
1695}

1697// Bit-reverse Load Intrinsic: Check if the instruction is a bit reverse load
1698// intrinsic.
1699static bool isBrevLdIntrinsic(const Value *Inst) {
unsigned ID = cast<IntrinsicInst>(Inst)->getIntrinsicID();
return (ID == Intrinsic::hexagon_L2_loadrd_pbr ||
        ID == Intrinsic::hexagon_L2_loadri_pbr ||
        ID == Intrinsic::hexagon_L2_loadrh_pbr ||
        ID == Intrinsic::hexagon_L2_loadruh_pbr ||
        ID == Intrinsic::hexagon_L2_loadrb_pbr ||
        ID == Intrinsic::hexagon_L2_loadrub_pbr);
1707}

1709// Bit-reverse Load Intrinsic :Crawl up and figure out the object from previous
1710// instruction. So far we only handle bitcast, extract value and bit reverse
1711// load intrinsic instructions. Should we handle CGEP ?
1712static Value *getBrevLdObject(Value *V) {
if (Operator::getOpcode(V) == Instruction::ExtractValue ||
    Operator::getOpcode(V) == Instruction::BitCast)
  V = cast<Operator>(V)->getOperand(0);
else if (isa<IntrinsicInst>(V) && isBrevLdIntrinsic(V))
  V = cast<Instruction>(V)->getOperand(0);
return V;
1719}

1721// Bit-reverse Load Intrinsic: For a PHI Node return either an incoming edge or
1722// a back edge. If the back edge comes from the intrinsic itself, the incoming
1723// edge is returned.
1724static Value *returnEdge(const PHINode *PN, Value *IntrBaseVal) {
const BasicBlock *Parent = PN->getParent();
int Idx = -1;
for (unsigned i = 0, e = PN->getNumIncomingValues(); i < e; ++i) {
  BasicBlock *Blk = PN->getIncomingBlock(i);
  // Determine if the back edge is originated from intrinsic.
  if (Blk == Parent) {
    Value *BackEdgeVal = PN->getIncomingValue(i);
    Value *BaseVal;
    // Loop over till we return the same Value or we hit the IntrBaseVal.
    do {
      BaseVal = BackEdgeVal;
      BackEdgeVal = getBrevLdObject(BackEdgeVal);
    } while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
    // If the getBrevLdObject returns IntrBaseVal, we should return the
    // incoming edge.
    if (IntrBaseVal == BackEdgeVal)
      continue;
    Idx = i;
    break;
  } else // Set the node to incoming edge.
    Idx = i;
}
assert(Idx >= 0 && "Unexpected index to incoming argument in PHI")((Idx >= 0 && "Unexpected index to incoming argument in PHI"
) ? static_cast<void> (0) : __assert_fail ("Idx >= 0 && \"Unexpected index to incoming argument in PHI\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1747, __PRETTY_FUNCTION__));
return PN->getIncomingValue(Idx);
1749}

1751// Bit-reverse Load Intrinsic: Figure out the underlying object the base
1752// pointer points to, for the bit-reverse load intrinsic. Setting this to
1753// memoperand might help alias analysis to figure out the dependencies.
1754static Value *getUnderLyingObjectForBrevLdIntr(Value *V) {
Value *IntrBaseVal = V;
Value *BaseVal;
// Loop over till we return the same Value, implies we either figure out
// the object or we hit a PHI
do {
  BaseVal = V;
  V = getBrevLdObject(V);
} while (BaseVal != V);

// Identify the object from PHINode.
if (const PHINode *PN = dyn_cast<PHINode>(V))
  return returnEdge(PN, IntrBaseVal);
// For non PHI nodes, the object is the last value returned by getBrevLdObject
else
  return V;
1770}

1772/// Given an intrinsic, checks if on the target the intrinsic will need to map
1773/// to a MemIntrinsicNode (touches memory). If this is the case, it returns
1774/// true and store the intrinsic information into the IntrinsicInfo that was
1775/// passed to the function.
1776bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
                                             const CallInst &I,
                                             MachineFunction &MF,
                                             unsigned Intrinsic) const {
switch (Intrinsic) {
case Intrinsic::hexagon_L2_loadrd_pbr:
case Intrinsic::hexagon_L2_loadri_pbr:
case Intrinsic::hexagon_L2_loadrh_pbr:
case Intrinsic::hexagon_L2_loadruh_pbr:
case Intrinsic::hexagon_L2_loadrb_pbr:
case Intrinsic::hexagon_L2_loadrub_pbr: {
  Info.opc = ISD::INTRINSIC_W_CHAIN;
  auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
  auto &Cont = I.getCalledFunction()->getParent()->getContext();
  // The intrinsic function call is of the form { ElTy, i8* }
  // @llvm.hexagon.L2.loadXX.pbr(i8*, i32). The pointer and memory access type
  // should be derived from ElTy.
  Type *ElTy = I.getCalledFunction()->getReturnType()->getStructElementType(0);
  Info.memVT = MVT::getVT(ElTy);
  llvm::Value *BasePtrVal = I.getOperand(0);
  Info.ptrVal = getUnderLyingObjectForBrevLdIntr(BasePtrVal);
  // The offset value comes through Modifier register. For now, assume the
  // offset is 0.
  Info.offset = 0;
  Info.align =
      MaybeAlign(DL.getABITypeAlignment(Info.memVT.getTypeForEVT(Cont)));
  Info.flags = MachineMemOperand::MOLoad;
  return true;
}
case Intrinsic::hexagon_V6_vgathermw:
case Intrinsic::hexagon_V6_vgathermw_128B:
case Intrinsic::hexagon_V6_vgathermh:
case Intrinsic::hexagon_V6_vgathermh_128B:
case Intrinsic::hexagon_V6_vgathermhw:
case Intrinsic::hexagon_V6_vgathermhw_128B:
case Intrinsic::hexagon_V6_vgathermwq:
case Intrinsic::hexagon_V6_vgathermwq_128B:
case Intrinsic::hexagon_V6_vgathermhq:
case Intrinsic::hexagon_V6_vgathermhq_128B:
case Intrinsic::hexagon_V6_vgathermhwq:
case Intrinsic::hexagon_V6_vgathermhwq_128B: {
  const Module &M = *I.getParent()->getParent()->getParent();
  Info.opc = ISD::INTRINSIC_W_CHAIN;
  Type *VecTy = I.getArgOperand(1)->getType();
  Info.memVT = MVT::getVT(VecTy);
  Info.ptrVal = I.getArgOperand(0);
  Info.offset = 0;
  Info.align =
      MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
  Info.flags = MachineMemOperand::MOLoad |
               MachineMemOperand::MOStore |
               MachineMemOperand::MOVolatile;
  return true;
}
default:
  break;
}
return false;
1834}

1836bool HexagonTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
return X.getValueType().isScalarInteger(); // 'tstbit'
1838}

1840bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
return isTruncateFree(EVT::getEVT(Ty1), EVT::getEVT(Ty2));
1842}

1844bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
if (!VT1.isSimple() || !VT2.isSimple())
  return false;
return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32;
1848}

1850bool HexagonTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
return isOperationLegalOrCustom(ISD::FMA, VT);
1852}

1854// Should we expand the build vector with shuffles?
1855bool HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
    unsigned DefinedValues) const {
return false;
1858}

1860bool HexagonTargetLowering::isShuffleMaskLegal(ArrayRef<int> Mask,
                                             EVT VT) const {
return true;
1863}

1865TargetLoweringBase::LegalizeTypeAction
1866HexagonTargetLowering::getPreferredVectorAction(MVT VT) const {
unsigned VecLen = VT.getVectorNumElements();
MVT ElemTy = VT.getVectorElementType();

if (VecLen == 1 || VT.isScalableVector())
  return TargetLoweringBase::TypeScalarizeVector;

if (Subtarget.useHVXOps()) {
  unsigned HwLen = Subtarget.getVectorLength();
  // If the size of VT is at least half of the vector length,
  // widen the vector. Note: the threshold was not selected in
  // any scientific way.
  ArrayRef<MVT> Tys = Subtarget.getHVXElementTypes();
  if (llvm::find(Tys, ElemTy) != Tys.end()) {
    unsigned HwWidth = 8*HwLen;
    unsigned VecWidth = VT.getSizeInBits();
    if (VecWidth >= HwWidth/2 && VecWidth < HwWidth)
      return TargetLoweringBase::TypeWidenVector;
  }
  // Split vectors of i1 that correspond to (byte) vector pairs.
  if (ElemTy == MVT::i1 && VecLen == 2*HwLen)
    return TargetLoweringBase::TypeSplitVector;
}

// Always widen (remaining) vectors of i1.
if (ElemTy == MVT::i1)
  return TargetLoweringBase::TypeWidenVector;

return TargetLoweringBase::TypeSplitVector;
1895}

1897std::pair<SDValue, int>
1898HexagonTargetLowering::getBaseAndOffset(SDValue Addr) const {
if (Addr.getOpcode() == ISD::ADD) {
  SDValue Op1 = Addr.getOperand(1);
  if (auto *CN = dyn_cast<const ConstantSDNode>(Op1.getNode()))
    return { Addr.getOperand(0), CN->getSExtValue() };
}
return { Addr, 0 };
1905}

1907// Lower a vector shuffle (V1, V2, V3).  V1 and V2 are the two vectors
1908// to select data from, V3 is the permutation.
1909SDValue
1910HexagonTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
    const {
const auto *SVN = cast<ShuffleVectorSDNode>(Op);
ArrayRef<int> AM = SVN->getMask();
assert(AM.size() <= 8 && "Unexpected shuffle mask")((AM.size() <= 8 && "Unexpected shuffle mask") ? static_cast
<void> (0) : __assert_fail ("AM.size() <= 8 && \"Unexpected shuffle mask\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1914, __PRETTY_FUNCTION__));
unsigned VecLen = AM.size();

MVT VecTy = ty(Op);
assert(!Subtarget.isHVXVectorType(VecTy, true) &&((!Subtarget.isHVXVectorType(VecTy, true) && "HVX shuffles should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isHVXVectorType(VecTy, true) && \"HVX shuffles should be legal\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1919, __PRETTY_FUNCTION__))
       "HVX shuffles should be legal")((!Subtarget.isHVXVectorType(VecTy, true) && "HVX shuffles should be legal"
) ? static_cast<void> (0) : __assert_fail ("!Subtarget.isHVXVectorType(VecTy, true) && \"HVX shuffles should be legal\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1919, __PRETTY_FUNCTION__));
assert(VecTy.getSizeInBits() <= 64 && "Unexpected vector length")((VecTy.getSizeInBits() <= 64 && "Unexpected vector length"
) ? static_cast<void> (0) : __assert_fail ("VecTy.getSizeInBits() <= 64 && \"Unexpected vector length\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1920, __PRETTY_FUNCTION__));

SDValue Op0 = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
const SDLoc &dl(Op);

// If the inputs are not the same as the output, bail. This is not an
// error situation, but complicates the handling and the default expansion
// (into BUILD_VECTOR) should be adequate.
if (ty(Op0) != VecTy || ty(Op1) != VecTy)
  return SDValue();

// Normalize the mask so that the first non-negative index comes from
// the first operand.
SmallVector<int,8> Mask(AM.begin(), AM.end());
unsigned F = llvm::find_if(AM, [](int M) { return M >= 0; }) - AM.data();
if (F == AM.size())
  return DAG.getUNDEF(VecTy);
if (AM[F] >= int(VecLen)) {
  ShuffleVectorSDNode::commuteMask(Mask);
  std::swap(Op0, Op1);
}

// Express the shuffle mask in terms of bytes.
SmallVector<int,8> ByteMask;
unsigned ElemBytes = VecTy.getVectorElementType().getSizeInBits() / 8;
for (unsigned i = 0, e = Mask.size(); i != e; ++i) {
  int M = Mask[i];
  if (M < 0) {
    for (unsigned j = 0; j != ElemBytes; ++j)
      ByteMask.push_back(-1);
  } else {
    for (unsigned j = 0; j != ElemBytes; ++j)
      ByteMask.push_back(M*ElemBytes + j);
  }
}
assert(ByteMask.size() <= 8)((ByteMask.size() <= 8) ? static_cast<void> (0) : __assert_fail
 ("ByteMask.size() <= 8", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 1956, __PRETTY_FUNCTION__));

// All non-undef (non-negative) indexes are well within [0..127], so they
// fit in a single byte. Build two 64-bit words:
// - MaskIdx where each byte is the corresponding index (for non-negative
//   indexes), and 0xFF for negative indexes, and
// - MaskUnd that has 0xFF for each negative index.
uint64_t MaskIdx = 0;
uint64_t MaskUnd = 0;
for (unsigned i = 0, e = ByteMask.size(); i != e; ++i) {
  unsigned S = 8*i;
  uint64_t M = ByteMask[i] & 0xFF;
  if (M == 0xFF)
    MaskUnd |= M << S;
  MaskIdx |= M << S;
}

if (ByteMask.size() == 4) {
  // Identity.
  if (MaskIdx == (0x03020100 | MaskUnd))
    return Op0;
  // Byte swap.
  if (MaskIdx == (0x00010203 | MaskUnd)) {
    SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
    SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
    return DAG.getBitcast(VecTy, T1);
  }

  // Byte packs.
  SDValue Concat10 = DAG.getNode(HexagonISD::COMBINE, dl,
                                 typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0});
  if (MaskIdx == (0x06040200 | MaskUnd))
    return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
  if (MaskIdx == (0x07050301 | MaskUnd))
    return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);

  SDValue Concat01 = DAG.getNode(HexagonISD::COMBINE, dl,
                                 typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1});
  if (MaskIdx == (0x02000604 | MaskUnd))
    return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
  if (MaskIdx == (0x03010705 | MaskUnd))
    return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
}

if (ByteMask.size() == 8) {
  // Identity.
  if (MaskIdx == (0x0706050403020100ull | MaskUnd))
    return Op0;
  // Byte swap.
  if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
    SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
    SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
    return DAG.getBitcast(VecTy, T1);
  }

  // Halfword picks.
  if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
    return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
  if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
    return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
  if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
    return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
  if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
    return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
  if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
    VectorPair P = opSplit(Op0, dl, DAG);
    return getInstr(Hexagon::S2_packhl, dl, VecTy, {P.second, P.first}, DAG);
  }

  // Byte packs.
  if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
    return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
  if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
    return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
}

return SDValue();
2033}

2035// Create a Hexagon-specific node for shifting a vector by an integer.
2036SDValue
2037HexagonTargetLowering::getVectorShiftByInt(SDValue Op, SelectionDAG &DAG)
    const {
if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) {
  if (SDValue S = BVN->getSplatValue()) {
    unsigned NewOpc;
    switch (Op.getOpcode()) {
      case ISD::SHL:
        NewOpc = HexagonISD::VASL;
        break;
      case ISD::SRA:
        NewOpc = HexagonISD::VASR;
        break;
      case ISD::SRL:
        NewOpc = HexagonISD::VLSR;
        break;
      default:
        llvm_unreachable("Unexpected shift opcode")::llvm::llvm_unreachable_internal("Unexpected shift opcode", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2053);
    }
    return DAG.getNode(NewOpc, SDLoc(Op), ty(Op), Op.getOperand(0), S);
  }
}

return SDValue();
2060}

2062SDValue
2063HexagonTargetLowering::LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const {
return getVectorShiftByInt(Op, DAG);
2065}

2067SDValue
2068HexagonTargetLowering::LowerROTL(SDValue Op, SelectionDAG &DAG) const {
if (isa<ConstantSDNode>(Op.getOperand(1).getNode()))
  return Op;
return SDValue();
2072}

2074SDValue
2075HexagonTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
MVT ResTy = ty(Op);
SDValue InpV = Op.getOperand(0);
MVT InpTy = ty(InpV);
assert(ResTy.getSizeInBits() == InpTy.getSizeInBits())((ResTy.getSizeInBits() == InpTy.getSizeInBits()) ? static_cast
<void> (0) : __assert_fail ("ResTy.getSizeInBits() == InpTy.getSizeInBits()"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2079, __PRETTY_FUNCTION__));
const SDLoc &dl(Op);

// Handle conversion from i8 to v8i1.
if (ResTy == MVT::v8i1) {
  SDValue Sc = DAG.getBitcast(tyScalar(InpTy), InpV);
  SDValue Ext = DAG.getZExtOrTrunc(Sc, dl, MVT::i32);
  return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
}

return SDValue();
2090}

2092bool
2093HexagonTargetLowering::getBuildVectorConstInts(ArrayRef<SDValue> Values,
    MVT VecTy, SelectionDAG &DAG,
    MutableArrayRef<ConstantInt*> Consts) const {
MVT ElemTy = VecTy.getVectorElementType();
unsigned ElemWidth = ElemTy.getSizeInBits();
IntegerType *IntTy = IntegerType::get(*DAG.getContext(), ElemWidth);
bool AllConst = true;

for (unsigned i = 0, e = Values.size(); i != e; ++i) {
  SDValue V = Values[i];
  if (V.isUndef()) {
    Consts[i] = ConstantInt::get(IntTy, 0);
    continue;
  }
  // Make sure to always cast to IntTy.
  if (auto *CN = dyn_cast<ConstantSDNode>(V.getNode())) {
    const ConstantInt *CI = CN->getConstantIntValue();
    Consts[i] = ConstantInt::get(IntTy, CI->getValue().getSExtValue());
  } else if (auto *CN = dyn_cast<ConstantFPSDNode>(V.getNode())) {
    const ConstantFP *CF = CN->getConstantFPValue();
    APInt A = CF->getValueAPF().bitcastToAPInt();
    Consts[i] = ConstantInt::get(IntTy, A.getZExtValue());
  } else {
    AllConst = false;
  }
}
return AllConst;
2120}

2122SDValue
2123HexagonTargetLowering::buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl,
                                   MVT VecTy, SelectionDAG &DAG) const {
MVT ElemTy = VecTy.getVectorElementType();
assert(VecTy.getVectorNumElements() == Elem.size())((VecTy.getVectorNumElements() == Elem.size()) ? static_cast<
void> (0) : __assert_fail ("VecTy.getVectorNumElements() == Elem.size()"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2126, __PRETTY_FUNCTION__));

SmallVector<ConstantInt*,4> Consts(Elem.size());
bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);

unsigned First, Num = Elem.size();
for (First = 0; First != Num; ++First)
  if (!isUndef(Elem[First]))
    break;
if (First == Num)
  return DAG.getUNDEF(VecTy);

if (AllConst &&
    llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
  return getZero(dl, VecTy, DAG);

if (ElemTy == MVT::i16) {
  assert(Elem.size() == 2)((Elem.size() == 2) ? static_cast<void> (0) : __assert_fail
 ("Elem.size() == 2", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2143, __PRETTY_FUNCTION__));
  if (AllConst) {
    uint32_t V = (Consts[0]->getZExtValue() & 0xFFFF) |
                 Consts[1]->getZExtValue() << 16;
    return DAG.getBitcast(MVT::v2i16, DAG.getConstant(V, dl, MVT::i32));
  }
  SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32,
                       {Elem[1], Elem[0]}, DAG);
  return DAG.getBitcast(MVT::v2i16, N);
}

if (ElemTy == MVT::i8) {
  // First try generating a constant.
  if (AllConst) {
    int32_t V = (Consts[0]->getZExtValue() & 0xFF) |
                (Consts[1]->getZExtValue() & 0xFF) << 8 |
                (Consts[1]->getZExtValue() & 0xFF) << 16 |
                Consts[2]->getZExtValue() << 24;
    return DAG.getBitcast(MVT::v4i8, DAG.getConstant(V, dl, MVT::i32));
  }

  // Then try splat.
  bool IsSplat = true;
  for (unsigned i = 0; i != Num; ++i) {
    if (i == First)
      continue;
    if (Elem[i] == Elem[First] || isUndef(Elem[i]))
      continue;
    IsSplat = false;
    break;
  }
  if (IsSplat) {
    // Legalize the operand to VSPLAT.
    SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
    return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
  }

  // Generate
  //   (zxtb(Elem[0]) | (zxtb(Elem[1]) << 8)) |
  //   (zxtb(Elem[2]) | (zxtb(Elem[3]) << 8)) << 16
  assert(Elem.size() == 4)((Elem.size() == 4) ? static_cast<void> (0) : __assert_fail
 ("Elem.size() == 4", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2183, __PRETTY_FUNCTION__));
  SDValue Vs[4];
  for (unsigned i = 0; i != 4; ++i) {
    Vs[i] = DAG.getZExtOrTrunc(Elem[i], dl, MVT::i32);
    Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8);
  }
  SDValue S8 = DAG.getConstant(8, dl, MVT::i32);
  SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
  SDValue T1 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[3], S8});
  SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
  SDValue B1 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[2], T1});

  SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
  return DAG.getBitcast(MVT::v4i8, R);
}

2199#ifndef NDEBUG
dbgs() << "VecTy: " << EVT(VecTy).getEVTString() << '\n';
2201#endif
llvm_unreachable("Unexpected vector element type")::llvm::llvm_unreachable_internal("Unexpected vector element type"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2202);
2203}

2205SDValue
2206HexagonTargetLowering::buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl,
                                   MVT VecTy, SelectionDAG &DAG) const {
MVT ElemTy = VecTy.getVectorElementType();
assert(VecTy.getVectorNumElements() == Elem.size())((VecTy.getVectorNumElements() == Elem.size()) ? static_cast<
void> (0) : __assert_fail ("VecTy.getVectorNumElements() == Elem.size()"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2209, __PRETTY_FUNCTION__));

SmallVector<ConstantInt*,8> Consts(Elem.size());
bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);

unsigned First, Num = Elem.size();
for (First = 0; First != Num; ++First)
  if (!isUndef(Elem[First]))
    break;
if (First == Num)
  return DAG.getUNDEF(VecTy);

if (AllConst &&
    llvm::all_of(Consts, [](ConstantInt *CI) { return CI->isZero(); }))
  return getZero(dl, VecTy, DAG);

// First try splat if possible.
if (ElemTy == MVT::i16) {
  bool IsSplat = true;
  for (unsigned i = 0; i != Num; ++i) {
    if (i == First)
      continue;
    if (Elem[i] == Elem[First] || isUndef(Elem[i]))
      continue;
    IsSplat = false;
    break;
  }
  if (IsSplat) {
    // Legalize the operand to VSPLAT.
    SDValue Ext = DAG.getZExtOrTrunc(Elem[First], dl, MVT::i32);
    return DAG.getNode(HexagonISD::VSPLAT, dl, VecTy, Ext);
  }
}

// Then try constant.
if (AllConst) {
  uint64_t Val = 0;
  unsigned W = ElemTy.getSizeInBits();
  uint64_t Mask = (ElemTy == MVT::i8)  ? 0xFFull
                : (ElemTy == MVT::i16) ? 0xFFFFull : 0xFFFFFFFFull;
  for (unsigned i = 0; i != Num; ++i)
    Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
  SDValue V0 = DAG.getConstant(Val, dl, MVT::i64);
  return DAG.getBitcast(VecTy, V0);
}

// Build two 32-bit vectors and concatenate.
MVT HalfTy = MVT::getVectorVT(ElemTy, Num/2);
SDValue L = (ElemTy == MVT::i32)
              ? Elem[0]
              : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
SDValue H = (ElemTy == MVT::i32)
              ? Elem[1]
              : buildVector32(Elem.drop_front(Num/2), dl, HalfTy, DAG);
return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, {H, L});
2264}

2266SDValue
2267HexagonTargetLowering::extractVector(SDValue VecV, SDValue IdxV,
                                   const SDLoc &dl, MVT ValTy, MVT ResTy,
                                   SelectionDAG &DAG) const {
MVT VecTy = ty(VecV);
assert(!ValTy.isVector() ||((!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.
getVectorElementType()) ? static_cast<void> (0) : __assert_fail
 ("!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.getVectorElementType()"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2272, __PRETTY_FUNCTION__))
       VecTy.getVectorElementType() == ValTy.getVectorElementType())((!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.
getVectorElementType()) ? static_cast<void> (0) : __assert_fail
 ("!ValTy.isVector() || VecTy.getVectorElementType() == ValTy.getVectorElementType()"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2272, __PRETTY_FUNCTION__));
unsigned VecWidth = VecTy.getSizeInBits();
unsigned ValWidth = ValTy.getSizeInBits();
unsigned ElemWidth = VecTy.getVectorElementType().getSizeInBits();
assert((VecWidth % ElemWidth) == 0)(((VecWidth % ElemWidth) == 0) ? static_cast<void> (0) :
 __assert_fail ("(VecWidth % ElemWidth) == 0", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2276, __PRETTY_FUNCTION__));
9
←
Assuming the condition is true→
10
←
'?' condition is true→
auto *IdxN = dyn_cast<ConstantSDNode>(IdxV);

// Special case for v{8,4,2}i1 (the only boolean vectors legal in Hexagon
// without any coprocessors).
if (ElemWidth == 1) {
11
←
Assuming 'ElemWidth' is equal to 1→
12
←
Taking true branch→
  assert(VecWidth == VecTy.getVectorNumElements() && "Sanity failure")((VecWidth == VecTy.getVectorNumElements() && "Sanity failure"
) ? static_cast<void> (0) : __assert_fail ("VecWidth == VecTy.getVectorNumElements() && \"Sanity failure\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2282, __PRETTY_FUNCTION__));
13
←
Assuming the condition is true→
14
←
'?' condition is true→
  assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2)((VecWidth == 8 || VecWidth == 4 || VecWidth == 2) ? static_cast
<void> (0) : __assert_fail ("VecWidth == 8 || VecWidth == 4 || VecWidth == 2"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2283, __PRETTY_FUNCTION__));
15
←
Assuming 'VecWidth' is equal to 8→
  // Check if this is an extract of the lowest bit.
  if (IdxN) {
16
←
Assuming 'IdxN' is null→
17
←
Assuming pointer value is null→
18
←
Taking false branch→
    // Extracting the lowest bit is a no-op, but it changes the type,
    // so it must be kept as an operation to avoid errors related to
    // type mismatches.
    if (IdxN->isNullValue() && ValTy.getSizeInBits() == 1)
      return DAG.getNode(HexagonISD::TYPECAST, dl, MVT::i1, VecV);
  }

  // If the value extracted is a single bit, use tstbit.
  if (ValWidth == 1) {
19
←
Assuming 'ValWidth' is not equal to 1→
20
←
Taking false branch→
    SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
    SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
    SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
    return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
  }

  // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in
  // a predicate register. The elements of the vector are repeated
  // in the register (if necessary) so that the total number is 8.
  // The extracted subvector will need to be expanded in such a way.
  unsigned Scale = VecWidth / ValWidth;

  // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
  // position 0.
  assert(ty(IdxV) == MVT::i32)((ty(IdxV) == MVT::i32) ? static_cast<void> (0) : __assert_fail
 ("ty(IdxV) == MVT::i32", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2309, __PRETTY_FUNCTION__));
21
←
Value assigned to 'Op.Node'→
22
←
Calling 'HexagonTargetLowering::ty'→
  unsigned VecRep = 8 / VecWidth;
  SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
                           DAG.getConstant(8*VecRep, dl, MVT::i32));
  SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
  SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
  while (Scale > 1) {
    // The longest possible subvector is at most 32 bits, so it is always
    // contained in the low subregister.
    T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1);
    T1 = expandPredicate(T1, dl, DAG);
    Scale /= 2;
  }

  return DAG.getNode(HexagonISD::D2P, dl, ResTy, T1);
}

assert(VecWidth == 32 || VecWidth == 64)((VecWidth == 32 || VecWidth == 64) ? static_cast<void>
 (0) : __assert_fail ("VecWidth == 32 || VecWidth == 64", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2326, __PRETTY_FUNCTION__));

// Cast everything to scalar integer types.
MVT ScalarTy = tyScalar(VecTy);
VecV = DAG.getBitcast(ScalarTy, VecV);

SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
SDValue ExtV;

if (IdxN) {
  unsigned Off = IdxN->getZExtValue() * ElemWidth;
  if (VecWidth == 64 && ValWidth == 32) {
    assert(Off == 0 || Off == 32)((Off == 0 || Off == 32) ? static_cast<void> (0) : __assert_fail
 ("Off == 0 || Off == 32", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2338, __PRETTY_FUNCTION__));
    unsigned SubIdx = Off == 0 ? Hexagon::isub_lo : Hexagon::isub_hi;
    ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV);
  } else if (Off == 0 && (ValWidth % 8) == 0) {
    ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy));
  } else {
    SDValue OffV = DAG.getConstant(Off, dl, MVT::i32);
    // The return type of EXTRACTU must be the same as the type of the
    // input vector.
    ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
                       {VecV, WidthV, OffV});
  }
} else {
  if (ty(IdxV) != MVT::i32)
    IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
                             DAG.getConstant(ElemWidth, dl, MVT::i32));
  ExtV = DAG.getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
                     {VecV, WidthV, OffV});
}

// Cast ExtV to the requested result type.
ExtV = DAG.getZExtOrTrunc(ExtV, dl, tyScalar(ResTy));
ExtV = DAG.getBitcast(ResTy, ExtV);
return ExtV;
2363}

2365SDValue
2366HexagonTargetLowering::insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
                                  const SDLoc &dl, MVT ValTy,
                                  SelectionDAG &DAG) const {
MVT VecTy = ty(VecV);
if (VecTy.getVectorElementType() == MVT::i1) {
  MVT ValTy = ty(ValV);
  assert(ValTy.getVectorElementType() == MVT::i1)((ValTy.getVectorElementType() == MVT::i1) ? static_cast<void
> (0) : __assert_fail ("ValTy.getVectorElementType() == MVT::i1"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2372, __PRETTY_FUNCTION__));
  SDValue ValR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, ValV);
  unsigned VecLen = VecTy.getVectorNumElements();
  unsigned Scale = VecLen / ValTy.getVectorNumElements();
  assert(Scale > 1)((Scale > 1) ? static_cast<void> (0) : __assert_fail
 ("Scale > 1", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2376, __PRETTY_FUNCTION__));

  for (unsigned R = Scale; R > 1; R /= 2) {
    ValR = contractPredicate(ValR, dl, DAG);
    ValR = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
                       DAG.getUNDEF(MVT::i32), ValR);
  }
  // The longest possible subvector is at most 32 bits, so it is always
  // contained in the low subregister.
  ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR);

  unsigned ValBytes = 64 / Scale;
  SDValue Width = DAG.getConstant(ValBytes*8, dl, MVT::i32);
  SDValue Idx = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
                            DAG.getConstant(8, dl, MVT::i32));
  SDValue VecR = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
  SDValue Ins = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32,
                            {VecR, ValR, Width, Idx});
  return DAG.getNode(HexagonISD::D2P, dl, VecTy, Ins);
}

unsigned VecWidth = VecTy.getSizeInBits();
unsigned ValWidth = ValTy.getSizeInBits();
assert(VecWidth == 32 || VecWidth == 64)((VecWidth == 32 || VecWidth == 64) ? static_cast<void>
 (0) : __assert_fail ("VecWidth == 32 || VecWidth == 64", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2399, __PRETTY_FUNCTION__));
assert((VecWidth % ValWidth) == 0)(((VecWidth % ValWidth) == 0) ? static_cast<void> (0) :
 __assert_fail ("(VecWidth % ValWidth) == 0", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2400, __PRETTY_FUNCTION__));

// Cast everything to scalar integer types.
MVT ScalarTy = MVT::getIntegerVT(VecWidth);
// The actual type of ValV may be different than ValTy (which is related
// to the vector type).
unsigned VW = ty(ValV).getSizeInBits();
ValV = DAG.getBitcast(MVT::getIntegerVT(VW), ValV);
VecV = DAG.getBitcast(ScalarTy, VecV);
if (VW != VecWidth)
  ValV = DAG.getAnyExtOrTrunc(ValV, dl, ScalarTy);

SDValue WidthV = DAG.getConstant(ValWidth, dl, MVT::i32);
SDValue InsV;

if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(IdxV)) {
  unsigned W = C->getZExtValue() * ValWidth;
  SDValue OffV = DAG.getConstant(W, dl, MVT::i32);
  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
                     {VecV, ValV, WidthV, OffV});
} else {
  if (ty(IdxV) != MVT::i32)
    IdxV = DAG.getZExtOrTrunc(IdxV, dl, MVT::i32);
  SDValue OffV = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, WidthV);
  InsV = DAG.getNode(HexagonISD::INSERT, dl, ScalarTy,
                     {VecV, ValV, WidthV, OffV});
}

return DAG.getNode(ISD::BITCAST, dl, VecTy, InsV);
2429}

2431SDValue
2432HexagonTargetLowering::expandPredicate(SDValue Vec32, const SDLoc &dl,
                                     SelectionDAG &DAG) const {
assert(ty(Vec32).getSizeInBits() == 32)((ty(Vec32).getSizeInBits() == 32) ? static_cast<void> (
0) : __assert_fail ("ty(Vec32).getSizeInBits() == 32", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2434, __PRETTY_FUNCTION__));
if (isUndef(Vec32))
  return DAG.getUNDEF(MVT::i64);
return getInstr(Hexagon::S2_vsxtbh, dl, MVT::i64, {Vec32}, DAG);
2438}

2440SDValue
2441HexagonTargetLowering::contractPredicate(SDValue Vec64, const SDLoc &dl,
                                       SelectionDAG &DAG) const {
assert(ty(Vec64).getSizeInBits() == 64)((ty(Vec64).getSizeInBits() == 64) ? static_cast<void> (
0) : __assert_fail ("ty(Vec64).getSizeInBits() == 64", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2443, __PRETTY_FUNCTION__));
if (isUndef(Vec64))
  return DAG.getUNDEF(MVT::i32);
return getInstr(Hexagon::S2_vtrunehb, dl, MVT::i32, {Vec64}, DAG);
2447}

2449SDValue
2450HexagonTargetLowering::getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG)
    const {
if (Ty.isVector()) {
  assert(Ty.isInteger() && "Only integer vectors are supported here")((Ty.isInteger() && "Only integer vectors are supported here"
) ? static_cast<void> (0) : __assert_fail ("Ty.isInteger() && \"Only integer vectors are supported here\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2453, __PRETTY_FUNCTION__));
  unsigned W = Ty.getSizeInBits();
  if (W <= 64)
    return DAG.getBitcast(Ty, DAG.getConstant(0, dl, MVT::getIntegerVT(W)));
  return DAG.getNode(HexagonISD::VZERO, dl, Ty);
}

if (Ty.isInteger())
  return DAG.getConstant(0, dl, Ty);
if (Ty.isFloatingPoint())
  return DAG.getConstantFP(0.0, dl, Ty);
llvm_unreachable("Invalid type for zero")::llvm::llvm_unreachable_internal("Invalid type for zero", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2464);
2465}

2467SDValue
2468HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
MVT VecTy = ty(Op);
unsigned BW = VecTy.getSizeInBits();
const SDLoc &dl(Op);
SmallVector<SDValue,8> Ops;
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
  Ops.push_back(Op.getOperand(i));

if (BW == 32)
  return buildVector32(Ops, dl, VecTy, DAG);
if (BW == 64)
  return buildVector64(Ops, dl, VecTy, DAG);

if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
  // Check if this is a special case or all-0 or all-1.
  bool All0 = true, All1 = true;
  for (SDValue P : Ops) {
    auto *CN = dyn_cast<ConstantSDNode>(P.getNode());
    if (CN == nullptr) {
      All0 = All1 = false;
      break;
    }
    uint32_t C = CN->getZExtValue();
    All0 &= (C == 0);
    All1 &= (C == 1);
  }
  if (All0)
    return DAG.getNode(HexagonISD::PFALSE, dl, VecTy);
  if (All1)
    return DAG.getNode(HexagonISD::PTRUE, dl, VecTy);

  // For each i1 element in the resulting predicate register, put 1
  // shifted by the index of the element into a general-purpose register,
  // then or them together and transfer it back into a predicate register.
  SDValue Rs[8];
  SDValue Z = getZero(dl, MVT::i32, DAG);
  // Always produce 8 bits, repeat inputs if necessary.
  unsigned Rep = 8 / VecTy.getVectorNumElements();
  for (unsigned i = 0; i != 8; ++i) {
    SDValue S = DAG.getConstant(1ull << i, dl, MVT::i32);
    Rs[i] = DAG.getSelect(dl, MVT::i32, Ops[i/Rep], S, Z);
  }
  for (ArrayRef<SDValue> A(Rs); A.size() != 1; A = A.drop_back(A.size()/2)) {
    for (unsigned i = 0, e = A.size()/2; i != e; ++i)
      Rs[i] = DAG.getNode(ISD::OR, dl, MVT::i32, Rs[2*i], Rs[2*i+1]);
  }
  // Move the value directly to a predicate register.
  return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
}

return SDValue();
2519}

2521SDValue
2522HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
                                         SelectionDAG &DAG) const {
MVT VecTy = ty(Op);
const SDLoc &dl(Op);
if (VecTy.getSizeInBits() == 64) {
  assert(Op.getNumOperands() == 2)((Op.getNumOperands() == 2) ? static_cast<void> (0) : __assert_fail
 ("Op.getNumOperands() == 2", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2527, __PRETTY_FUNCTION__));
  return DAG.getNode(HexagonISD::COMBINE, dl, VecTy, Op.getOperand(1),
                     Op.getOperand(0));
}

MVT ElemTy = VecTy.getVectorElementType();
if (ElemTy == MVT::i1) {
  assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1)((VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1
) ? static_cast<void> (0) : __assert_fail ("VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2534, __PRETTY_FUNCTION__));
  MVT OpTy = ty(Op.getOperand(0));
  // Scale is how many times the operands need to be contracted to match
  // the representation in the target register.
  unsigned Scale = VecTy.getVectorNumElements() / OpTy.getVectorNumElements();
  assert(Scale == Op.getNumOperands() && Scale > 1)((Scale == Op.getNumOperands() && Scale > 1) ? static_cast
<void> (0) : __assert_fail ("Scale == Op.getNumOperands() && Scale > 1"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2539, __PRETTY_FUNCTION__));

  // First, convert all bool vectors to integers, then generate pairwise
  // inserts to form values of doubled length. Up until there are only
  // two values left to concatenate, all of these values will fit in a
  // 32-bit integer, so keep them as i32 to use 32-bit inserts.
  SmallVector<SDValue,4> Words[2];
  unsigned IdxW = 0;

  for (SDValue P : Op.getNode()->op_values()) {
    SDValue W = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, P);
    for (unsigned R = Scale; R > 1; R /= 2) {
      W = contractPredicate(W, dl, DAG);
      W = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
                      DAG.getUNDEF(MVT::i32), W);
    }
    W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W);
    Words[IdxW].push_back(W);
  }

  while (Scale > 2) {
    SDValue WidthV = DAG.getConstant(64 / Scale, dl, MVT::i32);
    Words[IdxW ^ 1].clear();

    for (unsigned i = 0, e = Words[IdxW].size(); i != e; i += 2) {
      SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
      // Insert W1 into W0 right next to the significant bits of W0.
      SDValue T = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32,
                              {W0, W1, WidthV, WidthV});
      Words[IdxW ^ 1].push_back(T);
    }
    IdxW ^= 1;
    Scale /= 2;
  }

  // Another sanity check. At this point there should only be two words
  // left, and Scale should be 2.
  assert(Scale == 2 && Words[IdxW].size() == 2)((Scale == 2 && Words[IdxW].size() == 2) ? static_cast
<void> (0) : __assert_fail ("Scale == 2 && Words[IdxW].size() == 2"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2576, __PRETTY_FUNCTION__));

  SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64,
                           Words[IdxW][1], Words[IdxW][0]);
  return DAG.getNode(HexagonISD::D2P, dl, VecTy, WW);
}

return SDValue();
2584}

2586SDValue
2587HexagonTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
                                             SelectionDAG &DAG) const {
SDValue Vec = Op.getOperand(0);
MVT ElemTy = ty(Vec).getVectorElementType();
return extractVector(Vec, Op.getOperand(1), SDLoc(Op), ElemTy, ty(Op), DAG);
2592}

2594SDValue
2595HexagonTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
                                            SelectionDAG &DAG) const {
return extractVector(Op.getOperand(0), Op.getOperand(1), SDLoc(Op),
8
←
Calling 'HexagonTargetLowering::extractVector'→
                     ty(Op), ty(Op), DAG);
2599}

2601SDValue
2602HexagonTargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
                                            SelectionDAG &DAG) const {
return insertVector(Op.getOperand(0), Op.getOperand(1), Op.getOperand(2),
                    SDLoc(Op), ty(Op).getVectorElementType(), DAG);
2606}

2608SDValue
2609HexagonTargetLowering::LowerINSERT_SUBVECTOR(SDValue Op,
                                           SelectionDAG &DAG) const {
SDValue ValV = Op.getOperand(1);
return insertVector(Op.getOperand(0), ValV, Op.getOperand(2),
                    SDLoc(Op), ty(ValV), DAG);
2614}

2616bool
2617HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
// Assuming the caller does not have either a signext or zeroext modifier, and
// only one value is accepted, any reasonable truncation is allowed.
if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
  return false;

// FIXME: in principle up to 64-bit could be made safe, but it would be very
// fragile at the moment: any support for multiple value returns would be
// liable to disallow tail calls involving i64 -> iN truncation in many cases.
return Ty1->getPrimitiveSizeInBits() <= 32;
2627}

2629SDValue
2630HexagonTargetLowering::LowerLoad(SDValue Op, SelectionDAG &DAG) const {
LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
unsigned ClaimAlign = LN->getAlignment();
validateConstPtrAlignment(LN->getBasePtr(), SDLoc(Op), ClaimAlign);
// Call LowerUnalignedLoad for all loads, it recognizes loads that
// don't need extra aligning.
return LowerUnalignedLoad(Op, DAG);
2637}

2639SDValue
2640HexagonTargetLowering::LowerStore(SDValue Op, SelectionDAG &DAG) const {
StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
unsigned ClaimAlign = SN->getAlignment();
SDValue Ptr = SN->getBasePtr();
const SDLoc &dl(Op);
validateConstPtrAlignment(Ptr, dl, ClaimAlign);

MVT StoreTy = SN->getMemoryVT().getSimpleVT();
unsigned NeedAlign = Subtarget.getTypeAlignment(StoreTy);
if (ClaimAlign < NeedAlign)
  return expandUnalignedStore(SN, DAG);
return Op;
2652}

2654SDValue
2655HexagonTargetLowering::LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG)
    const {
LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
MVT LoadTy = ty(Op);
unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy);
unsigned HaveAlign = LN->getAlignment();
if (HaveAlign >= NeedAlign)
  return Op;

const SDLoc &dl(Op);
const DataLayout &DL = DAG.getDataLayout();
LLVMContext &Ctx = *DAG.getContext();

// If the load aligning is disabled or the load can be broken up into two
// smaller legal loads, do the default (target-independent) expansion.
bool DoDefault = false;
// Handle it in the default way if this is an indexed load.
if (!LN->isUnindexed())
  DoDefault = true;

if (!AlignLoads) {
  if (allowsMemoryAccessForAlignment(Ctx, DL, LN->getMemoryVT(),
                                     *LN->getMemOperand()))
    return Op;
  DoDefault = true;
}
if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
  // The PartTy is the equivalent of "getLoadableTypeOfSize(HaveAlign)".
  MVT PartTy = HaveAlign <= 8 ? MVT::getIntegerVT(8 * HaveAlign)
                              : MVT::getVectorVT(MVT::i8, HaveAlign);
  DoDefault =
      allowsMemoryAccessForAlignment(Ctx, DL, PartTy, *LN->getMemOperand());
}
if (DoDefault) {
  std::pair<SDValue, SDValue> P = expandUnalignedLoad(LN, DAG);
  return DAG.getMergeValues({P.first, P.second}, dl);
}

// The code below generates two loads, both aligned as NeedAlign, and
// with the distance of NeedAlign between them. For that to cover the
// bits that need to be loaded (and without overlapping), the size of
// the loads should be equal to NeedAlign. This is true for all loadable
// types, but add an assertion in case something changes in the future.
assert(LoadTy.getSizeInBits() == 8*NeedAlign)((LoadTy.getSizeInBits() == 8*NeedAlign) ? static_cast<void
> (0) : __assert_fail ("LoadTy.getSizeInBits() == 8*NeedAlign"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2698, __PRETTY_FUNCTION__));

unsigned LoadLen = NeedAlign;
SDValue Base = LN->getBasePtr();
SDValue Chain = LN->getChain();
auto BO = getBaseAndOffset(Base);
unsigned BaseOpc = BO.first.getOpcode();
if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
  return Op;

if (BO.second % LoadLen != 0) {
  BO.first = DAG.getNode(ISD::ADD, dl, MVT::i32, BO.first,
                         DAG.getConstant(BO.second % LoadLen, dl, MVT::i32));
  BO.second -= BO.second % LoadLen;
}
SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
    ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
                  DAG.getConstant(NeedAlign, dl, MVT::i32))
    : BO.first;
SDValue Base0 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second, dl);
SDValue Base1 = DAG.getMemBasePlusOffset(BaseNoOff, BO.second+LoadLen, dl);

MachineMemOperand *WideMMO = nullptr;
if (MachineMemOperand *MMO = LN->getMemOperand()) {
  MachineFunction &MF = DAG.getMachineFunction();
  WideMMO = MF.getMachineMemOperand(MMO->getPointerInfo(), MMO->getFlags(),
                  2*LoadLen, LoadLen, MMO->getAAInfo(), MMO->getRanges(),
                  MMO->getSyncScopeID(), MMO->getOrdering(),
                  MMO->getFailureOrdering());
}

SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO);
SDValue Load1 = DAG.getLoad(LoadTy, dl, Chain, Base1, WideMMO);

SDValue Aligned = DAG.getNode(HexagonISD::VALIGN, dl, LoadTy,
                              {Load1, Load0, BaseNoOff.getOperand(0)});
SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                               Load0.getValue(1), Load1.getValue(1));
SDValue M = DAG.getMergeValues({Aligned, NewChain}, dl);
return M;
2738}

2740SDValue
2741HexagonTargetLowering::LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const {
SDValue X = Op.getOperand(0), Y = Op.getOperand(1);
auto *CY = dyn_cast<ConstantSDNode>(Y);
if (!CY)
  return SDValue();

const SDLoc &dl(Op);
SDVTList VTs = Op.getNode()->getVTList();
assert(VTs.NumVTs == 2)((VTs.NumVTs == 2) ? static_cast<void> (0) : __assert_fail
 ("VTs.NumVTs == 2", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2749, __PRETTY_FUNCTION__));
assert(VTs.VTs[1] == MVT::i1)((VTs.VTs[1] == MVT::i1) ? static_cast<void> (0) : __assert_fail
 ("VTs.VTs[1] == MVT::i1", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2750, __PRETTY_FUNCTION__));
unsigned Opc = Op.getOpcode();

if (CY) {
  uint32_t VY = CY->getZExtValue();
  assert(VY != 0 && "This should have been folded")((VY != 0 && "This should have been folded") ? static_cast
<void> (0) : __assert_fail ("VY != 0 && \"This should have been folded\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2755, __PRETTY_FUNCTION__));
  // X +/- 1
  if (VY != 1)
    return SDValue();

  if (Opc == ISD::UADDO) {
    SDValue Op = DAG.getNode(ISD::ADD, dl, VTs.VTs[0], {X, Y});
    SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op, getZero(dl, ty(Op), DAG),
                              ISD::SETEQ);
    return DAG.getMergeValues({Op, Ov}, dl);
  }
  if (Opc == ISD::USUBO) {
    SDValue Op = DAG.getNode(ISD::SUB, dl, VTs.VTs[0], {X, Y});
    SDValue Ov = DAG.getSetCC(dl, MVT::i1, Op,
                              DAG.getConstant(-1, dl, ty(Op)), ISD::SETEQ);
    return DAG.getMergeValues({Op, Ov}, dl);
  }
}

return SDValue();
2775}

2777SDValue
2778HexagonTargetLowering::LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const {
const SDLoc &dl(Op);
unsigned Opc = Op.getOpcode();
SDValue X = Op.getOperand(0), Y = Op.getOperand(1), C = Op.getOperand(2);

if (Opc == ISD::ADDCARRY)
  return DAG.getNode(HexagonISD::ADDC, dl, Op.getNode()->getVTList(),
                     { X, Y, C });

EVT CarryTy = C.getValueType();
SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(),
                           { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
SDValue Out[] = { SubC.getValue(0),
                  DAG.getLogicalNOT(dl, SubC.getValue(1), CarryTy) };
return DAG.getMergeValues(Out, dl);
2793}

2795SDValue
2796HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain     = Op.getOperand(0);
SDValue Offset    = Op.getOperand(1);
SDValue Handler   = Op.getOperand(2);
SDLoc dl(Op);
auto PtrVT = getPointerTy(DAG.getDataLayout());

// Mark function as containing a call to EH_RETURN.
HexagonMachineFunctionInfo *FuncInfo =
  DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
FuncInfo->setHasEHReturn();

unsigned OffsetReg = Hexagon::R28;

SDValue StoreAddr =
    DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
                DAG.getIntPtrConstant(4, dl));
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo());
Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);

// Not needed we already use it as explict input to EH_RETURN.
// MF.getRegInfo().addLiveOut(OffsetReg);

return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2820}

2822SDValue
2823HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
unsigned Opc = Op.getOpcode();

// Handle INLINEASM first.
if (Opc == ISD::INLINEASM || Opc == ISD::INLINEASM_BR)
1
Assuming 'Opc' is not equal to INLINEASM→
2
←
Assuming 'Opc' is not equal to INLINEASM_BR→
3
←
Taking false branch→
  return LowerINLINEASM(Op, DAG);

if (isHvxOperation(Op)) {
4
←
Assuming the condition is false→
5
←
Taking false branch→
  // If HVX lowering returns nothing, try the default lowering.
  if (SDValue V = LowerHvxOperation(Op, DAG))
    return V;
}

switch (Opc) {
6
←
Control jumps to 'case EXTRACT_SUBVECTOR:'  at line 2847→
  default:
2838#ifndef NDEBUG
    Op.getNode()->dumpr(&DAG);
    if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
      errs() << "Error: check for a non-legal type in this operation\n";
2842#endif
    llvm_unreachable("Should not custom lower this!")::llvm::llvm_unreachable_internal("Should not custom lower this!"
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 2843);
  case ISD::CONCAT_VECTORS:       return LowerCONCAT_VECTORS(Op, DAG);
  case ISD::INSERT_SUBVECTOR:     return LowerINSERT_SUBVECTOR(Op, DAG);
  case ISD::INSERT_VECTOR_ELT:    return LowerINSERT_VECTOR_ELT(Op, DAG);
  case ISD::EXTRACT_SUBVECTOR:    return LowerEXTRACT_SUBVECTOR(Op, DAG);
7
←
Calling 'HexagonTargetLowering::LowerEXTRACT_SUBVECTOR'→
  case ISD::EXTRACT_VECTOR_ELT:   return LowerEXTRACT_VECTOR_ELT(Op, DAG);
  case ISD::BUILD_VECTOR:         return LowerBUILD_VECTOR(Op, DAG);
  case ISD::VECTOR_SHUFFLE:       return LowerVECTOR_SHUFFLE(Op, DAG);
  case ISD::BITCAST:              return LowerBITCAST(Op, DAG);
  case ISD::LOAD:                 return LowerLoad(Op, DAG);
  case ISD::STORE:                return LowerStore(Op, DAG);
  case ISD::UADDO:
  case ISD::USUBO:                return LowerUAddSubO(Op, DAG);
  case ISD::ADDCARRY:
  case ISD::SUBCARRY:             return LowerAddSubCarry(Op, DAG);
  case ISD::SRA:
  case ISD::SHL:
  case ISD::SRL:                  return LowerVECTOR_SHIFT(Op, DAG);
  case ISD::ROTL:                 return LowerROTL(Op, DAG);
  case ISD::ConstantPool:         return LowerConstantPool(Op, DAG);
  case ISD::JumpTable:            return LowerJumpTable(Op, DAG);
  case ISD::EH_RETURN:            return LowerEH_RETURN(Op, DAG);
  case ISD::RETURNADDR:           return LowerRETURNADDR(Op, DAG);
  case ISD::FRAMEADDR:            return LowerFRAMEADDR(Op, DAG);
  case ISD::GlobalTLSAddress:     return LowerGlobalTLSAddress(Op, DAG);
  case ISD::ATOMIC_FENCE:         return LowerATOMIC_FENCE(Op, DAG);
  case ISD::GlobalAddress:        return LowerGLOBALADDRESS(Op, DAG);
  case ISD::BlockAddress:         return LowerBlockAddress(Op, DAG);
  case ISD::GLOBAL_OFFSET_TABLE:  return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
  case ISD::VASTART:              return LowerVASTART(Op, DAG);
  case ISD::DYNAMIC_STACKALLOC:   return LowerDYNAMIC_STACKALLOC(Op, DAG);
  case ISD::SETCC:                return LowerSETCC(Op, DAG);
  case ISD::VSELECT:              return LowerVSELECT(Op, DAG);
  case ISD::INTRINSIC_WO_CHAIN:   return LowerINTRINSIC_WO_CHAIN(Op, DAG);
  case ISD::INTRINSIC_VOID:       return LowerINTRINSIC_VOID(Op, DAG);
  case ISD::PREFETCH:             return LowerPREFETCH(Op, DAG);
  case ISD::READCYCLECOUNTER:     return LowerREADCYCLECOUNTER(Op, DAG);
    break;
}

return SDValue();
2884}

2886void
2887HexagonTargetLowering::LowerOperationWrapper(SDNode *N,
                                           SmallVectorImpl<SDValue> &Results,
                                           SelectionDAG &DAG) const {
// We are only custom-lowering stores to verify the alignment of the
// address if it is a compile-time constant. Since a store can be modified
// during type-legalization (the value being stored may need legalization),
// return empty Results here to indicate that we don't really make any
// changes in the custom lowering.
if (N->getOpcode() != ISD::STORE)
  return TargetLowering::LowerOperationWrapper(N, Results, DAG);
2897}

2899void
2900HexagonTargetLowering::ReplaceNodeResults(SDNode *N,
                                        SmallVectorImpl<SDValue> &Results,
                                        SelectionDAG &DAG) const {
const SDLoc &dl(N);
switch (N->getOpcode()) {
  case ISD::SRL:
  case ISD::SRA:
  case ISD::SHL:
    return;
  case ISD::BITCAST:
    // Handle a bitcast from v8i1 to i8.
    if (N->getValueType(0) == MVT::i8) {
      SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
                           N->getOperand(0), DAG);
      SDValue T = DAG.getAnyExtOrTrunc(P, dl, MVT::i8);
      Results.push_back(T);
    }
    break;
}
2919}

2921SDValue
2922HexagonTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
    const {
SDValue Op(N, 0);
if (isHvxOperation(Op)) {
  if (SDValue V = PerformHvxDAGCombine(N, DCI))
    return V;
  return SDValue();
}

const SDLoc &dl(Op);
unsigned Opc = Op.getOpcode();

if (Opc == HexagonISD::P2D) {
  SDValue P = Op.getOperand(0);
  switch (P.getOpcode()) {
    case HexagonISD::PTRUE:
      return DCI.DAG.getConstant(-1, dl, ty(Op));
    case HexagonISD::PFALSE:
      return getZero(dl, ty(Op), DCI.DAG);
    default:
      break;
  }
} else if (Opc == ISD::VSELECT) {
  // This is pretty much duplicated in HexagonISelLoweringHVX...
  //
  // (vselect (xor x, ptrue), v0, v1) -> (vselect x, v1, v0)
  SDValue Cond = Op.getOperand(0);
  if (Cond->getOpcode() == ISD::XOR) {
    SDValue C0 = Cond.getOperand(0), C1 = Cond.getOperand(1);
    if (C1->getOpcode() == HexagonISD::PTRUE) {
      SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0,
                                     Op.getOperand(2), Op.getOperand(1));
      return VSel;
    }
  }
}

return SDValue();
2960}

2962/// Returns relocation base for the given PIC jumptable.
2963SDValue
2964HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
                                              SelectionDAG &DAG) const {
int Idx = cast<JumpTableSDNode>(Table)->getIndex();
EVT VT = Table.getValueType();
SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2970}

2972//===----------------------------------------------------------------------===//
2973// Inline Assembly Support
2974//===----------------------------------------------------------------------===//

2976TargetLowering::ConstraintType
2977HexagonTargetLowering::getConstraintType(StringRef Constraint) const {
if (Constraint.size() == 1) {
  switch (Constraint[0]) {
    case 'q':
    case 'v':
      if (Subtarget.useHVXOps())
        return C_RegisterClass;
      break;
    case 'a':
      return C_RegisterClass;
    default:
      break;
  }
}
return TargetLowering::getConstraintType(Constraint);
2992}

2994std::pair<unsigned, const TargetRegisterClass*>
2995HexagonTargetLowering::getRegForInlineAsmConstraint(
  const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {

if (Constraint.size() == 1) {
  switch (Constraint[0]) {
  case 'r':   // R0-R31
    switch (VT.SimpleTy) {
    default:
      return {0u, nullptr};
    case MVT::i1:
    case MVT::i8:
    case MVT::i16:
    case MVT::i32:
    case MVT::f32:
      return {0u, &Hexagon::IntRegsRegClass};
    case MVT::i64:
    case MVT::f64:
      return {0u, &Hexagon::DoubleRegsRegClass};
    }
    break;
  case 'a': // M0-M1
    if (VT != MVT::i32)
      return {0u, nullptr};
    return {0u, &Hexagon::ModRegsRegClass};
  case 'q': // q0-q3
    switch (VT.getSizeInBits()) {
    default:
      return {0u, nullptr};
    case 512:
    case 1024:
      return {0u, &Hexagon::HvxQRRegClass};
    }
    break;
  case 'v': // V0-V31
    switch (VT.getSizeInBits()) {
    default:
      return {0u, nullptr};
    case 512:
      return {0u, &Hexagon::HvxVRRegClass};
    case 1024:
      if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
        return {0u, &Hexagon::HvxVRRegClass};
      return {0u, &Hexagon::HvxWRRegClass};
    case 2048:
      return {0u, &Hexagon::HvxWRRegClass};
    }
    break;
  default:
    return {0u, nullptr};
  }
}

return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3048}

3050/// isFPImmLegal - Returns true if the target can instruction select the
3051/// specified FP immediate natively. If false, the legalizer will
3052/// materialize the FP immediate as a load from a constant pool.
3053bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                       bool ForCodeSize) const {
return true;
3056}

3058/// isLegalAddressingMode - Return true if the addressing mode represented by
3059/// AM is legal for this target, for a load/store of the specified type.
3060bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
                                                const AddrMode &AM, Type *Ty,
                                                unsigned AS, Instruction *I) const {
if (Ty->isSized()) {
  // When LSR detects uses of the same base address to access different
  // types (e.g. unions), it will assume a conservative type for these
  // uses:
  //   LSR Use: Kind=Address of void in addrspace(4294967295), ...
  // The type Ty passed here would then be "void". Skip the alignment
  // checks, but do not return false right away, since that confuses
  // LSR into crashing.
  unsigned A = DL.getABITypeAlignment(Ty);
  // The base offset must be a multiple of the alignment.
  if ((AM.BaseOffs % A) != 0)
    return false;
  // The shifted offset must fit in 11 bits.
  if (!isInt<11>(AM.BaseOffs >> Log2_32(A)))
    return false;
}

// No global is ever allowed as a base.
if (AM.BaseGV)
  return false;

int Scale = AM.Scale;
if (Scale < 0)
  Scale = -Scale;
switch (Scale) {
case 0:  // No scale reg, "r+i", "r", or just "i".
  break;
default: // No scaled addressing mode.
  return false;
}
return true;
3094}

3096/// Return true if folding a constant offset with the given GlobalAddress is
3097/// legal.  It is frequently not legal in PIC relocation models.
3098bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
    const {
return HTM.getRelocationModel() == Reloc::Static;
3101}

3103/// isLegalICmpImmediate - Return true if the specified immediate is legal
3104/// icmp immediate, that is the target has icmp instructions which can compare
3105/// a register against the immediate without having to materialize the
3106/// immediate into a register.
3107bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
return Imm >= -512 && Imm <= 511;
3109}

3111/// IsEligibleForTailCallOptimization - Check whether the call is eligible
3112/// for tail call optimization. Targets which want to do tail call
3113/// optimization should implement this function.
3114bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
                               SDValue Callee,
                               CallingConv::ID CalleeCC,
                               bool IsVarArg,
                               bool IsCalleeStructRet,
                               bool IsCallerStructRet,
                               const SmallVectorImpl<ISD::OutputArg> &Outs,
                               const SmallVectorImpl<SDValue> &OutVals,
                               const SmallVectorImpl<ISD::InputArg> &Ins,
                               SelectionDAG& DAG) const {
const Function &CallerF = DAG.getMachineFunction().getFunction();
CallingConv::ID CallerCC = CallerF.getCallingConv();
bool CCMatch = CallerCC == CalleeCC;

// ***************************************************************************
//  Look for obvious safe cases to perform tail call optimization that do not
//  require ABI changes.
// ***************************************************************************

// If this is a tail call via a function pointer, then don't do it!
if (!isa<GlobalAddressSDNode>(Callee) &&
    !isa<ExternalSymbolSDNode>(Callee)) {
  return false;
}

// Do not optimize if the calling conventions do not match and the conventions
// used are not C or Fast.
if (!CCMatch) {
  bool R = (CallerCC == CallingConv::C || CallerCC == CallingConv::Fast);
  bool E = (CalleeCC == CallingConv::C || CalleeCC == CallingConv::Fast);
  // If R & E, then ok.
  if (!R || !E)
    return false;
}

// Do not tail call optimize vararg calls.
if (IsVarArg)
  return false;

// Also avoid tail call optimization if either caller or callee uses struct
// return semantics.
if (IsCalleeStructRet || IsCallerStructRet)
  return false;

// In addition to the cases above, we also disable Tail Call Optimization if
// the calling convention code that at least one outgoing argument needs to
// go on the stack. We cannot check that here because at this point that
// information is not available.
return true;
3163}

3165/// Returns the target specific optimal type for load and store operations as
3166/// a result of memset, memcpy, and memmove lowering.
3167///
3168/// If DstAlign is zero that means it's safe to destination alignment can
3169/// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
3170/// a need to check it against alignment requirement, probably because the
3171/// source does not need to be loaded. If 'IsMemset' is true, that means it's
3172/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
3173/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
3174/// does not need to be loaded.  It returns EVT::Other if the type should be
3175/// determined using generic target-independent logic.
3176EVT HexagonTargetLowering::getOptimalMemOpType(uint64_t Size,
    unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset,
    bool MemcpyStrSrc, const AttributeList &FuncAttributes) const {

auto Aligned = [](unsigned GivenA, unsigned MinA) -> bool {
  return (GivenA % MinA) == 0;
};

if (Size >= 8 && Aligned(DstAlign, 8) && (IsMemset || Aligned(SrcAlign, 8)))
  return MVT::i64;
if (Size >= 4 && Aligned(DstAlign, 4) && (IsMemset || Aligned(SrcAlign, 4)))
  return MVT::i32;
if (Size >= 2 && Aligned(DstAlign, 2) && (IsMemset || Aligned(SrcAlign, 2)))
  return MVT::i16;

return MVT::Other;
3192}

3194bool HexagonTargetLowering::allowsMisalignedMemoryAccesses(
  EVT VT, unsigned AS, unsigned Align, MachineMemOperand::Flags Flags,
  bool *Fast) const {
if (Fast)
  *Fast = false;
return Subtarget.isHVXVectorType(VT.getSimpleVT());
3200}

3202std::pair<const TargetRegisterClass*, uint8_t>
3203HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
    MVT VT) const {
if (Subtarget.isHVXVectorType(VT, true)) {
  unsigned BitWidth = VT.getSizeInBits();
  unsigned VecWidth = Subtarget.getVectorLength() * 8;

  if (VT.getVectorElementType() == MVT::i1)
    return std::make_pair(&Hexagon::HvxQRRegClass, 1);
  if (BitWidth == VecWidth)
    return std::make_pair(&Hexagon::HvxVRRegClass, 1);
  assert(BitWidth == 2 * VecWidth)((BitWidth == 2 * VecWidth) ? static_cast<void> (0) : __assert_fail
 ("BitWidth == 2 * VecWidth", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3213, __PRETTY_FUNCTION__));
  return std::make_pair(&Hexagon::HvxWRRegClass, 1);
}

return TargetLowering::findRepresentativeClass(TRI, VT);
3218}

3220bool HexagonTargetLowering::shouldReduceLoadWidth(SDNode *Load,
    ISD::LoadExtType ExtTy, EVT NewVT) const {
// TODO: This may be worth removing. Check regression tests for diffs.
if (!TargetLoweringBase::shouldReduceLoadWidth(Load, ExtTy, NewVT))
  return false;

auto *L = cast<LoadSDNode>(Load);
std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr());
// Small-data object, do not shrink.
if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
  return false;
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(BO.first)) {
  auto &HTM = static_cast<const HexagonTargetMachine&>(getTargetMachine());
  const auto *GO = dyn_cast_or_null<const GlobalObject>(GA->getGlobal());
  return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
}
return true;
3237}

3239Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
    AtomicOrdering Ord) const {
BasicBlock *BB = Builder.GetInsertBlock();
Module *M = BB->getParent()->getParent();
auto PT = cast<PointerType>(Addr->getType());
Type *Ty = PT->getElementType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic loads supported\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3246, __PRETTY_FUNCTION__));
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
                                 : Intrinsic::hexagon_L4_loadd_locked;
Function *Fn = Intrinsic::getDeclaration(M, IntID);

PointerType *NewPtrTy
  = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
Addr = Builder.CreateBitCast(Addr, NewPtrTy);

Value *Call = Builder.CreateCall(Fn, Addr, "larx");

return Builder.CreateBitCast(Call, Ty);
3258}

3260/// Perform a store-conditional operation to Addr. Return the status of the
3261/// store. This should be 0 if the store succeeded, non-zero otherwise.
3262Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
    Value *Val, Value *Addr, AtomicOrdering Ord) const {
BasicBlock *BB = Builder.GetInsertBlock();
Module *M = BB->getParent()->getParent();
Type *Ty = Val->getType();
unsigned SZ = Ty->getPrimitiveSizeInBits();

Type *CastTy = Builder.getIntNTy(SZ);
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported")(((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported"
) ? static_cast<void> (0) : __assert_fail ("(SZ == 32 || SZ == 64) && \"Only 32/64-bit atomic stores supported\""
, "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.cpp"
, 3270, __PRETTY_FUNCTION__));
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
                                 : Intrinsic::hexagon_S4_stored_locked;
Function *Fn = Intrinsic::getDeclaration(M, IntID);

unsigned AS = Addr->getType()->getPointerAddressSpace();
Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
Val = Builder.CreateBitCast(Val, CastTy);

Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
return Ext;
3283}

3285TargetLowering::AtomicExpansionKind
3286HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
// Do not expand loads and stores that don't exceed 64 bits.
return LI->getType()->getPrimitiveSizeInBits() > 64
           ? AtomicExpansionKind::LLOnly
           : AtomicExpansionKind::None;
3291}

3293bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
// Do not expand loads and stores that don't exceed 64 bits.
return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
3296}

3298TargetLowering::AtomicExpansionKind
3299HexagonTargetLowering::shouldExpandAtomicCmpXchgInIR(
  AtomicCmpXchgInst *AI) const {
const DataLayout &DL = AI->getModule()->getDataLayout();
unsigned Size = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
if (Size >= 4 && Size <= 8)
  return AtomicExpansionKind::LLSC;
return AtomicExpansionKind::None;
3306}

←

/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.h

→

1//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that Hexagon uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//

14#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H
15#define LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H

17#include "Hexagon.h"
18#include "llvm/ADT/StringRef.h"
19#include "llvm/CodeGen/ISDOpcodes.h"
20#include "llvm/CodeGen/SelectionDAGNodes.h"
21#include "llvm/CodeGen/TargetLowering.h"
22#include "llvm/CodeGen/ValueTypes.h"
23#include "llvm/IR/CallingConv.h"
24#include "llvm/IR/InlineAsm.h"
25#include "llvm/Support/MachineValueType.h"
26#include <cstdint>
27#include <utility>

29namespace llvm {

31namespace HexagonISD {

  enum NodeType : unsigned {
    OP_BEGIN = ISD::BUILTIN_OP_END,

    CONST32 = OP_BEGIN,
    CONST32_GP,  // For marking data present in GP.
    ADDC,        // Add with carry: (X, Y, Cin) -> (X+Y, Cout).
    SUBC,        // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout).
    ALLOCA,

    AT_GOT,      // Index in GOT.
    AT_PCREL,    // Offset relative to PC.

    CALL,        // Function call.
    CALLnr,      // Function call that does not return.
    CALLR,

    RET_FLAG,    // Return with a flag operand.
    BARRIER,     // Memory barrier.
    JT,          // Jump table.
    CP,          // Constant pool.

    COMBINE,
    VSPLAT,      // Generic splat, selection depends on argument/return
                 // types.
    VASL,
    VASR,
    VLSR,

    TSTBIT,
    INSERT,
    EXTRACTU,
    VEXTRACTW,
    VINSERTW0,
    VROR,
    TC_RETURN,
    EH_RETURN,
    DCFETCH,
    READCYCLE,
    PTRUE,
    PFALSE,
    D2P,         // Convert 8-byte value to 8-bit predicate register. [*]
    P2D,         // Convert 8-bit predicate register to 8-byte value. [*]
    V2Q,         // Convert HVX vector to a vector predicate reg. [*]
    Q2V,         // Convert vector predicate to an HVX vector. [*]
                 // [*] The equivalence is defined as "Q <=> (V != 0)",
                 //     where the != operation compares bytes.
                 // Note: V != 0 is implemented as V >u 0.
    QCAT,
    QTRUE,
    QFALSE,
    VZERO,
    VSPLATW,     // HVX splat of a 32-bit word with an arbitrary result type.
    TYPECAST,    // No-op that's used to convert between different legal
                 // types in a register.
    VALIGN,      // Align two vectors (in Op0, Op1) to one that would have
                 // been loaded from address in Op2.
    VALIGNADDR,  // Align vector address: Op0 & -Op1, except when it is
                 // an address in a vector load, then it's a no-op.
    OP_END
  };

94} // end namespace HexagonISD

class HexagonSubtarget;

class HexagonTargetLowering : public TargetLowering {
  int VarArgsFrameOffset;   // Frame offset to start of varargs area.
  const HexagonTargetMachine &HTM;
  const HexagonSubtarget &Subtarget;

  bool CanReturnSmallStruct(const Function* CalleeFn, unsigned& RetSize)
      const;

public:
  explicit HexagonTargetLowering(const TargetMachine &TM,
                                 const HexagonSubtarget &ST);

  bool isHVXVectorType(MVT Ty) const;

  /// IsEligibleForTailCallOptimization - Check whether the call is eligible
  /// for tail call optimization. Targets which want to do tail call
  /// optimization should implement this function.
  bool IsEligibleForTailCallOptimization(SDValue Callee,
      CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet,
      bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
      const SmallVectorImpl<SDValue> &OutVals,
      const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;

  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                          MachineFunction &MF,
                          unsigned Intrinsic) const override;

  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
  bool isTruncateFree(EVT VT1, EVT VT2) const override;

  bool isCheapToSpeculateCttz() const override { return true; }
  bool isCheapToSpeculateCtlz() const override { return true; }
  bool isCtlzFast() const override { return true; }

  bool hasBitTest(SDValue X, SDValue Y) const override;

  bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;

  /// Return true if an FMA operation is faster than a pair of mul and add
  /// instructions. fmuladd intrinsics will be expanded to FMAs when this
  /// method returns true (and FMAs are legal), otherwise fmuladd is
  /// expanded to mul + add.
  bool isFMAFasterThanFMulAndFAdd(EVT) const override;

  // Should we expand the build vector with shuffles?
  bool shouldExpandBuildVectorWithShuffles(EVT VT,
      unsigned DefinedValues) const override;

  bool isShuffleMaskLegal(ArrayRef<int> Mask, EVT VT) const override;
  TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
      const override;

  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
  void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
                             SelectionDAG &DAG) const override;
  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
                          SelectionDAG &DAG) const override;

  const char *getTargetNodeName(unsigned Opcode) const override;

  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerANY_EXTEND(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerZERO_EXTEND(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerAddSubCarry(SDValue Op, SelectionDAG &DAG) const;

  SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
  SDValue
  LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::InputArg> &Ins,
                       const SDLoc &dl, SelectionDAG &DAG,
                       SmallVectorImpl<SDValue> &InVals) const override;
  SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
      SelectionDAG &DAG) const;
  SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA,
      SelectionDAG &DAG) const;
  SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA,
      SelectionDAG &DAG) const;
  SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain,
      GlobalAddressSDNode *GA, SDValue InFlag, EVT PtrVT,
      unsigned ReturnReg, unsigned char OperandFlags) const;
  SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;

  SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
      SmallVectorImpl<SDValue> &InVals) const override;
  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                          CallingConv::ID CallConv, bool isVarArg,
                          const SmallVectorImpl<ISD::InputArg> &Ins,
                          const SDLoc &dl, SelectionDAG &DAG,
                          SmallVectorImpl<SDValue> &InVals,
                          const SmallVectorImpl<SDValue> &OutVals,
                          SDValue Callee) const;

  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
  SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;

  bool CanLowerReturn(CallingConv::ID CallConv,
                      MachineFunction &MF, bool isVarArg,
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
                      LLVMContext &Context) const override;

  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                      const SmallVectorImpl<ISD::OutputArg> &Outs,
                      const SmallVectorImpl<SDValue> &OutVals,
                      const SDLoc &dl, SelectionDAG &DAG) const override;

  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;

  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;

  Register getRegisterByName(const char* RegName, EVT VT,
                             const MachineFunction &MF) const override;

  /// If a physical register, this returns the register that receives the
  /// exception address on entry to an EH pad.
  unsigned
  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
    return Hexagon::R0;
  }

  /// If a physical register, this returns the register that receives the
  /// exception typeid on entry to a landing pad.
  unsigned
  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
    return Hexagon::R1;
  }

  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;

  EVT getSetCCResultType(const DataLayout &, LLVMContext &C,
                         EVT VT) const override {
    if (!VT.isVector())
      return MVT::i1;
    else
      return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
  }

  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
                                  SDValue &Base, SDValue &Offset,
                                  ISD::MemIndexedMode &AM,
                                  SelectionDAG &DAG) const override;

  ConstraintType getConstraintType(StringRef Constraint) const override;

  std::pair<unsigned, const TargetRegisterClass *>
  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                               StringRef Constraint, MVT VT) const override;

  unsigned
  getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
    if (ConstraintCode == "o")
      return InlineAsm::Constraint_o;
    return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
  }

  // Intrinsics
  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
  /// isLegalAddressingMode - Return true if the addressing mode represented
  /// by AM is legal for this target, for a load/store of the specified type.
  /// The type may be VoidTy, in which case only return true if the addressing
  /// mode is legal for a load/store of any legal type.
  /// TODO: Handle pre/postinc as well.
  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
                             Type *Ty, unsigned AS,
                             Instruction *I = nullptr) const override;
  /// Return true if folding a constant offset with the given GlobalAddress
  /// is legal.  It is frequently not legal in PIC relocation models.
  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;

  bool isFPImmLegal(const APFloat &Imm, EVT VT,
                    bool ForCodeSize) const override;

  /// isLegalICmpImmediate - Return true if the specified immediate is legal
  /// icmp immediate, that is the target has icmp instructions which can
  /// compare a register against the immediate without having to materialize
  /// the immediate into a register.
  bool isLegalICmpImmediate(int64_t Imm) const override;

  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
      unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
      const AttributeList &FuncAttributes) const override;

  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
      unsigned Align, MachineMemOperand::Flags Flags, bool *Fast)
      const override;

  /// Returns relocation base for the given PIC jumptable.
  SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG)
                                   const override;

  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
                             EVT NewVT) const override;

  // Handling of atomic RMW instructions.
  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
      AtomicOrdering Ord) const override;
  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
      Value *Addr, AtomicOrdering Ord) const override;
  AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
  AtomicExpansionKind
  shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;

  AtomicExpansionKind
  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override {
    return AtomicExpansionKind::LLSC;
  }

private:
  void initializeHVXLowering();
  void validateConstPtrAlignment(SDValue Ptr, const SDLoc &dl,
                                 unsigned NeedAlign) const;

  std::pair<SDValue,int> getBaseAndOffset(SDValue Addr) const;

  bool getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy,
                               SelectionDAG &DAG,
                               MutableArrayRef<ConstantInt*> Consts) const;
  SDValue buildVector32(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
                        SelectionDAG &DAG) const;
  SDValue buildVector64(ArrayRef<SDValue> Elem, const SDLoc &dl, MVT VecTy,
                        SelectionDAG &DAG) const;
  SDValue extractVector(SDValue VecV, SDValue IdxV, const SDLoc &dl,
                        MVT ValTy, MVT ResTy, SelectionDAG &DAG) const;
  SDValue insertVector(SDValue VecV, SDValue ValV, SDValue IdxV,
                       const SDLoc &dl, MVT ValTy, SelectionDAG &DAG) const;
  SDValue expandPredicate(SDValue Vec32, const SDLoc &dl,
                          SelectionDAG &DAG) const;
  SDValue contractPredicate(SDValue Vec64, const SDLoc &dl,
                            SelectionDAG &DAG) const;
  SDValue getVectorShiftByInt(SDValue Op, SelectionDAG &DAG) const;

  bool isUndef(SDValue Op) const {
    if (Op.isMachineOpcode())
      return Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF;
    return Op.getOpcode() == ISD::UNDEF;
  }
  SDValue getInstr(unsigned MachineOpc, const SDLoc &dl, MVT Ty,
                   ArrayRef<SDValue> Ops, SelectionDAG &DAG) const {
    SDNode *N = DAG.getMachineNode(MachineOpc, dl, Ty, Ops);
    return SDValue(N, 0);
  }
  SDValue getZero(const SDLoc &dl, MVT Ty, SelectionDAG &DAG) const;

  using VectorPair = std::pair<SDValue, SDValue>;
  using TypePair = std::pair<MVT, MVT>;

  SDValue getInt(unsigned IntId, MVT ResTy, ArrayRef<SDValue> Ops,
                 const SDLoc &dl, SelectionDAG &DAG) const;

  MVT ty(SDValue Op) const {
    return Op.getValueType().getSimpleVT();
23
←
Calling 'SDValue::getValueType'→
  }
  TypePair ty(const VectorPair &Ops) const {
    return { Ops.first.getValueType().getSimpleVT(),
             Ops.second.getValueType().getSimpleVT() };
  }
  MVT tyScalar(MVT Ty) const {
    if (!Ty.isVector())
      return Ty;
    return MVT::getIntegerVT(Ty.getSizeInBits());
  }
  MVT tyVector(MVT Ty, MVT ElemTy) const {
    if (Ty.isVector() && Ty.getVectorElementType() == ElemTy)
      return Ty;
    unsigned TyWidth = Ty.getSizeInBits();
    unsigned ElemWidth = ElemTy.getSizeInBits();
    assert((TyWidth % ElemWidth) == 0)(((TyWidth % ElemWidth) == 0) ? static_cast<void> (0) :
 __assert_fail ("(TyWidth % ElemWidth) == 0", "/build/llvm-toolchain-snapshot-10~svn374814/lib/Target/Hexagon/HexagonISelLowering.h"
, 392, __PRETTY_FUNCTION__));
    return MVT::getVectorVT(ElemTy, TyWidth/ElemWidth);
  }

  MVT typeJoin(const TypePair &Tys) const;
  TypePair typeSplit(MVT Ty) const;
  MVT typeExtElem(MVT VecTy, unsigned Factor) const;
  MVT typeTruncElem(MVT VecTy, unsigned Factor) const;

  SDValue opJoin(const VectorPair &Ops, const SDLoc &dl,
                 SelectionDAG &DAG) const;
  VectorPair opSplit(SDValue Vec, const SDLoc &dl, SelectionDAG &DAG) const;
  SDValue opCastElem(SDValue Vec, MVT ElemTy, SelectionDAG &DAG) const;

  bool isHvxSingleTy(MVT Ty) const;
  bool isHvxPairTy(MVT Ty) const;
  SDValue convertToByteIndex(SDValue ElemIdx, MVT ElemTy,
                             SelectionDAG &DAG) const;
  SDValue getIndexInWord32(SDValue Idx, MVT ElemTy, SelectionDAG &DAG) const;
  SDValue getByteShuffle(const SDLoc &dl, SDValue Op0, SDValue Op1,
                         ArrayRef<int> Mask, SelectionDAG &DAG) const;

  SDValue buildHvxVectorReg(ArrayRef<SDValue> Values, const SDLoc &dl,
                            MVT VecTy, SelectionDAG &DAG) const;
  SDValue buildHvxVectorPred(ArrayRef<SDValue> Values, const SDLoc &dl,
                             MVT VecTy, SelectionDAG &DAG) const;
  SDValue createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
                              unsigned BitBytes, bool ZeroFill,
                              SelectionDAG &DAG) const;
  SDValue extractHvxElementReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
                               MVT ResTy, SelectionDAG &DAG) const;
  SDValue extractHvxElementPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
                                MVT ResTy, SelectionDAG &DAG) const;
  SDValue insertHvxElementReg(SDValue VecV, SDValue IdxV, SDValue ValV,
                              const SDLoc &dl, SelectionDAG &DAG) const;
  SDValue insertHvxElementPred(SDValue VecV, SDValue IdxV, SDValue ValV,
                               const SDLoc &dl, SelectionDAG &DAG) const;
  SDValue extractHvxSubvectorReg(SDValue VecV, SDValue IdxV, const SDLoc &dl,
                                 MVT ResTy, SelectionDAG &DAG) const;
  SDValue extractHvxSubvectorPred(SDValue VecV, SDValue IdxV, const SDLoc &dl,
                                  MVT ResTy, SelectionDAG &DAG) const;
  SDValue insertHvxSubvectorReg(SDValue VecV, SDValue SubV, SDValue IdxV,
                                const SDLoc &dl, SelectionDAG &DAG) const;
  SDValue insertHvxSubvectorPred(SDValue VecV, SDValue SubV, SDValue IdxV,
                                 const SDLoc &dl, SelectionDAG &DAG) const;
  SDValue extendHvxVectorPred(SDValue VecV, const SDLoc &dl, MVT ResTy,
                              bool ZeroExt, SelectionDAG &DAG) const;

  SDValue LowerHvxBuildVector(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxConcatVectors(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxExtractElement(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxInsertElement(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxExtractSubvector(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxInsertSubvector(SDValue Op, SelectionDAG &DAG) const;

  SDValue LowerHvxAnyExt(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxSignExt(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxZeroExt(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxCttz(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxMul(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxMulh(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxSetCC(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxExtend(SDValue Op, SelectionDAG &DAG) const;
  SDValue LowerHvxShift(SDValue Op, SelectionDAG &DAG) const;

  SDValue SplitHvxPairOp(SDValue Op, SelectionDAG &DAG) const;
  SDValue SplitHvxMemOp(SDValue Op, SelectionDAG &DAG) const;

  std::pair<const TargetRegisterClass*, uint8_t>
  findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
      const override;

  bool isHvxOperation(SDValue Op) const;
  SDValue LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const;

  SDValue PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
};

470} // end namespace llvm

472#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H

←

/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h

1//===- llvm/CodeGen/SelectionDAGNodes.h - SelectionDAG Nodes ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the SDNode class and derived classes, which are used to
10// represent the nodes and operations present in a SelectionDAG.  These nodes
11// and operations are machine code level operations, with some similarities to
12// the GCC RTL representation.
13//
14// Clients should include the SelectionDAG.h file instead of this file directly.
15//
16//===----------------------------------------------------------------------===//

18#ifndef LLVM_CODEGEN_SELECTIONDAGNODES_H
19#define LLVM_CODEGEN_SELECTIONDAGNODES_H

21#include "llvm/ADT/APFloat.h"
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/ADT/BitVector.h"
24#include "llvm/ADT/FoldingSet.h"
25#include "llvm/ADT/GraphTraits.h"
26#include "llvm/ADT/SmallPtrSet.h"
27#include "llvm/ADT/SmallVector.h"
28#include "llvm/ADT/ilist_node.h"
29#include "llvm/ADT/iterator.h"
30#include "llvm/ADT/iterator_range.h"
31#include "llvm/CodeGen/ISDOpcodes.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/ValueTypes.h"
34#include "llvm/IR/Constants.h"
35#include "llvm/IR/DebugLoc.h"
36#include "llvm/IR/Instruction.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/Metadata.h"
39#include "llvm/IR/Operator.h"
40#include "llvm/Support/AlignOf.h"
41#include "llvm/Support/AtomicOrdering.h"
42#include "llvm/Support/Casting.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/MachineValueType.h"
45#include <algorithm>
46#include <cassert>
47#include <climits>
48#include <cstddef>
49#include <cstdint>
50#include <cstring>
51#include <iterator>
52#include <string>
53#include <tuple>

55namespace llvm {

57class APInt;
58class Constant;
59template <typename T> struct DenseMapInfo;
60class GlobalValue;
61class MachineBasicBlock;
62class MachineConstantPoolValue;
63class MCSymbol;
64class raw_ostream;
65class SDNode;
66class SelectionDAG;
67class Type;
68class Value;

70void checkForCycles(const SDNode *N, const SelectionDAG *DAG = nullptr,
                  bool force = false);

73/// This represents a list of ValueType's that has been intern'd by
74/// a SelectionDAG.  Instances of this simple value class are returned by
75/// SelectionDAG::getVTList(...).
76///
77struct SDVTList {
const EVT *VTs;
unsigned int NumVTs;
80};

82namespace ISD {

/// Node predicates

/// If N is a BUILD_VECTOR node whose elements are all the same constant or
/// undefined, return true and return the constant value in \p SplatValue.
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue);

/// Return true if the specified node is a BUILD_VECTOR where all of the
/// elements are ~0 or undef.
bool isBuildVectorAllOnes(const SDNode *N);

/// Return true if the specified node is a BUILD_VECTOR where all of the
/// elements are 0 or undef.
bool isBuildVectorAllZeros(const SDNode *N);

/// Return true if the specified node is a BUILD_VECTOR node of all
/// ConstantSDNode or undef.
bool isBuildVectorOfConstantSDNodes(const SDNode *N);

/// Return true if the specified node is a BUILD_VECTOR node of all
/// ConstantFPSDNode or undef.
bool isBuildVectorOfConstantFPSDNodes(const SDNode *N);

/// Return true if the node has at least one operand and all operands of the
/// specified node are ISD::UNDEF.
bool allOperandsUndef(const SDNode *N);

110} // end namespace ISD

112//===----------------------------------------------------------------------===//
113/// Unlike LLVM values, Selection DAG nodes may return multiple
114/// values as the result of a computation.  Many nodes return multiple values,
115/// from loads (which define a token and a return value) to ADDC (which returns
116/// a result and a carry value), to calls (which may return an arbitrary number
117/// of values).
118///
119/// As such, each use of a SelectionDAG computation must indicate the node that
120/// computes it as well as which return value to use from that node.  This pair
121/// of information is represented with the SDValue value type.
122///
123class SDValue {
friend struct DenseMapInfo<SDValue>;

SDNode *Node = nullptr; // The node defining the value we are using.
unsigned ResNo = 0;     // Which return value of the node we are using.

129public:
SDValue() = default;
SDValue(SDNode *node, unsigned resno);

/// get the index which selects a specific result in the SDNode
unsigned getResNo() const { return ResNo; }

/// get the SDNode which holds the desired result
SDNode *getNode() const { return Node; }

/// set the SDNode
void setNode(SDNode *N) { Node = N; }

inline SDNode *operator->() const { return Node; }

bool operator==(const SDValue &O) const {
  return Node == O.Node && ResNo == O.ResNo;
}
bool operator!=(const SDValue &O) const {
  return !operator==(O);
}
bool operator<(const SDValue &O) const {
  return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
}
explicit operator bool() const {
  return Node != nullptr;
}

SDValue getValue(unsigned R) const {
  return SDValue(Node, R);
}

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return the ValueType of the referenced return value.
inline EVT getValueType() const;

/// Return the simple ValueType of the referenced return value.
MVT getSimpleValueType() const {
  return getValueType().getSimpleVT();
}

/// Returns the size of the value in bits.
unsigned getValueSizeInBits() const {
  return getValueType().getSizeInBits();
}

unsigned getScalarValueSizeInBits() const {
  return getValueType().getScalarType().getSizeInBits();
}

// Forwarding methods - These forward to the corresponding methods in SDNode.
inline unsigned getOpcode() const;
inline unsigned getNumOperands() const;
inline const SDValue &getOperand(unsigned i) const;
inline uint64_t getConstantOperandVal(unsigned i) const;
inline const APInt &getConstantOperandAPInt(unsigned i) const;
inline bool isTargetMemoryOpcode() const;
inline bool isTargetOpcode() const;
inline bool isMachineOpcode() const;
inline bool isUndef() const;
inline unsigned getMachineOpcode() const;
inline const DebugLoc &getDebugLoc() const;
inline void dump() const;
inline void dump(const SelectionDAG *G) const;
inline void dumpr() const;
inline void dumpr(const SelectionDAG *G) const;

/// Return true if this operand (which must be a chain) reaches the
/// specified operand without crossing any side-effecting instructions.
/// In practice, this looks through token factors and non-volatile loads.
/// In order to remain efficient, this only
/// looks a couple of nodes in, it does not do an exhaustive search.
bool reachesChainWithoutSideEffects(SDValue Dest,
                                    unsigned Depth = 2) const;

/// Return true if there are no nodes using value ResNo of Node.
inline bool use_empty() const;

/// Return true if there is exactly one node using value ResNo of Node.
inline bool hasOneUse() const;
211};

213template<> struct DenseMapInfo<SDValue> {
static inline SDValue getEmptyKey() {
  SDValue V;
  V.ResNo = -1U;
  return V;
}

static inline SDValue getTombstoneKey() {
  SDValue V;
  V.ResNo = -2U;
  return V;
}

static unsigned getHashValue(const SDValue &Val) {
  return ((unsigned)((uintptr_t)Val.getNode() >> 4) ^
          (unsigned)((uintptr_t)Val.getNode() >> 9)) + Val.getResNo();
}

static bool isEqual(const SDValue &LHS, const SDValue &RHS) {
  return LHS == RHS;
}
234};

236/// Allow casting operators to work directly on
237/// SDValues as if they were SDNode*'s.
238template<> struct simplify_type<SDValue> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDValue &Val) {
  return Val.getNode();
}
244};
245template<> struct simplify_type<const SDValue> {
using SimpleType = /*const*/ SDNode *;

static SimpleType getSimplifiedValue(const SDValue &Val) {
  return Val.getNode();
}
251};

253/// Represents a use of a SDNode. This class holds an SDValue,
254/// which records the SDNode being used and the result number, a
255/// pointer to the SDNode using the value, and Next and Prev pointers,
256/// which link together all the uses of an SDNode.
257///
258class SDUse {
/// Val - The value being used.
SDValue Val;
/// User - The user of this value.
SDNode *User = nullptr;
/// Prev, Next - Pointers to the uses list of the SDNode referred by
/// this operand.
SDUse **Prev = nullptr;
SDUse *Next = nullptr;

268public:
SDUse() = default;
SDUse(const SDUse &U) = delete;
SDUse &operator=(const SDUse &) = delete;

/// Normally SDUse will just implicitly convert to an SDValue that it holds.
operator const SDValue&() const { return Val; }

/// If implicit conversion to SDValue doesn't work, the get() method returns
/// the SDValue.
const SDValue &get() const { return Val; }

/// This returns the SDNode that contains this Use.
SDNode *getUser() { return User; }

/// Get the next SDUse in the use list.
SDUse *getNext() const { return Next; }

/// Convenience function for get().getNode().
SDNode *getNode() const { return Val.getNode(); }
/// Convenience function for get().getResNo().
unsigned getResNo() const { return Val.getResNo(); }
/// Convenience function for get().getValueType().
EVT getValueType() const { return Val.getValueType(); }

/// Convenience function for get().operator==
bool operator==(const SDValue &V) const {
  return Val == V;
}

/// Convenience function for get().operator!=
bool operator!=(const SDValue &V) const {
  return Val != V;
}

/// Convenience function for get().operator<
bool operator<(const SDValue &V) const {
  return Val < V;
}

308private:
friend class SelectionDAG;
friend class SDNode;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

void setUser(SDNode *p) { User = p; }

/// Remove this use from its existing use list, assign it the
/// given value, and add it to the new value's node's use list.
inline void set(const SDValue &V);
/// Like set, but only supports initializing a newly-allocated
/// SDUse with a non-null value.
inline void setInitial(const SDValue &V);
/// Like set, but only sets the Node portion of the value,
/// leaving the ResNo portion unmodified.
inline void setNode(SDNode *N);

void addToList(SDUse **List) {
  Next = *List;
  if (Next) Next->Prev = &Next;
  Prev = List;
  *List = this;
}

void removeFromList() {
  *Prev = Next;
  if (Next) Next->Prev = Prev;
}
337};

339/// simplify_type specializations - Allow casting operators to work directly on
340/// SDValues as if they were SDNode*'s.
341template<> struct simplify_type<SDUse> {
using SimpleType = SDNode *;

static SimpleType getSimplifiedValue(SDUse &Val) {
  return Val.getNode();
}
347};

349/// These are IR-level optimization flags that may be propagated to SDNodes.
350/// TODO: This data structure should be shared by the IR optimizer and the
351/// the backend.
352struct SDNodeFlags {
353private:
// This bit is used to determine if the flags are in a defined state.
// Flag bits can only be masked out during intersection if the masking flags
// are defined.
bool AnyDefined : 1;

bool NoUnsignedWrap : 1;
bool NoSignedWrap : 1;
bool Exact : 1;
bool NoNaNs : 1;
bool NoInfs : 1;
bool NoSignedZeros : 1;
bool AllowReciprocal : 1;
bool VectorReduction : 1;
bool AllowContract : 1;
bool ApproximateFuncs : 1;
bool AllowReassociation : 1;

// We assume instructions do not raise floating-point exceptions by default,
// and only those marked explicitly may do so.  We could choose to represent
// this via a positive "FPExcept" flags like on the MI level, but having a
// negative "NoFPExcept" flag here (that defaults to true) makes the flag
// intersection logic more straightforward.
bool NoFPExcept : 1;

378public:
/// Default constructor turns off all optimization flags.
SDNodeFlags()
    : AnyDefined(false), NoUnsignedWrap(false), NoSignedWrap(false),
      Exact(false), NoNaNs(false), NoInfs(false),
      NoSignedZeros(false), AllowReciprocal(false), VectorReduction(false),
      AllowContract(false), ApproximateFuncs(false),
      AllowReassociation(false), NoFPExcept(true) {}

/// Propagate the fast-math-flags from an IR FPMathOperator.
void copyFMF(const FPMathOperator &FPMO) {
  setNoNaNs(FPMO.hasNoNaNs());
  setNoInfs(FPMO.hasNoInfs());
  setNoSignedZeros(FPMO.hasNoSignedZeros());
  setAllowReciprocal(FPMO.hasAllowReciprocal());
  setAllowContract(FPMO.hasAllowContract());
  setApproximateFuncs(FPMO.hasApproxFunc());
  setAllowReassociation(FPMO.hasAllowReassoc());
}

/// Sets the state of the flags to the defined state.
void setDefined() { AnyDefined = true; }
/// Returns true if the flags are in a defined state.
bool isDefined() const { return AnyDefined; }

// These are mutators for each flag.
void setNoUnsignedWrap(bool b) {
  setDefined();
  NoUnsignedWrap = b;
}
void setNoSignedWrap(bool b) {
  setDefined();
  NoSignedWrap = b;
}
void setExact(bool b) {
  setDefined();
  Exact = b;
}
void setNoNaNs(bool b) {
  setDefined();
  NoNaNs = b;
}
void setNoInfs(bool b) {
  setDefined();
  NoInfs = b;
}
void setNoSignedZeros(bool b) {
  setDefined();
  NoSignedZeros = b;
}
void setAllowReciprocal(bool b) {
  setDefined();
  AllowReciprocal = b;
}
void setVectorReduction(bool b) {
  setDefined();
  VectorReduction = b;
}
void setAllowContract(bool b) {
  setDefined();
  AllowContract = b;
}
void setApproximateFuncs(bool b) {
  setDefined();
  ApproximateFuncs = b;
}
void setAllowReassociation(bool b) {
  setDefined();
  AllowReassociation = b;
}
void setFPExcept(bool b) {
  setDefined();
  NoFPExcept = !b;
}

// These are accessors for each flag.
bool hasNoUnsignedWrap() const { return NoUnsignedWrap; }
bool hasNoSignedWrap() const { return NoSignedWrap; }
bool hasExact() const { return Exact; }
bool hasNoNaNs() const { return NoNaNs; }
bool hasNoInfs() const { return NoInfs; }
bool hasNoSignedZeros() const { return NoSignedZeros; }
bool hasAllowReciprocal() const { return AllowReciprocal; }
bool hasVectorReduction() const { return VectorReduction; }
bool hasAllowContract() const { return AllowContract; }
bool hasApproximateFuncs() const { return ApproximateFuncs; }
bool hasAllowReassociation() const { return AllowReassociation; }
bool hasFPExcept() const { return !NoFPExcept; }

bool isFast() const {
  return NoSignedZeros && AllowReciprocal && NoNaNs && NoInfs && NoFPExcept &&
         AllowContract && ApproximateFuncs && AllowReassociation;
}

/// Clear any flags in this flag set that aren't also set in Flags.
/// If the given Flags are undefined then don't do anything.
void intersectWith(const SDNodeFlags Flags) {
  if (!Flags.isDefined())
    return;
  NoUnsignedWrap &= Flags.NoUnsignedWrap;
  NoSignedWrap &= Flags.NoSignedWrap;
  Exact &= Flags.Exact;
  NoNaNs &= Flags.NoNaNs;
  NoInfs &= Flags.NoInfs;
  NoSignedZeros &= Flags.NoSignedZeros;
  AllowReciprocal &= Flags.AllowReciprocal;
  VectorReduction &= Flags.VectorReduction;
  AllowContract &= Flags.AllowContract;
  ApproximateFuncs &= Flags.ApproximateFuncs;
  AllowReassociation &= Flags.AllowReassociation;
  NoFPExcept &= Flags.NoFPExcept;
}
490};

492/// Represents one node in the SelectionDAG.
493///
494class SDNode : public FoldingSetNode, public ilist_node<SDNode> {
495private:
/// The operation that this node performs.
int16_t NodeType;

499protected:
// We define a set of mini-helper classes to help us interpret the bits in our
// SubclassData.  These are designed to fit within a uint16_t so they pack
// with NodeType.

504#if defined(_AIX) && (!defined(__GNUC__4) || defined(__ibmxl__))
505// Except for GCC; by default, AIX compilers store bit-fields in 4-byte words
506// and give the `pack` pragma push semantics.
507#define BEGIN_TWO_BYTE_PACK() _Pragma("pack(2)")pack(2)
508#define END_TWO_BYTE_PACK() _Pragma("pack(pop)")pack(pop)
509#else
510#define BEGIN_TWO_BYTE_PACK()
511#define END_TWO_BYTE_PACK()
512#endif

514BEGIN_TWO_BYTE_PACK()
class SDNodeBitfields {
  friend class SDNode;
  friend class MemIntrinsicSDNode;
  friend class MemSDNode;
  friend class SelectionDAG;

  uint16_t HasDebugValue : 1;
  uint16_t IsMemIntrinsic : 1;
  uint16_t IsDivergent : 1;
};
enum { NumSDNodeBits = 3 };

class ConstantSDNodeBitfields {
  friend class ConstantSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsOpaque : 1;
};

class MemSDNodeBitfields {
  friend class MemSDNode;
  friend class MemIntrinsicSDNode;
  friend class AtomicSDNode;

  uint16_t : NumSDNodeBits;

  uint16_t IsVolatile : 1;
  uint16_t IsNonTemporal : 1;
  uint16_t IsDereferenceable : 1;
  uint16_t IsInvariant : 1;
};
enum { NumMemSDNodeBits = NumSDNodeBits + 4 };

class LSBaseSDNodeBitfields {
  friend class LSBaseSDNode;
  friend class MaskedGatherScatterSDNode;

  uint16_t : NumMemSDNodeBits;

  // This storage is shared between disparate class hierarchies to hold an
  // enumeration specific to the class hierarchy in use.
  //   LSBaseSDNode => enum ISD::MemIndexedMode
  //   MaskedGatherScatterSDNode => enum ISD::MemIndexType
  uint16_t AddressingMode : 3;
};
enum { NumLSBaseSDNodeBits = NumMemSDNodeBits + 3 };

class LoadSDNodeBitfields {
  friend class LoadSDNode;
  friend class MaskedLoadSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t ExtTy : 2; // enum ISD::LoadExtType
  uint16_t IsExpanding : 1;
};

class StoreSDNodeBitfields {
  friend class StoreSDNode;
  friend class MaskedStoreSDNode;

  uint16_t : NumLSBaseSDNodeBits;

  uint16_t IsTruncating : 1;
  uint16_t IsCompressing : 1;
};

union {
  char RawSDNodeBits[sizeof(uint16_t)];
  SDNodeBitfields SDNodeBits;
  ConstantSDNodeBitfields ConstantSDNodeBits;
  MemSDNodeBitfields MemSDNodeBits;
  LSBaseSDNodeBitfields LSBaseSDNodeBits;
  LoadSDNodeBitfields LoadSDNodeBits;
  StoreSDNodeBitfields StoreSDNodeBits;
};
592END_TWO_BYTE_PACK()
593#undef BEGIN_TWO_BYTE_PACK
594#undef END_TWO_BYTE_PACK

// RawSDNodeBits must cover the entirety of the union.  This means that all of
// the union's members must have size <= RawSDNodeBits.  We write the RHS as
// "2" instead of sizeof(RawSDNodeBits) because MSVC can't handle the latter.
static_assert(sizeof(SDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(ConstantSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(MemSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LSBaseSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(LoadSDNodeBitfields) <= 2, "field too wide");
static_assert(sizeof(StoreSDNodeBitfields) <= 2, "field too wide");

606private:
friend class SelectionDAG;
// TODO: unfriend HandleSDNode once we fix its operand handling.
friend class HandleSDNode;

/// Unique id per SDNode in the DAG.
int NodeId = -1;

/// The values that are used by this operation.
SDUse *OperandList = nullptr;

/// The types of the values this node defines.  SDNode's may
/// define multiple values simultaneously.
const EVT *ValueList;

/// List of uses for this SDNode.
SDUse *UseList = nullptr;

/// The number of entries in the Operand/Value list.
unsigned short NumOperands = 0;
unsigned short NumValues;

// The ordering of the SDNodes. It roughly corresponds to the ordering of the
// original LLVM instructions.
// This is used for turning off scheduling, because we'll forgo
// the normal scheduling algorithms and output the instructions according to
// this ordering.
unsigned IROrder;

/// Source line information.
DebugLoc debugLoc;

/// Return a pointer to the specified value type.
static const EVT *getValueTypeList(EVT VT);

SDNodeFlags Flags;

643public:
/// Unique and persistent id per SDNode in the DAG.
/// Used for debug printing.
uint16_t PersistentId;

//===--------------------------------------------------------------------===//
//  Accessors
//

/// Return the SelectionDAG opcode value for this node. For
/// pre-isel nodes (those for which isMachineOpcode returns false), these
/// are the opcode values in the ISD and <target>ISD namespaces. For
/// post-isel opcodes, see getMachineOpcode.
unsigned getOpcode()  const { return (unsigned short)NodeType; }

/// Test if this node has a target-specific opcode (in the
/// \<target\>ISD namespace).
bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }

/// Test if this node has a target-specific
/// memory-referencing opcode (in the \<target\>ISD namespace and
/// greater than FIRST_TARGET_MEMORY_OPCODE).
bool isTargetMemoryOpcode() const {
  return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
}

/// Return true if the type of the node type undefined.
bool isUndef() const { return NodeType == ISD::UNDEF; }

/// Test if this node is a memory intrinsic (with valid pointer information).
/// INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are sometimes created for
/// non-memory intrinsics (with chains) that are not really instances of
/// MemSDNode. For such nodes, we need some extra state to determine the
/// proper classof relationship.
bool isMemIntrinsic() const {
  return (NodeType == ISD::INTRINSIC_W_CHAIN ||
          NodeType == ISD::INTRINSIC_VOID) &&
         SDNodeBits.IsMemIntrinsic;
}

/// Test if this node is a strict floating point pseudo-op.
bool isStrictFPOpcode() {
  switch (NodeType) {
    default:
      return false;
    case ISD::STRICT_FADD:
    case ISD::STRICT_FSUB:
    case ISD::STRICT_FMUL:
    case ISD::STRICT_FDIV:
    case ISD::STRICT_FREM:
    case ISD::STRICT_FMA:
    case ISD::STRICT_FSQRT:
    case ISD::STRICT_FPOW:
    case ISD::STRICT_FPOWI:
    case ISD::STRICT_FSIN:
    case ISD::STRICT_FCOS:
    case ISD::STRICT_FEXP:
    case ISD::STRICT_FEXP2:
    case ISD::STRICT_FLOG:
    case ISD::STRICT_FLOG10:
    case ISD::STRICT_FLOG2:
    case ISD::STRICT_LRINT:
    case ISD::STRICT_LLRINT:
    case ISD::STRICT_FRINT:
    case ISD::STRICT_FNEARBYINT:
    case ISD::STRICT_FMAXNUM:
    case ISD::STRICT_FMINNUM:
    case ISD::STRICT_FCEIL:
    case ISD::STRICT_FFLOOR:
    case ISD::STRICT_LROUND:
    case ISD::STRICT_LLROUND:
    case ISD::STRICT_FROUND:
    case ISD::STRICT_FTRUNC:
    case ISD::STRICT_FP_TO_SINT:
    case ISD::STRICT_FP_TO_UINT:
    case ISD::STRICT_FP_ROUND:
    case ISD::STRICT_FP_EXTEND:
      return true;
  }
}

/// Test if this node has a post-isel opcode, directly
/// corresponding to a MachineInstr opcode.
bool isMachineOpcode() const { return NodeType < 0; }

/// This may only be called if isMachineOpcode returns
/// true. It returns the MachineInstr opcode value that the node's opcode
/// corresponds to.
unsigned getMachineOpcode() const {
  assert(isMachineOpcode() && "Not a MachineInstr opcode!")((isMachineOpcode() && "Not a MachineInstr opcode!") ?
 static_cast<void> (0) : __assert_fail ("isMachineOpcode() && \"Not a MachineInstr opcode!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 732, __PRETTY_FUNCTION__));
  return ~NodeType;
}

bool getHasDebugValue() const { return SDNodeBits.HasDebugValue; }
void setHasDebugValue(bool b) { SDNodeBits.HasDebugValue = b; }

bool isDivergent() const { return SDNodeBits.IsDivergent; }

/// Return true if there are no uses of this node.
bool use_empty() const { return UseList == nullptr; }

/// Return true if there is exactly one use of this node.
bool hasOneUse() const {
  return !use_empty() && std::next(use_begin()) == use_end();
}

/// Return the number of uses of this node. This method takes
/// time proportional to the number of uses.
size_t use_size() const { return std::distance(use_begin(), use_end()); }

/// Return the unique node id.
int getNodeId() const { return NodeId; }

/// Set unique node id.
void setNodeId(int Id) { NodeId = Id; }

/// Return the node ordering.
unsigned getIROrder() const { return IROrder; }

/// Set the node ordering.
void setIROrder(unsigned Order) { IROrder = Order; }

/// Return the source location info.
const DebugLoc &getDebugLoc() const { return debugLoc; }

/// Set source location info.  Try to avoid this, putting
/// it in the constructor is preferable.
void setDebugLoc(DebugLoc dl) { debugLoc = std::move(dl); }

/// This class provides iterator support for SDUse
/// operands that use a specific SDNode.
class use_iterator
  : public std::iterator<std::forward_iterator_tag, SDUse, ptrdiff_t> {
  friend class SDNode;

  SDUse *Op = nullptr;

  explicit use_iterator(SDUse *op) : Op(op) {}

public:
  using reference = std::iterator<std::forward_iterator_tag,
                                  SDUse, ptrdiff_t>::reference;
  using pointer = std::iterator<std::forward_iterator_tag,
                                SDUse, ptrdiff_t>::pointer;

  use_iterator() = default;
  use_iterator(const use_iterator &I) : Op(I.Op) {}

  bool operator==(const use_iterator &x) const {
    return Op == x.Op;
  }
  bool operator!=(const use_iterator &x) const {
    return !operator==(x);
  }

  /// Return true if this iterator is at the end of uses list.
  bool atEnd() const { return Op == nullptr; }

  // Iterator traversal: forward iteration only.
  use_iterator &operator++() {          // Preincrement
    assert(Op && "Cannot increment end iterator!")((Op && "Cannot increment end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot increment end iterator!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 803, __PRETTY_FUNCTION__));
    Op = Op->getNext();
    return *this;
  }

  use_iterator operator++(int) {        // Postincrement
    use_iterator tmp = *this; ++*this; return tmp;
  }

  /// Retrieve a pointer to the current user node.
  SDNode *operator*() const {
    assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 814, __PRETTY_FUNCTION__));
    return Op->getUser();
  }

  SDNode *operator->() const { return operator*(); }

  SDUse &getUse() const { return *Op; }

  /// Retrieve the operand # of this use in its user.
  unsigned getOperandNo() const {
    assert(Op && "Cannot dereference end iterator!")((Op && "Cannot dereference end iterator!") ? static_cast
<void> (0) : __assert_fail ("Op && \"Cannot dereference end iterator!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 824, __PRETTY_FUNCTION__));
    return (unsigned)(Op - Op->getUser()->OperandList);
  }
};

/// Provide iteration support to walk over all uses of an SDNode.
use_iterator use_begin() const {
  return use_iterator(UseList);
}

static use_iterator use_end() { return use_iterator(nullptr); }

inline iterator_range<use_iterator> uses() {
  return make_range(use_begin(), use_end());
}
inline iterator_range<use_iterator> uses() const {
  return make_range(use_begin(), use_end());
}

/// Return true if there are exactly NUSES uses of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const;

/// Return true if there are any use of the indicated value.
/// This method ignores uses of other values defined by this operation.
bool hasAnyUseOfValue(unsigned Value) const;

/// Return true if this node is the only use of N.
bool isOnlyUserOf(const SDNode *N) const;

/// Return true if this node is an operand of N.
bool isOperandOf(const SDNode *N) const;

/// Return true if this node is a predecessor of N.
/// NOTE: Implemented on top of hasPredecessor and every bit as
/// expensive. Use carefully.
bool isPredecessorOf(const SDNode *N) const {
  return N->hasPredecessor(this);
}

/// Return true if N is a predecessor of this node.
/// N is either an operand of this node, or can be reached by recursively
/// traversing up the operands.
/// NOTE: This is an expensive method. Use it carefully.
bool hasPredecessor(const SDNode *N) const;

/// Returns true if N is a predecessor of any node in Worklist. This
/// helper keeps Visited and Worklist sets externally to allow unions
/// searches to be performed in parallel, caching of results across
/// queries and incremental addition to Worklist. Stops early if N is
/// found but will resume. Remember to clear Visited and Worklists
/// if DAG changes. MaxSteps gives a maximum number of nodes to visit before
/// giving up. The TopologicalPrune flag signals that positive NodeIds are
/// topologically ordered (Operands have strictly smaller node id) and search
/// can be pruned leveraging this.
static bool hasPredecessorHelper(const SDNode *N,
                                 SmallPtrSetImpl<const SDNode *> &Visited,
                                 SmallVectorImpl<const SDNode *> &Worklist,
                                 unsigned int MaxSteps = 0,
                                 bool TopologicalPrune = false) {
  SmallVector<const SDNode *, 8> DeferredNodes;
  if (Visited.count(N))
    return true;

  // Node Id's are assigned in three places: As a topological
  // ordering (> 0), during legalization (results in values set to
  // 0), new nodes (set to -1). If N has a topolgical id then we
  // know that all nodes with ids smaller than it cannot be
  // successors and we need not check them. Filter out all node
  // that can't be matches. We add them to the worklist before exit
  // in case of multiple calls. Note that during selection the topological id
  // may be violated if a node's predecessor is selected before it. We mark
  // this at selection negating the id of unselected successors and
  // restricting topological pruning to positive ids.

  int NId = N->getNodeId();
  // If we Invalidated the Id, reconstruct original NId.
  if (NId < -1)
    NId = -(NId + 1);

  bool Found = false;
  while (!Worklist.empty()) {
    const SDNode *M = Worklist.pop_back_val();
    int MId = M->getNodeId();
    if (TopologicalPrune && M->getOpcode() != ISD::TokenFactor && (NId > 0) &&
        (MId > 0) && (MId < NId)) {
      DeferredNodes.push_back(M);
      continue;
    }
    for (const SDValue &OpV : M->op_values()) {
      SDNode *Op = OpV.getNode();
      if (Visited.insert(Op).second)
        Worklist.push_back(Op);
      if (Op == N)
        Found = true;
    }
    if (Found)
      break;
    if (MaxSteps != 0 && Visited.size() >= MaxSteps)
      break;
  }
  // Push deferred nodes back on worklist.
  Worklist.append(DeferredNodes.begin(), DeferredNodes.end());
  // If we bailed early, conservatively return found.
  if (MaxSteps != 0 && Visited.size() >= MaxSteps)
    return true;
  return Found;
}

/// Return true if all the users of N are contained in Nodes.
/// NOTE: Requires at least one match, but doesn't require them all.
static bool areOnlyUsersOf(ArrayRef<const SDNode *> Nodes, const SDNode *N);

/// Return the number of values used by this operation.
unsigned getNumOperands() const { return NumOperands; }

/// Return the maximum number of operands that a SDNode can hold.
static constexpr size_t getMaxNumOperands() {
  return std::numeric_limits<decltype(SDNode::NumOperands)>::max();
}

/// Helper method returns the integer value of a ConstantSDNode operand.
inline uint64_t getConstantOperandVal(unsigned Num) const;

/// Helper method returns the APInt of a ConstantSDNode operand.
inline const APInt &getConstantOperandAPInt(unsigned Num) const;

const SDValue &getOperand(unsigned Num) const {
  assert(Num < NumOperands && "Invalid child # of SDNode!")((Num < NumOperands && "Invalid child # of SDNode!"
) ? static_cast<void> (0) : __assert_fail ("Num < NumOperands && \"Invalid child # of SDNode!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 952, __PRETTY_FUNCTION__));
  return OperandList[Num];
}

using op_iterator = SDUse *;

op_iterator op_begin() const { return OperandList; }
op_iterator op_end() const { return OperandList+NumOperands; }
ArrayRef<SDUse> ops() const { return makeArrayRef(op_begin(), op_end()); }

/// Iterator for directly iterating over the operand SDValue's.
struct value_op_iterator
    : iterator_adaptor_base<value_op_iterator, op_iterator,
                            std::random_access_iterator_tag, SDValue,
                            ptrdiff_t, value_op_iterator *,
                            value_op_iterator *> {
  explicit value_op_iterator(SDUse *U = nullptr)
    : iterator_adaptor_base(U) {}

  const SDValue &operator*() const { return I->get(); }
};

iterator_range<value_op_iterator> op_values() const {
  return make_range(value_op_iterator(op_begin()),
                    value_op_iterator(op_end()));
}

SDVTList getVTList() const {
  SDVTList X = { ValueList, NumValues };
  return X;
}

/// If this node has a glue operand, return the node
/// to which the glue operand points. Otherwise return NULL.
SDNode *getGluedNode() const {
  if (getNumOperands() != 0 &&
      getOperand(getNumOperands()-1).getValueType() == MVT::Glue)
    return getOperand(getNumOperands()-1).getNode();
  return nullptr;
}

/// If this node has a glue value with a user, return
/// the user (there is at most one). Otherwise return NULL.
SDNode *getGluedUser() const {
  for (use_iterator UI = use_begin(), UE = use_end(); UI != UE; ++UI)
    if (UI.getUse().get().getValueType() == MVT::Glue)
      return *UI;
  return nullptr;
}

const SDNodeFlags getFlags() const { return Flags; }
void setFlags(SDNodeFlags NewFlags) { Flags = NewFlags; }
bool isFast() { return Flags.isFast(); }

/// Clear any flags in this node that aren't also set in Flags.
/// If Flags is not in a defined state then this has no effect.
void intersectFlagsWith(const SDNodeFlags Flags);

/// Return the number of values defined/returned by this operator.
unsigned getNumValues() const { return NumValues; }

/// Return the type of a specified result.
EVT getValueType(unsigned ResNo) const {
  assert(ResNo < NumValues && "Illegal result number!")((ResNo < NumValues && "Illegal result number!") ?
 static_cast<void> (0) : __assert_fail ("ResNo < NumValues && \"Illegal result number!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1015, __PRETTY_FUNCTION__));
  return ValueList[ResNo];
}

/// Return the type of a specified result as a simple type.
MVT getSimpleValueType(unsigned ResNo) const {
  return getValueType(ResNo).getSimpleVT();
}

/// Returns MVT::getSizeInBits(getValueType(ResNo)).
unsigned getValueSizeInBits(unsigned ResNo) const {
  return getValueType(ResNo).getSizeInBits();
}

using value_iterator = const EVT *;

value_iterator value_begin() const { return ValueList; }
value_iterator value_end() const { return ValueList+NumValues; }

/// Return the opcode of this operation for printing.
std::string getOperationName(const SelectionDAG *G = nullptr) const;
static const char* getIndexedModeName(ISD::MemIndexedMode AM);
void print_types(raw_ostream &OS, const SelectionDAG *G) const;
void print_details(raw_ostream &OS, const SelectionDAG *G) const;
void print(raw_ostream &OS, const SelectionDAG *G = nullptr) const;
void printr(raw_ostream &OS, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and all children down to
/// the leaves.  The given SelectionDAG allows target-specific nodes
/// to be printed in human-readable form.  Unlike printr, this will
/// print the whole DAG, including children that appear multiple
/// times.
///
void printrFull(raw_ostream &O, const SelectionDAG *G = nullptr) const;

/// Print a SelectionDAG node and children up to
/// depth "depth."  The given SelectionDAG allows target-specific
/// nodes to be printed in human-readable form.  Unlike printr, this
/// will print children that appear multiple times wherever they are
/// used.
///
void printrWithDepth(raw_ostream &O, const SelectionDAG *G = nullptr,
                     unsigned depth = 100) const;

/// Dump this node, for debugging.
void dump() const;

/// Dump (recursively) this node and its use-def subgraph.
void dumpr() const;

/// Dump this node, for debugging.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dump(const SelectionDAG *G) const;

/// Dump (recursively) this node and its use-def subgraph.
/// The given SelectionDAG allows target-specific nodes to be printed
/// in human-readable form.
void dumpr(const SelectionDAG *G) const;

/// printrFull to dbgs().  The given SelectionDAG allows
/// target-specific nodes to be printed in human-readable form.
/// Unlike dumpr, this will print the whole DAG, including children
/// that appear multiple times.
void dumprFull(const SelectionDAG *G = nullptr) const;

/// printrWithDepth to dbgs().  The given
/// SelectionDAG allows target-specific nodes to be printed in
/// human-readable form.  Unlike dumpr, this will print children
/// that appear multiple times wherever they are used.
///
void dumprWithDepth(const SelectionDAG *G = nullptr,
                    unsigned depth = 100) const;

/// Gather unique data for the node.
void Profile(FoldingSetNodeID &ID) const;

/// This method should only be used by the SDUse class.
void addUse(SDUse &U) { U.addToList(&UseList); }

1095protected:
static SDVTList getSDVTList(EVT VT) {
  SDVTList Ret = { getValueTypeList(VT), 1 };
  return Ret;
}

/// Create an SDNode.
///
/// SDNodes are created without any operands, and never own the operand
/// storage. To add operands, see SelectionDAG::createOperands.
SDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
    : NodeType(Opc), ValueList(VTs.VTs), NumValues(VTs.NumVTs),
      IROrder(Order), debugLoc(std::move(dl)) {
  memset(&RawSDNodeBits, 0, sizeof(RawSDNodeBits));
  assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1109, __PRETTY_FUNCTION__));
  assert(NumValues == VTs.NumVTs &&((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1111, __PRETTY_FUNCTION__))
         "NumValues wasn't wide enough for its operands!")((NumValues == VTs.NumVTs && "NumValues wasn't wide enough for its operands!"
) ? static_cast<void> (0) : __assert_fail ("NumValues == VTs.NumVTs && \"NumValues wasn't wide enough for its operands!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1111, __PRETTY_FUNCTION__));
}

/// Release the operands and set this node to have zero operands.
void DropOperands();
1116};

1118/// Wrapper class for IR location info (IR ordering and DebugLoc) to be passed
1119/// into SDNode creation functions.
1120/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracted
1121/// from the original Instruction, and IROrder is the ordinal position of
1122/// the instruction.
1123/// When an SDNode is created after the DAG is being built, both DebugLoc and
1124/// the IROrder are propagated from the original SDNode.
1125/// So SDLoc class provides two constructors besides the default one, one to
1126/// be used by the DAGBuilder, the other to be used by others.
1127class SDLoc {
1128private:
DebugLoc DL;
int IROrder = 0;

1132public:
SDLoc() = default;
SDLoc(const SDNode *N) : DL(N->getDebugLoc()), IROrder(N->getIROrder()) {}
SDLoc(const SDValue V) : SDLoc(V.getNode()) {}
SDLoc(const Instruction *I, int Order) : IROrder(Order) {
  assert(Order >= 0 && "bad IROrder")((Order >= 0 && "bad IROrder") ? static_cast<void
> (0) : __assert_fail ("Order >= 0 && \"bad IROrder\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1137, __PRETTY_FUNCTION__));
  if (I)
    DL = I->getDebugLoc();
}

unsigned getIROrder() const { return IROrder; }
const DebugLoc &getDebugLoc() const { return DL; }
1144};

1146// Define inline functions from the SDValue class.

1148inline SDValue::SDValue(SDNode *node, unsigned resno)
  : Node(node), ResNo(resno) {
// Explicitly check for !ResNo to avoid use-after-free, because there are
// callers that use SDValue(N, 0) with a deleted N to indicate successful
// combines.
assert((!Node || !ResNo || ResNo < Node->getNumValues()) &&(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
 "Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1154, __PRETTY_FUNCTION__))
       "Invalid result number for the given node!")(((!Node || !ResNo || ResNo < Node->getNumValues()) &&
 "Invalid result number for the given node!") ? static_cast<
void> (0) : __assert_fail ("(!Node || !ResNo || ResNo < Node->getNumValues()) && \"Invalid result number for the given node!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1154, __PRETTY_FUNCTION__));
assert(ResNo < -2U && "Cannot use result numbers reserved for DenseMaps.")((ResNo < -2U && "Cannot use result numbers reserved for DenseMaps."
) ? static_cast<void> (0) : __assert_fail ("ResNo < -2U && \"Cannot use result numbers reserved for DenseMaps.\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1155, __PRETTY_FUNCTION__));
1156}

1158inline unsigned SDValue::getOpcode() const {
return Node->getOpcode();
1160}

1162inline EVT SDValue::getValueType() const {
return Node->getValueType(ResNo);
24
←
Called C++ object pointer is null
1164}

1166inline unsigned SDValue::getNumOperands() const {
return Node->getNumOperands();
1168}

1170inline const SDValue &SDValue::getOperand(unsigned i) const {
return Node->getOperand(i);
1172}

1174inline uint64_t SDValue::getConstantOperandVal(unsigned i) const {
return Node->getConstantOperandVal(i);
1176}

1178inline const APInt &SDValue::getConstantOperandAPInt(unsigned i) const {
return Node->getConstantOperandAPInt(i);
1180}

1182inline bool SDValue::isTargetOpcode() const {
return Node->isTargetOpcode();
1184}

1186inline bool SDValue::isTargetMemoryOpcode() const {
return Node->isTargetMemoryOpcode();
1188}

1190inline bool SDValue::isMachineOpcode() const {
return Node->isMachineOpcode();
1192}

1194inline unsigned SDValue::getMachineOpcode() const {
return Node->getMachineOpcode();
1196}

1198inline bool SDValue::isUndef() const {
return Node->isUndef();
1200}

1202inline bool SDValue::use_empty() const {
return !Node->hasAnyUseOfValue(ResNo);
1204}

1206inline bool SDValue::hasOneUse() const {
return Node->hasNUsesOfValue(1, ResNo);
1208}

1210inline const DebugLoc &SDValue::getDebugLoc() const {
return Node->getDebugLoc();
1212}

1214inline void SDValue::dump() const {
return Node->dump();
1216}

1218inline void SDValue::dump(const SelectionDAG *G) const {
return Node->dump(G);
1220}

1222inline void SDValue::dumpr() const {
return Node->dumpr();
1224}

1226inline void SDValue::dumpr(const SelectionDAG *G) const {
return Node->dumpr(G);
1228}

1230// Define inline functions from the SDUse class.

1232inline void SDUse::set(const SDValue &V) {
if (Val.getNode()) removeFromList();
Val = V;
if (V.getNode()) V.getNode()->addUse(*this);
1236}

1238inline void SDUse::setInitial(const SDValue &V) {
Val = V;
V.getNode()->addUse(*this);
1241}

1243inline void SDUse::setNode(SDNode *N) {
if (Val.getNode()) removeFromList();
Val.setNode(N);
if (N) N->addUse(*this);
1247}

1249/// This class is used to form a handle around another node that
1250/// is persistent and is updated across invocations of replaceAllUsesWith on its
1251/// operand.  This node should be directly created by end-users and not added to
1252/// the AllNodes list.
1253class HandleSDNode : public SDNode {
SDUse Op;

1256public:
explicit HandleSDNode(SDValue X)
  : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
  // HandleSDNodes are never inserted into the DAG, so they won't be
  // auto-numbered. Use ID 65535 as a sentinel.
  PersistentId = 0xffff;

  // Manually set up the operand list. This node type is special in that it's
  // always stack allocated and SelectionDAG does not manage its operands.
  // TODO: This should either (a) not be in the SDNode hierarchy, or (b) not
  // be so special.
  Op.setUser(this);
  Op.setInitial(X);
  NumOperands = 1;
  OperandList = &Op;
}
~HandleSDNode();

const SDValue &getValue() const { return Op; }
1275};

1277class AddrSpaceCastSDNode : public SDNode {
1278private:
unsigned SrcAddrSpace;
unsigned DestAddrSpace;

1282public:
AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT,
                    unsigned SrcAS, unsigned DestAS);

unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
unsigned getDestAddressSpace() const { return DestAddrSpace; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ADDRSPACECAST;
}
1292};

1294/// This is an abstract virtual class for memory operations.
1295class MemSDNode : public SDNode {
1296private:
// VT of in-memory value.
EVT MemoryVT;

1300protected:
/// Memory reference information.
MachineMemOperand *MMO;

1304public:
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
          EVT memvt, MachineMemOperand *MMO);

bool readMem() const { return MMO->isLoad(); }
bool writeMem() const { return MMO->isStore(); }

/// Returns alignment and volatility of the memory access
unsigned getOriginalAlignment() const {
  return MMO->getBaseAlignment();
}
unsigned getAlignment() const {
  return MMO->getAlignment();
}

/// Return the SubclassData value, without HasDebugValue. This contains an
/// encoding of the volatile flag, as well as bits used by subclasses. This
/// function should only be used to compute a FoldingSetNodeID value.
/// The HasDebugValue bit is masked out because CSE map needs to match
/// nodes with debug info with nodes without debug info. Same is about
/// isDivergent bit.
unsigned getRawSubclassData() const {
  uint16_t Data;
  union {
    char RawSDNodeBits[sizeof(uint16_t)];
    SDNodeBitfields SDNodeBits;
  };
  memcpy(&RawSDNodeBits, &this->RawSDNodeBits, sizeof(this->RawSDNodeBits));
  SDNodeBits.HasDebugValue = 0;
  SDNodeBits.IsDivergent = false;
  memcpy(&Data, &RawSDNodeBits, sizeof(RawSDNodeBits));
  return Data;
}

bool isVolatile() const { return MemSDNodeBits.IsVolatile; }
bool isNonTemporal() const { return MemSDNodeBits.IsNonTemporal; }
bool isDereferenceable() const { return MemSDNodeBits.IsDereferenceable; }
bool isInvariant() const { return MemSDNodeBits.IsInvariant; }

// Returns the offset from the location of the access.
int64_t getSrcValueOffset() const { return MMO->getOffset(); }

/// Returns the AA info that describes the dereference.
AAMDNodes getAAInfo() const { return MMO->getAAInfo(); }

/// Returns the Ranges that describes the dereference.
const MDNode *getRanges() const { return MMO->getRanges(); }

/// Returns the synchronization scope ID for this memory operation.
SyncScope::ID getSyncScopeID() const { return MMO->getSyncScopeID(); }

/// Return the atomic ordering requirements for this memory operation. For
/// cmpxchg atomic operations, return the atomic ordering requirements when
/// store occurs.
AtomicOrdering getOrdering() const { return MMO->getOrdering(); }

/// Return true if the memory operation ordering is Unordered or higher.
bool isAtomic() const { return MMO->isAtomic(); }

/// Returns true if the memory operation doesn't imply any ordering
/// constraints on surrounding memory operations beyond the normal memory
/// aliasing rules.
bool isUnordered() const { return MMO->isUnordered(); }

/// Returns true if the memory operation is neither atomic or volatile.
bool isSimple() const { return !isAtomic() && !isVolatile(); }

/// Return the type of the in-memory value.
EVT getMemoryVT() const { return MemoryVT; }

/// Return a MachineMemOperand object describing the memory
/// reference performed by operation.
MachineMemOperand *getMemOperand() const { return MMO; }

const MachinePointerInfo &getPointerInfo() const {
  return MMO->getPointerInfo();
}

/// Return the address space for the associated pointer
unsigned getAddressSpace() const {
  return getPointerInfo().getAddrSpace();
}

/// Update this MemSDNode's MachineMemOperand information
/// to reflect the alignment of NewMMO, if it has a greater alignment.
/// This must only be used when the new alignment applies to all users of
/// this MachineMemOperand.
void refineAlignment(const MachineMemOperand *NewMMO) {
  MMO->refineAlignment(NewMMO);
}

const SDValue &getChain() const { return getOperand(0); }
const SDValue &getBasePtr() const {
  return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // For some targets, we lower some target intrinsics to a MemIntrinsicNode
  // with either an intrinsic or a target opcode.
  return N->getOpcode() == ISD::LOAD                ||
         N->getOpcode() == ISD::STORE               ||
         N->getOpcode() == ISD::PREFETCH            ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
         N->getOpcode() == ISD::ATOMIC_SWAP         ||
         N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_SUB     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_AND     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_CLR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_OR      ||
         N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_NAND    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FADD    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FSUB    ||
         N->getOpcode() == ISD::ATOMIC_LOAD         ||
         N->getOpcode() == ISD::ATOMIC_STORE        ||
         N->getOpcode() == ISD::MLOAD               ||
         N->getOpcode() == ISD::MSTORE              ||
         N->getOpcode() == ISD::MGATHER             ||
         N->getOpcode() == ISD::MSCATTER            ||
         N->isMemIntrinsic()                        ||
         N->isTargetMemoryOpcode();
}
1432};

1434/// This is an SDNode representing atomic operations.
1435class AtomicSDNode : public MemSDNode {
1436public:
AtomicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTL,
             EVT MemVT, MachineMemOperand *MMO)
  : MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
  assert(((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) ||((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __PRETTY_FUNCTION__))
          MMO->isAtomic()) && "then why are we using an AtomicSDNode?")((((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE
) || MMO->isAtomic()) && "then why are we using an AtomicSDNode?"
) ? static_cast<void> (0) : __assert_fail ("((Opc != ISD::ATOMIC_LOAD && Opc != ISD::ATOMIC_STORE) || MMO->isAtomic()) && \"then why are we using an AtomicSDNode?\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1441, __PRETTY_FUNCTION__));
}

const SDValue &getBasePtr() const { return getOperand(1); }
const SDValue &getVal() const { return getOperand(2); }

/// Returns true if this SDNode represents cmpxchg atomic operation, false
/// otherwise.
bool isCompareAndSwap() const {
  unsigned Op = getOpcode();
  return Op == ISD::ATOMIC_CMP_SWAP ||
         Op == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS;
}

/// For cmpxchg atomic operations, return the atomic ordering requirements
/// when store does not occur.
AtomicOrdering getFailureOrdering() const {
  assert(isCompareAndSwap() && "Must be cmpxchg operation")((isCompareAndSwap() && "Must be cmpxchg operation") ?
 static_cast<void> (0) : __assert_fail ("isCompareAndSwap() && \"Must be cmpxchg operation\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1458, __PRETTY_FUNCTION__));
  return MMO->getFailureOrdering();
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ATOMIC_CMP_SWAP     ||
         N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS ||
         N->getOpcode() == ISD::ATOMIC_SWAP         ||
         N->getOpcode() == ISD::ATOMIC_LOAD_ADD     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_SUB     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_AND     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_CLR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_OR      ||
         N->getOpcode() == ISD::ATOMIC_LOAD_XOR     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_NAND    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MIN     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_MAX     ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMIN    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_UMAX    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FADD    ||
         N->getOpcode() == ISD::ATOMIC_LOAD_FSUB    ||
         N->getOpcode() == ISD::ATOMIC_LOAD         ||
         N->getOpcode() == ISD::ATOMIC_STORE;
}
1483};

1485/// This SDNode is used for target intrinsics that touch
1486/// memory and need an associated MachineMemOperand. Its opcode may be
1487/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcode
1488/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
1489class MemIntrinsicSDNode : public MemSDNode {
1490public:
MemIntrinsicSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl,
                   SDVTList VTs, EVT MemoryVT, MachineMemOperand *MMO)
    : MemSDNode(Opc, Order, dl, VTs, MemoryVT, MMO) {
  SDNodeBits.IsMemIntrinsic = true;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  // We lower some target intrinsics to their target opcode
  // early a node with a target opcode can be of this class
  return N->isMemIntrinsic()             ||
         N->getOpcode() == ISD::PREFETCH ||
         N->isTargetMemoryOpcode();
}
1505};

1507/// This SDNode is used to implement the code generator
1508/// support for the llvm IR shufflevector instruction.  It combines elements
1509/// from two input vectors into a new input vector, with the selection and
1510/// ordering of elements determined by an array of integers, referred to as
1511/// the shuffle mask.  For input vectors of width N, mask indices of 0..N-1
1512/// refer to elements from the LHS input, and indices from N to 2N-1 the RHS.
1513/// An index of -1 is treated as undef, such that the code generator may put
1514/// any value in the corresponding element of the result.
1515class ShuffleVectorSDNode : public SDNode {
// The memory for Mask is owned by the SelectionDAG's OperandAllocator, and
// is freed when the SelectionDAG object is destroyed.
const int *Mask;

1520protected:
friend class SelectionDAG;

ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M)
    : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}

1526public:
ArrayRef<int> getMask() const {
  EVT VT = getValueType(0);
  return makeArrayRef(Mask, VT.getVectorNumElements());
}

int getMaskElt(unsigned Idx) const {
  assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of range!")((Idx < getValueType(0).getVectorNumElements() && "Idx out of range!"
) ? static_cast<void> (0) : __assert_fail ("Idx < getValueType(0).getVectorNumElements() && \"Idx out of range!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1533, __PRETTY_FUNCTION__));
  return Mask[Idx];
}

bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }

int getSplatIndex() const {
  assert(isSplat() && "Cannot get splat index for non-splat!")((isSplat() && "Cannot get splat index for non-splat!"
) ? static_cast<void> (0) : __assert_fail ("isSplat() && \"Cannot get splat index for non-splat!\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1540, __PRETTY_FUNCTION__));
  EVT VT = getValueType(0);
  for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
    if (Mask[i] >= 0)
      return Mask[i];

  // We can choose any index value here and be correct because all elements
  // are undefined. Return 0 for better potential for callers to simplify.
  return 0;
}

static bool isSplatMask(const int *Mask, EVT VT);

/// Change values in a shuffle permute mask assuming
/// the two vector operands have swapped position.
static void commuteMask(MutableArrayRef<int> Mask) {
  unsigned NumElems = Mask.size();
  for (unsigned i = 0; i != NumElems; ++i) {
    int idx = Mask[i];
    if (idx < 0)
      continue;
    else if (idx < (int)NumElems)
      Mask[i] = idx + NumElems;
    else
      Mask[i] = idx - NumElems;
  }
}

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::VECTOR_SHUFFLE;
}
1571};

1573class ConstantSDNode : public SDNode {
friend class SelectionDAG;

const ConstantInt *Value;

ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
             getSDVTList(VT)),
      Value(val) {
  ConstantSDNodeBits.IsOpaque = isOpaque;
}

1585public:
const ConstantInt *getConstantIntValue() const { return Value; }
const APInt &getAPIntValue() const { return Value->getValue(); }
uint64_t getZExtValue() const { return Value->getZExtValue(); }
int64_t getSExtValue() const { return Value->getSExtValue(); }
uint64_t getLimitedValue(uint64_t Limit = UINT64_MAX(18446744073709551615UL)) {
  return Value->getLimitedValue(Limit);
}

bool isOne() const { return Value->isOne(); }
bool isNullValue() const { return Value->isZero(); }
bool isAllOnesValue() const { return Value->isMinusOne(); }

bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Constant ||
         N->getOpcode() == ISD::TargetConstant;
}
1604};

1606uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getZExtValue();
1608}

1610const APInt &SDNode::getConstantOperandAPInt(unsigned Num) const {
return cast<ConstantSDNode>(getOperand(Num))->getAPIntValue();
1612}

1614class ConstantFPSDNode : public SDNode {
friend class SelectionDAG;

const ConstantFP *Value;

ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
    : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0,
             DebugLoc(), getSDVTList(VT)),
      Value(val) {}

1624public:
const APFloat& getValueAPF() const { return Value->getValueAPF(); }
const ConstantFP *getConstantFPValue() const { return Value; }

/// Return true if the value is positive or negative zero.
bool isZero() const { return Value->isZero(); }

/// Return true if the value is a NaN.
bool isNaN() const { return Value->isNaN(); }

/// Return true if the value is an infinity
bool isInfinity() const { return Value->isInfinity(); }

/// Return true if the value is negative.
bool isNegative() const { return Value->isNegative(); }

/// We don't rely on operator== working on double values, as
/// it returns true for things that are clearly not equal, like -0.0 and 0.0.
/// As such, this method can be used to do an exact bit-for-bit comparison of
/// two floating point values.

/// We leave the version with the double argument here because it's just so
/// convenient to write "2.0" and the like.  Without this function we'd
/// have to duplicate its logic everywhere it's called.
bool isExactlyValue(double V) const {
  return Value->getValueAPF().isExactlyValue(V);
}
bool isExactlyValue(const APFloat& V) const;

static bool isValueValidForType(EVT VT, const APFloat& Val);

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantFP ||
         N->getOpcode() == ISD::TargetConstantFP;
}
1659};

1661/// Returns true if \p V is a constant integer zero.
1662bool isNullConstant(SDValue V);

1664/// Returns true if \p V is an FP constant with a value of positive zero.
1665bool isNullFPConstant(SDValue V);

1667/// Returns true if \p V is an integer constant with all bits set.
1668bool isAllOnesConstant(SDValue V);

1670/// Returns true if \p V is a constant integer one.
1671bool isOneConstant(SDValue V);

1673/// Return the non-bitcasted source operand of \p V if it exists.
1674/// If \p V is not a bitcasted value, it is returned as-is.
1675SDValue peekThroughBitcasts(SDValue V);

1677/// Return the non-bitcasted and one-use source operand of \p V if it exists.
1678/// If \p V is not a bitcasted one-use value, it is returned as-is.
1679SDValue peekThroughOneUseBitcasts(SDValue V);

1681/// Return the non-extracted vector source operand of \p V if it exists.
1682/// If \p V is not an extracted subvector, it is returned as-is.
1683SDValue peekThroughExtractSubvectors(SDValue V);

1685/// Returns true if \p V is a bitwise not operation. Assumes that an all ones
1686/// constant is canonicalized to be operand 1.
1687bool isBitwiseNot(SDValue V, bool AllowUndefs = false);

1689/// Returns the SDNode if it is a constant splat BuildVector or constant int.
1690ConstantSDNode *isConstOrConstSplat(SDValue N, bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1693/// Returns the SDNode if it is a demanded constant splat BuildVector or
1694/// constant int.
1695ConstantSDNode *isConstOrConstSplat(SDValue N, const APInt &DemandedElts,
                                  bool AllowUndefs = false,
                                  bool AllowTruncation = false);

1699/// Returns the SDNode if it is a constant splat BuildVector or constant float.
1700ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, bool AllowUndefs = false);

1702/// Returns the SDNode if it is a demanded constant splat BuildVector or
1703/// constant float.
1704ConstantFPSDNode *isConstOrConstSplatFP(SDValue N, const APInt &DemandedElts,
                                      bool AllowUndefs = false);

1707/// Return true if the value is a constant 0 integer or a splatted vector of
1708/// a constant 0 integer (with no undefs by default).
1709/// Build vector implicit truncation is not an issue for null values.
1710bool isNullOrNullSplat(SDValue V, bool AllowUndefs = false);

1712/// Return true if the value is a constant 1 integer or a splatted vector of a
1713/// constant 1 integer (with no undefs).
1714/// Does not permit build vector implicit truncation.
1715bool isOneOrOneSplat(SDValue V);

1717/// Return true if the value is a constant -1 integer or a splatted vector of a
1718/// constant -1 integer (with no undefs).
1719/// Does not permit build vector implicit truncation.
1720bool isAllOnesOrAllOnesSplat(SDValue V);

1722class GlobalAddressSDNode : public SDNode {
friend class SelectionDAG;

const GlobalValue *TheGlobal;
int64_t Offset;
unsigned TargetFlags;

GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
                    const GlobalValue *GA, EVT VT, int64_t o,
                    unsigned TF);

1733public:
const GlobalValue *getGlobal() const { return TheGlobal; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }
// Return the address space this GlobalAddress belongs to.
unsigned getAddressSpace() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::GlobalAddress ||
         N->getOpcode() == ISD::TargetGlobalAddress ||
         N->getOpcode() == ISD::GlobalTLSAddress ||
         N->getOpcode() == ISD::TargetGlobalTLSAddress;
}
1746};

1748class FrameIndexSDNode : public SDNode {
friend class SelectionDAG;

int FI;

FrameIndexSDNode(int fi, EVT VT, bool isTarg)
  : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
    0, DebugLoc(), getSDVTList(VT)), FI(fi) {
}

1758public:
int getIndex() const { return FI; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::FrameIndex ||
         N->getOpcode() == ISD::TargetFrameIndex;
}
1765};

1767/// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate
1768/// the offet and size that are started/ended in the underlying FrameIndex.
1769class LifetimeSDNode : public SDNode {
friend class SelectionDAG;
int64_t Size;
int64_t Offset; // -1 if offset is unknown.

LifetimeSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl,
               SDVTList VTs, int64_t Size, int64_t Offset)
    : SDNode(Opcode, Order, dl, VTs), Size(Size), Offset(Offset) {}
1777public:
int64_t getFrameIndex() const {
  return cast<FrameIndexSDNode>(getOperand(1))->getIndex();
}

bool hasOffset() const { return Offset >= 0; }
int64_t getOffset() const {
  assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1784, __PRETTY_FUNCTION__));
  return Offset;
}
int64_t getSize() const {
  assert(hasOffset() && "offset is unknown")((hasOffset() && "offset is unknown") ? static_cast<
void> (0) : __assert_fail ("hasOffset() && \"offset is unknown\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1788, __PRETTY_FUNCTION__));
  return Size;
}

// Methods to support isa and dyn_cast
static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::LIFETIME_START ||
         N->getOpcode() == ISD::LIFETIME_END;
}
1797};

1799class JumpTableSDNode : public SDNode {
friend class SelectionDAG;

int JTI;
unsigned TargetFlags;

JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF)
  : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
    0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
}

1810public:
int getIndex() const { return JTI; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::JumpTable ||
         N->getOpcode() == ISD::TargetJumpTable;
}
1818};

1820class ConstantPoolSDNode : public SDNode {
friend class SelectionDAG;

union {
  const Constant *ConstVal;
  MachineConstantPoolValue *MachineCPVal;
} Val;
int Offset;  // It's a MachineConstantPoolValue if top bit is set.
unsigned Alignment;  // Minimum alignment requirement of CP (not log2 value).
unsigned TargetFlags;

ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
                   unsigned Align, unsigned TF)
  : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
           DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
           TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1836, __PRETTY_FUNCTION__));
  Val.ConstVal = c;
}

ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
                   EVT VT, int o, unsigned Align, unsigned TF)
  : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
           DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
           TargetFlags(TF) {
  assert(Offset >= 0 && "Offset is too large")((Offset >= 0 && "Offset is too large") ? static_cast
<void> (0) : __assert_fail ("Offset >= 0 && \"Offset is too large\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1845, __PRETTY_FUNCTION__));
  Val.MachineCPVal = v;
  Offset |= 1 << (sizeof(unsigned)*CHAR_BIT8-1);
}

1850public:
bool isMachineConstantPoolEntry() const {
  return Offset < 0;
}

const Constant *getConstVal() const {
  assert(!isMachineConstantPoolEntry() && "Wrong constantpool type")((!isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("!isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1856, __PRETTY_FUNCTION__));
  return Val.ConstVal;
}

MachineConstantPoolValue *getMachineCPVal() const {
  assert(isMachineConstantPoolEntry() && "Wrong constantpool type")((isMachineConstantPoolEntry() && "Wrong constantpool type"
) ? static_cast<void> (0) : __assert_fail ("isMachineConstantPoolEntry() && \"Wrong constantpool type\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 1861, __PRETTY_FUNCTION__));
  return Val.MachineCPVal;
}

int getOffset() const {
  return Offset & ~(1 << (sizeof(unsigned)*CHAR_BIT8-1));
}

// Return the alignment of this constant pool object, which is either 0 (for
// default alignment) or the desired value.
unsigned getAlignment() const { return Alignment; }
unsigned getTargetFlags() const { return TargetFlags; }

Type *getType() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::ConstantPool ||
         N->getOpcode() == ISD::TargetConstantPool;
}
1880};

1882/// Completely target-dependent object reference.
1883class TargetIndexSDNode : public SDNode {
friend class SelectionDAG;

unsigned TargetFlags;
int Index;
int64_t Offset;

1890public:
TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF)
    : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
      TargetFlags(TF), Index(Idx), Offset(Ofs) {}

unsigned getTargetFlags() const { return TargetFlags; }
int getIndex() const { return Index; }
int64_t getOffset() const { return Offset; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::TargetIndex;
}
1902};

1904class BasicBlockSDNode : public SDNode {
friend class SelectionDAG;

MachineBasicBlock *MBB;

/// Debug info is meaningful and potentially useful here, but we create
/// blocks out of order when they're jumped to, which makes it a bit
/// harder.  Let's see if we need it first.
explicit BasicBlockSDNode(MachineBasicBlock *mbb)
  : SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb)
{}

1916public:
MachineBasicBlock *getBasicBlock() const { return MBB; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BasicBlock;
}
1922};

1924/// A "pseudo-class" with methods for operating on BUILD_VECTORs.
1925class BuildVectorSDNode : public SDNode {
1926public:
// These are constructed as SDNodes and then cast to BuildVectorSDNodes.
explicit BuildVectorSDNode() = delete;

/// Check if this is a constant splat, and if so, find the
/// smallest element size that splats the vector.  If MinSplatBits is
/// nonzero, the element size must be at least that large.  Note that the
/// splat element may be the entire vector (i.e., a one element vector).
/// Returns the splat element value in SplatValue.  Any undefined bits in
/// that value are zero, and the corresponding bits in the SplatUndef mask
/// are set.  The SplatBitSize value is set to the splat element size in
/// bits.  HasAnyUndefs is set to true if any bits in the vector are
/// undefined.  isBigEndian describes the endianness of the target.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef,
                     unsigned &SplatBitSize, bool &HasAnyUndefs,
                     unsigned MinSplatBits = 0,
                     bool isBigEndian = false) const;

/// Returns the demanded splatted value or a null value if this is not a
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(const APInt &DemandedElts,
                      BitVector *UndefElements = nullptr) const;

/// Returns the splatted value or a null value if this is not a splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
SDValue getSplatValue(BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant or null if this is not a constant
/// splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(const APInt &DemandedElts,
                     BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant or null if this is not a constant
/// splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantSDNode *
getConstantSplatNode(BitVector *UndefElements = nullptr) const;

/// Returns the demanded splatted constant FP or null if this is not a
/// constant FP splat.
///
/// The DemandedElts mask indicates the elements that must be in the splat.
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(const APInt &DemandedElts,
                       BitVector *UndefElements = nullptr) const;

/// Returns the splatted constant FP or null if this is not a constant
/// FP splat.
///
/// If passed a non-null UndefElements bitvector, it will resize it to match
/// the vector width and set the bits where elements are undef.
ConstantFPSDNode *
getConstantFPSplatNode(BitVector *UndefElements = nullptr) const;

/// If this is a constant FP splat and the splatted constant FP is an
/// exact power or 2, return the log base 2 integer value.  Otherwise,
/// return -1.
///
/// The BitWidth specifies the necessary bit precision.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements,
                                        uint32_t BitWidth) const;

bool isConstant() const;

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BUILD_VECTOR;
}
2008};

2010/// An SDNode that holds an arbitrary LLVM IR Value. This is
2011/// used when the SelectionDAG needs to make a simple reference to something
2012/// in the LLVM IR representation.
2013///
2014class SrcValueSDNode : public SDNode {
friend class SelectionDAG;

const Value *V;

/// Create a SrcValue for a general value.
explicit SrcValueSDNode(const Value *v)
  : SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}

2023public:
/// Return the contained Value.
const Value *getValue() const { return V; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::SRCVALUE;
}
2030};

2032class MDNodeSDNode : public SDNode {
friend class SelectionDAG;

const MDNode *MD;

explicit MDNodeSDNode(const MDNode *md)
: SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(md)
{}

2041public:
const MDNode *getMD() const { return MD; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::MDNODE_SDNODE;
}
2047};

2049class RegisterSDNode : public SDNode {
friend class SelectionDAG;

unsigned Reg;

RegisterSDNode(unsigned reg, EVT VT)
  : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {}

2057public:
unsigned getReg() const { return Reg; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::Register;
}
2063};

2065class RegisterMaskSDNode : public SDNode {
friend class SelectionDAG;

// The memory for RegMask is not owned by the node.
const uint32_t *RegMask;

RegisterMaskSDNode(const uint32_t *mask)
  : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
    RegMask(mask) {}

2075public:
const uint32_t *getRegMask() const { return RegMask; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::RegisterMask;
}
2081};

2083class BlockAddressSDNode : public SDNode {
friend class SelectionDAG;

const BlockAddress *BA;
int64_t Offset;
unsigned TargetFlags;

BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
                   int64_t o, unsigned Flags)
  : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
           BA(ba), Offset(o), TargetFlags(Flags) {}

2095public:
const BlockAddress *getBlockAddress() const { return BA; }
int64_t getOffset() const { return Offset; }
unsigned getTargetFlags() const { return TargetFlags; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::BlockAddress ||
         N->getOpcode() == ISD::TargetBlockAddress;
}
2104};

2106class LabelSDNode : public SDNode {
friend class SelectionDAG;

MCSymbol *Label;

LabelSDNode(unsigned Opcode, unsigned Order, const DebugLoc &dl, MCSymbol *L)
    : SDNode(Opcode, Order, dl, getSDVTList(MVT::Other)), Label(L) {
  assert(LabelSDNode::classof(this) && "not a label opcode")((LabelSDNode::classof(this) && "not a label opcode")
 ? static_cast<void> (0) : __assert_fail ("LabelSDNode::classof(this) && \"not a label opcode\""
, "/build/llvm-toolchain-snapshot-10~svn374814/include/llvm/CodeGen/SelectionDAGNodes.h"
, 2113, __PRETTY_FUNCTION__));
}

2116public:
MCSymbol *getLabel() const { return Label; }

static bool classof(const SDNode *N) {
  return N->getOpcode() == ISD::EH_LABEL ||
         N->getOpcode() == ISD::ANNOTATION_LABEL;
}
2123};

2125class ExternalSymbolSDNode : public SDNode {
friend class SelectionDAG;

const char *Symbol;
unsigned TargetFlags;

ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT)
    : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0,
             DebugLoc(), getSDVTList(VT)),
      Symbol(Sym), TargetFlags(TF) {}

2136public:
2137