Bug Summary

File:lib/Target/Hexagon/HexagonInstrInfo.cpp
Location:line 1363, column 13
Description:Branch condition evaluates to a garbage value

Annotated Source Code

1//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Hexagon implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "HexagonInstrInfo.h"
15#include "Hexagon.h"
16#include "HexagonRegisterInfo.h"
17#include "HexagonSubtarget.h"
18#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
29#include "llvm/Support/MathExtras.h"
30#include "llvm/Support/raw_ostream.h"
31#include <cctype>
32
33using namespace llvm;
34
35#define DEBUG_TYPE"hexagon-instrinfo" "hexagon-instrinfo"
36
37#define GET_INSTRINFO_CTOR_DTOR
38#define GET_INSTRMAP_INFO
39#include "HexagonGenInstrInfo.inc"
40#include "HexagonGenDFAPacketizer.inc"
41
42using namespace llvm;
43
44cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
45 cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
46 "packetization boundary."));
47
48static cl::opt<bool> EnableBranchPrediction("hexagon-enable-branch-prediction",
49 cl::Hidden, cl::init(true), cl::desc("Enable branch prediction"));
50
51static cl::opt<bool> DisableNVSchedule("disable-hexagon-nv-schedule",
52 cl::Hidden, cl::ZeroOrMore, cl::init(false),
53 cl::desc("Disable schedule adjustment for new value stores."));
54
55static cl::opt<bool> EnableTimingClassLatency(
56 "enable-timing-class-latency", cl::Hidden, cl::init(false),
57 cl::desc("Enable timing class latency"));
58
59static cl::opt<bool> EnableALUForwarding(
60 "enable-alu-forwarding", cl::Hidden, cl::init(true),
61 cl::desc("Enable vec alu forwarding"));
62
63static cl::opt<bool> EnableACCForwarding(
64 "enable-acc-forwarding", cl::Hidden, cl::init(true),
65 cl::desc("Enable vec acc forwarding"));
66
67static cl::opt<bool> BranchRelaxAsmLarge("branch-relax-asm-large",
68 cl::init(true), cl::Hidden, cl::ZeroOrMore, cl::desc("branch relax asm"));
69
70///
71/// Constants for Hexagon instructions.
72///
73const int Hexagon_MEMV_OFFSET_MAX_128B = 2047; // #s7
74const int Hexagon_MEMV_OFFSET_MIN_128B = -2048; // #s7
75const int Hexagon_MEMV_OFFSET_MAX = 1023; // #s6
76const int Hexagon_MEMV_OFFSET_MIN = -1024; // #s6
77const int Hexagon_MEMW_OFFSET_MAX = 4095;
78const int Hexagon_MEMW_OFFSET_MIN = -4096;
79const int Hexagon_MEMD_OFFSET_MAX = 8191;
80const int Hexagon_MEMD_OFFSET_MIN = -8192;
81const int Hexagon_MEMH_OFFSET_MAX = 2047;
82const int Hexagon_MEMH_OFFSET_MIN = -2048;
83const int Hexagon_MEMB_OFFSET_MAX = 1023;
84const int Hexagon_MEMB_OFFSET_MIN = -1024;
85const int Hexagon_ADDI_OFFSET_MAX = 32767;
86const int Hexagon_ADDI_OFFSET_MIN = -32768;
87const int Hexagon_MEMD_AUTOINC_MAX = 56;
88const int Hexagon_MEMD_AUTOINC_MIN = -64;
89const int Hexagon_MEMW_AUTOINC_MAX = 28;
90const int Hexagon_MEMW_AUTOINC_MIN = -32;
91const int Hexagon_MEMH_AUTOINC_MAX = 14;
92const int Hexagon_MEMH_AUTOINC_MIN = -16;
93const int Hexagon_MEMB_AUTOINC_MAX = 7;
94const int Hexagon_MEMB_AUTOINC_MIN = -8;
95const int Hexagon_MEMV_AUTOINC_MAX = 192;
96const int Hexagon_MEMV_AUTOINC_MIN = -256;
97const int Hexagon_MEMV_AUTOINC_MAX_128B = 384;
98const int Hexagon_MEMV_AUTOINC_MIN_128B = -512;
99
100// Pin the vtable to this file.
101void HexagonInstrInfo::anchor() {}
102
103HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
104 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
105 RI() {}
106
107
108static bool isIntRegForSubInst(unsigned Reg) {
109 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
110 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23);
111}
112
113
114static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
117}
118
119
120/// Calculate number of instructions excluding the debug instructions.
121static unsigned nonDbgMICount(MachineBasicBlock::const_instr_iterator MIB,
122 MachineBasicBlock::const_instr_iterator MIE) {
123 unsigned Count = 0;
124 for (; MIB != MIE; ++MIB) {
125 if (!MIB->isDebugValue())
126 ++Count;
127 }
128 return Count;
129}
130
131
132/// Find the hardware loop instruction used to set-up the specified loop.
133/// On Hexagon, we have two instructions used to set-up the hardware loop
134/// (LOOP0, LOOP1) with corresponding endloop (ENDLOOP0, ENDLOOP1) instructions
135/// to indicate the end of a loop.
136static MachineInstr *findLoopInstr(MachineBasicBlock *BB, int EndLoopOp,
137 SmallPtrSet<MachineBasicBlock *, 8> &Visited) {
138 int LOOPi;
139 int LOOPr;
140 if (EndLoopOp == Hexagon::ENDLOOP0) {
141 LOOPi = Hexagon::J2_loop0i;
142 LOOPr = Hexagon::J2_loop0r;
143 } else { // EndLoopOp == Hexagon::EndLOOP1
144 LOOPi = Hexagon::J2_loop1i;
145 LOOPr = Hexagon::J2_loop1r;
146 }
147
148 // The loop set-up instruction will be in a predecessor block
149 for (MachineBasicBlock::pred_iterator PB = BB->pred_begin(),
150 PE = BB->pred_end(); PB != PE; ++PB) {
151 // If this has been visited, already skip it.
152 if (!Visited.insert(*PB).second)
153 continue;
154 if (*PB == BB)
155 continue;
156 for (MachineBasicBlock::reverse_instr_iterator I = (*PB)->instr_rbegin(),
157 E = (*PB)->instr_rend(); I != E; ++I) {
158 int Opc = I->getOpcode();
159 if (Opc == LOOPi || Opc == LOOPr)
160 return &*I;
161 // We've reached a different loop, which means the loop0 has been removed.
162 if (Opc == EndLoopOp)
163 return 0;
164 }
165 // Check the predecessors for the LOOP instruction.
166 MachineInstr *loop = findLoopInstr(*PB, EndLoopOp, Visited);
167 if (loop)
168 return loop;
169 }
170 return 0;
171}
172
173
174/// Gather register def/uses from MI.
175/// This treats possible (predicated) defs as actually happening ones
176/// (conservatively).
177static inline void parseOperands(const MachineInstr *MI,
178 SmallVector<unsigned, 4> &Defs, SmallVector<unsigned, 8> &Uses) {
179 Defs.clear();
180 Uses.clear();
181
182 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
183 const MachineOperand &MO = MI->getOperand(i);
184
185 if (!MO.isReg())
186 continue;
187
188 unsigned Reg = MO.getReg();
189 if (!Reg)
190 continue;
191
192 if (MO.isUse())
193 Uses.push_back(MO.getReg());
194
195 if (MO.isDef())
196 Defs.push_back(MO.getReg());
197 }
198}
199
200
201// Position dependent, so check twice for swap.
202static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) {
203 switch (Ga) {
204 case HexagonII::HSIG_None:
205 default:
206 return false;
207 case HexagonII::HSIG_L1:
208 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_A);
209 case HexagonII::HSIG_L2:
210 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
211 Gb == HexagonII::HSIG_A);
212 case HexagonII::HSIG_S1:
213 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
214 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_A);
215 case HexagonII::HSIG_S2:
216 return (Gb == HexagonII::HSIG_L1 || Gb == HexagonII::HSIG_L2 ||
217 Gb == HexagonII::HSIG_S1 || Gb == HexagonII::HSIG_S2 ||
218 Gb == HexagonII::HSIG_A);
219 case HexagonII::HSIG_A:
220 return (Gb == HexagonII::HSIG_A);
221 case HexagonII::HSIG_Compound:
222 return (Gb == HexagonII::HSIG_Compound);
223 }
224 return false;
225}
226
227
228
229/// isLoadFromStackSlot - If the specified machine instruction is a direct
230/// load from a stack slot, return the virtual or physical register number of
231/// the destination along with the FrameIndex of the loaded stack slot. If
232/// not, return 0. This predicate must return 0 if the instruction has
233/// any side effects other than loading from the stack slot.
234unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
235 int &FrameIndex) const {
236 switch (MI->getOpcode()) {
237 default:
238 break;
239 case Hexagon::L2_loadrb_io:
240 case Hexagon::L2_loadrub_io:
241 case Hexagon::L2_loadrh_io:
242 case Hexagon::L2_loadruh_io:
243 case Hexagon::L2_loadri_io:
244 case Hexagon::L2_loadrd_io:
245 case Hexagon::V6_vL32b_ai:
246 case Hexagon::V6_vL32b_ai_128B:
247 case Hexagon::V6_vL32Ub_ai:
248 case Hexagon::V6_vL32Ub_ai_128B:
249 case Hexagon::LDriw_pred:
250 case Hexagon::LDriw_mod:
251 case Hexagon::LDriq_pred_V6:
252 case Hexagon::LDriq_pred_vec_V6:
253 case Hexagon::LDriv_pseudo_V6:
254 case Hexagon::LDrivv_pseudo_V6:
255 case Hexagon::LDriq_pred_V6_128B:
256 case Hexagon::LDriq_pred_vec_V6_128B:
257 case Hexagon::LDriv_pseudo_V6_128B:
258 case Hexagon::LDrivv_pseudo_V6_128B: {
259 const MachineOperand OpFI = MI->getOperand(1);
260 if (!OpFI.isFI())
261 return 0;
262 const MachineOperand OpOff = MI->getOperand(2);
263 if (!OpOff.isImm() || OpOff.getImm() != 0)
264 return 0;
265 FrameIndex = OpFI.getIndex();
266 return MI->getOperand(0).getReg();
267 }
268
269 case Hexagon::L2_ploadrbt_io:
270 case Hexagon::L2_ploadrbf_io:
271 case Hexagon::L2_ploadrubt_io:
272 case Hexagon::L2_ploadrubf_io:
273 case Hexagon::L2_ploadrht_io:
274 case Hexagon::L2_ploadrhf_io:
275 case Hexagon::L2_ploadruht_io:
276 case Hexagon::L2_ploadruhf_io:
277 case Hexagon::L2_ploadrit_io:
278 case Hexagon::L2_ploadrif_io:
279 case Hexagon::L2_ploadrdt_io:
280 case Hexagon::L2_ploadrdf_io: {
281 const MachineOperand OpFI = MI->getOperand(2);
282 if (!OpFI.isFI())
283 return 0;
284 const MachineOperand OpOff = MI->getOperand(3);
285 if (!OpOff.isImm() || OpOff.getImm() != 0)
286 return 0;
287 FrameIndex = OpFI.getIndex();
288 return MI->getOperand(0).getReg();
289 }
290 }
291
292 return 0;
293}
294
295
296/// isStoreToStackSlot - If the specified machine instruction is a direct
297/// store to a stack slot, return the virtual or physical register number of
298/// the source reg along with the FrameIndex of the loaded stack slot. If
299/// not, return 0. This predicate must return 0 if the instruction has
300/// any side effects other than storing to the stack slot.
301unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
302 int &FrameIndex) const {
303 switch (MI->getOpcode()) {
304 default:
305 break;
306 case Hexagon::S2_storerb_io:
307 case Hexagon::S2_storerh_io:
308 case Hexagon::S2_storeri_io:
309 case Hexagon::S2_storerd_io:
310 case Hexagon::V6_vS32b_ai:
311 case Hexagon::V6_vS32b_ai_128B:
312 case Hexagon::V6_vS32Ub_ai:
313 case Hexagon::V6_vS32Ub_ai_128B:
314 case Hexagon::STriw_pred:
315 case Hexagon::STriw_mod:
316 case Hexagon::STriq_pred_V6:
317 case Hexagon::STriq_pred_vec_V6:
318 case Hexagon::STriv_pseudo_V6:
319 case Hexagon::STrivv_pseudo_V6:
320 case Hexagon::STriq_pred_V6_128B:
321 case Hexagon::STriq_pred_vec_V6_128B:
322 case Hexagon::STriv_pseudo_V6_128B:
323 case Hexagon::STrivv_pseudo_V6_128B: {
324 const MachineOperand &OpFI = MI->getOperand(0);
325 if (!OpFI.isFI())
326 return 0;
327 const MachineOperand &OpOff = MI->getOperand(1);
328 if (!OpOff.isImm() || OpOff.getImm() != 0)
329 return 0;
330 FrameIndex = OpFI.getIndex();
331 return MI->getOperand(2).getReg();
332 }
333
334 case Hexagon::S2_pstorerbt_io:
335 case Hexagon::S2_pstorerbf_io:
336 case Hexagon::S2_pstorerht_io:
337 case Hexagon::S2_pstorerhf_io:
338 case Hexagon::S2_pstorerit_io:
339 case Hexagon::S2_pstorerif_io:
340 case Hexagon::S2_pstorerdt_io:
341 case Hexagon::S2_pstorerdf_io: {
342 const MachineOperand &OpFI = MI->getOperand(1);
343 if (!OpFI.isFI())
344 return 0;
345 const MachineOperand &OpOff = MI->getOperand(2);
346 if (!OpOff.isImm() || OpOff.getImm() != 0)
347 return 0;
348 FrameIndex = OpFI.getIndex();
349 return MI->getOperand(3).getReg();
350 }
351 }
352
353 return 0;
354}
355
356
357/// This function can analyze one/two way branching only and should (mostly) be
358/// called by target independent side.
359/// First entry is always the opcode of the branching instruction, except when
360/// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
361/// BB with only unconditional jump. Subsequent entries depend upon the opcode,
362/// e.g. Jump_c p will have
363/// Cond[0] = Jump_c
364/// Cond[1] = p
365/// HW-loop ENDLOOP:
366/// Cond[0] = ENDLOOP
367/// Cond[1] = MBB
368/// New value jump:
369/// Cond[0] = Hexagon::CMPEQri_f_Jumpnv_t_V4 -- specific opcode
370/// Cond[1] = R
371/// Cond[2] = Imm
372///
373bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
374 MachineBasicBlock *&TBB,
375 MachineBasicBlock *&FBB,
376 SmallVectorImpl<MachineOperand> &Cond,
377 bool AllowModify) const {
378 TBB = nullptr;
379 FBB = nullptr;
380 Cond.clear();
381
382 // If the block has no terminators, it just falls into the block after it.
383 MachineBasicBlock::instr_iterator I = MBB.instr_end();
384 if (I == MBB.instr_begin())
385 return false;
386
387 // A basic block may looks like this:
388 //
389 // [ insn
390 // EH_LABEL
391 // insn
392 // insn
393 // insn
394 // EH_LABEL
395 // insn ]
396 //
397 // It has two succs but does not have a terminator
398 // Don't know how to handle it.
399 do {
400 --I;
401 if (I->isEHLabel())
402 // Don't analyze EH branches.
403 return true;
404 } while (I != MBB.instr_begin());
405
406 I = MBB.instr_end();
407 --I;
408
409 while (I->isDebugValue()) {
410 if (I == MBB.instr_begin())
411 return false;
412 --I;
413 }
414
415 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
416 I->getOperand(0).isMBB();
417 // Delete the J2_jump if it's equivalent to a fall-through.
418 if (AllowModify && JumpToBlock &&
419 MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
420 DEBUG(dbgs()<< "\nErasing the jump to successor block\n";)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs()<< "\nErasing the jump to successor block\n"
;; } } while (0);
421 I->eraseFromParent();
422 I = MBB.instr_end();
423 if (I == MBB.instr_begin())
424 return false;
425 --I;
426 }
427 if (!isUnpredicatedTerminator(*I))
428 return false;
429
430 // Get the last instruction in the block.
431 MachineInstr *LastInst = &*I;
432 MachineInstr *SecondLastInst = nullptr;
433 // Find one more terminator if present.
434 for (;;) {
435 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
436 if (!SecondLastInst)
437 SecondLastInst = &*I;
438 else
439 // This is a third branch.
440 return true;
441 }
442 if (I == MBB.instr_begin())
443 break;
444 --I;
445 }
446
447 int LastOpcode = LastInst->getOpcode();
448 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
449 // If the branch target is not a basic block, it could be a tail call.
450 // (It is, if the target is a function.)
451 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
452 return true;
453 if (SecLastOpcode == Hexagon::J2_jump &&
454 !SecondLastInst->getOperand(0).isMBB())
455 return true;
456
457 bool LastOpcodeHasJMP_c = PredOpcodeHasJMP_c(LastOpcode);
458 bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
459
460 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
461 return true;
462
463 // If there is only one terminator instruction, process it.
464 if (LastInst && !SecondLastInst) {
465 if (LastOpcode == Hexagon::J2_jump) {
466 TBB = LastInst->getOperand(0).getMBB();
467 return false;
468 }
469 if (isEndLoopN(LastOpcode)) {
470 TBB = LastInst->getOperand(0).getMBB();
471 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
472 Cond.push_back(LastInst->getOperand(0));
473 return false;
474 }
475 if (LastOpcodeHasJMP_c) {
476 TBB = LastInst->getOperand(1).getMBB();
477 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
478 Cond.push_back(LastInst->getOperand(0));
479 return false;
480 }
481 // Only supporting rr/ri versions of new-value jumps.
482 if (LastOpcodeHasNVJump && (LastInst->getNumExplicitOperands() == 3)) {
483 TBB = LastInst->getOperand(2).getMBB();
484 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
485 Cond.push_back(LastInst->getOperand(0));
486 Cond.push_back(LastInst->getOperand(1));
487 return false;
488 }
489 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nCant analyze BB#"
<< MBB.getNumber() << " with one jump\n";; } } while
(0)
490 << " with one jump\n";)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nCant analyze BB#"
<< MBB.getNumber() << " with one jump\n";; } } while
(0);
491 // Otherwise, don't know what this is.
492 return true;
493 }
494
495 bool SecLastOpcodeHasJMP_c = PredOpcodeHasJMP_c(SecLastOpcode);
496 bool SecLastOpcodeHasNVJump = isNewValueJump(SecondLastInst);
497 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) {
498 if (!SecondLastInst->getOperand(1).isMBB())
499 return true;
500 TBB = SecondLastInst->getOperand(1).getMBB();
501 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
502 Cond.push_back(SecondLastInst->getOperand(0));
503 FBB = LastInst->getOperand(0).getMBB();
504 return false;
505 }
506
507 // Only supporting rr/ri versions of new-value jumps.
508 if (SecLastOpcodeHasNVJump &&
509 (SecondLastInst->getNumExplicitOperands() == 3) &&
510 (LastOpcode == Hexagon::J2_jump)) {
511 TBB = SecondLastInst->getOperand(2).getMBB();
512 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
513 Cond.push_back(SecondLastInst->getOperand(0));
514 Cond.push_back(SecondLastInst->getOperand(1));
515 FBB = LastInst->getOperand(0).getMBB();
516 return false;
517 }
518
519 // If the block ends with two Hexagon:JMPs, handle it. The second one is not
520 // executed, so remove it.
521 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) {
522 TBB = SecondLastInst->getOperand(0).getMBB();
523 I = LastInst->getIterator();
524 if (AllowModify)
525 I->eraseFromParent();
526 return false;
527 }
528
529 // If the block ends with an ENDLOOP, and J2_jump, handle it.
530 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) {
531 TBB = SecondLastInst->getOperand(0).getMBB();
532 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
533 Cond.push_back(SecondLastInst->getOperand(0));
534 FBB = LastInst->getOperand(0).getMBB();
535 return false;
536 }
537 DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nCant analyze BB#"
<< MBB.getNumber() << " with two jumps";; } } while
(0)
538 << " with two jumps";)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nCant analyze BB#"
<< MBB.getNumber() << " with two jumps";; } } while
(0);
539 // Otherwise, can't handle this.
540 return true;
541}
542
543
544unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
545 DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nRemoving branches out of BB#"
<< MBB.getNumber(); } } while (0);
546 MachineBasicBlock::iterator I = MBB.end();
547 unsigned Count = 0;
548 while (I != MBB.begin()) {
549 --I;
550 if (I->isDebugValue())
551 continue;
552 // Only removing branches from end of MBB.
553 if (!I->isBranch())
554 return Count;
555 if (Count && (I->getOpcode() == Hexagon::J2_jump))
556 llvm_unreachable("Malformed basic block: unconditional branch not last")::llvm::llvm_unreachable_internal("Malformed basic block: unconditional branch not last"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 556);
557 MBB.erase(&MBB.back());
558 I = MBB.end();
559 ++Count;
560 }
561 return Count;
562}
563
564
565unsigned HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,
566 MachineBasicBlock *TBB, MachineBasicBlock *FBB,
567 ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
568 unsigned BOpc = Hexagon::J2_jump;
569 unsigned BccOpc = Hexagon::J2_jumpt;
570 assert(validateBranchCond(Cond) && "Invalid branching condition")((validateBranchCond(Cond) && "Invalid branching condition"
) ? static_cast<void> (0) : __assert_fail ("validateBranchCond(Cond) && \"Invalid branching condition\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 570, __PRETTY_FUNCTION__));
571 assert(TBB && "InsertBranch must not be told to insert a fallthrough")((TBB && "InsertBranch must not be told to insert a fallthrough"
) ? static_cast<void> (0) : __assert_fail ("TBB && \"InsertBranch must not be told to insert a fallthrough\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 571, __PRETTY_FUNCTION__));
572
573 // Check if ReverseBranchCondition has asked to reverse this branch
574 // If we want to reverse the branch an odd number of times, we want
575 // J2_jumpf.
576 if (!Cond.empty() && Cond[0].isImm())
577 BccOpc = Cond[0].getImm();
578
579 if (!FBB) {
580 if (Cond.empty()) {
581 // Due to a bug in TailMerging/CFG Optimization, we need to add a
582 // special case handling of a predicated jump followed by an
583 // unconditional jump. If not, Tail Merging and CFG Optimization go
584 // into an infinite loop.
585 MachineBasicBlock *NewTBB, *NewFBB;
586 SmallVector<MachineOperand, 4> Cond;
587 MachineInstr *Term = MBB.getFirstTerminator();
588 if (Term != MBB.end() && isPredicated(*Term) &&
589 !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) {
590 MachineBasicBlock *NextBB = &*++MBB.getIterator();
591 if (NewTBB == NextBB) {
592 ReverseBranchCondition(Cond);
593 RemoveBranch(MBB);
594 return InsertBranch(MBB, TBB, nullptr, Cond, DL);
595 }
596 }
597 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
598 } else if (isEndLoopN(Cond[0].getImm())) {
599 int EndLoopOp = Cond[0].getImm();
600 assert(Cond[1].isMBB())((Cond[1].isMBB()) ? static_cast<void> (0) : __assert_fail
("Cond[1].isMBB()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 600, __PRETTY_FUNCTION__));
601 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
602 // Check for it, and change the BB target if needed.
603 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
604 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
605 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP")((Loop != 0 && "Inserting an ENDLOOP without a LOOP")
? static_cast<void> (0) : __assert_fail ("Loop != 0 && \"Inserting an ENDLOOP without a LOOP\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 605, __PRETTY_FUNCTION__));
606 Loop->getOperand(0).setMBB(TBB);
607 // Add the ENDLOOP after the finding the LOOP0.
608 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
609 } else if (isNewValueJump(Cond[0].getImm())) {
610 assert((Cond.size() == 3) && "Only supporting rr/ri version of nvjump")(((Cond.size() == 3) && "Only supporting rr/ri version of nvjump"
) ? static_cast<void> (0) : __assert_fail ("(Cond.size() == 3) && \"Only supporting rr/ri version of nvjump\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 610, __PRETTY_FUNCTION__));
611 // New value jump
612 // (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
613 // (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
614 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
615 DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nInserting NVJump for BB#"
<< MBB.getNumber();; } } while (0);
616 if (Cond[2].isReg()) {
617 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
618 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
619 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
620 } else if(Cond[2].isImm()) {
621 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
622 addImm(Cond[2].getImm()).addMBB(TBB);
623 } else
624 llvm_unreachable("Invalid condition for branching")::llvm::llvm_unreachable_internal("Invalid condition for branching"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 624);
625 } else {
626 assert((Cond.size() == 2) && "Malformed cond vector")(((Cond.size() == 2) && "Malformed cond vector") ? static_cast
<void> (0) : __assert_fail ("(Cond.size() == 2) && \"Malformed cond vector\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 626, __PRETTY_FUNCTION__));
627 const MachineOperand &RO = Cond[1];
628 unsigned Flags = getUndefRegState(RO.isUndef());
629 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
630 }
631 return 1;
632 }
633 assert((!Cond.empty()) &&(((!Cond.empty()) && "Cond. cannot be empty when multiple branchings are required"
) ? static_cast<void> (0) : __assert_fail ("(!Cond.empty()) && \"Cond. cannot be empty when multiple branchings are required\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 634, __PRETTY_FUNCTION__))
634 "Cond. cannot be empty when multiple branchings are required")(((!Cond.empty()) && "Cond. cannot be empty when multiple branchings are required"
) ? static_cast<void> (0) : __assert_fail ("(!Cond.empty()) && \"Cond. cannot be empty when multiple branchings are required\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 634, __PRETTY_FUNCTION__));
635 assert((!isNewValueJump(Cond[0].getImm())) &&(((!isNewValueJump(Cond[0].getImm())) && "NV-jump cannot be inserted with another branch"
) ? static_cast<void> (0) : __assert_fail ("(!isNewValueJump(Cond[0].getImm())) && \"NV-jump cannot be inserted with another branch\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 636, __PRETTY_FUNCTION__))
636 "NV-jump cannot be inserted with another branch")(((!isNewValueJump(Cond[0].getImm())) && "NV-jump cannot be inserted with another branch"
) ? static_cast<void> (0) : __assert_fail ("(!isNewValueJump(Cond[0].getImm())) && \"NV-jump cannot be inserted with another branch\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 636, __PRETTY_FUNCTION__));
637 // Special case for hardware loops. The condition is a basic block.
638 if (isEndLoopN(Cond[0].getImm())) {
639 int EndLoopOp = Cond[0].getImm();
640 assert(Cond[1].isMBB())((Cond[1].isMBB()) ? static_cast<void> (0) : __assert_fail
("Cond[1].isMBB()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 640, __PRETTY_FUNCTION__));
641 // Since we're adding an ENDLOOP, there better be a LOOP instruction.
642 // Check for it, and change the BB target if needed.
643 SmallPtrSet<MachineBasicBlock *, 8> VisitedBBs;
644 MachineInstr *Loop = findLoopInstr(TBB, EndLoopOp, VisitedBBs);
645 assert(Loop != 0 && "Inserting an ENDLOOP without a LOOP")((Loop != 0 && "Inserting an ENDLOOP without a LOOP")
? static_cast<void> (0) : __assert_fail ("Loop != 0 && \"Inserting an ENDLOOP without a LOOP\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 645, __PRETTY_FUNCTION__));
646 Loop->getOperand(0).setMBB(TBB);
647 // Add the ENDLOOP after the finding the LOOP0.
648 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
649 } else {
650 const MachineOperand &RO = Cond[1];
651 unsigned Flags = getUndefRegState(RO.isUndef());
652 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
653 }
654 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
655
656 return 2;
657}
658
659
660bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
661 unsigned NumCycles, unsigned ExtraPredCycles,
662 BranchProbability Probability) const {
663 return nonDbgBBSize(&MBB) <= 3;
664}
665
666
667bool HexagonInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB,
668 unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB,
669 unsigned NumFCycles, unsigned ExtraFCycles, BranchProbability Probability)
670 const {
671 return nonDbgBBSize(&TMBB) <= 3 && nonDbgBBSize(&FMBB) <= 3;
672}
673
674
675bool HexagonInstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
676 unsigned NumInstrs, BranchProbability Probability) const {
677 return NumInstrs <= 4;
678}
679
680
681void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
682 MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg,
683 unsigned SrcReg, bool KillSrc) const {
684 auto &HRI = getRegisterInfo();
685 unsigned KillFlag = getKillRegState(KillSrc);
686
687 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
688 auto MIB = BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
689 .addReg(SrcReg, KillFlag);
690 // We could have a R12 = COPY R2, D1<imp-use, kill> instruction.
691 // Transfer the kill flags.
692 for (auto &Op : I->operands())
693 if (Op.isReg() && Op.isKill() && Op.isImplicit() && Op.isUse())
694 MIB.addReg(Op.getReg(), RegState::Kill | RegState::Implicit);
695 return;
696 }
697 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
698 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
699 .addReg(SrcReg, KillFlag);
700 return;
701 }
702 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
703 // Map Pd = Ps to Pd = or(Ps, Ps).
704 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
705 .addReg(SrcReg).addReg(SrcReg, KillFlag);
706 return;
707 }
708 if (Hexagon::CtrRegsRegClass.contains(DestReg) &&
709 Hexagon::IntRegsRegClass.contains(SrcReg)) {
710 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
711 .addReg(SrcReg, KillFlag);
712 return;
713 }
714 if (Hexagon::IntRegsRegClass.contains(DestReg) &&
715 Hexagon::CtrRegsRegClass.contains(SrcReg)) {
716 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
717 .addReg(SrcReg, KillFlag);
718 return;
719 }
720 if (Hexagon::ModRegsRegClass.contains(DestReg) &&
721 Hexagon::IntRegsRegClass.contains(SrcReg)) {
722 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
723 .addReg(SrcReg, KillFlag);
724 return;
725 }
726 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
727 Hexagon::IntRegsRegClass.contains(DestReg)) {
728 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
729 .addReg(SrcReg, KillFlag);
730 return;
731 }
732 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
733 Hexagon::PredRegsRegClass.contains(DestReg)) {
734 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
735 .addReg(SrcReg, KillFlag);
736 return;
737 }
738 if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
739 Hexagon::IntRegsRegClass.contains(DestReg)) {
740 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
741 .addReg(SrcReg, KillFlag);
742 return;
743 }
744 if (Hexagon::VectorRegsRegClass.contains(SrcReg, DestReg)) {
745 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
746 addReg(SrcReg, KillFlag);
747 return;
748 }
749 if (Hexagon::VecDblRegsRegClass.contains(SrcReg, DestReg)) {
750 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
751 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag)
752 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
753 return;
754 }
755 if (Hexagon::VecPredRegsRegClass.contains(SrcReg, DestReg)) {
756 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
757 .addReg(SrcReg)
758 .addReg(SrcReg, KillFlag);
759 return;
760 }
761 if (Hexagon::VecPredRegsRegClass.contains(SrcReg) &&
762 Hexagon::VectorRegsRegClass.contains(DestReg)) {
763 llvm_unreachable("Unimplemented pred to vec")::llvm::llvm_unreachable_internal("Unimplemented pred to vec"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 763);
764 return;
765 }
766 if (Hexagon::VecPredRegsRegClass.contains(DestReg) &&
767 Hexagon::VectorRegsRegClass.contains(SrcReg)) {
768 llvm_unreachable("Unimplemented vec to pred")::llvm::llvm_unreachable_internal("Unimplemented vec to pred"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 768);
769 return;
770 }
771 if (Hexagon::VecPredRegs128BRegClass.contains(SrcReg, DestReg)) {
772 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg);
773 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstHi)
774 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag);
775 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg);
776 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DstLo)
777 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
778 return;
779 }
780
781#ifndef NDEBUG
782 // Show the invalid registers to ease debugging.
783 dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
784 << ": " << PrintReg(DestReg, &HRI)
785 << " = " << PrintReg(SrcReg, &HRI) << '\n';
786#endif
787 llvm_unreachable("Unimplemented")::llvm::llvm_unreachable_internal("Unimplemented", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 787);
788}
789
790
791void HexagonInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
792 MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI,
793 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
794 DebugLoc DL = MBB.findDebugLoc(I);
795 MachineFunction &MF = *MBB.getParent();
796 MachineFrameInfo &MFI = *MF.getFrameInfo();
797 unsigned Align = MFI.getObjectAlignment(FI);
798 unsigned KillFlag = getKillRegState(isKill);
799
800 MachineMemOperand *MMO = MF.getMachineMemOperand(
801 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
802 MFI.getObjectSize(FI), Align);
803
804 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
805 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io))
806 .addFrameIndex(FI).addImm(0)
807 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
808 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
809 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io))
810 .addFrameIndex(FI).addImm(0)
811 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
812 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
813 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
814 .addFrameIndex(FI).addImm(0)
815 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
816 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
817 BuildMI(MBB, I, DL, get(Hexagon::STriw_mod))
818 .addFrameIndex(FI).addImm(0)
819 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
820 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
821 BuildMI(MBB, I, DL, get(Hexagon::STriq_pred_V6_128B))
822 .addFrameIndex(FI).addImm(0)
823 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
824 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
825 BuildMI(MBB, I, DL, get(Hexagon::STriq_pred_V6))
826 .addFrameIndex(FI).addImm(0)
827 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
828 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
829 DEBUG(dbgs() << "++Generating 128B vector spill")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating 128B vector spill"
; } } while (0);
830 BuildMI(MBB, I, DL, get(Hexagon::STriv_pseudo_V6_128B))
831 .addFrameIndex(FI).addImm(0)
832 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
833 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
834 DEBUG(dbgs() << "++Generating vector spill")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating vector spill"
; } } while (0);
835 BuildMI(MBB, I, DL, get(Hexagon::STriv_pseudo_V6))
836 .addFrameIndex(FI).addImm(0)
837 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
838 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
839 DEBUG(dbgs() << "++Generating double vector spill")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating double vector spill"
; } } while (0);
840 BuildMI(MBB, I, DL, get(Hexagon::STrivv_pseudo_V6))
841 .addFrameIndex(FI).addImm(0)
842 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
843 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
844 DEBUG(dbgs() << "++Generating 128B double vector spill")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating 128B double vector spill"
; } } while (0);
845 BuildMI(MBB, I, DL, get(Hexagon::STrivv_pseudo_V6_128B))
846 .addFrameIndex(FI).addImm(0)
847 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
848 } else {
849 llvm_unreachable("Unimplemented")::llvm::llvm_unreachable_internal("Unimplemented", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 849);
850 }
851}
852
853
854void HexagonInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
855 MachineBasicBlock::iterator I, unsigned DestReg, int FI,
856 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const {
857 DebugLoc DL = MBB.findDebugLoc(I);
858 MachineFunction &MF = *MBB.getParent();
859 MachineFrameInfo &MFI = *MF.getFrameInfo();
860 unsigned Align = MFI.getObjectAlignment(FI);
861
862 MachineMemOperand *MMO = MF.getMachineMemOperand(
863 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
864 MFI.getObjectSize(FI), Align);
865
866 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
867 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
868 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
869 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
870 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
871 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
872 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
873 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
874 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
875 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) {
876 BuildMI(MBB, I, DL, get(Hexagon::LDriw_mod), DestReg)
877 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
878 } else if (Hexagon::VecPredRegs128BRegClass.hasSubClassEq(RC)) {
879 BuildMI(MBB, I, DL, get(Hexagon::LDriq_pred_V6_128B), DestReg)
880 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
881 } else if (Hexagon::VecPredRegsRegClass.hasSubClassEq(RC)) {
882 BuildMI(MBB, I, DL, get(Hexagon::LDriq_pred_V6), DestReg)
883 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
884 } else if (Hexagon::VecDblRegs128BRegClass.hasSubClassEq(RC)) {
885 DEBUG(dbgs() << "++Generating 128B double vector restore")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating 128B double vector restore"
; } } while (0);
886 BuildMI(MBB, I, DL, get(Hexagon::LDrivv_pseudo_V6_128B), DestReg)
887 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
888 } else if (Hexagon::VectorRegs128BRegClass.hasSubClassEq(RC)) {
889 DEBUG(dbgs() << "++Generating 128B vector restore")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating 128B vector restore"
; } } while (0);
890 BuildMI(MBB, I, DL, get(Hexagon::LDriv_pseudo_V6_128B), DestReg)
891 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
892 } else if (Hexagon::VectorRegsRegClass.hasSubClassEq(RC)) {
893 DEBUG(dbgs() << "++Generating vector restore")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating vector restore"
; } } while (0);
894 BuildMI(MBB, I, DL, get(Hexagon::LDriv_pseudo_V6), DestReg)
895 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
896 } else if (Hexagon::VecDblRegsRegClass.hasSubClassEq(RC)) {
897 DEBUG(dbgs() << "++Generating double vector restore")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Generating double vector restore"
; } } while (0);
898 BuildMI(MBB, I, DL, get(Hexagon::LDrivv_pseudo_V6), DestReg)
899 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
900 } else {
901 llvm_unreachable("Can't store this register to stack slot")::llvm::llvm_unreachable_internal("Can't store this register to stack slot"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 901);
902 }
903}
904
905
906/// expandPostRAPseudo - This function is called for all pseudo instructions
907/// that remain after register allocation. Many pseudo instructions are
908/// created to help register allocation. This is the place to convert them
909/// into real instructions. The target can edit MI in place, or it can insert
910/// new instructions and erase MI. The function should return true if
911/// anything was changed.
912bool HexagonInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI)
913 const {
914 const HexagonRegisterInfo &HRI = getRegisterInfo();
915 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
916 MachineBasicBlock &MBB = *MI->getParent();
917 DebugLoc DL = MI->getDebugLoc();
918 unsigned Opc = MI->getOpcode();
919 const unsigned VecOffset = 1;
920 bool Is128B = false;
921
922 switch (Opc) {
923 case Hexagon::ALIGNA:
924 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI->getOperand(0).getReg())
925 .addReg(HRI.getFrameRegister())
926 .addImm(-MI->getOperand(1).getImm());
927 MBB.erase(MI);
928 return true;
929 case Hexagon::HEXAGON_V6_vassignp_128B:
930 case Hexagon::HEXAGON_V6_vassignp: {
931 unsigned SrcReg = MI->getOperand(1).getReg();
932 unsigned DstReg = MI->getOperand(0).getReg();
933 if (SrcReg != DstReg)
934 copyPhysReg(MBB, MI, DL, DstReg, SrcReg, MI->getOperand(1).isKill());
935 MBB.erase(MI);
936 return true;
937 }
938 case Hexagon::HEXAGON_V6_lo_128B:
939 case Hexagon::HEXAGON_V6_lo: {
940 unsigned SrcReg = MI->getOperand(1).getReg();
941 unsigned DstReg = MI->getOperand(0).getReg();
942 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
943 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI->getOperand(1).isKill());
944 MBB.erase(MI);
945 MRI.clearKillFlags(SrcSubLo);
946 return true;
947 }
948 case Hexagon::HEXAGON_V6_hi_128B:
949 case Hexagon::HEXAGON_V6_hi: {
950 unsigned SrcReg = MI->getOperand(1).getReg();
951 unsigned DstReg = MI->getOperand(0).getReg();
952 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
953 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI->getOperand(1).isKill());
954 MBB.erase(MI);
955 MRI.clearKillFlags(SrcSubHi);
956 return true;
957 }
958 case Hexagon::STrivv_indexed_128B:
959 Is128B = true;
960 case Hexagon::STrivv_indexed: {
961 unsigned SrcReg = MI->getOperand(2).getReg();
962 unsigned SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::subreg_hireg);
963 unsigned SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::subreg_loreg);
964 unsigned NewOpcd = Is128B ? Hexagon::V6_vS32b_ai_128B
965 : Hexagon::V6_vS32b_ai;
966 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
967 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpcd))
968 .addOperand(MI->getOperand(0))
969 .addImm(MI->getOperand(1).getImm())
970 .addReg(SrcSubLo)
971 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
972 MI1New->getOperand(0).setIsKill(false);
973 BuildMI(MBB, MI, DL, get(NewOpcd))
974 .addOperand(MI->getOperand(0))
975 // The Vectors are indexed in multiples of vector size.
976 .addImm(MI->getOperand(1).getImm()+Offset)
977 .addReg(SrcSubHi)
978 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
979 MBB.erase(MI);
980 return true;
981 }
982 case Hexagon::LDrivv_pseudo_V6_128B:
983 case Hexagon::LDrivv_indexed_128B:
984 Is128B = true;
985 case Hexagon::LDrivv_pseudo_V6:
986 case Hexagon::LDrivv_indexed: {
987 unsigned NewOpcd = Is128B ? Hexagon::V6_vL32b_ai_128B
988 : Hexagon::V6_vL32b_ai;
989 unsigned DstReg = MI->getOperand(0).getReg();
990 unsigned Offset = Is128B ? VecOffset << 7 : VecOffset << 6;
991 MachineInstr *MI1New =
992 BuildMI(MBB, MI, DL, get(NewOpcd),
993 HRI.getSubReg(DstReg, Hexagon::subreg_loreg))
994 .addOperand(MI->getOperand(1))
995 .addImm(MI->getOperand(2).getImm());
996 MI1New->getOperand(1).setIsKill(false);
997 BuildMI(MBB, MI, DL, get(NewOpcd),
998 HRI.getSubReg(DstReg, Hexagon::subreg_hireg))
999 .addOperand(MI->getOperand(1))
1000 // The Vectors are indexed in multiples of vector size.
1001 .addImm(MI->getOperand(2).getImm() + Offset)
1002 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1003 MBB.erase(MI);
1004 return true;
1005 }
1006 case Hexagon::LDriv_pseudo_V6_128B:
1007 Is128B = true;
1008 case Hexagon::LDriv_pseudo_V6: {
1009 unsigned DstReg = MI->getOperand(0).getReg();
1010 unsigned NewOpc = Is128B ? Hexagon::V6_vL32b_ai_128B
1011 : Hexagon::V6_vL32b_ai;
1012 int32_t Off = MI->getOperand(2).getImm();
1013 int32_t Idx = Off;
1014 BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
1015 .addOperand(MI->getOperand(1))
1016 .addImm(Idx)
1017 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1018 MBB.erase(MI);
1019 return true;
1020 }
1021 case Hexagon::STriv_pseudo_V6_128B:
1022 Is128B = true;
1023 case Hexagon::STriv_pseudo_V6: {
1024 unsigned NewOpc = Is128B ? Hexagon::V6_vS32b_ai_128B
1025 : Hexagon::V6_vS32b_ai;
1026 int32_t Off = MI->getOperand(1).getImm();
1027 int32_t Idx = Is128B ? (Off >> 7) : (Off >> 6);
1028 BuildMI(MBB, MI, DL, get(NewOpc))
1029 .addOperand(MI->getOperand(0))
1030 .addImm(Idx)
1031 .addOperand(MI->getOperand(2))
1032 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1033 MBB.erase(MI);
1034 return true;
1035 }
1036 case Hexagon::TFR_PdTrue: {
1037 unsigned Reg = MI->getOperand(0).getReg();
1038 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1039 .addReg(Reg, RegState::Undef)
1040 .addReg(Reg, RegState::Undef);
1041 MBB.erase(MI);
1042 return true;
1043 }
1044 case Hexagon::TFR_PdFalse: {
1045 unsigned Reg = MI->getOperand(0).getReg();
1046 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1047 .addReg(Reg, RegState::Undef)
1048 .addReg(Reg, RegState::Undef);
1049 MBB.erase(MI);
1050 return true;
1051 }
1052 case Hexagon::VMULW: {
1053 // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
1054 unsigned DstReg = MI->getOperand(0).getReg();
1055 unsigned Src1Reg = MI->getOperand(1).getReg();
1056 unsigned Src2Reg = MI->getOperand(2).getReg();
1057 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
1058 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
1059 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
1060 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
1061 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
1062 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
1063 .addReg(Src2SubHi);
1064 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_mpyi),
1065 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
1066 .addReg(Src2SubLo);
1067 MBB.erase(MI);
1068 MRI.clearKillFlags(Src1SubHi);
1069 MRI.clearKillFlags(Src1SubLo);
1070 MRI.clearKillFlags(Src2SubHi);
1071 MRI.clearKillFlags(Src2SubLo);
1072 return true;
1073 }
1074 case Hexagon::VMULW_ACC: {
1075 // Expand 64-bit vector multiply with addition into 2 scalar multiplies.
1076 unsigned DstReg = MI->getOperand(0).getReg();
1077 unsigned Src1Reg = MI->getOperand(1).getReg();
1078 unsigned Src2Reg = MI->getOperand(2).getReg();
1079 unsigned Src3Reg = MI->getOperand(3).getReg();
1080 unsigned Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::subreg_hireg);
1081 unsigned Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::subreg_loreg);
1082 unsigned Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::subreg_hireg);
1083 unsigned Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::subreg_loreg);
1084 unsigned Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::subreg_hireg);
1085 unsigned Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::subreg_loreg);
1086 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
1087 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(Src1SubHi)
1088 .addReg(Src2SubHi).addReg(Src3SubHi);
1089 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::M2_maci),
1090 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(Src1SubLo)
1091 .addReg(Src2SubLo).addReg(Src3SubLo);
1092 MBB.erase(MI);
1093 MRI.clearKillFlags(Src1SubHi);
1094 MRI.clearKillFlags(Src1SubLo);
1095 MRI.clearKillFlags(Src2SubHi);
1096 MRI.clearKillFlags(Src2SubLo);
1097 MRI.clearKillFlags(Src3SubHi);
1098 MRI.clearKillFlags(Src3SubLo);
1099 return true;
1100 }
1101 case Hexagon::Insert4: {
1102 unsigned DstReg = MI->getOperand(0).getReg();
1103 unsigned Src1Reg = MI->getOperand(1).getReg();
1104 unsigned Src2Reg = MI->getOperand(2).getReg();
1105 unsigned Src3Reg = MI->getOperand(3).getReg();
1106 unsigned Src4Reg = MI->getOperand(4).getReg();
1107 unsigned Src1RegIsKill = getKillRegState(MI->getOperand(1).isKill());
1108 unsigned Src2RegIsKill = getKillRegState(MI->getOperand(2).isKill());
1109 unsigned Src3RegIsKill = getKillRegState(MI->getOperand(3).isKill());
1110 unsigned Src4RegIsKill = getKillRegState(MI->getOperand(4).isKill());
1111 unsigned DstSubHi = HRI.getSubReg(DstReg, Hexagon::subreg_hireg);
1112 unsigned DstSubLo = HRI.getSubReg(DstReg, Hexagon::subreg_loreg);
1113 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
1114 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(DstSubLo)
1115 .addReg(Src1Reg, Src1RegIsKill).addImm(16).addImm(0);
1116 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
1117 HRI.getSubReg(DstReg, Hexagon::subreg_loreg)).addReg(DstSubLo)
1118 .addReg(Src2Reg, Src2RegIsKill).addImm(16).addImm(16);
1119 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
1120 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(DstSubHi)
1121 .addReg(Src3Reg, Src3RegIsKill).addImm(16).addImm(0);
1122 BuildMI(MBB, MI, MI->getDebugLoc(), get(Hexagon::S2_insert),
1123 HRI.getSubReg(DstReg, Hexagon::subreg_hireg)).addReg(DstSubHi)
1124 .addReg(Src4Reg, Src4RegIsKill).addImm(16).addImm(16);
1125 MBB.erase(MI);
1126 MRI.clearKillFlags(DstReg);
1127 MRI.clearKillFlags(DstSubHi);
1128 MRI.clearKillFlags(DstSubLo);
1129 return true;
1130 }
1131 case Hexagon::MUX64_rr: {
1132 const MachineOperand &Op0 = MI->getOperand(0);
1133 const MachineOperand &Op1 = MI->getOperand(1);
1134 const MachineOperand &Op2 = MI->getOperand(2);
1135 const MachineOperand &Op3 = MI->getOperand(3);
1136 unsigned Rd = Op0.getReg();
1137 unsigned Pu = Op1.getReg();
1138 unsigned Rs = Op2.getReg();
1139 unsigned Rt = Op3.getReg();
1140 DebugLoc DL = MI->getDebugLoc();
1141 unsigned K1 = getKillRegState(Op1.isKill());
1142 unsigned K2 = getKillRegState(Op2.isKill());
1143 unsigned K3 = getKillRegState(Op3.isKill());
1144 if (Rd != Rs)
1145 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1146 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1147 .addReg(Rs, K2);
1148 if (Rd != Rt)
1149 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1150 .addReg(Pu, K1)
1151 .addReg(Rt, K3);
1152 MBB.erase(MI);
1153 return true;
1154 }
1155 case Hexagon::TCRETURNi:
1156 MI->setDesc(get(Hexagon::J2_jump));
1157 return true;
1158 case Hexagon::TCRETURNr:
1159 MI->setDesc(get(Hexagon::J2_jumpr));
1160 return true;
1161 case Hexagon::TFRI_f:
1162 case Hexagon::TFRI_cPt_f:
1163 case Hexagon::TFRI_cNotPt_f: {
1164 unsigned Opx = (Opc == Hexagon::TFRI_f) ? 1 : 2;
1165 APFloat FVal = MI->getOperand(Opx).getFPImm()->getValueAPF();
1166 APInt IVal = FVal.bitcastToAPInt();
1167 MI->RemoveOperand(Opx);
1168 unsigned NewOpc = (Opc == Hexagon::TFRI_f) ? Hexagon::A2_tfrsi :
1169 (Opc == Hexagon::TFRI_cPt_f) ? Hexagon::C2_cmoveit :
1170 Hexagon::C2_cmoveif;
1171 MI->setDesc(get(NewOpc));
1172 MI->addOperand(MachineOperand::CreateImm(IVal.getZExtValue()));
1173 return true;
1174 }
1175 }
1176
1177 return false;
1178}
1179
1180
1181// We indicate that we want to reverse the branch by
1182// inserting the reversed branching opcode.
1183bool HexagonInstrInfo::ReverseBranchCondition(
1184 SmallVectorImpl<MachineOperand> &Cond) const {
1185 if (Cond.empty())
1186 return true;
1187 assert(Cond[0].isImm() && "First entry in the cond vector not imm-val")((Cond[0].isImm() && "First entry in the cond vector not imm-val"
) ? static_cast<void> (0) : __assert_fail ("Cond[0].isImm() && \"First entry in the cond vector not imm-val\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 1187, __PRETTY_FUNCTION__));
1188 unsigned opcode = Cond[0].getImm();
1189 //unsigned temp;
1190 assert(get(opcode).isBranch() && "Should be a branching condition.")((get(opcode).isBranch() && "Should be a branching condition."
) ? static_cast<void> (0) : __assert_fail ("get(opcode).isBranch() && \"Should be a branching condition.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 1190, __PRETTY_FUNCTION__));
1191 if (isEndLoopN(opcode))
1192 return true;
1193 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode);
1194 Cond[0].setImm(NewOpcode);
1195 return false;
1196}
1197
1198
1199void HexagonInstrInfo::insertNoop(MachineBasicBlock &MBB,
1200 MachineBasicBlock::iterator MI) const {
1201 DebugLoc DL;
1202 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop));
1203}
1204
1205
1206// Returns true if an instruction is predicated irrespective of the predicate
1207// sense. For example, all of the following will return true.
1208// if (p0) R1 = add(R2, R3)
1209// if (!p0) R1 = add(R2, R3)
1210// if (p0.new) R1 = add(R2, R3)
1211// if (!p0.new) R1 = add(R2, R3)
1212// Note: New-value stores are not included here as in the current
1213// implementation, we don't need to check their predicate sense.
1214bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const {
1215 const uint64_t F = MI.getDesc().TSFlags;
1216 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
1217}
1218
1219bool HexagonInstrInfo::PredicateInstruction(
1220 MachineInstr &MI, ArrayRef<MachineOperand> Cond) const {
1221 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) ||
1222 isEndLoopN(Cond[0].getImm())) {
1223 DEBUG(dbgs() << "\nCannot predicate:"; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nCannot predicate:"
; MI.dump();; } } while (0);
1224 return false;
1225 }
1226 int Opc = MI.getOpcode();
1227 assert (isPredicable(MI) && "Expected predicable instruction")((isPredicable(MI) && "Expected predicable instruction"
) ? static_cast<void> (0) : __assert_fail ("isPredicable(MI) && \"Expected predicable instruction\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 1227, __PRETTY_FUNCTION__));
1228 bool invertJump = predOpcodeHasNot(Cond);
1229
1230 // We have to predicate MI "in place", i.e. after this function returns,
1231 // MI will need to be transformed into a predicated form. To avoid com-
1232 // plicated manipulations with the operands (handling tied operands,
1233 // etc.), build a new temporary instruction, then overwrite MI with it.
1234
1235 MachineBasicBlock &B = *MI.getParent();
1236 DebugLoc DL = MI.getDebugLoc();
1237 unsigned PredOpc = getCondOpcode(Opc, invertJump);
1238 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
1239 unsigned NOp = 0, NumOps = MI.getNumOperands();
1240 while (NOp < NumOps) {
1241 MachineOperand &Op = MI.getOperand(NOp);
1242 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1243 break;
1244 T.addOperand(Op);
1245 NOp++;
1246 }
1247
1248 unsigned PredReg, PredRegPos, PredRegFlags;
1249 bool GotPredReg = getPredReg(Cond, PredReg, PredRegPos, PredRegFlags);
1250 (void)GotPredReg;
1251 assert(GotPredReg)((GotPredReg) ? static_cast<void> (0) : __assert_fail (
"GotPredReg", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 1251, __PRETTY_FUNCTION__));
1252 T.addReg(PredReg, PredRegFlags);
1253 while (NOp < NumOps)
1254 T.addOperand(MI.getOperand(NOp++));
1255
1256 MI.setDesc(get(PredOpc));
1257 while (unsigned n = MI.getNumOperands())
1258 MI.RemoveOperand(n-1);
1259 for (unsigned i = 0, n = T->getNumOperands(); i < n; ++i)
1260 MI.addOperand(T->getOperand(i));
1261
1262 MachineBasicBlock::instr_iterator TI = T->getIterator();
1263 B.erase(TI);
1264
1265 MachineRegisterInfo &MRI = B.getParent()->getRegInfo();
1266 MRI.clearKillFlags(PredReg);
1267 return true;
1268}
1269
1270
1271bool HexagonInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1272 ArrayRef<MachineOperand> Pred2) const {
1273 // TODO: Fix this
1274 return false;
1275}
1276
1277bool HexagonInstrInfo::DefinesPredicate(
1278 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
1279 auto &HRI = getRegisterInfo();
1280 for (unsigned oper = 0; oper < MI.getNumOperands(); ++oper) {
1281 MachineOperand MO = MI.getOperand(oper);
1282 if (MO.isReg() && MO.isDef()) {
1283 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1284 if (RC == &Hexagon::PredRegsRegClass) {
1285 Pred.push_back(MO);
1286 return true;
1287 }
1288 }
1289 }
1290 return false;
1291}
1292
1293bool HexagonInstrInfo::isPredicable(MachineInstr &MI) const {
1294 bool isPred = MI.getDesc().isPredicable();
1295
1296 if (!isPred)
1
Assuming 'isPred' is not equal to 0
→
2
←
Taking false branch
→
1297 return false;
1298
1299 const int Opc = MI.getOpcode();
1300 int NumOperands = MI.getNumOperands();
1301
1302 // Keep a flag for upto 4 operands in the instructions, to indicate if
1303 // that operand has been constant extended.
1304 bool OpCExtended[4];
1305 if (NumOperands > 4)
3
←
Assuming 'NumOperands' is <= 4
→
4
←
Taking false branch
→
1306 NumOperands = 4;
1307
1308 for (int i = 0; i < NumOperands; i++)
5
←
Assuming 'i' is < 'NumOperands'
→
6
←
Loop condition is true. Entering loop body
→
7
←
Assuming 'i' is < 'NumOperands'
→
8
←
Loop condition is true. Entering loop body
→
9
←
Assuming 'i' is >= 'NumOperands'
→
10
←
Loop condition is false. Execution continues on line 1311
→
1309 OpCExtended[i] = (isOperandExtended(&MI, i) && isConstExtended(&MI));
1310
1311 switch(Opc) {
11
←
Control jumps to 'case S4_storeiri_io:' at line 1361
→
1312 case Hexagon::A2_tfrsi:
1313 return (isOperandExtended(&MI, 1) && isConstExtended(&MI)) ||
1314 isInt<12>(MI.getOperand(1).getImm());
1315
1316 case Hexagon::S2_storerd_io:
1317 return isShiftedUInt<6,3>(MI.getOperand(1).getImm());
1318
1319 case Hexagon::S2_storeri_io:
1320 case Hexagon::S2_storerinew_io:
1321 return isShiftedUInt<6,2>(MI.getOperand(1).getImm());
1322
1323 case Hexagon::S2_storerh_io:
1324 case Hexagon::S2_storerhnew_io:
1325 return isShiftedUInt<6,1>(MI.getOperand(1).getImm());
1326
1327 case Hexagon::S2_storerb_io:
1328 case Hexagon::S2_storerbnew_io:
1329 return isUInt<6>(MI.getOperand(1).getImm());
1330
1331 case Hexagon::L2_loadrd_io:
1332 return isShiftedUInt<6,3>(MI.getOperand(2).getImm());
1333
1334 case Hexagon::L2_loadri_io:
1335 return isShiftedUInt<6,2>(MI.getOperand(2).getImm());
1336
1337 case Hexagon::L2_loadrh_io:
1338 case Hexagon::L2_loadruh_io:
1339 return isShiftedUInt<6,1>(MI.getOperand(2).getImm());
1340
1341 case Hexagon::L2_loadrb_io:
1342 case Hexagon::L2_loadrub_io:
1343 return isUInt<6>(MI.getOperand(2).getImm());
1344
1345 case Hexagon::L2_loadrd_pi:
1346 return isShiftedInt<4,3>(MI.getOperand(3).getImm());
1347
1348 case Hexagon::L2_loadri_pi:
1349 return isShiftedInt<4,2>(MI.getOperand(3).getImm());
1350
1351 case Hexagon::L2_loadrh_pi:
1352 case Hexagon::L2_loadruh_pi:
1353 return isShiftedInt<4,1>(MI.getOperand(3).getImm());
1354
1355 case Hexagon::L2_loadrb_pi:
1356 case Hexagon::L2_loadrub_pi:
1357 return isInt<4>(MI.getOperand(3).getImm());
1358
1359 case Hexagon::S4_storeirb_io:
1360 case Hexagon::S4_storeirh_io:
1361 case Hexagon::S4_storeiri_io:
1362 return (OpCExtended[1] || isUInt<6>(MI.getOperand(1).getImm())) &&
1363 (OpCExtended[2] || isInt<6>(MI.getOperand(2).getImm()));
12
←
Branch condition evaluates to a garbage value
1364
1365 case Hexagon::A2_addi:
1366 return isInt<8>(MI.getOperand(2).getImm());
1367
1368 case Hexagon::A2_aslh:
1369 case Hexagon::A2_asrh:
1370 case Hexagon::A2_sxtb:
1371 case Hexagon::A2_sxth:
1372 case Hexagon::A2_zxtb:
1373 case Hexagon::A2_zxth:
1374 return true;
1375 }
1376
1377 return true;
1378}
1379
1380
1381bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1382 const MachineBasicBlock *MBB, const MachineFunction &MF) const {
1383 // Debug info is never a scheduling boundary. It's necessary to be explicit
1384 // due to the special treatment of IT instructions below, otherwise a
1385 // dbg_value followed by an IT will result in the IT instruction being
1386 // considered a scheduling hazard, which is wrong. It should be the actual
1387 // instruction preceding the dbg_value instruction(s), just like it is
1388 // when debug info is not present.
1389 if (MI->isDebugValue())
1390 return false;
1391
1392 // Throwing call is a boundary.
1393 if (MI->isCall()) {
1394 // If any of the block's successors is a landing pad, this could be a
1395 // throwing call.
1396 for (auto I : MBB->successors())
1397 if (I->isEHPad())
1398 return true;
1399 }
1400
1401 // Don't mess around with no return calls.
1402 if (MI->getOpcode() == Hexagon::CALLv3nr)
1403 return true;
1404
1405 // Terminators and labels can't be scheduled around.
1406 if (MI->getDesc().isTerminator() || MI->isPosition())
1407 return true;
1408
1409 if (MI->isInlineAsm() && !ScheduleInlineAsm)
1410 return true;
1411
1412 return false;
1413}
1414
1415
1416/// Measure the specified inline asm to determine an approximation of its
1417/// length.
1418/// Comments (which run till the next SeparatorString or newline) do not
1419/// count as an instruction.
1420/// Any other non-whitespace text is considered an instruction, with
1421/// multiple instructions separated by SeparatorString or newlines.
1422/// Variable-length instructions are not handled here; this function
1423/// may be overloaded in the target code to do that.
1424/// Hexagon counts the number of ##'s and adjust for that many
1425/// constant exenders.
1426unsigned HexagonInstrInfo::getInlineAsmLength(const char *Str,
1427 const MCAsmInfo &MAI) const {
1428 StringRef AStr(Str);
1429 // Count the number of instructions in the asm.
1430 bool atInsnStart = true;
1431 unsigned Length = 0;
1432 for (; *Str; ++Str) {
1433 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
1434 strlen(MAI.getSeparatorString())) == 0)
1435 atInsnStart = true;
1436 if (atInsnStart && !std::isspace(static_cast<unsigned char>(*Str))) {
1437 Length += MAI.getMaxInstLength();
1438 atInsnStart = false;
1439 }
1440 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
1441 strlen(MAI.getCommentString())) == 0)
1442 atInsnStart = false;
1443 }
1444
1445 // Add to size number of constant extenders seen * 4.
1446 StringRef Occ("##");
1447 Length += AStr.count(Occ)*4;
1448 return Length;
1449}
1450
1451
1452ScheduleHazardRecognizer*
1453HexagonInstrInfo::CreateTargetPostRAHazardRecognizer(
1454 const InstrItineraryData *II, const ScheduleDAG *DAG) const {
1455 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
1456}
1457
1458
1459/// \brief For a comparison instruction, return the source registers in
1460/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1461/// compares against in CmpValue. Return true if the comparison instruction
1462/// can be analyzed.
1463bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
1464 unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const {
1465 unsigned Opc = MI->getOpcode();
1466
1467 // Set mask and the first source register.
1468 switch (Opc) {
1469 case Hexagon::C2_cmpeq:
1470 case Hexagon::C2_cmpeqp:
1471 case Hexagon::C2_cmpgt:
1472 case Hexagon::C2_cmpgtp:
1473 case Hexagon::C2_cmpgtu:
1474 case Hexagon::C2_cmpgtup:
1475 case Hexagon::C4_cmpneq:
1476 case Hexagon::C4_cmplte:
1477 case Hexagon::C4_cmplteu:
1478 case Hexagon::C2_cmpeqi:
1479 case Hexagon::C2_cmpgti:
1480 case Hexagon::C2_cmpgtui:
1481 case Hexagon::C4_cmpneqi:
1482 case Hexagon::C4_cmplteui:
1483 case Hexagon::C4_cmpltei:
1484 SrcReg = MI->getOperand(1).getReg();
1485 Mask = ~0;
1486 break;
1487 case Hexagon::A4_cmpbeq:
1488 case Hexagon::A4_cmpbgt:
1489 case Hexagon::A4_cmpbgtu:
1490 case Hexagon::A4_cmpbeqi:
1491 case Hexagon::A4_cmpbgti:
1492 case Hexagon::A4_cmpbgtui:
1493 SrcReg = MI->getOperand(1).getReg();
1494 Mask = 0xFF;
1495 break;
1496 case Hexagon::A4_cmpheq:
1497 case Hexagon::A4_cmphgt:
1498 case Hexagon::A4_cmphgtu:
1499 case Hexagon::A4_cmpheqi:
1500 case Hexagon::A4_cmphgti:
1501 case Hexagon::A4_cmphgtui:
1502 SrcReg = MI->getOperand(1).getReg();
1503 Mask = 0xFFFF;
1504 break;
1505 }
1506
1507 // Set the value/second source register.
1508 switch (Opc) {
1509 case Hexagon::C2_cmpeq:
1510 case Hexagon::C2_cmpeqp:
1511 case Hexagon::C2_cmpgt:
1512 case Hexagon::C2_cmpgtp:
1513 case Hexagon::C2_cmpgtu:
1514 case Hexagon::C2_cmpgtup:
1515 case Hexagon::A4_cmpbeq:
1516 case Hexagon::A4_cmpbgt:
1517 case Hexagon::A4_cmpbgtu:
1518 case Hexagon::A4_cmpheq:
1519 case Hexagon::A4_cmphgt:
1520 case Hexagon::A4_cmphgtu:
1521 case Hexagon::C4_cmpneq:
1522 case Hexagon::C4_cmplte:
1523 case Hexagon::C4_cmplteu:
1524 SrcReg2 = MI->getOperand(2).getReg();
1525 return true;
1526
1527 case Hexagon::C2_cmpeqi:
1528 case Hexagon::C2_cmpgtui:
1529 case Hexagon::C2_cmpgti:
1530 case Hexagon::C4_cmpneqi:
1531 case Hexagon::C4_cmplteui:
1532 case Hexagon::C4_cmpltei:
1533 case Hexagon::A4_cmpbeqi:
1534 case Hexagon::A4_cmpbgti:
1535 case Hexagon::A4_cmpbgtui:
1536 case Hexagon::A4_cmpheqi:
1537 case Hexagon::A4_cmphgti:
1538 case Hexagon::A4_cmphgtui:
1539 SrcReg2 = 0;
1540 Value = MI->getOperand(2).getImm();
1541 return true;
1542 }
1543
1544 return false;
1545}
1546
1547
1548unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
1549 const MachineInstr *MI, unsigned *PredCost) const {
1550 return getInstrTimingClassLatency(ItinData, MI);
1551}
1552
1553
1554DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
1555 const TargetSubtargetInfo &STI) const {
1556 const InstrItineraryData *II = STI.getInstrItineraryData();
1557 return static_cast<const HexagonSubtarget&>(STI).createDFAPacketizer(II);
1558}
1559
1560
1561// Inspired by this pair:
1562// %R13<def> = L2_loadri_io %R29, 136; mem:LD4[FixedStack0]
1563// S2_storeri_io %R29, 132, %R1<kill>; flags: mem:ST4[FixedStack1]
1564// Currently AA considers the addresses in these instructions to be aliasing.
1565bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1566 MachineInstr *MIb, AliasAnalysis *AA) const {
1567 int OffsetA = 0, OffsetB = 0;
1568 unsigned SizeA = 0, SizeB = 0;
1569
1570 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
1571 MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
1572 return false;
1573
1574 // Instructions that are pure loads, not loads and stores like memops are not
1575 // dependent.
1576 if (MIa->mayLoad() && !isMemOp(MIa) && MIb->mayLoad() && !isMemOp(MIb))
1577 return true;
1578
1579 // Get base, offset, and access size in MIa.
1580 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
1581 if (!BaseRegA || !SizeA)
1582 return false;
1583
1584 // Get base, offset, and access size in MIb.
1585 unsigned BaseRegB = getBaseAndOffset(MIb, OffsetB, SizeB);
1586 if (!BaseRegB || !SizeB)
1587 return false;
1588
1589 if (BaseRegA != BaseRegB)
1590 return false;
1591
1592 // This is a mem access with the same base register and known offsets from it.
1593 // Reason about it.
1594 if (OffsetA > OffsetB) {
1595 uint64_t offDiff = (uint64_t)((int64_t)OffsetA - (int64_t)OffsetB);
1596 return (SizeB <= offDiff);
1597 } else if (OffsetA < OffsetB) {
1598 uint64_t offDiff = (uint64_t)((int64_t)OffsetB - (int64_t)OffsetA);
1599 return (SizeA <= offDiff);
1600 }
1601
1602 return false;
1603}
1604
1605
1606unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
1607 MachineRegisterInfo &MRI = MF->getRegInfo();
1608 const TargetRegisterClass *TRC;
1609 if (VT == MVT::i1) {
1610 TRC = &Hexagon::PredRegsRegClass;
1611 } else if (VT == MVT::i32 || VT == MVT::f32) {
1612 TRC = &Hexagon::IntRegsRegClass;
1613 } else if (VT == MVT::i64 || VT == MVT::f64) {
1614 TRC = &Hexagon::DoubleRegsRegClass;
1615 } else {
1616 llvm_unreachable("Cannot handle this register class")::llvm::llvm_unreachable_internal("Cannot handle this register class"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 1616);
1617 }
1618
1619 unsigned NewReg = MRI.createVirtualRegister(TRC);
1620 return NewReg;
1621}
1622
1623
1624bool HexagonInstrInfo::isAbsoluteSet(const MachineInstr* MI) const {
1625 return (getAddrMode(MI) == HexagonII::AbsoluteSet);
1626}
1627
1628
1629bool HexagonInstrInfo::isAccumulator(const MachineInstr *MI) const {
1630 const uint64_t F = MI->getDesc().TSFlags;
1631 return((F >> HexagonII::AccumulatorPos) & HexagonII::AccumulatorMask);
1632}
1633
1634
1635bool HexagonInstrInfo::isComplex(const MachineInstr *MI) const {
1636 const MachineFunction *MF = MI->getParent()->getParent();
1637 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1638 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1639
1640 if (!(isTC1(MI))
1641 && !(QII->isTC2Early(MI))
1642 && !(MI->getDesc().mayLoad())
1643 && !(MI->getDesc().mayStore())
1644 && (MI->getDesc().getOpcode() != Hexagon::S2_allocframe)
1645 && (MI->getDesc().getOpcode() != Hexagon::L2_deallocframe)
1646 && !(QII->isMemOp(MI))
1647 && !(MI->isBranch())
1648 && !(MI->isReturn())
1649 && !MI->isCall())
1650 return true;
1651
1652 return false;
1653}
1654
1655
1656// Return true if the instruction is a compund branch instruction.
1657bool HexagonInstrInfo::isCompoundBranchInstr(const MachineInstr *MI) const {
1658 return (getType(MI) == HexagonII::TypeCOMPOUND && MI->isBranch());
1659}
1660
1661
1662bool HexagonInstrInfo::isCondInst(const MachineInstr *MI) const {
1663 return (MI->isBranch() && isPredicated(*MI)) ||
1664 isConditionalTransfer(MI) ||
1665 isConditionalALU32(MI) ||
1666 isConditionalLoad(MI) ||
1667 // Predicated stores which don't have a .new on any operands.
1668 (MI->mayStore() && isPredicated(*MI) && !isNewValueStore(MI) &&
1669 !isPredicatedNew(*MI));
1670}
1671
1672
1673bool HexagonInstrInfo::isConditionalALU32(const MachineInstr* MI) const {
1674 switch (MI->getOpcode()) {
1675 case Hexagon::A2_paddf:
1676 case Hexagon::A2_paddfnew:
1677 case Hexagon::A2_paddif:
1678 case Hexagon::A2_paddifnew:
1679 case Hexagon::A2_paddit:
1680 case Hexagon::A2_padditnew:
1681 case Hexagon::A2_paddt:
1682 case Hexagon::A2_paddtnew:
1683 case Hexagon::A2_pandf:
1684 case Hexagon::A2_pandfnew:
1685 case Hexagon::A2_pandt:
1686 case Hexagon::A2_pandtnew:
1687 case Hexagon::A2_porf:
1688 case Hexagon::A2_porfnew:
1689 case Hexagon::A2_port:
1690 case Hexagon::A2_portnew:
1691 case Hexagon::A2_psubf:
1692 case Hexagon::A2_psubfnew:
1693 case Hexagon::A2_psubt:
1694 case Hexagon::A2_psubtnew:
1695 case Hexagon::A2_pxorf:
1696 case Hexagon::A2_pxorfnew:
1697 case Hexagon::A2_pxort:
1698 case Hexagon::A2_pxortnew:
1699 case Hexagon::A4_paslhf:
1700 case Hexagon::A4_paslhfnew:
1701 case Hexagon::A4_paslht:
1702 case Hexagon::A4_paslhtnew:
1703 case Hexagon::A4_pasrhf:
1704 case Hexagon::A4_pasrhfnew:
1705 case Hexagon::A4_pasrht:
1706 case Hexagon::A4_pasrhtnew:
1707 case Hexagon::A4_psxtbf:
1708 case Hexagon::A4_psxtbfnew:
1709 case Hexagon::A4_psxtbt:
1710 case Hexagon::A4_psxtbtnew:
1711 case Hexagon::A4_psxthf:
1712 case Hexagon::A4_psxthfnew:
1713 case Hexagon::A4_psxtht:
1714 case Hexagon::A4_psxthtnew:
1715 case Hexagon::A4_pzxtbf:
1716 case Hexagon::A4_pzxtbfnew:
1717 case Hexagon::A4_pzxtbt:
1718 case Hexagon::A4_pzxtbtnew:
1719 case Hexagon::A4_pzxthf:
1720 case Hexagon::A4_pzxthfnew:
1721 case Hexagon::A4_pzxtht:
1722 case Hexagon::A4_pzxthtnew:
1723 case Hexagon::C2_ccombinewf:
1724 case Hexagon::C2_ccombinewt:
1725 return true;
1726 }
1727 return false;
1728}
1729
1730
1731// FIXME - Function name and it's functionality don't match.
1732// It should be renamed to hasPredNewOpcode()
1733bool HexagonInstrInfo::isConditionalLoad(const MachineInstr* MI) const {
1734 if (!MI->getDesc().mayLoad() || !isPredicated(*MI))
1735 return false;
1736
1737 int PNewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
1738 // Instruction with valid predicated-new opcode can be promoted to .new.
1739 return PNewOpcode >= 0;
1740}
1741
1742
1743// Returns true if an instruction is a conditional store.
1744//
1745// Note: It doesn't include conditional new-value stores as they can't be
1746// converted to .new predicate.
1747bool HexagonInstrInfo::isConditionalStore(const MachineInstr* MI) const {
1748 switch (MI->getOpcode()) {
1749 default: return false;
1750 case Hexagon::S4_storeirbt_io:
1751 case Hexagon::S4_storeirbf_io:
1752 case Hexagon::S4_pstorerbt_rr:
1753 case Hexagon::S4_pstorerbf_rr:
1754 case Hexagon::S2_pstorerbt_io:
1755 case Hexagon::S2_pstorerbf_io:
1756 case Hexagon::S2_pstorerbt_pi:
1757 case Hexagon::S2_pstorerbf_pi:
1758 case Hexagon::S2_pstorerdt_io:
1759 case Hexagon::S2_pstorerdf_io:
1760 case Hexagon::S4_pstorerdt_rr:
1761 case Hexagon::S4_pstorerdf_rr:
1762 case Hexagon::S2_pstorerdt_pi:
1763 case Hexagon::S2_pstorerdf_pi:
1764 case Hexagon::S2_pstorerht_io:
1765 case Hexagon::S2_pstorerhf_io:
1766 case Hexagon::S4_storeirht_io:
1767 case Hexagon::S4_storeirhf_io:
1768 case Hexagon::S4_pstorerht_rr:
1769 case Hexagon::S4_pstorerhf_rr:
1770 case Hexagon::S2_pstorerht_pi:
1771 case Hexagon::S2_pstorerhf_pi:
1772 case Hexagon::S2_pstorerit_io:
1773 case Hexagon::S2_pstorerif_io:
1774 case Hexagon::S4_storeirit_io:
1775 case Hexagon::S4_storeirif_io:
1776 case Hexagon::S4_pstorerit_rr:
1777 case Hexagon::S4_pstorerif_rr:
1778 case Hexagon::S2_pstorerit_pi:
1779 case Hexagon::S2_pstorerif_pi:
1780
1781 // V4 global address store before promoting to dot new.
1782 case Hexagon::S4_pstorerdt_abs:
1783 case Hexagon::S4_pstorerdf_abs:
1784 case Hexagon::S4_pstorerbt_abs:
1785 case Hexagon::S4_pstorerbf_abs:
1786 case Hexagon::S4_pstorerht_abs:
1787 case Hexagon::S4_pstorerhf_abs:
1788 case Hexagon::S4_pstorerit_abs:
1789 case Hexagon::S4_pstorerif_abs:
1790 return true;
1791
1792 // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
1793 // from the "Conditional Store" list. Because a predicated new value store
1794 // would NOT be promoted to a double dot new store.
1795 // This function returns yes for those stores that are predicated but not
1796 // yet promoted to predicate dot new instructions.
1797 }
1798}
1799
1800
1801bool HexagonInstrInfo::isConditionalTransfer(const MachineInstr *MI) const {
1802 switch (MI->getOpcode()) {
1803 case Hexagon::A2_tfrt:
1804 case Hexagon::A2_tfrf:
1805 case Hexagon::C2_cmoveit:
1806 case Hexagon::C2_cmoveif:
1807 case Hexagon::A2_tfrtnew:
1808 case Hexagon::A2_tfrfnew:
1809 case Hexagon::C2_cmovenewit:
1810 case Hexagon::C2_cmovenewif:
1811 case Hexagon::A2_tfrpt:
1812 case Hexagon::A2_tfrpf:
1813 return true;
1814
1815 default:
1816 return false;
1817 }
1818 return false;
1819}
1820
1821
1822// TODO: In order to have isExtendable for fpimm/f32Ext, we need to handle
1823// isFPImm and later getFPImm as well.
1824bool HexagonInstrInfo::isConstExtended(const MachineInstr *MI) const {
1825 const uint64_t F = MI->getDesc().TSFlags;
1826 unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
1827 if (isExtended) // Instruction must be extended.
1828 return true;
1829
1830 unsigned isExtendable =
1831 (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
1832 if (!isExtendable)
1833 return false;
1834
1835 if (MI->isCall())
1836 return false;
1837
1838 short ExtOpNum = getCExtOpNum(MI);
1839 const MachineOperand &MO = MI->getOperand(ExtOpNum);
1840 // Use MO operand flags to determine if MO
1841 // has the HMOTF_ConstExtended flag set.
1842 if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
1843 return true;
1844 // If this is a Machine BB address we are talking about, and it is
1845 // not marked as extended, say so.
1846 if (MO.isMBB())
1847 return false;
1848
1849 // We could be using an instruction with an extendable immediate and shoehorn
1850 // a global address into it. If it is a global address it will be constant
1851 // extended. We do this for COMBINE.
1852 // We currently only handle isGlobal() because it is the only kind of
1853 // object we are going to end up with here for now.
1854 // In the future we probably should add isSymbol(), etc.
1855 if (MO.isGlobal() || MO.isSymbol() || MO.isBlockAddress() ||
1856 MO.isJTI() || MO.isCPI())
1857 return true;
1858
1859 // If the extendable operand is not 'Immediate' type, the instruction should
1860 // have 'isExtended' flag set.
1861 assert(MO.isImm() && "Extendable operand must be Immediate type")((MO.isImm() && "Extendable operand must be Immediate type"
) ? static_cast<void> (0) : __assert_fail ("MO.isImm() && \"Extendable operand must be Immediate type\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 1861, __PRETTY_FUNCTION__));
1862
1863 int MinValue = getMinValue(MI);
1864 int MaxValue = getMaxValue(MI);
1865 int ImmValue = MO.getImm();
1866
1867 return (ImmValue < MinValue || ImmValue > MaxValue);
1868}
1869
1870
1871bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1872 switch (MI->getOpcode()) {
1873 case Hexagon::L4_return :
1874 case Hexagon::L4_return_t :
1875 case Hexagon::L4_return_f :
1876 case Hexagon::L4_return_tnew_pnt :
1877 case Hexagon::L4_return_fnew_pnt :
1878 case Hexagon::L4_return_tnew_pt :
1879 case Hexagon::L4_return_fnew_pt :
1880 return true;
1881 }
1882 return false;
1883}
1884
1885
1886// Return true when ConsMI uses a register defined by ProdMI.
1887bool HexagonInstrInfo::isDependent(const MachineInstr *ProdMI,
1888 const MachineInstr *ConsMI) const {
1889 const MCInstrDesc &ProdMCID = ProdMI->getDesc();
1890 if (!ProdMCID.getNumDefs())
1891 return false;
1892
1893 auto &HRI = getRegisterInfo();
1894
1895 SmallVector<unsigned, 4> DefsA;
1896 SmallVector<unsigned, 4> DefsB;
1897 SmallVector<unsigned, 8> UsesA;
1898 SmallVector<unsigned, 8> UsesB;
1899
1900 parseOperands(ProdMI, DefsA, UsesA);
1901 parseOperands(ConsMI, DefsB, UsesB);
1902
1903 for (auto &RegA : DefsA)
1904 for (auto &RegB : UsesB) {
1905 // True data dependency.
1906 if (RegA == RegB)
1907 return true;
1908
1909 if (Hexagon::DoubleRegsRegClass.contains(RegA))
1910 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
1911 if (RegB == *SubRegs)
1912 return true;
1913
1914 if (Hexagon::DoubleRegsRegClass.contains(RegB))
1915 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
1916 if (RegA == *SubRegs)
1917 return true;
1918 }
1919
1920 return false;
1921}
1922
1923
1924// Returns true if the instruction is alread a .cur.
1925bool HexagonInstrInfo::isDotCurInst(const MachineInstr* MI) const {
1926 switch (MI->getOpcode()) {
1927 case Hexagon::V6_vL32b_cur_pi:
1928 case Hexagon::V6_vL32b_cur_ai:
1929 case Hexagon::V6_vL32b_cur_pi_128B:
1930 case Hexagon::V6_vL32b_cur_ai_128B:
1931 return true;
1932 }
1933 return false;
1934}
1935
1936
1937// Returns true, if any one of the operands is a dot new
1938// insn, whether it is predicated dot new or register dot new.
1939bool HexagonInstrInfo::isDotNewInst(const MachineInstr* MI) const {
1940 if (isNewValueInst(MI) || (isPredicated(*MI) && isPredicatedNew(*MI)))
1941 return true;
1942
1943 return false;
1944}
1945
1946
1947/// Symmetrical. See if these two instructions are fit for duplex pair.
1948bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa,
1949 const MachineInstr *MIb) const {
1950 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
1951 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb);
1952 return (isDuplexPairMatch(MIaG, MIbG) || isDuplexPairMatch(MIbG, MIaG));
1953}
1954
1955
1956bool HexagonInstrInfo::isEarlySourceInstr(const MachineInstr *MI) const {
1957 if (!MI)
1958 return false;
1959
1960 if (MI->mayLoad() || MI->mayStore() || MI->isCompare())
1961 return true;
1962
1963 // Multiply
1964 unsigned SchedClass = MI->getDesc().getSchedClass();
1965 if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
1966 return true;
1967 return false;
1968}
1969
1970
1971bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
1972 return (Opcode == Hexagon::ENDLOOP0 ||
1973 Opcode == Hexagon::ENDLOOP1);
1974}
1975
1976
1977bool HexagonInstrInfo::isExpr(unsigned OpType) const {
1978 switch(OpType) {
1979 case MachineOperand::MO_MachineBasicBlock:
1980 case MachineOperand::MO_GlobalAddress:
1981 case MachineOperand::MO_ExternalSymbol:
1982 case MachineOperand::MO_JumpTableIndex:
1983 case MachineOperand::MO_ConstantPoolIndex:
1984 case MachineOperand::MO_BlockAddress:
1985 return true;
1986 default:
1987 return false;
1988 }
1989}
1990
1991
1992bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
1993 const MCInstrDesc &MID = MI->getDesc();
1994 const uint64_t F = MID.TSFlags;
1995 if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
1996 return true;
1997
1998 // TODO: This is largely obsolete now. Will need to be removed
1999 // in consecutive patches.
2000 switch(MI->getOpcode()) {
2001 // TFR_FI Remains a special case.
2002 case Hexagon::TFR_FI:
2003 return true;
2004 default:
2005 return false;
2006 }
2007 return false;
2008}
2009
2010
2011// This returns true in two cases:
2012// - The OP code itself indicates that this is an extended instruction.
2013// - One of MOs has been marked with HMOTF_ConstExtended flag.
2014bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
2015 // First check if this is permanently extended op code.
2016 const uint64_t F = MI->getDesc().TSFlags;
2017 if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
2018 return true;
2019 // Use MO operand flags to determine if one of MI's operands
2020 // has HMOTF_ConstExtended flag set.
2021 for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
2022 E = MI->operands_end(); I != E; ++I) {
2023 if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2024 return true;
2025 }
2026 return false;
2027}
2028
2029
2030bool HexagonInstrInfo::isFloat(const MachineInstr *MI) const {
2031 unsigned Opcode = MI->getOpcode();
2032 const uint64_t F = get(Opcode).TSFlags;
2033 return (F >> HexagonII::FPPos) & HexagonII::FPMask;
2034}
2035
2036
2037// No V60 HVX VMEM with A_INDIRECT.
2038bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr *I,
2039 const MachineInstr *J) const {
2040 if (!isV60VectorInstruction(I))
2041 return false;
2042 if (!I->mayLoad() && !I->mayStore())
2043 return false;
2044 return J->isIndirectBranch() || isIndirectCall(J) || isIndirectL4Return(J);
2045}
2046
2047
2048bool HexagonInstrInfo::isIndirectCall(const MachineInstr *MI) const {
2049 switch (MI->getOpcode()) {
2050 case Hexagon::J2_callr :
2051 case Hexagon::J2_callrf :
2052 case Hexagon::J2_callrt :
2053 return true;
2054 }
2055 return false;
2056}
2057
2058
2059bool HexagonInstrInfo::isIndirectL4Return(const MachineInstr *MI) const {
2060 switch (MI->getOpcode()) {
2061 case Hexagon::L4_return :
2062 case Hexagon::L4_return_t :
2063 case Hexagon::L4_return_f :
2064 case Hexagon::L4_return_fnew_pnt :
2065 case Hexagon::L4_return_fnew_pt :
2066 case Hexagon::L4_return_tnew_pnt :
2067 case Hexagon::L4_return_tnew_pt :
2068 return true;
2069 }
2070 return false;
2071}
2072
2073
2074bool HexagonInstrInfo::isJumpR(const MachineInstr *MI) const {
2075 switch (MI->getOpcode()) {
2076 case Hexagon::J2_jumpr :
2077 case Hexagon::J2_jumprt :
2078 case Hexagon::J2_jumprf :
2079 case Hexagon::J2_jumprtnewpt :
2080 case Hexagon::J2_jumprfnewpt :
2081 case Hexagon::J2_jumprtnew :
2082 case Hexagon::J2_jumprfnew :
2083 return true;
2084 }
2085 return false;
2086}
2087
2088
2089// Return true if a given MI can accomodate given offset.
2090// Use abs estimate as oppose to the exact number.
2091// TODO: This will need to be changed to use MC level
2092// definition of instruction extendable field size.
2093bool HexagonInstrInfo::isJumpWithinBranchRange(const MachineInstr *MI,
2094 unsigned offset) const {
2095 // This selection of jump instructions matches to that what
2096 // AnalyzeBranch can parse, plus NVJ.
2097 if (isNewValueJump(MI)) // r9:2
2098 return isInt<11>(offset);
2099
2100 switch (MI->getOpcode()) {
2101 // Still missing Jump to address condition on register value.
2102 default:
2103 return false;
2104 case Hexagon::J2_jump: // bits<24> dst; // r22:2
2105 case Hexagon::J2_call:
2106 case Hexagon::CALLv3nr:
2107 return isInt<24>(offset);
2108 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2
2109 case Hexagon::J2_jumpf:
2110 case Hexagon::J2_jumptnew:
2111 case Hexagon::J2_jumptnewpt:
2112 case Hexagon::J2_jumpfnew:
2113 case Hexagon::J2_jumpfnewpt:
2114 case Hexagon::J2_callt:
2115 case Hexagon::J2_callf:
2116 return isInt<17>(offset);
2117 case Hexagon::J2_loop0i:
2118 case Hexagon::J2_loop0iext:
2119 case Hexagon::J2_loop0r:
2120 case Hexagon::J2_loop0rext:
2121 case Hexagon::J2_loop1i:
2122 case Hexagon::J2_loop1iext:
2123 case Hexagon::J2_loop1r:
2124 case Hexagon::J2_loop1rext:
2125 return isInt<9>(offset);
2126 // TODO: Add all the compound branches here. Can we do this in Relation model?
2127 case Hexagon::J4_cmpeqi_tp0_jump_nt:
2128 case Hexagon::J4_cmpeqi_tp1_jump_nt:
2129 return isInt<11>(offset);
2130 }
2131}
2132
2133
2134bool HexagonInstrInfo::isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
2135 const MachineInstr *ESMI) const {
2136 if (!LRMI || !ESMI)
2137 return false;
2138
2139 bool isLate = isLateResultInstr(LRMI);
2140 bool isEarly = isEarlySourceInstr(ESMI);
2141
2142 DEBUG(dbgs() << "V60" << (isLate ? "-LR " : " -- "))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "V60" << (isLate
? "-LR " : " -- "); } } while (0);
2143 DEBUG(LRMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { LRMI->dump(); } } while (0);
2144 DEBUG(dbgs() << "V60" << (isEarly ? "-ES " : " -- "))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "V60" << (isEarly
? "-ES " : " -- "); } } while (0);
2145 DEBUG(ESMI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { ESMI->dump(); } } while (0);
2146
2147 if (isLate && isEarly) {
2148 DEBUG(dbgs() << "++Is Late Result feeding Early Source\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "++Is Late Result feeding Early Source\n"
; } } while (0);
2149 return true;
2150 }
2151
2152 return false;
2153}
2154
2155
2156bool HexagonInstrInfo::isLateResultInstr(const MachineInstr *MI) const {
2157 if (!MI)
2158 return false;
2159
2160 switch (MI->getOpcode()) {
2161 case TargetOpcode::EXTRACT_SUBREG:
2162 case TargetOpcode::INSERT_SUBREG:
2163 case TargetOpcode::SUBREG_TO_REG:
2164 case TargetOpcode::REG_SEQUENCE:
2165 case TargetOpcode::IMPLICIT_DEF:
2166 case TargetOpcode::COPY:
2167 case TargetOpcode::INLINEASM:
2168 case TargetOpcode::PHI:
2169 return false;
2170 default:
2171 break;
2172 }
2173
2174 unsigned SchedClass = MI->getDesc().getSchedClass();
2175
2176 switch (SchedClass) {
2177 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2178 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2179 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2180 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2181 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2182 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2183 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2184 case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
2185 case Hexagon::Sched::V2LDST_tc_st_SLOT0:
2186 case Hexagon::Sched::V2LDST_tc_st_SLOT01:
2187 case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
2188 case Hexagon::Sched::V4LDST_tc_st_SLOT0:
2189 case Hexagon::Sched::V4LDST_tc_st_SLOT01:
2190 return false;
2191 }
2192 return true;
2193}
2194
2195
2196bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr *MI) const {
2197 if (!MI)
2198 return false;
2199
2200 // Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
2201 // resource, but all operands can be received late like an ALU instruction.
2202 return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
2203}
2204
2205
2206bool HexagonInstrInfo::isLoopN(const MachineInstr *MI) const {
2207 unsigned Opcode = MI->getOpcode();
2208 return Opcode == Hexagon::J2_loop0i ||
2209 Opcode == Hexagon::J2_loop0r ||
2210 Opcode == Hexagon::J2_loop0iext ||
2211 Opcode == Hexagon::J2_loop0rext ||
2212 Opcode == Hexagon::J2_loop1i ||
2213 Opcode == Hexagon::J2_loop1r ||
2214 Opcode == Hexagon::J2_loop1iext ||
2215 Opcode == Hexagon::J2_loop1rext;
2216}
2217
2218
2219bool HexagonInstrInfo::isMemOp(const MachineInstr *MI) const {
2220 switch (MI->getOpcode()) {
2221 default: return false;
2222 case Hexagon::L4_iadd_memopw_io :
2223 case Hexagon::L4_isub_memopw_io :
2224 case Hexagon::L4_add_memopw_io :
2225 case Hexagon::L4_sub_memopw_io :
2226 case Hexagon::L4_and_memopw_io :
2227 case Hexagon::L4_or_memopw_io :
2228 case Hexagon::L4_iadd_memoph_io :
2229 case Hexagon::L4_isub_memoph_io :
2230 case Hexagon::L4_add_memoph_io :
2231 case Hexagon::L4_sub_memoph_io :
2232 case Hexagon::L4_and_memoph_io :
2233 case Hexagon::L4_or_memoph_io :
2234 case Hexagon::L4_iadd_memopb_io :
2235 case Hexagon::L4_isub_memopb_io :
2236 case Hexagon::L4_add_memopb_io :
2237 case Hexagon::L4_sub_memopb_io :
2238 case Hexagon::L4_and_memopb_io :
2239 case Hexagon::L4_or_memopb_io :
2240 case Hexagon::L4_ior_memopb_io:
2241 case Hexagon::L4_ior_memoph_io:
2242 case Hexagon::L4_ior_memopw_io:
2243 case Hexagon::L4_iand_memopb_io:
2244 case Hexagon::L4_iand_memoph_io:
2245 case Hexagon::L4_iand_memopw_io:
2246 return true;
2247 }
2248 return false;
2249}
2250
2251
2252bool HexagonInstrInfo::isNewValue(const MachineInstr* MI) const {
2253 const uint64_t F = MI->getDesc().TSFlags;
2254 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2255}
2256
2257
2258bool HexagonInstrInfo::isNewValue(unsigned Opcode) const {
2259 const uint64_t F = get(Opcode).TSFlags;
2260 return (F >> HexagonII::NewValuePos) & HexagonII::NewValueMask;
2261}
2262
2263
2264bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
2265 return isNewValueJump(MI) || isNewValueStore(MI);
2266}
2267
2268
2269bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
2270 return isNewValue(MI) && MI->isBranch();
2271}
2272
2273
2274bool HexagonInstrInfo::isNewValueJump(unsigned Opcode) const {
2275 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode);
2276}
2277
2278
2279bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
2280 const uint64_t F = MI->getDesc().TSFlags;
2281 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2282}
2283
2284
2285bool HexagonInstrInfo::isNewValueStore(unsigned Opcode) const {
2286 const uint64_t F = get(Opcode).TSFlags;
2287 return (F >> HexagonII::NVStorePos) & HexagonII::NVStoreMask;
2288}
2289
2290
2291// Returns true if a particular operand is extendable for an instruction.
2292bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2293 unsigned OperandNum) const {
2294 const uint64_t F = MI->getDesc().TSFlags;
2295 return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2296 == OperandNum;
2297}
2298
2299
2300bool HexagonInstrInfo::isPostIncrement(const MachineInstr* MI) const {
2301 return getAddrMode(MI) == HexagonII::PostInc;
2302}
2303
2304
2305bool HexagonInstrInfo::isPredicatedNew(const MachineInstr &MI) const {
2306 const uint64_t F = MI.getDesc().TSFlags;
2307 assert(isPredicated(MI))((isPredicated(MI)) ? static_cast<void> (0) : __assert_fail
("isPredicated(MI)", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2307, __PRETTY_FUNCTION__));
2308 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2309}
2310
2311
2312bool HexagonInstrInfo::isPredicatedNew(unsigned Opcode) const {
2313 const uint64_t F = get(Opcode).TSFlags;
2314 assert(isPredicated(Opcode))((isPredicated(Opcode)) ? static_cast<void> (0) : __assert_fail
("isPredicated(Opcode)", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2314, __PRETTY_FUNCTION__));
2315 return (F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask;
2316}
2317
2318
2319bool HexagonInstrInfo::isPredicatedTrue(const MachineInstr &MI) const {
2320 const uint64_t F = MI.getDesc().TSFlags;
2321 return !((F >> HexagonII::PredicatedFalsePos) &
2322 HexagonII::PredicatedFalseMask);
2323}
2324
2325
2326bool HexagonInstrInfo::isPredicatedTrue(unsigned Opcode) const {
2327 const uint64_t F = get(Opcode).TSFlags;
2328 // Make sure that the instruction is predicated.
2329 assert((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask)(((F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask
) ? static_cast<void> (0) : __assert_fail ("(F>> HexagonII::PredicatedPos) & HexagonII::PredicatedMask"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2329, __PRETTY_FUNCTION__));
2330 return !((F >> HexagonII::PredicatedFalsePos) &
2331 HexagonII::PredicatedFalseMask);
2332}
2333
2334
2335bool HexagonInstrInfo::isPredicated(unsigned Opcode) const {
2336 const uint64_t F = get(Opcode).TSFlags;
2337 return (F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask;
2338}
2339
2340
2341bool HexagonInstrInfo::isPredicateLate(unsigned Opcode) const {
2342 const uint64_t F = get(Opcode).TSFlags;
2343 return ~(F >> HexagonII::PredicateLatePos) & HexagonII::PredicateLateMask;
2344}
2345
2346
2347bool HexagonInstrInfo::isPredictedTaken(unsigned Opcode) const {
2348 const uint64_t F = get(Opcode).TSFlags;
2349 assert(get(Opcode).isBranch() &&((get(Opcode).isBranch() && (isPredicatedNew(Opcode) ||
isNewValue(Opcode))) ? static_cast<void> (0) : __assert_fail
("get(Opcode).isBranch() && (isPredicatedNew(Opcode) || isNewValue(Opcode))"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2350, __PRETTY_FUNCTION__))
2350 (isPredicatedNew(Opcode) || isNewValue(Opcode)))((get(Opcode).isBranch() && (isPredicatedNew(Opcode) ||
isNewValue(Opcode))) ? static_cast<void> (0) : __assert_fail
("get(Opcode).isBranch() && (isPredicatedNew(Opcode) || isNewValue(Opcode))"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2350, __PRETTY_FUNCTION__));
2351 return (F >> HexagonII::TakenPos) & HexagonII::TakenMask;
2352}
2353
2354
2355bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
2356 return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 ||
2357 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT ||
2358 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC ||
2359 MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC;
2360}
2361
2362
2363bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr* MI) const {
2364 switch (MI->getOpcode()) {
2365 // Byte
2366 case Hexagon::L2_loadrb_io:
2367 case Hexagon::L4_loadrb_ur:
2368 case Hexagon::L4_loadrb_ap:
2369 case Hexagon::L2_loadrb_pr:
2370 case Hexagon::L2_loadrb_pbr:
2371 case Hexagon::L2_loadrb_pi:
2372 case Hexagon::L2_loadrb_pci:
2373 case Hexagon::L2_loadrb_pcr:
2374 case Hexagon::L2_loadbsw2_io:
2375 case Hexagon::L4_loadbsw2_ur:
2376 case Hexagon::L4_loadbsw2_ap:
2377 case Hexagon::L2_loadbsw2_pr:
2378 case Hexagon::L2_loadbsw2_pbr:
2379 case Hexagon::L2_loadbsw2_pi:
2380 case Hexagon::L2_loadbsw2_pci:
2381 case Hexagon::L2_loadbsw2_pcr:
2382 case Hexagon::L2_loadbsw4_io:
2383 case Hexagon::L4_loadbsw4_ur:
2384 case Hexagon::L4_loadbsw4_ap:
2385 case Hexagon::L2_loadbsw4_pr:
2386 case Hexagon::L2_loadbsw4_pbr:
2387 case Hexagon::L2_loadbsw4_pi:
2388 case Hexagon::L2_loadbsw4_pci:
2389 case Hexagon::L2_loadbsw4_pcr:
2390 case Hexagon::L4_loadrb_rr:
2391 case Hexagon::L2_ploadrbt_io:
2392 case Hexagon::L2_ploadrbt_pi:
2393 case Hexagon::L2_ploadrbf_io:
2394 case Hexagon::L2_ploadrbf_pi:
2395 case Hexagon::L2_ploadrbtnew_io:
2396 case Hexagon::L2_ploadrbfnew_io:
2397 case Hexagon::L4_ploadrbt_rr:
2398 case Hexagon::L4_ploadrbf_rr:
2399 case Hexagon::L4_ploadrbtnew_rr:
2400 case Hexagon::L4_ploadrbfnew_rr:
2401 case Hexagon::L2_ploadrbtnew_pi:
2402 case Hexagon::L2_ploadrbfnew_pi:
2403 case Hexagon::L4_ploadrbt_abs:
2404 case Hexagon::L4_ploadrbf_abs:
2405 case Hexagon::L4_ploadrbtnew_abs:
2406 case Hexagon::L4_ploadrbfnew_abs:
2407 case Hexagon::L2_loadrbgp:
2408 // Half
2409 case Hexagon::L2_loadrh_io:
2410 case Hexagon::L4_loadrh_ur:
2411 case Hexagon::L4_loadrh_ap:
2412 case Hexagon::L2_loadrh_pr:
2413 case Hexagon::L2_loadrh_pbr:
2414 case Hexagon::L2_loadrh_pi:
2415 case Hexagon::L2_loadrh_pci:
2416 case Hexagon::L2_loadrh_pcr:
2417 case Hexagon::L4_loadrh_rr:
2418 case Hexagon::L2_ploadrht_io:
2419 case Hexagon::L2_ploadrht_pi:
2420 case Hexagon::L2_ploadrhf_io:
2421 case Hexagon::L2_ploadrhf_pi:
2422 case Hexagon::L2_ploadrhtnew_io:
2423 case Hexagon::L2_ploadrhfnew_io:
2424 case Hexagon::L4_ploadrht_rr:
2425 case Hexagon::L4_ploadrhf_rr:
2426 case Hexagon::L4_ploadrhtnew_rr:
2427 case Hexagon::L4_ploadrhfnew_rr:
2428 case Hexagon::L2_ploadrhtnew_pi:
2429 case Hexagon::L2_ploadrhfnew_pi:
2430 case Hexagon::L4_ploadrht_abs:
2431 case Hexagon::L4_ploadrhf_abs:
2432 case Hexagon::L4_ploadrhtnew_abs:
2433 case Hexagon::L4_ploadrhfnew_abs:
2434 case Hexagon::L2_loadrhgp:
2435 return true;
2436 default:
2437 return false;
2438 }
2439}
2440
2441
2442bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const {
2443 const uint64_t F = MI->getDesc().TSFlags;
2444 return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
2445}
2446
2447
2448bool HexagonInstrInfo::isSpillPredRegOp(const MachineInstr *MI) const {
2449 switch (MI->getOpcode()) {
2450 case Hexagon::STriw_pred :
2451 case Hexagon::LDriw_pred :
2452 return true;
2453 default:
2454 return false;
2455 }
2456}
2457
2458
2459// Returns true when SU has a timing class TC1.
2460bool HexagonInstrInfo::isTC1(const MachineInstr *MI) const {
2461 unsigned SchedClass = MI->getDesc().getSchedClass();
2462 switch (SchedClass) {
2463 case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
2464 case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
2465 case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
2466 case Hexagon::Sched::ALU64_tc_1_SLOT23:
2467 case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
2468 //case Hexagon::Sched::M_tc_1_SLOT23:
2469 case Hexagon::Sched::S_2op_tc_1_SLOT23:
2470 case Hexagon::Sched::S_3op_tc_1_SLOT23:
2471 return true;
2472
2473 default:
2474 return false;
2475 }
2476}
2477
2478
2479bool HexagonInstrInfo::isTC2(const MachineInstr *MI) const {
2480 unsigned SchedClass = MI->getDesc().getSchedClass();
2481 switch (SchedClass) {
2482 case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
2483 case Hexagon::Sched::ALU64_tc_2_SLOT23:
2484 case Hexagon::Sched::CR_tc_2_SLOT3:
2485 case Hexagon::Sched::M_tc_2_SLOT23:
2486 case Hexagon::Sched::S_2op_tc_2_SLOT23:
2487 case Hexagon::Sched::S_3op_tc_2_SLOT23:
2488 return true;
2489
2490 default:
2491 return false;
2492 }
2493}
2494
2495
2496bool HexagonInstrInfo::isTC2Early(const MachineInstr *MI) const {
2497 unsigned SchedClass = MI->getDesc().getSchedClass();
2498 switch (SchedClass) {
2499 case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
2500 case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
2501 case Hexagon::Sched::ALU64_tc_2early_SLOT23:
2502 case Hexagon::Sched::CR_tc_2early_SLOT23:
2503 case Hexagon::Sched::CR_tc_2early_SLOT3:
2504 case Hexagon::Sched::J_tc_2early_SLOT0123:
2505 case Hexagon::Sched::J_tc_2early_SLOT2:
2506 case Hexagon::Sched::J_tc_2early_SLOT23:
2507 case Hexagon::Sched::S_2op_tc_2early_SLOT23:
2508 case Hexagon::Sched::S_3op_tc_2early_SLOT23:
2509 return true;
2510
2511 default:
2512 return false;
2513 }
2514}
2515
2516
2517bool HexagonInstrInfo::isTC4x(const MachineInstr *MI) const {
2518 if (!MI)
2519 return false;
2520
2521 unsigned SchedClass = MI->getDesc().getSchedClass();
2522 return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
2523}
2524
2525
2526bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr *MI) const {
2527 if (!MI)
2528 return false;
2529
2530 const uint64_t V = getType(MI);
2531 return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
2532}
2533
2534
2535// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2536//
2537bool HexagonInstrInfo::isValidAutoIncImm(const EVT VT, const int Offset) const {
2538 if (VT == MVT::v16i32 || VT == MVT::v8i64 ||
2539 VT == MVT::v32i16 || VT == MVT::v64i8) {
2540 return (Offset >= Hexagon_MEMV_AUTOINC_MIN &&
2541 Offset <= Hexagon_MEMV_AUTOINC_MAX &&
2542 (Offset & 0x3f) == 0);
2543 }
2544 // 128B
2545 if (VT == MVT::v32i32 || VT == MVT::v16i64 ||
2546 VT == MVT::v64i16 || VT == MVT::v128i8) {
2547 return (Offset >= Hexagon_MEMV_AUTOINC_MIN_128B &&
2548 Offset <= Hexagon_MEMV_AUTOINC_MAX_128B &&
2549 (Offset & 0x7f) == 0);
2550 }
2551 if (VT == MVT::i64) {
2552 return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2553 Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2554 (Offset & 0x7) == 0);
2555 }
2556 if (VT == MVT::i32) {
2557 return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2558 Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2559 (Offset & 0x3) == 0);
2560 }
2561 if (VT == MVT::i16) {
2562 return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2563 Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2564 (Offset & 0x1) == 0);
2565 }
2566 if (VT == MVT::i8) {
2567 return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2568 Offset <= Hexagon_MEMB_AUTOINC_MAX);
2569 }
2570 llvm_unreachable("Not an auto-inc opc!")::llvm::llvm_unreachable_internal("Not an auto-inc opc!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2570);
2571}
2572
2573
2574bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
2575 bool Extend) const {
2576 // This function is to check whether the "Offset" is in the correct range of
2577 // the given "Opcode". If "Offset" is not in the correct range, "A2_addi" is
2578 // inserted to calculate the final address. Due to this reason, the function
2579 // assumes that the "Offset" has correct alignment.
2580 // We used to assert if the offset was not properly aligned, however,
2581 // there are cases where a misaligned pointer recast can cause this
2582 // problem, and we need to allow for it. The front end warns of such
2583 // misaligns with respect to load size.
2584
2585 switch (Opcode) {
2586 case Hexagon::STriq_pred_V6:
2587 case Hexagon::STriq_pred_vec_V6:
2588 case Hexagon::STriv_pseudo_V6:
2589 case Hexagon::STrivv_pseudo_V6:
2590 case Hexagon::LDriq_pred_V6:
2591 case Hexagon::LDriq_pred_vec_V6:
2592 case Hexagon::LDriv_pseudo_V6:
2593 case Hexagon::LDrivv_pseudo_V6:
2594 case Hexagon::LDrivv_indexed:
2595 case Hexagon::STrivv_indexed:
2596 case Hexagon::V6_vL32b_ai:
2597 case Hexagon::V6_vS32b_ai:
2598 case Hexagon::V6_vL32Ub_ai:
2599 case Hexagon::V6_vS32Ub_ai:
2600 return (Offset >= Hexagon_MEMV_OFFSET_MIN) &&
2601 (Offset <= Hexagon_MEMV_OFFSET_MAX);
2602
2603 case Hexagon::STriq_pred_V6_128B:
2604 case Hexagon::STriq_pred_vec_V6_128B:
2605 case Hexagon::STriv_pseudo_V6_128B:
2606 case Hexagon::STrivv_pseudo_V6_128B:
2607 case Hexagon::LDriq_pred_V6_128B:
2608 case Hexagon::LDriq_pred_vec_V6_128B:
2609 case Hexagon::LDriv_pseudo_V6_128B:
2610 case Hexagon::LDrivv_pseudo_V6_128B:
2611 case Hexagon::LDrivv_indexed_128B:
2612 case Hexagon::STrivv_indexed_128B:
2613 case Hexagon::V6_vL32b_ai_128B:
2614 case Hexagon::V6_vS32b_ai_128B:
2615 case Hexagon::V6_vL32Ub_ai_128B:
2616 case Hexagon::V6_vS32Ub_ai_128B:
2617 return (Offset >= Hexagon_MEMV_OFFSET_MIN_128B) &&
2618 (Offset <= Hexagon_MEMV_OFFSET_MAX_128B);
2619
2620 case Hexagon::J2_loop0i:
2621 case Hexagon::J2_loop1i:
2622 return isUInt<10>(Offset);
2623 }
2624
2625 if (Extend)
2626 return true;
2627
2628 switch (Opcode) {
2629 case Hexagon::L2_loadri_io:
2630 case Hexagon::S2_storeri_io:
2631 return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
2632 (Offset <= Hexagon_MEMW_OFFSET_MAX);
2633
2634 case Hexagon::L2_loadrd_io:
2635 case Hexagon::S2_storerd_io:
2636 return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
2637 (Offset <= Hexagon_MEMD_OFFSET_MAX);
2638
2639 case Hexagon::L2_loadrh_io:
2640 case Hexagon::L2_loadruh_io:
2641 case Hexagon::S2_storerh_io:
2642 return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
2643 (Offset <= Hexagon_MEMH_OFFSET_MAX);
2644
2645 case Hexagon::L2_loadrb_io:
2646 case Hexagon::L2_loadrub_io:
2647 case Hexagon::S2_storerb_io:
2648 return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2649 (Offset <= Hexagon_MEMB_OFFSET_MAX);
2650
2651 case Hexagon::A2_addi:
2652 return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2653 (Offset <= Hexagon_ADDI_OFFSET_MAX);
2654
2655 case Hexagon::L4_iadd_memopw_io :
2656 case Hexagon::L4_isub_memopw_io :
2657 case Hexagon::L4_add_memopw_io :
2658 case Hexagon::L4_sub_memopw_io :
2659 case Hexagon::L4_and_memopw_io :
2660 case Hexagon::L4_or_memopw_io :
2661 return (0 <= Offset && Offset <= 255);
2662
2663 case Hexagon::L4_iadd_memoph_io :
2664 case Hexagon::L4_isub_memoph_io :
2665 case Hexagon::L4_add_memoph_io :
2666 case Hexagon::L4_sub_memoph_io :
2667 case Hexagon::L4_and_memoph_io :
2668 case Hexagon::L4_or_memoph_io :
2669 return (0 <= Offset && Offset <= 127);
2670
2671 case Hexagon::L4_iadd_memopb_io :
2672 case Hexagon::L4_isub_memopb_io :
2673 case Hexagon::L4_add_memopb_io :
2674 case Hexagon::L4_sub_memopb_io :
2675 case Hexagon::L4_and_memopb_io :
2676 case Hexagon::L4_or_memopb_io :
2677 return (0 <= Offset && Offset <= 63);
2678
2679 // LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
2680 // any size. Later pass knows how to handle it.
2681 case Hexagon::STriw_pred:
2682 case Hexagon::LDriw_pred:
2683 case Hexagon::STriw_mod:
2684 case Hexagon::LDriw_mod:
2685 return true;
2686
2687 case Hexagon::TFR_FI:
2688 case Hexagon::TFR_FIA:
2689 case Hexagon::INLINEASM:
2690 return true;
2691
2692 case Hexagon::L2_ploadrbt_io:
2693 case Hexagon::L2_ploadrbf_io:
2694 case Hexagon::L2_ploadrubt_io:
2695 case Hexagon::L2_ploadrubf_io:
2696 case Hexagon::S2_pstorerbt_io:
2697 case Hexagon::S2_pstorerbf_io:
2698 case Hexagon::S4_storeirb_io:
2699 case Hexagon::S4_storeirbt_io:
2700 case Hexagon::S4_storeirbf_io:
2701 return isUInt<6>(Offset);
2702
2703 case Hexagon::L2_ploadrht_io:
2704 case Hexagon::L2_ploadrhf_io:
2705 case Hexagon::L2_ploadruht_io:
2706 case Hexagon::L2_ploadruhf_io:
2707 case Hexagon::S2_pstorerht_io:
2708 case Hexagon::S2_pstorerhf_io:
2709 case Hexagon::S4_storeirh_io:
2710 case Hexagon::S4_storeirht_io:
2711 case Hexagon::S4_storeirhf_io:
2712 return isShiftedUInt<6,1>(Offset);
2713
2714 case Hexagon::L2_ploadrit_io:
2715 case Hexagon::L2_ploadrif_io:
2716 case Hexagon::S2_pstorerit_io:
2717 case Hexagon::S2_pstorerif_io:
2718 case Hexagon::S4_storeiri_io:
2719 case Hexagon::S4_storeirit_io:
2720 case Hexagon::S4_storeirif_io:
2721 return isShiftedUInt<6,2>(Offset);
2722
2723 case Hexagon::L2_ploadrdt_io:
2724 case Hexagon::L2_ploadrdf_io:
2725 case Hexagon::S2_pstorerdt_io:
2726 case Hexagon::S2_pstorerdf_io:
2727 return isShiftedUInt<6,3>(Offset);
2728 } // switch
2729
2730 llvm_unreachable("No offset range is defined for this opcode. "::llvm::llvm_unreachable_internal("No offset range is defined for this opcode. "
"Please define it in the above switch statement!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2731)
2731 "Please define it in the above switch statement!")::llvm::llvm_unreachable_internal("No offset range is defined for this opcode. "
"Please define it in the above switch statement!", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 2731);
2732}
2733
2734
2735bool HexagonInstrInfo::isVecAcc(const MachineInstr *MI) const {
2736 return MI && isV60VectorInstruction(MI) && isAccumulator(MI);
2737}
2738
2739
2740bool HexagonInstrInfo::isVecALU(const MachineInstr *MI) const {
2741 if (!MI)
2742 return false;
2743 const uint64_t F = get(MI->getOpcode()).TSFlags;
2744 const uint64_t V = ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
2745 return
2746 V == HexagonII::TypeCVI_VA ||
2747 V == HexagonII::TypeCVI_VA_DV;
2748}
2749
2750
2751bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr *ProdMI,
2752 const MachineInstr *ConsMI) const {
2753 if (EnableACCForwarding && isVecAcc(ProdMI) && isVecAcc(ConsMI))
2754 return true;
2755
2756 if (EnableALUForwarding && (isVecALU(ConsMI) || isLateSourceInstr(ConsMI)))
2757 return true;
2758
2759 if (mayBeNewStore(ConsMI))
2760 return true;
2761
2762 return false;
2763}
2764
2765
2766bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr* MI) const {
2767 switch (MI->getOpcode()) {
2768 // Byte
2769 case Hexagon::L2_loadrub_io:
2770 case Hexagon::L4_loadrub_ur:
2771 case Hexagon::L4_loadrub_ap:
2772 case Hexagon::L2_loadrub_pr:
2773 case Hexagon::L2_loadrub_pbr:
2774 case Hexagon::L2_loadrub_pi:
2775 case Hexagon::L2_loadrub_pci:
2776 case Hexagon::L2_loadrub_pcr:
2777 case Hexagon::L2_loadbzw2_io:
2778 case Hexagon::L4_loadbzw2_ur:
2779 case Hexagon::L4_loadbzw2_ap:
2780 case Hexagon::L2_loadbzw2_pr:
2781 case Hexagon::L2_loadbzw2_pbr:
2782 case Hexagon::L2_loadbzw2_pi:
2783 case Hexagon::L2_loadbzw2_pci:
2784 case Hexagon::L2_loadbzw2_pcr:
2785 case Hexagon::L2_loadbzw4_io:
2786 case Hexagon::L4_loadbzw4_ur:
2787 case Hexagon::L4_loadbzw4_ap:
2788 case Hexagon::L2_loadbzw4_pr:
2789 case Hexagon::L2_loadbzw4_pbr:
2790 case Hexagon::L2_loadbzw4_pi:
2791 case Hexagon::L2_loadbzw4_pci:
2792 case Hexagon::L2_loadbzw4_pcr:
2793 case Hexagon::L4_loadrub_rr:
2794 case Hexagon::L2_ploadrubt_io:
2795 case Hexagon::L2_ploadrubt_pi:
2796 case Hexagon::L2_ploadrubf_io:
2797 case Hexagon::L2_ploadrubf_pi:
2798 case Hexagon::L2_ploadrubtnew_io:
2799 case Hexagon::L2_ploadrubfnew_io:
2800 case Hexagon::L4_ploadrubt_rr:
2801 case Hexagon::L4_ploadrubf_rr:
2802 case Hexagon::L4_ploadrubtnew_rr:
2803 case Hexagon::L4_ploadrubfnew_rr:
2804 case Hexagon::L2_ploadrubtnew_pi:
2805 case Hexagon::L2_ploadrubfnew_pi:
2806 case Hexagon::L4_ploadrubt_abs:
2807 case Hexagon::L4_ploadrubf_abs:
2808 case Hexagon::L4_ploadrubtnew_abs:
2809 case Hexagon::L4_ploadrubfnew_abs:
2810 case Hexagon::L2_loadrubgp:
2811 // Half
2812 case Hexagon::L2_loadruh_io:
2813 case Hexagon::L4_loadruh_ur:
2814 case Hexagon::L4_loadruh_ap:
2815 case Hexagon::L2_loadruh_pr:
2816 case Hexagon::L2_loadruh_pbr:
2817 case Hexagon::L2_loadruh_pi:
2818 case Hexagon::L2_loadruh_pci:
2819 case Hexagon::L2_loadruh_pcr:
2820 case Hexagon::L4_loadruh_rr:
2821 case Hexagon::L2_ploadruht_io:
2822 case Hexagon::L2_ploadruht_pi:
2823 case Hexagon::L2_ploadruhf_io:
2824 case Hexagon::L2_ploadruhf_pi:
2825 case Hexagon::L2_ploadruhtnew_io:
2826 case Hexagon::L2_ploadruhfnew_io:
2827 case Hexagon::L4_ploadruht_rr:
2828 case Hexagon::L4_ploadruhf_rr:
2829 case Hexagon::L4_ploadruhtnew_rr:
2830 case Hexagon::L4_ploadruhfnew_rr:
2831 case Hexagon::L2_ploadruhtnew_pi:
2832 case Hexagon::L2_ploadruhfnew_pi:
2833 case Hexagon::L4_ploadruht_abs:
2834 case Hexagon::L4_ploadruhf_abs:
2835 case Hexagon::L4_ploadruhtnew_abs:
2836 case Hexagon::L4_ploadruhfnew_abs:
2837 case Hexagon::L2_loadruhgp:
2838 return true;
2839 default:
2840 return false;
2841 }
2842}
2843
2844
2845/// \brief Can these instructions execute at the same time in a bundle.
2846bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr *First,
2847 const MachineInstr *Second) const {
2848 if (DisableNVSchedule)
2849 return false;
2850 if (mayBeNewStore(Second)) {
2851 // Make sure the definition of the first instruction is the value being
2852 // stored.
2853 const MachineOperand &Stored =
2854 Second->getOperand(Second->getNumOperands() - 1);
2855 if (!Stored.isReg())
2856 return false;
2857 for (unsigned i = 0, e = First->getNumOperands(); i < e; ++i) {
2858 const MachineOperand &Op = First->getOperand(i);
2859 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2860 return true;
2861 }
2862 }
2863 return false;
2864}
2865
2866
2867bool HexagonInstrInfo::hasEHLabel(const MachineBasicBlock *B) const {
2868 for (auto &I : *B)
2869 if (I.isEHLabel())
2870 return true;
2871 return false;
2872}
2873
2874
2875// Returns true if an instruction can be converted into a non-extended
2876// equivalent instruction.
2877bool HexagonInstrInfo::hasNonExtEquivalent(const MachineInstr *MI) const {
2878 short NonExtOpcode;
2879 // Check if the instruction has a register form that uses register in place
2880 // of the extended operand, if so return that as the non-extended form.
2881 if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2882 return true;
2883
2884 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2885 // Check addressing mode and retrieve non-ext equivalent instruction.
2886
2887 switch (getAddrMode(MI)) {
2888 case HexagonII::Absolute :
2889 // Load/store with absolute addressing mode can be converted into
2890 // base+offset mode.
2891 NonExtOpcode = Hexagon::getBaseWithImmOffset(MI->getOpcode());
2892 break;
2893 case HexagonII::BaseImmOffset :
2894 // Load/store with base+offset addressing mode can be converted into
2895 // base+register offset addressing mode. However left shift operand should
2896 // be set to 0.
2897 NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2898 break;
2899 case HexagonII::BaseLongOffset:
2900 NonExtOpcode = Hexagon::getRegShlForm(MI->getOpcode());
2901 break;
2902 default:
2903 return false;
2904 }
2905 if (NonExtOpcode < 0)
2906 return false;
2907 return true;
2908 }
2909 return false;
2910}
2911
2912
2913bool HexagonInstrInfo::hasPseudoInstrPair(const MachineInstr *MI) const {
2914 return Hexagon::getRealHWInstr(MI->getOpcode(),
2915 Hexagon::InstrType_Pseudo) >= 0;
2916}
2917
2918
2919bool HexagonInstrInfo::hasUncondBranch(const MachineBasicBlock *B)
2920 const {
2921 MachineBasicBlock::const_iterator I = B->getFirstTerminator(), E = B->end();
2922 while (I != E) {
2923 if (I->isBarrier())
2924 return true;
2925 ++I;
2926 }
2927 return false;
2928}
2929
2930
2931// Returns true, if a LD insn can be promoted to a cur load.
2932bool HexagonInstrInfo::mayBeCurLoad(const MachineInstr *MI) const {
2933 auto &HST = MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>();
2934 const uint64_t F = MI->getDesc().TSFlags;
2935 return ((F >> HexagonII::mayCVLoadPos) & HexagonII::mayCVLoadMask) &&
2936 HST.hasV60TOps();
2937}
2938
2939
2940// Returns true, if a ST insn can be promoted to a new-value store.
2941bool HexagonInstrInfo::mayBeNewStore(const MachineInstr *MI) const {
2942 const uint64_t F = MI->getDesc().TSFlags;
2943 return (F >> HexagonII::mayNVStorePos) & HexagonII::mayNVStoreMask;
2944}
2945
2946
2947bool HexagonInstrInfo::producesStall(const MachineInstr *ProdMI,
2948 const MachineInstr *ConsMI) const {
2949 // There is no stall when ProdMI is not a V60 vector.
2950 if (!isV60VectorInstruction(ProdMI))
2951 return false;
2952
2953 // There is no stall when ProdMI and ConsMI are not dependent.
2954 if (!isDependent(ProdMI, ConsMI))
2955 return false;
2956
2957 // When Forward Scheduling is enabled, there is no stall if ProdMI and ConsMI
2958 // are scheduled in consecutive packets.
2959 if (isVecUsableNextPacket(ProdMI, ConsMI))
2960 return false;
2961
2962 return true;
2963}
2964
2965
2966bool HexagonInstrInfo::producesStall(const MachineInstr *MI,
2967 MachineBasicBlock::const_instr_iterator BII) const {
2968 // There is no stall when I is not a V60 vector.
2969 if (!isV60VectorInstruction(MI))
2970 return false;
2971
2972 MachineBasicBlock::const_instr_iterator MII = BII;
2973 MachineBasicBlock::const_instr_iterator MIE = MII->getParent()->instr_end();
2974
2975 if (!(*MII).isBundle()) {
2976 const MachineInstr *J = &*MII;
2977 if (!isV60VectorInstruction(J))
2978 return false;
2979 else if (isVecUsableNextPacket(J, MI))
2980 return false;
2981 return true;
2982 }
2983
2984 for (++MII; MII != MIE && MII->isInsideBundle(); ++MII) {
2985 const MachineInstr *J = &*MII;
2986 if (producesStall(J, MI))
2987 return true;
2988 }
2989 return false;
2990}
2991
2992
2993bool HexagonInstrInfo::predCanBeUsedAsDotNew(const MachineInstr *MI,
2994 unsigned PredReg) const {
2995 for (unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2996 const MachineOperand &MO = MI->getOperand(opNum);
2997 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
2998 return false; // Predicate register must be explicitly defined.
2999 }
3000
3001 // Hexagon Programmer's Reference says that decbin, memw_locked, and
3002 // memd_locked cannot be used as .new as well,
3003 // but we don't seem to have these instructions defined.
3004 return MI->getOpcode() != Hexagon::A4_tlbmatch;
3005}
3006
3007
3008bool HexagonInstrInfo::PredOpcodeHasJMP_c(unsigned Opcode) const {
3009 return (Opcode == Hexagon::J2_jumpt) ||
3010 (Opcode == Hexagon::J2_jumpf) ||
3011 (Opcode == Hexagon::J2_jumptnew) ||
3012 (Opcode == Hexagon::J2_jumpfnew) ||
3013 (Opcode == Hexagon::J2_jumptnewpt) ||
3014 (Opcode == Hexagon::J2_jumpfnewpt);
3015}
3016
3017
3018bool HexagonInstrInfo::predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const {
3019 if (Cond.empty() || !isPredicated(Cond[0].getImm()))
3020 return false;
3021 return !isPredicatedTrue(Cond[0].getImm());
3022}
3023
3024
3025unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
3026 const uint64_t F = MI->getDesc().TSFlags;
3027 return (F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask;
3028}
3029
3030
3031// Returns the base register in a memory access (load/store). The offset is
3032// returned in Offset and the access size is returned in AccessSize.
3033unsigned HexagonInstrInfo::getBaseAndOffset(const MachineInstr *MI,
3034 int &Offset, unsigned &AccessSize) const {
3035 // Return if it is not a base+offset type instruction or a MemOp.
3036 if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
3037 getAddrMode(MI) != HexagonII::BaseLongOffset &&
3038 !isMemOp(MI) && !isPostIncrement(MI))
3039 return 0;
3040
3041 // Since it is a memory access instruction, getMemAccessSize() should never
3042 // return 0.
3043 assert (getMemAccessSize(MI) &&((getMemAccessSize(MI) && "BaseImmOffset or BaseLongOffset or MemOp without accessSize"
) ? static_cast<void> (0) : __assert_fail ("getMemAccessSize(MI) && \"BaseImmOffset or BaseLongOffset or MemOp without accessSize\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3044, __PRETTY_FUNCTION__))
3044 "BaseImmOffset or BaseLongOffset or MemOp without accessSize")((getMemAccessSize(MI) && "BaseImmOffset or BaseLongOffset or MemOp without accessSize"
) ? static_cast<void> (0) : __assert_fail ("getMemAccessSize(MI) && \"BaseImmOffset or BaseLongOffset or MemOp without accessSize\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3044, __PRETTY_FUNCTION__));
3045
3046 // Return Values of getMemAccessSize() are
3047 // 0 - Checked in the assert above.
3048 // 1, 2, 3, 4 & 7, 8 - The statement below is correct for all these.
3049 // MemAccessSize is represented as 1+log2(N) where N is size in bits.
3050 AccessSize = (1U << (getMemAccessSize(MI) - 1));
3051
3052 unsigned basePos = 0, offsetPos = 0;
3053 if (!getBaseAndOffsetPosition(MI, basePos, offsetPos))
3054 return 0;
3055
3056 // Post increment updates its EA after the mem access,
3057 // so we need to treat its offset as zero.
3058 if (isPostIncrement(MI))
3059 Offset = 0;
3060 else {
3061 Offset = MI->getOperand(offsetPos).getImm();
3062 }
3063
3064 return MI->getOperand(basePos).getReg();
3065}
3066
3067
3068/// Return the position of the base and offset operands for this instruction.
3069bool HexagonInstrInfo::getBaseAndOffsetPosition(const MachineInstr *MI,
3070 unsigned &BasePos, unsigned &OffsetPos) const {
3071 // Deal with memops first.
3072 if (isMemOp(MI)) {
3073 assert (MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&((MI->getOperand(0).isReg() && MI->getOperand(1
).isImm() && "Bad Memop.") ? static_cast<void> (
0) : __assert_fail ("MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && \"Bad Memop.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3074, __PRETTY_FUNCTION__))
3074 "Bad Memop.")((MI->getOperand(0).isReg() && MI->getOperand(1
).isImm() && "Bad Memop.") ? static_cast<void> (
0) : __assert_fail ("MI->getOperand(0).isReg() && MI->getOperand(1).isImm() && \"Bad Memop.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3074, __PRETTY_FUNCTION__));
3075 BasePos = 0;
3076 OffsetPos = 1;
3077 } else if (MI->mayStore()) {
3078 BasePos = 0;
3079 OffsetPos = 1;
3080 } else if (MI->mayLoad()) {
3081 BasePos = 1;
3082 OffsetPos = 2;
3083 } else
3084 return false;
3085
3086 if (isPredicated(*MI)) {
3087 BasePos++;
3088 OffsetPos++;
3089 }
3090 if (isPostIncrement(MI)) {
3091 BasePos++;
3092 OffsetPos++;
3093 }
3094
3095 if (!MI->getOperand(BasePos).isReg() || !MI->getOperand(OffsetPos).isImm())
3096 return false;
3097
3098 return true;
3099}
3100
3101
3102// Inserts branching instructions in reverse order of their occurence.
3103// e.g. jump_t t1 (i1)
3104// jump t2 (i2)
3105// Jumpers = {i2, i1}
3106SmallVector<MachineInstr*, 2> HexagonInstrInfo::getBranchingInstrs(
3107 MachineBasicBlock& MBB) const {
3108 SmallVector<MachineInstr*, 2> Jumpers;
3109 // If the block has no terminators, it just falls into the block after it.
3110 MachineBasicBlock::instr_iterator I = MBB.instr_end();
3111 if (I == MBB.instr_begin())
3112 return Jumpers;
3113
3114 // A basic block may looks like this:
3115 //
3116 // [ insn
3117 // EH_LABEL
3118 // insn
3119 // insn
3120 // insn
3121 // EH_LABEL
3122 // insn ]
3123 //
3124 // It has two succs but does not have a terminator
3125 // Don't know how to handle it.
3126 do {
3127 --I;
3128 if (I->isEHLabel())
3129 return Jumpers;
3130 } while (I != MBB.instr_begin());
3131
3132 I = MBB.instr_end();
3133 --I;
3134
3135 while (I->isDebugValue()) {
3136 if (I == MBB.instr_begin())
3137 return Jumpers;
3138 --I;
3139 }
3140 if (!isUnpredicatedTerminator(*I))
3141 return Jumpers;
3142
3143 // Get the last instruction in the block.
3144 MachineInstr *LastInst = &*I;
3145 Jumpers.push_back(LastInst);
3146 MachineInstr *SecondLastInst = nullptr;
3147 // Find one more terminator if present.
3148 do {
3149 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
3150 if (!SecondLastInst) {
3151 SecondLastInst = &*I;
3152 Jumpers.push_back(SecondLastInst);
3153 } else // This is a third branch.
3154 return Jumpers;
3155 }
3156 if (I == MBB.instr_begin())
3157 break;
3158 --I;
3159 } while (true);
3160 return Jumpers;
3161}
3162
3163
3164// Returns Operand Index for the constant extended instruction.
3165unsigned HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
3166 const uint64_t F = MI->getDesc().TSFlags;
3167 return (F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask;
3168}
3169
3170// See if instruction could potentially be a duplex candidate.
3171// If so, return its group. Zero otherwise.
3172HexagonII::CompoundGroup HexagonInstrInfo::getCompoundCandidateGroup(
3173 const MachineInstr *MI) const {
3174 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3175
3176 switch (MI->getOpcode()) {
3177 default:
3178 return HexagonII::HCG_None;
3179 //
3180 // Compound pairs.
3181 // "p0=cmp.eq(Rs16,Rt16); if (p0.new) jump:nt #r9:2"
3182 // "Rd16=#U6 ; jump #r9:2"
3183 // "Rd16=Rs16 ; jump #r9:2"
3184 //
3185 case Hexagon::C2_cmpeq:
3186 case Hexagon::C2_cmpgt:
3187 case Hexagon::C2_cmpgtu:
3188 DstReg = MI->getOperand(0).getReg();
3189 Src1Reg = MI->getOperand(1).getReg();
3190 Src2Reg = MI->getOperand(2).getReg();
3191 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3192 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3193 isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg))
3194 return HexagonII::HCG_A;
3195 break;
3196 case Hexagon::C2_cmpeqi:
3197 case Hexagon::C2_cmpgti:
3198 case Hexagon::C2_cmpgtui:
3199 // P0 = cmp.eq(Rs,#u2)
3200 DstReg = MI->getOperand(0).getReg();
3201 SrcReg = MI->getOperand(1).getReg();
3202 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3203 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3204 isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
3205 ((isUInt<5>(MI->getOperand(2).getImm())) ||
3206 (MI->getOperand(2).getImm() == -1)))
3207 return HexagonII::HCG_A;
3208 break;
3209 case Hexagon::A2_tfr:
3210 // Rd = Rs
3211 DstReg = MI->getOperand(0).getReg();
3212 SrcReg = MI->getOperand(1).getReg();
3213 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3214 return HexagonII::HCG_A;
3215 break;
3216 case Hexagon::A2_tfrsi:
3217 // Rd = #u6
3218 // Do not test for #u6 size since the const is getting extended
3219 // regardless and compound could be formed.
3220 DstReg = MI->getOperand(0).getReg();
3221 if (isIntRegForSubInst(DstReg))
3222 return HexagonII::HCG_A;
3223 break;
3224 case Hexagon::S2_tstbit_i:
3225 DstReg = MI->getOperand(0).getReg();
3226 Src1Reg = MI->getOperand(1).getReg();
3227 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3228 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) &&
3229 MI->getOperand(2).isImm() &&
3230 isIntRegForSubInst(Src1Reg) && (MI->getOperand(2).getImm() == 0))
3231 return HexagonII::HCG_A;
3232 break;
3233 // The fact that .new form is used pretty much guarantees
3234 // that predicate register will match. Nevertheless,
3235 // there could be some false positives without additional
3236 // checking.
3237 case Hexagon::J2_jumptnew:
3238 case Hexagon::J2_jumpfnew:
3239 case Hexagon::J2_jumptnewpt:
3240 case Hexagon::J2_jumpfnewpt:
3241 Src1Reg = MI->getOperand(0).getReg();
3242 if (Hexagon::PredRegsRegClass.contains(Src1Reg) &&
3243 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg))
3244 return HexagonII::HCG_B;
3245 break;
3246 // Transfer and jump:
3247 // Rd=#U6 ; jump #r9:2
3248 // Rd=Rs ; jump #r9:2
3249 // Do not test for jump range here.
3250 case Hexagon::J2_jump:
3251 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3252 return HexagonII::HCG_C;
3253 break;
3254 }
3255
3256 return HexagonII::HCG_None;
3257}
3258
3259
3260// Returns -1 when there is no opcode found.
3261unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr *GA,
3262 const MachineInstr *GB) const {
3263 assert(getCompoundCandidateGroup(GA) == HexagonII::HCG_A)((getCompoundCandidateGroup(GA) == HexagonII::HCG_A) ? static_cast
<void> (0) : __assert_fail ("getCompoundCandidateGroup(GA) == HexagonII::HCG_A"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3263, __PRETTY_FUNCTION__));
3264 assert(getCompoundCandidateGroup(GB) == HexagonII::HCG_B)((getCompoundCandidateGroup(GB) == HexagonII::HCG_B) ? static_cast
<void> (0) : __assert_fail ("getCompoundCandidateGroup(GB) == HexagonII::HCG_B"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3264, __PRETTY_FUNCTION__));
3265 if ((GA->getOpcode() != Hexagon::C2_cmpeqi) ||
3266 (GB->getOpcode() != Hexagon::J2_jumptnew))
3267 return -1;
3268 unsigned DestReg = GA->getOperand(0).getReg();
3269 if (!GB->readsRegister(DestReg))
3270 return -1;
3271 if (DestReg == Hexagon::P0)
3272 return Hexagon::J4_cmpeqi_tp0_jump_nt;
3273 if (DestReg == Hexagon::P1)
3274 return Hexagon::J4_cmpeqi_tp1_jump_nt;
3275 return -1;
3276}
3277
3278
3279int HexagonInstrInfo::getCondOpcode(int Opc, bool invertPredicate) const {
3280 enum Hexagon::PredSense inPredSense;
3281 inPredSense = invertPredicate ? Hexagon::PredSense_false :
3282 Hexagon::PredSense_true;
3283 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
3284 if (CondOpcode >= 0) // Valid Conditional opcode/instruction
3285 return CondOpcode;
3286
3287 // This switch case will be removed once all the instructions have been
3288 // modified to use relation maps.
3289 switch(Opc) {
3290 case Hexagon::TFRI_f:
3291 return !invertPredicate ? Hexagon::TFRI_cPt_f :
3292 Hexagon::TFRI_cNotPt_f;
3293 }
3294
3295 llvm_unreachable("Unexpected predicable instruction")::llvm::llvm_unreachable_internal("Unexpected predicable instruction"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3295);
3296}
3297
3298
3299// Return the cur value instruction for a given store.
3300int HexagonInstrInfo::getDotCurOp(const MachineInstr* MI) const {
3301 switch (MI->getOpcode()) {
3302 default: llvm_unreachable("Unknown .cur type")::llvm::llvm_unreachable_internal("Unknown .cur type", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3302);
3303 case Hexagon::V6_vL32b_pi:
3304 return Hexagon::V6_vL32b_cur_pi;
3305 case Hexagon::V6_vL32b_ai:
3306 return Hexagon::V6_vL32b_cur_ai;
3307 //128B
3308 case Hexagon::V6_vL32b_pi_128B:
3309 return Hexagon::V6_vL32b_cur_pi_128B;
3310 case Hexagon::V6_vL32b_ai_128B:
3311 return Hexagon::V6_vL32b_cur_ai_128B;
3312 }
3313 return 0;
3314}
3315
3316
3317
3318// The diagram below shows the steps involved in the conversion of a predicated
3319// store instruction to its .new predicated new-value form.
3320//
3321// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
3322// ^ ^
3323// / \ (not OK. it will cause new-value store to be
3324// / X conditional on p0.new while R2 producer is
3325// / \ on p0)
3326// / \.
3327// p.new store p.old NV store
3328// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new]
3329// ^ ^
3330// \ /
3331// \ /
3332// \ /
3333// p.old store
3334// [if (p0)memw(R0+#0)=R2]
3335//
3336//
3337// The following set of instructions further explains the scenario where
3338// conditional new-value store becomes invalid when promoted to .new predicate
3339// form.
3340//
3341// { 1) if (p0) r0 = add(r1, r2)
3342// 2) p0 = cmp.eq(r3, #0) }
3343//
3344// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with
3345// the first two instructions because in instr 1, r0 is conditional on old value
3346// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
3347// is not valid for new-value stores.
3348// Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
3349// from the "Conditional Store" list. Because a predicated new value store
3350// would NOT be promoted to a double dot new store. See diagram below:
3351// This function returns yes for those stores that are predicated but not
3352// yet promoted to predicate dot new instructions.
3353//
3354// +---------------------+
3355// /-----| if (p0) memw(..)=r0 |---------\~
3356// || +---------------------+ ||
3357// promote || /\ /\ || promote
3358// || /||\ /||\ ||
3359// \||/ demote || \||/
3360// \/ || || \/
3361// +-------------------------+ || +-------------------------+
3362// | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new |
3363// +-------------------------+ || +-------------------------+
3364// || || ||
3365// || demote \||/
3366// promote || \/ NOT possible
3367// || || /\~
3368// \||/ || /||\~
3369// \/ || ||
3370// +-----------------------------+
3371// | if (p0.new) memw(..)=r0.new |
3372// +-----------------------------+
3373// Double Dot New Store
3374//
3375// Returns the most basic instruction for the .new predicated instructions and
3376// new-value stores.
3377// For example, all of the following instructions will be converted back to the
3378// same instruction:
3379// 1) if (p0.new) memw(R0+#0) = R1.new --->
3380// 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
3381// 3) if (p0.new) memw(R0+#0) = R1 --->
3382//
3383// To understand the translation of instruction 1 to its original form, consider
3384// a packet with 3 instructions.
3385// { p0 = cmp.eq(R0,R1)
3386// if (p0.new) R2 = add(R3, R4)
3387// R5 = add (R3, R1)
3388// }
3389// if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
3390//
3391// This instruction can be part of the previous packet only if both p0 and R2
3392// are promoted to .new values. This promotion happens in steps, first
3393// predicate register is promoted to .new and in the next iteration R2 is
3394// promoted. Therefore, in case of dependence check failure (due to R5) during
3395// next iteration, it should be converted back to its most basic form.
3396
3397
3398// Return the new value instruction for a given store.
3399int HexagonInstrInfo::getDotNewOp(const MachineInstr* MI) const {
3400 int NVOpcode = Hexagon::getNewValueOpcode(MI->getOpcode());
3401 if (NVOpcode >= 0) // Valid new-value store instruction.
3402 return NVOpcode;
3403
3404 switch (MI->getOpcode()) {
3405 default: llvm_unreachable("Unknown .new type")::llvm::llvm_unreachable_internal("Unknown .new type", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3405);
3406 case Hexagon::S4_storerb_ur:
3407 return Hexagon::S4_storerbnew_ur;
3408
3409 case Hexagon::S2_storerb_pci:
3410 return Hexagon::S2_storerb_pci;
3411
3412 case Hexagon::S2_storeri_pci:
3413 return Hexagon::S2_storeri_pci;
3414
3415 case Hexagon::S2_storerh_pci:
3416 return Hexagon::S2_storerh_pci;
3417
3418 case Hexagon::S2_storerd_pci:
3419 return Hexagon::S2_storerd_pci;
3420
3421 case Hexagon::S2_storerf_pci:
3422 return Hexagon::S2_storerf_pci;
3423
3424 case Hexagon::V6_vS32b_ai:
3425 return Hexagon::V6_vS32b_new_ai;
3426
3427 case Hexagon::V6_vS32b_pi:
3428 return Hexagon::V6_vS32b_new_pi;
3429
3430 // 128B
3431 case Hexagon::V6_vS32b_ai_128B:
3432 return Hexagon::V6_vS32b_new_ai_128B;
3433
3434 case Hexagon::V6_vS32b_pi_128B:
3435 return Hexagon::V6_vS32b_new_pi_128B;
3436 }
3437 return 0;
3438}
3439
3440// Returns the opcode to use when converting MI, which is a conditional jump,
3441// into a conditional instruction which uses the .new value of the predicate.
3442// We also use branch probabilities to add a hint to the jump.
3443int HexagonInstrInfo::getDotNewPredJumpOp(const MachineInstr *MI,
3444 const MachineBranchProbabilityInfo *MBPI) const {
3445 // We assume that block can have at most two successors.
3446 bool taken = false;
3447 const MachineBasicBlock *Src = MI->getParent();
3448 const MachineOperand *BrTarget = &MI->getOperand(1);
3449 const MachineBasicBlock *Dst = BrTarget->getMBB();
3450
3451 const BranchProbability Prediction = MBPI->getEdgeProbability(Src, Dst);
3452 if (Prediction >= BranchProbability(1,2))
3453 taken = true;
3454
3455 switch (MI->getOpcode()) {
3456 case Hexagon::J2_jumpt:
3457 return taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew;
3458 case Hexagon::J2_jumpf:
3459 return taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew;
3460
3461 default:
3462 llvm_unreachable("Unexpected jump instruction.")::llvm::llvm_unreachable_internal("Unexpected jump instruction."
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3462);
3463 }
3464}
3465
3466
3467// Return .new predicate version for an instruction.
3468int HexagonInstrInfo::getDotNewPredOp(const MachineInstr *MI,
3469 const MachineBranchProbabilityInfo *MBPI) const {
3470 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode());
3471 if (NewOpcode >= 0) // Valid predicate new instruction
3472 return NewOpcode;
3473
3474 switch (MI->getOpcode()) {
3475 // Condtional Jumps
3476 case Hexagon::J2_jumpt:
3477 case Hexagon::J2_jumpf:
3478 return getDotNewPredJumpOp(MI, MBPI);
3479
3480 default:
3481 assert(0 && "Unknown .new type")((0 && "Unknown .new type") ? static_cast<void>
(0) : __assert_fail ("0 && \"Unknown .new type\"", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3481, __PRETTY_FUNCTION__));
3482 }
3483 return 0;
3484}
3485
3486
3487int HexagonInstrInfo::getDotOldOp(const int opc) const {
3488 int NewOp = opc;
3489 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form
3490 NewOp = Hexagon::getPredOldOpcode(NewOp);
3491 assert(NewOp >= 0 &&((NewOp >= 0 && "Couldn't change predicate new instruction to its old form."
) ? static_cast<void> (0) : __assert_fail ("NewOp >= 0 && \"Couldn't change predicate new instruction to its old form.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3492, __PRETTY_FUNCTION__))
3492 "Couldn't change predicate new instruction to its old form.")((NewOp >= 0 && "Couldn't change predicate new instruction to its old form."
) ? static_cast<void> (0) : __assert_fail ("NewOp >= 0 && \"Couldn't change predicate new instruction to its old form.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3492, __PRETTY_FUNCTION__));
3493 }
3494
3495 if (isNewValueStore(NewOp)) { // Convert into non-new-value format
3496 NewOp = Hexagon::getNonNVStore(NewOp);
3497 assert(NewOp >= 0 && "Couldn't change new-value store to its old form.")((NewOp >= 0 && "Couldn't change new-value store to its old form."
) ? static_cast<void> (0) : __assert_fail ("NewOp >= 0 && \"Couldn't change new-value store to its old form.\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3497, __PRETTY_FUNCTION__));
3498 }
3499 return NewOp;
3500}
3501
3502
3503// See if instruction could potentially be a duplex candidate.
3504// If so, return its group. Zero otherwise.
3505HexagonII::SubInstructionGroup HexagonInstrInfo::getDuplexCandidateGroup(
3506 const MachineInstr *MI) const {
3507 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
3508 auto &HRI = getRegisterInfo();
3509
3510 switch (MI->getOpcode()) {
3511 default:
3512 return HexagonII::HSIG_None;
3513 //
3514 // Group L1:
3515 //
3516 // Rd = memw(Rs+#u4:2)
3517 // Rd = memub(Rs+#u4:0)
3518 case Hexagon::L2_loadri_io:
3519 DstReg = MI->getOperand(0).getReg();
3520 SrcReg = MI->getOperand(1).getReg();
3521 // Special case this one from Group L2.
3522 // Rd = memw(r29+#u5:2)
3523 if (isIntRegForSubInst(DstReg)) {
3524 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3525 HRI.getStackRegister() == SrcReg &&
3526 MI->getOperand(2).isImm() &&
3527 isShiftedUInt<5,2>(MI->getOperand(2).getImm()))
3528 return HexagonII::HSIG_L2;
3529 // Rd = memw(Rs+#u4:2)
3530 if (isIntRegForSubInst(SrcReg) &&
3531 (MI->getOperand(2).isImm() &&
3532 isShiftedUInt<4,2>(MI->getOperand(2).getImm())))
3533 return HexagonII::HSIG_L1;
3534 }
3535 break;
3536 case Hexagon::L2_loadrub_io:
3537 // Rd = memub(Rs+#u4:0)
3538 DstReg = MI->getOperand(0).getReg();
3539 SrcReg = MI->getOperand(1).getReg();
3540 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3541 MI->getOperand(2).isImm() && isUInt<4>(MI->getOperand(2).getImm()))
3542 return HexagonII::HSIG_L1;
3543 break;
3544 //
3545 // Group L2:
3546 //
3547 // Rd = memh/memuh(Rs+#u3:1)
3548 // Rd = memb(Rs+#u3:0)
3549 // Rd = memw(r29+#u5:2) - Handled above.
3550 // Rdd = memd(r29+#u5:3)
3551 // deallocframe
3552 // [if ([!]p0[.new])] dealloc_return
3553 // [if ([!]p0[.new])] jumpr r31
3554 case Hexagon::L2_loadrh_io:
3555 case Hexagon::L2_loadruh_io:
3556 // Rd = memh/memuh(Rs+#u3:1)
3557 DstReg = MI->getOperand(0).getReg();
3558 SrcReg = MI->getOperand(1).getReg();
3559 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3560 MI->getOperand(2).isImm() &&
3561 isShiftedUInt<3,1>(MI->getOperand(2).getImm()))
3562 return HexagonII::HSIG_L2;
3563 break;
3564 case Hexagon::L2_loadrb_io:
3565 // Rd = memb(Rs+#u3:0)
3566 DstReg = MI->getOperand(0).getReg();
3567 SrcReg = MI->getOperand(1).getReg();
3568 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3569 MI->getOperand(2).isImm() &&
3570 isUInt<3>(MI->getOperand(2).getImm()))
3571 return HexagonII::HSIG_L2;
3572 break;
3573 case Hexagon::L2_loadrd_io:
3574 // Rdd = memd(r29+#u5:3)
3575 DstReg = MI->getOperand(0).getReg();
3576 SrcReg = MI->getOperand(1).getReg();
3577 if (isDblRegForSubInst(DstReg, HRI) &&
3578 Hexagon::IntRegsRegClass.contains(SrcReg) &&
3579 HRI.getStackRegister() == SrcReg &&
3580 MI->getOperand(2).isImm() &&
3581 isShiftedUInt<5,3>(MI->getOperand(2).getImm()))
3582 return HexagonII::HSIG_L2;
3583 break;
3584 // dealloc_return is not documented in Hexagon Manual, but marked
3585 // with A_SUBINSN attribute in iset_v4classic.py.
3586 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4:
3587 case Hexagon::L4_return:
3588 case Hexagon::L2_deallocframe:
3589 return HexagonII::HSIG_L2;
3590 case Hexagon::EH_RETURN_JMPR:
3591 case Hexagon::JMPret :
3592 // jumpr r31
3593 // Actual form JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,internal>.
3594 DstReg = MI->getOperand(0).getReg();
3595 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))
3596 return HexagonII::HSIG_L2;
3597 break;
3598 case Hexagon::JMPrett:
3599 case Hexagon::JMPretf:
3600 case Hexagon::JMPrettnewpt:
3601 case Hexagon::JMPretfnewpt :
3602 case Hexagon::JMPrettnew :
3603 case Hexagon::JMPretfnew :
3604 DstReg = MI->getOperand(1).getReg();
3605 SrcReg = MI->getOperand(0).getReg();
3606 // [if ([!]p0[.new])] jumpr r31
3607 if ((Hexagon::PredRegsRegClass.contains(SrcReg) &&
3608 (Hexagon::P0 == SrcReg)) &&
3609 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)))
3610 return HexagonII::HSIG_L2;
3611 break;
3612 case Hexagon::L4_return_t :
3613 case Hexagon::L4_return_f :
3614 case Hexagon::L4_return_tnew_pnt :
3615 case Hexagon::L4_return_fnew_pnt :
3616 case Hexagon::L4_return_tnew_pt :
3617 case Hexagon::L4_return_fnew_pt :
3618 // [if ([!]p0[.new])] dealloc_return
3619 SrcReg = MI->getOperand(0).getReg();
3620 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg))
3621 return HexagonII::HSIG_L2;
3622 break;
3623 //
3624 // Group S1:
3625 //
3626 // memw(Rs+#u4:2) = Rt
3627 // memb(Rs+#u4:0) = Rt
3628 case Hexagon::S2_storeri_io:
3629 // Special case this one from Group S2.
3630 // memw(r29+#u5:2) = Rt
3631 Src1Reg = MI->getOperand(0).getReg();
3632 Src2Reg = MI->getOperand(2).getReg();
3633 if (Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3634 isIntRegForSubInst(Src2Reg) &&
3635 HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
3636 isShiftedUInt<5,2>(MI->getOperand(1).getImm()))
3637 return HexagonII::HSIG_S2;
3638 // memw(Rs+#u4:2) = Rt
3639 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3640 MI->getOperand(1).isImm() &&
3641 isShiftedUInt<4,2>(MI->getOperand(1).getImm()))
3642 return HexagonII::HSIG_S1;
3643 break;
3644 case Hexagon::S2_storerb_io:
3645 // memb(Rs+#u4:0) = Rt
3646 Src1Reg = MI->getOperand(0).getReg();
3647 Src2Reg = MI->getOperand(2).getReg();
3648 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3649 MI->getOperand(1).isImm() && isUInt<4>(MI->getOperand(1).getImm()))
3650 return HexagonII::HSIG_S1;
3651 break;
3652 //
3653 // Group S2:
3654 //
3655 // memh(Rs+#u3:1) = Rt
3656 // memw(r29+#u5:2) = Rt
3657 // memd(r29+#s6:3) = Rtt
3658 // memw(Rs+#u4:2) = #U1
3659 // memb(Rs+#u4) = #U1
3660 // allocframe(#u5:3)
3661 case Hexagon::S2_storerh_io:
3662 // memh(Rs+#u3:1) = Rt
3663 Src1Reg = MI->getOperand(0).getReg();
3664 Src2Reg = MI->getOperand(2).getReg();
3665 if (isIntRegForSubInst(Src1Reg) && isIntRegForSubInst(Src2Reg) &&
3666 MI->getOperand(1).isImm() &&
3667 isShiftedUInt<3,1>(MI->getOperand(1).getImm()))
3668 return HexagonII::HSIG_S1;
3669 break;
3670 case Hexagon::S2_storerd_io:
3671 // memd(r29+#s6:3) = Rtt
3672 Src1Reg = MI->getOperand(0).getReg();
3673 Src2Reg = MI->getOperand(2).getReg();
3674 if (isDblRegForSubInst(Src2Reg, HRI) &&
3675 Hexagon::IntRegsRegClass.contains(Src1Reg) &&
3676 HRI.getStackRegister() == Src1Reg && MI->getOperand(1).isImm() &&
3677 isShiftedInt<6,3>(MI->getOperand(1).getImm()))
3678 return HexagonII::HSIG_S2;
3679 break;
3680 case Hexagon::S4_storeiri_io:
3681 // memw(Rs+#u4:2) = #U1
3682 Src1Reg = MI->getOperand(0).getReg();
3683 if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
3684 isShiftedUInt<4,2>(MI->getOperand(1).getImm()) &&
3685 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
3686 return HexagonII::HSIG_S2;
3687 break;
3688 case Hexagon::S4_storeirb_io:
3689 // memb(Rs+#u4) = #U1
3690 Src1Reg = MI->getOperand(0).getReg();
3691 if (isIntRegForSubInst(Src1Reg) && MI->getOperand(1).isImm() &&
3692 isUInt<4>(MI->getOperand(1).getImm()) && MI->getOperand(2).isImm() &&
3693 MI->getOperand(2).isImm() && isUInt<1>(MI->getOperand(2).getImm()))
3694 return HexagonII::HSIG_S2;
3695 break;
3696 case Hexagon::S2_allocframe:
3697 if (MI->getOperand(0).isImm() &&
3698 isShiftedUInt<5,3>(MI->getOperand(0).getImm()))
3699 return HexagonII::HSIG_S1;
3700 break;
3701 //
3702 // Group A:
3703 //
3704 // Rx = add(Rx,#s7)
3705 // Rd = Rs
3706 // Rd = #u6
3707 // Rd = #-1
3708 // if ([!]P0[.new]) Rd = #0
3709 // Rd = add(r29,#u6:2)
3710 // Rx = add(Rx,Rs)
3711 // P0 = cmp.eq(Rs,#u2)
3712 // Rdd = combine(#0,Rs)
3713 // Rdd = combine(Rs,#0)
3714 // Rdd = combine(#u2,#U2)
3715 // Rd = add(Rs,#1)
3716 // Rd = add(Rs,#-1)
3717 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3718 // Rd = and(Rs,#1)
3719 case Hexagon::A2_addi:
3720 DstReg = MI->getOperand(0).getReg();
3721 SrcReg = MI->getOperand(1).getReg();
3722 if (isIntRegForSubInst(DstReg)) {
3723 // Rd = add(r29,#u6:2)
3724 if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
3725 HRI.getStackRegister() == SrcReg && MI->getOperand(2).isImm() &&
3726 isShiftedUInt<6,2>(MI->getOperand(2).getImm()))
3727 return HexagonII::HSIG_A;
3728 // Rx = add(Rx,#s7)
3729 if ((DstReg == SrcReg) && MI->getOperand(2).isImm() &&
3730 isInt<7>(MI->getOperand(2).getImm()))
3731 return HexagonII::HSIG_A;
3732 // Rd = add(Rs,#1)
3733 // Rd = add(Rs,#-1)
3734 if (isIntRegForSubInst(SrcReg) && MI->getOperand(2).isImm() &&
3735 ((MI->getOperand(2).getImm() == 1) ||
3736 (MI->getOperand(2).getImm() == -1)))
3737 return HexagonII::HSIG_A;
3738 }
3739 break;
3740 case Hexagon::A2_add:
3741 // Rx = add(Rx,Rs)
3742 DstReg = MI->getOperand(0).getReg();
3743 Src1Reg = MI->getOperand(1).getReg();
3744 Src2Reg = MI->getOperand(2).getReg();
3745 if (isIntRegForSubInst(DstReg) && (DstReg == Src1Reg) &&
3746 isIntRegForSubInst(Src2Reg))
3747 return HexagonII::HSIG_A;
3748 break;
3749 case Hexagon::A2_andir:
3750 // Same as zxtb.
3751 // Rd16=and(Rs16,#255)
3752 // Rd16=and(Rs16,#1)
3753 DstReg = MI->getOperand(0).getReg();
3754 SrcReg = MI->getOperand(1).getReg();
3755 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg) &&
3756 MI->getOperand(2).isImm() &&
3757 ((MI->getOperand(2).getImm() == 1) ||
3758 (MI->getOperand(2).getImm() == 255)))
3759 return HexagonII::HSIG_A;
3760 break;
3761 case Hexagon::A2_tfr:
3762 // Rd = Rs
3763 DstReg = MI->getOperand(0).getReg();
3764 SrcReg = MI->getOperand(1).getReg();
3765 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3766 return HexagonII::HSIG_A;
3767 break;
3768 case Hexagon::A2_tfrsi:
3769 // Rd = #u6
3770 // Do not test for #u6 size since the const is getting extended
3771 // regardless and compound could be formed.
3772 // Rd = #-1
3773 DstReg = MI->getOperand(0).getReg();
3774 if (isIntRegForSubInst(DstReg))
3775 return HexagonII::HSIG_A;
3776 break;
3777 case Hexagon::C2_cmoveit:
3778 case Hexagon::C2_cmovenewit:
3779 case Hexagon::C2_cmoveif:
3780 case Hexagon::C2_cmovenewif:
3781 // if ([!]P0[.new]) Rd = #0
3782 // Actual form:
3783 // %R16<def> = C2_cmovenewit %P0<internal>, 0, %R16<imp-use,undef>;
3784 DstReg = MI->getOperand(0).getReg();
3785 SrcReg = MI->getOperand(1).getReg();
3786 if (isIntRegForSubInst(DstReg) &&
3787 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg &&
3788 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0)
3789 return HexagonII::HSIG_A;
3790 break;
3791 case Hexagon::C2_cmpeqi:
3792 // P0 = cmp.eq(Rs,#u2)
3793 DstReg = MI->getOperand(0).getReg();
3794 SrcReg = MI->getOperand(1).getReg();
3795 if (Hexagon::PredRegsRegClass.contains(DstReg) &&
3796 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) &&
3797 MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm()))
3798 return HexagonII::HSIG_A;
3799 break;
3800 case Hexagon::A2_combineii:
3801 case Hexagon::A4_combineii:
3802 // Rdd = combine(#u2,#U2)
3803 DstReg = MI->getOperand(0).getReg();
3804 if (isDblRegForSubInst(DstReg, HRI) &&
3805 ((MI->getOperand(1).isImm() && isUInt<2>(MI->getOperand(1).getImm())) ||
3806 (MI->getOperand(1).isGlobal() &&
3807 isUInt<2>(MI->getOperand(1).getOffset()))) &&
3808 ((MI->getOperand(2).isImm() && isUInt<2>(MI->getOperand(2).getImm())) ||
3809 (MI->getOperand(2).isGlobal() &&
3810 isUInt<2>(MI->getOperand(2).getOffset()))))
3811 return HexagonII::HSIG_A;
3812 break;
3813 case Hexagon::A4_combineri:
3814 // Rdd = combine(Rs,#0)
3815 DstReg = MI->getOperand(0).getReg();
3816 SrcReg = MI->getOperand(1).getReg();
3817 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3818 ((MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) ||
3819 (MI->getOperand(2).isGlobal() && MI->getOperand(2).getOffset() == 0)))
3820 return HexagonII::HSIG_A;
3821 break;
3822 case Hexagon::A4_combineir:
3823 // Rdd = combine(#0,Rs)
3824 DstReg = MI->getOperand(0).getReg();
3825 SrcReg = MI->getOperand(2).getReg();
3826 if (isDblRegForSubInst(DstReg, HRI) && isIntRegForSubInst(SrcReg) &&
3827 ((MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) ||
3828 (MI->getOperand(1).isGlobal() && MI->getOperand(1).getOffset() == 0)))
3829 return HexagonII::HSIG_A;
3830 break;
3831 case Hexagon::A2_sxtb:
3832 case Hexagon::A2_sxth:
3833 case Hexagon::A2_zxtb:
3834 case Hexagon::A2_zxth:
3835 // Rd = sxth/sxtb/zxtb/zxth(Rs)
3836 DstReg = MI->getOperand(0).getReg();
3837 SrcReg = MI->getOperand(1).getReg();
3838 if (isIntRegForSubInst(DstReg) && isIntRegForSubInst(SrcReg))
3839 return HexagonII::HSIG_A;
3840 break;
3841 }
3842
3843 return HexagonII::HSIG_None;
3844}
3845
3846
3847short HexagonInstrInfo::getEquivalentHWInstr(const MachineInstr *MI) const {
3848 return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Real);
3849}
3850
3851
3852// Return first non-debug instruction in the basic block.
3853MachineInstr *HexagonInstrInfo::getFirstNonDbgInst(MachineBasicBlock *BB)
3854 const {
3855 for (auto MII = BB->instr_begin(), End = BB->instr_end(); MII != End; MII++) {
3856 MachineInstr *MI = &*MII;
3857 if (MI->isDebugValue())
3858 continue;
3859 return MI;
3860 }
3861 return nullptr;
3862}
3863
3864
3865unsigned HexagonInstrInfo::getInstrTimingClassLatency(
3866 const InstrItineraryData *ItinData, const MachineInstr *MI) const {
3867 // Default to one cycle for no itinerary. However, an "empty" itinerary may
3868 // still have a MinLatency property, which getStageLatency checks.
3869 if (!ItinData)
3870 return getInstrLatency(ItinData, MI);
3871
3872 // Get the latency embedded in the itinerary. If we're not using timing class
3873 // latencies or if we using BSB scheduling, then restrict the maximum latency
3874 // to 1 (that is, either 0 or 1).
3875 if (MI->isTransient())
3876 return 0;
3877 unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass());
3878 if (!EnableTimingClassLatency ||
3879 MI->getParent()->getParent()->getSubtarget<HexagonSubtarget>().
3880 useBSBScheduling())
3881 if (Latency > 1)
3882 Latency = 1;
3883 return Latency;
3884}
3885
3886
3887// inverts the predication logic.
3888// p -> NotP
3889// NotP -> P
3890bool HexagonInstrInfo::getInvertedPredSense(
3891 SmallVectorImpl<MachineOperand> &Cond) const {
3892 if (Cond.empty())
3893 return false;
3894 unsigned Opc = getInvertedPredicatedOpcode(Cond[0].getImm());
3895 Cond[0].setImm(Opc);
3896 return true;
3897}
3898
3899
3900unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
3901 int InvPredOpcode;
3902 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc)
3903 : Hexagon::getTruePredOpcode(Opc);
3904 if (InvPredOpcode >= 0) // Valid instruction with the inverted predicate.
3905 return InvPredOpcode;
3906
3907 llvm_unreachable("Unexpected predicated instruction")::llvm::llvm_unreachable_internal("Unexpected predicated instruction"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3907);
3908}
3909
3910
3911// Returns the max value that doesn't need to be extended.
3912int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
3913 const uint64_t F = MI->getDesc().TSFlags;
3914 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3915 & HexagonII::ExtentSignedMask;
3916 unsigned bits = (F >> HexagonII::ExtentBitsPos)
3917 & HexagonII::ExtentBitsMask;
3918
3919 if (isSigned) // if value is signed
3920 return ~(-1U << (bits - 1));
3921 else
3922 return ~(-1U << bits);
3923}
3924
3925
3926unsigned HexagonInstrInfo::getMemAccessSize(const MachineInstr* MI) const {
3927 const uint64_t F = MI->getDesc().TSFlags;
3928 return (F >> HexagonII::MemAccessSizePos) & HexagonII::MemAccesSizeMask;
3929}
3930
3931
3932// Returns the min value that doesn't need to be extended.
3933int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
3934 const uint64_t F = MI->getDesc().TSFlags;
3935 unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
3936 & HexagonII::ExtentSignedMask;
3937 unsigned bits = (F >> HexagonII::ExtentBitsPos)
3938 & HexagonII::ExtentBitsMask;
3939
3940 if (isSigned) // if value is signed
3941 return -1U << (bits - 1);
3942 else
3943 return 0;
3944}
3945
3946
3947// Returns opcode of the non-extended equivalent instruction.
3948short HexagonInstrInfo::getNonExtOpcode(const MachineInstr *MI) const {
3949 // Check if the instruction has a register form that uses register in place
3950 // of the extended operand, if so return that as the non-extended form.
3951 short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
3952 if (NonExtOpcode >= 0)
3953 return NonExtOpcode;
3954
3955 if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
3956 // Check addressing mode and retrieve non-ext equivalent instruction.
3957 switch (getAddrMode(MI)) {
3958 case HexagonII::Absolute :
3959 return Hexagon::getBaseWithImmOffset(MI->getOpcode());
3960 case HexagonII::BaseImmOffset :
3961 return Hexagon::getBaseWithRegOffset(MI->getOpcode());
3962 case HexagonII::BaseLongOffset:
3963 return Hexagon::getRegShlForm(MI->getOpcode());
3964
3965 default:
3966 return -1;
3967 }
3968 }
3969 return -1;
3970}
3971
3972
3973bool HexagonInstrInfo::getPredReg(ArrayRef<MachineOperand> Cond,
3974 unsigned &PredReg, unsigned &PredRegPos, unsigned &PredRegFlags) const {
3975 if (Cond.empty())
3976 return false;
3977 assert(Cond.size() == 2)((Cond.size() == 2) ? static_cast<void> (0) : __assert_fail
("Cond.size() == 2", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 3977, __PRETTY_FUNCTION__));
3978 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) {
3979 DEBUG(dbgs() << "No predregs for new-value jumps/endloop")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "No predregs for new-value jumps/endloop"
; } } while (0);
3980 return false;
3981 }
3982 PredReg = Cond[1].getReg();
3983 PredRegPos = 1;
3984 // See IfConversion.cpp why we add RegState::Implicit | RegState::Undef
3985 PredRegFlags = 0;
3986 if (Cond[1].isImplicit())
3987 PredRegFlags = RegState::Implicit;
3988 if (Cond[1].isUndef())
3989 PredRegFlags |= RegState::Undef;
3990 return true;
3991}
3992
3993
3994short HexagonInstrInfo::getPseudoInstrPair(const MachineInstr *MI) const {
3995 return Hexagon::getRealHWInstr(MI->getOpcode(), Hexagon::InstrType_Pseudo);
3996}
3997
3998
3999short HexagonInstrInfo::getRegForm(const MachineInstr *MI) const {
4000 return Hexagon::getRegForm(MI->getOpcode());
4001}
4002
4003
4004// Return the number of bytes required to encode the instruction.
4005// Hexagon instructions are fixed length, 4 bytes, unless they
4006// use a constant extender, which requires another 4 bytes.
4007// For debug instructions and prolog labels, return 0.
4008unsigned HexagonInstrInfo::getSize(const MachineInstr *MI) const {
4009 if (MI->isDebugValue() || MI->isPosition())
4010 return 0;
4011
4012 unsigned Size = MI->getDesc().getSize();
4013 if (!Size)
4014 // Assume the default insn size in case it cannot be determined
4015 // for whatever reason.
4016 Size = HEXAGON_INSTR_SIZE4;
4017
4018 if (isConstExtended(MI) || isExtended(MI))
4019 Size += HEXAGON_INSTR_SIZE4;
4020
4021 // Try and compute number of instructions in asm.
4022 if (BranchRelaxAsmLarge && MI->getOpcode() == Hexagon::INLINEASM) {
4023 const MachineBasicBlock &MBB = *MI->getParent();
4024 const MachineFunction *MF = MBB.getParent();
4025 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
4026
4027 // Count the number of register definitions to find the asm string.
4028 unsigned NumDefs = 0;
4029 for (; MI->getOperand(NumDefs).isReg() && MI->getOperand(NumDefs).isDef();
4030 ++NumDefs)
4031 assert(NumDefs != MI->getNumOperands()-2 && "No asm string?")((NumDefs != MI->getNumOperands()-2 && "No asm string?"
) ? static_cast<void> (0) : __assert_fail ("NumDefs != MI->getNumOperands()-2 && \"No asm string?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4031, __PRETTY_FUNCTION__));
4032
4033 assert(MI->getOperand(NumDefs).isSymbol() && "No asm string?")((MI->getOperand(NumDefs).isSymbol() && "No asm string?"
) ? static_cast<void> (0) : __assert_fail ("MI->getOperand(NumDefs).isSymbol() && \"No asm string?\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4033, __PRETTY_FUNCTION__));
4034 // Disassemble the AsmStr and approximate number of instructions.
4035 const char *AsmStr = MI->getOperand(NumDefs).getSymbolName();
4036 Size = getInlineAsmLength(AsmStr, *MAI);
4037 }
4038
4039 return Size;
4040}
4041
4042
4043uint64_t HexagonInstrInfo::getType(const MachineInstr* MI) const {
4044 const uint64_t F = MI->getDesc().TSFlags;
4045 return (F >> HexagonII::TypePos) & HexagonII::TypeMask;
4046}
4047
4048
4049unsigned HexagonInstrInfo::getUnits(const MachineInstr* MI) const {
4050 const TargetSubtargetInfo &ST = MI->getParent()->getParent()->getSubtarget();
4051 const InstrItineraryData &II = *ST.getInstrItineraryData();
4052 const InstrStage &IS = *II.beginStage(MI->getDesc().getSchedClass());
4053
4054 return IS.getUnits();
4055}
4056
4057
4058unsigned HexagonInstrInfo::getValidSubTargets(const unsigned Opcode) const {
4059 const uint64_t F = get(Opcode).TSFlags;
4060 return (F >> HexagonII::validSubTargetPos) & HexagonII::validSubTargetMask;
4061}
4062
4063
4064// Calculate size of the basic block without debug instructions.
4065unsigned HexagonInstrInfo::nonDbgBBSize(const MachineBasicBlock *BB) const {
4066 return nonDbgMICount(BB->instr_begin(), BB->instr_end());
4067}
4068
4069
4070unsigned HexagonInstrInfo::nonDbgBundleSize(
4071 MachineBasicBlock::const_iterator BundleHead) const {
4072 assert(BundleHead->isBundle() && "Not a bundle header")((BundleHead->isBundle() && "Not a bundle header")
? static_cast<void> (0) : __assert_fail ("BundleHead->isBundle() && \"Not a bundle header\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4072, __PRETTY_FUNCTION__));
4073 auto MII = BundleHead.getInstrIterator();
4074 // Skip the bundle header.
4075 return nonDbgMICount(++MII, getBundleEnd(*BundleHead));
4076}
4077
4078
4079/// immediateExtend - Changes the instruction in place to one using an immediate
4080/// extender.
4081void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
4082 assert((isExtendable(MI)||isConstExtended(MI)) &&(((isExtendable(MI)||isConstExtended(MI)) && "Instruction must be extendable"
) ? static_cast<void> (0) : __assert_fail ("(isExtendable(MI)||isConstExtended(MI)) && \"Instruction must be extendable\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4083, __PRETTY_FUNCTION__))
4083 "Instruction must be extendable")(((isExtendable(MI)||isConstExtended(MI)) && "Instruction must be extendable"
) ? static_cast<void> (0) : __assert_fail ("(isExtendable(MI)||isConstExtended(MI)) && \"Instruction must be extendable\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4083, __PRETTY_FUNCTION__));
4084 // Find which operand is extendable.
4085 short ExtOpNum = getCExtOpNum(MI);
4086 MachineOperand &MO = MI->getOperand(ExtOpNum);
4087 // This needs to be something we understand.
4088 assert((MO.isMBB() || MO.isImm()) &&(((MO.isMBB() || MO.isImm()) && "Branch with unknown extendable field type"
) ? static_cast<void> (0) : __assert_fail ("(MO.isMBB() || MO.isImm()) && \"Branch with unknown extendable field type\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4089, __PRETTY_FUNCTION__))
4089 "Branch with unknown extendable field type")(((MO.isMBB() || MO.isImm()) && "Branch with unknown extendable field type"
) ? static_cast<void> (0) : __assert_fail ("(MO.isMBB() || MO.isImm()) && \"Branch with unknown extendable field type\""
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4089, __PRETTY_FUNCTION__));
4090 // Mark given operand as extended.
4091 MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
4092}
4093
4094
4095bool HexagonInstrInfo::invertAndChangeJumpTarget(
4096 MachineInstr* MI, MachineBasicBlock* NewTarget) const {
4097 DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
<< NewTarget->getNumber(); MI->dump();; } } while
(0)
4098 << NewTarget->getNumber(); MI->dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
<< NewTarget->getNumber(); MI->dump();; } } while
(0);
4099 assert(MI->isBranch())((MI->isBranch()) ? static_cast<void> (0) : __assert_fail
("MI->isBranch()", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4099, __PRETTY_FUNCTION__));
4100 unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode());
4101 int TargetPos = MI->getNumOperands() - 1;
4102 // In general branch target is the last operand,
4103 // but some implicit defs added at the end might change it.
4104 while ((TargetPos > -1) && !MI->getOperand(TargetPos).isMBB())
4105 --TargetPos;
4106 assert((TargetPos >= 0) && MI->getOperand(TargetPos).isMBB())(((TargetPos >= 0) && MI->getOperand(TargetPos)
.isMBB()) ? static_cast<void> (0) : __assert_fail ("(TargetPos >= 0) && MI->getOperand(TargetPos).isMBB()"
, "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4106, __PRETTY_FUNCTION__));
4107 MI->getOperand(TargetPos).setMBB(NewTarget);
4108 if (EnableBranchPrediction && isPredicatedNew(*MI)) {
4109 NewOpcode = reversePrediction(NewOpcode);
4110 }
4111 MI->setDesc(get(NewOpcode));
4112 return true;
4113}
4114
4115
4116void HexagonInstrInfo::genAllInsnTimingClasses(MachineFunction &MF) const {
4117 /* +++ The code below is used to generate complete set of Hexagon Insn +++ */
4118 MachineFunction::iterator A = MF.begin();
4119 MachineBasicBlock &B = *A;
4120 MachineBasicBlock::iterator I = B.begin();
4121 MachineInstr *MI = &*I;
4122 DebugLoc DL = MI->getDebugLoc();
4123 MachineInstr *NewMI;
4124
4125 for (unsigned insn = TargetOpcode::GENERIC_OP_END+1;
4126 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) {
4127 NewMI = BuildMI(B, MI, DL, get(insn));
4128 DEBUG(dbgs() << "\n" << getName(NewMI->getOpcode()) <<do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\n" << getName
(NewMI->getOpcode()) << " Class: " << NewMI->
getDesc().getSchedClass(); } } while (0)
4129 " Class: " << NewMI->getDesc().getSchedClass())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\n" << getName
(NewMI->getOpcode()) << " Class: " << NewMI->
getDesc().getSchedClass(); } } while (0);
4130 NewMI->eraseFromParent();
4131 }
4132 /* --- The code above is used to generate complete set of Hexagon Insn --- */
4133}
4134
4135
4136// inverts the predication logic.
4137// p -> NotP
4138// NotP -> P
4139bool HexagonInstrInfo::reversePredSense(MachineInstr* MI) const {
4140 DEBUG(dbgs() << "\nTrying to reverse pred. sense of:"; MI->dump())do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-instrinfo")) { dbgs() << "\nTrying to reverse pred. sense of:"
; MI->dump(); } } while (0);
4141 MI->setDesc(get(getInvertedPredicatedOpcode(MI->getOpcode())));
4142 return true;
4143}
4144
4145
4146// Reverse the branch prediction.
4147unsigned HexagonInstrInfo::reversePrediction(unsigned Opcode) const {
4148 int PredRevOpcode = -1;
4149 if (isPredictedTaken(Opcode))
4150 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode);
4151 else
4152 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode);
4153 assert(PredRevOpcode > 0)((PredRevOpcode > 0) ? static_cast<void> (0) : __assert_fail
("PredRevOpcode > 0", "/tmp/buildd/llvm-toolchain-snapshot-3.9~svn267387/lib/Target/Hexagon/HexagonInstrInfo.cpp"
, 4153, __PRETTY_FUNCTION__));
4154 return PredRevOpcode;
4155}
4156
4157
4158// TODO: Add more rigorous validation.
4159bool HexagonInstrInfo::validateBranchCond(const ArrayRef<MachineOperand> &Cond)
4160 const {
4161 return Cond.empty() || (Cond[0].isImm() && (Cond.size() != 1));
4162}
4163