Bug Summary

File:lib/Target/Hexagon/HexagonStoreWidening.cpp
Warning:line 341, column 32
Value stored to 'S2' during its initialization is never read

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name HexagonStoreWidening.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn338205/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/Target/Hexagon -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-29-043837-17923-1 -x c++ /build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp -faddrsig
1//===- HexagonStoreWidening.cpp -------------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9// Replace sequences of "narrow" stores to adjacent memory locations with
10// a fewer "wide" stores that have the same effect.
11// For example, replace:
12// S4_storeirb_io %100, 0, 0 ; store-immediate-byte
13// S4_storeirb_io %100, 1, 0 ; store-immediate-byte
14// with
15// S4_storeirh_io %100, 0, 0 ; store-immediate-halfword
16// The above is the general idea. The actual cases handled by the code
17// may be a bit more complex.
18// The purpose of this pass is to reduce the number of outstanding stores,
19// or as one could say, "reduce store queue pressure". Also, wide stores
20// mean fewer stores, and since there are only two memory instructions allowed
21// per packet, it also means fewer packets, and ultimately fewer cycles.
22//===---------------------------------------------------------------------===//
23
24#define DEBUG_TYPE"hexagon-widen-stores" "hexagon-widen-stores"
25
26#include "HexagonInstrInfo.h"
27#include "HexagonRegisterInfo.h"
28#include "HexagonSubtarget.h"
29#include "llvm/ADT/SmallPtrSet.h"
30#include "llvm/Analysis/AliasAnalysis.h"
31#include "llvm/Analysis/MemoryLocation.h"
32#include "llvm/CodeGen/MachineBasicBlock.h"
33#include "llvm/CodeGen/MachineFunction.h"
34#include "llvm/CodeGen/MachineFunctionPass.h"
35#include "llvm/CodeGen/MachineInstr.h"
36#include "llvm/CodeGen/MachineInstrBuilder.h"
37#include "llvm/CodeGen/MachineMemOperand.h"
38#include "llvm/CodeGen/MachineOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/IR/DebugLoc.h"
41#include "llvm/MC/MCInstrDesc.h"
42#include "llvm/Pass.h"
43#include "llvm/Support/Debug.h"
44#include "llvm/Support/ErrorHandling.h"
45#include "llvm/Support/MathExtras.h"
46#include "llvm/Support/raw_ostream.h"
47#include <algorithm>
48#include <cassert>
49#include <cstdint>
50#include <iterator>
51#include <vector>
52
53using namespace llvm;
54
55namespace llvm {
56
57FunctionPass *createHexagonStoreWidening();
58void initializeHexagonStoreWideningPass(PassRegistry&);
59
60} // end namespace llvm
61
62namespace {
63
64 struct HexagonStoreWidening : public MachineFunctionPass {
65 const HexagonInstrInfo *TII;
66 const HexagonRegisterInfo *TRI;
67 const MachineRegisterInfo *MRI;
68 AliasAnalysis *AA;
69 MachineFunction *MF;
70
71 public:
72 static char ID;
73
74 HexagonStoreWidening() : MachineFunctionPass(ID) {
75 initializeHexagonStoreWideningPass(*PassRegistry::getPassRegistry());
76 }
77
78 bool runOnMachineFunction(MachineFunction &MF) override;
79
80 StringRef getPassName() const override { return "Hexagon Store Widening"; }
81
82 void getAnalysisUsage(AnalysisUsage &AU) const override {
83 AU.addRequired<AAResultsWrapperPass>();
84 AU.addPreserved<AAResultsWrapperPass>();
85 MachineFunctionPass::getAnalysisUsage(AU);
86 }
87
88 static bool handledStoreType(const MachineInstr *MI);
89
90 private:
91 static const int MaxWideSize = 4;
92
93 using InstrGroup = std::vector<MachineInstr *>;
94 using InstrGroupList = std::vector<InstrGroup>;
95
96 bool instrAliased(InstrGroup &Stores, const MachineMemOperand &MMO);
97 bool instrAliased(InstrGroup &Stores, const MachineInstr *MI);
98 void createStoreGroup(MachineInstr *BaseStore, InstrGroup::iterator Begin,
99 InstrGroup::iterator End, InstrGroup &Group);
100 void createStoreGroups(MachineBasicBlock &MBB,
101 InstrGroupList &StoreGroups);
102 bool processBasicBlock(MachineBasicBlock &MBB);
103 bool processStoreGroup(InstrGroup &Group);
104 bool selectStores(InstrGroup::iterator Begin, InstrGroup::iterator End,
105 InstrGroup &OG, unsigned &TotalSize, unsigned MaxSize);
106 bool createWideStores(InstrGroup &OG, InstrGroup &NG, unsigned TotalSize);
107 bool replaceStores(InstrGroup &OG, InstrGroup &NG);
108 bool storesAreAdjacent(const MachineInstr *S1, const MachineInstr *S2);
109 };
110
111} // end anonymous namespace
112
113char HexagonStoreWidening::ID = 0;
114
115INITIALIZE_PASS_BEGIN(HexagonStoreWidening, "hexagon-widen-stores",static void *initializeHexagonStoreWideningPassOnce(PassRegistry
&Registry) {
116 "Hexason Store Widening", false, false)static void *initializeHexagonStoreWideningPassOnce(PassRegistry
&Registry) {
117INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)initializeAAResultsWrapperPassPass(Registry);
118INITIALIZE_PASS_END(HexagonStoreWidening, "hexagon-widen-stores",PassInfo *PI = new PassInfo( "Hexagon Store Widening", "hexagon-widen-stores"
, &HexagonStoreWidening::ID, PassInfo::NormalCtor_t(callDefaultCtor
<HexagonStoreWidening>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeHexagonStoreWideningPassFlag
; void llvm::initializeHexagonStoreWideningPass(PassRegistry &
Registry) { llvm::call_once(InitializeHexagonStoreWideningPassFlag
, initializeHexagonStoreWideningPassOnce, std::ref(Registry))
; }
119 "Hexagon Store Widening", false, false)PassInfo *PI = new PassInfo( "Hexagon Store Widening", "hexagon-widen-stores"
, &HexagonStoreWidening::ID, PassInfo::NormalCtor_t(callDefaultCtor
<HexagonStoreWidening>), false, false); Registry.registerPass
(*PI, true); return PI; } static llvm::once_flag InitializeHexagonStoreWideningPassFlag
; void llvm::initializeHexagonStoreWideningPass(PassRegistry &
Registry) { llvm::call_once(InitializeHexagonStoreWideningPassFlag
, initializeHexagonStoreWideningPassOnce, std::ref(Registry))
; }
120
121// Some local helper functions...
122static unsigned getBaseAddressRegister(const MachineInstr *MI) {
123 const MachineOperand &MO = MI->getOperand(0);
124 assert(MO.isReg() && "Expecting register operand")(static_cast <bool> (MO.isReg() && "Expecting register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Expecting register operand\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 124, __extension__ __PRETTY_FUNCTION__))
;
125 return MO.getReg();
126}
127
128static int64_t getStoreOffset(const MachineInstr *MI) {
129 unsigned OpC = MI->getOpcode();
130 assert(HexagonStoreWidening::handledStoreType(MI) && "Unhandled opcode")(static_cast <bool> (HexagonStoreWidening::handledStoreType
(MI) && "Unhandled opcode") ? void (0) : __assert_fail
("HexagonStoreWidening::handledStoreType(MI) && \"Unhandled opcode\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 130, __extension__ __PRETTY_FUNCTION__))
;
131
132 switch (OpC) {
133 case Hexagon::S4_storeirb_io:
134 case Hexagon::S4_storeirh_io:
135 case Hexagon::S4_storeiri_io: {
136 const MachineOperand &MO = MI->getOperand(1);
137 assert(MO.isImm() && "Expecting immediate offset")(static_cast <bool> (MO.isImm() && "Expecting immediate offset"
) ? void (0) : __assert_fail ("MO.isImm() && \"Expecting immediate offset\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 137, __extension__ __PRETTY_FUNCTION__))
;
138 return MO.getImm();
139 }
140 }
141 dbgs() << *MI;
142 llvm_unreachable("Store offset calculation missing for a handled opcode")::llvm::llvm_unreachable_internal("Store offset calculation missing for a handled opcode"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 142)
;
143 return 0;
144}
145
146static const MachineMemOperand &getStoreTarget(const MachineInstr *MI) {
147 assert(!MI->memoperands_empty() && "Expecting memory operands")(static_cast <bool> (!MI->memoperands_empty() &&
"Expecting memory operands") ? void (0) : __assert_fail ("!MI->memoperands_empty() && \"Expecting memory operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 147, __extension__ __PRETTY_FUNCTION__))
;
148 return **MI->memoperands_begin();
149}
150
151// Filtering function: any stores whose opcodes are not "approved" of by
152// this function will not be subjected to widening.
153inline bool HexagonStoreWidening::handledStoreType(const MachineInstr *MI) {
154 // For now, only handle stores of immediate values.
155 // Also, reject stores to stack slots.
156 unsigned Opc = MI->getOpcode();
157 switch (Opc) {
158 case Hexagon::S4_storeirb_io:
159 case Hexagon::S4_storeirh_io:
160 case Hexagon::S4_storeiri_io:
161 // Base address must be a register. (Implement FI later.)
162 return MI->getOperand(0).isReg();
163 default:
164 return false;
165 }
166}
167
168// Check if the machine memory operand MMO is aliased with any of the
169// stores in the store group Stores.
170bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
171 const MachineMemOperand &MMO) {
172 if (!MMO.getValue())
173 return true;
174
175 MemoryLocation L(MMO.getValue(), MMO.getSize(), MMO.getAAInfo());
176
177 for (auto SI : Stores) {
178 const MachineMemOperand &SMO = getStoreTarget(SI);
179 if (!SMO.getValue())
180 return true;
181
182 MemoryLocation SL(SMO.getValue(), SMO.getSize(), SMO.getAAInfo());
183 if (AA->alias(L, SL))
184 return true;
185 }
186
187 return false;
188}
189
190// Check if the machine instruction MI accesses any storage aliased with
191// any store in the group Stores.
192bool HexagonStoreWidening::instrAliased(InstrGroup &Stores,
193 const MachineInstr *MI) {
194 for (auto &I : MI->memoperands())
195 if (instrAliased(Stores, *I))
196 return true;
197 return false;
198}
199
200// Inspect a machine basic block, and generate store groups out of stores
201// encountered in the block.
202//
203// A store group is a group of stores that use the same base register,
204// and which can be reordered within that group without altering the
205// semantics of the program. A single store group could be widened as
206// a whole, if there existed a single store instruction with the same
207// semantics as the entire group. In many cases, a single store group
208// may need more than one wide store.
209void HexagonStoreWidening::createStoreGroups(MachineBasicBlock &MBB,
210 InstrGroupList &StoreGroups) {
211 InstrGroup AllInsns;
212
213 // Copy all instruction pointers from the basic block to a temporary
214 // list. This will allow operating on the list, and modifying its
215 // elements without affecting the basic block.
216 for (auto &I : MBB)
217 AllInsns.push_back(&I);
218
219 // Traverse all instructions in the AllInsns list, and if we encounter
220 // a store, then try to create a store group starting at that instruction
221 // i.e. a sequence of independent stores that can be widened.
222 for (auto I = AllInsns.begin(), E = AllInsns.end(); I != E; ++I) {
223 MachineInstr *MI = *I;
224 // Skip null pointers (processed instructions).
225 if (!MI || !handledStoreType(MI))
226 continue;
227
228 // Found a store. Try to create a store group.
229 InstrGroup G;
230 createStoreGroup(MI, I+1, E, G);
231 if (G.size() > 1)
232 StoreGroups.push_back(G);
233 }
234}
235
236// Create a single store group. The stores need to be independent between
237// themselves, and also there cannot be other instructions between them
238// that could read or modify storage being stored into.
239void HexagonStoreWidening::createStoreGroup(MachineInstr *BaseStore,
240 InstrGroup::iterator Begin, InstrGroup::iterator End, InstrGroup &Group) {
241 assert(handledStoreType(BaseStore) && "Unexpected instruction")(static_cast <bool> (handledStoreType(BaseStore) &&
"Unexpected instruction") ? void (0) : __assert_fail ("handledStoreType(BaseStore) && \"Unexpected instruction\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 241, __extension__ __PRETTY_FUNCTION__))
;
242 unsigned BaseReg = getBaseAddressRegister(BaseStore);
243 InstrGroup Other;
244
245 Group.push_back(BaseStore);
246
247 for (auto I = Begin; I != End; ++I) {
248 MachineInstr *MI = *I;
249 if (!MI)
250 continue;
251
252 if (handledStoreType(MI)) {
253 // If this store instruction is aliased with anything already in the
254 // group, terminate the group now.
255 if (instrAliased(Group, getStoreTarget(MI)))
256 return;
257 // If this store is aliased to any of the memory instructions we have
258 // seen so far (that are not a part of this group), terminate the group.
259 if (instrAliased(Other, getStoreTarget(MI)))
260 return;
261
262 unsigned BR = getBaseAddressRegister(MI);
263 if (BR == BaseReg) {
264 Group.push_back(MI);
265 *I = nullptr;
266 continue;
267 }
268 }
269
270 // Assume calls are aliased to everything.
271 if (MI->isCall() || MI->hasUnmodeledSideEffects())
272 return;
273
274 if (MI->mayLoad() || MI->mayStore()) {
275 if (MI->hasOrderedMemoryRef() || instrAliased(Group, MI))
276 return;
277 Other.push_back(MI);
278 }
279 } // for
280}
281
282// Check if store instructions S1 and S2 are adjacent. More precisely,
283// S2 has to access memory immediately following that accessed by S1.
284bool HexagonStoreWidening::storesAreAdjacent(const MachineInstr *S1,
285 const MachineInstr *S2) {
286 if (!handledStoreType(S1) || !handledStoreType(S2))
287 return false;
288
289 const MachineMemOperand &S1MO = getStoreTarget(S1);
290
291 // Currently only handling immediate stores.
292 int Off1 = S1->getOperand(1).getImm();
293 int Off2 = S2->getOperand(1).getImm();
294
295 return (Off1 >= 0) ? Off1+S1MO.getSize() == unsigned(Off2)
296 : int(Off1+S1MO.getSize()) == Off2;
297}
298
299/// Given a sequence of adjacent stores, and a maximum size of a single wide
300/// store, pick a group of stores that can be replaced by a single store
301/// of size not exceeding MaxSize. The selected sequence will be recorded
302/// in OG ("old group" of instructions).
303/// OG should be empty on entry, and should be left empty if the function
304/// fails.
305bool HexagonStoreWidening::selectStores(InstrGroup::iterator Begin,
306 InstrGroup::iterator End, InstrGroup &OG, unsigned &TotalSize,
307 unsigned MaxSize) {
308 assert(Begin != End && "No instructions to analyze")(static_cast <bool> (Begin != End && "No instructions to analyze"
) ? void (0) : __assert_fail ("Begin != End && \"No instructions to analyze\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 308, __extension__ __PRETTY_FUNCTION__))
;
309 assert(OG.empty() && "Old group not empty on entry")(static_cast <bool> (OG.empty() && "Old group not empty on entry"
) ? void (0) : __assert_fail ("OG.empty() && \"Old group not empty on entry\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 309, __extension__ __PRETTY_FUNCTION__))
;
310
311 if (std::distance(Begin, End) <= 1)
312 return false;
313
314 MachineInstr *FirstMI = *Begin;
315 assert(!FirstMI->memoperands_empty() && "Expecting some memory operands")(static_cast <bool> (!FirstMI->memoperands_empty() &&
"Expecting some memory operands") ? void (0) : __assert_fail
("!FirstMI->memoperands_empty() && \"Expecting some memory operands\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 315, __extension__ __PRETTY_FUNCTION__))
;
316 const MachineMemOperand &FirstMMO = getStoreTarget(FirstMI);
317 unsigned Alignment = FirstMMO.getAlignment();
318 unsigned SizeAccum = FirstMMO.getSize();
319 unsigned FirstOffset = getStoreOffset(FirstMI);
320
321 // The initial value of SizeAccum should always be a power of 2.
322 assert(isPowerOf2_32(SizeAccum) && "First store size not a power of 2")(static_cast <bool> (isPowerOf2_32(SizeAccum) &&
"First store size not a power of 2") ? void (0) : __assert_fail
("isPowerOf2_32(SizeAccum) && \"First store size not a power of 2\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 322, __extension__ __PRETTY_FUNCTION__))
;
323
324 // If the size of the first store equals to or exceeds the limit, do nothing.
325 if (SizeAccum >= MaxSize)
326 return false;
327
328 // If the size of the first store is greater than or equal to the address
329 // stored to, then the store cannot be made any wider.
330 if (SizeAccum >= Alignment)
331 return false;
332
333 // The offset of a store will put restrictions on how wide the store can be.
334 // Offsets in stores of size 2^n bytes need to have the n lowest bits be 0.
335 // If the first store already exhausts the offset limits, quit. Test this
336 // by checking if the next wider size would exceed the limit.
337 if ((2*SizeAccum-1) & FirstOffset)
338 return false;
339
340 OG.push_back(FirstMI);
341 MachineInstr *S1 = FirstMI, *S2 = *(Begin+1);
Value stored to 'S2' during its initialization is never read
342 InstrGroup::iterator I = Begin+1;
343
344 // Pow2Num will be the largest number of elements in OG such that the sum
345 // of sizes of stores 0...Pow2Num-1 will be a power of 2.
346 unsigned Pow2Num = 1;
347 unsigned Pow2Size = SizeAccum;
348
349 // Be greedy: keep accumulating stores as long as they are to adjacent
350 // memory locations, and as long as the total number of bytes stored
351 // does not exceed the limit (MaxSize).
352 // Keep track of when the total size covered is a power of 2, since
353 // this is a size a single store can cover.
354 while (I != End) {
355 S2 = *I;
356 // Stores are sorted, so if S1 and S2 are not adjacent, there won't be
357 // any other store to fill the "hole".
358 if (!storesAreAdjacent(S1, S2))
359 break;
360
361 unsigned S2Size = getStoreTarget(S2).getSize();
362 if (SizeAccum + S2Size > std::min(MaxSize, Alignment))
363 break;
364
365 OG.push_back(S2);
366 SizeAccum += S2Size;
367 if (isPowerOf2_32(SizeAccum)) {
368 Pow2Num = OG.size();
369 Pow2Size = SizeAccum;
370 }
371 if ((2*Pow2Size-1) & FirstOffset)
372 break;
373
374 S1 = S2;
375 ++I;
376 }
377
378 // The stores don't add up to anything that can be widened. Clean up.
379 if (Pow2Num <= 1) {
380 OG.clear();
381 return false;
382 }
383
384 // Only leave the stored being widened.
385 OG.resize(Pow2Num);
386 TotalSize = Pow2Size;
387 return true;
388}
389
390/// Given an "old group" OG of stores, create a "new group" NG of instructions
391/// to replace them. Ideally, NG would only have a single instruction in it,
392/// but that may only be possible for store-immediate.
393bool HexagonStoreWidening::createWideStores(InstrGroup &OG, InstrGroup &NG,
394 unsigned TotalSize) {
395 // XXX Current limitations:
396 // - only expect stores of immediate values in OG,
397 // - only handle a TotalSize of up to 4.
398
399 if (TotalSize > 4)
400 return false;
401
402 unsigned Acc = 0; // Value accumulator.
403 unsigned Shift = 0;
404
405 for (InstrGroup::iterator I = OG.begin(), E = OG.end(); I != E; ++I) {
406 MachineInstr *MI = *I;
407 const MachineMemOperand &MMO = getStoreTarget(MI);
408 MachineOperand &SO = MI->getOperand(2); // Source.
409 assert(SO.isImm() && "Expecting an immediate operand")(static_cast <bool> (SO.isImm() && "Expecting an immediate operand"
) ? void (0) : __assert_fail ("SO.isImm() && \"Expecting an immediate operand\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 409, __extension__ __PRETTY_FUNCTION__))
;
410
411 unsigned NBits = MMO.getSize()*8;
412 unsigned Mask = (0xFFFFFFFFU >> (32-NBits));
413 unsigned Val = (SO.getImm() & Mask) << Shift;
414 Acc |= Val;
415 Shift += NBits;
416 }
417
418 MachineInstr *FirstSt = OG.front();
419 DebugLoc DL = OG.back()->getDebugLoc();
420 const MachineMemOperand &OldM = getStoreTarget(FirstSt);
421 MachineMemOperand *NewM =
422 MF->getMachineMemOperand(OldM.getPointerInfo(), OldM.getFlags(),
423 TotalSize, OldM.getAlignment(),
424 OldM.getAAInfo());
425
426 if (Acc < 0x10000) {
427 // Create mem[hw] = #Acc
428 unsigned WOpc = (TotalSize == 2) ? Hexagon::S4_storeirh_io :
429 (TotalSize == 4) ? Hexagon::S4_storeiri_io : 0;
430 assert(WOpc && "Unexpected size")(static_cast <bool> (WOpc && "Unexpected size")
? void (0) : __assert_fail ("WOpc && \"Unexpected size\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 430, __extension__ __PRETTY_FUNCTION__))
;
431
432 int Val = (TotalSize == 2) ? int16_t(Acc) : int(Acc);
433 const MCInstrDesc &StD = TII->get(WOpc);
434 MachineOperand &MR = FirstSt->getOperand(0);
435 int64_t Off = FirstSt->getOperand(1).getImm();
436 MachineInstr *StI =
437 BuildMI(*MF, DL, StD)
438 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
439 .addImm(Off)
440 .addImm(Val);
441 StI->addMemOperand(*MF, NewM);
442 NG.push_back(StI);
443 } else {
444 // Create vreg = A2_tfrsi #Acc; mem[hw] = vreg
445 const MCInstrDesc &TfrD = TII->get(Hexagon::A2_tfrsi);
446 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
447 unsigned VReg = MF->getRegInfo().createVirtualRegister(RC);
448 MachineInstr *TfrI = BuildMI(*MF, DL, TfrD, VReg)
449 .addImm(int(Acc));
450 NG.push_back(TfrI);
451
452 unsigned WOpc = (TotalSize == 2) ? Hexagon::S2_storerh_io :
453 (TotalSize == 4) ? Hexagon::S2_storeri_io : 0;
454 assert(WOpc && "Unexpected size")(static_cast <bool> (WOpc && "Unexpected size")
? void (0) : __assert_fail ("WOpc && \"Unexpected size\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 454, __extension__ __PRETTY_FUNCTION__))
;
455
456 const MCInstrDesc &StD = TII->get(WOpc);
457 MachineOperand &MR = FirstSt->getOperand(0);
458 int64_t Off = FirstSt->getOperand(1).getImm();
459 MachineInstr *StI =
460 BuildMI(*MF, DL, StD)
461 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
462 .addImm(Off)
463 .addReg(VReg, RegState::Kill);
464 StI->addMemOperand(*MF, NewM);
465 NG.push_back(StI);
466 }
467
468 return true;
469}
470
471// Replace instructions from the old group OG with instructions from the
472// new group NG. Conceptually, remove all instructions in OG, and then
473// insert all instructions in NG, starting at where the first instruction
474// from OG was (in the order in which they appeared in the basic block).
475// (The ordering in OG does not have to match the order in the basic block.)
476bool HexagonStoreWidening::replaceStores(InstrGroup &OG, InstrGroup &NG) {
477 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
478 dbgs() << "Replacing:\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
479 for (auto I : OG)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
480 dbgs() << " " << *I;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
481 dbgs() << "with\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
482 for (auto I : NG)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
483 dbgs() << " " << *I;do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
484 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("hexagon-widen-stores")) { { dbgs() << "Replacing:\n";
for (auto I : OG) dbgs() << " " << *I; dbgs() <<
"with\n"; for (auto I : NG) dbgs() << " " << *I
; }; } } while (false)
;
485
486 MachineBasicBlock *MBB = OG.back()->getParent();
487 MachineBasicBlock::iterator InsertAt = MBB->end();
488
489 // Need to establish the insertion point. The best one is right before
490 // the first store in the OG, but in the order in which the stores occur
491 // in the program list. Since the ordering in OG does not correspond
492 // to the order in the program list, we need to do some work to find
493 // the insertion point.
494
495 // Create a set of all instructions in OG (for quick lookup).
496 SmallPtrSet<MachineInstr*, 4> InstrSet;
497 for (auto I : OG)
498 InstrSet.insert(I);
499
500 // Traverse the block, until we hit an instruction from OG.
501 for (auto &I : *MBB) {
502 if (InstrSet.count(&I)) {
503 InsertAt = I;
504 break;
505 }
506 }
507
508 assert((InsertAt != MBB->end()) && "Cannot locate any store from the group")(static_cast <bool> ((InsertAt != MBB->end()) &&
"Cannot locate any store from the group") ? void (0) : __assert_fail
("(InsertAt != MBB->end()) && \"Cannot locate any store from the group\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 508, __extension__ __PRETTY_FUNCTION__))
;
509
510 bool AtBBStart = false;
511
512 // InsertAt points at the first instruction that will be removed. We need
513 // to move it out of the way, so it remains valid after removing all the
514 // old stores, and so we are able to recover it back to the proper insertion
515 // position.
516 if (InsertAt != MBB->begin())
517 --InsertAt;
518 else
519 AtBBStart = true;
520
521 for (auto I : OG)
522 I->eraseFromParent();
523
524 if (!AtBBStart)
525 ++InsertAt;
526 else
527 InsertAt = MBB->begin();
528
529 for (auto I : NG)
530 MBB->insert(InsertAt, I);
531
532 return true;
533}
534
535// Break up the group into smaller groups, each of which can be replaced by
536// a single wide store. Widen each such smaller group and replace the old
537// instructions with the widened ones.
538bool HexagonStoreWidening::processStoreGroup(InstrGroup &Group) {
539 bool Changed = false;
540 InstrGroup::iterator I = Group.begin(), E = Group.end();
541 InstrGroup OG, NG; // Old and new groups.
542 unsigned CollectedSize;
543
544 while (I != E) {
545 OG.clear();
546 NG.clear();
547
548 bool Succ = selectStores(I++, E, OG, CollectedSize, MaxWideSize) &&
549 createWideStores(OG, NG, CollectedSize) &&
550 replaceStores(OG, NG);
551 if (!Succ)
552 continue;
553
554 assert(OG.size() > 1 && "Created invalid group")(static_cast <bool> (OG.size() > 1 && "Created invalid group"
) ? void (0) : __assert_fail ("OG.size() > 1 && \"Created invalid group\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 554, __extension__ __PRETTY_FUNCTION__))
;
555 assert(distance(I, E)+1 >= int(OG.size()) && "Too many elements")(static_cast <bool> (distance(I, E)+1 >= int(OG.size
()) && "Too many elements") ? void (0) : __assert_fail
("distance(I, E)+1 >= int(OG.size()) && \"Too many elements\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 555, __extension__ __PRETTY_FUNCTION__))
;
556 I += OG.size()-1;
557
558 Changed = true;
559 }
560
561 return Changed;
562}
563
564// Process a single basic block: create the store groups, and replace them
565// with the widened stores, if possible. Processing of each basic block
566// is independent from processing of any other basic block. This transfor-
567// mation could be stopped after having processed any basic block without
568// any ill effects (other than not having performed widening in the unpro-
569// cessed blocks). Also, the basic blocks can be processed in any order.
570bool HexagonStoreWidening::processBasicBlock(MachineBasicBlock &MBB) {
571 InstrGroupList SGs;
572 bool Changed = false;
573
574 createStoreGroups(MBB, SGs);
575
576 auto Less = [] (const MachineInstr *A, const MachineInstr *B) -> bool {
577 return getStoreOffset(A) < getStoreOffset(B);
578 };
579 for (auto &G : SGs) {
580 assert(G.size() > 1 && "Store group with fewer than 2 elements")(static_cast <bool> (G.size() > 1 && "Store group with fewer than 2 elements"
) ? void (0) : __assert_fail ("G.size() > 1 && \"Store group with fewer than 2 elements\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/Target/Hexagon/HexagonStoreWidening.cpp"
, 580, __extension__ __PRETTY_FUNCTION__))
;
581 llvm::sort(G.begin(), G.end(), Less);
582
583 Changed |= processStoreGroup(G);
584 }
585
586 return Changed;
587}
588
589bool HexagonStoreWidening::runOnMachineFunction(MachineFunction &MFn) {
590 if (skipFunction(MFn.getFunction()))
591 return false;
592
593 MF = &MFn;
594 auto &ST = MFn.getSubtarget<HexagonSubtarget>();
595 TII = ST.getInstrInfo();
596 TRI = ST.getRegisterInfo();
597 MRI = &MFn.getRegInfo();
598 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
599
600 bool Changed = false;
601
602 for (auto &B : MFn)
603 Changed |= processBasicBlock(B);
604
605 return Changed;
606}
607
608FunctionPass *llvm::createHexagonStoreWidening() {
609 return new HexagonStoreWidening();
610}