Bug Summary

File:lib/CodeGen/InlineSpiller.cpp
Warning:line 296, column 61
The left operand of '==' is a garbage value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name InlineSpiller.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn329677/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn329677/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-04-11-031539-24776-1 -x c++ /build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp

/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp

1//===- InlineSpiller.cpp - Insert spills and restores inline --------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// The inline spiller modifies the machine function directly instead of
11// inserting spills and restores in VirtRegMap.
12//
13//===----------------------------------------------------------------------===//
14
15#include "LiveRangeCalc.h"
16#include "Spiller.h"
17#include "SplitKit.h"
18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/DenseMap.h"
20#include "llvm/ADT/MapVector.h"
21#include "llvm/ADT/None.h"
22#include "llvm/ADT/STLExtras.h"
23#include "llvm/ADT/SetVector.h"
24#include "llvm/ADT/SmallPtrSet.h"
25#include "llvm/ADT/SmallVector.h"
26#include "llvm/ADT/Statistic.h"
27#include "llvm/Analysis/AliasAnalysis.h"
28#include "llvm/CodeGen/LiveInterval.h"
29#include "llvm/CodeGen/LiveIntervals.h"
30#include "llvm/CodeGen/LiveRangeEdit.h"
31#include "llvm/CodeGen/LiveStacks.h"
32#include "llvm/CodeGen/MachineBasicBlock.h"
33#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
34#include "llvm/CodeGen/MachineDominators.h"
35#include "llvm/CodeGen/MachineFunction.h"
36#include "llvm/CodeGen/MachineFunctionPass.h"
37#include "llvm/CodeGen/MachineInstr.h"
38#include "llvm/CodeGen/MachineInstrBuilder.h"
39#include "llvm/CodeGen/MachineInstrBundle.h"
40#include "llvm/CodeGen/MachineLoopInfo.h"
41#include "llvm/CodeGen/MachineOperand.h"
42#include "llvm/CodeGen/MachineRegisterInfo.h"
43#include "llvm/CodeGen/SlotIndexes.h"
44#include "llvm/CodeGen/TargetInstrInfo.h"
45#include "llvm/CodeGen/TargetOpcodes.h"
46#include "llvm/CodeGen/TargetRegisterInfo.h"
47#include "llvm/CodeGen/TargetSubtargetInfo.h"
48#include "llvm/CodeGen/VirtRegMap.h"
49#include "llvm/Support/BlockFrequency.h"
50#include "llvm/Support/BranchProbability.h"
51#include "llvm/Support/CommandLine.h"
52#include "llvm/Support/Compiler.h"
53#include "llvm/Support/Debug.h"
54#include "llvm/Support/ErrorHandling.h"
55#include "llvm/Support/raw_ostream.h"
56#include <cassert>
57#include <iterator>
58#include <tuple>
59#include <utility>
60#include <vector>
61
62using namespace llvm;
63
64#define DEBUG_TYPE"regalloc" "regalloc"
65
66STATISTIC(NumSpilledRanges, "Number of spilled live ranges")static llvm::Statistic NumSpilledRanges = {"regalloc", "NumSpilledRanges"
, "Number of spilled live ranges", {0}, {false}}
;
67STATISTIC(NumSnippets, "Number of spilled snippets")static llvm::Statistic NumSnippets = {"regalloc", "NumSnippets"
, "Number of spilled snippets", {0}, {false}}
;
68STATISTIC(NumSpills, "Number of spills inserted")static llvm::Statistic NumSpills = {"regalloc", "NumSpills", "Number of spills inserted"
, {0}, {false}}
;
69STATISTIC(NumSpillsRemoved, "Number of spills removed")static llvm::Statistic NumSpillsRemoved = {"regalloc", "NumSpillsRemoved"
, "Number of spills removed", {0}, {false}}
;
70STATISTIC(NumReloads, "Number of reloads inserted")static llvm::Statistic NumReloads = {"regalloc", "NumReloads"
, "Number of reloads inserted", {0}, {false}}
;
71STATISTIC(NumReloadsRemoved, "Number of reloads removed")static llvm::Statistic NumReloadsRemoved = {"regalloc", "NumReloadsRemoved"
, "Number of reloads removed", {0}, {false}}
;
72STATISTIC(NumFolded, "Number of folded stack accesses")static llvm::Statistic NumFolded = {"regalloc", "NumFolded", "Number of folded stack accesses"
, {0}, {false}}
;
73STATISTIC(NumFoldedLoads, "Number of folded loads")static llvm::Statistic NumFoldedLoads = {"regalloc", "NumFoldedLoads"
, "Number of folded loads", {0}, {false}}
;
74STATISTIC(NumRemats, "Number of rematerialized defs for spilling")static llvm::Statistic NumRemats = {"regalloc", "NumRemats", "Number of rematerialized defs for spilling"
, {0}, {false}}
;
75
76static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
77 cl::desc("Disable inline spill hoisting"));
78
79namespace {
80
81class HoistSpillHelper : private LiveRangeEdit::Delegate {
82 MachineFunction &MF;
83 LiveIntervals &LIS;
84 LiveStacks &LSS;
85 AliasAnalysis *AA;
86 MachineDominatorTree &MDT;
87 MachineLoopInfo &Loops;
88 VirtRegMap &VRM;
89 MachineRegisterInfo &MRI;
90 const TargetInstrInfo &TII;
91 const TargetRegisterInfo &TRI;
92 const MachineBlockFrequencyInfo &MBFI;
93
94 InsertPointAnalysis IPA;
95
96 // Map from StackSlot to the LiveInterval of the original register.
97 // Note the LiveInterval of the original register may have been deleted
98 // after it is spilled. We keep a copy here to track the range where
99 // spills can be moved.
100 DenseMap<int, std::unique_ptr<LiveInterval>> StackSlotToOrigLI;
101
102 // Map from pair of (StackSlot and Original VNI) to a set of spills which
103 // have the same stackslot and have equal values defined by Original VNI.
104 // These spills are mergeable and are hoist candiates.
105 using MergeableSpillsMap =
106 MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>;
107 MergeableSpillsMap MergeableSpills;
108
109 /// This is the map from original register to a set containing all its
110 /// siblings. To hoist a spill to another BB, we need to find out a live
111 /// sibling there and use it as the source of the new spill.
112 DenseMap<unsigned, SmallSetVector<unsigned, 16>> Virt2SiblingsMap;
113
114 bool isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
115 MachineBasicBlock &BB, unsigned &LiveReg);
116
117 void rmRedundantSpills(
118 SmallPtrSet<MachineInstr *, 16> &Spills,
119 SmallVectorImpl<MachineInstr *> &SpillsToRm,
120 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
121
122 void getVisitOrders(
123 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
124 SmallVectorImpl<MachineDomTreeNode *> &Orders,
125 SmallVectorImpl<MachineInstr *> &SpillsToRm,
126 DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
127 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
128
129 void runHoistSpills(LiveInterval &OrigLI, VNInfo &OrigVNI,
130 SmallPtrSet<MachineInstr *, 16> &Spills,
131 SmallVectorImpl<MachineInstr *> &SpillsToRm,
132 DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
133
134public:
135 HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
136 VirtRegMap &vrm)
137 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
138 LSS(pass.getAnalysis<LiveStacks>()),
139 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
140 MDT(pass.getAnalysis<MachineDominatorTree>()),
141 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
142 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
143 TRI(*mf.getSubtarget().getRegisterInfo()),
144 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
145 IPA(LIS, mf.getNumBlockIDs()) {}
146
147 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
148 unsigned Original);
149 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
150 void hoistAllSpills();
151 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
152};
153
154class InlineSpiller : public Spiller {
155 MachineFunction &MF;
156 LiveIntervals &LIS;
157 LiveStacks &LSS;
158 AliasAnalysis *AA;
159 MachineDominatorTree &MDT;
160 MachineLoopInfo &Loops;
161 VirtRegMap &VRM;
162 MachineRegisterInfo &MRI;
163 const TargetInstrInfo &TII;
164 const TargetRegisterInfo &TRI;
165 const MachineBlockFrequencyInfo &MBFI;
166
167 // Variables that are valid during spill(), but used by multiple methods.
168 LiveRangeEdit *Edit;
169 LiveInterval *StackInt;
170 int StackSlot;
171 unsigned Original;
172
173 // All registers to spill to StackSlot, including the main register.
174 SmallVector<unsigned, 8> RegsToSpill;
175
176 // All COPY instructions to/from snippets.
177 // They are ignored since both operands refer to the same stack slot.
178 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
179
180 // Values that failed to remat at some point.
181 SmallPtrSet<VNInfo*, 8> UsedValues;
182
183 // Dead defs generated during spilling.
184 SmallVector<MachineInstr*, 8> DeadDefs;
185
186 // Object records spills information and does the hoisting.
187 HoistSpillHelper HSpiller;
188
189 ~InlineSpiller() override = default;
190
191public:
192 InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
193 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
194 LSS(pass.getAnalysis<LiveStacks>()),
195 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
196 MDT(pass.getAnalysis<MachineDominatorTree>()),
197 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
198 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
199 TRI(*mf.getSubtarget().getRegisterInfo()),
200 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
201 HSpiller(pass, mf, vrm) {}
202
203 void spill(LiveRangeEdit &) override;
204 void postOptimization() override;
205
206private:
207 bool isSnippet(const LiveInterval &SnipLI);
208 void collectRegsToSpill();
209
210 bool isRegToSpill(unsigned Reg) { return is_contained(RegsToSpill, Reg); }
211
212 bool isSibling(unsigned Reg);
213 bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
214 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
215
216 void markValueUsed(LiveInterval*, VNInfo*);
217 bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
218 void reMaterializeAll();
219
220 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
221 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>>,
222 MachineInstr *LoadMI = nullptr);
223 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
224 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
225
226 void spillAroundUses(unsigned Reg);
227 void spillAll();
228};
229
230} // end anonymous namespace
231
232Spiller::~Spiller() = default;
233
234void Spiller::anchor() {}
235
236Spiller *llvm::createInlineSpiller(MachineFunctionPass &pass,
237 MachineFunction &mf,
238 VirtRegMap &vrm) {
239 return new InlineSpiller(pass, mf, vrm);
240}
241
242//===----------------------------------------------------------------------===//
243// Snippets
244//===----------------------------------------------------------------------===//
245
246// When spilling a virtual register, we also spill any snippets it is connected
247// to. The snippets are small live ranges that only have a single real use,
248// leftovers from live range splitting. Spilling them enables memory operand
249// folding or tightens the live range around the single use.
250//
251// This minimizes register pressure and maximizes the store-to-load distance for
252// spill slots which can be important in tight loops.
253
254/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
255/// otherwise return 0.
256static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
257 if (!MI.isFullCopy())
258 return 0;
259 if (MI.getOperand(0).getReg() == Reg)
260 return MI.getOperand(1).getReg();
261 if (MI.getOperand(1).getReg() == Reg)
262 return MI.getOperand(0).getReg();
263 return 0;
264}
265
266/// isSnippet - Identify if a live interval is a snippet that should be spilled.
267/// It is assumed that SnipLI is a virtual register with the same original as
268/// Edit->getReg().
269bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
270 unsigned Reg = Edit->getReg();
271
272 // A snippet is a tiny live range with only a single instruction using it
273 // besides copies to/from Reg or spills/fills. We accept:
274 //
275 // %snip = COPY %Reg / FILL fi#
276 // %snip = USE %snip
277 // %Reg = COPY %snip / SPILL %snip, fi#
278 //
279 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
1
Assuming the condition is false
2
Assuming the condition is false
3
Taking false branch
280 return false;
281
282 MachineInstr *UseMI = nullptr;
283
284 // Check that all uses satisfy our criteria.
285 for (MachineRegisterInfo::reg_instr_nodbg_iterator
4
Loop condition is true. Entering loop body
286 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
287 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
288 MachineInstr &MI = *RI++;
289
290 // Allow copies to/from Reg.
291 if (isFullCopyOf(MI, Reg))
5
Taking false branch
292 continue;
293
294 // Allow stack slot loads.
295 int FI;
6
'FI' declared without an initial value
296 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
7
Calling 'TargetInstrInfo::isLoadFromStackSlot'
9
Returning from 'TargetInstrInfo::isLoadFromStackSlot'
10
Assuming the condition is true
11
The left operand of '==' is a garbage value
297 continue;
298
299 // Allow stack slot stores.
300 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
301 continue;
302
303 // Allow a single additional instruction.
304 if (UseMI && &MI != UseMI)
305 return false;
306 UseMI = &MI;
307 }
308 return true;
309}
310
311/// collectRegsToSpill - Collect live range snippets that only have a single
312/// real use.
313void InlineSpiller::collectRegsToSpill() {
314 unsigned Reg = Edit->getReg();
315
316 // Main register always spills.
317 RegsToSpill.assign(1, Reg);
318 SnippetCopies.clear();
319
320 // Snippets all have the same original, so there can't be any for an original
321 // register.
322 if (Original == Reg)
323 return;
324
325 for (MachineRegisterInfo::reg_instr_iterator
326 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
327 MachineInstr &MI = *RI++;
328 unsigned SnipReg = isFullCopyOf(MI, Reg);
329 if (!isSibling(SnipReg))
330 continue;
331 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
332 if (!isSnippet(SnipLI))
333 continue;
334 SnippetCopies.insert(&MI);
335 if (isRegToSpill(SnipReg))
336 continue;
337 RegsToSpill.push_back(SnipReg);
338 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\talso spill snippet " <<
SnipLI << '\n'; } } while (false)
;
339 ++NumSnippets;
340 }
341}
342
343bool InlineSpiller::isSibling(unsigned Reg) {
344 return TargetRegisterInfo::isVirtualRegister(Reg) &&
345 VRM.getOriginal(Reg) == Original;
346}
347
348/// It is beneficial to spill to earlier place in the same BB in case
349/// as follows:
350/// There is an alternative def earlier in the same MBB.
351/// Hoist the spill as far as possible in SpillMBB. This can ease
352/// register pressure:
353///
354/// x = def
355/// y = use x
356/// s = copy x
357///
358/// Hoisting the spill of s to immediately after the def removes the
359/// interference between x and y:
360///
361/// x = def
362/// spill x
363/// y = use killed x
364///
365/// This hoist only helps when the copy kills its source.
366///
367bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
368 MachineInstr &CopyMI) {
369 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
370#ifndef NDEBUG
371 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
372 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy")(static_cast <bool> (VNI && VNI->def == Idx.
getRegSlot() && "Not defined by copy") ? void (0) : __assert_fail
("VNI && VNI->def == Idx.getRegSlot() && \"Not defined by copy\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 372, __extension__ __PRETTY_FUNCTION__))
;
373#endif
374
375 unsigned SrcReg = CopyMI.getOperand(1).getReg();
376 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
377 VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
378 LiveQueryResult SrcQ = SrcLI.Query(Idx);
379 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(SrcVNI->def);
380 if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
381 return false;
382
383 // Conservatively extend the stack slot range to the range of the original
384 // value. We may be able to do better with stack slot coloring by being more
385 // careful here.
386 assert(StackInt && "No stack slot assigned yet.")(static_cast <bool> (StackInt && "No stack slot assigned yet."
) ? void (0) : __assert_fail ("StackInt && \"No stack slot assigned yet.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 386, __extension__ __PRETTY_FUNCTION__))
;
387 LiveInterval &OrigLI = LIS.getInterval(Original);
388 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
389 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
390 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tmerged orig valno " <<
OrigVNI->id << ": " << *StackInt << '\n'
; } } while (false)
391 << *StackInt << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tmerged orig valno " <<
OrigVNI->id << ": " << *StackInt << '\n'
; } } while (false)
;
392
393 // We are going to spill SrcVNI immediately after its def, so clear out
394 // any later spills of the same value.
395 eliminateRedundantSpills(SrcLI, SrcVNI);
396
397 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def);
398 MachineBasicBlock::iterator MII;
399 if (SrcVNI->isPHIDef())
400 MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin());
401 else {
402 MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
403 assert(DefMI && "Defining instruction disappeared")(static_cast <bool> (DefMI && "Defining instruction disappeared"
) ? void (0) : __assert_fail ("DefMI && \"Defining instruction disappeared\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 403, __extension__ __PRETTY_FUNCTION__))
;
404 MII = DefMI;
405 ++MII;
406 }
407 // Insert spill without kill flag immediately after def.
408 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
409 MRI.getRegClass(SrcReg), &TRI);
410 --MII; // Point to store instruction.
411 LIS.InsertMachineInstrInMaps(*MII);
412 DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\thoisted: " << SrcVNI
->def << '\t' << *MII; } } while (false)
;
413
414 HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
415 ++NumSpills;
416 return true;
417}
418
419/// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
420/// redundant spills of this value in SLI.reg and sibling copies.
421void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
422 assert(VNI && "Missing value")(static_cast <bool> (VNI && "Missing value") ? void
(0) : __assert_fail ("VNI && \"Missing value\"", "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 422, __extension__ __PRETTY_FUNCTION__))
;
423 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
424 WorkList.push_back(std::make_pair(&SLI, VNI));
425 assert(StackInt && "No stack slot assigned yet.")(static_cast <bool> (StackInt && "No stack slot assigned yet."
) ? void (0) : __assert_fail ("StackInt && \"No stack slot assigned yet.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 425, __extension__ __PRETTY_FUNCTION__))
;
426
427 do {
428 LiveInterval *LI;
429 std::tie(LI, VNI) = WorkList.pop_back_val();
430 unsigned Reg = LI->reg;
431 DEBUG(dbgs() << "Checking redundant spills for "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Checking redundant spills for "
<< VNI->id << '@' << VNI->def <<
" in " << *LI << '\n'; } } while (false)
432 << VNI->id << '@' << VNI->def << " in " << *LI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Checking redundant spills for "
<< VNI->id << '@' << VNI->def <<
" in " << *LI << '\n'; } } while (false)
;
433
434 // Regs to spill are taken care of.
435 if (isRegToSpill(Reg))
436 continue;
437
438 // Add all of VNI's live range to StackInt.
439 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
440 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Merged to stack int: " <<
*StackInt << '\n'; } } while (false)
;
441
442 // Find all spills and copies of VNI.
443 for (MachineRegisterInfo::use_instr_nodbg_iterator
444 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
445 UI != E; ) {
446 MachineInstr &MI = *UI++;
447 if (!MI.isCopy() && !MI.mayStore())
448 continue;
449 SlotIndex Idx = LIS.getInstructionIndex(MI);
450 if (LI->getVNInfoAt(Idx) != VNI)
451 continue;
452
453 // Follow sibling copies down the dominator tree.
454 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
455 if (isSibling(DstReg)) {
456 LiveInterval &DstLI = LIS.getInterval(DstReg);
457 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
458 assert(DstVNI && "Missing defined value")(static_cast <bool> (DstVNI && "Missing defined value"
) ? void (0) : __assert_fail ("DstVNI && \"Missing defined value\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 458, __extension__ __PRETTY_FUNCTION__))
;
459 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot")(static_cast <bool> (DstVNI->def == Idx.getRegSlot()
&& "Wrong copy def slot") ? void (0) : __assert_fail
("DstVNI->def == Idx.getRegSlot() && \"Wrong copy def slot\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 459, __extension__ __PRETTY_FUNCTION__))
;
460 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
461 }
462 continue;
463 }
464
465 // Erase spills.
466 int FI;
467 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
468 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Redundant spill " << Idx
<< '\t' << MI; } } while (false)
;
469 // eliminateDeadDefs won't normally remove stores, so switch opcode.
470 MI.setDesc(TII.get(TargetOpcode::KILL));
471 DeadDefs.push_back(&MI);
472 ++NumSpillsRemoved;
473 if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
474 --NumSpills;
475 }
476 }
477 } while (!WorkList.empty());
478}
479
480//===----------------------------------------------------------------------===//
481// Rematerialization
482//===----------------------------------------------------------------------===//
483
484/// markValueUsed - Remember that VNI failed to rematerialize, so its defining
485/// instruction cannot be eliminated. See through snippet copies
486void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
487 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
488 WorkList.push_back(std::make_pair(LI, VNI));
489 do {
490 std::tie(LI, VNI) = WorkList.pop_back_val();
491 if (!UsedValues.insert(VNI).second)
492 continue;
493
494 if (VNI->isPHIDef()) {
495 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
496 for (MachineBasicBlock *P : MBB->predecessors()) {
497 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
498 if (PVNI)
499 WorkList.push_back(std::make_pair(LI, PVNI));
500 }
501 continue;
502 }
503
504 // Follow snippet copies.
505 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
506 if (!SnippetCopies.count(MI))
507 continue;
508 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
509 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy")(static_cast <bool> (isRegToSpill(SnipLI.reg) &&
"Unexpected register in copy") ? void (0) : __assert_fail ("isRegToSpill(SnipLI.reg) && \"Unexpected register in copy\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 509, __extension__ __PRETTY_FUNCTION__))
;
510 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
511 assert(SnipVNI && "Snippet undefined before copy")(static_cast <bool> (SnipVNI && "Snippet undefined before copy"
) ? void (0) : __assert_fail ("SnipVNI && \"Snippet undefined before copy\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 511, __extension__ __PRETTY_FUNCTION__))
;
512 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
513 } while (!WorkList.empty());
514}
515
516/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
517bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
518 // Analyze instruction
519 SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
520 MIBundleOperands::VirtRegInfo RI =
521 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
522
523 if (!RI.Reads)
524 return false;
525
526 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
527 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
528
529 if (!ParentVNI) {
530 DEBUG(dbgs() << "\tadding <undef> flags: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tadding <undef> flags: "
; } } while (false)
;
531 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
532 MachineOperand &MO = MI.getOperand(i);
533 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
534 MO.setIsUndef();
535 }
536 DEBUG(dbgs() << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << UseIdx << '\t' <<
MI; } } while (false)
;
537 return true;
538 }
539
540 if (SnippetCopies.count(&MI))
541 return false;
542
543 LiveInterval &OrigLI = LIS.getInterval(Original);
544 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
545 LiveRangeEdit::Remat RM(ParentVNI);
546 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
547
548 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) {
549 markValueUsed(&VirtReg, ParentVNI);
550 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tcannot remat for " <<
UseIdx << '\t' << MI; } } while (false)
;
551 return false;
552 }
553
554 // If the instruction also writes VirtReg.reg, it had better not require the
555 // same register for uses and defs.
556 if (RI.Tied) {
557 markValueUsed(&VirtReg, ParentVNI);
558 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tcannot remat tied reg: " <<
UseIdx << '\t' << MI; } } while (false)
;
559 return false;
560 }
561
562 // Before rematerializing into a register for a single instruction, try to
563 // fold a load into the instruction. That avoids allocating a new register.
564 if (RM.OrigMI->canFoldAsLoad() &&
565 foldMemoryOperand(Ops, RM.OrigMI)) {
566 Edit->markRematerialized(RM.ParentVNI);
567 ++NumFoldedLoads;
568 return true;
569 }
570
571 // Allocate a new register for the remat.
572 unsigned NewVReg = Edit->createFrom(Original);
573
574 // Finally we can rematerialize OrigMI before MI.
575 SlotIndex DefIdx =
576 Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI);
577
578 // We take the DebugLoc from MI, since OrigMI may be attributed to a
579 // different source location.
580 auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
581 NewMI->setDebugLoc(MI.getDebugLoc());
582
583 (void)DefIdx;
584 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremat: " << DefIdx <<
'\t' << *LIS.getInstructionFromIndex(DefIdx); } } while
(false)
585 << *LIS.getInstructionFromIndex(DefIdx))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremat: " << DefIdx <<
'\t' << *LIS.getInstructionFromIndex(DefIdx); } } while
(false)
;
586
587 // Replace operands
588 for (const auto &OpPair : Ops) {
589 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
590 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
591 MO.setReg(NewVReg);
592 MO.setIsKill();
593 }
594 }
595 DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t " << UseIdx <<
'\t' << MI << '\n'; } } while (false)
;
596
597 ++NumRemats;
598 return true;
599}
600
601/// reMaterializeAll - Try to rematerialize as many uses as possible,
602/// and trim the live ranges after.
603void InlineSpiller::reMaterializeAll() {
604 if (!Edit->anyRematerializable(AA))
605 return;
606
607 UsedValues.clear();
608
609 // Try to remat before all uses of snippets.
610 bool anyRemat = false;
611 for (unsigned Reg : RegsToSpill) {
612 LiveInterval &LI = LIS.getInterval(Reg);
613 for (MachineRegisterInfo::reg_bundle_iterator
614 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
615 RegI != E; ) {
616 MachineInstr &MI = *RegI++;
617
618 // Debug values are not allowed to affect codegen.
619 if (MI.isDebugValue())
620 continue;
621
622 anyRemat |= reMaterializeFor(LI, MI);
623 }
624 }
625 if (!anyRemat)
626 return;
627
628 // Remove any values that were completely rematted.
629 for (unsigned Reg : RegsToSpill) {
630 LiveInterval &LI = LIS.getInterval(Reg);
631 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
632 I != E; ++I) {
633 VNInfo *VNI = *I;
634 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
635 continue;
636 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
637 MI->addRegisterDead(Reg, &TRI);
638 if (!MI->allDefsAreDead())
639 continue;
640 DEBUG(dbgs() << "All defs dead: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "All defs dead: " << *MI
; } } while (false)
;
641 DeadDefs.push_back(MI);
642 }
643 }
644
645 // Eliminate dead code after remat. Note that some snippet copies may be
646 // deleted here.
647 if (DeadDefs.empty())
648 return;
649 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Remat created " << DeadDefs
.size() << " dead defs.\n"; } } while (false)
;
650 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
651
652 // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
653 // after rematerialization. To remove a VNI for a vreg from its LiveInterval,
654 // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all
655 // removed, PHI VNI are still left in the LiveInterval.
656 // So to get rid of unused reg, we need to check whether it has non-dbg
657 // reference instead of whether it has non-empty interval.
658 unsigned ResultPos = 0;
659 for (unsigned Reg : RegsToSpill) {
660 if (MRI.reg_nodbg_empty(Reg)) {
661 Edit->eraseVirtReg(Reg);
662 continue;
663 }
664
665 assert(LIS.hasInterval(Reg) &&(static_cast <bool> (LIS.hasInterval(Reg) && (!
LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
"Empty and not used live-range?!") ? void (0) : __assert_fail
("LIS.hasInterval(Reg) && (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) && \"Empty and not used live-range?!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 667, __extension__ __PRETTY_FUNCTION__))
666 (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&(static_cast <bool> (LIS.hasInterval(Reg) && (!
LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
"Empty and not used live-range?!") ? void (0) : __assert_fail
("LIS.hasInterval(Reg) && (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) && \"Empty and not used live-range?!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 667, __extension__ __PRETTY_FUNCTION__))
667 "Empty and not used live-range?!")(static_cast <bool> (LIS.hasInterval(Reg) && (!
LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&
"Empty and not used live-range?!") ? void (0) : __assert_fail
("LIS.hasInterval(Reg) && (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) && \"Empty and not used live-range?!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 667, __extension__ __PRETTY_FUNCTION__))
;
668
669 RegsToSpill[ResultPos++] = Reg;
670 }
671 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
672 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << RegsToSpill.size() << " registers to spill after remat.\n"
; } } while (false)
;
673}
674
675//===----------------------------------------------------------------------===//
676// Spilling
677//===----------------------------------------------------------------------===//
678
679/// If MI is a load or store of StackSlot, it can be removed.
680bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
681 int FI = 0;
682 unsigned InstrReg = TII.isLoadFromStackSlot(*MI, FI);
683 bool IsLoad = InstrReg;
684 if (!IsLoad)
685 InstrReg = TII.isStoreToStackSlot(*MI, FI);
686
687 // We have a stack access. Is it the right register and slot?
688 if (InstrReg != Reg || FI != StackSlot)
689 return false;
690
691 if (!IsLoad)
692 HSpiller.rmFromMergeableSpills(*MI, StackSlot);
693
694 DEBUG(dbgs() << "Coalescing stack access: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Coalescing stack access: " <<
*MI; } } while (false)
;
695 LIS.RemoveMachineInstrFromMaps(*MI);
696 MI->eraseFromParent();
697
698 if (IsLoad) {
699 ++NumReloadsRemoved;
700 --NumReloads;
701 } else {
702 ++NumSpillsRemoved;
703 --NumSpills;
704 }
705
706 return true;
707}
708
709#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
710LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__))
711// Dump the range of instructions from B to E with their slot indexes.
712static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
713 MachineBasicBlock::iterator E,
714 LiveIntervals const &LIS,
715 const char *const header,
716 unsigned VReg =0) {
717 char NextLine = '\n';
718 char SlotIndent = '\t';
719
720 if (std::next(B) == E) {
721 NextLine = ' ';
722 SlotIndent = ' ';
723 }
724
725 dbgs() << '\t' << header << ": " << NextLine;
726
727 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
728 SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
729
730 // If a register was passed in and this instruction has it as a
731 // destination that is marked as an early clobber, print the
732 // early-clobber slot index.
733 if (VReg) {
734 MachineOperand *MO = I->findRegisterDefOperand(VReg);
735 if (MO && MO->isEarlyClobber())
736 Idx = Idx.getRegSlot(true);
737 }
738
739 dbgs() << SlotIndent << Idx << '\t' << *I;
740 }
741}
742#endif
743
744/// foldMemoryOperand - Try folding stack slot references in Ops into their
745/// instructions.
746///
747/// @param Ops Operand indices from analyzeVirtReg().
748/// @param LoadMI Load instruction to use instead of stack slot when non-null.
749/// @return True on success.
750bool InlineSpiller::
751foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
752 MachineInstr *LoadMI) {
753 if (Ops.empty())
754 return false;
755 // Don't attempt folding in bundles.
756 MachineInstr *MI = Ops.front().first;
757 if (Ops.back().first != MI || MI->isBundled())
758 return false;
759
760 bool WasCopy = MI->isCopy();
761 unsigned ImpReg = 0;
762
763 // Spill subregs if the target allows it.
764 // We always want to spill subregs for stackmap/patchpoint pseudos.
765 bool SpillSubRegs = TII.isSubregFoldable() ||
766 MI->getOpcode() == TargetOpcode::STATEPOINT ||
767 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
768 MI->getOpcode() == TargetOpcode::STACKMAP;
769
770 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
771 // operands.
772 SmallVector<unsigned, 8> FoldOps;
773 for (const auto &OpPair : Ops) {
774 unsigned Idx = OpPair.second;
775 assert(MI == OpPair.first && "Instruction conflict during operand folding")(static_cast <bool> (MI == OpPair.first && "Instruction conflict during operand folding"
) ? void (0) : __assert_fail ("MI == OpPair.first && \"Instruction conflict during operand folding\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 775, __extension__ __PRETTY_FUNCTION__))
;
776 MachineOperand &MO = MI->getOperand(Idx);
777 if (MO.isImplicit()) {
778 ImpReg = MO.getReg();
779 continue;
780 }
781
782 if (!SpillSubRegs && MO.getSubReg())
783 return false;
784 // We cannot fold a load instruction into a def.
785 if (LoadMI && MO.isDef())
786 return false;
787 // Tied use operands should not be passed to foldMemoryOperand.
788 if (!MI->isRegTiedToDefOperand(Idx))
789 FoldOps.push_back(Idx);
790 }
791
792 // If we only have implicit uses, we won't be able to fold that.
793 // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try!
794 if (FoldOps.empty())
795 return false;
796
797 MachineInstrSpan MIS(MI);
798
799 MachineInstr *FoldMI =
800 LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS)
801 : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS);
802 if (!FoldMI)
803 return false;
804
805 // Remove LIS for any dead defs in the original MI not in FoldMI.
806 for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
807 if (!MO->isReg())
808 continue;
809 unsigned Reg = MO->getReg();
810 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
811 MRI.isReserved(Reg)) {
812 continue;
813 }
814 // Skip non-Defs, including undef uses and internal reads.
815 if (MO->isUse())
816 continue;
817 MIBundleOperands::PhysRegInfo RI =
818 MIBundleOperands(*FoldMI).analyzePhysReg(Reg, &TRI);
819 if (RI.FullyDefined)
820 continue;
821 // FoldMI does not define this physreg. Remove the LI segment.
822 assert(MO->isDead() && "Cannot fold physreg def")(static_cast <bool> (MO->isDead() && "Cannot fold physreg def"
) ? void (0) : __assert_fail ("MO->isDead() && \"Cannot fold physreg def\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 822, __extension__ __PRETTY_FUNCTION__))
;
823 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
824 LIS.removePhysRegDefAt(Reg, Idx);
825 }
826
827 int FI;
828 if (TII.isStoreToStackSlot(*MI, FI) &&
829 HSpiller.rmFromMergeableSpills(*MI, FI))
830 --NumSpills;
831 LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
832 MI->eraseFromParent();
833
834 // Insert any new instructions other than FoldMI into the LIS maps.
835 assert(!MIS.empty() && "Unexpected empty span of instructions!")(static_cast <bool> (!MIS.empty() && "Unexpected empty span of instructions!"
) ? void (0) : __assert_fail ("!MIS.empty() && \"Unexpected empty span of instructions!\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 835, __extension__ __PRETTY_FUNCTION__))
;
836 for (MachineInstr &MI : MIS)
837 if (&MI != FoldMI)
838 LIS.InsertMachineInstrInMaps(MI);
839
840 // TII.foldMemoryOperand may have left some implicit operands on the
841 // instruction. Strip them.
842 if (ImpReg)
843 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
844 MachineOperand &MO = FoldMI->getOperand(i - 1);
845 if (!MO.isReg() || !MO.isImplicit())
846 break;
847 if (MO.getReg() == ImpReg)
848 FoldMI->RemoveOperand(i - 1);
849 }
850
851 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MIS.end(), LIS, "folded"); } } while (false)
852 "folded"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MIS.end(), LIS, "folded"); } } while (false)
;
853
854 if (!WasCopy)
855 ++NumFolded;
856 else if (Ops.front().second == 0) {
857 ++NumSpills;
858 HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
859 } else
860 ++NumReloads;
861 return true;
862}
863
864void InlineSpiller::insertReload(unsigned NewVReg,
865 SlotIndex Idx,
866 MachineBasicBlock::iterator MI) {
867 MachineBasicBlock &MBB = *MI->getParent();
868
869 MachineInstrSpan MIS(MI);
870 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
871 MRI.getRegClass(NewVReg), &TRI);
872
873 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
874
875 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MI, LIS, "reload", NewVReg); } } while (false)
876 NewVReg))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MI, LIS, "reload", NewVReg); } } while (false)
;
877 ++NumReloads;
878}
879
880/// Check if \p Def fully defines a VReg with an undefined value.
881/// If that's the case, that means the value of VReg is actually
882/// not relevant.
883static bool isFullUndefDef(const MachineInstr &Def) {
884 if (!Def.isImplicitDef())
885 return false;
886 assert(Def.getNumOperands() == 1 &&(static_cast <bool> (Def.getNumOperands() == 1 &&
"Implicit def with more than one definition") ? void (0) : __assert_fail
("Def.getNumOperands() == 1 && \"Implicit def with more than one definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 887, __extension__ __PRETTY_FUNCTION__))
887 "Implicit def with more than one definition")(static_cast <bool> (Def.getNumOperands() == 1 &&
"Implicit def with more than one definition") ? void (0) : __assert_fail
("Def.getNumOperands() == 1 && \"Implicit def with more than one definition\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 887, __extension__ __PRETTY_FUNCTION__))
;
888 // We can say that the VReg defined by Def is undef, only if it is
889 // fully defined by Def. Otherwise, some of the lanes may not be
890 // undef and the value of the VReg matters.
891 return !Def.getOperand(0).getSubReg();
892}
893
894/// insertSpill - Insert a spill of NewVReg after MI.
895void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
896 MachineBasicBlock::iterator MI) {
897 MachineBasicBlock &MBB = *MI->getParent();
898
899 MachineInstrSpan MIS(MI);
900 bool IsRealSpill = true;
901 if (isFullUndefDef(*MI)) {
902 // Don't spill undef value.
903 // Anything works for undef, in particular keeping the memory
904 // uninitialized is a viable option and it saves code size and
905 // run time.
906 BuildMI(MBB, std::next(MI), MI->getDebugLoc(), TII.get(TargetOpcode::KILL))
907 .addReg(NewVReg, getKillRegState(isKill));
908 IsRealSpill = false;
909 } else
910 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
911 MRI.getRegClass(NewVReg), &TRI);
912
913 LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
914
915 DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(std::next(
MI), MIS.end(), LIS, "spill"); } } while (false)
916 "spill"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(std::next(
MI), MIS.end(), LIS, "spill"); } } while (false)
;
917 ++NumSpills;
918 if (IsRealSpill)
919 HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
920}
921
922/// spillAroundUses - insert spill code around each use of Reg.
923void InlineSpiller::spillAroundUses(unsigned Reg) {
924 DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "spillAroundUses " << printReg
(Reg) << '\n'; } } while (false)
;
925 LiveInterval &OldLI = LIS.getInterval(Reg);
926
927 // Iterate over instructions using Reg.
928 for (MachineRegisterInfo::reg_bundle_iterator
929 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
930 RegI != E; ) {
931 MachineInstr *MI = &*(RegI++);
932
933 // Debug values are not allowed to affect codegen.
934 if (MI->isDebugValue()) {
935 // Modify DBG_VALUE now that the value is in a spill slot.
936 MachineBasicBlock *MBB = MI->getParent();
937 DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Modifying debug info due to spill:\t"
<< *MI; } } while (false)
;
938 buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
939 MBB->erase(MI);
940 continue;
941 }
942
943 // Ignore copies to/from snippets. We'll delete them.
944 if (SnippetCopies.count(MI))
945 continue;
946
947 // Stack slot accesses may coalesce away.
948 if (coalesceStackAccess(MI, Reg))
949 continue;
950
951 // Analyze instruction.
952 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
953 MIBundleOperands::VirtRegInfo RI =
954 MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops);
955
956 // Find the slot index where this instruction reads and writes OldLI.
957 // This is usually the def slot, except for tied early clobbers.
958 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
959 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
960 if (SlotIndex::isSameInstr(Idx, VNI->def))
961 Idx = VNI->def;
962
963 // Check for a sibling copy.
964 unsigned SibReg = isFullCopyOf(*MI, Reg);
965 if (SibReg && isSibling(SibReg)) {
966 // This may actually be a copy between snippets.
967 if (isRegToSpill(SibReg)) {
968 DEBUG(dbgs() << "Found new snippet copy: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Found new snippet copy: " <<
*MI; } } while (false)
;
969 SnippetCopies.insert(MI);
970 continue;
971 }
972 if (RI.Writes) {
973 if (hoistSpillInsideBB(OldLI, *MI)) {
974 // This COPY is now dead, the value is already in the stack slot.
975 MI->getOperand(0).setIsDead();
976 DeadDefs.push_back(MI);
977 continue;
978 }
979 } else {
980 // This is a reload for a sib-reg copy. Drop spills downstream.
981 LiveInterval &SibLI = LIS.getInterval(SibReg);
982 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
983 // The COPY will fold to a reload below.
984 }
985 }
986
987 // Attempt to fold memory ops.
988 if (foldMemoryOperand(Ops))
989 continue;
990
991 // Create a new virtual register for spill/fill.
992 // FIXME: Infer regclass from instruction alone.
993 unsigned NewVReg = Edit->createFrom(Reg);
994
995 if (RI.Reads)
996 insertReload(NewVReg, Idx, MI);
997
998 // Rewrite instruction operands.
999 bool hasLiveDef = false;
1000 for (const auto &OpPair : Ops) {
1001 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
1002 MO.setReg(NewVReg);
1003 if (MO.isUse()) {
1004 if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
1005 MO.setIsKill();
1006 } else {
1007 if (!MO.isDead())
1008 hasLiveDef = true;
1009 }
1010 }
1011 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\trewrite: " << Idx <<
'\t' << *MI << '\n'; } } while (false)
;
1012
1013 // FIXME: Use a second vreg if instruction has no tied ops.
1014 if (RI.Writes)
1015 if (hasLiveDef)
1016 insertSpill(NewVReg, true, MI);
1017 }
1018}
1019
1020/// spillAll - Spill all registers remaining after rematerialization.
1021void InlineSpiller::spillAll() {
1022 // Update LiveStacks now that we are committed to spilling.
1023 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1024 StackSlot = VRM.assignVirt2StackSlot(Original);
1025 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1026 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
1027 } else
1028 StackInt = &LSS.getInterval(StackSlot);
1029
1030 if (Original != Edit->getReg())
1031 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
1032
1033 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values")(static_cast <bool> (StackInt->getNumValNums() == 1 &&
"Bad stack interval values") ? void (0) : __assert_fail ("StackInt->getNumValNums() == 1 && \"Bad stack interval values\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1033, __extension__ __PRETTY_FUNCTION__))
;
1034 for (unsigned Reg : RegsToSpill)
1035 StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
1036 StackInt->getValNumInfo(0));
1037 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Merged spilled regs: " <<
*StackInt << '\n'; } } while (false)
;
1038
1039 // Spill around uses of all RegsToSpill.
1040 for (unsigned Reg : RegsToSpill)
1041 spillAroundUses(Reg);
1042
1043 // Hoisted spills may cause dead code.
1044 if (!DeadDefs.empty()) {
1045 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Eliminating " << DeadDefs
.size() << " dead defs\n"; } } while (false)
;
1046 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
1047 }
1048
1049 // Finally delete the SnippetCopies.
1050 for (unsigned Reg : RegsToSpill) {
1051 for (MachineRegisterInfo::reg_instr_iterator
1052 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
1053 RI != E; ) {
1054 MachineInstr &MI = *(RI++);
1055 assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy")(static_cast <bool> (SnippetCopies.count(&MI) &&
"Remaining use wasn't a snippet copy") ? void (0) : __assert_fail
("SnippetCopies.count(&MI) && \"Remaining use wasn't a snippet copy\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1055, __extension__ __PRETTY_FUNCTION__))
;
1056 // FIXME: Do this with a LiveRangeEdit callback.
1057 LIS.RemoveMachineInstrFromMaps(MI);
1058 MI.eraseFromParent();
1059 }
1060 }
1061
1062 // Delete all spilled registers.
1063 for (unsigned Reg : RegsToSpill)
1064 Edit->eraseVirtReg(Reg);
1065}
1066
1067void InlineSpiller::spill(LiveRangeEdit &edit) {
1068 ++NumSpilledRanges;
1069 Edit = &edit;
1070 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())(static_cast <bool> (!TargetRegisterInfo::isStackSlot(edit
.getReg()) && "Trying to spill a stack slot.") ? void
(0) : __assert_fail ("!TargetRegisterInfo::isStackSlot(edit.getReg()) && \"Trying to spill a stack slot.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1071, __extension__ __PRETTY_FUNCTION__))
1071 && "Trying to spill a stack slot.")(static_cast <bool> (!TargetRegisterInfo::isStackSlot(edit
.getReg()) && "Trying to spill a stack slot.") ? void
(0) : __assert_fail ("!TargetRegisterInfo::isStackSlot(edit.getReg()) && \"Trying to spill a stack slot.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1071, __extension__ __PRETTY_FUNCTION__))
;
1072 // Share a stack slot among all descendants of Original.
1073 Original = VRM.getOriginal(edit.getReg());
1074 StackSlot = VRM.getStackSlot(Original);
1075 StackInt = nullptr;
1076
1077 DEBUG(dbgs() << "Inline spilling "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
printReg(Original) << '\n'; } } while (false)
1078 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
printReg(Original) << '\n'; } } while (false)
1079 << ':' << edit.getParent()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
printReg(Original) << '\n'; } } while (false)
1080 << "\nFrom original " << printReg(Original) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
printReg(Original) << '\n'; } } while (false)
;
1081 assert(edit.getParent().isSpillable() &&(static_cast <bool> (edit.getParent().isSpillable() &&
"Attempting to spill already spilled value.") ? void (0) : __assert_fail
("edit.getParent().isSpillable() && \"Attempting to spill already spilled value.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1082, __extension__ __PRETTY_FUNCTION__))
1082 "Attempting to spill already spilled value.")(static_cast <bool> (edit.getParent().isSpillable() &&
"Attempting to spill already spilled value.") ? void (0) : __assert_fail
("edit.getParent().isSpillable() && \"Attempting to spill already spilled value.\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1082, __extension__ __PRETTY_FUNCTION__))
;
1083 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs")(static_cast <bool> (DeadDefs.empty() && "Previous spill didn't remove dead defs"
) ? void (0) : __assert_fail ("DeadDefs.empty() && \"Previous spill didn't remove dead defs\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1083, __extension__ __PRETTY_FUNCTION__))
;
1084
1085 collectRegsToSpill();
1086 reMaterializeAll();
1087
1088 // Remat may handle everything.
1089 if (!RegsToSpill.empty())
1090 spillAll();
1091
1092 Edit->calculateRegClassAndHint(MF, Loops, MBFI);
1093}
1094
1095/// Optimizations after all the reg selections and spills are done.
1096void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
1097
1098/// When a spill is inserted, add the spill to MergeableSpills map.
1099void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1100 unsigned Original) {
1101 BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
1102 LiveInterval &OrigLI = LIS.getInterval(Original);
1103 // save a copy of LiveInterval in StackSlotToOrigLI because the original
1104 // LiveInterval may be cleared after all its references are spilled.
1105 if (StackSlotToOrigLI.find(StackSlot) == StackSlotToOrigLI.end()) {
1106 auto LI = llvm::make_unique<LiveInterval>(OrigLI.reg, OrigLI.weight);
1107 LI->assign(OrigLI, Allocator);
1108 StackSlotToOrigLI[StackSlot] = std::move(LI);
1109 }
1110 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1111 VNInfo *OrigVNI = StackSlotToOrigLI[StackSlot]->getVNInfoAt(Idx.getRegSlot());
1112 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1113 MergeableSpills[MIdx].insert(&Spill);
1114}
1115
1116/// When a spill is removed, remove the spill from MergeableSpills map.
1117/// Return true if the spill is removed successfully.
1118bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
1119 int StackSlot) {
1120 auto It = StackSlotToOrigLI.find(StackSlot);
1121 if (It == StackSlotToOrigLI.end())
1122 return false;
1123 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1124 VNInfo *OrigVNI = It->second->getVNInfoAt(Idx.getRegSlot());
1125 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1126 return MergeableSpills[MIdx].erase(&Spill);
1127}
1128
1129/// Check BB to see if it is a possible target BB to place a hoisted spill,
1130/// i.e., there should be a living sibling of OrigReg at the insert point.
1131bool HoistSpillHelper::isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI,
1132 MachineBasicBlock &BB, unsigned &LiveReg) {
1133 SlotIndex Idx;
1134 unsigned OrigReg = OrigLI.reg;
1135 MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, BB);
1136 if (MI != BB.end())
1137 Idx = LIS.getInstructionIndex(*MI);
1138 else
1139 Idx = LIS.getMBBEndIdx(&BB).getPrevSlot();
1140 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1141 assert(OrigLI.getVNInfoAt(Idx) == &OrigVNI && "Unexpected VNI")(static_cast <bool> (OrigLI.getVNInfoAt(Idx) == &OrigVNI
&& "Unexpected VNI") ? void (0) : __assert_fail ("OrigLI.getVNInfoAt(Idx) == &OrigVNI && \"Unexpected VNI\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1141, __extension__ __PRETTY_FUNCTION__))
;
1142
1143 for (auto const SibReg : Siblings) {
1144 LiveInterval &LI = LIS.getInterval(SibReg);
1145 VNInfo *VNI = LI.getVNInfoAt(Idx);
1146 if (VNI) {
1147 LiveReg = SibReg;
1148 return true;
1149 }
1150 }
1151 return false;
1152}
1153
1154/// Remove redundant spills in the same BB. Save those redundant spills in
1155/// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
1156void HoistSpillHelper::rmRedundantSpills(
1157 SmallPtrSet<MachineInstr *, 16> &Spills,
1158 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1159 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1160 // For each spill saw, check SpillBBToSpill[] and see if its BB already has
1161 // another spill inside. If a BB contains more than one spill, only keep the
1162 // earlier spill with smaller SlotIndex.
1163 for (const auto CurrentSpill : Spills) {
1164 MachineBasicBlock *Block = CurrentSpill->getParent();
1165 MachineDomTreeNode *Node = MDT.getBase().getNode(Block);
1166 MachineInstr *PrevSpill = SpillBBToSpill[Node];
1167 if (PrevSpill) {
1168 SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill);
1169 SlotIndex CIdx = LIS.getInstructionIndex(*CurrentSpill);
1170 MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1171 MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
1172 SpillsToRm.push_back(SpillToRm);
1173 SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep;
1174 } else {
1175 SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill;
1176 }
1177 }
1178 for (const auto SpillToRm : SpillsToRm)
1179 Spills.erase(SpillToRm);
1180}
1181
1182/// Starting from \p Root find a top-down traversal order of the dominator
1183/// tree to visit all basic blocks containing the elements of \p Spills.
1184/// Redundant spills will be found and put into \p SpillsToRm at the same
1185/// time. \p SpillBBToSpill will be populated as part of the process and
1186/// maps a basic block to the first store occurring in the basic block.
1187/// \post SpillsToRm.union(Spills\@post) == Spills\@pre
1188void HoistSpillHelper::getVisitOrders(
1189 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
1190 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1191 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1192 DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
1193 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1194 // The set contains all the possible BB nodes to which we may hoist
1195 // original spills.
1196 SmallPtrSet<MachineDomTreeNode *, 8> WorkSet;
1197 // Save the BB nodes on the path from the first BB node containing
1198 // non-redundant spill to the Root node.
1199 SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath;
1200 // All the spills to be hoisted must originate from a single def instruction
1201 // to the OrigReg. It means the def instruction should dominate all the spills
1202 // to be hoisted. We choose the BB where the def instruction is located as
1203 // the Root.
1204 MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom();
1205 // For every node on the dominator tree with spill, walk up on the dominator
1206 // tree towards the Root node until it is reached. If there is other node
1207 // containing spill in the middle of the path, the previous spill saw will
1208 // be redundant and the node containing it will be removed. All the nodes on
1209 // the path starting from the first node with non-redundant spill to the Root
1210 // node will be added to the WorkSet, which will contain all the possible
1211 // locations where spills may be hoisted to after the loop below is done.
1212 for (const auto Spill : Spills) {
1213 MachineBasicBlock *Block = Spill->getParent();
1214 MachineDomTreeNode *Node = MDT[Block];
1215 MachineInstr *SpillToRm = nullptr;
1216 while (Node != RootIDomNode) {
1217 // If Node dominates Block, and it already contains a spill, the spill in
1218 // Block will be redundant.
1219 if (Node != MDT[Block] && SpillBBToSpill[Node]) {
1220 SpillToRm = SpillBBToSpill[MDT[Block]];
1221 break;
1222 /// If we see the Node already in WorkSet, the path from the Node to
1223 /// the Root node must already be traversed by another spill.
1224 /// Then no need to repeat.
1225 } else if (WorkSet.count(Node)) {
1226 break;
1227 } else {
1228 NodesOnPath.insert(Node);
1229 }
1230 Node = Node->getIDom();
1231 }
1232 if (SpillToRm) {
1233 SpillsToRm.push_back(SpillToRm);
1234 } else {
1235 // Add a BB containing the original spills to SpillsToKeep -- i.e.,
1236 // set the initial status before hoisting start. The value of BBs
1237 // containing original spills is set to 0, in order to descriminate
1238 // with BBs containing hoisted spills which will be inserted to
1239 // SpillsToKeep later during hoisting.
1240 SpillsToKeep[MDT[Block]] = 0;
1241 WorkSet.insert(NodesOnPath.begin(), NodesOnPath.end());
1242 }
1243 NodesOnPath.clear();
1244 }
1245
1246 // Sort the nodes in WorkSet in top-down order and save the nodes
1247 // in Orders. Orders will be used for hoisting in runHoistSpills.
1248 unsigned idx = 0;
1249 Orders.push_back(MDT.getBase().getNode(Root));
1250 do {
1251 MachineDomTreeNode *Node = Orders[idx++];
1252 const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
1253 unsigned NumChildren = Children.size();
1254 for (unsigned i = 0; i != NumChildren; ++i) {
1255 MachineDomTreeNode *Child = Children[i];
1256 if (WorkSet.count(Child))
1257 Orders.push_back(Child);
1258 }
1259 } while (idx != Orders.size());
1260 assert(Orders.size() == WorkSet.size() &&(static_cast <bool> (Orders.size() == WorkSet.size() &&
"Orders have different size with WorkSet") ? void (0) : __assert_fail
("Orders.size() == WorkSet.size() && \"Orders have different size with WorkSet\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1261, __extension__ __PRETTY_FUNCTION__))
1261 "Orders have different size with WorkSet")(static_cast <bool> (Orders.size() == WorkSet.size() &&
"Orders have different size with WorkSet") ? void (0) : __assert_fail
("Orders.size() == WorkSet.size() && \"Orders have different size with WorkSet\""
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1261, __extension__ __PRETTY_FUNCTION__))
;
1262
1263#ifndef NDEBUG
1264 DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Orders size is " << Orders
.size() << "\n"; } } while (false)
;
1265 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1266 for (; RIt != Orders.rend(); RIt++)
1267 DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "BB" << (*RIt)->getBlock
()->getNumber() << ","; } } while (false)
;
1268 DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\n"; } } while (false)
;
1269#endif
1270}
1271
1272/// Try to hoist spills according to BB hotness. The spills to removed will
1273/// be saved in \p SpillsToRm. The spills to be inserted will be saved in
1274/// \p SpillsToIns.
1275void HoistSpillHelper::runHoistSpills(
1276 LiveInterval &OrigLI, VNInfo &OrigVNI,
1277 SmallPtrSet<MachineInstr *, 16> &Spills,
1278 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1279 DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) {
1280 // Visit order of dominator tree nodes.
1281 SmallVector<MachineDomTreeNode *, 32> Orders;
1282 // SpillsToKeep contains all the nodes where spills are to be inserted
1283 // during hoisting. If the spill to be inserted is an original spill
1284 // (not a hoisted one), the value of the map entry is 0. If the spill
1285 // is a hoisted spill, the value of the map entry is the VReg to be used
1286 // as the source of the spill.
1287 DenseMap<MachineDomTreeNode *, unsigned> SpillsToKeep;
1288 // Map from BB to the first spill inside of it.
1289 DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
1290
1291 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill);
1292
1293 MachineBasicBlock *Root = LIS.getMBBFromIndex(OrigVNI.def);
1294 getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep,
1295 SpillBBToSpill);
1296
1297 // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of
1298 // nodes set and the cost of all the spills inside those nodes.
1299 // The nodes set are the locations where spills are to be inserted
1300 // in the subtree of current node.
1301 using NodesCostPair =
1302 std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>;
1303 DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap;
1304
1305 // Iterate Orders set in reverse order, which will be a bottom-up order
1306 // in the dominator tree. Once we visit a dom tree node, we know its
1307 // children have already been visited and the spill locations in the
1308 // subtrees of all the children have been determined.
1309 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1310 for (; RIt != Orders.rend(); RIt++) {
1311 MachineBasicBlock *Block = (*RIt)->getBlock();
1312
1313 // If Block contains an original spill, simply continue.
1314 if (SpillsToKeep.find(*RIt) != SpillsToKeep.end() && !SpillsToKeep[*RIt]) {
1315 SpillsInSubTreeMap[*RIt].first.insert(*RIt);
1316 // SpillsInSubTreeMap[*RIt].second contains the cost of spill.
1317 SpillsInSubTreeMap[*RIt].second = MBFI.getBlockFreq(Block);
1318 continue;
1319 }
1320
1321 // Collect spills in subtree of current node (*RIt) to
1322 // SpillsInSubTreeMap[*RIt].first.
1323 const std::vector<MachineDomTreeNode *> &Children = (*RIt)->getChildren();
1324 unsigned NumChildren = Children.size();
1325 for (unsigned i = 0; i != NumChildren; ++i) {
1326 MachineDomTreeNode *Child = Children[i];
1327 if (SpillsInSubTreeMap.find(Child) == SpillsInSubTreeMap.end())
1328 continue;
1329 // The stmt "SpillsInSubTree = SpillsInSubTreeMap[*RIt].first" below
1330 // should be placed before getting the begin and end iterators of
1331 // SpillsInSubTreeMap[Child].first, or else the iterators may be
1332 // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time
1333 // and the map grows and then the original buckets in the map are moved.
1334 SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1335 SpillsInSubTreeMap[*RIt].first;
1336 BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1337 SubTreeCost += SpillsInSubTreeMap[Child].second;
1338 auto BI = SpillsInSubTreeMap[Child].first.begin();
1339 auto EI = SpillsInSubTreeMap[Child].first.end();
1340 SpillsInSubTree.insert(BI, EI);
1341 SpillsInSubTreeMap.erase(Child);
1342 }
1343
1344 SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1345 SpillsInSubTreeMap[*RIt].first;
1346 BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1347 // No spills in subtree, simply continue.
1348 if (SpillsInSubTree.empty())
1349 continue;
1350
1351 // Check whether Block is a possible candidate to insert spill.
1352 unsigned LiveReg = 0;
1353 if (!isSpillCandBB(OrigLI, OrigVNI, *Block, LiveReg))
1354 continue;
1355
1356 // If there are multiple spills that could be merged, bias a little
1357 // to hoist the spill.
1358 BranchProbability MarginProb = (SpillsInSubTree.size() > 1)
1359 ? BranchProbability(9, 10)
1360 : BranchProbability(1, 1);
1361 if (SubTreeCost > MBFI.getBlockFreq(Block) * MarginProb) {
1362 // Hoist: Move spills to current Block.
1363 for (const auto SpillBB : SpillsInSubTree) {
1364 // When SpillBB is a BB contains original spill, insert the spill
1365 // to SpillsToRm.
1366 if (SpillsToKeep.find(SpillBB) != SpillsToKeep.end() &&
1367 !SpillsToKeep[SpillBB]) {
1368 MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
1369 SpillsToRm.push_back(SpillToRm);
1370 }
1371 // SpillBB will not contain spill anymore, remove it from SpillsToKeep.
1372 SpillsToKeep.erase(SpillBB);
1373 }
1374 // Current Block is the BB containing the new hoisted spill. Add it to
1375 // SpillsToKeep. LiveReg is the source of the new spill.
1376 SpillsToKeep[*RIt] = LiveReg;
1377 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1378 dbgs() << "spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1379 for (const auto Rspill : SpillsInSubTree)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1380 dbgs() << Rspill->getBlock()->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1381 dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1382 << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1383 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
;
1384 SpillsInSubTree.clear();
1385 SpillsInSubTree.insert(*RIt);
1386 SubTreeCost = MBFI.getBlockFreq(Block);
1387 }
1388 }
1389 // For spills in SpillsToKeep with LiveReg set (i.e., not original spill),
1390 // save them to SpillsToIns.
1391 for (const auto Ent : SpillsToKeep) {
1392 if (Ent.second)
1393 SpillsToIns[Ent.first->getBlock()] = Ent.second;
1394 }
1395}
1396
1397/// For spills with equal values, remove redundant spills and hoist those left
1398/// to less hot spots.
1399///
1400/// Spills with equal values will be collected into the same set in
1401/// MergeableSpills when spill is inserted. These equal spills are originated
1402/// from the same defining instruction and are dominated by the instruction.
1403/// Before hoisting all the equal spills, redundant spills inside in the same
1404/// BB are first marked to be deleted. Then starting from the spills left, walk
1405/// up on the dominator tree towards the Root node where the define instruction
1406/// is located, mark the dominated spills to be deleted along the way and
1407/// collect the BB nodes on the path from non-dominated spills to the define
1408/// instruction into a WorkSet. The nodes in WorkSet are the candidate places
1409/// where we are considering to hoist the spills. We iterate the WorkSet in
1410/// bottom-up order, and for each node, we will decide whether to hoist spills
1411/// inside its subtree to that node. In this way, we can get benefit locally
1412/// even if hoisting all the equal spills to one cold place is impossible.
1413void HoistSpillHelper::hoistAllSpills() {
1414 SmallVector<unsigned, 4> NewVRegs;
1415 LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
1416
1417 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
1418 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1419 unsigned Original = VRM.getPreSplitReg(Reg);
1420 if (!MRI.def_empty(Reg))
1421 Virt2SiblingsMap[Original].insert(Reg);
1422 }
1423
1424 // Each entry in MergeableSpills contains a spill set with equal values.
1425 for (auto &Ent : MergeableSpills) {
1426 int Slot = Ent.first.first;
1427 LiveInterval &OrigLI = *StackSlotToOrigLI[Slot];
1428 VNInfo *OrigVNI = Ent.first.second;
1429 SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
1430 if (Ent.second.empty())
1431 continue;
1432
1433 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1434 dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1435 << "Equal spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1436 for (const auto spill : EqValSpills)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1437 dbgs() << spill->getParent()->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1438 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1439 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
;
1440
1441 // SpillsToRm is the spill set to be removed from EqValSpills.
1442 SmallVector<MachineInstr *, 16> SpillsToRm;
1443 // SpillsToIns is the spill set to be newly inserted after hoisting.
1444 DenseMap<MachineBasicBlock *, unsigned> SpillsToIns;
1445
1446 runHoistSpills(OrigLI, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);
1447
1448 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1449 dbgs() << "Finally inserted spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1450 for (const auto Ispill : SpillsToIns)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1451 dbgs() << Ispill.first->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1452 dbgs() << "\nFinally removed spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1453 for (const auto Rspill : SpillsToRm)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1454 dbgs() << Rspill->getParent()->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1455 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1456 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
;
1457
1458 // Stack live range update.
1459 LiveInterval &StackIntvl = LSS.getInterval(Slot);
1460 if (!SpillsToIns.empty() || !SpillsToRm.empty())
1461 StackIntvl.MergeValueInAsValue(OrigLI, OrigVNI,
1462 StackIntvl.getValNumInfo(0));
1463
1464 // Insert hoisted spills.
1465 for (auto const Insert : SpillsToIns) {
1466 MachineBasicBlock *BB = Insert.first;
1467 unsigned LiveReg = Insert.second;
1468 MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
1469 TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
1470 MRI.getRegClass(LiveReg), &TRI);
1471 LIS.InsertMachineInstrRangeInMaps(std::prev(MI), MI);
1472 ++NumSpills;
1473 }
1474
1475 // Remove redundant spills or change them to dead instructions.
1476 NumSpills -= SpillsToRm.size();
1477 for (auto const RMEnt : SpillsToRm) {
1478 RMEnt->setDesc(TII.get(TargetOpcode::KILL));
1479 for (unsigned i = RMEnt->getNumOperands(); i; --i) {
1480 MachineOperand &MO = RMEnt->getOperand(i - 1);
1481 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
1482 RMEnt->RemoveOperand(i - 1);
1483 }
1484 }
1485 Edit.eliminateDeadDefs(SpillsToRm, None, AA);
1486 }
1487}
1488
1489/// For VirtReg clone, the \p New register should have the same physreg or
1490/// stackslot as the \p old register.
1491void HoistSpillHelper::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
1492 if (VRM.hasPhys(Old))
1493 VRM.assignVirt2Phys(New, VRM.getPhys(Old));
1494 else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT)
1495 VRM.assignVirt2StackSlot(New, VRM.getStackSlot(Old));
1496 else
1497 llvm_unreachable("VReg should be assigned either physreg or stackslot")::llvm::llvm_unreachable_internal("VReg should be assigned either physreg or stackslot"
, "/build/llvm-toolchain-snapshot-7~svn329677/lib/CodeGen/InlineSpiller.cpp"
, 1497)
;
1498}

/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h

1//===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the target machine instruction set to the code generator.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_TARGET_TARGETINSTRINFO_H
15#define LLVM_TARGET_TARGETINSTRINFO_H
16
17#include "llvm/ADT/ArrayRef.h"
18#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/DenseMapInfo.h"
20#include "llvm/ADT/None.h"
21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineCombinerPattern.h"
23#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/MachineInstr.h"
25#include "llvm/CodeGen/MachineLoopInfo.h"
26#include "llvm/CodeGen/MachineOperand.h"
27#include "llvm/CodeGen/PseudoSourceValue.h"
28#include "llvm/MC/MCInstrInfo.h"
29#include "llvm/Support/BranchProbability.h"
30#include "llvm/Support/ErrorHandling.h"
31#include <cassert>
32#include <cstddef>
33#include <cstdint>
34#include <utility>
35#include <vector>
36
37namespace llvm {
38
39class DFAPacketizer;
40class InstrItineraryData;
41class LiveIntervals;
42class LiveVariables;
43class MachineMemOperand;
44class MachineRegisterInfo;
45class MCAsmInfo;
46class MCInst;
47struct MCSchedModel;
48class Module;
49class ScheduleDAG;
50class ScheduleHazardRecognizer;
51class SDNode;
52class SelectionDAG;
53class RegScavenger;
54class TargetRegisterClass;
55class TargetRegisterInfo;
56class TargetSchedModel;
57class TargetSubtargetInfo;
58
59template <class T> class SmallVectorImpl;
60
61//---------------------------------------------------------------------------
62///
63/// TargetInstrInfo - Interface to description of machine instruction set
64///
65class TargetInstrInfo : public MCInstrInfo {
66public:
67 TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u,
68 unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u)
69 : CallFrameSetupOpcode(CFSetupOpcode),
70 CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode),
71 ReturnOpcode(ReturnOpcode) {}
72 TargetInstrInfo(const TargetInstrInfo &) = delete;
73 TargetInstrInfo &operator=(const TargetInstrInfo &) = delete;
74 virtual ~TargetInstrInfo();
75
76 static bool isGenericOpcode(unsigned Opc) {
77 return Opc <= TargetOpcode::GENERIC_OP_END;
78 }
79
80 /// Given a machine instruction descriptor, returns the register
81 /// class constraint for OpNum, or NULL.
82 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
83 const TargetRegisterInfo *TRI,
84 const MachineFunction &MF) const;
85
86 /// Return true if the instruction is trivially rematerializable, meaning it
87 /// has no side effects and requires no operands that aren't always available.
88 /// This means the only allowed uses are constants and unallocatable physical
89 /// registers so that the instructions result is independent of the place
90 /// in the function.
91 bool isTriviallyReMaterializable(const MachineInstr &MI,
92 AliasAnalysis *AA = nullptr) const {
93 return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF ||
94 (MI.getDesc().isRematerializable() &&
95 (isReallyTriviallyReMaterializable(MI, AA) ||
96 isReallyTriviallyReMaterializableGeneric(MI, AA)));
97 }
98
99protected:
100 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
101 /// set, this hook lets the target specify whether the instruction is actually
102 /// trivially rematerializable, taking into consideration its operands. This
103 /// predicate must return false if the instruction has any side effects other
104 /// than producing a value, or if it requres any address registers that are
105 /// not always available.
106 /// Requirements must be check as stated in isTriviallyReMaterializable() .
107 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
108 AliasAnalysis *AA) const {
109 return false;
110 }
111
112 /// This method commutes the operands of the given machine instruction MI.
113 /// The operands to be commuted are specified by their indices OpIdx1 and
114 /// OpIdx2.
115 ///
116 /// If a target has any instructions that are commutable but require
117 /// converting to different instructions or making non-trivial changes
118 /// to commute them, this method can be overloaded to do that.
119 /// The default implementation simply swaps the commutable operands.
120 ///
121 /// If NewMI is false, MI is modified in place and returned; otherwise, a
122 /// new machine instruction is created and returned.
123 ///
124 /// Do not call this method for a non-commutable instruction.
125 /// Even though the instruction is commutable, the method may still
126 /// fail to commute the operands, null pointer is returned in such cases.
127 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
128 unsigned OpIdx1,
129 unsigned OpIdx2) const;
130
131 /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable
132 /// operand indices to (ResultIdx1, ResultIdx2).
133 /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be
134 /// predefined to some indices or be undefined (designated by the special
135 /// value 'CommuteAnyOperandIndex').
136 /// The predefined result indices cannot be re-defined.
137 /// The function returns true iff after the result pair redefinition
138 /// the fixed result pair is equal to or equivalent to the source pair of
139 /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that
140 /// the pairs (x,y) and (y,x) are equivalent.
141 static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2,
142 unsigned CommutableOpIdx1,
143 unsigned CommutableOpIdx2);
144
145private:
146 /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is
147 /// set and the target hook isReallyTriviallyReMaterializable returns false,
148 /// this function does target-independent tests to determine if the
149 /// instruction is really trivially rematerializable.
150 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
151 AliasAnalysis *AA) const;
152
153public:
154 /// These methods return the opcode of the frame setup/destroy instructions
155 /// if they exist (-1 otherwise). Some targets use pseudo instructions in
156 /// order to abstract away the difference between operating with a frame
157 /// pointer and operating without, through the use of these two instructions.
158 ///
159 unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
160 unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
161
162 /// Returns true if the argument is a frame pseudo instruction.
163 bool isFrameInstr(const MachineInstr &I) const {
164 return I.getOpcode() == getCallFrameSetupOpcode() ||
165 I.getOpcode() == getCallFrameDestroyOpcode();
166 }
167
168 /// Returns true if the argument is a frame setup pseudo instruction.
169 bool isFrameSetup(const MachineInstr &I) const {
170 return I.getOpcode() == getCallFrameSetupOpcode();
171 }
172
173 /// Returns size of the frame associated with the given frame instruction.
174 /// For frame setup instruction this is frame that is set up space set up
175 /// after the instruction. For frame destroy instruction this is the frame
176 /// freed by the caller.
177 /// Note, in some cases a call frame (or a part of it) may be prepared prior
178 /// to the frame setup instruction. It occurs in the calls that involve
179 /// inalloca arguments. This function reports only the size of the frame part
180 /// that is set up between the frame setup and destroy pseudo instructions.
181 int64_t getFrameSize(const MachineInstr &I) const {
182 assert(isFrameInstr(I) && "Not a frame instruction")(static_cast <bool> (isFrameInstr(I) && "Not a frame instruction"
) ? void (0) : __assert_fail ("isFrameInstr(I) && \"Not a frame instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 182, __extension__ __PRETTY_FUNCTION__))
;
183 assert(I.getOperand(0).getImm() >= 0)(static_cast <bool> (I.getOperand(0).getImm() >= 0) ?
void (0) : __assert_fail ("I.getOperand(0).getImm() >= 0"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 183, __extension__ __PRETTY_FUNCTION__))
;
184 return I.getOperand(0).getImm();
185 }
186
187 /// Returns the total frame size, which is made up of the space set up inside
188 /// the pair of frame start-stop instructions and the space that is set up
189 /// prior to the pair.
190 int64_t getFrameTotalSize(const MachineInstr &I) const {
191 if (isFrameSetup(I)) {
192 assert(I.getOperand(1).getImm() >= 0 &&(static_cast <bool> (I.getOperand(1).getImm() >= 0 &&
"Frame size must not be negative") ? void (0) : __assert_fail
("I.getOperand(1).getImm() >= 0 && \"Frame size must not be negative\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 193, __extension__ __PRETTY_FUNCTION__))
193 "Frame size must not be negative")(static_cast <bool> (I.getOperand(1).getImm() >= 0 &&
"Frame size must not be negative") ? void (0) : __assert_fail
("I.getOperand(1).getImm() >= 0 && \"Frame size must not be negative\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 193, __extension__ __PRETTY_FUNCTION__))
;
194 return getFrameSize(I) + I.getOperand(1).getImm();
195 }
196 return getFrameSize(I);
197 }
198
199 unsigned getCatchReturnOpcode() const { return CatchRetOpcode; }
200 unsigned getReturnOpcode() const { return ReturnOpcode; }
201
202 /// Returns the actual stack pointer adjustment made by an instruction
203 /// as part of a call sequence. By default, only call frame setup/destroy
204 /// instructions adjust the stack, but targets may want to override this
205 /// to enable more fine-grained adjustment, or adjust by a different value.
206 virtual int getSPAdjust(const MachineInstr &MI) const;
207
208 /// Return true if the instruction is a "coalescable" extension instruction.
209 /// That is, it's like a copy where it's legal for the source to overlap the
210 /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's
211 /// expected the pre-extension value is available as a subreg of the result
212 /// register. This also returns the sub-register index in SubIdx.
213 virtual bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
214 unsigned &DstReg, unsigned &SubIdx) const {
215 return false;
216 }
217
218 /// If the specified machine instruction is a direct
219 /// load from a stack slot, return the virtual or physical register number of
220 /// the destination along with the FrameIndex of the loaded stack slot. If
221 /// not, return 0. This predicate must return 0 if the instruction has
222 /// any side effects other than loading from the stack slot.
223 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI,
224 int &FrameIndex) const {
225 return 0;
8
Returning without writing to 'FrameIndex'
226 }
227
228 /// Check for post-frame ptr elimination stack locations as well.
229 /// This uses a heuristic so it isn't reliable for correctness.
230 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
231 int &FrameIndex) const {
232 return 0;
233 }
234
235 /// If the specified machine instruction has a load from a stack slot,
236 /// return true along with the FrameIndex of the loaded stack slot and the
237 /// machine mem operand containing the reference.
238 /// If not, return false. Unlike isLoadFromStackSlot, this returns true for
239 /// any instructions that loads from the stack. This is just a hint, as some
240 /// cases may be missed.
241 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
242 const MachineMemOperand *&MMO,
243 int &FrameIndex) const;
244
245 /// If the specified machine instruction is a direct
246 /// store to a stack slot, return the virtual or physical register number of
247 /// the source reg along with the FrameIndex of the loaded stack slot. If
248 /// not, return 0. This predicate must return 0 if the instruction has
249 /// any side effects other than storing to the stack slot.
250 virtual unsigned isStoreToStackSlot(const MachineInstr &MI,
251 int &FrameIndex) const {
252 return 0;
253 }
254
255 /// Check for post-frame ptr elimination stack locations as well.
256 /// This uses a heuristic, so it isn't reliable for correctness.
257 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
258 int &FrameIndex) const {
259 return 0;
260 }
261
262 /// If the specified machine instruction has a store to a stack slot,
263 /// return true along with the FrameIndex of the loaded stack slot and the
264 /// machine mem operand containing the reference.
265 /// If not, return false. Unlike isStoreToStackSlot,
266 /// this returns true for any instructions that stores to the
267 /// stack. This is just a hint, as some cases may be missed.
268 virtual bool hasStoreToStackSlot(const MachineInstr &MI,
269 const MachineMemOperand *&MMO,
270 int &FrameIndex) const;
271
272 /// Return true if the specified machine instruction
273 /// is a copy of one stack slot to another and has no other effect.
274 /// Provide the identity of the two frame indices.
275 virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
276 int &SrcFrameIndex) const {
277 return false;
278 }
279
280 /// Compute the size in bytes and offset within a stack slot of a spilled
281 /// register or subregister.
282 ///
283 /// \param [out] Size in bytes of the spilled value.
284 /// \param [out] Offset in bytes within the stack slot.
285 /// \returns true if both Size and Offset are successfully computed.
286 ///
287 /// Not all subregisters have computable spill slots. For example,
288 /// subregisters registers may not be byte-sized, and a pair of discontiguous
289 /// subregisters has no single offset.
290 ///
291 /// Targets with nontrivial bigendian implementations may need to override
292 /// this, particularly to support spilled vector registers.
293 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
294 unsigned &Size, unsigned &Offset,
295 const MachineFunction &MF) const;
296
297 /// Returns the size in bytes of the specified MachineInstr, or ~0U
298 /// when this function is not implemented by a target.
299 virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const {
300 return ~0U;
301 }
302
303 /// Return true if the instruction is as cheap as a move instruction.
304 ///
305 /// Targets for different archs need to override this, and different
306 /// micro-architectures can also be finely tuned inside.
307 virtual bool isAsCheapAsAMove(const MachineInstr &MI) const {
308 return MI.isAsCheapAsAMove();
309 }
310
311 /// Return true if the instruction should be sunk by MachineSink.
312 ///
313 /// MachineSink determines on its own whether the instruction is safe to sink;
314 /// this gives the target a hook to override the default behavior with regards
315 /// to which instructions should be sunk.
316 virtual bool shouldSink(const MachineInstr &MI) const { return true; }
317
318 /// Re-issue the specified 'original' instruction at the
319 /// specific location targeting a new destination register.
320 /// The register in Orig->getOperand(0).getReg() will be substituted by
321 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
322 /// SubIdx.
323 virtual void reMaterialize(MachineBasicBlock &MBB,
324 MachineBasicBlock::iterator MI, unsigned DestReg,
325 unsigned SubIdx, const MachineInstr &Orig,
326 const TargetRegisterInfo &TRI) const;
327
328 /// \brief Clones instruction or the whole instruction bundle \p Orig and
329 /// insert into \p MBB before \p InsertBefore. The target may update operands
330 /// that are required to be unique.
331 ///
332 /// \p Orig must not return true for MachineInstr::isNotDuplicable().
333 virtual MachineInstr &duplicate(MachineBasicBlock &MBB,
334 MachineBasicBlock::iterator InsertBefore,
335 const MachineInstr &Orig) const;
336
337 /// This method must be implemented by targets that
338 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
339 /// may be able to convert a two-address instruction into one or more true
340 /// three-address instructions on demand. This allows the X86 target (for
341 /// example) to convert ADD and SHL instructions into LEA instructions if they
342 /// would require register copies due to two-addressness.
343 ///
344 /// This method returns a null pointer if the transformation cannot be
345 /// performed, otherwise it returns the last new instruction.
346 ///
347 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
348 MachineInstr &MI,
349 LiveVariables *LV) const {
350 return nullptr;
351 }
352
353 // This constant can be used as an input value of operand index passed to
354 // the method findCommutedOpIndices() to tell the method that the
355 // corresponding operand index is not pre-defined and that the method
356 // can pick any commutable operand.
357 static const unsigned CommuteAnyOperandIndex = ~0U;
358
359 /// This method commutes the operands of the given machine instruction MI.
360 ///
361 /// The operands to be commuted are specified by their indices OpIdx1 and
362 /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value
363 /// 'CommuteAnyOperandIndex', which means that the method is free to choose
364 /// any arbitrarily chosen commutable operand. If both arguments are set to
365 /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable
366 /// operands; then commutes them if such operands could be found.
367 ///
368 /// If NewMI is false, MI is modified in place and returned; otherwise, a
369 /// new machine instruction is created and returned.
370 ///
371 /// Do not call this method for a non-commutable instruction or
372 /// for non-commuable operands.
373 /// Even though the instruction is commutable, the method may still
374 /// fail to commute the operands, null pointer is returned in such cases.
375 MachineInstr *
376 commuteInstruction(MachineInstr &MI, bool NewMI = false,
377 unsigned OpIdx1 = CommuteAnyOperandIndex,
378 unsigned OpIdx2 = CommuteAnyOperandIndex) const;
379
380 /// Returns true iff the routine could find two commutable operands in the
381 /// given machine instruction.
382 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments.
383 /// If any of the INPUT values is set to the special value
384 /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable
385 /// operand, then returns its index in the corresponding argument.
386 /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method
387 /// looks for 2 commutable operands.
388 /// If INPUT values refer to some operands of MI, then the method simply
389 /// returns true if the corresponding operands are commutable and returns
390 /// false otherwise.
391 ///
392 /// For example, calling this method this way:
393 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
394 /// findCommutedOpIndices(MI, Op1, Op2);
395 /// can be interpreted as a query asking to find an operand that would be
396 /// commutable with the operand#1.
397 virtual bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
398 unsigned &SrcOpIdx2) const;
399
400 /// A pair composed of a register and a sub-register index.
401 /// Used to give some type checking when modeling Reg:SubReg.
402 struct RegSubRegPair {
403 unsigned Reg;
404 unsigned SubReg;
405
406 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
407 : Reg(Reg), SubReg(SubReg) {}
408 };
409
410 /// A pair composed of a pair of a register and a sub-register index,
411 /// and another sub-register index.
412 /// Used to give some type checking when modeling Reg:SubReg1, SubReg2.
413 struct RegSubRegPairAndIdx : RegSubRegPair {
414 unsigned SubIdx;
415
416 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
417 unsigned SubIdx = 0)
418 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
419 };
420
421 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
422 /// and \p DefIdx.
423 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
424 /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef
425 /// flag are not added to this list.
426 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
427 /// two elements:
428 /// - %1:sub1, sub0
429 /// - %2<:0>, sub1
430 ///
431 /// \returns true if it is possible to build such an input sequence
432 /// with the pair \p MI, \p DefIdx. False otherwise.
433 ///
434 /// \pre MI.isRegSequence() or MI.isRegSequenceLike().
435 ///
436 /// \note The generic implementation does not provide any support for
437 /// MI.isRegSequenceLike(). In other words, one has to override
438 /// getRegSequenceLikeInputs for target specific instructions.
439 bool
440 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
441 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
442
443 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
444 /// and \p DefIdx.
445 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
446 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
447 /// - %1:sub1, sub0
448 ///
449 /// \returns true if it is possible to build such an input sequence
450 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
451 /// False otherwise.
452 ///
453 /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike().
454 ///
455 /// \note The generic implementation does not provide any support for
456 /// MI.isExtractSubregLike(). In other words, one has to override
457 /// getExtractSubregLikeInputs for target specific instructions.
458 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
459 RegSubRegPairAndIdx &InputReg) const;
460
461 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
462 /// and \p DefIdx.
463 /// \p [out] BaseReg and \p [out] InsertedReg contain
464 /// the equivalent inputs of INSERT_SUBREG.
465 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
466 /// - BaseReg: %0:sub0
467 /// - InsertedReg: %1:sub1, sub3
468 ///
469 /// \returns true if it is possible to build such an input sequence
470 /// with the pair \p MI, \p DefIdx and the operand has no undef flag set.
471 /// False otherwise.
472 ///
473 /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike().
474 ///
475 /// \note The generic implementation does not provide any support for
476 /// MI.isInsertSubregLike(). In other words, one has to override
477 /// getInsertSubregLikeInputs for target specific instructions.
478 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
479 RegSubRegPair &BaseReg,
480 RegSubRegPairAndIdx &InsertedReg) const;
481
482 /// Return true if two machine instructions would produce identical values.
483 /// By default, this is only true when the two instructions
484 /// are deemed identical except for defs. If this function is called when the
485 /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for
486 /// aggressive checks.
487 virtual bool produceSameValue(const MachineInstr &MI0,
488 const MachineInstr &MI1,
489 const MachineRegisterInfo *MRI = nullptr) const;
490
491 /// \returns true if a branch from an instruction with opcode \p BranchOpc
492 /// bytes is capable of jumping to a position \p BrOffset bytes away.
493 virtual bool isBranchOffsetInRange(unsigned BranchOpc,
494 int64_t BrOffset) const {
495 llvm_unreachable("target did not implement")::llvm::llvm_unreachable_internal("target did not implement",
"/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 495)
;
496 }
497
498 /// \returns The block that branch instruction \p MI jumps to.
499 virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const {
500 llvm_unreachable("target did not implement")::llvm::llvm_unreachable_internal("target did not implement",
"/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 500)
;
501 }
502
503 /// Insert an unconditional indirect branch at the end of \p MBB to \p
504 /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to
505 /// the offset of the position to insert the new branch.
506 ///
507 /// \returns The number of bytes added to the block.
508 virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB,
509 MachineBasicBlock &NewDestBB,
510 const DebugLoc &DL,
511 int64_t BrOffset = 0,
512 RegScavenger *RS = nullptr) const {
513 llvm_unreachable("target did not implement")::llvm::llvm_unreachable_internal("target did not implement",
"/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 513)
;
514 }
515
516 /// Analyze the branching code at the end of MBB, returning
517 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
518 /// implemented for a target). Upon success, this returns false and returns
519 /// with the following information in various cases:
520 ///
521 /// 1. If this block ends with no branches (it just falls through to its succ)
522 /// just return false, leaving TBB/FBB null.
523 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
524 /// the destination block.
525 /// 3. If this block ends with a conditional branch and it falls through to a
526 /// successor block, it sets TBB to be the branch destination block and a
527 /// list of operands that evaluate the condition. These operands can be
528 /// passed to other TargetInstrInfo methods to create new branches.
529 /// 4. If this block ends with a conditional branch followed by an
530 /// unconditional branch, it returns the 'true' destination in TBB, the
531 /// 'false' destination in FBB, and a list of operands that evaluate the
532 /// condition. These operands can be passed to other TargetInstrInfo
533 /// methods to create new branches.
534 ///
535 /// Note that removeBranch and insertBranch must be implemented to support
536 /// cases where this method returns success.
537 ///
538 /// If AllowModify is true, then this routine is allowed to modify the basic
539 /// block (e.g. delete instructions after the unconditional branch).
540 ///
541 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
542 /// before calling this function.
543 virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
544 MachineBasicBlock *&FBB,
545 SmallVectorImpl<MachineOperand> &Cond,
546 bool AllowModify = false) const {
547 return true;
548 }
549
550 /// Represents a predicate at the MachineFunction level. The control flow a
551 /// MachineBranchPredicate represents is:
552 ///
553 /// Reg = LHS `Predicate` RHS == ConditionDef
554 /// if Reg then goto TrueDest else goto FalseDest
555 ///
556 struct MachineBranchPredicate {
557 enum ComparePredicate {
558 PRED_EQ, // True if two values are equal
559 PRED_NE, // True if two values are not equal
560 PRED_INVALID // Sentinel value
561 };
562
563 ComparePredicate Predicate = PRED_INVALID;
564 MachineOperand LHS = MachineOperand::CreateImm(0);
565 MachineOperand RHS = MachineOperand::CreateImm(0);
566 MachineBasicBlock *TrueDest = nullptr;
567 MachineBasicBlock *FalseDest = nullptr;
568 MachineInstr *ConditionDef = nullptr;
569
570 /// SingleUseCondition is true if ConditionDef is dead except for the
571 /// branch(es) at the end of the basic block.
572 ///
573 bool SingleUseCondition = false;
574
575 explicit MachineBranchPredicate() = default;
576 };
577
578 /// Analyze the branching code at the end of MBB and parse it into the
579 /// MachineBranchPredicate structure if possible. Returns false on success
580 /// and true on failure.
581 ///
582 /// If AllowModify is true, then this routine is allowed to modify the basic
583 /// block (e.g. delete instructions after the unconditional branch).
584 ///
585 virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB,
586 MachineBranchPredicate &MBP,
587 bool AllowModify = false) const {
588 return true;
589 }
590
591 /// Remove the branching code at the end of the specific MBB.
592 /// This is only invoked in cases where AnalyzeBranch returns success. It
593 /// returns the number of instructions that were removed.
594 /// If \p BytesRemoved is non-null, report the change in code size from the
595 /// removed instructions.
596 virtual unsigned removeBranch(MachineBasicBlock &MBB,
597 int *BytesRemoved = nullptr) const {
598 llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::removeBranch!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 598)
;
599 }
600
601 /// Insert branch code into the end of the specified MachineBasicBlock. The
602 /// operands to this method are the same as those returned by AnalyzeBranch.
603 /// This is only invoked in cases where AnalyzeBranch returns success. It
604 /// returns the number of instructions inserted. If \p BytesAdded is non-null,
605 /// report the change in code size from the added instructions.
606 ///
607 /// It is also invoked by tail merging to add unconditional branches in
608 /// cases where AnalyzeBranch doesn't apply because there was no original
609 /// branch to analyze. At least this much must be implemented, else tail
610 /// merging needs to be disabled.
611 ///
612 /// The CFG information in MBB.Predecessors and MBB.Successors must be valid
613 /// before calling this function.
614 virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
615 MachineBasicBlock *FBB,
616 ArrayRef<MachineOperand> Cond,
617 const DebugLoc &DL,
618 int *BytesAdded = nullptr) const {
619 llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertBranch!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 619)
;
620 }
621
622 unsigned insertUnconditionalBranch(MachineBasicBlock &MBB,
623 MachineBasicBlock *DestBB,
624 const DebugLoc &DL,
625 int *BytesAdded = nullptr) const {
626 return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL,
627 BytesAdded);
628 }
629
630 /// Analyze the loop code, return true if it cannot be understoo. Upon
631 /// success, this function returns false and returns information about the
632 /// induction variable and compare instruction used at the end.
633 virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
634 MachineInstr *&CmpInst) const {
635 return true;
636 }
637
638 /// Generate code to reduce the loop iteration by one and check if the loop
639 /// is finished. Return the value/register of the new loop count. We need
640 /// this function when peeling off one or more iterations of a loop. This
641 /// function assumes the nth iteration is peeled first.
642 virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, MachineInstr *IndVar,
643 MachineInstr &Cmp,
644 SmallVectorImpl<MachineOperand> &Cond,
645 SmallVectorImpl<MachineInstr *> &PrevInsts,
646 unsigned Iter, unsigned MaxIter) const {
647 llvm_unreachable("Target didn't implement ReduceLoopCount")::llvm::llvm_unreachable_internal("Target didn't implement ReduceLoopCount"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 647)
;
648 }
649
650 /// Delete the instruction OldInst and everything after it, replacing it with
651 /// an unconditional branch to NewDest. This is used by the tail merging pass.
652 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
653 MachineBasicBlock *NewDest) const;
654
655 /// Return true if it's legal to split the given basic
656 /// block at the specified instruction (i.e. instruction would be the start
657 /// of a new basic block).
658 virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
659 MachineBasicBlock::iterator MBBI) const {
660 return true;
661 }
662
663 /// Return true if it's profitable to predicate
664 /// instructions with accumulated instruction latency of "NumCycles"
665 /// of the specified basic block, where the probability of the instructions
666 /// being executed is given by Probability, and Confidence is a measure
667 /// of our confidence that it will be properly predicted.
668 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
669 unsigned ExtraPredCycles,
670 BranchProbability Probability) const {
671 return false;
672 }
673
674 /// Second variant of isProfitableToIfCvt. This one
675 /// checks for the case where two basic blocks from true and false path
676 /// of a if-then-else (diamond) are predicated on mutally exclusive
677 /// predicates, where the probability of the true path being taken is given
678 /// by Probability, and Confidence is a measure of our confidence that it
679 /// will be properly predicted.
680 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles,
681 unsigned ExtraTCycles,
682 MachineBasicBlock &FMBB, unsigned NumFCycles,
683 unsigned ExtraFCycles,
684 BranchProbability Probability) const {
685 return false;
686 }
687
688 /// Return true if it's profitable for if-converter to duplicate instructions
689 /// of specified accumulated instruction latencies in the specified MBB to
690 /// enable if-conversion.
691 /// The probability of the instructions being executed is given by
692 /// Probability, and Confidence is a measure of our confidence that it
693 /// will be properly predicted.
694 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
695 unsigned NumCycles,
696 BranchProbability Probability) const {
697 return false;
698 }
699
700 /// Return true if it's profitable to unpredicate
701 /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually
702 /// exclusive predicates.
703 /// e.g.
704 /// subeq r0, r1, #1
705 /// addne r0, r1, #1
706 /// =>
707 /// sub r0, r1, #1
708 /// addne r0, r1, #1
709 ///
710 /// This may be profitable is conditional instructions are always executed.
711 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
712 MachineBasicBlock &FMBB) const {
713 return false;
714 }
715
716 /// Return true if it is possible to insert a select
717 /// instruction that chooses between TrueReg and FalseReg based on the
718 /// condition code in Cond.
719 ///
720 /// When successful, also return the latency in cycles from TrueReg,
721 /// FalseReg, and Cond to the destination register. In most cases, a select
722 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
723 ///
724 /// Some x86 implementations have 2-cycle cmov instructions.
725 ///
726 /// @param MBB Block where select instruction would be inserted.
727 /// @param Cond Condition returned by AnalyzeBranch.
728 /// @param TrueReg Virtual register to select when Cond is true.
729 /// @param FalseReg Virtual register to select when Cond is false.
730 /// @param CondCycles Latency from Cond+Branch to select output.
731 /// @param TrueCycles Latency from TrueReg to select output.
732 /// @param FalseCycles Latency from FalseReg to select output.
733 virtual bool canInsertSelect(const MachineBasicBlock &MBB,
734 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
735 unsigned FalseReg, int &CondCycles,
736 int &TrueCycles, int &FalseCycles) const {
737 return false;
738 }
739
740 /// Insert a select instruction into MBB before I that will copy TrueReg to
741 /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
742 ///
743 /// This function can only be called after canInsertSelect() returned true.
744 /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
745 /// that the same flags or registers required by Cond are available at the
746 /// insertion point.
747 ///
748 /// @param MBB Block where select instruction should be inserted.
749 /// @param I Insertion point.
750 /// @param DL Source location for debugging.
751 /// @param DstReg Virtual register to be defined by select instruction.
752 /// @param Cond Condition as computed by AnalyzeBranch.
753 /// @param TrueReg Virtual register to copy when Cond is true.
754 /// @param FalseReg Virtual register to copy when Cons is false.
755 virtual void insertSelect(MachineBasicBlock &MBB,
756 MachineBasicBlock::iterator I, const DebugLoc &DL,
757 unsigned DstReg, ArrayRef<MachineOperand> Cond,
758 unsigned TrueReg, unsigned FalseReg) const {
759 llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertSelect!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 759)
;
760 }
761
762 /// Analyze the given select instruction, returning true if
763 /// it cannot be understood. It is assumed that MI->isSelect() is true.
764 ///
765 /// When successful, return the controlling condition and the operands that
766 /// determine the true and false result values.
767 ///
768 /// Result = SELECT Cond, TrueOp, FalseOp
769 ///
770 /// Some targets can optimize select instructions, for example by predicating
771 /// the instruction defining one of the operands. Such targets should set
772 /// Optimizable.
773 ///
774 /// @param MI Select instruction to analyze.
775 /// @param Cond Condition controlling the select.
776 /// @param TrueOp Operand number of the value selected when Cond is true.
777 /// @param FalseOp Operand number of the value selected when Cond is false.
778 /// @param Optimizable Returned as true if MI is optimizable.
779 /// @returns False on success.
780 virtual bool analyzeSelect(const MachineInstr &MI,
781 SmallVectorImpl<MachineOperand> &Cond,
782 unsigned &TrueOp, unsigned &FalseOp,
783 bool &Optimizable) const {
784 assert(MI.getDesc().isSelect() && "MI must be a select instruction")(static_cast <bool> (MI.getDesc().isSelect() &&
"MI must be a select instruction") ? void (0) : __assert_fail
("MI.getDesc().isSelect() && \"MI must be a select instruction\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 784, __extension__ __PRETTY_FUNCTION__))
;
785 return true;
786 }
787
788 /// Given a select instruction that was understood by
789 /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by
790 /// merging it with one of its operands. Returns NULL on failure.
791 ///
792 /// When successful, returns the new select instruction. The client is
793 /// responsible for deleting MI.
794 ///
795 /// If both sides of the select can be optimized, PreferFalse is used to pick
796 /// a side.
797 ///
798 /// @param MI Optimizable select instruction.
799 /// @param NewMIs Set that record all MIs in the basic block up to \p
800 /// MI. Has to be updated with any newly created MI or deleted ones.
801 /// @param PreferFalse Try to optimize FalseOp instead of TrueOp.
802 /// @returns Optimized instruction or NULL.
803 virtual MachineInstr *optimizeSelect(MachineInstr &MI,
804 SmallPtrSetImpl<MachineInstr *> &NewMIs,
805 bool PreferFalse = false) const {
806 // This function must be implemented if Optimizable is ever set.
807 llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!")::llvm::llvm_unreachable_internal("Target must implement TargetInstrInfo::optimizeSelect!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 807)
;
808 }
809
810 /// Emit instructions to copy a pair of physical registers.
811 ///
812 /// This function should support copies within any legal register class as
813 /// well as any cross-class copies created during instruction selection.
814 ///
815 /// The source and destination registers may overlap, which may require a
816 /// careful implementation when multiple copy instructions are required for
817 /// large registers. See for example the ARM target.
818 virtual void copyPhysReg(MachineBasicBlock &MBB,
819 MachineBasicBlock::iterator MI, const DebugLoc &DL,
820 unsigned DestReg, unsigned SrcReg,
821 bool KillSrc) const {
822 llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::copyPhysReg!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 822)
;
823 }
824
825 /// Store the specified register of the given register class to the specified
826 /// stack frame index. The store instruction is to be added to the given
827 /// machine basic block before the specified machine instruction. If isKill
828 /// is true, the register operand is the last use and must be marked kill.
829 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
830 MachineBasicBlock::iterator MI,
831 unsigned SrcReg, bool isKill, int FrameIndex,
832 const TargetRegisterClass *RC,
833 const TargetRegisterInfo *TRI) const {
834 llvm_unreachable("Target didn't implement "::llvm::llvm_unreachable_internal("Target didn't implement " "TargetInstrInfo::storeRegToStackSlot!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 835)
835 "TargetInstrInfo::storeRegToStackSlot!")::llvm::llvm_unreachable_internal("Target didn't implement " "TargetInstrInfo::storeRegToStackSlot!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 835)
;
836 }
837
838 /// Load the specified register of the given register class from the specified
839 /// stack frame index. The load instruction is to be added to the given
840 /// machine basic block before the specified machine instruction.
841 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
842 MachineBasicBlock::iterator MI,
843 unsigned DestReg, int FrameIndex,
844 const TargetRegisterClass *RC,
845 const TargetRegisterInfo *TRI) const {
846 llvm_unreachable("Target didn't implement "::llvm::llvm_unreachable_internal("Target didn't implement " "TargetInstrInfo::loadRegFromStackSlot!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 847)
847 "TargetInstrInfo::loadRegFromStackSlot!")::llvm::llvm_unreachable_internal("Target didn't implement " "TargetInstrInfo::loadRegFromStackSlot!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 847)
;
848 }
849
850 /// This function is called for all pseudo instructions
851 /// that remain after register allocation. Many pseudo instructions are
852 /// created to help register allocation. This is the place to convert them
853 /// into real instructions. The target can edit MI in place, or it can insert
854 /// new instructions and erase MI. The function should return true if
855 /// anything was changed.
856 virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; }
857
858 /// Check whether the target can fold a load that feeds a subreg operand
859 /// (or a subreg operand that feeds a store).
860 /// For example, X86 may want to return true if it can fold
861 /// movl (%esp), %eax
862 /// subb, %al, ...
863 /// Into:
864 /// subb (%esp), ...
865 ///
866 /// Ideally, we'd like the target implementation of foldMemoryOperand() to
867 /// reject subregs - but since this behavior used to be enforced in the
868 /// target-independent code, moving this responsibility to the targets
869 /// has the potential of causing nasty silent breakage in out-of-tree targets.
870 virtual bool isSubregFoldable() const { return false; }
871
872 /// Attempt to fold a load or store of the specified stack
873 /// slot into the specified machine instruction for the specified operand(s).
874 /// If this is possible, a new instruction is returned with the specified
875 /// operand folded, otherwise NULL is returned.
876 /// The new instruction is inserted before MI, and the client is responsible
877 /// for removing the old instruction.
878 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
879 int FrameIndex,
880 LiveIntervals *LIS = nullptr) const;
881
882 /// Same as the previous version except it allows folding of any load and
883 /// store from / to any address, not just from a specific stack slot.
884 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops,
885 MachineInstr &LoadMI,
886 LiveIntervals *LIS = nullptr) const;
887
888 /// Return true when there is potentially a faster code sequence
889 /// for an instruction chain ending in \p Root. All potential patterns are
890 /// returned in the \p Pattern vector. Pattern should be sorted in priority
891 /// order since the pattern evaluator stops checking as soon as it finds a
892 /// faster sequence.
893 /// \param Root - Instruction that could be combined with one of its operands
894 /// \param Patterns - Vector of possible combination patterns
895 virtual bool getMachineCombinerPatterns(
896 MachineInstr &Root,
897 SmallVectorImpl<MachineCombinerPattern> &Patterns) const;
898
899 /// Return true when a code sequence can improve throughput. It
900 /// should be called only for instructions in loops.
901 /// \param Pattern - combiner pattern
902 virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const;
903
904 /// Return true if the input \P Inst is part of a chain of dependent ops
905 /// that are suitable for reassociation, otherwise return false.
906 /// If the instruction's operands must be commuted to have a previous
907 /// instruction of the same type define the first source operand, \P Commuted
908 /// will be set to true.
909 bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
910
911 /// Return true when \P Inst is both associative and commutative.
912 virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
913 return false;
914 }
915
916 /// Return true when \P Inst has reassociable operands in the same \P MBB.
917 virtual bool hasReassociableOperands(const MachineInstr &Inst,
918 const MachineBasicBlock *MBB) const;
919
920 /// Return true when \P Inst has reassociable sibling.
921 bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const;
922
923 /// When getMachineCombinerPatterns() finds patterns, this function generates
924 /// the instructions that could replace the original code sequence. The client
925 /// has to decide whether the actual replacement is beneficial or not.
926 /// \param Root - Instruction that could be combined with one of its operands
927 /// \param Pattern - Combination pattern for Root
928 /// \param InsInstrs - Vector of new instructions that implement P
929 /// \param DelInstrs - Old instructions, including Root, that could be
930 /// replaced by InsInstr
931 /// \param InstrIdxForVirtReg - map of virtual register to instruction in
932 /// InsInstr that defines it
933 virtual void genAlternativeCodeSequence(
934 MachineInstr &Root, MachineCombinerPattern Pattern,
935 SmallVectorImpl<MachineInstr *> &InsInstrs,
936 SmallVectorImpl<MachineInstr *> &DelInstrs,
937 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
938
939 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
940 /// reduce critical path length.
941 void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
942 MachineCombinerPattern Pattern,
943 SmallVectorImpl<MachineInstr *> &InsInstrs,
944 SmallVectorImpl<MachineInstr *> &DelInstrs,
945 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
946
947 /// This is an architecture-specific helper function of reassociateOps.
948 /// Set special operand attributes for new instructions after reassociation.
949 virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
950 MachineInstr &NewMI1,
951 MachineInstr &NewMI2) const {}
952
953 /// Return true when a target supports MachineCombiner.
954 virtual bool useMachineCombiner() const { return false; }
955
956 /// Return true if the given SDNode can be copied during scheduling
957 /// even if it has glue.
958 virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; }
959
960 /// Remember what registers the specified instruction uses and modifies.
961 virtual void trackRegDefsUses(const MachineInstr &MI, BitVector &ModifiedRegs,
962 BitVector &UsedRegs,
963 const TargetRegisterInfo *TRI) const;
964
965protected:
966 /// Target-dependent implementation for foldMemoryOperand.
967 /// Target-independent code in foldMemoryOperand will
968 /// take care of adding a MachineMemOperand to the newly created instruction.
969 /// The instruction and any auxiliary instructions necessary will be inserted
970 /// at InsertPt.
971 virtual MachineInstr *
972 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
973 ArrayRef<unsigned> Ops,
974 MachineBasicBlock::iterator InsertPt, int FrameIndex,
975 LiveIntervals *LIS = nullptr) const {
976 return nullptr;
977 }
978
979 /// Target-dependent implementation for foldMemoryOperand.
980 /// Target-independent code in foldMemoryOperand will
981 /// take care of adding a MachineMemOperand to the newly created instruction.
982 /// The instruction and any auxiliary instructions necessary will be inserted
983 /// at InsertPt.
984 virtual MachineInstr *foldMemoryOperandImpl(
985 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
986 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
987 LiveIntervals *LIS = nullptr) const {
988 return nullptr;
989 }
990
991 /// \brief Target-dependent implementation of getRegSequenceInputs.
992 ///
993 /// \returns true if it is possible to build the equivalent
994 /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise.
995 ///
996 /// \pre MI.isRegSequenceLike().
997 ///
998 /// \see TargetInstrInfo::getRegSequenceInputs.
999 virtual bool getRegSequenceLikeInputs(
1000 const MachineInstr &MI, unsigned DefIdx,
1001 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
1002 return false;
1003 }
1004
1005 /// \brief Target-dependent implementation of getExtractSubregInputs.
1006 ///
1007 /// \returns true if it is possible to build the equivalent
1008 /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1009 ///
1010 /// \pre MI.isExtractSubregLike().
1011 ///
1012 /// \see TargetInstrInfo::getExtractSubregInputs.
1013 virtual bool getExtractSubregLikeInputs(const MachineInstr &MI,
1014 unsigned DefIdx,
1015 RegSubRegPairAndIdx &InputReg) const {
1016 return false;
1017 }
1018
1019 /// \brief Target-dependent implementation of getInsertSubregInputs.
1020 ///
1021 /// \returns true if it is possible to build the equivalent
1022 /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise.
1023 ///
1024 /// \pre MI.isInsertSubregLike().
1025 ///
1026 /// \see TargetInstrInfo::getInsertSubregInputs.
1027 virtual bool
1028 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
1029 RegSubRegPair &BaseReg,
1030 RegSubRegPairAndIdx &InsertedReg) const {
1031 return false;
1032 }
1033
1034public:
1035 /// getAddressSpaceForPseudoSourceKind - Given the kind of memory
1036 /// (e.g. stack) the target returns the corresponding address space.
1037 virtual unsigned
1038 getAddressSpaceForPseudoSourceKind(PseudoSourceValue::PSVKind Kind) const {
1039 return 0;
1040 }
1041
1042 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
1043 /// a store or a load and a store into two or more instruction. If this is
1044 /// possible, returns true as well as the new instructions by reference.
1045 virtual bool
1046 unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg,
1047 bool UnfoldLoad, bool UnfoldStore,
1048 SmallVectorImpl<MachineInstr *> &NewMIs) const {
1049 return false;
1050 }
1051
1052 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
1053 SmallVectorImpl<SDNode *> &NewNodes) const {
1054 return false;
1055 }
1056
1057 /// Returns the opcode of the would be new
1058 /// instruction after load / store are unfolded from an instruction of the
1059 /// specified opcode. It returns zero if the specified unfolding is not
1060 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
1061 /// index of the operand which will hold the register holding the loaded
1062 /// value.
1063 virtual unsigned
1064 getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
1065 unsigned *LoadRegIndex = nullptr) const {
1066 return 0;
1067 }
1068
1069 /// This is used by the pre-regalloc scheduler to determine if two loads are
1070 /// loading from the same base address. It should only return true if the base
1071 /// pointers are the same and the only differences between the two addresses
1072 /// are the offset. It also returns the offsets by reference.
1073 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1074 int64_t &Offset1,
1075 int64_t &Offset2) const {
1076 return false;
1077 }
1078
1079 /// This is a used by the pre-regalloc scheduler to determine (in conjunction
1080 /// with areLoadsFromSameBasePtr) if two loads should be scheduled together.
1081 /// On some targets if two loads are loading from
1082 /// addresses in the same cache line, it's better if they are scheduled
1083 /// together. This function takes two integers that represent the load offsets
1084 /// from the common base address. It returns true if it decides it's desirable
1085 /// to schedule the two loads together. "NumLoads" is the number of loads that
1086 /// have already been scheduled after Load1.
1087 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1088 int64_t Offset1, int64_t Offset2,
1089 unsigned NumLoads) const {
1090 return false;
1091 }
1092
1093 /// Get the base register and byte offset of an instruction that reads/writes
1094 /// memory.
1095 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
1096 int64_t &Offset,
1097 const TargetRegisterInfo *TRI) const {
1098 return false;
1099 }
1100
1101 /// Return true if the instruction contains a base register and offset. If
1102 /// true, the function also sets the operand position in the instruction
1103 /// for the base register and offset.
1104 virtual bool getBaseAndOffsetPosition(const MachineInstr &MI,
1105 unsigned &BasePos,
1106 unsigned &OffsetPos) const {
1107 return false;
1108 }
1109
1110 /// If the instruction is an increment of a constant value, return the amount.
1111 virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const {
1112 return false;
1113 }
1114
1115 /// Returns true if the two given memory operations should be scheduled
1116 /// adjacent. Note that you have to add:
1117 /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
1118 /// or
1119 /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
1120 /// to TargetPassConfig::createMachineScheduler() to have an effect.
1121 virtual bool shouldClusterMemOps(MachineInstr &FirstLdSt, unsigned BaseReg1,
1122 MachineInstr &SecondLdSt, unsigned BaseReg2,
1123 unsigned NumLoads) const {
1124 llvm_unreachable("target did not implement shouldClusterMemOps()")::llvm::llvm_unreachable_internal("target did not implement shouldClusterMemOps()"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1124)
;
1125 }
1126
1127 /// Reverses the branch condition of the specified condition list,
1128 /// returning false on success and true if it cannot be reversed.
1129 virtual bool
1130 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1131 return true;
1132 }
1133
1134 /// Insert a noop into the instruction stream at the specified point.
1135 virtual void insertNoop(MachineBasicBlock &MBB,
1136 MachineBasicBlock::iterator MI) const;
1137
1138 /// Return the noop instruction to use for a noop.
1139 virtual void getNoop(MCInst &NopInst) const;
1140
1141 /// Return true for post-incremented instructions.
1142 virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
1143
1144 /// Returns true if the instruction is already predicated.
1145 virtual bool isPredicated(const MachineInstr &MI) const { return false; }
1146
1147 /// Returns true if the instruction is a
1148 /// terminator instruction that has not been predicated.
1149 virtual bool isUnpredicatedTerminator(const MachineInstr &MI) const;
1150
1151 /// Returns true if MI is an unconditional tail call.
1152 virtual bool isUnconditionalTailCall(const MachineInstr &MI) const {
1153 return false;
1154 }
1155
1156 /// Returns true if the tail call can be made conditional on BranchCond.
1157 virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
1158 const MachineInstr &TailCall) const {
1159 return false;
1160 }
1161
1162 /// Replace the conditional branch in MBB with a conditional tail call.
1163 virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB,
1164 SmallVectorImpl<MachineOperand> &Cond,
1165 const MachineInstr &TailCall) const {
1166 llvm_unreachable("Target didn't implement replaceBranchWithTailCall!")::llvm::llvm_unreachable_internal("Target didn't implement replaceBranchWithTailCall!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1166)
;
1167 }
1168
1169 /// Convert the instruction into a predicated instruction.
1170 /// It returns true if the operation was successful.
1171 virtual bool PredicateInstruction(MachineInstr &MI,
1172 ArrayRef<MachineOperand> Pred) const;
1173
1174 /// Returns true if the first specified predicate
1175 /// subsumes the second, e.g. GE subsumes GT.
1176 virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
1177 ArrayRef<MachineOperand> Pred2) const {
1178 return false;
1179 }
1180
1181 /// If the specified instruction defines any predicate
1182 /// or condition code register(s) used for predication, returns true as well
1183 /// as the definition predicate(s) by reference.
1184 virtual bool DefinesPredicate(MachineInstr &MI,
1185 std::vector<MachineOperand> &Pred) const {
1186 return false;
1187 }
1188
1189 /// Return true if the specified instruction can be predicated.
1190 /// By default, this returns true for every instruction with a
1191 /// PredicateOperand.
1192 virtual bool isPredicable(const MachineInstr &MI) const {
1193 return MI.getDesc().isPredicable();
1194 }
1195
1196 /// Return true if it's safe to move a machine
1197 /// instruction that defines the specified register class.
1198 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
1199 return true;
1200 }
1201
1202 /// Test if the given instruction should be considered a scheduling boundary.
1203 /// This primarily includes labels and terminators.
1204 virtual bool isSchedulingBoundary(const MachineInstr &MI,
1205 const MachineBasicBlock *MBB,
1206 const MachineFunction &MF) const;
1207
1208 /// Measure the specified inline asm to determine an approximation of its
1209 /// length.
1210 virtual unsigned getInlineAsmLength(const char *Str,
1211 const MCAsmInfo &MAI) const;
1212
1213 /// Allocate and return a hazard recognizer to use for this target when
1214 /// scheduling the machine instructions before register allocation.
1215 virtual ScheduleHazardRecognizer *
1216 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
1217 const ScheduleDAG *DAG) const;
1218
1219 /// Allocate and return a hazard recognizer to use for this target when
1220 /// scheduling the machine instructions before register allocation.
1221 virtual ScheduleHazardRecognizer *
1222 CreateTargetMIHazardRecognizer(const InstrItineraryData *,
1223 const ScheduleDAG *DAG) const;
1224
1225 /// Allocate and return a hazard recognizer to use for this target when
1226 /// scheduling the machine instructions after register allocation.
1227 virtual ScheduleHazardRecognizer *
1228 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *,
1229 const ScheduleDAG *DAG) const;
1230
1231 /// Allocate and return a hazard recognizer to use for by non-scheduling
1232 /// passes.
1233 virtual ScheduleHazardRecognizer *
1234 CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const {
1235 return nullptr;
1236 }
1237
1238 /// Provide a global flag for disabling the PreRA hazard recognizer that
1239 /// targets may choose to honor.
1240 bool usePreRAHazardRecognizer() const;
1241
1242 /// For a comparison instruction, return the source registers
1243 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1244 /// compares against in CmpValue. Return true if the comparison instruction
1245 /// can be analyzed.
1246 virtual bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
1247 unsigned &SrcReg2, int &Mask, int &Value) const {
1248 return false;
1249 }
1250
1251 /// See if the comparison instruction can be converted
1252 /// into something more efficient. E.g., on ARM most instructions can set the
1253 /// flags register, obviating the need for a separate CMP.
1254 virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
1255 unsigned SrcReg2, int Mask, int Value,
1256 const MachineRegisterInfo *MRI) const {
1257 return false;
1258 }
1259 virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; }
1260
1261 /// Try to remove the load by folding it to a register operand at the use.
1262 /// We fold the load instructions if and only if the
1263 /// def and use are in the same BB. We only look at one load and see
1264 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
1265 /// defined by the load we are trying to fold. DefMI returns the machine
1266 /// instruction that defines FoldAsLoadDefReg, and the function returns
1267 /// the machine instruction generated due to folding.
1268 virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI,
1269 const MachineRegisterInfo *MRI,
1270 unsigned &FoldAsLoadDefReg,
1271 MachineInstr *&DefMI) const {
1272 return nullptr;
1273 }
1274
1275 /// 'Reg' is known to be defined by a move immediate instruction,
1276 /// try to fold the immediate into the use instruction.
1277 /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true,
1278 /// then the caller may assume that DefMI has been erased from its parent
1279 /// block. The caller may assume that it will not be erased by this
1280 /// function otherwise.
1281 virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
1282 unsigned Reg, MachineRegisterInfo *MRI) const {
1283 return false;
1284 }
1285
1286 /// Return the number of u-operations the given machine
1287 /// instruction will be decoded to on the target cpu. The itinerary's
1288 /// IssueWidth is the number of microops that can be dispatched each
1289 /// cycle. An instruction with zero microops takes no dispatch resources.
1290 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1291 const MachineInstr &MI) const;
1292
1293 /// Return true for pseudo instructions that don't consume any
1294 /// machine resources in their current form. These are common cases that the
1295 /// scheduler should consider free, rather than conservatively handling them
1296 /// as instructions with no itinerary.
1297 bool isZeroCost(unsigned Opcode) const {
1298 return Opcode <= TargetOpcode::COPY;
1299 }
1300
1301 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1302 SDNode *DefNode, unsigned DefIdx,
1303 SDNode *UseNode, unsigned UseIdx) const;
1304
1305 /// Compute and return the use operand latency of a given pair of def and use.
1306 /// In most cases, the static scheduling itinerary was enough to determine the
1307 /// operand latency. But it may not be possible for instructions with variable
1308 /// number of defs / uses.
1309 ///
1310 /// This is a raw interface to the itinerary that may be directly overridden
1311 /// by a target. Use computeOperandLatency to get the best estimate of
1312 /// latency.
1313 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1314 const MachineInstr &DefMI, unsigned DefIdx,
1315 const MachineInstr &UseMI,
1316 unsigned UseIdx) const;
1317
1318 /// Compute the instruction latency of a given instruction.
1319 /// If the instruction has higher cost when predicated, it's returned via
1320 /// PredCost.
1321 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1322 const MachineInstr &MI,
1323 unsigned *PredCost = nullptr) const;
1324
1325 virtual unsigned getPredicationCost(const MachineInstr &MI) const;
1326
1327 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1328 SDNode *Node) const;
1329
1330 /// Return the default expected latency for a def based on its opcode.
1331 unsigned defaultDefLatency(const MCSchedModel &SchedModel,
1332 const MachineInstr &DefMI) const;
1333
1334 int computeDefOperandLatency(const InstrItineraryData *ItinData,
1335 const MachineInstr &DefMI) const;
1336
1337 /// Return true if this opcode has high latency to its result.
1338 virtual bool isHighLatencyDef(int opc) const { return false; }
1339
1340 /// Compute operand latency between a def of 'Reg'
1341 /// and a use in the current loop. Return true if the target considered
1342 /// it 'high'. This is used by optimization passes such as machine LICM to
1343 /// determine whether it makes sense to hoist an instruction out even in a
1344 /// high register pressure situation.
1345 virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
1346 const MachineRegisterInfo *MRI,
1347 const MachineInstr &DefMI, unsigned DefIdx,
1348 const MachineInstr &UseMI,
1349 unsigned UseIdx) const {
1350 return false;
1351 }
1352
1353 /// Compute operand latency of a def of 'Reg'. Return true
1354 /// if the target considered it 'low'.
1355 virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel,
1356 const MachineInstr &DefMI,
1357 unsigned DefIdx) const;
1358
1359 /// Perform target-specific instruction verification.
1360 virtual bool verifyInstruction(const MachineInstr &MI,
1361 StringRef &ErrInfo) const {
1362 return true;
1363 }
1364
1365 /// Return the current execution domain and bit mask of
1366 /// possible domains for instruction.
1367 ///
1368 /// Some micro-architectures have multiple execution domains, and multiple
1369 /// opcodes that perform the same operation in different domains. For
1370 /// example, the x86 architecture provides the por, orps, and orpd
1371 /// instructions that all do the same thing. There is a latency penalty if a
1372 /// register is written in one domain and read in another.
1373 ///
1374 /// This function returns a pair (domain, mask) containing the execution
1375 /// domain of MI, and a bit mask of possible domains. The setExecutionDomain
1376 /// function can be used to change the opcode to one of the domains in the
1377 /// bit mask. Instructions whose execution domain can't be changed should
1378 /// return a 0 mask.
1379 ///
1380 /// The execution domain numbers don't have any special meaning except domain
1381 /// 0 is used for instructions that are not associated with any interesting
1382 /// execution domain.
1383 ///
1384 virtual std::pair<uint16_t, uint16_t>
1385 getExecutionDomain(const MachineInstr &MI) const {
1386 return std::make_pair(0, 0);
1387 }
1388
1389 /// Change the opcode of MI to execute in Domain.
1390 ///
1391 /// The bit (1 << Domain) must be set in the mask returned from
1392 /// getExecutionDomain(MI).
1393 virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {}
1394
1395 /// Returns the preferred minimum clearance
1396 /// before an instruction with an unwanted partial register update.
1397 ///
1398 /// Some instructions only write part of a register, and implicitly need to
1399 /// read the other parts of the register. This may cause unwanted stalls
1400 /// preventing otherwise unrelated instructions from executing in parallel in
1401 /// an out-of-order CPU.
1402 ///
1403 /// For example, the x86 instruction cvtsi2ss writes its result to bits
1404 /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so
1405 /// the instruction needs to wait for the old value of the register to become
1406 /// available:
1407 ///
1408 /// addps %xmm1, %xmm0
1409 /// movaps %xmm0, (%rax)
1410 /// cvtsi2ss %rbx, %xmm0
1411 ///
1412 /// In the code above, the cvtsi2ss instruction needs to wait for the addps
1413 /// instruction before it can issue, even though the high bits of %xmm0
1414 /// probably aren't needed.
1415 ///
1416 /// This hook returns the preferred clearance before MI, measured in
1417 /// instructions. Other defs of MI's operand OpNum are avoided in the last N
1418 /// instructions before MI. It should only return a positive value for
1419 /// unwanted dependencies. If the old bits of the defined register have
1420 /// useful values, or if MI is determined to otherwise read the dependency,
1421 /// the hook should return 0.
1422 ///
1423 /// The unwanted dependency may be handled by:
1424 ///
1425 /// 1. Allocating the same register for an MI def and use. That makes the
1426 /// unwanted dependency identical to a required dependency.
1427 ///
1428 /// 2. Allocating a register for the def that has no defs in the previous N
1429 /// instructions.
1430 ///
1431 /// 3. Calling breakPartialRegDependency() with the same arguments. This
1432 /// allows the target to insert a dependency breaking instruction.
1433 ///
1434 virtual unsigned
1435 getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
1436 const TargetRegisterInfo *TRI) const {
1437 // The default implementation returns 0 for no partial register dependency.
1438 return 0;
1439 }
1440
1441 /// \brief Return the minimum clearance before an instruction that reads an
1442 /// unused register.
1443 ///
1444 /// For example, AVX instructions may copy part of a register operand into
1445 /// the unused high bits of the destination register.
1446 ///
1447 /// vcvtsi2sdq %rax, undef %xmm0, %xmm14
1448 ///
1449 /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a
1450 /// false dependence on any previous write to %xmm0.
1451 ///
1452 /// This hook works similarly to getPartialRegUpdateClearance, except that it
1453 /// does not take an operand index. Instead sets \p OpNum to the index of the
1454 /// unused register.
1455 virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
1456 const TargetRegisterInfo *TRI) const {
1457 // The default implementation returns 0 for no undef register dependency.
1458 return 0;
1459 }
1460
1461 /// Insert a dependency-breaking instruction
1462 /// before MI to eliminate an unwanted dependency on OpNum.
1463 ///
1464 /// If it wasn't possible to avoid a def in the last N instructions before MI
1465 /// (see getPartialRegUpdateClearance), this hook will be called to break the
1466 /// unwanted dependency.
1467 ///
1468 /// On x86, an xorps instruction can be used as a dependency breaker:
1469 ///
1470 /// addps %xmm1, %xmm0
1471 /// movaps %xmm0, (%rax)
1472 /// xorps %xmm0, %xmm0
1473 /// cvtsi2ss %rbx, %xmm0
1474 ///
1475 /// An <imp-kill> operand should be added to MI if an instruction was
1476 /// inserted. This ties the instructions together in the post-ra scheduler.
1477 ///
1478 virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
1479 const TargetRegisterInfo *TRI) const {}
1480
1481 /// Create machine specific model for scheduling.
1482 virtual DFAPacketizer *
1483 CreateTargetScheduleState(const TargetSubtargetInfo &) const {
1484 return nullptr;
1485 }
1486
1487 /// Sometimes, it is possible for the target
1488 /// to tell, even without aliasing information, that two MIs access different
1489 /// memory addresses. This function returns true if two MIs access different
1490 /// memory addresses and false otherwise.
1491 ///
1492 /// Assumes any physical registers used to compute addresses have the same
1493 /// value for both instructions. (This is the most useful assumption for
1494 /// post-RA scheduling.)
1495 ///
1496 /// See also MachineInstr::mayAlias, which is implemented on top of this
1497 /// function.
1498 virtual bool
1499 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1500 AliasAnalysis *AA = nullptr) const {
1501 assert((MIa.mayLoad() || MIa.mayStore()) &&(static_cast <bool> ((MIa.mayLoad() || MIa.mayStore()) &&
"MIa must load from or modify a memory location") ? void (0)
: __assert_fail ("(MIa.mayLoad() || MIa.mayStore()) && \"MIa must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1502, __extension__ __PRETTY_FUNCTION__))
1502 "MIa must load from or modify a memory location")(static_cast <bool> ((MIa.mayLoad() || MIa.mayStore()) &&
"MIa must load from or modify a memory location") ? void (0)
: __assert_fail ("(MIa.mayLoad() || MIa.mayStore()) && \"MIa must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1502, __extension__ __PRETTY_FUNCTION__))
;
1503 assert((MIb.mayLoad() || MIb.mayStore()) &&(static_cast <bool> ((MIb.mayLoad() || MIb.mayStore()) &&
"MIb must load from or modify a memory location") ? void (0)
: __assert_fail ("(MIb.mayLoad() || MIb.mayStore()) && \"MIb must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1504, __extension__ __PRETTY_FUNCTION__))
1504 "MIb must load from or modify a memory location")(static_cast <bool> ((MIb.mayLoad() || MIb.mayStore()) &&
"MIb must load from or modify a memory location") ? void (0)
: __assert_fail ("(MIb.mayLoad() || MIb.mayStore()) && \"MIb must load from or modify a memory location\""
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1504, __extension__ __PRETTY_FUNCTION__))
;
1505 return false;
1506 }
1507
1508 /// \brief Return the value to use for the MachineCSE's LookAheadLimit,
1509 /// which is a heuristic used for CSE'ing phys reg defs.
1510 virtual unsigned getMachineCSELookAheadLimit() const {
1511 // The default lookahead is small to prevent unprofitable quadratic
1512 // behavior.
1513 return 5;
1514 }
1515
1516 /// Return an array that contains the ids of the target indices (used for the
1517 /// TargetIndex machine operand) and their names.
1518 ///
1519 /// MIR Serialization is able to serialize only the target indices that are
1520 /// defined by this method.
1521 virtual ArrayRef<std::pair<int, const char *>>
1522 getSerializableTargetIndices() const {
1523 return None;
1524 }
1525
1526 /// Decompose the machine operand's target flags into two values - the direct
1527 /// target flag value and any of bit flags that are applied.
1528 virtual std::pair<unsigned, unsigned>
1529 decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const {
1530 return std::make_pair(0u, 0u);
1531 }
1532
1533 /// Return an array that contains the direct target flag values and their
1534 /// names.
1535 ///
1536 /// MIR Serialization is able to serialize only the target flags that are
1537 /// defined by this method.
1538 virtual ArrayRef<std::pair<unsigned, const char *>>
1539 getSerializableDirectMachineOperandTargetFlags() const {
1540 return None;
1541 }
1542
1543 /// Return an array that contains the bitmask target flag values and their
1544 /// names.
1545 ///
1546 /// MIR Serialization is able to serialize only the target flags that are
1547 /// defined by this method.
1548 virtual ArrayRef<std::pair<unsigned, const char *>>
1549 getSerializableBitmaskMachineOperandTargetFlags() const {
1550 return None;
1551 }
1552
1553 /// Return an array that contains the MMO target flag values and their
1554 /// names.
1555 ///
1556 /// MIR Serialization is able to serialize only the MMO target flags that are
1557 /// defined by this method.
1558 virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
1559 getSerializableMachineMemOperandTargetFlags() const {
1560 return None;
1561 }
1562
1563 /// Determines whether \p Inst is a tail call instruction. Override this
1564 /// method on targets that do not properly set MCID::Return and MCID::Call on
1565 /// tail call instructions."
1566 virtual bool isTailCall(const MachineInstr &Inst) const {
1567 return Inst.isReturn() && Inst.isCall();
1568 }
1569
1570 /// True if the instruction is bound to the top of its basic block and no
1571 /// other instructions shall be inserted before it. This can be implemented
1572 /// to prevent register allocator to insert spills before such instructions.
1573 virtual bool isBasicBlockPrologue(const MachineInstr &MI) const {
1574 return false;
1575 }
1576
1577 /// Returns true if the target implements the MachineOutliner.
1578 virtual bool useMachineOutliner() const { return false; }
1579
1580 /// \brief Describes the number of instructions that it will take to call and
1581 /// construct a frame for a given outlining candidate.
1582 struct MachineOutlinerInfo {
1583 /// Number of instructions to call an outlined function for this candidate.
1584 unsigned CallOverhead;
1585
1586 /// \brief Number of instructions to construct an outlined function frame
1587 /// for this candidate.
1588 unsigned FrameOverhead;
1589
1590 /// \brief Represents the specific instructions that must be emitted to
1591 /// construct a call to this candidate.
1592 unsigned CallConstructionID;
1593
1594 /// \brief Represents the specific instructions that must be emitted to
1595 /// construct a frame for this candidate's outlined function.
1596 unsigned FrameConstructionID;
1597
1598 MachineOutlinerInfo() {}
1599 MachineOutlinerInfo(unsigned CallOverhead, unsigned FrameOverhead,
1600 unsigned CallConstructionID,
1601 unsigned FrameConstructionID)
1602 : CallOverhead(CallOverhead), FrameOverhead(FrameOverhead),
1603 CallConstructionID(CallConstructionID),
1604 FrameConstructionID(FrameConstructionID) {}
1605 };
1606
1607 /// \brief Returns a \p MachineOutlinerInfo struct containing target-specific
1608 /// information for a set of outlining candidates.
1609 virtual MachineOutlinerInfo getOutlininingCandidateInfo(
1610 std::vector<
1611 std::pair<MachineBasicBlock::iterator, MachineBasicBlock::iterator>>
1612 &RepeatedSequenceLocs) const {
1613 llvm_unreachable(::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1614)
1614 "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1614)
;
1615 }
1616
1617 /// Represents how an instruction should be mapped by the outliner.
1618 /// \p Legal instructions are those which are safe to outline.
1619 /// \p Illegal instructions are those which cannot be outlined.
1620 /// \p Invisible instructions are instructions which can be outlined, but
1621 /// shouldn't actually impact the outlining result.
1622 enum MachineOutlinerInstrType { Legal, Illegal, Invisible };
1623
1624 /// Returns how or if \p MI should be outlined.
1625 virtual MachineOutlinerInstrType
1626 getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const {
1627 llvm_unreachable(::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::getOutliningType!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1628)
1628 "Target didn't implement TargetInstrInfo::getOutliningType!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::getOutliningType!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1628)
;
1629 }
1630
1631 /// \brief Returns target-defined flags defining properties of the MBB for
1632 /// the outliner.
1633 virtual unsigned getMachineOutlinerMBBFlags(MachineBasicBlock &MBB) const {
1634 return 0x0;
1635 }
1636
1637 /// Insert a custom epilogue for outlined functions.
1638 /// This may be empty, in which case no epilogue or return statement will be
1639 /// emitted.
1640 virtual void insertOutlinerEpilogue(MachineBasicBlock &MBB,
1641 MachineFunction &MF,
1642 const MachineOutlinerInfo &MInfo) const {
1643 llvm_unreachable(::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1644)
1644 "Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertOutlinerEpilogue!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1644)
;
1645 }
1646
1647 /// Insert a call to an outlined function into the program.
1648 /// Returns an iterator to the spot where we inserted the call. This must be
1649 /// implemented by the target.
1650 virtual MachineBasicBlock::iterator
1651 insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
1652 MachineBasicBlock::iterator &It, MachineFunction &MF,
1653 const MachineOutlinerInfo &MInfo) const {
1654 llvm_unreachable(::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertOutlinedCall!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1655)
1655 "Target didn't implement TargetInstrInfo::insertOutlinedCall!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertOutlinedCall!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1655)
;
1656 }
1657
1658 /// Insert a custom prologue for outlined functions.
1659 /// This may be empty, in which case no prologue will be emitted.
1660 virtual void insertOutlinerPrologue(MachineBasicBlock &MBB,
1661 MachineFunction &MF,
1662 const MachineOutlinerInfo &MInfo) const {
1663 llvm_unreachable(::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertOutlinerPrologue!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1664)
1664 "Target didn't implement TargetInstrInfo::insertOutlinerPrologue!")::llvm::llvm_unreachable_internal("Target didn't implement TargetInstrInfo::insertOutlinerPrologue!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1664)
;
1665 }
1666
1667 /// Return true if the function can safely be outlined from.
1668 /// A function \p MF is considered safe for outlining if an outlined function
1669 /// produced from instructions in F will produce a program which produces the
1670 /// same output for any set of given inputs.
1671 virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
1672 bool OutlineFromLinkOnceODRs) const {
1673 llvm_unreachable("Target didn't implement "::llvm::llvm_unreachable_internal("Target didn't implement " "TargetInstrInfo::isFunctionSafeToOutlineFrom!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1674)
1674 "TargetInstrInfo::isFunctionSafeToOutlineFrom!")::llvm::llvm_unreachable_internal("Target didn't implement " "TargetInstrInfo::isFunctionSafeToOutlineFrom!"
, "/build/llvm-toolchain-snapshot-7~svn329677/include/llvm/CodeGen/TargetInstrInfo.h"
, 1674)
;
1675 }
1676
1677private:
1678 unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode;
1679 unsigned CatchRetOpcode;
1680 unsigned ReturnOpcode;
1681};
1682
1683/// \brief Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair.
1684template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> {
1685 using RegInfo = DenseMapInfo<unsigned>;
1686
1687 static inline TargetInstrInfo::RegSubRegPair getEmptyKey() {
1688 return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(),
1689 RegInfo::getEmptyKey());
1690 }
1691
1692 static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() {
1693 return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(),
1694 RegInfo::getTombstoneKey());
1695 }
1696
1697 /// \brief Reuse getHashValue implementation from
1698 /// std::pair<unsigned, unsigned>.
1699 static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) {
1700 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1701 return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal);
1702 }
1703
1704 static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS,
1705 const TargetInstrInfo::RegSubRegPair &RHS) {
1706 return RegInfo::isEqual(LHS.Reg, RHS.Reg) &&
1707 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
1708 }
1709};
1710
1711} // end namespace llvm
1712
1713#endif // LLVM_TARGET_TARGETINSTRINFO_H