Bug Summary

File:lib/CodeGen/InlineSpiller.cpp
Warning:line 276, column 61
The left operand of '==' is a garbage value

Annotated Source Code

1//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// The inline spiller modifies the machine function directly instead of
11// inserting spills and restores in VirtRegMap.
12//
13//===----------------------------------------------------------------------===//
14
15#include "Spiller.h"
16#include "SplitKit.h"
17#include "llvm/ADT/MapVector.h"
18#include "llvm/ADT/SetVector.h"
19#include "llvm/ADT/Statistic.h"
20#include "llvm/ADT/TinyPtrVector.h"
21#include "llvm/Analysis/AliasAnalysis.h"
22#include "llvm/CodeGen/LiveIntervalAnalysis.h"
23#include "llvm/CodeGen/LiveRangeEdit.h"
24#include "llvm/CodeGen/LiveStackAnalysis.h"
25#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
26#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
27#include "llvm/CodeGen/MachineDominators.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineLoopInfo.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/VirtRegMap.h"
35#include "llvm/IR/DebugInfo.h"
36#include "llvm/Support/CommandLine.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/raw_ostream.h"
39#include "llvm/Target/TargetInstrInfo.h"
40
41using namespace llvm;
42
43#define DEBUG_TYPE"regalloc" "regalloc"
44
45STATISTIC(NumSpilledRanges, "Number of spilled live ranges")static llvm::Statistic NumSpilledRanges = {"regalloc", "NumSpilledRanges"
, "Number of spilled live ranges", {0}, false}
;
46STATISTIC(NumSnippets, "Number of spilled snippets")static llvm::Statistic NumSnippets = {"regalloc", "NumSnippets"
, "Number of spilled snippets", {0}, false}
;
47STATISTIC(NumSpills, "Number of spills inserted")static llvm::Statistic NumSpills = {"regalloc", "NumSpills", "Number of spills inserted"
, {0}, false}
;
48STATISTIC(NumSpillsRemoved, "Number of spills removed")static llvm::Statistic NumSpillsRemoved = {"regalloc", "NumSpillsRemoved"
, "Number of spills removed", {0}, false}
;
49STATISTIC(NumReloads, "Number of reloads inserted")static llvm::Statistic NumReloads = {"regalloc", "NumReloads"
, "Number of reloads inserted", {0}, false}
;
50STATISTIC(NumReloadsRemoved, "Number of reloads removed")static llvm::Statistic NumReloadsRemoved = {"regalloc", "NumReloadsRemoved"
, "Number of reloads removed", {0}, false}
;
51STATISTIC(NumFolded, "Number of folded stack accesses")static llvm::Statistic NumFolded = {"regalloc", "NumFolded", "Number of folded stack accesses"
, {0}, false}
;
52STATISTIC(NumFoldedLoads, "Number of folded loads")static llvm::Statistic NumFoldedLoads = {"regalloc", "NumFoldedLoads"
, "Number of folded loads", {0}, false}
;
53STATISTIC(NumRemats, "Number of rematerialized defs for spilling")static llvm::Statistic NumRemats = {"regalloc", "NumRemats", "Number of rematerialized defs for spilling"
, {0}, false}
;
54
55static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
56 cl::desc("Disable inline spill hoisting"));
57
58namespace {
59class HoistSpillHelper : private LiveRangeEdit::Delegate {
60 MachineFunction &MF;
61 LiveIntervals &LIS;
62 LiveStacks &LSS;
63 AliasAnalysis *AA;
64 MachineDominatorTree &MDT;
65 MachineLoopInfo &Loops;
66 VirtRegMap &VRM;
67 MachineFrameInfo &MFI;
68 MachineRegisterInfo &MRI;
69 const TargetInstrInfo &TII;
70 const TargetRegisterInfo &TRI;
71 const MachineBlockFrequencyInfo &MBFI;
72
73 InsertPointAnalysis IPA;
74
75 // Map from StackSlot to its original register.
76 DenseMap<int, unsigned> StackSlotToReg;
77 // Map from pair of (StackSlot and Original VNI) to a set of spills which
78 // have the same stackslot and have equal values defined by Original VNI.
79 // These spills are mergeable and are hoist candiates.
80 typedef MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>
81 MergeableSpillsMap;
82 MergeableSpillsMap MergeableSpills;
83
84 /// This is the map from original register to a set containing all its
85 /// siblings. To hoist a spill to another BB, we need to find out a live
86 /// sibling there and use it as the source of the new spill.
87 DenseMap<unsigned, SmallSetVector<unsigned, 16>> Virt2SiblingsMap;
88
89 bool isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, MachineBasicBlock &BB,
90 unsigned &LiveReg);
91
92 void rmRedundantSpills(
93 SmallPtrSet<MachineInstr *, 16> &Spills,
94 SmallVectorImpl<MachineInstr *> &SpillsToRm,
95 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
96
97 void getVisitOrders(
98 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
99 SmallVectorImpl<MachineDomTreeNode *> &Orders,
100 SmallVectorImpl<MachineInstr *> &SpillsToRm,
101 DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
102 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
103
104 void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
105 SmallPtrSet<MachineInstr *, 16> &Spills,
106 SmallVectorImpl<MachineInstr *> &SpillsToRm,
107 DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
108
109public:
110 HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf,
111 VirtRegMap &vrm)
112 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
113 LSS(pass.getAnalysis<LiveStacks>()),
114 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
115 MDT(pass.getAnalysis<MachineDominatorTree>()),
116 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
117 MFI(mf.getFrameInfo()), MRI(mf.getRegInfo()),
118 TII(*mf.getSubtarget().getInstrInfo()),
119 TRI(*mf.getSubtarget().getRegisterInfo()),
120 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
121 IPA(LIS, mf.getNumBlockIDs()) {}
122
123 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
124 unsigned Original);
125 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
126 void hoistAllSpills();
127 void LRE_DidCloneVirtReg(unsigned, unsigned) override;
128};
129
130class InlineSpiller : public Spiller {
131 MachineFunction &MF;
132 LiveIntervals &LIS;
133 LiveStacks &LSS;
134 AliasAnalysis *AA;
135 MachineDominatorTree &MDT;
136 MachineLoopInfo &Loops;
137 VirtRegMap &VRM;
138 MachineFrameInfo &MFI;
139 MachineRegisterInfo &MRI;
140 const TargetInstrInfo &TII;
141 const TargetRegisterInfo &TRI;
142 const MachineBlockFrequencyInfo &MBFI;
143
144 // Variables that are valid during spill(), but used by multiple methods.
145 LiveRangeEdit *Edit;
146 LiveInterval *StackInt;
147 int StackSlot;
148 unsigned Original;
149
150 // All registers to spill to StackSlot, including the main register.
151 SmallVector<unsigned, 8> RegsToSpill;
152
153 // All COPY instructions to/from snippets.
154 // They are ignored since both operands refer to the same stack slot.
155 SmallPtrSet<MachineInstr*, 8> SnippetCopies;
156
157 // Values that failed to remat at some point.
158 SmallPtrSet<VNInfo*, 8> UsedValues;
159
160 // Dead defs generated during spilling.
161 SmallVector<MachineInstr*, 8> DeadDefs;
162
163 // Object records spills information and does the hoisting.
164 HoistSpillHelper HSpiller;
165
166 ~InlineSpiller() override {}
167
168public:
169 InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
170 : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()),
171 LSS(pass.getAnalysis<LiveStacks>()),
172 AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()),
173 MDT(pass.getAnalysis<MachineDominatorTree>()),
174 Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm),
175 MFI(mf.getFrameInfo()), MRI(mf.getRegInfo()),
176 TII(*mf.getSubtarget().getInstrInfo()),
177 TRI(*mf.getSubtarget().getRegisterInfo()),
178 MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()),
179 HSpiller(pass, mf, vrm) {}
180
181 void spill(LiveRangeEdit &) override;
182 void postOptimization() override;
183
184private:
185 bool isSnippet(const LiveInterval &SnipLI);
186 void collectRegsToSpill();
187
188 bool isRegToSpill(unsigned Reg) { return is_contained(RegsToSpill, Reg); }
189
190 bool isSibling(unsigned Reg);
191 bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI);
192 void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI);
193
194 void markValueUsed(LiveInterval*, VNInfo*);
195 bool reMaterializeFor(LiveInterval &, MachineInstr &MI);
196 void reMaterializeAll();
197
198 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
199 bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> >,
200 MachineInstr *LoadMI = nullptr);
201 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
202 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
203
204 void spillAroundUses(unsigned Reg);
205 void spillAll();
206};
207}
208
209namespace llvm {
210
211Spiller::~Spiller() { }
212void Spiller::anchor() { }
213
214Spiller *createInlineSpiller(MachineFunctionPass &pass,
215 MachineFunction &mf,
216 VirtRegMap &vrm) {
217 return new InlineSpiller(pass, mf, vrm);
218}
219
220}
221
222//===----------------------------------------------------------------------===//
223// Snippets
224//===----------------------------------------------------------------------===//
225
226// When spilling a virtual register, we also spill any snippets it is connected
227// to. The snippets are small live ranges that only have a single real use,
228// leftovers from live range splitting. Spilling them enables memory operand
229// folding or tightens the live range around the single use.
230//
231// This minimizes register pressure and maximizes the store-to-load distance for
232// spill slots which can be important in tight loops.
233
234/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
235/// otherwise return 0.
236static unsigned isFullCopyOf(const MachineInstr &MI, unsigned Reg) {
237 if (!MI.isFullCopy())
238 return 0;
239 if (MI.getOperand(0).getReg() == Reg)
240 return MI.getOperand(1).getReg();
241 if (MI.getOperand(1).getReg() == Reg)
242 return MI.getOperand(0).getReg();
243 return 0;
244}
245
246/// isSnippet - Identify if a live interval is a snippet that should be spilled.
247/// It is assumed that SnipLI is a virtual register with the same original as
248/// Edit->getReg().
249bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
250 unsigned Reg = Edit->getReg();
251
252 // A snippet is a tiny live range with only a single instruction using it
253 // besides copies to/from Reg or spills/fills. We accept:
254 //
255 // %snip = COPY %Reg / FILL fi#
256 // %snip = USE %snip
257 // %Reg = COPY %snip / SPILL %snip, fi#
258 //
259 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI))
1
Assuming the condition is false
2
Assuming the condition is false
3
Taking false branch
260 return false;
261
262 MachineInstr *UseMI = nullptr;
263
264 // Check that all uses satisfy our criteria.
265 for (MachineRegisterInfo::reg_instr_nodbg_iterator
4
Loop condition is true. Entering loop body
266 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg),
267 E = MRI.reg_instr_nodbg_end(); RI != E; ) {
268 MachineInstr &MI = *RI++;
269
270 // Allow copies to/from Reg.
271 if (isFullCopyOf(MI, Reg))
5
Taking false branch
272 continue;
273
274 // Allow stack slot loads.
275 int FI;
6
'FI' declared without an initial value
276 if (SnipLI.reg == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
7
Calling 'TargetInstrInfo::isLoadFromStackSlot'
8
Returning from 'TargetInstrInfo::isLoadFromStackSlot'
9
Assuming the condition is true
10
The left operand of '==' is a garbage value
277 continue;
278
279 // Allow stack slot stores.
280 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
281 continue;
282
283 // Allow a single additional instruction.
284 if (UseMI && &MI != UseMI)
285 return false;
286 UseMI = &MI;
287 }
288 return true;
289}
290
291/// collectRegsToSpill - Collect live range snippets that only have a single
292/// real use.
293void InlineSpiller::collectRegsToSpill() {
294 unsigned Reg = Edit->getReg();
295
296 // Main register always spills.
297 RegsToSpill.assign(1, Reg);
298 SnippetCopies.clear();
299
300 // Snippets all have the same original, so there can't be any for an original
301 // register.
302 if (Original == Reg)
303 return;
304
305 for (MachineRegisterInfo::reg_instr_iterator
306 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) {
307 MachineInstr &MI = *RI++;
308 unsigned SnipReg = isFullCopyOf(MI, Reg);
309 if (!isSibling(SnipReg))
310 continue;
311 LiveInterval &SnipLI = LIS.getInterval(SnipReg);
312 if (!isSnippet(SnipLI))
313 continue;
314 SnippetCopies.insert(&MI);
315 if (isRegToSpill(SnipReg))
316 continue;
317 RegsToSpill.push_back(SnipReg);
318 DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\talso spill snippet " <<
SnipLI << '\n'; } } while (false)
;
319 ++NumSnippets;
320 }
321}
322
323bool InlineSpiller::isSibling(unsigned Reg) {
324 return TargetRegisterInfo::isVirtualRegister(Reg) &&
325 VRM.getOriginal(Reg) == Original;
326}
327
328/// It is beneficial to spill to earlier place in the same BB in case
329/// as follows:
330/// There is an alternative def earlier in the same MBB.
331/// Hoist the spill as far as possible in SpillMBB. This can ease
332/// register pressure:
333///
334/// x = def
335/// y = use x
336/// s = copy x
337///
338/// Hoisting the spill of s to immediately after the def removes the
339/// interference between x and y:
340///
341/// x = def
342/// spill x
343/// y = use x<kill>
344///
345/// This hoist only helps when the copy kills its source.
346///
347bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
348 MachineInstr &CopyMI) {
349 SlotIndex Idx = LIS.getInstructionIndex(CopyMI);
350#ifndef NDEBUG
351 VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot());
352 assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy")((VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy"
) ? static_cast<void> (0) : __assert_fail ("VNI && VNI->def == Idx.getRegSlot() && \"Not defined by copy\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 352, __PRETTY_FUNCTION__))
;
353#endif
354
355 unsigned SrcReg = CopyMI.getOperand(1).getReg();
356 LiveInterval &SrcLI = LIS.getInterval(SrcReg);
357 VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx);
358 LiveQueryResult SrcQ = SrcLI.Query(Idx);
359 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(SrcVNI->def);
360 if (DefMBB != CopyMI.getParent() || !SrcQ.isKill())
361 return false;
362
363 // Conservatively extend the stack slot range to the range of the original
364 // value. We may be able to do better with stack slot coloring by being more
365 // careful here.
366 assert(StackInt && "No stack slot assigned yet.")((StackInt && "No stack slot assigned yet.") ? static_cast
<void> (0) : __assert_fail ("StackInt && \"No stack slot assigned yet.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 366, __PRETTY_FUNCTION__))
;
367 LiveInterval &OrigLI = LIS.getInterval(Original);
368 VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
369 StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
370 DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tmerged orig valno " <<
OrigVNI->id << ": " << *StackInt << '\n'
; } } while (false)
371 << *StackInt << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tmerged orig valno " <<
OrigVNI->id << ": " << *StackInt << '\n'
; } } while (false)
;
372
373 // We are going to spill SrcVNI immediately after its def, so clear out
374 // any later spills of the same value.
375 eliminateRedundantSpills(SrcLI, SrcVNI);
376
377 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def);
378 MachineBasicBlock::iterator MII;
379 if (SrcVNI->isPHIDef())
380 MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin());
381 else {
382 MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def);
383 assert(DefMI && "Defining instruction disappeared")((DefMI && "Defining instruction disappeared") ? static_cast
<void> (0) : __assert_fail ("DefMI && \"Defining instruction disappeared\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 383, __PRETTY_FUNCTION__))
;
384 MII = DefMI;
385 ++MII;
386 }
387 // Insert spill without kill flag immediately after def.
388 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
389 MRI.getRegClass(SrcReg), &TRI);
390 --MII; // Point to store instruction.
391 LIS.InsertMachineInstrInMaps(*MII);
392 DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\thoisted: " << SrcVNI
->def << '\t' << *MII; } } while (false)
;
393
394 HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
395 ++NumSpills;
396 return true;
397}
398
399/// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any
400/// redundant spills of this value in SLI.reg and sibling copies.
401void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
402 assert(VNI && "Missing value")((VNI && "Missing value") ? static_cast<void> (
0) : __assert_fail ("VNI && \"Missing value\"", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 402, __PRETTY_FUNCTION__))
;
403 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
404 WorkList.push_back(std::make_pair(&SLI, VNI));
405 assert(StackInt && "No stack slot assigned yet.")((StackInt && "No stack slot assigned yet.") ? static_cast
<void> (0) : __assert_fail ("StackInt && \"No stack slot assigned yet.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 405, __PRETTY_FUNCTION__))
;
406
407 do {
408 LiveInterval *LI;
409 std::tie(LI, VNI) = WorkList.pop_back_val();
410 unsigned Reg = LI->reg;
411 DEBUG(dbgs() << "Checking redundant spills for "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Checking redundant spills for "
<< VNI->id << '@' << VNI->def <<
" in " << *LI << '\n'; } } while (false)
412 << VNI->id << '@' << VNI->def << " in " << *LI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Checking redundant spills for "
<< VNI->id << '@' << VNI->def <<
" in " << *LI << '\n'; } } while (false)
;
413
414 // Regs to spill are taken care of.
415 if (isRegToSpill(Reg))
416 continue;
417
418 // Add all of VNI's live range to StackInt.
419 StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
420 DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Merged to stack int: " <<
*StackInt << '\n'; } } while (false)
;
421
422 // Find all spills and copies of VNI.
423 for (MachineRegisterInfo::use_instr_nodbg_iterator
424 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end();
425 UI != E; ) {
426 MachineInstr &MI = *UI++;
427 if (!MI.isCopy() && !MI.mayStore())
428 continue;
429 SlotIndex Idx = LIS.getInstructionIndex(MI);
430 if (LI->getVNInfoAt(Idx) != VNI)
431 continue;
432
433 // Follow sibling copies down the dominator tree.
434 if (unsigned DstReg = isFullCopyOf(MI, Reg)) {
435 if (isSibling(DstReg)) {
436 LiveInterval &DstLI = LIS.getInterval(DstReg);
437 VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
438 assert(DstVNI && "Missing defined value")((DstVNI && "Missing defined value") ? static_cast<
void> (0) : __assert_fail ("DstVNI && \"Missing defined value\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 438, __PRETTY_FUNCTION__))
;
439 assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot")((DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot"
) ? static_cast<void> (0) : __assert_fail ("DstVNI->def == Idx.getRegSlot() && \"Wrong copy def slot\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 439, __PRETTY_FUNCTION__))
;
440 WorkList.push_back(std::make_pair(&DstLI, DstVNI));
441 }
442 continue;
443 }
444
445 // Erase spills.
446 int FI;
447 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
448 DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Redundant spill " << Idx
<< '\t' << MI; } } while (false)
;
449 // eliminateDeadDefs won't normally remove stores, so switch opcode.
450 MI.setDesc(TII.get(TargetOpcode::KILL));
451 DeadDefs.push_back(&MI);
452 ++NumSpillsRemoved;
453 if (HSpiller.rmFromMergeableSpills(MI, StackSlot))
454 --NumSpills;
455 }
456 }
457 } while (!WorkList.empty());
458}
459
460
461//===----------------------------------------------------------------------===//
462// Rematerialization
463//===----------------------------------------------------------------------===//
464
465/// markValueUsed - Remember that VNI failed to rematerialize, so its defining
466/// instruction cannot be eliminated. See through snippet copies
467void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
468 SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList;
469 WorkList.push_back(std::make_pair(LI, VNI));
470 do {
471 std::tie(LI, VNI) = WorkList.pop_back_val();
472 if (!UsedValues.insert(VNI).second)
473 continue;
474
475 if (VNI->isPHIDef()) {
476 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
477 for (MachineBasicBlock *P : MBB->predecessors()) {
478 VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
479 if (PVNI)
480 WorkList.push_back(std::make_pair(LI, PVNI));
481 }
482 continue;
483 }
484
485 // Follow snippet copies.
486 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
487 if (!SnippetCopies.count(MI))
488 continue;
489 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
490 assert(isRegToSpill(SnipLI.reg) && "Unexpected register in copy")((isRegToSpill(SnipLI.reg) && "Unexpected register in copy"
) ? static_cast<void> (0) : __assert_fail ("isRegToSpill(SnipLI.reg) && \"Unexpected register in copy\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 490, __PRETTY_FUNCTION__))
;
491 VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true));
492 assert(SnipVNI && "Snippet undefined before copy")((SnipVNI && "Snippet undefined before copy") ? static_cast
<void> (0) : __assert_fail ("SnipVNI && \"Snippet undefined before copy\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 492, __PRETTY_FUNCTION__))
;
493 WorkList.push_back(std::make_pair(&SnipLI, SnipVNI));
494 } while (!WorkList.empty());
495}
496
497/// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
498bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
499
500 // Analyze instruction
501 SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops;
502 MIBundleOperands::VirtRegInfo RI =
503 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
504
505 if (!RI.Reads)
506 return false;
507
508 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true);
509 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
510
511 if (!ParentVNI) {
512 DEBUG(dbgs() << "\tadding <undef> flags: ")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tadding <undef> flags: "
; } } while (false)
;
513 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
514 MachineOperand &MO = MI.getOperand(i);
515 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
516 MO.setIsUndef();
517 }
518 DEBUG(dbgs() << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << UseIdx << '\t' <<
MI; } } while (false)
;
519 return true;
520 }
521
522 if (SnippetCopies.count(&MI))
523 return false;
524
525 LiveInterval &OrigLI = LIS.getInterval(Original);
526 VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx);
527 LiveRangeEdit::Remat RM(ParentVNI);
528 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
529
530 if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) {
531 markValueUsed(&VirtReg, ParentVNI);
532 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tcannot remat for " <<
UseIdx << '\t' << MI; } } while (false)
;
533 return false;
534 }
535
536 // If the instruction also writes VirtReg.reg, it had better not require the
537 // same register for uses and defs.
538 if (RI.Tied) {
539 markValueUsed(&VirtReg, ParentVNI);
540 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tcannot remat tied reg: " <<
UseIdx << '\t' << MI; } } while (false)
;
541 return false;
542 }
543
544 // Before rematerializing into a register for a single instruction, try to
545 // fold a load into the instruction. That avoids allocating a new register.
546 if (RM.OrigMI->canFoldAsLoad() &&
547 foldMemoryOperand(Ops, RM.OrigMI)) {
548 Edit->markRematerialized(RM.ParentVNI);
549 ++NumFoldedLoads;
550 return true;
551 }
552
553 // Allocate a new register for the remat.
554 unsigned NewVReg = Edit->createFrom(Original);
555
556 // Finally we can rematerialize OrigMI before MI.
557 SlotIndex DefIdx =
558 Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI);
559
560 // We take the DebugLoc from MI, since OrigMI may be attributed to a
561 // different source location.
562 auto *NewMI = LIS.getInstructionFromIndex(DefIdx);
563 NewMI->setDebugLoc(MI.getDebugLoc());
564
565 (void)DefIdx;
566 DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremat: " << DefIdx <<
'\t' << *LIS.getInstructionFromIndex(DefIdx); } } while
(false)
567 << *LIS.getInstructionFromIndex(DefIdx))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\tremat: " << DefIdx <<
'\t' << *LIS.getInstructionFromIndex(DefIdx); } } while
(false)
;
568
569 // Replace operands
570 for (const auto &OpPair : Ops) {
571 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
572 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
573 MO.setReg(NewVReg);
574 MO.setIsKill();
575 }
576 }
577 DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\t " << UseIdx <<
'\t' << MI << '\n'; } } while (false)
;
578
579 ++NumRemats;
580 return true;
581}
582
583/// reMaterializeAll - Try to rematerialize as many uses as possible,
584/// and trim the live ranges after.
585void InlineSpiller::reMaterializeAll() {
586 if (!Edit->anyRematerializable(AA))
587 return;
588
589 UsedValues.clear();
590
591 // Try to remat before all uses of snippets.
592 bool anyRemat = false;
593 for (unsigned Reg : RegsToSpill) {
594 LiveInterval &LI = LIS.getInterval(Reg);
595 for (MachineRegisterInfo::reg_bundle_iterator
596 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
597 RegI != E; ) {
598 MachineInstr &MI = *RegI++;
599
600 // Debug values are not allowed to affect codegen.
601 if (MI.isDebugValue())
602 continue;
603
604 anyRemat |= reMaterializeFor(LI, MI);
605 }
606 }
607 if (!anyRemat)
608 return;
609
610 // Remove any values that were completely rematted.
611 for (unsigned Reg : RegsToSpill) {
612 LiveInterval &LI = LIS.getInterval(Reg);
613 for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
614 I != E; ++I) {
615 VNInfo *VNI = *I;
616 if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI))
617 continue;
618 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def);
619 MI->addRegisterDead(Reg, &TRI);
620 if (!MI->allDefsAreDead())
621 continue;
622 DEBUG(dbgs() << "All defs dead: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "All defs dead: " << *MI
; } } while (false)
;
623 DeadDefs.push_back(MI);
624 }
625 }
626
627 // Eliminate dead code after remat. Note that some snippet copies may be
628 // deleted here.
629 if (DeadDefs.empty())
630 return;
631 DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Remat created " << DeadDefs
.size() << " dead defs.\n"; } } while (false)
;
632 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
633
634 // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
635 // after rematerialization. To remove a VNI for a vreg from its LiveInterval,
636 // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all
637 // removed, PHI VNI are still left in the LiveInterval.
638 // So to get rid of unused reg, we need to check whether it has non-dbg
639 // reference instead of whether it has non-empty interval.
640 unsigned ResultPos = 0;
641 for (unsigned Reg : RegsToSpill) {
642 if (MRI.reg_nodbg_empty(Reg)) {
643 Edit->eraseVirtReg(Reg);
644 continue;
645 }
646 assert((LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty()) &&(((LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty
()) && "Reg with empty interval has reference") ? static_cast
<void> (0) : __assert_fail ("(LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty()) && \"Reg with empty interval has reference\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 647, __PRETTY_FUNCTION__))
647 "Reg with empty interval has reference")(((LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty
()) && "Reg with empty interval has reference") ? static_cast
<void> (0) : __assert_fail ("(LIS.hasInterval(Reg) && !LIS.getInterval(Reg).empty()) && \"Reg with empty interval has reference\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 647, __PRETTY_FUNCTION__))
;
648 RegsToSpill[ResultPos++] = Reg;
649 }
650 RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
651 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << RegsToSpill.size() << " registers to spill after remat.\n"
; } } while (false)
;
652}
653
654
655//===----------------------------------------------------------------------===//
656// Spilling
657//===----------------------------------------------------------------------===//
658
659/// If MI is a load or store of StackSlot, it can be removed.
660bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
661 int FI = 0;
662 unsigned InstrReg = TII.isLoadFromStackSlot(*MI, FI);
663 bool IsLoad = InstrReg;
664 if (!IsLoad)
665 InstrReg = TII.isStoreToStackSlot(*MI, FI);
666
667 // We have a stack access. Is it the right register and slot?
668 if (InstrReg != Reg || FI != StackSlot)
669 return false;
670
671 if (!IsLoad)
672 HSpiller.rmFromMergeableSpills(*MI, StackSlot);
673
674 DEBUG(dbgs() << "Coalescing stack access: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Coalescing stack access: " <<
*MI; } } while (false)
;
675 LIS.RemoveMachineInstrFromMaps(*MI);
676 MI->eraseFromParent();
677
678 if (IsLoad) {
679 ++NumReloadsRemoved;
680 --NumReloads;
681 } else {
682 ++NumSpillsRemoved;
683 --NumSpills;
684 }
685
686 return true;
687}
688
689#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
690LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__))
691// Dump the range of instructions from B to E with their slot indexes.
692static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B,
693 MachineBasicBlock::iterator E,
694 LiveIntervals const &LIS,
695 const char *const header,
696 unsigned VReg =0) {
697 char NextLine = '\n';
698 char SlotIndent = '\t';
699
700 if (std::next(B) == E) {
701 NextLine = ' ';
702 SlotIndent = ' ';
703 }
704
705 dbgs() << '\t' << header << ": " << NextLine;
706
707 for (MachineBasicBlock::iterator I = B; I != E; ++I) {
708 SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot();
709
710 // If a register was passed in and this instruction has it as a
711 // destination that is marked as an early clobber, print the
712 // early-clobber slot index.
713 if (VReg) {
714 MachineOperand *MO = I->findRegisterDefOperand(VReg);
715 if (MO && MO->isEarlyClobber())
716 Idx = Idx.getRegSlot(true);
717 }
718
719 dbgs() << SlotIndent << Idx << '\t' << *I;
720 }
721}
722#endif
723
724/// foldMemoryOperand - Try folding stack slot references in Ops into their
725/// instructions.
726///
727/// @param Ops Operand indices from analyzeVirtReg().
728/// @param LoadMI Load instruction to use instead of stack slot when non-null.
729/// @return True on success.
730bool InlineSpiller::
731foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
732 MachineInstr *LoadMI) {
733 if (Ops.empty())
734 return false;
735 // Don't attempt folding in bundles.
736 MachineInstr *MI = Ops.front().first;
737 if (Ops.back().first != MI || MI->isBundled())
738 return false;
739
740 bool WasCopy = MI->isCopy();
741 unsigned ImpReg = 0;
742
743 // Spill subregs if the target allows it.
744 // We always want to spill subregs for stackmap/patchpoint pseudos.
745 bool SpillSubRegs = TII.isSubregFoldable() ||
746 MI->getOpcode() == TargetOpcode::STATEPOINT ||
747 MI->getOpcode() == TargetOpcode::PATCHPOINT ||
748 MI->getOpcode() == TargetOpcode::STACKMAP;
749
750 // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
751 // operands.
752 SmallVector<unsigned, 8> FoldOps;
753 for (const auto &OpPair : Ops) {
754 unsigned Idx = OpPair.second;
755 assert(MI == OpPair.first && "Instruction conflict during operand folding")((MI == OpPair.first && "Instruction conflict during operand folding"
) ? static_cast<void> (0) : __assert_fail ("MI == OpPair.first && \"Instruction conflict during operand folding\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 755, __PRETTY_FUNCTION__))
;
756 MachineOperand &MO = MI->getOperand(Idx);
757 if (MO.isImplicit()) {
758 ImpReg = MO.getReg();
759 continue;
760 }
761
762 if (!SpillSubRegs && MO.getSubReg())
763 return false;
764 // We cannot fold a load instruction into a def.
765 if (LoadMI && MO.isDef())
766 return false;
767 // Tied use operands should not be passed to foldMemoryOperand.
768 if (!MI->isRegTiedToDefOperand(Idx))
769 FoldOps.push_back(Idx);
770 }
771
772 // If we only have implicit uses, we won't be able to fold that.
773 // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try!
774 if (FoldOps.empty())
775 return false;
776
777 MachineInstrSpan MIS(MI);
778
779 MachineInstr *FoldMI =
780 LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS)
781 : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS);
782 if (!FoldMI)
783 return false;
784
785 // Remove LIS for any dead defs in the original MI not in FoldMI.
786 for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) {
787 if (!MO->isReg())
788 continue;
789 unsigned Reg = MO->getReg();
790 if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
791 MRI.isReserved(Reg)) {
792 continue;
793 }
794 // Skip non-Defs, including undef uses and internal reads.
795 if (MO->isUse())
796 continue;
797 MIBundleOperands::PhysRegInfo RI =
798 MIBundleOperands(*FoldMI).analyzePhysReg(Reg, &TRI);
799 if (RI.FullyDefined)
800 continue;
801 // FoldMI does not define this physreg. Remove the LI segment.
802 assert(MO->isDead() && "Cannot fold physreg def")((MO->isDead() && "Cannot fold physreg def") ? static_cast
<void> (0) : __assert_fail ("MO->isDead() && \"Cannot fold physreg def\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 802, __PRETTY_FUNCTION__))
;
803 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
804 LIS.removePhysRegDefAt(Reg, Idx);
805 }
806
807 int FI;
808 if (TII.isStoreToStackSlot(*MI, FI) &&
809 HSpiller.rmFromMergeableSpills(*MI, FI))
810 --NumSpills;
811 LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI);
812 MI->eraseFromParent();
813
814 // Insert any new instructions other than FoldMI into the LIS maps.
815 assert(!MIS.empty() && "Unexpected empty span of instructions!")((!MIS.empty() && "Unexpected empty span of instructions!"
) ? static_cast<void> (0) : __assert_fail ("!MIS.empty() && \"Unexpected empty span of instructions!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 815, __PRETTY_FUNCTION__))
;
816 for (MachineInstr &MI : MIS)
817 if (&MI != FoldMI)
818 LIS.InsertMachineInstrInMaps(MI);
819
820 // TII.foldMemoryOperand may have left some implicit operands on the
821 // instruction. Strip them.
822 if (ImpReg)
823 for (unsigned i = FoldMI->getNumOperands(); i; --i) {
824 MachineOperand &MO = FoldMI->getOperand(i - 1);
825 if (!MO.isReg() || !MO.isImplicit())
826 break;
827 if (MO.getReg() == ImpReg)
828 FoldMI->RemoveOperand(i - 1);
829 }
830
831 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MIS.end(), LIS, "folded"); } } while (false)
832 "folded"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MIS.end(), LIS, "folded"); } } while (false)
;
833
834 if (!WasCopy)
835 ++NumFolded;
836 else if (Ops.front().second == 0) {
837 ++NumSpills;
838 HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original);
839 } else
840 ++NumReloads;
841 return true;
842}
843
844void InlineSpiller::insertReload(unsigned NewVReg,
845 SlotIndex Idx,
846 MachineBasicBlock::iterator MI) {
847 MachineBasicBlock &MBB = *MI->getParent();
848
849 MachineInstrSpan MIS(MI);
850 TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot,
851 MRI.getRegClass(NewVReg), &TRI);
852
853 LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
854
855 DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MI, LIS, "reload", NewVReg); } } while (false)
856 NewVReg))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(MIS.begin(
), MI, LIS, "reload", NewVReg); } } while (false)
;
857 ++NumReloads;
858}
859
860/// insertSpill - Insert a spill of NewVReg after MI.
861void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
862 MachineBasicBlock::iterator MI) {
863 MachineBasicBlock &MBB = *MI->getParent();
864
865 MachineInstrSpan MIS(MI);
866 TII.storeRegToStackSlot(MBB, std::next(MI), NewVReg, isKill, StackSlot,
867 MRI.getRegClass(NewVReg), &TRI);
868
869 LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
870
871 DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(std::next(
MI), MIS.end(), LIS, "spill"); } } while (false)
872 "spill"))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dumpMachineInstrRangeWithSlotIndex(std::next(
MI), MIS.end(), LIS, "spill"); } } while (false)
;
873 ++NumSpills;
874 HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
875}
876
877/// spillAroundUses - insert spill code around each use of Reg.
878void InlineSpiller::spillAroundUses(unsigned Reg) {
879 DEBUG(dbgs() << "spillAroundUses " << PrintReg(Reg) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "spillAroundUses " << PrintReg
(Reg) << '\n'; } } while (false)
;
880 LiveInterval &OldLI = LIS.getInterval(Reg);
881
882 // Iterate over instructions using Reg.
883 for (MachineRegisterInfo::reg_bundle_iterator
884 RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
885 RegI != E; ) {
886 MachineInstr *MI = &*(RegI++);
887
888 // Debug values are not allowed to affect codegen.
889 if (MI->isDebugValue()) {
890 // Modify DBG_VALUE now that the value is in a spill slot.
891 MachineBasicBlock *MBB = MI->getParent();
892 DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Modifying debug info due to spill:\t"
<< *MI; } } while (false)
;
893 buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
894 MBB->erase(MI);
895 continue;
896 }
897
898 // Ignore copies to/from snippets. We'll delete them.
899 if (SnippetCopies.count(MI))
900 continue;
901
902 // Stack slot accesses may coalesce away.
903 if (coalesceStackAccess(MI, Reg))
904 continue;
905
906 // Analyze instruction.
907 SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops;
908 MIBundleOperands::VirtRegInfo RI =
909 MIBundleOperands(*MI).analyzeVirtReg(Reg, &Ops);
910
911 // Find the slot index where this instruction reads and writes OldLI.
912 // This is usually the def slot, except for tied early clobbers.
913 SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot();
914 if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true)))
915 if (SlotIndex::isSameInstr(Idx, VNI->def))
916 Idx = VNI->def;
917
918 // Check for a sibling copy.
919 unsigned SibReg = isFullCopyOf(*MI, Reg);
920 if (SibReg && isSibling(SibReg)) {
921 // This may actually be a copy between snippets.
922 if (isRegToSpill(SibReg)) {
923 DEBUG(dbgs() << "Found new snippet copy: " << *MI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Found new snippet copy: " <<
*MI; } } while (false)
;
924 SnippetCopies.insert(MI);
925 continue;
926 }
927 if (RI.Writes) {
928 if (hoistSpillInsideBB(OldLI, *MI)) {
929 // This COPY is now dead, the value is already in the stack slot.
930 MI->getOperand(0).setIsDead();
931 DeadDefs.push_back(MI);
932 continue;
933 }
934 } else {
935 // This is a reload for a sib-reg copy. Drop spills downstream.
936 LiveInterval &SibLI = LIS.getInterval(SibReg);
937 eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx));
938 // The COPY will fold to a reload below.
939 }
940 }
941
942 // Attempt to fold memory ops.
943 if (foldMemoryOperand(Ops))
944 continue;
945
946 // Create a new virtual register for spill/fill.
947 // FIXME: Infer regclass from instruction alone.
948 unsigned NewVReg = Edit->createFrom(Reg);
949
950 if (RI.Reads)
951 insertReload(NewVReg, Idx, MI);
952
953 // Rewrite instruction operands.
954 bool hasLiveDef = false;
955 for (const auto &OpPair : Ops) {
956 MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
957 MO.setReg(NewVReg);
958 if (MO.isUse()) {
959 if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
960 MO.setIsKill();
961 } else {
962 if (!MO.isDead())
963 hasLiveDef = true;
964 }
965 }
966 DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\trewrite: " << Idx <<
'\t' << *MI << '\n'; } } while (false)
;
967
968 // FIXME: Use a second vreg if instruction has no tied ops.
969 if (RI.Writes)
970 if (hasLiveDef)
971 insertSpill(NewVReg, true, MI);
972 }
973}
974
975/// spillAll - Spill all registers remaining after rematerialization.
976void InlineSpiller::spillAll() {
977 // Update LiveStacks now that we are committed to spilling.
978 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
979 StackSlot = VRM.assignVirt2StackSlot(Original);
980 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
981 StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator());
982 } else
983 StackInt = &LSS.getInterval(StackSlot);
984
985 if (Original != Edit->getReg())
986 VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
987
988 assert(StackInt->getNumValNums() == 1 && "Bad stack interval values")((StackInt->getNumValNums() == 1 && "Bad stack interval values"
) ? static_cast<void> (0) : __assert_fail ("StackInt->getNumValNums() == 1 && \"Bad stack interval values\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 988, __PRETTY_FUNCTION__))
;
989 for (unsigned Reg : RegsToSpill)
990 StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
991 StackInt->getValNumInfo(0));
992 DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Merged spilled regs: " <<
*StackInt << '\n'; } } while (false)
;
993
994 // Spill around uses of all RegsToSpill.
995 for (unsigned Reg : RegsToSpill)
996 spillAroundUses(Reg);
997
998 // Hoisted spills may cause dead code.
999 if (!DeadDefs.empty()) {
1000 DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Eliminating " << DeadDefs
.size() << " dead defs\n"; } } while (false)
;
1001 Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
1002 }
1003
1004 // Finally delete the SnippetCopies.
1005 for (unsigned Reg : RegsToSpill) {
1006 for (MachineRegisterInfo::reg_instr_iterator
1007 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
1008 RI != E; ) {
1009 MachineInstr &MI = *(RI++);
1010 assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy")((SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy"
) ? static_cast<void> (0) : __assert_fail ("SnippetCopies.count(&MI) && \"Remaining use wasn't a snippet copy\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1010, __PRETTY_FUNCTION__))
;
1011 // FIXME: Do this with a LiveRangeEdit callback.
1012 LIS.RemoveMachineInstrFromMaps(MI);
1013 MI.eraseFromParent();
1014 }
1015 }
1016
1017 // Delete all spilled registers.
1018 for (unsigned Reg : RegsToSpill)
1019 Edit->eraseVirtReg(Reg);
1020}
1021
1022void InlineSpiller::spill(LiveRangeEdit &edit) {
1023 ++NumSpilledRanges;
1024 Edit = &edit;
1025 assert(!TargetRegisterInfo::isStackSlot(edit.getReg())((!TargetRegisterInfo::isStackSlot(edit.getReg()) && "Trying to spill a stack slot."
) ? static_cast<void> (0) : __assert_fail ("!TargetRegisterInfo::isStackSlot(edit.getReg()) && \"Trying to spill a stack slot.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1026, __PRETTY_FUNCTION__))
1026 && "Trying to spill a stack slot.")((!TargetRegisterInfo::isStackSlot(edit.getReg()) && "Trying to spill a stack slot."
) ? static_cast<void> (0) : __assert_fail ("!TargetRegisterInfo::isStackSlot(edit.getReg()) && \"Trying to spill a stack slot.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1026, __PRETTY_FUNCTION__))
;
1027 // Share a stack slot among all descendants of Original.
1028 Original = VRM.getOriginal(edit.getReg());
1029 StackSlot = VRM.getStackSlot(Original);
1030 StackInt = nullptr;
1031
1032 DEBUG(dbgs() << "Inline spilling "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
PrintReg(Original) << '\n'; } } while (false)
1033 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
PrintReg(Original) << '\n'; } } while (false)
1034 << ':' << edit.getParent()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
PrintReg(Original) << '\n'; } } while (false)
1035 << "\nFrom original " << PrintReg(Original) << '\n')do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Inline spilling " << TRI
.getRegClassName(MRI.getRegClass(edit.getReg())) << ':'
<< edit.getParent() << "\nFrom original " <<
PrintReg(Original) << '\n'; } } while (false)
;
1036 assert(edit.getParent().isSpillable() &&((edit.getParent().isSpillable() && "Attempting to spill already spilled value."
) ? static_cast<void> (0) : __assert_fail ("edit.getParent().isSpillable() && \"Attempting to spill already spilled value.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1037, __PRETTY_FUNCTION__))
1037 "Attempting to spill already spilled value.")((edit.getParent().isSpillable() && "Attempting to spill already spilled value."
) ? static_cast<void> (0) : __assert_fail ("edit.getParent().isSpillable() && \"Attempting to spill already spilled value.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1037, __PRETTY_FUNCTION__))
;
1038 assert(DeadDefs.empty() && "Previous spill didn't remove dead defs")((DeadDefs.empty() && "Previous spill didn't remove dead defs"
) ? static_cast<void> (0) : __assert_fail ("DeadDefs.empty() && \"Previous spill didn't remove dead defs\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1038, __PRETTY_FUNCTION__))
;
1039
1040 collectRegsToSpill();
1041 reMaterializeAll();
1042
1043 // Remat may handle everything.
1044 if (!RegsToSpill.empty())
1045 spillAll();
1046
1047 Edit->calculateRegClassAndHint(MF, Loops, MBFI);
1048}
1049
1050/// Optimizations after all the reg selections and spills are done.
1051///
1052void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
1053
1054/// When a spill is inserted, add the spill to MergeableSpills map.
1055///
1056void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
1057 unsigned Original) {
1058 StackSlotToReg[StackSlot] = Original;
1059 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1060 VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
1061 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1062 MergeableSpills[MIdx].insert(&Spill);
1063}
1064
1065/// When a spill is removed, remove the spill from MergeableSpills map.
1066/// Return true if the spill is removed successfully.
1067///
1068bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
1069 int StackSlot) {
1070 int Original = StackSlotToReg[StackSlot];
1071 if (!Original)
1072 return false;
1073 SlotIndex Idx = LIS.getInstructionIndex(Spill);
1074 VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
1075 std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
1076 return MergeableSpills[MIdx].erase(&Spill);
1077}
1078
1079/// Check BB to see if it is a possible target BB to place a hoisted spill,
1080/// i.e., there should be a living sibling of OrigReg at the insert point.
1081///
1082bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI,
1083 MachineBasicBlock &BB, unsigned &LiveReg) {
1084 SlotIndex Idx;
1085 LiveInterval &OrigLI = LIS.getInterval(OrigReg);
1086 MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, BB);
1087 if (MI != BB.end())
1088 Idx = LIS.getInstructionIndex(*MI);
1089 else
1090 Idx = LIS.getMBBEndIdx(&BB).getPrevSlot();
1091 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1092 assert((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI &&(((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI
&& "Unexpected VNI") ? static_cast<void> (0) :
__assert_fail ("(LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI && \"Unexpected VNI\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1093, __PRETTY_FUNCTION__))
1093 "Unexpected VNI")(((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI
&& "Unexpected VNI") ? static_cast<void> (0) :
__assert_fail ("(LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI && \"Unexpected VNI\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1093, __PRETTY_FUNCTION__))
;
1094
1095 for (auto const SibReg : Siblings) {
1096 LiveInterval &LI = LIS.getInterval(SibReg);
1097 VNInfo *VNI = LI.getVNInfoAt(Idx);
1098 if (VNI) {
1099 LiveReg = SibReg;
1100 return true;
1101 }
1102 }
1103 return false;
1104}
1105
1106/// Remove redundant spills in the same BB. Save those redundant spills in
1107/// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
1108///
1109void HoistSpillHelper::rmRedundantSpills(
1110 SmallPtrSet<MachineInstr *, 16> &Spills,
1111 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1112 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1113 // For each spill saw, check SpillBBToSpill[] and see if its BB already has
1114 // another spill inside. If a BB contains more than one spill, only keep the
1115 // earlier spill with smaller SlotIndex.
1116 for (const auto CurrentSpill : Spills) {
1117 MachineBasicBlock *Block = CurrentSpill->getParent();
1118 MachineDomTreeNode *Node = MDT.getBase().getNode(Block);
1119 MachineInstr *PrevSpill = SpillBBToSpill[Node];
1120 if (PrevSpill) {
1121 SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill);
1122 SlotIndex CIdx = LIS.getInstructionIndex(*CurrentSpill);
1123 MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill;
1124 MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill;
1125 SpillsToRm.push_back(SpillToRm);
1126 SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep;
1127 } else {
1128 SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill;
1129 }
1130 }
1131 for (const auto SpillToRm : SpillsToRm)
1132 Spills.erase(SpillToRm);
1133}
1134
1135/// Starting from \p Root find a top-down traversal order of the dominator
1136/// tree to visit all basic blocks containing the elements of \p Spills.
1137/// Redundant spills will be found and put into \p SpillsToRm at the same
1138/// time. \p SpillBBToSpill will be populated as part of the process and
1139/// maps a basic block to the first store occurring in the basic block.
1140/// \post SpillsToRm.union(Spills\@post) == Spills\@pre
1141///
1142void HoistSpillHelper::getVisitOrders(
1143 MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
1144 SmallVectorImpl<MachineDomTreeNode *> &Orders,
1145 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1146 DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
1147 DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
1148 // The set contains all the possible BB nodes to which we may hoist
1149 // original spills.
1150 SmallPtrSet<MachineDomTreeNode *, 8> WorkSet;
1151 // Save the BB nodes on the path from the first BB node containing
1152 // non-redundant spill to the Root node.
1153 SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath;
1154 // All the spills to be hoisted must originate from a single def instruction
1155 // to the OrigReg. It means the def instruction should dominate all the spills
1156 // to be hoisted. We choose the BB where the def instruction is located as
1157 // the Root.
1158 MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom();
1159 // For every node on the dominator tree with spill, walk up on the dominator
1160 // tree towards the Root node until it is reached. If there is other node
1161 // containing spill in the middle of the path, the previous spill saw will
1162 // be redundant and the node containing it will be removed. All the nodes on
1163 // the path starting from the first node with non-redundant spill to the Root
1164 // node will be added to the WorkSet, which will contain all the possible
1165 // locations where spills may be hoisted to after the loop below is done.
1166 for (const auto Spill : Spills) {
1167 MachineBasicBlock *Block = Spill->getParent();
1168 MachineDomTreeNode *Node = MDT[Block];
1169 MachineInstr *SpillToRm = nullptr;
1170 while (Node != RootIDomNode) {
1171 // If Node dominates Block, and it already contains a spill, the spill in
1172 // Block will be redundant.
1173 if (Node != MDT[Block] && SpillBBToSpill[Node]) {
1174 SpillToRm = SpillBBToSpill[MDT[Block]];
1175 break;
1176 /// If we see the Node already in WorkSet, the path from the Node to
1177 /// the Root node must already be traversed by another spill.
1178 /// Then no need to repeat.
1179 } else if (WorkSet.count(Node)) {
1180 break;
1181 } else {
1182 NodesOnPath.insert(Node);
1183 }
1184 Node = Node->getIDom();
1185 }
1186 if (SpillToRm) {
1187 SpillsToRm.push_back(SpillToRm);
1188 } else {
1189 // Add a BB containing the original spills to SpillsToKeep -- i.e.,
1190 // set the initial status before hoisting start. The value of BBs
1191 // containing original spills is set to 0, in order to descriminate
1192 // with BBs containing hoisted spills which will be inserted to
1193 // SpillsToKeep later during hoisting.
1194 SpillsToKeep[MDT[Block]] = 0;
1195 WorkSet.insert(NodesOnPath.begin(), NodesOnPath.end());
1196 }
1197 NodesOnPath.clear();
1198 }
1199
1200 // Sort the nodes in WorkSet in top-down order and save the nodes
1201 // in Orders. Orders will be used for hoisting in runHoistSpills.
1202 unsigned idx = 0;
1203 Orders.push_back(MDT.getBase().getNode(Root));
1204 do {
1205 MachineDomTreeNode *Node = Orders[idx++];
1206 const std::vector<MachineDomTreeNode *> &Children = Node->getChildren();
1207 unsigned NumChildren = Children.size();
1208 for (unsigned i = 0; i != NumChildren; ++i) {
1209 MachineDomTreeNode *Child = Children[i];
1210 if (WorkSet.count(Child))
1211 Orders.push_back(Child);
1212 }
1213 } while (idx != Orders.size());
1214 assert(Orders.size() == WorkSet.size() &&((Orders.size() == WorkSet.size() && "Orders have different size with WorkSet"
) ? static_cast<void> (0) : __assert_fail ("Orders.size() == WorkSet.size() && \"Orders have different size with WorkSet\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1215, __PRETTY_FUNCTION__))
1215 "Orders have different size with WorkSet")((Orders.size() == WorkSet.size() && "Orders have different size with WorkSet"
) ? static_cast<void> (0) : __assert_fail ("Orders.size() == WorkSet.size() && \"Orders have different size with WorkSet\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1215, __PRETTY_FUNCTION__))
;
1216
1217#ifndef NDEBUG
1218 DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "Orders size is " << Orders
.size() << "\n"; } } while (false)
;
1219 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1220 for (; RIt != Orders.rend(); RIt++)
1221 DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "BB" << (*RIt)->getBlock
()->getNumber() << ","; } } while (false)
;
1222 DEBUG(dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { dbgs() << "\n"; } } while (false)
;
1223#endif
1224}
1225
1226/// Try to hoist spills according to BB hotness. The spills to removed will
1227/// be saved in \p SpillsToRm. The spills to be inserted will be saved in
1228/// \p SpillsToIns.
1229///
1230void HoistSpillHelper::runHoistSpills(
1231 unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills,
1232 SmallVectorImpl<MachineInstr *> &SpillsToRm,
1233 DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) {
1234 // Visit order of dominator tree nodes.
1235 SmallVector<MachineDomTreeNode *, 32> Orders;
1236 // SpillsToKeep contains all the nodes where spills are to be inserted
1237 // during hoisting. If the spill to be inserted is an original spill
1238 // (not a hoisted one), the value of the map entry is 0. If the spill
1239 // is a hoisted spill, the value of the map entry is the VReg to be used
1240 // as the source of the spill.
1241 DenseMap<MachineDomTreeNode *, unsigned> SpillsToKeep;
1242 // Map from BB to the first spill inside of it.
1243 DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill;
1244
1245 rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill);
1246
1247 MachineBasicBlock *Root = LIS.getMBBFromIndex(OrigVNI.def);
1248 getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep,
1249 SpillBBToSpill);
1250
1251 // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of
1252 // nodes set and the cost of all the spills inside those nodes.
1253 // The nodes set are the locations where spills are to be inserted
1254 // in the subtree of current node.
1255 typedef std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>
1256 NodesCostPair;
1257 DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap;
1258 // Iterate Orders set in reverse order, which will be a bottom-up order
1259 // in the dominator tree. Once we visit a dom tree node, we know its
1260 // children have already been visited and the spill locations in the
1261 // subtrees of all the children have been determined.
1262 SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
1263 for (; RIt != Orders.rend(); RIt++) {
1264 MachineBasicBlock *Block = (*RIt)->getBlock();
1265
1266 // If Block contains an original spill, simply continue.
1267 if (SpillsToKeep.find(*RIt) != SpillsToKeep.end() && !SpillsToKeep[*RIt]) {
1268 SpillsInSubTreeMap[*RIt].first.insert(*RIt);
1269 // SpillsInSubTreeMap[*RIt].second contains the cost of spill.
1270 SpillsInSubTreeMap[*RIt].second = MBFI.getBlockFreq(Block);
1271 continue;
1272 }
1273
1274 // Collect spills in subtree of current node (*RIt) to
1275 // SpillsInSubTreeMap[*RIt].first.
1276 const std::vector<MachineDomTreeNode *> &Children = (*RIt)->getChildren();
1277 unsigned NumChildren = Children.size();
1278 for (unsigned i = 0; i != NumChildren; ++i) {
1279 MachineDomTreeNode *Child = Children[i];
1280 if (SpillsInSubTreeMap.find(Child) == SpillsInSubTreeMap.end())
1281 continue;
1282 // The stmt "SpillsInSubTree = SpillsInSubTreeMap[*RIt].first" below
1283 // should be placed before getting the begin and end iterators of
1284 // SpillsInSubTreeMap[Child].first, or else the iterators may be
1285 // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time
1286 // and the map grows and then the original buckets in the map are moved.
1287 SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1288 SpillsInSubTreeMap[*RIt].first;
1289 BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1290 SubTreeCost += SpillsInSubTreeMap[Child].second;
1291 auto BI = SpillsInSubTreeMap[Child].first.begin();
1292 auto EI = SpillsInSubTreeMap[Child].first.end();
1293 SpillsInSubTree.insert(BI, EI);
1294 SpillsInSubTreeMap.erase(Child);
1295 }
1296
1297 SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree =
1298 SpillsInSubTreeMap[*RIt].first;
1299 BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second;
1300 // No spills in subtree, simply continue.
1301 if (SpillsInSubTree.empty())
1302 continue;
1303
1304 // Check whether Block is a possible candidate to insert spill.
1305 unsigned LiveReg = 0;
1306 if (!isSpillCandBB(OrigReg, OrigVNI, *Block, LiveReg))
1307 continue;
1308
1309 // If there are multiple spills that could be merged, bias a little
1310 // to hoist the spill.
1311 BranchProbability MarginProb = (SpillsInSubTree.size() > 1)
1312 ? BranchProbability(9, 10)
1313 : BranchProbability(1, 1);
1314 if (SubTreeCost > MBFI.getBlockFreq(Block) * MarginProb) {
1315 // Hoist: Move spills to current Block.
1316 for (const auto SpillBB : SpillsInSubTree) {
1317 // When SpillBB is a BB contains original spill, insert the spill
1318 // to SpillsToRm.
1319 if (SpillsToKeep.find(SpillBB) != SpillsToKeep.end() &&
1320 !SpillsToKeep[SpillBB]) {
1321 MachineInstr *SpillToRm = SpillBBToSpill[SpillBB];
1322 SpillsToRm.push_back(SpillToRm);
1323 }
1324 // SpillBB will not contain spill anymore, remove it from SpillsToKeep.
1325 SpillsToKeep.erase(SpillBB);
1326 }
1327 // Current Block is the BB containing the new hoisted spill. Add it to
1328 // SpillsToKeep. LiveReg is the source of the new spill.
1329 SpillsToKeep[*RIt] = LiveReg;
1330 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1331 dbgs() << "spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1332 for (const auto Rspill : SpillsInSubTree)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1333 dbgs() << Rspill->getBlock()->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1334 dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1335 << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
1336 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "spills in BB: "; for (const
auto Rspill : SpillsInSubTree) dbgs() << Rspill->getBlock
()->getNumber() << " "; dbgs() << "were promoted to BB"
<< (*RIt)->getBlock()->getNumber() << "\n"
; }; } } while (false)
;
1337 SpillsInSubTree.clear();
1338 SpillsInSubTree.insert(*RIt);
1339 SubTreeCost = MBFI.getBlockFreq(Block);
1340 }
1341 }
1342 // For spills in SpillsToKeep with LiveReg set (i.e., not original spill),
1343 // save them to SpillsToIns.
1344 for (const auto Ent : SpillsToKeep) {
1345 if (Ent.second)
1346 SpillsToIns[Ent.first->getBlock()] = Ent.second;
1347 }
1348}
1349
1350/// For spills with equal values, remove redundant spills and hoist those left
1351/// to less hot spots.
1352///
1353/// Spills with equal values will be collected into the same set in
1354/// MergeableSpills when spill is inserted. These equal spills are originated
1355/// from the same defining instruction and are dominated by the instruction.
1356/// Before hoisting all the equal spills, redundant spills inside in the same
1357/// BB are first marked to be deleted. Then starting from the spills left, walk
1358/// up on the dominator tree towards the Root node where the define instruction
1359/// is located, mark the dominated spills to be deleted along the way and
1360/// collect the BB nodes on the path from non-dominated spills to the define
1361/// instruction into a WorkSet. The nodes in WorkSet are the candidate places
1362/// where we are considering to hoist the spills. We iterate the WorkSet in
1363/// bottom-up order, and for each node, we will decide whether to hoist spills
1364/// inside its subtree to that node. In this way, we can get benefit locally
1365/// even if hoisting all the equal spills to one cold place is impossible.
1366///
1367void HoistSpillHelper::hoistAllSpills() {
1368 SmallVector<unsigned, 4> NewVRegs;
1369 LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
1370
1371 // Save the mapping between stackslot and its original reg.
1372 DenseMap<int, unsigned> SlotToOrigReg;
1373 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
1374 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
1375 int Slot = VRM.getStackSlot(Reg);
1376 if (Slot != VirtRegMap::NO_STACK_SLOT)
1377 SlotToOrigReg[Slot] = VRM.getOriginal(Reg);
1378 unsigned Original = VRM.getPreSplitReg(Reg);
1379 if (!MRI.def_empty(Reg))
1380 Virt2SiblingsMap[Original].insert(Reg);
1381 }
1382
1383 // Each entry in MergeableSpills contains a spill set with equal values.
1384 for (auto &Ent : MergeableSpills) {
1385 int Slot = Ent.first.first;
1386 unsigned OrigReg = SlotToOrigReg[Slot];
1387 LiveInterval &OrigLI = LIS.getInterval(OrigReg);
1388 VNInfo *OrigVNI = Ent.first.second;
1389 SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
1390 if (Ent.second.empty())
1391 continue;
1392
1393 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1394 dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1395 << "Equal spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1396 for (const auto spill : EqValSpills)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1397 dbgs() << spill->getParent()->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1398 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
1399 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "\nFor Slot" << Slot <<
" and VN" << OrigVNI->id << ":\n" << "Equal spills in BB: "
; for (const auto spill : EqValSpills) dbgs() << spill->
getParent()->getNumber() << " "; dbgs() << "\n"
; }; } } while (false)
;
1400
1401 // SpillsToRm is the spill set to be removed from EqValSpills.
1402 SmallVector<MachineInstr *, 16> SpillsToRm;
1403 // SpillsToIns is the spill set to be newly inserted after hoisting.
1404 DenseMap<MachineBasicBlock *, unsigned> SpillsToIns;
1405
1406 runHoistSpills(OrigReg, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);
1407
1408 DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1409 dbgs() << "Finally inserted spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1410 for (const auto Ispill : SpillsToIns)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1411 dbgs() << Ispill.first->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1412 dbgs() << "\nFinally removed spills in BB: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1413 for (const auto Rspill : SpillsToRm)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1414 dbgs() << Rspill->getParent()->getNumber() << " ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1415 dbgs() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
1416 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("regalloc")) { { dbgs() << "Finally inserted spills in BB: "
; for (const auto Ispill : SpillsToIns) dbgs() << Ispill
.first->getNumber() << " "; dbgs() << "\nFinally removed spills in BB: "
; for (const auto Rspill : SpillsToRm) dbgs() << Rspill
->getParent()->getNumber() << " "; dbgs() <<
"\n"; }; } } while (false)
;
1417
1418 // Stack live range update.
1419 LiveInterval &StackIntvl = LSS.getInterval(Slot);
1420 if (!SpillsToIns.empty() || !SpillsToRm.empty())
1421 StackIntvl.MergeValueInAsValue(OrigLI, OrigVNI,
1422 StackIntvl.getValNumInfo(0));
1423
1424 // Insert hoisted spills.
1425 for (auto const Insert : SpillsToIns) {
1426 MachineBasicBlock *BB = Insert.first;
1427 unsigned LiveReg = Insert.second;
1428 MachineBasicBlock::iterator MI = IPA.getLastInsertPointIter(OrigLI, *BB);
1429 TII.storeRegToStackSlot(*BB, MI, LiveReg, false, Slot,
1430 MRI.getRegClass(LiveReg), &TRI);
1431 LIS.InsertMachineInstrRangeInMaps(std::prev(MI), MI);
1432 ++NumSpills;
1433 }
1434
1435 // Remove redundant spills or change them to dead instructions.
1436 NumSpills -= SpillsToRm.size();
1437 for (auto const RMEnt : SpillsToRm) {
1438 RMEnt->setDesc(TII.get(TargetOpcode::KILL));
1439 for (unsigned i = RMEnt->getNumOperands(); i; --i) {
1440 MachineOperand &MO = RMEnt->getOperand(i - 1);
1441 if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead())
1442 RMEnt->RemoveOperand(i - 1);
1443 }
1444 }
1445 Edit.eliminateDeadDefs(SpillsToRm, None, AA);
1446 }
1447}
1448
1449/// For VirtReg clone, the \p New register should have the same physreg or
1450/// stackslot as the \p old register.
1451void HoistSpillHelper::LRE_DidCloneVirtReg(unsigned New, unsigned Old) {
1452 if (VRM.hasPhys(Old))
1453 VRM.assignVirt2Phys(New, VRM.getPhys(Old));
1454 else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT)
1455 VRM.assignVirt2StackSlot(New, VRM.getStackSlot(Old));
1456 else
1457 llvm_unreachable("VReg should be assigned either physreg or stackslot")::llvm::llvm_unreachable_internal("VReg should be assigned either physreg or stackslot"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/lib/CodeGen/InlineSpiller.cpp"
, 1457)
;
1458}