Bug Summary

File:lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Warning:line 1694, column 7
Value stored to 'MadeChange' is never read

Annotated Source Code

1//===- InstCombineSimplifyDemanded.cpp ------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains logic for simplifying instructions based on information
11// about how they are used.
12//
13//===----------------------------------------------------------------------===//
14
15#include "InstCombineInternal.h"
16#include "llvm/Analysis/ValueTracking.h"
17#include "llvm/IR/IntrinsicInst.h"
18#include "llvm/IR/PatternMatch.h"
19#include "llvm/Support/KnownBits.h"
20
21using namespace llvm;
22using namespace llvm::PatternMatch;
23
24#define DEBUG_TYPE"instcombine" "instcombine"
25
26/// Check to see if the specified operand of the specified instruction is a
27/// constant integer. If so, check to see if there are any bits set in the
28/// constant that are not demanded. If so, shrink the constant and return true.
29static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
30 const APInt &Demanded) {
31 assert(I && "No instruction?")((I && "No instruction?") ? static_cast<void> (
0) : __assert_fail ("I && \"No instruction?\"", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 31, __PRETTY_FUNCTION__))
;
32 assert(OpNo < I->getNumOperands() && "Operand index too large")((OpNo < I->getNumOperands() && "Operand index too large"
) ? static_cast<void> (0) : __assert_fail ("OpNo < I->getNumOperands() && \"Operand index too large\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 32, __PRETTY_FUNCTION__))
;
33
34 // The operand must be a constant integer or splat integer.
35 Value *Op = I->getOperand(OpNo);
36 const APInt *C;
37 if (!match(Op, m_APInt(C)))
38 return false;
39
40 // If there are no bits set that aren't demanded, nothing to do.
41 if (C->isSubsetOf(Demanded))
42 return false;
43
44 // This instruction is producing bits that are not demanded. Shrink the RHS.
45 I->setOperand(OpNo, ConstantInt::get(Op->getType(), *C & Demanded));
46
47 return true;
48}
49
50
51
52/// Inst is an integer instruction that SimplifyDemandedBits knows about. See if
53/// the instruction has any properties that allow us to simplify its operands.
54bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) {
55 unsigned BitWidth = Inst.getType()->getScalarSizeInBits();
56 KnownBits Known(BitWidth);
57 APInt DemandedMask(APInt::getAllOnesValue(BitWidth));
58
59 Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, Known,
60 0, &Inst);
61 if (!V) return false;
62 if (V == &Inst) return true;
63 replaceInstUsesWith(Inst, V);
64 return true;
65}
66
67/// This form of SimplifyDemandedBits simplifies the specified instruction
68/// operand if possible, updating it in place. It returns true if it made any
69/// change and false otherwise.
70bool InstCombiner::SimplifyDemandedBits(Instruction *I, unsigned OpNo,
71 const APInt &DemandedMask,
72 KnownBits &Known,
73 unsigned Depth) {
74 Use &U = I->getOperandUse(OpNo);
75 Value *NewVal = SimplifyDemandedUseBits(U.get(), DemandedMask, Known,
76 Depth, I);
77 if (!NewVal) return false;
78 U = NewVal;
79 return true;
80}
81
82
83/// This function attempts to replace V with a simpler value based on the
84/// demanded bits. When this function is called, it is known that only the bits
85/// set in DemandedMask of the result of V are ever used downstream.
86/// Consequently, depending on the mask and V, it may be possible to replace V
87/// with a constant or one of its operands. In such cases, this function does
88/// the replacement and returns true. In all other cases, it returns false after
89/// analyzing the expression and setting KnownOne and known to be one in the
90/// expression. Known.Zero contains all the bits that are known to be zero in
91/// the expression. These are provided to potentially allow the caller (which
92/// might recursively be SimplifyDemandedBits itself) to simplify the
93/// expression.
94/// Known.One and Known.Zero always follow the invariant that:
95/// Known.One & Known.Zero == 0.
96/// That is, a bit can't be both 1 and 0. Note that the bits in Known.One and
97/// Known.Zero may only be accurate for those bits set in DemandedMask. Note
98/// also that the bitwidth of V, DemandedMask, Known.Zero and Known.One must all
99/// be the same.
100///
101/// This returns null if it did not change anything and it permits no
102/// simplification. This returns V itself if it did some simplification of V's
103/// operands based on the information about what bits are demanded. This returns
104/// some other non-null value if it found out that V is equal to another value
105/// in the context where the specified bits are demanded, but not for all users.
106Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
107 KnownBits &Known, unsigned Depth,
108 Instruction *CxtI) {
109 assert(V != nullptr && "Null pointer of Value???")((V != nullptr && "Null pointer of Value???") ? static_cast
<void> (0) : __assert_fail ("V != nullptr && \"Null pointer of Value???\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 109, __PRETTY_FUNCTION__))
;
110 assert(Depth <= 6 && "Limit Search Depth")((Depth <= 6 && "Limit Search Depth") ? static_cast
<void> (0) : __assert_fail ("Depth <= 6 && \"Limit Search Depth\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 110, __PRETTY_FUNCTION__))
;
111 uint32_t BitWidth = DemandedMask.getBitWidth();
112 Type *VTy = V->getType();
113 assert((((!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits
() == BitWidth) && Known.getBitWidth() == BitWidth &&
"Value *V, DemandedMask and Known must have same BitWidth") ?
static_cast<void> (0) : __assert_fail ("(!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) && Known.getBitWidth() == BitWidth && \"Value *V, DemandedMask and Known must have same BitWidth\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 116, __PRETTY_FUNCTION__))
114 (!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) &&(((!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits
() == BitWidth) && Known.getBitWidth() == BitWidth &&
"Value *V, DemandedMask and Known must have same BitWidth") ?
static_cast<void> (0) : __assert_fail ("(!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) && Known.getBitWidth() == BitWidth && \"Value *V, DemandedMask and Known must have same BitWidth\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 116, __PRETTY_FUNCTION__))
115 Known.getBitWidth() == BitWidth &&(((!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits
() == BitWidth) && Known.getBitWidth() == BitWidth &&
"Value *V, DemandedMask and Known must have same BitWidth") ?
static_cast<void> (0) : __assert_fail ("(!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) && Known.getBitWidth() == BitWidth && \"Value *V, DemandedMask and Known must have same BitWidth\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 116, __PRETTY_FUNCTION__))
116 "Value *V, DemandedMask and Known must have same BitWidth")(((!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits
() == BitWidth) && Known.getBitWidth() == BitWidth &&
"Value *V, DemandedMask and Known must have same BitWidth") ?
static_cast<void> (0) : __assert_fail ("(!VTy->isIntOrIntVectorTy() || VTy->getScalarSizeInBits() == BitWidth) && Known.getBitWidth() == BitWidth && \"Value *V, DemandedMask and Known must have same BitWidth\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 116, __PRETTY_FUNCTION__))
;
117
118 if (isa<Constant>(V)) {
119 computeKnownBits(V, Known, Depth, CxtI);
120 return nullptr;
121 }
122
123 Known.Zero.clearAllBits();
124 Known.One.clearAllBits();
125 if (DemandedMask == 0) // Not demanding any bits from V.
126 return UndefValue::get(VTy);
127
128 if (Depth == 6) // Limit search depth.
129 return nullptr;
130
131 Instruction *I = dyn_cast<Instruction>(V);
132 if (!I) {
133 computeKnownBits(V, Known, Depth, CxtI);
134 return nullptr; // Only analyze instructions.
135 }
136
137 // If there are multiple uses of this value and we aren't at the root, then
138 // we can't do any simplifications of the operands, because DemandedMask
139 // only reflects the bits demanded by *one* of the users.
140 if (Depth != 0 && !I->hasOneUse())
141 return SimplifyMultipleUseDemandedBits(I, DemandedMask, Known, Depth, CxtI);
142
143 KnownBits LHSKnown(BitWidth), RHSKnown(BitWidth);
144
145 // If this is the root being simplified, allow it to have multiple uses,
146 // just set the DemandedMask to all bits so that we can try to simplify the
147 // operands. This allows visitTruncInst (for example) to simplify the
148 // operand of a trunc without duplicating all the logic below.
149 if (Depth == 0 && !V->hasOneUse())
150 DemandedMask.setAllBits();
151
152 switch (I->getOpcode()) {
153 default:
154 computeKnownBits(I, Known, Depth, CxtI);
155 break;
156 case Instruction::And: {
157 // If either the LHS or the RHS are Zero, the result is zero.
158 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
159 SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.Zero, LHSKnown,
160 Depth + 1))
161 return I;
162 assert(!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?")((!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(RHSKnown.Zero & RHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 162, __PRETTY_FUNCTION__))
;
163 assert(!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?")((!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(LHSKnown.Zero & LHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 163, __PRETTY_FUNCTION__))
;
164
165 // Output known-0 are known to be clear if zero in either the LHS | RHS.
166 APInt IKnownZero = RHSKnown.Zero | LHSKnown.Zero;
167 // Output known-1 bits are only known if set in both the LHS & RHS.
168 APInt IKnownOne = RHSKnown.One & LHSKnown.One;
169
170 // If the client is only demanding bits that we know, return the known
171 // constant.
172 if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
173 return Constant::getIntegerValue(VTy, IKnownOne);
174
175 // If all of the demanded bits are known 1 on one side, return the other.
176 // These bits cannot contribute to the result of the 'and'.
177 if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
178 return I->getOperand(0);
179 if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
180 return I->getOperand(1);
181
182 // If the RHS is a constant, see if we can simplify it.
183 if (ShrinkDemandedConstant(I, 1, DemandedMask & ~LHSKnown.Zero))
184 return I;
185
186 Known.Zero = std::move(IKnownZero);
187 Known.One = std::move(IKnownOne);
188 break;
189 }
190 case Instruction::Or: {
191 // If either the LHS or the RHS are One, the result is One.
192 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
193 SimplifyDemandedBits(I, 0, DemandedMask & ~RHSKnown.One, LHSKnown,
194 Depth + 1))
195 return I;
196 assert(!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?")((!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(RHSKnown.Zero & RHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 196, __PRETTY_FUNCTION__))
;
197 assert(!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?")((!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(LHSKnown.Zero & LHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 197, __PRETTY_FUNCTION__))
;
198
199 // Output known-0 bits are only known if clear in both the LHS & RHS.
200 APInt IKnownZero = RHSKnown.Zero & LHSKnown.Zero;
201 // Output known-1 are known. to be set if s.et in either the LHS | RHS.
202 APInt IKnownOne = RHSKnown.One | LHSKnown.One;
203
204 // If the client is only demanding bits that we know, return the known
205 // constant.
206 if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
207 return Constant::getIntegerValue(VTy, IKnownOne);
208
209 // If all of the demanded bits are known zero on one side, return the other.
210 // These bits cannot contribute to the result of the 'or'.
211 if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
212 return I->getOperand(0);
213 if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
214 return I->getOperand(1);
215
216 // If the RHS is a constant, see if we can simplify it.
217 if (ShrinkDemandedConstant(I, 1, DemandedMask))
218 return I;
219
220 Known.Zero = std::move(IKnownZero);
221 Known.One = std::move(IKnownOne);
222 break;
223 }
224 case Instruction::Xor: {
225 if (SimplifyDemandedBits(I, 1, DemandedMask, RHSKnown, Depth + 1) ||
226 SimplifyDemandedBits(I, 0, DemandedMask, LHSKnown, Depth + 1))
227 return I;
228 assert(!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?")((!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(RHSKnown.Zero & RHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 228, __PRETTY_FUNCTION__))
;
229 assert(!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?")((!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(LHSKnown.Zero & LHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 229, __PRETTY_FUNCTION__))
;
230
231 // Output known-0 bits are known if clear or set in both the LHS & RHS.
232 APInt IKnownZero = (RHSKnown.Zero & LHSKnown.Zero) |
233 (RHSKnown.One & LHSKnown.One);
234 // Output known-1 are known to be set if set in only one of the LHS, RHS.
235 APInt IKnownOne = (RHSKnown.Zero & LHSKnown.One) |
236 (RHSKnown.One & LHSKnown.Zero);
237
238 // If the client is only demanding bits that we know, return the known
239 // constant.
240 if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
241 return Constant::getIntegerValue(VTy, IKnownOne);
242
243 // If all of the demanded bits are known zero on one side, return the other.
244 // These bits cannot contribute to the result of the 'xor'.
245 if (DemandedMask.isSubsetOf(RHSKnown.Zero))
246 return I->getOperand(0);
247 if (DemandedMask.isSubsetOf(LHSKnown.Zero))
248 return I->getOperand(1);
249
250 // If all of the demanded bits are known to be zero on one side or the
251 // other, turn this into an *inclusive* or.
252 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
253 if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.Zero)) {
254 Instruction *Or =
255 BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1),
256 I->getName());
257 return InsertNewInstWith(Or, *I);
258 }
259
260 // If all of the demanded bits on one side are known, and all of the set
261 // bits on that side are also known to be set on the other side, turn this
262 // into an AND, as we know the bits will be cleared.
263 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
264 if (DemandedMask.isSubsetOf(RHSKnown.Zero|RHSKnown.One) &&
265 RHSKnown.One.isSubsetOf(LHSKnown.One)) {
266 Constant *AndC = Constant::getIntegerValue(VTy,
267 ~RHSKnown.One & DemandedMask);
268 Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
269 return InsertNewInstWith(And, *I);
270 }
271
272 // If the RHS is a constant, see if we can simplify it.
273 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
274 if (ShrinkDemandedConstant(I, 1, DemandedMask))
275 return I;
276
277 // If our LHS is an 'and' and if it has one use, and if any of the bits we
278 // are flipping are known to be set, then the xor is just resetting those
279 // bits to zero. We can just knock out bits from the 'and' and the 'xor',
280 // simplifying both of them.
281 if (Instruction *LHSInst = dyn_cast<Instruction>(I->getOperand(0)))
282 if (LHSInst->getOpcode() == Instruction::And && LHSInst->hasOneUse() &&
283 isa<ConstantInt>(I->getOperand(1)) &&
284 isa<ConstantInt>(LHSInst->getOperand(1)) &&
285 (LHSKnown.One & RHSKnown.One & DemandedMask) != 0) {
286 ConstantInt *AndRHS = cast<ConstantInt>(LHSInst->getOperand(1));
287 ConstantInt *XorRHS = cast<ConstantInt>(I->getOperand(1));
288 APInt NewMask = ~(LHSKnown.One & RHSKnown.One & DemandedMask);
289
290 Constant *AndC =
291 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
292 Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC);
293 InsertNewInstWith(NewAnd, *I);
294
295 Constant *XorC =
296 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
297 Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC);
298 return InsertNewInstWith(NewXor, *I);
299 }
300
301 // Output known-0 bits are known if clear or set in both the LHS & RHS.
302 Known.Zero = std::move(IKnownZero);
303 // Output known-1 are known to be set if set in only one of the LHS, RHS.
304 Known.One = std::move(IKnownOne);
305 break;
306 }
307 case Instruction::Select:
308 // If this is a select as part of a min/max pattern, don't simplify any
309 // further in case we break the structure.
310 Value *LHS, *RHS;
311 if (matchSelectPattern(I, LHS, RHS).Flavor != SPF_UNKNOWN)
312 return nullptr;
313
314 if (SimplifyDemandedBits(I, 2, DemandedMask, RHSKnown, Depth + 1) ||
315 SimplifyDemandedBits(I, 1, DemandedMask, LHSKnown, Depth + 1))
316 return I;
317 assert(!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?")((!(RHSKnown.Zero & RHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(RHSKnown.Zero & RHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 317, __PRETTY_FUNCTION__))
;
318 assert(!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?")((!(LHSKnown.Zero & LHSKnown.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(LHSKnown.Zero & LHSKnown.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 318, __PRETTY_FUNCTION__))
;
319
320 // If the operands are constants, see if we can simplify them.
321 if (ShrinkDemandedConstant(I, 1, DemandedMask) ||
322 ShrinkDemandedConstant(I, 2, DemandedMask))
323 return I;
324
325 // Only known if known in both the LHS and RHS.
326 Known.One = RHSKnown.One & LHSKnown.One;
327 Known.Zero = RHSKnown.Zero & LHSKnown.Zero;
328 break;
329 case Instruction::Trunc: {
330 unsigned truncBf = I->getOperand(0)->getType()->getScalarSizeInBits();
331 DemandedMask = DemandedMask.zext(truncBf);
332 Known.Zero = Known.Zero.zext(truncBf);
333 Known.One = Known.One.zext(truncBf);
334 if (SimplifyDemandedBits(I, 0, DemandedMask, Known, Depth + 1))
335 return I;
336 DemandedMask = DemandedMask.trunc(BitWidth);
337 Known.Zero = Known.Zero.trunc(BitWidth);
338 Known.One = Known.One.trunc(BitWidth);
339 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 339, __PRETTY_FUNCTION__))
;
340 break;
341 }
342 case Instruction::BitCast:
343 if (!I->getOperand(0)->getType()->isIntOrIntVectorTy())
344 return nullptr; // vector->int or fp->int?
345
346 if (VectorType *DstVTy = dyn_cast<VectorType>(I->getType())) {
347 if (VectorType *SrcVTy =
348 dyn_cast<VectorType>(I->getOperand(0)->getType())) {
349 if (DstVTy->getNumElements() != SrcVTy->getNumElements())
350 // Don't touch a bitcast between vectors of different element counts.
351 return nullptr;
352 } else
353 // Don't touch a scalar-to-vector bitcast.
354 return nullptr;
355 } else if (I->getOperand(0)->getType()->isVectorTy())
356 // Don't touch a vector-to-scalar bitcast.
357 return nullptr;
358
359 if (SimplifyDemandedBits(I, 0, DemandedMask, Known, Depth + 1))
360 return I;
361 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 361, __PRETTY_FUNCTION__))
;
362 break;
363 case Instruction::ZExt: {
364 // Compute the bits in the result that are not present in the input.
365 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
366
367 DemandedMask = DemandedMask.trunc(SrcBitWidth);
368 Known.Zero = Known.Zero.trunc(SrcBitWidth);
369 Known.One = Known.One.trunc(SrcBitWidth);
370 if (SimplifyDemandedBits(I, 0, DemandedMask, Known, Depth + 1))
371 return I;
372 DemandedMask = DemandedMask.zext(BitWidth);
373 Known.Zero = Known.Zero.zext(BitWidth);
374 Known.One = Known.One.zext(BitWidth);
375 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 375, __PRETTY_FUNCTION__))
;
376 // The top bits are known to be zero.
377 Known.Zero.setBitsFrom(SrcBitWidth);
378 break;
379 }
380 case Instruction::SExt: {
381 // Compute the bits in the result that are not present in the input.
382 unsigned SrcBitWidth =I->getOperand(0)->getType()->getScalarSizeInBits();
383
384 APInt InputDemandedBits = DemandedMask &
385 APInt::getLowBitsSet(BitWidth, SrcBitWidth);
386
387 APInt NewBits(APInt::getBitsSetFrom(BitWidth, SrcBitWidth));
388 // If any of the sign extended bits are demanded, we know that the sign
389 // bit is demanded.
390 if ((NewBits & DemandedMask) != 0)
391 InputDemandedBits.setBit(SrcBitWidth-1);
392
393 InputDemandedBits = InputDemandedBits.trunc(SrcBitWidth);
394 Known.Zero = Known.Zero.trunc(SrcBitWidth);
395 Known.One = Known.One.trunc(SrcBitWidth);
396 if (SimplifyDemandedBits(I, 0, InputDemandedBits, Known, Depth + 1))
397 return I;
398 InputDemandedBits = InputDemandedBits.zext(BitWidth);
399 Known.Zero = Known.Zero.zext(BitWidth);
400 Known.One = Known.One.zext(BitWidth);
401 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 401, __PRETTY_FUNCTION__))
;
402
403 // If the sign bit of the input is known set or clear, then we know the
404 // top bits of the result.
405
406 // If the input sign bit is known zero, or if the NewBits are not demanded
407 // convert this into a zero extension.
408 if (Known.Zero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) {
409 // Convert to ZExt cast
410 CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName());
411 return InsertNewInstWith(NewCast, *I);
412 } else if (Known.One[SrcBitWidth-1]) { // Input sign bit known set
413 Known.One |= NewBits;
414 }
415 break;
416 }
417 case Instruction::Add:
418 case Instruction::Sub: {
419 /// If the high-bits of an ADD/SUB are not demanded, then we do not care
420 /// about the high bits of the operands.
421 unsigned NLZ = DemandedMask.countLeadingZeros();
422 if (NLZ > 0) {
423 // Right fill the mask of bits for this ADD/SUB to demand the most
424 // significant bit and all those below it.
425 APInt DemandedFromOps(APInt::getLowBitsSet(BitWidth, BitWidth-NLZ));
426 if (ShrinkDemandedConstant(I, 0, DemandedFromOps) ||
427 SimplifyDemandedBits(I, 0, DemandedFromOps, LHSKnown, Depth + 1) ||
428 ShrinkDemandedConstant(I, 1, DemandedFromOps) ||
429 SimplifyDemandedBits(I, 1, DemandedFromOps, RHSKnown, Depth + 1)) {
430 // Disable the nsw and nuw flags here: We can no longer guarantee that
431 // we won't wrap after simplification. Removing the nsw/nuw flags is
432 // legal here because the top bit is not demanded.
433 BinaryOperator &BinOP = *cast<BinaryOperator>(I);
434 BinOP.setHasNoSignedWrap(false);
435 BinOP.setHasNoUnsignedWrap(false);
436 return I;
437 }
438
439 // If we are known to be adding/subtracting zeros to every bit below
440 // the highest demanded bit, we just return the other side.
441 if (DemandedFromOps.isSubsetOf(RHSKnown.Zero))
442 return I->getOperand(0);
443 // We can't do this with the LHS for subtraction.
444 if (I->getOpcode() == Instruction::Add &&
445 DemandedFromOps.isSubsetOf(LHSKnown.Zero))
446 return I->getOperand(1);
447 }
448
449 // Otherwise just hand the add/sub off to computeKnownBits to fill in
450 // the known zeros and ones.
451 computeKnownBits(V, Known, Depth, CxtI);
452 break;
453 }
454 case Instruction::Shl: {
455 const APInt *SA;
456 if (match(I->getOperand(1), m_APInt(SA))) {
457 const APInt *ShrAmt;
458 if (match(I->getOperand(0), m_Shr(m_Value(), m_APInt(ShrAmt)))) {
459 Instruction *Shr = cast<Instruction>(I->getOperand(0));
460 if (Value *R = simplifyShrShlDemandedBits(
461 Shr, *ShrAmt, I, *SA, DemandedMask, Known))
462 return R;
463 }
464
465 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
466 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
467
468 // If the shift is NUW/NSW, then it does demand the high bits.
469 ShlOperator *IOp = cast<ShlOperator>(I);
470 if (IOp->hasNoSignedWrap())
471 DemandedMaskIn.setHighBits(ShiftAmt+1);
472 else if (IOp->hasNoUnsignedWrap())
473 DemandedMaskIn.setHighBits(ShiftAmt);
474
475 if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
476 return I;
477 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 477, __PRETTY_FUNCTION__))
;
478 Known.Zero <<= ShiftAmt;
479 Known.One <<= ShiftAmt;
480 // low bits known zero.
481 if (ShiftAmt)
482 Known.Zero.setLowBits(ShiftAmt);
483 }
484 break;
485 }
486 case Instruction::LShr: {
487 const APInt *SA;
488 if (match(I->getOperand(1), m_APInt(SA))) {
489 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
490
491 // Unsigned shift right.
492 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
493
494 // If the shift is exact, then it does demand the low bits (and knows that
495 // they are zero).
496 if (cast<LShrOperator>(I)->isExact())
497 DemandedMaskIn.setLowBits(ShiftAmt);
498
499 if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
500 return I;
501 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 501, __PRETTY_FUNCTION__))
;
502 Known.Zero.lshrInPlace(ShiftAmt);
503 Known.One.lshrInPlace(ShiftAmt);
504 if (ShiftAmt)
505 Known.Zero.setHighBits(ShiftAmt); // high bits known zero.
506 }
507 break;
508 }
509 case Instruction::AShr: {
510 // If this is an arithmetic shift right and only the low-bit is set, we can
511 // always convert this into a logical shr, even if the shift amount is
512 // variable. The low bit of the shift cannot be an input sign bit unless
513 // the shift amount is >= the size of the datatype, which is undefined.
514 if (DemandedMask == 1) {
515 // Perform the logical shift right.
516 Instruction *NewVal = BinaryOperator::CreateLShr(
517 I->getOperand(0), I->getOperand(1), I->getName());
518 return InsertNewInstWith(NewVal, *I);
519 }
520
521 // If the sign bit is the only bit demanded by this ashr, then there is no
522 // need to do it, the shift doesn't change the high bit.
523 if (DemandedMask.isSignMask())
524 return I->getOperand(0);
525
526 const APInt *SA;
527 if (match(I->getOperand(1), m_APInt(SA))) {
528 uint32_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
529
530 // Signed shift right.
531 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
532 // If any of the high bits are demanded, we should set the sign bit as
533 // demanded.
534 if (DemandedMask.countLeadingZeros() <= ShiftAmt)
535 DemandedMaskIn.setSignBit();
536
537 // If the shift is exact, then it does demand the low bits (and knows that
538 // they are zero).
539 if (cast<AShrOperator>(I)->isExact())
540 DemandedMaskIn.setLowBits(ShiftAmt);
541
542 if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1))
543 return I;
544
545 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 545, __PRETTY_FUNCTION__))
;
546 // Compute the new bits that are at the top now.
547 APInt HighBits(APInt::getHighBitsSet(BitWidth, ShiftAmt));
548 Known.Zero.lshrInPlace(ShiftAmt);
549 Known.One.lshrInPlace(ShiftAmt);
550
551 // Handle the sign bits.
552 APInt SignMask(APInt::getSignMask(BitWidth));
553 // Adjust to where it is now in the mask.
554 SignMask.lshrInPlace(ShiftAmt);
555
556 // If the input sign bit is known to be zero, or if none of the top bits
557 // are demanded, turn this into an unsigned shift right.
558 if (BitWidth <= ShiftAmt || Known.Zero[BitWidth-ShiftAmt-1] ||
559 !DemandedMask.intersects(HighBits)) {
560 BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
561 I->getOperand(1));
562 LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
563 return InsertNewInstWith(LShr, *I);
564 } else if (Known.One.intersects(SignMask)) { // New bits are known one.
565 Known.One |= HighBits;
566 }
567 }
568 break;
569 }
570 case Instruction::SRem:
571 if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {
572 // X % -1 demands all the bits because we don't want to introduce
573 // INT_MIN % -1 (== undef) by accident.
574 if (Rem->isAllOnesValue())
575 break;
576 APInt RA = Rem->getValue().abs();
577 if (RA.isPowerOf2()) {
578 if (DemandedMask.ult(RA)) // srem won't affect demanded bits
579 return I->getOperand(0);
580
581 APInt LowBits = RA - 1;
582 APInt Mask2 = LowBits | APInt::getSignMask(BitWidth);
583 if (SimplifyDemandedBits(I, 0, Mask2, LHSKnown, Depth + 1))
584 return I;
585
586 // The low bits of LHS are unchanged by the srem.
587 Known.Zero = LHSKnown.Zero & LowBits;
588 Known.One = LHSKnown.One & LowBits;
589
590 // If LHS is non-negative or has all low bits zero, then the upper bits
591 // are all zero.
592 if (LHSKnown.isNonNegative() || LowBits.isSubsetOf(LHSKnown.Zero))
593 Known.Zero |= ~LowBits;
594
595 // If LHS is negative and not all low bits are zero, then the upper bits
596 // are all one.
597 if (LHSKnown.isNegative() && LowBits.intersects(LHSKnown.One))
598 Known.One |= ~LowBits;
599
600 assert(!(Known.Zero & Known.One) && "Bits known to be one AND zero?")((!(Known.Zero & Known.One) && "Bits known to be one AND zero?"
) ? static_cast<void> (0) : __assert_fail ("!(Known.Zero & Known.One) && \"Bits known to be one AND zero?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 600, __PRETTY_FUNCTION__))
;
601 break;
602 }
603 }
604
605 // The sign bit is the LHS's sign bit, except when the result of the
606 // remainder is zero.
607 if (DemandedMask.isSignBitSet()) {
608 computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1, CxtI);
609 // If it's known zero, our sign bit is also zero.
610 if (LHSKnown.isNonNegative())
611 Known.makeNonNegative();
612 }
613 break;
614 case Instruction::URem: {
615 KnownBits Known2(BitWidth);
616 APInt AllOnes = APInt::getAllOnesValue(BitWidth);
617 if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) ||
618 SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1))
619 return I;
620
621 unsigned Leaders = Known2.Zero.countLeadingOnes();
622 Known.Zero = APInt::getHighBitsSet(BitWidth, Leaders) & DemandedMask;
623 break;
624 }
625 case Instruction::Call:
626 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
627 switch (II->getIntrinsicID()) {
628 default: break;
629 case Intrinsic::bswap: {
630 // If the only bits demanded come from one byte of the bswap result,
631 // just shift the input byte into position to eliminate the bswap.
632 unsigned NLZ = DemandedMask.countLeadingZeros();
633 unsigned NTZ = DemandedMask.countTrailingZeros();
634
635 // Round NTZ down to the next byte. If we have 11 trailing zeros, then
636 // we need all the bits down to bit 8. Likewise, round NLZ. If we
637 // have 14 leading zeros, round to 8.
638 NLZ &= ~7;
639 NTZ &= ~7;
640 // If we need exactly one byte, we can do this transformation.
641 if (BitWidth-NLZ-NTZ == 8) {
642 unsigned ResultBit = NTZ;
643 unsigned InputBit = BitWidth-NTZ-8;
644
645 // Replace this with either a left or right shift to get the byte into
646 // the right place.
647 Instruction *NewVal;
648 if (InputBit > ResultBit)
649 NewVal = BinaryOperator::CreateLShr(II->getArgOperand(0),
650 ConstantInt::get(I->getType(), InputBit-ResultBit));
651 else
652 NewVal = BinaryOperator::CreateShl(II->getArgOperand(0),
653 ConstantInt::get(I->getType(), ResultBit-InputBit));
654 NewVal->takeName(I);
655 return InsertNewInstWith(NewVal, *I);
656 }
657
658 // TODO: Could compute known zero/one bits based on the input.
659 break;
660 }
661 case Intrinsic::x86_mmx_pmovmskb:
662 case Intrinsic::x86_sse_movmsk_ps:
663 case Intrinsic::x86_sse2_movmsk_pd:
664 case Intrinsic::x86_sse2_pmovmskb_128:
665 case Intrinsic::x86_avx_movmsk_ps_256:
666 case Intrinsic::x86_avx_movmsk_pd_256:
667 case Intrinsic::x86_avx2_pmovmskb: {
668 // MOVMSK copies the vector elements' sign bits to the low bits
669 // and zeros the high bits.
670 unsigned ArgWidth;
671 if (II->getIntrinsicID() == Intrinsic::x86_mmx_pmovmskb) {
672 ArgWidth = 8; // Arg is x86_mmx, but treated as <8 x i8>.
673 } else {
674 auto Arg = II->getArgOperand(0);
675 auto ArgType = cast<VectorType>(Arg->getType());
676 ArgWidth = ArgType->getNumElements();
677 }
678
679 // If we don't need any of low bits then return zero,
680 // we know that DemandedMask is non-zero already.
681 APInt DemandedElts = DemandedMask.zextOrTrunc(ArgWidth);
682 if (DemandedElts == 0)
683 return ConstantInt::getNullValue(VTy);
684
685 // We know that the upper bits are set to zero.
686 Known.Zero.setBitsFrom(ArgWidth);
687 return nullptr;
688 }
689 case Intrinsic::x86_sse42_crc32_64_64:
690 Known.Zero.setBitsFrom(32);
691 return nullptr;
692 }
693 }
694 computeKnownBits(V, Known, Depth, CxtI);
695 break;
696 }
697
698 // If the client is only demanding bits that we know, return the known
699 // constant.
700 if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
701 return Constant::getIntegerValue(VTy, Known.One);
702 return nullptr;
703}
704
705/// Helper routine of SimplifyDemandedUseBits. It computes Known
706/// bits. It also tries to handle simplifications that can be done based on
707/// DemandedMask, but without modifying the Instruction.
708Value *InstCombiner::SimplifyMultipleUseDemandedBits(Instruction *I,
709 const APInt &DemandedMask,
710 KnownBits &Known,
711 unsigned Depth,
712 Instruction *CxtI) {
713 unsigned BitWidth = DemandedMask.getBitWidth();
714 Type *ITy = I->getType();
715
716 KnownBits LHSKnown(BitWidth);
717 KnownBits RHSKnown(BitWidth);
718
719 // Despite the fact that we can't simplify this instruction in all User's
720 // context, we can at least compute the known bits, and we can
721 // do simplifications that apply to *just* the one user if we know that
722 // this instruction has a simpler value in that context.
723 switch (I->getOpcode()) {
724 case Instruction::And: {
725 // If either the LHS or the RHS are Zero, the result is zero.
726 computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
727 computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
728 CxtI);
729
730 // Output known-0 are known to be clear if zero in either the LHS | RHS.
731 APInt IKnownZero = RHSKnown.Zero | LHSKnown.Zero;
732 // Output known-1 bits are only known if set in both the LHS & RHS.
733 APInt IKnownOne = RHSKnown.One & LHSKnown.One;
734
735 // If the client is only demanding bits that we know, return the known
736 // constant.
737 if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
738 return Constant::getIntegerValue(ITy, IKnownOne);
739
740 // If all of the demanded bits are known 1 on one side, return the other.
741 // These bits cannot contribute to the result of the 'and' in this
742 // context.
743 if (DemandedMask.isSubsetOf(LHSKnown.Zero | RHSKnown.One))
744 return I->getOperand(0);
745 if (DemandedMask.isSubsetOf(RHSKnown.Zero | LHSKnown.One))
746 return I->getOperand(1);
747
748 Known.Zero = std::move(IKnownZero);
749 Known.One = std::move(IKnownOne);
750 break;
751 }
752 case Instruction::Or: {
753 // We can simplify (X|Y) -> X or Y in the user's context if we know that
754 // only bits from X or Y are demanded.
755
756 // If either the LHS or the RHS are One, the result is One.
757 computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
758 computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
759 CxtI);
760
761 // Output known-0 bits are only known if clear in both the LHS & RHS.
762 APInt IKnownZero = RHSKnown.Zero & LHSKnown.Zero;
763 // Output known-1 are known to be set if set in either the LHS | RHS.
764 APInt IKnownOne = RHSKnown.One | LHSKnown.One;
765
766 // If the client is only demanding bits that we know, return the known
767 // constant.
768 if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
769 return Constant::getIntegerValue(ITy, IKnownOne);
770
771 // If all of the demanded bits are known zero on one side, return the
772 // other. These bits cannot contribute to the result of the 'or' in this
773 // context.
774 if (DemandedMask.isSubsetOf(LHSKnown.One | RHSKnown.Zero))
775 return I->getOperand(0);
776 if (DemandedMask.isSubsetOf(RHSKnown.One | LHSKnown.Zero))
777 return I->getOperand(1);
778
779 Known.Zero = std::move(IKnownZero);
780 Known.One = std::move(IKnownOne);
781 break;
782 }
783 case Instruction::Xor: {
784 // We can simplify (X^Y) -> X or Y in the user's context if we know that
785 // only bits from X or Y are demanded.
786
787 computeKnownBits(I->getOperand(1), RHSKnown, Depth + 1, CxtI);
788 computeKnownBits(I->getOperand(0), LHSKnown, Depth + 1,
789 CxtI);
790
791 // Output known-0 bits are known if clear or set in both the LHS & RHS.
792 APInt IKnownZero = (RHSKnown.Zero & LHSKnown.Zero) |
793 (RHSKnown.One & LHSKnown.One);
794 // Output known-1 are known to be set if set in only one of the LHS, RHS.
795 APInt IKnownOne = (RHSKnown.Zero & LHSKnown.One) |
796 (RHSKnown.One & LHSKnown.Zero);
797
798 // If the client is only demanding bits that we know, return the known
799 // constant.
800 if (DemandedMask.isSubsetOf(IKnownZero|IKnownOne))
801 return Constant::getIntegerValue(ITy, IKnownOne);
802
803 // If all of the demanded bits are known zero on one side, return the
804 // other.
805 if (DemandedMask.isSubsetOf(RHSKnown.Zero))
806 return I->getOperand(0);
807 if (DemandedMask.isSubsetOf(LHSKnown.Zero))
808 return I->getOperand(1);
809
810 // Output known-0 bits are known if clear or set in both the LHS & RHS.
811 Known.Zero = std::move(IKnownZero);
812 // Output known-1 are known to be set if set in only one of the LHS, RHS.
813 Known.One = std::move(IKnownOne);
814 break;
815 }
816 default:
817 // Compute the Known bits to simplify things downstream.
818 computeKnownBits(I, Known, Depth, CxtI);
819
820 // If this user is only demanding bits that we know, return the known
821 // constant.
822 if (DemandedMask.isSubsetOf(Known.Zero|Known.One))
823 return Constant::getIntegerValue(ITy, Known.One);
824
825 break;
826 }
827
828 return nullptr;
829}
830
831
832/// Helper routine of SimplifyDemandedUseBits. It tries to simplify
833/// "E1 = (X lsr C1) << C2", where the C1 and C2 are constant, into
834/// "E2 = X << (C2 - C1)" or "E2 = X >> (C1 - C2)", depending on the sign
835/// of "C2-C1".
836///
837/// Suppose E1 and E2 are generally different in bits S={bm, bm+1,
838/// ..., bn}, without considering the specific value X is holding.
839/// This transformation is legal iff one of following conditions is hold:
840/// 1) All the bit in S are 0, in this case E1 == E2.
841/// 2) We don't care those bits in S, per the input DemandedMask.
842/// 3) Combination of 1) and 2). Some bits in S are 0, and we don't care the
843/// rest bits.
844///
845/// Currently we only test condition 2).
846///
847/// As with SimplifyDemandedUseBits, it returns NULL if the simplification was
848/// not successful.
849Value *
850InstCombiner::simplifyShrShlDemandedBits(Instruction *Shr, const APInt &ShrOp1,
851 Instruction *Shl, const APInt &ShlOp1,
852 const APInt &DemandedMask,
853 KnownBits &Known) {
854 if (!ShlOp1 || !ShrOp1)
855 return nullptr; // No-op.
856
857 Value *VarX = Shr->getOperand(0);
858 Type *Ty = VarX->getType();
859 unsigned BitWidth = Ty->getScalarSizeInBits();
860 if (ShlOp1.uge(BitWidth) || ShrOp1.uge(BitWidth))
861 return nullptr; // Undef.
862
863 unsigned ShlAmt = ShlOp1.getZExtValue();
864 unsigned ShrAmt = ShrOp1.getZExtValue();
865
866 Known.One.clearAllBits();
867 Known.Zero.setLowBits(ShlAmt - 1);
868 Known.Zero &= DemandedMask;
869
870 APInt BitMask1(APInt::getAllOnesValue(BitWidth));
871 APInt BitMask2(APInt::getAllOnesValue(BitWidth));
872
873 bool isLshr = (Shr->getOpcode() == Instruction::LShr);
874 BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) :
875 (BitMask1.ashr(ShrAmt) << ShlAmt);
876
877 if (ShrAmt <= ShlAmt) {
878 BitMask2 <<= (ShlAmt - ShrAmt);
879 } else {
880 BitMask2 = isLshr ? BitMask2.lshr(ShrAmt - ShlAmt):
881 BitMask2.ashr(ShrAmt - ShlAmt);
882 }
883
884 // Check if condition-2 (see the comment to this function) is satified.
885 if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
886 if (ShrAmt == ShlAmt)
887 return VarX;
888
889 if (!Shr->hasOneUse())
890 return nullptr;
891
892 BinaryOperator *New;
893 if (ShrAmt < ShlAmt) {
894 Constant *Amt = ConstantInt::get(VarX->getType(), ShlAmt - ShrAmt);
895 New = BinaryOperator::CreateShl(VarX, Amt);
896 BinaryOperator *Orig = cast<BinaryOperator>(Shl);
897 New->setHasNoSignedWrap(Orig->hasNoSignedWrap());
898 New->setHasNoUnsignedWrap(Orig->hasNoUnsignedWrap());
899 } else {
900 Constant *Amt = ConstantInt::get(VarX->getType(), ShrAmt - ShlAmt);
901 New = isLshr ? BinaryOperator::CreateLShr(VarX, Amt) :
902 BinaryOperator::CreateAShr(VarX, Amt);
903 if (cast<BinaryOperator>(Shr)->isExact())
904 New->setIsExact(true);
905 }
906
907 return InsertNewInstWith(New, *Shl);
908 }
909
910 return nullptr;
911}
912
913/// The specified value produces a vector with any number of elements.
914/// DemandedElts contains the set of elements that are actually used by the
915/// caller. This method analyzes which elements of the operand are undef and
916/// returns that information in UndefElts.
917///
918/// If the information about demanded elements can be used to simplify the
919/// operation, the operation is simplified, then the resultant value is
920/// returned. This returns null if no change was made.
921Value *InstCombiner::SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
922 APInt &UndefElts,
923 unsigned Depth) {
924 unsigned VWidth = V->getType()->getVectorNumElements();
925 APInt EltMask(APInt::getAllOnesValue(VWidth));
926 assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!")(((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"
) ? static_cast<void> (0) : __assert_fail ("(DemandedElts & ~EltMask) == 0 && \"Invalid DemandedElts!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 926, __PRETTY_FUNCTION__))
;
927
928 if (isa<UndefValue>(V)) {
929 // If the entire vector is undefined, just return this info.
930 UndefElts = EltMask;
931 return nullptr;
932 }
933
934 if (DemandedElts == 0) { // If nothing is demanded, provide undef.
935 UndefElts = EltMask;
936 return UndefValue::get(V->getType());
937 }
938
939 UndefElts = 0;
940
941 // Handle ConstantAggregateZero, ConstantVector, ConstantDataSequential.
942 if (Constant *C = dyn_cast<Constant>(V)) {
943 // Check if this is identity. If so, return 0 since we are not simplifying
944 // anything.
945 if (DemandedElts.isAllOnesValue())
946 return nullptr;
947
948 Type *EltTy = cast<VectorType>(V->getType())->getElementType();
949 Constant *Undef = UndefValue::get(EltTy);
950
951 SmallVector<Constant*, 16> Elts;
952 for (unsigned i = 0; i != VWidth; ++i) {
953 if (!DemandedElts[i]) { // If not demanded, set to undef.
954 Elts.push_back(Undef);
955 UndefElts.setBit(i);
956 continue;
957 }
958
959 Constant *Elt = C->getAggregateElement(i);
960 if (!Elt) return nullptr;
961
962 if (isa<UndefValue>(Elt)) { // Already undef.
963 Elts.push_back(Undef);
964 UndefElts.setBit(i);
965 } else { // Otherwise, defined.
966 Elts.push_back(Elt);
967 }
968 }
969
970 // If we changed the constant, return it.
971 Constant *NewCV = ConstantVector::get(Elts);
972 return NewCV != C ? NewCV : nullptr;
973 }
974
975 // Limit search depth.
976 if (Depth == 10)
977 return nullptr;
978
979 // If multiple users are using the root value, proceed with
980 // simplification conservatively assuming that all elements
981 // are needed.
982 if (!V->hasOneUse()) {
983 // Quit if we find multiple users of a non-root value though.
984 // They'll be handled when it's their turn to be visited by
985 // the main instcombine process.
986 if (Depth != 0)
987 // TODO: Just compute the UndefElts information recursively.
988 return nullptr;
989
990 // Conservatively assume that all elements are needed.
991 DemandedElts = EltMask;
992 }
993
994 Instruction *I = dyn_cast<Instruction>(V);
995 if (!I) return nullptr; // Only analyze instructions.
996
997 bool MadeChange = false;
998 APInt UndefElts2(VWidth, 0);
999 APInt UndefElts3(VWidth, 0);
1000 Value *TmpV;
1001 switch (I->getOpcode()) {
1002 default: break;
1003
1004 case Instruction::InsertElement: {
1005 // If this is a variable index, we don't know which element it overwrites.
1006 // demand exactly the same input as we produce.
1007 ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
1008 if (!Idx) {
1009 // Note that we can't propagate undef elt info, because we don't know
1010 // which elt is getting updated.
1011 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts,
1012 UndefElts2, Depth + 1);
1013 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1014 break;
1015 }
1016
1017 // If this is inserting an element that isn't demanded, remove this
1018 // insertelement.
1019 unsigned IdxNo = Idx->getZExtValue();
1020 if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
1021 Worklist.Add(I);
1022 return I->getOperand(0);
1023 }
1024
1025 // Otherwise, the element inserted overwrites whatever was there, so the
1026 // input demanded set is simpler than the output set.
1027 APInt DemandedElts2 = DemandedElts;
1028 DemandedElts2.clearBit(IdxNo);
1029 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts2,
1030 UndefElts, Depth + 1);
1031 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1032
1033 // The inserted element is defined.
1034 UndefElts.clearBit(IdxNo);
1035 break;
1036 }
1037 case Instruction::ShuffleVector: {
1038 ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1039 unsigned LHSVWidth =
1040 Shuffle->getOperand(0)->getType()->getVectorNumElements();
1041 APInt LeftDemanded(LHSVWidth, 0), RightDemanded(LHSVWidth, 0);
1042 for (unsigned i = 0; i < VWidth; i++) {
1043 if (DemandedElts[i]) {
1044 unsigned MaskVal = Shuffle->getMaskValue(i);
1045 if (MaskVal != -1u) {
1046 assert(MaskVal < LHSVWidth * 2 &&((MaskVal < LHSVWidth * 2 && "shufflevector mask index out of range!"
) ? static_cast<void> (0) : __assert_fail ("MaskVal < LHSVWidth * 2 && \"shufflevector mask index out of range!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 1047, __PRETTY_FUNCTION__))
1047 "shufflevector mask index out of range!")((MaskVal < LHSVWidth * 2 && "shufflevector mask index out of range!"
) ? static_cast<void> (0) : __assert_fail ("MaskVal < LHSVWidth * 2 && \"shufflevector mask index out of range!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 1047, __PRETTY_FUNCTION__))
;
1048 if (MaskVal < LHSVWidth)
1049 LeftDemanded.setBit(MaskVal);
1050 else
1051 RightDemanded.setBit(MaskVal - LHSVWidth);
1052 }
1053 }
1054 }
1055
1056 APInt LHSUndefElts(LHSVWidth, 0);
1057 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), LeftDemanded,
1058 LHSUndefElts, Depth + 1);
1059 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1060
1061 APInt RHSUndefElts(LHSVWidth, 0);
1062 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), RightDemanded,
1063 RHSUndefElts, Depth + 1);
1064 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1065
1066 bool NewUndefElts = false;
1067 unsigned LHSIdx = -1u, LHSValIdx = -1u;
1068 unsigned RHSIdx = -1u, RHSValIdx = -1u;
1069 bool LHSUniform = true;
1070 bool RHSUniform = true;
1071 for (unsigned i = 0; i < VWidth; i++) {
1072 unsigned MaskVal = Shuffle->getMaskValue(i);
1073 if (MaskVal == -1u) {
1074 UndefElts.setBit(i);
1075 } else if (!DemandedElts[i]) {
1076 NewUndefElts = true;
1077 UndefElts.setBit(i);
1078 } else if (MaskVal < LHSVWidth) {
1079 if (LHSUndefElts[MaskVal]) {
1080 NewUndefElts = true;
1081 UndefElts.setBit(i);
1082 } else {
1083 LHSIdx = LHSIdx == -1u ? i : LHSVWidth;
1084 LHSValIdx = LHSValIdx == -1u ? MaskVal : LHSVWidth;
1085 LHSUniform = LHSUniform && (MaskVal == i);
1086 }
1087 } else {
1088 if (RHSUndefElts[MaskVal - LHSVWidth]) {
1089 NewUndefElts = true;
1090 UndefElts.setBit(i);
1091 } else {
1092 RHSIdx = RHSIdx == -1u ? i : LHSVWidth;
1093 RHSValIdx = RHSValIdx == -1u ? MaskVal - LHSVWidth : LHSVWidth;
1094 RHSUniform = RHSUniform && (MaskVal - LHSVWidth == i);
1095 }
1096 }
1097 }
1098
1099 // Try to transform shuffle with constant vector and single element from
1100 // this constant vector to single insertelement instruction.
1101 // shufflevector V, C, <v1, v2, .., ci, .., vm> ->
1102 // insertelement V, C[ci], ci-n
1103 if (LHSVWidth == Shuffle->getType()->getNumElements()) {
1104 Value *Op = nullptr;
1105 Constant *Value = nullptr;
1106 unsigned Idx = -1u;
1107
1108 // Find constant vector with the single element in shuffle (LHS or RHS).
1109 if (LHSIdx < LHSVWidth && RHSUniform) {
1110 if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(0))) {
1111 Op = Shuffle->getOperand(1);
1112 Value = CV->getOperand(LHSValIdx);
1113 Idx = LHSIdx;
1114 }
1115 }
1116 if (RHSIdx < LHSVWidth && LHSUniform) {
1117 if (auto *CV = dyn_cast<ConstantVector>(Shuffle->getOperand(1))) {
1118 Op = Shuffle->getOperand(0);
1119 Value = CV->getOperand(RHSValIdx);
1120 Idx = RHSIdx;
1121 }
1122 }
1123 // Found constant vector with single element - convert to insertelement.
1124 if (Op && Value) {
1125 Instruction *New = InsertElementInst::Create(
1126 Op, Value, ConstantInt::get(Type::getInt32Ty(I->getContext()), Idx),
1127 Shuffle->getName());
1128 InsertNewInstWith(New, *Shuffle);
1129 return New;
1130 }
1131 }
1132 if (NewUndefElts) {
1133 // Add additional discovered undefs.
1134 SmallVector<Constant*, 16> Elts;
1135 for (unsigned i = 0; i < VWidth; ++i) {
1136 if (UndefElts[i])
1137 Elts.push_back(UndefValue::get(Type::getInt32Ty(I->getContext())));
1138 else
1139 Elts.push_back(ConstantInt::get(Type::getInt32Ty(I->getContext()),
1140 Shuffle->getMaskValue(i)));
1141 }
1142 I->setOperand(2, ConstantVector::get(Elts));
1143 MadeChange = true;
1144 }
1145 break;
1146 }
1147 case Instruction::Select: {
1148 APInt LeftDemanded(DemandedElts), RightDemanded(DemandedElts);
1149 if (ConstantVector* CV = dyn_cast<ConstantVector>(I->getOperand(0))) {
1150 for (unsigned i = 0; i < VWidth; i++) {
1151 Constant *CElt = CV->getAggregateElement(i);
1152 // Method isNullValue always returns false when called on a
1153 // ConstantExpr. If CElt is a ConstantExpr then skip it in order to
1154 // to avoid propagating incorrect information.
1155 if (isa<ConstantExpr>(CElt))
1156 continue;
1157 if (CElt->isNullValue())
1158 LeftDemanded.clearBit(i);
1159 else
1160 RightDemanded.clearBit(i);
1161 }
1162 }
1163
1164 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), LeftDemanded, UndefElts,
1165 Depth + 1);
1166 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1167
1168 TmpV = SimplifyDemandedVectorElts(I->getOperand(2), RightDemanded,
1169 UndefElts2, Depth + 1);
1170 if (TmpV) { I->setOperand(2, TmpV); MadeChange = true; }
1171
1172 // Output elements are undefined if both are undefined.
1173 UndefElts &= UndefElts2;
1174 break;
1175 }
1176 case Instruction::BitCast: {
1177 // Vector->vector casts only.
1178 VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
1179 if (!VTy) break;
1180 unsigned InVWidth = VTy->getNumElements();
1181 APInt InputDemandedElts(InVWidth, 0);
1182 UndefElts2 = APInt(InVWidth, 0);
1183 unsigned Ratio;
1184
1185 if (VWidth == InVWidth) {
1186 // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
1187 // elements as are demanded of us.
1188 Ratio = 1;
1189 InputDemandedElts = DemandedElts;
1190 } else if ((VWidth % InVWidth) == 0) {
1191 // If the number of elements in the output is a multiple of the number of
1192 // elements in the input then an input element is live if any of the
1193 // corresponding output elements are live.
1194 Ratio = VWidth / InVWidth;
1195 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1196 if (DemandedElts[OutIdx])
1197 InputDemandedElts.setBit(OutIdx / Ratio);
1198 } else if ((InVWidth % VWidth) == 0) {
1199 // If the number of elements in the input is a multiple of the number of
1200 // elements in the output then an input element is live if the
1201 // corresponding output element is live.
1202 Ratio = InVWidth / VWidth;
1203 for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
1204 if (DemandedElts[InIdx / Ratio])
1205 InputDemandedElts.setBit(InIdx);
1206 } else {
1207 // Unsupported so far.
1208 break;
1209 }
1210
1211 // div/rem demand all inputs, because they don't want divide by zero.
1212 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), InputDemandedElts,
1213 UndefElts2, Depth + 1);
1214 if (TmpV) {
1215 I->setOperand(0, TmpV);
1216 MadeChange = true;
1217 }
1218
1219 if (VWidth == InVWidth) {
1220 UndefElts = UndefElts2;
1221 } else if ((VWidth % InVWidth) == 0) {
1222 // If the number of elements in the output is a multiple of the number of
1223 // elements in the input then an output element is undef if the
1224 // corresponding input element is undef.
1225 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
1226 if (UndefElts2[OutIdx / Ratio])
1227 UndefElts.setBit(OutIdx);
1228 } else if ((InVWidth % VWidth) == 0) {
1229 // If the number of elements in the input is a multiple of the number of
1230 // elements in the output then an output element is undef if all of the
1231 // corresponding input elements are undef.
1232 for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
1233 APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
1234 if (SubUndef.countPopulation() == Ratio)
1235 UndefElts.setBit(OutIdx);
1236 }
1237 } else {
1238 llvm_unreachable("Unimp")::llvm::llvm_unreachable_internal("Unimp", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 1238)
;
1239 }
1240 break;
1241 }
1242 case Instruction::And:
1243 case Instruction::Or:
1244 case Instruction::Xor:
1245 case Instruction::Add:
1246 case Instruction::Sub:
1247 case Instruction::Mul:
1248 // div/rem demand all inputs, because they don't want divide by zero.
1249 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
1250 Depth + 1);
1251 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1252 TmpV = SimplifyDemandedVectorElts(I->getOperand(1), DemandedElts,
1253 UndefElts2, Depth + 1);
1254 if (TmpV) { I->setOperand(1, TmpV); MadeChange = true; }
1255
1256 // Output elements are undefined if both are undefined. Consider things
1257 // like undef&0. The result is known zero, not undef.
1258 UndefElts &= UndefElts2;
1259 break;
1260 case Instruction::FPTrunc:
1261 case Instruction::FPExt:
1262 TmpV = SimplifyDemandedVectorElts(I->getOperand(0), DemandedElts, UndefElts,
1263 Depth + 1);
1264 if (TmpV) { I->setOperand(0, TmpV); MadeChange = true; }
1265 break;
1266
1267 case Instruction::Call: {
1268 IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
1269 if (!II) break;
1270 switch (II->getIntrinsicID()) {
1271 default: break;
1272
1273 case Intrinsic::x86_xop_vfrcz_ss:
1274 case Intrinsic::x86_xop_vfrcz_sd:
1275 // The instructions for these intrinsics are speced to zero upper bits not
1276 // pass them through like other scalar intrinsics. So we shouldn't just
1277 // use Arg0 if DemandedElts[0] is clear like we do for other intrinsics.
1278 // Instead we should return a zero vector.
1279 if (!DemandedElts[0]) {
1280 Worklist.Add(II);
1281 return ConstantAggregateZero::get(II->getType());
1282 }
1283
1284 // Only the lower element is used.
1285 DemandedElts = 1;
1286 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1287 UndefElts, Depth + 1);
1288 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1289
1290 // Only the lower element is undefined. The high elements are zero.
1291 UndefElts = UndefElts[0];
1292 break;
1293
1294 // Unary scalar-as-vector operations that work column-wise.
1295 case Intrinsic::x86_sse_rcp_ss:
1296 case Intrinsic::x86_sse_rsqrt_ss:
1297 case Intrinsic::x86_sse_sqrt_ss:
1298 case Intrinsic::x86_sse2_sqrt_sd:
1299 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1300 UndefElts, Depth + 1);
1301 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1302
1303 // If lowest element of a scalar op isn't used then use Arg0.
1304 if (!DemandedElts[0]) {
1305 Worklist.Add(II);
1306 return II->getArgOperand(0);
1307 }
1308 // TODO: If only low elt lower SQRT to FSQRT (with rounding/exceptions
1309 // checks).
1310 break;
1311
1312 // Binary scalar-as-vector operations that work column-wise. The high
1313 // elements come from operand 0. The low element is a function of both
1314 // operands.
1315 case Intrinsic::x86_sse_min_ss:
1316 case Intrinsic::x86_sse_max_ss:
1317 case Intrinsic::x86_sse_cmp_ss:
1318 case Intrinsic::x86_sse2_min_sd:
1319 case Intrinsic::x86_sse2_max_sd:
1320 case Intrinsic::x86_sse2_cmp_sd: {
1321 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1322 UndefElts, Depth + 1);
1323 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1324
1325 // If lowest element of a scalar op isn't used then use Arg0.
1326 if (!DemandedElts[0]) {
1327 Worklist.Add(II);
1328 return II->getArgOperand(0);
1329 }
1330
1331 // Only lower element is used for operand 1.
1332 DemandedElts = 1;
1333 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1334 UndefElts2, Depth + 1);
1335 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1336
1337 // Lower element is undefined if both lower elements are undefined.
1338 // Consider things like undef&0. The result is known zero, not undef.
1339 if (!UndefElts2[0])
1340 UndefElts.clearBit(0);
1341
1342 break;
1343 }
1344
1345 // Binary scalar-as-vector operations that work column-wise. The high
1346 // elements come from operand 0 and the low element comes from operand 1.
1347 case Intrinsic::x86_sse41_round_ss:
1348 case Intrinsic::x86_sse41_round_sd: {
1349 // Don't use the low element of operand 0.
1350 APInt DemandedElts2 = DemandedElts;
1351 DemandedElts2.clearBit(0);
1352 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts2,
1353 UndefElts, Depth + 1);
1354 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1355
1356 // If lowest element of a scalar op isn't used then use Arg0.
1357 if (!DemandedElts[0]) {
1358 Worklist.Add(II);
1359 return II->getArgOperand(0);
1360 }
1361
1362 // Only lower element is used for operand 1.
1363 DemandedElts = 1;
1364 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1365 UndefElts2, Depth + 1);
1366 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1367
1368 // Take the high undef elements from operand 0 and take the lower element
1369 // from operand 1.
1370 UndefElts.clearBit(0);
1371 UndefElts |= UndefElts2[0];
1372 break;
1373 }
1374
1375 // Three input scalar-as-vector operations that work column-wise. The high
1376 // elements come from operand 0 and the low element is a function of all
1377 // three inputs.
1378 case Intrinsic::x86_avx512_mask_add_ss_round:
1379 case Intrinsic::x86_avx512_mask_div_ss_round:
1380 case Intrinsic::x86_avx512_mask_mul_ss_round:
1381 case Intrinsic::x86_avx512_mask_sub_ss_round:
1382 case Intrinsic::x86_avx512_mask_max_ss_round:
1383 case Intrinsic::x86_avx512_mask_min_ss_round:
1384 case Intrinsic::x86_avx512_mask_add_sd_round:
1385 case Intrinsic::x86_avx512_mask_div_sd_round:
1386 case Intrinsic::x86_avx512_mask_mul_sd_round:
1387 case Intrinsic::x86_avx512_mask_sub_sd_round:
1388 case Intrinsic::x86_avx512_mask_max_sd_round:
1389 case Intrinsic::x86_avx512_mask_min_sd_round:
1390 case Intrinsic::x86_fma_vfmadd_ss:
1391 case Intrinsic::x86_fma_vfmsub_ss:
1392 case Intrinsic::x86_fma_vfnmadd_ss:
1393 case Intrinsic::x86_fma_vfnmsub_ss:
1394 case Intrinsic::x86_fma_vfmadd_sd:
1395 case Intrinsic::x86_fma_vfmsub_sd:
1396 case Intrinsic::x86_fma_vfnmadd_sd:
1397 case Intrinsic::x86_fma_vfnmsub_sd:
1398 case Intrinsic::x86_avx512_mask_vfmadd_ss:
1399 case Intrinsic::x86_avx512_mask_vfmadd_sd:
1400 case Intrinsic::x86_avx512_maskz_vfmadd_ss:
1401 case Intrinsic::x86_avx512_maskz_vfmadd_sd:
1402 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1403 UndefElts, Depth + 1);
1404 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1405
1406 // If lowest element of a scalar op isn't used then use Arg0.
1407 if (!DemandedElts[0]) {
1408 Worklist.Add(II);
1409 return II->getArgOperand(0);
1410 }
1411
1412 // Only lower element is used for operand 1 and 2.
1413 DemandedElts = 1;
1414 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1415 UndefElts2, Depth + 1);
1416 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1417 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(2), DemandedElts,
1418 UndefElts3, Depth + 1);
1419 if (TmpV) { II->setArgOperand(2, TmpV); MadeChange = true; }
1420
1421 // Lower element is undefined if all three lower elements are undefined.
1422 // Consider things like undef&0. The result is known zero, not undef.
1423 if (!UndefElts2[0] || !UndefElts3[0])
1424 UndefElts.clearBit(0);
1425
1426 break;
1427
1428 case Intrinsic::x86_avx512_mask3_vfmadd_ss:
1429 case Intrinsic::x86_avx512_mask3_vfmadd_sd:
1430 case Intrinsic::x86_avx512_mask3_vfmsub_ss:
1431 case Intrinsic::x86_avx512_mask3_vfmsub_sd:
1432 case Intrinsic::x86_avx512_mask3_vfnmsub_ss:
1433 case Intrinsic::x86_avx512_mask3_vfnmsub_sd:
1434 // These intrinsics get the passthru bits from operand 2.
1435 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(2), DemandedElts,
1436 UndefElts, Depth + 1);
1437 if (TmpV) { II->setArgOperand(2, TmpV); MadeChange = true; }
1438
1439 // If lowest element of a scalar op isn't used then use Arg2.
1440 if (!DemandedElts[0]) {
1441 Worklist.Add(II);
1442 return II->getArgOperand(2);
1443 }
1444
1445 // Only lower element is used for operand 0 and 1.
1446 DemandedElts = 1;
1447 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), DemandedElts,
1448 UndefElts2, Depth + 1);
1449 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1450 TmpV = SimplifyDemandedVectorElts(II->getArgOperand(1), DemandedElts,
1451 UndefElts3, Depth + 1);
1452 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1453
1454 // Lower element is undefined if all three lower elements are undefined.
1455 // Consider things like undef&0. The result is known zero, not undef.
1456 if (!UndefElts2[0] || !UndefElts3[0])
1457 UndefElts.clearBit(0);
1458
1459 break;
1460
1461 case Intrinsic::x86_sse2_pmulu_dq:
1462 case Intrinsic::x86_sse41_pmuldq:
1463 case Intrinsic::x86_avx2_pmul_dq:
1464 case Intrinsic::x86_avx2_pmulu_dq:
1465 case Intrinsic::x86_avx512_pmul_dq_512:
1466 case Intrinsic::x86_avx512_pmulu_dq_512: {
1467 Value *Op0 = II->getArgOperand(0);
1468 Value *Op1 = II->getArgOperand(1);
1469 unsigned InnerVWidth = Op0->getType()->getVectorNumElements();
1470 assert((VWidth * 2) == InnerVWidth && "Unexpected input size")(((VWidth * 2) == InnerVWidth && "Unexpected input size"
) ? static_cast<void> (0) : __assert_fail ("(VWidth * 2) == InnerVWidth && \"Unexpected input size\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 1470, __PRETTY_FUNCTION__))
;
1471
1472 APInt InnerDemandedElts(InnerVWidth, 0);
1473 for (unsigned i = 0; i != VWidth; ++i)
1474 if (DemandedElts[i])
1475 InnerDemandedElts.setBit(i * 2);
1476
1477 UndefElts2 = APInt(InnerVWidth, 0);
1478 TmpV = SimplifyDemandedVectorElts(Op0, InnerDemandedElts, UndefElts2,
1479 Depth + 1);
1480 if (TmpV) { II->setArgOperand(0, TmpV); MadeChange = true; }
1481
1482 UndefElts3 = APInt(InnerVWidth, 0);
1483 TmpV = SimplifyDemandedVectorElts(Op1, InnerDemandedElts, UndefElts3,
1484 Depth + 1);
1485 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1486
1487 break;
1488 }
1489
1490 case Intrinsic::x86_sse2_packssdw_128:
1491 case Intrinsic::x86_sse2_packsswb_128:
1492 case Intrinsic::x86_sse2_packuswb_128:
1493 case Intrinsic::x86_sse41_packusdw:
1494 case Intrinsic::x86_avx2_packssdw:
1495 case Intrinsic::x86_avx2_packsswb:
1496 case Intrinsic::x86_avx2_packusdw:
1497 case Intrinsic::x86_avx2_packuswb:
1498 case Intrinsic::x86_avx512_packssdw_512:
1499 case Intrinsic::x86_avx512_packsswb_512:
1500 case Intrinsic::x86_avx512_packusdw_512:
1501 case Intrinsic::x86_avx512_packuswb_512: {
1502 auto *Ty0 = II->getArgOperand(0)->getType();
1503 unsigned InnerVWidth = Ty0->getVectorNumElements();
1504 assert(VWidth == (InnerVWidth * 2) && "Unexpected input size")((VWidth == (InnerVWidth * 2) && "Unexpected input size"
) ? static_cast<void> (0) : __assert_fail ("VWidth == (InnerVWidth * 2) && \"Unexpected input size\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301769/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp"
, 1504, __PRETTY_FUNCTION__))
;
1505
1506 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128;
1507 unsigned VWidthPerLane = VWidth / NumLanes;
1508 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes;
1509
1510 // Per lane, pack the elements of the first input and then the second.
1511 // e.g.
1512 // v8i16 PACK(v4i32 X, v4i32 Y) - (X[0..3],Y[0..3])
1513 // v32i8 PACK(v16i16 X, v16i16 Y) - (X[0..7],Y[0..7]),(X[8..15],Y[8..15])
1514 for (int OpNum = 0; OpNum != 2; ++OpNum) {
1515 APInt OpDemandedElts(InnerVWidth, 0);
1516 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1517 unsigned LaneIdx = Lane * VWidthPerLane;
1518 for (unsigned Elt = 0; Elt != InnerVWidthPerLane; ++Elt) {
1519 unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum;
1520 if (DemandedElts[Idx])
1521 OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt);
1522 }
1523 }
1524
1525 // Demand elements from the operand.
1526 auto *Op = II->getArgOperand(OpNum);
1527 APInt OpUndefElts(InnerVWidth, 0);
1528 TmpV = SimplifyDemandedVectorElts(Op, OpDemandedElts, OpUndefElts,
1529 Depth + 1);
1530 if (TmpV) {
1531 II->setArgOperand(OpNum, TmpV);
1532 MadeChange = true;
1533 }
1534
1535 // Pack the operand's UNDEF elements, one lane at a time.
1536 OpUndefElts = OpUndefElts.zext(VWidth);
1537 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
1538 APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane);
1539 LaneElts = LaneElts.getLoBits(InnerVWidthPerLane);
1540 LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum);
1541 UndefElts |= LaneElts;
1542 }
1543 }
1544 break;
1545 }
1546
1547 // PSHUFB
1548 case Intrinsic::x86_ssse3_pshuf_b_128:
1549 case Intrinsic::x86_avx2_pshuf_b:
1550 case Intrinsic::x86_avx512_pshuf_b_512:
1551 // PERMILVAR
1552 case Intrinsic::x86_avx_vpermilvar_ps:
1553 case Intrinsic::x86_avx_vpermilvar_ps_256:
1554 case Intrinsic::x86_avx512_vpermilvar_ps_512:
1555 case Intrinsic::x86_avx_vpermilvar_pd:
1556 case Intrinsic::x86_avx_vpermilvar_pd_256:
1557 case Intrinsic::x86_avx512_vpermilvar_pd_512:
1558 // PERMV
1559 case Intrinsic::x86_avx2_permd:
1560 case Intrinsic::x86_avx2_permps: {
1561 Value *Op1 = II->getArgOperand(1);
1562 TmpV = SimplifyDemandedVectorElts(Op1, DemandedElts, UndefElts,
1563 Depth + 1);
1564 if (TmpV) { II->setArgOperand(1, TmpV); MadeChange = true; }
1565 break;
1566 }
1567
1568 // SSE4A instructions leave the upper 64-bits of the 128-bit result
1569 // in an undefined state.
1570 case Intrinsic::x86_sse4a_extrq:
1571 case Intrinsic::x86_sse4a_extrqi:
1572 case Intrinsic::x86_sse4a_insertq:
1573 case Intrinsic::x86_sse4a_insertqi:
1574 UndefElts.setHighBits(VWidth / 2);
1575 break;
1576 case Intrinsic::amdgcn_buffer_load:
1577 case Intrinsic::amdgcn_buffer_load_format:
1578 case Intrinsic::amdgcn_image_sample:
1579 case Intrinsic::amdgcn_image_sample_cl:
1580 case Intrinsic::amdgcn_image_sample_d:
1581 case Intrinsic::amdgcn_image_sample_d_cl:
1582 case Intrinsic::amdgcn_image_sample_l:
1583 case Intrinsic::amdgcn_image_sample_b:
1584 case Intrinsic::amdgcn_image_sample_b_cl:
1585 case Intrinsic::amdgcn_image_sample_lz:
1586 case Intrinsic::amdgcn_image_sample_cd:
1587 case Intrinsic::amdgcn_image_sample_cd_cl:
1588
1589 case Intrinsic::amdgcn_image_sample_c:
1590 case Intrinsic::amdgcn_image_sample_c_cl:
1591 case Intrinsic::amdgcn_image_sample_c_d:
1592 case Intrinsic::amdgcn_image_sample_c_d_cl:
1593 case Intrinsic::amdgcn_image_sample_c_l:
1594 case Intrinsic::amdgcn_image_sample_c_b:
1595 case Intrinsic::amdgcn_image_sample_c_b_cl:
1596 case Intrinsic::amdgcn_image_sample_c_lz:
1597 case Intrinsic::amdgcn_image_sample_c_cd:
1598 case Intrinsic::amdgcn_image_sample_c_cd_cl:
1599
1600 case Intrinsic::amdgcn_image_sample_o:
1601 case Intrinsic::amdgcn_image_sample_cl_o:
1602 case Intrinsic::amdgcn_image_sample_d_o:
1603 case Intrinsic::amdgcn_image_sample_d_cl_o:
1604 case Intrinsic::amdgcn_image_sample_l_o:
1605 case Intrinsic::amdgcn_image_sample_b_o:
1606 case Intrinsic::amdgcn_image_sample_b_cl_o:
1607 case Intrinsic::amdgcn_image_sample_lz_o:
1608 case Intrinsic::amdgcn_image_sample_cd_o:
1609 case Intrinsic::amdgcn_image_sample_cd_cl_o:
1610
1611 case Intrinsic::amdgcn_image_sample_c_o:
1612 case Intrinsic::amdgcn_image_sample_c_cl_o:
1613 case Intrinsic::amdgcn_image_sample_c_d_o:
1614 case Intrinsic::amdgcn_image_sample_c_d_cl_o:
1615 case Intrinsic::amdgcn_image_sample_c_l_o:
1616 case Intrinsic::amdgcn_image_sample_c_b_o:
1617 case Intrinsic::amdgcn_image_sample_c_b_cl_o:
1618 case Intrinsic::amdgcn_image_sample_c_lz_o:
1619 case Intrinsic::amdgcn_image_sample_c_cd_o:
1620 case Intrinsic::amdgcn_image_sample_c_cd_cl_o:
1621
1622 case Intrinsic::amdgcn_image_getlod: {
1623 if (VWidth == 1 || !DemandedElts.isMask())
1624 return nullptr;
1625
1626 // TODO: Handle 3 vectors when supported in code gen.
1627 unsigned NewNumElts = PowerOf2Ceil(DemandedElts.countTrailingOnes());
1628 if (NewNumElts == VWidth)
1629 return nullptr;
1630
1631 Module *M = II->getParent()->getParent()->getParent();
1632 Type *EltTy = V->getType()->getVectorElementType();
1633
1634 Type *NewTy = (NewNumElts == 1) ? EltTy :
1635 VectorType::get(EltTy, NewNumElts);
1636
1637 auto IID = II->getIntrinsicID();
1638
1639 bool IsBuffer = IID == Intrinsic::amdgcn_buffer_load ||
1640 IID == Intrinsic::amdgcn_buffer_load_format;
1641
1642 Function *NewIntrin = IsBuffer ?
1643 Intrinsic::getDeclaration(M, IID, NewTy) :
1644 // Samplers have 3 mangled types.
1645 Intrinsic::getDeclaration(M, IID,
1646 { NewTy, II->getArgOperand(0)->getType(),
1647 II->getArgOperand(1)->getType()});
1648
1649 SmallVector<Value *, 5> Args;
1650 for (unsigned I = 0, E = II->getNumArgOperands(); I != E; ++I)
1651 Args.push_back(II->getArgOperand(I));
1652
1653 IRBuilderBase::InsertPointGuard Guard(*Builder);
1654 Builder->SetInsertPoint(II);
1655
1656 CallInst *NewCall = Builder->CreateCall(NewIntrin, Args);
1657 NewCall->takeName(II);
1658 NewCall->copyMetadata(*II);
1659
1660 if (!IsBuffer) {
1661 ConstantInt *DMask = dyn_cast<ConstantInt>(NewCall->getArgOperand(3));
1662 if (DMask) {
1663 unsigned DMaskVal = DMask->getZExtValue() & 0xf;
1664
1665 unsigned PopCnt = 0;
1666 unsigned NewDMask = 0;
1667 for (unsigned I = 0; I < 4; ++I) {
1668 const unsigned Bit = 1 << I;
1669 if (!!(DMaskVal & Bit)) {
1670 if (++PopCnt > NewNumElts)
1671 break;
1672
1673 NewDMask |= Bit;
1674 }
1675 }
1676
1677 NewCall->setArgOperand(3, ConstantInt::get(DMask->getType(), NewDMask));
1678 }
1679 }
1680
1681
1682 if (NewNumElts == 1) {
1683 return Builder->CreateInsertElement(UndefValue::get(V->getType()),
1684 NewCall, static_cast<uint64_t>(0));
1685 }
1686
1687 SmallVector<uint32_t, 8> EltMask;
1688 for (unsigned I = 0; I < VWidth; ++I)
1689 EltMask.push_back(I);
1690
1691 Value *Shuffle = Builder->CreateShuffleVector(
1692 NewCall, UndefValue::get(NewTy), EltMask);
1693
1694 MadeChange = true;
Value stored to 'MadeChange' is never read
1695 return Shuffle;
1696 }
1697 }
1698 break;
1699 }
1700 }
1701 return MadeChange ? I : nullptr;
1702}