Bug Summary

File:build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc
Warning:line 774, column 10
Excessive padding in 'struct llvm::(anonymous namespace)::MatchEntry' (2 padding bytes, where 0 is optimal). Optimal fields order: Opcode, Mnemonic, ConvertFn, RequiredFeatures, Classes, consider reordering the fields or adding explicit padding members

Annotated Source Code

1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_ASSEMBLER_HEADER
11#undef GET_ASSEMBLER_HEADER
12 // This should be included into the middle of the declaration of
13 // your subclasses implementation of MCTargetAsmParser.
14 uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 const OperandVector &Operands);
17 void convertToMapAndConstraints(unsigned Kind,
18 const OperandVector &Operands) override;
19 unsigned MatchInstructionImpl(const OperandVector &Operands,
20 MCInst &Inst,
21 uint64_t &ErrorInfo, bool matchingInlineAsm,
22 unsigned VariantID = 0);
23 OperandMatchResultTy MatchOperandParserImpl(
24 OperandVector &Operands,
25 StringRef Mnemonic);
26 OperandMatchResultTy tryCustomParseOperand(
27 OperandVector &Operands,
28 unsigned MCK);
29
30#endif // GET_ASSEMBLER_HEADER_INFO
31
32
33#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
34#undef GET_OPERAND_DIAGNOSTIC_TYPES
35
36#endif // GET_OPERAND_DIAGNOSTIC_TYPES
37
38
39#ifdef GET_REGISTER_MATCHER
40#undef GET_REGISTER_MATCHER
41
42// Flags for subtarget features that participate in instruction matching.
43enum SubtargetFeatureFlag : uint8_t {
44 Feature_None = 0
45};
46
47static unsigned MatchRegisterName(StringRef Name) {
48 switch (Name.size()) {
49 default: break;
50 case 2: // 15 strings to match.
51 switch (Name[0]) {
52 default: break;
53 case 'f': // 1 string to match.
54 if (Name[1] != 'p')
55 break;
56 return 1; // "fp"
57 case 'p': // 1 string to match.
58 if (Name[1] != 'c')
59 break;
60 return 2; // "pc"
61 case 'r': // 11 strings to match.
62 switch (Name[1]) {
63 default: break;
64 case '0': // 1 string to match.
65 return 7; // "r0"
66 case '1': // 1 string to match.
67 return 8; // "r1"
68 case '2': // 1 string to match.
69 return 9; // "r2"
70 case '3': // 1 string to match.
71 return 10; // "r3"
72 case '4': // 1 string to match.
73 return 11; // "r4"
74 case '5': // 1 string to match.
75 return 12; // "r5"
76 case '6': // 1 string to match.
77 return 13; // "r6"
78 case '7': // 1 string to match.
79 return 14; // "r7"
80 case '8': // 1 string to match.
81 return 15; // "r8"
82 case '9': // 1 string to match.
83 return 16; // "r9"
84 case 'v': // 1 string to match.
85 return 4; // "rv"
86 }
87 break;
88 case 's': // 2 strings to match.
89 switch (Name[1]) {
90 default: break;
91 case 'p': // 1 string to match.
92 return 5; // "sp"
93 case 'w': // 1 string to match.
94 return 6; // "sw"
95 }
96 break;
97 }
98 break;
99 case 3: // 25 strings to match.
100 if (Name[0] != 'r')
101 break;
102 switch (Name[1]) {
103 default: break;
104 case '1': // 10 strings to match.
105 switch (Name[2]) {
106 default: break;
107 case '0': // 1 string to match.
108 return 17; // "r10"
109 case '1': // 1 string to match.
110 return 18; // "r11"
111 case '2': // 1 string to match.
112 return 19; // "r12"
113 case '3': // 1 string to match.
114 return 20; // "r13"
115 case '4': // 1 string to match.
116 return 21; // "r14"
117 case '5': // 1 string to match.
118 return 22; // "r15"
119 case '6': // 1 string to match.
120 return 23; // "r16"
121 case '7': // 1 string to match.
122 return 24; // "r17"
123 case '8': // 1 string to match.
124 return 25; // "r18"
125 case '9': // 1 string to match.
126 return 26; // "r19"
127 }
128 break;
129 case '2': // 10 strings to match.
130 switch (Name[2]) {
131 default: break;
132 case '0': // 1 string to match.
133 return 27; // "r20"
134 case '1': // 1 string to match.
135 return 28; // "r21"
136 case '2': // 1 string to match.
137 return 29; // "r22"
138 case '3': // 1 string to match.
139 return 30; // "r23"
140 case '4': // 1 string to match.
141 return 31; // "r24"
142 case '5': // 1 string to match.
143 return 32; // "r25"
144 case '6': // 1 string to match.
145 return 33; // "r26"
146 case '7': // 1 string to match.
147 return 34; // "r27"
148 case '8': // 1 string to match.
149 return 35; // "r28"
150 case '9': // 1 string to match.
151 return 36; // "r29"
152 }
153 break;
154 case '3': // 2 strings to match.
155 switch (Name[2]) {
156 default: break;
157 case '0': // 1 string to match.
158 return 37; // "r30"
159 case '1': // 1 string to match.
160 return 38; // "r31"
161 }
162 break;
163 case 'c': // 1 string to match.
164 if (Name[2] != 'a')
165 break;
166 return 3; // "rca"
167 case 'r': // 2 strings to match.
168 switch (Name[2]) {
169 default: break;
170 case '1': // 1 string to match.
171 return 39; // "rr1"
172 case '2': // 1 string to match.
173 return 40; // "rr2"
174 }
175 break;
176 }
177 break;
178 }
179 return 0;
180}
181
182#endif // GET_REGISTER_MATCHER
183
184
185#ifdef GET_SUBTARGET_FEATURE_NAME
186#undef GET_SUBTARGET_FEATURE_NAME
187
188// User-level names for subtarget features that participate in
189// instruction matching.
190static const char *getSubtargetFeatureName(uint64_t Val) {
191 return "(unknown)";
192}
193
194#endif // GET_SUBTARGET_FEATURE_NAME
195
196
197#ifdef GET_MATCHER_IMPLEMENTATION
198#undef GET_MATCHER_IMPLEMENTATION
199
200namespace {
201enum OperatorConversionKind {
202 CVT_Done,
203 CVT_Reg,
204 CVT_Tied,
205 CVT_95_addImmOperands,
206 CVT_95_Reg,
207 CVT_95_addHiImm16Operands,
208 CVT_95_addLoImm16Operands,
209 CVT_95_addCondCodeOperands,
210 CVT_95_addHiImm16AndOperands,
211 CVT_95_addLoImm16AndOperands,
212 CVT_95_addBrTargetOperands,
213 CVT_95_addMemImmOperands,
214 CVT_95_addMemRegImmOperands,
215 CVT_95_addMemRegRegOperands,
216 CVT_95_addMemSplsOperands,
217 CVT_regR0,
218 CVT_imm_95_0,
219 CVT_regR1,
220 CVT_95_addLoImm21Operands,
221 CVT_95_addImmShiftOperands,
222 CVT_NUM_CONVERTERS
223};
224
225enum InstructionConversionKind {
226 Convert__Imm1_0,
227 Convert__Imm1_0__Imm1_1,
228 Convert__Reg1_0__Reg1_1,
229 Convert__Reg1_2__Reg1_0__HiImm161_1,
230 Convert__Reg1_2__Reg1_0__LoImm161_1,
231 Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0,
232 Convert__Reg1_2__Reg1_0__HiImm16And1_1,
233 Convert__Reg1_2__Reg1_0__LoImm16And1_1,
234 Convert__Reg1_1__Imm1_0,
235 Convert__BrTarget1_1__Imm1_0,
236 Convert__Imm1_2__Imm1_0,
237 Convert__Reg1_1__Reg1_3__Imm1_0,
238 Convert__Reg1_0,
239 Convert__BrTarget1_0,
240 Convert__Reg1_1__MemImm1_0,
241 Convert__Reg1_1__MemRegImm3_0,
242 Convert__Reg1_1__MemRegReg3_0,
243 Convert_NoOperands,
244 Convert__Reg1_1__MemSpls3_0,
245 Convert__Reg1_1__Reg1_0,
246 Convert__Reg1_1__Reg1_0__regR0__imm_95_0,
247 Convert__Reg1_1__regR1__HiImm16And1_0,
248 Convert__Reg1_1__regR0__HiImm161_0,
249 Convert__Reg1_1__regR1__LoImm16And1_0,
250 Convert__Reg1_1__regR0__LoImm161_0,
251 Convert__Reg1_1__LoImm211_0,
252 Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0,
253 Convert__Reg1_2__Reg1_0__ImmShift1_1,
254 Convert__Reg1_0__MemImm1_1,
255 Convert__Reg1_0__MemRegImm3_1,
256 Convert__Reg1_0__MemRegReg3_1,
257 Convert__Reg1_0__MemSpls3_1,
258 CVT_NUM_SIGNATURES
259};
260
261} // end anonymous namespace
262
263static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
264 // Convert__Imm1_0
265 { CVT_95_addImmOperands, 1, CVT_Done },
266 // Convert__Imm1_0__Imm1_1
267 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
268 // Convert__Reg1_0__Reg1_1
269 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
270 // Convert__Reg1_2__Reg1_0__HiImm161_1
271 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16Operands, 2, CVT_Done },
272 // Convert__Reg1_2__Reg1_0__LoImm161_1
273 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16Operands, 2, CVT_Done },
274 // Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0
275 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
276 // Convert__Reg1_2__Reg1_0__HiImm16And1_1
277 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16AndOperands, 2, CVT_Done },
278 // Convert__Reg1_2__Reg1_0__LoImm16And1_1
279 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16AndOperands, 2, CVT_Done },
280 // Convert__Reg1_1__Imm1_0
281 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
282 // Convert__BrTarget1_1__Imm1_0
283 { CVT_95_addBrTargetOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
284 // Convert__Imm1_2__Imm1_0
285 { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
286 // Convert__Reg1_1__Reg1_3__Imm1_0
287 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
288 // Convert__Reg1_0
289 { CVT_95_Reg, 1, CVT_Done },
290 // Convert__BrTarget1_0
291 { CVT_95_addBrTargetOperands, 1, CVT_Done },
292 // Convert__Reg1_1__MemImm1_0
293 { CVT_95_Reg, 2, CVT_95_addMemImmOperands, 1, CVT_Done },
294 // Convert__Reg1_1__MemRegImm3_0
295 { CVT_95_Reg, 2, CVT_95_addMemRegImmOperands, 1, CVT_Done },
296 // Convert__Reg1_1__MemRegReg3_0
297 { CVT_95_Reg, 2, CVT_95_addMemRegRegOperands, 1, CVT_Done },
298 // Convert_NoOperands
299 { CVT_Done },
300 // Convert__Reg1_1__MemSpls3_0
301 { CVT_95_Reg, 2, CVT_95_addMemSplsOperands, 1, CVT_Done },
302 // Convert__Reg1_1__Reg1_0
303 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
304 // Convert__Reg1_1__Reg1_0__regR0__imm_95_0
305 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
306 // Convert__Reg1_1__regR1__HiImm16And1_0
307 { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addHiImm16AndOperands, 1, CVT_Done },
308 // Convert__Reg1_1__regR0__HiImm161_0
309 { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addHiImm16Operands, 1, CVT_Done },
310 // Convert__Reg1_1__regR1__LoImm16And1_0
311 { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addLoImm16AndOperands, 1, CVT_Done },
312 // Convert__Reg1_1__regR0__LoImm161_0
313 { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addLoImm16Operands, 1, CVT_Done },
314 // Convert__Reg1_1__LoImm211_0
315 { CVT_95_Reg, 2, CVT_95_addLoImm21Operands, 1, CVT_Done },
316 // Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0
317 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
318 // Convert__Reg1_2__Reg1_0__ImmShift1_1
319 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmShiftOperands, 2, CVT_Done },
320 // Convert__Reg1_0__MemImm1_1
321 { CVT_95_Reg, 1, CVT_95_addMemImmOperands, 2, CVT_Done },
322 // Convert__Reg1_0__MemRegImm3_1
323 { CVT_95_Reg, 1, CVT_95_addMemRegImmOperands, 2, CVT_Done },
324 // Convert__Reg1_0__MemRegReg3_1
325 { CVT_95_Reg, 1, CVT_95_addMemRegRegOperands, 2, CVT_Done },
326 // Convert__Reg1_0__MemSpls3_1
327 { CVT_95_Reg, 1, CVT_95_addMemSplsOperands, 2, CVT_Done },
328};
329
330void LanaiAsmParser::
331convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
332 const OperandVector &Operands) {
333 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!")((Kind < CVT_NUM_SIGNATURES && "Invalid signature!"
) ? static_cast<void> (0) : __assert_fail ("Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 333, __PRETTY_FUNCTION__))
;
334 const uint8_t *Converter = ConversionTable[Kind];
335 unsigned OpIdx;
336 Inst.setOpcode(Opcode);
337 for (const uint8_t *p = Converter; *p; p+= 2) {
338 OpIdx = *(p + 1);
339 switch (*p) {
340 default: llvm_unreachable("invalid conversion entry!")::llvm::llvm_unreachable_internal("invalid conversion entry!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 340)
;
341 case CVT_Reg:
342 static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
343 break;
344 case CVT_Tied:
345 Inst.addOperand(Inst.getOperand(OpIdx));
346 break;
347 case CVT_95_addImmOperands:
348 static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
349 break;
350 case CVT_95_Reg:
351 static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
352 break;
353 case CVT_95_addHiImm16Operands:
354 static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16Operands(Inst, 1);
355 break;
356 case CVT_95_addLoImm16Operands:
357 static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16Operands(Inst, 1);
358 break;
359 case CVT_95_addCondCodeOperands:
360 static_cast<LanaiOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
361 break;
362 case CVT_95_addHiImm16AndOperands:
363 static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16AndOperands(Inst, 1);
364 break;
365 case CVT_95_addLoImm16AndOperands:
366 static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16AndOperands(Inst, 1);
367 break;
368 case CVT_95_addBrTargetOperands:
369 static_cast<LanaiOperand&>(*Operands[OpIdx]).addBrTargetOperands(Inst, 1);
370 break;
371 case CVT_95_addMemImmOperands:
372 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemImmOperands(Inst, 1);
373 break;
374 case CVT_95_addMemRegImmOperands:
375 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegImmOperands(Inst, 3);
376 break;
377 case CVT_95_addMemRegRegOperands:
378 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegRegOperands(Inst, 3);
379 break;
380 case CVT_95_addMemSplsOperands:
381 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemSplsOperands(Inst, 3);
382 break;
383 case CVT_regR0:
384 Inst.addOperand(MCOperand::createReg(Lanai::R0));
385 break;
386 case CVT_imm_95_0:
387 Inst.addOperand(MCOperand::createImm(0));
388 break;
389 case CVT_regR1:
390 Inst.addOperand(MCOperand::createReg(Lanai::R1));
391 break;
392 case CVT_95_addLoImm21Operands:
393 static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm21Operands(Inst, 1);
394 break;
395 case CVT_95_addImmShiftOperands:
396 static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmShiftOperands(Inst, 1);
397 break;
398 }
399 }
400}
401
402void LanaiAsmParser::
403convertToMapAndConstraints(unsigned Kind,
404 const OperandVector &Operands) {
405 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!")((Kind < CVT_NUM_SIGNATURES && "Invalid signature!"
) ? static_cast<void> (0) : __assert_fail ("Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 405, __PRETTY_FUNCTION__))
;
406 unsigned NumMCOperands = 0;
407 const uint8_t *Converter = ConversionTable[Kind];
408 for (const uint8_t *p = Converter; *p; p+= 2) {
409 switch (*p) {
410 default: llvm_unreachable("invalid conversion entry!")::llvm::llvm_unreachable_internal("invalid conversion entry!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 410)
;
411 case CVT_Reg:
412 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
413 Operands[*(p + 1)]->setConstraint("r");
414 ++NumMCOperands;
415 break;
416 case CVT_Tied:
417 ++NumMCOperands;
418 break;
419 case CVT_95_addImmOperands:
420 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
421 Operands[*(p + 1)]->setConstraint("m");
422 NumMCOperands += 1;
423 break;
424 case CVT_95_Reg:
425 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
426 Operands[*(p + 1)]->setConstraint("r");
427 NumMCOperands += 1;
428 break;
429 case CVT_95_addHiImm16Operands:
430 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
431 Operands[*(p + 1)]->setConstraint("m");
432 NumMCOperands += 1;
433 break;
434 case CVT_95_addLoImm16Operands:
435 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
436 Operands[*(p + 1)]->setConstraint("m");
437 NumMCOperands += 1;
438 break;
439 case CVT_95_addCondCodeOperands:
440 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
441 Operands[*(p + 1)]->setConstraint("m");
442 NumMCOperands += 1;
443 break;
444 case CVT_95_addHiImm16AndOperands:
445 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
446 Operands[*(p + 1)]->setConstraint("m");
447 NumMCOperands += 1;
448 break;
449 case CVT_95_addLoImm16AndOperands:
450 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
451 Operands[*(p + 1)]->setConstraint("m");
452 NumMCOperands += 1;
453 break;
454 case CVT_95_addBrTargetOperands:
455 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
456 Operands[*(p + 1)]->setConstraint("m");
457 NumMCOperands += 1;
458 break;
459 case CVT_95_addMemImmOperands:
460 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
461 Operands[*(p + 1)]->setConstraint("m");
462 NumMCOperands += 1;
463 break;
464 case CVT_95_addMemRegImmOperands:
465 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
466 Operands[*(p + 1)]->setConstraint("m");
467 NumMCOperands += 3;
468 break;
469 case CVT_95_addMemRegRegOperands:
470 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
471 Operands[*(p + 1)]->setConstraint("m");
472 NumMCOperands += 3;
473 break;
474 case CVT_95_addMemSplsOperands:
475 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
476 Operands[*(p + 1)]->setConstraint("m");
477 NumMCOperands += 3;
478 break;
479 case CVT_regR0:
480 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
481 Operands[*(p + 1)]->setConstraint("m");
482 ++NumMCOperands;
483 break;
484 case CVT_imm_95_0:
485 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
486 Operands[*(p + 1)]->setConstraint("");
487 ++NumMCOperands;
488 break;
489 case CVT_regR1:
490 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
491 Operands[*(p + 1)]->setConstraint("m");
492 ++NumMCOperands;
493 break;
494 case CVT_95_addLoImm21Operands:
495 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
496 Operands[*(p + 1)]->setConstraint("m");
497 NumMCOperands += 1;
498 break;
499 case CVT_95_addImmShiftOperands:
500 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
501 Operands[*(p + 1)]->setConstraint("m");
502 NumMCOperands += 1;
503 break;
504 }
505 }
506}
507
508namespace {
509
510/// MatchClassKind - The kinds of classes which participate in
511/// instruction matching.
512enum MatchClassKind {
513 InvalidMatchClass = 0,
514 OptionalMatchClass = 1,
515 MCK__EXCLAIM_, // '!'
516 MCK__PCT_fp, // '%fp'
517 MCK__PCT_pc, // '%pc'
518 MCK__MINUS_4, // '-4'
519 MCK__DOT_r, // '.r'
520 MCK__91_, // '['
521 MCK__93_, // ']'
522 MCK_add, // 'add'
523 MCK_return, // 'return'
524 MCK_CCR, // register class 'CCR'
525 MCK_Reg1, // derived register class
526 MCK_GPR, // register class 'GPR'
527 MCK_BrTarget, // user defined class 'BrTargetAsmOperand'
528 MCK_CallTarget, // user defined class 'CallTargetAsmOperand'
529 MCK_CondCode, // user defined class 'CondCodeOperand'
530 MCK_HiImm16And, // user defined class 'HiImm16AndAsmOperand'
531 MCK_HiImm16, // user defined class 'HiImm16AsmOperand'
532 MCK_Imm10, // user defined class 'Imm10AsmOperand'
533 MCK_Imm, // user defined class 'ImmAsmOperand'
534 MCK_ImmShift, // user defined class 'ImmShiftAsmOperand'
535 MCK_LoImm16And, // user defined class 'LoImm16AndAsmOperand'
536 MCK_LoImm16, // user defined class 'LoImm16AsmOperand'
537 MCK_LoImm21, // user defined class 'LoImm21AsmOperand'
538 MCK_MemImm, // user defined class 'MemImmAsmOperand'
539 MCK_MemRegImm, // user defined class 'MemRegImmAsmOperand'
540 MCK_MemRegReg, // user defined class 'MemRegRegAsmOperand'
541 MCK_MemSpls, // user defined class 'MemSplsAsmOperand'
542 NumMatchClassKinds
543};
544
545}
546
547static MatchClassKind matchTokenString(StringRef Name) {
548 switch (Name.size()) {
549 default: break;
550 case 1: // 3 strings to match.
551 switch (Name[0]) {
552 default: break;
553 case '!': // 1 string to match.
554 return MCK__EXCLAIM_; // "!"
555 case '[': // 1 string to match.
556 return MCK__91_; // "["
557 case ']': // 1 string to match.
558 return MCK__93_; // "]"
559 }
560 break;
561 case 2: // 2 strings to match.
562 switch (Name[0]) {
563 default: break;
564 case '-': // 1 string to match.
565 if (Name[1] != '4')
566 break;
567 return MCK__MINUS_4; // "-4"
568 case '.': // 1 string to match.
569 if (Name[1] != 'r')
570 break;
571 return MCK__DOT_r; // ".r"
572 }
573 break;
574 case 3: // 3 strings to match.
575 switch (Name[0]) {
576 default: break;
577 case '%': // 2 strings to match.
578 switch (Name[1]) {
579 default: break;
580 case 'f': // 1 string to match.
581 if (Name[2] != 'p')
582 break;
583 return MCK__PCT_fp; // "%fp"
584 case 'p': // 1 string to match.
585 if (Name[2] != 'c')
586 break;
587 return MCK__PCT_pc; // "%pc"
588 }
589 break;
590 case 'a': // 1 string to match.
591 if (memcmp(Name.data()+1, "dd", 2) != 0)
592 break;
593 return MCK_add; // "add"
594 }
595 break;
596 case 6: // 1 string to match.
597 if (memcmp(Name.data()+0, "return", 6) != 0)
598 break;
599 return MCK_return; // "return"
600 }
601 return InvalidMatchClass;
602}
603
604/// isSubclass - Compute whether \p A is a subclass of \p B.
605static bool isSubclass(MatchClassKind A, MatchClassKind B) {
606 if (A == B)
607 return true;
608
609 switch (A) {
610 default:
611 return false;
612
613 case MCK_Reg1:
614 return B == MCK_GPR;
615 }
616}
617
618static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
619 LanaiOperand &Operand = (LanaiOperand&)GOp;
620 if (Kind == InvalidMatchClass)
621 return MCTargetAsmParser::Match_InvalidOperand;
622
623 if (Operand.isToken())
624 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
625 MCTargetAsmParser::Match_Success :
626 MCTargetAsmParser::Match_InvalidOperand;
627
628 switch (Kind) {
629 default: break;
630 // 'BrTarget' class
631 case MCK_BrTarget:
632 if (Operand.isBrTarget())
633 return MCTargetAsmParser::Match_Success;
634 break;
635 // 'CallTarget' class
636 case MCK_CallTarget:
637 if (Operand.isCallTarget())
638 return MCTargetAsmParser::Match_Success;
639 break;
640 // 'CondCode' class
641 case MCK_CondCode:
642 if (Operand.isCondCode())
643 return MCTargetAsmParser::Match_Success;
644 break;
645 // 'HiImm16And' class
646 case MCK_HiImm16And:
647 if (Operand.isHiImm16And())
648 return MCTargetAsmParser::Match_Success;
649 break;
650 // 'HiImm16' class
651 case MCK_HiImm16:
652 if (Operand.isHiImm16())
653 return MCTargetAsmParser::Match_Success;
654 break;
655 // 'Imm10' class
656 case MCK_Imm10:
657 if (Operand.isImm10())
658 return MCTargetAsmParser::Match_Success;
659 break;
660 // 'Imm' class
661 case MCK_Imm:
662 if (Operand.isImm())
663 return MCTargetAsmParser::Match_Success;
664 break;
665 // 'ImmShift' class
666 case MCK_ImmShift:
667 if (Operand.isImmShift())
668 return MCTargetAsmParser::Match_Success;
669 break;
670 // 'LoImm16And' class
671 case MCK_LoImm16And:
672 if (Operand.isLoImm16And())
673 return MCTargetAsmParser::Match_Success;
674 break;
675 // 'LoImm16' class
676 case MCK_LoImm16:
677 if (Operand.isLoImm16())
678 return MCTargetAsmParser::Match_Success;
679 break;
680 // 'LoImm21' class
681 case MCK_LoImm21:
682 if (Operand.isLoImm21())
683 return MCTargetAsmParser::Match_Success;
684 break;
685 // 'MemImm' class
686 case MCK_MemImm:
687 if (Operand.isMemImm())
688 return MCTargetAsmParser::Match_Success;
689 break;
690 // 'MemRegImm' class
691 case MCK_MemRegImm:
692 if (Operand.isMemRegImm())
693 return MCTargetAsmParser::Match_Success;
694 break;
695 // 'MemRegReg' class
696 case MCK_MemRegReg:
697 if (Operand.isMemRegReg())
698 return MCTargetAsmParser::Match_Success;
699 break;
700 // 'MemSpls' class
701 case MCK_MemSpls:
702 if (Operand.isMemSpls())
703 return MCTargetAsmParser::Match_Success;
704 break;
705 } // end switch (Kind)
706
707 if (Operand.isReg()) {
708 MatchClassKind OpKind;
709 switch (Operand.getReg()) {
710 default: OpKind = InvalidMatchClass; break;
711 case Lanai::R0: OpKind = MCK_GPR; break;
712 case Lanai::R1: OpKind = MCK_GPR; break;
713 case Lanai::R2: OpKind = MCK_GPR; break;
714 case Lanai::R3: OpKind = MCK_GPR; break;
715 case Lanai::R4: OpKind = MCK_GPR; break;
716 case Lanai::R5: OpKind = MCK_GPR; break;
717 case Lanai::R6: OpKind = MCK_GPR; break;
718 case Lanai::R7: OpKind = MCK_GPR; break;
719 case Lanai::R8: OpKind = MCK_GPR; break;
720 case Lanai::R9: OpKind = MCK_GPR; break;
721 case Lanai::R10: OpKind = MCK_GPR; break;
722 case Lanai::R11: OpKind = MCK_GPR; break;
723 case Lanai::R12: OpKind = MCK_GPR; break;
724 case Lanai::R13: OpKind = MCK_GPR; break;
725 case Lanai::R14: OpKind = MCK_GPR; break;
726 case Lanai::R15: OpKind = MCK_GPR; break;
727 case Lanai::R16: OpKind = MCK_GPR; break;
728 case Lanai::R17: OpKind = MCK_GPR; break;
729 case Lanai::R18: OpKind = MCK_GPR; break;
730 case Lanai::R19: OpKind = MCK_GPR; break;
731 case Lanai::R20: OpKind = MCK_GPR; break;
732 case Lanai::R21: OpKind = MCK_GPR; break;
733 case Lanai::R22: OpKind = MCK_GPR; break;
734 case Lanai::R23: OpKind = MCK_GPR; break;
735 case Lanai::R24: OpKind = MCK_GPR; break;
736 case Lanai::R25: OpKind = MCK_GPR; break;
737 case Lanai::R26: OpKind = MCK_GPR; break;
738 case Lanai::R27: OpKind = MCK_GPR; break;
739 case Lanai::R28: OpKind = MCK_GPR; break;
740 case Lanai::R29: OpKind = MCK_GPR; break;
741 case Lanai::R30: OpKind = MCK_GPR; break;
742 case Lanai::R31: OpKind = MCK_GPR; break;
743 case Lanai::PC: OpKind = MCK_Reg1; break;
744 case Lanai::SP: OpKind = MCK_Reg1; break;
745 case Lanai::FP: OpKind = MCK_Reg1; break;
746 case Lanai::RV: OpKind = MCK_Reg1; break;
747 case Lanai::RR1: OpKind = MCK_Reg1; break;
748 case Lanai::RR2: OpKind = MCK_Reg1; break;
749 case Lanai::RCA: OpKind = MCK_Reg1; break;
750 case Lanai::SR: OpKind = MCK_CCR; break;
751 }
752 return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
753 MCTargetAsmParser::Match_InvalidOperand;
754 }
755
756 return MCTargetAsmParser::Match_InvalidOperand;
757}
758
759uint64_t LanaiAsmParser::
760ComputeAvailableFeatures(const FeatureBitset& FB) const {
761 uint64_t Features = 0;
762 return Features;
763}
764
765static const char *const MnemonicTable =
766 "\021#ADJCALLSTACKDOWN\017#ADJCALLSTACKUP\014#ADJDYNALLOC\003add\005add."
767 "f\004addc\006addc.f\003and\005and.f\001b\002bt\002ld\004ld.b\004ld.h\005"
768 "leadz\005log_0\005log_1\005log_2\005log_3\005log_4\003mov\003nop\002or\004"
769 "or.f\004popc\001s\004sel.\002sh\004sh.f\003sha\005sha.f\002st\004st.b\004"
770 "st.h\003sub\005sub.f\004subb\006subb.f\006trailz\003uld\005uld.b\005uld"
771 ".h\003xor\005xor.f";
772
773namespace {
774 struct MatchEntry {
Excessive padding in 'struct llvm::(anonymous namespace)::MatchEntry' (2 padding bytes, where 0 is optimal). Optimal fields order: Opcode, Mnemonic, ConvertFn, RequiredFeatures, Classes, consider reordering the fields or adding explicit padding members
775 uint8_t Mnemonic;
776 uint16_t Opcode;
777 uint8_t ConvertFn;
778 uint8_t RequiredFeatures;
779 uint8_t Classes[7];
780 StringRef getMnemonic() const {
781 return StringRef(MnemonicTable + Mnemonic + 1,
782 MnemonicTable[Mnemonic]);
783 }
784 };
785
786 // Predicate for searching for an opcode.
787 struct LessOpcode {
788 bool operator()(const MatchEntry &LHS, StringRef RHS) {
789 return LHS.getMnemonic() < RHS;
790 }
791 bool operator()(StringRef LHS, const MatchEntry &RHS) {
792 return LHS < RHS.getMnemonic();
793 }
794 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
795 return LHS.getMnemonic() < RHS.getMnemonic();
796 }
797 };
798} // end anonymous namespace.
799
800static const MatchEntry MatchTable0[] = {
801 { 0 /* #ADJCALLSTACKDOWN */, Lanai::ADJCALLSTACKDOWN, Convert__Imm1_0, 0, { MCK_Imm }, },
802 { 18 /* #ADJCALLSTACKUP */, Lanai::ADJCALLSTACKUP, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
803 { 34 /* #ADJDYNALLOC */, Lanai::ADJDYNALLOC, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR, MCK_GPR }, },
804 { 47 /* add */, Lanai::ADD_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
805 { 47 /* add */, Lanai::ADD_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
806 { 47 /* add */, Lanai::ADD_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
807 { 51 /* add.f */, Lanai::ADD_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
808 { 51 /* add.f */, Lanai::ADD_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
809 { 51 /* add.f */, Lanai::ADD_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
810 { 57 /* addc */, Lanai::ADDC_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
811 { 57 /* addc */, Lanai::ADDC_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
812 { 57 /* addc */, Lanai::ADDC_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
813 { 62 /* addc.f */, Lanai::ADDC_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
814 { 62 /* addc.f */, Lanai::ADDC_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
815 { 62 /* addc.f */, Lanai::ADDC_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
816 { 69 /* and */, Lanai::AND_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
817 { 69 /* and */, Lanai::AND_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
818 { 69 /* and */, Lanai::AND_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
819 { 73 /* and.f */, Lanai::AND_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
820 { 73 /* and.f */, Lanai::AND_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
821 { 73 /* and.f */, Lanai::AND_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
822 { 79 /* b */, Lanai::BRIND_CC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
823 { 79 /* b */, Lanai::BRCC, Convert__BrTarget1_1__Imm1_0, 0, { MCK_Imm, MCK_BrTarget }, },
824 { 79 /* b */, Lanai::BRR, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__DOT_r, MCK_Imm }, },
825 { 79 /* b */, Lanai::BRIND_CCA, Convert__Reg1_1__Reg1_3__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_add, MCK_GPR }, },
826 { 81 /* bt */, Lanai::JR, Convert__Reg1_0, 0, { MCK_GPR }, },
827 { 81 /* bt */, Lanai::BT, Convert__BrTarget1_0, 0, { MCK_BrTarget }, },
828 { 84 /* ld */, Lanai::LDADDR, Convert__Reg1_1__MemImm1_0, 0, { MCK_MemImm, MCK_GPR }, },
829 { 84 /* ld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
830 { 84 /* ld */, Lanai::LDW_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
831 { 84 /* ld */, Lanai::RET, Convert_NoOperands, 0, { MCK__MINUS_4, MCK__91_, MCK__PCT_fp, MCK__93_, MCK__PCT_pc, MCK__EXCLAIM_, MCK_return }, },
832 { 87 /* ld.b */, Lanai::LDBs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
833 { 87 /* ld.b */, Lanai::LDBs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
834 { 92 /* ld.h */, Lanai::LDHs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
835 { 92 /* ld.h */, Lanai::LDHs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
836 { 97 /* leadz */, Lanai::LEADZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
837 { 103 /* log_0 */, Lanai::LOG0, Convert_NoOperands, 0, { }, },
838 { 109 /* log_1 */, Lanai::LOG1, Convert_NoOperands, 0, { }, },
839 { 115 /* log_2 */, Lanai::LOG2, Convert_NoOperands, 0, { }, },
840 { 121 /* log_3 */, Lanai::LOG3, Convert_NoOperands, 0, { }, },
841 { 127 /* log_4 */, Lanai::LOG4, Convert_NoOperands, 0, { }, },
842 { 133 /* mov */, Lanai::ADD_R, Convert__Reg1_1__Reg1_0__regR0__imm_95_0, 0, { MCK_GPR, MCK_GPR }, },
843 { 133 /* mov */, Lanai::AND_I_HI, Convert__Reg1_1__regR1__HiImm16And1_0, 0, { MCK_HiImm16And, MCK_GPR }, },
844 { 133 /* mov */, Lanai::ADD_I_HI, Convert__Reg1_1__regR0__HiImm161_0, 0, { MCK_HiImm16, MCK_GPR }, },
845 { 133 /* mov */, Lanai::AND_I_LO, Convert__Reg1_1__regR1__LoImm16And1_0, 0, { MCK_LoImm16And, MCK_GPR }, },
846 { 133 /* mov */, Lanai::ADD_I_LO, Convert__Reg1_1__regR0__LoImm161_0, 0, { MCK_LoImm16, MCK_GPR }, },
847 { 133 /* mov */, Lanai::SLI, Convert__Reg1_1__LoImm211_0, 0, { MCK_LoImm21, MCK_GPR }, },
848 { 137 /* nop */, Lanai::NOP, Convert_NoOperands, 0, { }, },
849 { 141 /* or */, Lanai::OR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
850 { 141 /* or */, Lanai::OR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
851 { 141 /* or */, Lanai::OR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
852 { 144 /* or.f */, Lanai::OR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
853 { 144 /* or.f */, Lanai::OR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
854 { 144 /* or.f */, Lanai::OR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
855 { 149 /* popc */, Lanai::POPC, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
856 { 154 /* s */, Lanai::SCC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
857 { 156 /* sel. */, Lanai::SELECT, Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_GPR, MCK_GPR }, },
858 { 161 /* sh */, Lanai::SL_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
859 { 161 /* sh */, Lanai::SHL_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
860 { 164 /* sh.f */, Lanai::SL_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
861 { 164 /* sh.f */, Lanai::SHL_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
862 { 169 /* sha */, Lanai::SA_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
863 { 169 /* sha */, Lanai::SRA_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
864 { 173 /* sha.f */, Lanai::SA_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
865 { 173 /* sha.f */, Lanai::SRA_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
866 { 179 /* st */, Lanai::STADDR, Convert__Reg1_0__MemImm1_1, 0, { MCK_GPR, MCK_MemImm }, },
867 { 179 /* st */, Lanai::SW_RI, Convert__Reg1_0__MemRegImm3_1, 0, { MCK_GPR, MCK_MemRegImm }, },
868 { 179 /* st */, Lanai::SW_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
869 { 182 /* st.b */, Lanai::STB_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
870 { 182 /* st.b */, Lanai::STB_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
871 { 187 /* st.h */, Lanai::STH_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
872 { 187 /* st.h */, Lanai::STH_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
873 { 192 /* sub */, Lanai::SUB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
874 { 192 /* sub */, Lanai::SUB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
875 { 192 /* sub */, Lanai::SUB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
876 { 196 /* sub.f */, Lanai::SUB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
877 { 196 /* sub.f */, Lanai::SUB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
878 { 196 /* sub.f */, Lanai::SUB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
879 { 202 /* subb */, Lanai::SUBB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
880 { 202 /* subb */, Lanai::SUBB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
881 { 202 /* subb */, Lanai::SUBB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
882 { 207 /* subb.f */, Lanai::SUBB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
883 { 207 /* subb.f */, Lanai::SUBB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
884 { 207 /* subb.f */, Lanai::SUBB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
885 { 214 /* trailz */, Lanai::TRAILZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
886 { 221 /* uld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
887 { 221 /* uld */, Lanai::LDWz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
888 { 225 /* uld.b */, Lanai::LDBz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
889 { 225 /* uld.b */, Lanai::LDBz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
890 { 231 /* uld.h */, Lanai::LDHz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
891 { 231 /* uld.h */, Lanai::LDHz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
892 { 237 /* xor */, Lanai::XOR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
893 { 237 /* xor */, Lanai::XOR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
894 { 237 /* xor */, Lanai::XOR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
895 { 241 /* xor.f */, Lanai::XOR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
896 { 241 /* xor.f */, Lanai::XOR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
897 { 241 /* xor.f */, Lanai::XOR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
898};
899
900unsigned LanaiAsmParser::
901MatchInstructionImpl(const OperandVector &Operands,
902 MCInst &Inst, uint64_t &ErrorInfo,
903 bool matchingInlineAsm, unsigned VariantID) {
904 // Eliminate obvious mismatches.
905 if (Operands.size() > 8) {
906 ErrorInfo = 8;
907 return Match_InvalidOperand;
908 }
909
910 // Get the current feature set.
911 uint64_t AvailableFeatures = getAvailableFeatures();
912
913 // Get the instruction mnemonic, which is the first token.
914 StringRef Mnemonic = ((LanaiOperand&)*Operands[0]).getToken();
915
916 // Some state to try to produce better error messages.
917 bool HadMatchOtherThanFeatures = false;
918 bool HadMatchOtherThanPredicate = false;
919 unsigned RetCode = Match_InvalidOperand;
920 uint64_t MissingFeatures = ~0ULL;
921 // Set ErrorInfo to the operand that mismatches if it is
922 // wrong for all instances of the instruction.
923 ErrorInfo = ~0ULL;
924 // Find the appropriate table for this asm variant.
925 const MatchEntry *Start, *End;
926 switch (VariantID) {
927 default: llvm_unreachable("invalid variant!")::llvm::llvm_unreachable_internal("invalid variant!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 927)
;
928 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
929 }
930 // Search the table.
931 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
932
933 // Return a more specific error code if no mnemonics match.
934 if (MnemonicRange.first == MnemonicRange.second)
935 return Match_MnemonicFail;
936
937 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
938 it != ie; ++it) {
939 // equal_range guarantees that instruction mnemonic matches.
940 assert(Mnemonic == it->getMnemonic())((Mnemonic == it->getMnemonic()) ? static_cast<void>
(0) : __assert_fail ("Mnemonic == it->getMnemonic()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 940, __PRETTY_FUNCTION__))
;
941 bool OperandsValid = true;
942 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; ++FormalIdx) {
943 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
944 if (ActualIdx >= Operands.size()) {
945 OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
946 if (!OperandsValid) ErrorInfo = ActualIdx;
947 break;
948 }
949 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
950 unsigned Diag = validateOperandClass(Actual, Formal);
951 if (Diag == Match_Success) {
952 ++ActualIdx;
953 continue;
954 }
955 // If the generic handler indicates an invalid operand
956 // failure, check for a special case.
957 if (Diag == Match_InvalidOperand) {
958 Diag = validateTargetOperandClass(Actual, Formal);
959 if (Diag == Match_Success) {
960 ++ActualIdx;
961 continue;
962 }
963 }
964 // If current formal operand wasn't matched and it is optional
965 // then try to match next formal operand
966 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
967 continue;
968 }
969 // If this operand is broken for all of the instances of this
970 // mnemonic, keep track of it so we can report loc info.
971 // If we already had a match that only failed due to a
972 // target predicate, that diagnostic is preferred.
973 if (!HadMatchOtherThanPredicate &&
974 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
975 ErrorInfo = ActualIdx;
976 // InvalidOperand is the default. Prefer specificity.
977 if (Diag != Match_InvalidOperand)
978 RetCode = Diag;
979 }
980 // Otherwise, just reject this instance of the mnemonic.
981 OperandsValid = false;
982 break;
983 }
984
985 if (!OperandsValid) continue;
986 if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
987 HadMatchOtherThanFeatures = true;
988 uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
989 if (countPopulation(NewMissingFeatures) <=
990 countPopulation(MissingFeatures))
991 MissingFeatures = NewMissingFeatures;
992 continue;
993 }
994
995 Inst.clear();
996
997 Inst.setOpcode(it->Opcode);
998 // We have a potential match but have not rendered the operands.
999 // Check the target predicate to handle any context sensitive
1000 // constraints.
1001 // For example, Ties that are referenced multiple times must be
1002 // checked here to ensure the input is the same for each match
1003 // constraints. If we leave it any later the ties will have been
1004 // canonicalized
1005 unsigned MatchResult;
1006 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1007 Inst.clear();
1008 RetCode = MatchResult;
1009 HadMatchOtherThanPredicate = true;
1010 continue;
1011 }
1012
1013 if (matchingInlineAsm) {
1014 convertToMapAndConstraints(it->ConvertFn, Operands);
1015 return Match_Success;
1016 }
1017
1018 // We have selected a definite instruction, convert the parsed
1019 // operands into the appropriate MCInst.
1020 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1021
1022 // We have a potential match. Check the target predicate to
1023 // handle any context sensitive constraints.
1024 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1025 Inst.clear();
1026 RetCode = MatchResult;
1027 HadMatchOtherThanPredicate = true;
1028 continue;
1029 }
1030
1031 return Match_Success;
1032 }
1033
1034 // Okay, we had no match. Try to return a useful error code.
1035 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1036 return RetCode;
1037
1038 // Missing feature matches return which features were missing
1039 ErrorInfo = MissingFeatures;
1040 return Match_MissingFeature;
1041}
1042
1043namespace {
1044 struct OperandMatchEntry {
1045 uint8_t RequiredFeatures;
1046 uint8_t Mnemonic;
1047 uint8_t Class;
1048 uint8_t OperandMask;
1049
1050 StringRef getMnemonic() const {
1051 return StringRef(MnemonicTable + Mnemonic + 1,
1052 MnemonicTable[Mnemonic]);
1053 }
1054 };
1055
1056 // Predicate for searching for an opcode.
1057 struct LessOpcodeOperand {
1058 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1059 return LHS.getMnemonic() < RHS;
1060 }
1061 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1062 return LHS < RHS.getMnemonic();
1063 }
1064 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1065 return LHS.getMnemonic() < RHS.getMnemonic();
1066 }
1067 };
1068} // end anonymous namespace.
1069
1070static const OperandMatchEntry OperandMatchTable[20] = {
1071 /* Operand List Mask, Mnemonic, Operand Class, Features */
1072 { 0, 84 /* ld */, MCK_MemImm, 1 /* 0 */ },
1073 { 0, 84 /* ld */, MCK_MemRegImm, 1 /* 0 */ },
1074 { 0, 84 /* ld */, MCK_MemRegReg, 1 /* 0 */ },
1075 { 0, 87 /* ld.b */, MCK_MemRegReg, 1 /* 0 */ },
1076 { 0, 87 /* ld.b */, MCK_MemSpls, 1 /* 0 */ },
1077 { 0, 92 /* ld.h */, MCK_MemRegReg, 1 /* 0 */ },
1078 { 0, 92 /* ld.h */, MCK_MemSpls, 1 /* 0 */ },
1079 { 0, 179 /* st */, MCK_MemImm, 2 /* 1 */ },
1080 { 0, 179 /* st */, MCK_MemRegImm, 2 /* 1 */ },
1081 { 0, 179 /* st */, MCK_MemRegReg, 2 /* 1 */ },
1082 { 0, 182 /* st.b */, MCK_MemRegReg, 2 /* 1 */ },
1083 { 0, 182 /* st.b */, MCK_MemSpls, 2 /* 1 */ },
1084 { 0, 187 /* st.h */, MCK_MemRegReg, 2 /* 1 */ },
1085 { 0, 187 /* st.h */, MCK_MemSpls, 2 /* 1 */ },
1086 { 0, 221 /* uld */, MCK_MemRegImm, 1 /* 0 */ },
1087 { 0, 221 /* uld */, MCK_MemRegReg, 1 /* 0 */ },
1088 { 0, 225 /* uld.b */, MCK_MemRegReg, 1 /* 0 */ },
1089 { 0, 225 /* uld.b */, MCK_MemSpls, 1 /* 0 */ },
1090 { 0, 231 /* uld.h */, MCK_MemRegReg, 1 /* 0 */ },
1091 { 0, 231 /* uld.h */, MCK_MemSpls, 1 /* 0 */ },
1092};
1093
1094OperandMatchResultTy LanaiAsmParser::
1095tryCustomParseOperand(OperandVector &Operands,
1096 unsigned MCK) {
1097
1098 switch(MCK) {
1099 case MCK_MemImm:
1100 return parseMemoryOperand(Operands);
1101 case MCK_MemRegImm:
1102 return parseMemoryOperand(Operands);
1103 case MCK_MemRegReg:
1104 return parseMemoryOperand(Operands);
1105 case MCK_MemSpls:
1106 return parseMemoryOperand(Operands);
1107 default:
1108 return MatchOperand_NoMatch;
1109 }
1110 return MatchOperand_NoMatch;
1111}
1112
1113OperandMatchResultTy LanaiAsmParser::
1114MatchOperandParserImpl(OperandVector &Operands,
1115 StringRef Mnemonic) {
1116 // Get the current feature set.
1117 uint64_t AvailableFeatures = getAvailableFeatures();
1118
1119 // Get the next operand index.
1120 unsigned NextOpNum = Operands.size() - 1;
1121 // Search the table.
1122 auto MnemonicRange =
1123 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1124 Mnemonic, LessOpcodeOperand());
1125
1126 if (MnemonicRange.first == MnemonicRange.second)
1127 return MatchOperand_NoMatch;
1128
1129 for (const OperandMatchEntry *it = MnemonicRange.first,
1130 *ie = MnemonicRange.second; it != ie; ++it) {
1131 // equal_range guarantees that instruction mnemonic matches.
1132 assert(Mnemonic == it->getMnemonic())((Mnemonic == it->getMnemonic()) ? static_cast<void>
(0) : __assert_fail ("Mnemonic == it->getMnemonic()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn301135/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 1132, __PRETTY_FUNCTION__))
;
1133
1134 // check if the available features match
1135 if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
1136 continue;
1137 }
1138
1139 // check if the operand in question has a custom parser.
1140 if (!(it->OperandMask & (1 << NextOpNum)))
1141 continue;
1142
1143 // call custom parse method to handle the operand
1144 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
1145 if (Result != MatchOperand_NoMatch)
1146 return Result;
1147 }
1148
1149 // Okay, we had no match.
1150 return MatchOperand_NoMatch;
1151}
1152
1153#endif // GET_MATCHER_IMPLEMENTATION
1154