Bug Summary

File:build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc
Warning:line 771, column 10
Excessive padding in 'struct llvm::(anonymous namespace)::MatchEntry' (2 padding bytes, where 0 is optimal). Optimal fields order: Opcode, Mnemonic, ConvertFn, RequiredFeatures, Classes, consider reordering the fields or adding explicit padding members

Annotated Source Code

1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Assembly Matcher Source Fragment *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9
10#ifdef GET_ASSEMBLER_HEADER
11#undef GET_ASSEMBLER_HEADER
12 // This should be included into the middle of the declaration of
13 // your subclasses implementation of MCTargetAsmParser.
14 uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16 const OperandVector &Operands);
17 void convertToMapAndConstraints(unsigned Kind,
18 const OperandVector &Operands) override;
19 unsigned MatchInstructionImpl(const OperandVector &Operands,
20 MCInst &Inst,
21 uint64_t &ErrorInfo, bool matchingInlineAsm,
22 unsigned VariantID = 0);
23 OperandMatchResultTy MatchOperandParserImpl(
24 OperandVector &Operands,
25 StringRef Mnemonic);
26 OperandMatchResultTy tryCustomParseOperand(
27 OperandVector &Operands,
28 unsigned MCK);
29
30#endif // GET_ASSEMBLER_HEADER_INFO
31
32
33#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
34#undef GET_OPERAND_DIAGNOSTIC_TYPES
35
36#endif // GET_OPERAND_DIAGNOSTIC_TYPES
37
38
39#ifdef GET_REGISTER_MATCHER
40#undef GET_REGISTER_MATCHER
41
42// Flags for subtarget features that participate in instruction matching.
43enum SubtargetFeatureFlag : uint8_t {
44 Feature_None = 0
45};
46
47static unsigned MatchRegisterName(StringRef Name) {
48 switch (Name.size()) {
49 default: break;
50 case 2: // 15 strings to match.
51 switch (Name[0]) {
52 default: break;
53 case 'f': // 1 string to match.
54 if (Name[1] != 'p')
55 break;
56 return 1; // "fp"
57 case 'p': // 1 string to match.
58 if (Name[1] != 'c')
59 break;
60 return 2; // "pc"
61 case 'r': // 11 strings to match.
62 switch (Name[1]) {
63 default: break;
64 case '0': // 1 string to match.
65 return 7; // "r0"
66 case '1': // 1 string to match.
67 return 8; // "r1"
68 case '2': // 1 string to match.
69 return 9; // "r2"
70 case '3': // 1 string to match.
71 return 10; // "r3"
72 case '4': // 1 string to match.
73 return 11; // "r4"
74 case '5': // 1 string to match.
75 return 12; // "r5"
76 case '6': // 1 string to match.
77 return 13; // "r6"
78 case '7': // 1 string to match.
79 return 14; // "r7"
80 case '8': // 1 string to match.
81 return 15; // "r8"
82 case '9': // 1 string to match.
83 return 16; // "r9"
84 case 'v': // 1 string to match.
85 return 4; // "rv"
86 }
87 break;
88 case 's': // 2 strings to match.
89 switch (Name[1]) {
90 default: break;
91 case 'p': // 1 string to match.
92 return 5; // "sp"
93 case 'w': // 1 string to match.
94 return 6; // "sw"
95 }
96 break;
97 }
98 break;
99 case 3: // 25 strings to match.
100 if (Name[0] != 'r')
101 break;
102 switch (Name[1]) {
103 default: break;
104 case '1': // 10 strings to match.
105 switch (Name[2]) {
106 default: break;
107 case '0': // 1 string to match.
108 return 17; // "r10"
109 case '1': // 1 string to match.
110 return 18; // "r11"
111 case '2': // 1 string to match.
112 return 19; // "r12"
113 case '3': // 1 string to match.
114 return 20; // "r13"
115 case '4': // 1 string to match.
116 return 21; // "r14"
117 case '5': // 1 string to match.
118 return 22; // "r15"
119 case '6': // 1 string to match.
120 return 23; // "r16"
121 case '7': // 1 string to match.
122 return 24; // "r17"
123 case '8': // 1 string to match.
124 return 25; // "r18"
125 case '9': // 1 string to match.
126 return 26; // "r19"
127 }
128 break;
129 case '2': // 10 strings to match.
130 switch (Name[2]) {
131 default: break;
132 case '0': // 1 string to match.
133 return 27; // "r20"
134 case '1': // 1 string to match.
135 return 28; // "r21"
136 case '2': // 1 string to match.
137 return 29; // "r22"
138 case '3': // 1 string to match.
139 return 30; // "r23"
140 case '4': // 1 string to match.
141 return 31; // "r24"
142 case '5': // 1 string to match.
143 return 32; // "r25"
144 case '6': // 1 string to match.
145 return 33; // "r26"
146 case '7': // 1 string to match.
147 return 34; // "r27"
148 case '8': // 1 string to match.
149 return 35; // "r28"
150 case '9': // 1 string to match.
151 return 36; // "r29"
152 }
153 break;
154 case '3': // 2 strings to match.
155 switch (Name[2]) {
156 default: break;
157 case '0': // 1 string to match.
158 return 37; // "r30"
159 case '1': // 1 string to match.
160 return 38; // "r31"
161 }
162 break;
163 case 'c': // 1 string to match.
164 if (Name[2] != 'a')
165 break;
166 return 3; // "rca"
167 case 'r': // 2 strings to match.
168 switch (Name[2]) {
169 default: break;
170 case '1': // 1 string to match.
171 return 39; // "rr1"
172 case '2': // 1 string to match.
173 return 40; // "rr2"
174 }
175 break;
176 }
177 break;
178 }
179 return 0;
180}
181
182#endif // GET_REGISTER_MATCHER
183
184
185#ifdef GET_SUBTARGET_FEATURE_NAME
186#undef GET_SUBTARGET_FEATURE_NAME
187
188// User-level names for subtarget features that participate in
189// instruction matching.
190static const char *getSubtargetFeatureName(uint64_t Val) {
191 return "(unknown)";
192}
193
194#endif // GET_SUBTARGET_FEATURE_NAME
195
196
197#ifdef GET_MATCHER_IMPLEMENTATION
198#undef GET_MATCHER_IMPLEMENTATION
199
200namespace {
201enum OperatorConversionKind {
202 CVT_Done,
203 CVT_Reg,
204 CVT_Tied,
205 CVT_95_addImmOperands,
206 CVT_95_Reg,
207 CVT_95_addHiImm16Operands,
208 CVT_95_addLoImm16Operands,
209 CVT_95_addCondCodeOperands,
210 CVT_95_addHiImm16AndOperands,
211 CVT_95_addLoImm16AndOperands,
212 CVT_95_addBrTargetOperands,
213 CVT_95_addMemImmOperands,
214 CVT_95_addMemRegImmOperands,
215 CVT_95_addMemRegRegOperands,
216 CVT_95_addMemSplsOperands,
217 CVT_regR0,
218 CVT_imm_95_0,
219 CVT_regR1,
220 CVT_95_addLoImm21Operands,
221 CVT_95_addImmShiftOperands,
222 CVT_NUM_CONVERTERS
223};
224
225enum InstructionConversionKind {
226 Convert__Imm1_0__Imm1_1,
227 Convert__Reg1_0__Reg1_1,
228 Convert__Reg1_2__Reg1_0__HiImm161_1,
229 Convert__Reg1_2__Reg1_0__LoImm161_1,
230 Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0,
231 Convert__Reg1_2__Reg1_0__HiImm16And1_1,
232 Convert__Reg1_2__Reg1_0__LoImm16And1_1,
233 Convert__Reg1_1__Imm1_0,
234 Convert__BrTarget1_1__Imm1_0,
235 Convert__Imm1_2__Imm1_0,
236 Convert__Reg1_1__Reg1_3__Imm1_0,
237 Convert__Reg1_0,
238 Convert__BrTarget1_0,
239 Convert__Reg1_1__MemImm1_0,
240 Convert__Reg1_1__MemRegImm3_0,
241 Convert__Reg1_1__MemRegReg3_0,
242 Convert_NoOperands,
243 Convert__Reg1_1__MemSpls3_0,
244 Convert__Reg1_1__Reg1_0,
245 Convert__Reg1_1__Reg1_0__regR0__imm_95_0,
246 Convert__Reg1_1__regR1__HiImm16And1_0,
247 Convert__Reg1_1__regR0__HiImm161_0,
248 Convert__Reg1_1__regR1__LoImm16And1_0,
249 Convert__Reg1_1__regR0__LoImm161_0,
250 Convert__Reg1_1__LoImm211_0,
251 Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0,
252 Convert__Reg1_2__Reg1_0__ImmShift1_1,
253 Convert__Reg1_0__MemImm1_1,
254 Convert__Reg1_0__MemRegImm3_1,
255 Convert__Reg1_0__MemRegReg3_1,
256 Convert__Reg1_0__MemSpls3_1,
257 CVT_NUM_SIGNATURES
258};
259
260} // end anonymous namespace
261
262static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
263 // Convert__Imm1_0__Imm1_1
264 { CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
265 // Convert__Reg1_0__Reg1_1
266 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
267 // Convert__Reg1_2__Reg1_0__HiImm161_1
268 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16Operands, 2, CVT_Done },
269 // Convert__Reg1_2__Reg1_0__LoImm161_1
270 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16Operands, 2, CVT_Done },
271 // Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0
272 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addCondCodeOperands, 1, CVT_Done },
273 // Convert__Reg1_2__Reg1_0__HiImm16And1_1
274 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addHiImm16AndOperands, 2, CVT_Done },
275 // Convert__Reg1_2__Reg1_0__LoImm16And1_1
276 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addLoImm16AndOperands, 2, CVT_Done },
277 // Convert__Reg1_1__Imm1_0
278 { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
279 // Convert__BrTarget1_1__Imm1_0
280 { CVT_95_addBrTargetOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
281 // Convert__Imm1_2__Imm1_0
282 { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
283 // Convert__Reg1_1__Reg1_3__Imm1_0
284 { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_Done },
285 // Convert__Reg1_0
286 { CVT_95_Reg, 1, CVT_Done },
287 // Convert__BrTarget1_0
288 { CVT_95_addBrTargetOperands, 1, CVT_Done },
289 // Convert__Reg1_1__MemImm1_0
290 { CVT_95_Reg, 2, CVT_95_addMemImmOperands, 1, CVT_Done },
291 // Convert__Reg1_1__MemRegImm3_0
292 { CVT_95_Reg, 2, CVT_95_addMemRegImmOperands, 1, CVT_Done },
293 // Convert__Reg1_1__MemRegReg3_0
294 { CVT_95_Reg, 2, CVT_95_addMemRegRegOperands, 1, CVT_Done },
295 // Convert_NoOperands
296 { CVT_Done },
297 // Convert__Reg1_1__MemSpls3_0
298 { CVT_95_Reg, 2, CVT_95_addMemSplsOperands, 1, CVT_Done },
299 // Convert__Reg1_1__Reg1_0
300 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
301 // Convert__Reg1_1__Reg1_0__regR0__imm_95_0
302 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regR0, 0, CVT_imm_95_0, 0, CVT_Done },
303 // Convert__Reg1_1__regR1__HiImm16And1_0
304 { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addHiImm16AndOperands, 1, CVT_Done },
305 // Convert__Reg1_1__regR0__HiImm161_0
306 { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addHiImm16Operands, 1, CVT_Done },
307 // Convert__Reg1_1__regR1__LoImm16And1_0
308 { CVT_95_Reg, 2, CVT_regR1, 0, CVT_95_addLoImm16AndOperands, 1, CVT_Done },
309 // Convert__Reg1_1__regR0__LoImm161_0
310 { CVT_95_Reg, 2, CVT_regR0, 0, CVT_95_addLoImm16Operands, 1, CVT_Done },
311 // Convert__Reg1_1__LoImm211_0
312 { CVT_95_Reg, 2, CVT_95_addLoImm21Operands, 1, CVT_Done },
313 // Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0
314 { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
315 // Convert__Reg1_2__Reg1_0__ImmShift1_1
316 { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmShiftOperands, 2, CVT_Done },
317 // Convert__Reg1_0__MemImm1_1
318 { CVT_95_Reg, 1, CVT_95_addMemImmOperands, 2, CVT_Done },
319 // Convert__Reg1_0__MemRegImm3_1
320 { CVT_95_Reg, 1, CVT_95_addMemRegImmOperands, 2, CVT_Done },
321 // Convert__Reg1_0__MemRegReg3_1
322 { CVT_95_Reg, 1, CVT_95_addMemRegRegOperands, 2, CVT_Done },
323 // Convert__Reg1_0__MemSpls3_1
324 { CVT_95_Reg, 1, CVT_95_addMemSplsOperands, 2, CVT_Done },
325};
326
327void LanaiAsmParser::
328convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
329 const OperandVector &Operands) {
330 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!")((Kind < CVT_NUM_SIGNATURES && "Invalid signature!"
) ? static_cast<void> (0) : __assert_fail ("Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 330, __PRETTY_FUNCTION__))
;
331 const uint8_t *Converter = ConversionTable[Kind];
332 unsigned OpIdx;
333 Inst.setOpcode(Opcode);
334 for (const uint8_t *p = Converter; *p; p+= 2) {
335 OpIdx = *(p + 1);
336 switch (*p) {
337 default: llvm_unreachable("invalid conversion entry!")::llvm::llvm_unreachable_internal("invalid conversion entry!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 337)
;
338 case CVT_Reg:
339 static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
340 break;
341 case CVT_Tied:
342 Inst.addOperand(Inst.getOperand(OpIdx));
343 break;
344 case CVT_95_addImmOperands:
345 static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1);
346 break;
347 case CVT_95_Reg:
348 static_cast<LanaiOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1);
349 break;
350 case CVT_95_addHiImm16Operands:
351 static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16Operands(Inst, 1);
352 break;
353 case CVT_95_addLoImm16Operands:
354 static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16Operands(Inst, 1);
355 break;
356 case CVT_95_addCondCodeOperands:
357 static_cast<LanaiOperand&>(*Operands[OpIdx]).addCondCodeOperands(Inst, 1);
358 break;
359 case CVT_95_addHiImm16AndOperands:
360 static_cast<LanaiOperand&>(*Operands[OpIdx]).addHiImm16AndOperands(Inst, 1);
361 break;
362 case CVT_95_addLoImm16AndOperands:
363 static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm16AndOperands(Inst, 1);
364 break;
365 case CVT_95_addBrTargetOperands:
366 static_cast<LanaiOperand&>(*Operands[OpIdx]).addBrTargetOperands(Inst, 1);
367 break;
368 case CVT_95_addMemImmOperands:
369 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemImmOperands(Inst, 1);
370 break;
371 case CVT_95_addMemRegImmOperands:
372 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegImmOperands(Inst, 3);
373 break;
374 case CVT_95_addMemRegRegOperands:
375 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemRegRegOperands(Inst, 3);
376 break;
377 case CVT_95_addMemSplsOperands:
378 static_cast<LanaiOperand&>(*Operands[OpIdx]).addMemSplsOperands(Inst, 3);
379 break;
380 case CVT_regR0:
381 Inst.addOperand(MCOperand::createReg(Lanai::R0));
382 break;
383 case CVT_imm_95_0:
384 Inst.addOperand(MCOperand::createImm(0));
385 break;
386 case CVT_regR1:
387 Inst.addOperand(MCOperand::createReg(Lanai::R1));
388 break;
389 case CVT_95_addLoImm21Operands:
390 static_cast<LanaiOperand&>(*Operands[OpIdx]).addLoImm21Operands(Inst, 1);
391 break;
392 case CVT_95_addImmShiftOperands:
393 static_cast<LanaiOperand&>(*Operands[OpIdx]).addImmShiftOperands(Inst, 1);
394 break;
395 }
396 }
397}
398
399void LanaiAsmParser::
400convertToMapAndConstraints(unsigned Kind,
401 const OperandVector &Operands) {
402 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!")((Kind < CVT_NUM_SIGNATURES && "Invalid signature!"
) ? static_cast<void> (0) : __assert_fail ("Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 402, __PRETTY_FUNCTION__))
;
403 unsigned NumMCOperands = 0;
404 const uint8_t *Converter = ConversionTable[Kind];
405 for (const uint8_t *p = Converter; *p; p+= 2) {
406 switch (*p) {
407 default: llvm_unreachable("invalid conversion entry!")::llvm::llvm_unreachable_internal("invalid conversion entry!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 407)
;
408 case CVT_Reg:
409 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
410 Operands[*(p + 1)]->setConstraint("r");
411 ++NumMCOperands;
412 break;
413 case CVT_Tied:
414 ++NumMCOperands;
415 break;
416 case CVT_95_addImmOperands:
417 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
418 Operands[*(p + 1)]->setConstraint("m");
419 NumMCOperands += 1;
420 break;
421 case CVT_95_Reg:
422 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
423 Operands[*(p + 1)]->setConstraint("r");
424 NumMCOperands += 1;
425 break;
426 case CVT_95_addHiImm16Operands:
427 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
428 Operands[*(p + 1)]->setConstraint("m");
429 NumMCOperands += 1;
430 break;
431 case CVT_95_addLoImm16Operands:
432 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
433 Operands[*(p + 1)]->setConstraint("m");
434 NumMCOperands += 1;
435 break;
436 case CVT_95_addCondCodeOperands:
437 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
438 Operands[*(p + 1)]->setConstraint("m");
439 NumMCOperands += 1;
440 break;
441 case CVT_95_addHiImm16AndOperands:
442 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
443 Operands[*(p + 1)]->setConstraint("m");
444 NumMCOperands += 1;
445 break;
446 case CVT_95_addLoImm16AndOperands:
447 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
448 Operands[*(p + 1)]->setConstraint("m");
449 NumMCOperands += 1;
450 break;
451 case CVT_95_addBrTargetOperands:
452 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
453 Operands[*(p + 1)]->setConstraint("m");
454 NumMCOperands += 1;
455 break;
456 case CVT_95_addMemImmOperands:
457 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
458 Operands[*(p + 1)]->setConstraint("m");
459 NumMCOperands += 1;
460 break;
461 case CVT_95_addMemRegImmOperands:
462 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
463 Operands[*(p + 1)]->setConstraint("m");
464 NumMCOperands += 3;
465 break;
466 case CVT_95_addMemRegRegOperands:
467 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
468 Operands[*(p + 1)]->setConstraint("m");
469 NumMCOperands += 3;
470 break;
471 case CVT_95_addMemSplsOperands:
472 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
473 Operands[*(p + 1)]->setConstraint("m");
474 NumMCOperands += 3;
475 break;
476 case CVT_regR0:
477 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
478 Operands[*(p + 1)]->setConstraint("m");
479 ++NumMCOperands;
480 break;
481 case CVT_imm_95_0:
482 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
483 Operands[*(p + 1)]->setConstraint("");
484 ++NumMCOperands;
485 break;
486 case CVT_regR1:
487 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
488 Operands[*(p + 1)]->setConstraint("m");
489 ++NumMCOperands;
490 break;
491 case CVT_95_addLoImm21Operands:
492 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
493 Operands[*(p + 1)]->setConstraint("m");
494 NumMCOperands += 1;
495 break;
496 case CVT_95_addImmShiftOperands:
497 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
498 Operands[*(p + 1)]->setConstraint("m");
499 NumMCOperands += 1;
500 break;
501 }
502 }
503}
504
505namespace {
506
507/// MatchClassKind - The kinds of classes which participate in
508/// instruction matching.
509enum MatchClassKind {
510 InvalidMatchClass = 0,
511 OptionalMatchClass = 1,
512 MCK__EXCLAIM_, // '!'
513 MCK__PCT_fp, // '%fp'
514 MCK__PCT_pc, // '%pc'
515 MCK__MINUS_4, // '-4'
516 MCK__DOT_r, // '.r'
517 MCK__91_, // '['
518 MCK__93_, // ']'
519 MCK_add, // 'add'
520 MCK_return, // 'return'
521 MCK_CCR, // register class 'CCR'
522 MCK_Reg1, // derived register class
523 MCK_GPR, // register class 'GPR'
524 MCK_BrTarget, // user defined class 'BrTargetAsmOperand'
525 MCK_CallTarget, // user defined class 'CallTargetAsmOperand'
526 MCK_CondCode, // user defined class 'CondCodeOperand'
527 MCK_HiImm16And, // user defined class 'HiImm16AndAsmOperand'
528 MCK_HiImm16, // user defined class 'HiImm16AsmOperand'
529 MCK_Imm10, // user defined class 'Imm10AsmOperand'
530 MCK_Imm, // user defined class 'ImmAsmOperand'
531 MCK_ImmShift, // user defined class 'ImmShiftAsmOperand'
532 MCK_LoImm16And, // user defined class 'LoImm16AndAsmOperand'
533 MCK_LoImm16, // user defined class 'LoImm16AsmOperand'
534 MCK_LoImm21, // user defined class 'LoImm21AsmOperand'
535 MCK_MemImm, // user defined class 'MemImmAsmOperand'
536 MCK_MemRegImm, // user defined class 'MemRegImmAsmOperand'
537 MCK_MemRegReg, // user defined class 'MemRegRegAsmOperand'
538 MCK_MemSpls, // user defined class 'MemSplsAsmOperand'
539 NumMatchClassKinds
540};
541
542}
543
544static MatchClassKind matchTokenString(StringRef Name) {
545 switch (Name.size()) {
546 default: break;
547 case 1: // 3 strings to match.
548 switch (Name[0]) {
549 default: break;
550 case '!': // 1 string to match.
551 return MCK__EXCLAIM_; // "!"
552 case '[': // 1 string to match.
553 return MCK__91_; // "["
554 case ']': // 1 string to match.
555 return MCK__93_; // "]"
556 }
557 break;
558 case 2: // 2 strings to match.
559 switch (Name[0]) {
560 default: break;
561 case '-': // 1 string to match.
562 if (Name[1] != '4')
563 break;
564 return MCK__MINUS_4; // "-4"
565 case '.': // 1 string to match.
566 if (Name[1] != 'r')
567 break;
568 return MCK__DOT_r; // ".r"
569 }
570 break;
571 case 3: // 3 strings to match.
572 switch (Name[0]) {
573 default: break;
574 case '%': // 2 strings to match.
575 switch (Name[1]) {
576 default: break;
577 case 'f': // 1 string to match.
578 if (Name[2] != 'p')
579 break;
580 return MCK__PCT_fp; // "%fp"
581 case 'p': // 1 string to match.
582 if (Name[2] != 'c')
583 break;
584 return MCK__PCT_pc; // "%pc"
585 }
586 break;
587 case 'a': // 1 string to match.
588 if (memcmp(Name.data()+1, "dd", 2) != 0)
589 break;
590 return MCK_add; // "add"
591 }
592 break;
593 case 6: // 1 string to match.
594 if (memcmp(Name.data()+0, "return", 6) != 0)
595 break;
596 return MCK_return; // "return"
597 }
598 return InvalidMatchClass;
599}
600
601/// isSubclass - Compute whether \p A is a subclass of \p B.
602static bool isSubclass(MatchClassKind A, MatchClassKind B) {
603 if (A == B)
604 return true;
605
606 switch (A) {
607 default:
608 return false;
609
610 case MCK_Reg1:
611 return B == MCK_GPR;
612 }
613}
614
615static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
616 LanaiOperand &Operand = (LanaiOperand&)GOp;
617 if (Kind == InvalidMatchClass)
618 return MCTargetAsmParser::Match_InvalidOperand;
619
620 if (Operand.isToken())
621 return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
622 MCTargetAsmParser::Match_Success :
623 MCTargetAsmParser::Match_InvalidOperand;
624
625 switch (Kind) {
626 default: break;
627 // 'BrTarget' class
628 case MCK_BrTarget:
629 if (Operand.isBrTarget())
630 return MCTargetAsmParser::Match_Success;
631 break;
632 // 'CallTarget' class
633 case MCK_CallTarget:
634 if (Operand.isCallTarget())
635 return MCTargetAsmParser::Match_Success;
636 break;
637 // 'CondCode' class
638 case MCK_CondCode:
639 if (Operand.isCondCode())
640 return MCTargetAsmParser::Match_Success;
641 break;
642 // 'HiImm16And' class
643 case MCK_HiImm16And:
644 if (Operand.isHiImm16And())
645 return MCTargetAsmParser::Match_Success;
646 break;
647 // 'HiImm16' class
648 case MCK_HiImm16:
649 if (Operand.isHiImm16())
650 return MCTargetAsmParser::Match_Success;
651 break;
652 // 'Imm10' class
653 case MCK_Imm10:
654 if (Operand.isImm10())
655 return MCTargetAsmParser::Match_Success;
656 break;
657 // 'Imm' class
658 case MCK_Imm:
659 if (Operand.isImm())
660 return MCTargetAsmParser::Match_Success;
661 break;
662 // 'ImmShift' class
663 case MCK_ImmShift:
664 if (Operand.isImmShift())
665 return MCTargetAsmParser::Match_Success;
666 break;
667 // 'LoImm16And' class
668 case MCK_LoImm16And:
669 if (Operand.isLoImm16And())
670 return MCTargetAsmParser::Match_Success;
671 break;
672 // 'LoImm16' class
673 case MCK_LoImm16:
674 if (Operand.isLoImm16())
675 return MCTargetAsmParser::Match_Success;
676 break;
677 // 'LoImm21' class
678 case MCK_LoImm21:
679 if (Operand.isLoImm21())
680 return MCTargetAsmParser::Match_Success;
681 break;
682 // 'MemImm' class
683 case MCK_MemImm:
684 if (Operand.isMemImm())
685 return MCTargetAsmParser::Match_Success;
686 break;
687 // 'MemRegImm' class
688 case MCK_MemRegImm:
689 if (Operand.isMemRegImm())
690 return MCTargetAsmParser::Match_Success;
691 break;
692 // 'MemRegReg' class
693 case MCK_MemRegReg:
694 if (Operand.isMemRegReg())
695 return MCTargetAsmParser::Match_Success;
696 break;
697 // 'MemSpls' class
698 case MCK_MemSpls:
699 if (Operand.isMemSpls())
700 return MCTargetAsmParser::Match_Success;
701 break;
702 } // end switch (Kind)
703
704 if (Operand.isReg()) {
705 MatchClassKind OpKind;
706 switch (Operand.getReg()) {
707 default: OpKind = InvalidMatchClass; break;
708 case Lanai::R0: OpKind = MCK_GPR; break;
709 case Lanai::R1: OpKind = MCK_GPR; break;
710 case Lanai::R2: OpKind = MCK_GPR; break;
711 case Lanai::R3: OpKind = MCK_GPR; break;
712 case Lanai::R4: OpKind = MCK_GPR; break;
713 case Lanai::R5: OpKind = MCK_GPR; break;
714 case Lanai::R6: OpKind = MCK_GPR; break;
715 case Lanai::R7: OpKind = MCK_GPR; break;
716 case Lanai::R8: OpKind = MCK_GPR; break;
717 case Lanai::R9: OpKind = MCK_GPR; break;
718 case Lanai::R10: OpKind = MCK_GPR; break;
719 case Lanai::R11: OpKind = MCK_GPR; break;
720 case Lanai::R12: OpKind = MCK_GPR; break;
721 case Lanai::R13: OpKind = MCK_GPR; break;
722 case Lanai::R14: OpKind = MCK_GPR; break;
723 case Lanai::R15: OpKind = MCK_GPR; break;
724 case Lanai::R16: OpKind = MCK_GPR; break;
725 case Lanai::R17: OpKind = MCK_GPR; break;
726 case Lanai::R18: OpKind = MCK_GPR; break;
727 case Lanai::R19: OpKind = MCK_GPR; break;
728 case Lanai::R20: OpKind = MCK_GPR; break;
729 case Lanai::R21: OpKind = MCK_GPR; break;
730 case Lanai::R22: OpKind = MCK_GPR; break;
731 case Lanai::R23: OpKind = MCK_GPR; break;
732 case Lanai::R24: OpKind = MCK_GPR; break;
733 case Lanai::R25: OpKind = MCK_GPR; break;
734 case Lanai::R26: OpKind = MCK_GPR; break;
735 case Lanai::R27: OpKind = MCK_GPR; break;
736 case Lanai::R28: OpKind = MCK_GPR; break;
737 case Lanai::R29: OpKind = MCK_GPR; break;
738 case Lanai::R30: OpKind = MCK_GPR; break;
739 case Lanai::R31: OpKind = MCK_GPR; break;
740 case Lanai::PC: OpKind = MCK_Reg1; break;
741 case Lanai::SP: OpKind = MCK_Reg1; break;
742 case Lanai::FP: OpKind = MCK_Reg1; break;
743 case Lanai::RV: OpKind = MCK_Reg1; break;
744 case Lanai::RR1: OpKind = MCK_Reg1; break;
745 case Lanai::RR2: OpKind = MCK_Reg1; break;
746 case Lanai::RCA: OpKind = MCK_Reg1; break;
747 case Lanai::SR: OpKind = MCK_CCR; break;
748 }
749 return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
750 MCTargetAsmParser::Match_InvalidOperand;
751 }
752
753 return MCTargetAsmParser::Match_InvalidOperand;
754}
755
756uint64_t LanaiAsmParser::
757ComputeAvailableFeatures(const FeatureBitset& FB) const {
758 uint64_t Features = 0;
759 return Features;
760}
761
762static const char *const MnemonicTable =
763 "\021#ADJCALLSTACKDOWN\017#ADJCALLSTACKUP\014#ADJDYNALLOC\003add\005add."
764 "f\004addc\006addc.f\003and\005and.f\001b\002bt\002ld\004ld.b\004ld.h\005"
765 "leadz\005log_0\005log_1\005log_2\005log_3\005log_4\003mov\003nop\002or\004"
766 "or.f\004popc\001s\004sel.\002sh\004sh.f\003sha\005sha.f\002st\004st.b\004"
767 "st.h\003sub\005sub.f\004subb\006subb.f\006trailz\003uld\005uld.b\005uld"
768 ".h\003xor\005xor.f";
769
770namespace {
771 struct MatchEntry {
Excessive padding in 'struct llvm::(anonymous namespace)::MatchEntry' (2 padding bytes, where 0 is optimal). Optimal fields order: Opcode, Mnemonic, ConvertFn, RequiredFeatures, Classes, consider reordering the fields or adding explicit padding members
772 uint8_t Mnemonic;
773 uint16_t Opcode;
774 uint8_t ConvertFn;
775 uint8_t RequiredFeatures;
776 uint8_t Classes[7];
777 StringRef getMnemonic() const {
778 return StringRef(MnemonicTable + Mnemonic + 1,
779 MnemonicTable[Mnemonic]);
780 }
781 };
782
783 // Predicate for searching for an opcode.
784 struct LessOpcode {
785 bool operator()(const MatchEntry &LHS, StringRef RHS) {
786 return LHS.getMnemonic() < RHS;
787 }
788 bool operator()(StringRef LHS, const MatchEntry &RHS) {
789 return LHS < RHS.getMnemonic();
790 }
791 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
792 return LHS.getMnemonic() < RHS.getMnemonic();
793 }
794 };
795} // end anonymous namespace.
796
797static const MatchEntry MatchTable0[] = {
798 { 0 /* #ADJCALLSTACKDOWN */, Lanai::ADJCALLSTACKDOWN, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
799 { 18 /* #ADJCALLSTACKUP */, Lanai::ADJCALLSTACKUP, Convert__Imm1_0__Imm1_1, 0, { MCK_Imm, MCK_Imm }, },
800 { 34 /* #ADJDYNALLOC */, Lanai::ADJDYNALLOC, Convert__Reg1_0__Reg1_1, 0, { MCK_GPR, MCK_GPR }, },
801 { 47 /* add */, Lanai::ADD_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
802 { 47 /* add */, Lanai::ADD_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
803 { 47 /* add */, Lanai::ADD_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
804 { 51 /* add.f */, Lanai::ADD_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
805 { 51 /* add.f */, Lanai::ADD_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
806 { 51 /* add.f */, Lanai::ADD_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
807 { 57 /* addc */, Lanai::ADDC_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
808 { 57 /* addc */, Lanai::ADDC_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
809 { 57 /* addc */, Lanai::ADDC_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
810 { 62 /* addc.f */, Lanai::ADDC_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
811 { 62 /* addc.f */, Lanai::ADDC_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
812 { 62 /* addc.f */, Lanai::ADDC_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
813 { 69 /* and */, Lanai::AND_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
814 { 69 /* and */, Lanai::AND_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
815 { 69 /* and */, Lanai::AND_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
816 { 73 /* and.f */, Lanai::AND_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm16And1_1, 0, { MCK_GPR, MCK_HiImm16And, MCK_GPR }, },
817 { 73 /* and.f */, Lanai::AND_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm16And1_1, 0, { MCK_GPR, MCK_LoImm16And, MCK_GPR }, },
818 { 73 /* and.f */, Lanai::AND_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
819 { 79 /* b */, Lanai::BRIND_CC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
820 { 79 /* b */, Lanai::BRCC, Convert__BrTarget1_1__Imm1_0, 0, { MCK_Imm, MCK_BrTarget }, },
821 { 79 /* b */, Lanai::BRR, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__DOT_r, MCK_Imm }, },
822 { 79 /* b */, Lanai::BRIND_CCA, Convert__Reg1_1__Reg1_3__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_add, MCK_GPR }, },
823 { 81 /* bt */, Lanai::JR, Convert__Reg1_0, 0, { MCK_GPR }, },
824 { 81 /* bt */, Lanai::BT, Convert__BrTarget1_0, 0, { MCK_BrTarget }, },
825 { 84 /* ld */, Lanai::LDADDR, Convert__Reg1_1__MemImm1_0, 0, { MCK_MemImm, MCK_GPR }, },
826 { 84 /* ld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
827 { 84 /* ld */, Lanai::LDW_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
828 { 84 /* ld */, Lanai::RET, Convert_NoOperands, 0, { MCK__MINUS_4, MCK__91_, MCK__PCT_fp, MCK__93_, MCK__PCT_pc, MCK__EXCLAIM_, MCK_return }, },
829 { 87 /* ld.b */, Lanai::LDBs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
830 { 87 /* ld.b */, Lanai::LDBs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
831 { 92 /* ld.h */, Lanai::LDHs_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
832 { 92 /* ld.h */, Lanai::LDHs_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
833 { 97 /* leadz */, Lanai::LEADZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
834 { 103 /* log_0 */, Lanai::LOG0, Convert_NoOperands, 0, { }, },
835 { 109 /* log_1 */, Lanai::LOG1, Convert_NoOperands, 0, { }, },
836 { 115 /* log_2 */, Lanai::LOG2, Convert_NoOperands, 0, { }, },
837 { 121 /* log_3 */, Lanai::LOG3, Convert_NoOperands, 0, { }, },
838 { 127 /* log_4 */, Lanai::LOG4, Convert_NoOperands, 0, { }, },
839 { 133 /* mov */, Lanai::ADD_R, Convert__Reg1_1__Reg1_0__regR0__imm_95_0, 0, { MCK_GPR, MCK_GPR }, },
840 { 133 /* mov */, Lanai::AND_I_HI, Convert__Reg1_1__regR1__HiImm16And1_0, 0, { MCK_HiImm16And, MCK_GPR }, },
841 { 133 /* mov */, Lanai::ADD_I_HI, Convert__Reg1_1__regR0__HiImm161_0, 0, { MCK_HiImm16, MCK_GPR }, },
842 { 133 /* mov */, Lanai::AND_I_LO, Convert__Reg1_1__regR1__LoImm16And1_0, 0, { MCK_LoImm16And, MCK_GPR }, },
843 { 133 /* mov */, Lanai::ADD_I_LO, Convert__Reg1_1__regR0__LoImm161_0, 0, { MCK_LoImm16, MCK_GPR }, },
844 { 133 /* mov */, Lanai::SLI, Convert__Reg1_1__LoImm211_0, 0, { MCK_LoImm21, MCK_GPR }, },
845 { 137 /* nop */, Lanai::NOP, Convert_NoOperands, 0, { }, },
846 { 141 /* or */, Lanai::OR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
847 { 141 /* or */, Lanai::OR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
848 { 141 /* or */, Lanai::OR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
849 { 144 /* or.f */, Lanai::OR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
850 { 144 /* or.f */, Lanai::OR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
851 { 144 /* or.f */, Lanai::OR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
852 { 149 /* popc */, Lanai::POPC, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
853 { 154 /* s */, Lanai::SCC, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_GPR }, },
854 { 156 /* sel. */, Lanai::SELECT, Convert__Reg1_3__Reg1_1__Reg1_2__Imm1_0, 0, { MCK_Imm, MCK_GPR, MCK_GPR, MCK_GPR }, },
855 { 161 /* sh */, Lanai::SL_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
856 { 161 /* sh */, Lanai::SHL_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
857 { 164 /* sh.f */, Lanai::SL_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
858 { 164 /* sh.f */, Lanai::SHL_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
859 { 169 /* sha */, Lanai::SA_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
860 { 169 /* sha */, Lanai::SRA_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
861 { 173 /* sha.f */, Lanai::SA_F_I, Convert__Reg1_2__Reg1_0__ImmShift1_1, 0, { MCK_GPR, MCK_ImmShift, MCK_GPR }, },
862 { 173 /* sha.f */, Lanai::SRA_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
863 { 179 /* st */, Lanai::STADDR, Convert__Reg1_0__MemImm1_1, 0, { MCK_GPR, MCK_MemImm }, },
864 { 179 /* st */, Lanai::SW_RI, Convert__Reg1_0__MemRegImm3_1, 0, { MCK_GPR, MCK_MemRegImm }, },
865 { 179 /* st */, Lanai::SW_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
866 { 182 /* st.b */, Lanai::STB_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
867 { 182 /* st.b */, Lanai::STB_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
868 { 187 /* st.h */, Lanai::STH_RR, Convert__Reg1_0__MemRegReg3_1, 0, { MCK_GPR, MCK_MemRegReg }, },
869 { 187 /* st.h */, Lanai::STH_RI, Convert__Reg1_0__MemSpls3_1, 0, { MCK_GPR, MCK_MemSpls }, },
870 { 192 /* sub */, Lanai::SUB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
871 { 192 /* sub */, Lanai::SUB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
872 { 192 /* sub */, Lanai::SUB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
873 { 196 /* sub.f */, Lanai::SUB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
874 { 196 /* sub.f */, Lanai::SUB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
875 { 196 /* sub.f */, Lanai::SUB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
876 { 202 /* subb */, Lanai::SUBB_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
877 { 202 /* subb */, Lanai::SUBB_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
878 { 202 /* subb */, Lanai::SUBB_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
879 { 207 /* subb.f */, Lanai::SUBB_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
880 { 207 /* subb.f */, Lanai::SUBB_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
881 { 207 /* subb.f */, Lanai::SUBB_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
882 { 214 /* trailz */, Lanai::TRAILZ, Convert__Reg1_1__Reg1_0, 0, { MCK_GPR, MCK_GPR }, },
883 { 221 /* uld */, Lanai::LDW_RI, Convert__Reg1_1__MemRegImm3_0, 0, { MCK_MemRegImm, MCK_GPR }, },
884 { 221 /* uld */, Lanai::LDWz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
885 { 225 /* uld.b */, Lanai::LDBz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
886 { 225 /* uld.b */, Lanai::LDBz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
887 { 231 /* uld.h */, Lanai::LDHz_RR, Convert__Reg1_1__MemRegReg3_0, 0, { MCK_MemRegReg, MCK_GPR }, },
888 { 231 /* uld.h */, Lanai::LDHz_RI, Convert__Reg1_1__MemSpls3_0, 0, { MCK_MemSpls, MCK_GPR }, },
889 { 237 /* xor */, Lanai::XOR_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
890 { 237 /* xor */, Lanai::XOR_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
891 { 237 /* xor */, Lanai::XOR_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
892 { 241 /* xor.f */, Lanai::XOR_F_I_HI, Convert__Reg1_2__Reg1_0__HiImm161_1, 0, { MCK_GPR, MCK_HiImm16, MCK_GPR }, },
893 { 241 /* xor.f */, Lanai::XOR_F_I_LO, Convert__Reg1_2__Reg1_0__LoImm161_1, 0, { MCK_GPR, MCK_LoImm16, MCK_GPR }, },
894 { 241 /* xor.f */, Lanai::XOR_F_R, Convert__Reg1_3__Reg1_1__Reg1_2__CondCode1_0, 0, { MCK_CondCode, MCK_GPR, MCK_GPR, MCK_GPR }, },
895};
896
897unsigned LanaiAsmParser::
898MatchInstructionImpl(const OperandVector &Operands,
899 MCInst &Inst, uint64_t &ErrorInfo,
900 bool matchingInlineAsm, unsigned VariantID) {
901 // Eliminate obvious mismatches.
902 if (Operands.size() > 8) {
903 ErrorInfo = 8;
904 return Match_InvalidOperand;
905 }
906
907 // Get the current feature set.
908 uint64_t AvailableFeatures = getAvailableFeatures();
909
910 // Get the instruction mnemonic, which is the first token.
911 StringRef Mnemonic = ((LanaiOperand&)*Operands[0]).getToken();
912
913 // Some state to try to produce better error messages.
914 bool HadMatchOtherThanFeatures = false;
915 bool HadMatchOtherThanPredicate = false;
916 unsigned RetCode = Match_InvalidOperand;
917 uint64_t MissingFeatures = ~0ULL;
918 // Set ErrorInfo to the operand that mismatches if it is
919 // wrong for all instances of the instruction.
920 ErrorInfo = ~0ULL;
921 // Find the appropriate table for this asm variant.
922 const MatchEntry *Start, *End;
923 switch (VariantID) {
924 default: llvm_unreachable("invalid variant!")::llvm::llvm_unreachable_internal("invalid variant!", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 924)
;
925 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
926 }
927 // Search the table.
928 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
929
930 // Return a more specific error code if no mnemonics match.
931 if (MnemonicRange.first == MnemonicRange.second)
932 return Match_MnemonicFail;
933
934 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
935 it != ie; ++it) {
936 // equal_range guarantees that instruction mnemonic matches.
937 assert(Mnemonic == it->getMnemonic())((Mnemonic == it->getMnemonic()) ? static_cast<void>
(0) : __assert_fail ("Mnemonic == it->getMnemonic()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 937, __PRETTY_FUNCTION__))
;
938 bool OperandsValid = true;
939 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; ++FormalIdx) {
940 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
941 if (ActualIdx >= Operands.size()) {
942 OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);
943 if (!OperandsValid) ErrorInfo = ActualIdx;
944 break;
945 }
946 MCParsedAsmOperand &Actual = *Operands[ActualIdx];
947 unsigned Diag = validateOperandClass(Actual, Formal);
948 if (Diag == Match_Success) {
949 ++ActualIdx;
950 continue;
951 }
952 // If the generic handler indicates an invalid operand
953 // failure, check for a special case.
954 if (Diag == Match_InvalidOperand) {
955 Diag = validateTargetOperandClass(Actual, Formal);
956 if (Diag == Match_Success) {
957 ++ActualIdx;
958 continue;
959 }
960 }
961 // If current formal operand wasn't matched and it is optional
962 // then try to match next formal operand
963 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
964 continue;
965 }
966 // If this operand is broken for all of the instances of this
967 // mnemonic, keep track of it so we can report loc info.
968 // If we already had a match that only failed due to a
969 // target predicate, that diagnostic is preferred.
970 if (!HadMatchOtherThanPredicate &&
971 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
972 ErrorInfo = ActualIdx;
973 // InvalidOperand is the default. Prefer specificity.
974 if (Diag != Match_InvalidOperand)
975 RetCode = Diag;
976 }
977 // Otherwise, just reject this instance of the mnemonic.
978 OperandsValid = false;
979 break;
980 }
981
982 if (!OperandsValid) continue;
983 if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
984 HadMatchOtherThanFeatures = true;
985 uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
986 if (countPopulation(NewMissingFeatures) <=
987 countPopulation(MissingFeatures))
988 MissingFeatures = NewMissingFeatures;
989 continue;
990 }
991
992 Inst.clear();
993
994 Inst.setOpcode(it->Opcode);
995 // We have a potential match but have not rendered the operands.
996 // Check the target predicate to handle any context sensitive
997 // constraints.
998 // For example, Ties that are referenced multiple times must be
999 // checked here to ensure the input is the same for each match
1000 // constraints. If we leave it any later the ties will have been
1001 // canonicalized
1002 unsigned MatchResult;
1003 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1004 Inst.clear();
1005 RetCode = MatchResult;
1006 HadMatchOtherThanPredicate = true;
1007 continue;
1008 }
1009
1010 if (matchingInlineAsm) {
1011 convertToMapAndConstraints(it->ConvertFn, Operands);
1012 return Match_Success;
1013 }
1014
1015 // We have selected a definite instruction, convert the parsed
1016 // operands into the appropriate MCInst.
1017 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1018
1019 // We have a potential match. Check the target predicate to
1020 // handle any context sensitive constraints.
1021 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1022 Inst.clear();
1023 RetCode = MatchResult;
1024 HadMatchOtherThanPredicate = true;
1025 continue;
1026 }
1027
1028 return Match_Success;
1029 }
1030
1031 // Okay, we had no match. Try to return a useful error code.
1032 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1033 return RetCode;
1034
1035 // Missing feature matches return which features were missing
1036 ErrorInfo = MissingFeatures;
1037 return Match_MissingFeature;
1038}
1039
1040namespace {
1041 struct OperandMatchEntry {
1042 uint8_t RequiredFeatures;
1043 uint8_t Mnemonic;
1044 uint8_t Class;
1045 uint8_t OperandMask;
1046
1047 StringRef getMnemonic() const {
1048 return StringRef(MnemonicTable + Mnemonic + 1,
1049 MnemonicTable[Mnemonic]);
1050 }
1051 };
1052
1053 // Predicate for searching for an opcode.
1054 struct LessOpcodeOperand {
1055 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
1056 return LHS.getMnemonic() < RHS;
1057 }
1058 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
1059 return LHS < RHS.getMnemonic();
1060 }
1061 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
1062 return LHS.getMnemonic() < RHS.getMnemonic();
1063 }
1064 };
1065} // end anonymous namespace.
1066
1067static const OperandMatchEntry OperandMatchTable[20] = {
1068 /* Operand List Mask, Mnemonic, Operand Class, Features */
1069 { 0, 84 /* ld */, MCK_MemImm, 1 /* 0 */ },
1070 { 0, 84 /* ld */, MCK_MemRegImm, 1 /* 0 */ },
1071 { 0, 84 /* ld */, MCK_MemRegReg, 1 /* 0 */ },
1072 { 0, 87 /* ld.b */, MCK_MemRegReg, 1 /* 0 */ },
1073 { 0, 87 /* ld.b */, MCK_MemSpls, 1 /* 0 */ },
1074 { 0, 92 /* ld.h */, MCK_MemRegReg, 1 /* 0 */ },
1075 { 0, 92 /* ld.h */, MCK_MemSpls, 1 /* 0 */ },
1076 { 0, 179 /* st */, MCK_MemImm, 2 /* 1 */ },
1077 { 0, 179 /* st */, MCK_MemRegImm, 2 /* 1 */ },
1078 { 0, 179 /* st */, MCK_MemRegReg, 2 /* 1 */ },
1079 { 0, 182 /* st.b */, MCK_MemRegReg, 2 /* 1 */ },
1080 { 0, 182 /* st.b */, MCK_MemSpls, 2 /* 1 */ },
1081 { 0, 187 /* st.h */, MCK_MemRegReg, 2 /* 1 */ },
1082 { 0, 187 /* st.h */, MCK_MemSpls, 2 /* 1 */ },
1083 { 0, 221 /* uld */, MCK_MemRegImm, 1 /* 0 */ },
1084 { 0, 221 /* uld */, MCK_MemRegReg, 1 /* 0 */ },
1085 { 0, 225 /* uld.b */, MCK_MemRegReg, 1 /* 0 */ },
1086 { 0, 225 /* uld.b */, MCK_MemSpls, 1 /* 0 */ },
1087 { 0, 231 /* uld.h */, MCK_MemRegReg, 1 /* 0 */ },
1088 { 0, 231 /* uld.h */, MCK_MemSpls, 1 /* 0 */ },
1089};
1090
1091OperandMatchResultTy LanaiAsmParser::
1092tryCustomParseOperand(OperandVector &Operands,
1093 unsigned MCK) {
1094
1095 switch(MCK) {
1096 case MCK_MemImm:
1097 return parseMemoryOperand(Operands);
1098 case MCK_MemRegImm:
1099 return parseMemoryOperand(Operands);
1100 case MCK_MemRegReg:
1101 return parseMemoryOperand(Operands);
1102 case MCK_MemSpls:
1103 return parseMemoryOperand(Operands);
1104 default:
1105 return MatchOperand_NoMatch;
1106 }
1107 return MatchOperand_NoMatch;
1108}
1109
1110OperandMatchResultTy LanaiAsmParser::
1111MatchOperandParserImpl(OperandVector &Operands,
1112 StringRef Mnemonic) {
1113 // Get the current feature set.
1114 uint64_t AvailableFeatures = getAvailableFeatures();
1115
1116 // Get the next operand index.
1117 unsigned NextOpNum = Operands.size() - 1;
1118 // Search the table.
1119 auto MnemonicRange =
1120 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
1121 Mnemonic, LessOpcodeOperand());
1122
1123 if (MnemonicRange.first == MnemonicRange.second)
1124 return MatchOperand_NoMatch;
1125
1126 for (const OperandMatchEntry *it = MnemonicRange.first,
1127 *ie = MnemonicRange.second; it != ie; ++it) {
1128 // equal_range guarantees that instruction mnemonic matches.
1129 assert(Mnemonic == it->getMnemonic())((Mnemonic == it->getMnemonic()) ? static_cast<void>
(0) : __assert_fail ("Mnemonic == it->getMnemonic()", "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn303373/build-llvm/lib/Target/Lanai/LanaiGenAsmMatcher.inc"
, 1129, __PRETTY_FUNCTION__))
;
1130
1131 // check if the available features match
1132 if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
1133 continue;
1134 }
1135
1136 // check if the operand in question has a custom parser.
1137 if (!(it->OperandMask & (1 << NextOpNum)))
1138 continue;
1139
1140 // call custom parse method to handle the operand
1141 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
1142 if (Result != MatchOperand_NoMatch)
1143 return Result;
1144 }
1145
1146 // Okay, we had no match.
1147 return MatchOperand_NoMatch;
1148}
1149
1150#endif // GET_MATCHER_IMPLEMENTATION
1151