Bug Summary

File:lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Warning:line 1000, column 39
The result of the '<<' expression is undefined

Annotated Source Code

1//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the SelectionDAG::LegalizeVectors method.
11//
12// The vector legalizer looks for vector operations which might need to be
13// scalarized and legalizes them. This is a separate step from Legalize because
14// scalarizing can introduce illegal types. For example, suppose we have an
15// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17// operation, which introduces nodes with the illegal type i64 which must be
18// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19// the operation must be unrolled, which introduces nodes with the illegal
20// type i8 which must be promoted.
21//
22// This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23// or operations that happen to take a vector which are custom-lowered;
24// the legalization for such operations never produces nodes
25// with illegal types, so it's okay to put off legalizing them until
26// SelectionDAG::Legalize runs.
27//
28//===----------------------------------------------------------------------===//
29
30#include "llvm/CodeGen/SelectionDAG.h"
31#include "llvm/Target/TargetLowering.h"
32using namespace llvm;
33
34namespace {
35class VectorLegalizer {
36 SelectionDAG& DAG;
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
39
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
44
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
49 if (From != To)
50 LegalizedNodes.insert(std::make_pair(To, To));
51 }
52
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
55
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
58
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
61
62 /// \brief Implement expand-based legalization of vector operations.
63 ///
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
67
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
69 /// FSUB isn't legal.
70 ///
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
74
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
77
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
79 ///
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
82 /// undef.
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
84
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
86 ///
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
89 /// extension.
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
91
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
93 ///
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
97
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
100
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108 SDValue ExpandFSUB(SDValue Op);
109 SDValue ExpandBITREVERSE(SDValue Op);
110 SDValue ExpandCTLZ(SDValue Op);
111 SDValue ExpandCTTZ_ZERO_UNDEF(SDValue Op);
112
113 /// \brief Implements vector promotion.
114 ///
115 /// This is essentially just bitcasting the operands to a different type and
116 /// bitcasting the result back to the original type.
117 SDValue Promote(SDValue Op);
118
119 /// \brief Implements [SU]INT_TO_FP vector promotion.
120 ///
121 /// This is a [zs]ext of the input operand to the next size up.
122 SDValue PromoteINT_TO_FP(SDValue Op);
123
124 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
125 ///
126 /// It is promoted to the next size up integer type. The result is then
127 /// truncated back to the original type.
128 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
129
130public:
131 /// \brief Begin legalizer the vector operations in the DAG.
132 bool Run();
133 VectorLegalizer(SelectionDAG& dag) :
134 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
135};
136
137bool VectorLegalizer::Run() {
138 // Before we start legalizing vector nodes, check if there are any vectors.
139 bool HasVectors = false;
140 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
141 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
142 // Check if the values of the nodes contain vectors. We don't need to check
143 // the operands because we are going to check their values at some point.
144 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
145 J != E; ++J)
146 HasVectors |= J->isVector();
147
148 // If we found a vector node we can start the legalization.
149 if (HasVectors)
150 break;
151 }
152
153 // If this basic block has no vectors then no need to legalize vectors.
154 if (!HasVectors)
155 return false;
156
157 // The legalize process is inherently a bottom-up recursive process (users
158 // legalize their uses before themselves). Given infinite stack space, we
159 // could just start legalizing on the root and traverse the whole graph. In
160 // practice however, this causes us to run out of stack space on large basic
161 // blocks. To avoid this problem, compute an ordering of the nodes where each
162 // node is only legalized after all of its operands are legalized.
163 DAG.AssignTopologicalOrder();
164 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
165 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
166 LegalizeOp(SDValue(&*I, 0));
167
168 // Finally, it's possible the root changed. Get the new root.
169 SDValue OldRoot = DAG.getRoot();
170 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?")((LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"
) ? static_cast<void> (0) : __assert_fail ("LegalizedNodes.count(OldRoot) && \"Root didn't get legalized?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 170, __PRETTY_FUNCTION__))
;
171 DAG.setRoot(LegalizedNodes[OldRoot]);
172
173 LegalizedNodes.clear();
174
175 // Remove dead nodes now.
176 DAG.RemoveDeadNodes();
177
178 return Changed;
179}
180
181SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
182 // Generic legalization: just pass the operand through.
183 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
184 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
185 return Result.getValue(Op.getResNo());
186}
187
188SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
189 // Note that LegalizeOp may be reentered even from single-use nodes, which
190 // means that we always must cache transformed nodes.
191 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
192 if (I != LegalizedNodes.end()) return I->second;
193
194 SDNode* Node = Op.getNode();
195
196 // Legalize the operands
197 SmallVector<SDValue, 8> Ops;
198 for (const SDValue &Op : Node->op_values())
199 Ops.push_back(LegalizeOp(Op));
200
201 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
202
203 bool HasVectorValue = false;
204 if (Op.getOpcode() == ISD::LOAD) {
205 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
206 ISD::LoadExtType ExtType = LD->getExtensionType();
207 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
208 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
209 LD->getMemoryVT())) {
210 default: llvm_unreachable("This action is not supported yet!")::llvm::llvm_unreachable_internal("This action is not supported yet!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 210)
;
211 case TargetLowering::Legal:
212 return TranslateLegalizeResults(Op, Result);
213 case TargetLowering::Custom:
214 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
215 if (Lowered == Result)
216 return TranslateLegalizeResults(Op, Lowered);
217 Changed = true;
218 if (Lowered->getNumValues() != Op->getNumValues()) {
219 // This expanded to something other than the load. Assume the
220 // lowering code took care of any chain values, and just handle the
221 // returned value.
222 assert(Result.getValue(1).use_empty() &&((Result.getValue(1).use_empty() && "There are still live users of the old chain!"
) ? static_cast<void> (0) : __assert_fail ("Result.getValue(1).use_empty() && \"There are still live users of the old chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 223, __PRETTY_FUNCTION__))
223 "There are still live users of the old chain!")((Result.getValue(1).use_empty() && "There are still live users of the old chain!"
) ? static_cast<void> (0) : __assert_fail ("Result.getValue(1).use_empty() && \"There are still live users of the old chain!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 223, __PRETTY_FUNCTION__))
;
224 return LegalizeOp(Lowered);
225 }
226 return TranslateLegalizeResults(Op, Lowered);
227 }
228 LLVM_FALLTHROUGH[[clang::fallthrough]];
229 case TargetLowering::Expand:
230 Changed = true;
231 return LegalizeOp(ExpandLoad(Op));
232 }
233 } else if (Op.getOpcode() == ISD::STORE) {
234 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
235 EVT StVT = ST->getMemoryVT();
236 MVT ValVT = ST->getValue().getSimpleValueType();
237 if (StVT.isVector() && ST->isTruncatingStore())
238 switch (TLI.getTruncStoreAction(ValVT, StVT)) {
239 default: llvm_unreachable("This action is not supported yet!")::llvm::llvm_unreachable_internal("This action is not supported yet!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 239)
;
240 case TargetLowering::Legal:
241 return TranslateLegalizeResults(Op, Result);
242 case TargetLowering::Custom: {
243 SDValue Lowered = TLI.LowerOperation(Result, DAG);
244 Changed = Lowered != Result;
245 return TranslateLegalizeResults(Op, Lowered);
246 }
247 case TargetLowering::Expand:
248 Changed = true;
249 return LegalizeOp(ExpandStore(Op));
250 }
251 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
252 HasVectorValue = true;
253
254 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
255 J != E;
256 ++J)
257 HasVectorValue |= J->isVector();
258 if (!HasVectorValue)
259 return TranslateLegalizeResults(Op, Result);
260
261 EVT QueryType;
262 switch (Op.getOpcode()) {
263 default:
264 return TranslateLegalizeResults(Op, Result);
265 case ISD::ADD:
266 case ISD::SUB:
267 case ISD::MUL:
268 case ISD::SDIV:
269 case ISD::UDIV:
270 case ISD::SREM:
271 case ISD::UREM:
272 case ISD::SDIVREM:
273 case ISD::UDIVREM:
274 case ISD::FADD:
275 case ISD::FSUB:
276 case ISD::FMUL:
277 case ISD::FDIV:
278 case ISD::FREM:
279 case ISD::AND:
280 case ISD::OR:
281 case ISD::XOR:
282 case ISD::SHL:
283 case ISD::SRA:
284 case ISD::SRL:
285 case ISD::ROTL:
286 case ISD::ROTR:
287 case ISD::BSWAP:
288 case ISD::BITREVERSE:
289 case ISD::CTLZ:
290 case ISD::CTTZ:
291 case ISD::CTLZ_ZERO_UNDEF:
292 case ISD::CTTZ_ZERO_UNDEF:
293 case ISD::CTPOP:
294 case ISD::SELECT:
295 case ISD::VSELECT:
296 case ISD::SELECT_CC:
297 case ISD::SETCC:
298 case ISD::ZERO_EXTEND:
299 case ISD::ANY_EXTEND:
300 case ISD::TRUNCATE:
301 case ISD::SIGN_EXTEND:
302 case ISD::FP_TO_SINT:
303 case ISD::FP_TO_UINT:
304 case ISD::FNEG:
305 case ISD::FABS:
306 case ISD::FMINNUM:
307 case ISD::FMAXNUM:
308 case ISD::FMINNAN:
309 case ISD::FMAXNAN:
310 case ISD::FCOPYSIGN:
311 case ISD::FSQRT:
312 case ISD::FSIN:
313 case ISD::FCOS:
314 case ISD::FPOWI:
315 case ISD::FPOW:
316 case ISD::FLOG:
317 case ISD::FLOG2:
318 case ISD::FLOG10:
319 case ISD::FEXP:
320 case ISD::FEXP2:
321 case ISD::FCEIL:
322 case ISD::FTRUNC:
323 case ISD::FRINT:
324 case ISD::FNEARBYINT:
325 case ISD::FROUND:
326 case ISD::FFLOOR:
327 case ISD::FP_ROUND:
328 case ISD::FP_EXTEND:
329 case ISD::FMA:
330 case ISD::SIGN_EXTEND_INREG:
331 case ISD::ANY_EXTEND_VECTOR_INREG:
332 case ISD::SIGN_EXTEND_VECTOR_INREG:
333 case ISD::ZERO_EXTEND_VECTOR_INREG:
334 case ISD::SMIN:
335 case ISD::SMAX:
336 case ISD::UMIN:
337 case ISD::UMAX:
338 case ISD::SMUL_LOHI:
339 case ISD::UMUL_LOHI:
340 QueryType = Node->getValueType(0);
341 break;
342 case ISD::FP_ROUND_INREG:
343 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
344 break;
345 case ISD::SINT_TO_FP:
346 case ISD::UINT_TO_FP:
347 QueryType = Node->getOperand(0).getValueType();
348 break;
349 case ISD::MSCATTER:
350 QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
351 break;
352 case ISD::MSTORE:
353 QueryType = cast<MaskedStoreSDNode>(Node)->getValue().getValueType();
354 break;
355 }
356
357 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
358 default: llvm_unreachable("This action is not supported yet!")::llvm::llvm_unreachable_internal("This action is not supported yet!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 358)
;
359 case TargetLowering::Promote:
360 Result = Promote(Op);
361 Changed = true;
362 break;
363 case TargetLowering::Legal:
364 break;
365 case TargetLowering::Custom: {
366 if (SDValue Tmp1 = TLI.LowerOperation(Op, DAG)) {
367 Result = Tmp1;
368 break;
369 }
370 LLVM_FALLTHROUGH[[clang::fallthrough]];
371 }
372 case TargetLowering::Expand:
373 Result = Expand(Op);
374 }
375
376 // Make sure that the generated code is itself legal.
377 if (Result != Op) {
378 Result = LegalizeOp(Result);
379 Changed = true;
380 }
381
382 // Note that LegalizeOp may be reentered even from single-use nodes, which
383 // means that we always must cache transformed nodes.
384 AddLegalizedOperand(Op, Result);
385 return Result;
386}
387
388SDValue VectorLegalizer::Promote(SDValue Op) {
389 // For a few operations there is a specific concept for promotion based on
390 // the operand's type.
391 switch (Op.getOpcode()) {
392 case ISD::SINT_TO_FP:
393 case ISD::UINT_TO_FP:
394 // "Promote" the operation by extending the operand.
395 return PromoteINT_TO_FP(Op);
396 case ISD::FP_TO_UINT:
397 case ISD::FP_TO_SINT:
398 // Promote the operation by extending the operand.
399 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
400 }
401
402 // There are currently two cases of vector promotion:
403 // 1) Bitcasting a vector of integers to a different type to a vector of the
404 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
405 // 2) Extending a vector of floats to a vector of the same number of larger
406 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
407 MVT VT = Op.getSimpleValueType();
408 assert(Op.getNode()->getNumValues() == 1 &&((Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"Can't promote a vector with multiple results!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 409, __PRETTY_FUNCTION__))
409 "Can't promote a vector with multiple results!")((Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"Can't promote a vector with multiple results!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 409, __PRETTY_FUNCTION__))
;
410 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
411 SDLoc dl(Op);
412 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
413
414 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
415 if (Op.getOperand(j).getValueType().isVector())
416 if (Op.getOperand(j)
417 .getValueType()
418 .getVectorElementType()
419 .isFloatingPoint() &&
420 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
421 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
422 else
423 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
424 else
425 Operands[j] = Op.getOperand(j);
426 }
427
428 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
429 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
430 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
431 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
432 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
433 else
434 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
435}
436
437SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
438 // INT_TO_FP operations may require the input operand be promoted even
439 // when the type is otherwise legal.
440 EVT VT = Op.getOperand(0).getValueType();
441 assert(Op.getNode()->getNumValues() == 1 &&((Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"Can't promote a vector with multiple results!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 442, __PRETTY_FUNCTION__))
442 "Can't promote a vector with multiple results!")((Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"Can't promote a vector with multiple results!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 442, __PRETTY_FUNCTION__))
;
443
444 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
445 // by widening the vector w/ the same element width and twice the number
446 // of elements. We want the other way around, the same number of elements,
447 // each twice the width.
448 //
449 // Increase the bitwidth of the element to the next pow-of-two
450 // (which is greater than 8 bits).
451
452 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
453 assert(NVT.isSimple() && "Promoting to a non-simple vector type!")((NVT.isSimple() && "Promoting to a non-simple vector type!"
) ? static_cast<void> (0) : __assert_fail ("NVT.isSimple() && \"Promoting to a non-simple vector type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 453, __PRETTY_FUNCTION__))
;
454 SDLoc dl(Op);
455 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
456
457 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
458 ISD::SIGN_EXTEND;
459 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
460 if (Op.getOperand(j).getValueType().isVector())
461 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
462 else
463 Operands[j] = Op.getOperand(j);
464 }
465
466 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
467}
468
469// For FP_TO_INT we promote the result type to a vector type with wider
470// elements and then truncate the result. This is different from the default
471// PromoteVector which uses bitcast to promote thus assumning that the
472// promoted vector type has the same overall size.
473SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
474 assert(Op.getNode()->getNumValues() == 1 &&((Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"Can't promote a vector with multiple results!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 475, __PRETTY_FUNCTION__))
475 "Can't promote a vector with multiple results!")((Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"
) ? static_cast<void> (0) : __assert_fail ("Op.getNode()->getNumValues() == 1 && \"Can't promote a vector with multiple results!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 475, __PRETTY_FUNCTION__))
;
476 EVT VT = Op.getValueType();
477
478 EVT NewVT;
479 unsigned NewOpc;
480 while (1) {
481 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
482 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!")((NewVT.isSimple() && "Promoting to a non-simple vector type!"
) ? static_cast<void> (0) : __assert_fail ("NewVT.isSimple() && \"Promoting to a non-simple vector type!\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 482, __PRETTY_FUNCTION__))
;
483 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
484 NewOpc = ISD::FP_TO_SINT;
485 break;
486 }
487 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
488 NewOpc = ISD::FP_TO_UINT;
489 break;
490 }
491 }
492
493 SDLoc loc(Op);
494 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
495 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
496}
497
498
499SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
500 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
501
502 EVT SrcVT = LD->getMemoryVT();
503 EVT SrcEltVT = SrcVT.getScalarType();
504 unsigned NumElem = SrcVT.getVectorNumElements();
505
506
507 SDValue NewChain;
508 SDValue Value;
509 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
510 SDLoc dl(Op);
511
512 SmallVector<SDValue, 8> Vals;
513 SmallVector<SDValue, 8> LoadChains;
514
515 EVT DstEltVT = LD->getValueType(0).getScalarType();
516 SDValue Chain = LD->getChain();
517 SDValue BasePTR = LD->getBasePtr();
518 ISD::LoadExtType ExtType = LD->getExtensionType();
519
520 // When elements in a vector is not byte-addressable, we cannot directly
521 // load each element by advancing pointer, which could only address bytes.
522 // Instead, we load all significant words, mask bits off, and concatenate
523 // them to form each element. Finally, they are extended to destination
524 // scalar type to build the destination vector.
525 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
526
527 assert(WideVT.isRound() &&((WideVT.isRound() && "Could not handle the sophisticated case when the widest integer is"
" not power of 2.") ? static_cast<void> (0) : __assert_fail
("WideVT.isRound() && \"Could not handle the sophisticated case when the widest integer is\" \" not power of 2.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 529, __PRETTY_FUNCTION__))
528 "Could not handle the sophisticated case when the widest integer is"((WideVT.isRound() && "Could not handle the sophisticated case when the widest integer is"
" not power of 2.") ? static_cast<void> (0) : __assert_fail
("WideVT.isRound() && \"Could not handle the sophisticated case when the widest integer is\" \" not power of 2.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 529, __PRETTY_FUNCTION__))
529 " not power of 2.")((WideVT.isRound() && "Could not handle the sophisticated case when the widest integer is"
" not power of 2.") ? static_cast<void> (0) : __assert_fail
("WideVT.isRound() && \"Could not handle the sophisticated case when the widest integer is\" \" not power of 2.\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 529, __PRETTY_FUNCTION__))
;
530 assert(WideVT.bitsGE(SrcEltVT) &&((WideVT.bitsGE(SrcEltVT) && "Type is not legalized?"
) ? static_cast<void> (0) : __assert_fail ("WideVT.bitsGE(SrcEltVT) && \"Type is not legalized?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 531, __PRETTY_FUNCTION__))
531 "Type is not legalized?")((WideVT.bitsGE(SrcEltVT) && "Type is not legalized?"
) ? static_cast<void> (0) : __assert_fail ("WideVT.bitsGE(SrcEltVT) && \"Type is not legalized?\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 531, __PRETTY_FUNCTION__))
;
532
533 unsigned WideBytes = WideVT.getStoreSize();
534 unsigned Offset = 0;
535 unsigned RemainingBytes = SrcVT.getStoreSize();
536 SmallVector<SDValue, 8> LoadVals;
537
538 while (RemainingBytes > 0) {
539 SDValue ScalarLoad;
540 unsigned LoadBytes = WideBytes;
541
542 if (RemainingBytes >= LoadBytes) {
543 ScalarLoad =
544 DAG.getLoad(WideVT, dl, Chain, BasePTR,
545 LD->getPointerInfo().getWithOffset(Offset),
546 MinAlign(LD->getAlignment(), Offset),
547 LD->getMemOperand()->getFlags(), LD->getAAInfo());
548 } else {
549 EVT LoadVT = WideVT;
550 while (RemainingBytes < LoadBytes) {
551 LoadBytes >>= 1; // Reduce the load size by half.
552 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
553 }
554 ScalarLoad =
555 DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
556 LD->getPointerInfo().getWithOffset(Offset), LoadVT,
557 MinAlign(LD->getAlignment(), Offset),
558 LD->getMemOperand()->getFlags(), LD->getAAInfo());
559 }
560
561 RemainingBytes -= LoadBytes;
562 Offset += LoadBytes;
563 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
564 DAG.getConstant(LoadBytes, dl,
565 BasePTR.getValueType()));
566
567 LoadVals.push_back(ScalarLoad.getValue(0));
568 LoadChains.push_back(ScalarLoad.getValue(1));
569 }
570
571 // Extract bits, pack and extend/trunc them into destination type.
572 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
573 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
574
575 unsigned BitOffset = 0;
576 unsigned WideIdx = 0;
577 unsigned WideBits = WideVT.getSizeInBits();
578
579 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
580 SDValue Lo, Hi, ShAmt;
581
582 if (BitOffset < WideBits) {
583 ShAmt = DAG.getConstant(
584 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
585 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
586 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
587 }
588
589 BitOffset += SrcEltBits;
590 if (BitOffset >= WideBits) {
591 WideIdx++;
592 BitOffset -= WideBits;
593 if (BitOffset > 0) {
594 ShAmt = DAG.getConstant(
595 SrcEltBits - BitOffset, dl,
596 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
597 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
598 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
599 }
600 }
601
602 if (Hi.getNode())
603 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
604
605 switch (ExtType) {
606 default: llvm_unreachable("Unknown extended-load op!")::llvm::llvm_unreachable_internal("Unknown extended-load op!"
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 606)
;
607 case ISD::EXTLOAD:
608 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
609 break;
610 case ISD::ZEXTLOAD:
611 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
612 break;
613 case ISD::SEXTLOAD:
614 ShAmt =
615 DAG.getConstant(WideBits - SrcEltBits, dl,
616 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
617 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
618 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
619 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
620 break;
621 }
622 Vals.push_back(Lo);
623 }
624
625 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
626 Value = DAG.getBuildVector(Op.getNode()->getValueType(0), dl, Vals);
627 } else {
628 SDValue Scalarized = TLI.scalarizeVectorLoad(LD, DAG);
629
630 NewChain = Scalarized.getValue(1);
631 Value = Scalarized.getValue(0);
632 }
633
634 AddLegalizedOperand(Op.getValue(0), Value);
635 AddLegalizedOperand(Op.getValue(1), NewChain);
636
637 return (Op.getResNo() ? NewChain : Value);
638}
639
640SDValue VectorLegalizer::ExpandStore(SDValue Op) {
641 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
642
643 EVT StVT = ST->getMemoryVT();
644 EVT MemSclVT = StVT.getScalarType();
645 unsigned ScalarSize = MemSclVT.getSizeInBits();
646
647 // Round odd types to the next pow of two.
648 if (!isPowerOf2_32(ScalarSize)) {
649 // FIXME: This is completely broken and inconsistent with ExpandLoad
650 // handling.
651
652 // For sub-byte element sizes, this ends up with 0 stride between elements,
653 // so the same element just gets re-written to the same location. There seem
654 // to be tests explicitly testing for this broken behavior though. tests
655 // for this broken behavior.
656
657 LLVMContext &Ctx = *DAG.getContext();
658
659 EVT NewMemVT
660 = EVT::getVectorVT(Ctx,
661 MemSclVT.getIntegerVT(Ctx, NextPowerOf2(ScalarSize)),
662 StVT.getVectorNumElements());
663
664 SDValue NewVectorStore = DAG.getTruncStore(
665 ST->getChain(), SDLoc(Op), ST->getValue(), ST->getBasePtr(),
666 ST->getPointerInfo(), NewMemVT, ST->getAlignment(),
667 ST->getMemOperand()->getFlags(), ST->getAAInfo());
668 ST = cast<StoreSDNode>(NewVectorStore.getNode());
669 }
670
671 SDValue TF = TLI.scalarizeVectorStore(ST, DAG);
672 AddLegalizedOperand(Op, TF);
673 return TF;
674}
675
676SDValue VectorLegalizer::Expand(SDValue Op) {
677 switch (Op->getOpcode()) {
678 case ISD::SIGN_EXTEND_INREG:
679 return ExpandSEXTINREG(Op);
680 case ISD::ANY_EXTEND_VECTOR_INREG:
681 return ExpandANY_EXTEND_VECTOR_INREG(Op);
682 case ISD::SIGN_EXTEND_VECTOR_INREG:
683 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
684 case ISD::ZERO_EXTEND_VECTOR_INREG:
685 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
686 case ISD::BSWAP:
687 return ExpandBSWAP(Op);
688 case ISD::VSELECT:
689 return ExpandVSELECT(Op);
690 case ISD::SELECT:
691 return ExpandSELECT(Op);
692 case ISD::UINT_TO_FP:
693 return ExpandUINT_TO_FLOAT(Op);
694 case ISD::FNEG:
695 return ExpandFNEG(Op);
696 case ISD::FSUB:
697 return ExpandFSUB(Op);
698 case ISD::SETCC:
699 return UnrollVSETCC(Op);
700 case ISD::BITREVERSE:
701 return ExpandBITREVERSE(Op);
702 case ISD::CTLZ:
703 case ISD::CTLZ_ZERO_UNDEF:
704 return ExpandCTLZ(Op);
705 case ISD::CTTZ_ZERO_UNDEF:
706 return ExpandCTTZ_ZERO_UNDEF(Op);
707 default:
708 return DAG.UnrollVectorOp(Op.getNode());
709 }
710}
711
712SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
713 // Lower a select instruction where the condition is a scalar and the
714 // operands are vectors. Lower this select to VSELECT and implement it
715 // using XOR AND OR. The selector bit is broadcasted.
716 EVT VT = Op.getValueType();
717 SDLoc DL(Op);
718
719 SDValue Mask = Op.getOperand(0);
720 SDValue Op1 = Op.getOperand(1);
721 SDValue Op2 = Op.getOperand(2);
722
723 assert(VT.isVector() && !Mask.getValueType().isVector()((VT.isVector() && !Mask.getValueType().isVector() &&
Op1.getValueType() == Op2.getValueType() && "Invalid type"
) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && !Mask.getValueType().isVector() && Op1.getValueType() == Op2.getValueType() && \"Invalid type\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 724, __PRETTY_FUNCTION__))
724 && Op1.getValueType() == Op2.getValueType() && "Invalid type")((VT.isVector() && !Mask.getValueType().isVector() &&
Op1.getValueType() == Op2.getValueType() && "Invalid type"
) ? static_cast<void> (0) : __assert_fail ("VT.isVector() && !Mask.getValueType().isVector() && Op1.getValueType() == Op2.getValueType() && \"Invalid type\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 724, __PRETTY_FUNCTION__))
;
725
726 // If we can't even use the basic vector operations of
727 // AND,OR,XOR, we will have to scalarize the op.
728 // Notice that the operation may be 'promoted' which means that it is
729 // 'bitcasted' to another type which is handled.
730 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
731 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
732 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
733 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
734 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
735 return DAG.UnrollVectorOp(Op.getNode());
736
737 // Generate a mask operand.
738 EVT MaskTy = VT.changeVectorElementTypeToInteger();
739
740 // What is the size of each element in the vector mask.
741 EVT BitTy = MaskTy.getScalarType();
742
743 Mask = DAG.getSelect(DL, BitTy, Mask,
744 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
745 BitTy),
746 DAG.getConstant(0, DL, BitTy));
747
748 // Broadcast the mask so that the entire vector is all-one or all zero.
749 Mask = DAG.getSplatBuildVector(MaskTy, DL, Mask);
750
751 // Bitcast the operands to be the same type as the mask.
752 // This is needed when we select between FP types because
753 // the mask is a vector of integers.
754 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
756
757 SDValue AllOnes = DAG.getConstant(
758 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
759 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
760
761 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
762 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
763 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
764 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
765}
766
767SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
768 EVT VT = Op.getValueType();
769
770 // Make sure that the SRA and SHL instructions are available.
771 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
772 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
773 return DAG.UnrollVectorOp(Op.getNode());
774
775 SDLoc DL(Op);
776 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
777
778 unsigned BW = VT.getScalarSizeInBits();
779 unsigned OrigBW = OrigTy.getScalarSizeInBits();
780 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
781
782 Op = Op.getOperand(0);
783 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
784 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
785}
786
787// Generically expand a vector anyext in register to a shuffle of the relevant
788// lanes into the appropriate locations, with other lanes left undef.
789SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
790 SDLoc DL(Op);
791 EVT VT = Op.getValueType();
792 int NumElements = VT.getVectorNumElements();
793 SDValue Src = Op.getOperand(0);
794 EVT SrcVT = Src.getValueType();
795 int NumSrcElements = SrcVT.getVectorNumElements();
796
797 // Build a base mask of undef shuffles.
798 SmallVector<int, 16> ShuffleMask;
799 ShuffleMask.resize(NumSrcElements, -1);
800
801 // Place the extended lanes into the correct locations.
802 int ExtLaneScale = NumSrcElements / NumElements;
803 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
804 for (int i = 0; i < NumElements; ++i)
805 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
806
807 return DAG.getNode(
808 ISD::BITCAST, DL, VT,
809 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
810}
811
812SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
813 SDLoc DL(Op);
814 EVT VT = Op.getValueType();
815 SDValue Src = Op.getOperand(0);
816 EVT SrcVT = Src.getValueType();
817
818 // First build an any-extend node which can be legalized above when we
819 // recurse through it.
820 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
821
822 // Now we need sign extend. Do this by shifting the elements. Even if these
823 // aren't legal operations, they have a better chance of being legalized
824 // without full scalarization than the sign extension does.
825 unsigned EltWidth = VT.getScalarSizeInBits();
826 unsigned SrcEltWidth = SrcVT.getScalarSizeInBits();
827 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
828 return DAG.getNode(ISD::SRA, DL, VT,
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
830 ShiftAmount);
831}
832
833// Generically expand a vector zext in register to a shuffle of the relevant
834// lanes into the appropriate locations, a blend of zero into the high bits,
835// and a bitcast to the wider element type.
836SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
837 SDLoc DL(Op);
838 EVT VT = Op.getValueType();
839 int NumElements = VT.getVectorNumElements();
840 SDValue Src = Op.getOperand(0);
841 EVT SrcVT = Src.getValueType();
842 int NumSrcElements = SrcVT.getVectorNumElements();
843
844 // Build up a zero vector to blend into this one.
845 SDValue Zero = DAG.getConstant(0, DL, SrcVT);
846
847 // Shuffle the incoming lanes into the correct position, and pull all other
848 // lanes from the zero vector.
849 SmallVector<int, 16> ShuffleMask;
850 ShuffleMask.reserve(NumSrcElements);
851 for (int i = 0; i < NumSrcElements; ++i)
852 ShuffleMask.push_back(i);
853
854 int ExtLaneScale = NumSrcElements / NumElements;
855 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
856 for (int i = 0; i < NumElements; ++i)
857 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
858
859 return DAG.getNode(ISD::BITCAST, DL, VT,
860 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
861}
862
863static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) {
864 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
865 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
866 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
867 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
868}
869
870SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
871 EVT VT = Op.getValueType();
872
873 // Generate a byte wise shuffle mask for the BSWAP.
874 SmallVector<int, 16> ShuffleMask;
875 createBSWAPShuffleMask(VT, ShuffleMask);
876 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
877
878 // Only emit a shuffle if the mask is legal.
879 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
880 return DAG.UnrollVectorOp(Op.getNode());
881
882 SDLoc DL(Op);
883 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
884 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT), ShuffleMask);
885 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
886}
887
888SDValue VectorLegalizer::ExpandBITREVERSE(SDValue Op) {
889 EVT VT = Op.getValueType();
890
891 // If we have the scalar operation, it's probably cheaper to unroll it.
892 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
893 return DAG.UnrollVectorOp(Op.getNode());
894
895 // If the vector element width is a whole number of bytes, test if its legal
896 // to BSWAP shuffle the bytes and then perform the BITREVERSE on the byte
897 // vector. This greatly reduces the number of bit shifts necessary.
898 unsigned ScalarSizeInBits = VT.getScalarSizeInBits();
899 if (ScalarSizeInBits > 8 && (ScalarSizeInBits % 8) == 0) {
900 SmallVector<int, 16> BSWAPMask;
901 createBSWAPShuffleMask(VT, BSWAPMask);
902
903 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, BSWAPMask.size());
904 if (TLI.isShuffleMaskLegal(BSWAPMask, ByteVT) &&
905 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
906 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
907 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
908 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
909 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
910 SDLoc DL(Op);
911 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
912 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
913 BSWAPMask);
914 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
915 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
916 }
917 }
918
919 // If we have the appropriate vector bit operations, it is better to use them
920 // than unrolling and expanding each component.
921 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
922 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
923 !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
924 !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
925 return DAG.UnrollVectorOp(Op.getNode());
926
927 // Let LegalizeDAG handle this later.
928 return Op;
929}
930
931SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
932 // Implement VSELECT in terms of XOR, AND, OR
933 // on platforms which do not support blend natively.
934 SDLoc DL(Op);
935
936 SDValue Mask = Op.getOperand(0);
937 SDValue Op1 = Op.getOperand(1);
938 SDValue Op2 = Op.getOperand(2);
939
940 EVT VT = Mask.getValueType();
941
942 // If we can't even use the basic vector operations of
943 // AND,OR,XOR, we will have to scalarize the op.
944 // Notice that the operation may be 'promoted' which means that it is
945 // 'bitcasted' to another type which is handled.
946 // This operation also isn't safe with AND, OR, XOR when the boolean
947 // type is 0/1 as we need an all ones vector constant to mask with.
948 // FIXME: Sign extend 1 to all ones if thats legal on the target.
949 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
950 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
951 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
952 TLI.getBooleanContents(Op1.getValueType()) !=
953 TargetLowering::ZeroOrNegativeOneBooleanContent)
954 return DAG.UnrollVectorOp(Op.getNode());
955
956 // If the mask and the type are different sizes, unroll the vector op. This
957 // can occur when getSetCCResultType returns something that is different in
958 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
959 if (VT.getSizeInBits() != Op1.getValueSizeInBits())
960 return DAG.UnrollVectorOp(Op.getNode());
961
962 // Bitcast the operands to be the same type as the mask.
963 // This is needed when we select between FP types because
964 // the mask is a vector of integers.
965 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
966 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
967
968 SDValue AllOnes = DAG.getConstant(
969 APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT);
970 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
971
972 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
973 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
974 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
975 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
976}
977
978SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
979 EVT VT = Op.getOperand(0).getValueType();
980 SDLoc DL(Op);
981
982 // Make sure that the SINT_TO_FP and SRL instructions are available.
983 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
1
Taking false branch
984 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
985 return DAG.UnrollVectorOp(Op.getNode());
986
987 unsigned BW = VT.getScalarSizeInBits();
988 assert((BW == 64 || BW == 32) &&(((BW == 64 || BW == 32) && "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide"
) ? static_cast<void> (0) : __assert_fail ("(BW == 64 || BW == 32) && \"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 989, __PRETTY_FUNCTION__))
989 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide")(((BW == 64 || BW == 32) && "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide"
) ? static_cast<void> (0) : __assert_fail ("(BW == 64 || BW == 32) && \"Elements in vector-UINT_TO_FP must be 32 or 64 bits wide\""
, "/tmp/buildd/llvm-toolchain-snapshot-5.0~svn306458/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp"
, 989, __PRETTY_FUNCTION__))
;
990
991 SDValue HalfWord = DAG.getConstant(BW / 2, DL, VT);
992
993 // Constants to clear the upper part of the word.
994 // Notice that we can also use SHL+SHR, but using a constant is slightly
995 // faster on x86.
996 uint64_t HWMask = (BW == 64) ? 0x00000000FFFFFFFF : 0x0000FFFF;
2
'?' condition is true
997 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
998
999 // Two to the power of half-word-size.
1000 SDValue TWOHW = DAG.getConstantFP(1 << (BW / 2), DL, Op.getValueType());
3
The result of the '<<' expression is undefined
1001
1002 // Clear upper part of LO, lower HI
1003 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1004 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1005
1006 // Convert hi and lo to floats
1007 // Convert the hi part back to the upper values
1008 // TODO: Can any fast-math-flags be set on these nodes?
1009 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1010 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1011 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1012
1013 // Add the two halves
1014 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1015}
1016
1017SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1018 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1019 SDLoc DL(Op);
1020 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1021 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1022 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1023 Zero, Op.getOperand(0));
1024 }
1025 return DAG.UnrollVectorOp(Op.getNode());
1026}
1027
1028SDValue VectorLegalizer::ExpandFSUB(SDValue Op) {
1029 // For floating-point values, (a-b) is the same as a+(-b). If FNEG is legal,
1030 // we can defer this to operation legalization where it will be lowered as
1031 // a+(-b).
1032 EVT VT = Op.getValueType();
1033 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
1034 TLI.isOperationLegalOrCustom(ISD::FADD, VT))
1035 return Op; // Defer to LegalizeDAG
1036
1037 return DAG.UnrollVectorOp(Op.getNode());
1038}
1039
1040SDValue VectorLegalizer::ExpandCTLZ(SDValue Op) {
1041 EVT VT = Op.getValueType();
1042 unsigned NumBitsPerElt = VT.getScalarSizeInBits();
1043
1044 // If the non-ZERO_UNDEF version is supported we can use that instead.
1045 if (Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF &&
1046 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) {
1047 SDLoc DL(Op);
1048 return DAG.getNode(ISD::CTLZ, DL, Op.getValueType(), Op.getOperand(0));
1049 }
1050
1051 // If CTPOP is available we can lower with a CTPOP based method:
1052 // u16 ctlz(u16 x) {
1053 // x |= (x >> 1);
1054 // x |= (x >> 2);
1055 // x |= (x >> 4);
1056 // x |= (x >> 8);
1057 // return ctpop(~x);
1058 // }
1059 // Ref: "Hacker's Delight" by Henry Warren
1060 if (isPowerOf2_32(NumBitsPerElt) &&
1061 TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
1062 TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&
1063 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT) &&
1064 TLI.isOperationLegalOrCustomOrPromote(ISD::XOR, VT)) {
1065 SDLoc DL(Op);
1066 SDValue Res = Op.getOperand(0);
1067 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
1068
1069 for (unsigned i = 1; i != NumBitsPerElt; i *= 2)
1070 Res = DAG.getNode(
1071 ISD::OR, DL, VT, Res,
1072 DAG.getNode(ISD::SRL, DL, VT, Res, DAG.getConstant(i, DL, ShiftTy)));
1073
1074 Res = DAG.getNOT(DL, Res, VT);
1075 return DAG.getNode(ISD::CTPOP, DL, VT, Res);
1076 }
1077
1078 // Otherwise go ahead and unroll.
1079 return DAG.UnrollVectorOp(Op.getNode());
1080}
1081
1082SDValue VectorLegalizer::ExpandCTTZ_ZERO_UNDEF(SDValue Op) {
1083 // If the non-ZERO_UNDEF version is supported we can use that instead.
1084 if (TLI.isOperationLegalOrCustom(ISD::CTTZ, Op.getValueType())) {
1085 SDLoc DL(Op);
1086 return DAG.getNode(ISD::CTTZ, DL, Op.getValueType(), Op.getOperand(0));
1087 }
1088
1089 // Otherwise go ahead and unroll.
1090 return DAG.UnrollVectorOp(Op.getNode());
1091}
1092
1093SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1094 EVT VT = Op.getValueType();
1095 unsigned NumElems = VT.getVectorNumElements();
1096 EVT EltVT = VT.getVectorElementType();
1097 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1098 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1099 SDLoc dl(Op);
1100 SmallVector<SDValue, 8> Ops(NumElems);
1101 for (unsigned i = 0; i < NumElems; ++i) {
1102 SDValue LHSElem = DAG.getNode(
1103 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1104 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1105 SDValue RHSElem = DAG.getNode(
1106 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1107 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1108 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1109 TLI.getSetCCResultType(DAG.getDataLayout(),
1110 *DAG.getContext(), TmpEltVT),
1111 LHSElem, RHSElem, CC);
1112 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1113 DAG.getConstant(APInt::getAllOnesValue
1114 (EltVT.getSizeInBits()), dl, EltVT),
1115 DAG.getConstant(0, dl, EltVT));
1116 }
1117 return DAG.getBuildVector(VT, dl, Ops);
1118}
1119
1120}
1121
1122bool SelectionDAG::LegalizeVectors() {
1123 return VectorLegalizer(*this).Run();
1124}