Bug Summary

File:lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Warning:line 4162, column 48
Division by zero

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LegalizeVectorTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn338205/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/x86_64-linux-gnu/c++/8 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/8/../../../../include/c++/8/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/lib/gcc/x86_64-linux-gnu/8/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-class-memaccess -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn338205/build-llvm/lib/CodeGen/SelectionDAG -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-07-29-043837-17923-1 -x c++ /build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp -faddrsig

/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file performs vector type splitting and scalarization for LegalizeTypes.
11// Scalarization is the act of changing a computation in an illegal one-element
12// vector type to be a computation in its scalar element type. For example,
13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14// as a base case when scalarizing vector arithmetic like <4 x f32>, which
15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
16// types.
17// Splitting is the act of changing a computation in an invalid vector type to
18// be a computation in two vectors of half the size. For example, implementing
19// <128 x f32> operations in terms of two <64 x f32> operations.
20//
21//===----------------------------------------------------------------------===//
22
23#include "LegalizeTypes.h"
24#include "llvm/IR/DataLayout.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/raw_ostream.h"
27using namespace llvm;
28
29#define DEBUG_TYPE"legalize-types" "legalize-types"
30
31//===----------------------------------------------------------------------===//
32// Result Vector Scalarization: <1 x ty> -> ty.
33//===----------------------------------------------------------------------===//
34
35void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node result "
<< ResNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
37 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node result "
<< ResNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
;
38 SDValue R = SDValue();
39
40 switch (N->getOpcode()) {
41 default:
42#ifndef NDEBUG
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
44 N->dump(&DAG);
45 dbgs() << "\n";
46#endif
47 report_fatal_error("Do not know how to scalarize the result of this "
48 "operator!\n");
49
50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
52 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
67 case ISD::ANY_EXTEND_VECTOR_INREG:
68 case ISD::SIGN_EXTEND_VECTOR_INREG:
69 case ISD::ZERO_EXTEND_VECTOR_INREG:
70 R = ScalarizeVecRes_VecInregOp(N);
71 break;
72 case ISD::ANY_EXTEND:
73 case ISD::BITREVERSE:
74 case ISD::BSWAP:
75 case ISD::CTLZ:
76 case ISD::CTLZ_ZERO_UNDEF:
77 case ISD::CTPOP:
78 case ISD::CTTZ:
79 case ISD::CTTZ_ZERO_UNDEF:
80 case ISD::FABS:
81 case ISD::FCEIL:
82 case ISD::FCOS:
83 case ISD::FEXP:
84 case ISD::FEXP2:
85 case ISD::FFLOOR:
86 case ISD::FLOG:
87 case ISD::FLOG10:
88 case ISD::FLOG2:
89 case ISD::FNEARBYINT:
90 case ISD::FNEG:
91 case ISD::FP_EXTEND:
92 case ISD::FP_TO_SINT:
93 case ISD::FP_TO_UINT:
94 case ISD::FRINT:
95 case ISD::FROUND:
96 case ISD::FSIN:
97 case ISD::FSQRT:
98 case ISD::FTRUNC:
99 case ISD::SIGN_EXTEND:
100 case ISD::SINT_TO_FP:
101 case ISD::TRUNCATE:
102 case ISD::UINT_TO_FP:
103 case ISD::ZERO_EXTEND:
104 case ISD::FCANONICALIZE:
105 R = ScalarizeVecRes_UnaryOp(N);
106 break;
107
108 case ISD::ADD:
109 case ISD::AND:
110 case ISD::FADD:
111 case ISD::FCOPYSIGN:
112 case ISD::FDIV:
113 case ISD::FMUL:
114 case ISD::FMINNUM:
115 case ISD::FMAXNUM:
116 case ISD::FMINNAN:
117 case ISD::FMAXNAN:
118 case ISD::SMIN:
119 case ISD::SMAX:
120 case ISD::UMIN:
121 case ISD::UMAX:
122
123 case ISD::FPOW:
124 case ISD::FREM:
125 case ISD::FSUB:
126 case ISD::MUL:
127 case ISD::OR:
128 case ISD::SDIV:
129 case ISD::SREM:
130 case ISD::SUB:
131 case ISD::UDIV:
132 case ISD::UREM:
133 case ISD::XOR:
134 case ISD::SHL:
135 case ISD::SRA:
136 case ISD::SRL:
137 R = ScalarizeVecRes_BinOp(N);
138 break;
139 case ISD::FMA:
140 R = ScalarizeVecRes_TernaryOp(N);
141 break;
142 }
143
144 // If R is null, the sub-method took care of registering the result.
145 if (R.getNode())
146 SetScalarizedVector(SDValue(N, ResNo), R);
147}
148
149SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
150 SDValue LHS = GetScalarizedVector(N->getOperand(0));
151 SDValue RHS = GetScalarizedVector(N->getOperand(1));
152 return DAG.getNode(N->getOpcode(), SDLoc(N),
153 LHS.getValueType(), LHS, RHS, N->getFlags());
154}
155
156SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
157 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
158 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
159 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
160 return DAG.getNode(N->getOpcode(), SDLoc(N),
161 Op0.getValueType(), Op0, Op1, Op2);
162}
163
164SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
165 unsigned ResNo) {
166 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
167 return GetScalarizedVector(Op);
168}
169
170SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
171 SDValue Op = N->getOperand(0);
172 if (Op.getValueType().isVector()
173 && Op.getValueType().getVectorNumElements() == 1
174 && !isSimpleLegalType(Op.getValueType()))
175 Op = GetScalarizedVector(Op);
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 return DAG.getNode(ISD::BITCAST, SDLoc(N),
178 NewVT, Op);
179}
180
181SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
182 EVT EltVT = N->getValueType(0).getVectorElementType();
183 SDValue InOp = N->getOperand(0);
184 // The BUILD_VECTOR operands may be of wider element types and
185 // we may need to truncate them back to the requested return type.
186 if (EltVT.isInteger())
187 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
188 return InOp;
189}
190
191SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
192 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
193 N->getValueType(0).getVectorElementType(),
194 N->getOperand(0), N->getOperand(1));
195}
196
197SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
198 EVT NewVT = N->getValueType(0).getVectorElementType();
199 SDValue Op = GetScalarizedVector(N->getOperand(0));
200 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
201 NewVT, Op, N->getOperand(1));
202}
203
204SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
205 SDValue Op = GetScalarizedVector(N->getOperand(0));
206 return DAG.getNode(ISD::FPOWI, SDLoc(N),
207 Op.getValueType(), Op, N->getOperand(1));
208}
209
210SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
211 // The value to insert may have a wider type than the vector element type,
212 // so be sure to truncate it to the element type if necessary.
213 SDValue Op = N->getOperand(1);
214 EVT EltVT = N->getValueType(0).getVectorElementType();
215 if (Op.getValueType() != EltVT)
216 // FIXME: Can this happen for floating point types?
217 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
218 return Op;
219}
220
221SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
222 assert(N->isUnindexed() && "Indexed vector load?")(static_cast <bool> (N->isUnindexed() && "Indexed vector load?"
) ? void (0) : __assert_fail ("N->isUnindexed() && \"Indexed vector load?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 222, __extension__ __PRETTY_FUNCTION__))
;
223
224 SDValue Result = DAG.getLoad(
225 ISD::UNINDEXED, N->getExtensionType(),
226 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
227 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
228 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
229 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
230 N->getAAInfo());
231
232 // Legalize the chain result - switch anything that used the old chain to
233 // use the new one.
234 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
235 return Result;
236}
237
238SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
239 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
240 EVT DestVT = N->getValueType(0).getVectorElementType();
241 SDValue Op = N->getOperand(0);
242 EVT OpVT = Op.getValueType();
243 SDLoc DL(N);
244 // The result needs scalarizing, but it's not a given that the source does.
245 // This is a workaround for targets where it's impossible to scalarize the
246 // result of a conversion, because the source type is legal.
247 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
248 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
249 // legal and was not scalarized.
250 // See the similar logic in ScalarizeVecRes_SETCC
251 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
252 Op = GetScalarizedVector(Op);
253 } else {
254 EVT VT = OpVT.getVectorElementType();
255 Op = DAG.getNode(
256 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
257 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
258 }
259 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260}
261
262SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
263 EVT EltVT = N->getValueType(0).getVectorElementType();
264 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
265 SDValue LHS = GetScalarizedVector(N->getOperand(0));
266 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
267 LHS, DAG.getValueType(ExtVT));
268}
269
270SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
271 SDLoc DL(N);
272 SDValue Op = N->getOperand(0);
273
274 EVT OpVT = Op.getValueType();
275 EVT OpEltVT = OpVT.getVectorElementType();
276 EVT EltVT = N->getValueType(0).getVectorElementType();
277
278 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
279 Op = GetScalarizedVector(Op);
280 } else {
281 Op = DAG.getNode(
282 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
283 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
284 }
285
286 switch (N->getOpcode()) {
287 case ISD::ANY_EXTEND_VECTOR_INREG:
288 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
289 case ISD::SIGN_EXTEND_VECTOR_INREG:
290 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
291 case ISD::ZERO_EXTEND_VECTOR_INREG:
292 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
293 }
294
295 llvm_unreachable("Illegal extend_vector_inreg opcode")::llvm::llvm_unreachable_internal("Illegal extend_vector_inreg opcode"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 295)
;
296}
297
298SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
299 // If the operand is wider than the vector element type then it is implicitly
300 // truncated. Make that explicit here.
301 EVT EltVT = N->getValueType(0).getVectorElementType();
302 SDValue InOp = N->getOperand(0);
303 if (InOp.getValueType() != EltVT)
304 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
305 return InOp;
306}
307
308SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
309 SDValue Cond = N->getOperand(0);
310 EVT OpVT = Cond.getValueType();
311 SDLoc DL(N);
312 // The vselect result and true/value operands needs scalarizing, but it's
313 // not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
314 // See the similar logic in ScalarizeVecRes_SETCC
315 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
316 Cond = GetScalarizedVector(Cond);
317 } else {
318 EVT VT = OpVT.getVectorElementType();
319 Cond = DAG.getNode(
320 ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
321 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
322 }
323
324 SDValue LHS = GetScalarizedVector(N->getOperand(1));
325 TargetLowering::BooleanContent ScalarBool =
326 TLI.getBooleanContents(false, false);
327 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
328
329 // If integer and float booleans have different contents then we can't
330 // reliably optimize in all cases. There is a full explanation for this in
331 // DAGCombiner::visitSELECT() where the same issue affects folding
332 // (select C, 0, 1) to (xor C, 1).
333 if (TLI.getBooleanContents(false, false) !=
334 TLI.getBooleanContents(false, true)) {
335 // At least try the common case where the boolean is generated by a
336 // comparison.
337 if (Cond->getOpcode() == ISD::SETCC) {
338 EVT OpVT = Cond->getOperand(0).getValueType();
339 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
340 VecBool = TLI.getBooleanContents(OpVT);
341 } else
342 ScalarBool = TargetLowering::UndefinedBooleanContent;
343 }
344
345 EVT CondVT = Cond.getValueType();
346 if (ScalarBool != VecBool) {
347 switch (ScalarBool) {
348 case TargetLowering::UndefinedBooleanContent:
349 break;
350 case TargetLowering::ZeroOrOneBooleanContent:
351 assert(VecBool == TargetLowering::UndefinedBooleanContent ||(static_cast <bool> (VecBool == TargetLowering::UndefinedBooleanContent
|| VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent
) ? void (0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 352, __extension__ __PRETTY_FUNCTION__))
352 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent)(static_cast <bool> (VecBool == TargetLowering::UndefinedBooleanContent
|| VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent
) ? void (0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 352, __extension__ __PRETTY_FUNCTION__))
;
353 // Vector read from all ones, scalar expects a single 1 so mask.
354 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
355 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
356 break;
357 case TargetLowering::ZeroOrNegativeOneBooleanContent:
358 assert(VecBool == TargetLowering::UndefinedBooleanContent ||(static_cast <bool> (VecBool == TargetLowering::UndefinedBooleanContent
|| VecBool == TargetLowering::ZeroOrOneBooleanContent) ? void
(0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrOneBooleanContent"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 359, __extension__ __PRETTY_FUNCTION__))
359 VecBool == TargetLowering::ZeroOrOneBooleanContent)(static_cast <bool> (VecBool == TargetLowering::UndefinedBooleanContent
|| VecBool == TargetLowering::ZeroOrOneBooleanContent) ? void
(0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrOneBooleanContent"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 359, __extension__ __PRETTY_FUNCTION__))
;
360 // Vector reads from a one, scalar from all ones so sign extend.
361 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
362 Cond, DAG.getValueType(MVT::i1));
363 break;
364 }
365 }
366
367 // Truncate the condition if needed
368 auto BoolVT = getSetCCResultType(CondVT);
369 if (BoolVT.bitsLT(CondVT))
370 Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
371
372 return DAG.getSelect(SDLoc(N),
373 LHS.getValueType(), Cond, LHS,
374 GetScalarizedVector(N->getOperand(2)));
375}
376
377SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
378 SDValue LHS = GetScalarizedVector(N->getOperand(1));
379 return DAG.getSelect(SDLoc(N),
380 LHS.getValueType(), N->getOperand(0), LHS,
381 GetScalarizedVector(N->getOperand(2)));
382}
383
384SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
385 SDValue LHS = GetScalarizedVector(N->getOperand(2));
386 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
387 N->getOperand(0), N->getOperand(1),
388 LHS, GetScalarizedVector(N->getOperand(3)),
389 N->getOperand(4));
390}
391
392SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
393 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
394}
395
396SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
397 // Figure out if the scalar is the LHS or RHS and return it.
398 SDValue Arg = N->getOperand(2).getOperand(0);
399 if (Arg.isUndef())
400 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
401 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
402 return GetScalarizedVector(N->getOperand(Op));
403}
404
405SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
406 assert(N->getValueType(0).isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 408, __extension__ __PRETTY_FUNCTION__))
407 N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 408, __extension__ __PRETTY_FUNCTION__))
408 "Operand types must be vectors")(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 408, __extension__ __PRETTY_FUNCTION__))
;
409 SDValue LHS = N->getOperand(0);
410 SDValue RHS = N->getOperand(1);
411 EVT OpVT = LHS.getValueType();
412 EVT NVT = N->getValueType(0).getVectorElementType();
413 SDLoc DL(N);
414
415 // The result needs scalarizing, but it's not a given that the source does.
416 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
417 LHS = GetScalarizedVector(LHS);
418 RHS = GetScalarizedVector(RHS);
419 } else {
420 EVT VT = OpVT.getVectorElementType();
421 LHS = DAG.getNode(
422 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
423 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
424 RHS = DAG.getNode(
425 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
426 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
427 }
428
429 // Turn it into a scalar SETCC.
430 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
431 N->getOperand(2));
432 // Vectors may have a different boolean contents to scalars. Promote the
433 // value appropriately.
434 ISD::NodeType ExtendCode =
435 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
436 return DAG.getNode(ExtendCode, DL, NVT, Res);
437}
438
439
440//===----------------------------------------------------------------------===//
441// Operand Vector Scalarization <1 x ty> -> ty.
442//===----------------------------------------------------------------------===//
443
444bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
445 LLVM_DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node operand "
<< OpNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
446 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node operand "
<< OpNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
;
447 SDValue Res = SDValue();
448
449 if (!Res.getNode()) {
450 switch (N->getOpcode()) {
451 default:
452#ifndef NDEBUG
453 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
454 N->dump(&DAG);
455 dbgs() << "\n";
456#endif
457 report_fatal_error("Do not know how to scalarize this operator's "
458 "operand!\n");
459 case ISD::BITCAST:
460 Res = ScalarizeVecOp_BITCAST(N);
461 break;
462 case ISD::ANY_EXTEND:
463 case ISD::ZERO_EXTEND:
464 case ISD::SIGN_EXTEND:
465 case ISD::TRUNCATE:
466 case ISD::FP_TO_SINT:
467 case ISD::FP_TO_UINT:
468 case ISD::SINT_TO_FP:
469 case ISD::UINT_TO_FP:
470 Res = ScalarizeVecOp_UnaryOp(N);
471 break;
472 case ISD::CONCAT_VECTORS:
473 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
474 break;
475 case ISD::EXTRACT_VECTOR_ELT:
476 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
477 break;
478 case ISD::VSELECT:
479 Res = ScalarizeVecOp_VSELECT(N);
480 break;
481 case ISD::SETCC:
482 Res = ScalarizeVecOp_VSETCC(N);
483 break;
484 case ISD::STORE:
485 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
486 break;
487 case ISD::FP_ROUND:
488 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
489 break;
490 }
491 }
492
493 // If the result is null, the sub-method took care of registering results etc.
494 if (!Res.getNode()) return false;
495
496 // If the result is N, the sub-method updated N in place. Tell the legalizer
497 // core about this.
498 if (Res.getNode() == N)
499 return true;
500
501 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 502, __extension__ __PRETTY_FUNCTION__))
502 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 502, __extension__ __PRETTY_FUNCTION__))
;
503
504 ReplaceValueWith(SDValue(N, 0), Res);
505 return false;
506}
507
508/// If the value to convert is a vector that needs to be scalarized, it must be
509/// <1 x ty>. Convert the element instead.
510SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
511 SDValue Elt = GetScalarizedVector(N->getOperand(0));
512 return DAG.getNode(ISD::BITCAST, SDLoc(N),
513 N->getValueType(0), Elt);
514}
515
516/// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
517/// Do the operation on the element instead.
518SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
519 assert(N->getValueType(0).getVectorNumElements() == 1 &&(static_cast <bool> (N->getValueType(0).getVectorNumElements
() == 1 && "Unexpected vector type!") ? void (0) : __assert_fail
("N->getValueType(0).getVectorNumElements() == 1 && \"Unexpected vector type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 520, __extension__ __PRETTY_FUNCTION__))
520 "Unexpected vector type!")(static_cast <bool> (N->getValueType(0).getVectorNumElements
() == 1 && "Unexpected vector type!") ? void (0) : __assert_fail
("N->getValueType(0).getVectorNumElements() == 1 && \"Unexpected vector type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 520, __extension__ __PRETTY_FUNCTION__))
;
521 SDValue Elt = GetScalarizedVector(N->getOperand(0));
522 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
523 N->getValueType(0).getScalarType(), Elt);
524 // Revectorize the result so the types line up with what the uses of this
525 // expression expect.
526 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
527}
528
529/// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
530SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
531 SmallVector<SDValue, 8> Ops(N->getNumOperands());
532 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
533 Ops[i] = GetScalarizedVector(N->getOperand(i));
534 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
535}
536
537/// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
538/// so just return the element, ignoring the index.
539SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
540 EVT VT = N->getValueType(0);
541 SDValue Res = GetScalarizedVector(N->getOperand(0));
542 if (Res.getValueType() != VT)
543 Res = VT.isFloatingPoint()
544 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
545 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
546 return Res;
547}
548
549/// If the input condition is a vector that needs to be scalarized, it must be
550/// <1 x i1>, so just convert to a normal ISD::SELECT
551/// (still with vector output type since that was acceptable if we got here).
552SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
553 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
554 EVT VT = N->getValueType(0);
555
556 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
557 N->getOperand(2));
558}
559
560/// If the operand is a vector that needs to be scalarized then the
561/// result must be v1i1, so just convert to a scalar SETCC and wrap
562/// with a scalar_to_vector since the res type is legal if we got here
563SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) {
564 assert(N->getValueType(0).isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 566, __extension__ __PRETTY_FUNCTION__))
565 N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 566, __extension__ __PRETTY_FUNCTION__))
566 "Operand types must be vectors")(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 566, __extension__ __PRETTY_FUNCTION__))
;
567 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type")(static_cast <bool> (N->getValueType(0) == MVT::v1i1
&& "Expected v1i1 type") ? void (0) : __assert_fail (
"N->getValueType(0) == MVT::v1i1 && \"Expected v1i1 type\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 567, __extension__ __PRETTY_FUNCTION__))
;
568
569 EVT VT = N->getValueType(0);
570 SDValue LHS = GetScalarizedVector(N->getOperand(0));
571 SDValue RHS = GetScalarizedVector(N->getOperand(1));
572
573 EVT OpVT = N->getOperand(0).getValueType();
574 EVT NVT = VT.getVectorElementType();
575 SDLoc DL(N);
576 // Turn it into a scalar SETCC.
577 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
578 N->getOperand(2));
579
580 // Vectors may have a different boolean contents to scalars. Promote the
581 // value appropriately.
582 ISD::NodeType ExtendCode =
583 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
584
585 Res = DAG.getNode(ExtendCode, DL, NVT, Res);
586
587 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
588}
589
590/// If the value to store is a vector that needs to be scalarized, it must be
591/// <1 x ty>. Just store the element.
592SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
593 assert(N->isUnindexed() && "Indexed store of one-element vector?")(static_cast <bool> (N->isUnindexed() && "Indexed store of one-element vector?"
) ? void (0) : __assert_fail ("N->isUnindexed() && \"Indexed store of one-element vector?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 593, __extension__ __PRETTY_FUNCTION__))
;
594 assert(OpNo == 1 && "Do not know how to scalarize this operand!")(static_cast <bool> (OpNo == 1 && "Do not know how to scalarize this operand!"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Do not know how to scalarize this operand!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 594, __extension__ __PRETTY_FUNCTION__))
;
595 SDLoc dl(N);
596
597 if (N->isTruncatingStore())
598 return DAG.getTruncStore(
599 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
600 N->getBasePtr(), N->getPointerInfo(),
601 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
602 N->getMemOperand()->getFlags(), N->getAAInfo());
603
604 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
605 N->getBasePtr(), N->getPointerInfo(),
606 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
607 N->getAAInfo());
608}
609
610/// If the value to round is a vector that needs to be scalarized, it must be
611/// <1 x ty>. Convert the element instead.
612SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
613 SDValue Elt = GetScalarizedVector(N->getOperand(0));
614 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
615 N->getValueType(0).getVectorElementType(), Elt,
616 N->getOperand(1));
617 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
618}
619
620//===----------------------------------------------------------------------===//
621// Result Vector Splitting
622//===----------------------------------------------------------------------===//
623
624/// This method is called when the specified result of the specified node is
625/// found to need vector splitting. At this point, the node may also have
626/// invalid operands or may have other results that need legalization, we just
627/// know that (at least) one result needs vector splitting.
628void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
629 LLVM_DEBUG(dbgs() << "Split node result: "; N->dump(&DAG); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split node result: "; N
->dump(&DAG); dbgs() << "\n"; } } while (false)
;
630 SDValue Lo, Hi;
631
632 // See if the target wants to custom expand this node.
633 if (CustomLowerNode(N, N->getValueType(ResNo), true))
634 return;
635
636 switch (N->getOpcode()) {
637 default:
638#ifndef NDEBUG
639 dbgs() << "SplitVectorResult #" << ResNo << ": ";
640 N->dump(&DAG);
641 dbgs() << "\n";
642#endif
643 report_fatal_error("Do not know how to split the result of this "
644 "operator!\n");
645
646 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
647 case ISD::VSELECT:
648 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
649 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
650 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
651 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
652 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
653 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
654 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
655 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
656 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
657 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
658 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
659 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
660 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
661 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
662 case ISD::LOAD:
663 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
664 break;
665 case ISD::MLOAD:
666 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
667 break;
668 case ISD::MGATHER:
669 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
670 break;
671 case ISD::SETCC:
672 SplitVecRes_SETCC(N, Lo, Hi);
673 break;
674 case ISD::VECTOR_SHUFFLE:
675 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
676 break;
677
678 case ISD::ANY_EXTEND_VECTOR_INREG:
679 case ISD::SIGN_EXTEND_VECTOR_INREG:
680 case ISD::ZERO_EXTEND_VECTOR_INREG:
681 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
682 break;
683
684 case ISD::BITREVERSE:
685 case ISD::BSWAP:
686 case ISD::CTLZ:
687 case ISD::CTTZ:
688 case ISD::CTLZ_ZERO_UNDEF:
689 case ISD::CTTZ_ZERO_UNDEF:
690 case ISD::CTPOP:
691 case ISD::FABS:
692 case ISD::FCEIL:
693 case ISD::FCOS:
694 case ISD::FEXP:
695 case ISD::FEXP2:
696 case ISD::FFLOOR:
697 case ISD::FLOG:
698 case ISD::FLOG10:
699 case ISD::FLOG2:
700 case ISD::FNEARBYINT:
701 case ISD::FNEG:
702 case ISD::FP_EXTEND:
703 case ISD::FP_ROUND:
704 case ISD::FP_TO_SINT:
705 case ISD::FP_TO_UINT:
706 case ISD::FRINT:
707 case ISD::FROUND:
708 case ISD::FSIN:
709 case ISD::FSQRT:
710 case ISD::FTRUNC:
711 case ISD::SINT_TO_FP:
712 case ISD::TRUNCATE:
713 case ISD::UINT_TO_FP:
714 case ISD::FCANONICALIZE:
715 SplitVecRes_UnaryOp(N, Lo, Hi);
716 break;
717
718 case ISD::ANY_EXTEND:
719 case ISD::SIGN_EXTEND:
720 case ISD::ZERO_EXTEND:
721 SplitVecRes_ExtendOp(N, Lo, Hi);
722 break;
723
724 case ISD::ADD:
725 case ISD::SUB:
726 case ISD::MUL:
727 case ISD::MULHS:
728 case ISD::MULHU:
729 case ISD::FADD:
730 case ISD::FSUB:
731 case ISD::FMUL:
732 case ISD::FMINNUM:
733 case ISD::FMAXNUM:
734 case ISD::FMINNAN:
735 case ISD::FMAXNAN:
736 case ISD::SDIV:
737 case ISD::UDIV:
738 case ISD::FDIV:
739 case ISD::FPOW:
740 case ISD::AND:
741 case ISD::OR:
742 case ISD::XOR:
743 case ISD::SHL:
744 case ISD::SRA:
745 case ISD::SRL:
746 case ISD::UREM:
747 case ISD::SREM:
748 case ISD::FREM:
749 case ISD::SMIN:
750 case ISD::SMAX:
751 case ISD::UMIN:
752 case ISD::UMAX:
753 SplitVecRes_BinOp(N, Lo, Hi);
754 break;
755 case ISD::FMA:
756 SplitVecRes_TernaryOp(N, Lo, Hi);
757 break;
758 case ISD::STRICT_FADD:
759 case ISD::STRICT_FSUB:
760 case ISD::STRICT_FMUL:
761 case ISD::STRICT_FDIV:
762 case ISD::STRICT_FSQRT:
763 case ISD::STRICT_FMA:
764 case ISD::STRICT_FPOW:
765 case ISD::STRICT_FPOWI:
766 case ISD::STRICT_FSIN:
767 case ISD::STRICT_FCOS:
768 case ISD::STRICT_FEXP:
769 case ISD::STRICT_FEXP2:
770 case ISD::STRICT_FLOG:
771 case ISD::STRICT_FLOG10:
772 case ISD::STRICT_FLOG2:
773 case ISD::STRICT_FRINT:
774 case ISD::STRICT_FNEARBYINT:
775 SplitVecRes_StrictFPOp(N, Lo, Hi);
776 break;
777 }
778
779 // If Lo/Hi is null, the sub-method took care of registering results etc.
780 if (Lo.getNode())
781 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
782}
783
784void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
785 SDValue &Hi) {
786 SDValue LHSLo, LHSHi;
787 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
788 SDValue RHSLo, RHSHi;
789 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
790 SDLoc dl(N);
791
792 const SDNodeFlags Flags = N->getFlags();
793 unsigned Opcode = N->getOpcode();
794 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
795 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
796}
797
798void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
799 SDValue &Hi) {
800 SDValue Op0Lo, Op0Hi;
801 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
802 SDValue Op1Lo, Op1Hi;
803 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
804 SDValue Op2Lo, Op2Hi;
805 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
806 SDLoc dl(N);
807
808 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
809 Op0Lo, Op1Lo, Op2Lo);
810 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
811 Op0Hi, Op1Hi, Op2Hi);
812}
813
814void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
815 SDValue &Hi) {
816 // We know the result is a vector. The input may be either a vector or a
817 // scalar value.
818 EVT LoVT, HiVT;
819 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
820 SDLoc dl(N);
821
822 SDValue InOp = N->getOperand(0);
823 EVT InVT = InOp.getValueType();
824
825 // Handle some special cases efficiently.
826 switch (getTypeAction(InVT)) {
827 case TargetLowering::TypeLegal:
828 case TargetLowering::TypePromoteInteger:
829 case TargetLowering::TypePromoteFloat:
830 case TargetLowering::TypeSoftenFloat:
831 case TargetLowering::TypeScalarizeVector:
832 case TargetLowering::TypeWidenVector:
833 break;
834 case TargetLowering::TypeExpandInteger:
835 case TargetLowering::TypeExpandFloat:
836 // A scalar to vector conversion, where the scalar needs expansion.
837 // If the vector is being split in two then we can just convert the
838 // expanded pieces.
839 if (LoVT == HiVT) {
840 GetExpandedOp(InOp, Lo, Hi);
841 if (DAG.getDataLayout().isBigEndian())
842 std::swap(Lo, Hi);
843 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
844 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
845 return;
846 }
847 break;
848 case TargetLowering::TypeSplitVector:
849 // If the input is a vector that needs to be split, convert each split
850 // piece of the input now.
851 GetSplitVector(InOp, Lo, Hi);
852 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
853 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
854 return;
855 }
856
857 // In the general case, convert the input to an integer and split it by hand.
858 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
859 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
860 if (DAG.getDataLayout().isBigEndian())
861 std::swap(LoIntVT, HiIntVT);
862
863 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
864
865 if (DAG.getDataLayout().isBigEndian())
866 std::swap(Lo, Hi);
867 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
868 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
869}
870
871void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
872 SDValue &Hi) {
873 EVT LoVT, HiVT;
874 SDLoc dl(N);
875 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
876 unsigned LoNumElts = LoVT.getVectorNumElements();
877 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
878 Lo = DAG.getBuildVector(LoVT, dl, LoOps);
879
880 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
881 Hi = DAG.getBuildVector(HiVT, dl, HiOps);
882}
883
884void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
885 SDValue &Hi) {
886 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS")(static_cast <bool> (!(N->getNumOperands() & 1) &&
"Unsupported CONCAT_VECTORS") ? void (0) : __assert_fail ("!(N->getNumOperands() & 1) && \"Unsupported CONCAT_VECTORS\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 886, __extension__ __PRETTY_FUNCTION__))
;
887 SDLoc dl(N);
888 unsigned NumSubvectors = N->getNumOperands() / 2;
889 if (NumSubvectors == 1) {
890 Lo = N->getOperand(0);
891 Hi = N->getOperand(1);
892 return;
893 }
894
895 EVT LoVT, HiVT;
896 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
897
898 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
899 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
900
901 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
902 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
903}
904
905void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
906 SDValue &Hi) {
907 SDValue Vec = N->getOperand(0);
908 SDValue Idx = N->getOperand(1);
909 SDLoc dl(N);
910
911 EVT LoVT, HiVT;
912 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
913
914 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
915 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
916 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
917 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
918 TLI.getVectorIdxTy(DAG.getDataLayout())));
919}
920
921void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
922 SDValue &Hi) {
923 SDValue Vec = N->getOperand(0);
924 SDValue SubVec = N->getOperand(1);
925 SDValue Idx = N->getOperand(2);
926 SDLoc dl(N);
927 GetSplitVector(Vec, Lo, Hi);
928
929 EVT VecVT = Vec.getValueType();
930 unsigned VecElems = VecVT.getVectorNumElements();
931 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
932
933 // If we know the index is 0, and we know the subvector doesn't cross the
934 // boundary between the halves, we can avoid spilling the vector, and insert
935 // into the lower half of the split vector directly.
936 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
937 // the index is constant and there is no boundary crossing. But those cases
938 // don't seem to get hit in practice.
939 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
940 unsigned IdxVal = ConstIdx->getZExtValue();
941 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
942 EVT LoVT, HiVT;
943 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
944 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
945 return;
946 }
947 }
948
949 // Spill the vector to the stack.
950 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
951 SDValue Store =
952 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
953
954 // Store the new subvector into the specified index.
955 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
956 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
957 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
958 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
959
960 // Load the Lo part from the stack slot.
961 Lo =
962 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
963
964 // Increment the pointer to the other part.
965 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
966 StackPtr =
967 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
968 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
969
970 // Load the Hi part from the stack slot.
971 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
972 MinAlign(Alignment, IncrementSize));
973}
974
975void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
976 SDValue &Hi) {
977 SDLoc dl(N);
978 GetSplitVector(N->getOperand(0), Lo, Hi);
979 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
980 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
981}
982
983void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
984 SDValue &Hi) {
985 SDValue LHSLo, LHSHi;
986 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
987 SDLoc DL(N);
988
989 SDValue RHSLo, RHSHi;
990 SDValue RHS = N->getOperand(1);
991 EVT RHSVT = RHS.getValueType();
992 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
993 GetSplitVector(RHS, RHSLo, RHSHi);
994 else
995 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
996
997
998 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
999 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
1000}
1001
1002void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
1003 SDValue &Hi) {
1004 SDValue LHSLo, LHSHi;
1005 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1006 SDLoc dl(N);
1007
1008 EVT LoVT, HiVT;
1009 std::tie(LoVT, HiVT) =
1010 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
1011
1012 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
1013 DAG.getValueType(LoVT));
1014 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
1015 DAG.getValueType(HiVT));
1016}
1017
1018void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
1019 SDValue &Hi) {
1020 unsigned Opcode = N->getOpcode();
1021 SDValue N0 = N->getOperand(0);
1022
1023 SDLoc dl(N);
1024 SDValue InLo, InHi;
1025
1026 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
1027 GetSplitVector(N0, InLo, InHi);
1028 else
1029 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
1030
1031 EVT InLoVT = InLo.getValueType();
1032 unsigned InNumElements = InLoVT.getVectorNumElements();
1033
1034 EVT OutLoVT, OutHiVT;
1035 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1036 unsigned OutNumElements = OutLoVT.getVectorNumElements();
1037 assert((2 * OutNumElements) <= InNumElements &&(static_cast <bool> ((2 * OutNumElements) <= InNumElements
&& "Illegal extend vector in reg split") ? void (0) :
__assert_fail ("(2 * OutNumElements) <= InNumElements && \"Illegal extend vector in reg split\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1038, __extension__ __PRETTY_FUNCTION__))
1038 "Illegal extend vector in reg split")(static_cast <bool> ((2 * OutNumElements) <= InNumElements
&& "Illegal extend vector in reg split") ? void (0) :
__assert_fail ("(2 * OutNumElements) <= InNumElements && \"Illegal extend vector in reg split\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1038, __extension__ __PRETTY_FUNCTION__))
;
1039
1040 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
1041 // input vector (i.e. we only use InLo):
1042 // OutLo will extend the first OutNumElements from InLo.
1043 // OutHi will extend the next OutNumElements from InLo.
1044
1045 // Shuffle the elements from InLo for OutHi into the bottom elements to
1046 // create a 'fake' InHi.
1047 SmallVector<int, 8> SplitHi(InNumElements, -1);
1048 for (unsigned i = 0; i != OutNumElements; ++i)
1049 SplitHi[i] = i + OutNumElements;
1050 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
1051
1052 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
1053 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
1054}
1055
1056void DAGTypeLegalizer::SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo,
1057 SDValue &Hi) {
1058 unsigned NumOps = N->getNumOperands();
1059 SDValue Chain = N->getOperand(0);
1060 EVT LoVT, HiVT;
1061 SDLoc dl(N);
1062 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1063
1064 SmallVector<SDValue, 4> OpsLo;
1065 SmallVector<SDValue, 4> OpsHi;
1066
1067 // The Chain is the first operand.
1068 OpsLo.push_back(Chain);
1069 OpsHi.push_back(Chain);
1070
1071 // Now process the remaining operands.
1072 for (unsigned i = 1; i < NumOps; ++i) {
1073 SDValue Op = N->getOperand(i);
1074 SDValue OpLo = Op;
1075 SDValue OpHi = Op;
1076
1077 EVT InVT = Op.getValueType();
1078 if (InVT.isVector()) {
1079 // If the input also splits, handle it directly for a
1080 // compile time speedup. Otherwise split it by hand.
1081 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1082 GetSplitVector(Op, OpLo, OpHi);
1083 else
1084 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i);
1085 }
1086
1087 OpsLo.push_back(OpLo);
1088 OpsHi.push_back(OpHi);
1089 }
1090
1091 EVT LoValueVTs[] = {LoVT, MVT::Other};
1092 EVT HiValueVTs[] = {HiVT, MVT::Other};
1093 Lo = DAG.getNode(N->getOpcode(), dl, LoValueVTs, OpsLo);
1094 Hi = DAG.getNode(N->getOpcode(), dl, HiValueVTs, OpsHi);
1095
1096 // Build a factor node to remember that this Op is independent of the
1097 // other one.
1098 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1099 Lo.getValue(1), Hi.getValue(1));
1100
1101 // Legalize the chain result - switch anything that used the old chain to
1102 // use the new one.
1103 ReplaceValueWith(SDValue(N, 1), Chain);
1104}
1105
1106void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
1107 SDValue &Hi) {
1108 SDValue Vec = N->getOperand(0);
1109 SDValue Elt = N->getOperand(1);
1110 SDValue Idx = N->getOperand(2);
1111 SDLoc dl(N);
1112 GetSplitVector(Vec, Lo, Hi);
1113
1114 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1115 unsigned IdxVal = CIdx->getZExtValue();
1116 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1117 if (IdxVal < LoNumElts)
1118 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1119 Lo.getValueType(), Lo, Elt, Idx);
1120 else
1121 Hi =
1122 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1123 DAG.getConstant(IdxVal - LoNumElts, dl,
1124 TLI.getVectorIdxTy(DAG.getDataLayout())));
1125 return;
1126 }
1127
1128 // See if the target wants to custom expand this node.
1129 if (CustomLowerNode(N, N->getValueType(0), true))
1130 return;
1131
1132 // Make the vector elements byte-addressable if they aren't already.
1133 EVT VecVT = Vec.getValueType();
1134 EVT EltVT = VecVT.getVectorElementType();
1135 if (VecVT.getScalarSizeInBits() < 8) {
1136 EltVT = MVT::i8;
1137 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1138 VecVT.getVectorNumElements());
1139 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1140 // Extend the element type to match if needed.
1141 if (EltVT.bitsGT(Elt.getValueType()))
1142 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt);
1143 }
1144
1145 // Spill the vector to the stack.
1146 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1147 auto &MF = DAG.getMachineFunction();
1148 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1149 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1150 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1151
1152 // Store the new element. This may be larger than the vector element type,
1153 // so use a truncating store.
1154 SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1155 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1156 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1157 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr,
1158 MachinePointerInfo::getUnknownStack(MF), EltVT);
1159
1160 EVT LoVT, HiVT;
1161 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT);
1162
1163 // Load the Lo part from the stack slot.
1164 Lo = DAG.getLoad(LoVT, dl, Store, StackPtr, PtrInfo);
1165
1166 // Increment the pointer to the other part.
1167 unsigned IncrementSize = LoVT.getSizeInBits() / 8;
1168 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1169 DAG.getConstant(IncrementSize, dl,
1170 StackPtr.getValueType()));
1171
1172 // Load the Hi part from the stack slot.
1173 Hi = DAG.getLoad(HiVT, dl, Store, StackPtr,
1174 PtrInfo.getWithOffset(IncrementSize),
1175 MinAlign(Alignment, IncrementSize));
1176
1177 // If we adjusted the original type, we need to truncate the results.
1178 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1179 if (LoVT != Lo.getValueType())
1180 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo);
1181 if (HiVT != Hi.getValueType())
1182 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
1183}
1184
1185void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1186 SDValue &Hi) {
1187 EVT LoVT, HiVT;
1188 SDLoc dl(N);
1189 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1190 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1191 Hi = DAG.getUNDEF(HiVT);
1192}
1193
1194void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1195 SDValue &Hi) {
1196 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!")(static_cast <bool> (ISD::isUNINDEXEDLoad(LD) &&
"Indexed load during type legalization!") ? void (0) : __assert_fail
("ISD::isUNINDEXEDLoad(LD) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1196, __extension__ __PRETTY_FUNCTION__))
;
1197 EVT LoVT, HiVT;
1198 SDLoc dl(LD);
1199 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1200
1201 ISD::LoadExtType ExtType = LD->getExtensionType();
1202 SDValue Ch = LD->getChain();
1203 SDValue Ptr = LD->getBasePtr();
1204 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1205 EVT MemoryVT = LD->getMemoryVT();
1206 unsigned Alignment = LD->getOriginalAlignment();
1207 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1208 AAMDNodes AAInfo = LD->getAAInfo();
1209
1210 EVT LoMemVT, HiMemVT;
1211 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1212
1213 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1214 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1215
1216 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1217 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
1218 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1219 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1220 Alignment, MMOFlags, AAInfo);
1221
1222 // Build a factor node to remember that this load is independent of the
1223 // other one.
1224 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1225 Hi.getValue(1));
1226
1227 // Legalize the chain result - switch anything that used the old chain to
1228 // use the new one.
1229 ReplaceValueWith(SDValue(LD, 1), Ch);
1230}
1231
1232void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1233 SDValue &Lo, SDValue &Hi) {
1234 EVT LoVT, HiVT;
1235 SDLoc dl(MLD);
1236 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1237
1238 SDValue Ch = MLD->getChain();
1239 SDValue Ptr = MLD->getBasePtr();
1240 SDValue Mask = MLD->getMask();
1241 SDValue Src0 = MLD->getSrc0();
1242 unsigned Alignment = MLD->getOriginalAlignment();
1243 ISD::LoadExtType ExtType = MLD->getExtensionType();
1244
1245 // if Alignment is equal to the vector size,
1246 // take the half of it for the second part
1247 unsigned SecondHalfAlignment =
1248 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1249 Alignment/2 : Alignment;
1250
1251 // Split Mask operand
1252 SDValue MaskLo, MaskHi;
1253 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1254 GetSplitVector(Mask, MaskLo, MaskHi);
1255 else
1256 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1257
1258 EVT MemoryVT = MLD->getMemoryVT();
1259 EVT LoMemVT, HiMemVT;
1260 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1261
1262 SDValue Src0Lo, Src0Hi;
1263 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1264 GetSplitVector(Src0, Src0Lo, Src0Hi);
1265 else
1266 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1267
1268 MachineMemOperand *MMO = DAG.getMachineFunction().
1269 getMachineMemOperand(MLD->getPointerInfo(),
1270 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1271 Alignment, MLD->getAAInfo(), MLD->getRanges());
1272
1273 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1274 ExtType, MLD->isExpandingLoad());
1275
1276 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1277 MLD->isExpandingLoad());
1278 unsigned HiOffset = LoMemVT.getStoreSize();
1279
1280 MMO = DAG.getMachineFunction().getMachineMemOperand(
1281 MLD->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOLoad,
1282 HiMemVT.getStoreSize(), SecondHalfAlignment, MLD->getAAInfo(),
1283 MLD->getRanges());
1284
1285 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1286 ExtType, MLD->isExpandingLoad());
1287
1288 // Build a factor node to remember that this load is independent of the
1289 // other one.
1290 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1291 Hi.getValue(1));
1292
1293 // Legalize the chain result - switch anything that used the old chain to
1294 // use the new one.
1295 ReplaceValueWith(SDValue(MLD, 1), Ch);
1296
1297}
1298
1299void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1300 SDValue &Lo, SDValue &Hi) {
1301 EVT LoVT, HiVT;
1302 SDLoc dl(MGT);
1303 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1304
1305 SDValue Ch = MGT->getChain();
1306 SDValue Ptr = MGT->getBasePtr();
1307 SDValue Mask = MGT->getMask();
1308 SDValue Src0 = MGT->getValue();
1309 SDValue Index = MGT->getIndex();
1310 SDValue Scale = MGT->getScale();
1311 unsigned Alignment = MGT->getOriginalAlignment();
1312
1313 // Split Mask operand
1314 SDValue MaskLo, MaskHi;
1315 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1316 GetSplitVector(Mask, MaskLo, MaskHi);
1317 else
1318 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1319
1320 EVT MemoryVT = MGT->getMemoryVT();
1321 EVT LoMemVT, HiMemVT;
1322 // Split MemoryVT
1323 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1324
1325 SDValue Src0Lo, Src0Hi;
1326 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1327 GetSplitVector(Src0, Src0Lo, Src0Hi);
1328 else
1329 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1330
1331 SDValue IndexHi, IndexLo;
1332 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1333 GetSplitVector(Index, IndexLo, IndexHi);
1334 else
1335 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1336
1337 MachineMemOperand *MMO = DAG.getMachineFunction().
1338 getMachineMemOperand(MGT->getPointerInfo(),
1339 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1340 Alignment, MGT->getAAInfo(), MGT->getRanges());
1341
1342 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo, Scale};
1343 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1344 MMO);
1345
1346 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi, Scale};
1347 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1348 MMO);
1349
1350 // Build a factor node to remember that this load is independent of the
1351 // other one.
1352 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1353 Hi.getValue(1));
1354
1355 // Legalize the chain result - switch anything that used the old chain to
1356 // use the new one.
1357 ReplaceValueWith(SDValue(MGT, 1), Ch);
1358}
1359
1360
1361void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1362 assert(N->getValueType(0).isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1364, __extension__ __PRETTY_FUNCTION__))
1363 N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1364, __extension__ __PRETTY_FUNCTION__))
1364 "Operand types must be vectors")(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1364, __extension__ __PRETTY_FUNCTION__))
;
1365
1366 EVT LoVT, HiVT;
1367 SDLoc DL(N);
1368 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1369
1370 // If the input also splits, handle it directly. Otherwise split it by hand.
1371 SDValue LL, LH, RL, RH;
1372 if (getTypeAction(N->getOperand(0).getValueType()) ==
1373 TargetLowering::TypeSplitVector)
1374 GetSplitVector(N->getOperand(0), LL, LH);
1375 else
1376 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1377
1378 if (getTypeAction(N->getOperand(1).getValueType()) ==
1379 TargetLowering::TypeSplitVector)
1380 GetSplitVector(N->getOperand(1), RL, RH);
1381 else
1382 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1383
1384 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1385 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1386}
1387
1388void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1389 SDValue &Hi) {
1390 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1391 EVT LoVT, HiVT;
1392 SDLoc dl(N);
1393 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1394
1395 // If the input also splits, handle it directly for a compile time speedup.
1396 // Otherwise split it by hand.
1397 EVT InVT = N->getOperand(0).getValueType();
1398 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1399 GetSplitVector(N->getOperand(0), Lo, Hi);
1400 else
1401 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1402
1403 if (N->getOpcode() == ISD::FP_ROUND) {
1404 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1405 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1406 } else {
1407 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1408 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1409 }
1410}
1411
1412void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1413 SDValue &Hi) {
1414 SDLoc dl(N);
1415 EVT SrcVT = N->getOperand(0).getValueType();
1416 EVT DestVT = N->getValueType(0);
1417 EVT LoVT, HiVT;
1418 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1419
1420 // We can do better than a generic split operation if the extend is doing
1421 // more than just doubling the width of the elements and the following are
1422 // true:
1423 // - The number of vector elements is even,
1424 // - the source type is legal,
1425 // - the type of a split source is illegal,
1426 // - the type of an extended (by doubling element size) source is legal, and
1427 // - the type of that extended source when split is legal.
1428 //
1429 // This won't necessarily completely legalize the operation, but it will
1430 // more effectively move in the right direction and prevent falling down
1431 // to scalarization in many cases due to the input vector being split too
1432 // far.
1433 unsigned NumElements = SrcVT.getVectorNumElements();
1434 if ((NumElements & 1) == 0 &&
1435 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1436 LLVMContext &Ctx = *DAG.getContext();
1437 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
1438 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
1439
1440 EVT SplitLoVT, SplitHiVT;
1441 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1442 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1443 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1444 LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split vector extend via incremental extend:"
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1445 N->dump(&DAG); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split vector extend via incremental extend:"
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1446 // Extend the source vector by one step.
1447 SDValue NewSrc =
1448 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1449 // Get the low and high halves of the new, extended one step, vector.
1450 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1451 // Extend those vector halves the rest of the way.
1452 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1453 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1454 return;
1455 }
1456 }
1457 // Fall back to the generic unary operator splitting otherwise.
1458 SplitVecRes_UnaryOp(N, Lo, Hi);
1459}
1460
1461void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1462 SDValue &Lo, SDValue &Hi) {
1463 // The low and high parts of the original input give four input vectors.
1464 SDValue Inputs[4];
1465 SDLoc dl(N);
1466 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1467 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1468 EVT NewVT = Inputs[0].getValueType();
1469 unsigned NewElts = NewVT.getVectorNumElements();
1470
1471 // If Lo or Hi uses elements from at most two of the four input vectors, then
1472 // express it as a vector shuffle of those two inputs. Otherwise extract the
1473 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1474 SmallVector<int, 16> Ops;
1475 for (unsigned High = 0; High < 2; ++High) {
1476 SDValue &Output = High ? Hi : Lo;
1477
1478 // Build a shuffle mask for the output, discovering on the fly which
1479 // input vectors to use as shuffle operands (recorded in InputUsed).
1480 // If building a suitable shuffle vector proves too hard, then bail
1481 // out with useBuildVector set.
1482 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1483 unsigned FirstMaskIdx = High * NewElts;
1484 bool useBuildVector = false;
1485 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1486 // The mask element. This indexes into the input.
1487 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1488
1489 // The input vector this mask element indexes into.
1490 unsigned Input = (unsigned)Idx / NewElts;
1491
1492 if (Input >= array_lengthof(Inputs)) {
1493 // The mask element does not index into any input vector.
1494 Ops.push_back(-1);
1495 continue;
1496 }
1497
1498 // Turn the index into an offset from the start of the input vector.
1499 Idx -= Input * NewElts;
1500
1501 // Find or create a shuffle vector operand to hold this input.
1502 unsigned OpNo;
1503 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1504 if (InputUsed[OpNo] == Input) {
1505 // This input vector is already an operand.
1506 break;
1507 } else if (InputUsed[OpNo] == -1U) {
1508 // Create a new operand for this input vector.
1509 InputUsed[OpNo] = Input;
1510 break;
1511 }
1512 }
1513
1514 if (OpNo >= array_lengthof(InputUsed)) {
1515 // More than two input vectors used! Give up on trying to create a
1516 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1517 useBuildVector = true;
1518 break;
1519 }
1520
1521 // Add the mask index for the new shuffle vector.
1522 Ops.push_back(Idx + OpNo * NewElts);
1523 }
1524
1525 if (useBuildVector) {
1526 EVT EltVT = NewVT.getVectorElementType();
1527 SmallVector<SDValue, 16> SVOps;
1528
1529 // Extract the input elements by hand.
1530 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1531 // The mask element. This indexes into the input.
1532 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1533
1534 // The input vector this mask element indexes into.
1535 unsigned Input = (unsigned)Idx / NewElts;
1536
1537 if (Input >= array_lengthof(Inputs)) {
1538 // The mask element is "undef" or indexes off the end of the input.
1539 SVOps.push_back(DAG.getUNDEF(EltVT));
1540 continue;
1541 }
1542
1543 // Turn the index into an offset from the start of the input vector.
1544 Idx -= Input * NewElts;
1545
1546 // Extract the vector element by hand.
1547 SVOps.push_back(DAG.getNode(
1548 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1549 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1550 }
1551
1552 // Construct the Lo/Hi output using a BUILD_VECTOR.
1553 Output = DAG.getBuildVector(NewVT, dl, SVOps);
1554 } else if (InputUsed[0] == -1U) {
1555 // No input vectors were used! The result is undefined.
1556 Output = DAG.getUNDEF(NewVT);
1557 } else {
1558 SDValue Op0 = Inputs[InputUsed[0]];
1559 // If only one input was used, use an undefined vector for the other.
1560 SDValue Op1 = InputUsed[1] == -1U ?
1561 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1562 // At least one input vector was used. Create a new shuffle vector.
1563 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1564 }
1565
1566 Ops.clear();
1567 }
1568}
1569
1570
1571//===----------------------------------------------------------------------===//
1572// Operand Vector Splitting
1573//===----------------------------------------------------------------------===//
1574
1575/// This method is called when the specified operand of the specified node is
1576/// found to need vector splitting. At this point, all of the result types of
1577/// the node are known to be legal, but other operands of the node may need
1578/// legalization as well as the specified one.
1579bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1580 LLVM_DEBUG(dbgs() << "Split node operand: "; N->dump(&DAG); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split node operand: ";
N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1581 SDValue Res = SDValue();
1582
1583 // See if the target wants to custom split this node.
1584 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1585 return false;
1586
1587 if (!Res.getNode()) {
1588 switch (N->getOpcode()) {
1589 default:
1590#ifndef NDEBUG
1591 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1592 N->dump(&DAG);
1593 dbgs() << "\n";
1594#endif
1595 report_fatal_error("Do not know how to split this operator's "
1596 "operand!\n");
1597
1598 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1599 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1600 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1601 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1602 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1603 case ISD::TRUNCATE:
1604 Res = SplitVecOp_TruncateHelper(N);
1605 break;
1606 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1607 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1608 case ISD::STORE:
1609 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1610 break;
1611 case ISD::MSTORE:
1612 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1613 break;
1614 case ISD::MSCATTER:
1615 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1616 break;
1617 case ISD::MGATHER:
1618 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1619 break;
1620 case ISD::VSELECT:
1621 Res = SplitVecOp_VSELECT(N, OpNo);
1622 break;
1623 case ISD::FP_TO_SINT:
1624 case ISD::FP_TO_UINT:
1625 if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
1626 Res = SplitVecOp_TruncateHelper(N);
1627 else
1628 Res = SplitVecOp_UnaryOp(N);
1629 break;
1630 case ISD::SINT_TO_FP:
1631 case ISD::UINT_TO_FP:
1632 if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
1633 Res = SplitVecOp_TruncateHelper(N);
1634 else
1635 Res = SplitVecOp_UnaryOp(N);
1636 break;
1637 case ISD::CTTZ:
1638 case ISD::CTLZ:
1639 case ISD::CTPOP:
1640 case ISD::FP_EXTEND:
1641 case ISD::SIGN_EXTEND:
1642 case ISD::ZERO_EXTEND:
1643 case ISD::ANY_EXTEND:
1644 case ISD::FTRUNC:
1645 case ISD::FCANONICALIZE:
1646 Res = SplitVecOp_UnaryOp(N);
1647 break;
1648
1649 case ISD::ANY_EXTEND_VECTOR_INREG:
1650 case ISD::SIGN_EXTEND_VECTOR_INREG:
1651 case ISD::ZERO_EXTEND_VECTOR_INREG:
1652 Res = SplitVecOp_ExtVecInRegOp(N);
1653 break;
1654
1655 case ISD::VECREDUCE_FADD:
1656 case ISD::VECREDUCE_FMUL:
1657 case ISD::VECREDUCE_ADD:
1658 case ISD::VECREDUCE_MUL:
1659 case ISD::VECREDUCE_AND:
1660 case ISD::VECREDUCE_OR:
1661 case ISD::VECREDUCE_XOR:
1662 case ISD::VECREDUCE_SMAX:
1663 case ISD::VECREDUCE_SMIN:
1664 case ISD::VECREDUCE_UMAX:
1665 case ISD::VECREDUCE_UMIN:
1666 case ISD::VECREDUCE_FMAX:
1667 case ISD::VECREDUCE_FMIN:
1668 Res = SplitVecOp_VECREDUCE(N, OpNo);
1669 break;
1670 }
1671 }
1672
1673 // If the result is null, the sub-method took care of registering results etc.
1674 if (!Res.getNode()) return false;
1675
1676 // If the result is N, the sub-method updated N in place. Tell the legalizer
1677 // core about this.
1678 if (Res.getNode() == N)
1679 return true;
1680
1681 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1682, __extension__ __PRETTY_FUNCTION__))
1682 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1682, __extension__ __PRETTY_FUNCTION__))
;
1683
1684 ReplaceValueWith(SDValue(N, 0), Res);
1685 return false;
1686}
1687
1688SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1689 // The only possibility for an illegal operand is the mask, since result type
1690 // legalization would have handled this node already otherwise.
1691 assert(OpNo == 0 && "Illegal operand must be mask")(static_cast <bool> (OpNo == 0 && "Illegal operand must be mask"
) ? void (0) : __assert_fail ("OpNo == 0 && \"Illegal operand must be mask\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1691, __extension__ __PRETTY_FUNCTION__))
;
1692
1693 SDValue Mask = N->getOperand(0);
1694 SDValue Src0 = N->getOperand(1);
1695 SDValue Src1 = N->getOperand(2);
1696 EVT Src0VT = Src0.getValueType();
1697 SDLoc DL(N);
1698 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?")(static_cast <bool> (Mask.getValueType().isVector() &&
"VSELECT without a vector mask?") ? void (0) : __assert_fail
("Mask.getValueType().isVector() && \"VSELECT without a vector mask?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1698, __extension__ __PRETTY_FUNCTION__))
;
1699
1700 SDValue Lo, Hi;
1701 GetSplitVector(N->getOperand(0), Lo, Hi);
1702 assert(Lo.getValueType() == Hi.getValueType() &&(static_cast <bool> (Lo.getValueType() == Hi.getValueType
() && "Lo and Hi have differing types") ? void (0) : __assert_fail
("Lo.getValueType() == Hi.getValueType() && \"Lo and Hi have differing types\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1703, __extension__ __PRETTY_FUNCTION__))
1703 "Lo and Hi have differing types")(static_cast <bool> (Lo.getValueType() == Hi.getValueType
() && "Lo and Hi have differing types") ? void (0) : __assert_fail
("Lo.getValueType() == Hi.getValueType() && \"Lo and Hi have differing types\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1703, __extension__ __PRETTY_FUNCTION__))
;
1704
1705 EVT LoOpVT, HiOpVT;
1706 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1707 assert(LoOpVT == HiOpVT && "Asymmetric vector split?")(static_cast <bool> (LoOpVT == HiOpVT && "Asymmetric vector split?"
) ? void (0) : __assert_fail ("LoOpVT == HiOpVT && \"Asymmetric vector split?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1707, __extension__ __PRETTY_FUNCTION__))
;
1708
1709 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1710 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1711 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1712 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1713
1714 SDValue LoSelect =
1715 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1716 SDValue HiSelect =
1717 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1718
1719 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1720}
1721
1722SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
1723 EVT ResVT = N->getValueType(0);
1724 SDValue Lo, Hi;
1725 SDLoc dl(N);
1726
1727 SDValue VecOp = N->getOperand(OpNo);
1728 EVT VecVT = VecOp.getValueType();
1729 assert(VecVT.isVector() && "Can only split reduce vector operand")(static_cast <bool> (VecVT.isVector() && "Can only split reduce vector operand"
) ? void (0) : __assert_fail ("VecVT.isVector() && \"Can only split reduce vector operand\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1729, __extension__ __PRETTY_FUNCTION__))
;
1730 GetSplitVector(VecOp, Lo, Hi);
1731 EVT LoOpVT, HiOpVT;
1732 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
1733
1734 bool NoNaN = N->getFlags().hasNoNaNs();
1735 unsigned CombineOpc = 0;
1736 switch (N->getOpcode()) {
1737 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
1738 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
1739 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
1740 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
1741 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
1742 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
1743 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
1744 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
1745 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
1746 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
1747 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
1748 case ISD::VECREDUCE_FMAX:
1749 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXNAN;
1750 break;
1751 case ISD::VECREDUCE_FMIN:
1752 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINNAN;
1753 break;
1754 default:
1755 llvm_unreachable("Unexpected reduce ISD node")::llvm::llvm_unreachable_internal("Unexpected reduce ISD node"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1755)
;
1756 }
1757
1758 // Use the appropriate scalar instruction on the split subvectors before
1759 // reducing the now partially reduced smaller vector.
1760 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
1761 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
1762}
1763
1764SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1765 // The result has a legal vector type, but the input needs splitting.
1766 EVT ResVT = N->getValueType(0);
1767 SDValue Lo, Hi;
1768 SDLoc dl(N);
1769 GetSplitVector(N->getOperand(0), Lo, Hi);
1770 EVT InVT = Lo.getValueType();
1771
1772 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1773 InVT.getVectorNumElements());
1774
1775 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1776 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1777
1778 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1779}
1780
1781SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1782 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1783 // end up being split all the way down to individual components. Convert the
1784 // split pieces into integers and reassemble.
1785 SDValue Lo, Hi;
1786 GetSplitVector(N->getOperand(0), Lo, Hi);
1787 Lo = BitConvertToInteger(Lo);
1788 Hi = BitConvertToInteger(Hi);
1789
1790 if (DAG.getDataLayout().isBigEndian())
1791 std::swap(Lo, Hi);
1792
1793 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1794 JoinIntegers(Lo, Hi));
1795}
1796
1797SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1798 // We know that the extracted result type is legal.
1799 EVT SubVT = N->getValueType(0);
1800 SDValue Idx = N->getOperand(1);
1801 SDLoc dl(N);
1802 SDValue Lo, Hi;
1803 GetSplitVector(N->getOperand(0), Lo, Hi);
1804
1805 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1806 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1807
1808 if (IdxVal < LoElts) {
1809 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&(static_cast <bool> (IdxVal + SubVT.getVectorNumElements
() <= LoElts && "Extracted subvector crosses vector split!"
) ? void (0) : __assert_fail ("IdxVal + SubVT.getVectorNumElements() <= LoElts && \"Extracted subvector crosses vector split!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1810, __extension__ __PRETTY_FUNCTION__))
1810 "Extracted subvector crosses vector split!")(static_cast <bool> (IdxVal + SubVT.getVectorNumElements
() <= LoElts && "Extracted subvector crosses vector split!"
) ? void (0) : __assert_fail ("IdxVal + SubVT.getVectorNumElements() <= LoElts && \"Extracted subvector crosses vector split!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1810, __extension__ __PRETTY_FUNCTION__))
;
1811 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1812 } else {
1813 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1814 DAG.getConstant(IdxVal - LoElts, dl,
1815 Idx.getValueType()));
1816 }
1817}
1818
1819SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1820 SDValue Vec = N->getOperand(0);
1821 SDValue Idx = N->getOperand(1);
1822 EVT VecVT = Vec.getValueType();
1823
1824 if (isa<ConstantSDNode>(Idx)) {
1825 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1826 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!")(static_cast <bool> (IdxVal < VecVT.getVectorNumElements
() && "Invalid vector index!") ? void (0) : __assert_fail
("IdxVal < VecVT.getVectorNumElements() && \"Invalid vector index!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1826, __extension__ __PRETTY_FUNCTION__))
;
1827
1828 SDValue Lo, Hi;
1829 GetSplitVector(Vec, Lo, Hi);
1830
1831 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1832
1833 if (IdxVal < LoElts)
1834 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1835 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1836 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1837 Idx.getValueType())), 0);
1838 }
1839
1840 // See if the target wants to custom expand this node.
1841 if (CustomLowerNode(N, N->getValueType(0), true))
1842 return SDValue();
1843
1844 // Make the vector elements byte-addressable if they aren't already.
1845 SDLoc dl(N);
1846 EVT EltVT = VecVT.getVectorElementType();
1847 if (VecVT.getScalarSizeInBits() < 8) {
1848 EltVT = MVT::i8;
1849 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1850 VecVT.getVectorNumElements());
1851 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1852 }
1853
1854 // Store the vector to the stack.
1855 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1856 auto &MF = DAG.getMachineFunction();
1857 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1858 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1859 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1860
1861 // Load back the required element.
1862 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1863 return DAG.getExtLoad(
1864 ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1865 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT);
1866}
1867
1868SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
1869 SDValue Lo, Hi;
1870
1871 // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
1872 // splitting the result has the same effect as splitting the input operand.
1873 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
1874
1875 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
1876}
1877
1878SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1879 unsigned OpNo) {
1880 EVT LoVT, HiVT;
1881 SDLoc dl(MGT);
1882 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1883
1884 SDValue Ch = MGT->getChain();
1885 SDValue Ptr = MGT->getBasePtr();
1886 SDValue Index = MGT->getIndex();
1887 SDValue Scale = MGT->getScale();
1888 SDValue Mask = MGT->getMask();
1889 SDValue Src0 = MGT->getValue();
1890 unsigned Alignment = MGT->getOriginalAlignment();
1891
1892 SDValue MaskLo, MaskHi;
1893 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1894 // Split Mask operand
1895 GetSplitVector(Mask, MaskLo, MaskHi);
1896 else
1897 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1898
1899 EVT MemoryVT = MGT->getMemoryVT();
1900 EVT LoMemVT, HiMemVT;
1901 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1902
1903 SDValue Src0Lo, Src0Hi;
1904 if (getTypeAction(Src0.getValueType()) == TargetLowering::TypeSplitVector)
1905 GetSplitVector(Src0, Src0Lo, Src0Hi);
1906 else
1907 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1908
1909 SDValue IndexHi, IndexLo;
1910 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1911 GetSplitVector(Index, IndexLo, IndexHi);
1912 else
1913 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1914
1915 MachineMemOperand *MMO = DAG.getMachineFunction().
1916 getMachineMemOperand(MGT->getPointerInfo(),
1917 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1918 Alignment, MGT->getAAInfo(), MGT->getRanges());
1919
1920 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo, Scale};
1921 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1922 OpsLo, MMO);
1923
1924 MMO = DAG.getMachineFunction().
1925 getMachineMemOperand(MGT->getPointerInfo(),
1926 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1927 Alignment, MGT->getAAInfo(),
1928 MGT->getRanges());
1929
1930 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi, Scale};
1931 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1932 OpsHi, MMO);
1933
1934 // Build a factor node to remember that this load is independent of the
1935 // other one.
1936 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1937 Hi.getValue(1));
1938
1939 // Legalize the chain result - switch anything that used the old chain to
1940 // use the new one.
1941 ReplaceValueWith(SDValue(MGT, 1), Ch);
1942
1943 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1944 Hi);
1945 ReplaceValueWith(SDValue(MGT, 0), Res);
1946 return SDValue();
1947}
1948
1949SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1950 unsigned OpNo) {
1951 SDValue Ch = N->getChain();
1952 SDValue Ptr = N->getBasePtr();
1953 SDValue Mask = N->getMask();
1954 SDValue Data = N->getValue();
1955 EVT MemoryVT = N->getMemoryVT();
1956 unsigned Alignment = N->getOriginalAlignment();
1957 SDLoc DL(N);
1958
1959 EVT LoMemVT, HiMemVT;
1960 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1961
1962 SDValue DataLo, DataHi;
1963 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
1964 // Split Data operand
1965 GetSplitVector(Data, DataLo, DataHi);
1966 else
1967 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
1968
1969 SDValue MaskLo, MaskHi;
1970 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1971 // Split Mask operand
1972 GetSplitVector(Mask, MaskLo, MaskHi);
1973 else
1974 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
1975
1976 // if Alignment is equal to the vector size,
1977 // take the half of it for the second part
1978 unsigned SecondHalfAlignment =
1979 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1980 Alignment/2 : Alignment;
1981
1982 SDValue Lo, Hi;
1983 MachineMemOperand *MMO = DAG.getMachineFunction().
1984 getMachineMemOperand(N->getPointerInfo(),
1985 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1986 Alignment, N->getAAInfo(), N->getRanges());
1987
1988 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1989 N->isTruncatingStore(),
1990 N->isCompressingStore());
1991
1992 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
1993 N->isCompressingStore());
1994 unsigned HiOffset = LoMemVT.getStoreSize();
1995
1996 MMO = DAG.getMachineFunction().getMachineMemOperand(
1997 N->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOStore,
1998 HiMemVT.getStoreSize(), SecondHalfAlignment, N->getAAInfo(),
1999 N->getRanges());
2000
2001 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
2002 N->isTruncatingStore(), N->isCompressingStore());
2003
2004 // Build a factor node to remember that this store is independent of the
2005 // other one.
2006 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2007}
2008
2009SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
2010 unsigned OpNo) {
2011 SDValue Ch = N->getChain();
2012 SDValue Ptr = N->getBasePtr();
2013 SDValue Mask = N->getMask();
2014 SDValue Index = N->getIndex();
2015 SDValue Scale = N->getScale();
2016 SDValue Data = N->getValue();
2017 EVT MemoryVT = N->getMemoryVT();
2018 unsigned Alignment = N->getOriginalAlignment();
2019 SDLoc DL(N);
2020
2021 // Split all operands
2022 EVT LoMemVT, HiMemVT;
2023 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2024
2025 SDValue DataLo, DataHi;
2026 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2027 // Split Data operand
2028 GetSplitVector(Data, DataLo, DataHi);
2029 else
2030 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2031
2032 SDValue MaskLo, MaskHi;
2033 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2034 // Split Mask operand
2035 GetSplitVector(Mask, MaskLo, MaskHi);
2036 else
2037 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2038
2039 SDValue IndexHi, IndexLo;
2040 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
2041 GetSplitVector(Index, IndexLo, IndexHi);
2042 else
2043 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
2044
2045 SDValue Lo;
2046 MachineMemOperand *MMO = DAG.getMachineFunction().
2047 getMachineMemOperand(N->getPointerInfo(),
2048 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
2049 Alignment, N->getAAInfo(), N->getRanges());
2050
2051 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo, Scale};
2052 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
2053 DL, OpsLo, MMO);
2054
2055 MMO = DAG.getMachineFunction().
2056 getMachineMemOperand(N->getPointerInfo(),
2057 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
2058 Alignment, N->getAAInfo(), N->getRanges());
2059
2060 // The order of the Scatter operation after split is well defined. The "Hi"
2061 // part comes after the "Lo". So these two operations should be chained one
2062 // after another.
2063 SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi, Scale};
2064 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
2065 DL, OpsHi, MMO);
2066}
2067
2068SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
2069 assert(N->isUnindexed() && "Indexed store of vector?")(static_cast <bool> (N->isUnindexed() && "Indexed store of vector?"
) ? void (0) : __assert_fail ("N->isUnindexed() && \"Indexed store of vector?\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2069, __extension__ __PRETTY_FUNCTION__))
;
2070 assert(OpNo == 1 && "Can only split the stored value")(static_cast <bool> (OpNo == 1 && "Can only split the stored value"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Can only split the stored value\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2070, __extension__ __PRETTY_FUNCTION__))
;
2071 SDLoc DL(N);
2072
2073 bool isTruncating = N->isTruncatingStore();
2074 SDValue Ch = N->getChain();
2075 SDValue Ptr = N->getBasePtr();
2076 EVT MemoryVT = N->getMemoryVT();
2077 unsigned Alignment = N->getOriginalAlignment();
2078 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2079 AAMDNodes AAInfo = N->getAAInfo();
2080 SDValue Lo, Hi;
2081 GetSplitVector(N->getOperand(1), Lo, Hi);
2082
2083 EVT LoMemVT, HiMemVT;
2084 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2085
2086 // Scalarize if the split halves are not byte-sized.
2087 if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized())
2088 return TLI.scalarizeVectorStore(N, DAG);
2089
2090 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
2091
2092 if (isTruncating)
2093 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
2094 Alignment, MMOFlags, AAInfo);
2095 else
2096 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2097 AAInfo);
2098
2099 // Increment the pointer to the other half.
2100 Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize);
2101
2102 if (isTruncating)
2103 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
2104 N->getPointerInfo().getWithOffset(IncrementSize),
2105 HiMemVT, Alignment, MMOFlags, AAInfo);
2106 else
2107 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
2108 N->getPointerInfo().getWithOffset(IncrementSize),
2109 Alignment, MMOFlags, AAInfo);
2110
2111 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2112}
2113
2114SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
2115 SDLoc DL(N);
2116
2117 // The input operands all must have the same type, and we know the result
2118 // type is valid. Convert this to a buildvector which extracts all the
2119 // input elements.
2120 // TODO: If the input elements are power-two vectors, we could convert this to
2121 // a new CONCAT_VECTORS node with elements that are half-wide.
2122 SmallVector<SDValue, 32> Elts;
2123 EVT EltVT = N->getValueType(0).getVectorElementType();
2124 for (const SDValue &Op : N->op_values()) {
2125 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
2126 i != e; ++i) {
2127 Elts.push_back(DAG.getNode(
2128 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
2129 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2130 }
2131 }
2132
2133 return DAG.getBuildVector(N->getValueType(0), DL, Elts);
2134}
2135
2136SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
2137 // The result type is legal, but the input type is illegal. If splitting
2138 // ends up with the result type of each half still being legal, just
2139 // do that. If, however, that would result in an illegal result type,
2140 // we can try to get more clever with power-two vectors. Specifically,
2141 // split the input type, but also widen the result element size, then
2142 // concatenate the halves and truncate again. For example, consider a target
2143 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
2144 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
2145 // %inlo = v4i32 extract_subvector %in, 0
2146 // %inhi = v4i32 extract_subvector %in, 4
2147 // %lo16 = v4i16 trunc v4i32 %inlo
2148 // %hi16 = v4i16 trunc v4i32 %inhi
2149 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
2150 // %res = v8i8 trunc v8i16 %in16
2151 //
2152 // Without this transform, the original truncate would end up being
2153 // scalarized, which is pretty much always a last resort.
2154 SDValue InVec = N->getOperand(0);
2155 EVT InVT = InVec->getValueType(0);
2156 EVT OutVT = N->getValueType(0);
2157 unsigned NumElements = OutVT.getVectorNumElements();
2158 bool IsFloat = OutVT.isFloatingPoint();
2159
2160 // Widening should have already made sure this is a power-two vector
2161 // if we're trying to split it at all. assert() that's true, just in case.
2162 assert(!(NumElements & 1) && "Splitting vector, but not in half!")(static_cast <bool> (!(NumElements & 1) && "Splitting vector, but not in half!"
) ? void (0) : __assert_fail ("!(NumElements & 1) && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2162, __extension__ __PRETTY_FUNCTION__))
;
2163
2164 unsigned InElementSize = InVT.getScalarSizeInBits();
2165 unsigned OutElementSize = OutVT.getScalarSizeInBits();
2166
2167 // If the input elements are only 1/2 the width of the result elements,
2168 // just use the normal splitting. Our trick only work if there's room
2169 // to split more than once.
2170 if (InElementSize <= OutElementSize * 2)
2171 return SplitVecOp_UnaryOp(N);
2172 SDLoc DL(N);
2173
2174 // Get the split input vector.
2175 SDValue InLoVec, InHiVec;
2176 GetSplitVector(InVec, InLoVec, InHiVec);
2177 // Truncate them to 1/2 the element size.
2178 EVT HalfElementVT = IsFloat ?
2179 EVT::getFloatingPointVT(InElementSize/2) :
2180 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
2181 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
2182 NumElements/2);
2183 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2184 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
2185 // Concatenate them to get the full intermediate truncation result.
2186 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
2187 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
2188 HalfHi);
2189 // Now finish up by truncating all the way down to the original result
2190 // type. This should normally be something that ends up being legal directly,
2191 // but in theory if a target has very wide vectors and an annoyingly
2192 // restricted set of legal types, this split can chain to build things up.
2193 return IsFloat
2194 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2195 DAG.getTargetConstant(
2196 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
2197 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
2198}
2199
2200SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
2201 assert(N->getValueType(0).isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2203, __extension__ __PRETTY_FUNCTION__))
2202 N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2203, __extension__ __PRETTY_FUNCTION__))
2203 "Operand types must be vectors")(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operand types must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2203, __extension__ __PRETTY_FUNCTION__))
;
2204 // The result has a legal vector type, but the input needs splitting.
2205 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
2206 SDLoc DL(N);
2207 GetSplitVector(N->getOperand(0), Lo0, Hi0);
2208 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2209 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
2210 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
2211 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
2212
2213 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2214 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2215 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2216 return PromoteTargetBoolean(Con, N->getValueType(0));
2217}
2218
2219
2220SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2221 // The result has a legal vector type, but the input needs splitting.
2222 EVT ResVT = N->getValueType(0);
2223 SDValue Lo, Hi;
2224 SDLoc DL(N);
2225 GetSplitVector(N->getOperand(0), Lo, Hi);
2226 EVT InVT = Lo.getValueType();
2227
2228 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2229 InVT.getVectorNumElements());
2230
2231 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2232 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2233
2234 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2235}
2236
2237SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2238 // The result (and the first input) has a legal vector type, but the second
2239 // input needs splitting.
2240 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2241}
2242
2243
2244//===----------------------------------------------------------------------===//
2245// Result Vector Widening
2246//===----------------------------------------------------------------------===//
2247
2248void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2249 LLVM_DEBUG(dbgs() << "Widen node result " << ResNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node result " <<
ResNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
2250 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node result " <<
ResNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
;
2251
2252 // See if the target wants to custom widen this node.
2253 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2254 return;
2255
2256 SDValue Res = SDValue();
2257 switch (N->getOpcode()) {
2258 default:
2259#ifndef NDEBUG
2260 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2261 N->dump(&DAG);
2262 dbgs() << "\n";
2263#endif
2264 llvm_unreachable("Do not know how to widen the result of this operator!")::llvm::llvm_unreachable_internal("Do not know how to widen the result of this operator!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2264)
;
2265
2266 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2267 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2268 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2269 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2270 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2271 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2272 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2273 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2274 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2275 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2276 case ISD::VSELECT:
2277 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2278 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2279 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2280 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2281 case ISD::VECTOR_SHUFFLE:
2282 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2283 break;
2284 case ISD::MLOAD:
2285 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2286 break;
2287 case ISD::MGATHER:
2288 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2289 break;
2290
2291 case ISD::ADD:
2292 case ISD::AND:
2293 case ISD::MUL:
2294 case ISD::MULHS:
2295 case ISD::MULHU:
2296 case ISD::OR:
2297 case ISD::SUB:
2298 case ISD::XOR:
2299 case ISD::FMINNUM:
2300 case ISD::FMAXNUM:
2301 case ISD::FMINNAN:
2302 case ISD::FMAXNAN:
2303 case ISD::SMIN:
2304 case ISD::SMAX:
2305 case ISD::UMIN:
2306 case ISD::UMAX:
2307 Res = WidenVecRes_Binary(N);
2308 break;
2309
2310 case ISD::FADD:
2311 case ISD::FMUL:
2312 case ISD::FPOW:
2313 case ISD::FSUB:
2314 case ISD::FDIV:
2315 case ISD::FREM:
2316 case ISD::SDIV:
2317 case ISD::UDIV:
2318 case ISD::SREM:
2319 case ISD::UREM:
2320 Res = WidenVecRes_BinaryCanTrap(N);
2321 break;
2322
2323 case ISD::FCOPYSIGN:
2324 Res = WidenVecRes_FCOPYSIGN(N);
2325 break;
2326
2327 case ISD::FPOWI:
2328 Res = WidenVecRes_POWI(N);
2329 break;
2330
2331 case ISD::SHL:
2332 case ISD::SRA:
2333 case ISD::SRL:
2334 Res = WidenVecRes_Shift(N);
2335 break;
2336
2337 case ISD::ANY_EXTEND_VECTOR_INREG:
2338 case ISD::SIGN_EXTEND_VECTOR_INREG:
2339 case ISD::ZERO_EXTEND_VECTOR_INREG:
2340 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2341 break;
2342
2343 case ISD::ANY_EXTEND:
2344 case ISD::FP_EXTEND:
2345 case ISD::FP_ROUND:
2346 case ISD::FP_TO_SINT:
2347 case ISD::FP_TO_UINT:
2348 case ISD::SIGN_EXTEND:
2349 case ISD::SINT_TO_FP:
2350 case ISD::TRUNCATE:
2351 case ISD::UINT_TO_FP:
2352 case ISD::ZERO_EXTEND:
2353 Res = WidenVecRes_Convert(N);
2354 break;
2355
2356 case ISD::BITREVERSE:
2357 case ISD::BSWAP:
2358 case ISD::CTLZ:
2359 case ISD::CTPOP:
2360 case ISD::CTTZ:
2361 case ISD::FABS:
2362 case ISD::FCEIL:
2363 case ISD::FCOS:
2364 case ISD::FEXP:
2365 case ISD::FEXP2:
2366 case ISD::FFLOOR:
2367 case ISD::FLOG:
2368 case ISD::FLOG10:
2369 case ISD::FLOG2:
2370 case ISD::FNEARBYINT:
2371 case ISD::FNEG:
2372 case ISD::FRINT:
2373 case ISD::FROUND:
2374 case ISD::FSIN:
2375 case ISD::FSQRT:
2376 case ISD::FTRUNC:
2377 Res = WidenVecRes_Unary(N);
2378 break;
2379 case ISD::FMA:
2380 Res = WidenVecRes_Ternary(N);
2381 break;
2382 }
2383
2384 // If Res is null, the sub-method took care of registering the result.
2385 if (Res.getNode())
2386 SetWidenedVector(SDValue(N, ResNo), Res);
2387}
2388
2389SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2390 // Ternary op widening.
2391 SDLoc dl(N);
2392 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2393 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2394 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2395 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2396 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2397}
2398
2399SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2400 // Binary op widening.
2401 SDLoc dl(N);
2402 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2403 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2404 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2405 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2406}
2407
2408SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2409 // Binary op widening for operations that can trap.
2410 unsigned Opcode = N->getOpcode();
2411 SDLoc dl(N);
2412 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2413 EVT WidenEltVT = WidenVT.getVectorElementType();
2414 EVT VT = WidenVT;
2415 unsigned NumElts = VT.getVectorNumElements();
2416 const SDNodeFlags Flags = N->getFlags();
2417 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2418 NumElts = NumElts / 2;
2419 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2420 }
2421
2422 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2423 // Operation doesn't trap so just widen as normal.
2424 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2425 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2426 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2427 }
2428
2429 // No legal vector version so unroll the vector operation and then widen.
2430 if (NumElts == 1)
2431 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2432
2433 // Since the operation can trap, apply operation on the original vector.
2434 EVT MaxVT = VT;
2435 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2436 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2437 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2438
2439 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2440 unsigned ConcatEnd = 0; // Current ConcatOps index.
2441 int Idx = 0; // Current Idx into input vectors.
2442
2443 // NumElts := greatest legal vector size (at most WidenVT)
2444 // while (orig. vector has unhandled elements) {
2445 // take munches of size NumElts from the beginning and add to ConcatOps
2446 // NumElts := next smaller supported vector size or 1
2447 // }
2448 while (CurNumElts != 0) {
2449 while (CurNumElts >= NumElts) {
2450 SDValue EOp1 = DAG.getNode(
2451 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2452 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2453 SDValue EOp2 = DAG.getNode(
2454 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2455 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2456 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2457 Idx += NumElts;
2458 CurNumElts -= NumElts;
2459 }
2460 do {
2461 NumElts = NumElts / 2;
2462 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2463 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2464
2465 if (NumElts == 1) {
2466 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2467 SDValue EOp1 = DAG.getNode(
2468 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2469 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2470 SDValue EOp2 = DAG.getNode(
2471 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2472 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2473 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2474 EOp1, EOp2, Flags);
2475 }
2476 CurNumElts = 0;
2477 }
2478 }
2479
2480 // Check to see if we have a single operation with the widen type.
2481 if (ConcatEnd == 1) {
2482 VT = ConcatOps[0].getValueType();
2483 if (VT == WidenVT)
2484 return ConcatOps[0];
2485 }
2486
2487 // while (Some element of ConcatOps is not of type MaxVT) {
2488 // From the end of ConcatOps, collect elements of the same type and put
2489 // them into an op of the next larger supported type
2490 // }
2491 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2492 Idx = ConcatEnd - 1;
2493 VT = ConcatOps[Idx--].getValueType();
2494 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2495 Idx--;
2496
2497 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2498 EVT NextVT;
2499 do {
2500 NextSize *= 2;
2501 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2502 } while (!TLI.isTypeLegal(NextVT));
2503
2504 if (!VT.isVector()) {
2505 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2506 SDValue VecOp = DAG.getUNDEF(NextVT);
2507 unsigned NumToInsert = ConcatEnd - Idx - 1;
2508 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2509 VecOp = DAG.getNode(
2510 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2511 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2512 }
2513 ConcatOps[Idx+1] = VecOp;
2514 ConcatEnd = Idx + 2;
2515 } else {
2516 // Vector type, create a CONCAT_VECTORS of type NextVT
2517 SDValue undefVec = DAG.getUNDEF(VT);
2518 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2519 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2520 unsigned RealVals = ConcatEnd - Idx - 1;
2521 unsigned SubConcatEnd = 0;
2522 unsigned SubConcatIdx = Idx + 1;
2523 while (SubConcatEnd < RealVals)
2524 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2525 while (SubConcatEnd < OpsToConcat)
2526 SubConcatOps[SubConcatEnd++] = undefVec;
2527 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2528 NextVT, SubConcatOps);
2529 ConcatEnd = SubConcatIdx + 1;
2530 }
2531 }
2532
2533 // Check to see if we have a single operation with the widen type.
2534 if (ConcatEnd == 1) {
2535 VT = ConcatOps[0].getValueType();
2536 if (VT == WidenVT)
2537 return ConcatOps[0];
2538 }
2539
2540 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2541 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2542 if (NumOps != ConcatEnd ) {
2543 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2544 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2545 ConcatOps[j] = UndefVal;
2546 }
2547 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2548 makeArrayRef(ConcatOps.data(), NumOps));
2549}
2550
2551SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2552 SDValue InOp = N->getOperand(0);
2553 SDLoc DL(N);
2554
2555 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2556 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2557
2558 EVT InVT = InOp.getValueType();
2559 EVT InEltVT = InVT.getVectorElementType();
2560 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2561
2562 unsigned Opcode = N->getOpcode();
2563 unsigned InVTNumElts = InVT.getVectorNumElements();
2564 const SDNodeFlags Flags = N->getFlags();
2565 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2566 InOp = GetWidenedVector(N->getOperand(0));
2567 InVT = InOp.getValueType();
2568 InVTNumElts = InVT.getVectorNumElements();
2569 if (InVTNumElts == WidenNumElts) {
2570 if (N->getNumOperands() == 1)
2571 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2572 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2573 }
2574 if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
2575 // If both input and result vector types are of same width, extend
2576 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
2577 // accepts fewer elements in the result than in the input.
2578 if (Opcode == ISD::SIGN_EXTEND)
2579 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2580 if (Opcode == ISD::ZERO_EXTEND)
2581 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2582 }
2583 }
2584
2585 if (TLI.isTypeLegal(InWidenVT)) {
2586 // Because the result and the input are different vector types, widening
2587 // the result could create a legal type but widening the input might make
2588 // it an illegal type that might lead to repeatedly splitting the input
2589 // and then widening it. To avoid this, we widen the input only if
2590 // it results in a legal type.
2591 if (WidenNumElts % InVTNumElts == 0) {
2592 // Widen the input and call convert on the widened input vector.
2593 unsigned NumConcat = WidenNumElts/InVTNumElts;
2594 SmallVector<SDValue, 16> Ops(NumConcat);
2595 Ops[0] = InOp;
2596 SDValue UndefVal = DAG.getUNDEF(InVT);
2597 for (unsigned i = 1; i != NumConcat; ++i)
2598 Ops[i] = UndefVal;
2599 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2600 if (N->getNumOperands() == 1)
2601 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2602 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2603 }
2604
2605 if (InVTNumElts % WidenNumElts == 0) {
2606 SDValue InVal = DAG.getNode(
2607 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2608 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2609 // Extract the input and convert the shorten input vector.
2610 if (N->getNumOperands() == 1)
2611 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2612 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2613 }
2614 }
2615
2616 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2617 SmallVector<SDValue, 16> Ops(WidenNumElts);
2618 EVT EltVT = WidenVT.getVectorElementType();
2619 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2620 unsigned i;
2621 for (i=0; i < MinElts; ++i) {
2622 SDValue Val = DAG.getNode(
2623 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2624 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2625 if (N->getNumOperands() == 1)
2626 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2627 else
2628 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2629 }
2630
2631 SDValue UndefVal = DAG.getUNDEF(EltVT);
2632 for (; i < WidenNumElts; ++i)
2633 Ops[i] = UndefVal;
2634
2635 return DAG.getBuildVector(WidenVT, DL, Ops);
2636}
2637
2638SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2639 unsigned Opcode = N->getOpcode();
2640 SDValue InOp = N->getOperand(0);
2641 SDLoc DL(N);
2642
2643 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2644 EVT WidenSVT = WidenVT.getVectorElementType();
2645 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2646
2647 EVT InVT = InOp.getValueType();
2648 EVT InSVT = InVT.getVectorElementType();
2649 unsigned InVTNumElts = InVT.getVectorNumElements();
2650
2651 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2652 InOp = GetWidenedVector(InOp);
2653 InVT = InOp.getValueType();
2654 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2655 switch (Opcode) {
2656 case ISD::ANY_EXTEND_VECTOR_INREG:
2657 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2658 case ISD::SIGN_EXTEND_VECTOR_INREG:
2659 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2660 case ISD::ZERO_EXTEND_VECTOR_INREG:
2661 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2662 }
2663 }
2664 }
2665
2666 // Unroll, extend the scalars and rebuild the vector.
2667 SmallVector<SDValue, 16> Ops;
2668 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2669 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2670 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2671 switch (Opcode) {
2672 case ISD::ANY_EXTEND_VECTOR_INREG:
2673 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2674 break;
2675 case ISD::SIGN_EXTEND_VECTOR_INREG:
2676 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2677 break;
2678 case ISD::ZERO_EXTEND_VECTOR_INREG:
2679 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2680 break;
2681 default:
2682 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected")::llvm::llvm_unreachable_internal("A *_EXTEND_VECTOR_INREG node was expected"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2682)
;
2683 }
2684 Ops.push_back(Val);
2685 }
2686
2687 while (Ops.size() != WidenNumElts)
2688 Ops.push_back(DAG.getUNDEF(WidenSVT));
2689
2690 return DAG.getBuildVector(WidenVT, DL, Ops);
2691}
2692
2693SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2694 // If this is an FCOPYSIGN with same input types, we can treat it as a
2695 // normal (can trap) binary op.
2696 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2697 return WidenVecRes_BinaryCanTrap(N);
2698
2699 // If the types are different, fall back to unrolling.
2700 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2701 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2702}
2703
2704SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2705 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2706 SDValue InOp = GetWidenedVector(N->getOperand(0));
2707 SDValue ShOp = N->getOperand(1);
2708 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2709}
2710
2711SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2712 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2713 SDValue InOp = GetWidenedVector(N->getOperand(0));
2714 SDValue ShOp = N->getOperand(1);
2715
2716 EVT ShVT = ShOp.getValueType();
2717 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2718 ShOp = GetWidenedVector(ShOp);
2719 ShVT = ShOp.getValueType();
2720 }
2721 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2722 ShVT.getVectorElementType(),
2723 WidenVT.getVectorNumElements());
2724 if (ShVT != ShWidenVT)
2725 ShOp = ModifyToType(ShOp, ShWidenVT);
2726
2727 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2728}
2729
2730SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2731 // Unary op widening.
2732 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2733 SDValue InOp = GetWidenedVector(N->getOperand(0));
2734 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2735}
2736
2737SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2738 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2739 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2740 cast<VTSDNode>(N->getOperand(1))->getVT()
2741 .getVectorElementType(),
2742 WidenVT.getVectorNumElements());
2743 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2744 return DAG.getNode(N->getOpcode(), SDLoc(N),
2745 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2746}
2747
2748SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2749 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2750 return GetWidenedVector(WidenVec);
2751}
2752
2753SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2754 SDValue InOp = N->getOperand(0);
2755 EVT InVT = InOp.getValueType();
2756 EVT VT = N->getValueType(0);
2757 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2758 SDLoc dl(N);
2759
2760 switch (getTypeAction(InVT)) {
2761 case TargetLowering::TypeLegal:
2762 break;
2763 case TargetLowering::TypePromoteInteger:
2764 // If the incoming type is a vector that is being promoted, then
2765 // we know that the elements are arranged differently and that we
2766 // must perform the conversion using a stack slot.
2767 if (InVT.isVector())
2768 break;
2769
2770 // If the InOp is promoted to the same size, convert it. Otherwise,
2771 // fall out of the switch and widen the promoted input.
2772 InOp = GetPromotedInteger(InOp);
2773 InVT = InOp.getValueType();
2774 if (WidenVT.bitsEq(InVT))
2775 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2776 break;
2777 case TargetLowering::TypeSoftenFloat:
2778 case TargetLowering::TypePromoteFloat:
2779 case TargetLowering::TypeExpandInteger:
2780 case TargetLowering::TypeExpandFloat:
2781 case TargetLowering::TypeScalarizeVector:
2782 case TargetLowering::TypeSplitVector:
2783 break;
2784 case TargetLowering::TypeWidenVector:
2785 // If the InOp is widened to the same size, convert it. Otherwise, fall
2786 // out of the switch and widen the widened input.
2787 InOp = GetWidenedVector(InOp);
2788 InVT = InOp.getValueType();
2789 if (WidenVT.bitsEq(InVT))
2790 // The input widens to the same size. Convert to the widen value.
2791 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2792 break;
2793 }
2794
2795 unsigned WidenSize = WidenVT.getSizeInBits();
2796 unsigned InSize = InVT.getSizeInBits();
2797 // x86mmx is not an acceptable vector element type, so don't try.
2798 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2799 // Determine new input vector type. The new input vector type will use
2800 // the same element type (if its a vector) or use the input type as a
2801 // vector. It is the same size as the type to widen to.
2802 EVT NewInVT;
2803 unsigned NewNumElts = WidenSize / InSize;
2804 if (InVT.isVector()) {
2805 EVT InEltVT = InVT.getVectorElementType();
2806 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2807 WidenSize / InEltVT.getSizeInBits());
2808 } else {
2809 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2810 }
2811
2812 if (TLI.isTypeLegal(NewInVT)) {
2813 // Because the result and the input are different vector types, widening
2814 // the result could create a legal type but widening the input might make
2815 // it an illegal type that might lead to repeatedly splitting the input
2816 // and then widening it. To avoid this, we widen the input only if
2817 // it results in a legal type.
2818 SmallVector<SDValue, 16> Ops(NewNumElts);
2819 SDValue UndefVal = DAG.getUNDEF(InVT);
2820 Ops[0] = InOp;
2821 for (unsigned i = 1; i < NewNumElts; ++i)
2822 Ops[i] = UndefVal;
2823
2824 SDValue NewVec;
2825 if (InVT.isVector())
2826 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2827 else
2828 NewVec = DAG.getBuildVector(NewInVT, dl, Ops);
2829 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2830 }
2831 }
2832
2833 return CreateStackStoreLoad(InOp, WidenVT);
2834}
2835
2836SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2837 SDLoc dl(N);
2838 // Build a vector with undefined for the new nodes.
2839 EVT VT = N->getValueType(0);
2840
2841 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2842 // type. The UNDEFs need to have the same type as the existing operands.
2843 EVT EltVT = N->getOperand(0).getValueType();
2844 unsigned NumElts = VT.getVectorNumElements();
2845
2846 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2847 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2848
2849 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2850 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!")(static_cast <bool> (WidenNumElts >= NumElts &&
"Shrinking vector instead of widening!") ? void (0) : __assert_fail
("WidenNumElts >= NumElts && \"Shrinking vector instead of widening!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2850, __extension__ __PRETTY_FUNCTION__))
;
2851 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2852
2853 return DAG.getBuildVector(WidenVT, dl, NewOps);
2854}
2855
2856SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2857 EVT InVT = N->getOperand(0).getValueType();
2858 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2859 SDLoc dl(N);
2860 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2861 unsigned NumInElts = InVT.getVectorNumElements();
2862 unsigned NumOperands = N->getNumOperands();
2863
2864 bool InputWidened = false; // Indicates we need to widen the input.
2865 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2866 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2867 // Add undef vectors to widen to correct length.
2868 unsigned NumConcat = WidenVT.getVectorNumElements() /
2869 InVT.getVectorNumElements();
2870 SDValue UndefVal = DAG.getUNDEF(InVT);
2871 SmallVector<SDValue, 16> Ops(NumConcat);
2872 for (unsigned i=0; i < NumOperands; ++i)
2873 Ops[i] = N->getOperand(i);
2874 for (unsigned i = NumOperands; i != NumConcat; ++i)
2875 Ops[i] = UndefVal;
2876 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2877 }
2878 } else {
2879 InputWidened = true;
2880 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2881 // The inputs and the result are widen to the same value.
2882 unsigned i;
2883 for (i=1; i < NumOperands; ++i)
2884 if (!N->getOperand(i).isUndef())
2885 break;
2886
2887 if (i == NumOperands)
2888 // Everything but the first operand is an UNDEF so just return the
2889 // widened first operand.
2890 return GetWidenedVector(N->getOperand(0));
2891
2892 if (NumOperands == 2) {
2893 // Replace concat of two operands with a shuffle.
2894 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2895 for (unsigned i = 0; i < NumInElts; ++i) {
2896 MaskOps[i] = i;
2897 MaskOps[i + NumInElts] = i + WidenNumElts;
2898 }
2899 return DAG.getVectorShuffle(WidenVT, dl,
2900 GetWidenedVector(N->getOperand(0)),
2901 GetWidenedVector(N->getOperand(1)),
2902 MaskOps);
2903 }
2904 }
2905 }
2906
2907 // Fall back to use extracts and build vector.
2908 EVT EltVT = WidenVT.getVectorElementType();
2909 SmallVector<SDValue, 16> Ops(WidenNumElts);
2910 unsigned Idx = 0;
2911 for (unsigned i=0; i < NumOperands; ++i) {
2912 SDValue InOp = N->getOperand(i);
2913 if (InputWidened)
2914 InOp = GetWidenedVector(InOp);
2915 for (unsigned j=0; j < NumInElts; ++j)
2916 Ops[Idx++] = DAG.getNode(
2917 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2918 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2919 }
2920 SDValue UndefVal = DAG.getUNDEF(EltVT);
2921 for (; Idx < WidenNumElts; ++Idx)
2922 Ops[Idx] = UndefVal;
2923 return DAG.getBuildVector(WidenVT, dl, Ops);
2924}
2925
2926SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2927 EVT VT = N->getValueType(0);
2928 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2929 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2930 SDValue InOp = N->getOperand(0);
2931 SDValue Idx = N->getOperand(1);
2932 SDLoc dl(N);
2933
2934 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2935 InOp = GetWidenedVector(InOp);
2936
2937 EVT InVT = InOp.getValueType();
2938
2939 // Check if we can just return the input vector after widening.
2940 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2941 if (IdxVal == 0 && InVT == WidenVT)
2942 return InOp;
2943
2944 // Check if we can extract from the vector.
2945 unsigned InNumElts = InVT.getVectorNumElements();
2946 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2947 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2948
2949 // We could try widening the input to the right length but for now, extract
2950 // the original elements, fill the rest with undefs and build a vector.
2951 SmallVector<SDValue, 16> Ops(WidenNumElts);
2952 EVT EltVT = VT.getVectorElementType();
2953 unsigned NumElts = VT.getVectorNumElements();
2954 unsigned i;
2955 for (i=0; i < NumElts; ++i)
2956 Ops[i] =
2957 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2958 DAG.getConstant(IdxVal + i, dl,
2959 TLI.getVectorIdxTy(DAG.getDataLayout())));
2960
2961 SDValue UndefVal = DAG.getUNDEF(EltVT);
2962 for (; i < WidenNumElts; ++i)
2963 Ops[i] = UndefVal;
2964 return DAG.getBuildVector(WidenVT, dl, Ops);
2965}
2966
2967SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2968 SDValue InOp = GetWidenedVector(N->getOperand(0));
2969 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2970 InOp.getValueType(), InOp,
2971 N->getOperand(1), N->getOperand(2));
2972}
2973
2974SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2975 LoadSDNode *LD = cast<LoadSDNode>(N);
2976 ISD::LoadExtType ExtType = LD->getExtensionType();
2977
2978 SDValue Result;
2979 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2980 if (ExtType != ISD::NON_EXTLOAD)
2981 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2982 else
2983 Result = GenWidenVectorLoads(LdChain, LD);
2984
2985 // If we generate a single load, we can use that for the chain. Otherwise,
2986 // build a factor node to remember the multiple loads are independent and
2987 // chain to that.
2988 SDValue NewChain;
2989 if (LdChain.size() == 1)
2990 NewChain = LdChain[0];
2991 else
2992 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2993
2994 // Modified the chain - switch anything that used the old chain to use
2995 // the new one.
2996 ReplaceValueWith(SDValue(N, 1), NewChain);
2997
2998 return Result;
2999}
3000
3001SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
3002
3003 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
3004 SDValue Mask = N->getMask();
3005 EVT MaskVT = Mask.getValueType();
3006 SDValue Src0 = GetWidenedVector(N->getSrc0());
3007 ISD::LoadExtType ExtType = N->getExtensionType();
3008 SDLoc dl(N);
3009
3010 // The mask should be widened as well
3011 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3012 MaskVT.getVectorElementType(),
3013 WidenVT.getVectorNumElements());
3014 Mask = ModifyToType(Mask, WideMaskVT, true);
3015
3016 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
3017 Mask, Src0, N->getMemoryVT(),
3018 N->getMemOperand(), ExtType,
3019 N->isExpandingLoad());
3020 // Legalize the chain result - switch anything that used the old chain to
3021 // use the new one.
3022 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3023 return Res;
3024}
3025
3026SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
3027
3028 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3029 SDValue Mask = N->getMask();
3030 EVT MaskVT = Mask.getValueType();
3031 SDValue Src0 = GetWidenedVector(N->getValue());
3032 SDValue Scale = N->getScale();
3033 unsigned NumElts = WideVT.getVectorNumElements();
3034 SDLoc dl(N);
3035
3036 // The mask should be widened as well
3037 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3038 MaskVT.getVectorElementType(),
3039 WideVT.getVectorNumElements());
3040 Mask = ModifyToType(Mask, WideMaskVT, true);
3041
3042 // Widen the Index operand
3043 SDValue Index = N->getIndex();
3044 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3045 Index.getValueType().getScalarType(),
3046 NumElts);
3047 Index = ModifyToType(Index, WideIndexVT);
3048 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index, Scale };
3049 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
3050 N->getMemoryVT(), dl, Ops,
3051 N->getMemOperand());
3052
3053 // Legalize the chain result - switch anything that used the old chain to
3054 // use the new one.
3055 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3056 return Res;
3057}
3058
3059SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
3060 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3061 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
3062 WidenVT, N->getOperand(0));
3063}
3064
3065// Return true if this is a node that could have two SETCCs as operands.
3066static inline bool isLogicalMaskOp(unsigned Opcode) {
3067 switch (Opcode) {
3068 case ISD::AND:
3069 case ISD::OR:
3070 case ISD::XOR:
3071 return true;
3072 }
3073 return false;
3074}
3075
3076// This is used just for the assert in convertMask(). Check that this either
3077// a SETCC or a previously handled SETCC by convertMask().
3078#ifndef NDEBUG
3079static inline bool isSETCCorConvertedSETCC(SDValue N) {
3080 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
3081 N = N.getOperand(0);
3082 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
3083 for (unsigned i = 1; i < N->getNumOperands(); ++i)
3084 if (!N->getOperand(i)->isUndef())
3085 return false;
3086 N = N.getOperand(0);
3087 }
3088
3089 if (N.getOpcode() == ISD::TRUNCATE)
3090 N = N.getOperand(0);
3091 else if (N.getOpcode() == ISD::SIGN_EXTEND)
3092 N = N.getOperand(0);
3093
3094 if (isLogicalMaskOp(N.getOpcode()))
3095 return isSETCCorConvertedSETCC(N.getOperand(0)) &&
3096 isSETCCorConvertedSETCC(N.getOperand(1));
3097
3098 return (N.getOpcode() == ISD::SETCC ||
3099 ISD::isBuildVectorOfConstantSDNodes(N.getNode()));
3100}
3101#endif
3102
3103// Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
3104// to ToMaskVT if needed with vector extension or truncation.
3105SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
3106 EVT ToMaskVT) {
3107 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
3108 // FIXME: This code seems to be too restrictive, we might consider
3109 // generalizing it or dropping it.
3110 assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.")(static_cast <bool> (isSETCCorConvertedSETCC(InMask) &&
"Unexpected mask argument.") ? void (0) : __assert_fail ("isSETCCorConvertedSETCC(InMask) && \"Unexpected mask argument.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3110, __extension__ __PRETTY_FUNCTION__))
;
3111
3112 // Make a new Mask node, with a legal result VT.
3113 SmallVector<SDValue, 4> Ops;
3114 for (unsigned i = 0, e = InMask->getNumOperands(); i < e; ++i)
3115 Ops.push_back(InMask->getOperand(i));
3116 SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3117
3118 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
3119 // extend or truncate is needed.
3120 LLVMContext &Ctx = *DAG.getContext();
3121 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
3122 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
3123 if (MaskScalarBits < ToMaskScalBits) {
3124 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3125 MaskVT.getVectorNumElements());
3126 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
3127 } else if (MaskScalarBits > ToMaskScalBits) {
3128 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3129 MaskVT.getVectorNumElements());
3130 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
3131 }
3132
3133 assert(Mask->getValueType(0).getScalarSizeInBits() ==(static_cast <bool> (Mask->getValueType(0).getScalarSizeInBits
() == ToMaskVT.getScalarSizeInBits() && "Mask should have the right element size by now."
) ? void (0) : __assert_fail ("Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.getScalarSizeInBits() && \"Mask should have the right element size by now.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3135, __extension__ __PRETTY_FUNCTION__))
3134 ToMaskVT.getScalarSizeInBits() &&(static_cast <bool> (Mask->getValueType(0).getScalarSizeInBits
() == ToMaskVT.getScalarSizeInBits() && "Mask should have the right element size by now."
) ? void (0) : __assert_fail ("Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.getScalarSizeInBits() && \"Mask should have the right element size by now.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3135, __extension__ __PRETTY_FUNCTION__))
3135 "Mask should have the right element size by now.")(static_cast <bool> (Mask->getValueType(0).getScalarSizeInBits
() == ToMaskVT.getScalarSizeInBits() && "Mask should have the right element size by now."
) ? void (0) : __assert_fail ("Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.getScalarSizeInBits() && \"Mask should have the right element size by now.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3135, __extension__ __PRETTY_FUNCTION__))
;
3136
3137 // Adjust Mask to the right number of elements.
3138 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
3139 if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
3140 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
3141 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy);
3142 Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
3143 ZeroIdx);
3144 } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
3145 unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
3146 EVT SubVT = Mask->getValueType(0);
3147 SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
3148 SubOps[0] = Mask;
3149 Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
3150 }
3151
3152 assert((Mask->getValueType(0) == ToMaskVT) &&(static_cast <bool> ((Mask->getValueType(0) == ToMaskVT
) && "A mask of ToMaskVT should have been produced by now."
) ? void (0) : __assert_fail ("(Mask->getValueType(0) == ToMaskVT) && \"A mask of ToMaskVT should have been produced by now.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3153, __extension__ __PRETTY_FUNCTION__))
3153 "A mask of ToMaskVT should have been produced by now.")(static_cast <bool> ((Mask->getValueType(0) == ToMaskVT
) && "A mask of ToMaskVT should have been produced by now."
) ? void (0) : __assert_fail ("(Mask->getValueType(0) == ToMaskVT) && \"A mask of ToMaskVT should have been produced by now.\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3153, __extension__ __PRETTY_FUNCTION__))
;
3154
3155 return Mask;
3156}
3157
3158// Get the target mask VT, and widen if needed.
3159EVT DAGTypeLegalizer::getSETCCWidenedResultTy(SDValue SetCC) {
3160 assert(SetCC->getOpcode() == ISD::SETCC)(static_cast <bool> (SetCC->getOpcode() == ISD::SETCC
) ? void (0) : __assert_fail ("SetCC->getOpcode() == ISD::SETCC"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3160, __extension__ __PRETTY_FUNCTION__))
;
3161 LLVMContext &Ctx = *DAG.getContext();
3162 EVT MaskVT = getSetCCResultType(SetCC->getOperand(0).getValueType());
3163 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3164 MaskVT = TLI.getTypeToTransformTo(Ctx, MaskVT);
3165 return MaskVT;
3166}
3167
3168// This method tries to handle VSELECT and its mask by legalizing operands
3169// (which may require widening) and if needed adjusting the mask vector type
3170// to match that of the VSELECT. Without it, many cases end up with
3171// scalarization of the SETCC, with many unnecessary instructions.
3172SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
3173 LLVMContext &Ctx = *DAG.getContext();
3174 SDValue Cond = N->getOperand(0);
3175
3176 if (N->getOpcode() != ISD::VSELECT)
3177 return SDValue();
3178
3179 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3180 return SDValue();
3181
3182 // If this is a splitted VSELECT that was previously already handled, do
3183 // nothing.
3184 EVT CondVT = Cond->getValueType(0);
3185 if (CondVT.getScalarSizeInBits() != 1)
3186 return SDValue();
3187
3188 EVT VSelVT = N->getValueType(0);
3189 // Only handle vector types which are a power of 2.
3190 if (!isPowerOf2_64(VSelVT.getSizeInBits()))
3191 return SDValue();
3192
3193 // Don't touch if this will be scalarized.
3194 EVT FinalVT = VSelVT;
3195 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
3196 FinalVT = FinalVT.getHalfNumVectorElementsVT(Ctx);
3197
3198 if (FinalVT.getVectorNumElements() == 1)
3199 return SDValue();
3200
3201 // If there is support for an i1 vector mask, don't touch.
3202 if (Cond.getOpcode() == ISD::SETCC) {
3203 EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3204 while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3205 SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3206 EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3207 if (SetCCResVT.getScalarSizeInBits() == 1)
3208 return SDValue();
3209 } else if (CondVT.getScalarType() == MVT::i1) {
3210 // If there is support for an i1 vector mask (or only scalar i1 conditions),
3211 // don't touch.
3212 while (TLI.getTypeAction(Ctx, CondVT) != TargetLowering::TypeLegal)
3213 CondVT = TLI.getTypeToTransformTo(Ctx, CondVT);
3214
3215 if (CondVT.getScalarType() == MVT::i1)
3216 return SDValue();
3217 }
3218
3219 // Get the VT and operands for VSELECT, and widen if needed.
3220 SDValue VSelOp1 = N->getOperand(1);
3221 SDValue VSelOp2 = N->getOperand(2);
3222 if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
3223 VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
3224 VSelOp1 = GetWidenedVector(VSelOp1);
3225 VSelOp2 = GetWidenedVector(VSelOp2);
3226 }
3227
3228 // The mask of the VSELECT should have integer elements.
3229 EVT ToMaskVT = VSelVT;
3230 if (!ToMaskVT.getScalarType().isInteger())
3231 ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
3232
3233 SDValue Mask;
3234 if (Cond->getOpcode() == ISD::SETCC) {
3235 EVT MaskVT = getSETCCWidenedResultTy(Cond);
3236 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3237 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3238 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3239 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3240 // Cond is (AND/OR/XOR (SETCC, SETCC))
3241 SDValue SETCC0 = Cond->getOperand(0);
3242 SDValue SETCC1 = Cond->getOperand(1);
3243 EVT VT0 = getSETCCWidenedResultTy(SETCC0);
3244 EVT VT1 = getSETCCWidenedResultTy(SETCC1);
3245 unsigned ScalarBits0 = VT0.getScalarSizeInBits();
3246 unsigned ScalarBits1 = VT1.getScalarSizeInBits();
3247 unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
3248 EVT MaskVT;
3249 // If the two SETCCs have different VTs, either extend/truncate one of
3250 // them to the other "towards" ToMaskVT, or truncate one and extend the
3251 // other to ToMaskVT.
3252 if (ScalarBits0 != ScalarBits1) {
3253 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
3254 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
3255 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
3256 MaskVT = WideVT;
3257 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
3258 MaskVT = NarrowVT;
3259 else
3260 MaskVT = ToMaskVT;
3261 } else
3262 // If the two SETCCs have the same VT, don't change it.
3263 MaskVT = VT0;
3264
3265 // Make new SETCCs and logical nodes.
3266 SETCC0 = convertMask(SETCC0, VT0, MaskVT);
3267 SETCC1 = convertMask(SETCC1, VT1, MaskVT);
3268 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
3269
3270 // Convert the logical op for VSELECT if needed.
3271 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3272 } else
3273 return SDValue();
3274
3275 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
3276}
3277
3278SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
3279 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3280 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3281
3282 SDValue Cond1 = N->getOperand(0);
3283 EVT CondVT = Cond1.getValueType();
3284 if (CondVT.isVector()) {
3285 if (SDValue Res = WidenVSELECTAndMask(N))
3286 return Res;
3287
3288 EVT CondEltVT = CondVT.getVectorElementType();
3289 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
3290 CondEltVT, WidenNumElts);
3291 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
3292 Cond1 = GetWidenedVector(Cond1);
3293
3294 // If we have to split the condition there is no point in widening the
3295 // select. This would result in an cycle of widening the select ->
3296 // widening the condition operand -> splitting the condition operand ->
3297 // splitting the select -> widening the select. Instead split this select
3298 // further and widen the resulting type.
3299 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
3300 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
3301 SDValue Res = ModifyToType(SplitSelect, WidenVT);
3302 return Res;
3303 }
3304
3305 if (Cond1.getValueType() != CondWidenVT)
3306 Cond1 = ModifyToType(Cond1, CondWidenVT);
3307 }
3308
3309 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3310 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
3311 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT)(static_cast <bool> (InOp1.getValueType() == WidenVT &&
InOp2.getValueType() == WidenVT) ? void (0) : __assert_fail (
"InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3311, __extension__ __PRETTY_FUNCTION__))
;
3312 return DAG.getNode(N->getOpcode(), SDLoc(N),
3313 WidenVT, Cond1, InOp1, InOp2);
3314}
3315
3316SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
3317 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
3318 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
3319 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
3320 InOp1.getValueType(), N->getOperand(0),
3321 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
3322}
3323
3324SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
3325 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3326 return DAG.getUNDEF(WidenVT);
3327}
3328
3329SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
3330 EVT VT = N->getValueType(0);
3331 SDLoc dl(N);
3332
3333 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3334 unsigned NumElts = VT.getVectorNumElements();
3335 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3336
3337 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3338 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3339
3340 // Adjust mask based on new input vector length.
3341 SmallVector<int, 16> NewMask;
3342 for (unsigned i = 0; i != NumElts; ++i) {
3343 int Idx = N->getMaskElt(i);
3344 if (Idx < (int)NumElts)
3345 NewMask.push_back(Idx);
3346 else
3347 NewMask.push_back(Idx - NumElts + WidenNumElts);
3348 }
3349 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3350 NewMask.push_back(-1);
3351 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3352}
3353
3354SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
3355 assert(N->getValueType(0).isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operands must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operands must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3357, __extension__ __PRETTY_FUNCTION__))
3356 N->getOperand(0).getValueType().isVector() &&(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operands must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operands must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3357, __extension__ __PRETTY_FUNCTION__))
3357 "Operands must be vectors")(static_cast <bool> (N->getValueType(0).isVector() &&
N->getOperand(0).getValueType().isVector() && "Operands must be vectors"
) ? void (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operands must be vectors\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3357, __extension__ __PRETTY_FUNCTION__))
;
3358 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3359 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3360
3361 SDValue InOp1 = N->getOperand(0);
3362 EVT InVT = InOp1.getValueType();
3363 assert(InVT.isVector() && "can not widen non-vector type")(static_cast <bool> (InVT.isVector() && "can not widen non-vector type"
) ? void (0) : __assert_fail ("InVT.isVector() && \"can not widen non-vector type\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3363, __extension__ __PRETTY_FUNCTION__))
;
3364 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3365 InVT.getVectorElementType(), WidenNumElts);
3366
3367 // The input and output types often differ here, and it could be that while
3368 // we'd prefer to widen the result type, the input operands have been split.
3369 // In this case, we also need to split the result of this node as well.
3370 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3371 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3372 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3373 return Res;
3374 }
3375
3376 InOp1 = GetWidenedVector(InOp1);
3377 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3378
3379 // Assume that the input and output will be widen appropriately. If not,
3380 // we will have to unroll it at some point.
3381 assert(InOp1.getValueType() == WidenInVT &&(static_cast <bool> (InOp1.getValueType() == WidenInVT &&
InOp2.getValueType() == WidenInVT && "Input not widened to expected type!"
) ? void (0) : __assert_fail ("InOp1.getValueType() == WidenInVT && InOp2.getValueType() == WidenInVT && \"Input not widened to expected type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3383, __extension__ __PRETTY_FUNCTION__))
3382 InOp2.getValueType() == WidenInVT &&(static_cast <bool> (InOp1.getValueType() == WidenInVT &&
InOp2.getValueType() == WidenInVT && "Input not widened to expected type!"
) ? void (0) : __assert_fail ("InOp1.getValueType() == WidenInVT && InOp2.getValueType() == WidenInVT && \"Input not widened to expected type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3383, __extension__ __PRETTY_FUNCTION__))
3383 "Input not widened to expected type!")(static_cast <bool> (InOp1.getValueType() == WidenInVT &&
InOp2.getValueType() == WidenInVT && "Input not widened to expected type!"
) ? void (0) : __assert_fail ("InOp1.getValueType() == WidenInVT && InOp2.getValueType() == WidenInVT && \"Input not widened to expected type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3383, __extension__ __PRETTY_FUNCTION__))
;
3384 (void)WidenInVT;
3385 return DAG.getNode(ISD::SETCC, SDLoc(N),
3386 WidenVT, InOp1, InOp2, N->getOperand(2));
3387}
3388
3389
3390//===----------------------------------------------------------------------===//
3391// Widen Vector Operand
3392//===----------------------------------------------------------------------===//
3393bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3394 LLVM_DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node operand " <<
OpNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
3395 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node operand " <<
OpNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
;
3396 SDValue Res = SDValue();
3397
3398 // See if the target wants to custom widen this node.
3399 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1
Assuming the condition is false
2
Taking false branch
3400 return false;
3401
3402 switch (N->getOpcode()) {
3
Control jumps to 'case MSTORE:' at line 3416
3403 default:
3404#ifndef NDEBUG
3405 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3406 N->dump(&DAG);
3407 dbgs() << "\n";
3408#endif
3409 llvm_unreachable("Do not know how to widen this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to widen this operator's operand!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3409)
;
3410
3411 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3412 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3413 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3414 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3415 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3416 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
4
Calling 'DAGTypeLegalizer::WidenVecOp_MSTORE'
3417 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3418 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3419 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3420
3421 case ISD::ANY_EXTEND:
3422 case ISD::SIGN_EXTEND:
3423 case ISD::ZERO_EXTEND:
3424 Res = WidenVecOp_EXTEND(N);
3425 break;
3426
3427 case ISD::FP_EXTEND:
3428 case ISD::FP_TO_SINT:
3429 case ISD::FP_TO_UINT:
3430 case ISD::SINT_TO_FP:
3431 case ISD::UINT_TO_FP:
3432 case ISD::TRUNCATE:
3433 Res = WidenVecOp_Convert(N);
3434 break;
3435 }
3436
3437 // If Res is null, the sub-method took care of registering the result.
3438 if (!Res.getNode()) return false;
3439
3440 // If the result is N, the sub-method updated N in place. Tell the legalizer
3441 // core about this.
3442 if (Res.getNode() == N)
3443 return true;
3444
3445
3446 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3447, __extension__ __PRETTY_FUNCTION__))
3447 "Invalid operand expansion")(static_cast <bool> (Res.getValueType() == N->getValueType
(0) && N->getNumValues() == 1 && "Invalid operand expansion"
) ? void (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3447, __extension__ __PRETTY_FUNCTION__))
;
3448
3449 ReplaceValueWith(SDValue(N, 0), Res);
3450 return false;
3451}
3452
3453SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3454 SDLoc DL(N);
3455 EVT VT = N->getValueType(0);
3456
3457 SDValue InOp = N->getOperand(0);
3458 assert(getTypeAction(InOp.getValueType()) ==(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3460, __extension__ __PRETTY_FUNCTION__))
3459 TargetLowering::TypeWidenVector &&(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3460, __extension__ __PRETTY_FUNCTION__))
3460 "Unexpected type action")(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3460, __extension__ __PRETTY_FUNCTION__))
;
3461 InOp = GetWidenedVector(InOp);
3462 assert(VT.getVectorNumElements() <(static_cast <bool> (VT.getVectorNumElements() < InOp
.getValueType().getVectorNumElements() && "Input wasn't widened!"
) ? void (0) : __assert_fail ("VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements() && \"Input wasn't widened!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3464, __extension__ __PRETTY_FUNCTION__))
3463 InOp.getValueType().getVectorNumElements() &&(static_cast <bool> (VT.getVectorNumElements() < InOp
.getValueType().getVectorNumElements() && "Input wasn't widened!"
) ? void (0) : __assert_fail ("VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements() && \"Input wasn't widened!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3464, __extension__ __PRETTY_FUNCTION__))
3464 "Input wasn't widened!")(static_cast <bool> (VT.getVectorNumElements() < InOp
.getValueType().getVectorNumElements() && "Input wasn't widened!"
) ? void (0) : __assert_fail ("VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements() && \"Input wasn't widened!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3464, __extension__ __PRETTY_FUNCTION__))
;
3465
3466 // We may need to further widen the operand until it has the same total
3467 // vector size as the result.
3468 EVT InVT = InOp.getValueType();
3469 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3470 EVT InEltVT = InVT.getVectorElementType();
3471 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3472 EVT FixedVT = (MVT::SimpleValueType)i;
3473 EVT FixedEltVT = FixedVT.getVectorElementType();
3474 if (TLI.isTypeLegal(FixedVT) &&
3475 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3476 FixedEltVT == InEltVT) {
3477 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&(static_cast <bool> (FixedVT.getVectorNumElements() >=
VT.getVectorNumElements() && "Not enough elements in the fixed type for the operand!"
) ? void (0) : __assert_fail ("FixedVT.getVectorNumElements() >= VT.getVectorNumElements() && \"Not enough elements in the fixed type for the operand!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3478, __extension__ __PRETTY_FUNCTION__))
3478 "Not enough elements in the fixed type for the operand!")(static_cast <bool> (FixedVT.getVectorNumElements() >=
VT.getVectorNumElements() && "Not enough elements in the fixed type for the operand!"
) ? void (0) : __assert_fail ("FixedVT.getVectorNumElements() >= VT.getVectorNumElements() && \"Not enough elements in the fixed type for the operand!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3478, __extension__ __PRETTY_FUNCTION__))
;
3479 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&(static_cast <bool> (FixedVT.getVectorNumElements() != InVT
.getVectorNumElements() && "We can't have the same type as we started with!"
) ? void (0) : __assert_fail ("FixedVT.getVectorNumElements() != InVT.getVectorNumElements() && \"We can't have the same type as we started with!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3480, __extension__ __PRETTY_FUNCTION__))
3480 "We can't have the same type as we started with!")(static_cast <bool> (FixedVT.getVectorNumElements() != InVT
.getVectorNumElements() && "We can't have the same type as we started with!"
) ? void (0) : __assert_fail ("FixedVT.getVectorNumElements() != InVT.getVectorNumElements() && \"We can't have the same type as we started with!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3480, __extension__ __PRETTY_FUNCTION__))
;
3481 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3482 InOp = DAG.getNode(
3483 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3484 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3485 else
3486 InOp = DAG.getNode(
3487 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3488 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3489 break;
3490 }
3491 }
3492 InVT = InOp.getValueType();
3493 if (InVT.getSizeInBits() != VT.getSizeInBits())
3494 // We couldn't find a legal vector type that was a widening of the input
3495 // and could be extended in-register to the result type, so we have to
3496 // scalarize.
3497 return WidenVecOp_Convert(N);
3498 }
3499
3500 // Use special DAG nodes to represent the operation of extending the
3501 // low lanes.
3502 switch (N->getOpcode()) {
3503 default:
3504 llvm_unreachable("Extend legalization on extend operation!")::llvm::llvm_unreachable_internal("Extend legalization on extend operation!"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3504)
;
3505 case ISD::ANY_EXTEND:
3506 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3507 case ISD::SIGN_EXTEND:
3508 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3509 case ISD::ZERO_EXTEND:
3510 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3511 }
3512}
3513
3514SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3515 // The result (and first input) is legal, but the second input is illegal.
3516 // We can't do much to fix that, so just unroll and let the extracts off of
3517 // the second input be widened as needed later.
3518 return DAG.UnrollVectorOp(N);
3519}
3520
3521SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3522 // Since the result is legal and the input is illegal.
3523 EVT VT = N->getValueType(0);
3524 EVT EltVT = VT.getVectorElementType();
3525 SDLoc dl(N);
3526 unsigned NumElts = VT.getVectorNumElements();
3527 SDValue InOp = N->getOperand(0);
3528 assert(getTypeAction(InOp.getValueType()) ==(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3530, __extension__ __PRETTY_FUNCTION__))
3529 TargetLowering::TypeWidenVector &&(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3530, __extension__ __PRETTY_FUNCTION__))
3530 "Unexpected type action")(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3530, __extension__ __PRETTY_FUNCTION__))
;
3531 InOp = GetWidenedVector(InOp);
3532 EVT InVT = InOp.getValueType();
3533 unsigned Opcode = N->getOpcode();
3534
3535 // See if a widened result type would be legal, if so widen the node.
3536 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
3537 InVT.getVectorNumElements());
3538 if (TLI.isTypeLegal(WideVT)) {
3539 SDValue Res = DAG.getNode(Opcode, dl, WideVT, InOp);
3540 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Res,
3541 DAG.getIntPtrConstant(0, dl));
3542 }
3543
3544 EVT InEltVT = InVT.getVectorElementType();
3545
3546 // Unroll the convert into some scalar code and create a nasty build vector.
3547 SmallVector<SDValue, 16> Ops(NumElts);
3548 for (unsigned i=0; i < NumElts; ++i)
3549 Ops[i] = DAG.getNode(
3550 Opcode, dl, EltVT,
3551 DAG.getNode(
3552 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3553 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3554
3555 return DAG.getBuildVector(VT, dl, Ops);
3556}
3557
3558SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3559 EVT VT = N->getValueType(0);
3560 SDValue InOp = GetWidenedVector(N->getOperand(0));
3561 EVT InWidenVT = InOp.getValueType();
3562 SDLoc dl(N);
3563
3564 // Check if we can convert between two legal vector types and extract.
3565 unsigned InWidenSize = InWidenVT.getSizeInBits();
3566 unsigned Size = VT.getSizeInBits();
3567 // x86mmx is not an acceptable vector element type, so don't try.
3568 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3569 unsigned NewNumElts = InWidenSize / Size;
3570 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3571 if (TLI.isTypeLegal(NewVT)) {
3572 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3573 return DAG.getNode(
3574 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3575 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3576 }
3577 }
3578
3579 return CreateStackStoreLoad(InOp, VT);
3580}
3581
3582SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3583 // If the input vector is not legal, it is likely that we will not find a
3584 // legal vector of the same size. Replace the concatenate vector with a
3585 // nasty build vector.
3586 EVT VT = N->getValueType(0);
3587 EVT EltVT = VT.getVectorElementType();
3588 SDLoc dl(N);
3589 unsigned NumElts = VT.getVectorNumElements();
3590 SmallVector<SDValue, 16> Ops(NumElts);
3591
3592 EVT InVT = N->getOperand(0).getValueType();
3593 unsigned NumInElts = InVT.getVectorNumElements();
3594
3595 unsigned Idx = 0;
3596 unsigned NumOperands = N->getNumOperands();
3597 for (unsigned i=0; i < NumOperands; ++i) {
3598 SDValue InOp = N->getOperand(i);
3599 assert(getTypeAction(InOp.getValueType()) ==(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3601, __extension__ __PRETTY_FUNCTION__))
3600 TargetLowering::TypeWidenVector &&(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3601, __extension__ __PRETTY_FUNCTION__))
3601 "Unexpected type action")(static_cast <bool> (getTypeAction(InOp.getValueType())
== TargetLowering::TypeWidenVector && "Unexpected type action"
) ? void (0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3601, __extension__ __PRETTY_FUNCTION__))
;
3602 InOp = GetWidenedVector(InOp);
3603 for (unsigned j=0; j < NumInElts; ++j)
3604 Ops[Idx++] = DAG.getNode(
3605 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3606 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3607 }
3608 return DAG.getBuildVector(VT, dl, Ops);
3609}
3610
3611SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3612 SDValue InOp = GetWidenedVector(N->getOperand(0));
3613 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3614 N->getValueType(0), InOp, N->getOperand(1));
3615}
3616
3617SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3618 SDValue InOp = GetWidenedVector(N->getOperand(0));
3619 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3620 N->getValueType(0), InOp, N->getOperand(1));
3621}
3622
3623SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3624 // We have to widen the value, but we want only to store the original
3625 // vector type.
3626 StoreSDNode *ST = cast<StoreSDNode>(N);
3627
3628 if (!ST->getMemoryVT().getScalarType().isByteSized())
3629 return TLI.scalarizeVectorStore(ST, DAG);
3630
3631 SmallVector<SDValue, 16> StChain;
3632 if (ST->isTruncatingStore())
3633 GenWidenVectorTruncStores(StChain, ST);
3634 else
3635 GenWidenVectorStores(StChain, ST);
3636
3637 if (StChain.size() == 1)
3638 return StChain[0];
3639 else
3640 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3641}
3642
3643SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3644 assert(OpNo == 3 && "Can widen only data operand of mstore")(static_cast <bool> (OpNo == 3 && "Can widen only data operand of mstore"
) ? void (0) : __assert_fail ("OpNo == 3 && \"Can widen only data operand of mstore\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3644, __extension__ __PRETTY_FUNCTION__))
;
3645 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3646 SDValue Mask = MST->getMask();
3647 EVT MaskVT = Mask.getValueType();
3648 SDValue StVal = MST->getValue();
3649 // Widen the value
3650 SDValue WideVal = GetWidenedVector(StVal);
3651 SDLoc dl(N);
3652
3653 // The mask should be widened as well.
3654 EVT WideVT = WideVal.getValueType();
3655 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3656 MaskVT.getVectorElementType(),
3657 WideVT.getVectorNumElements());
3658 Mask = ModifyToType(Mask, WideMaskVT, true);
5
Calling 'DAGTypeLegalizer::ModifyToType'
3659
3660 assert(Mask.getValueType().getVectorNumElements() ==(static_cast <bool> (Mask.getValueType().getVectorNumElements
() == WideVal.getValueType().getVectorNumElements() &&
"Mask and data vectors should have the same number of elements"
) ? void (0) : __assert_fail ("Mask.getValueType().getVectorNumElements() == WideVal.getValueType().getVectorNumElements() && \"Mask and data vectors should have the same number of elements\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3662, __extension__ __PRETTY_FUNCTION__))
3661 WideVal.getValueType().getVectorNumElements() &&(static_cast <bool> (Mask.getValueType().getVectorNumElements
() == WideVal.getValueType().getVectorNumElements() &&
"Mask and data vectors should have the same number of elements"
) ? void (0) : __assert_fail ("Mask.getValueType().getVectorNumElements() == WideVal.getValueType().getVectorNumElements() && \"Mask and data vectors should have the same number of elements\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3662, __extension__ __PRETTY_FUNCTION__))
3662 "Mask and data vectors should have the same number of elements")(static_cast <bool> (Mask.getValueType().getVectorNumElements
() == WideVal.getValueType().getVectorNumElements() &&
"Mask and data vectors should have the same number of elements"
) ? void (0) : __assert_fail ("Mask.getValueType().getVectorNumElements() == WideVal.getValueType().getVectorNumElements() && \"Mask and data vectors should have the same number of elements\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3662, __extension__ __PRETTY_FUNCTION__))
;
3663 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3664 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3665 false, MST->isCompressingStore());
3666}
3667
3668SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3669 assert(OpNo == 1 && "Can widen only data operand of mscatter")(static_cast <bool> (OpNo == 1 && "Can widen only data operand of mscatter"
) ? void (0) : __assert_fail ("OpNo == 1 && \"Can widen only data operand of mscatter\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3669, __extension__ __PRETTY_FUNCTION__))
;
3670 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3671 SDValue DataOp = MSC->getValue();
3672 SDValue Mask = MSC->getMask();
3673 EVT MaskVT = Mask.getValueType();
3674 SDValue Scale = MSC->getScale();
3675
3676 // Widen the value.
3677 SDValue WideVal = GetWidenedVector(DataOp);
3678 EVT WideVT = WideVal.getValueType();
3679 unsigned NumElts = WideVT.getVectorNumElements();
3680 SDLoc dl(N);
3681
3682 // The mask should be widened as well.
3683 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3684 MaskVT.getVectorElementType(), NumElts);
3685 Mask = ModifyToType(Mask, WideMaskVT, true);
3686
3687 // Widen index.
3688 SDValue Index = MSC->getIndex();
3689 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3690 Index.getValueType().getScalarType(),
3691 NumElts);
3692 Index = ModifyToType(Index, WideIndexVT);
3693
3694 SDValue Ops[] = {MSC->getChain(), WideVal, Mask, MSC->getBasePtr(), Index,
3695 Scale};
3696 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3697 MSC->getMemoryVT(), dl, Ops,
3698 MSC->getMemOperand());
3699}
3700
3701SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3702 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3703 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3704 SDLoc dl(N);
3705 EVT VT = N->getValueType(0);
3706
3707 // WARNING: In this code we widen the compare instruction with garbage.
3708 // This garbage may contain denormal floats which may be slow. Is this a real
3709 // concern ? Should we zero the unused lanes if this is a float compare ?
3710
3711 // Get a new SETCC node to compare the newly widened operands.
3712 // Only some of the compared elements are legal.
3713 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3714 InOp0.getValueType());
3715 // The result type is legal, if its vXi1, keep vXi1 for the new SETCC.
3716 if (VT.getScalarType() == MVT::i1)
3717 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
3718 SVT.getVectorNumElements());
3719
3720 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3721 SVT, InOp0, InOp1, N->getOperand(2));
3722
3723 // Extract the needed results from the result vector.
3724 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3725 SVT.getVectorElementType(),
3726 VT.getVectorNumElements());
3727 SDValue CC = DAG.getNode(
3728 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3729 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3730
3731 return PromoteTargetBoolean(CC, VT);
3732}
3733
3734
3735//===----------------------------------------------------------------------===//
3736// Vector Widening Utilities
3737//===----------------------------------------------------------------------===//
3738
3739// Utility function to find the type to chop up a widen vector for load/store
3740// TLI: Target lowering used to determine legal types.
3741// Width: Width left need to load/store.
3742// WidenVT: The widen vector type to load to/store from
3743// Align: If 0, don't allow use of a wider type
3744// WidenEx: If Align is not 0, the amount additional we can load/store from.
3745
3746static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3747 unsigned Width, EVT WidenVT,
3748 unsigned Align = 0, unsigned WidenEx = 0) {
3749 EVT WidenEltVT = WidenVT.getVectorElementType();
3750 unsigned WidenWidth = WidenVT.getSizeInBits();
3751 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3752 unsigned AlignInBits = Align*8;
3753
3754 // If we have one element to load/store, return it.
3755 EVT RetVT = WidenEltVT;
3756 if (Width == WidenEltWidth)
3757 return RetVT;
3758
3759 // See if there is larger legal integer than the element type to load/store.
3760 unsigned VT;
3761 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3762 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3763 EVT MemVT((MVT::SimpleValueType) VT);
3764 unsigned MemVTWidth = MemVT.getSizeInBits();
3765 if (MemVT.getSizeInBits() <= WidenEltWidth)
3766 break;
3767 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3768 if ((Action == TargetLowering::TypeLegal ||
3769 Action == TargetLowering::TypePromoteInteger) &&
3770 (WidenWidth % MemVTWidth) == 0 &&
3771 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3772 (MemVTWidth <= Width ||
3773 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3774 RetVT = MemVT;
3775 break;
3776 }
3777 }
3778
3779 // See if there is a larger vector type to load/store that has the same vector
3780 // element type and is evenly divisible with the WidenVT.
3781 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3782 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3783 EVT MemVT = (MVT::SimpleValueType) VT;
3784 unsigned MemVTWidth = MemVT.getSizeInBits();
3785 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3786 (WidenWidth % MemVTWidth) == 0 &&
3787 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3788 (MemVTWidth <= Width ||
3789 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3790 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3791 return MemVT;
3792 }
3793 }
3794
3795 return RetVT;
3796}
3797
3798// Builds a vector type from scalar loads
3799// VecTy: Resulting Vector type
3800// LDOps: Load operators to build a vector type
3801// [Start,End) the list of loads to use.
3802static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3803 SmallVectorImpl<SDValue> &LdOps,
3804 unsigned Start, unsigned End) {
3805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3806 SDLoc dl(LdOps[Start]);
3807 EVT LdTy = LdOps[Start].getValueType();
3808 unsigned Width = VecTy.getSizeInBits();
3809 unsigned NumElts = Width / LdTy.getSizeInBits();
3810 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3811
3812 unsigned Idx = 1;
3813 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3814
3815 for (unsigned i = Start + 1; i != End; ++i) {
3816 EVT NewLdTy = LdOps[i].getValueType();
3817 if (NewLdTy != LdTy) {
3818 NumElts = Width / NewLdTy.getSizeInBits();
3819 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3820 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3821 // Readjust position and vector position based on new load type.
3822 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3823 LdTy = NewLdTy;
3824 }
3825 VecOp = DAG.getNode(
3826 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3827 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3828 }
3829 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3830}
3831
3832SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3833 LoadSDNode *LD) {
3834 // The strategy assumes that we can efficiently load power-of-two widths.
3835 // The routine chops the vector into the largest vector loads with the same
3836 // element type or scalar loads and then recombines it to the widen vector
3837 // type.
3838 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3839 unsigned WidenWidth = WidenVT.getSizeInBits();
3840 EVT LdVT = LD->getMemoryVT();
3841 SDLoc dl(LD);
3842 assert(LdVT.isVector() && WidenVT.isVector())(static_cast <bool> (LdVT.isVector() && WidenVT
.isVector()) ? void (0) : __assert_fail ("LdVT.isVector() && WidenVT.isVector()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3842, __extension__ __PRETTY_FUNCTION__))
;
3843 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType())(static_cast <bool> (LdVT.getVectorElementType() == WidenVT
.getVectorElementType()) ? void (0) : __assert_fail ("LdVT.getVectorElementType() == WidenVT.getVectorElementType()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3843, __extension__ __PRETTY_FUNCTION__))
;
3844
3845 // Load information
3846 SDValue Chain = LD->getChain();
3847 SDValue BasePtr = LD->getBasePtr();
3848 unsigned Align = LD->getAlignment();
3849 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
3850 AAMDNodes AAInfo = LD->getAAInfo();
3851
3852 int LdWidth = LdVT.getSizeInBits();
3853 int WidthDiff = WidenWidth - LdWidth;
3854 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
3855
3856 // Find the vector type that can load from.
3857 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3858 int NewVTWidth = NewVT.getSizeInBits();
3859 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3860 Align, MMOFlags, AAInfo);
3861 LdChain.push_back(LdOp.getValue(1));
3862
3863 // Check if we can load the element with one instruction.
3864 if (LdWidth <= NewVTWidth) {
3865 if (!NewVT.isVector()) {
3866 unsigned NumElts = WidenWidth / NewVTWidth;
3867 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3868 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3869 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3870 }
3871 if (NewVT == WidenVT)
3872 return LdOp;
3873
3874 assert(WidenWidth % NewVTWidth == 0)(static_cast <bool> (WidenWidth % NewVTWidth == 0) ? void
(0) : __assert_fail ("WidenWidth % NewVTWidth == 0", "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3874, __extension__ __PRETTY_FUNCTION__))
;
3875 unsigned NumConcat = WidenWidth / NewVTWidth;
3876 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3877 SDValue UndefVal = DAG.getUNDEF(NewVT);
3878 ConcatOps[0] = LdOp;
3879 for (unsigned i = 1; i != NumConcat; ++i)
3880 ConcatOps[i] = UndefVal;
3881 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3882 }
3883
3884 // Load vector by using multiple loads from largest vector to scalar.
3885 SmallVector<SDValue, 16> LdOps;
3886 LdOps.push_back(LdOp);
3887
3888 LdWidth -= NewVTWidth;
3889 unsigned Offset = 0;
3890
3891 while (LdWidth > 0) {
3892 unsigned Increment = NewVTWidth / 8;
3893 Offset += Increment;
3894 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
3895
3896 SDValue L;
3897 if (LdWidth < NewVTWidth) {
3898 // The current type we are using is too large. Find a better size.
3899 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3900 NewVTWidth = NewVT.getSizeInBits();
3901 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3902 LD->getPointerInfo().getWithOffset(Offset),
3903 MinAlign(Align, Increment), MMOFlags, AAInfo);
3904 LdChain.push_back(L.getValue(1));
3905 if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
3906 // Later code assumes the vector loads produced will be mergeable, so we
3907 // must pad the final entry up to the previous width. Scalars are
3908 // combined separately.
3909 SmallVector<SDValue, 16> Loads;
3910 Loads.push_back(L);
3911 unsigned size = L->getValueSizeInBits(0);
3912 while (size < LdOp->getValueSizeInBits(0)) {
3913 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3914 size += L->getValueSizeInBits(0);
3915 }
3916 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3917 }
3918 } else {
3919 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3920 LD->getPointerInfo().getWithOffset(Offset),
3921 MinAlign(Align, Increment), MMOFlags, AAInfo);
3922 LdChain.push_back(L.getValue(1));
3923 }
3924
3925 LdOps.push_back(L);
3926 LdOp = L;
3927
3928 LdWidth -= NewVTWidth;
3929 }
3930
3931 // Build the vector from the load operations.
3932 unsigned End = LdOps.size();
3933 if (!LdOps[0].getValueType().isVector())
3934 // All the loads are scalar loads.
3935 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3936
3937 // If the load contains vectors, build the vector using concat vector.
3938 // All of the vectors used to load are power-of-2, and the scalar loads can be
3939 // combined to make a power-of-2 vector.
3940 SmallVector<SDValue, 16> ConcatOps(End);
3941 int i = End - 1;
3942 int Idx = End;
3943 EVT LdTy = LdOps[i].getValueType();
3944 // First, combine the scalar loads to a vector.
3945 if (!LdTy.isVector()) {
3946 for (--i; i >= 0; --i) {
3947 LdTy = LdOps[i].getValueType();
3948 if (LdTy.isVector())
3949 break;
3950 }
3951 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
3952 }
3953 ConcatOps[--Idx] = LdOps[i];
3954 for (--i; i >= 0; --i) {
3955 EVT NewLdTy = LdOps[i].getValueType();
3956 if (NewLdTy != LdTy) {
3957 // Create a larger vector.
3958 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3959 makeArrayRef(&ConcatOps[Idx], End - Idx));
3960 Idx = End - 1;
3961 LdTy = NewLdTy;
3962 }
3963 ConcatOps[--Idx] = LdOps[i];
3964 }
3965
3966 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
3967 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3968 makeArrayRef(&ConcatOps[Idx], End - Idx));
3969
3970 // We need to fill the rest with undefs to build the vector.
3971 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3972 SmallVector<SDValue, 16> WidenOps(NumOps);
3973 SDValue UndefVal = DAG.getUNDEF(LdTy);
3974 {
3975 unsigned i = 0;
3976 for (; i != End-Idx; ++i)
3977 WidenOps[i] = ConcatOps[Idx+i];
3978 for (; i != NumOps; ++i)
3979 WidenOps[i] = UndefVal;
3980 }
3981 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3982}
3983
3984SDValue
3985DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3986 LoadSDNode *LD,
3987 ISD::LoadExtType ExtType) {
3988 // For extension loads, it may not be more efficient to chop up the vector
3989 // and then extend it. Instead, we unroll the load and build a new vector.
3990 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3991 EVT LdVT = LD->getMemoryVT();
3992 SDLoc dl(LD);
3993 assert(LdVT.isVector() && WidenVT.isVector())(static_cast <bool> (LdVT.isVector() && WidenVT
.isVector()) ? void (0) : __assert_fail ("LdVT.isVector() && WidenVT.isVector()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3993, __extension__ __PRETTY_FUNCTION__))
;
3994
3995 // Load information
3996 SDValue Chain = LD->getChain();
3997 SDValue BasePtr = LD->getBasePtr();
3998 unsigned Align = LD->getAlignment();
3999 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
4000 AAMDNodes AAInfo = LD->getAAInfo();
4001
4002 EVT EltVT = WidenVT.getVectorElementType();
4003 EVT LdEltVT = LdVT.getVectorElementType();
4004 unsigned NumElts = LdVT.getVectorNumElements();
4005
4006 // Load each element and widen.
4007 unsigned WidenNumElts = WidenVT.getVectorNumElements();
4008 SmallVector<SDValue, 16> Ops(WidenNumElts);
4009 unsigned Increment = LdEltVT.getSizeInBits() / 8;
4010 Ops[0] =
4011 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
4012 LdEltVT, Align, MMOFlags, AAInfo);
4013 LdChain.push_back(Ops[0].getValue(1));
4014 unsigned i = 0, Offset = Increment;
4015 for (i=1; i < NumElts; ++i, Offset += Increment) {
4016 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4017 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
4018 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
4019 Align, MMOFlags, AAInfo);
4020 LdChain.push_back(Ops[i].getValue(1));
4021 }
4022
4023 // Fill the rest with undefs.
4024 SDValue UndefVal = DAG.getUNDEF(EltVT);
4025 for (; i != WidenNumElts; ++i)
4026 Ops[i] = UndefVal;
4027
4028 return DAG.getBuildVector(WidenVT, dl, Ops);
4029}
4030
4031void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
4032 StoreSDNode *ST) {
4033 // The strategy assumes that we can efficiently store power-of-two widths.
4034 // The routine chops the vector into the largest vector stores with the same
4035 // element type or scalar stores.
4036 SDValue Chain = ST->getChain();
4037 SDValue BasePtr = ST->getBasePtr();
4038 unsigned Align = ST->getAlignment();
4039 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
4040 AAMDNodes AAInfo = ST->getAAInfo();
4041 SDValue ValOp = GetWidenedVector(ST->getValue());
4042 SDLoc dl(ST);
4043
4044 EVT StVT = ST->getMemoryVT();
4045 unsigned StWidth = StVT.getSizeInBits();
4046 EVT ValVT = ValOp.getValueType();
4047 unsigned ValWidth = ValVT.getSizeInBits();
4048 EVT ValEltVT = ValVT.getVectorElementType();
4049 unsigned ValEltWidth = ValEltVT.getSizeInBits();
4050 assert(StVT.getVectorElementType() == ValEltVT)(static_cast <bool> (StVT.getVectorElementType() == ValEltVT
) ? void (0) : __assert_fail ("StVT.getVectorElementType() == ValEltVT"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4050, __extension__ __PRETTY_FUNCTION__))
;
4051
4052 int Idx = 0; // current index to store
4053 unsigned Offset = 0; // offset from base to store
4054 while (StWidth != 0) {
4055 // Find the largest vector type we can store with.
4056 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
4057 unsigned NewVTWidth = NewVT.getSizeInBits();
4058 unsigned Increment = NewVTWidth / 8;
4059 if (NewVT.isVector()) {
4060 unsigned NumVTElts = NewVT.getVectorNumElements();
4061 do {
4062 SDValue EOp = DAG.getNode(
4063 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
4064 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4065 StChain.push_back(DAG.getStore(
4066 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
4067 MinAlign(Align, Offset), MMOFlags, AAInfo));
4068 StWidth -= NewVTWidth;
4069 Offset += Increment;
4070 Idx += NumVTElts;
4071
4072 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4073 } while (StWidth != 0 && StWidth >= NewVTWidth);
4074 } else {
4075 // Cast the vector to the scalar type we can store.
4076 unsigned NumElts = ValWidth / NewVTWidth;
4077 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
4078 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
4079 // Readjust index position based on new vector type.
4080 Idx = Idx * ValEltWidth / NewVTWidth;
4081 do {
4082 SDValue EOp = DAG.getNode(
4083 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
4084 DAG.getConstant(Idx++, dl,
4085 TLI.getVectorIdxTy(DAG.getDataLayout())));
4086 StChain.push_back(DAG.getStore(
4087 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
4088 MinAlign(Align, Offset), MMOFlags, AAInfo));
4089 StWidth -= NewVTWidth;
4090 Offset += Increment;
4091 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4092 } while (StWidth != 0 && StWidth >= NewVTWidth);
4093 // Restore index back to be relative to the original widen element type.
4094 Idx = Idx * NewVTWidth / ValEltWidth;
4095 }
4096 }
4097}
4098
4099void
4100DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
4101 StoreSDNode *ST) {
4102 // For extension loads, it may not be more efficient to truncate the vector
4103 // and then store it. Instead, we extract each element and then store it.
4104 SDValue Chain = ST->getChain();
4105 SDValue BasePtr = ST->getBasePtr();
4106 unsigned Align = ST->getAlignment();
4107 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
4108 AAMDNodes AAInfo = ST->getAAInfo();
4109 SDValue ValOp = GetWidenedVector(ST->getValue());
4110 SDLoc dl(ST);
4111
4112 EVT StVT = ST->getMemoryVT();
4113 EVT ValVT = ValOp.getValueType();
4114
4115 // It must be true that the wide vector type is bigger than where we need to
4116 // store.
4117 assert(StVT.isVector() && ValOp.getValueType().isVector())(static_cast <bool> (StVT.isVector() && ValOp.getValueType
().isVector()) ? void (0) : __assert_fail ("StVT.isVector() && ValOp.getValueType().isVector()"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4117, __extension__ __PRETTY_FUNCTION__))
;
4118 assert(StVT.bitsLT(ValOp.getValueType()))(static_cast <bool> (StVT.bitsLT(ValOp.getValueType()))
? void (0) : __assert_fail ("StVT.bitsLT(ValOp.getValueType())"
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4118, __extension__ __PRETTY_FUNCTION__))
;
4119
4120 // For truncating stores, we can not play the tricks of chopping legal vector
4121 // types and bitcast it to the right type. Instead, we unroll the store.
4122 EVT StEltVT = StVT.getVectorElementType();
4123 EVT ValEltVT = ValVT.getVectorElementType();
4124 unsigned Increment = ValEltVT.getSizeInBits() / 8;
4125 unsigned NumElts = StVT.getVectorNumElements();
4126 SDValue EOp = DAG.getNode(
4127 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4128 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4129 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
4130 ST->getPointerInfo(), StEltVT, Align,
4131 MMOFlags, AAInfo));
4132 unsigned Offset = Increment;
4133 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
4134 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4135 SDValue EOp = DAG.getNode(
4136 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4137 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4138 StChain.push_back(DAG.getTruncStore(
4139 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
4140 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
4141 }
4142}
4143
4144/// Modifies a vector input (widen or narrows) to a vector of NVT. The
4145/// input vector must have the same element type as NVT.
4146/// FillWithZeroes specifies that the vector should be widened with zeroes.
4147SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
4148 bool FillWithZeroes) {
4149 // Note that InOp might have been widened so it might already have
4150 // the right width or it might need be narrowed.
4151 EVT InVT = InOp.getValueType();
4152 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&(static_cast <bool> (InVT.getVectorElementType() == NVT
.getVectorElementType() && "input and widen element type must match"
) ? void (0) : __assert_fail ("InVT.getVectorElementType() == NVT.getVectorElementType() && \"input and widen element type must match\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4153, __extension__ __PRETTY_FUNCTION__))
4153 "input and widen element type must match")(static_cast <bool> (InVT.getVectorElementType() == NVT
.getVectorElementType() && "input and widen element type must match"
) ? void (0) : __assert_fail ("InVT.getVectorElementType() == NVT.getVectorElementType() && \"input and widen element type must match\""
, "/build/llvm-toolchain-snapshot-7~svn338205/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4153, __extension__ __PRETTY_FUNCTION__))
;
4154 SDLoc dl(InOp);
4155
4156 // Check if InOp already has the right width.
4157 if (InVT == NVT)
6
Taking false branch
4158 return InOp;
4159
4160 unsigned InNumElts = InVT.getVectorNumElements();
7
Calling 'EVT::getVectorNumElements'
10
Returning from 'EVT::getVectorNumElements'
11
'InNumElts' initialized here
4161 unsigned WidenNumElts = NVT.getVectorNumElements();
4162 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
12
Assuming 'WidenNumElts' is > 'InNumElts'
13
Division by zero
4163 unsigned NumConcat = WidenNumElts / InNumElts;
4164 SmallVector<SDValue, 16> Ops(NumConcat);
4165 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
4166 DAG.getUNDEF(InVT);
4167 Ops[0] = InOp;
4168 for (unsigned i = 1; i != NumConcat; ++i)
4169 Ops[i] = FillVal;
4170
4171 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
4172 }
4173
4174 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
4175 return DAG.getNode(
4176 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
4177 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4178
4179 // Fall back to extract and build.
4180 SmallVector<SDValue, 16> Ops(WidenNumElts);
4181 EVT EltVT = NVT.getVectorElementType();
4182 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
4183 unsigned Idx;
4184 for (Idx = 0; Idx < MinNumElts; ++Idx)
4185 Ops[Idx] = DAG.getNode(
4186 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4187 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4188
4189 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
4190 DAG.getUNDEF(EltVT);
4191 for ( ; Idx < WidenNumElts; ++Idx)
4192 Ops[Idx] = FillVal;
4193 return DAG.getBuildVector(NVT, dl, Ops);
4194}

/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h

1//===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the set of low-level target independent types which various
11// values in the code generator are. This allows the target specific behavior
12// of instructions to be described to target independent passes.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_CODEGEN_VALUETYPES_H
17#define LLVM_CODEGEN_VALUETYPES_H
18
19#include "llvm/Support/Compiler.h"
20#include "llvm/Support/MachineValueType.h"
21#include "llvm/Support/MathExtras.h"
22#include <cassert>
23#include <cstdint>
24#include <string>
25
26namespace llvm {
27
28 class LLVMContext;
29 class Type;
30
31 /// Extended Value Type. Capable of holding value types which are not native
32 /// for any processor (such as the i12345 type), as well as the types an MVT
33 /// can represent.
34 struct EVT {
35 private:
36 MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE;
37 Type *LLVMTy = nullptr;
38
39 public:
40 constexpr EVT() = default;
41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {}
42 constexpr EVT(MVT S) : V(S) {}
43
44 bool operator==(EVT VT) const {
45 return !(*this != VT);
46 }
47 bool operator!=(EVT VT) const {
48 if (V.SimpleTy != VT.V.SimpleTy)
49 return true;
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
51 return LLVMTy != VT.LLVMTy;
52 return false;
53 }
54
55 /// Returns the EVT that represents a floating-point type with the given
56 /// number of bits. There are two floating-point types with 128 bits - this
57 /// returns f128 rather than ppcf128.
58 static EVT getFloatingPointVT(unsigned BitWidth) {
59 return MVT::getFloatingPointVT(BitWidth);
60 }
61
62 /// Returns the EVT that represents an integer with the given number of
63 /// bits.
64 static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth) {
65 MVT M = MVT::getIntegerVT(BitWidth);
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
67 return M;
68 return getExtendedIntegerVT(Context, BitWidth);
69 }
70
71 /// Returns the EVT that represents a vector NumElements in length, where
72 /// each element is of type VT.
73 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
74 bool IsScalable = false) {
75 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
77 return M;
78
79 assert(!IsScalable && "We don't support extended scalable types yet")(static_cast <bool> (!IsScalable && "We don't support extended scalable types yet"
) ? void (0) : __assert_fail ("!IsScalable && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 79, __extension__ __PRETTY_FUNCTION__))
;
80 return getExtendedVectorVT(Context, VT, NumElements);
81 }
82
83 /// Returns the EVT that represents a vector EC.Min elements in length,
84 /// where each element is of type VT.
85 static EVT getVectorVT(LLVMContext &Context, EVT VT, MVT::ElementCount EC) {
86 MVT M = MVT::getVectorVT(VT.V, EC);
87 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
88 return M;
89 assert (!EC.Scalable && "We don't support extended scalable types yet")(static_cast <bool> (!EC.Scalable && "We don't support extended scalable types yet"
) ? void (0) : __assert_fail ("!EC.Scalable && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 89, __extension__ __PRETTY_FUNCTION__))
;
90 return getExtendedVectorVT(Context, VT, EC.Min);
91 }
92
93 /// Return a vector with the same number of elements as this vector, but
94 /// with the element type converted to an integer type with the same
95 /// bitwidth.
96 EVT changeVectorElementTypeToInteger() const {
97 if (!isSimple()) {
98 assert (!isScalableVector() &&(static_cast <bool> (!isScalableVector() && "We don't support extended scalable types yet"
) ? void (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 99, __extension__ __PRETTY_FUNCTION__))
99 "We don't support extended scalable types yet")(static_cast <bool> (!isScalableVector() && "We don't support extended scalable types yet"
) ? void (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 99, __extension__ __PRETTY_FUNCTION__))
;
100 return changeExtendedVectorElementTypeToInteger();
101 }
102 MVT EltTy = getSimpleVT().getVectorElementType();
103 unsigned BitWidth = EltTy.getSizeInBits();
104 MVT IntTy = MVT::getIntegerVT(BitWidth);
105 MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements(),
106 isScalableVector());
107 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE
&& "Simple vector VT not representable by simple integer vector VT!"
) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 108, __extension__ __PRETTY_FUNCTION__))
108 "Simple vector VT not representable by simple integer vector VT!")(static_cast <bool> (VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE
&& "Simple vector VT not representable by simple integer vector VT!"
) ? void (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 108, __extension__ __PRETTY_FUNCTION__))
;
109 return VecTy;
110 }
111
112 /// Return the type converted to an equivalently sized integer or vector
113 /// with integer element type. Similar to changeVectorElementTypeToInteger,
114 /// but also handles scalars.
115 EVT changeTypeToInteger() {
116 if (isVector())
117 return changeVectorElementTypeToInteger();
118
119 if (isSimple())
120 return MVT::getIntegerVT(getSizeInBits());
121
122 return changeExtendedTypeToInteger();
123 }
124
125 /// Test if the given EVT is simple (as opposed to being extended).
126 bool isSimple() const {
127 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE;
128 }
129
130 /// Test if the given EVT is extended (as opposed to being simple).
131 bool isExtended() const {
132 return !isSimple();
133 }
134
135 /// Return true if this is a FP or a vector FP type.
136 bool isFloatingPoint() const {
137 return isSimple() ? V.isFloatingPoint() : isExtendedFloatingPoint();
138 }
139
140 /// Return true if this is an integer or a vector integer type.
141 bool isInteger() const {
142 return isSimple() ? V.isInteger() : isExtendedInteger();
143 }
144
145 /// Return true if this is an integer, but not a vector.
146 bool isScalarInteger() const {
147 return isSimple() ? V.isScalarInteger() : isExtendedScalarInteger();
148 }
149
150 /// Return true if this is a vector value type.
151 bool isVector() const {
152 return isSimple() ? V.isVector() : isExtendedVector();
153 }
154
155 /// Return true if this is a vector type where the runtime
156 /// length is machine dependent
157 bool isScalableVector() const {
158 // FIXME: We don't support extended scalable types yet, because the
159 // matching IR type doesn't exist. Once it has been added, this can
160 // be changed to call isExtendedScalableVector.
161 if (!isSimple())
162 return false;
163 return V.isScalableVector();
164 }
165
166 /// Return true if this is a 16-bit vector type.
167 bool is16BitVector() const {
168 return isSimple() ? V.is16BitVector() : isExtended16BitVector();
169 }
170
171 /// Return true if this is a 32-bit vector type.
172 bool is32BitVector() const {
173 return isSimple() ? V.is32BitVector() : isExtended32BitVector();
174 }
175
176 /// Return true if this is a 64-bit vector type.
177 bool is64BitVector() const {
178 return isSimple() ? V.is64BitVector() : isExtended64BitVector();
179 }
180
181 /// Return true if this is a 128-bit vector type.
182 bool is128BitVector() const {
183 return isSimple() ? V.is128BitVector() : isExtended128BitVector();
184 }
185
186 /// Return true if this is a 256-bit vector type.
187 bool is256BitVector() const {
188 return isSimple() ? V.is256BitVector() : isExtended256BitVector();
189 }
190
191 /// Return true if this is a 512-bit vector type.
192 bool is512BitVector() const {
193 return isSimple() ? V.is512BitVector() : isExtended512BitVector();
194 }
195
196 /// Return true if this is a 1024-bit vector type.
197 bool is1024BitVector() const {
198 return isSimple() ? V.is1024BitVector() : isExtended1024BitVector();
199 }
200
201 /// Return true if this is a 2048-bit vector type.
202 bool is2048BitVector() const {
203 return isSimple() ? V.is2048BitVector() : isExtended2048BitVector();
204 }
205
206 /// Return true if this is an overloaded type for TableGen.
207 bool isOverloaded() const {
208 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
209 }
210
211 /// Return true if the bit size is a multiple of 8.
212 bool isByteSized() const {
213 return (getSizeInBits() & 7) == 0;
214 }
215
216 /// Return true if the size is a power-of-two number of bytes.
217 bool isRound() const {
218 unsigned BitSize = getSizeInBits();
219 return BitSize >= 8 && !(BitSize & (BitSize - 1));
220 }
221
222 /// Return true if this has the same number of bits as VT.
223 bool bitsEq(EVT VT) const {
224 if (EVT::operator==(VT)) return true;
225 return getSizeInBits() == VT.getSizeInBits();
226 }
227
228 /// Return true if this has more bits than VT.
229 bool bitsGT(EVT VT) const {
230 if (EVT::operator==(VT)) return false;
231 return getSizeInBits() > VT.getSizeInBits();
232 }
233
234 /// Return true if this has no less bits than VT.
235 bool bitsGE(EVT VT) const {
236 if (EVT::operator==(VT)) return true;
237 return getSizeInBits() >= VT.getSizeInBits();
238 }
239
240 /// Return true if this has less bits than VT.
241 bool bitsLT(EVT VT) const {
242 if (EVT::operator==(VT)) return false;
243 return getSizeInBits() < VT.getSizeInBits();
244 }
245
246 /// Return true if this has no more bits than VT.
247 bool bitsLE(EVT VT) const {
248 if (EVT::operator==(VT)) return true;
249 return getSizeInBits() <= VT.getSizeInBits();
250 }
251
252 /// Return the SimpleValueType held in the specified simple EVT.
253 MVT getSimpleVT() const {
254 assert(isSimple() && "Expected a SimpleValueType!")(static_cast <bool> (isSimple() && "Expected a SimpleValueType!"
) ? void (0) : __assert_fail ("isSimple() && \"Expected a SimpleValueType!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 254, __extension__ __PRETTY_FUNCTION__))
;
255 return V;
256 }
257
258 /// If this is a vector type, return the element type, otherwise return
259 /// this.
260 EVT getScalarType() const {
261 return isVector() ? getVectorElementType() : *this;
262 }
263
264 /// Given a vector type, return the type of each element.
265 EVT getVectorElementType() const {
266 assert(isVector() && "Invalid vector type!")(static_cast <bool> (isVector() && "Invalid vector type!"
) ? void (0) : __assert_fail ("isVector() && \"Invalid vector type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 266, __extension__ __PRETTY_FUNCTION__))
;
267 if (isSimple())
268 return V.getVectorElementType();
269 return getExtendedVectorElementType();
270 }
271
272 /// Given a vector type, return the number of elements it contains.
273 unsigned getVectorNumElements() const {
274 assert(isVector() && "Invalid vector type!")(static_cast <bool> (isVector() && "Invalid vector type!"
) ? void (0) : __assert_fail ("isVector() && \"Invalid vector type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 274, __extension__ __PRETTY_FUNCTION__))
;
8
Within the expansion of the macro 'assert':
a
Assuming the condition is true
275 if (isSimple())
9
Taking false branch
276 return V.getVectorNumElements();
277 return getExtendedVectorNumElements();
278 }
279
280 // Given a (possibly scalable) vector type, return the ElementCount
281 MVT::ElementCount getVectorElementCount() const {
282 assert((isVector()) && "Invalid vector type!")(static_cast <bool> ((isVector()) && "Invalid vector type!"
) ? void (0) : __assert_fail ("(isVector()) && \"Invalid vector type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 282, __extension__ __PRETTY_FUNCTION__))
;
283 if (isSimple())
284 return V.getVectorElementCount();
285
286 assert(!isScalableVector() &&(static_cast <bool> (!isScalableVector() && "We don't support extended scalable types yet"
) ? void (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 287, __extension__ __PRETTY_FUNCTION__))
287 "We don't support extended scalable types yet")(static_cast <bool> (!isScalableVector() && "We don't support extended scalable types yet"
) ? void (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 287, __extension__ __PRETTY_FUNCTION__))
;
288 return {getExtendedVectorNumElements(), false};
289 }
290
291 /// Return the size of the specified value type in bits.
292 unsigned getSizeInBits() const {
293 if (isSimple())
294 return V.getSizeInBits();
295 return getExtendedSizeInBits();
296 }
297
298 unsigned getScalarSizeInBits() const {
299 return getScalarType().getSizeInBits();
300 }
301
302 /// Return the number of bytes overwritten by a store of the specified value
303 /// type.
304 unsigned getStoreSize() const {
305 return (getSizeInBits() + 7) / 8;
306 }
307
308 /// Return the number of bits overwritten by a store of the specified value
309 /// type.
310 unsigned getStoreSizeInBits() const {
311 return getStoreSize() * 8;
312 }
313
314 /// Rounds the bit-width of the given integer EVT up to the nearest power of
315 /// two (and at least to eight), and returns the integer EVT with that
316 /// number of bits.
317 EVT getRoundIntegerType(LLVMContext &Context) const {
318 assert(isInteger() && !isVector() && "Invalid integer type!")(static_cast <bool> (isInteger() && !isVector()
&& "Invalid integer type!") ? void (0) : __assert_fail
("isInteger() && !isVector() && \"Invalid integer type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 318, __extension__ __PRETTY_FUNCTION__))
;
319 unsigned BitWidth = getSizeInBits();
320 if (BitWidth <= 8)
321 return EVT(MVT::i8);
322 return getIntegerVT(Context, 1 << Log2_32_Ceil(BitWidth));
323 }
324
325 /// Finds the smallest simple value type that is greater than or equal to
326 /// half the width of this EVT. If no simple value type can be found, an
327 /// extended integer value type of half the size (rounded up) is returned.
328 EVT getHalfSizedIntegerVT(LLVMContext &Context) const {
329 assert(isInteger() && !isVector() && "Invalid integer type!")(static_cast <bool> (isInteger() && !isVector()
&& "Invalid integer type!") ? void (0) : __assert_fail
("isInteger() && !isVector() && \"Invalid integer type!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 329, __extension__ __PRETTY_FUNCTION__))
;
330 unsigned EVTSize = getSizeInBits();
331 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
332 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) {
333 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT);
334 if (HalfVT.getSizeInBits() * 2 >= EVTSize)
335 return HalfVT;
336 }
337 return getIntegerVT(Context, (EVTSize + 1) / 2);
338 }
339
340 /// Return a VT for an integer vector type with the size of the
341 /// elements doubled. The typed returned may be an extended type.
342 EVT widenIntegerVectorElementType(LLVMContext &Context) const {
343 EVT EltVT = getVectorElementType();
344 EltVT = EVT::getIntegerVT(Context, 2 * EltVT.getSizeInBits());
345 return EVT::getVectorVT(Context, EltVT, getVectorElementCount());
346 }
347
348 // Return a VT for a vector type with the same element type but
349 // half the number of elements. The type returned may be an
350 // extended type.
351 EVT getHalfNumVectorElementsVT(LLVMContext &Context) const {
352 EVT EltVT = getVectorElementType();
353 auto EltCnt = getVectorElementCount();
354 assert(!(EltCnt.Min & 1) && "Splitting vector, but not in half!")(static_cast <bool> (!(EltCnt.Min & 1) && "Splitting vector, but not in half!"
) ? void (0) : __assert_fail ("!(EltCnt.Min & 1) && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-7~svn338205/include/llvm/CodeGen/ValueTypes.h"
, 354, __extension__ __PRETTY_FUNCTION__))
;
355 return EVT::getVectorVT(Context, EltVT, EltCnt / 2);
356 }
357
358 /// Returns true if the given vector is a power of 2.
359 bool isPow2VectorType() const {
360 unsigned NElts = getVectorNumElements();
361 return !(NElts & (NElts - 1));
362 }
363
364 /// Widens the length of the given vector EVT up to the nearest power of 2
365 /// and returns that type.
366 EVT getPow2VectorType(LLVMContext &Context) const {
367 if (!isPow2VectorType()) {
368 unsigned NElts = getVectorNumElements();
369 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
370 return EVT::getVectorVT(Context, getVectorElementType(), Pow2NElts,
371 isScalableVector());
372 }
373 else {
374 return *this;
375 }
376 }
377
378 /// This function returns value type as a string, e.g. "i32".
379 std::string getEVTString() const;
380
381 /// This method returns an LLVM type corresponding to the specified EVT.
382 /// For integer types, this returns an unsigned type. Note that this will
383 /// abort for types that cannot be represented.
384 Type *getTypeForEVT(LLVMContext &Context) const;
385
386 /// Return the value type corresponding to the specified type.
387 /// This returns all pointers as iPTR. If HandleUnknown is true, unknown
388 /// types are returned as Other, otherwise they are invalid.
389 static EVT getEVT(Type *Ty, bool HandleUnknown = false);
390
391 intptr_t getRawBits() const {
392 if (isSimple())
393 return V.SimpleTy;
394 else
395 return (intptr_t)(LLVMTy);
396 }
397
398 /// A meaningless but well-behaved order, useful for constructing
399 /// containers.
400 struct compareRawBits {
401 bool operator()(EVT L, EVT R) const {
402 if (L.V.SimpleTy == R.V.SimpleTy)
403 return L.LLVMTy < R.LLVMTy;
404 else
405 return L.V.SimpleTy < R.V.SimpleTy;
406 }
407 };
408
409 private:
410 // Methods for handling the Extended-type case in functions above.
411 // These are all out-of-line to prevent users of this header file
412 // from having a dependency on Type.h.
413 EVT changeExtendedTypeToInteger() const;
414 EVT changeExtendedVectorElementTypeToInteger() const;
415 static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
416 static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
417 unsigned NumElements);
418 bool isExtendedFloatingPoint() const LLVM_READONLY__attribute__((__pure__));
419 bool isExtendedInteger() const LLVM_READONLY__attribute__((__pure__));
420 bool isExtendedScalarInteger() const LLVM_READONLY__attribute__((__pure__));
421 bool isExtendedVector() const LLVM_READONLY__attribute__((__pure__));
422 bool isExtended16BitVector() const LLVM_READONLY__attribute__((__pure__));
423 bool isExtended32BitVector() const LLVM_READONLY__attribute__((__pure__));
424 bool isExtended64BitVector() const LLVM_READONLY__attribute__((__pure__));
425 bool isExtended128BitVector() const LLVM_READONLY__attribute__((__pure__));
426 bool isExtended256BitVector() const LLVM_READONLY__attribute__((__pure__));
427 bool isExtended512BitVector() const LLVM_READONLY__attribute__((__pure__));
428 bool isExtended1024BitVector() const LLVM_READONLY__attribute__((__pure__));
429 bool isExtended2048BitVector() const LLVM_READONLY__attribute__((__pure__));
430 EVT getExtendedVectorElementType() const;
431 unsigned getExtendedVectorNumElements() const LLVM_READONLY__attribute__((__pure__));
432 unsigned getExtendedSizeInBits() const LLVM_READONLY__attribute__((__pure__));
433 };
434
435} // end namespace llvm
436
437#endif // LLVM_CODEGEN_VALUETYPES_H