Bug Summary

File:lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Warning:line 4420, column 48
Division by zero

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LegalizeVectorTypes.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/CodeGen/SelectionDAG -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp -faddrsig

/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

1//===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file performs vector type splitting and scalarization for LegalizeTypes.
11// Scalarization is the act of changing a computation in an illegal one-element
12// vector type to be a computation in its scalar element type. For example,
13// implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14// as a base case when scalarizing vector arithmetic like <4 x f32>, which
15// eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
16// types.
17// Splitting is the act of changing a computation in an invalid vector type to
18// be a computation in two vectors of half the size. For example, implementing
19// <128 x f32> operations in terms of two <64 x f32> operations.
20//
21//===----------------------------------------------------------------------===//
22
23#include "LegalizeTypes.h"
24#include "llvm/IR/DataLayout.h"
25#include "llvm/Support/ErrorHandling.h"
26#include "llvm/Support/raw_ostream.h"
27using namespace llvm;
28
29#define DEBUG_TYPE"legalize-types" "legalize-types"
30
31//===----------------------------------------------------------------------===//
32// Result Vector Scalarization: <1 x ty> -> ty.
33//===----------------------------------------------------------------------===//
34
35void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node result "
<< ResNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
37 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node result "
<< ResNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
;
38 SDValue R = SDValue();
39
40 switch (N->getOpcode()) {
41 default:
42#ifndef NDEBUG
43 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
44 N->dump(&DAG);
45 dbgs() << "\n";
46#endif
47 report_fatal_error("Do not know how to scalarize the result of this "
48 "operator!\n");
49
50 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
52 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
59 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
63 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
64 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
65 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
67 case ISD::ANY_EXTEND_VECTOR_INREG:
68 case ISD::SIGN_EXTEND_VECTOR_INREG:
69 case ISD::ZERO_EXTEND_VECTOR_INREG:
70 R = ScalarizeVecRes_VecInregOp(N);
71 break;
72 case ISD::ANY_EXTEND:
73 case ISD::BITREVERSE:
74 case ISD::BSWAP:
75 case ISD::CTLZ:
76 case ISD::CTLZ_ZERO_UNDEF:
77 case ISD::CTPOP:
78 case ISD::CTTZ:
79 case ISD::CTTZ_ZERO_UNDEF:
80 case ISD::FABS:
81 case ISD::FCEIL:
82 case ISD::FCOS:
83 case ISD::FEXP:
84 case ISD::FEXP2:
85 case ISD::FFLOOR:
86 case ISD::FLOG:
87 case ISD::FLOG10:
88 case ISD::FLOG2:
89 case ISD::FNEARBYINT:
90 case ISD::FNEG:
91 case ISD::FP_EXTEND:
92 case ISD::FP_TO_SINT:
93 case ISD::FP_TO_UINT:
94 case ISD::FRINT:
95 case ISD::FROUND:
96 case ISD::FSIN:
97 case ISD::FSQRT:
98 case ISD::FTRUNC:
99 case ISD::SIGN_EXTEND:
100 case ISD::SINT_TO_FP:
101 case ISD::TRUNCATE:
102 case ISD::UINT_TO_FP:
103 case ISD::ZERO_EXTEND:
104 case ISD::FCANONICALIZE:
105 R = ScalarizeVecRes_UnaryOp(N);
106 break;
107
108 case ISD::ADD:
109 case ISD::AND:
110 case ISD::FADD:
111 case ISD::FCOPYSIGN:
112 case ISD::FDIV:
113 case ISD::FMUL:
114 case ISD::FMINNUM:
115 case ISD::FMAXNUM:
116 case ISD::FMINNUM_IEEE:
117 case ISD::FMAXNUM_IEEE:
118 case ISD::FMINIMUM:
119 case ISD::FMAXIMUM:
120 case ISD::SMIN:
121 case ISD::SMAX:
122 case ISD::UMIN:
123 case ISD::UMAX:
124
125 case ISD::SADDSAT:
126 case ISD::UADDSAT:
127
128 case ISD::FPOW:
129 case ISD::FREM:
130 case ISD::FSUB:
131 case ISD::MUL:
132 case ISD::OR:
133 case ISD::SDIV:
134 case ISD::SREM:
135 case ISD::SUB:
136 case ISD::UDIV:
137 case ISD::UREM:
138 case ISD::XOR:
139 case ISD::SHL:
140 case ISD::SRA:
141 case ISD::SRL:
142 R = ScalarizeVecRes_BinOp(N);
143 break;
144 case ISD::FMA:
145 R = ScalarizeVecRes_TernaryOp(N);
146 break;
147 case ISD::STRICT_FADD:
148 case ISD::STRICT_FSUB:
149 case ISD::STRICT_FMUL:
150 case ISD::STRICT_FDIV:
151 case ISD::STRICT_FREM:
152 case ISD::STRICT_FSQRT:
153 case ISD::STRICT_FMA:
154 case ISD::STRICT_FPOW:
155 case ISD::STRICT_FPOWI:
156 case ISD::STRICT_FSIN:
157 case ISD::STRICT_FCOS:
158 case ISD::STRICT_FEXP:
159 case ISD::STRICT_FEXP2:
160 case ISD::STRICT_FLOG:
161 case ISD::STRICT_FLOG10:
162 case ISD::STRICT_FLOG2:
163 case ISD::STRICT_FRINT:
164 case ISD::STRICT_FNEARBYINT:
165 R = ScalarizeVecRes_StrictFPOp(N);
166 break;
167 }
168
169 // If R is null, the sub-method took care of registering the result.
170 if (R.getNode())
171 SetScalarizedVector(SDValue(N, ResNo), R);
172}
173
174SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
175 SDValue LHS = GetScalarizedVector(N->getOperand(0));
176 SDValue RHS = GetScalarizedVector(N->getOperand(1));
177 return DAG.getNode(N->getOpcode(), SDLoc(N),
178 LHS.getValueType(), LHS, RHS, N->getFlags());
179}
180
181SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
182 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
183 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
184 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
185 return DAG.getNode(N->getOpcode(), SDLoc(N),
186 Op0.getValueType(), Op0, Op1, Op2);
187}
188
189SDValue DAGTypeLegalizer::ScalarizeVecRes_StrictFPOp(SDNode *N) {
190 EVT VT = N->getValueType(0).getVectorElementType();
191 unsigned NumOpers = N->getNumOperands();
192 SDValue Chain = N->getOperand(0);
193 EVT ValueVTs[] = {VT, MVT::Other};
194 SDLoc dl(N);
195
196 SmallVector<SDValue, 4> Opers;
197
198 // The Chain is the first operand.
199 Opers.push_back(Chain);
200
201 // Now process the remaining operands.
202 for (unsigned i = 1; i < NumOpers; ++i) {
203 SDValue Oper = N->getOperand(i);
204
205 if (Oper.getValueType().isVector())
206 Oper = GetScalarizedVector(Oper);
207
208 Opers.push_back(Oper);
209 }
210
211 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers);
212
213 // Legalize the chain result - switch anything that used the old chain to
214 // use the new one.
215 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
216 return Result;
217}
218
219SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
220 unsigned ResNo) {
221 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
222 return GetScalarizedVector(Op);
223}
224
225SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
226 SDValue Op = N->getOperand(0);
227 if (Op.getValueType().isVector()
228 && Op.getValueType().getVectorNumElements() == 1
229 && !isSimpleLegalType(Op.getValueType()))
230 Op = GetScalarizedVector(Op);
231 EVT NewVT = N->getValueType(0).getVectorElementType();
232 return DAG.getNode(ISD::BITCAST, SDLoc(N),
233 NewVT, Op);
234}
235
236SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
237 EVT EltVT = N->getValueType(0).getVectorElementType();
238 SDValue InOp = N->getOperand(0);
239 // The BUILD_VECTOR operands may be of wider element types and
240 // we may need to truncate them back to the requested return type.
241 if (EltVT.isInteger())
242 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
243 return InOp;
244}
245
246SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
247 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
248 N->getValueType(0).getVectorElementType(),
249 N->getOperand(0), N->getOperand(1));
250}
251
252SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
253 EVT NewVT = N->getValueType(0).getVectorElementType();
254 SDValue Op = GetScalarizedVector(N->getOperand(0));
255 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
256 NewVT, Op, N->getOperand(1));
257}
258
259SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
260 SDValue Op = GetScalarizedVector(N->getOperand(0));
261 return DAG.getNode(ISD::FPOWI, SDLoc(N),
262 Op.getValueType(), Op, N->getOperand(1));
263}
264
265SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
266 // The value to insert may have a wider type than the vector element type,
267 // so be sure to truncate it to the element type if necessary.
268 SDValue Op = N->getOperand(1);
269 EVT EltVT = N->getValueType(0).getVectorElementType();
270 if (Op.getValueType() != EltVT)
271 // FIXME: Can this happen for floating point types?
272 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
273 return Op;
274}
275
276SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
277 assert(N->isUnindexed() && "Indexed vector load?")((N->isUnindexed() && "Indexed vector load?") ? static_cast
<void> (0) : __assert_fail ("N->isUnindexed() && \"Indexed vector load?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 277, __PRETTY_FUNCTION__))
;
278
279 SDValue Result = DAG.getLoad(
280 ISD::UNINDEXED, N->getExtensionType(),
281 N->getValueType(0).getVectorElementType(), SDLoc(N), N->getChain(),
282 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()),
283 N->getPointerInfo(), N->getMemoryVT().getVectorElementType(),
284 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
285 N->getAAInfo());
286
287 // Legalize the chain result - switch anything that used the old chain to
288 // use the new one.
289 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
290 return Result;
291}
292
293SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
294 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
295 EVT DestVT = N->getValueType(0).getVectorElementType();
296 SDValue Op = N->getOperand(0);
297 EVT OpVT = Op.getValueType();
298 SDLoc DL(N);
299 // The result needs scalarizing, but it's not a given that the source does.
300 // This is a workaround for targets where it's impossible to scalarize the
301 // result of a conversion, because the source type is legal.
302 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
303 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
304 // legal and was not scalarized.
305 // See the similar logic in ScalarizeVecRes_SETCC
306 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
307 Op = GetScalarizedVector(Op);
308 } else {
309 EVT VT = OpVT.getVectorElementType();
310 Op = DAG.getNode(
311 ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
312 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
313 }
314 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
315}
316
317SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
318 EVT EltVT = N->getValueType(0).getVectorElementType();
319 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
320 SDValue LHS = GetScalarizedVector(N->getOperand(0));
321 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
322 LHS, DAG.getValueType(ExtVT));
323}
324
325SDValue DAGTypeLegalizer::ScalarizeVecRes_VecInregOp(SDNode *N) {
326 SDLoc DL(N);
327 SDValue Op = N->getOperand(0);
328
329 EVT OpVT = Op.getValueType();
330 EVT OpEltVT = OpVT.getVectorElementType();
331 EVT EltVT = N->getValueType(0).getVectorElementType();
332
333 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
334 Op = GetScalarizedVector(Op);
335 } else {
336 Op = DAG.getNode(
337 ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op,
338 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
339 }
340
341 switch (N->getOpcode()) {
342 case ISD::ANY_EXTEND_VECTOR_INREG:
343 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op);
344 case ISD::SIGN_EXTEND_VECTOR_INREG:
345 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op);
346 case ISD::ZERO_EXTEND_VECTOR_INREG:
347 return DAG.getNode(ISD::ZERO_EXTEND, DL, EltVT, Op);
348 }
349
350 llvm_unreachable("Illegal extend_vector_inreg opcode")::llvm::llvm_unreachable_internal("Illegal extend_vector_inreg opcode"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 350)
;
351}
352
353SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
354 // If the operand is wider than the vector element type then it is implicitly
355 // truncated. Make that explicit here.
356 EVT EltVT = N->getValueType(0).getVectorElementType();
357 SDValue InOp = N->getOperand(0);
358 if (InOp.getValueType() != EltVT)
359 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
360 return InOp;
361}
362
363SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
364 SDValue Cond = N->getOperand(0);
365 EVT OpVT = Cond.getValueType();
366 SDLoc DL(N);
367 // The vselect result and true/value operands needs scalarizing, but it's
368 // not a given that the Cond does. For instance, in AVX512 v1i1 is legal.
369 // See the similar logic in ScalarizeVecRes_SETCC
370 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
371 Cond = GetScalarizedVector(Cond);
372 } else {
373 EVT VT = OpVT.getVectorElementType();
374 Cond = DAG.getNode(
375 ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond,
376 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
377 }
378
379 SDValue LHS = GetScalarizedVector(N->getOperand(1));
380 TargetLowering::BooleanContent ScalarBool =
381 TLI.getBooleanContents(false, false);
382 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
383
384 // If integer and float booleans have different contents then we can't
385 // reliably optimize in all cases. There is a full explanation for this in
386 // DAGCombiner::visitSELECT() where the same issue affects folding
387 // (select C, 0, 1) to (xor C, 1).
388 if (TLI.getBooleanContents(false, false) !=
389 TLI.getBooleanContents(false, true)) {
390 // At least try the common case where the boolean is generated by a
391 // comparison.
392 if (Cond->getOpcode() == ISD::SETCC) {
393 EVT OpVT = Cond->getOperand(0).getValueType();
394 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
395 VecBool = TLI.getBooleanContents(OpVT);
396 } else
397 ScalarBool = TargetLowering::UndefinedBooleanContent;
398 }
399
400 EVT CondVT = Cond.getValueType();
401 if (ScalarBool != VecBool) {
402 switch (ScalarBool) {
403 case TargetLowering::UndefinedBooleanContent:
404 break;
405 case TargetLowering::ZeroOrOneBooleanContent:
406 assert(VecBool == TargetLowering::UndefinedBooleanContent ||((VecBool == TargetLowering::UndefinedBooleanContent || VecBool
== TargetLowering::ZeroOrNegativeOneBooleanContent) ? static_cast
<void> (0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 407, __PRETTY_FUNCTION__))
407 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent)((VecBool == TargetLowering::UndefinedBooleanContent || VecBool
== TargetLowering::ZeroOrNegativeOneBooleanContent) ? static_cast
<void> (0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 407, __PRETTY_FUNCTION__))
;
408 // Vector read from all ones, scalar expects a single 1 so mask.
409 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
410 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
411 break;
412 case TargetLowering::ZeroOrNegativeOneBooleanContent:
413 assert(VecBool == TargetLowering::UndefinedBooleanContent ||((VecBool == TargetLowering::UndefinedBooleanContent || VecBool
== TargetLowering::ZeroOrOneBooleanContent) ? static_cast<
void> (0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrOneBooleanContent"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 414, __PRETTY_FUNCTION__))
414 VecBool == TargetLowering::ZeroOrOneBooleanContent)((VecBool == TargetLowering::UndefinedBooleanContent || VecBool
== TargetLowering::ZeroOrOneBooleanContent) ? static_cast<
void> (0) : __assert_fail ("VecBool == TargetLowering::UndefinedBooleanContent || VecBool == TargetLowering::ZeroOrOneBooleanContent"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 414, __PRETTY_FUNCTION__))
;
415 // Vector reads from a one, scalar from all ones so sign extend.
416 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
417 Cond, DAG.getValueType(MVT::i1));
418 break;
419 }
420 }
421
422 // Truncate the condition if needed
423 auto BoolVT = getSetCCResultType(CondVT);
424 if (BoolVT.bitsLT(CondVT))
425 Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
426
427 return DAG.getSelect(SDLoc(N),
428 LHS.getValueType(), Cond, LHS,
429 GetScalarizedVector(N->getOperand(2)));
430}
431
432SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
433 SDValue LHS = GetScalarizedVector(N->getOperand(1));
434 return DAG.getSelect(SDLoc(N),
435 LHS.getValueType(), N->getOperand(0), LHS,
436 GetScalarizedVector(N->getOperand(2)));
437}
438
439SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
440 SDValue LHS = GetScalarizedVector(N->getOperand(2));
441 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
442 N->getOperand(0), N->getOperand(1),
443 LHS, GetScalarizedVector(N->getOperand(3)),
444 N->getOperand(4));
445}
446
447SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
448 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
449}
450
451SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
452 // Figure out if the scalar is the LHS or RHS and return it.
453 SDValue Arg = N->getOperand(2).getOperand(0);
454 if (Arg.isUndef())
455 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
456 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
457 return GetScalarizedVector(N->getOperand(Op));
458}
459
460SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
461 assert(N->getValueType(0).isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 463, __PRETTY_FUNCTION__))
462 N->getOperand(0).getValueType().isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 463, __PRETTY_FUNCTION__))
463 "Operand types must be vectors")((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 463, __PRETTY_FUNCTION__))
;
464 SDValue LHS = N->getOperand(0);
465 SDValue RHS = N->getOperand(1);
466 EVT OpVT = LHS.getValueType();
467 EVT NVT = N->getValueType(0).getVectorElementType();
468 SDLoc DL(N);
469
470 // The result needs scalarizing, but it's not a given that the source does.
471 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
472 LHS = GetScalarizedVector(LHS);
473 RHS = GetScalarizedVector(RHS);
474 } else {
475 EVT VT = OpVT.getVectorElementType();
476 LHS = DAG.getNode(
477 ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
478 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
479 RHS = DAG.getNode(
480 ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
481 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
482 }
483
484 // Turn it into a scalar SETCC.
485 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
486 N->getOperand(2));
487 // Vectors may have a different boolean contents to scalars. Promote the
488 // value appropriately.
489 ISD::NodeType ExtendCode =
490 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
491 return DAG.getNode(ExtendCode, DL, NVT, Res);
492}
493
494
495//===----------------------------------------------------------------------===//
496// Operand Vector Scalarization <1 x ty> -> ty.
497//===----------------------------------------------------------------------===//
498
499bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
500 LLVM_DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node operand "
<< OpNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
501 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Scalarize node operand "
<< OpNo << ": "; N->dump(&DAG); dbgs() <<
"\n"; } } while (false)
;
502 SDValue Res = SDValue();
503
504 if (!Res.getNode()) {
505 switch (N->getOpcode()) {
506 default:
507#ifndef NDEBUG
508 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
509 N->dump(&DAG);
510 dbgs() << "\n";
511#endif
512 report_fatal_error("Do not know how to scalarize this operator's "
513 "operand!\n");
514 case ISD::BITCAST:
515 Res = ScalarizeVecOp_BITCAST(N);
516 break;
517 case ISD::ANY_EXTEND:
518 case ISD::ZERO_EXTEND:
519 case ISD::SIGN_EXTEND:
520 case ISD::TRUNCATE:
521 case ISD::FP_TO_SINT:
522 case ISD::FP_TO_UINT:
523 case ISD::SINT_TO_FP:
524 case ISD::UINT_TO_FP:
525 Res = ScalarizeVecOp_UnaryOp(N);
526 break;
527 case ISD::CONCAT_VECTORS:
528 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
529 break;
530 case ISD::EXTRACT_VECTOR_ELT:
531 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
532 break;
533 case ISD::VSELECT:
534 Res = ScalarizeVecOp_VSELECT(N);
535 break;
536 case ISD::SETCC:
537 Res = ScalarizeVecOp_VSETCC(N);
538 break;
539 case ISD::STORE:
540 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
541 break;
542 case ISD::FP_ROUND:
543 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
544 break;
545 }
546 }
547
548 // If the result is null, the sub-method took care of registering results etc.
549 if (!Res.getNode()) return false;
550
551 // If the result is N, the sub-method updated N in place. Tell the legalizer
552 // core about this.
553 if (Res.getNode() == N)
554 return true;
555
556 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 557, __PRETTY_FUNCTION__))
557 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 557, __PRETTY_FUNCTION__))
;
558
559 ReplaceValueWith(SDValue(N, 0), Res);
560 return false;
561}
562
563/// If the value to convert is a vector that needs to be scalarized, it must be
564/// <1 x ty>. Convert the element instead.
565SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
566 SDValue Elt = GetScalarizedVector(N->getOperand(0));
567 return DAG.getNode(ISD::BITCAST, SDLoc(N),
568 N->getValueType(0), Elt);
569}
570
571/// If the input is a vector that needs to be scalarized, it must be <1 x ty>.
572/// Do the operation on the element instead.
573SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
574 assert(N->getValueType(0).getVectorNumElements() == 1 &&((N->getValueType(0).getVectorNumElements() == 1 &&
"Unexpected vector type!") ? static_cast<void> (0) : __assert_fail
("N->getValueType(0).getVectorNumElements() == 1 && \"Unexpected vector type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 575, __PRETTY_FUNCTION__))
575 "Unexpected vector type!")((N->getValueType(0).getVectorNumElements() == 1 &&
"Unexpected vector type!") ? static_cast<void> (0) : __assert_fail
("N->getValueType(0).getVectorNumElements() == 1 && \"Unexpected vector type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 575, __PRETTY_FUNCTION__))
;
576 SDValue Elt = GetScalarizedVector(N->getOperand(0));
577 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
578 N->getValueType(0).getScalarType(), Elt);
579 // Revectorize the result so the types line up with what the uses of this
580 // expression expect.
581 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Op);
582}
583
584/// The vectors to concatenate have length one - use a BUILD_VECTOR instead.
585SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
586 SmallVector<SDValue, 8> Ops(N->getNumOperands());
587 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
588 Ops[i] = GetScalarizedVector(N->getOperand(i));
589 return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
590}
591
592/// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
593/// so just return the element, ignoring the index.
594SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
595 EVT VT = N->getValueType(0);
596 SDValue Res = GetScalarizedVector(N->getOperand(0));
597 if (Res.getValueType() != VT)
598 Res = VT.isFloatingPoint()
599 ? DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res)
600 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
601 return Res;
602}
603
604/// If the input condition is a vector that needs to be scalarized, it must be
605/// <1 x i1>, so just convert to a normal ISD::SELECT
606/// (still with vector output type since that was acceptable if we got here).
607SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
608 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
609 EVT VT = N->getValueType(0);
610
611 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
612 N->getOperand(2));
613}
614
615/// If the operand is a vector that needs to be scalarized then the
616/// result must be v1i1, so just convert to a scalar SETCC and wrap
617/// with a scalar_to_vector since the res type is legal if we got here
618SDValue DAGTypeLegalizer::ScalarizeVecOp_VSETCC(SDNode *N) {
619 assert(N->getValueType(0).isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 621, __PRETTY_FUNCTION__))
620 N->getOperand(0).getValueType().isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 621, __PRETTY_FUNCTION__))
621 "Operand types must be vectors")((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 621, __PRETTY_FUNCTION__))
;
622 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type")((N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0) == MVT::v1i1 && \"Expected v1i1 type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 622, __PRETTY_FUNCTION__))
;
623
624 EVT VT = N->getValueType(0);
625 SDValue LHS = GetScalarizedVector(N->getOperand(0));
626 SDValue RHS = GetScalarizedVector(N->getOperand(1));
627
628 EVT OpVT = N->getOperand(0).getValueType();
629 EVT NVT = VT.getVectorElementType();
630 SDLoc DL(N);
631 // Turn it into a scalar SETCC.
632 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
633 N->getOperand(2));
634
635 // Vectors may have a different boolean contents to scalars. Promote the
636 // value appropriately.
637 ISD::NodeType ExtendCode =
638 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
639
640 Res = DAG.getNode(ExtendCode, DL, NVT, Res);
641
642 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Res);
643}
644
645/// If the value to store is a vector that needs to be scalarized, it must be
646/// <1 x ty>. Just store the element.
647SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
648 assert(N->isUnindexed() && "Indexed store of one-element vector?")((N->isUnindexed() && "Indexed store of one-element vector?"
) ? static_cast<void> (0) : __assert_fail ("N->isUnindexed() && \"Indexed store of one-element vector?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 648, __PRETTY_FUNCTION__))
;
649 assert(OpNo == 1 && "Do not know how to scalarize this operand!")((OpNo == 1 && "Do not know how to scalarize this operand!"
) ? static_cast<void> (0) : __assert_fail ("OpNo == 1 && \"Do not know how to scalarize this operand!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 649, __PRETTY_FUNCTION__))
;
650 SDLoc dl(N);
651
652 if (N->isTruncatingStore())
653 return DAG.getTruncStore(
654 N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
655 N->getBasePtr(), N->getPointerInfo(),
656 N->getMemoryVT().getVectorElementType(), N->getAlignment(),
657 N->getMemOperand()->getFlags(), N->getAAInfo());
658
659 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
660 N->getBasePtr(), N->getPointerInfo(),
661 N->getOriginalAlignment(), N->getMemOperand()->getFlags(),
662 N->getAAInfo());
663}
664
665/// If the value to round is a vector that needs to be scalarized, it must be
666/// <1 x ty>. Convert the element instead.
667SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
668 SDValue Elt = GetScalarizedVector(N->getOperand(0));
669 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
670 N->getValueType(0).getVectorElementType(), Elt,
671 N->getOperand(1));
672 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
673}
674
675//===----------------------------------------------------------------------===//
676// Result Vector Splitting
677//===----------------------------------------------------------------------===//
678
679/// This method is called when the specified result of the specified node is
680/// found to need vector splitting. At this point, the node may also have
681/// invalid operands or may have other results that need legalization, we just
682/// know that (at least) one result needs vector splitting.
683void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
684 LLVM_DEBUG(dbgs() << "Split node result: "; N->dump(&DAG); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split node result: "; N
->dump(&DAG); dbgs() << "\n"; } } while (false)
;
685 SDValue Lo, Hi;
686
687 // See if the target wants to custom expand this node.
688 if (CustomLowerNode(N, N->getValueType(ResNo), true))
689 return;
690
691 switch (N->getOpcode()) {
692 default:
693#ifndef NDEBUG
694 dbgs() << "SplitVectorResult #" << ResNo << ": ";
695 N->dump(&DAG);
696 dbgs() << "\n";
697#endif
698 report_fatal_error("Do not know how to split the result of this "
699 "operator!\n");
700
701 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
702 case ISD::VSELECT:
703 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
704 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
705 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
706 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
707 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
708 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
709 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
710 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
711 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
712 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
713 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
714 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
715 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
716 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
717 case ISD::LOAD:
718 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
719 break;
720 case ISD::MLOAD:
721 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
722 break;
723 case ISD::MGATHER:
724 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
725 break;
726 case ISD::SETCC:
727 SplitVecRes_SETCC(N, Lo, Hi);
728 break;
729 case ISD::VECTOR_SHUFFLE:
730 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
731 break;
732
733 case ISD::ANY_EXTEND_VECTOR_INREG:
734 case ISD::SIGN_EXTEND_VECTOR_INREG:
735 case ISD::ZERO_EXTEND_VECTOR_INREG:
736 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
737 break;
738
739 case ISD::BITREVERSE:
740 case ISD::BSWAP:
741 case ISD::CTLZ:
742 case ISD::CTTZ:
743 case ISD::CTLZ_ZERO_UNDEF:
744 case ISD::CTTZ_ZERO_UNDEF:
745 case ISD::CTPOP:
746 case ISD::FABS:
747 case ISD::FCEIL:
748 case ISD::FCOS:
749 case ISD::FEXP:
750 case ISD::FEXP2:
751 case ISD::FFLOOR:
752 case ISD::FLOG:
753 case ISD::FLOG10:
754 case ISD::FLOG2:
755 case ISD::FNEARBYINT:
756 case ISD::FNEG:
757 case ISD::FP_EXTEND:
758 case ISD::FP_ROUND:
759 case ISD::FP_TO_SINT:
760 case ISD::FP_TO_UINT:
761 case ISD::FRINT:
762 case ISD::FROUND:
763 case ISD::FSIN:
764 case ISD::FSQRT:
765 case ISD::FTRUNC:
766 case ISD::SINT_TO_FP:
767 case ISD::TRUNCATE:
768 case ISD::UINT_TO_FP:
769 case ISD::FCANONICALIZE:
770 SplitVecRes_UnaryOp(N, Lo, Hi);
771 break;
772
773 case ISD::ANY_EXTEND:
774 case ISD::SIGN_EXTEND:
775 case ISD::ZERO_EXTEND:
776 SplitVecRes_ExtendOp(N, Lo, Hi);
777 break;
778
779 case ISD::ADD:
780 case ISD::SUB:
781 case ISD::MUL:
782 case ISD::MULHS:
783 case ISD::MULHU:
784 case ISD::FADD:
785 case ISD::FSUB:
786 case ISD::FMUL:
787 case ISD::FMINNUM:
788 case ISD::FMAXNUM:
789 case ISD::FMINIMUM:
790 case ISD::FMAXIMUM:
791 case ISD::SDIV:
792 case ISD::UDIV:
793 case ISD::FDIV:
794 case ISD::FPOW:
795 case ISD::AND:
796 case ISD::OR:
797 case ISD::XOR:
798 case ISD::SHL:
799 case ISD::SRA:
800 case ISD::SRL:
801 case ISD::UREM:
802 case ISD::SREM:
803 case ISD::FREM:
804 case ISD::SMIN:
805 case ISD::SMAX:
806 case ISD::UMIN:
807 case ISD::UMAX:
808 case ISD::SADDSAT:
809 case ISD::UADDSAT:
810 SplitVecRes_BinOp(N, Lo, Hi);
811 break;
812 case ISD::FMA:
813 SplitVecRes_TernaryOp(N, Lo, Hi);
814 break;
815 case ISD::STRICT_FADD:
816 case ISD::STRICT_FSUB:
817 case ISD::STRICT_FMUL:
818 case ISD::STRICT_FDIV:
819 case ISD::STRICT_FREM:
820 case ISD::STRICT_FSQRT:
821 case ISD::STRICT_FMA:
822 case ISD::STRICT_FPOW:
823 case ISD::STRICT_FPOWI:
824 case ISD::STRICT_FSIN:
825 case ISD::STRICT_FCOS:
826 case ISD::STRICT_FEXP:
827 case ISD::STRICT_FEXP2:
828 case ISD::STRICT_FLOG:
829 case ISD::STRICT_FLOG10:
830 case ISD::STRICT_FLOG2:
831 case ISD::STRICT_FRINT:
832 case ISD::STRICT_FNEARBYINT:
833 SplitVecRes_StrictFPOp(N, Lo, Hi);
834 break;
835 }
836
837 // If Lo/Hi is null, the sub-method took care of registering results etc.
838 if (Lo.getNode())
839 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
840}
841
842void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
843 SDValue &Hi) {
844 SDValue LHSLo, LHSHi;
845 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
846 SDValue RHSLo, RHSHi;
847 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
848 SDLoc dl(N);
849
850 const SDNodeFlags Flags = N->getFlags();
851 unsigned Opcode = N->getOpcode();
852 Lo = DAG.getNode(Opcode, dl, LHSLo.getValueType(), LHSLo, RHSLo, Flags);
853 Hi = DAG.getNode(Opcode, dl, LHSHi.getValueType(), LHSHi, RHSHi, Flags);
854}
855
856void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
857 SDValue &Hi) {
858 SDValue Op0Lo, Op0Hi;
859 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
860 SDValue Op1Lo, Op1Hi;
861 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
862 SDValue Op2Lo, Op2Hi;
863 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
864 SDLoc dl(N);
865
866 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
867 Op0Lo, Op1Lo, Op2Lo);
868 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
869 Op0Hi, Op1Hi, Op2Hi);
870}
871
872void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
873 SDValue &Hi) {
874 // We know the result is a vector. The input may be either a vector or a
875 // scalar value.
876 EVT LoVT, HiVT;
877 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
878 SDLoc dl(N);
879
880 SDValue InOp = N->getOperand(0);
881 EVT InVT = InOp.getValueType();
882
883 // Handle some special cases efficiently.
884 switch (getTypeAction(InVT)) {
885 case TargetLowering::TypeLegal:
886 case TargetLowering::TypePromoteInteger:
887 case TargetLowering::TypePromoteFloat:
888 case TargetLowering::TypeSoftenFloat:
889 case TargetLowering::TypeScalarizeVector:
890 case TargetLowering::TypeWidenVector:
891 break;
892 case TargetLowering::TypeExpandInteger:
893 case TargetLowering::TypeExpandFloat:
894 // A scalar to vector conversion, where the scalar needs expansion.
895 // If the vector is being split in two then we can just convert the
896 // expanded pieces.
897 if (LoVT == HiVT) {
898 GetExpandedOp(InOp, Lo, Hi);
899 if (DAG.getDataLayout().isBigEndian())
900 std::swap(Lo, Hi);
901 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
902 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
903 return;
904 }
905 break;
906 case TargetLowering::TypeSplitVector:
907 // If the input is a vector that needs to be split, convert each split
908 // piece of the input now.
909 GetSplitVector(InOp, Lo, Hi);
910 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
911 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
912 return;
913 }
914
915 // In the general case, convert the input to an integer and split it by hand.
916 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
917 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
918 if (DAG.getDataLayout().isBigEndian())
919 std::swap(LoIntVT, HiIntVT);
920
921 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
922
923 if (DAG.getDataLayout().isBigEndian())
924 std::swap(Lo, Hi);
925 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
926 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
927}
928
929void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
930 SDValue &Hi) {
931 EVT LoVT, HiVT;
932 SDLoc dl(N);
933 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
934 unsigned LoNumElts = LoVT.getVectorNumElements();
935 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
936 Lo = DAG.getBuildVector(LoVT, dl, LoOps);
937
938 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
939 Hi = DAG.getBuildVector(HiVT, dl, HiOps);
940}
941
942void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
943 SDValue &Hi) {
944 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS")((!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"
) ? static_cast<void> (0) : __assert_fail ("!(N->getNumOperands() & 1) && \"Unsupported CONCAT_VECTORS\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 944, __PRETTY_FUNCTION__))
;
945 SDLoc dl(N);
946 unsigned NumSubvectors = N->getNumOperands() / 2;
947 if (NumSubvectors == 1) {
948 Lo = N->getOperand(0);
949 Hi = N->getOperand(1);
950 return;
951 }
952
953 EVT LoVT, HiVT;
954 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
955
956 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
957 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
958
959 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
960 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
961}
962
963void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
964 SDValue &Hi) {
965 SDValue Vec = N->getOperand(0);
966 SDValue Idx = N->getOperand(1);
967 SDLoc dl(N);
968
969 EVT LoVT, HiVT;
970 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
971
972 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
973 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
974 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
975 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
976 TLI.getVectorIdxTy(DAG.getDataLayout())));
977}
978
979void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
980 SDValue &Hi) {
981 SDValue Vec = N->getOperand(0);
982 SDValue SubVec = N->getOperand(1);
983 SDValue Idx = N->getOperand(2);
984 SDLoc dl(N);
985 GetSplitVector(Vec, Lo, Hi);
986
987 EVT VecVT = Vec.getValueType();
988 unsigned VecElems = VecVT.getVectorNumElements();
989 unsigned SubElems = SubVec.getValueType().getVectorNumElements();
990
991 // If we know the index is 0, and we know the subvector doesn't cross the
992 // boundary between the halves, we can avoid spilling the vector, and insert
993 // into the lower half of the split vector directly.
994 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
995 // the index is constant and there is no boundary crossing. But those cases
996 // don't seem to get hit in practice.
997 if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
998 unsigned IdxVal = ConstIdx->getZExtValue();
999 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
1000 EVT LoVT, HiVT;
1001 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1002 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx);
1003 return;
1004 }
1005 }
1006
1007 // Spill the vector to the stack.
1008 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1009 SDValue Store =
1010 DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, MachinePointerInfo());
1011
1012 // Store the new subvector into the specified index.
1013 SDValue SubVecPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1014 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1015 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1016 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo());
1017
1018 // Load the Lo part from the stack slot.
1019 Lo =
1020 DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo());
1021
1022 // Increment the pointer to the other part.
1023 unsigned IncrementSize = Lo.getValueSizeInBits() / 8;
1024 StackPtr =
1025 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1026 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
1027
1028 // Load the Hi part from the stack slot.
1029 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
1030 MinAlign(Alignment, IncrementSize));
1031}
1032
1033void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
1034 SDValue &Hi) {
1035 SDLoc dl(N);
1036 GetSplitVector(N->getOperand(0), Lo, Hi);
1037 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
1038 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
1039}
1040
1041void DAGTypeLegalizer::SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo,
1042 SDValue &Hi) {
1043 SDValue LHSLo, LHSHi;
1044 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1045 SDLoc DL(N);
1046
1047 SDValue RHSLo, RHSHi;
1048 SDValue RHS = N->getOperand(1);
1049 EVT RHSVT = RHS.getValueType();
1050 if (getTypeAction(RHSVT) == TargetLowering::TypeSplitVector)
1051 GetSplitVector(RHS, RHSLo, RHSHi);
1052 else
1053 std::tie(RHSLo, RHSHi) = DAG.SplitVector(RHS, SDLoc(RHS));
1054
1055
1056 Lo = DAG.getNode(ISD::FCOPYSIGN, DL, LHSLo.getValueType(), LHSLo, RHSLo);
1057 Hi = DAG.getNode(ISD::FCOPYSIGN, DL, LHSHi.getValueType(), LHSHi, RHSHi);
1058}
1059
1060void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
1061 SDValue &Hi) {
1062 SDValue LHSLo, LHSHi;
1063 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
1064 SDLoc dl(N);
1065
1066 EVT LoVT, HiVT;
1067 std::tie(LoVT, HiVT) =
1068 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
1069
1070 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
1071 DAG.getValueType(LoVT));
1072 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
1073 DAG.getValueType(HiVT));
1074}
1075
1076void DAGTypeLegalizer::SplitVecRes_ExtVecInRegOp(SDNode *N, SDValue &Lo,
1077 SDValue &Hi) {
1078 unsigned Opcode = N->getOpcode();
1079 SDValue N0 = N->getOperand(0);
1080
1081 SDLoc dl(N);
1082 SDValue InLo, InHi;
1083
1084 if (getTypeAction(N0.getValueType()) == TargetLowering::TypeSplitVector)
1085 GetSplitVector(N0, InLo, InHi);
1086 else
1087 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0);
1088
1089 EVT InLoVT = InLo.getValueType();
1090 unsigned InNumElements = InLoVT.getVectorNumElements();
1091
1092 EVT OutLoVT, OutHiVT;
1093 std::tie(OutLoVT, OutHiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1094 unsigned OutNumElements = OutLoVT.getVectorNumElements();
1095 assert((2 * OutNumElements) <= InNumElements &&(((2 * OutNumElements) <= InNumElements && "Illegal extend vector in reg split"
) ? static_cast<void> (0) : __assert_fail ("(2 * OutNumElements) <= InNumElements && \"Illegal extend vector in reg split\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1096, __PRETTY_FUNCTION__))
1096 "Illegal extend vector in reg split")(((2 * OutNumElements) <= InNumElements && "Illegal extend vector in reg split"
) ? static_cast<void> (0) : __assert_fail ("(2 * OutNumElements) <= InNumElements && \"Illegal extend vector in reg split\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1096, __PRETTY_FUNCTION__))
;
1097
1098 // *_EXTEND_VECTOR_INREG instructions extend the lowest elements of the
1099 // input vector (i.e. we only use InLo):
1100 // OutLo will extend the first OutNumElements from InLo.
1101 // OutHi will extend the next OutNumElements from InLo.
1102
1103 // Shuffle the elements from InLo for OutHi into the bottom elements to
1104 // create a 'fake' InHi.
1105 SmallVector<int, 8> SplitHi(InNumElements, -1);
1106 for (unsigned i = 0; i != OutNumElements; ++i)
1107 SplitHi[i] = i + OutNumElements;
1108 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi);
1109
1110 Lo = DAG.getNode(Opcode, dl, OutLoVT, InLo);
1111 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi);
1112}
1113
1114void DAGTypeLegalizer::SplitVecRes_StrictFPOp(SDNode *N, SDValue &Lo,
1115 SDValue &Hi) {
1116 unsigned NumOps = N->getNumOperands();
1117 SDValue Chain = N->getOperand(0);
1118 EVT LoVT, HiVT;
1119 SDLoc dl(N);
1120 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1121
1122 SmallVector<SDValue, 4> OpsLo;
1123 SmallVector<SDValue, 4> OpsHi;
1124
1125 // The Chain is the first operand.
1126 OpsLo.push_back(Chain);
1127 OpsHi.push_back(Chain);
1128
1129 // Now process the remaining operands.
1130 for (unsigned i = 1; i < NumOps; ++i) {
1131 SDValue Op = N->getOperand(i);
1132 SDValue OpLo = Op;
1133 SDValue OpHi = Op;
1134
1135 EVT InVT = Op.getValueType();
1136 if (InVT.isVector()) {
1137 // If the input also splits, handle it directly for a
1138 // compile time speedup. Otherwise split it by hand.
1139 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1140 GetSplitVector(Op, OpLo, OpHi);
1141 else
1142 std::tie(OpLo, OpHi) = DAG.SplitVectorOperand(N, i);
1143 }
1144
1145 OpsLo.push_back(OpLo);
1146 OpsHi.push_back(OpHi);
1147 }
1148
1149 EVT LoValueVTs[] = {LoVT, MVT::Other};
1150 EVT HiValueVTs[] = {HiVT, MVT::Other};
1151 Lo = DAG.getNode(N->getOpcode(), dl, LoValueVTs, OpsLo);
1152 Hi = DAG.getNode(N->getOpcode(), dl, HiValueVTs, OpsHi);
1153
1154 // Build a factor node to remember that this Op is independent of the
1155 // other one.
1156 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1157 Lo.getValue(1), Hi.getValue(1));
1158
1159 // Legalize the chain result - switch anything that used the old chain to
1160 // use the new one.
1161 ReplaceValueWith(SDValue(N, 1), Chain);
1162}
1163
1164void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
1165 SDValue &Hi) {
1166 SDValue Vec = N->getOperand(0);
1167 SDValue Elt = N->getOperand(1);
1168 SDValue Idx = N->getOperand(2);
1169 SDLoc dl(N);
1170 GetSplitVector(Vec, Lo, Hi);
1171
1172 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
1173 unsigned IdxVal = CIdx->getZExtValue();
1174 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
1175 if (IdxVal < LoNumElts)
1176 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
1177 Lo.getValueType(), Lo, Elt, Idx);
1178 else
1179 Hi =
1180 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
1181 DAG.getConstant(IdxVal - LoNumElts, dl,
1182 TLI.getVectorIdxTy(DAG.getDataLayout())));
1183 return;
1184 }
1185
1186 // See if the target wants to custom expand this node.
1187 if (CustomLowerNode(N, N->getValueType(0), true))
1188 return;
1189
1190 // Make the vector elements byte-addressable if they aren't already.
1191 EVT VecVT = Vec.getValueType();
1192 EVT EltVT = VecVT.getVectorElementType();
1193 if (VecVT.getScalarSizeInBits() < 8) {
1194 EltVT = MVT::i8;
1195 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1196 VecVT.getVectorNumElements());
1197 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1198 // Extend the element type to match if needed.
1199 if (EltVT.bitsGT(Elt.getValueType()))
1200 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt);
1201 }
1202
1203 // Spill the vector to the stack.
1204 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1205 auto &MF = DAG.getMachineFunction();
1206 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1207 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1208 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1209
1210 // Store the new element. This may be larger than the vector element type,
1211 // so use a truncating store.
1212 SDValue EltPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1213 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
1214 unsigned Alignment = DAG.getDataLayout().getPrefTypeAlignment(VecType);
1215 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr,
1216 MachinePointerInfo::getUnknownStack(MF), EltVT);
1217
1218 EVT LoVT, HiVT;
1219 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VecVT);
1220
1221 // Load the Lo part from the stack slot.
1222 Lo = DAG.getLoad(LoVT, dl, Store, StackPtr, PtrInfo);
1223
1224 // Increment the pointer to the other part.
1225 unsigned IncrementSize = LoVT.getSizeInBits() / 8;
1226 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
1227 DAG.getConstant(IncrementSize, dl,
1228 StackPtr.getValueType()));
1229
1230 // Load the Hi part from the stack slot.
1231 Hi = DAG.getLoad(HiVT, dl, Store, StackPtr,
1232 PtrInfo.getWithOffset(IncrementSize),
1233 MinAlign(Alignment, IncrementSize));
1234
1235 // If we adjusted the original type, we need to truncate the results.
1236 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1237 if (LoVT != Lo.getValueType())
1238 Lo = DAG.getNode(ISD::TRUNCATE, dl, LoVT, Lo);
1239 if (HiVT != Hi.getValueType())
1240 Hi = DAG.getNode(ISD::TRUNCATE, dl, HiVT, Hi);
1241}
1242
1243void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
1244 SDValue &Hi) {
1245 EVT LoVT, HiVT;
1246 SDLoc dl(N);
1247 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1248 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
1249 Hi = DAG.getUNDEF(HiVT);
1250}
1251
1252void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
1253 SDValue &Hi) {
1254 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!")((ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"
) ? static_cast<void> (0) : __assert_fail ("ISD::isUNINDEXEDLoad(LD) && \"Indexed load during type legalization!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1254, __PRETTY_FUNCTION__))
;
1255 EVT LoVT, HiVT;
1256 SDLoc dl(LD);
1257 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
1258
1259 ISD::LoadExtType ExtType = LD->getExtensionType();
1260 SDValue Ch = LD->getChain();
1261 SDValue Ptr = LD->getBasePtr();
1262 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
1263 EVT MemoryVT = LD->getMemoryVT();
1264 unsigned Alignment = LD->getOriginalAlignment();
1265 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
1266 AAMDNodes AAInfo = LD->getAAInfo();
1267
1268 EVT LoMemVT, HiMemVT;
1269 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1270
1271 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
1272 LD->getPointerInfo(), LoMemVT, Alignment, MMOFlags, AAInfo);
1273
1274 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1275 Ptr = DAG.getObjectPtrOffset(dl, Ptr, IncrementSize);
1276 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
1277 LD->getPointerInfo().getWithOffset(IncrementSize), HiMemVT,
1278 Alignment, MMOFlags, AAInfo);
1279
1280 // Build a factor node to remember that this load is independent of the
1281 // other one.
1282 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1283 Hi.getValue(1));
1284
1285 // Legalize the chain result - switch anything that used the old chain to
1286 // use the new one.
1287 ReplaceValueWith(SDValue(LD, 1), Ch);
1288}
1289
1290void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
1291 SDValue &Lo, SDValue &Hi) {
1292 EVT LoVT, HiVT;
1293 SDLoc dl(MLD);
1294 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1295
1296 SDValue Ch = MLD->getChain();
1297 SDValue Ptr = MLD->getBasePtr();
1298 SDValue Mask = MLD->getMask();
1299 SDValue PassThru = MLD->getPassThru();
1300 unsigned Alignment = MLD->getOriginalAlignment();
1301 ISD::LoadExtType ExtType = MLD->getExtensionType();
1302
1303 // if Alignment is equal to the vector size,
1304 // take the half of it for the second part
1305 unsigned SecondHalfAlignment =
1306 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1307 Alignment/2 : Alignment;
1308
1309 // Split Mask operand
1310 SDValue MaskLo, MaskHi;
1311 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1312 GetSplitVector(Mask, MaskLo, MaskHi);
1313 else
1314 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1315
1316 EVT MemoryVT = MLD->getMemoryVT();
1317 EVT LoMemVT, HiMemVT;
1318 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1319
1320 SDValue PassThruLo, PassThruHi;
1321 if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1322 GetSplitVector(PassThru, PassThruLo, PassThruHi);
1323 else
1324 std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1325
1326 MachineMemOperand *MMO = DAG.getMachineFunction().
1327 getMachineMemOperand(MLD->getPointerInfo(),
1328 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1329 Alignment, MLD->getAAInfo(), MLD->getRanges());
1330
1331 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, PassThruLo, LoMemVT, MMO,
1332 ExtType, MLD->isExpandingLoad());
1333
1334 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, dl, LoMemVT, DAG,
1335 MLD->isExpandingLoad());
1336 unsigned HiOffset = LoMemVT.getStoreSize();
1337
1338 MMO = DAG.getMachineFunction().getMachineMemOperand(
1339 MLD->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOLoad,
1340 HiMemVT.getStoreSize(), SecondHalfAlignment, MLD->getAAInfo(),
1341 MLD->getRanges());
1342
1343 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, PassThruHi, HiMemVT, MMO,
1344 ExtType, MLD->isExpandingLoad());
1345
1346 // Build a factor node to remember that this load is independent of the
1347 // other one.
1348 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1349 Hi.getValue(1));
1350
1351 // Legalize the chain result - switch anything that used the old chain to
1352 // use the new one.
1353 ReplaceValueWith(SDValue(MLD, 1), Ch);
1354
1355}
1356
1357void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1358 SDValue &Lo, SDValue &Hi) {
1359 EVT LoVT, HiVT;
1360 SDLoc dl(MGT);
1361 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1362
1363 SDValue Ch = MGT->getChain();
1364 SDValue Ptr = MGT->getBasePtr();
1365 SDValue Mask = MGT->getMask();
1366 SDValue PassThru = MGT->getPassThru();
1367 SDValue Index = MGT->getIndex();
1368 SDValue Scale = MGT->getScale();
1369 unsigned Alignment = MGT->getOriginalAlignment();
1370
1371 // Split Mask operand
1372 SDValue MaskLo, MaskHi;
1373 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1374 GetSplitVector(Mask, MaskLo, MaskHi);
1375 else
1376 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1377
1378 EVT MemoryVT = MGT->getMemoryVT();
1379 EVT LoMemVT, HiMemVT;
1380 // Split MemoryVT
1381 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1382
1383 SDValue PassThruLo, PassThruHi;
1384 if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1385 GetSplitVector(PassThru, PassThruLo, PassThruHi);
1386 else
1387 std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1388
1389 SDValue IndexHi, IndexLo;
1390 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1391 GetSplitVector(Index, IndexLo, IndexHi);
1392 else
1393 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1394
1395 MachineMemOperand *MMO = DAG.getMachineFunction().
1396 getMachineMemOperand(MGT->getPointerInfo(),
1397 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1398 Alignment, MGT->getAAInfo(), MGT->getRanges());
1399
1400 SDValue OpsLo[] = {Ch, PassThruLo, MaskLo, Ptr, IndexLo, Scale};
1401 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1402 MMO);
1403
1404 SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Scale};
1405 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1406 MMO);
1407
1408 // Build a factor node to remember that this load is independent of the
1409 // other one.
1410 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1411 Hi.getValue(1));
1412
1413 // Legalize the chain result - switch anything that used the old chain to
1414 // use the new one.
1415 ReplaceValueWith(SDValue(MGT, 1), Ch);
1416}
1417
1418
1419void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1420 assert(N->getValueType(0).isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1422, __PRETTY_FUNCTION__))
1421 N->getOperand(0).getValueType().isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1422, __PRETTY_FUNCTION__))
1422 "Operand types must be vectors")((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1422, __PRETTY_FUNCTION__))
;
1423
1424 EVT LoVT, HiVT;
1425 SDLoc DL(N);
1426 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1427
1428 // If the input also splits, handle it directly. Otherwise split it by hand.
1429 SDValue LL, LH, RL, RH;
1430 if (getTypeAction(N->getOperand(0).getValueType()) ==
1431 TargetLowering::TypeSplitVector)
1432 GetSplitVector(N->getOperand(0), LL, LH);
1433 else
1434 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1435
1436 if (getTypeAction(N->getOperand(1).getValueType()) ==
1437 TargetLowering::TypeSplitVector)
1438 GetSplitVector(N->getOperand(1), RL, RH);
1439 else
1440 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1441
1442 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1443 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1444}
1445
1446void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1447 SDValue &Hi) {
1448 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1449 EVT LoVT, HiVT;
1450 SDLoc dl(N);
1451 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1452
1453 // If the input also splits, handle it directly for a compile time speedup.
1454 // Otherwise split it by hand.
1455 EVT InVT = N->getOperand(0).getValueType();
1456 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1457 GetSplitVector(N->getOperand(0), Lo, Hi);
1458 else
1459 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1460
1461 if (N->getOpcode() == ISD::FP_ROUND) {
1462 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1463 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1464 } else {
1465 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1466 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1467 }
1468}
1469
1470void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1471 SDValue &Hi) {
1472 SDLoc dl(N);
1473 EVT SrcVT = N->getOperand(0).getValueType();
1474 EVT DestVT = N->getValueType(0);
1475 EVT LoVT, HiVT;
1476 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1477
1478 // We can do better than a generic split operation if the extend is doing
1479 // more than just doubling the width of the elements and the following are
1480 // true:
1481 // - The number of vector elements is even,
1482 // - the source type is legal,
1483 // - the type of a split source is illegal,
1484 // - the type of an extended (by doubling element size) source is legal, and
1485 // - the type of that extended source when split is legal.
1486 //
1487 // This won't necessarily completely legalize the operation, but it will
1488 // more effectively move in the right direction and prevent falling down
1489 // to scalarization in many cases due to the input vector being split too
1490 // far.
1491 unsigned NumElements = SrcVT.getVectorNumElements();
1492 if ((NumElements & 1) == 0 &&
1493 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1494 LLVMContext &Ctx = *DAG.getContext();
1495 EVT NewSrcVT = SrcVT.widenIntegerVectorElementType(Ctx);
1496 EVT SplitSrcVT = SrcVT.getHalfNumVectorElementsVT(Ctx);
1497
1498 EVT SplitLoVT, SplitHiVT;
1499 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1500 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1501 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1502 LLVM_DEBUG(dbgs() << "Split vector extend via incremental extend:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split vector extend via incremental extend:"
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
1503 N->dump(&DAG); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split vector extend via incremental extend:"
; N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1504 // Extend the source vector by one step.
1505 SDValue NewSrc =
1506 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1507 // Get the low and high halves of the new, extended one step, vector.
1508 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1509 // Extend those vector halves the rest of the way.
1510 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1511 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1512 return;
1513 }
1514 }
1515 // Fall back to the generic unary operator splitting otherwise.
1516 SplitVecRes_UnaryOp(N, Lo, Hi);
1517}
1518
1519void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1520 SDValue &Lo, SDValue &Hi) {
1521 // The low and high parts of the original input give four input vectors.
1522 SDValue Inputs[4];
1523 SDLoc dl(N);
1524 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1525 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1526 EVT NewVT = Inputs[0].getValueType();
1527 unsigned NewElts = NewVT.getVectorNumElements();
1528
1529 // If Lo or Hi uses elements from at most two of the four input vectors, then
1530 // express it as a vector shuffle of those two inputs. Otherwise extract the
1531 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1532 SmallVector<int, 16> Ops;
1533 for (unsigned High = 0; High < 2; ++High) {
1534 SDValue &Output = High ? Hi : Lo;
1535
1536 // Build a shuffle mask for the output, discovering on the fly which
1537 // input vectors to use as shuffle operands (recorded in InputUsed).
1538 // If building a suitable shuffle vector proves too hard, then bail
1539 // out with useBuildVector set.
1540 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1541 unsigned FirstMaskIdx = High * NewElts;
1542 bool useBuildVector = false;
1543 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1544 // The mask element. This indexes into the input.
1545 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1546
1547 // The input vector this mask element indexes into.
1548 unsigned Input = (unsigned)Idx / NewElts;
1549
1550 if (Input >= array_lengthof(Inputs)) {
1551 // The mask element does not index into any input vector.
1552 Ops.push_back(-1);
1553 continue;
1554 }
1555
1556 // Turn the index into an offset from the start of the input vector.
1557 Idx -= Input * NewElts;
1558
1559 // Find or create a shuffle vector operand to hold this input.
1560 unsigned OpNo;
1561 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1562 if (InputUsed[OpNo] == Input) {
1563 // This input vector is already an operand.
1564 break;
1565 } else if (InputUsed[OpNo] == -1U) {
1566 // Create a new operand for this input vector.
1567 InputUsed[OpNo] = Input;
1568 break;
1569 }
1570 }
1571
1572 if (OpNo >= array_lengthof(InputUsed)) {
1573 // More than two input vectors used! Give up on trying to create a
1574 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1575 useBuildVector = true;
1576 break;
1577 }
1578
1579 // Add the mask index for the new shuffle vector.
1580 Ops.push_back(Idx + OpNo * NewElts);
1581 }
1582
1583 if (useBuildVector) {
1584 EVT EltVT = NewVT.getVectorElementType();
1585 SmallVector<SDValue, 16> SVOps;
1586
1587 // Extract the input elements by hand.
1588 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1589 // The mask element. This indexes into the input.
1590 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1591
1592 // The input vector this mask element indexes into.
1593 unsigned Input = (unsigned)Idx / NewElts;
1594
1595 if (Input >= array_lengthof(Inputs)) {
1596 // The mask element is "undef" or indexes off the end of the input.
1597 SVOps.push_back(DAG.getUNDEF(EltVT));
1598 continue;
1599 }
1600
1601 // Turn the index into an offset from the start of the input vector.
1602 Idx -= Input * NewElts;
1603
1604 // Extract the vector element by hand.
1605 SVOps.push_back(DAG.getNode(
1606 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Inputs[Input],
1607 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
1608 }
1609
1610 // Construct the Lo/Hi output using a BUILD_VECTOR.
1611 Output = DAG.getBuildVector(NewVT, dl, SVOps);
1612 } else if (InputUsed[0] == -1U) {
1613 // No input vectors were used! The result is undefined.
1614 Output = DAG.getUNDEF(NewVT);
1615 } else {
1616 SDValue Op0 = Inputs[InputUsed[0]];
1617 // If only one input was used, use an undefined vector for the other.
1618 SDValue Op1 = InputUsed[1] == -1U ?
1619 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1620 // At least one input vector was used. Create a new shuffle vector.
1621 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, Ops);
1622 }
1623
1624 Ops.clear();
1625 }
1626}
1627
1628
1629//===----------------------------------------------------------------------===//
1630// Operand Vector Splitting
1631//===----------------------------------------------------------------------===//
1632
1633/// This method is called when the specified operand of the specified node is
1634/// found to need vector splitting. At this point, all of the result types of
1635/// the node are known to be legal, but other operands of the node may need
1636/// legalization as well as the specified one.
1637bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1638 LLVM_DEBUG(dbgs() << "Split node operand: "; N->dump(&DAG); dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Split node operand: ";
N->dump(&DAG); dbgs() << "\n"; } } while (false
)
;
1639 SDValue Res = SDValue();
1640
1641 // See if the target wants to custom split this node.
1642 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1643 return false;
1644
1645 if (!Res.getNode()) {
1646 switch (N->getOpcode()) {
1647 default:
1648#ifndef NDEBUG
1649 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1650 N->dump(&DAG);
1651 dbgs() << "\n";
1652#endif
1653 report_fatal_error("Do not know how to split this operator's "
1654 "operand!\n");
1655
1656 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1657 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1658 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1659 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1660 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1661 case ISD::TRUNCATE:
1662 Res = SplitVecOp_TruncateHelper(N);
1663 break;
1664 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1665 case ISD::FCOPYSIGN: Res = SplitVecOp_FCOPYSIGN(N); break;
1666 case ISD::STORE:
1667 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1668 break;
1669 case ISD::MSTORE:
1670 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1671 break;
1672 case ISD::MSCATTER:
1673 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1674 break;
1675 case ISD::MGATHER:
1676 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1677 break;
1678 case ISD::VSELECT:
1679 Res = SplitVecOp_VSELECT(N, OpNo);
1680 break;
1681 case ISD::FP_TO_SINT:
1682 case ISD::FP_TO_UINT:
1683 if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
1684 Res = SplitVecOp_TruncateHelper(N);
1685 else
1686 Res = SplitVecOp_UnaryOp(N);
1687 break;
1688 case ISD::SINT_TO_FP:
1689 case ISD::UINT_TO_FP:
1690 if (N->getValueType(0).bitsLT(N->getOperand(0).getValueType()))
1691 Res = SplitVecOp_TruncateHelper(N);
1692 else
1693 Res = SplitVecOp_UnaryOp(N);
1694 break;
1695 case ISD::CTTZ:
1696 case ISD::CTLZ:
1697 case ISD::CTPOP:
1698 case ISD::FP_EXTEND:
1699 case ISD::SIGN_EXTEND:
1700 case ISD::ZERO_EXTEND:
1701 case ISD::ANY_EXTEND:
1702 case ISD::FTRUNC:
1703 case ISD::FCANONICALIZE:
1704 Res = SplitVecOp_UnaryOp(N);
1705 break;
1706
1707 case ISD::ANY_EXTEND_VECTOR_INREG:
1708 case ISD::SIGN_EXTEND_VECTOR_INREG:
1709 case ISD::ZERO_EXTEND_VECTOR_INREG:
1710 Res = SplitVecOp_ExtVecInRegOp(N);
1711 break;
1712
1713 case ISD::VECREDUCE_FADD:
1714 case ISD::VECREDUCE_FMUL:
1715 case ISD::VECREDUCE_ADD:
1716 case ISD::VECREDUCE_MUL:
1717 case ISD::VECREDUCE_AND:
1718 case ISD::VECREDUCE_OR:
1719 case ISD::VECREDUCE_XOR:
1720 case ISD::VECREDUCE_SMAX:
1721 case ISD::VECREDUCE_SMIN:
1722 case ISD::VECREDUCE_UMAX:
1723 case ISD::VECREDUCE_UMIN:
1724 case ISD::VECREDUCE_FMAX:
1725 case ISD::VECREDUCE_FMIN:
1726 Res = SplitVecOp_VECREDUCE(N, OpNo);
1727 break;
1728 }
1729 }
1730
1731 // If the result is null, the sub-method took care of registering results etc.
1732 if (!Res.getNode()) return false;
1733
1734 // If the result is N, the sub-method updated N in place. Tell the legalizer
1735 // core about this.
1736 if (Res.getNode() == N)
1737 return true;
1738
1739 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1740, __PRETTY_FUNCTION__))
1740 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1740, __PRETTY_FUNCTION__))
;
1741
1742 ReplaceValueWith(SDValue(N, 0), Res);
1743 return false;
1744}
1745
1746SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1747 // The only possibility for an illegal operand is the mask, since result type
1748 // legalization would have handled this node already otherwise.
1749 assert(OpNo == 0 && "Illegal operand must be mask")((OpNo == 0 && "Illegal operand must be mask") ? static_cast
<void> (0) : __assert_fail ("OpNo == 0 && \"Illegal operand must be mask\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1749, __PRETTY_FUNCTION__))
;
1750
1751 SDValue Mask = N->getOperand(0);
1752 SDValue Src0 = N->getOperand(1);
1753 SDValue Src1 = N->getOperand(2);
1754 EVT Src0VT = Src0.getValueType();
1755 SDLoc DL(N);
1756 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?")((Mask.getValueType().isVector() && "VSELECT without a vector mask?"
) ? static_cast<void> (0) : __assert_fail ("Mask.getValueType().isVector() && \"VSELECT without a vector mask?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1756, __PRETTY_FUNCTION__))
;
1757
1758 SDValue Lo, Hi;
1759 GetSplitVector(N->getOperand(0), Lo, Hi);
1760 assert(Lo.getValueType() == Hi.getValueType() &&((Lo.getValueType() == Hi.getValueType() && "Lo and Hi have differing types"
) ? static_cast<void> (0) : __assert_fail ("Lo.getValueType() == Hi.getValueType() && \"Lo and Hi have differing types\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1761, __PRETTY_FUNCTION__))
1761 "Lo and Hi have differing types")((Lo.getValueType() == Hi.getValueType() && "Lo and Hi have differing types"
) ? static_cast<void> (0) : __assert_fail ("Lo.getValueType() == Hi.getValueType() && \"Lo and Hi have differing types\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1761, __PRETTY_FUNCTION__))
;
1762
1763 EVT LoOpVT, HiOpVT;
1764 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1765 assert(LoOpVT == HiOpVT && "Asymmetric vector split?")((LoOpVT == HiOpVT && "Asymmetric vector split?") ? static_cast
<void> (0) : __assert_fail ("LoOpVT == HiOpVT && \"Asymmetric vector split?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1765, __PRETTY_FUNCTION__))
;
1766
1767 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1768 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1769 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1770 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1771
1772 SDValue LoSelect =
1773 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1774 SDValue HiSelect =
1775 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1776
1777 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1778}
1779
1780SDValue DAGTypeLegalizer::SplitVecOp_VECREDUCE(SDNode *N, unsigned OpNo) {
1781 EVT ResVT = N->getValueType(0);
1782 SDValue Lo, Hi;
1783 SDLoc dl(N);
1784
1785 SDValue VecOp = N->getOperand(OpNo);
1786 EVT VecVT = VecOp.getValueType();
1787 assert(VecVT.isVector() && "Can only split reduce vector operand")((VecVT.isVector() && "Can only split reduce vector operand"
) ? static_cast<void> (0) : __assert_fail ("VecVT.isVector() && \"Can only split reduce vector operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1787, __PRETTY_FUNCTION__))
;
1788 GetSplitVector(VecOp, Lo, Hi);
1789 EVT LoOpVT, HiOpVT;
1790 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(VecVT);
1791
1792 bool NoNaN = N->getFlags().hasNoNaNs();
1793 unsigned CombineOpc = 0;
1794 switch (N->getOpcode()) {
1795 case ISD::VECREDUCE_FADD: CombineOpc = ISD::FADD; break;
1796 case ISD::VECREDUCE_FMUL: CombineOpc = ISD::FMUL; break;
1797 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
1798 case ISD::VECREDUCE_MUL: CombineOpc = ISD::MUL; break;
1799 case ISD::VECREDUCE_AND: CombineOpc = ISD::AND; break;
1800 case ISD::VECREDUCE_OR: CombineOpc = ISD::OR; break;
1801 case ISD::VECREDUCE_XOR: CombineOpc = ISD::XOR; break;
1802 case ISD::VECREDUCE_SMAX: CombineOpc = ISD::SMAX; break;
1803 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break;
1804 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
1805 case ISD::VECREDUCE_UMIN: CombineOpc = ISD::UMIN; break;
1806 case ISD::VECREDUCE_FMAX:
1807 CombineOpc = NoNaN ? ISD::FMAXNUM : ISD::FMAXIMUM;
1808 break;
1809 case ISD::VECREDUCE_FMIN:
1810 CombineOpc = NoNaN ? ISD::FMINNUM : ISD::FMINIMUM;
1811 break;
1812 default:
1813 llvm_unreachable("Unexpected reduce ISD node")::llvm::llvm_unreachable_internal("Unexpected reduce ISD node"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1813)
;
1814 }
1815
1816 // Use the appropriate scalar instruction on the split subvectors before
1817 // reducing the now partially reduced smaller vector.
1818 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
1819 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
1820}
1821
1822SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1823 // The result has a legal vector type, but the input needs splitting.
1824 EVT ResVT = N->getValueType(0);
1825 SDValue Lo, Hi;
1826 SDLoc dl(N);
1827 GetSplitVector(N->getOperand(0), Lo, Hi);
1828 EVT InVT = Lo.getValueType();
1829
1830 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1831 InVT.getVectorNumElements());
1832
1833 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1834 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1835
1836 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1837}
1838
1839SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1840 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1841 // end up being split all the way down to individual components. Convert the
1842 // split pieces into integers and reassemble.
1843 SDValue Lo, Hi;
1844 GetSplitVector(N->getOperand(0), Lo, Hi);
1845 Lo = BitConvertToInteger(Lo);
1846 Hi = BitConvertToInteger(Hi);
1847
1848 if (DAG.getDataLayout().isBigEndian())
1849 std::swap(Lo, Hi);
1850
1851 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1852 JoinIntegers(Lo, Hi));
1853}
1854
1855SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1856 // We know that the extracted result type is legal.
1857 EVT SubVT = N->getValueType(0);
1858 SDValue Idx = N->getOperand(1);
1859 SDLoc dl(N);
1860 SDValue Lo, Hi;
1861 GetSplitVector(N->getOperand(0), Lo, Hi);
1862
1863 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1864 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1865
1866 if (IdxVal < LoElts) {
1867 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&((IdxVal + SubVT.getVectorNumElements() <= LoElts &&
"Extracted subvector crosses vector split!") ? static_cast<
void> (0) : __assert_fail ("IdxVal + SubVT.getVectorNumElements() <= LoElts && \"Extracted subvector crosses vector split!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1868, __PRETTY_FUNCTION__))
1868 "Extracted subvector crosses vector split!")((IdxVal + SubVT.getVectorNumElements() <= LoElts &&
"Extracted subvector crosses vector split!") ? static_cast<
void> (0) : __assert_fail ("IdxVal + SubVT.getVectorNumElements() <= LoElts && \"Extracted subvector crosses vector split!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1868, __PRETTY_FUNCTION__))
;
1869 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1870 } else {
1871 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1872 DAG.getConstant(IdxVal - LoElts, dl,
1873 Idx.getValueType()));
1874 }
1875}
1876
1877SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1878 SDValue Vec = N->getOperand(0);
1879 SDValue Idx = N->getOperand(1);
1880 EVT VecVT = Vec.getValueType();
1881
1882 if (isa<ConstantSDNode>(Idx)) {
1883 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1884 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!")((IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!"
) ? static_cast<void> (0) : __assert_fail ("IdxVal < VecVT.getVectorNumElements() && \"Invalid vector index!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 1884, __PRETTY_FUNCTION__))
;
1885
1886 SDValue Lo, Hi;
1887 GetSplitVector(Vec, Lo, Hi);
1888
1889 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1890
1891 if (IdxVal < LoElts)
1892 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1893 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1894 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1895 Idx.getValueType())), 0);
1896 }
1897
1898 // See if the target wants to custom expand this node.
1899 if (CustomLowerNode(N, N->getValueType(0), true))
1900 return SDValue();
1901
1902 // Make the vector elements byte-addressable if they aren't already.
1903 SDLoc dl(N);
1904 EVT EltVT = VecVT.getVectorElementType();
1905 if (VecVT.getScalarSizeInBits() < 8) {
1906 EltVT = MVT::i8;
1907 VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
1908 VecVT.getVectorNumElements());
1909 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec);
1910 }
1911
1912 // Store the vector to the stack.
1913 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1914 auto &MF = DAG.getMachineFunction();
1915 auto FrameIndex = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1916 auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
1917 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo);
1918
1919 // Load back the required element.
1920 StackPtr = TLI.getVectorElementPointer(DAG, StackPtr, VecVT, Idx);
1921 return DAG.getExtLoad(
1922 ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1923 MachinePointerInfo::getUnknownStack(DAG.getMachineFunction()), EltVT);
1924}
1925
1926SDValue DAGTypeLegalizer::SplitVecOp_ExtVecInRegOp(SDNode *N) {
1927 SDValue Lo, Hi;
1928
1929 // *_EXTEND_VECTOR_INREG only reference the lower half of the input, so
1930 // splitting the result has the same effect as splitting the input operand.
1931 SplitVecRes_ExtVecInRegOp(N, Lo, Hi);
1932
1933 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), N->getValueType(0), Lo, Hi);
1934}
1935
1936SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1937 unsigned OpNo) {
1938 EVT LoVT, HiVT;
1939 SDLoc dl(MGT);
1940 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1941
1942 SDValue Ch = MGT->getChain();
1943 SDValue Ptr = MGT->getBasePtr();
1944 SDValue Index = MGT->getIndex();
1945 SDValue Scale = MGT->getScale();
1946 SDValue Mask = MGT->getMask();
1947 SDValue PassThru = MGT->getPassThru();
1948 unsigned Alignment = MGT->getOriginalAlignment();
1949
1950 SDValue MaskLo, MaskHi;
1951 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
1952 // Split Mask operand
1953 GetSplitVector(Mask, MaskLo, MaskHi);
1954 else
1955 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1956
1957 EVT MemoryVT = MGT->getMemoryVT();
1958 EVT LoMemVT, HiMemVT;
1959 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1960
1961 SDValue PassThruLo, PassThruHi;
1962 if (getTypeAction(PassThru.getValueType()) == TargetLowering::TypeSplitVector)
1963 GetSplitVector(PassThru, PassThruLo, PassThruHi);
1964 else
1965 std::tie(PassThruLo, PassThruHi) = DAG.SplitVector(PassThru, dl);
1966
1967 SDValue IndexHi, IndexLo;
1968 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
1969 GetSplitVector(Index, IndexLo, IndexHi);
1970 else
1971 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1972
1973 MachineMemOperand *MMO = DAG.getMachineFunction().
1974 getMachineMemOperand(MGT->getPointerInfo(),
1975 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1976 Alignment, MGT->getAAInfo(), MGT->getRanges());
1977
1978 SDValue OpsLo[] = {Ch, PassThruLo, MaskLo, Ptr, IndexLo, Scale};
1979 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1980 OpsLo, MMO);
1981
1982 MMO = DAG.getMachineFunction().
1983 getMachineMemOperand(MGT->getPointerInfo(),
1984 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1985 Alignment, MGT->getAAInfo(),
1986 MGT->getRanges());
1987
1988 SDValue OpsHi[] = {Ch, PassThruHi, MaskHi, Ptr, IndexHi, Scale};
1989 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1990 OpsHi, MMO);
1991
1992 // Build a factor node to remember that this load is independent of the
1993 // other one.
1994 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1995 Hi.getValue(1));
1996
1997 // Legalize the chain result - switch anything that used the old chain to
1998 // use the new one.
1999 ReplaceValueWith(SDValue(MGT, 1), Ch);
2000
2001 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
2002 Hi);
2003 ReplaceValueWith(SDValue(MGT, 0), Res);
2004 return SDValue();
2005}
2006
2007SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
2008 unsigned OpNo) {
2009 SDValue Ch = N->getChain();
2010 SDValue Ptr = N->getBasePtr();
2011 SDValue Mask = N->getMask();
2012 SDValue Data = N->getValue();
2013 EVT MemoryVT = N->getMemoryVT();
2014 unsigned Alignment = N->getOriginalAlignment();
2015 SDLoc DL(N);
2016
2017 EVT LoMemVT, HiMemVT;
2018 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2019
2020 SDValue DataLo, DataHi;
2021 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2022 // Split Data operand
2023 GetSplitVector(Data, DataLo, DataHi);
2024 else
2025 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2026
2027 SDValue MaskLo, MaskHi;
2028 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2029 // Split Mask operand
2030 GetSplitVector(Mask, MaskLo, MaskHi);
2031 else
2032 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2033
2034 // if Alignment is equal to the vector size,
2035 // take the half of it for the second part
2036 unsigned SecondHalfAlignment =
2037 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
2038 Alignment/2 : Alignment;
2039
2040 SDValue Lo, Hi;
2041 MachineMemOperand *MMO = DAG.getMachineFunction().
2042 getMachineMemOperand(N->getPointerInfo(),
2043 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
2044 Alignment, N->getAAInfo(), N->getRanges());
2045
2046 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
2047 N->isTruncatingStore(),
2048 N->isCompressingStore());
2049
2050 Ptr = TLI.IncrementMemoryAddress(Ptr, MaskLo, DL, LoMemVT, DAG,
2051 N->isCompressingStore());
2052 unsigned HiOffset = LoMemVT.getStoreSize();
2053
2054 MMO = DAG.getMachineFunction().getMachineMemOperand(
2055 N->getPointerInfo().getWithOffset(HiOffset), MachineMemOperand::MOStore,
2056 HiMemVT.getStoreSize(), SecondHalfAlignment, N->getAAInfo(),
2057 N->getRanges());
2058
2059 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
2060 N->isTruncatingStore(), N->isCompressingStore());
2061
2062 // Build a factor node to remember that this store is independent of the
2063 // other one.
2064 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2065}
2066
2067SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
2068 unsigned OpNo) {
2069 SDValue Ch = N->getChain();
2070 SDValue Ptr = N->getBasePtr();
2071 SDValue Mask = N->getMask();
2072 SDValue Index = N->getIndex();
2073 SDValue Scale = N->getScale();
2074 SDValue Data = N->getValue();
2075 EVT MemoryVT = N->getMemoryVT();
2076 unsigned Alignment = N->getOriginalAlignment();
2077 SDLoc DL(N);
2078
2079 // Split all operands
2080 EVT LoMemVT, HiMemVT;
2081 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2082
2083 SDValue DataLo, DataHi;
2084 if (getTypeAction(Data.getValueType()) == TargetLowering::TypeSplitVector)
2085 // Split Data operand
2086 GetSplitVector(Data, DataLo, DataHi);
2087 else
2088 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
2089
2090 SDValue MaskLo, MaskHi;
2091 if (getTypeAction(Mask.getValueType()) == TargetLowering::TypeSplitVector)
2092 // Split Mask operand
2093 GetSplitVector(Mask, MaskLo, MaskHi);
2094 else
2095 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, DL);
2096
2097 SDValue IndexHi, IndexLo;
2098 if (getTypeAction(Index.getValueType()) == TargetLowering::TypeSplitVector)
2099 GetSplitVector(Index, IndexLo, IndexHi);
2100 else
2101 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
2102
2103 SDValue Lo;
2104 MachineMemOperand *MMO = DAG.getMachineFunction().
2105 getMachineMemOperand(N->getPointerInfo(),
2106 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
2107 Alignment, N->getAAInfo(), N->getRanges());
2108
2109 SDValue OpsLo[] = {Ch, DataLo, MaskLo, Ptr, IndexLo, Scale};
2110 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
2111 DL, OpsLo, MMO);
2112
2113 MMO = DAG.getMachineFunction().
2114 getMachineMemOperand(N->getPointerInfo(),
2115 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
2116 Alignment, N->getAAInfo(), N->getRanges());
2117
2118 // The order of the Scatter operation after split is well defined. The "Hi"
2119 // part comes after the "Lo". So these two operations should be chained one
2120 // after another.
2121 SDValue OpsHi[] = {Lo, DataHi, MaskHi, Ptr, IndexHi, Scale};
2122 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
2123 DL, OpsHi, MMO);
2124}
2125
2126SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
2127 assert(N->isUnindexed() && "Indexed store of vector?")((N->isUnindexed() && "Indexed store of vector?") ?
static_cast<void> (0) : __assert_fail ("N->isUnindexed() && \"Indexed store of vector?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2127, __PRETTY_FUNCTION__))
;
2128 assert(OpNo == 1 && "Can only split the stored value")((OpNo == 1 && "Can only split the stored value") ? static_cast
<void> (0) : __assert_fail ("OpNo == 1 && \"Can only split the stored value\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2128, __PRETTY_FUNCTION__))
;
2129 SDLoc DL(N);
2130
2131 bool isTruncating = N->isTruncatingStore();
2132 SDValue Ch = N->getChain();
2133 SDValue Ptr = N->getBasePtr();
2134 EVT MemoryVT = N->getMemoryVT();
2135 unsigned Alignment = N->getOriginalAlignment();
2136 MachineMemOperand::Flags MMOFlags = N->getMemOperand()->getFlags();
2137 AAMDNodes AAInfo = N->getAAInfo();
2138 SDValue Lo, Hi;
2139 GetSplitVector(N->getOperand(1), Lo, Hi);
2140
2141 EVT LoMemVT, HiMemVT;
2142 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
2143
2144 // Scalarize if the split halves are not byte-sized.
2145 if (!LoMemVT.isByteSized() || !HiMemVT.isByteSized())
2146 return TLI.scalarizeVectorStore(N, DAG);
2147
2148 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
2149
2150 if (isTruncating)
2151 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), LoMemVT,
2152 Alignment, MMOFlags, AAInfo);
2153 else
2154 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(), Alignment, MMOFlags,
2155 AAInfo);
2156
2157 // Increment the pointer to the other half.
2158 Ptr = DAG.getObjectPtrOffset(DL, Ptr, IncrementSize);
2159
2160 if (isTruncating)
2161 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
2162 N->getPointerInfo().getWithOffset(IncrementSize),
2163 HiMemVT, Alignment, MMOFlags, AAInfo);
2164 else
2165 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
2166 N->getPointerInfo().getWithOffset(IncrementSize),
2167 Alignment, MMOFlags, AAInfo);
2168
2169 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
2170}
2171
2172SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
2173 SDLoc DL(N);
2174
2175 // The input operands all must have the same type, and we know the result
2176 // type is valid. Convert this to a buildvector which extracts all the
2177 // input elements.
2178 // TODO: If the input elements are power-two vectors, we could convert this to
2179 // a new CONCAT_VECTORS node with elements that are half-wide.
2180 SmallVector<SDValue, 32> Elts;
2181 EVT EltVT = N->getValueType(0).getVectorElementType();
2182 for (const SDValue &Op : N->op_values()) {
2183 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
2184 i != e; ++i) {
2185 Elts.push_back(DAG.getNode(
2186 ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Op,
2187 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
2188 }
2189 }
2190
2191 return DAG.getBuildVector(N->getValueType(0), DL, Elts);
2192}
2193
2194SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
2195 // The result type is legal, but the input type is illegal. If splitting
2196 // ends up with the result type of each half still being legal, just
2197 // do that. If, however, that would result in an illegal result type,
2198 // we can try to get more clever with power-two vectors. Specifically,
2199 // split the input type, but also widen the result element size, then
2200 // concatenate the halves and truncate again. For example, consider a target
2201 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
2202 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
2203 // %inlo = v4i32 extract_subvector %in, 0
2204 // %inhi = v4i32 extract_subvector %in, 4
2205 // %lo16 = v4i16 trunc v4i32 %inlo
2206 // %hi16 = v4i16 trunc v4i32 %inhi
2207 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
2208 // %res = v8i8 trunc v8i16 %in16
2209 //
2210 // Without this transform, the original truncate would end up being
2211 // scalarized, which is pretty much always a last resort.
2212 SDValue InVec = N->getOperand(0);
2213 EVT InVT = InVec->getValueType(0);
2214 EVT OutVT = N->getValueType(0);
2215 unsigned NumElements = OutVT.getVectorNumElements();
2216 bool IsFloat = OutVT.isFloatingPoint();
2217
2218 // Widening should have already made sure this is a power-two vector
2219 // if we're trying to split it at all. assert() that's true, just in case.
2220 assert(!(NumElements & 1) && "Splitting vector, but not in half!")((!(NumElements & 1) && "Splitting vector, but not in half!"
) ? static_cast<void> (0) : __assert_fail ("!(NumElements & 1) && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2220, __PRETTY_FUNCTION__))
;
2221
2222 unsigned InElementSize = InVT.getScalarSizeInBits();
2223 unsigned OutElementSize = OutVT.getScalarSizeInBits();
2224
2225 // If the input elements are only 1/2 the width of the result elements,
2226 // just use the normal splitting. Our trick only work if there's room
2227 // to split more than once.
2228 if (InElementSize <= OutElementSize * 2)
2229 return SplitVecOp_UnaryOp(N);
2230 SDLoc DL(N);
2231
2232 // Get the split input vector.
2233 SDValue InLoVec, InHiVec;
2234 GetSplitVector(InVec, InLoVec, InHiVec);
2235 // Truncate them to 1/2 the element size.
2236 EVT HalfElementVT = IsFloat ?
2237 EVT::getFloatingPointVT(InElementSize/2) :
2238 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
2239 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
2240 NumElements/2);
2241 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
2242 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
2243 // Concatenate them to get the full intermediate truncation result.
2244 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
2245 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
2246 HalfHi);
2247 // Now finish up by truncating all the way down to the original result
2248 // type. This should normally be something that ends up being legal directly,
2249 // but in theory if a target has very wide vectors and an annoyingly
2250 // restricted set of legal types, this split can chain to build things up.
2251 return IsFloat
2252 ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
2253 DAG.getTargetConstant(
2254 0, DL, TLI.getPointerTy(DAG.getDataLayout())))
2255 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
2256}
2257
2258SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
2259 assert(N->getValueType(0).isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2261, __PRETTY_FUNCTION__))
2260 N->getOperand(0).getValueType().isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2261, __PRETTY_FUNCTION__))
2261 "Operand types must be vectors")((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operand types must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operand types must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2261, __PRETTY_FUNCTION__))
;
2262 // The result has a legal vector type, but the input needs splitting.
2263 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
2264 SDLoc DL(N);
2265 GetSplitVector(N->getOperand(0), Lo0, Hi0);
2266 GetSplitVector(N->getOperand(1), Lo1, Hi1);
2267 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
2268 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
2269 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
2270
2271 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
2272 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
2273 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
2274 return PromoteTargetBoolean(Con, N->getValueType(0));
2275}
2276
2277
2278SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
2279 // The result has a legal vector type, but the input needs splitting.
2280 EVT ResVT = N->getValueType(0);
2281 SDValue Lo, Hi;
2282 SDLoc DL(N);
2283 GetSplitVector(N->getOperand(0), Lo, Hi);
2284 EVT InVT = Lo.getValueType();
2285
2286 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
2287 InVT.getVectorNumElements());
2288
2289 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
2290 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
2291
2292 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
2293}
2294
2295SDValue DAGTypeLegalizer::SplitVecOp_FCOPYSIGN(SDNode *N) {
2296 // The result (and the first input) has a legal vector type, but the second
2297 // input needs splitting.
2298 return DAG.UnrollVectorOp(N, N->getValueType(0).getVectorNumElements());
2299}
2300
2301
2302//===----------------------------------------------------------------------===//
2303// Result Vector Widening
2304//===----------------------------------------------------------------------===//
2305
2306void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
2307 LLVM_DEBUG(dbgs() << "Widen node result " << ResNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node result " <<
ResNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
2308 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node result " <<
ResNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
;
2309
2310 // See if the target wants to custom widen this node.
2311 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
2312 return;
2313
2314 SDValue Res = SDValue();
2315 switch (N->getOpcode()) {
2316 default:
2317#ifndef NDEBUG
2318 dbgs() << "WidenVectorResult #" << ResNo << ": ";
2319 N->dump(&DAG);
2320 dbgs() << "\n";
2321#endif
2322 llvm_unreachable("Do not know how to widen the result of this operator!")::llvm::llvm_unreachable_internal("Do not know how to widen the result of this operator!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2322)
;
2323
2324 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
2325 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
2326 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
2327 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
2328 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2329 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
2330 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
2331 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
2332 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
2333 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
2334 case ISD::VSELECT:
2335 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
2336 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
2337 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
2338 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
2339 case ISD::VECTOR_SHUFFLE:
2340 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
2341 break;
2342 case ISD::MLOAD:
2343 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
2344 break;
2345 case ISD::MGATHER:
2346 Res = WidenVecRes_MGATHER(cast<MaskedGatherSDNode>(N));
2347 break;
2348
2349 case ISD::ADD:
2350 case ISD::AND:
2351 case ISD::MUL:
2352 case ISD::MULHS:
2353 case ISD::MULHU:
2354 case ISD::OR:
2355 case ISD::SUB:
2356 case ISD::XOR:
2357 case ISD::FMINNUM:
2358 case ISD::FMAXNUM:
2359 case ISD::FMINIMUM:
2360 case ISD::FMAXIMUM:
2361 case ISD::SMIN:
2362 case ISD::SMAX:
2363 case ISD::UMIN:
2364 case ISD::UMAX:
2365 Res = WidenVecRes_Binary(N);
2366 break;
2367
2368 case ISD::FADD:
2369 case ISD::FMUL:
2370 case ISD::FPOW:
2371 case ISD::FSUB:
2372 case ISD::FDIV:
2373 case ISD::FREM:
2374 case ISD::SDIV:
2375 case ISD::UDIV:
2376 case ISD::SREM:
2377 case ISD::UREM:
2378 Res = WidenVecRes_BinaryCanTrap(N);
2379 break;
2380
2381 case ISD::STRICT_FADD:
2382 case ISD::STRICT_FSUB:
2383 case ISD::STRICT_FMUL:
2384 case ISD::STRICT_FDIV:
2385 case ISD::STRICT_FREM:
2386 case ISD::STRICT_FSQRT:
2387 case ISD::STRICT_FMA:
2388 case ISD::STRICT_FPOW:
2389 case ISD::STRICT_FPOWI:
2390 case ISD::STRICT_FSIN:
2391 case ISD::STRICT_FCOS:
2392 case ISD::STRICT_FEXP:
2393 case ISD::STRICT_FEXP2:
2394 case ISD::STRICT_FLOG:
2395 case ISD::STRICT_FLOG10:
2396 case ISD::STRICT_FLOG2:
2397 case ISD::STRICT_FRINT:
2398 case ISD::STRICT_FNEARBYINT:
2399 Res = WidenVecRes_StrictFP(N);
2400 break;
2401
2402 case ISD::FCOPYSIGN:
2403 Res = WidenVecRes_FCOPYSIGN(N);
2404 break;
2405
2406 case ISD::FPOWI:
2407 Res = WidenVecRes_POWI(N);
2408 break;
2409
2410 case ISD::SHL:
2411 case ISD::SRA:
2412 case ISD::SRL:
2413 Res = WidenVecRes_Shift(N);
2414 break;
2415
2416 case ISD::ANY_EXTEND_VECTOR_INREG:
2417 case ISD::SIGN_EXTEND_VECTOR_INREG:
2418 case ISD::ZERO_EXTEND_VECTOR_INREG:
2419 Res = WidenVecRes_EXTEND_VECTOR_INREG(N);
2420 break;
2421
2422 case ISD::ANY_EXTEND:
2423 case ISD::FP_EXTEND:
2424 case ISD::FP_ROUND:
2425 case ISD::FP_TO_SINT:
2426 case ISD::FP_TO_UINT:
2427 case ISD::SIGN_EXTEND:
2428 case ISD::SINT_TO_FP:
2429 case ISD::TRUNCATE:
2430 case ISD::UINT_TO_FP:
2431 case ISD::ZERO_EXTEND:
2432 Res = WidenVecRes_Convert(N);
2433 break;
2434
2435 case ISD::FABS:
2436 case ISD::FCEIL:
2437 case ISD::FCOS:
2438 case ISD::FEXP:
2439 case ISD::FEXP2:
2440 case ISD::FFLOOR:
2441 case ISD::FLOG:
2442 case ISD::FLOG10:
2443 case ISD::FLOG2:
2444 case ISD::FNEARBYINT:
2445 case ISD::FRINT:
2446 case ISD::FROUND:
2447 case ISD::FSIN:
2448 case ISD::FSQRT:
2449 case ISD::FTRUNC: {
2450 // We're going to widen this vector op to a legal type by padding with undef
2451 // elements. If the wide vector op is eventually going to be expanded to
2452 // scalar libcalls, then unroll into scalar ops now to avoid unnecessary
2453 // libcalls on the undef elements. We are assuming that if the scalar op
2454 // requires expanding, then the vector op needs expanding too.
2455 EVT VT = N->getValueType(0);
2456 if (TLI.isOperationExpand(N->getOpcode(), VT.getScalarType())) {
2457 EVT WideVecVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2458 assert(!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) &&((!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT)
&& "Target supports vector op, but scalar requires expansion?"
) ? static_cast<void> (0) : __assert_fail ("!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) && \"Target supports vector op, but scalar requires expansion?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2459, __PRETTY_FUNCTION__))
2459 "Target supports vector op, but scalar requires expansion?")((!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT)
&& "Target supports vector op, but scalar requires expansion?"
) ? static_cast<void> (0) : __assert_fail ("!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) && \"Target supports vector op, but scalar requires expansion?\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2459, __PRETTY_FUNCTION__))
;
2460 Res = DAG.UnrollVectorOp(N, WideVecVT.getVectorNumElements());
2461 break;
2462 }
2463 }
2464 // If the target has custom/legal support for the scalar FP intrinsic ops
2465 // (they are probably not destined to become libcalls), then widen those like
2466 // any other unary ops.
2467 LLVM_FALLTHROUGH[[clang::fallthrough]];
2468
2469 case ISD::BITREVERSE:
2470 case ISD::BSWAP:
2471 case ISD::CTLZ:
2472 case ISD::CTPOP:
2473 case ISD::CTTZ:
2474 case ISD::FNEG:
2475 case ISD::FCANONICALIZE:
2476 Res = WidenVecRes_Unary(N);
2477 break;
2478 case ISD::FMA:
2479 Res = WidenVecRes_Ternary(N);
2480 break;
2481 }
2482
2483 // If Res is null, the sub-method took care of registering the result.
2484 if (Res.getNode())
2485 SetWidenedVector(SDValue(N, ResNo), Res);
2486}
2487
2488SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2489 // Ternary op widening.
2490 SDLoc dl(N);
2491 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2492 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2493 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2494 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2495 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2496}
2497
2498SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2499 // Binary op widening.
2500 SDLoc dl(N);
2501 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2502 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2503 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2504 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2505}
2506
2507// Given a vector of operations that have been broken up to widen, see
2508// if we can collect them together into the next widest legal VT. This
2509// implementation is trap-safe.
2510static SDValue CollectOpsToWiden(SelectionDAG &DAG, const TargetLowering &TLI,
2511 SmallVectorImpl<SDValue> &ConcatOps,
2512 unsigned ConcatEnd, EVT VT, EVT MaxVT,
2513 EVT WidenVT) {
2514 // Check to see if we have a single operation with the widen type.
2515 if (ConcatEnd == 1) {
2516 VT = ConcatOps[0].getValueType();
2517 if (VT == WidenVT)
2518 return ConcatOps[0];
2519 }
2520
2521 SDLoc dl(ConcatOps[0]);
2522 EVT WidenEltVT = WidenVT.getVectorElementType();
2523 int Idx = 0;
2524
2525 // while (Some element of ConcatOps is not of type MaxVT) {
2526 // From the end of ConcatOps, collect elements of the same type and put
2527 // them into an op of the next larger supported type
2528 // }
2529 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2530 Idx = ConcatEnd - 1;
2531 VT = ConcatOps[Idx--].getValueType();
2532 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2533 Idx--;
2534
2535 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2536 EVT NextVT;
2537 do {
2538 NextSize *= 2;
2539 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2540 } while (!TLI.isTypeLegal(NextVT));
2541
2542 if (!VT.isVector()) {
2543 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2544 SDValue VecOp = DAG.getUNDEF(NextVT);
2545 unsigned NumToInsert = ConcatEnd - Idx - 1;
2546 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2547 VecOp = DAG.getNode(
2548 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx],
2549 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2550 }
2551 ConcatOps[Idx+1] = VecOp;
2552 ConcatEnd = Idx + 2;
2553 } else {
2554 // Vector type, create a CONCAT_VECTORS of type NextVT
2555 SDValue undefVec = DAG.getUNDEF(VT);
2556 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2557 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2558 unsigned RealVals = ConcatEnd - Idx - 1;
2559 unsigned SubConcatEnd = 0;
2560 unsigned SubConcatIdx = Idx + 1;
2561 while (SubConcatEnd < RealVals)
2562 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2563 while (SubConcatEnd < OpsToConcat)
2564 SubConcatOps[SubConcatEnd++] = undefVec;
2565 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2566 NextVT, SubConcatOps);
2567 ConcatEnd = SubConcatIdx + 1;
2568 }
2569 }
2570
2571 // Check to see if we have a single operation with the widen type.
2572 if (ConcatEnd == 1) {
2573 VT = ConcatOps[0].getValueType();
2574 if (VT == WidenVT)
2575 return ConcatOps[0];
2576 }
2577
2578 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2579 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2580 if (NumOps != ConcatEnd ) {
2581 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2582 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2583 ConcatOps[j] = UndefVal;
2584 }
2585 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2586 makeArrayRef(ConcatOps.data(), NumOps));
2587}
2588
2589SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2590 // Binary op widening for operations that can trap.
2591 unsigned Opcode = N->getOpcode();
2592 SDLoc dl(N);
2593 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2594 EVT WidenEltVT = WidenVT.getVectorElementType();
2595 EVT VT = WidenVT;
2596 unsigned NumElts = VT.getVectorNumElements();
2597 const SDNodeFlags Flags = N->getFlags();
2598 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2599 NumElts = NumElts / 2;
2600 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2601 }
2602
2603 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2604 // Operation doesn't trap so just widen as normal.
2605 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2606 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2607 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, Flags);
2608 }
2609
2610 // No legal vector version so unroll the vector operation and then widen.
2611 if (NumElts == 1)
2612 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2613
2614 // Since the operation can trap, apply operation on the original vector.
2615 EVT MaxVT = VT;
2616 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2617 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2618 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2619
2620 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2621 unsigned ConcatEnd = 0; // Current ConcatOps index.
2622 int Idx = 0; // Current Idx into input vectors.
2623
2624 // NumElts := greatest legal vector size (at most WidenVT)
2625 // while (orig. vector has unhandled elements) {
2626 // take munches of size NumElts from the beginning and add to ConcatOps
2627 // NumElts := next smaller supported vector size or 1
2628 // }
2629 while (CurNumElts != 0) {
2630 while (CurNumElts >= NumElts) {
2631 SDValue EOp1 = DAG.getNode(
2632 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2633 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2634 SDValue EOp2 = DAG.getNode(
2635 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2636 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2637 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2, Flags);
2638 Idx += NumElts;
2639 CurNumElts -= NumElts;
2640 }
2641 do {
2642 NumElts = NumElts / 2;
2643 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2644 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2645
2646 if (NumElts == 1) {
2647 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2648 SDValue EOp1 = DAG.getNode(
2649 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp1,
2650 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2651 SDValue EOp2 = DAG.getNode(
2652 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, InOp2,
2653 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2654 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2655 EOp1, EOp2, Flags);
2656 }
2657 CurNumElts = 0;
2658 }
2659 }
2660
2661 return CollectOpsToWiden(DAG, TLI, ConcatOps, ConcatEnd, VT, MaxVT, WidenVT);
2662}
2663
2664SDValue DAGTypeLegalizer::WidenVecRes_StrictFP(SDNode *N) {
2665 // StrictFP op widening for operations that can trap.
2666 unsigned NumOpers = N->getNumOperands();
2667 unsigned Opcode = N->getOpcode();
2668 SDLoc dl(N);
2669 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2670 EVT WidenEltVT = WidenVT.getVectorElementType();
2671 EVT VT = WidenVT;
2672 unsigned NumElts = VT.getVectorNumElements();
2673 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2674 NumElts = NumElts / 2;
2675 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2676 }
2677
2678 // No legal vector version so unroll the vector operation and then widen.
2679 if (NumElts == 1)
2680 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2681
2682 // Since the operation can trap, apply operation on the original vector.
2683 EVT MaxVT = VT;
2684 SmallVector<SDValue, 4> InOps;
2685 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2686
2687 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2688 SmallVector<SDValue, 16> Chains;
2689 unsigned ConcatEnd = 0; // Current ConcatOps index.
2690 int Idx = 0; // Current Idx into input vectors.
2691
2692 // The Chain is the first operand.
2693 InOps.push_back(N->getOperand(0));
2694
2695 // Now process the remaining operands.
2696 for (unsigned i = 1; i < NumOpers; ++i) {
2697 SDValue Oper = N->getOperand(i);
2698
2699 if (Oper.getValueType().isVector()) {
2700 assert(Oper.getValueType() == N->getValueType(0) &&((Oper.getValueType() == N->getValueType(0) && "Invalid operand type to widen!"
) ? static_cast<void> (0) : __assert_fail ("Oper.getValueType() == N->getValueType(0) && \"Invalid operand type to widen!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2701, __PRETTY_FUNCTION__))
2701 "Invalid operand type to widen!")((Oper.getValueType() == N->getValueType(0) && "Invalid operand type to widen!"
) ? static_cast<void> (0) : __assert_fail ("Oper.getValueType() == N->getValueType(0) && \"Invalid operand type to widen!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2701, __PRETTY_FUNCTION__))
;
2702 Oper = GetWidenedVector(Oper);
2703 }
2704
2705 InOps.push_back(Oper);
2706 }
2707
2708 // NumElts := greatest legal vector size (at most WidenVT)
2709 // while (orig. vector has unhandled elements) {
2710 // take munches of size NumElts from the beginning and add to ConcatOps
2711 // NumElts := next smaller supported vector size or 1
2712 // }
2713 while (CurNumElts != 0) {
2714 while (CurNumElts >= NumElts) {
2715 SmallVector<SDValue, 4> EOps;
2716
2717 for (unsigned i = 0; i < NumOpers; ++i) {
2718 SDValue Op = InOps[i];
2719
2720 if (Op.getValueType().isVector())
2721 Op = DAG.getNode(
2722 ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
2723 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
2724
2725 EOps.push_back(Op);
2726 }
2727
2728 EVT OperVT[] = {VT, MVT::Other};
2729 SDValue Oper = DAG.getNode(Opcode, dl, OperVT, EOps);
2730 ConcatOps[ConcatEnd++] = Oper;
2731 Chains.push_back(Oper.getValue(1));
2732 Idx += NumElts;
2733 CurNumElts -= NumElts;
2734 }
2735 do {
2736 NumElts = NumElts / 2;
2737 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2738 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2739
2740 if (NumElts == 1) {
2741 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2742 SmallVector<SDValue, 4> EOps;
2743
2744 for (unsigned i = 0; i < NumOpers; ++i) {
2745 SDValue Op = InOps[i];
2746
2747 if (Op.getValueType().isVector())
2748 Op = DAG.getNode(
2749 ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT, Op,
2750 DAG.getConstant(Idx, dl,
2751 TLI.getVectorIdxTy(DAG.getDataLayout())));
2752
2753 EOps.push_back(Op);
2754 }
2755
2756 EVT WidenVT[] = {WidenEltVT, MVT::Other};
2757 SDValue Oper = DAG.getNode(Opcode, dl, WidenVT, EOps);
2758 ConcatOps[ConcatEnd++] = Oper;
2759 Chains.push_back(Oper.getValue(1));
2760 }
2761 CurNumElts = 0;
2762 }
2763 }
2764
2765 // Build a factor node to remember all the Ops that have been created.
2766 SDValue NewChain;
2767 if (Chains.size() == 1)
2768 NewChain = Chains[0];
2769 else
2770 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
2771 ReplaceValueWith(SDValue(N, 1), NewChain);
2772
2773 return CollectOpsToWiden(DAG, TLI, ConcatOps, ConcatEnd, VT, MaxVT, WidenVT);
2774}
2775
2776SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2777 SDValue InOp = N->getOperand(0);
2778 SDLoc DL(N);
2779
2780 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2781 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2782
2783 EVT InVT = InOp.getValueType();
2784 EVT InEltVT = InVT.getVectorElementType();
2785 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2786
2787 unsigned Opcode = N->getOpcode();
2788 unsigned InVTNumElts = InVT.getVectorNumElements();
2789 const SDNodeFlags Flags = N->getFlags();
2790 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2791 InOp = GetWidenedVector(N->getOperand(0));
2792 InVT = InOp.getValueType();
2793 InVTNumElts = InVT.getVectorNumElements();
2794 if (InVTNumElts == WidenNumElts) {
2795 if (N->getNumOperands() == 1)
2796 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2797 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1), Flags);
2798 }
2799 if (WidenVT.getSizeInBits() == InVT.getSizeInBits()) {
2800 // If both input and result vector types are of same width, extend
2801 // operations should be done with SIGN/ZERO_EXTEND_VECTOR_INREG, which
2802 // accepts fewer elements in the result than in the input.
2803 if (Opcode == ISD::SIGN_EXTEND)
2804 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2805 if (Opcode == ISD::ZERO_EXTEND)
2806 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2807 }
2808 }
2809
2810 if (TLI.isTypeLegal(InWidenVT)) {
2811 // Because the result and the input are different vector types, widening
2812 // the result could create a legal type but widening the input might make
2813 // it an illegal type that might lead to repeatedly splitting the input
2814 // and then widening it. To avoid this, we widen the input only if
2815 // it results in a legal type.
2816 if (WidenNumElts % InVTNumElts == 0) {
2817 // Widen the input and call convert on the widened input vector.
2818 unsigned NumConcat = WidenNumElts/InVTNumElts;
2819 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
2820 Ops[0] = InOp;
2821 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2822 if (N->getNumOperands() == 1)
2823 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2824 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1), Flags);
2825 }
2826
2827 if (InVTNumElts % WidenNumElts == 0) {
2828 SDValue InVal = DAG.getNode(
2829 ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2830 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2831 // Extract the input and convert the shorten input vector.
2832 if (N->getNumOperands() == 1)
2833 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2834 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1), Flags);
2835 }
2836 }
2837
2838 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2839 EVT EltVT = WidenVT.getVectorElementType();
2840 SmallVector<SDValue, 16> Ops(WidenNumElts, DAG.getUNDEF(EltVT));
2841 // Use the original element count so we don't do more scalar opts than
2842 // necessary.
2843 unsigned MinElts = N->getValueType(0).getVectorNumElements();
2844 for (unsigned i=0; i < MinElts; ++i) {
2845 SDValue Val = DAG.getNode(
2846 ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2847 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2848 if (N->getNumOperands() == 1)
2849 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2850 else
2851 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1), Flags);
2852 }
2853
2854 return DAG.getBuildVector(WidenVT, DL, Ops);
2855}
2856
2857SDValue DAGTypeLegalizer::WidenVecRes_EXTEND_VECTOR_INREG(SDNode *N) {
2858 unsigned Opcode = N->getOpcode();
2859 SDValue InOp = N->getOperand(0);
2860 SDLoc DL(N);
2861
2862 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2863 EVT WidenSVT = WidenVT.getVectorElementType();
2864 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2865
2866 EVT InVT = InOp.getValueType();
2867 EVT InSVT = InVT.getVectorElementType();
2868 unsigned InVTNumElts = InVT.getVectorNumElements();
2869
2870 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2871 InOp = GetWidenedVector(InOp);
2872 InVT = InOp.getValueType();
2873 if (InVT.getSizeInBits() == WidenVT.getSizeInBits()) {
2874 switch (Opcode) {
2875 case ISD::ANY_EXTEND_VECTOR_INREG:
2876 return DAG.getAnyExtendVectorInReg(InOp, DL, WidenVT);
2877 case ISD::SIGN_EXTEND_VECTOR_INREG:
2878 return DAG.getSignExtendVectorInReg(InOp, DL, WidenVT);
2879 case ISD::ZERO_EXTEND_VECTOR_INREG:
2880 return DAG.getZeroExtendVectorInReg(InOp, DL, WidenVT);
2881 }
2882 }
2883 }
2884
2885 // Unroll, extend the scalars and rebuild the vector.
2886 SmallVector<SDValue, 16> Ops;
2887 for (unsigned i = 0, e = std::min(InVTNumElts, WidenNumElts); i != e; ++i) {
2888 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InSVT, InOp,
2889 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
2890 switch (Opcode) {
2891 case ISD::ANY_EXTEND_VECTOR_INREG:
2892 Val = DAG.getNode(ISD::ANY_EXTEND, DL, WidenSVT, Val);
2893 break;
2894 case ISD::SIGN_EXTEND_VECTOR_INREG:
2895 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val);
2896 break;
2897 case ISD::ZERO_EXTEND_VECTOR_INREG:
2898 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenSVT, Val);
2899 break;
2900 default:
2901 llvm_unreachable("A *_EXTEND_VECTOR_INREG node was expected")::llvm::llvm_unreachable_internal("A *_EXTEND_VECTOR_INREG node was expected"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 2901)
;
2902 }
2903 Ops.push_back(Val);
2904 }
2905
2906 while (Ops.size() != WidenNumElts)
2907 Ops.push_back(DAG.getUNDEF(WidenSVT));
2908
2909 return DAG.getBuildVector(WidenVT, DL, Ops);
2910}
2911
2912SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) {
2913 // If this is an FCOPYSIGN with same input types, we can treat it as a
2914 // normal (can trap) binary op.
2915 if (N->getOperand(0).getValueType() == N->getOperand(1).getValueType())
2916 return WidenVecRes_BinaryCanTrap(N);
2917
2918 // If the types are different, fall back to unrolling.
2919 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2920 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2921}
2922
2923SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2924 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2925 SDValue InOp = GetWidenedVector(N->getOperand(0));
2926 SDValue ShOp = N->getOperand(1);
2927 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2928}
2929
2930SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2931 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2932 SDValue InOp = GetWidenedVector(N->getOperand(0));
2933 SDValue ShOp = N->getOperand(1);
2934
2935 EVT ShVT = ShOp.getValueType();
2936 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2937 ShOp = GetWidenedVector(ShOp);
2938 ShVT = ShOp.getValueType();
2939 }
2940 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2941 ShVT.getVectorElementType(),
2942 WidenVT.getVectorNumElements());
2943 if (ShVT != ShWidenVT)
2944 ShOp = ModifyToType(ShOp, ShWidenVT);
2945
2946 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2947}
2948
2949SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2950 // Unary op widening.
2951 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2952 SDValue InOp = GetWidenedVector(N->getOperand(0));
2953 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2954}
2955
2956SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2957 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2958 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2959 cast<VTSDNode>(N->getOperand(1))->getVT()
2960 .getVectorElementType(),
2961 WidenVT.getVectorNumElements());
2962 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2963 return DAG.getNode(N->getOpcode(), SDLoc(N),
2964 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2965}
2966
2967SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2968 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2969 return GetWidenedVector(WidenVec);
2970}
2971
2972SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2973 SDValue InOp = N->getOperand(0);
2974 EVT InVT = InOp.getValueType();
2975 EVT VT = N->getValueType(0);
2976 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2977 SDLoc dl(N);
2978
2979 switch (getTypeAction(InVT)) {
2980 case TargetLowering::TypeLegal:
2981 break;
2982 case TargetLowering::TypePromoteInteger:
2983 // If the incoming type is a vector that is being promoted, then
2984 // we know that the elements are arranged differently and that we
2985 // must perform the conversion using a stack slot.
2986 if (InVT.isVector())
2987 break;
2988
2989 // If the InOp is promoted to the same size, convert it. Otherwise,
2990 // fall out of the switch and widen the promoted input.
2991 InOp = GetPromotedInteger(InOp);
2992 InVT = InOp.getValueType();
2993 if (WidenVT.bitsEq(InVT))
2994 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2995 break;
2996 case TargetLowering::TypeSoftenFloat:
2997 case TargetLowering::TypePromoteFloat:
2998 case TargetLowering::TypeExpandInteger:
2999 case TargetLowering::TypeExpandFloat:
3000 case TargetLowering::TypeScalarizeVector:
3001 case TargetLowering::TypeSplitVector:
3002 break;
3003 case TargetLowering::TypeWidenVector:
3004 // If the InOp is widened to the same size, convert it. Otherwise, fall
3005 // out of the switch and widen the widened input.
3006 InOp = GetWidenedVector(InOp);
3007 InVT = InOp.getValueType();
3008 if (WidenVT.bitsEq(InVT))
3009 // The input widens to the same size. Convert to the widen value.
3010 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
3011 break;
3012 }
3013
3014 unsigned WidenSize = WidenVT.getSizeInBits();
3015 unsigned InSize = InVT.getSizeInBits();
3016 // x86mmx is not an acceptable vector element type, so don't try.
3017 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
3018 // Determine new input vector type. The new input vector type will use
3019 // the same element type (if its a vector) or use the input type as a
3020 // vector. It is the same size as the type to widen to.
3021 EVT NewInVT;
3022 unsigned NewNumElts = WidenSize / InSize;
3023 if (InVT.isVector()) {
3024 EVT InEltVT = InVT.getVectorElementType();
3025 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
3026 WidenSize / InEltVT.getSizeInBits());
3027 } else {
3028 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
3029 }
3030
3031 if (TLI.isTypeLegal(NewInVT)) {
3032 SDValue NewVec;
3033 if (InVT.isVector()) {
3034 // Because the result and the input are different vector types, widening
3035 // the result could create a legal type but widening the input might make
3036 // it an illegal type that might lead to repeatedly splitting the input
3037 // and then widening it. To avoid this, we widen the input only if
3038 // it results in a legal type.
3039 SmallVector<SDValue, 16> Ops(NewNumElts, DAG.getUNDEF(InVT));
3040 Ops[0] = InOp;
3041
3042 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
3043 } else {
3044 NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp);
3045 }
3046 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
3047 }
3048 }
3049
3050 return CreateStackStoreLoad(InOp, WidenVT);
3051}
3052
3053SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
3054 SDLoc dl(N);
3055 // Build a vector with undefined for the new nodes.
3056 EVT VT = N->getValueType(0);
3057
3058 // Integer BUILD_VECTOR operands may be larger than the node's vector element
3059 // type. The UNDEFs need to have the same type as the existing operands.
3060 EVT EltVT = N->getOperand(0).getValueType();
3061 unsigned NumElts = VT.getVectorNumElements();
3062
3063 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3064 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3065
3066 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
3067 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!")((WidenNumElts >= NumElts && "Shrinking vector instead of widening!"
) ? static_cast<void> (0) : __assert_fail ("WidenNumElts >= NumElts && \"Shrinking vector instead of widening!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3067, __PRETTY_FUNCTION__))
;
3068 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
3069
3070 return DAG.getBuildVector(WidenVT, dl, NewOps);
3071}
3072
3073SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
3074 EVT InVT = N->getOperand(0).getValueType();
3075 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3076 SDLoc dl(N);
3077 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3078 unsigned NumInElts = InVT.getVectorNumElements();
3079 unsigned NumOperands = N->getNumOperands();
3080
3081 bool InputWidened = false; // Indicates we need to widen the input.
3082 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
3083 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
3084 // Add undef vectors to widen to correct length.
3085 unsigned NumConcat = WidenVT.getVectorNumElements() /
3086 InVT.getVectorNumElements();
3087 SDValue UndefVal = DAG.getUNDEF(InVT);
3088 SmallVector<SDValue, 16> Ops(NumConcat);
3089 for (unsigned i=0; i < NumOperands; ++i)
3090 Ops[i] = N->getOperand(i);
3091 for (unsigned i = NumOperands; i != NumConcat; ++i)
3092 Ops[i] = UndefVal;
3093 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
3094 }
3095 } else {
3096 InputWidened = true;
3097 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
3098 // The inputs and the result are widen to the same value.
3099 unsigned i;
3100 for (i=1; i < NumOperands; ++i)
3101 if (!N->getOperand(i).isUndef())
3102 break;
3103
3104 if (i == NumOperands)
3105 // Everything but the first operand is an UNDEF so just return the
3106 // widened first operand.
3107 return GetWidenedVector(N->getOperand(0));
3108
3109 if (NumOperands == 2) {
3110 // Replace concat of two operands with a shuffle.
3111 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
3112 for (unsigned i = 0; i < NumInElts; ++i) {
3113 MaskOps[i] = i;
3114 MaskOps[i + NumInElts] = i + WidenNumElts;
3115 }
3116 return DAG.getVectorShuffle(WidenVT, dl,
3117 GetWidenedVector(N->getOperand(0)),
3118 GetWidenedVector(N->getOperand(1)),
3119 MaskOps);
3120 }
3121 }
3122 }
3123
3124 // Fall back to use extracts and build vector.
3125 EVT EltVT = WidenVT.getVectorElementType();
3126 SmallVector<SDValue, 16> Ops(WidenNumElts);
3127 unsigned Idx = 0;
3128 for (unsigned i=0; i < NumOperands; ++i) {
3129 SDValue InOp = N->getOperand(i);
3130 if (InputWidened)
3131 InOp = GetWidenedVector(InOp);
3132 for (unsigned j=0; j < NumInElts; ++j)
3133 Ops[Idx++] = DAG.getNode(
3134 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3135 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3136 }
3137 SDValue UndefVal = DAG.getUNDEF(EltVT);
3138 for (; Idx < WidenNumElts; ++Idx)
3139 Ops[Idx] = UndefVal;
3140 return DAG.getBuildVector(WidenVT, dl, Ops);
3141}
3142
3143SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
3144 EVT VT = N->getValueType(0);
3145 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3146 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3147 SDValue InOp = N->getOperand(0);
3148 SDValue Idx = N->getOperand(1);
3149 SDLoc dl(N);
3150
3151 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
3152 InOp = GetWidenedVector(InOp);
3153
3154 EVT InVT = InOp.getValueType();
3155
3156 // Check if we can just return the input vector after widening.
3157 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
3158 if (IdxVal == 0 && InVT == WidenVT)
3159 return InOp;
3160
3161 // Check if we can extract from the vector.
3162 unsigned InNumElts = InVT.getVectorNumElements();
3163 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
3164 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
3165
3166 // We could try widening the input to the right length but for now, extract
3167 // the original elements, fill the rest with undefs and build a vector.
3168 SmallVector<SDValue, 16> Ops(WidenNumElts);
3169 EVT EltVT = VT.getVectorElementType();
3170 unsigned NumElts = VT.getVectorNumElements();
3171 unsigned i;
3172 for (i=0; i < NumElts; ++i)
3173 Ops[i] =
3174 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3175 DAG.getConstant(IdxVal + i, dl,
3176 TLI.getVectorIdxTy(DAG.getDataLayout())));
3177
3178 SDValue UndefVal = DAG.getUNDEF(EltVT);
3179 for (; i < WidenNumElts; ++i)
3180 Ops[i] = UndefVal;
3181 return DAG.getBuildVector(WidenVT, dl, Ops);
3182}
3183
3184SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
3185 SDValue InOp = GetWidenedVector(N->getOperand(0));
3186 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
3187 InOp.getValueType(), InOp,
3188 N->getOperand(1), N->getOperand(2));
3189}
3190
3191SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
3192 LoadSDNode *LD = cast<LoadSDNode>(N);
3193 ISD::LoadExtType ExtType = LD->getExtensionType();
3194
3195 SDValue Result;
3196 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
3197 if (ExtType != ISD::NON_EXTLOAD)
3198 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
3199 else
3200 Result = GenWidenVectorLoads(LdChain, LD);
3201
3202 // If we generate a single load, we can use that for the chain. Otherwise,
3203 // build a factor node to remember the multiple loads are independent and
3204 // chain to that.
3205 SDValue NewChain;
3206 if (LdChain.size() == 1)
3207 NewChain = LdChain[0];
3208 else
3209 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
3210
3211 // Modified the chain - switch anything that used the old chain to use
3212 // the new one.
3213 ReplaceValueWith(SDValue(N, 1), NewChain);
3214
3215 return Result;
3216}
3217
3218SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
3219
3220 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
3221 SDValue Mask = N->getMask();
3222 EVT MaskVT = Mask.getValueType();
3223 SDValue PassThru = GetWidenedVector(N->getPassThru());
3224 ISD::LoadExtType ExtType = N->getExtensionType();
3225 SDLoc dl(N);
3226
3227 // The mask should be widened as well
3228 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3229 MaskVT.getVectorElementType(),
3230 WidenVT.getVectorNumElements());
3231 Mask = ModifyToType(Mask, WideMaskVT, true);
3232
3233 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
3234 Mask, PassThru, N->getMemoryVT(),
3235 N->getMemOperand(), ExtType,
3236 N->isExpandingLoad());
3237 // Legalize the chain result - switch anything that used the old chain to
3238 // use the new one.
3239 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3240 return Res;
3241}
3242
3243SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
3244
3245 EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3246 SDValue Mask = N->getMask();
3247 EVT MaskVT = Mask.getValueType();
3248 SDValue PassThru = GetWidenedVector(N->getPassThru());
3249 SDValue Scale = N->getScale();
3250 unsigned NumElts = WideVT.getVectorNumElements();
3251 SDLoc dl(N);
3252
3253 // The mask should be widened as well
3254 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3255 MaskVT.getVectorElementType(),
3256 WideVT.getVectorNumElements());
3257 Mask = ModifyToType(Mask, WideMaskVT, true);
3258
3259 // Widen the Index operand
3260 SDValue Index = N->getIndex();
3261 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3262 Index.getValueType().getScalarType(),
3263 NumElts);
3264 Index = ModifyToType(Index, WideIndexVT);
3265 SDValue Ops[] = { N->getChain(), PassThru, Mask, N->getBasePtr(), Index,
3266 Scale };
3267 SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
3268 N->getMemoryVT(), dl, Ops,
3269 N->getMemOperand());
3270
3271 // Legalize the chain result - switch anything that used the old chain to
3272 // use the new one.
3273 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3274 return Res;
3275}
3276
3277SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
3278 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3279 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
3280 WidenVT, N->getOperand(0));
3281}
3282
3283// Return true if this is a node that could have two SETCCs as operands.
3284static inline bool isLogicalMaskOp(unsigned Opcode) {
3285 switch (Opcode) {
3286 case ISD::AND:
3287 case ISD::OR:
3288 case ISD::XOR:
3289 return true;
3290 }
3291 return false;
3292}
3293
3294// This is used just for the assert in convertMask(). Check that this either
3295// a SETCC or a previously handled SETCC by convertMask().
3296#ifndef NDEBUG
3297static inline bool isSETCCorConvertedSETCC(SDValue N) {
3298 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
3299 N = N.getOperand(0);
3300 else if (N.getOpcode() == ISD::CONCAT_VECTORS) {
3301 for (unsigned i = 1; i < N->getNumOperands(); ++i)
3302 if (!N->getOperand(i)->isUndef())
3303 return false;
3304 N = N.getOperand(0);
3305 }
3306
3307 if (N.getOpcode() == ISD::TRUNCATE)
3308 N = N.getOperand(0);
3309 else if (N.getOpcode() == ISD::SIGN_EXTEND)
3310 N = N.getOperand(0);
3311
3312 if (isLogicalMaskOp(N.getOpcode()))
3313 return isSETCCorConvertedSETCC(N.getOperand(0)) &&
3314 isSETCCorConvertedSETCC(N.getOperand(1));
3315
3316 return (N.getOpcode() == ISD::SETCC ||
3317 ISD::isBuildVectorOfConstantSDNodes(N.getNode()));
3318}
3319#endif
3320
3321// Return a mask of vector type MaskVT to replace InMask. Also adjust MaskVT
3322// to ToMaskVT if needed with vector extension or truncation.
3323SDValue DAGTypeLegalizer::convertMask(SDValue InMask, EVT MaskVT,
3324 EVT ToMaskVT) {
3325 // Currently a SETCC or a AND/OR/XOR with two SETCCs are handled.
3326 // FIXME: This code seems to be too restrictive, we might consider
3327 // generalizing it or dropping it.
3328 assert(isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument.")((isSETCCorConvertedSETCC(InMask) && "Unexpected mask argument."
) ? static_cast<void> (0) : __assert_fail ("isSETCCorConvertedSETCC(InMask) && \"Unexpected mask argument.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3328, __PRETTY_FUNCTION__))
;
3329
3330 // Make a new Mask node, with a legal result VT.
3331 SmallVector<SDValue, 4> Ops;
3332 for (unsigned i = 0, e = InMask->getNumOperands(); i < e; ++i)
3333 Ops.push_back(InMask->getOperand(i));
3334 SDValue Mask = DAG.getNode(InMask->getOpcode(), SDLoc(InMask), MaskVT, Ops);
3335
3336 // If MaskVT has smaller or bigger elements than ToMaskVT, a vector sign
3337 // extend or truncate is needed.
3338 LLVMContext &Ctx = *DAG.getContext();
3339 unsigned MaskScalarBits = MaskVT.getScalarSizeInBits();
3340 unsigned ToMaskScalBits = ToMaskVT.getScalarSizeInBits();
3341 if (MaskScalarBits < ToMaskScalBits) {
3342 EVT ExtVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3343 MaskVT.getVectorNumElements());
3344 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask);
3345 } else if (MaskScalarBits > ToMaskScalBits) {
3346 EVT TruncVT = EVT::getVectorVT(Ctx, ToMaskVT.getVectorElementType(),
3347 MaskVT.getVectorNumElements());
3348 Mask = DAG.getNode(ISD::TRUNCATE, SDLoc(Mask), TruncVT, Mask);
3349 }
3350
3351 assert(Mask->getValueType(0).getScalarSizeInBits() ==((Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.
getScalarSizeInBits() && "Mask should have the right element size by now."
) ? static_cast<void> (0) : __assert_fail ("Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.getScalarSizeInBits() && \"Mask should have the right element size by now.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3353, __PRETTY_FUNCTION__))
3352 ToMaskVT.getScalarSizeInBits() &&((Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.
getScalarSizeInBits() && "Mask should have the right element size by now."
) ? static_cast<void> (0) : __assert_fail ("Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.getScalarSizeInBits() && \"Mask should have the right element size by now.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3353, __PRETTY_FUNCTION__))
3353 "Mask should have the right element size by now.")((Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.
getScalarSizeInBits() && "Mask should have the right element size by now."
) ? static_cast<void> (0) : __assert_fail ("Mask->getValueType(0).getScalarSizeInBits() == ToMaskVT.getScalarSizeInBits() && \"Mask should have the right element size by now.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3353, __PRETTY_FUNCTION__))
;
3354
3355 // Adjust Mask to the right number of elements.
3356 unsigned CurrMaskNumEls = Mask->getValueType(0).getVectorNumElements();
3357 if (CurrMaskNumEls > ToMaskVT.getVectorNumElements()) {
3358 MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
3359 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy);
3360 Mask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Mask), ToMaskVT, Mask,
3361 ZeroIdx);
3362 } else if (CurrMaskNumEls < ToMaskVT.getVectorNumElements()) {
3363 unsigned NumSubVecs = (ToMaskVT.getVectorNumElements() / CurrMaskNumEls);
3364 EVT SubVT = Mask->getValueType(0);
3365 SmallVector<SDValue, 16> SubOps(NumSubVecs, DAG.getUNDEF(SubVT));
3366 SubOps[0] = Mask;
3367 Mask = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Mask), ToMaskVT, SubOps);
3368 }
3369
3370 assert((Mask->getValueType(0) == ToMaskVT) &&(((Mask->getValueType(0) == ToMaskVT) && "A mask of ToMaskVT should have been produced by now."
) ? static_cast<void> (0) : __assert_fail ("(Mask->getValueType(0) == ToMaskVT) && \"A mask of ToMaskVT should have been produced by now.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3371, __PRETTY_FUNCTION__))
3371 "A mask of ToMaskVT should have been produced by now.")(((Mask->getValueType(0) == ToMaskVT) && "A mask of ToMaskVT should have been produced by now."
) ? static_cast<void> (0) : __assert_fail ("(Mask->getValueType(0) == ToMaskVT) && \"A mask of ToMaskVT should have been produced by now.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3371, __PRETTY_FUNCTION__))
;
3372
3373 return Mask;
3374}
3375
3376// This method tries to handle VSELECT and its mask by legalizing operands
3377// (which may require widening) and if needed adjusting the mask vector type
3378// to match that of the VSELECT. Without it, many cases end up with
3379// scalarization of the SETCC, with many unnecessary instructions.
3380SDValue DAGTypeLegalizer::WidenVSELECTAndMask(SDNode *N) {
3381 LLVMContext &Ctx = *DAG.getContext();
3382 SDValue Cond = N->getOperand(0);
3383
3384 if (N->getOpcode() != ISD::VSELECT)
3385 return SDValue();
3386
3387 if (Cond->getOpcode() != ISD::SETCC && !isLogicalMaskOp(Cond->getOpcode()))
3388 return SDValue();
3389
3390 // If this is a splitted VSELECT that was previously already handled, do
3391 // nothing.
3392 EVT CondVT = Cond->getValueType(0);
3393 if (CondVT.getScalarSizeInBits() != 1)
3394 return SDValue();
3395
3396 EVT VSelVT = N->getValueType(0);
3397 // Only handle vector types which are a power of 2.
3398 if (!isPowerOf2_64(VSelVT.getSizeInBits()))
3399 return SDValue();
3400
3401 // Don't touch if this will be scalarized.
3402 EVT FinalVT = VSelVT;
3403 while (getTypeAction(FinalVT) == TargetLowering::TypeSplitVector)
3404 FinalVT = FinalVT.getHalfNumVectorElementsVT(Ctx);
3405
3406 if (FinalVT.getVectorNumElements() == 1)
3407 return SDValue();
3408
3409 // If there is support for an i1 vector mask, don't touch.
3410 if (Cond.getOpcode() == ISD::SETCC) {
3411 EVT SetCCOpVT = Cond->getOperand(0).getValueType();
3412 while (TLI.getTypeAction(Ctx, SetCCOpVT) != TargetLowering::TypeLegal)
3413 SetCCOpVT = TLI.getTypeToTransformTo(Ctx, SetCCOpVT);
3414 EVT SetCCResVT = getSetCCResultType(SetCCOpVT);
3415 if (SetCCResVT.getScalarSizeInBits() == 1)
3416 return SDValue();
3417 } else if (CondVT.getScalarType() == MVT::i1) {
3418 // If there is support for an i1 vector mask (or only scalar i1 conditions),
3419 // don't touch.
3420 while (TLI.getTypeAction(Ctx, CondVT) != TargetLowering::TypeLegal)
3421 CondVT = TLI.getTypeToTransformTo(Ctx, CondVT);
3422
3423 if (CondVT.getScalarType() == MVT::i1)
3424 return SDValue();
3425 }
3426
3427 // Get the VT and operands for VSELECT, and widen if needed.
3428 SDValue VSelOp1 = N->getOperand(1);
3429 SDValue VSelOp2 = N->getOperand(2);
3430 if (getTypeAction(VSelVT) == TargetLowering::TypeWidenVector) {
3431 VSelVT = TLI.getTypeToTransformTo(Ctx, VSelVT);
3432 VSelOp1 = GetWidenedVector(VSelOp1);
3433 VSelOp2 = GetWidenedVector(VSelOp2);
3434 }
3435
3436 // The mask of the VSELECT should have integer elements.
3437 EVT ToMaskVT = VSelVT;
3438 if (!ToMaskVT.getScalarType().isInteger())
3439 ToMaskVT = ToMaskVT.changeVectorElementTypeToInteger();
3440
3441 SDValue Mask;
3442 if (Cond->getOpcode() == ISD::SETCC) {
3443 EVT MaskVT = getSetCCResultType(Cond.getOperand(0).getValueType());
3444 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3445 } else if (isLogicalMaskOp(Cond->getOpcode()) &&
3446 Cond->getOperand(0).getOpcode() == ISD::SETCC &&
3447 Cond->getOperand(1).getOpcode() == ISD::SETCC) {
3448 // Cond is (AND/OR/XOR (SETCC, SETCC))
3449 SDValue SETCC0 = Cond->getOperand(0);
3450 SDValue SETCC1 = Cond->getOperand(1);
3451 EVT VT0 = getSetCCResultType(SETCC0.getOperand(0).getValueType());
3452 EVT VT1 = getSetCCResultType(SETCC1.getOperand(0).getValueType());
3453 unsigned ScalarBits0 = VT0.getScalarSizeInBits();
3454 unsigned ScalarBits1 = VT1.getScalarSizeInBits();
3455 unsigned ScalarBits_ToMask = ToMaskVT.getScalarSizeInBits();
3456 EVT MaskVT;
3457 // If the two SETCCs have different VTs, either extend/truncate one of
3458 // them to the other "towards" ToMaskVT, or truncate one and extend the
3459 // other to ToMaskVT.
3460 if (ScalarBits0 != ScalarBits1) {
3461 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1);
3462 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0);
3463 if (ScalarBits_ToMask >= WideVT.getScalarSizeInBits())
3464 MaskVT = WideVT;
3465 else if (ScalarBits_ToMask <= NarrowVT.getScalarSizeInBits())
3466 MaskVT = NarrowVT;
3467 else
3468 MaskVT = ToMaskVT;
3469 } else
3470 // If the two SETCCs have the same VT, don't change it.
3471 MaskVT = VT0;
3472
3473 // Make new SETCCs and logical nodes.
3474 SETCC0 = convertMask(SETCC0, VT0, MaskVT);
3475 SETCC1 = convertMask(SETCC1, VT1, MaskVT);
3476 Cond = DAG.getNode(Cond->getOpcode(), SDLoc(Cond), MaskVT, SETCC0, SETCC1);
3477
3478 // Convert the logical op for VSELECT if needed.
3479 Mask = convertMask(Cond, MaskVT, ToMaskVT);
3480 } else
3481 return SDValue();
3482
3483 return DAG.getNode(ISD::VSELECT, SDLoc(N), VSelVT, Mask, VSelOp1, VSelOp2);
3484}
3485
3486SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
3487 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3488 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3489
3490 SDValue Cond1 = N->getOperand(0);
3491 EVT CondVT = Cond1.getValueType();
3492 if (CondVT.isVector()) {
3493 if (SDValue Res = WidenVSELECTAndMask(N))
3494 return Res;
3495
3496 EVT CondEltVT = CondVT.getVectorElementType();
3497 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
3498 CondEltVT, WidenNumElts);
3499 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
3500 Cond1 = GetWidenedVector(Cond1);
3501
3502 // If we have to split the condition there is no point in widening the
3503 // select. This would result in an cycle of widening the select ->
3504 // widening the condition operand -> splitting the condition operand ->
3505 // splitting the select -> widening the select. Instead split this select
3506 // further and widen the resulting type.
3507 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
3508 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
3509 SDValue Res = ModifyToType(SplitSelect, WidenVT);
3510 return Res;
3511 }
3512
3513 if (Cond1.getValueType() != CondWidenVT)
3514 Cond1 = ModifyToType(Cond1, CondWidenVT);
3515 }
3516
3517 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3518 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
3519 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT)((InOp1.getValueType() == WidenVT && InOp2.getValueType
() == WidenVT) ? static_cast<void> (0) : __assert_fail (
"InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3519, __PRETTY_FUNCTION__))
;
3520 return DAG.getNode(N->getOpcode(), SDLoc(N),
3521 WidenVT, Cond1, InOp1, InOp2);
3522}
3523
3524SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
3525 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
3526 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
3527 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
3528 InOp1.getValueType(), N->getOperand(0),
3529 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
3530}
3531
3532SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
3533 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3534 return DAG.getUNDEF(WidenVT);
3535}
3536
3537SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
3538 EVT VT = N->getValueType(0);
3539 SDLoc dl(N);
3540
3541 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
3542 unsigned NumElts = VT.getVectorNumElements();
3543 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3544
3545 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
3546 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3547
3548 // Adjust mask based on new input vector length.
3549 SmallVector<int, 16> NewMask;
3550 for (unsigned i = 0; i != NumElts; ++i) {
3551 int Idx = N->getMaskElt(i);
3552 if (Idx < (int)NumElts)
3553 NewMask.push_back(Idx);
3554 else
3555 NewMask.push_back(Idx - NumElts + WidenNumElts);
3556 }
3557 for (unsigned i = NumElts; i != WidenNumElts; ++i)
3558 NewMask.push_back(-1);
3559 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, NewMask);
3560}
3561
3562SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
3563 assert(N->getValueType(0).isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operands must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operands must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3565, __PRETTY_FUNCTION__))
3564 N->getOperand(0).getValueType().isVector() &&((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operands must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operands must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3565, __PRETTY_FUNCTION__))
3565 "Operands must be vectors")((N->getValueType(0).isVector() && N->getOperand
(0).getValueType().isVector() && "Operands must be vectors"
) ? static_cast<void> (0) : __assert_fail ("N->getValueType(0).isVector() && N->getOperand(0).getValueType().isVector() && \"Operands must be vectors\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3565, __PRETTY_FUNCTION__))
;
3566 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
3567 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3568
3569 SDValue InOp1 = N->getOperand(0);
3570 EVT InVT = InOp1.getValueType();
3571 assert(InVT.isVector() && "can not widen non-vector type")((InVT.isVector() && "can not widen non-vector type")
? static_cast<void> (0) : __assert_fail ("InVT.isVector() && \"can not widen non-vector type\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3571, __PRETTY_FUNCTION__))
;
3572 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
3573 InVT.getVectorElementType(), WidenNumElts);
3574
3575 // The input and output types often differ here, and it could be that while
3576 // we'd prefer to widen the result type, the input operands have been split.
3577 // In this case, we also need to split the result of this node as well.
3578 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
3579 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
3580 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
3581 return Res;
3582 }
3583
3584 InOp1 = GetWidenedVector(InOp1);
3585 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
3586
3587 // Assume that the input and output will be widen appropriately. If not,
3588 // we will have to unroll it at some point.
3589 assert(InOp1.getValueType() == WidenInVT &&((InOp1.getValueType() == WidenInVT && InOp2.getValueType
() == WidenInVT && "Input not widened to expected type!"
) ? static_cast<void> (0) : __assert_fail ("InOp1.getValueType() == WidenInVT && InOp2.getValueType() == WidenInVT && \"Input not widened to expected type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3591, __PRETTY_FUNCTION__))
3590 InOp2.getValueType() == WidenInVT &&((InOp1.getValueType() == WidenInVT && InOp2.getValueType
() == WidenInVT && "Input not widened to expected type!"
) ? static_cast<void> (0) : __assert_fail ("InOp1.getValueType() == WidenInVT && InOp2.getValueType() == WidenInVT && \"Input not widened to expected type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3591, __PRETTY_FUNCTION__))
3591 "Input not widened to expected type!")((InOp1.getValueType() == WidenInVT && InOp2.getValueType
() == WidenInVT && "Input not widened to expected type!"
) ? static_cast<void> (0) : __assert_fail ("InOp1.getValueType() == WidenInVT && InOp2.getValueType() == WidenInVT && \"Input not widened to expected type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3591, __PRETTY_FUNCTION__))
;
3592 (void)WidenInVT;
3593 return DAG.getNode(ISD::SETCC, SDLoc(N),
3594 WidenVT, InOp1, InOp2, N->getOperand(2));
3595}
3596
3597
3598//===----------------------------------------------------------------------===//
3599// Widen Vector Operand
3600//===----------------------------------------------------------------------===//
3601bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
3602 LLVM_DEBUG(dbgs() << "Widen node operand " << OpNo << ": "; N->dump(&DAG);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node operand " <<
OpNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
3603 dbgs() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("legalize-types")) { dbgs() << "Widen node operand " <<
OpNo << ": "; N->dump(&DAG); dbgs() << "\n"
; } } while (false)
;
3604 SDValue Res = SDValue();
3605
3606 // See if the target wants to custom widen this node.
3607 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1
Assuming the condition is false
2
Taking false branch
3608 return false;
3609
3610 switch (N->getOpcode()) {
3
Control jumps to 'case MSTORE:' at line 3624
3611 default:
3612#ifndef NDEBUG
3613 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
3614 N->dump(&DAG);
3615 dbgs() << "\n";
3616#endif
3617 llvm_unreachable("Do not know how to widen this operator's operand!")::llvm::llvm_unreachable_internal("Do not know how to widen this operator's operand!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3617)
;
3618
3619 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
3620 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
3621 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
3622 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
3623 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
3624 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
4
Calling 'DAGTypeLegalizer::WidenVecOp_MSTORE'
3625 case ISD::MGATHER: Res = WidenVecOp_MGATHER(N, OpNo); break;
3626 case ISD::MSCATTER: Res = WidenVecOp_MSCATTER(N, OpNo); break;
3627 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
3628 case ISD::FCOPYSIGN: Res = WidenVecOp_FCOPYSIGN(N); break;
3629
3630 case ISD::ANY_EXTEND:
3631 case ISD::SIGN_EXTEND:
3632 case ISD::ZERO_EXTEND:
3633 Res = WidenVecOp_EXTEND(N);
3634 break;
3635
3636 case ISD::FP_EXTEND:
3637 case ISD::FP_TO_SINT:
3638 case ISD::FP_TO_UINT:
3639 case ISD::SINT_TO_FP:
3640 case ISD::UINT_TO_FP:
3641 case ISD::TRUNCATE:
3642 Res = WidenVecOp_Convert(N);
3643 break;
3644 }
3645
3646 // If Res is null, the sub-method took care of registering the result.
3647 if (!Res.getNode()) return false;
3648
3649 // If the result is N, the sub-method updated N in place. Tell the legalizer
3650 // core about this.
3651 if (Res.getNode() == N)
3652 return true;
3653
3654
3655 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3656, __PRETTY_FUNCTION__))
3656 "Invalid operand expansion")((Res.getValueType() == N->getValueType(0) && N->
getNumValues() == 1 && "Invalid operand expansion") ?
static_cast<void> (0) : __assert_fail ("Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 && \"Invalid operand expansion\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3656, __PRETTY_FUNCTION__))
;
3657
3658 ReplaceValueWith(SDValue(N, 0), Res);
3659 return false;
3660}
3661
3662SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
3663 SDLoc DL(N);
3664 EVT VT = N->getValueType(0);
3665
3666 SDValue InOp = N->getOperand(0);
3667 assert(getTypeAction(InOp.getValueType()) ==((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3669, __PRETTY_FUNCTION__))
3668 TargetLowering::TypeWidenVector &&((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3669, __PRETTY_FUNCTION__))
3669 "Unexpected type action")((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3669, __PRETTY_FUNCTION__))
;
3670 InOp = GetWidenedVector(InOp);
3671 assert(VT.getVectorNumElements() <((VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements
() && "Input wasn't widened!") ? static_cast<void>
(0) : __assert_fail ("VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements() && \"Input wasn't widened!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3673, __PRETTY_FUNCTION__))
3672 InOp.getValueType().getVectorNumElements() &&((VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements
() && "Input wasn't widened!") ? static_cast<void>
(0) : __assert_fail ("VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements() && \"Input wasn't widened!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3673, __PRETTY_FUNCTION__))
3673 "Input wasn't widened!")((VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements
() && "Input wasn't widened!") ? static_cast<void>
(0) : __assert_fail ("VT.getVectorNumElements() < InOp.getValueType().getVectorNumElements() && \"Input wasn't widened!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3673, __PRETTY_FUNCTION__))
;
3674
3675 // We may need to further widen the operand until it has the same total
3676 // vector size as the result.
3677 EVT InVT = InOp.getValueType();
3678 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
3679 EVT InEltVT = InVT.getVectorElementType();
3680 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
3681 EVT FixedVT = (MVT::SimpleValueType)i;
3682 EVT FixedEltVT = FixedVT.getVectorElementType();
3683 if (TLI.isTypeLegal(FixedVT) &&
3684 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
3685 FixedEltVT == InEltVT) {
3686 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&((FixedVT.getVectorNumElements() >= VT.getVectorNumElements
() && "Not enough elements in the fixed type for the operand!"
) ? static_cast<void> (0) : __assert_fail ("FixedVT.getVectorNumElements() >= VT.getVectorNumElements() && \"Not enough elements in the fixed type for the operand!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3687, __PRETTY_FUNCTION__))
3687 "Not enough elements in the fixed type for the operand!")((FixedVT.getVectorNumElements() >= VT.getVectorNumElements
() && "Not enough elements in the fixed type for the operand!"
) ? static_cast<void> (0) : __assert_fail ("FixedVT.getVectorNumElements() >= VT.getVectorNumElements() && \"Not enough elements in the fixed type for the operand!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3687, __PRETTY_FUNCTION__))
;
3688 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&((FixedVT.getVectorNumElements() != InVT.getVectorNumElements
() && "We can't have the same type as we started with!"
) ? static_cast<void> (0) : __assert_fail ("FixedVT.getVectorNumElements() != InVT.getVectorNumElements() && \"We can't have the same type as we started with!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3689, __PRETTY_FUNCTION__))
3689 "We can't have the same type as we started with!")((FixedVT.getVectorNumElements() != InVT.getVectorNumElements
() && "We can't have the same type as we started with!"
) ? static_cast<void> (0) : __assert_fail ("FixedVT.getVectorNumElements() != InVT.getVectorNumElements() && \"We can't have the same type as we started with!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3689, __PRETTY_FUNCTION__))
;
3690 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
3691 InOp = DAG.getNode(
3692 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp,
3693 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3694 else
3695 InOp = DAG.getNode(
3696 ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
3697 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
3698 break;
3699 }
3700 }
3701 InVT = InOp.getValueType();
3702 if (InVT.getSizeInBits() != VT.getSizeInBits())
3703 // We couldn't find a legal vector type that was a widening of the input
3704 // and could be extended in-register to the result type, so we have to
3705 // scalarize.
3706 return WidenVecOp_Convert(N);
3707 }
3708
3709 // Use special DAG nodes to represent the operation of extending the
3710 // low lanes.
3711 switch (N->getOpcode()) {
3712 default:
3713 llvm_unreachable("Extend legalization on extend operation!")::llvm::llvm_unreachable_internal("Extend legalization on extend operation!"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3713)
;
3714 case ISD::ANY_EXTEND:
3715 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
3716 case ISD::SIGN_EXTEND:
3717 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
3718 case ISD::ZERO_EXTEND:
3719 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
3720 }
3721}
3722
3723SDValue DAGTypeLegalizer::WidenVecOp_FCOPYSIGN(SDNode *N) {
3724 // The result (and first input) is legal, but the second input is illegal.
3725 // We can't do much to fix that, so just unroll and let the extracts off of
3726 // the second input be widened as needed later.
3727 return DAG.UnrollVectorOp(N);
3728}
3729
3730SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
3731 // Since the result is legal and the input is illegal.
3732 EVT VT = N->getValueType(0);
3733 EVT EltVT = VT.getVectorElementType();
3734 SDLoc dl(N);
3735 unsigned NumElts = VT.getVectorNumElements();
3736 SDValue InOp = N->getOperand(0);
3737 assert(getTypeAction(InOp.getValueType()) ==((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3739, __PRETTY_FUNCTION__))
3738 TargetLowering::TypeWidenVector &&((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3739, __PRETTY_FUNCTION__))
3739 "Unexpected type action")((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3739, __PRETTY_FUNCTION__))
;
3740 InOp = GetWidenedVector(InOp);
3741 EVT InVT = InOp.getValueType();
3742 unsigned Opcode = N->getOpcode();
3743
3744 // See if a widened result type would be legal, if so widen the node.
3745 EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT,
3746 InVT.getVectorNumElements());
3747 if (TLI.isTypeLegal(WideVT)) {
3748 SDValue Res = DAG.getNode(Opcode, dl, WideVT, InOp);
3749 return DAG.getNode(
3750 ISD::EXTRACT_SUBVECTOR, dl, VT, Res,
3751 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3752 }
3753
3754 EVT InEltVT = InVT.getVectorElementType();
3755
3756 // Unroll the convert into some scalar code and create a nasty build vector.
3757 SmallVector<SDValue, 16> Ops(NumElts);
3758 for (unsigned i=0; i < NumElts; ++i)
3759 Ops[i] = DAG.getNode(
3760 Opcode, dl, EltVT,
3761 DAG.getNode(
3762 ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
3763 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3764
3765 return DAG.getBuildVector(VT, dl, Ops);
3766}
3767
3768SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
3769 EVT VT = N->getValueType(0);
3770 SDValue InOp = GetWidenedVector(N->getOperand(0));
3771 EVT InWidenVT = InOp.getValueType();
3772 SDLoc dl(N);
3773
3774 // Check if we can convert between two legal vector types and extract.
3775 unsigned InWidenSize = InWidenVT.getSizeInBits();
3776 unsigned Size = VT.getSizeInBits();
3777 // x86mmx is not an acceptable vector element type, so don't try.
3778 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
3779 unsigned NewNumElts = InWidenSize / Size;
3780 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
3781 if (TLI.isTypeLegal(NewVT)) {
3782 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
3783 return DAG.getNode(
3784 ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
3785 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3786 }
3787 }
3788
3789 return CreateStackStoreLoad(InOp, VT);
3790}
3791
3792SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
3793 EVT VT = N->getValueType(0);
3794 EVT EltVT = VT.getVectorElementType();
3795 EVT InVT = N->getOperand(0).getValueType();
3796 SDLoc dl(N);
3797
3798 // If the widen width for this operand is the same as the width of the concat
3799 // and all but the first operand is undef, just use the widened operand.
3800 unsigned NumOperands = N->getNumOperands();
3801 if (VT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
3802 unsigned i;
3803 for (i = 1; i < NumOperands; ++i)
3804 if (!N->getOperand(i).isUndef())
3805 break;
3806
3807 if (i == NumOperands)
3808 return GetWidenedVector(N->getOperand(0));
3809 }
3810
3811 // Otherwise, fall back to a nasty build vector.
3812 unsigned NumElts = VT.getVectorNumElements();
3813 SmallVector<SDValue, 16> Ops(NumElts);
3814
3815 unsigned NumInElts = InVT.getVectorNumElements();
3816
3817 unsigned Idx = 0;
3818 for (unsigned i=0; i < NumOperands; ++i) {
3819 SDValue InOp = N->getOperand(i);
3820 assert(getTypeAction(InOp.getValueType()) ==((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3822, __PRETTY_FUNCTION__))
3821 TargetLowering::TypeWidenVector &&((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3822, __PRETTY_FUNCTION__))
3822 "Unexpected type action")((getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector
&& "Unexpected type action") ? static_cast<void>
(0) : __assert_fail ("getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector && \"Unexpected type action\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3822, __PRETTY_FUNCTION__))
;
3823 InOp = GetWidenedVector(InOp);
3824 for (unsigned j=0; j < NumInElts; ++j)
3825 Ops[Idx++] = DAG.getNode(
3826 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3827 DAG.getConstant(j, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3828 }
3829 return DAG.getBuildVector(VT, dl, Ops);
3830}
3831
3832SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
3833 SDValue InOp = GetWidenedVector(N->getOperand(0));
3834 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
3835 N->getValueType(0), InOp, N->getOperand(1));
3836}
3837
3838SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3839 SDValue InOp = GetWidenedVector(N->getOperand(0));
3840 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
3841 N->getValueType(0), InOp, N->getOperand(1));
3842}
3843
3844SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
3845 // We have to widen the value, but we want only to store the original
3846 // vector type.
3847 StoreSDNode *ST = cast<StoreSDNode>(N);
3848
3849 if (!ST->getMemoryVT().getScalarType().isByteSized())
3850 return TLI.scalarizeVectorStore(ST, DAG);
3851
3852 SmallVector<SDValue, 16> StChain;
3853 if (ST->isTruncatingStore())
3854 GenWidenVectorTruncStores(StChain, ST);
3855 else
3856 GenWidenVectorStores(StChain, ST);
3857
3858 if (StChain.size() == 1)
3859 return StChain[0];
3860 else
3861 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3862}
3863
3864SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3865 assert((OpNo == 1 || OpNo == 3) &&(((OpNo == 1 || OpNo == 3) && "Can widen only data or mask operand of mstore"
) ? static_cast<void> (0) : __assert_fail ("(OpNo == 1 || OpNo == 3) && \"Can widen only data or mask operand of mstore\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3866, __PRETTY_FUNCTION__))
3866 "Can widen only data or mask operand of mstore")(((OpNo == 1 || OpNo == 3) && "Can widen only data or mask operand of mstore"
) ? static_cast<void> (0) : __assert_fail ("(OpNo == 1 || OpNo == 3) && \"Can widen only data or mask operand of mstore\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3866, __PRETTY_FUNCTION__))
;
3867 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3868 SDValue Mask = MST->getMask();
3869 EVT MaskVT = Mask.getValueType();
3870 SDValue StVal = MST->getValue();
3871 SDLoc dl(N);
3872
3873 if (OpNo == 1) {
5
Taking false branch
3874 // Widen the value.
3875 StVal = GetWidenedVector(StVal);
3876
3877 // The mask should be widened as well.
3878 EVT WideVT = StVal.getValueType();
3879 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3880 MaskVT.getVectorElementType(),
3881 WideVT.getVectorNumElements());
3882 Mask = ModifyToType(Mask, WideMaskVT, true);
3883 } else {
3884 // Widen the mask.
3885 EVT WideMaskVT = TLI.getTypeToTransformTo(*DAG.getContext(), MaskVT);
3886 Mask = ModifyToType(Mask, WideMaskVT, true);
6
Calling 'DAGTypeLegalizer::ModifyToType'
3887
3888 EVT ValueVT = StVal.getValueType();
3889 EVT WideVT = EVT::getVectorVT(*DAG.getContext(),
3890 ValueVT.getVectorElementType(),
3891 WideMaskVT.getVectorNumElements());
3892 StVal = ModifyToType(StVal, WideVT);
3893 }
3894
3895 assert(Mask.getValueType().getVectorNumElements() ==((Mask.getValueType().getVectorNumElements() == StVal.getValueType
().getVectorNumElements() && "Mask and data vectors should have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("Mask.getValueType().getVectorNumElements() == StVal.getValueType().getVectorNumElements() && \"Mask and data vectors should have the same number of elements\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3897, __PRETTY_FUNCTION__))
3896 StVal.getValueType().getVectorNumElements() &&((Mask.getValueType().getVectorNumElements() == StVal.getValueType
().getVectorNumElements() && "Mask and data vectors should have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("Mask.getValueType().getVectorNumElements() == StVal.getValueType().getVectorNumElements() && \"Mask and data vectors should have the same number of elements\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3897, __PRETTY_FUNCTION__))
3897 "Mask and data vectors should have the same number of elements")((Mask.getValueType().getVectorNumElements() == StVal.getValueType
().getVectorNumElements() && "Mask and data vectors should have the same number of elements"
) ? static_cast<void> (0) : __assert_fail ("Mask.getValueType().getVectorNumElements() == StVal.getValueType().getVectorNumElements() && \"Mask and data vectors should have the same number of elements\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3897, __PRETTY_FUNCTION__))
;
3898 return DAG.getMaskedStore(MST->getChain(), dl, StVal, MST->getBasePtr(),
3899 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3900 false, MST->isCompressingStore());
3901}
3902
3903SDValue DAGTypeLegalizer::WidenVecOp_MGATHER(SDNode *N, unsigned OpNo) {
3904 assert(OpNo == 4 && "Can widen only the index of mgather")((OpNo == 4 && "Can widen only the index of mgather")
? static_cast<void> (0) : __assert_fail ("OpNo == 4 && \"Can widen only the index of mgather\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3904, __PRETTY_FUNCTION__))
;
3905 auto *MG = cast<MaskedGatherSDNode>(N);
3906 SDValue DataOp = MG->getPassThru();
3907 SDValue Mask = MG->getMask();
3908 SDValue Scale = MG->getScale();
3909
3910 // Just widen the index. It's allowed to have extra elements.
3911 SDValue Index = GetWidenedVector(MG->getIndex());
3912
3913 SDLoc dl(N);
3914 SDValue Ops[] = {MG->getChain(), DataOp, Mask, MG->getBasePtr(), Index,
3915 Scale};
3916 SDValue Res = DAG.getMaskedGather(MG->getVTList(), MG->getMemoryVT(), dl, Ops,
3917 MG->getMemOperand());
3918 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
3919 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
3920 return SDValue();
3921}
3922
3923SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
3924 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
3925 SDValue DataOp = MSC->getValue();
3926 SDValue Mask = MSC->getMask();
3927 SDValue Index = MSC->getIndex();
3928 SDValue Scale = MSC->getScale();
3929
3930 unsigned NumElts;
3931 if (OpNo == 1) {
3932 DataOp = GetWidenedVector(DataOp);
3933 NumElts = DataOp.getValueType().getVectorNumElements();
3934
3935 // Widen index.
3936 EVT IndexVT = Index.getValueType();
3937 EVT WideIndexVT = EVT::getVectorVT(*DAG.getContext(),
3938 IndexVT.getVectorElementType(), NumElts);
3939 Index = ModifyToType(Index, WideIndexVT);
3940
3941 // The mask should be widened as well.
3942 EVT MaskVT = Mask.getValueType();
3943 EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
3944 MaskVT.getVectorElementType(), NumElts);
3945 Mask = ModifyToType(Mask, WideMaskVT, true);
3946 } else if (OpNo == 4) {
3947 // Just widen the index. It's allowed to have extra elements.
3948 Index = GetWidenedVector(Index);
3949 } else
3950 llvm_unreachable("Can't widen this operand of mscatter")::llvm::llvm_unreachable_internal("Can't widen this operand of mscatter"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 3950)
;
3951
3952 SDValue Ops[] = {MSC->getChain(), DataOp, Mask, MSC->getBasePtr(), Index,
3953 Scale};
3954 return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
3955 MSC->getMemoryVT(), SDLoc(N), Ops,
3956 MSC->getMemOperand());
3957}
3958
3959SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3960 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3961 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3962 SDLoc dl(N);
3963 EVT VT = N->getValueType(0);
3964
3965 // WARNING: In this code we widen the compare instruction with garbage.
3966 // This garbage may contain denormal floats which may be slow. Is this a real
3967 // concern ? Should we zero the unused lanes if this is a float compare ?
3968
3969 // Get a new SETCC node to compare the newly widened operands.
3970 // Only some of the compared elements are legal.
3971 EVT SVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
3972 InOp0.getValueType());
3973 // The result type is legal, if its vXi1, keep vXi1 for the new SETCC.
3974 if (VT.getScalarType() == MVT::i1)
3975 SVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
3976 SVT.getVectorNumElements());
3977
3978 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3979 SVT, InOp0, InOp1, N->getOperand(2));
3980
3981 // Extract the needed results from the result vector.
3982 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3983 SVT.getVectorElementType(),
3984 VT.getVectorNumElements());
3985 SDValue CC = DAG.getNode(
3986 ISD::EXTRACT_SUBVECTOR, dl, ResVT, WideSETCC,
3987 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3988
3989 return PromoteTargetBoolean(CC, VT);
3990}
3991
3992
3993//===----------------------------------------------------------------------===//
3994// Vector Widening Utilities
3995//===----------------------------------------------------------------------===//
3996
3997// Utility function to find the type to chop up a widen vector for load/store
3998// TLI: Target lowering used to determine legal types.
3999// Width: Width left need to load/store.
4000// WidenVT: The widen vector type to load to/store from
4001// Align: If 0, don't allow use of a wider type
4002// WidenEx: If Align is not 0, the amount additional we can load/store from.
4003
4004static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
4005 unsigned Width, EVT WidenVT,
4006 unsigned Align = 0, unsigned WidenEx = 0) {
4007 EVT WidenEltVT = WidenVT.getVectorElementType();
4008 unsigned WidenWidth = WidenVT.getSizeInBits();
4009 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
4010 unsigned AlignInBits = Align*8;
4011
4012 // If we have one element to load/store, return it.
4013 EVT RetVT = WidenEltVT;
4014 if (Width == WidenEltWidth)
4015 return RetVT;
4016
4017 // See if there is larger legal integer than the element type to load/store.
4018 unsigned VT;
4019 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
4020 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
4021 EVT MemVT((MVT::SimpleValueType) VT);
4022 unsigned MemVTWidth = MemVT.getSizeInBits();
4023 if (MemVT.getSizeInBits() <= WidenEltWidth)
4024 break;
4025 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
4026 if ((Action == TargetLowering::TypeLegal ||
4027 Action == TargetLowering::TypePromoteInteger) &&
4028 (WidenWidth % MemVTWidth) == 0 &&
4029 isPowerOf2_32(WidenWidth / MemVTWidth) &&
4030 (MemVTWidth <= Width ||
4031 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
4032 RetVT = MemVT;
4033 break;
4034 }
4035 }
4036
4037 // See if there is a larger vector type to load/store that has the same vector
4038 // element type and is evenly divisible with the WidenVT.
4039 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
4040 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
4041 EVT MemVT = (MVT::SimpleValueType) VT;
4042 unsigned MemVTWidth = MemVT.getSizeInBits();
4043 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
4044 (WidenWidth % MemVTWidth) == 0 &&
4045 isPowerOf2_32(WidenWidth / MemVTWidth) &&
4046 (MemVTWidth <= Width ||
4047 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
4048 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
4049 return MemVT;
4050 }
4051 }
4052
4053 return RetVT;
4054}
4055
4056// Builds a vector type from scalar loads
4057// VecTy: Resulting Vector type
4058// LDOps: Load operators to build a vector type
4059// [Start,End) the list of loads to use.
4060static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
4061 SmallVectorImpl<SDValue> &LdOps,
4062 unsigned Start, unsigned End) {
4063 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4064 SDLoc dl(LdOps[Start]);
4065 EVT LdTy = LdOps[Start].getValueType();
4066 unsigned Width = VecTy.getSizeInBits();
4067 unsigned NumElts = Width / LdTy.getSizeInBits();
4068 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
4069
4070 unsigned Idx = 1;
4071 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
4072
4073 for (unsigned i = Start + 1; i != End; ++i) {
4074 EVT NewLdTy = LdOps[i].getValueType();
4075 if (NewLdTy != LdTy) {
4076 NumElts = Width / NewLdTy.getSizeInBits();
4077 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
4078 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
4079 // Readjust position and vector position based on new load type.
4080 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
4081 LdTy = NewLdTy;
4082 }
4083 VecOp = DAG.getNode(
4084 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
4085 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4086 }
4087 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
4088}
4089
4090SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
4091 LoadSDNode *LD) {
4092 // The strategy assumes that we can efficiently load power-of-two widths.
4093 // The routine chops the vector into the largest vector loads with the same
4094 // element type or scalar loads and then recombines it to the widen vector
4095 // type.
4096 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
4097 unsigned WidenWidth = WidenVT.getSizeInBits();
4098 EVT LdVT = LD->getMemoryVT();
4099 SDLoc dl(LD);
4100 assert(LdVT.isVector() && WidenVT.isVector())((LdVT.isVector() && WidenVT.isVector()) ? static_cast
<void> (0) : __assert_fail ("LdVT.isVector() && WidenVT.isVector()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4100, __PRETTY_FUNCTION__))
;
4101 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType())((LdVT.getVectorElementType() == WidenVT.getVectorElementType
()) ? static_cast<void> (0) : __assert_fail ("LdVT.getVectorElementType() == WidenVT.getVectorElementType()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4101, __PRETTY_FUNCTION__))
;
4102
4103 // Load information
4104 SDValue Chain = LD->getChain();
4105 SDValue BasePtr = LD->getBasePtr();
4106 unsigned Align = LD->getAlignment();
4107 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
4108 AAMDNodes AAInfo = LD->getAAInfo();
4109
4110 int LdWidth = LdVT.getSizeInBits();
4111 int WidthDiff = WidenWidth - LdWidth;
4112 unsigned LdAlign = LD->isVolatile() ? 0 : Align; // Allow wider loads.
4113
4114 // Find the vector type that can load from.
4115 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
4116 int NewVTWidth = NewVT.getSizeInBits();
4117 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
4118 Align, MMOFlags, AAInfo);
4119 LdChain.push_back(LdOp.getValue(1));
4120
4121 // Check if we can load the element with one instruction.
4122 if (LdWidth <= NewVTWidth) {
4123 if (!NewVT.isVector()) {
4124 unsigned NumElts = WidenWidth / NewVTWidth;
4125 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
4126 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
4127 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
4128 }
4129 if (NewVT == WidenVT)
4130 return LdOp;
4131
4132 assert(WidenWidth % NewVTWidth == 0)((WidenWidth % NewVTWidth == 0) ? static_cast<void> (0)
: __assert_fail ("WidenWidth % NewVTWidth == 0", "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4132, __PRETTY_FUNCTION__))
;
4133 unsigned NumConcat = WidenWidth / NewVTWidth;
4134 SmallVector<SDValue, 16> ConcatOps(NumConcat);
4135 SDValue UndefVal = DAG.getUNDEF(NewVT);
4136 ConcatOps[0] = LdOp;
4137 for (unsigned i = 1; i != NumConcat; ++i)
4138 ConcatOps[i] = UndefVal;
4139 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
4140 }
4141
4142 // Load vector by using multiple loads from largest vector to scalar.
4143 SmallVector<SDValue, 16> LdOps;
4144 LdOps.push_back(LdOp);
4145
4146 LdWidth -= NewVTWidth;
4147 unsigned Offset = 0;
4148
4149 while (LdWidth > 0) {
4150 unsigned Increment = NewVTWidth / 8;
4151 Offset += Increment;
4152 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4153
4154 SDValue L;
4155 if (LdWidth < NewVTWidth) {
4156 // The current type we are using is too large. Find a better size.
4157 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
4158 NewVTWidth = NewVT.getSizeInBits();
4159 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
4160 LD->getPointerInfo().getWithOffset(Offset),
4161 MinAlign(Align, Increment), MMOFlags, AAInfo);
4162 LdChain.push_back(L.getValue(1));
4163 if (L->getValueType(0).isVector() && NewVTWidth >= LdWidth) {
4164 // Later code assumes the vector loads produced will be mergeable, so we
4165 // must pad the final entry up to the previous width. Scalars are
4166 // combined separately.
4167 SmallVector<SDValue, 16> Loads;
4168 Loads.push_back(L);
4169 unsigned size = L->getValueSizeInBits(0);
4170 while (size < LdOp->getValueSizeInBits(0)) {
4171 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
4172 size += L->getValueSizeInBits(0);
4173 }
4174 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
4175 }
4176 } else {
4177 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
4178 LD->getPointerInfo().getWithOffset(Offset),
4179 MinAlign(Align, Increment), MMOFlags, AAInfo);
4180 LdChain.push_back(L.getValue(1));
4181 }
4182
4183 LdOps.push_back(L);
4184 LdOp = L;
4185
4186 LdWidth -= NewVTWidth;
4187 }
4188
4189 // Build the vector from the load operations.
4190 unsigned End = LdOps.size();
4191 if (!LdOps[0].getValueType().isVector())
4192 // All the loads are scalar loads.
4193 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
4194
4195 // If the load contains vectors, build the vector using concat vector.
4196 // All of the vectors used to load are power-of-2, and the scalar loads can be
4197 // combined to make a power-of-2 vector.
4198 SmallVector<SDValue, 16> ConcatOps(End);
4199 int i = End - 1;
4200 int Idx = End;
4201 EVT LdTy = LdOps[i].getValueType();
4202 // First, combine the scalar loads to a vector.
4203 if (!LdTy.isVector()) {
4204 for (--i; i >= 0; --i) {
4205 LdTy = LdOps[i].getValueType();
4206 if (LdTy.isVector())
4207 break;
4208 }
4209 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i + 1, End);
4210 }
4211 ConcatOps[--Idx] = LdOps[i];
4212 for (--i; i >= 0; --i) {
4213 EVT NewLdTy = LdOps[i].getValueType();
4214 if (NewLdTy != LdTy) {
4215 // Create a larger vector.
4216 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
4217 makeArrayRef(&ConcatOps[Idx], End - Idx));
4218 Idx = End - 1;
4219 LdTy = NewLdTy;
4220 }
4221 ConcatOps[--Idx] = LdOps[i];
4222 }
4223
4224 if (WidenWidth == LdTy.getSizeInBits() * (End - Idx))
4225 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
4226 makeArrayRef(&ConcatOps[Idx], End - Idx));
4227
4228 // We need to fill the rest with undefs to build the vector.
4229 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
4230 SmallVector<SDValue, 16> WidenOps(NumOps);
4231 SDValue UndefVal = DAG.getUNDEF(LdTy);
4232 {
4233 unsigned i = 0;
4234 for (; i != End-Idx; ++i)
4235 WidenOps[i] = ConcatOps[Idx+i];
4236 for (; i != NumOps; ++i)
4237 WidenOps[i] = UndefVal;
4238 }
4239 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
4240}
4241
4242SDValue
4243DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
4244 LoadSDNode *LD,
4245 ISD::LoadExtType ExtType) {
4246 // For extension loads, it may not be more efficient to chop up the vector
4247 // and then extend it. Instead, we unroll the load and build a new vector.
4248 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
4249 EVT LdVT = LD->getMemoryVT();
4250 SDLoc dl(LD);
4251 assert(LdVT.isVector() && WidenVT.isVector())((LdVT.isVector() && WidenVT.isVector()) ? static_cast
<void> (0) : __assert_fail ("LdVT.isVector() && WidenVT.isVector()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4251, __PRETTY_FUNCTION__))
;
4252
4253 // Load information
4254 SDValue Chain = LD->getChain();
4255 SDValue BasePtr = LD->getBasePtr();
4256 unsigned Align = LD->getAlignment();
4257 MachineMemOperand::Flags MMOFlags = LD->getMemOperand()->getFlags();
4258 AAMDNodes AAInfo = LD->getAAInfo();
4259
4260 EVT EltVT = WidenVT.getVectorElementType();
4261 EVT LdEltVT = LdVT.getVectorElementType();
4262 unsigned NumElts = LdVT.getVectorNumElements();
4263
4264 // Load each element and widen.
4265 unsigned WidenNumElts = WidenVT.getVectorNumElements();
4266 SmallVector<SDValue, 16> Ops(WidenNumElts);
4267 unsigned Increment = LdEltVT.getSizeInBits() / 8;
4268 Ops[0] =
4269 DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, LD->getPointerInfo(),
4270 LdEltVT, Align, MMOFlags, AAInfo);
4271 LdChain.push_back(Ops[0].getValue(1));
4272 unsigned i = 0, Offset = Increment;
4273 for (i=1; i < NumElts; ++i, Offset += Increment) {
4274 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4275 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
4276 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
4277 Align, MMOFlags, AAInfo);
4278 LdChain.push_back(Ops[i].getValue(1));
4279 }
4280
4281 // Fill the rest with undefs.
4282 SDValue UndefVal = DAG.getUNDEF(EltVT);
4283 for (; i != WidenNumElts; ++i)
4284 Ops[i] = UndefVal;
4285
4286 return DAG.getBuildVector(WidenVT, dl, Ops);
4287}
4288
4289void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
4290 StoreSDNode *ST) {
4291 // The strategy assumes that we can efficiently store power-of-two widths.
4292 // The routine chops the vector into the largest vector stores with the same
4293 // element type or scalar stores.
4294 SDValue Chain = ST->getChain();
4295 SDValue BasePtr = ST->getBasePtr();
4296 unsigned Align = ST->getAlignment();
4297 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
4298 AAMDNodes AAInfo = ST->getAAInfo();
4299 SDValue ValOp = GetWidenedVector(ST->getValue());
4300 SDLoc dl(ST);
4301
4302 EVT StVT = ST->getMemoryVT();
4303 unsigned StWidth = StVT.getSizeInBits();
4304 EVT ValVT = ValOp.getValueType();
4305 unsigned ValWidth = ValVT.getSizeInBits();
4306 EVT ValEltVT = ValVT.getVectorElementType();
4307 unsigned ValEltWidth = ValEltVT.getSizeInBits();
4308 assert(StVT.getVectorElementType() == ValEltVT)((StVT.getVectorElementType() == ValEltVT) ? static_cast<void
> (0) : __assert_fail ("StVT.getVectorElementType() == ValEltVT"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4308, __PRETTY_FUNCTION__))
;
4309
4310 int Idx = 0; // current index to store
4311 unsigned Offset = 0; // offset from base to store
4312 while (StWidth != 0) {
4313 // Find the largest vector type we can store with.
4314 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
4315 unsigned NewVTWidth = NewVT.getSizeInBits();
4316 unsigned Increment = NewVTWidth / 8;
4317 if (NewVT.isVector()) {
4318 unsigned NumVTElts = NewVT.getVectorNumElements();
4319 do {
4320 SDValue EOp = DAG.getNode(
4321 ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
4322 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4323 StChain.push_back(DAG.getStore(
4324 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
4325 MinAlign(Align, Offset), MMOFlags, AAInfo));
4326 StWidth -= NewVTWidth;
4327 Offset += Increment;
4328 Idx += NumVTElts;
4329
4330 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4331 } while (StWidth != 0 && StWidth >= NewVTWidth);
4332 } else {
4333 // Cast the vector to the scalar type we can store.
4334 unsigned NumElts = ValWidth / NewVTWidth;
4335 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
4336 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
4337 // Readjust index position based on new vector type.
4338 Idx = Idx * ValEltWidth / NewVTWidth;
4339 do {
4340 SDValue EOp = DAG.getNode(
4341 ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
4342 DAG.getConstant(Idx++, dl,
4343 TLI.getVectorIdxTy(DAG.getDataLayout())));
4344 StChain.push_back(DAG.getStore(
4345 Chain, dl, EOp, BasePtr, ST->getPointerInfo().getWithOffset(Offset),
4346 MinAlign(Align, Offset), MMOFlags, AAInfo));
4347 StWidth -= NewVTWidth;
4348 Offset += Increment;
4349 BasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Increment);
4350 } while (StWidth != 0 && StWidth >= NewVTWidth);
4351 // Restore index back to be relative to the original widen element type.
4352 Idx = Idx * NewVTWidth / ValEltWidth;
4353 }
4354 }
4355}
4356
4357void
4358DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
4359 StoreSDNode *ST) {
4360 // For extension loads, it may not be more efficient to truncate the vector
4361 // and then store it. Instead, we extract each element and then store it.
4362 SDValue Chain = ST->getChain();
4363 SDValue BasePtr = ST->getBasePtr();
4364 unsigned Align = ST->getAlignment();
4365 MachineMemOperand::Flags MMOFlags = ST->getMemOperand()->getFlags();
4366 AAMDNodes AAInfo = ST->getAAInfo();
4367 SDValue ValOp = GetWidenedVector(ST->getValue());
4368 SDLoc dl(ST);
4369
4370 EVT StVT = ST->getMemoryVT();
4371 EVT ValVT = ValOp.getValueType();
4372
4373 // It must be true that the wide vector type is bigger than where we need to
4374 // store.
4375 assert(StVT.isVector() && ValOp.getValueType().isVector())((StVT.isVector() && ValOp.getValueType().isVector())
? static_cast<void> (0) : __assert_fail ("StVT.isVector() && ValOp.getValueType().isVector()"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4375, __PRETTY_FUNCTION__))
;
4376 assert(StVT.bitsLT(ValOp.getValueType()))((StVT.bitsLT(ValOp.getValueType())) ? static_cast<void>
(0) : __assert_fail ("StVT.bitsLT(ValOp.getValueType())", "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4376, __PRETTY_FUNCTION__))
;
4377
4378 // For truncating stores, we can not play the tricks of chopping legal vector
4379 // types and bitcast it to the right type. Instead, we unroll the store.
4380 EVT StEltVT = StVT.getVectorElementType();
4381 EVT ValEltVT = ValVT.getVectorElementType();
4382 unsigned Increment = ValEltVT.getSizeInBits() / 8;
4383 unsigned NumElts = StVT.getVectorNumElements();
4384 SDValue EOp = DAG.getNode(
4385 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4386 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4387 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
4388 ST->getPointerInfo(), StEltVT, Align,
4389 MMOFlags, AAInfo));
4390 unsigned Offset = Increment;
4391 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
4392 SDValue NewBasePtr = DAG.getObjectPtrOffset(dl, BasePtr, Offset);
4393 SDValue EOp = DAG.getNode(
4394 ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
4395 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4396 StChain.push_back(DAG.getTruncStore(
4397 Chain, dl, EOp, NewBasePtr, ST->getPointerInfo().getWithOffset(Offset),
4398 StEltVT, MinAlign(Align, Offset), MMOFlags, AAInfo));
4399 }
4400}
4401
4402/// Modifies a vector input (widen or narrows) to a vector of NVT. The
4403/// input vector must have the same element type as NVT.
4404/// FillWithZeroes specifies that the vector should be widened with zeroes.
4405SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT,
4406 bool FillWithZeroes) {
4407 // Note that InOp might have been widened so it might already have
4408 // the right width or it might need be narrowed.
4409 EVT InVT = InOp.getValueType();
4410 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&((InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match") ? static_cast<
void> (0) : __assert_fail ("InVT.getVectorElementType() == NVT.getVectorElementType() && \"input and widen element type must match\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4411, __PRETTY_FUNCTION__))
4411 "input and widen element type must match")((InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match") ? static_cast<
void> (0) : __assert_fail ("InVT.getVectorElementType() == NVT.getVectorElementType() && \"input and widen element type must match\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp"
, 4411, __PRETTY_FUNCTION__))
;
4412 SDLoc dl(InOp);
4413
4414 // Check if InOp already has the right width.
4415 if (InVT == NVT)
7
Taking false branch
4416 return InOp;
4417
4418 unsigned InNumElts = InVT.getVectorNumElements();
8
Calling 'EVT::getVectorNumElements'
12
Returning from 'EVT::getVectorNumElements'
13
'InNumElts' initialized here
4419 unsigned WidenNumElts = NVT.getVectorNumElements();
4420 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
14
Assuming 'WidenNumElts' is > 'InNumElts'
15
Division by zero
4421 unsigned NumConcat = WidenNumElts / InNumElts;
4422 SmallVector<SDValue, 16> Ops(NumConcat);
4423 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, InVT) :
4424 DAG.getUNDEF(InVT);
4425 Ops[0] = InOp;
4426 for (unsigned i = 1; i != NumConcat; ++i)
4427 Ops[i] = FillVal;
4428
4429 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
4430 }
4431
4432 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
4433 return DAG.getNode(
4434 ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
4435 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4436
4437 // Fall back to extract and build.
4438 SmallVector<SDValue, 16> Ops(WidenNumElts);
4439 EVT EltVT = NVT.getVectorElementType();
4440 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
4441 unsigned Idx;
4442 for (Idx = 0; Idx < MinNumElts; ++Idx)
4443 Ops[Idx] = DAG.getNode(
4444 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
4445 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
4446
4447 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
4448 DAG.getUNDEF(EltVT);
4449 for ( ; Idx < WidenNumElts; ++Idx)
4450 Ops[Idx] = FillVal;
4451 return DAG.getBuildVector(NVT, dl, Ops);
4452}

/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h

1//===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the set of low-level target independent types which various
11// values in the code generator are. This allows the target specific behavior
12// of instructions to be described to target independent passes.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef LLVM_CODEGEN_VALUETYPES_H
17#define LLVM_CODEGEN_VALUETYPES_H
18
19#include "llvm/Support/Compiler.h"
20#include "llvm/Support/MachineValueType.h"
21#include "llvm/Support/MathExtras.h"
22#include <cassert>
23#include <cstdint>
24#include <string>
25
26namespace llvm {
27
28 class LLVMContext;
29 class Type;
30
31 /// Extended Value Type. Capable of holding value types which are not native
32 /// for any processor (such as the i12345 type), as well as the types an MVT
33 /// can represent.
34 struct EVT {
35 private:
36 MVT V = MVT::INVALID_SIMPLE_VALUE_TYPE;
37 Type *LLVMTy = nullptr;
38
39 public:
40 constexpr EVT() = default;
41 constexpr EVT(MVT::SimpleValueType SVT) : V(SVT) {}
42 constexpr EVT(MVT S) : V(S) {}
43
44 bool operator==(EVT VT) const {
45 return !(*this != VT);
46 }
47 bool operator!=(EVT VT) const {
48 if (V.SimpleTy != VT.V.SimpleTy)
49 return true;
50 if (V.SimpleTy == MVT::INVALID_SIMPLE_VALUE_TYPE)
51 return LLVMTy != VT.LLVMTy;
52 return false;
53 }
54
55 /// Returns the EVT that represents a floating-point type with the given
56 /// number of bits. There are two floating-point types with 128 bits - this
57 /// returns f128 rather than ppcf128.
58 static EVT getFloatingPointVT(unsigned BitWidth) {
59 return MVT::getFloatingPointVT(BitWidth);
60 }
61
62 /// Returns the EVT that represents an integer with the given number of
63 /// bits.
64 static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth) {
65 MVT M = MVT::getIntegerVT(BitWidth);
66 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
67 return M;
68 return getExtendedIntegerVT(Context, BitWidth);
69 }
70
71 /// Returns the EVT that represents a vector NumElements in length, where
72 /// each element is of type VT.
73 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements,
74 bool IsScalable = false) {
75 MVT M = MVT::getVectorVT(VT.V, NumElements, IsScalable);
76 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
77 return M;
78
79 assert(!IsScalable && "We don't support extended scalable types yet")((!IsScalable && "We don't support extended scalable types yet"
) ? static_cast<void> (0) : __assert_fail ("!IsScalable && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 79, __PRETTY_FUNCTION__))
;
80 return getExtendedVectorVT(Context, VT, NumElements);
81 }
82
83 /// Returns the EVT that represents a vector EC.Min elements in length,
84 /// where each element is of type VT.
85 static EVT getVectorVT(LLVMContext &Context, EVT VT, MVT::ElementCount EC) {
86 MVT M = MVT::getVectorVT(VT.V, EC);
87 if (M.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE)
88 return M;
89 assert (!EC.Scalable && "We don't support extended scalable types yet")((!EC.Scalable && "We don't support extended scalable types yet"
) ? static_cast<void> (0) : __assert_fail ("!EC.Scalable && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 89, __PRETTY_FUNCTION__))
;
90 return getExtendedVectorVT(Context, VT, EC.Min);
91 }
92
93 /// Return a vector with the same number of elements as this vector, but
94 /// with the element type converted to an integer type with the same
95 /// bitwidth.
96 EVT changeVectorElementTypeToInteger() const {
97 if (!isSimple()) {
98 assert (!isScalableVector() &&((!isScalableVector() && "We don't support extended scalable types yet"
) ? static_cast<void> (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 99, __PRETTY_FUNCTION__))
99 "We don't support extended scalable types yet")((!isScalableVector() && "We don't support extended scalable types yet"
) ? static_cast<void> (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 99, __PRETTY_FUNCTION__))
;
100 return changeExtendedVectorElementTypeToInteger();
101 }
102 MVT EltTy = getSimpleVT().getVectorElementType();
103 unsigned BitWidth = EltTy.getSizeInBits();
104 MVT IntTy = MVT::getIntegerVT(BitWidth);
105 MVT VecTy = MVT::getVectorVT(IntTy, getVectorNumElements(),
106 isScalableVector());
107 assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 108, __PRETTY_FUNCTION__))
108 "Simple vector VT not representable by simple integer vector VT!")((VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!"
) ? static_cast<void> (0) : __assert_fail ("VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE && \"Simple vector VT not representable by simple integer vector VT!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 108, __PRETTY_FUNCTION__))
;
109 return VecTy;
110 }
111
112 /// Return the type converted to an equivalently sized integer or vector
113 /// with integer element type. Similar to changeVectorElementTypeToInteger,
114 /// but also handles scalars.
115 EVT changeTypeToInteger() {
116 if (isVector())
117 return changeVectorElementTypeToInteger();
118
119 if (isSimple())
120 return MVT::getIntegerVT(getSizeInBits());
121
122 return changeExtendedTypeToInteger();
123 }
124
125 /// Test if the given EVT is simple (as opposed to being extended).
126 bool isSimple() const {
127 return V.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE;
128 }
129
130 /// Test if the given EVT is extended (as opposed to being simple).
131 bool isExtended() const {
132 return !isSimple();
133 }
134
135 /// Return true if this is a FP or a vector FP type.
136 bool isFloatingPoint() const {
137 return isSimple() ? V.isFloatingPoint() : isExtendedFloatingPoint();
138 }
139
140 /// Return true if this is an integer or a vector integer type.
141 bool isInteger() const {
142 return isSimple() ? V.isInteger() : isExtendedInteger();
143 }
144
145 /// Return true if this is an integer, but not a vector.
146 bool isScalarInteger() const {
147 return isSimple() ? V.isScalarInteger() : isExtendedScalarInteger();
148 }
149
150 /// Return true if this is a vector value type.
151 bool isVector() const {
152 return isSimple() ? V.isVector() : isExtendedVector();
153 }
154
155 /// Return true if this is a vector type where the runtime
156 /// length is machine dependent
157 bool isScalableVector() const {
158 // FIXME: We don't support extended scalable types yet, because the
159 // matching IR type doesn't exist. Once it has been added, this can
160 // be changed to call isExtendedScalableVector.
161 if (!isSimple())
162 return false;
163 return V.isScalableVector();
164 }
165
166 /// Return true if this is a 16-bit vector type.
167 bool is16BitVector() const {
168 return isSimple() ? V.is16BitVector() : isExtended16BitVector();
169 }
170
171 /// Return true if this is a 32-bit vector type.
172 bool is32BitVector() const {
173 return isSimple() ? V.is32BitVector() : isExtended32BitVector();
174 }
175
176 /// Return true if this is a 64-bit vector type.
177 bool is64BitVector() const {
178 return isSimple() ? V.is64BitVector() : isExtended64BitVector();
179 }
180
181 /// Return true if this is a 128-bit vector type.
182 bool is128BitVector() const {
183 return isSimple() ? V.is128BitVector() : isExtended128BitVector();
184 }
185
186 /// Return true if this is a 256-bit vector type.
187 bool is256BitVector() const {
188 return isSimple() ? V.is256BitVector() : isExtended256BitVector();
189 }
190
191 /// Return true if this is a 512-bit vector type.
192 bool is512BitVector() const {
193 return isSimple() ? V.is512BitVector() : isExtended512BitVector();
194 }
195
196 /// Return true if this is a 1024-bit vector type.
197 bool is1024BitVector() const {
198 return isSimple() ? V.is1024BitVector() : isExtended1024BitVector();
199 }
200
201 /// Return true if this is a 2048-bit vector type.
202 bool is2048BitVector() const {
203 return isSimple() ? V.is2048BitVector() : isExtended2048BitVector();
204 }
205
206 /// Return true if this is an overloaded type for TableGen.
207 bool isOverloaded() const {
208 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
209 }
210
211 /// Return true if the bit size is a multiple of 8.
212 bool isByteSized() const {
213 return (getSizeInBits() & 7) == 0;
214 }
215
216 /// Return true if the size is a power-of-two number of bytes.
217 bool isRound() const {
218 unsigned BitSize = getSizeInBits();
219 return BitSize >= 8 && !(BitSize & (BitSize - 1));
220 }
221
222 /// Return true if this has the same number of bits as VT.
223 bool bitsEq(EVT VT) const {
224 if (EVT::operator==(VT)) return true;
225 return getSizeInBits() == VT.getSizeInBits();
226 }
227
228 /// Return true if this has more bits than VT.
229 bool bitsGT(EVT VT) const {
230 if (EVT::operator==(VT)) return false;
231 return getSizeInBits() > VT.getSizeInBits();
232 }
233
234 /// Return true if this has no less bits than VT.
235 bool bitsGE(EVT VT) const {
236 if (EVT::operator==(VT)) return true;
237 return getSizeInBits() >= VT.getSizeInBits();
238 }
239
240 /// Return true if this has less bits than VT.
241 bool bitsLT(EVT VT) const {
242 if (EVT::operator==(VT)) return false;
243 return getSizeInBits() < VT.getSizeInBits();
244 }
245
246 /// Return true if this has no more bits than VT.
247 bool bitsLE(EVT VT) const {
248 if (EVT::operator==(VT)) return true;
249 return getSizeInBits() <= VT.getSizeInBits();
250 }
251
252 /// Return the SimpleValueType held in the specified simple EVT.
253 MVT getSimpleVT() const {
254 assert(isSimple() && "Expected a SimpleValueType!")((isSimple() && "Expected a SimpleValueType!") ? static_cast
<void> (0) : __assert_fail ("isSimple() && \"Expected a SimpleValueType!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 254, __PRETTY_FUNCTION__))
;
255 return V;
256 }
257
258 /// If this is a vector type, return the element type, otherwise return
259 /// this.
260 EVT getScalarType() const {
261 return isVector() ? getVectorElementType() : *this;
262 }
263
264 /// Given a vector type, return the type of each element.
265 EVT getVectorElementType() const {
266 assert(isVector() && "Invalid vector type!")((isVector() && "Invalid vector type!") ? static_cast
<void> (0) : __assert_fail ("isVector() && \"Invalid vector type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 266, __PRETTY_FUNCTION__))
;
267 if (isSimple())
268 return V.getVectorElementType();
269 return getExtendedVectorElementType();
270 }
271
272 /// Given a vector type, return the number of elements it contains.
273 unsigned getVectorNumElements() const {
274 assert(isVector() && "Invalid vector type!")((isVector() && "Invalid vector type!") ? static_cast
<void> (0) : __assert_fail ("isVector() && \"Invalid vector type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 274, __PRETTY_FUNCTION__))
;
9
Within the expansion of the macro 'assert':
a
Assuming the condition is true
275 if (isSimple())
10
Taking false branch
276 return V.getVectorNumElements();
277 return getExtendedVectorNumElements();
11
Returning value
278 }
279
280 // Given a (possibly scalable) vector type, return the ElementCount
281 MVT::ElementCount getVectorElementCount() const {
282 assert((isVector()) && "Invalid vector type!")(((isVector()) && "Invalid vector type!") ? static_cast
<void> (0) : __assert_fail ("(isVector()) && \"Invalid vector type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 282, __PRETTY_FUNCTION__))
;
283 if (isSimple())
284 return V.getVectorElementCount();
285
286 assert(!isScalableVector() &&((!isScalableVector() && "We don't support extended scalable types yet"
) ? static_cast<void> (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 287, __PRETTY_FUNCTION__))
287 "We don't support extended scalable types yet")((!isScalableVector() && "We don't support extended scalable types yet"
) ? static_cast<void> (0) : __assert_fail ("!isScalableVector() && \"We don't support extended scalable types yet\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 287, __PRETTY_FUNCTION__))
;
288 return {getExtendedVectorNumElements(), false};
289 }
290
291 /// Return the size of the specified value type in bits.
292 unsigned getSizeInBits() const {
293 if (isSimple())
294 return V.getSizeInBits();
295 return getExtendedSizeInBits();
296 }
297
298 unsigned getScalarSizeInBits() const {
299 return getScalarType().getSizeInBits();
300 }
301
302 /// Return the number of bytes overwritten by a store of the specified value
303 /// type.
304 unsigned getStoreSize() const {
305 return (getSizeInBits() + 7) / 8;
306 }
307
308 /// Return the number of bits overwritten by a store of the specified value
309 /// type.
310 unsigned getStoreSizeInBits() const {
311 return getStoreSize() * 8;
312 }
313
314 /// Rounds the bit-width of the given integer EVT up to the nearest power of
315 /// two (and at least to eight), and returns the integer EVT with that
316 /// number of bits.
317 EVT getRoundIntegerType(LLVMContext &Context) const {
318 assert(isInteger() && !isVector() && "Invalid integer type!")((isInteger() && !isVector() && "Invalid integer type!"
) ? static_cast<void> (0) : __assert_fail ("isInteger() && !isVector() && \"Invalid integer type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 318, __PRETTY_FUNCTION__))
;
319 unsigned BitWidth = getSizeInBits();
320 if (BitWidth <= 8)
321 return EVT(MVT::i8);
322 return getIntegerVT(Context, 1 << Log2_32_Ceil(BitWidth));
323 }
324
325 /// Finds the smallest simple value type that is greater than or equal to
326 /// half the width of this EVT. If no simple value type can be found, an
327 /// extended integer value type of half the size (rounded up) is returned.
328 EVT getHalfSizedIntegerVT(LLVMContext &Context) const {
329 assert(isInteger() && !isVector() && "Invalid integer type!")((isInteger() && !isVector() && "Invalid integer type!"
) ? static_cast<void> (0) : __assert_fail ("isInteger() && !isVector() && \"Invalid integer type!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 329, __PRETTY_FUNCTION__))
;
330 unsigned EVTSize = getSizeInBits();
331 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE;
332 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) {
333 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT);
334 if (HalfVT.getSizeInBits() * 2 >= EVTSize)
335 return HalfVT;
336 }
337 return getIntegerVT(Context, (EVTSize + 1) / 2);
338 }
339
340 /// Return a VT for an integer vector type with the size of the
341 /// elements doubled. The typed returned may be an extended type.
342 EVT widenIntegerVectorElementType(LLVMContext &Context) const {
343 EVT EltVT = getVectorElementType();
344 EltVT = EVT::getIntegerVT(Context, 2 * EltVT.getSizeInBits());
345 return EVT::getVectorVT(Context, EltVT, getVectorElementCount());
346 }
347
348 // Return a VT for a vector type with the same element type but
349 // half the number of elements. The type returned may be an
350 // extended type.
351 EVT getHalfNumVectorElementsVT(LLVMContext &Context) const {
352 EVT EltVT = getVectorElementType();
353 auto EltCnt = getVectorElementCount();
354 assert(!(EltCnt.Min & 1) && "Splitting vector, but not in half!")((!(EltCnt.Min & 1) && "Splitting vector, but not in half!"
) ? static_cast<void> (0) : __assert_fail ("!(EltCnt.Min & 1) && \"Splitting vector, but not in half!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/ValueTypes.h"
, 354, __PRETTY_FUNCTION__))
;
355 return EVT::getVectorVT(Context, EltVT, EltCnt / 2);
356 }
357
358 /// Returns true if the given vector is a power of 2.
359 bool isPow2VectorType() const {
360 unsigned NElts = getVectorNumElements();
361 return !(NElts & (NElts - 1));
362 }
363
364 /// Widens the length of the given vector EVT up to the nearest power of 2
365 /// and returns that type.
366 EVT getPow2VectorType(LLVMContext &Context) const {
367 if (!isPow2VectorType()) {
368 unsigned NElts = getVectorNumElements();
369 unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
370 return EVT::getVectorVT(Context, getVectorElementType(), Pow2NElts,
371 isScalableVector());
372 }
373 else {
374 return *this;
375 }
376 }
377
378 /// This function returns value type as a string, e.g. "i32".
379 std::string getEVTString() const;
380
381 /// This method returns an LLVM type corresponding to the specified EVT.
382 /// For integer types, this returns an unsigned type. Note that this will
383 /// abort for types that cannot be represented.
384 Type *getTypeForEVT(LLVMContext &Context) const;
385
386 /// Return the value type corresponding to the specified type.
387 /// This returns all pointers as iPTR. If HandleUnknown is true, unknown
388 /// types are returned as Other, otherwise they are invalid.
389 static EVT getEVT(Type *Ty, bool HandleUnknown = false);
390
391 intptr_t getRawBits() const {
392 if (isSimple())
393 return V.SimpleTy;
394 else
395 return (intptr_t)(LLVMTy);
396 }
397
398 /// A meaningless but well-behaved order, useful for constructing
399 /// containers.
400 struct compareRawBits {
401 bool operator()(EVT L, EVT R) const {
402 if (L.V.SimpleTy == R.V.SimpleTy)
403 return L.LLVMTy < R.LLVMTy;
404 else
405 return L.V.SimpleTy < R.V.SimpleTy;
406 }
407 };
408
409 private:
410 // Methods for handling the Extended-type case in functions above.
411 // These are all out-of-line to prevent users of this header file
412 // from having a dependency on Type.h.
413 EVT changeExtendedTypeToInteger() const;
414 EVT changeExtendedVectorElementTypeToInteger() const;
415 static EVT getExtendedIntegerVT(LLVMContext &C, unsigned BitWidth);
416 static EVT getExtendedVectorVT(LLVMContext &C, EVT VT,
417 unsigned NumElements);
418 bool isExtendedFloatingPoint() const LLVM_READONLY__attribute__((__pure__));
419 bool isExtendedInteger() const LLVM_READONLY__attribute__((__pure__));
420 bool isExtendedScalarInteger() const LLVM_READONLY__attribute__((__pure__));
421 bool isExtendedVector() const LLVM_READONLY__attribute__((__pure__));
422 bool isExtended16BitVector() const LLVM_READONLY__attribute__((__pure__));
423 bool isExtended32BitVector() const LLVM_READONLY__attribute__((__pure__));
424 bool isExtended64BitVector() const LLVM_READONLY__attribute__((__pure__));
425 bool isExtended128BitVector() const LLVM_READONLY__attribute__((__pure__));
426 bool isExtended256BitVector() const LLVM_READONLY__attribute__((__pure__));
427 bool isExtended512BitVector() const LLVM_READONLY__attribute__((__pure__));
428 bool isExtended1024BitVector() const LLVM_READONLY__attribute__((__pure__));
429 bool isExtended2048BitVector() const LLVM_READONLY__attribute__((__pure__));
430 EVT getExtendedVectorElementType() const;
431 unsigned getExtendedVectorNumElements() const LLVM_READONLY__attribute__((__pure__));
432 unsigned getExtendedSizeInBits() const LLVM_READONLY__attribute__((__pure__));
433 };
434
435} // end namespace llvm
436
437#endif // LLVM_CODEGEN_VALUETYPES_H