Bug Summary

File:lib/CodeGen/LiveDebugValues.cpp
Warning:line 881, column 13
The left operand of '!=' is a garbage value

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LiveDebugValues.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn374877/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn374877/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn374877=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fgnuc-version=4.2.1 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-15-233810-7101-1 -x c++ /build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp

/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp

→
1//===- LiveDebugValues.cpp - Tracking Debug Value MIs ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This pass implements a data flow analysis that propagates debug location
10/// information by inserting additional DBG_VALUE insts into the machine
11/// instruction stream. Before running, each DBG_VALUE inst corresponds to a
12/// source assignment of a variable. Afterwards, a DBG_VALUE inst specifies a
13/// variable location for the current basic block (see SourceLevelDebugging.rst).
14///
15/// This is a separate pass from DbgValueHistoryCalculator to facilitate
16/// testing and improve modularity.
17///
18/// Each variable location is represented by a VarLoc object that identifies the
19/// source variable, its current machine-location, and the DBG_VALUE inst that
20/// specifies the location. Each VarLoc is indexed in the (function-scope)
21/// VarLocMap, giving each VarLoc a unique index. Rather than operate directly
22/// on machine locations, the dataflow analysis in this pass identifies
23/// locations by their index in the VarLocMap, meaning all the variable
24/// locations in a block can be described by a sparse vector of VarLocMap
25/// indexes.
26///
27//===----------------------------------------------------------------------===//
28
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/PostOrderIterator.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/SparseBitVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/UniqueVector.h"
37#include "llvm/CodeGen/LexicalScopes.h"
38#include "llvm/CodeGen/MachineBasicBlock.h"
39#include "llvm/CodeGen/MachineFrameInfo.h"
40#include "llvm/CodeGen/MachineFunction.h"
41#include "llvm/CodeGen/MachineFunctionPass.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineMemOperand.h"
45#include "llvm/CodeGen/MachineOperand.h"
46#include "llvm/CodeGen/PseudoSourceValue.h"
47#include "llvm/CodeGen/RegisterScavenging.h"
48#include "llvm/CodeGen/TargetFrameLowering.h"
49#include "llvm/CodeGen/TargetInstrInfo.h"
50#include "llvm/CodeGen/TargetLowering.h"
51#include "llvm/CodeGen/TargetPassConfig.h"
52#include "llvm/CodeGen/TargetRegisterInfo.h"
53#include "llvm/CodeGen/TargetSubtargetInfo.h"
54#include "llvm/Config/llvm-config.h"
55#include "llvm/IR/DIBuilder.h"
56#include "llvm/IR/DebugInfoMetadata.h"
57#include "llvm/IR/DebugLoc.h"
58#include "llvm/IR/Function.h"
59#include "llvm/IR/Module.h"
60#include "llvm/MC/MCRegisterInfo.h"
61#include "llvm/Pass.h"
62#include "llvm/Support/Casting.h"
63#include "llvm/Support/Compiler.h"
64#include "llvm/Support/Debug.h"
65#include "llvm/Support/raw_ostream.h"
66#include <algorithm>
67#include <cassert>
68#include <cstdint>
69#include <functional>
70#include <queue>
71#include <tuple>
72#include <utility>
73#include <vector>
74
75using namespace llvm;
76
77#define DEBUG_TYPE"livedebugvalues" "livedebugvalues"
78
79STATISTIC(NumInserted, "Number of DBG_VALUE instructions inserted")static llvm::Statistic NumInserted = {"livedebugvalues", "NumInserted"
, "Number of DBG_VALUE instructions inserted"};
80STATISTIC(NumRemoved, "Number of DBG_VALUE instructions removed")static llvm::Statistic NumRemoved = {"livedebugvalues", "NumRemoved"
, "Number of DBG_VALUE instructions removed"};
81
82// If @MI is a DBG_VALUE with debug value described by a defined
83// register, returns the number of this register. In the other case, returns 0.
84static Register isDbgValueDescribedByReg(const MachineInstr &MI) {
85 assert(MI.isDebugValue() && "expected a DBG_VALUE")((MI.isDebugValue() && "expected a DBG_VALUE") ? static_cast
<void> (0) : __assert_fail ("MI.isDebugValue() && \"expected a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 85, __PRETTY_FUNCTION__));
86 assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE")((MI.getNumOperands() == 4 && "malformed DBG_VALUE") ?
static_cast<void> (0) : __assert_fail ("MI.getNumOperands() == 4 && \"malformed DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 86, __PRETTY_FUNCTION__));
87 // If location of variable is described using a register (directly
88 // or indirectly), this register is always a first operand.
89 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
90}
91
92namespace {
93
94class LiveDebugValues : public MachineFunctionPass {
95private:
96 const TargetRegisterInfo *TRI;
97 const TargetInstrInfo *TII;
98 const TargetFrameLowering *TFI;
99 BitVector CalleeSavedRegs;
100 LexicalScopes LS;
101
102 enum struct TransferKind { TransferCopy, TransferSpill, TransferRestore };
103
104 /// Keeps track of lexical scopes associated with a user value's source
105 /// location.
106 class UserValueScopes {
107 DebugLoc DL;
108 LexicalScopes &LS;
109 SmallPtrSet<const MachineBasicBlock *, 4> LBlocks;
110
111 public:
112 UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(std::move(D)), LS(L) {}
113
114 /// Return true if current scope dominates at least one machine
115 /// instruction in a given machine basic block.
116 bool dominates(MachineBasicBlock *MBB) {
117 if (LBlocks.empty())
118 LS.getMachineBasicBlocks(DL, LBlocks);
119 return LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB);
120 }
121 };
122
123 using FragmentInfo = DIExpression::FragmentInfo;
124 using OptFragmentInfo = Optional<DIExpression::FragmentInfo>;
125
126 /// Storage for identifying a potentially inlined instance of a variable,
127 /// or a fragment thereof.
128 class DebugVariable {
129 const DILocalVariable *Variable;
130 OptFragmentInfo Fragment;
131 const DILocation *InlinedAt;
132
133 /// Fragment that will overlap all other fragments. Used as default when
134 /// caller demands a fragment.
135 static const FragmentInfo DefaultFragment;
136
137 public:
138 DebugVariable(const DILocalVariable *Var, OptFragmentInfo &&FragmentInfo,
139 const DILocation *InlinedAt)
140 : Variable(Var), Fragment(FragmentInfo), InlinedAt(InlinedAt) {}
141
142 DebugVariable(const DILocalVariable *Var, OptFragmentInfo &FragmentInfo,
143 const DILocation *InlinedAt)
144 : Variable(Var), Fragment(FragmentInfo), InlinedAt(InlinedAt) {}
145
146 DebugVariable(const DILocalVariable *Var, const DIExpression *DIExpr,
147 const DILocation *InlinedAt)
148 : DebugVariable(Var, DIExpr->getFragmentInfo(), InlinedAt) {}
149
150 DebugVariable(const MachineInstr &MI)
151 : DebugVariable(MI.getDebugVariable(),
152 MI.getDebugExpression()->getFragmentInfo(),
153 MI.getDebugLoc()->getInlinedAt()) {}
154
155 const DILocalVariable *getVar() const { return Variable; }
156 const OptFragmentInfo &getFragment() const { return Fragment; }
157 const DILocation *getInlinedAt() const { return InlinedAt; }
158
159 const FragmentInfo getFragmentDefault() const {
160 return Fragment.getValueOr(DefaultFragment);
161 }
162
163 static bool isFragmentDefault(FragmentInfo &F) {
164 return F == DefaultFragment;
165 }
166
167 bool operator==(const DebugVariable &Other) const {
168 return std::tie(Variable, Fragment, InlinedAt) ==
169 std::tie(Other.Variable, Other.Fragment, Other.InlinedAt);
170 }
171
172 bool operator<(const DebugVariable &Other) const {
173 return std::tie(Variable, Fragment, InlinedAt) <
174 std::tie(Other.Variable, Other.Fragment, Other.InlinedAt);
175 }
176 };
177
178 friend struct llvm::DenseMapInfo<DebugVariable>;
179
180 /// A pair of debug variable and value location.
181 struct VarLoc {
182 // The location at which a spilled variable resides. It consists of a
183 // register and an offset.
184 struct SpillLoc {
185 unsigned SpillBase;
186 int SpillOffset;
187 bool operator==(const SpillLoc &Other) const {
188 return SpillBase == Other.SpillBase && SpillOffset == Other.SpillOffset;
189 }
190 };
191
192 /// Identity of the variable at this location.
193 const DebugVariable Var;
194
195 /// The expression applied to this location.
196 const DIExpression *Expr;
197
198 /// DBG_VALUE to clone var/expr information from if this location
199 /// is moved.
200 const MachineInstr &MI;
201
202 mutable UserValueScopes UVS;
203 enum VarLocKind {
204 InvalidKind = 0,
205 RegisterKind,
206 SpillLocKind,
207 ImmediateKind,
208 EntryValueKind
209 } Kind = InvalidKind;
210
211 /// The value location. Stored separately to avoid repeatedly
212 /// extracting it from MI.
213 union {
214 uint64_t RegNo;
215 SpillLoc SpillLocation;
216 uint64_t Hash;
217 int64_t Immediate;
218 const ConstantFP *FPImm;
219 const ConstantInt *CImm;
220 } Loc;
221
222 VarLoc(const MachineInstr &MI, LexicalScopes &LS)
223 : Var(MI), Expr(MI.getDebugExpression()), MI(MI),
224 UVS(MI.getDebugLoc(), LS) {
225 static_assert((sizeof(Loc) == sizeof(uint64_t)),
226 "hash does not cover all members of Loc");
227 assert(MI.isDebugValue() && "not a DBG_VALUE")((MI.isDebugValue() && "not a DBG_VALUE") ? static_cast
<void> (0) : __assert_fail ("MI.isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 227, __PRETTY_FUNCTION__));
228 assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE")((MI.getNumOperands() == 4 && "malformed DBG_VALUE") ?
static_cast<void> (0) : __assert_fail ("MI.getNumOperands() == 4 && \"malformed DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 228, __PRETTY_FUNCTION__));
229 if (int RegNo = isDbgValueDescribedByReg(MI)) {
230 Kind = MI.isDebugEntryValue() ? EntryValueKind : RegisterKind;
231 Loc.RegNo = RegNo;
232 } else if (MI.getOperand(0).isImm()) {
233 Kind = ImmediateKind;
234 Loc.Immediate = MI.getOperand(0).getImm();
235 } else if (MI.getOperand(0).isFPImm()) {
236 Kind = ImmediateKind;
237 Loc.FPImm = MI.getOperand(0).getFPImm();
238 } else if (MI.getOperand(0).isCImm()) {
239 Kind = ImmediateKind;
240 Loc.CImm = MI.getOperand(0).getCImm();
241 }
242 assert((Kind != ImmediateKind || !MI.isDebugEntryValue()) &&(((Kind != ImmediateKind || !MI.isDebugEntryValue()) &&
"entry values must be register locations") ? static_cast<
void> (0) : __assert_fail ("(Kind != ImmediateKind || !MI.isDebugEntryValue()) && \"entry values must be register locations\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 243, __PRETTY_FUNCTION__))
243 "entry values must be register locations")(((Kind != ImmediateKind || !MI.isDebugEntryValue()) &&
"entry values must be register locations") ? static_cast<
void> (0) : __assert_fail ("(Kind != ImmediateKind || !MI.isDebugEntryValue()) && \"entry values must be register locations\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 243, __PRETTY_FUNCTION__));
244 }
245
246 /// Take the variable and machine-location in DBG_VALUE MI, and build an
247 /// entry location using the given expression.
248 static VarLoc CreateEntryLoc(const MachineInstr &MI, LexicalScopes &LS,
249 const DIExpression *EntryExpr) {
250 VarLoc VL(MI, LS);
251 VL.Kind = EntryValueKind;
252 VL.Expr = EntryExpr;
253 return VL;
254 }
255
256 /// Copy the register location in DBG_VALUE MI, updating the register to
257 /// be NewReg.
258 static VarLoc CreateCopyLoc(const MachineInstr &MI, LexicalScopes &LS,
259 unsigned NewReg) {
260 VarLoc VL(MI, LS);
261 assert(VL.Kind == RegisterKind)((VL.Kind == RegisterKind) ? static_cast<void> (0) : __assert_fail
("VL.Kind == RegisterKind", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 261, __PRETTY_FUNCTION__));
262 VL.Loc.RegNo = NewReg;
263 return VL;
264 }
265
266 /// Take the variable described by DBG_VALUE MI, and create a VarLoc
267 /// locating it in the specified spill location.
268 static VarLoc CreateSpillLoc(const MachineInstr &MI, unsigned SpillBase,
269 int SpillOffset, LexicalScopes &LS) {
270 VarLoc VL(MI, LS);
271 assert(VL.Kind == RegisterKind)((VL.Kind == RegisterKind) ? static_cast<void> (0) : __assert_fail
("VL.Kind == RegisterKind", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 271, __PRETTY_FUNCTION__));
272 VL.Kind = SpillLocKind;
273 VL.Loc.SpillLocation = {SpillBase, SpillOffset};
274 return VL;
275 }
276
277 /// Create a DBG_VALUE representing this VarLoc in the given function.
278 /// Copies variable-specific information such as DILocalVariable and
279 /// inlining information from the original DBG_VALUE instruction, which may
280 /// have been several transfers ago.
281 MachineInstr *BuildDbgValue(MachineFunction &MF) const {
282 const DebugLoc &DbgLoc = MI.getDebugLoc();
283 bool Indirect = MI.isIndirectDebugValue();
284 const auto &IID = MI.getDesc();
285 const DILocalVariable *Var = MI.getDebugVariable();
286 const DIExpression *DIExpr = MI.getDebugExpression();
287
288 switch (Kind) {
289 case EntryValueKind:
290 // An entry value is a register location -- but with an updated
291 // expression.
292 return BuildMI(MF, DbgLoc, IID, Indirect, Loc.RegNo, Var, Expr);
293 case RegisterKind:
294 // Register locations are like the source DBG_VALUE, but with the
295 // register number from this VarLoc.
296 return BuildMI(MF, DbgLoc, IID, Indirect, Loc.RegNo, Var, DIExpr);
297 case SpillLocKind: {
298 // Spills are indirect DBG_VALUEs, with a base register and offset.
299 // Use the original DBG_VALUEs expression to build the spilt location
300 // on top of. FIXME: spill locations created before this pass runs
301 // are not recognized, and not handled here.
302 auto *SpillExpr = DIExpression::prepend(
303 DIExpr, DIExpression::ApplyOffset, Loc.SpillLocation.SpillOffset);
304 unsigned Base = Loc.SpillLocation.SpillBase;
305 return BuildMI(MF, DbgLoc, IID, true, Base, Var, SpillExpr);
306 }
307 case ImmediateKind: {
308 MachineOperand MO = MI.getOperand(0);
309 return BuildMI(MF, DbgLoc, IID, Indirect, MO, Var, DIExpr);
310 }
311 case InvalidKind:
312 llvm_unreachable("Tried to produce DBG_VALUE for invalid VarLoc")::llvm::llvm_unreachable_internal("Tried to produce DBG_VALUE for invalid VarLoc"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 312);
313 }
314 llvm_unreachable("Unrecognized LiveDebugValues.VarLoc.Kind enum")::llvm::llvm_unreachable_internal("Unrecognized LiveDebugValues.VarLoc.Kind enum"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 314);
315 }
316
317 /// Is the Loc field a constant or constant object?
318 bool isConstant() const { return Kind == ImmediateKind; }
319
320 /// If this variable is described by a register, return it,
321 /// otherwise return 0.
322 unsigned isDescribedByReg() const {
323 if (Kind == RegisterKind)
324 return Loc.RegNo;
325 return 0;
326 }
327
328 /// Determine whether the lexical scope of this value's debug location
329 /// dominates MBB.
330 bool dominates(MachineBasicBlock &MBB) const { return UVS.dominates(&MBB); }
331
332#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
333 // TRI can be null.
334 void dump(const TargetRegisterInfo *TRI, raw_ostream &Out = dbgs()) const {
335 dbgs() << "VarLoc(";
336 switch (Kind) {
337 case RegisterKind:
338 case EntryValueKind:
339 dbgs() << printReg(Loc.RegNo, TRI);
340 break;
341 case SpillLocKind:
342 dbgs() << printReg(Loc.SpillLocation.SpillBase, TRI);
343 dbgs() << "[" << Loc.SpillLocation.SpillOffset << "]";
344 break;
345 case ImmediateKind:
346 dbgs() << Loc.Immediate;
347 break;
348 case InvalidKind:
349 llvm_unreachable("Invalid VarLoc in dump method")::llvm::llvm_unreachable_internal("Invalid VarLoc in dump method"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 349);
350 }
351
352 dbgs() << ", \"" << Var.getVar()->getName() << "\", " << *Expr << ", ";
353 if (Var.getInlinedAt())
354 dbgs() << "!" << Var.getInlinedAt()->getMetadataID() << ")\n";
355 else
356 dbgs() << "(null))\n";
357 }
358#endif
359
360 bool operator==(const VarLoc &Other) const {
361 return Kind == Other.Kind && Var == Other.Var &&
362 Loc.Hash == Other.Loc.Hash && Expr == Other.Expr;
363 }
364
365 /// This operator guarantees that VarLocs are sorted by Variable first.
366 bool operator<(const VarLoc &Other) const {
367 return std::tie(Var, Kind, Loc.Hash, Expr) <
368 std::tie(Other.Var, Other.Kind, Other.Loc.Hash, Other.Expr);
369 }
370 };
371
372 using DebugParamMap = SmallDenseMap<const DILocalVariable *, MachineInstr *>;
373 using VarLocMap = UniqueVector<VarLoc>;
374 using VarLocSet = SparseBitVector<>;
375 using VarLocInMBB = SmallDenseMap<const MachineBasicBlock *, VarLocSet>;
376 struct TransferDebugPair {
377 MachineInstr *TransferInst; /// Instruction where this transfer occurs.
378 unsigned LocationID; /// Location number for the transfer dest.
379 };
380 using TransferMap = SmallVector<TransferDebugPair, 4>;
381
382 // Types for recording sets of variable fragments that overlap. For a given
383 // local variable, we record all other fragments of that variable that could
384 // overlap it, to reduce search time.
385 using FragmentOfVar =
386 std::pair<const DILocalVariable *, DIExpression::FragmentInfo>;
387 using OverlapMap =
388 DenseMap<FragmentOfVar, SmallVector<DIExpression::FragmentInfo, 1>>;
389
390 // Helper while building OverlapMap, a map of all fragments seen for a given
391 // DILocalVariable.
392 using VarToFragments =
393 DenseMap<const DILocalVariable *, SmallSet<FragmentInfo, 4>>;
394
395 /// This holds the working set of currently open ranges. For fast
396 /// access, this is done both as a set of VarLocIDs, and a map of
397 /// DebugVariable to recent VarLocID. Note that a DBG_VALUE ends all
398 /// previous open ranges for the same variable.
399 class OpenRangesSet {
400 VarLocSet VarLocs;
401 SmallDenseMap<DebugVariable, unsigned, 8> Vars;
402 OverlapMap &OverlappingFragments;
403
404 public:
405 OpenRangesSet(OverlapMap &_OLapMap) : OverlappingFragments(_OLapMap) {}
406
407 const VarLocSet &getVarLocs() const { return VarLocs; }
408
409 /// Terminate all open ranges for Var by removing it from the set.
410 void erase(DebugVariable Var);
411
412 /// Terminate all open ranges listed in \c KillSet by removing
413 /// them from the set.
414 void erase(const VarLocSet &KillSet, const VarLocMap &VarLocIDs) {
415 VarLocs.intersectWithComplement(KillSet);
416 for (unsigned ID : KillSet)
417 Vars.erase(VarLocIDs[ID].Var);
418 }
419
420 /// Insert a new range into the set.
421 void insert(unsigned VarLocID, DebugVariable Var) {
422 VarLocs.set(VarLocID);
423 Vars.insert({Var, VarLocID});
424 }
425
426 /// Insert a set of ranges.
427 void insertFromLocSet(const VarLocSet &ToLoad, const VarLocMap &Map) {
428 for (unsigned Id : ToLoad) {
429 const VarLoc &Var = Map[Id];
430 insert(Id, Var.Var);
431 }
432 }
433
434 /// Empty the set.
435 void clear() {
436 VarLocs.clear();
437 Vars.clear();
438 }
439
440 /// Return whether the set is empty or not.
441 bool empty() const {
442 assert(Vars.empty() == VarLocs.empty() && "open ranges are inconsistent")((Vars.empty() == VarLocs.empty() && "open ranges are inconsistent"
) ? static_cast<void> (0) : __assert_fail ("Vars.empty() == VarLocs.empty() && \"open ranges are inconsistent\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 442, __PRETTY_FUNCTION__));
443 return VarLocs.empty();
444 }
445 };
446
447 /// Tests whether this instruction is a spill to a stack location.
448 bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF);
449
450 /// Decide if @MI is a spill instruction and return true if it is. We use 2
451 /// criteria to make this decision:
452 /// - Is this instruction a store to a spill slot?
453 /// - Is there a register operand that is both used and killed?
454 /// TODO: Store optimization can fold spills into other stores (including
455 /// other spills). We do not handle this yet (more than one memory operand).
456 bool isLocationSpill(const MachineInstr &MI, MachineFunction *MF,
457 unsigned &Reg);
458
459 /// If a given instruction is identified as a spill, return the spill location
460 /// and set \p Reg to the spilled register.
461 Optional<VarLoc::SpillLoc> isRestoreInstruction(const MachineInstr &MI,
462 MachineFunction *MF,
463 unsigned &Reg);
464 /// Given a spill instruction, extract the register and offset used to
465 /// address the spill location in a target independent way.
466 VarLoc::SpillLoc extractSpillBaseRegAndOffset(const MachineInstr &MI);
467 void insertTransferDebugPair(MachineInstr &MI, OpenRangesSet &OpenRanges,
468 TransferMap &Transfers, VarLocMap &VarLocIDs,
469 unsigned OldVarID, TransferKind Kind,
470 unsigned NewReg = 0);
471
472 void transferDebugValue(const MachineInstr &MI, OpenRangesSet &OpenRanges,
473 VarLocMap &VarLocIDs);
474 void transferSpillOrRestoreInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
475 VarLocMap &VarLocIDs, TransferMap &Transfers);
476 void emitEntryValues(MachineInstr &MI, OpenRangesSet &OpenRanges,
477 VarLocMap &VarLocIDs, TransferMap &Transfers,
478 DebugParamMap &DebugEntryVals,
479 SparseBitVector<> &KillSet);
480 void transferRegisterCopy(MachineInstr &MI, OpenRangesSet &OpenRanges,
481 VarLocMap &VarLocIDs, TransferMap &Transfers);
482 void transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges,
483 VarLocMap &VarLocIDs, TransferMap &Transfers,
484 DebugParamMap &DebugEntryVals);
485 bool transferTerminator(MachineBasicBlock *MBB, OpenRangesSet &OpenRanges,
486 VarLocInMBB &OutLocs, const VarLocMap &VarLocIDs);
487
488 void process(MachineInstr &MI, OpenRangesSet &OpenRanges,
489 VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
490 TransferMap &Transfers, DebugParamMap &DebugEntryVals,
491 OverlapMap &OverlapFragments,
492 VarToFragments &SeenFragments);
493
494 void accumulateFragmentMap(MachineInstr &MI, VarToFragments &SeenFragments,
495 OverlapMap &OLapMap);
496
497 bool join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
498 const VarLocMap &VarLocIDs,
499 SmallPtrSet<const MachineBasicBlock *, 16> &Visited,
500 SmallPtrSetImpl<const MachineBasicBlock *> &ArtificialBlocks,
501 VarLocInMBB &PendingInLocs);
502
503 /// Create DBG_VALUE insts for inlocs that have been propagated but
504 /// had their instruction creation deferred.
505 void flushPendingLocs(VarLocInMBB &PendingInLocs, VarLocMap &VarLocIDs);
506
507 bool ExtendRanges(MachineFunction &MF);
508
509public:
510 static char ID;
511
512 /// Default construct and initialize the pass.
513 LiveDebugValues();
514
515 /// Tell the pass manager which passes we depend on and what
516 /// information we preserve.
517 void getAnalysisUsage(AnalysisUsage &AU) const override;
518
519 MachineFunctionProperties getRequiredProperties() const override {
520 return MachineFunctionProperties().set(
521 MachineFunctionProperties::Property::NoVRegs);
522 }
523
524 /// Print to ostream with a message.
525 void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V,
526 const VarLocMap &VarLocIDs, const char *msg,
527 raw_ostream &Out) const;
528
529 /// Calculate the liveness information for the given machine function.
530 bool runOnMachineFunction(MachineFunction &MF) override;
531};
532
533} // end anonymous namespace
534
535namespace llvm {
536
537template <> struct DenseMapInfo<LiveDebugValues::DebugVariable> {
538 using DV = LiveDebugValues::DebugVariable;
539 using OptFragmentInfo = LiveDebugValues::OptFragmentInfo;
540 using FragmentInfo = LiveDebugValues::FragmentInfo;
541
542 // Empty key: no key should be generated that has no DILocalVariable.
543 static inline DV getEmptyKey() {
544 return DV(nullptr, OptFragmentInfo(), nullptr);
545 }
546
547 // Difference in tombstone is that the Optional is meaningful
548 static inline DV getTombstoneKey() {
549 return DV(nullptr, OptFragmentInfo({0, 0}), nullptr);
550 }
551
552 static unsigned getHashValue(const DV &D) {
553 unsigned HV = 0;
554 const OptFragmentInfo &Fragment = D.getFragment();
555 if (Fragment)
556 HV = DenseMapInfo<FragmentInfo>::getHashValue(*Fragment);
557
558 return hash_combine(D.getVar(), HV, D.getInlinedAt());
559 }
560
561 static bool isEqual(const DV &A, const DV &B) { return A == B; }
562};
563
564} // namespace llvm
565
566//===----------------------------------------------------------------------===//
567// Implementation
568//===----------------------------------------------------------------------===//
569
570const DIExpression::FragmentInfo
571 LiveDebugValues::DebugVariable::DefaultFragment = {
572 std::numeric_limits<uint64_t>::max(),
573 std::numeric_limits<uint64_t>::min()};
574
575char LiveDebugValues::ID = 0;
576
577char &llvm::LiveDebugValuesID = LiveDebugValues::ID;
578
579INITIALIZE_PASS(LiveDebugValues, DEBUG_TYPE, "Live DEBUG_VALUE analysis",static void *initializeLiveDebugValuesPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Live DEBUG_VALUE analysis"
, "livedebugvalues", &LiveDebugValues::ID, PassInfo::NormalCtor_t
(callDefaultCtor<LiveDebugValues>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeLiveDebugValuesPassFlag; void llvm::initializeLiveDebugValuesPass
(PassRegistry &Registry) { llvm::call_once(InitializeLiveDebugValuesPassFlag
, initializeLiveDebugValuesPassOnce, std::ref(Registry)); }
580 false, false)static void *initializeLiveDebugValuesPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Live DEBUG_VALUE analysis"
, "livedebugvalues", &LiveDebugValues::ID, PassInfo::NormalCtor_t
(callDefaultCtor<LiveDebugValues>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeLiveDebugValuesPassFlag; void llvm::initializeLiveDebugValuesPass
(PassRegistry &Registry) { llvm::call_once(InitializeLiveDebugValuesPassFlag
, initializeLiveDebugValuesPassOnce, std::ref(Registry)); }
581
582/// Default construct and initialize the pass.
583LiveDebugValues::LiveDebugValues() : MachineFunctionPass(ID) {
584 initializeLiveDebugValuesPass(*PassRegistry::getPassRegistry());
585}
586
587/// Tell the pass manager which passes we depend on and what information we
588/// preserve.
589void LiveDebugValues::getAnalysisUsage(AnalysisUsage &AU) const {
590 AU.setPreservesCFG();
591 MachineFunctionPass::getAnalysisUsage(AU);
592}
593
594/// Erase a variable from the set of open ranges, and additionally erase any
595/// fragments that may overlap it.
596void LiveDebugValues::OpenRangesSet::erase(DebugVariable Var) {
597 // Erasure helper.
598 auto DoErase = [this](DebugVariable VarToErase) {
599 auto It = Vars.find(VarToErase);
600 if (It != Vars.end()) {
601 unsigned ID = It->second;
602 VarLocs.reset(ID);
603 Vars.erase(It);
604 }
605 };
606
607 // Erase the variable/fragment that ends here.
608 DoErase(Var);
609
610 // Extract the fragment. Interpret an empty fragment as one that covers all
611 // possible bits.
612 FragmentInfo ThisFragment = Var.getFragmentDefault();
613
614 // There may be fragments that overlap the designated fragment. Look them up
615 // in the pre-computed overlap map, and erase them too.
616 auto MapIt = OverlappingFragments.find({Var.getVar(), ThisFragment});
617 if (MapIt != OverlappingFragments.end()) {
618 for (auto Fragment : MapIt->second) {
619 LiveDebugValues::OptFragmentInfo FragmentHolder;
620 if (!DebugVariable::isFragmentDefault(Fragment))
621 FragmentHolder = LiveDebugValues::OptFragmentInfo(Fragment);
622 DoErase({Var.getVar(), FragmentHolder, Var.getInlinedAt()});
623 }
624 }
625}
626
627//===----------------------------------------------------------------------===//
628// Debug Range Extension Implementation
629//===----------------------------------------------------------------------===//
630
631#ifndef NDEBUG
632void LiveDebugValues::printVarLocInMBB(const MachineFunction &MF,
633 const VarLocInMBB &V,
634 const VarLocMap &VarLocIDs,
635 const char *msg,
636 raw_ostream &Out) const {
637 Out << '\n' << msg << '\n';
638 for (const MachineBasicBlock &BB : MF) {
639 const VarLocSet &L = V.lookup(&BB);
640 if (L.empty())
641 continue;
642 Out << "MBB: " << BB.getNumber() << ":\n";
643 for (unsigned VLL : L) {
644 const VarLoc &VL = VarLocIDs[VLL];
645 Out << " Var: " << VL.Var.getVar()->getName();
646 Out << " MI: ";
647 VL.dump(TRI, Out);
648 }
649 }
650 Out << "\n";
651}
652#endif
653
654LiveDebugValues::VarLoc::SpillLoc
655LiveDebugValues::extractSpillBaseRegAndOffset(const MachineInstr &MI) {
656 assert(MI.hasOneMemOperand() &&((MI.hasOneMemOperand() && "Spill instruction does not have exactly one memory operand?"
) ? static_cast<void> (0) : __assert_fail ("MI.hasOneMemOperand() && \"Spill instruction does not have exactly one memory operand?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 657, __PRETTY_FUNCTION__))
657 "Spill instruction does not have exactly one memory operand?")((MI.hasOneMemOperand() && "Spill instruction does not have exactly one memory operand?"
) ? static_cast<void> (0) : __assert_fail ("MI.hasOneMemOperand() && \"Spill instruction does not have exactly one memory operand?\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 657, __PRETTY_FUNCTION__));
658 auto MMOI = MI.memoperands_begin();
659 const PseudoSourceValue *PVal = (*MMOI)->getPseudoValue();
660 assert(PVal->kind() == PseudoSourceValue::FixedStack &&((PVal->kind() == PseudoSourceValue::FixedStack &&
"Inconsistent memory operand in spill instruction") ? static_cast
<void> (0) : __assert_fail ("PVal->kind() == PseudoSourceValue::FixedStack && \"Inconsistent memory operand in spill instruction\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 661, __PRETTY_FUNCTION__))
661 "Inconsistent memory operand in spill instruction")((PVal->kind() == PseudoSourceValue::FixedStack &&
"Inconsistent memory operand in spill instruction") ? static_cast
<void> (0) : __assert_fail ("PVal->kind() == PseudoSourceValue::FixedStack && \"Inconsistent memory operand in spill instruction\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 661, __PRETTY_FUNCTION__));
662 int FI = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
663 const MachineBasicBlock *MBB = MI.getParent();
664 unsigned Reg;
665 int Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg);
666 return {Reg, Offset};
667}
668
669/// End all previous ranges related to @MI and start a new range from @MI
670/// if it is a DBG_VALUE instr.
671void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
672 OpenRangesSet &OpenRanges,
673 VarLocMap &VarLocIDs) {
674 if (!MI.isDebugValue())
675 return;
676 const DILocalVariable *Var = MI.getDebugVariable();
677 const DIExpression *Expr = MI.getDebugExpression();
678 const DILocation *DebugLoc = MI.getDebugLoc();
679 const DILocation *InlinedAt = DebugLoc->getInlinedAt();
680 assert(Var->isValidLocationForIntrinsic(DebugLoc) &&((Var->isValidLocationForIntrinsic(DebugLoc) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Var->isValidLocationForIntrinsic(DebugLoc) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 681, __PRETTY_FUNCTION__))
681 "Expected inlined-at fields to agree")((Var->isValidLocationForIntrinsic(DebugLoc) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Var->isValidLocationForIntrinsic(DebugLoc) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 681, __PRETTY_FUNCTION__));
682
683 // End all previous ranges of Var.
684 DebugVariable V(Var, Expr, InlinedAt);
685 OpenRanges.erase(V);
686
687 // Add the VarLoc to OpenRanges from this DBG_VALUE.
688 unsigned ID;
689 if (isDbgValueDescribedByReg(MI) || MI.getOperand(0).isImm() ||
690 MI.getOperand(0).isFPImm() || MI.getOperand(0).isCImm()) {
691 // Use normal VarLoc constructor for registers and immediates.
692 VarLoc VL(MI, LS);
693 ID = VarLocIDs.insert(VL);
694 OpenRanges.insert(ID, VL.Var);
695 } else if (MI.hasOneMemOperand()) {
696 llvm_unreachable("DBG_VALUE with mem operand encountered after regalloc?")::llvm::llvm_unreachable_internal("DBG_VALUE with mem operand encountered after regalloc?"
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 696);
697 } else {
698 // This must be an undefined location. We should leave OpenRanges closed.
699 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&((MI.getOperand(0).isReg() && MI.getOperand(0).getReg
() == 0 && "Unexpected non-undef DBG_VALUE encountered"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 && \"Unexpected non-undef DBG_VALUE encountered\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 700, __PRETTY_FUNCTION__))
700 "Unexpected non-undef DBG_VALUE encountered")((MI.getOperand(0).isReg() && MI.getOperand(0).getReg
() == 0 && "Unexpected non-undef DBG_VALUE encountered"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 && \"Unexpected non-undef DBG_VALUE encountered\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 700, __PRETTY_FUNCTION__));
701 }
702}
703
704void LiveDebugValues::emitEntryValues(MachineInstr &MI,
705 OpenRangesSet &OpenRanges,
706 VarLocMap &VarLocIDs,
707 TransferMap &Transfers,
708 DebugParamMap &DebugEntryVals,
709 SparseBitVector<> &KillSet) {
710 for (unsigned ID : KillSet) {
711 if (!VarLocIDs[ID].Var.getVar()->isParameter())
712 continue;
713
714 const MachineInstr *CurrDebugInstr = &VarLocIDs[ID].MI;
715
716 // If parameter's DBG_VALUE is not in the map that means we can't
717 // generate parameter's entry value.
718 if (!DebugEntryVals.count(CurrDebugInstr->getDebugVariable()))
719 continue;
720
721 auto ParamDebugInstr = DebugEntryVals[CurrDebugInstr->getDebugVariable()];
722 DIExpression *NewExpr = DIExpression::prepend(
723 ParamDebugInstr->getDebugExpression(), DIExpression::EntryValue);
724
725 VarLoc EntryLoc = VarLoc::CreateEntryLoc(*ParamDebugInstr, LS, NewExpr);
726
727 unsigned EntryValLocID = VarLocIDs.insert(EntryLoc);
728 Transfers.push_back({&MI, EntryValLocID});
729 OpenRanges.insert(EntryValLocID, EntryLoc.Var);
730 }
731}
732
733/// Create new TransferDebugPair and insert it in \p Transfers. The VarLoc
734/// with \p OldVarID should be deleted form \p OpenRanges and replaced with
735/// new VarLoc. If \p NewReg is different than default zero value then the
736/// new location will be register location created by the copy like instruction,
737/// otherwise it is variable's location on the stack.
738void LiveDebugValues::insertTransferDebugPair(
739 MachineInstr &MI, OpenRangesSet &OpenRanges, TransferMap &Transfers,
740 VarLocMap &VarLocIDs, unsigned OldVarID, TransferKind Kind,
741 unsigned NewReg) {
742 const MachineInstr *DebugInstr = &VarLocIDs[OldVarID].MI;
743
744 auto ProcessVarLoc = [&MI, &OpenRanges, &Transfers, &DebugInstr,
745 &VarLocIDs](VarLoc &VL) {
746 unsigned LocId = VarLocIDs.insert(VL);
747
748 // Close this variable's previous location range.
749 DebugVariable V(*DebugInstr);
750 OpenRanges.erase(V);
751
752 // Record the new location as an open range, and a postponed transfer
753 // inserting a DBG_VALUE for this location.
754 OpenRanges.insert(LocId, VL.Var);
755 TransferDebugPair MIP = {&MI, LocId};
756 Transfers.push_back(MIP);
757 };
758
759 // End all previous ranges of Var.
760 OpenRanges.erase(VarLocIDs[OldVarID].Var);
761 switch (Kind) {
762 case TransferKind::TransferCopy: {
763 assert(NewReg &&((NewReg && "No register supplied when handling a copy of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a copy of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 764, __PRETTY_FUNCTION__))
764 "No register supplied when handling a copy of a debug value")((NewReg && "No register supplied when handling a copy of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a copy of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 764, __PRETTY_FUNCTION__));
765 // Create a DBG_VALUE instruction to describe the Var in its new
766 // register location.
767 VarLoc VL = VarLoc::CreateCopyLoc(*DebugInstr, LS, NewReg);
768 ProcessVarLoc(VL);
769 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for register copy:"
; VL.dump(TRI); }; } } while (false)
770 dbgs() << "Creating VarLoc for register copy:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for register copy:"
; VL.dump(TRI); }; } } while (false)
771 VL.dump(TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for register copy:"
; VL.dump(TRI); }; } } while (false)
772 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for register copy:"
; VL.dump(TRI); }; } } while (false);
773 return;
774 }
775 case TransferKind::TransferSpill: {
776 // Create a DBG_VALUE instruction to describe the Var in its spilled
777 // location.
778 VarLoc::SpillLoc SpillLocation = extractSpillBaseRegAndOffset(MI);
779 VarLoc VL = VarLoc::CreateSpillLoc(*DebugInstr, SpillLocation.SpillBase,
780 SpillLocation.SpillOffset, LS);
781 ProcessVarLoc(VL);
782 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for spill:"
; VL.dump(TRI); }; } } while (false)
783 dbgs() << "Creating VarLoc for spill:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for spill:"
; VL.dump(TRI); }; } } while (false)
784 VL.dump(TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for spill:"
; VL.dump(TRI); }; } } while (false)
785 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for spill:"
; VL.dump(TRI); }; } } while (false);
786 return;
787 }
788 case TransferKind::TransferRestore: {
789 assert(NewReg &&((NewReg && "No register supplied when handling a restore of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a restore of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 790, __PRETTY_FUNCTION__))
790 "No register supplied when handling a restore of a debug value")((NewReg && "No register supplied when handling a restore of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a restore of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 790, __PRETTY_FUNCTION__));
791 MachineFunction *MF = MI.getMF();
792 DIBuilder DIB(*const_cast<Function &>(MF->getFunction()).getParent());
793 // DebugInstr refers to the pre-spill location, therefore we can reuse
794 // its expression.
795 VarLoc VL = VarLoc::CreateCopyLoc(*DebugInstr, LS, NewReg);
796 ProcessVarLoc(VL);
797 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for restore:"
; VL.dump(TRI); }; } } while (false)
798 dbgs() << "Creating VarLoc for restore:";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for restore:"
; VL.dump(TRI); }; } } while (false)
799 VL.dump(TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for restore:"
; VL.dump(TRI); }; } } while (false)
800 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { dbgs() << "Creating VarLoc for restore:"
; VL.dump(TRI); }; } } while (false);
801 return;
802 }
803 }
804 llvm_unreachable("Invalid transfer kind")::llvm::llvm_unreachable_internal("Invalid transfer kind", "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 804);
805}
806
807/// A definition of a register may mark the end of a range.
808void LiveDebugValues::transferRegisterDef(
809 MachineInstr &MI, OpenRangesSet &OpenRanges, VarLocMap &VarLocIDs,
810 TransferMap &Transfers, DebugParamMap &DebugEntryVals) {
811 MachineFunction *MF = MI.getMF();
812 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
813 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
814 SparseBitVector<> KillSet;
815 for (const MachineOperand &MO : MI.operands()) {
816 // Determine whether the operand is a register def. Assume that call
817 // instructions never clobber SP, because some backends (e.g., AArch64)
818 // never list SP in the regmask.
819 if (MO.isReg() && MO.isDef() && MO.getReg() &&
820 Register::isPhysicalRegister(MO.getReg()) &&
821 !(MI.isCall() && MO.getReg() == SP)) {
822 // Remove ranges of all aliased registers.
823 for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
824 for (unsigned ID : OpenRanges.getVarLocs())
825 if (VarLocIDs[ID].isDescribedByReg() == *RAI)
826 KillSet.set(ID);
827 } else if (MO.isRegMask()) {
828 // Remove ranges of all clobbered registers. Register masks don't usually
829 // list SP as preserved. While the debug info may be off for an
830 // instruction or two around callee-cleanup calls, transferring the
831 // DEBUG_VALUE across the call is still a better user experience.
832 for (unsigned ID : OpenRanges.getVarLocs()) {
833 unsigned Reg = VarLocIDs[ID].isDescribedByReg();
834 if (Reg && Reg != SP && MO.clobbersPhysReg(Reg))
835 KillSet.set(ID);
836 }
837 }
838 }
839 OpenRanges.erase(KillSet, VarLocIDs);
840
841 if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>()) {
842 auto &TM = TPC->getTM<TargetMachine>();
843 if (TM.Options.EnableDebugEntryValues)
844 emitEntryValues(MI, OpenRanges, VarLocIDs, Transfers, DebugEntryVals,
845 KillSet);
846 }
847}
848
849bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
850 MachineFunction *MF) {
851 // TODO: Handle multiple stores folded into one.
852 if (!MI.hasOneMemOperand())
29
←
Calling 'MachineInstr::hasOneMemOperand'
→
32
←
Returning from 'MachineInstr::hasOneMemOperand'
→
33
←
Taking false branch
→
853 return false;
854
855 if (!MI.getSpillSize(TII) && !MI.getFoldedSpillSize(TII))
34
←
Assuming the condition is false
→
35
←
Taking false branch
→
856 return false; // This is not a spill instruction, since no valid size was
857 // returned from either function.
858
859 return true;
36
←
Returning the value 1, which participates in a condition later
→
860}
861
862bool LiveDebugValues::isLocationSpill(const MachineInstr &MI,
863 MachineFunction *MF, unsigned &Reg) {
864 if (!isSpillInstruction(MI, MF))
28
←
Calling 'LiveDebugValues::isSpillInstruction'
→
37
←
Returning from 'LiveDebugValues::isSpillInstruction'
→
38
←
Taking false branch
→
865 return false;
866
867 auto isKilledReg = [&](const MachineOperand MO, unsigned &Reg) {
868 if (!MO.isReg() || !MO.isUse()) {
869 Reg = 0;
870 return false;
41
←
Returning without writing to 'Reg'
→
42
←
Returning zero, which participates in a condition later
→
871 }
872 Reg = MO.getReg();
873 return MO.isKill();
874 };
875
876 for (const MachineOperand &MO : MI.operands()) {
39
←
Assuming '__begin1' is not equal to '__end1'
→
877 // In a spill instruction generated by the InlineSpiller the spilled
878 // register has its kill flag set.
879 if (isKilledReg(MO, Reg))
40
←
Calling 'operator()'
→
43
←
Returning from 'operator()'
→
44
←
Taking false branch
→
880 return true;
881 if (Reg != 0) {
45
←
The left operand of '!=' is a garbage value
882 // Check whether next instruction kills the spilled register.
883 // FIXME: Current solution does not cover search for killed register in
884 // bundles and instructions further down the chain.
885 auto NextI = std::next(MI.getIterator());
886 // Skip next instruction that points to basic block end iterator.
887 if (MI.getParent()->end() == NextI)
888 continue;
889 unsigned RegNext;
890 for (const MachineOperand &MONext : NextI->operands()) {
891 // Return true if we came across the register from the
892 // previous spill instruction that is killed in NextI.
893 if (isKilledReg(MONext, RegNext) && RegNext == Reg)
894 return true;
895 }
896 }
897 }
898 // Return false if we didn't find spilled register.
899 return false;
900}
901
902Optional<LiveDebugValues::VarLoc::SpillLoc>
903LiveDebugValues::isRestoreInstruction(const MachineInstr &MI,
904 MachineFunction *MF, unsigned &Reg) {
905 if (!MI.hasOneMemOperand())
906 return None;
907
908 // FIXME: Handle folded restore instructions with more than one memory
909 // operand.
910 if (MI.getRestoreSize(TII)) {
911 Reg = MI.getOperand(0).getReg();
912 return extractSpillBaseRegAndOffset(MI);
913 }
914 return None;
915}
916
917/// A spilled register may indicate that we have to end the current range of
918/// a variable and create a new one for the spill location.
919/// A restored register may indicate the reverse situation.
920/// We don't want to insert any instructions in process(), so we just create
921/// the DBG_VALUE without inserting it and keep track of it in \p Transfers.
922/// It will be inserted into the BB when we're done iterating over the
923/// instructions.
924void LiveDebugValues::transferSpillOrRestoreInst(MachineInstr &MI,
925 OpenRangesSet &OpenRanges,
926 VarLocMap &VarLocIDs,
927 TransferMap &Transfers) {
928 MachineFunction *MF = MI.getMF();
929 TransferKind TKind;
930 unsigned Reg;
22
←
'Reg' declared without an initial value
→
931 Optional<VarLoc::SpillLoc> Loc;
932
933 LLVM_DEBUG(dbgs() << "Examining instruction: "; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Examining instruction: "
; MI.dump();; } } while (false);
23
←
Assuming 'DebugFlag' is false
→
24
←
Loop condition is false. Exiting loop
→
934
935 // First, if there are any DBG_VALUEs pointing at a spill slot that is
936 // written to, then close the variable location. The value in memory
937 // will have changed.
938 VarLocSet KillSet;
939 if (isSpillInstruction(MI, MF)) {
25
←
Taking false branch
→
940 Loc = extractSpillBaseRegAndOffset(MI);
941 for (unsigned ID : OpenRanges.getVarLocs()) {
942 const VarLoc &VL = VarLocIDs[ID];
943 if (VL.Kind == VarLoc::SpillLocKind && VL.Loc.SpillLocation == *Loc) {
944 // This location is overwritten by the current instruction -- terminate
945 // the open range, and insert an explicit DBG_VALUE $noreg.
946 //
947 // Doing this at a later stage would require re-interpreting all
948 // DBG_VALUes and DIExpressions to identify whether they point at
949 // memory, and then analysing all memory writes to see if they
950 // overwrite that memory, which is expensive.
951 //
952 // At this stage, we already know which DBG_VALUEs are for spills and
953 // where they are located; it's best to fix handle overwrites now.
954 KillSet.set(ID);
955 VarLoc UndefVL = VarLoc::CreateCopyLoc(VL.MI, LS, 0);
956 unsigned UndefLocID = VarLocIDs.insert(UndefVL);
957 Transfers.push_back({&MI, UndefLocID});
958 }
959 }
960 OpenRanges.erase(KillSet, VarLocIDs);
961 }
962
963 // Try to recognise spill and restore instructions that may create a new
964 // variable location.
965 if (isLocationSpill(MI, MF, Reg)) {
26
←
Passing value via 3rd parameter 'Reg'
→
27
←
Calling 'LiveDebugValues::isLocationSpill'
→
966 TKind = TransferKind::TransferSpill;
967 LLVM_DEBUG(dbgs() << "Recognized as spill: "; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Recognized as spill: "
; MI.dump();; } } while (false);
968 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false)
969 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false);
970 } else {
971 if (!(Loc = isRestoreInstruction(MI, MF, Reg)))
972 return;
973 TKind = TransferKind::TransferRestore;
974 LLVM_DEBUG(dbgs() << "Recognized as restore: "; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Recognized as restore: "
; MI.dump();; } } while (false);
975 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false)
976 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false);
977 }
978 // Check if the register or spill location is the location of a debug value.
979 for (unsigned ID : OpenRanges.getVarLocs()) {
980 if (TKind == TransferKind::TransferSpill &&
981 VarLocIDs[ID].isDescribedByReg() == Reg) {
982 LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Spilling Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false)
983 << VarLocIDs[ID].Var.getVar()->getName() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Spilling Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false);
984 } else if (TKind == TransferKind::TransferRestore &&
985 VarLocIDs[ID].Kind == VarLoc::SpillLocKind &&
986 VarLocIDs[ID].Loc.SpillLocation == *Loc) {
987 LLVM_DEBUG(dbgs() << "Restoring Register " << printReg(Reg, TRI) << '('do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Restoring Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false)
988 << VarLocIDs[ID].Var.getVar()->getName() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Restoring Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false);
989 } else
990 continue;
991 insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID, TKind,
992 Reg);
993 return;
994 }
995}
996
997/// If \p MI is a register copy instruction, that copies a previously tracked
998/// value from one register to another register that is callee saved, we
999/// create new DBG_VALUE instruction described with copy destination register.
1000void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
1001 OpenRangesSet &OpenRanges,
1002 VarLocMap &VarLocIDs,
1003 TransferMap &Transfers) {
1004 const MachineOperand *SrcRegOp, *DestRegOp;
1005
1006 if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
1007 !DestRegOp->isDef())
1008 return;
1009
1010 auto isCalleSavedReg = [&](unsigned Reg) {
1011 for (MCRegAliasIterator RAI(Reg, TRI, true); RAI.isValid(); ++RAI)
1012 if (CalleeSavedRegs.test(*RAI))
1013 return true;
1014 return false;
1015 };
1016
1017 Register SrcReg = SrcRegOp->getReg();
1018 Register DestReg = DestRegOp->getReg();
1019
1020 // We want to recognize instructions where destination register is callee
1021 // saved register. If register that could be clobbered by the call is
1022 // included, there would be a great chance that it is going to be clobbered
1023 // soon. It is more likely that previous register location, which is callee
1024 // saved, is going to stay unclobbered longer, even if it is killed.
1025 if (!isCalleSavedReg(DestReg))
1026 return;
1027
1028 for (unsigned ID : OpenRanges.getVarLocs()) {
1029 if (VarLocIDs[ID].isDescribedByReg() == SrcReg) {
1030 insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID,
1031 TransferKind::TransferCopy, DestReg);
1032 return;
1033 }
1034 }
1035}
1036
1037/// Terminate all open ranges at the end of the current basic block.
1038bool LiveDebugValues::transferTerminator(MachineBasicBlock *CurMBB,
1039 OpenRangesSet &OpenRanges,
1040 VarLocInMBB &OutLocs,
1041 const VarLocMap &VarLocIDs) {
1042 bool Changed = false;
1043
1044 LLVM_DEBUG(for (unsigned IDdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(TRI); }; }
} while (false)
1045 : OpenRanges.getVarLocs()) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(TRI); }; }
} while (false)
1046 // Copy OpenRanges to OutLocs, if not already present.do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(TRI); }; }
} while (false)
1047 dbgs() << "Add to OutLocs in MBB #" << CurMBB->getNumber() << ": ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(TRI); }; }
} while (false)
1048 VarLocIDs[ID].dump(TRI);do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(TRI); }; }
} while (false)
1049 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(TRI); }; }
} while (false);
1050 VarLocSet &VLS = OutLocs[CurMBB];
1051 Changed = VLS != OpenRanges.getVarLocs();
1052 // New OutLocs set may be different due to spill, restore or register
1053 // copy instruction processing.
1054 if (Changed)
1055 VLS = OpenRanges.getVarLocs();
1056 OpenRanges.clear();
1057 return Changed;
1058}
1059
1060/// Accumulate a mapping between each DILocalVariable fragment and other
1061/// fragments of that DILocalVariable which overlap. This reduces work during
1062/// the data-flow stage from "Find any overlapping fragments" to "Check if the
1063/// known-to-overlap fragments are present".
1064/// \param MI A previously unprocessed DEBUG_VALUE instruction to analyze for
1065/// fragment usage.
1066/// \param SeenFragments Map from DILocalVariable to all fragments of that
1067/// Variable which are known to exist.
1068/// \param OverlappingFragments The overlap map being constructed, from one
1069/// Var/Fragment pair to a vector of fragments known to overlap.
1070void LiveDebugValues::accumulateFragmentMap(MachineInstr &MI,
1071 VarToFragments &SeenFragments,
1072 OverlapMap &OverlappingFragments) {
1073 DebugVariable MIVar(MI);
1074 FragmentInfo ThisFragment = MIVar.getFragmentDefault();
1075
1076 // If this is the first sighting of this variable, then we are guaranteed
1077 // there are currently no overlapping fragments either. Initialize the set
1078 // of seen fragments, record no overlaps for the current one, and return.
1079 auto SeenIt = SeenFragments.find(MIVar.getVar());
1080 if (SeenIt == SeenFragments.end()) {
1081 SmallSet<FragmentInfo, 4> OneFragment;
1082 OneFragment.insert(ThisFragment);
1083 SeenFragments.insert({MIVar.getVar(), OneFragment});
1084
1085 OverlappingFragments.insert({{MIVar.getVar(), ThisFragment}, {}});
1086 return;
1087 }
1088
1089 // If this particular Variable/Fragment pair already exists in the overlap
1090 // map, it has already been accounted for.
1091 auto IsInOLapMap =
1092 OverlappingFragments.insert({{MIVar.getVar(), ThisFragment}, {}});
1093 if (!IsInOLapMap.second)
1094 return;
1095
1096 auto &ThisFragmentsOverlaps = IsInOLapMap.first->second;
1097 auto &AllSeenFragments = SeenIt->second;
1098
1099 // Otherwise, examine all other seen fragments for this variable, with "this"
1100 // fragment being a previously unseen fragment. Record any pair of
1101 // overlapping fragments.
1102 for (auto &ASeenFragment : AllSeenFragments) {
1103 // Does this previously seen fragment overlap?
1104 if (DIExpression::fragmentsOverlap(ThisFragment, ASeenFragment)) {
1105 // Yes: Mark the current fragment as being overlapped.
1106 ThisFragmentsOverlaps.push_back(ASeenFragment);
1107 // Mark the previously seen fragment as being overlapped by the current
1108 // one.
1109 auto ASeenFragmentsOverlaps =
1110 OverlappingFragments.find({MIVar.getVar(), ASeenFragment});
1111 assert(ASeenFragmentsOverlaps != OverlappingFragments.end() &&((ASeenFragmentsOverlaps != OverlappingFragments.end() &&
"Previously seen var fragment has no vector of overlaps") ? static_cast
<void> (0) : __assert_fail ("ASeenFragmentsOverlaps != OverlappingFragments.end() && \"Previously seen var fragment has no vector of overlaps\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 1112, __PRETTY_FUNCTION__))
1112 "Previously seen var fragment has no vector of overlaps")((ASeenFragmentsOverlaps != OverlappingFragments.end() &&
"Previously seen var fragment has no vector of overlaps") ? static_cast
<void> (0) : __assert_fail ("ASeenFragmentsOverlaps != OverlappingFragments.end() && \"Previously seen var fragment has no vector of overlaps\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 1112, __PRETTY_FUNCTION__));
1113 ASeenFragmentsOverlaps->second.push_back(ThisFragment);
1114 }
1115 }
1116
1117 AllSeenFragments.insert(ThisFragment);
1118}
1119
1120/// This routine creates OpenRanges and OutLocs.
1121void LiveDebugValues::process(MachineInstr &MI, OpenRangesSet &OpenRanges,
1122 VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
1123 TransferMap &Transfers,
1124 DebugParamMap &DebugEntryVals,
1125 OverlapMap &OverlapFragments,
1126 VarToFragments &SeenFragments) {
1127 transferDebugValue(MI, OpenRanges, VarLocIDs);
1128 transferRegisterDef(MI, OpenRanges, VarLocIDs, Transfers,
1129 DebugEntryVals);
1130 transferRegisterCopy(MI, OpenRanges, VarLocIDs, Transfers);
1131 transferSpillOrRestoreInst(MI, OpenRanges, VarLocIDs, Transfers);
21
←
Calling 'LiveDebugValues::transferSpillOrRestoreInst'
→
1132}
1133
1134/// This routine joins the analysis results of all incoming edges in @MBB by
1135/// inserting a new DBG_VALUE instruction at the start of the @MBB - if the same
1136/// source variable in all the predecessors of @MBB reside in the same location.
1137bool LiveDebugValues::join(
1138 MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
1139 const VarLocMap &VarLocIDs,
1140 SmallPtrSet<const MachineBasicBlock *, 16> &Visited,
1141 SmallPtrSetImpl<const MachineBasicBlock *> &ArtificialBlocks,
1142 VarLocInMBB &PendingInLocs) {
1143 LLVM_DEBUG(dbgs() << "join MBB: " << MBB.getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "join MBB: " << MBB
.getNumber() << "\n"; } } while (false);
1144 bool Changed = false;
1145
1146 VarLocSet InLocsT; // Temporary incoming locations.
1147
1148 // For all predecessors of this MBB, find the set of VarLocs that
1149 // can be joined.
1150 int NumVisited = 0;
1151 for (auto p : MBB.predecessors()) {
1152 // Ignore backedges if we have not visited the predecessor yet. As the
1153 // predecessor hasn't yet had locations propagated into it, most locations
1154 // will not yet be valid, so treat them as all being uninitialized and
1155 // potentially valid. If a location guessed to be correct here is
1156 // invalidated later, we will remove it when we revisit this block.
1157 if (!Visited.count(p)) {
1158 LLVM_DEBUG(dbgs() << " ignoring unvisited pred MBB: " << p->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << " ignoring unvisited pred MBB: "
<< p->getNumber() << "\n"; } } while (false)
1159 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << " ignoring unvisited pred MBB: "
<< p->getNumber() << "\n"; } } while (false);
1160 continue;
1161 }
1162 auto OL = OutLocs.find(p);
1163 // Join is null in case of empty OutLocs from any of the pred.
1164 if (OL == OutLocs.end())
1165 return false;
1166
1167 // Just copy over the Out locs to incoming locs for the first visited
1168 // predecessor, and for all other predecessors join the Out locs.
1169 if (!NumVisited)
1170 InLocsT = OL->second;
1171 else
1172 InLocsT &= OL->second;
1173
1174 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1175 if (!InLocsT.empty()) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1176 for (auto ID : InLocsT)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1177 dbgs() << " gathered candidate incoming var: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1178 << VarLocIDs[ID].Var.getVar()->getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1179 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1180 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false);
1181
1182 NumVisited++;
1183 }
1184
1185 // Filter out DBG_VALUES that are out of scope.
1186 VarLocSet KillSet;
1187 bool IsArtificial = ArtificialBlocks.count(&MBB);
1188 if (!IsArtificial) {
1189 for (auto ID : InLocsT) {
1190 if (!VarLocIDs[ID].dominates(MBB)) {
1191 KillSet.set(ID);
1192 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
1193 auto Name = VarLocIDs[ID].Var.getVar()->getName();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
1194 dbgs() << " killing " << Name << ", it doesn't dominate MBB\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
1195 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false);
1196 }
1197 }
1198 }
1199 InLocsT.intersectWithComplement(KillSet);
1200
1201 // As we are processing blocks in reverse post-order we
1202 // should have processed at least one predecessor, unless it
1203 // is the entry block which has no predecessor.
1204 assert((NumVisited || MBB.pred_empty()) &&(((NumVisited || MBB.pred_empty()) && "Should have processed at least one predecessor"
) ? static_cast<void> (0) : __assert_fail ("(NumVisited || MBB.pred_empty()) && \"Should have processed at least one predecessor\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 1205, __PRETTY_FUNCTION__))
1205 "Should have processed at least one predecessor")(((NumVisited || MBB.pred_empty()) && "Should have processed at least one predecessor"
) ? static_cast<void> (0) : __assert_fail ("(NumVisited || MBB.pred_empty()) && \"Should have processed at least one predecessor\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 1205, __PRETTY_FUNCTION__));
1206
1207 VarLocSet &ILS = InLocs[&MBB];
1208 VarLocSet &Pending = PendingInLocs[&MBB];
1209
1210 // New locations will have DBG_VALUE insts inserted at the start of the
1211 // block, after location propagation has finished. Record the insertions
1212 // that we need to perform in the Pending set.
1213 VarLocSet Diff = InLocsT;
1214 Diff.intersectWithComplement(ILS);
1215 for (auto ID : Diff) {
1216 Pending.set(ID);
1217 ILS.set(ID);
1218 ++NumInserted;
1219 Changed = true;
1220 }
1221
1222 // We may have lost locations by learning about a predecessor that either
1223 // loses or moves a variable. Find any locations in ILS that are not in the
1224 // new in-locations, and delete those.
1225 VarLocSet Removed = ILS;
1226 Removed.intersectWithComplement(InLocsT);
1227 for (auto ID : Removed) {
1228 Pending.reset(ID);
1229 ILS.reset(ID);
1230 ++NumRemoved;
1231 Changed = true;
1232 }
1233
1234 return Changed;
1235}
1236
1237void LiveDebugValues::flushPendingLocs(VarLocInMBB &PendingInLocs,
1238 VarLocMap &VarLocIDs) {
1239 // PendingInLocs records all locations propagated into blocks, which have
1240 // not had DBG_VALUE insts created. Go through and create those insts now.
1241 for (auto &Iter : PendingInLocs) {
1242 // Map is keyed on a constant pointer, unwrap it so we can insert insts.
1243 auto &MBB = const_cast<MachineBasicBlock &>(*Iter.first);
1244 VarLocSet &Pending = Iter.second;
1245
1246 for (unsigned ID : Pending) {
1247 // The ID location is live-in to MBB -- work out what kind of machine
1248 // location it is and create a DBG_VALUE.
1249 const VarLoc &DiffIt = VarLocIDs[ID];
1250 MachineInstr *MI = DiffIt.BuildDbgValue(*MBB.getParent());
1251 MBB.insert(MBB.instr_begin(), MI);
1252
1253 (void)MI;
1254 LLVM_DEBUG(dbgs() << "Inserted: "; MI->dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Inserted: "; MI->dump
();; } } while (false);
1255 }
1256 }
1257}
1258
1259/// Calculate the liveness information for the given machine function and
1260/// extend ranges across basic blocks.
1261bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
1262 LLVM_DEBUG(dbgs() << "\nDebug Range Extension\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "\nDebug Range Extension\n"
; } } while (false);
6
←
Assuming 'DebugFlag' is false
→
7
←
Loop condition is false. Exiting loop
→
1263
1264 bool Changed = false;
1265 bool OLChanged = false;
1266 bool MBBJoined = false;
1267
1268 VarLocMap VarLocIDs; // Map VarLoc<>unique ID for use in bitvectors.
1269 OverlapMap OverlapFragments; // Map of overlapping variable fragments
1270 OpenRangesSet OpenRanges(OverlapFragments);
1271 // Ranges that are open until end of bb.
1272 VarLocInMBB OutLocs; // Ranges that exist beyond bb.
1273 VarLocInMBB InLocs; // Ranges that are incoming after joining.
1274 TransferMap Transfers; // DBG_VALUEs associated with spills.
1275 VarLocInMBB PendingInLocs; // Ranges that are incoming after joining, but
1276 // that we have deferred creating DBG_VALUE insts
1277 // for immediately.
1278
1279 VarToFragments SeenFragments;
1280
1281 // Blocks which are artificial, i.e. blocks which exclusively contain
1282 // instructions without locations, or with line 0 locations.
1283 SmallPtrSet<const MachineBasicBlock *, 16> ArtificialBlocks;
1284
1285 DenseMap<unsigned int, MachineBasicBlock *> OrderToBB;
1286 DenseMap<MachineBasicBlock *, unsigned int> BBToOrder;
1287 std::priority_queue<unsigned int, std::vector<unsigned int>,
1288 std::greater<unsigned int>>
1289 Worklist;
1290 std::priority_queue<unsigned int, std::vector<unsigned int>,
1291 std::greater<unsigned int>>
1292 Pending;
1293
1294 // Besides parameter's modification, check whether a DBG_VALUE is inlined
1295 // in order to deduce whether the variable that it tracks comes from
1296 // a different function. If that is the case we can't track its entry value.
1297 auto IsUnmodifiedFuncParam = [&](const MachineInstr &MI) {
1298 auto *DIVar = MI.getDebugVariable();
1299 return DIVar->isParameter() && DIVar->isNotModified() &&
1300 !MI.getDebugLoc()->getInlinedAt();
1301 };
1302
1303 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
1304 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
1305 Register FP = TRI->getFrameRegister(MF);
1306 auto IsRegOtherThanSPAndFP = [&](const MachineOperand &Op) -> bool {
1307 return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
1308 };
1309
1310 // Working set of currently collected debug variables mapped to DBG_VALUEs
1311 // representing candidates for production of debug entry values.
1312 DebugParamMap DebugEntryVals;
1313
1314 MachineBasicBlock &First_MBB = *(MF.begin());
1315 // Only in the case of entry MBB collect DBG_VALUEs representing
1316 // function parameters in order to generate debug entry values for them.
1317 // Currently, we generate debug entry values only for parameters that are
1318 // unmodified throughout the function and located in a register.
1319 // TODO: Add support for parameters that are described as fragments.
1320 // TODO: Add support for modified arguments that can be expressed
1321 // by using its entry value.
1322 // TODO: Add support for local variables that are expressed in terms of
1323 // parameters entry values.
1324 for (auto &MI : First_MBB)
1325 if (MI.isDebugValue() && IsUnmodifiedFuncParam(MI) &&
1326 !MI.isIndirectDebugValue() && IsRegOtherThanSPAndFP(MI.getOperand(0)) &&
1327 !DebugEntryVals.count(MI.getDebugVariable()) &&
1328 !MI.getDebugExpression()->isFragment())
1329 DebugEntryVals[MI.getDebugVariable()] = &MI;
1330
1331 // Initialize per-block structures and scan for fragment overlaps.
1332 for (auto &MBB : MF) {
1333 PendingInLocs[&MBB] = VarLocSet();
1334
1335 for (auto &MI : MBB) {
1336 if (MI.isDebugValue())
1337 accumulateFragmentMap(MI, SeenFragments, OverlapFragments);
1338 }
1339 }
1340
1341 auto hasNonArtificialLocation = [](const MachineInstr &MI) -> bool {
1342 if (const DebugLoc &DL = MI.getDebugLoc())
1343 return DL.getLine() != 0;
1344 return false;
1345 };
1346 for (auto &MBB : MF)
1347 if (none_of(MBB.instrs(), hasNonArtificialLocation))
1348 ArtificialBlocks.insert(&MBB);
1349
1350 LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after initialization", dbgs()); } } while (false)
8
←
Assuming 'DebugFlag' is false
→
9
←
Loop condition is false. Exiting loop
→
1351 "OutLocs after initialization", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after initialization", dbgs()); } } while (false);
1352
1353 ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
1354 unsigned int RPONumber = 0;
1355 for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
10
←
Loop condition is false. Execution continues on line 1365
→
1356 OrderToBB[RPONumber] = *RI;
1357 BBToOrder[*RI] = RPONumber;
1358 Worklist.push(RPONumber);
1359 ++RPONumber;
1360 }
1361 // This is a standard "union of predecessor outs" dataflow problem.
1362 // To solve it, we perform join() and process() using the two worklist method
1363 // until the ranges converge.
1364 // Ranges have converged when both worklists are empty.
1365 SmallPtrSet<const MachineBasicBlock *, 16> Visited;
1366 while (!Worklist.empty() || !Pending.empty()) {
11
←
Assuming the condition is false
→
12
←
Assuming the condition is true
→
13
←
Loop condition is true. Entering loop body
→
1367 // We track what is on the pending worklist to avoid inserting the same
1368 // thing twice. We could avoid this with a custom priority queue, but this
1369 // is probably not worth it.
1370 SmallPtrSet<MachineBasicBlock *, 16> OnPending;
1371 LLVM_DEBUG(dbgs() << "Processing Worklist\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Processing Worklist\n"
; } } while (false);
14
←
Assuming 'DebugFlag' is false
→
15
←
Loop condition is false. Exiting loop
→
1372 while (!Worklist.empty()) {
16
←
Assuming the condition is true
→
17
←
Loop condition is true. Entering loop body
→
1373 MachineBasicBlock *MBB = OrderToBB[Worklist.top()];
1374 Worklist.pop();
1375 MBBJoined = join(*MBB, OutLocs, InLocs, VarLocIDs, Visited,
1376 ArtificialBlocks, PendingInLocs);
1377 MBBJoined |= Visited.insert(MBB).second;
1378 if (MBBJoined) {
18
←
Assuming 'MBBJoined' is true
→
19
←
Taking true branch
→
1379 MBBJoined = false;
1380 Changed = true;
1381 // Now that we have started to extend ranges across BBs we need to
1382 // examine spill instructions to see whether they spill registers that
1383 // correspond to user variables.
1384 // First load any pending inlocs.
1385 OpenRanges.insertFromLocSet(PendingInLocs[MBB], VarLocIDs);
1386 for (auto &MI : *MBB)
1387 process(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
20
←
Calling 'LiveDebugValues::process'
→
1388 DebugEntryVals, OverlapFragments, SeenFragments);
1389 OLChanged |= transferTerminator(MBB, OpenRanges, OutLocs, VarLocIDs);
1390
1391 LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after propagating", dbgs()); } } while (false)
1392 "OutLocs after propagating", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after propagating", dbgs()); } } while (false);
1393 LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, InLocs, VarLocIDs
, "InLocs after propagating", dbgs()); } } while (false)
1394 "InLocs after propagating", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, InLocs, VarLocIDs
, "InLocs after propagating", dbgs()); } } while (false);
1395
1396 if (OLChanged) {
1397 OLChanged = false;
1398 for (auto s : MBB->successors())
1399 if (OnPending.insert(s).second) {
1400 Pending.push(BBToOrder[s]);
1401 }
1402 }
1403 }
1404 }
1405 Worklist.swap(Pending);
1406 // At this point, pending must be empty, since it was just the empty
1407 // worklist
1408 assert(Pending.empty() && "Pending should be empty")((Pending.empty() && "Pending should be empty") ? static_cast
<void> (0) : __assert_fail ("Pending.empty() && \"Pending should be empty\""
, "/build/llvm-toolchain-snapshot-10~svn374877/lib/CodeGen/LiveDebugValues.cpp"
, 1408, __PRETTY_FUNCTION__));
1409 }
1410
1411 // Add any DBG_VALUE instructions created by location transfers.
1412 for (auto &TR : Transfers) {
1413 MachineBasicBlock *MBB = TR.TransferInst->getParent();
1414 const VarLoc &VL = VarLocIDs[TR.LocationID];
1415 MachineInstr *MI = VL.BuildDbgValue(MF);
1416 MBB->insertAfterBundle(TR.TransferInst->getIterator(), MI);
1417 }
1418 Transfers.clear();
1419
1420 // Deferred inlocs will not have had any DBG_VALUE insts created; do
1421 // that now.
1422 flushPendingLocs(PendingInLocs, VarLocIDs);
1423
1424 LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "Final OutLocs", dbgs()); } } while (false);
1425 LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, InLocs, VarLocIDs
, "Final InLocs", dbgs()); } } while (false);
1426 return Changed;
1427}
1428
1429bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
1430 if (!MF.getFunction().getSubprogram())
1
Assuming the condition is false
→
2
←
Taking false branch
→
1431 // LiveDebugValues will already have removed all DBG_VALUEs.
1432 return false;
1433
1434 // Skip functions from NoDebug compilation units.
1435 if (MF.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
3
←
Assuming the condition is false
→
4
←
Taking false branch
→
1436 DICompileUnit::NoDebug)
1437 return false;
1438
1439 TRI = MF.getSubtarget().getRegisterInfo();
1440 TII = MF.getSubtarget().getInstrInfo();
1441 TFI = MF.getSubtarget().getFrameLowering();
1442 TFI->determineCalleeSaves(MF, CalleeSavedRegs,
1443 std::make_unique<RegScavenger>().get());
1444 LS.initialize(MF);
1445
1446 bool Changed = ExtendRanges(MF);
5
←
Calling 'LiveDebugValues::ExtendRanges'
→
1447 return Changed;
1448}
←

/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h

1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
22#include "llvm/ADT/iterator_range.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DebugInfoMetadata.h"
28#include "llvm/IR/DebugLoc.h"
29#include "llvm/IR/InlineAsm.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Support/ArrayRecycler.h"
33#include "llvm/Support/TrailingObjects.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41template <typename T> class ArrayRef;
42class DIExpression;
43class DILocalVariable;
44class MachineBasicBlock;
45class MachineFunction;
46class MachineMemOperand;
47class MachineRegisterInfo;
48class ModuleSlotTracker;
49class raw_ostream;
50template <typename T> class SmallVectorImpl;
51class SmallBitVector;
52class StringRef;
53class TargetInstrInfo;
54class TargetRegisterClass;
55class TargetRegisterInfo;
56
57//===----------------------------------------------------------------------===//
58/// Representation of each machine instruction.
59///
60/// This class isn't a POD type, but it must have a trivial destructor. When a
61/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62/// without having their destructor called.
63///
64class MachineInstr
65 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66 ilist_sentinel_tracking<true>> {
67public:
68 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
69
70 /// Flags to specify different kinds of comments to output in
71 /// assembly code. These flags carry semantic information not
72 /// otherwise easily derivable from the IR text.
73 ///
74 enum CommentFlag {
75 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
76 NoSchedComment = 0x2,
77 TAsmComments = 0x4 // Target Asm comments should start from this value.
78 };
79
80 enum MIFlag {
81 NoFlags = 0,
82 FrameSetup = 1 << 0, // Instruction is used as a part of
83 // function frame setup code.
84 FrameDestroy = 1 << 1, // Instruction is used as a part of
85 // function frame destruction code.
86 BundledPred = 1 << 2, // Instruction has bundled predecessors.
87 BundledSucc = 1 << 3, // Instruction has bundled successors.
88 FmNoNans = 1 << 4, // Instruction does not support Fast
89 // math nan values.
90 FmNoInfs = 1 << 5, // Instruction does not support Fast
91 // math infinity values.
92 FmNsz = 1 << 6, // Instruction is not required to retain
93 // signed zero values.
94 FmArcp = 1 << 7, // Instruction supports Fast math
95 // reciprocal approximations.
96 FmContract = 1 << 8, // Instruction supports Fast math
97 // contraction operations like fma.
98 FmAfn = 1 << 9, // Instruction may map to Fast math
99 // instrinsic approximation.
100 FmReassoc = 1 << 10, // Instruction supports Fast math
101 // reassociation of operand order.
102 NoUWrap = 1 << 11, // Instruction supports binary operator
103 // no unsigned wrap.
104 NoSWrap = 1 << 12, // Instruction supports binary operator
105 // no signed wrap.
106 IsExact = 1 << 13, // Instruction supports division is
107 // known to be exact.
108 FPExcept = 1 << 14, // Instruction may raise floating-point
109 // exceptions.
110 };
111
112private:
113 const MCInstrDesc *MCID; // Instruction descriptor.
114 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
115
116 // Operands are allocated by an ArrayRecycler.
117 MachineOperand *Operands = nullptr; // Pointer to the first operand.
118 unsigned NumOperands = 0; // Number of operands on instruction.
119 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
120 OperandCapacity CapOperands; // Capacity of the Operands array.
121
122 uint16_t Flags = 0; // Various bits of additional
123 // information about machine
124 // instruction.
125
126 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
127 // the AsmPrinter to emit helpful
128 // comments. This is *not* semantic
129 // information. Do not use this for
130 // anything other than to convey comment
131 // information to AsmPrinter.
132
133 /// Internal implementation detail class that provides out-of-line storage for
134 /// extra info used by the machine instruction when this info cannot be stored
135 /// in-line within the instruction itself.
136 ///
137 /// This has to be defined eagerly due to the implementation constraints of
138 /// `PointerSumType` where it is used.
139 class ExtraInfo final
140 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
141 public:
142 static ExtraInfo *create(BumpPtrAllocator &Allocator,
143 ArrayRef<MachineMemOperand *> MMOs,
144 MCSymbol *PreInstrSymbol = nullptr,
145 MCSymbol *PostInstrSymbol = nullptr) {
146 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
147 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
148 auto *Result = new (Allocator.Allocate(
149 totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
150 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
151 alignof(ExtraInfo)))
152 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
153
154 // Copy the actual data into the trailing objects.
155 std::copy(MMOs.begin(), MMOs.end(),
156 Result->getTrailingObjects<MachineMemOperand *>());
157
158 if (HasPreInstrSymbol)
159 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
160 if (HasPostInstrSymbol)
161 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
162 PostInstrSymbol;
163
164 return Result;
165 }
166
167 ArrayRef<MachineMemOperand *> getMMOs() const {
168 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
169 }
170
171 MCSymbol *getPreInstrSymbol() const {
172 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
173 }
174
175 MCSymbol *getPostInstrSymbol() const {
176 return HasPostInstrSymbol
177 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
178 : nullptr;
179 }
180
181 private:
182 friend TrailingObjects;
183
184 // Description of the extra info, used to interpret the actual optional
185 // data appended.
186 //
187 // Note that this is not terribly space optimized. This leaves a great deal
188 // of flexibility to fit more in here later.
189 const int NumMMOs;
190 const bool HasPreInstrSymbol;
191 const bool HasPostInstrSymbol;
192
193 // Implement the `TrailingObjects` internal API.
194 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
195 return NumMMOs;
196 }
197 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
198 return HasPreInstrSymbol + HasPostInstrSymbol;
199 }
200
201 // Just a boring constructor to allow us to initialize the sizes. Always use
202 // the `create` routine above.
203 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
204 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
205 HasPostInstrSymbol(HasPostInstrSymbol) {}
206 };
207
208 /// Enumeration of the kinds of inline extra info available. It is important
209 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
210 /// it accessible as an `ArrayRef`.
211 enum ExtraInfoInlineKinds {
212 EIIK_MMO = 0,
213 EIIK_PreInstrSymbol,
214 EIIK_PostInstrSymbol,
215 EIIK_OutOfLine
216 };
217
218 // We store extra information about the instruction here. The common case is
219 // expected to be nothing or a single pointer (typically a MMO or a symbol).
220 // We work to optimize this common case by storing it inline here rather than
221 // requiring a separate allocation, but we fall back to an allocation when
222 // multiple pointers are needed.
223 PointerSumType<ExtraInfoInlineKinds,
224 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
225 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
226 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
227 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
228 Info;
229
230 DebugLoc debugLoc; // Source line information.
231
232 // Intrusive list support
233 friend struct ilist_traits<MachineInstr>;
234 friend struct ilist_callback_traits<MachineBasicBlock>;
235 void setParent(MachineBasicBlock *P) { Parent = P; }
236
237 /// This constructor creates a copy of the given
238 /// MachineInstr in the given MachineFunction.
239 MachineInstr(MachineFunction &, const MachineInstr &);
240
241 /// This constructor create a MachineInstr and add the implicit operands.
242 /// It reserves space for number of operands specified by
243 /// MCInstrDesc. An explicit DebugLoc is supplied.
244 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
245 bool NoImp = false);
246
247 // MachineInstrs are pool-allocated and owned by MachineFunction.
248 friend class MachineFunction;
249
250public:
251 MachineInstr(const MachineInstr &) = delete;
252 MachineInstr &operator=(const MachineInstr &) = delete;
253 // Use MachineFunction::DeleteMachineInstr() instead.
254 ~MachineInstr() = delete;
255
256 const MachineBasicBlock* getParent() const { return Parent; }
257 MachineBasicBlock* getParent() { return Parent; }
258
259 /// Return the function that contains the basic block that this instruction
260 /// belongs to.
261 ///
262 /// Note: this is undefined behaviour if the instruction does not have a
263 /// parent.
264 const MachineFunction *getMF() const;
265 MachineFunction *getMF() {
266 return const_cast<MachineFunction *>(
267 static_cast<const MachineInstr *>(this)->getMF());
268 }
269
270 /// Return the asm printer flags bitvector.
271 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
272
273 /// Clear the AsmPrinter bitvector.
274 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
275
276 /// Return whether an AsmPrinter flag is set.
277 bool getAsmPrinterFlag(CommentFlag Flag) const {
278 return AsmPrinterFlags & Flag;
279 }
280
281 /// Set a flag for the AsmPrinter.
282 void setAsmPrinterFlag(uint8_t Flag) {
283 AsmPrinterFlags |= Flag;
284 }
285
286 /// Clear specific AsmPrinter flags.
287 void clearAsmPrinterFlag(CommentFlag Flag) {
288 AsmPrinterFlags &= ~Flag;
289 }
290
291 /// Return the MI flags bitvector.
292 uint16_t getFlags() const {
293 return Flags;
294 }
295
296 /// Return whether an MI flag is set.
297 bool getFlag(MIFlag Flag) const {
298 return Flags & Flag;
299 }
300
301 /// Set a MI flag.
302 void setFlag(MIFlag Flag) {
303 Flags |= (uint16_t)Flag;
304 }
305
306 void setFlags(unsigned flags) {
307 // Filter out the automatically maintained flags.
308 unsigned Mask = BundledPred | BundledSucc;
309 Flags = (Flags & Mask) | (flags & ~Mask);
310 }
311
312 /// clearFlag - Clear a MI flag.
313 void clearFlag(MIFlag Flag) {
314 Flags &= ~((uint16_t)Flag);
315 }
316
317 /// Return true if MI is in a bundle (but not the first MI in a bundle).
318 ///
319 /// A bundle looks like this before it's finalized:
320 /// ----------------
321 /// | MI |
322 /// ----------------
323 /// |
324 /// ----------------
325 /// | MI * |
326 /// ----------------
327 /// |
328 /// ----------------
329 /// | MI * |
330 /// ----------------
331 /// In this case, the first MI starts a bundle but is not inside a bundle, the
332 /// next 2 MIs are considered "inside" the bundle.
333 ///
334 /// After a bundle is finalized, it looks like this:
335 /// ----------------
336 /// | Bundle |
337 /// ----------------
338 /// |
339 /// ----------------
340 /// | MI * |
341 /// ----------------
342 /// |
343 /// ----------------
344 /// | MI * |
345 /// ----------------
346 /// |
347 /// ----------------
348 /// | MI * |
349 /// ----------------
350 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
351 /// a bundle, but the next three MIs are.
352 bool isInsideBundle() const {
353 return getFlag(BundledPred);
354 }
355
356 /// Return true if this instruction part of a bundle. This is true
357 /// if either itself or its following instruction is marked "InsideBundle".
358 bool isBundled() const {
359 return isBundledWithPred() || isBundledWithSucc();
360 }
361
362 /// Return true if this instruction is part of a bundle, and it is not the
363 /// first instruction in the bundle.
364 bool isBundledWithPred() const { return getFlag(BundledPred); }
365
366 /// Return true if this instruction is part of a bundle, and it is not the
367 /// last instruction in the bundle.
368 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
369
370 /// Bundle this instruction with its predecessor. This can be an unbundled
371 /// instruction, or it can be the first instruction in a bundle.
372 void bundleWithPred();
373
374 /// Bundle this instruction with its successor. This can be an unbundled
375 /// instruction, or it can be the last instruction in a bundle.
376 void bundleWithSucc();
377
378 /// Break bundle above this instruction.
379 void unbundleFromPred();
380
381 /// Break bundle below this instruction.
382 void unbundleFromSucc();
383
384 /// Returns the debug location id of this MachineInstr.
385 const DebugLoc &getDebugLoc() const { return debugLoc; }
386
387 /// Return the debug variable referenced by
388 /// this DBG_VALUE instruction.
389 const DILocalVariable *getDebugVariable() const;
390
391 /// Return the complex address expression referenced by
392 /// this DBG_VALUE instruction.
393 const DIExpression *getDebugExpression() const;
394
395 /// Return the debug label referenced by
396 /// this DBG_LABEL instruction.
397 const DILabel *getDebugLabel() const;
398
399 /// Emit an error referring to the source location of this instruction.
400 /// This should only be used for inline assembly that is somehow
401 /// impossible to compile. Other errors should have been handled much
402 /// earlier.
403 ///
404 /// If this method returns, the caller should try to recover from the error.
405 void emitError(StringRef Msg) const;
406
407 /// Returns the target instruction descriptor of this MachineInstr.
408 const MCInstrDesc &getDesc() const { return *MCID; }
409
410 /// Returns the opcode of this MachineInstr.
411 unsigned getOpcode() const { return MCID->Opcode; }
412
413 /// Retuns the total number of operands.
414 unsigned getNumOperands() const { return NumOperands; }
415
416 const MachineOperand& getOperand(unsigned i) const {
417 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 417, __PRETTY_FUNCTION__));
418 return Operands[i];
419 }
420 MachineOperand& getOperand(unsigned i) {
421 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 421, __PRETTY_FUNCTION__));
422 return Operands[i];
423 }
424
425 /// Returns the total number of definitions.
426 unsigned getNumDefs() const {
427 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
428 }
429
430 /// Returns true if the instruction has implicit definition.
431 bool hasImplicitDef() const {
432 for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
433 I != E; ++I) {
434 const MachineOperand &MO = getOperand(I);
435 if (MO.isDef() && MO.isImplicit())
436 return true;
437 }
438 return false;
439 }
440
441 /// Returns the implicit operands number.
442 unsigned getNumImplicitOperands() const {
443 return getNumOperands() - getNumExplicitOperands();
444 }
445
446 /// Return true if operand \p OpIdx is a subregister index.
447 bool isOperandSubregIdx(unsigned OpIdx) const {
448 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 449, __PRETTY_FUNCTION__))
449 "Expected MO_Immediate operand type.")((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 449, __PRETTY_FUNCTION__));
450 if (isExtractSubreg() && OpIdx == 2)
451 return true;
452 if (isInsertSubreg() && OpIdx == 3)
453 return true;
454 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
455 return true;
456 if (isSubregToReg() && OpIdx == 3)
457 return true;
458 return false;
459 }
460
461 /// Returns the number of non-implicit operands.
462 unsigned getNumExplicitOperands() const;
463
464 /// Returns the number of non-implicit definitions.
465 unsigned getNumExplicitDefs() const;
466
467 /// iterator/begin/end - Iterate over all operands of a machine instruction.
468 using mop_iterator = MachineOperand *;
469 using const_mop_iterator = const MachineOperand *;
470
471 mop_iterator operands_begin() { return Operands; }
472 mop_iterator operands_end() { return Operands + NumOperands; }
473
474 const_mop_iterator operands_begin() const { return Operands; }
475 const_mop_iterator operands_end() const { return Operands + NumOperands; }
476
477 iterator_range<mop_iterator> operands() {
478 return make_range(operands_begin(), operands_end());
479 }
480 iterator_range<const_mop_iterator> operands() const {
481 return make_range(operands_begin(), operands_end());
482 }
483 iterator_range<mop_iterator> explicit_operands() {
484 return make_range(operands_begin(),
485 operands_begin() + getNumExplicitOperands());
486 }
487 iterator_range<const_mop_iterator> explicit_operands() const {
488 return make_range(operands_begin(),
489 operands_begin() + getNumExplicitOperands());
490 }
491 iterator_range<mop_iterator> implicit_operands() {
492 return make_range(explicit_operands().end(), operands_end());
493 }
494 iterator_range<const_mop_iterator> implicit_operands() const {
495 return make_range(explicit_operands().end(), operands_end());
496 }
497 /// Returns a range over all explicit operands that are register definitions.
498 /// Implicit definition are not included!
499 iterator_range<mop_iterator> defs() {
500 return make_range(operands_begin(),
501 operands_begin() + getNumExplicitDefs());
502 }
503 /// \copydoc defs()
504 iterator_range<const_mop_iterator> defs() const {
505 return make_range(operands_begin(),
506 operands_begin() + getNumExplicitDefs());
507 }
508 /// Returns a range that includes all operands that are register uses.
509 /// This may include unrelated operands which are not register uses.
510 iterator_range<mop_iterator> uses() {
511 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
512 }
513 /// \copydoc uses()
514 iterator_range<const_mop_iterator> uses() const {
515 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
516 }
517 iterator_range<mop_iterator> explicit_uses() {
518 return make_range(operands_begin() + getNumExplicitDefs(),
519 operands_begin() + getNumExplicitOperands());
520 }
521 iterator_range<const_mop_iterator> explicit_uses() const {
522 return make_range(operands_begin() + getNumExplicitDefs(),
523 operands_begin() + getNumExplicitOperands());
524 }
525
526 /// Returns the number of the operand iterator \p I points to.
527 unsigned getOperandNo(const_mop_iterator I) const {
528 return I - operands_begin();
529 }
530
531 /// Access to memory operands of the instruction. If there are none, that does
532 /// not imply anything about whether the function accesses memory. Instead,
533 /// the caller must behave conservatively.
534 ArrayRef<MachineMemOperand *> memoperands() const {
535 if (!Info)
536 return {};
537
538 if (Info.is<EIIK_MMO>())
539 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
540
541 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
542 return EI->getMMOs();
543
544 return {};
545 }
546
547 /// Access to memory operands of the instruction.
548 ///
549 /// If `memoperands_begin() == memoperands_end()`, that does not imply
550 /// anything about whether the function accesses memory. Instead, the caller
551 /// must behave conservatively.
552 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
553
554 /// Access to memory operands of the instruction.
555 ///
556 /// If `memoperands_begin() == memoperands_end()`, that does not imply
557 /// anything about whether the function accesses memory. Instead, the caller
558 /// must behave conservatively.
559 mmo_iterator memoperands_end() const { return memoperands().end(); }
560
561 /// Return true if we don't have any memory operands which described the
562 /// memory access done by this instruction. If this is true, calling code
563 /// must be conservative.
564 bool memoperands_empty() const { return memoperands().empty(); }
565
566 /// Return true if this instruction has exactly one MachineMemOperand.
567 bool hasOneMemOperand() const { return memoperands().size() == 1; }
30
←
Assuming the condition is true
→
31
←
Returning the value 1, which participates in a condition later
→
568
569 /// Return the number of memory operands.
570 unsigned getNumMemOperands() const { return memoperands().size(); }
571
572 /// Helper to extract a pre-instruction symbol if one has been added.
573 MCSymbol *getPreInstrSymbol() const {
574 if (!Info)
575 return nullptr;
576 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
577 return S;
578 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
579 return EI->getPreInstrSymbol();
580
581 return nullptr;
582 }
583
584 /// Helper to extract a post-instruction symbol if one has been added.
585 MCSymbol *getPostInstrSymbol() const {
586 if (!Info)
587 return nullptr;
588 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
589 return S;
590 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
591 return EI->getPostInstrSymbol();
592
593 return nullptr;
594 }
595
596 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
597 /// queries but they are bundle aware.
598
599 enum QueryType {
600 IgnoreBundle, // Ignore bundles
601 AnyInBundle, // Return true if any instruction in bundle has property
602 AllInBundle // Return true if all instructions in bundle have property
603 };
604
605 /// Return true if the instruction (or in the case of a bundle,
606 /// the instructions inside the bundle) has the specified property.
607 /// The first argument is the property being queried.
608 /// The second argument indicates whether the query should look inside
609 /// instruction bundles.
610 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
611 assert(MCFlag < 64 &&((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 612, __PRETTY_FUNCTION__))
612 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 612, __PRETTY_FUNCTION__));
613 // Inline the fast path for unbundled or bundle-internal instructions.
614 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
615 return getDesc().getFlags() & (1ULL << MCFlag);
616
617 // If this is the first instruction in a bundle, take the slow path.
618 return hasPropertyInBundle(1ULL << MCFlag, Type);
619 }
620
621 /// Return true if this is an instruction that should go through the usual
622 /// legalization steps.
623 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const {
624 return hasProperty(MCID::PreISelOpcode, Type);
625 }
626
627 /// Return true if this instruction can have a variable number of operands.
628 /// In this case, the variable operands will be after the normal
629 /// operands but before the implicit definitions and uses (if any are
630 /// present).
631 bool isVariadic(QueryType Type = IgnoreBundle) const {
632 return hasProperty(MCID::Variadic, Type);
633 }
634
635 /// Set if this instruction has an optional definition, e.g.
636 /// ARM instructions which can set condition code if 's' bit is set.
637 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
638 return hasProperty(MCID::HasOptionalDef, Type);
639 }
640
641 /// Return true if this is a pseudo instruction that doesn't
642 /// correspond to a real machine instruction.
643 bool isPseudo(QueryType Type = IgnoreBundle) const {
644 return hasProperty(MCID::Pseudo, Type);
645 }
646
647 bool isReturn(QueryType Type = AnyInBundle) const {
648 return hasProperty(MCID::Return, Type);
649 }
650
651 /// Return true if this is an instruction that marks the end of an EH scope,
652 /// i.e., a catchpad or a cleanuppad instruction.
653 bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
654 return hasProperty(MCID::EHScopeReturn, Type);
655 }
656
657 bool isCall(QueryType Type = AnyInBundle) const {
658 return hasProperty(MCID::Call, Type);
659 }
660
661 /// Returns true if the specified instruction stops control flow
662 /// from executing the instruction immediately following it. Examples include
663 /// unconditional branches and return instructions.
664 bool isBarrier(QueryType Type = AnyInBundle) const {
665 return hasProperty(MCID::Barrier, Type);
666 }
667
668 /// Returns true if this instruction part of the terminator for a basic block.
669 /// Typically this is things like return and branch instructions.
670 ///
671 /// Various passes use this to insert code into the bottom of a basic block,
672 /// but before control flow occurs.
673 bool isTerminator(QueryType Type = AnyInBundle) const {
674 return hasProperty(MCID::Terminator, Type);
675 }
676
677 /// Returns true if this is a conditional, unconditional, or indirect branch.
678 /// Predicates below can be used to discriminate between
679 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
680 /// get more information.
681 bool isBranch(QueryType Type = AnyInBundle) const {
682 return hasProperty(MCID::Branch, Type);
683 }
684
685 /// Return true if this is an indirect branch, such as a
686 /// branch through a register.
687 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
688 return hasProperty(MCID::IndirectBranch, Type);
689 }
690
691 /// Return true if this is a branch which may fall
692 /// through to the next instruction or may transfer control flow to some other
693 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
694 /// information about this branch.
695 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
696 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
697 }
698
699 /// Return true if this is a branch which always
700 /// transfers control flow to some other block. The
701 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
702 /// about this branch.
703 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
704 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
705 }
706
707 /// Return true if this instruction has a predicate operand that
708 /// controls execution. It may be set to 'always', or may be set to other
709 /// values. There are various methods in TargetInstrInfo that can be used to
710 /// control and modify the predicate in this instruction.
711 bool isPredicable(QueryType Type = AllInBundle) const {
712 // If it's a bundle than all bundled instructions must be predicable for this
713 // to return true.
714 return hasProperty(MCID::Predicable, Type);
715 }
716
717 /// Return true if this instruction is a comparison.
718 bool isCompare(QueryType Type = IgnoreBundle) const {
719 return hasProperty(MCID::Compare, Type);
720 }
721
722 /// Return true if this instruction is a move immediate
723 /// (including conditional moves) instruction.
724 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
725 return hasProperty(MCID::MoveImm, Type);
726 }
727
728 /// Return true if this instruction is a register move.
729 /// (including moving values from subreg to reg)
730 bool isMoveReg(QueryType Type = IgnoreBundle) const {
731 return hasProperty(MCID::MoveReg, Type);
732 }
733
734 /// Return true if this instruction is a bitcast instruction.
735 bool isBitcast(QueryType Type = IgnoreBundle) const {
736 return hasProperty(MCID::Bitcast, Type);
737 }
738
739 /// Return true if this instruction is a select instruction.
740 bool isSelect(QueryType Type = IgnoreBundle) const {
741 return hasProperty(MCID::Select, Type);
742 }
743
744 /// Return true if this instruction cannot be safely duplicated.
745 /// For example, if the instruction has a unique labels attached
746 /// to it, duplicating it would cause multiple definition errors.
747 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
748 return hasProperty(MCID::NotDuplicable, Type);
749 }
750
751 /// Return true if this instruction is convergent.
752 /// Convergent instructions can not be made control-dependent on any
753 /// additional values.
754 bool isConvergent(QueryType Type = AnyInBundle) const {
755 if (isInlineAsm()) {
756 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
757 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
758 return true;
759 }
760 return hasProperty(MCID::Convergent, Type);
761 }
762
763 /// Returns true if the specified instruction has a delay slot
764 /// which must be filled by the code generator.
765 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
766 return hasProperty(MCID::DelaySlot, Type);
767 }
768
769 /// Return true for instructions that can be folded as
770 /// memory operands in other instructions. The most common use for this
771 /// is instructions that are simple loads from memory that don't modify
772 /// the loaded value in any way, but it can also be used for instructions
773 /// that can be expressed as constant-pool loads, such as V_SETALLONES
774 /// on x86, to allow them to be folded when it is beneficial.
775 /// This should only be set on instructions that return a value in their
776 /// only virtual register definition.
777 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
778 return hasProperty(MCID::FoldableAsLoad, Type);
779 }
780
781 /// Return true if this instruction behaves
782 /// the same way as the generic REG_SEQUENCE instructions.
783 /// E.g., on ARM,
784 /// dX VMOVDRR rY, rZ
785 /// is equivalent to
786 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
787 ///
788 /// Note that for the optimizers to be able to take advantage of
789 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
790 /// override accordingly.
791 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
792 return hasProperty(MCID::RegSequence, Type);
793 }
794
795 /// Return true if this instruction behaves
796 /// the same way as the generic EXTRACT_SUBREG instructions.
797 /// E.g., on ARM,
798 /// rX, rY VMOVRRD dZ
799 /// is equivalent to two EXTRACT_SUBREG:
800 /// rX = EXTRACT_SUBREG dZ, ssub_0
801 /// rY = EXTRACT_SUBREG dZ, ssub_1
802 ///
803 /// Note that for the optimizers to be able to take advantage of
804 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
805 /// override accordingly.
806 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
807 return hasProperty(MCID::ExtractSubreg, Type);
808 }
809
810 /// Return true if this instruction behaves
811 /// the same way as the generic INSERT_SUBREG instructions.
812 /// E.g., on ARM,
813 /// dX = VSETLNi32 dY, rZ, Imm
814 /// is equivalent to a INSERT_SUBREG:
815 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
816 ///
817 /// Note that for the optimizers to be able to take advantage of
818 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
819 /// override accordingly.
820 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
821 return hasProperty(MCID::InsertSubreg, Type);
822 }
823
824 //===--------------------------------------------------------------------===//
825 // Side Effect Analysis
826 //===--------------------------------------------------------------------===//
827
828 /// Return true if this instruction could possibly read memory.
829 /// Instructions with this flag set are not necessarily simple load
830 /// instructions, they may load a value and modify it, for example.
831 bool mayLoad(QueryType Type = AnyInBundle) const {
832 if (isInlineAsm()) {
833 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
834 if (ExtraInfo & InlineAsm::Extra_MayLoad)
835 return true;
836 }
837 return hasProperty(MCID::MayLoad, Type);
838 }
839
840 /// Return true if this instruction could possibly modify memory.
841 /// Instructions with this flag set are not necessarily simple store
842 /// instructions, they may store a modified value based on their operands, or
843 /// may not actually modify anything, for example.
844 bool mayStore(QueryType Type = AnyInBundle) const {
845 if (isInlineAsm()) {
846 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
847 if (ExtraInfo & InlineAsm::Extra_MayStore)
848 return true;
849 }
850 return hasProperty(MCID::MayStore, Type);
851 }
852
853 /// Return true if this instruction could possibly read or modify memory.
854 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
855 return mayLoad(Type) || mayStore(Type);
856 }
857
858 /// Return true if this instruction could possibly raise a floating-point
859 /// exception. This is the case if the instruction is a floating-point
860 /// instruction that can in principle raise an exception, as indicated
861 /// by the MCID::MayRaiseFPException property, *and* at the same time,
862 /// the instruction is used in a context where we expect floating-point
863 /// exceptions might be enabled, as indicated by the FPExcept MI flag.
864 bool mayRaiseFPException() const {
865 return hasProperty(MCID::MayRaiseFPException) &&
866 getFlag(MachineInstr::MIFlag::FPExcept);
867 }
868
869 //===--------------------------------------------------------------------===//
870 // Flags that indicate whether an instruction can be modified by a method.
871 //===--------------------------------------------------------------------===//
872
873 /// Return true if this may be a 2- or 3-address
874 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
875 /// result if Y and Z are exchanged. If this flag is set, then the
876 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
877 /// instruction.
878 ///
879 /// Note that this flag may be set on instructions that are only commutable
880 /// sometimes. In these cases, the call to commuteInstruction will fail.
881 /// Also note that some instructions require non-trivial modification to
882 /// commute them.
883 bool isCommutable(QueryType Type = IgnoreBundle) const {
884 return hasProperty(MCID::Commutable, Type);
885 }
886
887 /// Return true if this is a 2-address instruction
888 /// which can be changed into a 3-address instruction if needed. Doing this
889 /// transformation can be profitable in the register allocator, because it
890 /// means that the instruction can use a 2-address form if possible, but
891 /// degrade into a less efficient form if the source and dest register cannot
892 /// be assigned to the same register. For example, this allows the x86
893 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
894 /// is the same speed as the shift but has bigger code size.
895 ///
896 /// If this returns true, then the target must implement the
897 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
898 /// is allowed to fail if the transformation isn't valid for this specific
899 /// instruction (e.g. shl reg, 4 on x86).
900 ///
901 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
902 return hasProperty(MCID::ConvertibleTo3Addr, Type);
903 }
904
905 /// Return true if this instruction requires
906 /// custom insertion support when the DAG scheduler is inserting it into a
907 /// machine basic block. If this is true for the instruction, it basically
908 /// means that it is a pseudo instruction used at SelectionDAG time that is
909 /// expanded out into magic code by the target when MachineInstrs are formed.
910 ///
911 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
912 /// is used to insert this into the MachineBasicBlock.
913 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
914 return hasProperty(MCID::UsesCustomInserter, Type);
915 }
916
917 /// Return true if this instruction requires *adjustment*
918 /// after instruction selection by calling a target hook. For example, this
919 /// can be used to fill in ARM 's' optional operand depending on whether
920 /// the conditional flag register is used.
921 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
922 return hasProperty(MCID::HasPostISelHook, Type);
923 }
924
925 /// Returns true if this instruction is a candidate for remat.
926 /// This flag is deprecated, please don't use it anymore. If this
927 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
928 /// verify the instruction is really rematable.
929 bool isRematerializable(QueryType Type = AllInBundle) const {
930 // It's only possible to re-mat a bundle if all bundled instructions are
931 // re-materializable.
932 return hasProperty(MCID::Rematerializable, Type);
933 }
934
935 /// Returns true if this instruction has the same cost (or less) than a move
936 /// instruction. This is useful during certain types of optimizations
937 /// (e.g., remat during two-address conversion or machine licm)
938 /// where we would like to remat or hoist the instruction, but not if it costs
939 /// more than moving the instruction into the appropriate register. Note, we
940 /// are not marking copies from and to the same register class with this flag.
941 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
942 // Only returns true for a bundle if all bundled instructions are cheap.
943 return hasProperty(MCID::CheapAsAMove, Type);
944 }
945
946 /// Returns true if this instruction source operands
947 /// have special register allocation requirements that are not captured by the
948 /// operand register classes. e.g. ARM::STRD's two source registers must be an
949 /// even / odd pair, ARM::STM registers have to be in ascending order.
950 /// Post-register allocation passes should not attempt to change allocations
951 /// for sources of instructions with this flag.
952 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
953 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
954 }
955
956 /// Returns true if this instruction def operands
957 /// have special register allocation requirements that are not captured by the
958 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
959 /// even / odd pair, ARM::LDM registers have to be in ascending order.
960 /// Post-register allocation passes should not attempt to change allocations
961 /// for definitions of instructions with this flag.
962 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
963 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
964 }
965
966 enum MICheckType {
967 CheckDefs, // Check all operands for equality
968 CheckKillDead, // Check all operands including kill / dead markers
969 IgnoreDefs, // Ignore all definitions
970 IgnoreVRegDefs // Ignore virtual register definitions
971 };
972
973 /// Return true if this instruction is identical to \p Other.
974 /// Two instructions are identical if they have the same opcode and all their
975 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
976 /// Note that this means liveness related flags (dead, undef, kill) do not
977 /// affect the notion of identical.
978 bool isIdenticalTo(const MachineInstr &Other,
979 MICheckType Check = CheckDefs) const;
980
981 /// Unlink 'this' from the containing basic block, and return it without
982 /// deleting it.
983 ///
984 /// This function can not be used on bundled instructions, use
985 /// removeFromBundle() to remove individual instructions from a bundle.
986 MachineInstr *removeFromParent();
987
988 /// Unlink this instruction from its basic block and return it without
989 /// deleting it.
990 ///
991 /// If the instruction is part of a bundle, the other instructions in the
992 /// bundle remain bundled.
993 MachineInstr *removeFromBundle();
994
995 /// Unlink 'this' from the containing basic block and delete it.
996 ///
997 /// If this instruction is the header of a bundle, the whole bundle is erased.
998 /// This function can not be used for instructions inside a bundle, use
999 /// eraseFromBundle() to erase individual bundled instructions.
1000 void eraseFromParent();
1001
1002 /// Unlink 'this' from the containing basic block and delete it.
1003 ///
1004 /// For all definitions mark their uses in DBG_VALUE nodes
1005 /// as undefined. Otherwise like eraseFromParent().
1006 void eraseFromParentAndMarkDBGValuesForRemoval();
1007
1008 /// Unlink 'this' form its basic block and delete it.
1009 ///
1010 /// If the instruction is part of a bundle, the other instructions in the
1011 /// bundle remain bundled.
1012 void eraseFromBundle();
1013
1014 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1015 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1016 bool isAnnotationLabel() const {
1017 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1018 }
1019
1020 /// Returns true if the MachineInstr represents a label.
1021 bool isLabel() const {
1022 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1023 }
1024
1025 bool isCFIInstruction() const {
1026 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1027 }
1028
1029 // True if the instruction represents a position in the function.
1030 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1031
1032 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1033 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1034 bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
1035
1036 /// A DBG_VALUE is indirect iff the first operand is a register and
1037 /// the second operand is an immediate.
1038 bool isIndirectDebugValue() const {
1039 return isDebugValue()
1040 && getOperand(0).isReg()
1041 && getOperand(1).isImm();
1042 }
1043
1044 /// A DBG_VALUE is an entry value iff its debug expression contains the
1045 /// DW_OP_entry_value DWARF operation.
1046 bool isDebugEntryValue() const {
1047 return isDebugValue() && getDebugExpression()->isEntryValue();
1048 }
1049
1050 /// Return true if the instruction is a debug value which describes a part of
1051 /// a variable as unavailable.
1052 bool isUndefDebugValue() const {
1053 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1054 }
1055
1056 bool isPHI() const {
1057 return getOpcode() == TargetOpcode::PHI ||
1058 getOpcode() == TargetOpcode::G_PHI;
1059 }
1060 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1061 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1062 bool isInlineAsm() const {
1063 return getOpcode() == TargetOpcode::INLINEASM ||
1064 getOpcode() == TargetOpcode::INLINEASM_BR;
1065 }
1066
1067 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1068 /// specific, be attached to a generic MachineInstr.
1069 bool isMSInlineAsm() const {
1070 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1071 }
1072
1073 bool isStackAligningInlineAsm() const;
1074 InlineAsm::AsmDialect getInlineAsmDialect() const;
1075
1076 bool isInsertSubreg() const {
1077 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1078 }
1079
1080 bool isSubregToReg() const {
1081 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1082 }
1083
1084 bool isRegSequence() const {
1085 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1086 }
1087
1088 bool isBundle() const {
1089 return getOpcode() == TargetOpcode::BUNDLE;
1090 }
1091
1092 bool isCopy() const {
1093 return getOpcode() == TargetOpcode::COPY;
1094 }
1095
1096 bool isFullCopy() const {
1097 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1098 }
1099
1100 bool isExtractSubreg() const {
1101 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1102 }
1103
1104 /// Return true if the instruction behaves like a copy.
1105 /// This does not include native copy instructions.
1106 bool isCopyLike() const {
1107 return isCopy() || isSubregToReg();
1108 }
1109
1110 /// Return true is the instruction is an identity copy.
1111 bool isIdentityCopy() const {
1112 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1113 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1114 }
1115
1116 /// Return true if this instruction doesn't produce any output in the form of
1117 /// executable instructions.
1118 bool isMetaInstruction() const {
1119 switch (getOpcode()) {
1120 default:
1121 return false;
1122 case TargetOpcode::IMPLICIT_DEF:
1123 case TargetOpcode::KILL:
1124 case TargetOpcode::CFI_INSTRUCTION:
1125 case TargetOpcode::EH_LABEL:
1126 case TargetOpcode::GC_LABEL:
1127 case TargetOpcode::DBG_VALUE:
1128 case TargetOpcode::DBG_LABEL:
1129 case TargetOpcode::LIFETIME_START:
1130 case TargetOpcode::LIFETIME_END:
1131 return true;
1132 }
1133 }
1134
1135 /// Return true if this is a transient instruction that is either very likely
1136 /// to be eliminated during register allocation (such as copy-like
1137 /// instructions), or if this instruction doesn't have an execution-time cost.
1138 bool isTransient() const {
1139 switch (getOpcode()) {
1140 default:
1141 return isMetaInstruction();
1142 // Copy-like instructions are usually eliminated during register allocation.
1143 case TargetOpcode::PHI:
1144 case TargetOpcode::G_PHI:
1145 case TargetOpcode::COPY:
1146 case TargetOpcode::INSERT_SUBREG:
1147 case TargetOpcode::SUBREG_TO_REG:
1148 case TargetOpcode::REG_SEQUENCE:
1149 return true;
1150 }
1151 }
1152
1153 /// Return the number of instructions inside the MI bundle, excluding the
1154 /// bundle header.
1155 ///
1156 /// This is the number of instructions that MachineBasicBlock::iterator
1157 /// skips, 0 for unbundled instructions.
1158 unsigned getBundleSize() const;
1159
1160 /// Return true if the MachineInstr reads the specified register.
1161 /// If TargetRegisterInfo is passed, then it also checks if there
1162 /// is a read of a super-register.
1163 /// This does not count partial redefines of virtual registers as reads:
1164 /// %reg1024:6 = OP.
1165 bool readsRegister(Register Reg,
1166 const TargetRegisterInfo *TRI = nullptr) const {
1167 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1168 }
1169
1170 /// Return true if the MachineInstr reads the specified virtual register.
1171 /// Take into account that a partial define is a
1172 /// read-modify-write operation.
1173 bool readsVirtualRegister(Register Reg) const {
1174 return readsWritesVirtualRegister(Reg).first;
1175 }
1176
1177 /// Return a pair of bools (reads, writes) indicating if this instruction
1178 /// reads or writes Reg. This also considers partial defines.
1179 /// If Ops is not null, all operand indices for Reg are added.
1180 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1181 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1182
1183 /// Return true if the MachineInstr kills the specified register.
1184 /// If TargetRegisterInfo is passed, then it also checks if there is
1185 /// a kill of a super-register.
1186 bool killsRegister(Register Reg,
1187 const TargetRegisterInfo *TRI = nullptr) const {
1188 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1189 }
1190
1191 /// Return true if the MachineInstr fully defines the specified register.
1192 /// If TargetRegisterInfo is passed, then it also checks
1193 /// if there is a def of a super-register.
1194 /// NOTE: It's ignoring subreg indices on virtual registers.
1195 bool definesRegister(Register Reg,
1196 const TargetRegisterInfo *TRI = nullptr) const {
1197 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1198 }
1199
1200 /// Return true if the MachineInstr modifies (fully define or partially
1201 /// define) the specified register.
1202 /// NOTE: It's ignoring subreg indices on virtual registers.
1203 bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1204 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1205 }
1206
1207 /// Returns true if the register is dead in this machine instruction.
1208 /// If TargetRegisterInfo is passed, then it also checks
1209 /// if there is a dead def of a super-register.
1210 bool registerDefIsDead(Register Reg,
1211 const TargetRegisterInfo *TRI = nullptr) const {
1212 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1213 }
1214
1215 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1216 /// the given register (not considering sub/super-registers).
1217 bool hasRegisterImplicitUseOperand(Register Reg) const;
1218
1219 /// Returns the operand index that is a use of the specific register or -1
1220 /// if it is not found. It further tightens the search criteria to a use
1221 /// that kills the register if isKill is true.
1222 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1223 const TargetRegisterInfo *TRI = nullptr) const;
1224
1225 /// Wrapper for findRegisterUseOperandIdx, it returns
1226 /// a pointer to the MachineOperand rather than an index.
1227 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1228 const TargetRegisterInfo *TRI = nullptr) {
1229 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1230 return (Idx == -1) ? nullptr : &getOperand(Idx);
1231 }
1232
1233 const MachineOperand *findRegisterUseOperand(
1234 Register Reg, bool isKill = false,
1235 const TargetRegisterInfo *TRI = nullptr) const {
1236 return const_cast<MachineInstr *>(this)->
1237 findRegisterUseOperand(Reg, isKill, TRI);
1238 }
1239
1240 /// Returns the operand index that is a def of the specified register or
1241 /// -1 if it is not found. If isDead is true, defs that are not dead are
1242 /// skipped. If Overlap is true, then it also looks for defs that merely
1243 /// overlap the specified register. If TargetRegisterInfo is non-null,
1244 /// then it also checks if there is a def of a super-register.
1245 /// This may also return a register mask operand when Overlap is true.
1246 int findRegisterDefOperandIdx(Register Reg,
1247 bool isDead = false, bool Overlap = false,
1248 const TargetRegisterInfo *TRI = nullptr) const;
1249
1250 /// Wrapper for findRegisterDefOperandIdx, it returns
1251 /// a pointer to the MachineOperand rather than an index.
1252 MachineOperand *
1253 findRegisterDefOperand(Register Reg, bool isDead = false,
1254 bool Overlap = false,
1255 const TargetRegisterInfo *TRI = nullptr) {
1256 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1257 return (Idx == -1) ? nullptr : &getOperand(Idx);
1258 }
1259
1260 const MachineOperand *
1261 findRegisterDefOperand(Register Reg, bool isDead = false,
1262 bool Overlap = false,
1263 const TargetRegisterInfo *TRI = nullptr) const {
1264 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1265 Reg, isDead, Overlap, TRI);
1266 }
1267
1268 /// Find the index of the first operand in the
1269 /// operand list that is used to represent the predicate. It returns -1 if
1270 /// none is found.
1271 int findFirstPredOperandIdx() const;
1272
1273 /// Find the index of the flag word operand that
1274 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1275 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1276 ///
1277 /// If GroupNo is not NULL, it will receive the number of the operand group
1278 /// containing OpIdx.
1279 ///
1280 /// The flag operand is an immediate that can be decoded with methods like
1281 /// InlineAsm::hasRegClassConstraint().
1282 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1283
1284 /// Compute the static register class constraint for operand OpIdx.
1285 /// For normal instructions, this is derived from the MCInstrDesc.
1286 /// For inline assembly it is derived from the flag words.
1287 ///
1288 /// Returns NULL if the static register class constraint cannot be
1289 /// determined.
1290 const TargetRegisterClass*
1291 getRegClassConstraint(unsigned OpIdx,
1292 const TargetInstrInfo *TII,
1293 const TargetRegisterInfo *TRI) const;
1294
1295 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1296 /// the given \p CurRC.
1297 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1298 /// instructions inside the bundle will be taken into account. In other words,
1299 /// this method accumulates all the constraints of the operand of this MI and
1300 /// the related bundle if MI is a bundle or inside a bundle.
1301 ///
1302 /// Returns the register class that satisfies both \p CurRC and the
1303 /// constraints set by MI. Returns NULL if such a register class does not
1304 /// exist.
1305 ///
1306 /// \pre CurRC must not be NULL.
1307 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1308 Register Reg, const TargetRegisterClass *CurRC,
1309 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1310 bool ExploreBundle = false) const;
1311
1312 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1313 /// to the given \p CurRC.
1314 ///
1315 /// Returns the register class that satisfies both \p CurRC and the
1316 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1317 /// does not exist.
1318 ///
1319 /// \pre CurRC must not be NULL.
1320 /// \pre The operand at \p OpIdx must be a register.
1321 const TargetRegisterClass *
1322 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1323 const TargetInstrInfo *TII,
1324 const TargetRegisterInfo *TRI) const;
1325
1326 /// Add a tie between the register operands at DefIdx and UseIdx.
1327 /// The tie will cause the register allocator to ensure that the two
1328 /// operands are assigned the same physical register.
1329 ///
1330 /// Tied operands are managed automatically for explicit operands in the
1331 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1332 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1333
1334 /// Given the index of a tied register operand, find the
1335 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1336 /// index of the tied operand which must exist.
1337 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1338
1339 /// Given the index of a register def operand,
1340 /// check if the register def is tied to a source operand, due to either
1341 /// two-address elimination or inline assembly constraints. Returns the
1342 /// first tied use operand index by reference if UseOpIdx is not null.
1343 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1344 unsigned *UseOpIdx = nullptr) const {
1345 const MachineOperand &MO = getOperand(DefOpIdx);
1346 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1347 return false;
1348 if (UseOpIdx)
1349 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1350 return true;
1351 }
1352
1353 /// Return true if the use operand of the specified index is tied to a def
1354 /// operand. It also returns the def operand index by reference if DefOpIdx
1355 /// is not null.
1356 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1357 unsigned *DefOpIdx = nullptr) const {
1358 const MachineOperand &MO = getOperand(UseOpIdx);
1359 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1360 return false;
1361 if (DefOpIdx)
1362 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1363 return true;
1364 }
1365
1366 /// Clears kill flags on all operands.
1367 void clearKillInfo();
1368
1369 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1370 /// properly composing subreg indices where necessary.
1371 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1372 const TargetRegisterInfo &RegInfo);
1373
1374 /// We have determined MI kills a register. Look for the
1375 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1376 /// add a implicit operand if it's not found. Returns true if the operand
1377 /// exists / is added.
1378 bool addRegisterKilled(Register IncomingReg,
1379 const TargetRegisterInfo *RegInfo,
1380 bool AddIfNotFound = false);
1381
1382 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1383 /// all aliasing registers.
1384 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1385
1386 /// We have determined MI defined a register without a use.
1387 /// Look for the operand that defines it and mark it as IsDead. If
1388 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1389 /// true if the operand exists / is added.
1390 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1391 bool AddIfNotFound = false);
1392
1393 /// Clear all dead flags on operands defining register @p Reg.
1394 void clearRegisterDeads(Register Reg);
1395
1396 /// Mark all subregister defs of register @p Reg with the undef flag.
1397 /// This function is used when we determined to have a subregister def in an
1398 /// otherwise undefined super register.
1399 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1400
1401 /// We have determined MI defines a register. Make sure there is an operand
1402 /// defining Reg.
1403 void addRegisterDefined(Register Reg,
1404 const TargetRegisterInfo *RegInfo = nullptr);
1405
1406 /// Mark every physreg used by this instruction as
1407 /// dead except those in the UsedRegs list.
1408 ///
1409 /// On instructions with register mask operands, also add implicit-def
1410 /// operands for all registers in UsedRegs.
1411 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1412 const TargetRegisterInfo &TRI);
1413
1414 /// Return true if it is safe to move this instruction. If
1415 /// SawStore is set to true, it means that there is a store (or call) between
1416 /// the instruction's location and its intended destination.
1417 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1418
1419 /// Returns true if this instruction's memory access aliases the memory
1420 /// access of Other.
1421 //
1422 /// Assumes any physical registers used to compute addresses
1423 /// have the same value for both instructions. Returns false if neither
1424 /// instruction writes to memory.
1425 ///
1426 /// @param AA Optional alias analysis, used to compare memory operands.
1427 /// @param Other MachineInstr to check aliasing against.
1428 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1429 bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const;
1430
1431 /// Return true if this instruction may have an ordered
1432 /// or volatile memory reference, or if the information describing the memory
1433 /// reference is not available. Return false if it is known to have no
1434 /// ordered or volatile memory references.
1435 bool hasOrderedMemoryRef() const;
1436
1437 /// Return true if this load instruction never traps and points to a memory
1438 /// location whose value doesn't change during the execution of this function.
1439 ///
1440 /// Examples include loading a value from the constant pool or from the
1441 /// argument area of a function (if it does not change). If the instruction
1442 /// does multiple loads, this returns true only if all of the loads are
1443 /// dereferenceable and invariant.
1444 bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1445
1446 /// If the specified instruction is a PHI that always merges together the
1447 /// same virtual register, return the register, otherwise return 0.
1448 unsigned isConstantValuePHI() const;
1449
1450 /// Return true if this instruction has side effects that are not modeled
1451 /// by mayLoad / mayStore, etc.
1452 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1453 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1454 /// INLINEASM instruction, in which case the side effect property is encoded
1455 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1456 ///
1457 bool hasUnmodeledSideEffects() const;
1458
1459 /// Returns true if it is illegal to fold a load across this instruction.
1460 bool isLoadFoldBarrier() const;
1461
1462 /// Return true if all the defs of this instruction are dead.
1463 bool allDefsAreDead() const;
1464
1465 /// Return a valid size if the instruction is a spill instruction.
1466 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1467
1468 /// Return a valid size if the instruction is a folded spill instruction.
1469 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1470
1471 /// Return a valid size if the instruction is a restore instruction.
1472 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1473
1474 /// Return a valid size if the instruction is a folded restore instruction.
1475 Optional<unsigned>
1476 getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1477
1478 /// Copy implicit register operands from specified
1479 /// instruction to this instruction.
1480 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1481
1482 /// Debugging support
1483 /// @{
1484 /// Determine the generic type to be printed (if needed) on uses and defs.
1485 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1486 const MachineRegisterInfo &MRI) const;
1487
1488 /// Return true when an instruction has tied register that can't be determined
1489 /// by the instruction's descriptor. This is useful for MIR printing, to
1490 /// determine whether we need to print the ties or not.
1491 bool hasComplexRegisterTies() const;
1492
1493 /// Print this MI to \p OS.
1494 /// Don't print information that can be inferred from other instructions if
1495 /// \p IsStandalone is false. It is usually true when only a fragment of the
1496 /// function is printed.
1497 /// Only print the defs and the opcode if \p SkipOpers is true.
1498 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1499 /// Otherwise, also print the debug loc, with a terminating newline.
1500 /// \p TII is used to print the opcode name. If it's not present, but the
1501 /// MI is in a function, the opcode will be printed using the function's TII.
1502 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1503 bool SkipDebugLoc = false, bool AddNewLine = true,
1504 const TargetInstrInfo *TII = nullptr) const;
1505 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1506 bool SkipOpers = false, bool SkipDebugLoc = false,
1507 bool AddNewLine = true,
1508 const TargetInstrInfo *TII = nullptr) const;
1509 void dump() const;
1510 /// @}
1511
1512 //===--------------------------------------------------------------------===//
1513 // Accessors used to build up machine instructions.
1514
1515 /// Add the specified operand to the instruction. If it is an implicit
1516 /// operand, it is added to the end of the operand list. If it is an
1517 /// explicit operand it is added at the end of the explicit operand list
1518 /// (before the first implicit operand).
1519 ///
1520 /// MF must be the machine function that was used to allocate this
1521 /// instruction.
1522 ///
1523 /// MachineInstrBuilder provides a more convenient interface for creating
1524 /// instructions and adding operands.
1525 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1526
1527 /// Add an operand without providing an MF reference. This only works for
1528 /// instructions that are inserted in a basic block.
1529 ///
1530 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1531 /// preferred.
1532 void addOperand(const MachineOperand &Op);
1533
1534 /// Replace the instruction descriptor (thus opcode) of
1535 /// the current instruction with a new one.
1536 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1537
1538 /// Replace current source information with new such.
1539 /// Avoid using this, the constructor argument is preferable.
1540 void setDebugLoc(DebugLoc dl) {
1541 debugLoc = std::move(dl);
1542 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~svn374877/include/llvm/CodeGen/MachineInstr.h"
, 1542, __PRETTY_FUNCTION__));
1543 }
1544
1545 /// Erase an operand from an instruction, leaving it with one
1546 /// fewer operand than it started with.
1547 void RemoveOperand(unsigned OpNo);
1548
1549 /// Clear this MachineInstr's memory reference descriptor list. This resets
1550 /// the memrefs to their most conservative state. This should be used only
1551 /// as a last resort since it greatly pessimizes our knowledge of the memory
1552 /// access performed by the instruction.
1553 void dropMemRefs(MachineFunction &MF);
1554
1555 /// Assign this MachineInstr's memory reference descriptor list.
1556 ///
1557 /// Unlike other methods, this *will* allocate them into a new array
1558 /// associated with the provided `MachineFunction`.
1559 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1560
1561 /// Add a MachineMemOperand to the machine instruction.
1562 /// This function should be used only occasionally. The setMemRefs function
1563 /// is the primary method for setting up a MachineInstr's MemRefs list.
1564 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1565
1566 /// Clone another MachineInstr's memory reference descriptor list and replace
1567 /// ours with it.
1568 ///
1569 /// Note that `*this` may be the incoming MI!
1570 ///
1571 /// Prefer this API whenever possible as it can avoid allocations in common
1572 /// cases.
1573 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1574
1575 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1576 /// list and replace ours with it.
1577 ///
1578 /// Note that `*this` may be one of the incoming MIs!
1579 ///
1580 /// Prefer this API whenever possible as it can avoid allocations in common
1581 /// cases.
1582 void cloneMergedMemRefs(MachineFunction &MF,
1583 ArrayRef<const MachineInstr *> MIs);
1584
1585 /// Set a symbol that will be emitted just prior to the instruction itself.
1586 ///
1587 /// Setting this to a null pointer will remove any such symbol.
1588 ///
1589 /// FIXME: This is not fully implemented yet.
1590 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1591
1592 /// Set a symbol that will be emitted just after the instruction itself.
1593 ///
1594 /// Setting this to a null pointer will remove any such symbol.
1595 ///
1596 /// FIXME: This is not fully implemented yet.
1597 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1598
1599 /// Clone another MachineInstr's pre- and post- instruction symbols and
1600 /// replace ours with it.
1601 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1602
1603 /// Return the MIFlags which represent both MachineInstrs. This
1604 /// should be used when merging two MachineInstrs into one. This routine does
1605 /// not modify the MIFlags of this MachineInstr.
1606 uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1607
1608 static uint16_t copyFlagsFromInstruction(const Instruction &I);
1609
1610 /// Copy all flags to MachineInst MIFlags
1611 void copyIRFlags(const Instruction &I);
1612
1613 /// Break any tie involving OpIdx.
1614 void untieRegOperand(unsigned OpIdx) {
1615 MachineOperand &MO = getOperand(OpIdx);
1616 if (MO.isReg() && MO.isTied()) {
1617 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1618 MO.TiedTo = 0;
1619 }
1620 }
1621
1622 /// Add all implicit def and use operands to this instruction.
1623 void addImplicitDefUseOperands(MachineFunction &MF);
1624
1625 /// Scan instructions following MI and collect any matching DBG_VALUEs.
1626 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1627
1628 /// Find all DBG_VALUEs that point to the register def in this instruction
1629 /// and point them to \p Reg instead.
1630 void changeDebugValuesDefReg(Register Reg);
1631
1632 /// Returns the Intrinsic::ID for this instruction.
1633 /// \pre Must have an intrinsic ID operand.
1634 unsigned getIntrinsicID() const {
1635 return getOperand(getNumExplicitDefs()).getIntrinsicID();
1636 }
1637
1638private:
1639 /// If this instruction is embedded into a MachineFunction, return the
1640 /// MachineRegisterInfo object for the current function, otherwise
1641 /// return null.
1642 MachineRegisterInfo *getRegInfo();
1643
1644 /// Unlink all of the register operands in this instruction from their
1645 /// respective use lists. This requires that the operands already be on their
1646 /// use lists.
1647 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1648
1649 /// Add all of the register operands in this instruction from their
1650 /// respective use lists. This requires that the operands not be on their
1651 /// use lists yet.
1652 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1653
1654 /// Slow path for hasProperty when we're dealing with a bundle.
1655 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1656
1657 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1658 /// this MI and the given operand index \p OpIdx.
1659 /// If the related operand does not constrained Reg, this returns CurRC.
1660 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1661 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1662 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1663};
1664
1665/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1666/// instruction rather than by pointer value.
1667/// The hashing and equality testing functions ignore definitions so this is
1668/// useful for CSE, etc.
1669struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1670 static inline MachineInstr *getEmptyKey() {
1671 return nullptr;
1672 }
1673
1674 static inline MachineInstr *getTombstoneKey() {
1675 return reinterpret_cast<MachineInstr*>(-1);
1676 }
1677
1678 static unsigned getHashValue(const MachineInstr* const &MI);
1679
1680 static bool isEqual(const MachineInstr* const &LHS,
1681 const MachineInstr* const &RHS) {
1682 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1683 LHS == getEmptyKey() || LHS == getTombstoneKey())
1684 return LHS == RHS;
1685 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1686 }
1687};
1688
1689//===----------------------------------------------------------------------===//
1690// Debugging Support
1691
1692inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1693 MI.print(OS);
1694 return OS;
1695}
1696
1697} // end namespace llvm
1698
1699#endif // LLVM_CODEGEN_MACHINEINSTR_H