Bug Summary

File:lib/CodeGen/LiveDebugValues.cpp
Warning:line 926, column 42
The right operand of '==' is a garbage value

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name LiveDebugValues.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -analyzer-config-compatibility-mode=true -mrelocation-model pic -pic-level 2 -mthread-model posix -mframe-pointer=none -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-10/lib/clang/10.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen -I /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/include -I /build/llvm-toolchain-snapshot-10~svn373517/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-10/lib/clang/10.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-10~svn373517/build-llvm/lib/CodeGen -fdebug-prefix-map=/build/llvm-toolchain-snapshot-10~svn373517=. -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -stack-protector 2 -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -faddrsig -o /tmp/scan-build-2019-10-02-234743-9763-1 -x c++ /build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp

/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp

1//===- LiveDebugValues.cpp - Tracking Debug Value MIs ---------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// This pass implements a data flow analysis that propagates debug location
10/// information by inserting additional DBG_VALUE insts into the machine
11/// instruction stream. Before running, each DBG_VALUE inst corresponds to a
12/// source assignment of a variable. Afterwards, a DBG_VALUE inst specifies a
13/// variable location for the current basic block (see SourceLevelDebugging.rst).
14///
15/// This is a separate pass from DbgValueHistoryCalculator to facilitate
16/// testing and improve modularity.
17///
18/// Each variable location is represented by a VarLoc object that identifies the
19/// source variable, its current machine-location, and the DBG_VALUE inst that
20/// specifies the location. Each VarLoc is indexed in the (function-scope)
21/// VarLocMap, giving each VarLoc a unique index. Rather than operate directly
22/// on machine locations, the dataflow analysis in this pass identifies
23/// locations by their index in the VarLocMap, meaning all the variable
24/// locations in a block can be described by a sparse vector of VarLocMap
25/// indexes.
26///
27//===----------------------------------------------------------------------===//
28
29#include "llvm/ADT/DenseMap.h"
30#include "llvm/ADT/PostOrderIterator.h"
31#include "llvm/ADT/SmallPtrSet.h"
32#include "llvm/ADT/SmallSet.h"
33#include "llvm/ADT/SmallVector.h"
34#include "llvm/ADT/SparseBitVector.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/ADT/UniqueVector.h"
37#include "llvm/CodeGen/LexicalScopes.h"
38#include "llvm/CodeGen/MachineBasicBlock.h"
39#include "llvm/CodeGen/MachineFrameInfo.h"
40#include "llvm/CodeGen/MachineFunction.h"
41#include "llvm/CodeGen/MachineFunctionPass.h"
42#include "llvm/CodeGen/MachineInstr.h"
43#include "llvm/CodeGen/MachineInstrBuilder.h"
44#include "llvm/CodeGen/MachineMemOperand.h"
45#include "llvm/CodeGen/MachineOperand.h"
46#include "llvm/CodeGen/PseudoSourceValue.h"
47#include "llvm/CodeGen/RegisterScavenging.h"
48#include "llvm/CodeGen/TargetFrameLowering.h"
49#include "llvm/CodeGen/TargetInstrInfo.h"
50#include "llvm/CodeGen/TargetLowering.h"
51#include "llvm/CodeGen/TargetPassConfig.h"
52#include "llvm/CodeGen/TargetRegisterInfo.h"
53#include "llvm/CodeGen/TargetSubtargetInfo.h"
54#include "llvm/Config/llvm-config.h"
55#include "llvm/IR/DIBuilder.h"
56#include "llvm/IR/DebugInfoMetadata.h"
57#include "llvm/IR/DebugLoc.h"
58#include "llvm/IR/Function.h"
59#include "llvm/IR/Module.h"
60#include "llvm/MC/MCRegisterInfo.h"
61#include "llvm/Pass.h"
62#include "llvm/Support/Casting.h"
63#include "llvm/Support/Compiler.h"
64#include "llvm/Support/Debug.h"
65#include "llvm/Support/raw_ostream.h"
66#include <algorithm>
67#include <cassert>
68#include <cstdint>
69#include <functional>
70#include <queue>
71#include <tuple>
72#include <utility>
73#include <vector>
74
75using namespace llvm;
76
77#define DEBUG_TYPE"livedebugvalues" "livedebugvalues"
78
79STATISTIC(NumInserted, "Number of DBG_VALUE instructions inserted")static llvm::Statistic NumInserted = {"livedebugvalues", "NumInserted"
, "Number of DBG_VALUE instructions inserted", {0}, {false}}
;
80STATISTIC(NumRemoved, "Number of DBG_VALUE instructions removed")static llvm::Statistic NumRemoved = {"livedebugvalues", "NumRemoved"
, "Number of DBG_VALUE instructions removed", {0}, {false}}
;
81
82// If @MI is a DBG_VALUE with debug value described by a defined
83// register, returns the number of this register. In the other case, returns 0.
84static Register isDbgValueDescribedByReg(const MachineInstr &MI) {
85 assert(MI.isDebugValue() && "expected a DBG_VALUE")((MI.isDebugValue() && "expected a DBG_VALUE") ? static_cast
<void> (0) : __assert_fail ("MI.isDebugValue() && \"expected a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 85, __PRETTY_FUNCTION__))
;
86 assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE")((MI.getNumOperands() == 4 && "malformed DBG_VALUE") ?
static_cast<void> (0) : __assert_fail ("MI.getNumOperands() == 4 && \"malformed DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 86, __PRETTY_FUNCTION__))
;
87 // If location of variable is described using a register (directly
88 // or indirectly), this register is always a first operand.
89 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
90}
91
92namespace {
93
94class LiveDebugValues : public MachineFunctionPass {
95private:
96 const TargetRegisterInfo *TRI;
97 const TargetInstrInfo *TII;
98 const TargetFrameLowering *TFI;
99 BitVector CalleeSavedRegs;
100 LexicalScopes LS;
101
102 enum struct TransferKind { TransferCopy, TransferSpill, TransferRestore };
103
104 /// Keeps track of lexical scopes associated with a user value's source
105 /// location.
106 class UserValueScopes {
107 DebugLoc DL;
108 LexicalScopes &LS;
109 SmallPtrSet<const MachineBasicBlock *, 4> LBlocks;
110
111 public:
112 UserValueScopes(DebugLoc D, LexicalScopes &L) : DL(std::move(D)), LS(L) {}
113
114 /// Return true if current scope dominates at least one machine
115 /// instruction in a given machine basic block.
116 bool dominates(MachineBasicBlock *MBB) {
117 if (LBlocks.empty())
118 LS.getMachineBasicBlocks(DL, LBlocks);
119 return LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB);
120 }
121 };
122
123 using FragmentInfo = DIExpression::FragmentInfo;
124 using OptFragmentInfo = Optional<DIExpression::FragmentInfo>;
125
126 /// Storage for identifying a potentially inlined instance of a variable,
127 /// or a fragment thereof.
128 class DebugVariable {
129 const DILocalVariable *Variable;
130 OptFragmentInfo Fragment;
131 const DILocation *InlinedAt;
132
133 /// Fragment that will overlap all other fragments. Used as default when
134 /// caller demands a fragment.
135 static const FragmentInfo DefaultFragment;
136
137 public:
138 DebugVariable(const DILocalVariable *Var, OptFragmentInfo &&FragmentInfo,
139 const DILocation *InlinedAt)
140 : Variable(Var), Fragment(FragmentInfo), InlinedAt(InlinedAt) {}
141
142 DebugVariable(const DILocalVariable *Var, OptFragmentInfo &FragmentInfo,
143 const DILocation *InlinedAt)
144 : Variable(Var), Fragment(FragmentInfo), InlinedAt(InlinedAt) {}
145
146 DebugVariable(const DILocalVariable *Var, const DIExpression *DIExpr,
147 const DILocation *InlinedAt)
148 : DebugVariable(Var, DIExpr->getFragmentInfo(), InlinedAt) {}
149
150 DebugVariable(const MachineInstr &MI)
151 : DebugVariable(MI.getDebugVariable(),
152 MI.getDebugExpression()->getFragmentInfo(),
153 MI.getDebugLoc()->getInlinedAt()) {}
154
155 const DILocalVariable *getVar() const { return Variable; }
156 const OptFragmentInfo &getFragment() const { return Fragment; }
157 const DILocation *getInlinedAt() const { return InlinedAt; }
158
159 const FragmentInfo getFragmentDefault() const {
160 return Fragment.getValueOr(DefaultFragment);
161 }
162
163 static bool isFragmentDefault(FragmentInfo &F) {
164 return F == DefaultFragment;
165 }
166
167 bool operator==(const DebugVariable &Other) const {
168 return std::tie(Variable, Fragment, InlinedAt) ==
169 std::tie(Other.Variable, Other.Fragment, Other.InlinedAt);
170 }
171
172 bool operator<(const DebugVariable &Other) const {
173 return std::tie(Variable, Fragment, InlinedAt) <
174 std::tie(Other.Variable, Other.Fragment, Other.InlinedAt);
175 }
176 };
177
178 friend struct llvm::DenseMapInfo<DebugVariable>;
179
180 /// A pair of debug variable and value location.
181 struct VarLoc {
182 // The location at which a spilled variable resides. It consists of a
183 // register and an offset.
184 struct SpillLoc {
185 unsigned SpillBase;
186 int SpillOffset;
187 bool operator==(const SpillLoc &Other) const {
188 return SpillBase == Other.SpillBase && SpillOffset == Other.SpillOffset;
189 }
190 };
191
192 /// Identity of the variable at this location.
193 const DebugVariable Var;
194
195 /// The expression applied to this location.
196 const DIExpression *Expr;
197
198 /// DBG_VALUE to clone var/expr information from if this location
199 /// is moved.
200 const MachineInstr &MI;
201
202 mutable UserValueScopes UVS;
203 enum VarLocKind {
204 InvalidKind = 0,
205 RegisterKind,
206 SpillLocKind,
207 ImmediateKind,
208 EntryValueKind
209 } Kind = InvalidKind;
210
211 /// The value location. Stored separately to avoid repeatedly
212 /// extracting it from MI.
213 union {
214 uint64_t RegNo;
215 SpillLoc SpillLocation;
216 uint64_t Hash;
217 int64_t Immediate;
218 const ConstantFP *FPImm;
219 const ConstantInt *CImm;
220 } Loc;
221
222 VarLoc(const MachineInstr &MI, LexicalScopes &LS,
223 VarLocKind K = InvalidKind)
224 : Var(MI), Expr(MI.getDebugExpression()), MI(MI),
225 UVS(MI.getDebugLoc(), LS) {
226 static_assert((sizeof(Loc) == sizeof(uint64_t)),
227 "hash does not cover all members of Loc");
228 assert(MI.isDebugValue() && "not a DBG_VALUE")((MI.isDebugValue() && "not a DBG_VALUE") ? static_cast
<void> (0) : __assert_fail ("MI.isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 228, __PRETTY_FUNCTION__))
;
229 assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE")((MI.getNumOperands() == 4 && "malformed DBG_VALUE") ?
static_cast<void> (0) : __assert_fail ("MI.getNumOperands() == 4 && \"malformed DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 229, __PRETTY_FUNCTION__))
;
230 if (int RegNo = isDbgValueDescribedByReg(MI)) {
231 Kind = MI.isDebugEntryValue() ? EntryValueKind : RegisterKind;
232 Loc.RegNo = RegNo;
233 } else if (MI.getOperand(0).isImm()) {
234 Kind = ImmediateKind;
235 Loc.Immediate = MI.getOperand(0).getImm();
236 } else if (MI.getOperand(0).isFPImm()) {
237 Kind = ImmediateKind;
238 Loc.FPImm = MI.getOperand(0).getFPImm();
239 } else if (MI.getOperand(0).isCImm()) {
240 Kind = ImmediateKind;
241 Loc.CImm = MI.getOperand(0).getCImm();
242 }
243 assert((Kind != ImmediateKind || !MI.isDebugEntryValue()) &&(((Kind != ImmediateKind || !MI.isDebugEntryValue()) &&
"entry values must be register locations") ? static_cast<
void> (0) : __assert_fail ("(Kind != ImmediateKind || !MI.isDebugEntryValue()) && \"entry values must be register locations\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 244, __PRETTY_FUNCTION__))
244 "entry values must be register locations")(((Kind != ImmediateKind || !MI.isDebugEntryValue()) &&
"entry values must be register locations") ? static_cast<
void> (0) : __assert_fail ("(Kind != ImmediateKind || !MI.isDebugEntryValue()) && \"entry values must be register locations\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 244, __PRETTY_FUNCTION__))
;
245 }
246
247 /// The constructor for spill locations.
248 VarLoc(const MachineInstr &MI, unsigned SpillBase, int SpillOffset,
249 LexicalScopes &LS, const MachineInstr &OrigMI)
250 : Var(MI), Expr(MI.getDebugExpression()), MI(OrigMI),
251 UVS(MI.getDebugLoc(), LS) {
252 assert(MI.isDebugValue() && "not a DBG_VALUE")((MI.isDebugValue() && "not a DBG_VALUE") ? static_cast
<void> (0) : __assert_fail ("MI.isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 252, __PRETTY_FUNCTION__))
;
253 assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE")((MI.getNumOperands() == 4 && "malformed DBG_VALUE") ?
static_cast<void> (0) : __assert_fail ("MI.getNumOperands() == 4 && \"malformed DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 253, __PRETTY_FUNCTION__))
;
254 Kind = SpillLocKind;
255 Loc.SpillLocation = {SpillBase, SpillOffset};
256 }
257
258 // Is the Loc field a constant or constant object?
259 bool isConstant() const { return Kind == ImmediateKind; }
260
261 /// If this variable is described by a register, return it,
262 /// otherwise return 0.
263 unsigned isDescribedByReg() const {
264 if (Kind == RegisterKind)
265 return Loc.RegNo;
266 return 0;
267 }
268
269 /// Determine whether the lexical scope of this value's debug location
270 /// dominates MBB.
271 bool dominates(MachineBasicBlock &MBB) const { return UVS.dominates(&MBB); }
272
273#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
274 LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void dump() const { MI.dump(); }
275#endif
276
277 bool operator==(const VarLoc &Other) const {
278 return Kind == Other.Kind && Var == Other.Var &&
279 Loc.Hash == Other.Loc.Hash && Expr == Other.Expr;
280 }
281
282 /// This operator guarantees that VarLocs are sorted by Variable first.
283 bool operator<(const VarLoc &Other) const {
284 return std::tie(Var, Kind, Loc.Hash, Expr) <
285 std::tie(Other.Var, Other.Kind, Other.Loc.Hash, Other.Expr);
286 }
287 };
288
289 using DebugParamMap = SmallDenseMap<const DILocalVariable *, MachineInstr *>;
290 using VarLocMap = UniqueVector<VarLoc>;
291 using VarLocSet = SparseBitVector<>;
292 using VarLocInMBB = SmallDenseMap<const MachineBasicBlock *, VarLocSet>;
293 struct TransferDebugPair {
294 MachineInstr *TransferInst;
295 MachineInstr *DebugInst;
296 };
297 using TransferMap = SmallVector<TransferDebugPair, 4>;
298
299 // Types for recording sets of variable fragments that overlap. For a given
300 // local variable, we record all other fragments of that variable that could
301 // overlap it, to reduce search time.
302 using FragmentOfVar =
303 std::pair<const DILocalVariable *, DIExpression::FragmentInfo>;
304 using OverlapMap =
305 DenseMap<FragmentOfVar, SmallVector<DIExpression::FragmentInfo, 1>>;
306
307 // Helper while building OverlapMap, a map of all fragments seen for a given
308 // DILocalVariable.
309 using VarToFragments =
310 DenseMap<const DILocalVariable *, SmallSet<FragmentInfo, 4>>;
311
312 /// This holds the working set of currently open ranges. For fast
313 /// access, this is done both as a set of VarLocIDs, and a map of
314 /// DebugVariable to recent VarLocID. Note that a DBG_VALUE ends all
315 /// previous open ranges for the same variable.
316 class OpenRangesSet {
317 VarLocSet VarLocs;
318 SmallDenseMap<DebugVariable, unsigned, 8> Vars;
319 OverlapMap &OverlappingFragments;
320
321 public:
322 OpenRangesSet(OverlapMap &_OLapMap) : OverlappingFragments(_OLapMap) {}
323
324 const VarLocSet &getVarLocs() const { return VarLocs; }
325
326 /// Terminate all open ranges for Var by removing it from the set.
327 void erase(DebugVariable Var);
328
329 /// Terminate all open ranges listed in \c KillSet by removing
330 /// them from the set.
331 void erase(const VarLocSet &KillSet, const VarLocMap &VarLocIDs) {
332 VarLocs.intersectWithComplement(KillSet);
333 for (unsigned ID : KillSet)
334 Vars.erase(VarLocIDs[ID].Var);
335 }
336
337 /// Insert a new range into the set.
338 void insert(unsigned VarLocID, DebugVariable Var) {
339 VarLocs.set(VarLocID);
340 Vars.insert({Var, VarLocID});
341 }
342
343 /// Insert a set of ranges.
344 void insertFromLocSet(const VarLocSet &ToLoad, const VarLocMap &Map) {
345 for (unsigned Id : ToLoad) {
346 const VarLoc &Var = Map[Id];
347 insert(Id, Var.Var);
348 }
349 }
350
351 /// Empty the set.
352 void clear() {
353 VarLocs.clear();
354 Vars.clear();
355 }
356
357 /// Return whether the set is empty or not.
358 bool empty() const {
359 assert(Vars.empty() == VarLocs.empty() && "open ranges are inconsistent")((Vars.empty() == VarLocs.empty() && "open ranges are inconsistent"
) ? static_cast<void> (0) : __assert_fail ("Vars.empty() == VarLocs.empty() && \"open ranges are inconsistent\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 359, __PRETTY_FUNCTION__))
;
360 return VarLocs.empty();
361 }
362 };
363
364 /// Tests whether this instruction is a spill to a stack location.
365 bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF);
366
367 /// Decide if @MI is a spill instruction and return true if it is. We use 2
368 /// criteria to make this decision:
369 /// - Is this instruction a store to a spill slot?
370 /// - Is there a register operand that is both used and killed?
371 /// TODO: Store optimization can fold spills into other stores (including
372 /// other spills). We do not handle this yet (more than one memory operand).
373 bool isLocationSpill(const MachineInstr &MI, MachineFunction *MF,
374 unsigned &Reg);
375
376 /// If a given instruction is identified as a spill, return the spill location
377 /// and set \p Reg to the spilled register.
378 Optional<VarLoc::SpillLoc> isRestoreInstruction(const MachineInstr &MI,
379 MachineFunction *MF,
380 unsigned &Reg);
381 /// Given a spill instruction, extract the register and offset used to
382 /// address the spill location in a target independent way.
383 VarLoc::SpillLoc extractSpillBaseRegAndOffset(const MachineInstr &MI);
384 void insertTransferDebugPair(MachineInstr &MI, OpenRangesSet &OpenRanges,
385 TransferMap &Transfers, VarLocMap &VarLocIDs,
386 unsigned OldVarID, TransferKind Kind,
387 unsigned NewReg = 0);
388
389 void transferDebugValue(const MachineInstr &MI, OpenRangesSet &OpenRanges,
390 VarLocMap &VarLocIDs);
391 void transferSpillOrRestoreInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
392 VarLocMap &VarLocIDs, TransferMap &Transfers);
393 void emitEntryValues(MachineInstr &MI, OpenRangesSet &OpenRanges,
394 VarLocMap &VarLocIDs, TransferMap &Transfers,
395 DebugParamMap &DebugEntryVals,
396 SparseBitVector<> &KillSet);
397 void transferRegisterCopy(MachineInstr &MI, OpenRangesSet &OpenRanges,
398 VarLocMap &VarLocIDs, TransferMap &Transfers);
399 void transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges,
400 VarLocMap &VarLocIDs, TransferMap &Transfers,
401 DebugParamMap &DebugEntryVals);
402 bool transferTerminator(MachineBasicBlock *MBB, OpenRangesSet &OpenRanges,
403 VarLocInMBB &OutLocs, const VarLocMap &VarLocIDs);
404
405 void process(MachineInstr &MI, OpenRangesSet &OpenRanges,
406 VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
407 TransferMap &Transfers, DebugParamMap &DebugEntryVals,
408 OverlapMap &OverlapFragments,
409 VarToFragments &SeenFragments);
410
411 void accumulateFragmentMap(MachineInstr &MI, VarToFragments &SeenFragments,
412 OverlapMap &OLapMap);
413
414 bool join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
415 const VarLocMap &VarLocIDs,
416 SmallPtrSet<const MachineBasicBlock *, 16> &Visited,
417 SmallPtrSetImpl<const MachineBasicBlock *> &ArtificialBlocks,
418 VarLocInMBB &PendingInLocs);
419
420 /// Create DBG_VALUE insts for inlocs that have been propagated but
421 /// had their instruction creation deferred.
422 void flushPendingLocs(VarLocInMBB &PendingInLocs, VarLocMap &VarLocIDs);
423
424 bool ExtendRanges(MachineFunction &MF);
425
426public:
427 static char ID;
428
429 /// Default construct and initialize the pass.
430 LiveDebugValues();
431
432 /// Tell the pass manager which passes we depend on and what
433 /// information we preserve.
434 void getAnalysisUsage(AnalysisUsage &AU) const override;
435
436 MachineFunctionProperties getRequiredProperties() const override {
437 return MachineFunctionProperties().set(
438 MachineFunctionProperties::Property::NoVRegs);
439 }
440
441 /// Print to ostream with a message.
442 void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V,
443 const VarLocMap &VarLocIDs, const char *msg,
444 raw_ostream &Out) const;
445
446 /// Calculate the liveness information for the given machine function.
447 bool runOnMachineFunction(MachineFunction &MF) override;
448};
449
450} // end anonymous namespace
451
452namespace llvm {
453
454template <> struct DenseMapInfo<LiveDebugValues::DebugVariable> {
455 using DV = LiveDebugValues::DebugVariable;
456 using OptFragmentInfo = LiveDebugValues::OptFragmentInfo;
457 using FragmentInfo = LiveDebugValues::FragmentInfo;
458
459 // Empty key: no key should be generated that has no DILocalVariable.
460 static inline DV getEmptyKey() {
461 return DV(nullptr, OptFragmentInfo(), nullptr);
462 }
463
464 // Difference in tombstone is that the Optional is meaningful
465 static inline DV getTombstoneKey() {
466 return DV(nullptr, OptFragmentInfo({0, 0}), nullptr);
467 }
468
469 static unsigned getHashValue(const DV &D) {
470 unsigned HV = 0;
471 const OptFragmentInfo &Fragment = D.getFragment();
472 if (Fragment)
473 HV = DenseMapInfo<FragmentInfo>::getHashValue(*Fragment);
474
475 return hash_combine(D.getVar(), HV, D.getInlinedAt());
476 }
477
478 static bool isEqual(const DV &A, const DV &B) { return A == B; }
479};
480
481} // namespace llvm
482
483//===----------------------------------------------------------------------===//
484// Implementation
485//===----------------------------------------------------------------------===//
486
487const DIExpression::FragmentInfo
488 LiveDebugValues::DebugVariable::DefaultFragment = {
489 std::numeric_limits<uint64_t>::max(),
490 std::numeric_limits<uint64_t>::min()};
491
492char LiveDebugValues::ID = 0;
493
494char &llvm::LiveDebugValuesID = LiveDebugValues::ID;
495
496INITIALIZE_PASS(LiveDebugValues, DEBUG_TYPE, "Live DEBUG_VALUE analysis",static void *initializeLiveDebugValuesPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Live DEBUG_VALUE analysis"
, "livedebugvalues", &LiveDebugValues::ID, PassInfo::NormalCtor_t
(callDefaultCtor<LiveDebugValues>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeLiveDebugValuesPassFlag; void llvm::initializeLiveDebugValuesPass
(PassRegistry &Registry) { llvm::call_once(InitializeLiveDebugValuesPassFlag
, initializeLiveDebugValuesPassOnce, std::ref(Registry)); }
497 false, false)static void *initializeLiveDebugValuesPassOnce(PassRegistry &
Registry) { PassInfo *PI = new PassInfo( "Live DEBUG_VALUE analysis"
, "livedebugvalues", &LiveDebugValues::ID, PassInfo::NormalCtor_t
(callDefaultCtor<LiveDebugValues>), false, false); Registry
.registerPass(*PI, true); return PI; } static llvm::once_flag
InitializeLiveDebugValuesPassFlag; void llvm::initializeLiveDebugValuesPass
(PassRegistry &Registry) { llvm::call_once(InitializeLiveDebugValuesPassFlag
, initializeLiveDebugValuesPassOnce, std::ref(Registry)); }
498
499/// Default construct and initialize the pass.
500LiveDebugValues::LiveDebugValues() : MachineFunctionPass(ID) {
501 initializeLiveDebugValuesPass(*PassRegistry::getPassRegistry());
502}
503
504/// Tell the pass manager which passes we depend on and what information we
505/// preserve.
506void LiveDebugValues::getAnalysisUsage(AnalysisUsage &AU) const {
507 AU.setPreservesCFG();
508 MachineFunctionPass::getAnalysisUsage(AU);
509}
510
511/// Erase a variable from the set of open ranges, and additionally erase any
512/// fragments that may overlap it.
513void LiveDebugValues::OpenRangesSet::erase(DebugVariable Var) {
514 // Erasure helper.
515 auto DoErase = [this](DebugVariable VarToErase) {
516 auto It = Vars.find(VarToErase);
517 if (It != Vars.end()) {
518 unsigned ID = It->second;
519 VarLocs.reset(ID);
520 Vars.erase(It);
521 }
522 };
523
524 // Erase the variable/fragment that ends here.
525 DoErase(Var);
526
527 // Extract the fragment. Interpret an empty fragment as one that covers all
528 // possible bits.
529 FragmentInfo ThisFragment = Var.getFragmentDefault();
530
531 // There may be fragments that overlap the designated fragment. Look them up
532 // in the pre-computed overlap map, and erase them too.
533 auto MapIt = OverlappingFragments.find({Var.getVar(), ThisFragment});
534 if (MapIt != OverlappingFragments.end()) {
535 for (auto Fragment : MapIt->second) {
536 LiveDebugValues::OptFragmentInfo FragmentHolder;
537 if (!DebugVariable::isFragmentDefault(Fragment))
538 FragmentHolder = LiveDebugValues::OptFragmentInfo(Fragment);
539 DoErase({Var.getVar(), FragmentHolder, Var.getInlinedAt()});
540 }
541 }
542}
543
544//===----------------------------------------------------------------------===//
545// Debug Range Extension Implementation
546//===----------------------------------------------------------------------===//
547
548#ifndef NDEBUG
549void LiveDebugValues::printVarLocInMBB(const MachineFunction &MF,
550 const VarLocInMBB &V,
551 const VarLocMap &VarLocIDs,
552 const char *msg,
553 raw_ostream &Out) const {
554 Out << '\n' << msg << '\n';
555 for (const MachineBasicBlock &BB : MF) {
556 const VarLocSet &L = V.lookup(&BB);
557 if (L.empty())
558 continue;
559 Out << "MBB: " << BB.getNumber() << ":\n";
560 for (unsigned VLL : L) {
561 const VarLoc &VL = VarLocIDs[VLL];
562 Out << " Var: " << VL.Var.getVar()->getName();
563 Out << " MI: ";
564 VL.dump();
565 }
566 }
567 Out << "\n";
568}
569#endif
570
571LiveDebugValues::VarLoc::SpillLoc
572LiveDebugValues::extractSpillBaseRegAndOffset(const MachineInstr &MI) {
573 assert(MI.hasOneMemOperand() &&((MI.hasOneMemOperand() && "Spill instruction does not have exactly one memory operand?"
) ? static_cast<void> (0) : __assert_fail ("MI.hasOneMemOperand() && \"Spill instruction does not have exactly one memory operand?\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 574, __PRETTY_FUNCTION__))
574 "Spill instruction does not have exactly one memory operand?")((MI.hasOneMemOperand() && "Spill instruction does not have exactly one memory operand?"
) ? static_cast<void> (0) : __assert_fail ("MI.hasOneMemOperand() && \"Spill instruction does not have exactly one memory operand?\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 574, __PRETTY_FUNCTION__))
;
575 auto MMOI = MI.memoperands_begin();
576 const PseudoSourceValue *PVal = (*MMOI)->getPseudoValue();
577 assert(PVal->kind() == PseudoSourceValue::FixedStack &&((PVal->kind() == PseudoSourceValue::FixedStack &&
"Inconsistent memory operand in spill instruction") ? static_cast
<void> (0) : __assert_fail ("PVal->kind() == PseudoSourceValue::FixedStack && \"Inconsistent memory operand in spill instruction\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 578, __PRETTY_FUNCTION__))
578 "Inconsistent memory operand in spill instruction")((PVal->kind() == PseudoSourceValue::FixedStack &&
"Inconsistent memory operand in spill instruction") ? static_cast
<void> (0) : __assert_fail ("PVal->kind() == PseudoSourceValue::FixedStack && \"Inconsistent memory operand in spill instruction\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 578, __PRETTY_FUNCTION__))
;
579 int FI = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
580 const MachineBasicBlock *MBB = MI.getParent();
581 unsigned Reg;
582 int Offset = TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg);
583 return {Reg, Offset};
584}
585
586/// End all previous ranges related to @MI and start a new range from @MI
587/// if it is a DBG_VALUE instr.
588void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
589 OpenRangesSet &OpenRanges,
590 VarLocMap &VarLocIDs) {
591 if (!MI.isDebugValue())
592 return;
593 const DILocalVariable *Var = MI.getDebugVariable();
594 const DIExpression *Expr = MI.getDebugExpression();
595 const DILocation *DebugLoc = MI.getDebugLoc();
596 const DILocation *InlinedAt = DebugLoc->getInlinedAt();
597 assert(Var->isValidLocationForIntrinsic(DebugLoc) &&((Var->isValidLocationForIntrinsic(DebugLoc) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Var->isValidLocationForIntrinsic(DebugLoc) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 598, __PRETTY_FUNCTION__))
598 "Expected inlined-at fields to agree")((Var->isValidLocationForIntrinsic(DebugLoc) && "Expected inlined-at fields to agree"
) ? static_cast<void> (0) : __assert_fail ("Var->isValidLocationForIntrinsic(DebugLoc) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 598, __PRETTY_FUNCTION__))
;
599
600 // End all previous ranges of Var.
601 DebugVariable V(Var, Expr, InlinedAt);
602 OpenRanges.erase(V);
603
604 // Add the VarLoc to OpenRanges from this DBG_VALUE.
605 unsigned ID;
606 if (isDbgValueDescribedByReg(MI) || MI.getOperand(0).isImm() ||
607 MI.getOperand(0).isFPImm() || MI.getOperand(0).isCImm()) {
608 // Use normal VarLoc constructor for registers and immediates.
609 VarLoc VL(MI, LS);
610 ID = VarLocIDs.insert(VL);
611 OpenRanges.insert(ID, VL.Var);
612 } else if (MI.hasOneMemOperand()) {
613 llvm_unreachable("DBG_VALUE with mem operand encountered after regalloc?")::llvm::llvm_unreachable_internal("DBG_VALUE with mem operand encountered after regalloc?"
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 613)
;
614 } else {
615 // This must be an undefined location. We should leave OpenRanges closed.
616 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&((MI.getOperand(0).isReg() && MI.getOperand(0).getReg
() == 0 && "Unexpected non-undef DBG_VALUE encountered"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 && \"Unexpected non-undef DBG_VALUE encountered\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 617, __PRETTY_FUNCTION__))
617 "Unexpected non-undef DBG_VALUE encountered")((MI.getOperand(0).isReg() && MI.getOperand(0).getReg
() == 0 && "Unexpected non-undef DBG_VALUE encountered"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 && \"Unexpected non-undef DBG_VALUE encountered\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 617, __PRETTY_FUNCTION__))
;
618 }
619}
620
621void LiveDebugValues::emitEntryValues(MachineInstr &MI,
622 OpenRangesSet &OpenRanges,
623 VarLocMap &VarLocIDs,
624 TransferMap &Transfers,
625 DebugParamMap &DebugEntryVals,
626 SparseBitVector<> &KillSet) {
627 MachineFunction *MF = MI.getParent()->getParent();
628 for (unsigned ID : KillSet) {
629 if (!VarLocIDs[ID].Var.getVar()->isParameter())
630 continue;
631
632 const MachineInstr *CurrDebugInstr = &VarLocIDs[ID].MI;
633
634 // If parameter's DBG_VALUE is not in the map that means we can't
635 // generate parameter's entry value.
636 if (!DebugEntryVals.count(CurrDebugInstr->getDebugVariable()))
637 continue;
638
639 auto ParamDebugInstr = DebugEntryVals[CurrDebugInstr->getDebugVariable()];
640 DIExpression *NewExpr = DIExpression::prepend(
641 ParamDebugInstr->getDebugExpression(), DIExpression::EntryValue);
642 MachineInstr *EntryValDbgMI =
643 BuildMI(*MF, ParamDebugInstr->getDebugLoc(), ParamDebugInstr->getDesc(),
644 ParamDebugInstr->isIndirectDebugValue(),
645 ParamDebugInstr->getOperand(0).getReg(),
646 ParamDebugInstr->getDebugVariable(), NewExpr);
647
648 if (ParamDebugInstr->isIndirectDebugValue())
649 EntryValDbgMI->getOperand(1).setImm(
650 ParamDebugInstr->getOperand(1).getImm());
651
652 Transfers.push_back({&MI, EntryValDbgMI});
653 VarLoc VL(*EntryValDbgMI, LS);
654 unsigned EntryValLocID = VarLocIDs.insert(VL);
655 OpenRanges.insert(EntryValLocID, VL.Var);
656 }
657}
658
659/// Create new TransferDebugPair and insert it in \p Transfers. The VarLoc
660/// with \p OldVarID should be deleted form \p OpenRanges and replaced with
661/// new VarLoc. If \p NewReg is different than default zero value then the
662/// new location will be register location created by the copy like instruction,
663/// otherwise it is variable's location on the stack.
664void LiveDebugValues::insertTransferDebugPair(
665 MachineInstr &MI, OpenRangesSet &OpenRanges, TransferMap &Transfers,
666 VarLocMap &VarLocIDs, unsigned OldVarID, TransferKind Kind,
667 unsigned NewReg) {
668 const MachineInstr *DebugInstr = &VarLocIDs[OldVarID].MI;
669 MachineFunction *MF = MI.getParent()->getParent();
670 MachineInstr *NewDebugInstr;
671
672 auto ProcessVarLoc = [&MI, &OpenRanges, &Transfers, &DebugInstr,
673 &VarLocIDs](VarLoc &VL, MachineInstr *NewDebugInstr) {
674 unsigned LocId = VarLocIDs.insert(VL);
675
676 // Close this variable's previous location range.
677 DebugVariable V(*DebugInstr);
678 OpenRanges.erase(V);
679
680 OpenRanges.insert(LocId, VL.Var);
681 // The newly created DBG_VALUE instruction NewDebugInstr must be inserted
682 // after MI. Keep track of the pairing.
683 TransferDebugPair MIP = {&MI, NewDebugInstr};
684 Transfers.push_back(MIP);
685 };
686
687 // End all previous ranges of Var.
688 OpenRanges.erase(VarLocIDs[OldVarID].Var);
689 switch (Kind) {
690 case TransferKind::TransferCopy: {
691 assert(NewReg &&((NewReg && "No register supplied when handling a copy of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a copy of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 692, __PRETTY_FUNCTION__))
692 "No register supplied when handling a copy of a debug value")((NewReg && "No register supplied when handling a copy of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a copy of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 692, __PRETTY_FUNCTION__))
;
693 // Create a DBG_VALUE instruction to describe the Var in its new
694 // register location.
695 NewDebugInstr = BuildMI(
696 *MF, DebugInstr->getDebugLoc(), DebugInstr->getDesc(),
697 DebugInstr->isIndirectDebugValue(), NewReg,
698 DebugInstr->getDebugVariable(), DebugInstr->getDebugExpression());
699 if (DebugInstr->isIndirectDebugValue())
700 NewDebugInstr->getOperand(1).setImm(DebugInstr->getOperand(1).getImm());
701 VarLoc VL(*NewDebugInstr, LS);
702 ProcessVarLoc(VL, NewDebugInstr);
703 LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for register copy: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register copy: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
704 NewDebugInstr->print(dbgs(), /*IsStandalone*/false,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register copy: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
705 /*SkipOpers*/false, /*SkipDebugLoc*/false,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register copy: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
706 /*AddNewLine*/true, TII))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register copy: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
;
707 return;
708 }
709 case TransferKind::TransferSpill: {
710 // Create a DBG_VALUE instruction to describe the Var in its spilled
711 // location.
712 VarLoc::SpillLoc SpillLocation = extractSpillBaseRegAndOffset(MI);
713 auto *SpillExpr = DIExpression::prepend(DebugInstr->getDebugExpression(),
714 DIExpression::ApplyOffset,
715 SpillLocation.SpillOffset);
716 NewDebugInstr = BuildMI(
717 *MF, DebugInstr->getDebugLoc(), DebugInstr->getDesc(), true,
718 SpillLocation.SpillBase, DebugInstr->getDebugVariable(), SpillExpr);
719 VarLoc VL(*NewDebugInstr, SpillLocation.SpillBase,
720 SpillLocation.SpillOffset, LS, *DebugInstr);
721 ProcessVarLoc(VL, NewDebugInstr);
722 LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for spill: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
723 NewDebugInstr->print(dbgs(), /*IsStandalone*/false,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for spill: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
724 /*SkipOpers*/false, /*SkipDebugLoc*/false,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for spill: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
725 /*AddNewLine*/true, TII))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for spill: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
;
726 return;
727 }
728 case TransferKind::TransferRestore: {
729 assert(NewReg &&((NewReg && "No register supplied when handling a restore of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a restore of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 730, __PRETTY_FUNCTION__))
730 "No register supplied when handling a restore of a debug value")((NewReg && "No register supplied when handling a restore of a debug value"
) ? static_cast<void> (0) : __assert_fail ("NewReg && \"No register supplied when handling a restore of a debug value\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 730, __PRETTY_FUNCTION__))
;
731 MachineFunction *MF = MI.getMF();
732 DIBuilder DIB(*const_cast<Function &>(MF->getFunction()).getParent());
733 // DebugInstr refers to the pre-spill location, therefore we can reuse
734 // its expression.
735 NewDebugInstr = BuildMI(
736 *MF, DebugInstr->getDebugLoc(), DebugInstr->getDesc(), false, NewReg,
737 DebugInstr->getDebugVariable(), DebugInstr->getDebugExpression());
738 VarLoc VL(*NewDebugInstr, LS);
739 ProcessVarLoc(VL, NewDebugInstr);
740 LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for register restore: ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register restore: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
741 NewDebugInstr->print(dbgs(), /*IsStandalone*/false,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register restore: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
742 /*SkipOpers*/false, /*SkipDebugLoc*/false,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register restore: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
743 /*AddNewLine*/true, TII))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Creating DBG_VALUE inst for register restore: "
; NewDebugInstr->print(dbgs(), false, false, false, true, TII
); } } while (false)
;
744 return;
745 }
746 }
747 llvm_unreachable("Invalid transfer kind")::llvm::llvm_unreachable_internal("Invalid transfer kind", "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 747)
;
748}
749
750/// A definition of a register may mark the end of a range.
751void LiveDebugValues::transferRegisterDef(
752 MachineInstr &MI, OpenRangesSet &OpenRanges, VarLocMap &VarLocIDs,
753 TransferMap &Transfers, DebugParamMap &DebugEntryVals) {
754 MachineFunction *MF = MI.getMF();
755 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
756 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
757 SparseBitVector<> KillSet;
758 for (const MachineOperand &MO : MI.operands()) {
759 // Determine whether the operand is a register def. Assume that call
760 // instructions never clobber SP, because some backends (e.g., AArch64)
761 // never list SP in the regmask.
762 if (MO.isReg() && MO.isDef() && MO.getReg() &&
763 Register::isPhysicalRegister(MO.getReg()) &&
764 !(MI.isCall() && MO.getReg() == SP)) {
765 // Remove ranges of all aliased registers.
766 for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
767 for (unsigned ID : OpenRanges.getVarLocs())
768 if (VarLocIDs[ID].isDescribedByReg() == *RAI)
769 KillSet.set(ID);
770 } else if (MO.isRegMask()) {
771 // Remove ranges of all clobbered registers. Register masks don't usually
772 // list SP as preserved. While the debug info may be off for an
773 // instruction or two around callee-cleanup calls, transferring the
774 // DEBUG_VALUE across the call is still a better user experience.
775 for (unsigned ID : OpenRanges.getVarLocs()) {
776 unsigned Reg = VarLocIDs[ID].isDescribedByReg();
777 if (Reg && Reg != SP && MO.clobbersPhysReg(Reg))
778 KillSet.set(ID);
779 }
780 }
781 }
782 OpenRanges.erase(KillSet, VarLocIDs);
783
784 if (auto *TPC = getAnalysisIfAvailable<TargetPassConfig>()) {
785 auto &TM = TPC->getTM<TargetMachine>();
786 if (TM.Options.EnableDebugEntryValues)
787 emitEntryValues(MI, OpenRanges, VarLocIDs, Transfers, DebugEntryVals,
788 KillSet);
789 }
790}
791
792bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
793 MachineFunction *MF) {
794 // TODO: Handle multiple stores folded into one.
795 if (!MI.hasOneMemOperand())
28
Calling 'MachineInstr::hasOneMemOperand'
31
Returning from 'MachineInstr::hasOneMemOperand'
32
Taking false branch
796 return false;
797
798 if (!MI.getSpillSize(TII) && !MI.getFoldedSpillSize(TII))
33
Assuming the condition is false
34
Taking false branch
799 return false; // This is not a spill instruction, since no valid size was
800 // returned from either function.
801
802 return true;
35
Returning the value 1, which participates in a condition later
803}
804
805bool LiveDebugValues::isLocationSpill(const MachineInstr &MI,
806 MachineFunction *MF, unsigned &Reg) {
807 if (!isSpillInstruction(MI, MF))
27
Calling 'LiveDebugValues::isSpillInstruction'
36
Returning from 'LiveDebugValues::isSpillInstruction'
37
Taking false branch
808 return false;
809
810 auto isKilledReg = [&](const MachineOperand MO, unsigned &Reg) {
811 if (!MO.isReg() || !MO.isUse()) {
40
Calling 'MachineOperand::isReg'
43
Returning from 'MachineOperand::isReg'
44
Assuming the condition is false
45
Taking false branch
812 Reg = 0;
813 return false;
814 }
815 Reg = MO.getReg();
816 return MO.isKill();
46
Returning without writing to 'Reg'
47
Returning value, which participates in a condition later
817 };
818
819 for (const MachineOperand &MO : MI.operands()) {
38
Assuming '__begin1' is not equal to '__end1'
820 // In a spill instruction generated by the InlineSpiller the spilled
821 // register has its kill flag set.
822 if (isKilledReg(MO, Reg))
39
Calling 'operator()'
48
Returning from 'operator()'
49
Assuming the condition is true
50
Taking true branch
823 return true;
51
Returning without writing to 'Reg'
52
Returning the value 1, which participates in a condition later
824 if (Reg != 0) {
825 // Check whether next instruction kills the spilled register.
826 // FIXME: Current solution does not cover search for killed register in
827 // bundles and instructions further down the chain.
828 auto NextI = std::next(MI.getIterator());
829 // Skip next instruction that points to basic block end iterator.
830 if (MI.getParent()->end() == NextI)
831 continue;
832 unsigned RegNext;
833 for (const MachineOperand &MONext : NextI->operands()) {
834 // Return true if we came across the register from the
835 // previous spill instruction that is killed in NextI.
836 if (isKilledReg(MONext, RegNext) && RegNext == Reg)
837 return true;
838 }
839 }
840 }
841 // Return false if we didn't find spilled register.
842 return false;
843}
844
845Optional<LiveDebugValues::VarLoc::SpillLoc>
846LiveDebugValues::isRestoreInstruction(const MachineInstr &MI,
847 MachineFunction *MF, unsigned &Reg) {
848 if (!MI.hasOneMemOperand())
849 return None;
850
851 // FIXME: Handle folded restore instructions with more than one memory
852 // operand.
853 if (MI.getRestoreSize(TII)) {
854 Reg = MI.getOperand(0).getReg();
855 return extractSpillBaseRegAndOffset(MI);
856 }
857 return None;
858}
859
860/// A spilled register may indicate that we have to end the current range of
861/// a variable and create a new one for the spill location.
862/// A restored register may indicate the reverse situation.
863/// We don't want to insert any instructions in process(), so we just create
864/// the DBG_VALUE without inserting it and keep track of it in \p Transfers.
865/// It will be inserted into the BB when we're done iterating over the
866/// instructions.
867void LiveDebugValues::transferSpillOrRestoreInst(MachineInstr &MI,
868 OpenRangesSet &OpenRanges,
869 VarLocMap &VarLocIDs,
870 TransferMap &Transfers) {
871 MachineFunction *MF = MI.getMF();
872 TransferKind TKind;
873 unsigned Reg;
22
'Reg' declared without an initial value
874 Optional<VarLoc::SpillLoc> Loc;
875
876 LLVM_DEBUG(dbgs() << "Examining instruction: "; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Examining instruction: "
; MI.dump();; } } while (false)
;
23
Assuming 'DebugFlag' is false
24
Loop condition is false. Exiting loop
877
878 // First, if there are any DBG_VALUEs pointing at a spill slot that is
879 // written to, then close the variable location. The value in memory
880 // will have changed.
881 VarLocSet KillSet;
882 if (isSpillInstruction(MI, MF)) {
25
Taking false branch
883 Loc = extractSpillBaseRegAndOffset(MI);
884 for (unsigned ID : OpenRanges.getVarLocs()) {
885 const VarLoc &VL = VarLocIDs[ID];
886 if (VL.Kind == VarLoc::SpillLocKind && VL.Loc.SpillLocation == *Loc) {
887 // This location is overwritten by the current instruction -- terminate
888 // the open range, and insert an explicit DBG_VALUE $noreg.
889 //
890 // Doing this at a later stage would require re-interpreting all
891 // DBG_VALUes and DIExpressions to identify whether they point at
892 // memory, and then analysing all memory writes to see if they
893 // overwrite that memory, which is expensive.
894 //
895 // At this stage, we already know which DBG_VALUEs are for spills and
896 // where they are located; it's best to fix handle overwrites now.
897 KillSet.set(ID);
898 MachineInstr *NewDebugInstr =
899 BuildMI(*MF, VL.MI.getDebugLoc(), VL.MI.getDesc(),
900 VL.MI.isIndirectDebugValue(), 0, // $noreg
901 VL.MI.getDebugVariable(), VL.MI.getDebugExpression());
902 Transfers.push_back({&MI, NewDebugInstr});
903 }
904 }
905 OpenRanges.erase(KillSet, VarLocIDs);
906 }
907
908 // Try to recognise spill and restore instructions that may create a new
909 // variable location.
910 if (isLocationSpill(MI, MF, Reg)) {
26
Calling 'LiveDebugValues::isLocationSpill'
53
Returning from 'LiveDebugValues::isLocationSpill'
54
Taking true branch
911 TKind = TransferKind::TransferSpill;
912 LLVM_DEBUG(dbgs() << "Recognized as spill: "; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Recognized as spill: "
; MI.dump();; } } while (false)
;
55
Assuming 'DebugFlag' is false
56
Loop condition is false. Exiting loop
913 LLVM_DEBUG
56.1
'DebugFlag' is false
56.1
'DebugFlag' is false
56.1
'DebugFlag' is false
(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false)
57
Loop condition is false. Exiting loop
914 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false)
;
915 } else {
916 if (!(Loc = isRestoreInstruction(MI, MF, Reg)))
917 return;
918 TKind = TransferKind::TransferRestore;
919 LLVM_DEBUG(dbgs() << "Recognized as restore: "; MI.dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Recognized as restore: "
; MI.dump();; } } while (false)
;
920 LLVM_DEBUG(dbgs() << "Register: " << Reg << " " << printReg(Reg, TRI)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false)
921 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Register: " << Reg
<< " " << printReg(Reg, TRI) << "\n"; } } while
(false)
;
922 }
923 // Check if the register or spill location is the location of a debug value.
924 for (unsigned ID : OpenRanges.getVarLocs()) {
925 if (TKind
57.1
'TKind' is equal to TransferSpill
57.1
'TKind' is equal to TransferSpill
57.1
'TKind' is equal to TransferSpill
== TransferKind::TransferSpill &&
926 VarLocIDs[ID].isDescribedByReg() == Reg) {
58
The right operand of '==' is a garbage value
927 LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Spilling Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false)
928 << VarLocIDs[ID].Var.getVar()->getName() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Spilling Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false)
;
929 } else if (TKind == TransferKind::TransferRestore &&
930 VarLocIDs[ID].Kind == VarLoc::SpillLocKind &&
931 VarLocIDs[ID].Loc.SpillLocation == *Loc) {
932 LLVM_DEBUG(dbgs() << "Restoring Register " << printReg(Reg, TRI) << '('do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Restoring Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false)
933 << VarLocIDs[ID].Var.getVar()->getName() << ")\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Restoring Register " <<
printReg(Reg, TRI) << '(' << VarLocIDs[ID].Var.getVar
()->getName() << ")\n"; } } while (false)
;
934 } else
935 continue;
936 insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID, TKind,
937 Reg);
938 return;
939 }
940}
941
942/// If \p MI is a register copy instruction, that copies a previously tracked
943/// value from one register to another register that is callee saved, we
944/// create new DBG_VALUE instruction described with copy destination register.
945void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
946 OpenRangesSet &OpenRanges,
947 VarLocMap &VarLocIDs,
948 TransferMap &Transfers) {
949 const MachineOperand *SrcRegOp, *DestRegOp;
950
951 if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
952 !DestRegOp->isDef())
953 return;
954
955 auto isCalleSavedReg = [&](unsigned Reg) {
956 for (MCRegAliasIterator RAI(Reg, TRI, true); RAI.isValid(); ++RAI)
957 if (CalleeSavedRegs.test(*RAI))
958 return true;
959 return false;
960 };
961
962 Register SrcReg = SrcRegOp->getReg();
963 Register DestReg = DestRegOp->getReg();
964
965 // We want to recognize instructions where destination register is callee
966 // saved register. If register that could be clobbered by the call is
967 // included, there would be a great chance that it is going to be clobbered
968 // soon. It is more likely that previous register location, which is callee
969 // saved, is going to stay unclobbered longer, even if it is killed.
970 if (!isCalleSavedReg(DestReg))
971 return;
972
973 for (unsigned ID : OpenRanges.getVarLocs()) {
974 if (VarLocIDs[ID].isDescribedByReg() == SrcReg) {
975 insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID,
976 TransferKind::TransferCopy, DestReg);
977 return;
978 }
979 }
980}
981
982/// Terminate all open ranges at the end of the current basic block.
983bool LiveDebugValues::transferTerminator(MachineBasicBlock *CurMBB,
984 OpenRangesSet &OpenRanges,
985 VarLocInMBB &OutLocs,
986 const VarLocMap &VarLocIDs) {
987 bool Changed = false;
988
989 if (OpenRanges.empty())
990 return false;
991
992 LLVM_DEBUG(for (unsigned IDdo { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(); }; } }
while (false)
993 : OpenRanges.getVarLocs()) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(); }; } }
while (false)
994 // Copy OpenRanges to OutLocs, if not already present.do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(); }; } }
while (false)
995 dbgs() << "Add to OutLocs in MBB #" << CurMBB->getNumber() << ": ";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(); }; } }
while (false)
996 VarLocIDs[ID].dump();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(); }; } }
while (false)
997 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { for (unsigned ID : OpenRanges.getVarLocs
()) { dbgs() << "Add to OutLocs in MBB #" << CurMBB
->getNumber() << ": "; VarLocIDs[ID].dump(); }; } }
while (false)
;
998 VarLocSet &VLS = OutLocs[CurMBB];
999 Changed = VLS != OpenRanges.getVarLocs();
1000 // New OutLocs set may be different due to spill, restore or register
1001 // copy instruction processing.
1002 if (Changed)
1003 VLS = OpenRanges.getVarLocs();
1004 OpenRanges.clear();
1005 return Changed;
1006}
1007
1008/// Accumulate a mapping between each DILocalVariable fragment and other
1009/// fragments of that DILocalVariable which overlap. This reduces work during
1010/// the data-flow stage from "Find any overlapping fragments" to "Check if the
1011/// known-to-overlap fragments are present".
1012/// \param MI A previously unprocessed DEBUG_VALUE instruction to analyze for
1013/// fragment usage.
1014/// \param SeenFragments Map from DILocalVariable to all fragments of that
1015/// Variable which are known to exist.
1016/// \param OverlappingFragments The overlap map being constructed, from one
1017/// Var/Fragment pair to a vector of fragments known to overlap.
1018void LiveDebugValues::accumulateFragmentMap(MachineInstr &MI,
1019 VarToFragments &SeenFragments,
1020 OverlapMap &OverlappingFragments) {
1021 DebugVariable MIVar(MI);
1022 FragmentInfo ThisFragment = MIVar.getFragmentDefault();
1023
1024 // If this is the first sighting of this variable, then we are guaranteed
1025 // there are currently no overlapping fragments either. Initialize the set
1026 // of seen fragments, record no overlaps for the current one, and return.
1027 auto SeenIt = SeenFragments.find(MIVar.getVar());
1028 if (SeenIt == SeenFragments.end()) {
1029 SmallSet<FragmentInfo, 4> OneFragment;
1030 OneFragment.insert(ThisFragment);
1031 SeenFragments.insert({MIVar.getVar(), OneFragment});
1032
1033 OverlappingFragments.insert({{MIVar.getVar(), ThisFragment}, {}});
1034 return;
1035 }
1036
1037 // If this particular Variable/Fragment pair already exists in the overlap
1038 // map, it has already been accounted for.
1039 auto IsInOLapMap =
1040 OverlappingFragments.insert({{MIVar.getVar(), ThisFragment}, {}});
1041 if (!IsInOLapMap.second)
1042 return;
1043
1044 auto &ThisFragmentsOverlaps = IsInOLapMap.first->second;
1045 auto &AllSeenFragments = SeenIt->second;
1046
1047 // Otherwise, examine all other seen fragments for this variable, with "this"
1048 // fragment being a previously unseen fragment. Record any pair of
1049 // overlapping fragments.
1050 for (auto &ASeenFragment : AllSeenFragments) {
1051 // Does this previously seen fragment overlap?
1052 if (DIExpression::fragmentsOverlap(ThisFragment, ASeenFragment)) {
1053 // Yes: Mark the current fragment as being overlapped.
1054 ThisFragmentsOverlaps.push_back(ASeenFragment);
1055 // Mark the previously seen fragment as being overlapped by the current
1056 // one.
1057 auto ASeenFragmentsOverlaps =
1058 OverlappingFragments.find({MIVar.getVar(), ASeenFragment});
1059 assert(ASeenFragmentsOverlaps != OverlappingFragments.end() &&((ASeenFragmentsOverlaps != OverlappingFragments.end() &&
"Previously seen var fragment has no vector of overlaps") ? static_cast
<void> (0) : __assert_fail ("ASeenFragmentsOverlaps != OverlappingFragments.end() && \"Previously seen var fragment has no vector of overlaps\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 1060, __PRETTY_FUNCTION__))
1060 "Previously seen var fragment has no vector of overlaps")((ASeenFragmentsOverlaps != OverlappingFragments.end() &&
"Previously seen var fragment has no vector of overlaps") ? static_cast
<void> (0) : __assert_fail ("ASeenFragmentsOverlaps != OverlappingFragments.end() && \"Previously seen var fragment has no vector of overlaps\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 1060, __PRETTY_FUNCTION__))
;
1061 ASeenFragmentsOverlaps->second.push_back(ThisFragment);
1062 }
1063 }
1064
1065 AllSeenFragments.insert(ThisFragment);
1066}
1067
1068/// This routine creates OpenRanges and OutLocs.
1069void LiveDebugValues::process(MachineInstr &MI, OpenRangesSet &OpenRanges,
1070 VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
1071 TransferMap &Transfers,
1072 DebugParamMap &DebugEntryVals,
1073 OverlapMap &OverlapFragments,
1074 VarToFragments &SeenFragments) {
1075 transferDebugValue(MI, OpenRanges, VarLocIDs);
1076 transferRegisterDef(MI, OpenRanges, VarLocIDs, Transfers,
1077 DebugEntryVals);
1078 transferRegisterCopy(MI, OpenRanges, VarLocIDs, Transfers);
1079 transferSpillOrRestoreInst(MI, OpenRanges, VarLocIDs, Transfers);
21
Calling 'LiveDebugValues::transferSpillOrRestoreInst'
1080}
1081
1082/// This routine joins the analysis results of all incoming edges in @MBB by
1083/// inserting a new DBG_VALUE instruction at the start of the @MBB - if the same
1084/// source variable in all the predecessors of @MBB reside in the same location.
1085bool LiveDebugValues::join(
1086 MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
1087 const VarLocMap &VarLocIDs,
1088 SmallPtrSet<const MachineBasicBlock *, 16> &Visited,
1089 SmallPtrSetImpl<const MachineBasicBlock *> &ArtificialBlocks,
1090 VarLocInMBB &PendingInLocs) {
1091 LLVM_DEBUG(dbgs() << "join MBB: " << MBB.getNumber() << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "join MBB: " << MBB
.getNumber() << "\n"; } } while (false)
;
1092 bool Changed = false;
1093
1094 VarLocSet InLocsT; // Temporary incoming locations.
1095
1096 // For all predecessors of this MBB, find the set of VarLocs that
1097 // can be joined.
1098 int NumVisited = 0;
1099 for (auto p : MBB.predecessors()) {
1100 // Ignore backedges if we have not visited the predecessor yet. As the
1101 // predecessor hasn't yet had locations propagated into it, most locations
1102 // will not yet be valid, so treat them as all being uninitialized and
1103 // potentially valid. If a location guessed to be correct here is
1104 // invalidated later, we will remove it when we revisit this block.
1105 if (!Visited.count(p)) {
1106 LLVM_DEBUG(dbgs() << " ignoring unvisited pred MBB: " << p->getNumber()do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << " ignoring unvisited pred MBB: "
<< p->getNumber() << "\n"; } } while (false)
1107 << "\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << " ignoring unvisited pred MBB: "
<< p->getNumber() << "\n"; } } while (false)
;
1108 continue;
1109 }
1110 auto OL = OutLocs.find(p);
1111 // Join is null in case of empty OutLocs from any of the pred.
1112 if (OL == OutLocs.end())
1113 return false;
1114
1115 // Just copy over the Out locs to incoming locs for the first visited
1116 // predecessor, and for all other predecessors join the Out locs.
1117 if (!NumVisited)
1118 InLocsT = OL->second;
1119 else
1120 InLocsT &= OL->second;
1121
1122 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1123 if (!InLocsT.empty()) {do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1124 for (auto ID : InLocsT)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1125 dbgs() << " gathered candidate incoming var: "do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1126 << VarLocIDs[ID].Var.getVar()->getName() << "\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1127 }do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
1128 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { if (!InLocsT.empty()) { for (auto ID
: InLocsT) dbgs() << " gathered candidate incoming var: "
<< VarLocIDs[ID].Var.getVar()->getName() << "\n"
; } }; } } while (false)
;
1129
1130 NumVisited++;
1131 }
1132
1133 // Filter out DBG_VALUES that are out of scope.
1134 VarLocSet KillSet;
1135 bool IsArtificial = ArtificialBlocks.count(&MBB);
1136 if (!IsArtificial) {
1137 for (auto ID : InLocsT) {
1138 if (!VarLocIDs[ID].dominates(MBB)) {
1139 KillSet.set(ID);
1140 LLVM_DEBUG({do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
1141 auto Name = VarLocIDs[ID].Var.getVar()->getName();do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
1142 dbgs() << " killing " << Name << ", it doesn't dominate MBB\n";do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
1143 })do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { { auto Name = VarLocIDs[ID].Var.getVar
()->getName(); dbgs() << " killing " << Name <<
", it doesn't dominate MBB\n"; }; } } while (false)
;
1144 }
1145 }
1146 }
1147 InLocsT.intersectWithComplement(KillSet);
1148
1149 // As we are processing blocks in reverse post-order we
1150 // should have processed at least one predecessor, unless it
1151 // is the entry block which has no predecessor.
1152 assert((NumVisited || MBB.pred_empty()) &&(((NumVisited || MBB.pred_empty()) && "Should have processed at least one predecessor"
) ? static_cast<void> (0) : __assert_fail ("(NumVisited || MBB.pred_empty()) && \"Should have processed at least one predecessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 1153, __PRETTY_FUNCTION__))
1153 "Should have processed at least one predecessor")(((NumVisited || MBB.pred_empty()) && "Should have processed at least one predecessor"
) ? static_cast<void> (0) : __assert_fail ("(NumVisited || MBB.pred_empty()) && \"Should have processed at least one predecessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 1153, __PRETTY_FUNCTION__))
;
1154
1155 VarLocSet &ILS = InLocs[&MBB];
1156 VarLocSet &Pending = PendingInLocs[&MBB];
1157
1158 // New locations will have DBG_VALUE insts inserted at the start of the
1159 // block, after location propagation has finished. Record the insertions
1160 // that we need to perform in the Pending set.
1161 VarLocSet Diff = InLocsT;
1162 Diff.intersectWithComplement(ILS);
1163 for (auto ID : Diff) {
1164 Pending.set(ID);
1165 ILS.set(ID);
1166 ++NumInserted;
1167 Changed = true;
1168 }
1169
1170 // We may have lost locations by learning about a predecessor that either
1171 // loses or moves a variable. Find any locations in ILS that are not in the
1172 // new in-locations, and delete those.
1173 VarLocSet Removed = ILS;
1174 Removed.intersectWithComplement(InLocsT);
1175 for (auto ID : Removed) {
1176 Pending.reset(ID);
1177 ILS.reset(ID);
1178 ++NumRemoved;
1179 Changed = true;
1180 }
1181
1182 return Changed;
1183}
1184
1185void LiveDebugValues::flushPendingLocs(VarLocInMBB &PendingInLocs,
1186 VarLocMap &VarLocIDs) {
1187 // PendingInLocs records all locations propagated into blocks, which have
1188 // not had DBG_VALUE insts created. Go through and create those insts now.
1189 for (auto &Iter : PendingInLocs) {
1190 // Map is keyed on a constant pointer, unwrap it so we can insert insts.
1191 auto &MBB = const_cast<MachineBasicBlock &>(*Iter.first);
1192 VarLocSet &Pending = Iter.second;
1193
1194 for (unsigned ID : Pending) {
1195 // The ID location is live-in to MBB -- work out what kind of machine
1196 // location it is and create a DBG_VALUE.
1197 const VarLoc &DiffIt = VarLocIDs[ID];
1198 const MachineInstr *DebugInstr = &DiffIt.MI;
1199 MachineInstr *MI = nullptr;
1200
1201 if (DiffIt.isConstant()) {
1202 MachineOperand MO(DebugInstr->getOperand(0));
1203 MI = BuildMI(MBB, MBB.instr_begin(), DebugInstr->getDebugLoc(),
1204 DebugInstr->getDesc(), false, MO,
1205 DebugInstr->getDebugVariable(),
1206 DebugInstr->getDebugExpression());
1207 } else {
1208 auto *DebugExpr = DebugInstr->getDebugExpression();
1209 Register Reg = DebugInstr->getOperand(0).getReg();
1210 bool IsIndirect = DebugInstr->isIndirectDebugValue();
1211
1212 if (DiffIt.Kind == VarLoc::SpillLocKind) {
1213 // This is is a spilt location; DebugInstr refers to the unspilt
1214 // location. We need to rebuild the spilt location expression and
1215 // point the DBG_VALUE at the frame register.
1216 DebugExpr = DIExpression::prepend(
1217 DebugInstr->getDebugExpression(), DIExpression::ApplyOffset,
1218 DiffIt.Loc.SpillLocation.SpillOffset);
1219 Reg = TRI->getFrameRegister(*DebugInstr->getMF());
1220 IsIndirect = true;
1221 }
1222
1223 MI = BuildMI(MBB, MBB.instr_begin(), DebugInstr->getDebugLoc(),
1224 DebugInstr->getDesc(), IsIndirect, Reg,
1225 DebugInstr->getDebugVariable(), DebugExpr);
1226 }
1227 (void)MI;
1228 LLVM_DEBUG(dbgs() << "Inserted: "; MI->dump();)do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Inserted: "; MI->dump
();; } } while (false)
;
1229 }
1230 }
1231}
1232
1233/// Calculate the liveness information for the given machine function and
1234/// extend ranges across basic blocks.
1235bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
1236 LLVM_DEBUG(dbgs() << "\nDebug Range Extension\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "\nDebug Range Extension\n"
; } } while (false)
;
6
Assuming 'DebugFlag' is false
7
Loop condition is false. Exiting loop
1237
1238 bool Changed = false;
1239 bool OLChanged = false;
1240 bool MBBJoined = false;
1241
1242 VarLocMap VarLocIDs; // Map VarLoc<>unique ID for use in bitvectors.
1243 OverlapMap OverlapFragments; // Map of overlapping variable fragments
1244 OpenRangesSet OpenRanges(OverlapFragments);
1245 // Ranges that are open until end of bb.
1246 VarLocInMBB OutLocs; // Ranges that exist beyond bb.
1247 VarLocInMBB InLocs; // Ranges that are incoming after joining.
1248 TransferMap Transfers; // DBG_VALUEs associated with spills.
1249 VarLocInMBB PendingInLocs; // Ranges that are incoming after joining, but
1250 // that we have deferred creating DBG_VALUE insts
1251 // for immediately.
1252
1253 VarToFragments SeenFragments;
1254
1255 // Blocks which are artificial, i.e. blocks which exclusively contain
1256 // instructions without locations, or with line 0 locations.
1257 SmallPtrSet<const MachineBasicBlock *, 16> ArtificialBlocks;
1258
1259 DenseMap<unsigned int, MachineBasicBlock *> OrderToBB;
1260 DenseMap<MachineBasicBlock *, unsigned int> BBToOrder;
1261 std::priority_queue<unsigned int, std::vector<unsigned int>,
1262 std::greater<unsigned int>>
1263 Worklist;
1264 std::priority_queue<unsigned int, std::vector<unsigned int>,
1265 std::greater<unsigned int>>
1266 Pending;
1267
1268 // Besides parameter's modification, check whether a DBG_VALUE is inlined
1269 // in order to deduce whether the variable that it tracks comes from
1270 // a different function. If that is the case we can't track its entry value.
1271 auto IsUnmodifiedFuncParam = [&](const MachineInstr &MI) {
1272 auto *DIVar = MI.getDebugVariable();
1273 return DIVar->isParameter() && DIVar->isNotModified() &&
1274 !MI.getDebugLoc()->getInlinedAt();
1275 };
1276
1277 const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
1278 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
1279 Register FP = TRI->getFrameRegister(MF);
1280 auto IsRegOtherThanSPAndFP = [&](const MachineOperand &Op) -> bool {
1281 return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
1282 };
1283
1284 // Working set of currently collected debug variables mapped to DBG_VALUEs
1285 // representing candidates for production of debug entry values.
1286 DebugParamMap DebugEntryVals;
1287
1288 MachineBasicBlock &First_MBB = *(MF.begin());
1289 // Only in the case of entry MBB collect DBG_VALUEs representing
1290 // function parameters in order to generate debug entry values for them.
1291 // Currently, we generate debug entry values only for parameters that are
1292 // unmodified throughout the function and located in a register.
1293 // TODO: Add support for parameters that are described as fragments.
1294 // TODO: Add support for modified arguments that can be expressed
1295 // by using its entry value.
1296 // TODO: Add support for local variables that are expressed in terms of
1297 // parameters entry values.
1298 for (auto &MI : First_MBB)
1299 if (MI.isDebugValue() && IsUnmodifiedFuncParam(MI) &&
1300 !MI.isIndirectDebugValue() && IsRegOtherThanSPAndFP(MI.getOperand(0)) &&
1301 !DebugEntryVals.count(MI.getDebugVariable()) &&
1302 !MI.getDebugExpression()->isFragment())
1303 DebugEntryVals[MI.getDebugVariable()] = &MI;
1304
1305 // Initialize per-block structures and scan for fragment overlaps.
1306 for (auto &MBB : MF) {
1307 PendingInLocs[&MBB] = VarLocSet();
1308
1309 for (auto &MI : MBB) {
1310 if (MI.isDebugValue())
1311 accumulateFragmentMap(MI, SeenFragments, OverlapFragments);
1312 }
1313 }
1314
1315 auto hasNonArtificialLocation = [](const MachineInstr &MI) -> bool {
1316 if (const DebugLoc &DL = MI.getDebugLoc())
1317 return DL.getLine() != 0;
1318 return false;
1319 };
1320 for (auto &MBB : MF)
1321 if (none_of(MBB.instrs(), hasNonArtificialLocation))
1322 ArtificialBlocks.insert(&MBB);
1323
1324 LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after initialization", dbgs()); } } while (false)
8
Assuming 'DebugFlag' is false
9
Loop condition is false. Exiting loop
1325 "OutLocs after initialization", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after initialization", dbgs()); } } while (false)
;
1326
1327 ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
1328 unsigned int RPONumber = 0;
1329 for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
10
Loop condition is false. Execution continues on line 1339
1330 OrderToBB[RPONumber] = *RI;
1331 BBToOrder[*RI] = RPONumber;
1332 Worklist.push(RPONumber);
1333 ++RPONumber;
1334 }
1335 // This is a standard "union of predecessor outs" dataflow problem.
1336 // To solve it, we perform join() and process() using the two worklist method
1337 // until the ranges converge.
1338 // Ranges have converged when both worklists are empty.
1339 SmallPtrSet<const MachineBasicBlock *, 16> Visited;
1340 while (!Worklist.empty() || !Pending.empty()) {
11
Assuming the condition is false
12
Assuming the condition is true
13
Loop condition is true. Entering loop body
1341 // We track what is on the pending worklist to avoid inserting the same
1342 // thing twice. We could avoid this with a custom priority queue, but this
1343 // is probably not worth it.
1344 SmallPtrSet<MachineBasicBlock *, 16> OnPending;
1345 LLVM_DEBUG(dbgs() << "Processing Worklist\n")do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { dbgs() << "Processing Worklist\n"
; } } while (false)
;
14
Assuming 'DebugFlag' is false
15
Loop condition is false. Exiting loop
1346 while (!Worklist.empty()) {
16
Assuming the condition is true
17
Loop condition is true. Entering loop body
1347 MachineBasicBlock *MBB = OrderToBB[Worklist.top()];
1348 Worklist.pop();
1349 MBBJoined = join(*MBB, OutLocs, InLocs, VarLocIDs, Visited,
1350 ArtificialBlocks, PendingInLocs);
1351 MBBJoined |= Visited.insert(MBB).second;
1352 if (MBBJoined) {
18
Assuming 'MBBJoined' is true
19
Taking true branch
1353 MBBJoined = false;
1354 Changed = true;
1355 // Now that we have started to extend ranges across BBs we need to
1356 // examine spill instructions to see whether they spill registers that
1357 // correspond to user variables.
1358 // First load any pending inlocs.
1359 OpenRanges.insertFromLocSet(PendingInLocs[MBB], VarLocIDs);
1360 for (auto &MI : *MBB)
1361 process(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
20
Calling 'LiveDebugValues::process'
1362 DebugEntryVals, OverlapFragments, SeenFragments);
1363 OLChanged |= transferTerminator(MBB, OpenRanges, OutLocs, VarLocIDs);
1364
1365 // Add any DBG_VALUE instructions necessitated by spills.
1366 for (auto &TR : Transfers)
1367 MBB->insertAfterBundle(TR.TransferInst->getIterator(), TR.DebugInst);
1368 Transfers.clear();
1369
1370 LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after propagating", dbgs()); } } while (false)
1371 "OutLocs after propagating", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "OutLocs after propagating", dbgs()); } } while (false)
;
1372 LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, InLocs, VarLocIDs
, "InLocs after propagating", dbgs()); } } while (false)
1373 "InLocs after propagating", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, InLocs, VarLocIDs
, "InLocs after propagating", dbgs()); } } while (false)
;
1374
1375 if (OLChanged) {
1376 OLChanged = false;
1377 for (auto s : MBB->successors())
1378 if (OnPending.insert(s).second) {
1379 Pending.push(BBToOrder[s]);
1380 }
1381 }
1382 }
1383 }
1384 Worklist.swap(Pending);
1385 // At this point, pending must be empty, since it was just the empty
1386 // worklist
1387 assert(Pending.empty() && "Pending should be empty")((Pending.empty() && "Pending should be empty") ? static_cast
<void> (0) : __assert_fail ("Pending.empty() && \"Pending should be empty\""
, "/build/llvm-toolchain-snapshot-10~svn373517/lib/CodeGen/LiveDebugValues.cpp"
, 1387, __PRETTY_FUNCTION__))
;
1388 }
1389
1390 // Deferred inlocs will not have had any DBG_VALUE insts created; do
1391 // that now.
1392 flushPendingLocs(PendingInLocs, VarLocIDs);
1393
1394 LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, OutLocs, VarLocIDs
, "Final OutLocs", dbgs()); } } while (false)
;
1395 LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs()))do { if (::llvm::DebugFlag && ::llvm::isCurrentDebugType
("livedebugvalues")) { printVarLocInMBB(MF, InLocs, VarLocIDs
, "Final InLocs", dbgs()); } } while (false)
;
1396 return Changed;
1397}
1398
1399bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
1400 if (!MF.getFunction().getSubprogram())
1
Assuming the condition is false
2
Taking false branch
1401 // LiveDebugValues will already have removed all DBG_VALUEs.
1402 return false;
1403
1404 // Skip functions from NoDebug compilation units.
1405 if (MF.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
3
Assuming the condition is false
4
Taking false branch
1406 DICompileUnit::NoDebug)
1407 return false;
1408
1409 TRI = MF.getSubtarget().getRegisterInfo();
1410 TII = MF.getSubtarget().getInstrInfo();
1411 TFI = MF.getSubtarget().getFrameLowering();
1412 TFI->determineCalleeSaves(MF, CalleeSavedRegs,
1413 std::make_unique<RegScavenger>().get());
1414 LS.initialize(MF);
1415
1416 bool Changed = ExtendRanges(MF);
5
Calling 'LiveDebugValues::ExtendRanges'
1417 return Changed;
1418}

/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h

1//===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineInstr class, which is the
10// basic representation for all target dependent machine instructions used by
11// the back end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEINSTR_H
16#define LLVM_CODEGEN_MACHINEINSTR_H
17
18#include "llvm/ADT/DenseMapInfo.h"
19#include "llvm/ADT/PointerSumType.h"
20#include "llvm/ADT/ilist.h"
21#include "llvm/ADT/ilist_node.h"
22#include "llvm/ADT/iterator_range.h"
23#include "llvm/Analysis/AliasAnalysis.h"
24#include "llvm/CodeGen/MachineMemOperand.h"
25#include "llvm/CodeGen/MachineOperand.h"
26#include "llvm/CodeGen/TargetOpcodes.h"
27#include "llvm/IR/DebugInfoMetadata.h"
28#include "llvm/IR/DebugLoc.h"
29#include "llvm/IR/InlineAsm.h"
30#include "llvm/MC/MCInstrDesc.h"
31#include "llvm/MC/MCSymbol.h"
32#include "llvm/Support/ArrayRecycler.h"
33#include "llvm/Support/TrailingObjects.h"
34#include <algorithm>
35#include <cassert>
36#include <cstdint>
37#include <utility>
38
39namespace llvm {
40
41template <typename T> class ArrayRef;
42class DIExpression;
43class DILocalVariable;
44class MachineBasicBlock;
45class MachineFunction;
46class MachineMemOperand;
47class MachineRegisterInfo;
48class ModuleSlotTracker;
49class raw_ostream;
50template <typename T> class SmallVectorImpl;
51class SmallBitVector;
52class StringRef;
53class TargetInstrInfo;
54class TargetRegisterClass;
55class TargetRegisterInfo;
56
57//===----------------------------------------------------------------------===//
58/// Representation of each machine instruction.
59///
60/// This class isn't a POD type, but it must have a trivial destructor. When a
61/// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62/// without having their destructor called.
63///
64class MachineInstr
65 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock,
66 ilist_sentinel_tracking<true>> {
67public:
68 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator;
69
70 /// Flags to specify different kinds of comments to output in
71 /// assembly code. These flags carry semantic information not
72 /// otherwise easily derivable from the IR text.
73 ///
74 enum CommentFlag {
75 ReloadReuse = 0x1, // higher bits are reserved for target dep comments.
76 NoSchedComment = 0x2,
77 TAsmComments = 0x4 // Target Asm comments should start from this value.
78 };
79
80 enum MIFlag {
81 NoFlags = 0,
82 FrameSetup = 1 << 0, // Instruction is used as a part of
83 // function frame setup code.
84 FrameDestroy = 1 << 1, // Instruction is used as a part of
85 // function frame destruction code.
86 BundledPred = 1 << 2, // Instruction has bundled predecessors.
87 BundledSucc = 1 << 3, // Instruction has bundled successors.
88 FmNoNans = 1 << 4, // Instruction does not support Fast
89 // math nan values.
90 FmNoInfs = 1 << 5, // Instruction does not support Fast
91 // math infinity values.
92 FmNsz = 1 << 6, // Instruction is not required to retain
93 // signed zero values.
94 FmArcp = 1 << 7, // Instruction supports Fast math
95 // reciprocal approximations.
96 FmContract = 1 << 8, // Instruction supports Fast math
97 // contraction operations like fma.
98 FmAfn = 1 << 9, // Instruction may map to Fast math
99 // instrinsic approximation.
100 FmReassoc = 1 << 10, // Instruction supports Fast math
101 // reassociation of operand order.
102 NoUWrap = 1 << 11, // Instruction supports binary operator
103 // no unsigned wrap.
104 NoSWrap = 1 << 12, // Instruction supports binary operator
105 // no signed wrap.
106 IsExact = 1 << 13, // Instruction supports division is
107 // known to be exact.
108 FPExcept = 1 << 14, // Instruction may raise floating-point
109 // exceptions.
110 };
111
112private:
113 const MCInstrDesc *MCID; // Instruction descriptor.
114 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block.
115
116 // Operands are allocated by an ArrayRecycler.
117 MachineOperand *Operands = nullptr; // Pointer to the first operand.
118 unsigned NumOperands = 0; // Number of operands on instruction.
119 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity;
120 OperandCapacity CapOperands; // Capacity of the Operands array.
121
122 uint16_t Flags = 0; // Various bits of additional
123 // information about machine
124 // instruction.
125
126 uint8_t AsmPrinterFlags = 0; // Various bits of information used by
127 // the AsmPrinter to emit helpful
128 // comments. This is *not* semantic
129 // information. Do not use this for
130 // anything other than to convey comment
131 // information to AsmPrinter.
132
133 /// Internal implementation detail class that provides out-of-line storage for
134 /// extra info used by the machine instruction when this info cannot be stored
135 /// in-line within the instruction itself.
136 ///
137 /// This has to be defined eagerly due to the implementation constraints of
138 /// `PointerSumType` where it is used.
139 class ExtraInfo final
140 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *> {
141 public:
142 static ExtraInfo *create(BumpPtrAllocator &Allocator,
143 ArrayRef<MachineMemOperand *> MMOs,
144 MCSymbol *PreInstrSymbol = nullptr,
145 MCSymbol *PostInstrSymbol = nullptr) {
146 bool HasPreInstrSymbol = PreInstrSymbol != nullptr;
147 bool HasPostInstrSymbol = PostInstrSymbol != nullptr;
148 auto *Result = new (Allocator.Allocate(
149 totalSizeToAlloc<MachineMemOperand *, MCSymbol *>(
150 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol),
151 alignof(ExtraInfo)))
152 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol);
153
154 // Copy the actual data into the trailing objects.
155 std::copy(MMOs.begin(), MMOs.end(),
156 Result->getTrailingObjects<MachineMemOperand *>());
157
158 if (HasPreInstrSymbol)
159 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol;
160 if (HasPostInstrSymbol)
161 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] =
162 PostInstrSymbol;
163
164 return Result;
165 }
166
167 ArrayRef<MachineMemOperand *> getMMOs() const {
168 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs);
169 }
170
171 MCSymbol *getPreInstrSymbol() const {
172 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr;
173 }
174
175 MCSymbol *getPostInstrSymbol() const {
176 return HasPostInstrSymbol
177 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol]
178 : nullptr;
179 }
180
181 private:
182 friend TrailingObjects;
183
184 // Description of the extra info, used to interpret the actual optional
185 // data appended.
186 //
187 // Note that this is not terribly space optimized. This leaves a great deal
188 // of flexibility to fit more in here later.
189 const int NumMMOs;
190 const bool HasPreInstrSymbol;
191 const bool HasPostInstrSymbol;
192
193 // Implement the `TrailingObjects` internal API.
194 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const {
195 return NumMMOs;
196 }
197 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const {
198 return HasPreInstrSymbol + HasPostInstrSymbol;
199 }
200
201 // Just a boring constructor to allow us to initialize the sizes. Always use
202 // the `create` routine above.
203 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol)
204 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol),
205 HasPostInstrSymbol(HasPostInstrSymbol) {}
206 };
207
208 /// Enumeration of the kinds of inline extra info available. It is important
209 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
210 /// it accessible as an `ArrayRef`.
211 enum ExtraInfoInlineKinds {
212 EIIK_MMO = 0,
213 EIIK_PreInstrSymbol,
214 EIIK_PostInstrSymbol,
215 EIIK_OutOfLine
216 };
217
218 // We store extra information about the instruction here. The common case is
219 // expected to be nothing or a single pointer (typically a MMO or a symbol).
220 // We work to optimize this common case by storing it inline here rather than
221 // requiring a separate allocation, but we fall back to an allocation when
222 // multiple pointers are needed.
223 PointerSumType<ExtraInfoInlineKinds,
224 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>,
225 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>,
226 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>,
227 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>>
228 Info;
229
230 DebugLoc debugLoc; // Source line information.
231
232 // Intrusive list support
233 friend struct ilist_traits<MachineInstr>;
234 friend struct ilist_callback_traits<MachineBasicBlock>;
235 void setParent(MachineBasicBlock *P) { Parent = P; }
236
237 /// This constructor creates a copy of the given
238 /// MachineInstr in the given MachineFunction.
239 MachineInstr(MachineFunction &, const MachineInstr &);
240
241 /// This constructor create a MachineInstr and add the implicit operands.
242 /// It reserves space for number of operands specified by
243 /// MCInstrDesc. An explicit DebugLoc is supplied.
244 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
245 bool NoImp = false);
246
247 // MachineInstrs are pool-allocated and owned by MachineFunction.
248 friend class MachineFunction;
249
250public:
251 MachineInstr(const MachineInstr &) = delete;
252 MachineInstr &operator=(const MachineInstr &) = delete;
253 // Use MachineFunction::DeleteMachineInstr() instead.
254 ~MachineInstr() = delete;
255
256 const MachineBasicBlock* getParent() const { return Parent; }
257 MachineBasicBlock* getParent() { return Parent; }
258
259 /// Return the function that contains the basic block that this instruction
260 /// belongs to.
261 ///
262 /// Note: this is undefined behaviour if the instruction does not have a
263 /// parent.
264 const MachineFunction *getMF() const;
265 MachineFunction *getMF() {
266 return const_cast<MachineFunction *>(
267 static_cast<const MachineInstr *>(this)->getMF());
268 }
269
270 /// Return the asm printer flags bitvector.
271 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
272
273 /// Clear the AsmPrinter bitvector.
274 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
275
276 /// Return whether an AsmPrinter flag is set.
277 bool getAsmPrinterFlag(CommentFlag Flag) const {
278 return AsmPrinterFlags & Flag;
279 }
280
281 /// Set a flag for the AsmPrinter.
282 void setAsmPrinterFlag(uint8_t Flag) {
283 AsmPrinterFlags |= Flag;
284 }
285
286 /// Clear specific AsmPrinter flags.
287 void clearAsmPrinterFlag(CommentFlag Flag) {
288 AsmPrinterFlags &= ~Flag;
289 }
290
291 /// Return the MI flags bitvector.
292 uint16_t getFlags() const {
293 return Flags;
294 }
295
296 /// Return whether an MI flag is set.
297 bool getFlag(MIFlag Flag) const {
298 return Flags & Flag;
299 }
300
301 /// Set a MI flag.
302 void setFlag(MIFlag Flag) {
303 Flags |= (uint16_t)Flag;
304 }
305
306 void setFlags(unsigned flags) {
307 // Filter out the automatically maintained flags.
308 unsigned Mask = BundledPred | BundledSucc;
309 Flags = (Flags & Mask) | (flags & ~Mask);
310 }
311
312 /// clearFlag - Clear a MI flag.
313 void clearFlag(MIFlag Flag) {
314 Flags &= ~((uint16_t)Flag);
315 }
316
317 /// Return true if MI is in a bundle (but not the first MI in a bundle).
318 ///
319 /// A bundle looks like this before it's finalized:
320 /// ----------------
321 /// | MI |
322 /// ----------------
323 /// |
324 /// ----------------
325 /// | MI * |
326 /// ----------------
327 /// |
328 /// ----------------
329 /// | MI * |
330 /// ----------------
331 /// In this case, the first MI starts a bundle but is not inside a bundle, the
332 /// next 2 MIs are considered "inside" the bundle.
333 ///
334 /// After a bundle is finalized, it looks like this:
335 /// ----------------
336 /// | Bundle |
337 /// ----------------
338 /// |
339 /// ----------------
340 /// | MI * |
341 /// ----------------
342 /// |
343 /// ----------------
344 /// | MI * |
345 /// ----------------
346 /// |
347 /// ----------------
348 /// | MI * |
349 /// ----------------
350 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
351 /// a bundle, but the next three MIs are.
352 bool isInsideBundle() const {
353 return getFlag(BundledPred);
354 }
355
356 /// Return true if this instruction part of a bundle. This is true
357 /// if either itself or its following instruction is marked "InsideBundle".
358 bool isBundled() const {
359 return isBundledWithPred() || isBundledWithSucc();
360 }
361
362 /// Return true if this instruction is part of a bundle, and it is not the
363 /// first instruction in the bundle.
364 bool isBundledWithPred() const { return getFlag(BundledPred); }
365
366 /// Return true if this instruction is part of a bundle, and it is not the
367 /// last instruction in the bundle.
368 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
369
370 /// Bundle this instruction with its predecessor. This can be an unbundled
371 /// instruction, or it can be the first instruction in a bundle.
372 void bundleWithPred();
373
374 /// Bundle this instruction with its successor. This can be an unbundled
375 /// instruction, or it can be the last instruction in a bundle.
376 void bundleWithSucc();
377
378 /// Break bundle above this instruction.
379 void unbundleFromPred();
380
381 /// Break bundle below this instruction.
382 void unbundleFromSucc();
383
384 /// Returns the debug location id of this MachineInstr.
385 const DebugLoc &getDebugLoc() const { return debugLoc; }
386
387 /// Return the debug variable referenced by
388 /// this DBG_VALUE instruction.
389 const DILocalVariable *getDebugVariable() const;
390
391 /// Return the complex address expression referenced by
392 /// this DBG_VALUE instruction.
393 const DIExpression *getDebugExpression() const;
394
395 /// Return the debug label referenced by
396 /// this DBG_LABEL instruction.
397 const DILabel *getDebugLabel() const;
398
399 /// Emit an error referring to the source location of this instruction.
400 /// This should only be used for inline assembly that is somehow
401 /// impossible to compile. Other errors should have been handled much
402 /// earlier.
403 ///
404 /// If this method returns, the caller should try to recover from the error.
405 void emitError(StringRef Msg) const;
406
407 /// Returns the target instruction descriptor of this MachineInstr.
408 const MCInstrDesc &getDesc() const { return *MCID; }
409
410 /// Returns the opcode of this MachineInstr.
411 unsigned getOpcode() const { return MCID->Opcode; }
412
413 /// Retuns the total number of operands.
414 unsigned getNumOperands() const { return NumOperands; }
415
416 const MachineOperand& getOperand(unsigned i) const {
417 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 417, __PRETTY_FUNCTION__))
;
418 return Operands[i];
419 }
420 MachineOperand& getOperand(unsigned i) {
421 assert(i < getNumOperands() && "getOperand() out of range!")((i < getNumOperands() && "getOperand() out of range!"
) ? static_cast<void> (0) : __assert_fail ("i < getNumOperands() && \"getOperand() out of range!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 421, __PRETTY_FUNCTION__))
;
422 return Operands[i];
423 }
424
425 /// Returns the total number of definitions.
426 unsigned getNumDefs() const {
427 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
428 }
429
430 /// Returns true if the instruction has implicit definition.
431 bool hasImplicitDef() const {
432 for (unsigned I = getNumExplicitOperands(), E = getNumOperands();
433 I != E; ++I) {
434 const MachineOperand &MO = getOperand(I);
435 if (MO.isDef() && MO.isImplicit())
436 return true;
437 }
438 return false;
439 }
440
441 /// Returns the implicit operands number.
442 unsigned getNumImplicitOperands() const {
443 return getNumOperands() - getNumExplicitOperands();
444 }
445
446 /// Return true if operand \p OpIdx is a subregister index.
447 bool isOperandSubregIdx(unsigned OpIdx) const {
448 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 449, __PRETTY_FUNCTION__))
449 "Expected MO_Immediate operand type.")((getOperand(OpIdx).getType() == MachineOperand::MO_Immediate
&& "Expected MO_Immediate operand type.") ? static_cast
<void> (0) : __assert_fail ("getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && \"Expected MO_Immediate operand type.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 449, __PRETTY_FUNCTION__))
;
450 if (isExtractSubreg() && OpIdx == 2)
451 return true;
452 if (isInsertSubreg() && OpIdx == 3)
453 return true;
454 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)
455 return true;
456 if (isSubregToReg() && OpIdx == 3)
457 return true;
458 return false;
459 }
460
461 /// Returns the number of non-implicit operands.
462 unsigned getNumExplicitOperands() const;
463
464 /// Returns the number of non-implicit definitions.
465 unsigned getNumExplicitDefs() const;
466
467 /// iterator/begin/end - Iterate over all operands of a machine instruction.
468 using mop_iterator = MachineOperand *;
469 using const_mop_iterator = const MachineOperand *;
470
471 mop_iterator operands_begin() { return Operands; }
472 mop_iterator operands_end() { return Operands + NumOperands; }
473
474 const_mop_iterator operands_begin() const { return Operands; }
475 const_mop_iterator operands_end() const { return Operands + NumOperands; }
476
477 iterator_range<mop_iterator> operands() {
478 return make_range(operands_begin(), operands_end());
479 }
480 iterator_range<const_mop_iterator> operands() const {
481 return make_range(operands_begin(), operands_end());
482 }
483 iterator_range<mop_iterator> explicit_operands() {
484 return make_range(operands_begin(),
485 operands_begin() + getNumExplicitOperands());
486 }
487 iterator_range<const_mop_iterator> explicit_operands() const {
488 return make_range(operands_begin(),
489 operands_begin() + getNumExplicitOperands());
490 }
491 iterator_range<mop_iterator> implicit_operands() {
492 return make_range(explicit_operands().end(), operands_end());
493 }
494 iterator_range<const_mop_iterator> implicit_operands() const {
495 return make_range(explicit_operands().end(), operands_end());
496 }
497 /// Returns a range over all explicit operands that are register definitions.
498 /// Implicit definition are not included!
499 iterator_range<mop_iterator> defs() {
500 return make_range(operands_begin(),
501 operands_begin() + getNumExplicitDefs());
502 }
503 /// \copydoc defs()
504 iterator_range<const_mop_iterator> defs() const {
505 return make_range(operands_begin(),
506 operands_begin() + getNumExplicitDefs());
507 }
508 /// Returns a range that includes all operands that are register uses.
509 /// This may include unrelated operands which are not register uses.
510 iterator_range<mop_iterator> uses() {
511 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
512 }
513 /// \copydoc uses()
514 iterator_range<const_mop_iterator> uses() const {
515 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
516 }
517 iterator_range<mop_iterator> explicit_uses() {
518 return make_range(operands_begin() + getNumExplicitDefs(),
519 operands_begin() + getNumExplicitOperands());
520 }
521 iterator_range<const_mop_iterator> explicit_uses() const {
522 return make_range(operands_begin() + getNumExplicitDefs(),
523 operands_begin() + getNumExplicitOperands());
524 }
525
526 /// Returns the number of the operand iterator \p I points to.
527 unsigned getOperandNo(const_mop_iterator I) const {
528 return I - operands_begin();
529 }
530
531 /// Access to memory operands of the instruction. If there are none, that does
532 /// not imply anything about whether the function accesses memory. Instead,
533 /// the caller must behave conservatively.
534 ArrayRef<MachineMemOperand *> memoperands() const {
535 if (!Info)
536 return {};
537
538 if (Info.is<EIIK_MMO>())
539 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1);
540
541 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
542 return EI->getMMOs();
543
544 return {};
545 }
546
547 /// Access to memory operands of the instruction.
548 ///
549 /// If `memoperands_begin() == memoperands_end()`, that does not imply
550 /// anything about whether the function accesses memory. Instead, the caller
551 /// must behave conservatively.
552 mmo_iterator memoperands_begin() const { return memoperands().begin(); }
553
554 /// Access to memory operands of the instruction.
555 ///
556 /// If `memoperands_begin() == memoperands_end()`, that does not imply
557 /// anything about whether the function accesses memory. Instead, the caller
558 /// must behave conservatively.
559 mmo_iterator memoperands_end() const { return memoperands().end(); }
560
561 /// Return true if we don't have any memory operands which described the
562 /// memory access done by this instruction. If this is true, calling code
563 /// must be conservative.
564 bool memoperands_empty() const { return memoperands().empty(); }
565
566 /// Return true if this instruction has exactly one MachineMemOperand.
567 bool hasOneMemOperand() const { return memoperands().size() == 1; }
29
Assuming the condition is true
30
Returning the value 1, which participates in a condition later
568
569 /// Return the number of memory operands.
570 unsigned getNumMemOperands() const { return memoperands().size(); }
571
572 /// Helper to extract a pre-instruction symbol if one has been added.
573 MCSymbol *getPreInstrSymbol() const {
574 if (!Info)
575 return nullptr;
576 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>())
577 return S;
578 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
579 return EI->getPreInstrSymbol();
580
581 return nullptr;
582 }
583
584 /// Helper to extract a post-instruction symbol if one has been added.
585 MCSymbol *getPostInstrSymbol() const {
586 if (!Info)
587 return nullptr;
588 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>())
589 return S;
590 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>())
591 return EI->getPostInstrSymbol();
592
593 return nullptr;
594 }
595
596 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
597 /// queries but they are bundle aware.
598
599 enum QueryType {
600 IgnoreBundle, // Ignore bundles
601 AnyInBundle, // Return true if any instruction in bundle has property
602 AllInBundle // Return true if all instructions in bundle have property
603 };
604
605 /// Return true if the instruction (or in the case of a bundle,
606 /// the instructions inside the bundle) has the specified property.
607 /// The first argument is the property being queried.
608 /// The second argument indicates whether the query should look inside
609 /// instruction bundles.
610 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
611 assert(MCFlag < 64 &&((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 612, __PRETTY_FUNCTION__))
612 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")((MCFlag < 64 && "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."
) ? static_cast<void> (0) : __assert_fail ("MCFlag < 64 && \"MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 612, __PRETTY_FUNCTION__))
;
613 // Inline the fast path for unbundled or bundle-internal instructions.
614 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
615 return getDesc().getFlags() & (1ULL << MCFlag);
616
617 // If this is the first instruction in a bundle, take the slow path.
618 return hasPropertyInBundle(1ULL << MCFlag, Type);
619 }
620
621 /// Return true if this instruction can have a variable number of operands.
622 /// In this case, the variable operands will be after the normal
623 /// operands but before the implicit definitions and uses (if any are
624 /// present).
625 bool isVariadic(QueryType Type = IgnoreBundle) const {
626 return hasProperty(MCID::Variadic, Type);
627 }
628
629 /// Set if this instruction has an optional definition, e.g.
630 /// ARM instructions which can set condition code if 's' bit is set.
631 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
632 return hasProperty(MCID::HasOptionalDef, Type);
633 }
634
635 /// Return true if this is a pseudo instruction that doesn't
636 /// correspond to a real machine instruction.
637 bool isPseudo(QueryType Type = IgnoreBundle) const {
638 return hasProperty(MCID::Pseudo, Type);
639 }
640
641 bool isReturn(QueryType Type = AnyInBundle) const {
642 return hasProperty(MCID::Return, Type);
643 }
644
645 /// Return true if this is an instruction that marks the end of an EH scope,
646 /// i.e., a catchpad or a cleanuppad instruction.
647 bool isEHScopeReturn(QueryType Type = AnyInBundle) const {
648 return hasProperty(MCID::EHScopeReturn, Type);
649 }
650
651 bool isCall(QueryType Type = AnyInBundle) const {
652 return hasProperty(MCID::Call, Type);
653 }
654
655 /// Returns true if the specified instruction stops control flow
656 /// from executing the instruction immediately following it. Examples include
657 /// unconditional branches and return instructions.
658 bool isBarrier(QueryType Type = AnyInBundle) const {
659 return hasProperty(MCID::Barrier, Type);
660 }
661
662 /// Returns true if this instruction part of the terminator for a basic block.
663 /// Typically this is things like return and branch instructions.
664 ///
665 /// Various passes use this to insert code into the bottom of a basic block,
666 /// but before control flow occurs.
667 bool isTerminator(QueryType Type = AnyInBundle) const {
668 return hasProperty(MCID::Terminator, Type);
669 }
670
671 /// Returns true if this is a conditional, unconditional, or indirect branch.
672 /// Predicates below can be used to discriminate between
673 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
674 /// get more information.
675 bool isBranch(QueryType Type = AnyInBundle) const {
676 return hasProperty(MCID::Branch, Type);
677 }
678
679 /// Return true if this is an indirect branch, such as a
680 /// branch through a register.
681 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
682 return hasProperty(MCID::IndirectBranch, Type);
683 }
684
685 /// Return true if this is a branch which may fall
686 /// through to the next instruction or may transfer control flow to some other
687 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
688 /// information about this branch.
689 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
690 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
691 }
692
693 /// Return true if this is a branch which always
694 /// transfers control flow to some other block. The
695 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
696 /// about this branch.
697 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
698 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
699 }
700
701 /// Return true if this instruction has a predicate operand that
702 /// controls execution. It may be set to 'always', or may be set to other
703 /// values. There are various methods in TargetInstrInfo that can be used to
704 /// control and modify the predicate in this instruction.
705 bool isPredicable(QueryType Type = AllInBundle) const {
706 // If it's a bundle than all bundled instructions must be predicable for this
707 // to return true.
708 return hasProperty(MCID::Predicable, Type);
709 }
710
711 /// Return true if this instruction is a comparison.
712 bool isCompare(QueryType Type = IgnoreBundle) const {
713 return hasProperty(MCID::Compare, Type);
714 }
715
716 /// Return true if this instruction is a move immediate
717 /// (including conditional moves) instruction.
718 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
719 return hasProperty(MCID::MoveImm, Type);
720 }
721
722 /// Return true if this instruction is a register move.
723 /// (including moving values from subreg to reg)
724 bool isMoveReg(QueryType Type = IgnoreBundle) const {
725 return hasProperty(MCID::MoveReg, Type);
726 }
727
728 /// Return true if this instruction is a bitcast instruction.
729 bool isBitcast(QueryType Type = IgnoreBundle) const {
730 return hasProperty(MCID::Bitcast, Type);
731 }
732
733 /// Return true if this instruction is a select instruction.
734 bool isSelect(QueryType Type = IgnoreBundle) const {
735 return hasProperty(MCID::Select, Type);
736 }
737
738 /// Return true if this instruction cannot be safely duplicated.
739 /// For example, if the instruction has a unique labels attached
740 /// to it, duplicating it would cause multiple definition errors.
741 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
742 return hasProperty(MCID::NotDuplicable, Type);
743 }
744
745 /// Return true if this instruction is convergent.
746 /// Convergent instructions can not be made control-dependent on any
747 /// additional values.
748 bool isConvergent(QueryType Type = AnyInBundle) const {
749 if (isInlineAsm()) {
750 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
751 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
752 return true;
753 }
754 return hasProperty(MCID::Convergent, Type);
755 }
756
757 /// Returns true if the specified instruction has a delay slot
758 /// which must be filled by the code generator.
759 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
760 return hasProperty(MCID::DelaySlot, Type);
761 }
762
763 /// Return true for instructions that can be folded as
764 /// memory operands in other instructions. The most common use for this
765 /// is instructions that are simple loads from memory that don't modify
766 /// the loaded value in any way, but it can also be used for instructions
767 /// that can be expressed as constant-pool loads, such as V_SETALLONES
768 /// on x86, to allow them to be folded when it is beneficial.
769 /// This should only be set on instructions that return a value in their
770 /// only virtual register definition.
771 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
772 return hasProperty(MCID::FoldableAsLoad, Type);
773 }
774
775 /// Return true if this instruction behaves
776 /// the same way as the generic REG_SEQUENCE instructions.
777 /// E.g., on ARM,
778 /// dX VMOVDRR rY, rZ
779 /// is equivalent to
780 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
781 ///
782 /// Note that for the optimizers to be able to take advantage of
783 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
784 /// override accordingly.
785 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
786 return hasProperty(MCID::RegSequence, Type);
787 }
788
789 /// Return true if this instruction behaves
790 /// the same way as the generic EXTRACT_SUBREG instructions.
791 /// E.g., on ARM,
792 /// rX, rY VMOVRRD dZ
793 /// is equivalent to two EXTRACT_SUBREG:
794 /// rX = EXTRACT_SUBREG dZ, ssub_0
795 /// rY = EXTRACT_SUBREG dZ, ssub_1
796 ///
797 /// Note that for the optimizers to be able to take advantage of
798 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
799 /// override accordingly.
800 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
801 return hasProperty(MCID::ExtractSubreg, Type);
802 }
803
804 /// Return true if this instruction behaves
805 /// the same way as the generic INSERT_SUBREG instructions.
806 /// E.g., on ARM,
807 /// dX = VSETLNi32 dY, rZ, Imm
808 /// is equivalent to a INSERT_SUBREG:
809 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
810 ///
811 /// Note that for the optimizers to be able to take advantage of
812 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
813 /// override accordingly.
814 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
815 return hasProperty(MCID::InsertSubreg, Type);
816 }
817
818 //===--------------------------------------------------------------------===//
819 // Side Effect Analysis
820 //===--------------------------------------------------------------------===//
821
822 /// Return true if this instruction could possibly read memory.
823 /// Instructions with this flag set are not necessarily simple load
824 /// instructions, they may load a value and modify it, for example.
825 bool mayLoad(QueryType Type = AnyInBundle) const {
826 if (isInlineAsm()) {
827 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
828 if (ExtraInfo & InlineAsm::Extra_MayLoad)
829 return true;
830 }
831 return hasProperty(MCID::MayLoad, Type);
832 }
833
834 /// Return true if this instruction could possibly modify memory.
835 /// Instructions with this flag set are not necessarily simple store
836 /// instructions, they may store a modified value based on their operands, or
837 /// may not actually modify anything, for example.
838 bool mayStore(QueryType Type = AnyInBundle) const {
839 if (isInlineAsm()) {
840 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
841 if (ExtraInfo & InlineAsm::Extra_MayStore)
842 return true;
843 }
844 return hasProperty(MCID::MayStore, Type);
845 }
846
847 /// Return true if this instruction could possibly read or modify memory.
848 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
849 return mayLoad(Type) || mayStore(Type);
850 }
851
852 /// Return true if this instruction could possibly raise a floating-point
853 /// exception. This is the case if the instruction is a floating-point
854 /// instruction that can in principle raise an exception, as indicated
855 /// by the MCID::MayRaiseFPException property, *and* at the same time,
856 /// the instruction is used in a context where we expect floating-point
857 /// exceptions might be enabled, as indicated by the FPExcept MI flag.
858 bool mayRaiseFPException() const {
859 return hasProperty(MCID::MayRaiseFPException) &&
860 getFlag(MachineInstr::MIFlag::FPExcept);
861 }
862
863 //===--------------------------------------------------------------------===//
864 // Flags that indicate whether an instruction can be modified by a method.
865 //===--------------------------------------------------------------------===//
866
867 /// Return true if this may be a 2- or 3-address
868 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
869 /// result if Y and Z are exchanged. If this flag is set, then the
870 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
871 /// instruction.
872 ///
873 /// Note that this flag may be set on instructions that are only commutable
874 /// sometimes. In these cases, the call to commuteInstruction will fail.
875 /// Also note that some instructions require non-trivial modification to
876 /// commute them.
877 bool isCommutable(QueryType Type = IgnoreBundle) const {
878 return hasProperty(MCID::Commutable, Type);
879 }
880
881 /// Return true if this is a 2-address instruction
882 /// which can be changed into a 3-address instruction if needed. Doing this
883 /// transformation can be profitable in the register allocator, because it
884 /// means that the instruction can use a 2-address form if possible, but
885 /// degrade into a less efficient form if the source and dest register cannot
886 /// be assigned to the same register. For example, this allows the x86
887 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
888 /// is the same speed as the shift but has bigger code size.
889 ///
890 /// If this returns true, then the target must implement the
891 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
892 /// is allowed to fail if the transformation isn't valid for this specific
893 /// instruction (e.g. shl reg, 4 on x86).
894 ///
895 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
896 return hasProperty(MCID::ConvertibleTo3Addr, Type);
897 }
898
899 /// Return true if this instruction requires
900 /// custom insertion support when the DAG scheduler is inserting it into a
901 /// machine basic block. If this is true for the instruction, it basically
902 /// means that it is a pseudo instruction used at SelectionDAG time that is
903 /// expanded out into magic code by the target when MachineInstrs are formed.
904 ///
905 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
906 /// is used to insert this into the MachineBasicBlock.
907 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
908 return hasProperty(MCID::UsesCustomInserter, Type);
909 }
910
911 /// Return true if this instruction requires *adjustment*
912 /// after instruction selection by calling a target hook. For example, this
913 /// can be used to fill in ARM 's' optional operand depending on whether
914 /// the conditional flag register is used.
915 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
916 return hasProperty(MCID::HasPostISelHook, Type);
917 }
918
919 /// Returns true if this instruction is a candidate for remat.
920 /// This flag is deprecated, please don't use it anymore. If this
921 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
922 /// verify the instruction is really rematable.
923 bool isRematerializable(QueryType Type = AllInBundle) const {
924 // It's only possible to re-mat a bundle if all bundled instructions are
925 // re-materializable.
926 return hasProperty(MCID::Rematerializable, Type);
927 }
928
929 /// Returns true if this instruction has the same cost (or less) than a move
930 /// instruction. This is useful during certain types of optimizations
931 /// (e.g., remat during two-address conversion or machine licm)
932 /// where we would like to remat or hoist the instruction, but not if it costs
933 /// more than moving the instruction into the appropriate register. Note, we
934 /// are not marking copies from and to the same register class with this flag.
935 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
936 // Only returns true for a bundle if all bundled instructions are cheap.
937 return hasProperty(MCID::CheapAsAMove, Type);
938 }
939
940 /// Returns true if this instruction source operands
941 /// have special register allocation requirements that are not captured by the
942 /// operand register classes. e.g. ARM::STRD's two source registers must be an
943 /// even / odd pair, ARM::STM registers have to be in ascending order.
944 /// Post-register allocation passes should not attempt to change allocations
945 /// for sources of instructions with this flag.
946 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
947 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
948 }
949
950 /// Returns true if this instruction def operands
951 /// have special register allocation requirements that are not captured by the
952 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
953 /// even / odd pair, ARM::LDM registers have to be in ascending order.
954 /// Post-register allocation passes should not attempt to change allocations
955 /// for definitions of instructions with this flag.
956 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
957 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
958 }
959
960 enum MICheckType {
961 CheckDefs, // Check all operands for equality
962 CheckKillDead, // Check all operands including kill / dead markers
963 IgnoreDefs, // Ignore all definitions
964 IgnoreVRegDefs // Ignore virtual register definitions
965 };
966
967 /// Return true if this instruction is identical to \p Other.
968 /// Two instructions are identical if they have the same opcode and all their
969 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
970 /// Note that this means liveness related flags (dead, undef, kill) do not
971 /// affect the notion of identical.
972 bool isIdenticalTo(const MachineInstr &Other,
973 MICheckType Check = CheckDefs) const;
974
975 /// Unlink 'this' from the containing basic block, and return it without
976 /// deleting it.
977 ///
978 /// This function can not be used on bundled instructions, use
979 /// removeFromBundle() to remove individual instructions from a bundle.
980 MachineInstr *removeFromParent();
981
982 /// Unlink this instruction from its basic block and return it without
983 /// deleting it.
984 ///
985 /// If the instruction is part of a bundle, the other instructions in the
986 /// bundle remain bundled.
987 MachineInstr *removeFromBundle();
988
989 /// Unlink 'this' from the containing basic block and delete it.
990 ///
991 /// If this instruction is the header of a bundle, the whole bundle is erased.
992 /// This function can not be used for instructions inside a bundle, use
993 /// eraseFromBundle() to erase individual bundled instructions.
994 void eraseFromParent();
995
996 /// Unlink 'this' from the containing basic block and delete it.
997 ///
998 /// For all definitions mark their uses in DBG_VALUE nodes
999 /// as undefined. Otherwise like eraseFromParent().
1000 void eraseFromParentAndMarkDBGValuesForRemoval();
1001
1002 /// Unlink 'this' form its basic block and delete it.
1003 ///
1004 /// If the instruction is part of a bundle, the other instructions in the
1005 /// bundle remain bundled.
1006 void eraseFromBundle();
1007
1008 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
1009 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
1010 bool isAnnotationLabel() const {
1011 return getOpcode() == TargetOpcode::ANNOTATION_LABEL;
1012 }
1013
1014 /// Returns true if the MachineInstr represents a label.
1015 bool isLabel() const {
1016 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1017 }
1018
1019 bool isCFIInstruction() const {
1020 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
1021 }
1022
1023 // True if the instruction represents a position in the function.
1024 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1025
1026 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
1027 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
1028 bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
1029
1030 /// A DBG_VALUE is indirect iff the first operand is a register and
1031 /// the second operand is an immediate.
1032 bool isIndirectDebugValue() const {
1033 return isDebugValue()
1034 && getOperand(0).isReg()
1035 && getOperand(1).isImm();
1036 }
1037
1038 /// A DBG_VALUE is an entry value iff its debug expression contains the
1039 /// DW_OP_entry_value DWARF operation.
1040 bool isDebugEntryValue() const {
1041 return isDebugValue() && getDebugExpression()->isEntryValue();
1042 }
1043
1044 /// Return true if the instruction is a debug value which describes a part of
1045 /// a variable as unavailable.
1046 bool isUndefDebugValue() const {
1047 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1048 }
1049
1050 bool isPHI() const {
1051 return getOpcode() == TargetOpcode::PHI ||
1052 getOpcode() == TargetOpcode::G_PHI;
1053 }
1054 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
1055 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
1056 bool isInlineAsm() const {
1057 return getOpcode() == TargetOpcode::INLINEASM ||
1058 getOpcode() == TargetOpcode::INLINEASM_BR;
1059 }
1060
1061 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1062 /// specific, be attached to a generic MachineInstr.
1063 bool isMSInlineAsm() const {
1064 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel;
1065 }
1066
1067 bool isStackAligningInlineAsm() const;
1068 InlineAsm::AsmDialect getInlineAsmDialect() const;
1069
1070 bool isInsertSubreg() const {
1071 return getOpcode() == TargetOpcode::INSERT_SUBREG;
1072 }
1073
1074 bool isSubregToReg() const {
1075 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
1076 }
1077
1078 bool isRegSequence() const {
1079 return getOpcode() == TargetOpcode::REG_SEQUENCE;
1080 }
1081
1082 bool isBundle() const {
1083 return getOpcode() == TargetOpcode::BUNDLE;
1084 }
1085
1086 bool isCopy() const {
1087 return getOpcode() == TargetOpcode::COPY;
1088 }
1089
1090 bool isFullCopy() const {
1091 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1092 }
1093
1094 bool isExtractSubreg() const {
1095 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
1096 }
1097
1098 /// Return true if the instruction behaves like a copy.
1099 /// This does not include native copy instructions.
1100 bool isCopyLike() const {
1101 return isCopy() || isSubregToReg();
1102 }
1103
1104 /// Return true is the instruction is an identity copy.
1105 bool isIdentityCopy() const {
1106 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1107 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1108 }
1109
1110 /// Return true if this instruction doesn't produce any output in the form of
1111 /// executable instructions.
1112 bool isMetaInstruction() const {
1113 switch (getOpcode()) {
1114 default:
1115 return false;
1116 case TargetOpcode::IMPLICIT_DEF:
1117 case TargetOpcode::KILL:
1118 case TargetOpcode::CFI_INSTRUCTION:
1119 case TargetOpcode::EH_LABEL:
1120 case TargetOpcode::GC_LABEL:
1121 case TargetOpcode::DBG_VALUE:
1122 case TargetOpcode::DBG_LABEL:
1123 case TargetOpcode::LIFETIME_START:
1124 case TargetOpcode::LIFETIME_END:
1125 return true;
1126 }
1127 }
1128
1129 /// Return true if this is a transient instruction that is either very likely
1130 /// to be eliminated during register allocation (such as copy-like
1131 /// instructions), or if this instruction doesn't have an execution-time cost.
1132 bool isTransient() const {
1133 switch (getOpcode()) {
1134 default:
1135 return isMetaInstruction();
1136 // Copy-like instructions are usually eliminated during register allocation.
1137 case TargetOpcode::PHI:
1138 case TargetOpcode::G_PHI:
1139 case TargetOpcode::COPY:
1140 case TargetOpcode::INSERT_SUBREG:
1141 case TargetOpcode::SUBREG_TO_REG:
1142 case TargetOpcode::REG_SEQUENCE:
1143 return true;
1144 }
1145 }
1146
1147 /// Return the number of instructions inside the MI bundle, excluding the
1148 /// bundle header.
1149 ///
1150 /// This is the number of instructions that MachineBasicBlock::iterator
1151 /// skips, 0 for unbundled instructions.
1152 unsigned getBundleSize() const;
1153
1154 /// Return true if the MachineInstr reads the specified register.
1155 /// If TargetRegisterInfo is passed, then it also checks if there
1156 /// is a read of a super-register.
1157 /// This does not count partial redefines of virtual registers as reads:
1158 /// %reg1024:6 = OP.
1159 bool readsRegister(Register Reg,
1160 const TargetRegisterInfo *TRI = nullptr) const {
1161 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
1162 }
1163
1164 /// Return true if the MachineInstr reads the specified virtual register.
1165 /// Take into account that a partial define is a
1166 /// read-modify-write operation.
1167 bool readsVirtualRegister(Register Reg) const {
1168 return readsWritesVirtualRegister(Reg).first;
1169 }
1170
1171 /// Return a pair of bools (reads, writes) indicating if this instruction
1172 /// reads or writes Reg. This also considers partial defines.
1173 /// If Ops is not null, all operand indices for Reg are added.
1174 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg,
1175 SmallVectorImpl<unsigned> *Ops = nullptr) const;
1176
1177 /// Return true if the MachineInstr kills the specified register.
1178 /// If TargetRegisterInfo is passed, then it also checks if there is
1179 /// a kill of a super-register.
1180 bool killsRegister(Register Reg,
1181 const TargetRegisterInfo *TRI = nullptr) const {
1182 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
1183 }
1184
1185 /// Return true if the MachineInstr fully defines the specified register.
1186 /// If TargetRegisterInfo is passed, then it also checks
1187 /// if there is a def of a super-register.
1188 /// NOTE: It's ignoring subreg indices on virtual registers.
1189 bool definesRegister(Register Reg,
1190 const TargetRegisterInfo *TRI = nullptr) const {
1191 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1192 }
1193
1194 /// Return true if the MachineInstr modifies (fully define or partially
1195 /// define) the specified register.
1196 /// NOTE: It's ignoring subreg indices on virtual registers.
1197 bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1198 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1199 }
1200
1201 /// Returns true if the register is dead in this machine instruction.
1202 /// If TargetRegisterInfo is passed, then it also checks
1203 /// if there is a dead def of a super-register.
1204 bool registerDefIsDead(Register Reg,
1205 const TargetRegisterInfo *TRI = nullptr) const {
1206 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1207 }
1208
1209 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1210 /// the given register (not considering sub/super-registers).
1211 bool hasRegisterImplicitUseOperand(Register Reg) const;
1212
1213 /// Returns the operand index that is a use of the specific register or -1
1214 /// if it is not found. It further tightens the search criteria to a use
1215 /// that kills the register if isKill is true.
1216 int findRegisterUseOperandIdx(Register Reg, bool isKill = false,
1217 const TargetRegisterInfo *TRI = nullptr) const;
1218
1219 /// Wrapper for findRegisterUseOperandIdx, it returns
1220 /// a pointer to the MachineOperand rather than an index.
1221 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false,
1222 const TargetRegisterInfo *TRI = nullptr) {
1223 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
1224 return (Idx == -1) ? nullptr : &getOperand(Idx);
1225 }
1226
1227 const MachineOperand *findRegisterUseOperand(
1228 Register Reg, bool isKill = false,
1229 const TargetRegisterInfo *TRI = nullptr) const {
1230 return const_cast<MachineInstr *>(this)->
1231 findRegisterUseOperand(Reg, isKill, TRI);
1232 }
1233
1234 /// Returns the operand index that is a def of the specified register or
1235 /// -1 if it is not found. If isDead is true, defs that are not dead are
1236 /// skipped. If Overlap is true, then it also looks for defs that merely
1237 /// overlap the specified register. If TargetRegisterInfo is non-null,
1238 /// then it also checks if there is a def of a super-register.
1239 /// This may also return a register mask operand when Overlap is true.
1240 int findRegisterDefOperandIdx(Register Reg,
1241 bool isDead = false, bool Overlap = false,
1242 const TargetRegisterInfo *TRI = nullptr) const;
1243
1244 /// Wrapper for findRegisterDefOperandIdx, it returns
1245 /// a pointer to the MachineOperand rather than an index.
1246 MachineOperand *
1247 findRegisterDefOperand(Register Reg, bool isDead = false,
1248 bool Overlap = false,
1249 const TargetRegisterInfo *TRI = nullptr) {
1250 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
1251 return (Idx == -1) ? nullptr : &getOperand(Idx);
1252 }
1253
1254 const MachineOperand *
1255 findRegisterDefOperand(Register Reg, bool isDead = false,
1256 bool Overlap = false,
1257 const TargetRegisterInfo *TRI = nullptr) const {
1258 return const_cast<MachineInstr *>(this)->findRegisterDefOperand(
1259 Reg, isDead, Overlap, TRI);
1260 }
1261
1262 /// Find the index of the first operand in the
1263 /// operand list that is used to represent the predicate. It returns -1 if
1264 /// none is found.
1265 int findFirstPredOperandIdx() const;
1266
1267 /// Find the index of the flag word operand that
1268 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1269 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1270 ///
1271 /// If GroupNo is not NULL, it will receive the number of the operand group
1272 /// containing OpIdx.
1273 ///
1274 /// The flag operand is an immediate that can be decoded with methods like
1275 /// InlineAsm::hasRegClassConstraint().
1276 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
1277
1278 /// Compute the static register class constraint for operand OpIdx.
1279 /// For normal instructions, this is derived from the MCInstrDesc.
1280 /// For inline assembly it is derived from the flag words.
1281 ///
1282 /// Returns NULL if the static register class constraint cannot be
1283 /// determined.
1284 const TargetRegisterClass*
1285 getRegClassConstraint(unsigned OpIdx,
1286 const TargetInstrInfo *TII,
1287 const TargetRegisterInfo *TRI) const;
1288
1289 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1290 /// the given \p CurRC.
1291 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1292 /// instructions inside the bundle will be taken into account. In other words,
1293 /// this method accumulates all the constraints of the operand of this MI and
1294 /// the related bundle if MI is a bundle or inside a bundle.
1295 ///
1296 /// Returns the register class that satisfies both \p CurRC and the
1297 /// constraints set by MI. Returns NULL if such a register class does not
1298 /// exist.
1299 ///
1300 /// \pre CurRC must not be NULL.
1301 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1302 Register Reg, const TargetRegisterClass *CurRC,
1303 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1304 bool ExploreBundle = false) const;
1305
1306 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1307 /// to the given \p CurRC.
1308 ///
1309 /// Returns the register class that satisfies both \p CurRC and the
1310 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1311 /// does not exist.
1312 ///
1313 /// \pre CurRC must not be NULL.
1314 /// \pre The operand at \p OpIdx must be a register.
1315 const TargetRegisterClass *
1316 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1317 const TargetInstrInfo *TII,
1318 const TargetRegisterInfo *TRI) const;
1319
1320 /// Add a tie between the register operands at DefIdx and UseIdx.
1321 /// The tie will cause the register allocator to ensure that the two
1322 /// operands are assigned the same physical register.
1323 ///
1324 /// Tied operands are managed automatically for explicit operands in the
1325 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1326 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1327
1328 /// Given the index of a tied register operand, find the
1329 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1330 /// index of the tied operand which must exist.
1331 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1332
1333 /// Given the index of a register def operand,
1334 /// check if the register def is tied to a source operand, due to either
1335 /// two-address elimination or inline assembly constraints. Returns the
1336 /// first tied use operand index by reference if UseOpIdx is not null.
1337 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1338 unsigned *UseOpIdx = nullptr) const {
1339 const MachineOperand &MO = getOperand(DefOpIdx);
1340 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1341 return false;
1342 if (UseOpIdx)
1343 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1344 return true;
1345 }
1346
1347 /// Return true if the use operand of the specified index is tied to a def
1348 /// operand. It also returns the def operand index by reference if DefOpIdx
1349 /// is not null.
1350 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1351 unsigned *DefOpIdx = nullptr) const {
1352 const MachineOperand &MO = getOperand(UseOpIdx);
1353 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1354 return false;
1355 if (DefOpIdx)
1356 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1357 return true;
1358 }
1359
1360 /// Clears kill flags on all operands.
1361 void clearKillInfo();
1362
1363 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1364 /// properly composing subreg indices where necessary.
1365 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx,
1366 const TargetRegisterInfo &RegInfo);
1367
1368 /// We have determined MI kills a register. Look for the
1369 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1370 /// add a implicit operand if it's not found. Returns true if the operand
1371 /// exists / is added.
1372 bool addRegisterKilled(Register IncomingReg,
1373 const TargetRegisterInfo *RegInfo,
1374 bool AddIfNotFound = false);
1375
1376 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1377 /// all aliasing registers.
1378 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1379
1380 /// We have determined MI defined a register without a use.
1381 /// Look for the operand that defines it and mark it as IsDead. If
1382 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1383 /// true if the operand exists / is added.
1384 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1385 bool AddIfNotFound = false);
1386
1387 /// Clear all dead flags on operands defining register @p Reg.
1388 void clearRegisterDeads(Register Reg);
1389
1390 /// Mark all subregister defs of register @p Reg with the undef flag.
1391 /// This function is used when we determined to have a subregister def in an
1392 /// otherwise undefined super register.
1393 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true);
1394
1395 /// We have determined MI defines a register. Make sure there is an operand
1396 /// defining Reg.
1397 void addRegisterDefined(Register Reg,
1398 const TargetRegisterInfo *RegInfo = nullptr);
1399
1400 /// Mark every physreg used by this instruction as
1401 /// dead except those in the UsedRegs list.
1402 ///
1403 /// On instructions with register mask operands, also add implicit-def
1404 /// operands for all registers in UsedRegs.
1405 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
1406 const TargetRegisterInfo &TRI);
1407
1408 /// Return true if it is safe to move this instruction. If
1409 /// SawStore is set to true, it means that there is a store (or call) between
1410 /// the instruction's location and its intended destination.
1411 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1412
1413 /// Returns true if this instruction's memory access aliases the memory
1414 /// access of Other.
1415 //
1416 /// Assumes any physical registers used to compute addresses
1417 /// have the same value for both instructions. Returns false if neither
1418 /// instruction writes to memory.
1419 ///
1420 /// @param AA Optional alias analysis, used to compare memory operands.
1421 /// @param Other MachineInstr to check aliasing against.
1422 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1423 bool mayAlias(AliasAnalysis *AA, const MachineInstr &Other, bool UseTBAA) const;
1424
1425 /// Return true if this instruction may have an ordered
1426 /// or volatile memory reference, or if the information describing the memory
1427 /// reference is not available. Return false if it is known to have no
1428 /// ordered or volatile memory references.
1429 bool hasOrderedMemoryRef() const;
1430
1431 /// Return true if this load instruction never traps and points to a memory
1432 /// location whose value doesn't change during the execution of this function.
1433 ///
1434 /// Examples include loading a value from the constant pool or from the
1435 /// argument area of a function (if it does not change). If the instruction
1436 /// does multiple loads, this returns true only if all of the loads are
1437 /// dereferenceable and invariant.
1438 bool isDereferenceableInvariantLoad(AliasAnalysis *AA) const;
1439
1440 /// If the specified instruction is a PHI that always merges together the
1441 /// same virtual register, return the register, otherwise return 0.
1442 unsigned isConstantValuePHI() const;
1443
1444 /// Return true if this instruction has side effects that are not modeled
1445 /// by mayLoad / mayStore, etc.
1446 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1447 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1448 /// INLINEASM instruction, in which case the side effect property is encoded
1449 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1450 ///
1451 bool hasUnmodeledSideEffects() const;
1452
1453 /// Returns true if it is illegal to fold a load across this instruction.
1454 bool isLoadFoldBarrier() const;
1455
1456 /// Return true if all the defs of this instruction are dead.
1457 bool allDefsAreDead() const;
1458
1459 /// Return a valid size if the instruction is a spill instruction.
1460 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const;
1461
1462 /// Return a valid size if the instruction is a folded spill instruction.
1463 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const;
1464
1465 /// Return a valid size if the instruction is a restore instruction.
1466 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const;
1467
1468 /// Return a valid size if the instruction is a folded restore instruction.
1469 Optional<unsigned>
1470 getFoldedRestoreSize(const TargetInstrInfo *TII) const;
1471
1472 /// Copy implicit register operands from specified
1473 /// instruction to this instruction.
1474 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI);
1475
1476 /// Debugging support
1477 /// @{
1478 /// Determine the generic type to be printed (if needed) on uses and defs.
1479 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1480 const MachineRegisterInfo &MRI) const;
1481
1482 /// Return true when an instruction has tied register that can't be determined
1483 /// by the instruction's descriptor. This is useful for MIR printing, to
1484 /// determine whether we need to print the ties or not.
1485 bool hasComplexRegisterTies() const;
1486
1487 /// Print this MI to \p OS.
1488 /// Don't print information that can be inferred from other instructions if
1489 /// \p IsStandalone is false. It is usually true when only a fragment of the
1490 /// function is printed.
1491 /// Only print the defs and the opcode if \p SkipOpers is true.
1492 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1493 /// Otherwise, also print the debug loc, with a terminating newline.
1494 /// \p TII is used to print the opcode name. If it's not present, but the
1495 /// MI is in a function, the opcode will be printed using the function's TII.
1496 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false,
1497 bool SkipDebugLoc = false, bool AddNewLine = true,
1498 const TargetInstrInfo *TII = nullptr) const;
1499 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true,
1500 bool SkipOpers = false, bool SkipDebugLoc = false,
1501 bool AddNewLine = true,
1502 const TargetInstrInfo *TII = nullptr) const;
1503 void dump() const;
1504 /// @}
1505
1506 //===--------------------------------------------------------------------===//
1507 // Accessors used to build up machine instructions.
1508
1509 /// Add the specified operand to the instruction. If it is an implicit
1510 /// operand, it is added to the end of the operand list. If it is an
1511 /// explicit operand it is added at the end of the explicit operand list
1512 /// (before the first implicit operand).
1513 ///
1514 /// MF must be the machine function that was used to allocate this
1515 /// instruction.
1516 ///
1517 /// MachineInstrBuilder provides a more convenient interface for creating
1518 /// instructions and adding operands.
1519 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1520
1521 /// Add an operand without providing an MF reference. This only works for
1522 /// instructions that are inserted in a basic block.
1523 ///
1524 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1525 /// preferred.
1526 void addOperand(const MachineOperand &Op);
1527
1528 /// Replace the instruction descriptor (thus opcode) of
1529 /// the current instruction with a new one.
1530 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1531
1532 /// Replace current source information with new such.
1533 /// Avoid using this, the constructor argument is preferable.
1534 void setDebugLoc(DebugLoc dl) {
1535 debugLoc = std::move(dl);
1536 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineInstr.h"
, 1536, __PRETTY_FUNCTION__))
;
1537 }
1538
1539 /// Erase an operand from an instruction, leaving it with one
1540 /// fewer operand than it started with.
1541 void RemoveOperand(unsigned OpNo);
1542
1543 /// Clear this MachineInstr's memory reference descriptor list. This resets
1544 /// the memrefs to their most conservative state. This should be used only
1545 /// as a last resort since it greatly pessimizes our knowledge of the memory
1546 /// access performed by the instruction.
1547 void dropMemRefs(MachineFunction &MF);
1548
1549 /// Assign this MachineInstr's memory reference descriptor list.
1550 ///
1551 /// Unlike other methods, this *will* allocate them into a new array
1552 /// associated with the provided `MachineFunction`.
1553 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs);
1554
1555 /// Add a MachineMemOperand to the machine instruction.
1556 /// This function should be used only occasionally. The setMemRefs function
1557 /// is the primary method for setting up a MachineInstr's MemRefs list.
1558 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1559
1560 /// Clone another MachineInstr's memory reference descriptor list and replace
1561 /// ours with it.
1562 ///
1563 /// Note that `*this` may be the incoming MI!
1564 ///
1565 /// Prefer this API whenever possible as it can avoid allocations in common
1566 /// cases.
1567 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI);
1568
1569 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1570 /// list and replace ours with it.
1571 ///
1572 /// Note that `*this` may be one of the incoming MIs!
1573 ///
1574 /// Prefer this API whenever possible as it can avoid allocations in common
1575 /// cases.
1576 void cloneMergedMemRefs(MachineFunction &MF,
1577 ArrayRef<const MachineInstr *> MIs);
1578
1579 /// Set a symbol that will be emitted just prior to the instruction itself.
1580 ///
1581 /// Setting this to a null pointer will remove any such symbol.
1582 ///
1583 /// FIXME: This is not fully implemented yet.
1584 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1585
1586 /// Set a symbol that will be emitted just after the instruction itself.
1587 ///
1588 /// Setting this to a null pointer will remove any such symbol.
1589 ///
1590 /// FIXME: This is not fully implemented yet.
1591 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol);
1592
1593 /// Clone another MachineInstr's pre- and post- instruction symbols and
1594 /// replace ours with it.
1595 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI);
1596
1597 /// Return the MIFlags which represent both MachineInstrs. This
1598 /// should be used when merging two MachineInstrs into one. This routine does
1599 /// not modify the MIFlags of this MachineInstr.
1600 uint16_t mergeFlagsWith(const MachineInstr& Other) const;
1601
1602 static uint16_t copyFlagsFromInstruction(const Instruction &I);
1603
1604 /// Copy all flags to MachineInst MIFlags
1605 void copyIRFlags(const Instruction &I);
1606
1607 /// Break any tie involving OpIdx.
1608 void untieRegOperand(unsigned OpIdx) {
1609 MachineOperand &MO = getOperand(OpIdx);
1610 if (MO.isReg() && MO.isTied()) {
1611 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1612 MO.TiedTo = 0;
1613 }
1614 }
1615
1616 /// Add all implicit def and use operands to this instruction.
1617 void addImplicitDefUseOperands(MachineFunction &MF);
1618
1619 /// Scan instructions following MI and collect any matching DBG_VALUEs.
1620 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues);
1621
1622 /// Find all DBG_VALUEs that point to the register def in this instruction
1623 /// and point them to \p Reg instead.
1624 void changeDebugValuesDefReg(Register Reg);
1625
1626 /// Returns the Intrinsic::ID for this instruction.
1627 /// \pre Must have an intrinsic ID operand.
1628 unsigned getIntrinsicID() const {
1629 return getOperand(getNumExplicitDefs()).getIntrinsicID();
1630 }
1631
1632private:
1633 /// If this instruction is embedded into a MachineFunction, return the
1634 /// MachineRegisterInfo object for the current function, otherwise
1635 /// return null.
1636 MachineRegisterInfo *getRegInfo();
1637
1638 /// Unlink all of the register operands in this instruction from their
1639 /// respective use lists. This requires that the operands already be on their
1640 /// use lists.
1641 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1642
1643 /// Add all of the register operands in this instruction from their
1644 /// respective use lists. This requires that the operands not be on their
1645 /// use lists yet.
1646 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1647
1648 /// Slow path for hasProperty when we're dealing with a bundle.
1649 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
1650
1651 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1652 /// this MI and the given operand index \p OpIdx.
1653 /// If the related operand does not constrained Reg, this returns CurRC.
1654 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1655 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
1656 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1657};
1658
1659/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1660/// instruction rather than by pointer value.
1661/// The hashing and equality testing functions ignore definitions so this is
1662/// useful for CSE, etc.
1663struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1664 static inline MachineInstr *getEmptyKey() {
1665 return nullptr;
1666 }
1667
1668 static inline MachineInstr *getTombstoneKey() {
1669 return reinterpret_cast<MachineInstr*>(-1);
1670 }
1671
1672 static unsigned getHashValue(const MachineInstr* const &MI);
1673
1674 static bool isEqual(const MachineInstr* const &LHS,
1675 const MachineInstr* const &RHS) {
1676 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1677 LHS == getEmptyKey() || LHS == getTombstoneKey())
1678 return LHS == RHS;
1679 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs);
1680 }
1681};
1682
1683//===----------------------------------------------------------------------===//
1684// Debugging Support
1685
1686inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1687 MI.print(OS);
1688 return OS;
1689}
1690
1691} // end namespace llvm
1692
1693#endif // LLVM_CODEGEN_MACHINEINSTR_H

/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h

1//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineOperand class.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
14#define LLVM_CODEGEN_MACHINEOPERAND_H
15
16#include "llvm/ADT/DenseMap.h"
17#include "llvm/CodeGen/Register.h"
18#include "llvm/IR/Intrinsics.h"
19#include "llvm/Support/DataTypes.h"
20#include "llvm/Support/LowLevelTypeImpl.h"
21#include <cassert>
22
23namespace llvm {
24
25class BlockAddress;
26class Constant;
27class ConstantFP;
28class ConstantInt;
29class GlobalValue;
30class MachineBasicBlock;
31class MachineInstr;
32class MachineRegisterInfo;
33class MCCFIInstruction;
34class MDNode;
35class ModuleSlotTracker;
36class TargetMachine;
37class TargetIntrinsicInfo;
38class TargetRegisterInfo;
39class hash_code;
40class raw_ostream;
41class MCSymbol;
42
43/// MachineOperand class - Representation of each machine instruction operand.
44///
45/// This class isn't a POD type because it has a private constructor, but its
46/// destructor must be trivial. Functions like MachineInstr::addOperand(),
47/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
48/// not having to call the MachineOperand destructor.
49///
50class MachineOperand {
51public:
52 enum MachineOperandType : unsigned char {
53 MO_Register, ///< Register operand.
54 MO_Immediate, ///< Immediate operand
55 MO_CImmediate, ///< Immediate >64bit operand
56 MO_FPImmediate, ///< Floating-point immediate operand
57 MO_MachineBasicBlock, ///< MachineBasicBlock reference
58 MO_FrameIndex, ///< Abstract Stack Frame Index
59 MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
60 MO_TargetIndex, ///< Target-dependent index+offset operand.
61 MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
62 MO_ExternalSymbol, ///< Name of external global symbol
63 MO_GlobalAddress, ///< Address of a global value
64 MO_BlockAddress, ///< Address of a basic block
65 MO_RegisterMask, ///< Mask of preserved registers.
66 MO_RegisterLiveOut, ///< Mask of live-out registers.
67 MO_Metadata, ///< Metadata reference (for debug info)
68 MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
69 MO_CFIIndex, ///< MCCFIInstruction index.
70 MO_IntrinsicID, ///< Intrinsic ID for ISel
71 MO_Predicate, ///< Generic predicate for ISel
72 MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
73 MO_Last = MO_ShuffleMask
74 };
75
76private:
77 /// OpKind - Specify what kind of operand this is. This discriminates the
78 /// union.
79 unsigned OpKind : 8;
80
81 /// Subregister number for MO_Register. A value of 0 indicates the
82 /// MO_Register has no subReg.
83 ///
84 /// For all other kinds of operands, this field holds target-specific flags.
85 unsigned SubReg_TargetFlags : 12;
86
87 /// TiedTo - Non-zero when this register operand is tied to another register
88 /// operand. The encoding of this field is described in the block comment
89 /// before MachineInstr::tieOperands().
90 unsigned TiedTo : 4;
91
92 /// IsDef - True if this is a def, false if this is a use of the register.
93 /// This is only valid on register operands.
94 ///
95 unsigned IsDef : 1;
96
97 /// IsImp - True if this is an implicit def or use, false if it is explicit.
98 /// This is only valid on register opderands.
99 ///
100 unsigned IsImp : 1;
101
102 /// IsDeadOrKill
103 /// For uses: IsKill - True if this instruction is the last use of the
104 /// register on this path through the function.
105 /// For defs: IsDead - True if this register is never used by a subsequent
106 /// instruction.
107 /// This is only valid on register operands.
108 unsigned IsDeadOrKill : 1;
109
110 /// See isRenamable().
111 unsigned IsRenamable : 1;
112
113 /// IsUndef - True if this register operand reads an "undef" value, i.e. the
114 /// read value doesn't matter. This flag can be set on both use and def
115 /// operands. On a sub-register def operand, it refers to the part of the
116 /// register that isn't written. On a full-register def operand, it is a
117 /// noop. See readsReg().
118 ///
119 /// This is only valid on registers.
120 ///
121 /// Note that an instruction may have multiple <undef> operands referring to
122 /// the same register. In that case, the instruction may depend on those
123 /// operands reading the same dont-care value. For example:
124 ///
125 /// %1 = XOR undef %2, undef %2
126 ///
127 /// Any register can be used for %2, and its value doesn't matter, but
128 /// the two operands must be the same register.
129 ///
130 unsigned IsUndef : 1;
131
132 /// IsInternalRead - True if this operand reads a value that was defined
133 /// inside the same instruction or bundle. This flag can be set on both use
134 /// and def operands. On a sub-register def operand, it refers to the part
135 /// of the register that isn't written. On a full-register def operand, it
136 /// is a noop.
137 ///
138 /// When this flag is set, the instruction bundle must contain at least one
139 /// other def of the register. If multiple instructions in the bundle define
140 /// the register, the meaning is target-defined.
141 unsigned IsInternalRead : 1;
142
143 /// IsEarlyClobber - True if this MO_Register 'def' operand is written to
144 /// by the MachineInstr before all input registers are read. This is used to
145 /// model the GCC inline asm '&' constraint modifier.
146 unsigned IsEarlyClobber : 1;
147
148 /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
149 /// not a real instruction. Such uses should be ignored during codegen.
150 unsigned IsDebug : 1;
151
152 /// SmallContents - This really should be part of the Contents union, but
153 /// lives out here so we can get a better packed struct.
154 /// MO_Register: Register number.
155 /// OffsetedInfo: Low bits of offset.
156 union {
157 unsigned RegNo; // For MO_Register.
158 unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi.
159 } SmallContents;
160
161 /// ParentMI - This is the instruction that this operand is embedded into.
162 /// This is valid for all operand types, when the operand is in an instr.
163 MachineInstr *ParentMI;
164
165 /// Contents union - This contains the payload for the various operand types.
166 union {
167 MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
168 const ConstantFP *CFP; // For MO_FPImmediate.
169 const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
170 int64_t ImmVal; // For MO_Immediate.
171 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
172 const MDNode *MD; // For MO_Metadata.
173 MCSymbol *Sym; // For MO_MCSymbol.
174 unsigned CFIIndex; // For MO_CFI.
175 Intrinsic::ID IntrinsicID; // For MO_IntrinsicID.
176 unsigned Pred; // For MO_Predicate
177 const Constant *ShuffleMask; // For MO_ShuffleMask
178
179 struct { // For MO_Register.
180 // Register number is in SmallContents.RegNo.
181 MachineOperand *Prev; // Access list for register. See MRI.
182 MachineOperand *Next;
183 } Reg;
184
185 /// OffsetedInfo - This struct contains the offset and an object identifier.
186 /// this represent the object as with an optional offset from it.
187 struct {
188 union {
189 int Index; // For MO_*Index - The index itself.
190 const char *SymbolName; // For MO_ExternalSymbol.
191 const GlobalValue *GV; // For MO_GlobalAddress.
192 const BlockAddress *BA; // For MO_BlockAddress.
193 } Val;
194 // Low bits of offset are in SmallContents.OffsetLo.
195 int OffsetHi; // An offset from the object, high 32 bits.
196 } OffsetedInfo;
197 } Contents;
198
199 explicit MachineOperand(MachineOperandType K)
200 : OpKind(K), SubReg_TargetFlags(0), ParentMI(nullptr) {
201 // Assert that the layout is what we expect. It's easy to grow this object.
202 static_assert(alignof(MachineOperand) <= alignof(int64_t),
203 "MachineOperand shouldn't be more than 8 byte aligned");
204 static_assert(sizeof(Contents) <= 2 * sizeof(void *),
205 "Contents should be at most two pointers");
206 static_assert(sizeof(MachineOperand) <=
207 alignTo<alignof(int64_t)>(2 * sizeof(unsigned) +
208 3 * sizeof(void *)),
209 "MachineOperand too big. Should be Kind, SmallContents, "
210 "ParentMI, and Contents");
211 }
212
213public:
214 /// getType - Returns the MachineOperandType for this operand.
215 ///
216 MachineOperandType getType() const { return (MachineOperandType)OpKind; }
217
218 unsigned getTargetFlags() const {
219 return isReg() ? 0 : SubReg_TargetFlags;
220 }
221 void setTargetFlags(unsigned F) {
222 assert(!isReg() && "Register operands can't have target flags")((!isReg() && "Register operands can't have target flags"
) ? static_cast<void> (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 222, __PRETTY_FUNCTION__))
;
223 SubReg_TargetFlags = F;
224 assert(SubReg_TargetFlags == F && "Target flags out of range")((SubReg_TargetFlags == F && "Target flags out of range"
) ? static_cast<void> (0) : __assert_fail ("SubReg_TargetFlags == F && \"Target flags out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 224, __PRETTY_FUNCTION__))
;
225 }
226 void addTargetFlag(unsigned F) {
227 assert(!isReg() && "Register operands can't have target flags")((!isReg() && "Register operands can't have target flags"
) ? static_cast<void> (0) : __assert_fail ("!isReg() && \"Register operands can't have target flags\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 227, __PRETTY_FUNCTION__))
;
228 SubReg_TargetFlags |= F;
229 assert((SubReg_TargetFlags & F) && "Target flags out of range")(((SubReg_TargetFlags & F) && "Target flags out of range"
) ? static_cast<void> (0) : __assert_fail ("(SubReg_TargetFlags & F) && \"Target flags out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 229, __PRETTY_FUNCTION__))
;
230 }
231
232
233 /// getParent - Return the instruction that this operand belongs to.
234 ///
235 MachineInstr *getParent() { return ParentMI; }
236 const MachineInstr *getParent() const { return ParentMI; }
237
238 /// clearParent - Reset the parent pointer.
239 ///
240 /// The MachineOperand copy constructor also copies ParentMI, expecting the
241 /// original to be deleted. If a MachineOperand is ever stored outside a
242 /// MachineInstr, the parent pointer must be cleared.
243 ///
244 /// Never call clearParent() on an operand in a MachineInstr.
245 ///
246 void clearParent() { ParentMI = nullptr; }
247
248 /// Print a subreg index operand.
249 /// MO_Immediate operands can also be subreg idices. If it's the case, the
250 /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be
251 /// called to check this.
252 static void printSubRegIdx(raw_ostream &OS, uint64_t Index,
253 const TargetRegisterInfo *TRI);
254
255 /// Print operand target flags.
256 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
257
258 /// Print a MCSymbol as an operand.
259 static void printSymbol(raw_ostream &OS, MCSymbol &Sym);
260
261 /// Print a stack object reference.
262 static void printStackObjectReference(raw_ostream &OS, unsigned FrameIndex,
263 bool IsFixed, StringRef Name);
264
265 /// Print the offset with explicit +/- signs.
266 static void printOperandOffset(raw_ostream &OS, int64_t Offset);
267
268 /// Print an IRSlotNumber.
269 static void printIRSlotNumber(raw_ostream &OS, int Slot);
270
271 /// Print the MachineOperand to \p os.
272 /// Providing a valid \p TRI and \p IntrinsicInfo results in a more
273 /// target-specific printing. If \p TRI and \p IntrinsicInfo are null, the
274 /// function will try to pick it up from the parent.
275 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
276 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
277
278 /// More complex way of printing a MachineOperand.
279 /// \param TypeToPrint specifies the generic type to be printed on uses and
280 /// defs. It can be determined using MachineInstr::getTypeToPrint.
281 /// \param PrintDef - whether we want to print `def` on an operand which
282 /// isDef. Sometimes, if the operand is printed before '=', we don't print
283 /// `def`.
284 /// \param IsStandalone - whether we want a verbose output of the MO. This
285 /// prints extra information that can be easily inferred when printing the
286 /// whole function, but not when printing only a fragment of it.
287 /// \param ShouldPrintRegisterTies - whether we want to print register ties.
288 /// Sometimes they are easily determined by the instruction's descriptor
289 /// (MachineInstr::hasComplexRegiterTies can determine if it's needed).
290 /// \param TiedOperandIdx - if we need to print register ties this needs to
291 /// provide the index of the tied register. If not, it will be ignored.
292 /// \param TRI - provide more target-specific information to the printer.
293 /// Unlike the previous function, this one will not try and get the
294 /// information from it's parent.
295 /// \param IntrinsicInfo - same as \p TRI.
296 void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint,
297 bool PrintDef, bool IsStandalone, bool ShouldPrintRegisterTies,
298 unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
299 const TargetIntrinsicInfo *IntrinsicInfo) const;
300
301 /// Same as print(os, TRI, IntrinsicInfo), but allows to specify the low-level
302 /// type to be printed the same way the full version of print(...) does it.
303 void print(raw_ostream &os, LLT TypeToPrint,
304 const TargetRegisterInfo *TRI = nullptr,
305 const TargetIntrinsicInfo *IntrinsicInfo = nullptr) const;
306
307 void dump() const;
308
309 //===--------------------------------------------------------------------===//
310 // Accessors that tell you what kind of MachineOperand you're looking at.
311 //===--------------------------------------------------------------------===//
312
313 /// isReg - Tests if this is a MO_Register operand.
314 bool isReg() const { return OpKind == MO_Register; }
41
Assuming field 'OpKind' is equal to MO_Register
42
Returning the value 1, which participates in a condition later
315 /// isImm - Tests if this is a MO_Immediate operand.
316 bool isImm() const { return OpKind == MO_Immediate; }
317 /// isCImm - Test if this is a MO_CImmediate operand.
318 bool isCImm() const { return OpKind == MO_CImmediate; }
319 /// isFPImm - Tests if this is a MO_FPImmediate operand.
320 bool isFPImm() const { return OpKind == MO_FPImmediate; }
321 /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
322 bool isMBB() const { return OpKind == MO_MachineBasicBlock; }
323 /// isFI - Tests if this is a MO_FrameIndex operand.
324 bool isFI() const { return OpKind == MO_FrameIndex; }
325 /// isCPI - Tests if this is a MO_ConstantPoolIndex operand.
326 bool isCPI() const { return OpKind == MO_ConstantPoolIndex; }
327 /// isTargetIndex - Tests if this is a MO_TargetIndex operand.
328 bool isTargetIndex() const { return OpKind == MO_TargetIndex; }
329 /// isJTI - Tests if this is a MO_JumpTableIndex operand.
330 bool isJTI() const { return OpKind == MO_JumpTableIndex; }
331 /// isGlobal - Tests if this is a MO_GlobalAddress operand.
332 bool isGlobal() const { return OpKind == MO_GlobalAddress; }
333 /// isSymbol - Tests if this is a MO_ExternalSymbol operand.
334 bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
335 /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
336 bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
337 /// isRegMask - Tests if this is a MO_RegisterMask operand.
338 bool isRegMask() const { return OpKind == MO_RegisterMask; }
339 /// isRegLiveOut - Tests if this is a MO_RegisterLiveOut operand.
340 bool isRegLiveOut() const { return OpKind == MO_RegisterLiveOut; }
341 /// isMetadata - Tests if this is a MO_Metadata operand.
342 bool isMetadata() const { return OpKind == MO_Metadata; }
343 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
344 bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
345 bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
346 bool isPredicate() const { return OpKind == MO_Predicate; }
347 bool isShuffleMask() const { return OpKind == MO_ShuffleMask; }
348 //===--------------------------------------------------------------------===//
349 // Accessors for Register Operands
350 //===--------------------------------------------------------------------===//
351
352 /// getReg - Returns the register number.
353 Register getReg() const {
354 assert(isReg() && "This is not a register operand!")((isReg() && "This is not a register operand!") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"This is not a register operand!\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 354, __PRETTY_FUNCTION__))
;
355 return Register(SmallContents.RegNo);
356 }
357
358 unsigned getSubReg() const {
359 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 359, __PRETTY_FUNCTION__))
;
360 return SubReg_TargetFlags;
361 }
362
363 bool isUse() const {
364 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 364, __PRETTY_FUNCTION__))
;
365 return !IsDef;
366 }
367
368 bool isDef() const {
369 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 369, __PRETTY_FUNCTION__))
;
370 return IsDef;
371 }
372
373 bool isImplicit() const {
374 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 374, __PRETTY_FUNCTION__))
;
375 return IsImp;
376 }
377
378 bool isDead() const {
379 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 379, __PRETTY_FUNCTION__))
;
380 return IsDeadOrKill & IsDef;
381 }
382
383 bool isKill() const {
384 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 384, __PRETTY_FUNCTION__))
;
385 return IsDeadOrKill & !IsDef;
386 }
387
388 bool isUndef() const {
389 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 389, __PRETTY_FUNCTION__))
;
390 return IsUndef;
391 }
392
393 /// isRenamable - Returns true if this register may be renamed, i.e. it does
394 /// not generate a value that is somehow read in a way that is not represented
395 /// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
396 /// valid on physical register operands. Virtual registers are assumed to
397 /// always be renamable regardless of the value of this field.
398 ///
399 /// Operands that are renamable can freely be changed to any other register
400 /// that is a member of the register class returned by
401 /// MI->getRegClassConstraint().
402 ///
403 /// isRenamable can return false for several different reasons:
404 ///
405 /// - ABI constraints (since liveness is not always precisely modeled). We
406 /// conservatively handle these cases by setting all physical register
407 /// operands that didn’t start out as virtual regs to not be renamable.
408 /// Also any physical register operands created after register allocation or
409 /// whose register is changed after register allocation will not be
410 /// renamable. This state is tracked in the MachineOperand::IsRenamable
411 /// bit.
412 ///
413 /// - Opcode/target constraints: for opcodes that have complex register class
414 /// requirements (e.g. that depend on other operands/instructions), we set
415 /// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
416 /// description. Operands belonging to instructions with opcodes that are
417 /// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
418 /// isRenamable(). Additionally, the AllowRegisterRenaming target property
419 /// prevents any operands from being marked renamable for targets that don't
420 /// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
421 /// values.
422 bool isRenamable() const;
423
424 bool isInternalRead() const {
425 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 425, __PRETTY_FUNCTION__))
;
426 return IsInternalRead;
427 }
428
429 bool isEarlyClobber() const {
430 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 430, __PRETTY_FUNCTION__))
;
431 return IsEarlyClobber;
432 }
433
434 bool isTied() const {
435 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 435, __PRETTY_FUNCTION__))
;
436 return TiedTo;
437 }
438
439 bool isDebug() const {
440 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 440, __PRETTY_FUNCTION__))
;
441 return IsDebug;
442 }
443
444 /// readsReg - Returns true if this operand reads the previous value of its
445 /// register. A use operand with the <undef> flag set doesn't read its
446 /// register. A sub-register def implicitly reads the other parts of the
447 /// register being redefined unless the <undef> flag is set.
448 ///
449 /// This refers to reading the register value from before the current
450 /// instruction or bundle. Internal bundle reads are not included.
451 bool readsReg() const {
452 assert(isReg() && "Wrong MachineOperand accessor")((isReg() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 452, __PRETTY_FUNCTION__))
;
453 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
454 }
455
456 //===--------------------------------------------------------------------===//
457 // Mutators for Register Operands
458 //===--------------------------------------------------------------------===//
459
460 /// Change the register this operand corresponds to.
461 ///
462 void setReg(Register Reg);
463
464 void setSubReg(unsigned subReg) {
465 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 465, __PRETTY_FUNCTION__))
;
466 SubReg_TargetFlags = subReg;
467 assert(SubReg_TargetFlags == subReg && "SubReg out of range")((SubReg_TargetFlags == subReg && "SubReg out of range"
) ? static_cast<void> (0) : __assert_fail ("SubReg_TargetFlags == subReg && \"SubReg out of range\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 467, __PRETTY_FUNCTION__))
;
468 }
469
470 /// substVirtReg - Substitute the current register with the virtual
471 /// subregister Reg:SubReg. Take any existing SubReg index into account,
472 /// using TargetRegisterInfo to compose the subreg indices if necessary.
473 /// Reg must be a virtual register, SubIdx can be 0.
474 ///
475 void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
476
477 /// substPhysReg - Substitute the current register with the physical register
478 /// Reg, taking any existing SubReg into account. For instance,
479 /// substPhysReg(%eax) will change %reg1024:sub_8bit to %al.
480 ///
481 void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
482
483 void setIsUse(bool Val = true) { setIsDef(!Val); }
484
485 /// Change a def to a use, or a use to a def.
486 void setIsDef(bool Val = true);
487
488 void setImplicit(bool Val = true) {
489 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 489, __PRETTY_FUNCTION__))
;
490 IsImp = Val;
491 }
492
493 void setIsKill(bool Val = true) {
494 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")((isReg() && !IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 494, __PRETTY_FUNCTION__))
;
495 assert((!Val || !isDebug()) && "Marking a debug operation as kill")(((!Val || !isDebug()) && "Marking a debug operation as kill"
) ? static_cast<void> (0) : __assert_fail ("(!Val || !isDebug()) && \"Marking a debug operation as kill\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 495, __PRETTY_FUNCTION__))
;
496 IsDeadOrKill = Val;
497 }
498
499 void setIsDead(bool Val = true) {
500 assert(isReg() && IsDef && "Wrong MachineOperand mutator")((isReg() && IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 500, __PRETTY_FUNCTION__))
;
501 IsDeadOrKill = Val;
502 }
503
504 void setIsUndef(bool Val = true) {
505 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 505, __PRETTY_FUNCTION__))
;
506 IsUndef = Val;
507 }
508
509 void setIsRenamable(bool Val = true);
510
511 void setIsInternalRead(bool Val = true) {
512 assert(isReg() && "Wrong MachineOperand mutator")((isReg() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isReg() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 512, __PRETTY_FUNCTION__))
;
513 IsInternalRead = Val;
514 }
515
516 void setIsEarlyClobber(bool Val = true) {
517 assert(isReg() && IsDef && "Wrong MachineOperand mutator")((isReg() && IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 517, __PRETTY_FUNCTION__))
;
518 IsEarlyClobber = Val;
519 }
520
521 void setIsDebug(bool Val = true) {
522 assert(isReg() && !IsDef && "Wrong MachineOperand mutator")((isReg() && !IsDef && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("isReg() && !IsDef && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 522, __PRETTY_FUNCTION__))
;
523 IsDebug = Val;
524 }
525
526 //===--------------------------------------------------------------------===//
527 // Accessors for various operand types.
528 //===--------------------------------------------------------------------===//
529
530 int64_t getImm() const {
531 assert(isImm() && "Wrong MachineOperand accessor")((isImm() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 531, __PRETTY_FUNCTION__))
;
532 return Contents.ImmVal;
533 }
534
535 const ConstantInt *getCImm() const {
536 assert(isCImm() && "Wrong MachineOperand accessor")((isCImm() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 536, __PRETTY_FUNCTION__))
;
537 return Contents.CI;
538 }
539
540 const ConstantFP *getFPImm() const {
541 assert(isFPImm() && "Wrong MachineOperand accessor")((isFPImm() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 541, __PRETTY_FUNCTION__))
;
542 return Contents.CFP;
543 }
544
545 MachineBasicBlock *getMBB() const {
546 assert(isMBB() && "Wrong MachineOperand accessor")((isMBB() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 546, __PRETTY_FUNCTION__))
;
547 return Contents.MBB;
548 }
549
550 int getIndex() const {
551 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand accessor") ? static_cast<void> (
0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 552, __PRETTY_FUNCTION__))
552 "Wrong MachineOperand accessor")(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand accessor") ? static_cast<void> (
0) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 552, __PRETTY_FUNCTION__))
;
553 return Contents.OffsetedInfo.Val.Index;
554 }
555
556 const GlobalValue *getGlobal() const {
557 assert(isGlobal() && "Wrong MachineOperand accessor")((isGlobal() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isGlobal() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 557, __PRETTY_FUNCTION__))
;
558 return Contents.OffsetedInfo.Val.GV;
559 }
560
561 const BlockAddress *getBlockAddress() const {
562 assert(isBlockAddress() && "Wrong MachineOperand accessor")((isBlockAddress() && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("isBlockAddress() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 562, __PRETTY_FUNCTION__))
;
563 return Contents.OffsetedInfo.Val.BA;
564 }
565
566 MCSymbol *getMCSymbol() const {
567 assert(isMCSymbol() && "Wrong MachineOperand accessor")((isMCSymbol() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isMCSymbol() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 567, __PRETTY_FUNCTION__))
;
568 return Contents.Sym;
569 }
570
571 unsigned getCFIIndex() const {
572 assert(isCFIIndex() && "Wrong MachineOperand accessor")((isCFIIndex() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isCFIIndex() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 572, __PRETTY_FUNCTION__))
;
573 return Contents.CFIIndex;
574 }
575
576 Intrinsic::ID getIntrinsicID() const {
577 assert(isIntrinsicID() && "Wrong MachineOperand accessor")((isIntrinsicID() && "Wrong MachineOperand accessor")
? static_cast<void> (0) : __assert_fail ("isIntrinsicID() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 577, __PRETTY_FUNCTION__))
;
578 return Contents.IntrinsicID;
579 }
580
581 unsigned getPredicate() const {
582 assert(isPredicate() && "Wrong MachineOperand accessor")((isPredicate() && "Wrong MachineOperand accessor") ?
static_cast<void> (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 582, __PRETTY_FUNCTION__))
;
583 return Contents.Pred;
584 }
585
586 const Constant *getShuffleMask() const {
587 assert(isShuffleMask() && "Wrong MachineOperand accessor")((isShuffleMask() && "Wrong MachineOperand accessor")
? static_cast<void> (0) : __assert_fail ("isShuffleMask() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 587, __PRETTY_FUNCTION__))
;
588 return Contents.ShuffleMask;
589 }
590
591 /// Return the offset from the symbol in this operand. This always returns 0
592 /// for ExternalSymbol operands.
593 int64_t getOffset() const {
594 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 596, __PRETTY_FUNCTION__))
595 isTargetIndex() || isBlockAddress()) &&(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 596, __PRETTY_FUNCTION__))
596 "Wrong MachineOperand accessor")(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand accessor"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 596, __PRETTY_FUNCTION__))
;
597 return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) |
598 SmallContents.OffsetLo;
599 }
600
601 const char *getSymbolName() const {
602 assert(isSymbol() && "Wrong MachineOperand accessor")((isSymbol() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isSymbol() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 602, __PRETTY_FUNCTION__))
;
603 return Contents.OffsetedInfo.Val.SymbolName;
604 }
605
606 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
607 /// It is sometimes necessary to detach the register mask pointer from its
608 /// machine operand. This static method can be used for such detached bit
609 /// mask pointers.
610 static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) {
611 // See TargetRegisterInfo.h.
612 assert(PhysReg < (1u << 30) && "Not a physical register")((PhysReg < (1u << 30) && "Not a physical register"
) ? static_cast<void> (0) : __assert_fail ("PhysReg < (1u << 30) && \"Not a physical register\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 612, __PRETTY_FUNCTION__))
;
613 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32));
614 }
615
616 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
617 bool clobbersPhysReg(unsigned PhysReg) const {
618 return clobbersPhysReg(getRegMask(), PhysReg);
619 }
620
621 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
622 /// operand.
623 const uint32_t *getRegMask() const {
624 assert(isRegMask() && "Wrong MachineOperand accessor")((isRegMask() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 624, __PRETTY_FUNCTION__))
;
625 return Contents.RegMask;
626 }
627
628 /// Returns number of elements needed for a regmask array.
629 static unsigned getRegMaskSize(unsigned NumRegs) {
630 return (NumRegs + 31) / 32;
631 }
632
633 /// getRegLiveOut - Returns a bit mask of live-out registers.
634 const uint32_t *getRegLiveOut() const {
635 assert(isRegLiveOut() && "Wrong MachineOperand accessor")((isRegLiveOut() && "Wrong MachineOperand accessor") ?
static_cast<void> (0) : __assert_fail ("isRegLiveOut() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 635, __PRETTY_FUNCTION__))
;
636 return Contents.RegMask;
637 }
638
639 const MDNode *getMetadata() const {
640 assert(isMetadata() && "Wrong MachineOperand accessor")((isMetadata() && "Wrong MachineOperand accessor") ? static_cast
<void> (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand accessor\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 640, __PRETTY_FUNCTION__))
;
641 return Contents.MD;
642 }
643
644 //===--------------------------------------------------------------------===//
645 // Mutators for various operand types.
646 //===--------------------------------------------------------------------===//
647
648 void setImm(int64_t immVal) {
649 assert(isImm() && "Wrong MachineOperand mutator")((isImm() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 649, __PRETTY_FUNCTION__))
;
650 Contents.ImmVal = immVal;
651 }
652
653 void setCImm(const ConstantInt *CI) {
654 assert(isCImm() && "Wrong MachineOperand mutator")((isCImm() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isCImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 654, __PRETTY_FUNCTION__))
;
655 Contents.CI = CI;
656 }
657
658 void setFPImm(const ConstantFP *CFP) {
659 assert(isFPImm() && "Wrong MachineOperand mutator")((isFPImm() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isFPImm() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 659, __PRETTY_FUNCTION__))
;
660 Contents.CFP = CFP;
661 }
662
663 void setOffset(int64_t Offset) {
664 assert((isGlobal() || isSymbol() || isMCSymbol() || isCPI() ||(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 666, __PRETTY_FUNCTION__))
665 isTargetIndex() || isBlockAddress()) &&(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 666, __PRETTY_FUNCTION__))
666 "Wrong MachineOperand mutator")(((isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex
() || isBlockAddress()) && "Wrong MachineOperand mutator"
) ? static_cast<void> (0) : __assert_fail ("(isGlobal() || isSymbol() || isMCSymbol() || isCPI() || isTargetIndex() || isBlockAddress()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 666, __PRETTY_FUNCTION__))
;
667 SmallContents.OffsetLo = unsigned(Offset);
668 Contents.OffsetedInfo.OffsetHi = int(Offset >> 32);
669 }
670
671 void setIndex(int Idx) {
672 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand mutator") ? static_cast<void> (0
) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 673, __PRETTY_FUNCTION__))
673 "Wrong MachineOperand mutator")(((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
"Wrong MachineOperand mutator") ? static_cast<void> (0
) : __assert_fail ("(isFI() || isCPI() || isTargetIndex() || isJTI()) && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 673, __PRETTY_FUNCTION__))
;
674 Contents.OffsetedInfo.Val.Index = Idx;
675 }
676
677 void setMetadata(const MDNode *MD) {
678 assert(isMetadata() && "Wrong MachineOperand mutator")((isMetadata() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isMetadata() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 678, __PRETTY_FUNCTION__))
;
679 Contents.MD = MD;
680 }
681
682 void setMBB(MachineBasicBlock *MBB) {
683 assert(isMBB() && "Wrong MachineOperand mutator")((isMBB() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isMBB() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 683, __PRETTY_FUNCTION__))
;
684 Contents.MBB = MBB;
685 }
686
687 /// Sets value of register mask operand referencing Mask. The
688 /// operand does not take ownership of the memory referenced by Mask, it must
689 /// remain valid for the lifetime of the operand. See CreateRegMask().
690 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
691 void setRegMask(const uint32_t *RegMaskPtr) {
692 assert(isRegMask() && "Wrong MachineOperand mutator")((isRegMask() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isRegMask() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 692, __PRETTY_FUNCTION__))
;
693 Contents.RegMask = RegMaskPtr;
694 }
695
696 void setPredicate(unsigned Predicate) {
697 assert(isPredicate() && "Wrong MachineOperand mutator")((isPredicate() && "Wrong MachineOperand mutator") ? static_cast
<void> (0) : __assert_fail ("isPredicate() && \"Wrong MachineOperand mutator\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 697, __PRETTY_FUNCTION__))
;
698 Contents.Pred = Predicate;
699 }
700
701 //===--------------------------------------------------------------------===//
702 // Other methods.
703 //===--------------------------------------------------------------------===//
704
705 /// Returns true if this operand is identical to the specified operand except
706 /// for liveness related flags (isKill, isUndef and isDead). Note that this
707 /// should stay in sync with the hash_value overload below.
708 bool isIdenticalTo(const MachineOperand &Other) const;
709
710 /// MachineOperand hash_value overload.
711 ///
712 /// Note that this includes the same information in the hash that
713 /// isIdenticalTo uses for comparison. It is thus suited for use in hash
714 /// tables which use that function for equality comparisons only. This must
715 /// stay exactly in sync with isIdenticalTo above.
716 friend hash_code hash_value(const MachineOperand &MO);
717
718 /// ChangeToImmediate - Replace this operand with a new immediate operand of
719 /// the specified value. If an operand is known to be an immediate already,
720 /// the setImm method should be used.
721 void ChangeToImmediate(int64_t ImmVal);
722
723 /// ChangeToFPImmediate - Replace this operand with a new FP immediate operand
724 /// of the specified value. If an operand is known to be an FP immediate
725 /// already, the setFPImm method should be used.
726 void ChangeToFPImmediate(const ConstantFP *FPImm);
727
728 /// ChangeToES - Replace this operand with a new external symbol operand.
729 void ChangeToES(const char *SymName, unsigned TargetFlags = 0);
730
731 /// ChangeToGA - Replace this operand with a new global address operand.
732 void ChangeToGA(const GlobalValue *GV, int64_t Offset,
733 unsigned TargetFlags = 0);
734
735 /// ChangeToMCSymbol - Replace this operand with a new MC symbol operand.
736 void ChangeToMCSymbol(MCSymbol *Sym);
737
738 /// Replace this operand with a frame index.
739 void ChangeToFrameIndex(int Idx);
740
741 /// Replace this operand with a target index.
742 void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
743 unsigned TargetFlags = 0);
744
745 /// ChangeToRegister - Replace this operand with a new register operand of
746 /// the specified value. If an operand is known to be an register already,
747 /// the setReg method should be used.
748 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
749 bool isKill = false, bool isDead = false,
750 bool isUndef = false, bool isDebug = false);
751
752 //===--------------------------------------------------------------------===//
753 // Construction methods.
754 //===--------------------------------------------------------------------===//
755
756 static MachineOperand CreateImm(int64_t Val) {
757 MachineOperand Op(MachineOperand::MO_Immediate);
758 Op.setImm(Val);
759 return Op;
760 }
761
762 static MachineOperand CreateCImm(const ConstantInt *CI) {
763 MachineOperand Op(MachineOperand::MO_CImmediate);
764 Op.Contents.CI = CI;
765 return Op;
766 }
767
768 static MachineOperand CreateFPImm(const ConstantFP *CFP) {
769 MachineOperand Op(MachineOperand::MO_FPImmediate);
770 Op.Contents.CFP = CFP;
771 return Op;
772 }
773
774 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
775 bool isKill = false, bool isDead = false,
776 bool isUndef = false,
777 bool isEarlyClobber = false,
778 unsigned SubReg = 0, bool isDebug = false,
779 bool isInternalRead = false,
780 bool isRenamable = false) {
781 assert(!(isDead && !isDef) && "Dead flag on non-def")((!(isDead && !isDef) && "Dead flag on non-def"
) ? static_cast<void> (0) : __assert_fail ("!(isDead && !isDef) && \"Dead flag on non-def\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 781, __PRETTY_FUNCTION__))
;
782 assert(!(isKill && isDef) && "Kill flag on def")((!(isKill && isDef) && "Kill flag on def") ?
static_cast<void> (0) : __assert_fail ("!(isKill && isDef) && \"Kill flag on def\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 782, __PRETTY_FUNCTION__))
;
783 MachineOperand Op(MachineOperand::MO_Register);
784 Op.IsDef = isDef;
785 Op.IsImp = isImp;
786 Op.IsDeadOrKill = isKill | isDead;
787 Op.IsRenamable = isRenamable;
788 Op.IsUndef = isUndef;
789 Op.IsInternalRead = isInternalRead;
790 Op.IsEarlyClobber = isEarlyClobber;
791 Op.TiedTo = 0;
792 Op.IsDebug = isDebug;
793 Op.SmallContents.RegNo = Reg;
794 Op.Contents.Reg.Prev = nullptr;
795 Op.Contents.Reg.Next = nullptr;
796 Op.setSubReg(SubReg);
797 return Op;
798 }
799 static MachineOperand CreateMBB(MachineBasicBlock *MBB,
800 unsigned TargetFlags = 0) {
801 MachineOperand Op(MachineOperand::MO_MachineBasicBlock);
802 Op.setMBB(MBB);
803 Op.setTargetFlags(TargetFlags);
804 return Op;
805 }
806 static MachineOperand CreateFI(int Idx) {
807 MachineOperand Op(MachineOperand::MO_FrameIndex);
808 Op.setIndex(Idx);
809 return Op;
810 }
811 static MachineOperand CreateCPI(unsigned Idx, int Offset,
812 unsigned TargetFlags = 0) {
813 MachineOperand Op(MachineOperand::MO_ConstantPoolIndex);
814 Op.setIndex(Idx);
815 Op.setOffset(Offset);
816 Op.setTargetFlags(TargetFlags);
817 return Op;
818 }
819 static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset,
820 unsigned TargetFlags = 0) {
821 MachineOperand Op(MachineOperand::MO_TargetIndex);
822 Op.setIndex(Idx);
823 Op.setOffset(Offset);
824 Op.setTargetFlags(TargetFlags);
825 return Op;
826 }
827 static MachineOperand CreateJTI(unsigned Idx, unsigned TargetFlags = 0) {
828 MachineOperand Op(MachineOperand::MO_JumpTableIndex);
829 Op.setIndex(Idx);
830 Op.setTargetFlags(TargetFlags);
831 return Op;
832 }
833 static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset,
834 unsigned TargetFlags = 0) {
835 MachineOperand Op(MachineOperand::MO_GlobalAddress);
836 Op.Contents.OffsetedInfo.Val.GV = GV;
837 Op.setOffset(Offset);
838 Op.setTargetFlags(TargetFlags);
839 return Op;
840 }
841 static MachineOperand CreateES(const char *SymName,
842 unsigned TargetFlags = 0) {
843 MachineOperand Op(MachineOperand::MO_ExternalSymbol);
844 Op.Contents.OffsetedInfo.Val.SymbolName = SymName;
845 Op.setOffset(0); // Offset is always 0.
846 Op.setTargetFlags(TargetFlags);
847 return Op;
848 }
849 static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset,
850 unsigned TargetFlags = 0) {
851 MachineOperand Op(MachineOperand::MO_BlockAddress);
852 Op.Contents.OffsetedInfo.Val.BA = BA;
853 Op.setOffset(Offset);
854 Op.setTargetFlags(TargetFlags);
855 return Op;
856 }
857 /// CreateRegMask - Creates a register mask operand referencing Mask. The
858 /// operand does not take ownership of the memory referenced by Mask, it
859 /// must remain valid for the lifetime of the operand.
860 ///
861 /// A RegMask operand represents a set of non-clobbered physical registers
862 /// on an instruction that clobbers many registers, typically a call. The
863 /// bit mask has a bit set for each physreg that is preserved by this
864 /// instruction, as described in the documentation for
865 /// TargetRegisterInfo::getCallPreservedMask().
866 ///
867 /// Any physreg with a 0 bit in the mask is clobbered by the instruction.
868 ///
869 static MachineOperand CreateRegMask(const uint32_t *Mask) {
870 assert(Mask && "Missing register mask")((Mask && "Missing register mask") ? static_cast<void
> (0) : __assert_fail ("Mask && \"Missing register mask\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 870, __PRETTY_FUNCTION__))
;
871 MachineOperand Op(MachineOperand::MO_RegisterMask);
872 Op.Contents.RegMask = Mask;
873 return Op;
874 }
875 static MachineOperand CreateRegLiveOut(const uint32_t *Mask) {
876 assert(Mask && "Missing live-out register mask")((Mask && "Missing live-out register mask") ? static_cast
<void> (0) : __assert_fail ("Mask && \"Missing live-out register mask\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 876, __PRETTY_FUNCTION__))
;
877 MachineOperand Op(MachineOperand::MO_RegisterLiveOut);
878 Op.Contents.RegMask = Mask;
879 return Op;
880 }
881 static MachineOperand CreateMetadata(const MDNode *Meta) {
882 MachineOperand Op(MachineOperand::MO_Metadata);
883 Op.Contents.MD = Meta;
884 return Op;
885 }
886
887 static MachineOperand CreateMCSymbol(MCSymbol *Sym,
888 unsigned TargetFlags = 0) {
889 MachineOperand Op(MachineOperand::MO_MCSymbol);
890 Op.Contents.Sym = Sym;
891 Op.setOffset(0);
892 Op.setTargetFlags(TargetFlags);
893 return Op;
894 }
895
896 static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
897 MachineOperand Op(MachineOperand::MO_CFIIndex);
898 Op.Contents.CFIIndex = CFIIndex;
899 return Op;
900 }
901
902 static MachineOperand CreateIntrinsicID(Intrinsic::ID ID) {
903 MachineOperand Op(MachineOperand::MO_IntrinsicID);
904 Op.Contents.IntrinsicID = ID;
905 return Op;
906 }
907
908 static MachineOperand CreatePredicate(unsigned Pred) {
909 MachineOperand Op(MachineOperand::MO_Predicate);
910 Op.Contents.Pred = Pred;
911 return Op;
912 }
913
914 static MachineOperand CreateShuffleMask(const Constant *C) {
915 MachineOperand Op(MachineOperand::MO_ShuffleMask);
916 Op.Contents.ShuffleMask = C;
917 return Op;
918 }
919
920 friend class MachineInstr;
921 friend class MachineRegisterInfo;
922
923private:
924 // If this operand is currently a register operand, and if this is in a
925 // function, deregister the operand from the register's use/def list.
926 void removeRegFromUses();
927
928 /// Artificial kinds for DenseMap usage.
929 enum : unsigned char {
930 MO_Empty = MO_Last + 1,
931 MO_Tombstone,
932 };
933
934 friend struct DenseMapInfo<MachineOperand>;
935
936 //===--------------------------------------------------------------------===//
937 // Methods for handling register use/def lists.
938 //===--------------------------------------------------------------------===//
939
940 /// isOnRegUseList - Return true if this operand is on a register use/def
941 /// list or false if not. This can only be called for register operands
942 /// that are part of a machine instruction.
943 bool isOnRegUseList() const {
944 assert(isReg() && "Can only add reg operand to use lists")((isReg() && "Can only add reg operand to use lists")
? static_cast<void> (0) : __assert_fail ("isReg() && \"Can only add reg operand to use lists\""
, "/build/llvm-toolchain-snapshot-10~svn373517/include/llvm/CodeGen/MachineOperand.h"
, 944, __PRETTY_FUNCTION__))
;
945 return Contents.Reg.Prev != nullptr;
946 }
947};
948
949template <> struct DenseMapInfo<MachineOperand> {
950 static MachineOperand getEmptyKey() {
951 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
952 MachineOperand::MO_Empty));
953 }
954 static MachineOperand getTombstoneKey() {
955 return MachineOperand(static_cast<MachineOperand::MachineOperandType>(
956 MachineOperand::MO_Tombstone));
957 }
958 static unsigned getHashValue(const MachineOperand &MO) {
959 return hash_value(MO);
960 }
961 static bool isEqual(const MachineOperand &LHS, const MachineOperand &RHS) {
962 if (LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
963 MachineOperand::MO_Empty) ||
964 LHS.getType() == static_cast<MachineOperand::MachineOperandType>(
965 MachineOperand::MO_Tombstone))
966 return LHS.getType() == RHS.getType();
967 return LHS.isIdenticalTo(RHS);
968 }
969};
970
971inline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand &MO) {
972 MO.print(OS);
973 return OS;
974}
975
976// See friend declaration above. This additional declaration is required in
977// order to compile LLVM with IBM xlC compiler.
978hash_code hash_value(const MachineOperand &MO);
979} // namespace llvm
980
981#endif