Bug Summary

File:lib/CodeGen/MachineInstr.cpp
Warning:line 263, column 19
Access to field 'ParentMI' results in a dereference of a null pointer (loaded from variable 'NewMO')

Annotated Source Code

Press '?' to see keyboard shortcuts

clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-8/lib/clang/8.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen -I /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/include -I /build/llvm-toolchain-snapshot-8~svn345461/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/x86_64-linux-gnu/c++/6.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/6.3.0/../../../../include/c++/6.3.0/backward -internal-isystem /usr/include/clang/8.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-8/lib/clang/8.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-8~svn345461/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-10-27-211344-32123-1 -x c++ /build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp -faddrsig

/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp

1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/FoldingSet.h"
18#include "llvm/ADT/Hashing.h"
19#include "llvm/ADT/None.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallBitVector.h"
22#include "llvm/ADT/SmallString.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/Analysis/AliasAnalysis.h"
25#include "llvm/Analysis/Loads.h"
26#include "llvm/Analysis/MemoryLocation.h"
27#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
28#include "llvm/CodeGen/MachineBasicBlock.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetRegisterInfo.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/Config/llvm-config.h"
41#include "llvm/IR/Constants.h"
42#include "llvm/IR/DebugInfoMetadata.h"
43#include "llvm/IR/DebugLoc.h"
44#include "llvm/IR/DerivedTypes.h"
45#include "llvm/IR/Function.h"
46#include "llvm/IR/InlineAsm.h"
47#include "llvm/IR/InstrTypes.h"
48#include "llvm/IR/Intrinsics.h"
49#include "llvm/IR/LLVMContext.h"
50#include "llvm/IR/Metadata.h"
51#include "llvm/IR/Module.h"
52#include "llvm/IR/ModuleSlotTracker.h"
53#include "llvm/IR/Type.h"
54#include "llvm/IR/Value.h"
55#include "llvm/IR/Operator.h"
56#include "llvm/MC/MCInstrDesc.h"
57#include "llvm/MC/MCRegisterInfo.h"
58#include "llvm/MC/MCSymbol.h"
59#include "llvm/Support/Casting.h"
60#include "llvm/Support/CommandLine.h"
61#include "llvm/Support/Compiler.h"
62#include "llvm/Support/Debug.h"
63#include "llvm/Support/ErrorHandling.h"
64#include "llvm/Support/LowLevelTypeImpl.h"
65#include "llvm/Support/MathExtras.h"
66#include "llvm/Support/raw_ostream.h"
67#include "llvm/Target/TargetIntrinsicInfo.h"
68#include "llvm/Target/TargetMachine.h"
69#include <algorithm>
70#include <cassert>
71#include <cstddef>
72#include <cstdint>
73#include <cstring>
74#include <iterator>
75#include <utility>
76
77using namespace llvm;
78
79static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
80 if (const MachineBasicBlock *MBB = MI.getParent())
81 if (const MachineFunction *MF = MBB->getParent())
82 return MF;
83 return nullptr;
84}
85
86// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
87// it.
88static void tryToGetTargetInfo(const MachineInstr &MI,
89 const TargetRegisterInfo *&TRI,
90 const MachineRegisterInfo *&MRI,
91 const TargetIntrinsicInfo *&IntrinsicInfo,
92 const TargetInstrInfo *&TII) {
93
94 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
95 TRI = MF->getSubtarget().getRegisterInfo();
96 MRI = &MF->getRegInfo();
97 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
98 TII = MF->getSubtarget().getInstrInfo();
99 }
100}
101
102void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
103 if (MCID->ImplicitDefs)
104 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
105 ++ImpDefs)
106 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
107 if (MCID->ImplicitUses)
108 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
109 ++ImpUses)
110 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
111}
112
113/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
114/// implicit operands. It reserves space for the number of operands specified by
115/// the MCInstrDesc.
116MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
117 DebugLoc dl, bool NoImp)
118 : MCID(&tid), debugLoc(std::move(dl)) {
119 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 119, __PRETTY_FUNCTION__))
;
120
121 // Reserve space for the expected number of operands.
122 if (unsigned NumOps = MCID->getNumOperands() +
123 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
124 CapOperands = OperandCapacity::get(NumOps);
125 Operands = MF.allocateOperandArray(CapOperands);
126 }
127
128 if (!NoImp)
129 addImplicitDefUseOperands(MF);
130}
131
132/// MachineInstr ctor - Copies MachineInstr arg exactly
133///
134MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
135 : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) {
136 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor"
) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 136, __PRETTY_FUNCTION__))
;
137
138 CapOperands = OperandCapacity::get(MI.getNumOperands());
139 Operands = MF.allocateOperandArray(CapOperands);
140
141 // Copy operands.
142 for (const MachineOperand &MO : MI.operands())
143 addOperand(MF, MO);
144
145 // Copy all the sensible flags.
146 setFlags(MI.Flags);
147}
148
149/// getRegInfo - If this instruction is embedded into a MachineFunction,
150/// return the MachineRegisterInfo object for the current function, otherwise
151/// return null.
152MachineRegisterInfo *MachineInstr::getRegInfo() {
153 if (MachineBasicBlock *MBB = getParent())
154 return &MBB->getParent()->getRegInfo();
155 return nullptr;
156}
157
158/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
159/// this instruction from their respective use lists. This requires that the
160/// operands already be on their use lists.
161void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
162 for (MachineOperand &MO : operands())
163 if (MO.isReg())
164 MRI.removeRegOperandFromUseList(&MO);
165}
166
167/// AddRegOperandsToUseLists - Add all of the register operands in
168/// this instruction from their respective use lists. This requires that the
169/// operands not be on their use lists yet.
170void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
171 for (MachineOperand &MO : operands())
172 if (MO.isReg())
173 MRI.addRegOperandToUseList(&MO);
174}
175
176void MachineInstr::addOperand(const MachineOperand &Op) {
177 MachineBasicBlock *MBB = getParent();
178 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 178, __PRETTY_FUNCTION__))
;
179 MachineFunction *MF = MBB->getParent();
180 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 180, __PRETTY_FUNCTION__))
;
181 addOperand(*MF, Op);
182}
183
184/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
185/// ranges. If MRI is non-null also update use-def chains.
186static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
187 unsigned NumOps, MachineRegisterInfo *MRI) {
188 if (MRI)
189 return MRI->moveOperands(Dst, Src, NumOps);
190
191 // MachineOperand is a trivially copyable type so we can just use memmove.
192 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
193}
194
195/// addOperand - Add the specified operand to the instruction. If it is an
196/// implicit operand, it is added to the end of the operand list. If it is
197/// an explicit operand it is added at the end of the explicit operand list
198/// (before the first implicit operand).
199void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
200 assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor"
) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 200, __PRETTY_FUNCTION__))
;
201
202 // Check if we're adding one of our existing operands.
203 if (&Op >= Operands && &Op < Operands + NumOperands) {
204 // This is unusual: MI->addOperand(MI->getOperand(i)).
205 // If adding Op requires reallocating or moving existing operands around,
206 // the Op reference could go stale. Support it by copying Op.
207 MachineOperand CopyOp(Op);
208 return addOperand(MF, CopyOp);
209 }
210
211 // Find the insert location for the new operand. Implicit registers go at
212 // the end, everything else goes before the implicit regs.
213 //
214 // FIXME: Allow mixed explicit and implicit operands on inline asm.
215 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
216 // implicit-defs, but they must not be moved around. See the FIXME in
217 // InstrEmitter.cpp.
218 unsigned OpNo = getNumOperands();
219 bool isImpReg = Op.isReg() && Op.isImplicit();
220 if (!isImpReg && !isInlineAsm()) {
3
Taking true branch
221 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
4
Assuming 'OpNo' is 0
222 --OpNo;
223 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 223, __PRETTY_FUNCTION__))
;
224 }
225 }
226
227#ifndef NDEBUG
228 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
229 // OpNo now points as the desired insertion point. Unless this is a variadic
230 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
231 // RegMask operands go between the explicit and implicit operands.
232 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isMetaDataOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 234, __PRETTY_FUNCTION__))
233 OpNo < MCID->getNumOperands() || isMetaDataOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isMetaDataOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 234, __PRETTY_FUNCTION__))
234 "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo
< MCID->getNumOperands() || isMetaDataOp) && "Trying to add an operand to a machine instr that is already done!"
) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 234, __PRETTY_FUNCTION__))
;
235#endif
236
237 MachineRegisterInfo *MRI = getRegInfo();
238
239 // Determine if the Operands array needs to be reallocated.
240 // Save the old capacity and operand array.
241 OperandCapacity OldCap = CapOperands;
242 MachineOperand *OldOperands = Operands;
243 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
5
Assuming 'OldOperands' is null
244 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
6
'?' condition is false
245 Operands = MF.allocateOperandArray(CapOperands);
246 // Move the operands before the insertion point.
247 if (OpNo)
7
Taking false branch
248 moveOperands(Operands, OldOperands, OpNo, MRI);
249 }
250
251 // Move the operands following the insertion point.
252 if (OpNo != NumOperands)
8
Taking false branch
253 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
254 MRI);
255 ++NumOperands;
256
257 // Deallocate the old operand array.
258 if (OldOperands != Operands && OldOperands)
9
Assuming the condition is false
259 MF.deallocateOperandArray(OldCap, OldOperands);
260
261 // Copy Op into place. It still needs to be inserted into the MRI use lists.
262 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
10
'NewMO' initialized to a null pointer value
263 NewMO->ParentMI = this;
11
Access to field 'ParentMI' results in a dereference of a null pointer (loaded from variable 'NewMO')
264
265 // When adding a register operand, tell MRI about it.
266 if (NewMO->isReg()) {
267 // Ensure isOnRegUseList() returns false, regardless of Op's status.
268 NewMO->Contents.Reg.Prev = nullptr;
269 // Ignore existing ties. This is not a property that can be copied.
270 NewMO->TiedTo = 0;
271 // Add the new operand to MRI, but only for instructions in an MBB.
272 if (MRI)
273 MRI->addRegOperandToUseList(NewMO);
274 // The MCID operand information isn't accurate until we start adding
275 // explicit operands. The implicit operands are added first, then the
276 // explicits are inserted before them.
277 if (!isImpReg) {
278 // Tie uses to defs as indicated in MCInstrDesc.
279 if (NewMO->isUse()) {
280 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
281 if (DefIdx != -1)
282 tieOperands(DefIdx, OpNo);
283 }
284 // If the register operand is flagged as early, mark the operand as such.
285 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
286 NewMO->setIsEarlyClobber(true);
287 }
288 }
289}
290
291/// RemoveOperand - Erase an operand from an instruction, leaving it with one
292/// fewer operand than it started with.
293///
294void MachineInstr::RemoveOperand(unsigned OpNo) {
295 assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number"
) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 295, __PRETTY_FUNCTION__))
;
296 untieRegOperand(OpNo);
297
298#ifndef NDEBUG
299 // Moving tied operands would break the ties.
300 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
301 if (Operands[i].isReg())
302 assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands"
) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 302, __PRETTY_FUNCTION__))
;
303#endif
304
305 MachineRegisterInfo *MRI = getRegInfo();
306 if (MRI && Operands[OpNo].isReg())
307 MRI->removeRegOperandFromUseList(Operands + OpNo);
308
309 // Don't call the MachineOperand destructor. A lot of this code depends on
310 // MachineOperand having a trivial destructor anyway, and adding a call here
311 // wouldn't make it 'destructor-correct'.
312
313 if (unsigned N = NumOperands - 1 - OpNo)
314 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
315 --NumOperands;
316}
317
318void MachineInstr::dropMemRefs(MachineFunction &MF) {
319 if (memoperands_empty())
320 return;
321
322 // See if we can just drop all of our extra info.
323 if (!getPreInstrSymbol() && !getPostInstrSymbol()) {
324 Info.clear();
325 return;
326 }
327 if (!getPostInstrSymbol()) {
328 Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
329 return;
330 }
331 if (!getPreInstrSymbol()) {
332 Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
333 return;
334 }
335
336 // Otherwise allocate a fresh extra info with just these symbols.
337 Info.set<EIIK_OutOfLine>(
338 MF.createMIExtraInfo({}, getPreInstrSymbol(), getPostInstrSymbol()));
339}
340
341void MachineInstr::setMemRefs(MachineFunction &MF,
342 ArrayRef<MachineMemOperand *> MMOs) {
343 if (MMOs.empty()) {
344 dropMemRefs(MF);
345 return;
346 }
347
348 // Try to store a single MMO inline.
349 if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) {
350 Info.set<EIIK_MMO>(MMOs[0]);
351 return;
352 }
353
354 // Otherwise create an extra info struct with all of our info.
355 Info.set<EIIK_OutOfLine>(
356 MF.createMIExtraInfo(MMOs, getPreInstrSymbol(), getPostInstrSymbol()));
357}
358
359void MachineInstr::addMemOperand(MachineFunction &MF,
360 MachineMemOperand *MO) {
361 SmallVector<MachineMemOperand *, 2> MMOs;
362 MMOs.append(memoperands_begin(), memoperands_end());
363 MMOs.push_back(MO);
364 setMemRefs(MF, MMOs);
365}
366
367void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) {
368 if (this == &MI)
369 // Nothing to do for a self-clone!
370 return;
371
372 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 373, __PRETTY_FUNCTION__))
373 "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 373, __PRETTY_FUNCTION__))
;
374 // See if we can just steal the extra info already allocated for the
375 // instruction. We can do this whenever the pre- and post-instruction symbols
376 // are the same (including null).
377 if (getPreInstrSymbol() == MI.getPreInstrSymbol() &&
378 getPostInstrSymbol() == MI.getPostInstrSymbol()) {
379 Info = MI.Info;
380 return;
381 }
382
383 // Otherwise, fall back on a copy-based clone.
384 setMemRefs(MF, MI.memoperands());
385}
386
387/// Check to see if the MMOs pointed to by the two MemRefs arrays are
388/// identical.
389static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS,
390 ArrayRef<MachineMemOperand *> RHS) {
391 if (LHS.size() != RHS.size())
392 return false;
393
394 auto LHSPointees = make_pointee_range(LHS);
395 auto RHSPointees = make_pointee_range(RHS);
396 return std::equal(LHSPointees.begin(), LHSPointees.end(),
397 RHSPointees.begin());
398}
399
400void MachineInstr::cloneMergedMemRefs(MachineFunction &MF,
401 ArrayRef<const MachineInstr *> MIs) {
402 // Try handling easy numbers of MIs with simpler mechanisms.
403 if (MIs.empty()) {
404 dropMemRefs(MF);
405 return;
406 }
407 if (MIs.size() == 1) {
408 cloneMemRefs(MF, *MIs[0]);
409 return;
410 }
411 // Because an empty memoperands list provides *no* information and must be
412 // handled conservatively (assuming the instruction can do anything), the only
413 // way to merge with it is to drop all other memoperands.
414 if (MIs[0]->memoperands_empty()) {
415 dropMemRefs(MF);
416 return;
417 }
418
419 // Handle the general case.
420 SmallVector<MachineMemOperand *, 2> MergedMMOs;
421 // Start with the first instruction.
422 assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 423, __PRETTY_FUNCTION__))
423 "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 423, __PRETTY_FUNCTION__))
;
424 MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end());
425 // Now walk all the other instructions and accumulate any different MMOs.
426 for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) {
427 assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 428, __PRETTY_FUNCTION__))
428 "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!"
) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 428, __PRETTY_FUNCTION__))
;
429
430 // Skip MIs with identical operands to the first. This is a somewhat
431 // arbitrary hack but will catch common cases without being quadratic.
432 // TODO: We could fully implement merge semantics here if needed.
433 if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands()))
434 continue;
435
436 // Because an empty memoperands list provides *no* information and must be
437 // handled conservatively (assuming the instruction can do anything), the
438 // only way to merge with it is to drop all other memoperands.
439 if (MI.memoperands_empty()) {
440 dropMemRefs(MF);
441 return;
442 }
443
444 // Otherwise accumulate these into our temporary buffer of the merged state.
445 MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end());
446 }
447
448 setMemRefs(MF, MergedMMOs);
449}
450
451void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
452 MCSymbol *OldSymbol = getPreInstrSymbol();
453 if (OldSymbol == Symbol)
454 return;
455 if (OldSymbol && !Symbol) {
456 // We're removing a symbol rather than adding one. Try to clean up any
457 // extra info carried around.
458 if (Info.is<EIIK_PreInstrSymbol>()) {
459 Info.clear();
460 return;
461 }
462
463 if (memoperands_empty()) {
464 assert(getPostInstrSymbol() &&((getPostInstrSymbol() && "Should never have only a single symbol allocated out-of-line!"
) ? static_cast<void> (0) : __assert_fail ("getPostInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 465, __PRETTY_FUNCTION__))
465 "Should never have only a single symbol allocated out-of-line!")((getPostInstrSymbol() && "Should never have only a single symbol allocated out-of-line!"
) ? static_cast<void> (0) : __assert_fail ("getPostInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 465, __PRETTY_FUNCTION__))
;
466 Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol());
467 return;
468 }
469
470 // Otherwise fallback on the generic update.
471 } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) {
472 // If we don't have any other extra info, we can store this inline.
473 Info.set<EIIK_PreInstrSymbol>(Symbol);
474 return;
475 }
476
477 // Otherwise, allocate a full new set of extra info.
478 // FIXME: Maybe we should make the symbols in the extra info mutable?
479 Info.set<EIIK_OutOfLine>(
480 MF.createMIExtraInfo(memoperands(), Symbol, getPostInstrSymbol()));
481}
482
483void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) {
484 MCSymbol *OldSymbol = getPostInstrSymbol();
485 if (OldSymbol == Symbol)
486 return;
487 if (OldSymbol && !Symbol) {
488 // We're removing a symbol rather than adding one. Try to clean up any
489 // extra info carried around.
490 if (Info.is<EIIK_PostInstrSymbol>()) {
491 Info.clear();
492 return;
493 }
494
495 if (memoperands_empty()) {
496 assert(getPreInstrSymbol() &&((getPreInstrSymbol() && "Should never have only a single symbol allocated out-of-line!"
) ? static_cast<void> (0) : __assert_fail ("getPreInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 497, __PRETTY_FUNCTION__))
497 "Should never have only a single symbol allocated out-of-line!")((getPreInstrSymbol() && "Should never have only a single symbol allocated out-of-line!"
) ? static_cast<void> (0) : __assert_fail ("getPreInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 497, __PRETTY_FUNCTION__))
;
498 Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol());
499 return;
500 }
501
502 // Otherwise fallback on the generic update.
503 } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) {
504 // If we don't have any other extra info, we can store this inline.
505 Info.set<EIIK_PostInstrSymbol>(Symbol);
506 return;
507 }
508
509 // Otherwise, allocate a full new set of extra info.
510 // FIXME: Maybe we should make the symbols in the extra info mutable?
511 Info.set<EIIK_OutOfLine>(
512 MF.createMIExtraInfo(memoperands(), getPreInstrSymbol(), Symbol));
513}
514
515uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const {
516 // For now, the just return the union of the flags. If the flags get more
517 // complicated over time, we might need more logic here.
518 return getFlags() | Other.getFlags();
519}
520
521void MachineInstr::copyIRFlags(const Instruction &I) {
522 // Copy the wrapping flags.
523 if (const OverflowingBinaryOperator *OB =
524 dyn_cast<OverflowingBinaryOperator>(&I)) {
525 if (OB->hasNoSignedWrap())
526 setFlag(MachineInstr::MIFlag::NoSWrap);
527 if (OB->hasNoUnsignedWrap())
528 setFlag(MachineInstr::MIFlag::NoUWrap);
529 }
530
531 // Copy the exact flag.
532 if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I))
533 if (PE->isExact())
534 setFlag(MachineInstr::MIFlag::IsExact);
535
536 // Copy the fast-math flags.
537 if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) {
538 const FastMathFlags Flags = FP->getFastMathFlags();
539 if (Flags.noNaNs())
540 setFlag(MachineInstr::MIFlag::FmNoNans);
541 if (Flags.noInfs())
542 setFlag(MachineInstr::MIFlag::FmNoInfs);
543 if (Flags.noSignedZeros())
544 setFlag(MachineInstr::MIFlag::FmNsz);
545 if (Flags.allowReciprocal())
546 setFlag(MachineInstr::MIFlag::FmArcp);
547 if (Flags.allowContract())
548 setFlag(MachineInstr::MIFlag::FmContract);
549 if (Flags.approxFunc())
550 setFlag(MachineInstr::MIFlag::FmAfn);
551 if (Flags.allowReassoc())
552 setFlag(MachineInstr::MIFlag::FmReassoc);
553 }
554}
555
556bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const {
557 assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 557, __PRETTY_FUNCTION__))
;
558 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
559 if (MII->getDesc().getFlags() & Mask) {
560 if (Type == AnyInBundle)
561 return true;
562 } else {
563 if (Type == AllInBundle && !MII->isBundle())
564 return false;
565 }
566 // This was the last instruction in the bundle.
567 if (!MII->isBundledWithSucc())
568 return Type == AllInBundle;
569 }
570}
571
572bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
573 MICheckType Check) const {
574 // If opcodes or number of operands are not the same then the two
575 // instructions are obviously not identical.
576 if (Other.getOpcode() != getOpcode() ||
577 Other.getNumOperands() != getNumOperands())
578 return false;
579
580 if (isBundle()) {
581 // We have passed the test above that both instructions have the same
582 // opcode, so we know that both instructions are bundles here. Let's compare
583 // MIs inside the bundle.
584 assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles."
) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 584, __PRETTY_FUNCTION__))
;
585 MachineBasicBlock::const_instr_iterator I1 = getIterator();
586 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
587 // Loop until we analysed the last intruction inside at least one of the
588 // bundles.
589 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
590 ++I1;
591 ++I2;
592 if (!I1->isIdenticalTo(*I2, Check))
593 return false;
594 }
595 // If we've reached the end of just one of the two bundles, but not both,
596 // the instructions are not identical.
597 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
598 return false;
599 }
600
601 // Check operands to make sure they match.
602 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
603 const MachineOperand &MO = getOperand(i);
604 const MachineOperand &OMO = Other.getOperand(i);
605 if (!MO.isReg()) {
606 if (!MO.isIdenticalTo(OMO))
607 return false;
608 continue;
609 }
610
611 // Clients may or may not want to ignore defs when testing for equality.
612 // For example, machine CSE pass only cares about finding common
613 // subexpressions, so it's safe to ignore virtual register defs.
614 if (MO.isDef()) {
615 if (Check == IgnoreDefs)
616 continue;
617 else if (Check == IgnoreVRegDefs) {
618 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
619 !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
620 if (!MO.isIdenticalTo(OMO))
621 return false;
622 } else {
623 if (!MO.isIdenticalTo(OMO))
624 return false;
625 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
626 return false;
627 }
628 } else {
629 if (!MO.isIdenticalTo(OMO))
630 return false;
631 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
632 return false;
633 }
634 }
635 // If DebugLoc does not match then two debug instructions are not identical.
636 if (isDebugInstr())
637 if (getDebugLoc() && Other.getDebugLoc() &&
638 getDebugLoc() != Other.getDebugLoc())
639 return false;
640 return true;
641}
642
643const MachineFunction *MachineInstr::getMF() const {
644 return getParent()->getParent();
645}
646
647MachineInstr *MachineInstr::removeFromParent() {
648 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 648, __PRETTY_FUNCTION__))
;
649 return getParent()->remove(this);
650}
651
652MachineInstr *MachineInstr::removeFromBundle() {
653 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 653, __PRETTY_FUNCTION__))
;
654 return getParent()->remove_instr(this);
655}
656
657void MachineInstr::eraseFromParent() {
658 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 658, __PRETTY_FUNCTION__))
;
659 getParent()->erase(this);
660}
661
662void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
663 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 663, __PRETTY_FUNCTION__))
;
664 MachineBasicBlock *MBB = getParent();
665 MachineFunction *MF = MBB->getParent();
666 assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast<
void> (0) : __assert_fail ("MF && \"Not embedded in a function!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 666, __PRETTY_FUNCTION__))
;
667
668 MachineInstr *MI = (MachineInstr *)this;
669 MachineRegisterInfo &MRI = MF->getRegInfo();
670
671 for (const MachineOperand &MO : MI->operands()) {
672 if (!MO.isReg() || !MO.isDef())
673 continue;
674 unsigned Reg = MO.getReg();
675 if (!TargetRegisterInfo::isVirtualRegister(Reg))
676 continue;
677 MRI.markUsesInDebugValueAsUndef(Reg);
678 }
679 MI->eraseFromParent();
680}
681
682void MachineInstr::eraseFromBundle() {
683 assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast
<void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 683, __PRETTY_FUNCTION__))
;
684 getParent()->erase_instr(this);
685}
686
687unsigned MachineInstr::getNumExplicitOperands() const {
688 unsigned NumOperands = MCID->getNumOperands();
689 if (!MCID->isVariadic())
690 return NumOperands;
691
692 for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) {
693 const MachineOperand &MO = getOperand(I);
694 // The operands must always be in the following order:
695 // - explicit reg defs,
696 // - other explicit operands (reg uses, immediates, etc.),
697 // - implicit reg defs
698 // - implicit reg uses
699 if (MO.isReg() && MO.isImplicit())
700 break;
701 ++NumOperands;
702 }
703 return NumOperands;
704}
705
706unsigned MachineInstr::getNumExplicitDefs() const {
707 unsigned NumDefs = MCID->getNumDefs();
708 if (!MCID->isVariadic())
709 return NumDefs;
710
711 for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) {
712 const MachineOperand &MO = getOperand(I);
713 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
714 break;
715 ++NumDefs;
716 }
717 return NumDefs;
718}
719
720void MachineInstr::bundleWithPred() {
721 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 721, __PRETTY_FUNCTION__))
;
722 setFlag(BundledPred);
723 MachineBasicBlock::instr_iterator Pred = getIterator();
724 --Pred;
725 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 725, __PRETTY_FUNCTION__))
;
726 Pred->setFlag(BundledSucc);
727}
728
729void MachineInstr::bundleWithSucc() {
730 assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 730, __PRETTY_FUNCTION__))
;
731 setFlag(BundledSucc);
732 MachineBasicBlock::instr_iterator Succ = getIterator();
733 ++Succ;
734 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 734, __PRETTY_FUNCTION__))
;
735 Succ->setFlag(BundledPred);
736}
737
738void MachineInstr::unbundleFromPred() {
739 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 739, __PRETTY_FUNCTION__))
;
740 clearFlag(BundledPred);
741 MachineBasicBlock::instr_iterator Pred = getIterator();
742 --Pred;
743 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 743, __PRETTY_FUNCTION__))
;
744 Pred->clearFlag(BundledSucc);
745}
746
747void MachineInstr::unbundleFromSucc() {
748 assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor"
) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 748, __PRETTY_FUNCTION__))
;
749 clearFlag(BundledSucc);
750 MachineBasicBlock::instr_iterator Succ = getIterator();
751 ++Succ;
752 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags"
) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 752, __PRETTY_FUNCTION__))
;
753 Succ->clearFlag(BundledPred);
754}
755
756bool MachineInstr::isStackAligningInlineAsm() const {
757 if (isInlineAsm()) {
758 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
759 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
760 return true;
761 }
762 return false;
763}
764
765InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
766 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 766, __PRETTY_FUNCTION__))
;
767 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
768 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
769}
770
771int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
772 unsigned *GroupNo) const {
773 assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction"
) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 773, __PRETTY_FUNCTION__))
;
774 assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range"
) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 774, __PRETTY_FUNCTION__))
;
775
776 // Ignore queries about the initial operands.
777 if (OpIdx < InlineAsm::MIOp_FirstOperand)
778 return -1;
779
780 unsigned Group = 0;
781 unsigned NumOps;
782 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
783 i += NumOps) {
784 const MachineOperand &FlagMO = getOperand(i);
785 // If we reach the implicit register operands, stop looking.
786 if (!FlagMO.isImm())
787 return -1;
788 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
789 if (i + NumOps > OpIdx) {
790 if (GroupNo)
791 *GroupNo = Group;
792 return i;
793 }
794 ++Group;
795 }
796 return -1;
797}
798
799const DILabel *MachineInstr::getDebugLabel() const {
800 assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast<
void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 800, __PRETTY_FUNCTION__))
;
801 return cast<DILabel>(getOperand(0).getMetadata());
802}
803
804const DILocalVariable *MachineInstr::getDebugVariable() const {
805 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 805, __PRETTY_FUNCTION__))
;
806 return cast<DILocalVariable>(getOperand(2).getMetadata());
807}
808
809const DIExpression *MachineInstr::getDebugExpression() const {
810 assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast<
void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 810, __PRETTY_FUNCTION__))
;
811 return cast<DIExpression>(getOperand(3).getMetadata());
812}
813
814const TargetRegisterClass*
815MachineInstr::getRegClassConstraint(unsigned OpIdx,
816 const TargetInstrInfo *TII,
817 const TargetRegisterInfo *TRI) const {
818 assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!")
? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 818, __PRETTY_FUNCTION__))
;
819 assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast
<void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 819, __PRETTY_FUNCTION__))
;
820 const MachineFunction &MF = *getMF();
821
822 // Most opcodes have fixed constraints in their MCInstrDesc.
823 if (!isInlineAsm())
824 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
825
826 if (!getOperand(OpIdx).isReg())
827 return nullptr;
828
829 // For tied uses on inline asm, get the constraint from the def.
830 unsigned DefIdx;
831 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
832 OpIdx = DefIdx;
833
834 // Inline asm stores register class constraints in the flag word.
835 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
836 if (FlagIdx < 0)
837 return nullptr;
838
839 unsigned Flag = getOperand(FlagIdx).getImm();
840 unsigned RCID;
841 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
842 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
843 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
844 InlineAsm::hasRegClassConstraint(Flag, RCID))
845 return TRI->getRegClass(RCID);
846
847 // Assume that all registers in a memory operand are pointers.
848 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
849 return TRI->getPointerRegClass(MF);
850
851 return nullptr;
852}
853
854const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
855 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
856 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
857 // Check every operands inside the bundle if we have
858 // been asked to.
859 if (ExploreBundle)
860 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
861 ++OpndIt)
862 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
863 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
864 else
865 // Otherwise, just check the current operands.
866 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
867 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
868 return CurRC;
869}
870
871const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
872 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
873 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
874 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 874, __PRETTY_FUNCTION__))
;
875 // Check if Reg is constrained by some of its use/def from MI.
876 const MachineOperand &MO = getOperand(OpIdx);
877 if (!MO.isReg() || MO.getReg() != Reg)
878 return CurRC;
879 // If yes, accumulate the constraints through the operand.
880 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
881}
882
883const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
884 unsigned OpIdx, const TargetRegisterClass *CurRC,
885 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
886 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
887 const MachineOperand &MO = getOperand(OpIdx);
888 assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 889, __PRETTY_FUNCTION__))
889 "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand"
) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 889, __PRETTY_FUNCTION__))
;
890 assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast
<void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 890, __PRETTY_FUNCTION__))
;
891 if (unsigned SubIdx = MO.getSubReg()) {
892 if (OpRC)
893 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
894 else
895 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
896 } else if (OpRC)
897 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
898 return CurRC;
899}
900
901/// Return the number of instructions inside the MI bundle, not counting the
902/// header instruction.
903unsigned MachineInstr::getBundleSize() const {
904 MachineBasicBlock::const_instr_iterator I = getIterator();
905 unsigned Size = 0;
906 while (I->isBundledWithSucc()) {
907 ++Size;
908 ++I;
909 }
910 return Size;
911}
912
913/// Returns true if the MachineInstr has an implicit-use operand of exactly
914/// the given register (not considering sub/super-registers).
915bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
916 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
917 const MachineOperand &MO = getOperand(i);
918 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
919 return true;
920 }
921 return false;
922}
923
924/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
925/// the specific register or -1 if it is not found. It further tightens
926/// the search criteria to a use that kills the register if isKill is true.
927int MachineInstr::findRegisterUseOperandIdx(
928 unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
929 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
930 const MachineOperand &MO = getOperand(i);
931 if (!MO.isReg() || !MO.isUse())
932 continue;
933 unsigned MOReg = MO.getReg();
934 if (!MOReg)
935 continue;
936 if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
937 TargetRegisterInfo::isPhysicalRegister(Reg) &&
938 TRI->isSubRegister(MOReg, Reg)))
939 if (!isKill || MO.isKill())
940 return i;
941 }
942 return -1;
943}
944
945/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
946/// indicating if this instruction reads or writes Reg. This also considers
947/// partial defines.
948std::pair<bool,bool>
949MachineInstr::readsWritesVirtualRegister(unsigned Reg,
950 SmallVectorImpl<unsigned> *Ops) const {
951 bool PartDef = false; // Partial redefine.
952 bool FullDef = false; // Full define.
953 bool Use = false;
954
955 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
956 const MachineOperand &MO = getOperand(i);
957 if (!MO.isReg() || MO.getReg() != Reg)
958 continue;
959 if (Ops)
960 Ops->push_back(i);
961 if (MO.isUse())
962 Use |= !MO.isUndef();
963 else if (MO.getSubReg() && !MO.isUndef())
964 // A partial def undef doesn't count as reading the register.
965 PartDef = true;
966 else
967 FullDef = true;
968 }
969 // A partial redefine uses Reg unless there is also a full define.
970 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
971}
972
973/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
974/// the specified register or -1 if it is not found. If isDead is true, defs
975/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
976/// also checks if there is a def of a super-register.
977int
978MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
979 const TargetRegisterInfo *TRI) const {
980 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
981 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
982 const MachineOperand &MO = getOperand(i);
983 // Accept regmask operands when Overlap is set.
984 // Ignore them when looking for a specific def operand (Overlap == false).
985 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
986 return i;
987 if (!MO.isReg() || !MO.isDef())
988 continue;
989 unsigned MOReg = MO.getReg();
990 bool Found = (MOReg == Reg);
991 if (!Found && TRI && isPhys &&
992 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
993 if (Overlap)
994 Found = TRI->regsOverlap(MOReg, Reg);
995 else
996 Found = TRI->isSubRegister(MOReg, Reg);
997 }
998 if (Found && (!isDead || MO.isDead()))
999 return i;
1000 }
1001 return -1;
1002}
1003
1004/// findFirstPredOperandIdx() - Find the index of the first operand in the
1005/// operand list that is used to represent the predicate. It returns -1 if
1006/// none is found.
1007int MachineInstr::findFirstPredOperandIdx() const {
1008 // Don't call MCID.findFirstPredOperandIdx() because this variant
1009 // is sometimes called on an instruction that's not yet complete, and
1010 // so the number of operands is less than the MCID indicates. In
1011 // particular, the PTX target does this.
1012 const MCInstrDesc &MCID = getDesc();
1013 if (MCID.isPredicable()) {
1014 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1015 if (MCID.OpInfo[i].isPredicate())
1016 return i;
1017 }
1018
1019 return -1;
1020}
1021
1022// MachineOperand::TiedTo is 4 bits wide.
1023const unsigned TiedMax = 15;
1024
1025/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1026///
1027/// Use and def operands can be tied together, indicated by a non-zero TiedTo
1028/// field. TiedTo can have these values:
1029///
1030/// 0: Operand is not tied to anything.
1031/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1032/// TiedMax: Tied to an operand >= TiedMax-1.
1033///
1034/// The tied def must be one of the first TiedMax operands on a normal
1035/// instruction. INLINEASM instructions allow more tied defs.
1036///
1037void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1038 MachineOperand &DefMO = getOperand(DefIdx);
1039 MachineOperand &UseMO = getOperand(UseIdx);
1040 assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast
<void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1040, __PRETTY_FUNCTION__))
;
1041 assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast
<void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1041, __PRETTY_FUNCTION__))
;
1042 assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use"
) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1042, __PRETTY_FUNCTION__))
;
1043 assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def"
) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1043, __PRETTY_FUNCTION__))
;
1044
1045 if (DefIdx < TiedMax)
1046 UseMO.TiedTo = DefIdx + 1;
1047 else {
1048 // Inline asm can use the group descriptors to find tied operands, but on
1049 // normal instruction, the tied def must be within the first TiedMax
1050 // operands.
1051 assert(isInlineAsm() && "DefIdx out of range")((isInlineAsm() && "DefIdx out of range") ? static_cast
<void> (0) : __assert_fail ("isInlineAsm() && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1051, __PRETTY_FUNCTION__))
;
1052 UseMO.TiedTo = TiedMax;
1053 }
1054
1055 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1056 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1057}
1058
1059/// Given the index of a tied register operand, find the operand it is tied to.
1060/// Defs are tied to uses and vice versa. Returns the index of the tied operand
1061/// which must exist.
1062unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1063 const MachineOperand &MO = getOperand(OpIdx);
1064 assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast<
void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1064, __PRETTY_FUNCTION__))
;
1065
1066 // Normally TiedTo is in range.
1067 if (MO.TiedTo < TiedMax)
1068 return MO.TiedTo - 1;
1069
1070 // Uses on normal instructions can be out of range.
1071 if (!isInlineAsm()) {
1072 // Normal tied defs must be in the 0..TiedMax-1 range.
1073 if (MO.isUse())
1074 return TiedMax - 1;
1075 // MO is a def. Search for the tied use.
1076 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1077 const MachineOperand &UseMO = getOperand(i);
1078 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1079 return i;
1080 }
1081 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1081)
;
1082 }
1083
1084 // Now deal with inline asm by parsing the operand group descriptor flags.
1085 // Find the beginning of each operand group.
1086 SmallVector<unsigned, 8> GroupIdx;
1087 unsigned OpIdxGroup = ~0u;
1088 unsigned NumOps;
1089 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1090 i += NumOps) {
1091 const MachineOperand &FlagMO = getOperand(i);
1092 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1092, __PRETTY_FUNCTION__))
;
1093 unsigned CurGroup = GroupIdx.size();
1094 GroupIdx.push_back(i);
1095 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1096 // OpIdx belongs to this operand group.
1097 if (OpIdx > i && OpIdx < i + NumOps)
1098 OpIdxGroup = CurGroup;
1099 unsigned TiedGroup;
1100 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1101 continue;
1102 // Operands in this group are tied to operands in TiedGroup which must be
1103 // earlier. Find the number of operands between the two groups.
1104 unsigned Delta = i - GroupIdx[TiedGroup];
1105
1106 // OpIdx is a use tied to TiedGroup.
1107 if (OpIdxGroup == CurGroup)
1108 return OpIdx - Delta;
1109
1110 // OpIdx is a def tied to this use group.
1111 if (OpIdxGroup == TiedGroup)
1112 return OpIdx + Delta;
1113 }
1114 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1114)
;
1115}
1116
1117/// clearKillInfo - Clears kill flags on all operands.
1118///
1119void MachineInstr::clearKillInfo() {
1120 for (MachineOperand &MO : operands()) {
1121 if (MO.isReg() && MO.isUse())
1122 MO.setIsKill(false);
1123 }
1124}
1125
1126void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
1127 unsigned SubIdx,
1128 const TargetRegisterInfo &RegInfo) {
1129 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1130 if (SubIdx)
1131 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1132 for (MachineOperand &MO : operands()) {
1133 if (!MO.isReg() || MO.getReg() != FromReg)
1134 continue;
1135 MO.substPhysReg(ToReg, RegInfo);
1136 }
1137 } else {
1138 for (MachineOperand &MO : operands()) {
1139 if (!MO.isReg() || MO.getReg() != FromReg)
1140 continue;
1141 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1142 }
1143 }
1144}
1145
1146/// isSafeToMove - Return true if it is safe to move this instruction. If
1147/// SawStore is set to true, it means that there is a store (or call) between
1148/// the instruction's location and its intended destination.
1149bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1150 // Ignore stuff that we obviously can't move.
1151 //
1152 // Treat volatile loads as stores. This is not strictly necessary for
1153 // volatiles, but it is required for atomic loads. It is not allowed to move
1154 // a load across an atomic load with Ordering > Monotonic.
1155 if (mayStore() || isCall() || isPHI() ||
1156 (mayLoad() && hasOrderedMemoryRef())) {
1157 SawStore = true;
1158 return false;
1159 }
1160
1161 if (isPosition() || isDebugInstr() || isTerminator() ||
1162 hasUnmodeledSideEffects())
1163 return false;
1164
1165 // See if this instruction does a load. If so, we have to guarantee that the
1166 // loaded value doesn't change between the load and the its intended
1167 // destination. The check for isInvariantLoad gives the targe the chance to
1168 // classify the load as always returning a constant, e.g. a constant pool
1169 // load.
1170 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
1171 // Otherwise, this is a real load. If there is a store between the load and
1172 // end of block, we can't move it.
1173 return !SawStore;
1174
1175 return true;
1176}
1177
1178bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
1179 bool UseTBAA) {
1180 const MachineFunction *MF = getMF();
1181 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
1182 const MachineFrameInfo &MFI = MF->getFrameInfo();
1183
1184 // If neither instruction stores to memory, they can't alias in any
1185 // meaningful way, even if they read from the same address.
1186 if (!mayStore() && !Other.mayStore())
1187 return false;
1188
1189 // Let the target decide if memory accesses cannot possibly overlap.
1190 if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1191 return false;
1192
1193 // FIXME: Need to handle multiple memory operands to support all targets.
1194 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1195 return true;
1196
1197 MachineMemOperand *MMOa = *memoperands_begin();
1198 MachineMemOperand *MMOb = *Other.memoperands_begin();
1199
1200 // The following interface to AA is fashioned after DAGCombiner::isAlias
1201 // and operates with MachineMemOperand offset with some important
1202 // assumptions:
1203 // - LLVM fundamentally assumes flat address spaces.
1204 // - MachineOperand offset can *only* result from legalization and
1205 // cannot affect queries other than the trivial case of overlap
1206 // checking.
1207 // - These offsets never wrap and never step outside
1208 // of allocated objects.
1209 // - There should never be any negative offsets here.
1210 //
1211 // FIXME: Modify API to hide this math from "user"
1212 // Even before we go to AA we can reason locally about some
1213 // memory objects. It can save compile time, and possibly catch some
1214 // corner cases not currently covered.
1215
1216 int64_t OffsetA = MMOa->getOffset();
1217 int64_t OffsetB = MMOb->getOffset();
1218 int64_t MinOffset = std::min(OffsetA, OffsetB);
1219
1220 uint64_t WidthA = MMOa->getSize();
1221 uint64_t WidthB = MMOb->getSize();
1222 bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
1223 bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
1224
1225 const Value *ValA = MMOa->getValue();
1226 const Value *ValB = MMOb->getValue();
1227 bool SameVal = (ValA && ValB && (ValA == ValB));
1228 if (!SameVal) {
1229 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1230 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1231 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1232 return false;
1233 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1234 return false;
1235 if (PSVa && PSVb && (PSVa == PSVb))
1236 SameVal = true;
1237 }
1238
1239 if (SameVal) {
1240 if (!KnownWidthA || !KnownWidthB)
1241 return true;
1242 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1243 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1244 return (MinOffset + LowWidth > MaxOffset);
1245 }
1246
1247 if (!AA)
1248 return true;
1249
1250 if (!ValA || !ValB)
1251 return true;
1252
1253 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1253, __PRETTY_FUNCTION__))
;
1254 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1254, __PRETTY_FUNCTION__))
;
1255
1256 int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
1257 : MemoryLocation::UnknownSize;
1258 int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
1259 : MemoryLocation::UnknownSize;
1260
1261 AliasResult AAResult = AA->alias(
1262 MemoryLocation(ValA, OverlapA,
1263 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1264 MemoryLocation(ValB, OverlapB,
1265 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1266
1267 return (AAResult != NoAlias);
1268}
1269
1270/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1271/// or volatile memory reference, or if the information describing the memory
1272/// reference is not available. Return false if it is known to have no ordered
1273/// memory references.
1274bool MachineInstr::hasOrderedMemoryRef() const {
1275 // An instruction known never to access memory won't have a volatile access.
1276 if (!mayStore() &&
1277 !mayLoad() &&
1278 !isCall() &&
1279 !hasUnmodeledSideEffects())
1280 return false;
1281
1282 // Otherwise, if the instruction has no memory reference information,
1283 // conservatively assume it wasn't preserved.
1284 if (memoperands_empty())
1285 return true;
1286
1287 // Check if any of our memory operands are ordered.
1288 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1289 return !MMO->isUnordered();
1290 });
1291}
1292
1293/// isDereferenceableInvariantLoad - Return true if this instruction will never
1294/// trap and is loading from a location whose value is invariant across a run of
1295/// this function.
1296bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
1297 // If the instruction doesn't load at all, it isn't an invariant load.
1298 if (!mayLoad())
1299 return false;
1300
1301 // If the instruction has lost its memoperands, conservatively assume that
1302 // it may not be an invariant load.
1303 if (memoperands_empty())
1304 return false;
1305
1306 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1307
1308 for (MachineMemOperand *MMO : memoperands()) {
1309 if (MMO->isVolatile()) return false;
1310 if (MMO->isStore()) return false;
1311 if (MMO->isInvariant() && MMO->isDereferenceable())
1312 continue;
1313
1314 // A load from a constant PseudoSourceValue is invariant.
1315 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1316 if (PSV->isConstant(&MFI))
1317 continue;
1318
1319 if (const Value *V = MMO->getValue()) {
1320 // If we have an AliasAnalysis, ask it whether the memory is constant.
1321 if (AA &&
1322 AA->pointsToConstantMemory(
1323 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1324 continue;
1325 }
1326
1327 // Otherwise assume conservatively.
1328 return false;
1329 }
1330
1331 // Everything checks out.
1332 return true;
1333}
1334
1335/// isConstantValuePHI - If the specified instruction is a PHI that always
1336/// merges together the same virtual register, return the register, otherwise
1337/// return 0.
1338unsigned MachineInstr::isConstantValuePHI() const {
1339 if (!isPHI())
1340 return 0;
1341 assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1342, __PRETTY_FUNCTION__))
1342 "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1342, __PRETTY_FUNCTION__))
;
1343
1344 unsigned Reg = getOperand(1).getReg();
1345 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1346 if (getOperand(i).getReg() != Reg)
1347 return 0;
1348 return Reg;
1349}
1350
1351bool MachineInstr::hasUnmodeledSideEffects() const {
1352 if (hasProperty(MCID::UnmodeledSideEffects))
1353 return true;
1354 if (isInlineAsm()) {
1355 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1356 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1357 return true;
1358 }
1359
1360 return false;
1361}
1362
1363bool MachineInstr::isLoadFoldBarrier() const {
1364 return mayStore() || isCall() || hasUnmodeledSideEffects();
1365}
1366
1367/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1368///
1369bool MachineInstr::allDefsAreDead() const {
1370 for (const MachineOperand &MO : operands()) {
1371 if (!MO.isReg() || MO.isUse())
1372 continue;
1373 if (!MO.isDead())
1374 return false;
1375 }
1376 return true;
1377}
1378
1379/// copyImplicitOps - Copy implicit register operands from specified
1380/// instruction to this instruction.
1381void MachineInstr::copyImplicitOps(MachineFunction &MF,
1382 const MachineInstr &MI) {
1383 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1384 i != e; ++i) {
1385 const MachineOperand &MO = MI.getOperand(i);
1386 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1387 addOperand(MF, MO);
1388 }
1389}
1390
1391bool MachineInstr::hasComplexRegisterTies() const {
1392 const MCInstrDesc &MCID = getDesc();
1393 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1394 const auto &Operand = getOperand(I);
1395 if (!Operand.isReg() || Operand.isDef())
1396 // Ignore the defined registers as MCID marks only the uses as tied.
1397 continue;
1398 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1399 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1400 if (ExpectedTiedIdx != TiedIdx)
1401 return true;
1402 }
1403 return false;
1404}
1405
1406LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1407 const MachineRegisterInfo &MRI) const {
1408 const MachineOperand &Op = getOperand(OpIdx);
1409 if (!Op.isReg())
1410 return LLT{};
1411
1412 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1413 return MRI.getType(Op.getReg());
1414
1415 auto &OpInfo = getDesc().OpInfo[OpIdx];
1416 if (!OpInfo.isGenericType())
1417 return MRI.getType(Op.getReg());
1418
1419 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1420 return LLT{};
1421
1422 LLT TypeToPrint = MRI.getType(Op.getReg());
1423 // Don't mark the type index printed if it wasn't actually printed: maybe
1424 // another operand with the same type index has an actual type attached:
1425 if (TypeToPrint.isValid())
1426 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1427 return TypeToPrint;
1428}
1429
1430#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1431LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1432 dbgs() << " ";
1433 print(dbgs());
1434}
1435#endif
1436
1437void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1438 bool SkipDebugLoc, bool AddNewLine,
1439 const TargetInstrInfo *TII) const {
1440 const Module *M = nullptr;
1441 const Function *F = nullptr;
1442 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1443 F = &MF->getFunction();
1444 M = F->getParent();
1445 if (!TII)
1446 TII = MF->getSubtarget().getInstrInfo();
1447 }
1448
1449 ModuleSlotTracker MST(M);
1450 if (F)
1451 MST.incorporateFunction(*F);
1452 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1453}
1454
1455void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1456 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1457 bool AddNewLine, const TargetInstrInfo *TII) const {
1458 // We can be a bit tidier if we know the MachineFunction.
1459 const MachineFunction *MF = nullptr;
1460 const TargetRegisterInfo *TRI = nullptr;
1461 const MachineRegisterInfo *MRI = nullptr;
1462 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1463 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1464
1465 if (isCFIInstruction())
1466 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1466, __PRETTY_FUNCTION__))
;
1467
1468 SmallBitVector PrintedTypes(8);
1469 bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies();
1470 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1471 if (!ShouldPrintRegisterTies)
1472 return 0U;
1473 const MachineOperand &MO = getOperand(OpIdx);
1474 if (MO.isReg() && MO.isTied() && !MO.isDef())
1475 return findTiedOperandIdx(OpIdx);
1476 return 0U;
1477 };
1478 unsigned StartOp = 0;
1479 unsigned e = getNumOperands();
1480
1481 // Print explicitly defined operands on the left of an assignment syntax.
1482 while (StartOp < e) {
1483 const MachineOperand &MO = getOperand(StartOp);
1484 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1485 break;
1486
1487 if (StartOp != 0)
1488 OS << ", ";
1489
1490 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1491 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1492 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1493 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1494 ++StartOp;
1495 }
1496
1497 if (StartOp != 0)
1498 OS << " = ";
1499
1500 if (getFlag(MachineInstr::FrameSetup))
1501 OS << "frame-setup ";
1502 if (getFlag(MachineInstr::FrameDestroy))
1503 OS << "frame-destroy ";
1504 if (getFlag(MachineInstr::FmNoNans))
1505 OS << "nnan ";
1506 if (getFlag(MachineInstr::FmNoInfs))
1507 OS << "ninf ";
1508 if (getFlag(MachineInstr::FmNsz))
1509 OS << "nsz ";
1510 if (getFlag(MachineInstr::FmArcp))
1511 OS << "arcp ";
1512 if (getFlag(MachineInstr::FmContract))
1513 OS << "contract ";
1514 if (getFlag(MachineInstr::FmAfn))
1515 OS << "afn ";
1516 if (getFlag(MachineInstr::FmReassoc))
1517 OS << "reassoc ";
1518 if (getFlag(MachineInstr::NoUWrap))
1519 OS << "nuw ";
1520 if (getFlag(MachineInstr::NoSWrap))
1521 OS << "nsw ";
1522 if (getFlag(MachineInstr::IsExact))
1523 OS << "exact ";
1524
1525 // Print the opcode name.
1526 if (TII)
1527 OS << TII->getName(getOpcode());
1528 else
1529 OS << "UNKNOWN";
1530
1531 if (SkipOpers)
1532 return;
1533
1534 // Print the rest of the operands.
1535 bool FirstOp = true;
1536 unsigned AsmDescOp = ~0u;
1537 unsigned AsmOpCount = 0;
1538
1539 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1540 // Print asm string.
1541 OS << " ";
1542 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1543 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1544 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1545 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1546 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1547 IntrinsicInfo);
1548
1549 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1550 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1551 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1552 OS << " [sideeffect]";
1553 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1554 OS << " [mayload]";
1555 if (ExtraInfo & InlineAsm::Extra_MayStore)
1556 OS << " [maystore]";
1557 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1558 OS << " [isconvergent]";
1559 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1560 OS << " [alignstack]";
1561 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1562 OS << " [attdialect]";
1563 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1564 OS << " [inteldialect]";
1565
1566 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1567 FirstOp = false;
1568 }
1569
1570 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1571 const MachineOperand &MO = getOperand(i);
1572
1573 if (FirstOp) FirstOp = false; else OS << ",";
1574 OS << " ";
1575
1576 if (isDebugValue() && MO.isMetadata()) {
1577 // Pretty print DBG_VALUE instructions.
1578 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1579 if (DIV && !DIV->getName().empty())
1580 OS << "!\"" << DIV->getName() << '\"';
1581 else {
1582 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1583 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1584 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1585 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1586 }
1587 } else if (isDebugLabel() && MO.isMetadata()) {
1588 // Pretty print DBG_LABEL instructions.
1589 auto *DIL = dyn_cast<DILabel>(MO.getMetadata());
1590 if (DIL && !DIL->getName().empty())
1591 OS << "\"" << DIL->getName() << '\"';
1592 else {
1593 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1594 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1595 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1596 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1597 }
1598 } else if (i == AsmDescOp && MO.isImm()) {
1599 // Pretty print the inline asm operand descriptor.
1600 OS << '$' << AsmOpCount++;
1601 unsigned Flag = MO.getImm();
1602 switch (InlineAsm::getKind(Flag)) {
1603 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1604 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1605 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1606 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1607 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1608 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1609 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1610 }
1611
1612 unsigned RCID = 0;
1613 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1614 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1615 if (TRI) {
1616 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1617 } else
1618 OS << ":RC" << RCID;
1619 }
1620
1621 if (InlineAsm::isMemKind(Flag)) {
1622 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1623 switch (MCID) {
1624 case InlineAsm::Constraint_es: OS << ":es"; break;
1625 case InlineAsm::Constraint_i: OS << ":i"; break;
1626 case InlineAsm::Constraint_m: OS << ":m"; break;
1627 case InlineAsm::Constraint_o: OS << ":o"; break;
1628 case InlineAsm::Constraint_v: OS << ":v"; break;
1629 case InlineAsm::Constraint_Q: OS << ":Q"; break;
1630 case InlineAsm::Constraint_R: OS << ":R"; break;
1631 case InlineAsm::Constraint_S: OS << ":S"; break;
1632 case InlineAsm::Constraint_T: OS << ":T"; break;
1633 case InlineAsm::Constraint_Um: OS << ":Um"; break;
1634 case InlineAsm::Constraint_Un: OS << ":Un"; break;
1635 case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1636 case InlineAsm::Constraint_Us: OS << ":Us"; break;
1637 case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1638 case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1639 case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1640 case InlineAsm::Constraint_X: OS << ":X"; break;
1641 case InlineAsm::Constraint_Z: OS << ":Z"; break;
1642 case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1643 case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1644 default: OS << ":?"; break;
1645 }
1646 }
1647
1648 unsigned TiedTo = 0;
1649 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1650 OS << " tiedto:$" << TiedTo;
1651
1652 OS << ']';
1653
1654 // Compute the index of the next operand descriptor.
1655 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1656 } else {
1657 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1658 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1659 if (MO.isImm() && isOperandSubregIdx(i))
1660 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1661 else
1662 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1663 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1664 }
1665 }
1666
1667 // Print any optional symbols attached to this instruction as-if they were
1668 // operands.
1669 if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
1670 if (!FirstOp) {
1671 FirstOp = false;
1672 OS << ',';
1673 }
1674 OS << " pre-instr-symbol ";
1675 MachineOperand::printSymbol(OS, *PreInstrSymbol);
1676 }
1677 if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
1678 if (!FirstOp) {
1679 FirstOp = false;
1680 OS << ',';
1681 }
1682 OS << " post-instr-symbol ";
1683 MachineOperand::printSymbol(OS, *PostInstrSymbol);
1684 }
1685
1686 if (!SkipDebugLoc) {
1687 if (const DebugLoc &DL = getDebugLoc()) {
1688 if (!FirstOp)
1689 OS << ',';
1690 OS << " debug-location ";
1691 DL->printAsOperand(OS, MST);
1692 }
1693 }
1694
1695 if (!memoperands_empty()) {
1696 SmallVector<StringRef, 0> SSNs;
1697 const LLVMContext *Context = nullptr;
1698 std::unique_ptr<LLVMContext> CtxPtr;
1699 const MachineFrameInfo *MFI = nullptr;
1700 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1701 MFI = &MF->getFrameInfo();
1702 Context = &MF->getFunction().getContext();
1703 } else {
1704 CtxPtr = llvm::make_unique<LLVMContext>();
1705 Context = CtxPtr.get();
1706 }
1707
1708 OS << " :: ";
1709 bool NeedComma = false;
1710 for (const MachineMemOperand *Op : memoperands()) {
1711 if (NeedComma)
1712 OS << ", ";
1713 Op->print(OS, MST, SSNs, *Context, MFI, TII);
1714 NeedComma = true;
1715 }
1716 }
1717
1718 if (SkipDebugLoc)
1719 return;
1720
1721 bool HaveSemi = false;
1722
1723 // Print debug location information.
1724 if (const DebugLoc &DL = getDebugLoc()) {
1725 if (!HaveSemi) {
1726 OS << ';';
1727 HaveSemi = true;
1728 }
1729 OS << ' ';
1730 DL.print(OS);
1731 }
1732
1733 // Print extra comments for DEBUG_VALUE.
1734 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1735 if (!HaveSemi) {
1736 OS << ";";
1737 HaveSemi = true;
1738 }
1739 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1740 OS << " line no:" << DV->getLine();
1741 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1742 DebugLoc InlinedAtDL(InlinedAt);
1743 if (InlinedAtDL && MF) {
1744 OS << " inlined @[ ";
1745 InlinedAtDL.print(OS);
1746 OS << " ]";
1747 }
1748 }
1749 if (isIndirectDebugValue())
1750 OS << " indirect";
1751 }
1752 // TODO: DBG_LABEL
1753
1754 if (AddNewLine)
1755 OS << '\n';
1756}
1757
1758bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1759 const TargetRegisterInfo *RegInfo,
1760 bool AddIfNotFound) {
1761 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1762 bool hasAliases = isPhysReg &&
1763 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1764 bool Found = false;
1765 SmallVector<unsigned,4> DeadOps;
1766 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1767 MachineOperand &MO = getOperand(i);
1768 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1769 continue;
1770
1771 // DEBUG_VALUE nodes do not contribute to code generation and should
1772 // always be ignored. Failure to do so may result in trying to modify
1773 // KILL flags on DEBUG_VALUE nodes.
1774 if (MO.isDebug())
1775 continue;
1776
1777 unsigned Reg = MO.getReg();
1778 if (!Reg)
1779 continue;
1780
1781 if (Reg == IncomingReg) {
1782 if (!Found) {
1783 if (MO.isKill())
1784 // The register is already marked kill.
1785 return true;
1786 if (isPhysReg && isRegTiedToDefOperand(i))
1787 // Two-address uses of physregs must not be marked kill.
1788 return true;
1789 MO.setIsKill();
1790 Found = true;
1791 }
1792 } else if (hasAliases && MO.isKill() &&
1793 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1794 // A super-register kill already exists.
1795 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1796 return true;
1797 if (RegInfo->isSubRegister(IncomingReg, Reg))
1798 DeadOps.push_back(i);
1799 }
1800 }
1801
1802 // Trim unneeded kill operands.
1803 while (!DeadOps.empty()) {
1804 unsigned OpIdx = DeadOps.back();
1805 if (getOperand(OpIdx).isImplicit() &&
1806 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1807 RemoveOperand(OpIdx);
1808 else
1809 getOperand(OpIdx).setIsKill(false);
1810 DeadOps.pop_back();
1811 }
1812
1813 // If not found, this means an alias of one of the operands is killed. Add a
1814 // new implicit operand if required.
1815 if (!Found && AddIfNotFound) {
1816 addOperand(MachineOperand::CreateReg(IncomingReg,
1817 false /*IsDef*/,
1818 true /*IsImp*/,
1819 true /*IsKill*/));
1820 return true;
1821 }
1822 return Found;
1823}
1824
1825void MachineInstr::clearRegisterKills(unsigned Reg,
1826 const TargetRegisterInfo *RegInfo) {
1827 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1828 RegInfo = nullptr;
1829 for (MachineOperand &MO : operands()) {
1830 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1831 continue;
1832 unsigned OpReg = MO.getReg();
1833 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1834 MO.setIsKill(false);
1835 }
1836}
1837
1838bool MachineInstr::addRegisterDead(unsigned Reg,
1839 const TargetRegisterInfo *RegInfo,
1840 bool AddIfNotFound) {
1841 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1842 bool hasAliases = isPhysReg &&
1843 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1844 bool Found = false;
1845 SmallVector<unsigned,4> DeadOps;
1846 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1847 MachineOperand &MO = getOperand(i);
1848 if (!MO.isReg() || !MO.isDef())
1849 continue;
1850 unsigned MOReg = MO.getReg();
1851 if (!MOReg)
1852 continue;
1853
1854 if (MOReg == Reg) {
1855 MO.setIsDead();
1856 Found = true;
1857 } else if (hasAliases && MO.isDead() &&
1858 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1859 // There exists a super-register that's marked dead.
1860 if (RegInfo->isSuperRegister(Reg, MOReg))
1861 return true;
1862 if (RegInfo->isSubRegister(Reg, MOReg))
1863 DeadOps.push_back(i);
1864 }
1865 }
1866
1867 // Trim unneeded dead operands.
1868 while (!DeadOps.empty()) {
1869 unsigned OpIdx = DeadOps.back();
1870 if (getOperand(OpIdx).isImplicit() &&
1871 (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0))
1872 RemoveOperand(OpIdx);
1873 else
1874 getOperand(OpIdx).setIsDead(false);
1875 DeadOps.pop_back();
1876 }
1877
1878 // If not found, this means an alias of one of the operands is dead. Add a
1879 // new implicit operand if required.
1880 if (Found || !AddIfNotFound)
1881 return Found;
1882
1883 addOperand(MachineOperand::CreateReg(Reg,
1884 true /*IsDef*/,
1885 true /*IsImp*/,
1886 false /*IsKill*/,
1887 true /*IsDead*/));
1888 return true;
1889}
1890
1891void MachineInstr::clearRegisterDeads(unsigned Reg) {
1892 for (MachineOperand &MO : operands()) {
1893 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1894 continue;
1895 MO.setIsDead(false);
1896 }
1897}
1898
1899void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1900 for (MachineOperand &MO : operands()) {
1901 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1902 continue;
1903 MO.setIsUndef(IsUndef);
1904 }
1905}
1906
1907void MachineInstr::addRegisterDefined(unsigned Reg,
1908 const TargetRegisterInfo *RegInfo) {
1909 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1910 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1911 if (MO)
1912 return;
1913 } else {
1914 for (const MachineOperand &MO : operands()) {
1915 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1916 MO.getSubReg() == 0)
1917 return;
1918 }
1919 }
1920 addOperand(MachineOperand::CreateReg(Reg,
1921 true /*IsDef*/,
1922 true /*IsImp*/));
1923}
1924
1925void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1926 const TargetRegisterInfo &TRI) {
1927 bool HasRegMask = false;
1928 for (MachineOperand &MO : operands()) {
1929 if (MO.isRegMask()) {
1930 HasRegMask = true;
1931 continue;
1932 }
1933 if (!MO.isReg() || !MO.isDef()) continue;
1934 unsigned Reg = MO.getReg();
1935 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1936 // If there are no uses, including partial uses, the def is dead.
1937 if (llvm::none_of(UsedRegs,
1938 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1939 MO.setIsDead();
1940 }
1941
1942 // This is a call with a register mask operand.
1943 // Mask clobbers are always dead, so add defs for the non-dead defines.
1944 if (HasRegMask)
1945 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1946 I != E; ++I)
1947 addRegisterDefined(*I, &TRI);
1948}
1949
1950unsigned
1951MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1952 // Build up a buffer of hash code components.
1953 SmallVector<size_t, 8> HashComponents;
1954 HashComponents.reserve(MI->getNumOperands() + 1);
1955 HashComponents.push_back(MI->getOpcode());
1956 for (const MachineOperand &MO : MI->operands()) {
1957 if (MO.isReg() && MO.isDef() &&
1958 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1959 continue; // Skip virtual register defs.
1960
1961 HashComponents.push_back(hash_value(MO));
1962 }
1963 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1964}
1965
1966void MachineInstr::emitError(StringRef Msg) const {
1967 // Find the source location cookie.
1968 unsigned LocCookie = 0;
1969 const MDNode *LocMD = nullptr;
1970 for (unsigned i = getNumOperands(); i != 0; --i) {
1971 if (getOperand(i-1).isMetadata() &&
1972 (LocMD = getOperand(i-1).getMetadata()) &&
1973 LocMD->getNumOperands() != 0) {
1974 if (const ConstantInt *CI =
1975 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1976 LocCookie = CI->getZExtValue();
1977 break;
1978 }
1979 }
1980 }
1981
1982 if (const MachineBasicBlock *MBB = getParent())
1983 if (const MachineFunction *MF = MBB->getParent())
1984 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1985 report_fatal_error(Msg);
1986}
1987
1988MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
1989 const MCInstrDesc &MCID, bool IsIndirect,
1990 unsigned Reg, const MDNode *Variable,
1991 const MDNode *Expr) {
1992 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1992, __PRETTY_FUNCTION__))
;
1993 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1993, __PRETTY_FUNCTION__))
;
1994 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1995, __PRETTY_FUNCTION__))
1995 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 1995, __PRETTY_FUNCTION__))
;
1996 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
1997 if (IsIndirect)
1998 MIB.addImm(0U);
1999 else
2000 MIB.addReg(0U, RegState::Debug);
2001 return MIB.addMetadata(Variable).addMetadata(Expr);
2002}
2003
2004MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2005 const MCInstrDesc &MCID, bool IsIndirect,
2006 MachineOperand &MO, const MDNode *Variable,
2007 const MDNode *Expr) {
2008 assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable"
) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2008, __PRETTY_FUNCTION__))
;
2009 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression"
) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2009, __PRETTY_FUNCTION__))
;
2010 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2011, __PRETTY_FUNCTION__))
2011 "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic
(DL) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2011, __PRETTY_FUNCTION__))
;
2012 if (MO.isReg())
2013 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2014
2015 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2016 if (IsIndirect)
2017 MIB.addImm(0U);
2018 else
2019 MIB.addReg(0U, RegState::Debug);
2020 return MIB.addMetadata(Variable).addMetadata(Expr);
2021 }
2022
2023MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2024 MachineBasicBlock::iterator I,
2025 const DebugLoc &DL, const MCInstrDesc &MCID,
2026 bool IsIndirect, unsigned Reg,
2027 const MDNode *Variable, const MDNode *Expr) {
2028 MachineFunction &MF = *BB.getParent();
2029 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
2030 BB.insert(I, MI);
2031 return MachineInstrBuilder(MF, MI);
2032}
2033
2034MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2035 MachineBasicBlock::iterator I,
2036 const DebugLoc &DL, const MCInstrDesc &MCID,
2037 bool IsIndirect, MachineOperand &MO,
2038 const MDNode *Variable, const MDNode *Expr) {
2039 MachineFunction &MF = *BB.getParent();
2040 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
2041 BB.insert(I, MI);
2042 return MachineInstrBuilder(MF, *MI);
2043}
2044
2045/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
2046/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
2047static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
2048 assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2048, __PRETTY_FUNCTION__))
;
2049 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2050, __PRETTY_FUNCTION__))
2050 "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc
()) && "Expected inlined-at fields to agree") ? static_cast
<void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2050, __PRETTY_FUNCTION__))
;
2051
2052 const DIExpression *Expr = MI.getDebugExpression();
2053 if (MI.isIndirectDebugValue()) {
2054 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset")((MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset"
) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(1).getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-8~svn345461/lib/CodeGen/MachineInstr.cpp"
, 2054, __PRETTY_FUNCTION__))
;
2055 Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
2056 }
2057 return Expr;
2058}
2059
2060MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
2061 MachineBasicBlock::iterator I,
2062 const MachineInstr &Orig,
2063 int FrameIndex) {
2064 const DIExpression *Expr = computeExprForSpill(Orig);
2065 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
1
Calling 'MachineInstrBuilder::addFrameIndex'
2066 .addFrameIndex(FrameIndex)
2067 .addImm(0U)
2068 .addMetadata(Orig.getDebugVariable())
2069 .addMetadata(Expr);
2070}
2071
2072void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
2073 const DIExpression *Expr = computeExprForSpill(Orig);
2074 Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
2075 Orig.getOperand(1).ChangeToImmediate(0U);
2076 Orig.getOperand(3).setMetadata(Expr);
2077}
2078
2079void MachineInstr::collectDebugValues(
2080 SmallVectorImpl<MachineInstr *> &DbgValues) {
2081 MachineInstr &MI = *this;
2082 if (!MI.getOperand(0).isReg())
2083 return;
2084
2085 MachineBasicBlock::iterator DI = MI; ++DI;
2086 for (MachineBasicBlock::iterator DE = MI.getParent()->end();
2087 DI != DE; ++DI) {
2088 if (!DI->isDebugValue())
2089 return;
2090 if (DI->getOperand(0).isReg() &&
2091 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2092 DbgValues.push_back(&*DI);
2093 }
2094}
2095
2096void MachineInstr::changeDebugValuesDefReg(unsigned Reg) {
2097 // Collect matching debug values.
2098 SmallVector<MachineInstr *, 2> DbgValues;
2099 collectDebugValues(DbgValues);
2100
2101 // Propagate Reg to debug value instructions.
2102 for (auto *DBI : DbgValues)
2103 DBI->getOperand(0).setReg(Reg);
2104}

/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h

1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file exposes a function named BuildMI, which is useful for dramatically
11// simplifying how MachineInstr's are created. It allows use of code like this:
12//
13// M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
14// .addReg(argVal1)
15// .addReg(argVal2);
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
21
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/CodeGen/GlobalISel/Utils.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/Support/ErrorHandling.h"
33#include <cassert>
34#include <cstdint>
35#include <utility>
36
37namespace llvm {
38
39class MCInstrDesc;
40class MDNode;
41
42namespace RegState {
43
44 enum {
45 Define = 0x2,
46 Implicit = 0x4,
47 Kill = 0x8,
48 Dead = 0x10,
49 Undef = 0x20,
50 EarlyClobber = 0x40,
51 Debug = 0x80,
52 InternalRead = 0x100,
53 Renamable = 0x200,
54 DefineNoRead = Define | Undef,
55 ImplicitDefine = Implicit | Define,
56 ImplicitKill = Implicit | Kill
57 };
58
59} // end namespace RegState
60
61class MachineInstrBuilder {
62 MachineFunction *MF = nullptr;
63 MachineInstr *MI = nullptr;
64
65public:
66 MachineInstrBuilder() = default;
67
68 /// Create a MachineInstrBuilder for manipulating an existing instruction.
69 /// F must be the machine function that was used to allocate I.
70 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
71 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
72 : MF(&F), MI(&*I) {}
73
74 /// Allow automatic conversion to the machine instruction we are working on.
75 operator MachineInstr*() const { return MI; }
76 MachineInstr *operator->() const { return MI; }
77 operator MachineBasicBlock::iterator() const { return MI; }
78
79 /// If conversion operators fail, use this method to get the MachineInstr
80 /// explicitly.
81 MachineInstr *getInstr() const { return MI; }
82
83 /// Add a new virtual register operand.
84 const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
85 unsigned SubReg = 0) const {
86 assert((flags & 0x1) == 0 &&(((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."
) ? static_cast<void> (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 87, __PRETTY_FUNCTION__))
87 "Passing in 'true' to addReg is forbidden! Use enums instead.")(((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."
) ? static_cast<void> (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 87, __PRETTY_FUNCTION__))
;
88 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
89 flags & RegState::Define,
90 flags & RegState::Implicit,
91 flags & RegState::Kill,
92 flags & RegState::Dead,
93 flags & RegState::Undef,
94 flags & RegState::EarlyClobber,
95 SubReg,
96 flags & RegState::Debug,
97 flags & RegState::InternalRead,
98 flags & RegState::Renamable));
99 return *this;
100 }
101
102 /// Add a virtual register definition operand.
103 const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0,
104 unsigned SubReg = 0) const {
105 return addReg(RegNo, Flags | RegState::Define, SubReg);
106 }
107
108 /// Add a virtual register use operand. It is an error for Flags to contain
109 /// `RegState::Define` when calling this function.
110 const MachineInstrBuilder &addUse(unsigned RegNo, unsigned Flags = 0,
111 unsigned SubReg = 0) const {
112 assert(!(Flags & RegState::Define) &&((!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead."
) ? static_cast<void> (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 113, __PRETTY_FUNCTION__))
113 "Misleading addUse defines register, use addReg instead.")((!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead."
) ? static_cast<void> (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 113, __PRETTY_FUNCTION__))
;
114 return addReg(RegNo, Flags, SubReg);
115 }
116
117 /// Add a new immediate operand.
118 const MachineInstrBuilder &addImm(int64_t Val) const {
119 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
120 return *this;
121 }
122
123 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
124 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
125 return *this;
126 }
127
128 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
129 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
130 return *this;
131 }
132
133 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
134 unsigned char TargetFlags = 0) const {
135 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
136 return *this;
137 }
138
139 const MachineInstrBuilder &addFrameIndex(int Idx) const {
140 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
2
Calling 'MachineInstr::addOperand'
141 return *this;
142 }
143
144 const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
145 int Offset = 0,
146 unsigned char TargetFlags = 0) const {
147 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
148 return *this;
149 }
150
151 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
152 unsigned char TargetFlags = 0) const {
153 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
154 TargetFlags));
155 return *this;
156 }
157
158 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
159 unsigned char TargetFlags = 0) const {
160 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
161 return *this;
162 }
163
164 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
165 int64_t Offset = 0,
166 unsigned char TargetFlags = 0) const {
167 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
168 return *this;
169 }
170
171 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
172 unsigned char TargetFlags = 0) const {
173 MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
174 return *this;
175 }
176
177 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
178 int64_t Offset = 0,
179 unsigned char TargetFlags = 0) const {
180 MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
181 return *this;
182 }
183
184 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
185 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
186 return *this;
187 }
188
189 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
190 MI->addMemOperand(*MF, MMO);
191 return *this;
192 }
193
194 const MachineInstrBuilder &
195 setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const {
196 MI->setMemRefs(*MF, MMOs);
197 return *this;
198 }
199
200 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
201 MI->cloneMemRefs(*MF, OtherMI);
202 return *this;
203 }
204
205 const MachineInstrBuilder &
206 cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const {
207 MI->cloneMergedMemRefs(*MF, OtherMIs);
208 return *this;
209 }
210
211 const MachineInstrBuilder &add(const MachineOperand &MO) const {
212 MI->addOperand(*MF, MO);
213 return *this;
214 }
215
216 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
217 for (const MachineOperand &MO : MOs) {
218 MI->addOperand(*MF, MO);
219 }
220 return *this;
221 }
222
223 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
224 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
225 assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable
()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 227, __PRETTY_FUNCTION__))
226 : true) &&(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable
()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 227, __PRETTY_FUNCTION__))
227 "first MDNode argument of a DBG_VALUE not a variable")(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable
()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 227, __PRETTY_FUNCTION__))
;
228 assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel
()) : true) && "first MDNode argument of a DBG_LABEL not a label"
) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 230, __PRETTY_FUNCTION__))
229 : true) &&(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel
()) : true) && "first MDNode argument of a DBG_LABEL not a label"
) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 230, __PRETTY_FUNCTION__))
230 "first MDNode argument of a DBG_LABEL not a label")(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel
()) : true) && "first MDNode argument of a DBG_LABEL not a label"
) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 230, __PRETTY_FUNCTION__))
;
231 return *this;
232 }
233
234 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
235 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
236 return *this;
237 }
238
239 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
240 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
241 return *this;
242 }
243
244 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
245 MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
246 return *this;
247 }
248
249 const MachineInstrBuilder &addSym(MCSymbol *Sym,
250 unsigned char TargetFlags = 0) const {
251 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
252 return *this;
253 }
254
255 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
256 MI->setFlags(Flags);
257 return *this;
258 }
259
260 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
261 MI->setFlag(Flag);
262 return *this;
263 }
264
265 // Add a displacement from an existing MachineOperand with an added offset.
266 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
267 unsigned char TargetFlags = 0) const {
268 // If caller specifies new TargetFlags then use it, otherwise the
269 // default behavior is to copy the target flags from the existing
270 // MachineOperand. This means if the caller wants to clear the
271 // target flags it needs to do so explicitly.
272 if (0 == TargetFlags)
273 TargetFlags = Disp.getTargetFlags();
274
275 switch (Disp.getType()) {
276 default:
277 llvm_unreachable("Unhandled operand type in addDisp()")::llvm::llvm_unreachable_internal("Unhandled operand type in addDisp()"
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 277)
;
278 case MachineOperand::MO_Immediate:
279 return addImm(Disp.getImm() + off);
280 case MachineOperand::MO_ConstantPoolIndex:
281 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
282 TargetFlags);
283 case MachineOperand::MO_GlobalAddress:
284 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
285 TargetFlags);
286 }
287 }
288
289 /// Copy all the implicit operands from OtherMI onto this one.
290 const MachineInstrBuilder &
291 copyImplicitOps(const MachineInstr &OtherMI) const {
292 MI->copyImplicitOps(*MF, OtherMI);
293 return *this;
294 }
295
296 bool constrainAllUses(const TargetInstrInfo &TII,
297 const TargetRegisterInfo &TRI,
298 const RegisterBankInfo &RBI) const {
299 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
300 }
301};
302
303/// Builder interface. Specify how to create the initial instruction itself.
304inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
305 const MCInstrDesc &MCID) {
306 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
307}
308
309/// This version of the builder sets up the first operand as a
310/// destination virtual register.
311inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
312 const MCInstrDesc &MCID, unsigned DestReg) {
313 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
314 .addReg(DestReg, RegState::Define);
315}
316
317/// This version of the builder inserts the newly-built instruction before
318/// the given position in the given MachineBasicBlock, and sets up the first
319/// operand as a destination virtual register.
320inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
321 MachineBasicBlock::iterator I,
322 const DebugLoc &DL, const MCInstrDesc &MCID,
323 unsigned DestReg) {
324 MachineFunction &MF = *BB.getParent();
325 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
326 BB.insert(I, MI);
327 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
328}
329
330/// This version of the builder inserts the newly-built instruction before
331/// the given position in the given MachineBasicBlock, and sets up the first
332/// operand as a destination virtual register.
333///
334/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
335/// added to the same bundle.
336inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
337 MachineBasicBlock::instr_iterator I,
338 const DebugLoc &DL, const MCInstrDesc &MCID,
339 unsigned DestReg) {
340 MachineFunction &MF = *BB.getParent();
341 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
342 BB.insert(I, MI);
343 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
344}
345
346inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
347 const DebugLoc &DL, const MCInstrDesc &MCID,
348 unsigned DestReg) {
349 // Calling the overload for instr_iterator is always correct. However, the
350 // definition is not available in headers, so inline the check.
351 if (I.isInsideBundle())
352 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
353 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
354}
355
356inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
357 const DebugLoc &DL, const MCInstrDesc &MCID,
358 unsigned DestReg) {
359 return BuildMI(BB, *I, DL, MCID, DestReg);
360}
361
362/// This version of the builder inserts the newly-built instruction before the
363/// given position in the given MachineBasicBlock, and does NOT take a
364/// destination register.
365inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
366 MachineBasicBlock::iterator I,
367 const DebugLoc &DL,
368 const MCInstrDesc &MCID) {
369 MachineFunction &MF = *BB.getParent();
370 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
371 BB.insert(I, MI);
372 return MachineInstrBuilder(MF, MI);
373}
374
375inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
376 MachineBasicBlock::instr_iterator I,
377 const DebugLoc &DL,
378 const MCInstrDesc &MCID) {
379 MachineFunction &MF = *BB.getParent();
380 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
381 BB.insert(I, MI);
382 return MachineInstrBuilder(MF, MI);
383}
384
385inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
386 const DebugLoc &DL,
387 const MCInstrDesc &MCID) {
388 // Calling the overload for instr_iterator is always correct. However, the
389 // definition is not available in headers, so inline the check.
390 if (I.isInsideBundle())
391 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID);
392 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
393}
394
395inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
396 const DebugLoc &DL,
397 const MCInstrDesc &MCID) {
398 return BuildMI(BB, *I, DL, MCID);
399}
400
401/// This version of the builder inserts the newly-built instruction at the end
402/// of the given MachineBasicBlock, and does NOT take a destination register.
403inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
404 const MCInstrDesc &MCID) {
405 return BuildMI(*BB, BB->end(), DL, MCID);
406}
407
408/// This version of the builder inserts the newly-built instruction at the
409/// end of the given MachineBasicBlock, and sets up the first operand as a
410/// destination virtual register.
411inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
412 const MCInstrDesc &MCID, unsigned DestReg) {
413 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
414}
415
416/// This version of the builder builds a DBG_VALUE intrinsic
417/// for either a value in a register or a register-indirect
418/// address. The convention is that a DBG_VALUE is indirect iff the
419/// second operand is an immediate.
420MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
421 const MCInstrDesc &MCID, bool IsIndirect,
422 unsigned Reg, const MDNode *Variable,
423 const MDNode *Expr);
424
425/// This version of the builder builds a DBG_VALUE intrinsic
426/// for a MachineOperand.
427MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
428 const MCInstrDesc &MCID, bool IsIndirect,
429 MachineOperand &MO, const MDNode *Variable,
430 const MDNode *Expr);
431
432/// This version of the builder builds a DBG_VALUE intrinsic
433/// for either a value in a register or a register-indirect
434/// address and inserts it at position I.
435MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
436 MachineBasicBlock::iterator I, const DebugLoc &DL,
437 const MCInstrDesc &MCID, bool IsIndirect,
438 unsigned Reg, const MDNode *Variable,
439 const MDNode *Expr);
440
441/// This version of the builder builds a DBG_VALUE intrinsic
442/// for a machine operand and inserts it at position I.
443MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
444 MachineBasicBlock::iterator I, const DebugLoc &DL,
445 const MCInstrDesc &MCID, bool IsIndirect,
446 MachineOperand &MO, const MDNode *Variable,
447 const MDNode *Expr);
448
449/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
450MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
451 MachineBasicBlock::iterator I,
452 const MachineInstr &Orig, int FrameIndex);
453
454/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
455/// modifying an instruction in place while iterating over a basic block.
456void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex);
457
458inline unsigned getDefRegState(bool B) {
459 return B ? RegState::Define : 0;
460}
461inline unsigned getImplRegState(bool B) {
462 return B ? RegState::Implicit : 0;
463}
464inline unsigned getKillRegState(bool B) {
465 return B ? RegState::Kill : 0;
466}
467inline unsigned getDeadRegState(bool B) {
468 return B ? RegState::Dead : 0;
469}
470inline unsigned getUndefRegState(bool B) {
471 return B ? RegState::Undef : 0;
472}
473inline unsigned getInternalReadRegState(bool B) {
474 return B ? RegState::InternalRead : 0;
475}
476inline unsigned getDebugRegState(bool B) {
477 return B ? RegState::Debug : 0;
478}
479inline unsigned getRenamableRegState(bool B) {
480 return B ? RegState::Renamable : 0;
481}
482
483/// Get all register state flags from machine operand \p RegOp.
484inline unsigned getRegState(const MachineOperand &RegOp) {
485 assert(RegOp.isReg() && "Not a register operand")((RegOp.isReg() && "Not a register operand") ? static_cast
<void> (0) : __assert_fail ("RegOp.isReg() && \"Not a register operand\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 485, __PRETTY_FUNCTION__))
;
486 return getDefRegState(RegOp.isDef()) |
487 getImplRegState(RegOp.isImplicit()) |
488 getKillRegState(RegOp.isKill()) |
489 getDeadRegState(RegOp.isDead()) |
490 getUndefRegState(RegOp.isUndef()) |
491 getInternalReadRegState(RegOp.isInternalRead()) |
492 getDebugRegState(RegOp.isDebug()) |
493 getRenamableRegState(
494 TargetRegisterInfo::isPhysicalRegister(RegOp.getReg()) &&
495 RegOp.isRenamable());
496}
497
498/// Helper class for constructing bundles of MachineInstrs.
499///
500/// MIBundleBuilder can create a bundle from scratch by inserting new
501/// MachineInstrs one at a time, or it can create a bundle from a sequence of
502/// existing MachineInstrs in a basic block.
503class MIBundleBuilder {
504 MachineBasicBlock &MBB;
505 MachineBasicBlock::instr_iterator Begin;
506 MachineBasicBlock::instr_iterator End;
507
508public:
509 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
510 /// BB above the bundle or instruction at Pos.
511 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
512 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
513
514 /// Create a bundle from the sequence of instructions between B and E.
515 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
516 MachineBasicBlock::iterator E)
517 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
518 assert(B != E && "No instructions to bundle")((B != E && "No instructions to bundle") ? static_cast
<void> (0) : __assert_fail ("B != E && \"No instructions to bundle\""
, "/build/llvm-toolchain-snapshot-8~svn345461/include/llvm/CodeGen/MachineInstrBuilder.h"
, 518, __PRETTY_FUNCTION__))
;
519 ++B;
520 while (B != E) {
521 MachineInstr &MI = *B;
522 ++B;
523 MI.bundleWithPred();
524 }
525 }
526
527 /// Create an MIBundleBuilder representing an existing instruction or bundle
528 /// that has MI as its head.
529 explicit MIBundleBuilder(MachineInstr *MI)
530 : MBB(*MI->getParent()), Begin(MI),
531 End(getBundleEnd(MI->getIterator())) {}
532
533 /// Return a reference to the basic block containing this bundle.
534 MachineBasicBlock &getMBB() const { return MBB; }
535
536 /// Return true if no instructions have been inserted in this bundle yet.
537 /// Empty bundles aren't representable in a MachineBasicBlock.
538 bool empty() const { return Begin == End; }
539
540 /// Return an iterator to the first bundled instruction.
541 MachineBasicBlock::instr_iterator begin() const { return Begin; }
542
543 /// Return an iterator beyond the last bundled instruction.
544 MachineBasicBlock::instr_iterator end() const { return End; }
545
546 /// Insert MI into this bundle before I which must point to an instruction in
547 /// the bundle, or end().
548 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
549 MachineInstr *MI) {
550 MBB.insert(I, MI);
551 if (I == Begin) {
552 if (!empty())
553 MI->bundleWithSucc();
554 Begin = MI->getIterator();
555 return *this;
556 }
557 if (I == End) {
558 MI->bundleWithPred();
559 return *this;
560 }
561 // MI was inserted in the middle of the bundle, so its neighbors' flags are
562 // already fine. Update MI's bundle flags manually.
563 MI->setFlag(MachineInstr::BundledPred);
564 MI->setFlag(MachineInstr::BundledSucc);
565 return *this;
566 }
567
568 /// Insert MI into MBB by prepending it to the instructions in the bundle.
569 /// MI will become the first instruction in the bundle.
570 MIBundleBuilder &prepend(MachineInstr *MI) {
571 return insert(begin(), MI);
572 }
573
574 /// Insert MI into MBB by appending it to the instructions in the bundle.
575 /// MI will become the last instruction in the bundle.
576 MIBundleBuilder &append(MachineInstr *MI) {
577 return insert(end(), MI);
578 }
579};
580
581} // end namespace llvm
582
583#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H