File: | lib/CodeGen/MachineInstr.cpp |
Warning: | line 264, column 19 Access to field 'ParentMI' results in a dereference of a null pointer (loaded from variable 'NewMO') |
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1 | //===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===// | |||
2 | // | |||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
4 | // See https://llvm.org/LICENSE.txt for license information. | |||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
6 | // | |||
7 | //===----------------------------------------------------------------------===// | |||
8 | // | |||
9 | // Methods common to all machine instructions. | |||
10 | // | |||
11 | //===----------------------------------------------------------------------===// | |||
12 | ||||
13 | #include "llvm/CodeGen/MachineInstr.h" | |||
14 | #include "llvm/ADT/APFloat.h" | |||
15 | #include "llvm/ADT/ArrayRef.h" | |||
16 | #include "llvm/ADT/FoldingSet.h" | |||
17 | #include "llvm/ADT/Hashing.h" | |||
18 | #include "llvm/ADT/None.h" | |||
19 | #include "llvm/ADT/STLExtras.h" | |||
20 | #include "llvm/ADT/SmallBitVector.h" | |||
21 | #include "llvm/ADT/SmallString.h" | |||
22 | #include "llvm/ADT/SmallVector.h" | |||
23 | #include "llvm/Analysis/AliasAnalysis.h" | |||
24 | #include "llvm/Analysis/Loads.h" | |||
25 | #include "llvm/Analysis/MemoryLocation.h" | |||
26 | #include "llvm/CodeGen/GlobalISel/RegisterBank.h" | |||
27 | #include "llvm/CodeGen/MachineBasicBlock.h" | |||
28 | #include "llvm/CodeGen/MachineFrameInfo.h" | |||
29 | #include "llvm/CodeGen/MachineFunction.h" | |||
30 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |||
31 | #include "llvm/CodeGen/MachineInstrBundle.h" | |||
32 | #include "llvm/CodeGen/MachineMemOperand.h" | |||
33 | #include "llvm/CodeGen/MachineModuleInfo.h" | |||
34 | #include "llvm/CodeGen/MachineOperand.h" | |||
35 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |||
36 | #include "llvm/CodeGen/PseudoSourceValue.h" | |||
37 | #include "llvm/CodeGen/TargetInstrInfo.h" | |||
38 | #include "llvm/CodeGen/TargetRegisterInfo.h" | |||
39 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | |||
40 | #include "llvm/Config/llvm-config.h" | |||
41 | #include "llvm/IR/Constants.h" | |||
42 | #include "llvm/IR/DebugInfoMetadata.h" | |||
43 | #include "llvm/IR/DebugLoc.h" | |||
44 | #include "llvm/IR/DerivedTypes.h" | |||
45 | #include "llvm/IR/Function.h" | |||
46 | #include "llvm/IR/InlineAsm.h" | |||
47 | #include "llvm/IR/InstrTypes.h" | |||
48 | #include "llvm/IR/Intrinsics.h" | |||
49 | #include "llvm/IR/LLVMContext.h" | |||
50 | #include "llvm/IR/Metadata.h" | |||
51 | #include "llvm/IR/Module.h" | |||
52 | #include "llvm/IR/ModuleSlotTracker.h" | |||
53 | #include "llvm/IR/Operator.h" | |||
54 | #include "llvm/IR/Type.h" | |||
55 | #include "llvm/IR/Value.h" | |||
56 | #include "llvm/MC/MCInstrDesc.h" | |||
57 | #include "llvm/MC/MCRegisterInfo.h" | |||
58 | #include "llvm/MC/MCSymbol.h" | |||
59 | #include "llvm/Support/Casting.h" | |||
60 | #include "llvm/Support/CommandLine.h" | |||
61 | #include "llvm/Support/Compiler.h" | |||
62 | #include "llvm/Support/Debug.h" | |||
63 | #include "llvm/Support/ErrorHandling.h" | |||
64 | #include "llvm/Support/LowLevelTypeImpl.h" | |||
65 | #include "llvm/Support/MathExtras.h" | |||
66 | #include "llvm/Support/raw_ostream.h" | |||
67 | #include "llvm/Target/TargetIntrinsicInfo.h" | |||
68 | #include "llvm/Target/TargetMachine.h" | |||
69 | #include <algorithm> | |||
70 | #include <cassert> | |||
71 | #include <cstddef> | |||
72 | #include <cstdint> | |||
73 | #include <cstring> | |||
74 | #include <iterator> | |||
75 | #include <utility> | |||
76 | ||||
77 | using namespace llvm; | |||
78 | ||||
79 | static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) { | |||
80 | if (const MachineBasicBlock *MBB = MI.getParent()) | |||
81 | if (const MachineFunction *MF = MBB->getParent()) | |||
82 | return MF; | |||
83 | return nullptr; | |||
84 | } | |||
85 | ||||
86 | // Try to crawl up to the machine function and get TRI and IntrinsicInfo from | |||
87 | // it. | |||
88 | static void tryToGetTargetInfo(const MachineInstr &MI, | |||
89 | const TargetRegisterInfo *&TRI, | |||
90 | const MachineRegisterInfo *&MRI, | |||
91 | const TargetIntrinsicInfo *&IntrinsicInfo, | |||
92 | const TargetInstrInfo *&TII) { | |||
93 | ||||
94 | if (const MachineFunction *MF = getMFIfAvailable(MI)) { | |||
95 | TRI = MF->getSubtarget().getRegisterInfo(); | |||
96 | MRI = &MF->getRegInfo(); | |||
97 | IntrinsicInfo = MF->getTarget().getIntrinsicInfo(); | |||
98 | TII = MF->getSubtarget().getInstrInfo(); | |||
99 | } | |||
100 | } | |||
101 | ||||
102 | void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) { | |||
103 | if (MCID->ImplicitDefs) | |||
104 | for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; | |||
105 | ++ImpDefs) | |||
106 | addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true)); | |||
107 | if (MCID->ImplicitUses) | |||
108 | for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses; | |||
109 | ++ImpUses) | |||
110 | addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true)); | |||
111 | } | |||
112 | ||||
113 | /// MachineInstr ctor - This constructor creates a MachineInstr and adds the | |||
114 | /// implicit operands. It reserves space for the number of operands specified by | |||
115 | /// the MCInstrDesc. | |||
116 | MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, | |||
117 | DebugLoc dl, bool NoImp) | |||
118 | : MCID(&tid), debugLoc(std::move(dl)) { | |||
119 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor" ) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 119, __PRETTY_FUNCTION__)); | |||
120 | ||||
121 | // Reserve space for the expected number of operands. | |||
122 | if (unsigned NumOps = MCID->getNumOperands() + | |||
123 | MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) { | |||
124 | CapOperands = OperandCapacity::get(NumOps); | |||
125 | Operands = MF.allocateOperandArray(CapOperands); | |||
126 | } | |||
127 | ||||
128 | if (!NoImp) | |||
129 | addImplicitDefUseOperands(MF); | |||
130 | } | |||
131 | ||||
132 | /// MachineInstr ctor - Copies MachineInstr arg exactly | |||
133 | /// | |||
134 | MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) | |||
135 | : MCID(&MI.getDesc()), Info(MI.Info), debugLoc(MI.getDebugLoc()) { | |||
136 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((debugLoc.hasTrivialDestructor() && "Expected trivial destructor" ) ? static_cast<void> (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 136, __PRETTY_FUNCTION__)); | |||
137 | ||||
138 | CapOperands = OperandCapacity::get(MI.getNumOperands()); | |||
139 | Operands = MF.allocateOperandArray(CapOperands); | |||
140 | ||||
141 | // Copy operands. | |||
142 | for (const MachineOperand &MO : MI.operands()) | |||
143 | addOperand(MF, MO); | |||
144 | ||||
145 | // Copy all the sensible flags. | |||
146 | setFlags(MI.Flags); | |||
147 | } | |||
148 | ||||
149 | /// getRegInfo - If this instruction is embedded into a MachineFunction, | |||
150 | /// return the MachineRegisterInfo object for the current function, otherwise | |||
151 | /// return null. | |||
152 | MachineRegisterInfo *MachineInstr::getRegInfo() { | |||
153 | if (MachineBasicBlock *MBB = getParent()) | |||
154 | return &MBB->getParent()->getRegInfo(); | |||
155 | return nullptr; | |||
156 | } | |||
157 | ||||
158 | /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in | |||
159 | /// this instruction from their respective use lists. This requires that the | |||
160 | /// operands already be on their use lists. | |||
161 | void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) { | |||
162 | for (MachineOperand &MO : operands()) | |||
163 | if (MO.isReg()) | |||
164 | MRI.removeRegOperandFromUseList(&MO); | |||
165 | } | |||
166 | ||||
167 | /// AddRegOperandsToUseLists - Add all of the register operands in | |||
168 | /// this instruction from their respective use lists. This requires that the | |||
169 | /// operands not be on their use lists yet. | |||
170 | void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) { | |||
171 | for (MachineOperand &MO : operands()) | |||
172 | if (MO.isReg()) | |||
173 | MRI.addRegOperandToUseList(&MO); | |||
174 | } | |||
175 | ||||
176 | void MachineInstr::addOperand(const MachineOperand &Op) { | |||
177 | MachineBasicBlock *MBB = getParent(); | |||
178 | assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")((MBB && "Use MachineInstrBuilder to add operands to dangling instrs" ) ? static_cast<void> (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 178, __PRETTY_FUNCTION__)); | |||
179 | MachineFunction *MF = MBB->getParent(); | |||
180 | assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")((MF && "Use MachineInstrBuilder to add operands to dangling instrs" ) ? static_cast<void> (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 180, __PRETTY_FUNCTION__)); | |||
181 | addOperand(*MF, Op); | |||
182 | } | |||
183 | ||||
184 | /// Move NumOps MachineOperands from Src to Dst, with support for overlapping | |||
185 | /// ranges. If MRI is non-null also update use-def chains. | |||
186 | static void moveOperands(MachineOperand *Dst, MachineOperand *Src, | |||
187 | unsigned NumOps, MachineRegisterInfo *MRI) { | |||
188 | if (MRI) | |||
189 | return MRI->moveOperands(Dst, Src, NumOps); | |||
190 | ||||
191 | // MachineOperand is a trivially copyable type so we can just use memmove. | |||
192 | std::memmove(Dst, Src, NumOps * sizeof(MachineOperand)); | |||
193 | } | |||
194 | ||||
195 | /// addOperand - Add the specified operand to the instruction. If it is an | |||
196 | /// implicit operand, it is added to the end of the operand list. If it is | |||
197 | /// an explicit operand it is added at the end of the explicit operand list | |||
198 | /// (before the first implicit operand). | |||
199 | void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) { | |||
200 | assert(MCID && "Cannot add operands before providing an instr descriptor")((MCID && "Cannot add operands before providing an instr descriptor" ) ? static_cast<void> (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 200, __PRETTY_FUNCTION__)); | |||
201 | ||||
202 | // Check if we're adding one of our existing operands. | |||
203 | if (&Op >= Operands && &Op < Operands + NumOperands) { | |||
204 | // This is unusual: MI->addOperand(MI->getOperand(i)). | |||
205 | // If adding Op requires reallocating or moving existing operands around, | |||
206 | // the Op reference could go stale. Support it by copying Op. | |||
207 | MachineOperand CopyOp(Op); | |||
208 | return addOperand(MF, CopyOp); | |||
209 | } | |||
210 | ||||
211 | // Find the insert location for the new operand. Implicit registers go at | |||
212 | // the end, everything else goes before the implicit regs. | |||
213 | // | |||
214 | // FIXME: Allow mixed explicit and implicit operands on inline asm. | |||
215 | // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as | |||
216 | // implicit-defs, but they must not be moved around. See the FIXME in | |||
217 | // InstrEmitter.cpp. | |||
218 | unsigned OpNo = getNumOperands(); | |||
219 | bool isImpReg = Op.isReg() && Op.isImplicit(); | |||
220 | if (!isImpReg && !isInlineAsm()) { | |||
221 | while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { | |||
222 | --OpNo; | |||
223 | assert(!Operands[OpNo].isTied() && "Cannot move tied operands")((!Operands[OpNo].isTied() && "Cannot move tied operands" ) ? static_cast<void> (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 223, __PRETTY_FUNCTION__)); | |||
224 | } | |||
225 | } | |||
226 | ||||
227 | #ifndef NDEBUG | |||
228 | bool isDebugOp = Op.getType() == MachineOperand::MO_Metadata || | |||
229 | Op.getType() == MachineOperand::MO_MCSymbol; | |||
230 | // OpNo now points as the desired insertion point. Unless this is a variadic | |||
231 | // instruction, only implicit regs are allowed beyond MCID->getNumOperands(). | |||
232 | // RegMask operands go between the explicit and implicit operands. | |||
233 | assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!" ) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 235, __PRETTY_FUNCTION__)) | |||
234 | OpNo < MCID->getNumOperands() || isDebugOp) &&(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!" ) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 235, __PRETTY_FUNCTION__)) | |||
235 | "Trying to add an operand to a machine instr that is already done!")(((isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && "Trying to add an operand to a machine instr that is already done!" ) ? static_cast<void> (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isDebugOp) && \"Trying to add an operand to a machine instr that is already done!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 235, __PRETTY_FUNCTION__)); | |||
236 | #endif | |||
237 | ||||
238 | MachineRegisterInfo *MRI = getRegInfo(); | |||
239 | ||||
240 | // Determine if the Operands array needs to be reallocated. | |||
241 | // Save the old capacity and operand array. | |||
242 | OperandCapacity OldCap = CapOperands; | |||
243 | MachineOperand *OldOperands = Operands; | |||
244 | if (!OldOperands || OldCap.getSize() == getNumOperands()) { | |||
245 | CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1); | |||
246 | Operands = MF.allocateOperandArray(CapOperands); | |||
247 | // Move the operands before the insertion point. | |||
248 | if (OpNo) | |||
249 | moveOperands(Operands, OldOperands, OpNo, MRI); | |||
250 | } | |||
251 | ||||
252 | // Move the operands following the insertion point. | |||
253 | if (OpNo != NumOperands) | |||
254 | moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo, | |||
255 | MRI); | |||
256 | ++NumOperands; | |||
257 | ||||
258 | // Deallocate the old operand array. | |||
259 | if (OldOperands != Operands && OldOperands) | |||
260 | MF.deallocateOperandArray(OldCap, OldOperands); | |||
261 | ||||
262 | // Copy Op into place. It still needs to be inserted into the MRI use lists. | |||
263 | MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op); | |||
264 | NewMO->ParentMI = this; | |||
| ||||
265 | ||||
266 | // When adding a register operand, tell MRI about it. | |||
267 | if (NewMO->isReg()) { | |||
268 | // Ensure isOnRegUseList() returns false, regardless of Op's status. | |||
269 | NewMO->Contents.Reg.Prev = nullptr; | |||
270 | // Ignore existing ties. This is not a property that can be copied. | |||
271 | NewMO->TiedTo = 0; | |||
272 | // Add the new operand to MRI, but only for instructions in an MBB. | |||
273 | if (MRI) | |||
274 | MRI->addRegOperandToUseList(NewMO); | |||
275 | // The MCID operand information isn't accurate until we start adding | |||
276 | // explicit operands. The implicit operands are added first, then the | |||
277 | // explicits are inserted before them. | |||
278 | if (!isImpReg) { | |||
279 | // Tie uses to defs as indicated in MCInstrDesc. | |||
280 | if (NewMO->isUse()) { | |||
281 | int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); | |||
282 | if (DefIdx != -1) | |||
283 | tieOperands(DefIdx, OpNo); | |||
284 | } | |||
285 | // If the register operand is flagged as early, mark the operand as such. | |||
286 | if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) | |||
287 | NewMO->setIsEarlyClobber(true); | |||
288 | } | |||
289 | } | |||
290 | } | |||
291 | ||||
292 | /// RemoveOperand - Erase an operand from an instruction, leaving it with one | |||
293 | /// fewer operand than it started with. | |||
294 | /// | |||
295 | void MachineInstr::RemoveOperand(unsigned OpNo) { | |||
296 | assert(OpNo < getNumOperands() && "Invalid operand number")((OpNo < getNumOperands() && "Invalid operand number" ) ? static_cast<void> (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 296, __PRETTY_FUNCTION__)); | |||
297 | untieRegOperand(OpNo); | |||
298 | ||||
299 | #ifndef NDEBUG | |||
300 | // Moving tied operands would break the ties. | |||
301 | for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i) | |||
302 | if (Operands[i].isReg()) | |||
303 | assert(!Operands[i].isTied() && "Cannot move tied operands")((!Operands[i].isTied() && "Cannot move tied operands" ) ? static_cast<void> (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 303, __PRETTY_FUNCTION__)); | |||
304 | #endif | |||
305 | ||||
306 | MachineRegisterInfo *MRI = getRegInfo(); | |||
307 | if (MRI && Operands[OpNo].isReg()) | |||
308 | MRI->removeRegOperandFromUseList(Operands + OpNo); | |||
309 | ||||
310 | // Don't call the MachineOperand destructor. A lot of this code depends on | |||
311 | // MachineOperand having a trivial destructor anyway, and adding a call here | |||
312 | // wouldn't make it 'destructor-correct'. | |||
313 | ||||
314 | if (unsigned N = NumOperands - 1 - OpNo) | |||
315 | moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI); | |||
316 | --NumOperands; | |||
317 | } | |||
318 | ||||
319 | void MachineInstr::dropMemRefs(MachineFunction &MF) { | |||
320 | if (memoperands_empty()) | |||
321 | return; | |||
322 | ||||
323 | // See if we can just drop all of our extra info. | |||
324 | if (!getPreInstrSymbol() && !getPostInstrSymbol()) { | |||
325 | Info.clear(); | |||
326 | return; | |||
327 | } | |||
328 | if (!getPostInstrSymbol()) { | |||
329 | Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol()); | |||
330 | return; | |||
331 | } | |||
332 | if (!getPreInstrSymbol()) { | |||
333 | Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol()); | |||
334 | return; | |||
335 | } | |||
336 | ||||
337 | // Otherwise allocate a fresh extra info with just these symbols. | |||
338 | Info.set<EIIK_OutOfLine>( | |||
339 | MF.createMIExtraInfo({}, getPreInstrSymbol(), getPostInstrSymbol())); | |||
340 | } | |||
341 | ||||
342 | void MachineInstr::setMemRefs(MachineFunction &MF, | |||
343 | ArrayRef<MachineMemOperand *> MMOs) { | |||
344 | if (MMOs.empty()) { | |||
345 | dropMemRefs(MF); | |||
346 | return; | |||
347 | } | |||
348 | ||||
349 | // Try to store a single MMO inline. | |||
350 | if (MMOs.size() == 1 && !getPreInstrSymbol() && !getPostInstrSymbol()) { | |||
351 | Info.set<EIIK_MMO>(MMOs[0]); | |||
352 | return; | |||
353 | } | |||
354 | ||||
355 | // Otherwise create an extra info struct with all of our info. | |||
356 | Info.set<EIIK_OutOfLine>( | |||
357 | MF.createMIExtraInfo(MMOs, getPreInstrSymbol(), getPostInstrSymbol())); | |||
358 | } | |||
359 | ||||
360 | void MachineInstr::addMemOperand(MachineFunction &MF, | |||
361 | MachineMemOperand *MO) { | |||
362 | SmallVector<MachineMemOperand *, 2> MMOs; | |||
363 | MMOs.append(memoperands_begin(), memoperands_end()); | |||
364 | MMOs.push_back(MO); | |||
365 | setMemRefs(MF, MMOs); | |||
366 | } | |||
367 | ||||
368 | void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) { | |||
369 | if (this == &MI) | |||
370 | // Nothing to do for a self-clone! | |||
371 | return; | |||
372 | ||||
373 | assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 374, __PRETTY_FUNCTION__)) | |||
374 | "Invalid machine functions when cloning memory refrences!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory refrences!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory refrences!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 374, __PRETTY_FUNCTION__)); | |||
375 | // See if we can just steal the extra info already allocated for the | |||
376 | // instruction. We can do this whenever the pre- and post-instruction symbols | |||
377 | // are the same (including null). | |||
378 | if (getPreInstrSymbol() == MI.getPreInstrSymbol() && | |||
379 | getPostInstrSymbol() == MI.getPostInstrSymbol()) { | |||
380 | Info = MI.Info; | |||
381 | return; | |||
382 | } | |||
383 | ||||
384 | // Otherwise, fall back on a copy-based clone. | |||
385 | setMemRefs(MF, MI.memoperands()); | |||
386 | } | |||
387 | ||||
388 | /// Check to see if the MMOs pointed to by the two MemRefs arrays are | |||
389 | /// identical. | |||
390 | static bool hasIdenticalMMOs(ArrayRef<MachineMemOperand *> LHS, | |||
391 | ArrayRef<MachineMemOperand *> RHS) { | |||
392 | if (LHS.size() != RHS.size()) | |||
393 | return false; | |||
394 | ||||
395 | auto LHSPointees = make_pointee_range(LHS); | |||
396 | auto RHSPointees = make_pointee_range(RHS); | |||
397 | return std::equal(LHSPointees.begin(), LHSPointees.end(), | |||
398 | RHSPointees.begin()); | |||
399 | } | |||
400 | ||||
401 | void MachineInstr::cloneMergedMemRefs(MachineFunction &MF, | |||
402 | ArrayRef<const MachineInstr *> MIs) { | |||
403 | // Try handling easy numbers of MIs with simpler mechanisms. | |||
404 | if (MIs.empty()) { | |||
405 | dropMemRefs(MF); | |||
406 | return; | |||
407 | } | |||
408 | if (MIs.size() == 1) { | |||
409 | cloneMemRefs(MF, *MIs[0]); | |||
410 | return; | |||
411 | } | |||
412 | // Because an empty memoperands list provides *no* information and must be | |||
413 | // handled conservatively (assuming the instruction can do anything), the only | |||
414 | // way to merge with it is to drop all other memoperands. | |||
415 | if (MIs[0]->memoperands_empty()) { | |||
416 | dropMemRefs(MF); | |||
417 | return; | |||
418 | } | |||
419 | ||||
420 | // Handle the general case. | |||
421 | SmallVector<MachineMemOperand *, 2> MergedMMOs; | |||
422 | // Start with the first instruction. | |||
423 | assert(&MF == MIs[0]->getMF() &&((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 424, __PRETTY_FUNCTION__)) | |||
424 | "Invalid machine functions when cloning memory references!")((&MF == MIs[0]->getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MIs[0]->getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 424, __PRETTY_FUNCTION__)); | |||
425 | MergedMMOs.append(MIs[0]->memoperands_begin(), MIs[0]->memoperands_end()); | |||
426 | // Now walk all the other instructions and accumulate any different MMOs. | |||
427 | for (const MachineInstr &MI : make_pointee_range(MIs.slice(1))) { | |||
428 | assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 429, __PRETTY_FUNCTION__)) | |||
429 | "Invalid machine functions when cloning memory references!")((&MF == MI.getMF() && "Invalid machine functions when cloning memory references!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning memory references!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 429, __PRETTY_FUNCTION__)); | |||
430 | ||||
431 | // Skip MIs with identical operands to the first. This is a somewhat | |||
432 | // arbitrary hack but will catch common cases without being quadratic. | |||
433 | // TODO: We could fully implement merge semantics here if needed. | |||
434 | if (hasIdenticalMMOs(MIs[0]->memoperands(), MI.memoperands())) | |||
435 | continue; | |||
436 | ||||
437 | // Because an empty memoperands list provides *no* information and must be | |||
438 | // handled conservatively (assuming the instruction can do anything), the | |||
439 | // only way to merge with it is to drop all other memoperands. | |||
440 | if (MI.memoperands_empty()) { | |||
441 | dropMemRefs(MF); | |||
442 | return; | |||
443 | } | |||
444 | ||||
445 | // Otherwise accumulate these into our temporary buffer of the merged state. | |||
446 | MergedMMOs.append(MI.memoperands_begin(), MI.memoperands_end()); | |||
447 | } | |||
448 | ||||
449 | setMemRefs(MF, MergedMMOs); | |||
450 | } | |||
451 | ||||
452 | void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { | |||
453 | MCSymbol *OldSymbol = getPreInstrSymbol(); | |||
454 | if (OldSymbol == Symbol) | |||
455 | return; | |||
456 | if (OldSymbol && !Symbol) { | |||
457 | // We're removing a symbol rather than adding one. Try to clean up any | |||
458 | // extra info carried around. | |||
459 | if (Info.is<EIIK_PreInstrSymbol>()) { | |||
460 | Info.clear(); | |||
461 | return; | |||
462 | } | |||
463 | ||||
464 | if (memoperands_empty()) { | |||
465 | assert(getPostInstrSymbol() &&((getPostInstrSymbol() && "Should never have only a single symbol allocated out-of-line!" ) ? static_cast<void> (0) : __assert_fail ("getPostInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 466, __PRETTY_FUNCTION__)) | |||
466 | "Should never have only a single symbol allocated out-of-line!")((getPostInstrSymbol() && "Should never have only a single symbol allocated out-of-line!" ) ? static_cast<void> (0) : __assert_fail ("getPostInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 466, __PRETTY_FUNCTION__)); | |||
467 | Info.set<EIIK_PostInstrSymbol>(getPostInstrSymbol()); | |||
468 | return; | |||
469 | } | |||
470 | ||||
471 | // Otherwise fallback on the generic update. | |||
472 | } else if (!Info || Info.is<EIIK_PreInstrSymbol>()) { | |||
473 | // If we don't have any other extra info, we can store this inline. | |||
474 | Info.set<EIIK_PreInstrSymbol>(Symbol); | |||
475 | return; | |||
476 | } | |||
477 | ||||
478 | // Otherwise, allocate a full new set of extra info. | |||
479 | // FIXME: Maybe we should make the symbols in the extra info mutable? | |||
480 | Info.set<EIIK_OutOfLine>( | |||
481 | MF.createMIExtraInfo(memoperands(), Symbol, getPostInstrSymbol())); | |||
482 | } | |||
483 | ||||
484 | void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { | |||
485 | MCSymbol *OldSymbol = getPostInstrSymbol(); | |||
486 | if (OldSymbol == Symbol) | |||
487 | return; | |||
488 | if (OldSymbol && !Symbol) { | |||
489 | // We're removing a symbol rather than adding one. Try to clean up any | |||
490 | // extra info carried around. | |||
491 | if (Info.is<EIIK_PostInstrSymbol>()) { | |||
492 | Info.clear(); | |||
493 | return; | |||
494 | } | |||
495 | ||||
496 | if (memoperands_empty()) { | |||
497 | assert(getPreInstrSymbol() &&((getPreInstrSymbol() && "Should never have only a single symbol allocated out-of-line!" ) ? static_cast<void> (0) : __assert_fail ("getPreInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 498, __PRETTY_FUNCTION__)) | |||
498 | "Should never have only a single symbol allocated out-of-line!")((getPreInstrSymbol() && "Should never have only a single symbol allocated out-of-line!" ) ? static_cast<void> (0) : __assert_fail ("getPreInstrSymbol() && \"Should never have only a single symbol allocated out-of-line!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 498, __PRETTY_FUNCTION__)); | |||
499 | Info.set<EIIK_PreInstrSymbol>(getPreInstrSymbol()); | |||
500 | return; | |||
501 | } | |||
502 | ||||
503 | // Otherwise fallback on the generic update. | |||
504 | } else if (!Info || Info.is<EIIK_PostInstrSymbol>()) { | |||
505 | // If we don't have any other extra info, we can store this inline. | |||
506 | Info.set<EIIK_PostInstrSymbol>(Symbol); | |||
507 | return; | |||
508 | } | |||
509 | ||||
510 | // Otherwise, allocate a full new set of extra info. | |||
511 | // FIXME: Maybe we should make the symbols in the extra info mutable? | |||
512 | Info.set<EIIK_OutOfLine>( | |||
513 | MF.createMIExtraInfo(memoperands(), getPreInstrSymbol(), Symbol)); | |||
514 | } | |||
515 | ||||
516 | void MachineInstr::cloneInstrSymbols(MachineFunction &MF, | |||
517 | const MachineInstr &MI) { | |||
518 | if (this == &MI) | |||
519 | // Nothing to do for a self-clone! | |||
520 | return; | |||
521 | ||||
522 | assert(&MF == MI.getMF() &&((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 523, __PRETTY_FUNCTION__)) | |||
523 | "Invalid machine functions when cloning instruction symbols!")((&MF == MI.getMF() && "Invalid machine functions when cloning instruction symbols!" ) ? static_cast<void> (0) : __assert_fail ("&MF == MI.getMF() && \"Invalid machine functions when cloning instruction symbols!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 523, __PRETTY_FUNCTION__)); | |||
524 | ||||
525 | setPreInstrSymbol(MF, MI.getPreInstrSymbol()); | |||
526 | setPostInstrSymbol(MF, MI.getPostInstrSymbol()); | |||
527 | } | |||
528 | ||||
529 | uint16_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const { | |||
530 | // For now, the just return the union of the flags. If the flags get more | |||
531 | // complicated over time, we might need more logic here. | |||
532 | return getFlags() | Other.getFlags(); | |||
533 | } | |||
534 | ||||
535 | uint16_t MachineInstr::copyFlagsFromInstruction(const Instruction &I) { | |||
536 | uint16_t MIFlags = 0; | |||
537 | // Copy the wrapping flags. | |||
538 | if (const OverflowingBinaryOperator *OB = | |||
539 | dyn_cast<OverflowingBinaryOperator>(&I)) { | |||
540 | if (OB->hasNoSignedWrap()) | |||
541 | MIFlags |= MachineInstr::MIFlag::NoSWrap; | |||
542 | if (OB->hasNoUnsignedWrap()) | |||
543 | MIFlags |= MachineInstr::MIFlag::NoUWrap; | |||
544 | } | |||
545 | ||||
546 | // Copy the exact flag. | |||
547 | if (const PossiblyExactOperator *PE = dyn_cast<PossiblyExactOperator>(&I)) | |||
548 | if (PE->isExact()) | |||
549 | MIFlags |= MachineInstr::MIFlag::IsExact; | |||
550 | ||||
551 | // Copy the fast-math flags. | |||
552 | if (const FPMathOperator *FP = dyn_cast<FPMathOperator>(&I)) { | |||
553 | const FastMathFlags Flags = FP->getFastMathFlags(); | |||
554 | if (Flags.noNaNs()) | |||
555 | MIFlags |= MachineInstr::MIFlag::FmNoNans; | |||
556 | if (Flags.noInfs()) | |||
557 | MIFlags |= MachineInstr::MIFlag::FmNoInfs; | |||
558 | if (Flags.noSignedZeros()) | |||
559 | MIFlags |= MachineInstr::MIFlag::FmNsz; | |||
560 | if (Flags.allowReciprocal()) | |||
561 | MIFlags |= MachineInstr::MIFlag::FmArcp; | |||
562 | if (Flags.allowContract()) | |||
563 | MIFlags |= MachineInstr::MIFlag::FmContract; | |||
564 | if (Flags.approxFunc()) | |||
565 | MIFlags |= MachineInstr::MIFlag::FmAfn; | |||
566 | if (Flags.allowReassoc()) | |||
567 | MIFlags |= MachineInstr::MIFlag::FmReassoc; | |||
568 | } | |||
569 | ||||
570 | return MIFlags; | |||
571 | } | |||
572 | ||||
573 | void MachineInstr::copyIRFlags(const Instruction &I) { | |||
574 | Flags = copyFlagsFromInstruction(I); | |||
575 | } | |||
576 | ||||
577 | bool MachineInstr::hasPropertyInBundle(uint64_t Mask, QueryType Type) const { | |||
578 | assert(!isBundledWithPred() && "Must be called on bundle header")((!isBundledWithPred() && "Must be called on bundle header" ) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 578, __PRETTY_FUNCTION__)); | |||
579 | for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) { | |||
580 | if (MII->getDesc().getFlags() & Mask) { | |||
581 | if (Type == AnyInBundle) | |||
582 | return true; | |||
583 | } else { | |||
584 | if (Type == AllInBundle && !MII->isBundle()) | |||
585 | return false; | |||
586 | } | |||
587 | // This was the last instruction in the bundle. | |||
588 | if (!MII->isBundledWithSucc()) | |||
589 | return Type == AllInBundle; | |||
590 | } | |||
591 | } | |||
592 | ||||
593 | bool MachineInstr::isIdenticalTo(const MachineInstr &Other, | |||
594 | MICheckType Check) const { | |||
595 | // If opcodes or number of operands are not the same then the two | |||
596 | // instructions are obviously not identical. | |||
597 | if (Other.getOpcode() != getOpcode() || | |||
598 | Other.getNumOperands() != getNumOperands()) | |||
599 | return false; | |||
600 | ||||
601 | if (isBundle()) { | |||
602 | // We have passed the test above that both instructions have the same | |||
603 | // opcode, so we know that both instructions are bundles here. Let's compare | |||
604 | // MIs inside the bundle. | |||
605 | assert(Other.isBundle() && "Expected that both instructions are bundles.")((Other.isBundle() && "Expected that both instructions are bundles." ) ? static_cast<void> (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 605, __PRETTY_FUNCTION__)); | |||
606 | MachineBasicBlock::const_instr_iterator I1 = getIterator(); | |||
607 | MachineBasicBlock::const_instr_iterator I2 = Other.getIterator(); | |||
608 | // Loop until we analysed the last intruction inside at least one of the | |||
609 | // bundles. | |||
610 | while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) { | |||
611 | ++I1; | |||
612 | ++I2; | |||
613 | if (!I1->isIdenticalTo(*I2, Check)) | |||
614 | return false; | |||
615 | } | |||
616 | // If we've reached the end of just one of the two bundles, but not both, | |||
617 | // the instructions are not identical. | |||
618 | if (I1->isBundledWithSucc() || I2->isBundledWithSucc()) | |||
619 | return false; | |||
620 | } | |||
621 | ||||
622 | // Check operands to make sure they match. | |||
623 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
624 | const MachineOperand &MO = getOperand(i); | |||
625 | const MachineOperand &OMO = Other.getOperand(i); | |||
626 | if (!MO.isReg()) { | |||
627 | if (!MO.isIdenticalTo(OMO)) | |||
628 | return false; | |||
629 | continue; | |||
630 | } | |||
631 | ||||
632 | // Clients may or may not want to ignore defs when testing for equality. | |||
633 | // For example, machine CSE pass only cares about finding common | |||
634 | // subexpressions, so it's safe to ignore virtual register defs. | |||
635 | if (MO.isDef()) { | |||
636 | if (Check == IgnoreDefs) | |||
637 | continue; | |||
638 | else if (Check == IgnoreVRegDefs) { | |||
639 | if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) || | |||
640 | !TargetRegisterInfo::isVirtualRegister(OMO.getReg())) | |||
641 | if (!MO.isIdenticalTo(OMO)) | |||
642 | return false; | |||
643 | } else { | |||
644 | if (!MO.isIdenticalTo(OMO)) | |||
645 | return false; | |||
646 | if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) | |||
647 | return false; | |||
648 | } | |||
649 | } else { | |||
650 | if (!MO.isIdenticalTo(OMO)) | |||
651 | return false; | |||
652 | if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) | |||
653 | return false; | |||
654 | } | |||
655 | } | |||
656 | // If DebugLoc does not match then two debug instructions are not identical. | |||
657 | if (isDebugInstr()) | |||
658 | if (getDebugLoc() && Other.getDebugLoc() && | |||
659 | getDebugLoc() != Other.getDebugLoc()) | |||
660 | return false; | |||
661 | return true; | |||
662 | } | |||
663 | ||||
664 | const MachineFunction *MachineInstr::getMF() const { | |||
665 | return getParent()->getParent(); | |||
666 | } | |||
667 | ||||
668 | MachineInstr *MachineInstr::removeFromParent() { | |||
669 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 669, __PRETTY_FUNCTION__)); | |||
670 | return getParent()->remove(this); | |||
671 | } | |||
672 | ||||
673 | MachineInstr *MachineInstr::removeFromBundle() { | |||
674 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 674, __PRETTY_FUNCTION__)); | |||
675 | return getParent()->remove_instr(this); | |||
676 | } | |||
677 | ||||
678 | void MachineInstr::eraseFromParent() { | |||
679 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 679, __PRETTY_FUNCTION__)); | |||
680 | getParent()->erase(this); | |||
681 | } | |||
682 | ||||
683 | void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() { | |||
684 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 684, __PRETTY_FUNCTION__)); | |||
685 | MachineBasicBlock *MBB = getParent(); | |||
686 | MachineFunction *MF = MBB->getParent(); | |||
687 | assert(MF && "Not embedded in a function!")((MF && "Not embedded in a function!") ? static_cast< void> (0) : __assert_fail ("MF && \"Not embedded in a function!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 687, __PRETTY_FUNCTION__)); | |||
688 | ||||
689 | MachineInstr *MI = (MachineInstr *)this; | |||
690 | MachineRegisterInfo &MRI = MF->getRegInfo(); | |||
691 | ||||
692 | for (const MachineOperand &MO : MI->operands()) { | |||
693 | if (!MO.isReg() || !MO.isDef()) | |||
694 | continue; | |||
695 | unsigned Reg = MO.getReg(); | |||
696 | if (!TargetRegisterInfo::isVirtualRegister(Reg)) | |||
697 | continue; | |||
698 | MRI.markUsesInDebugValueAsUndef(Reg); | |||
699 | } | |||
700 | MI->eraseFromParent(); | |||
701 | } | |||
702 | ||||
703 | void MachineInstr::eraseFromBundle() { | |||
704 | assert(getParent() && "Not embedded in a basic block!")((getParent() && "Not embedded in a basic block!") ? static_cast <void> (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 704, __PRETTY_FUNCTION__)); | |||
705 | getParent()->erase_instr(this); | |||
706 | } | |||
707 | ||||
708 | unsigned MachineInstr::getNumExplicitOperands() const { | |||
709 | unsigned NumOperands = MCID->getNumOperands(); | |||
710 | if (!MCID->isVariadic()) | |||
711 | return NumOperands; | |||
712 | ||||
713 | for (unsigned I = NumOperands, E = getNumOperands(); I != E; ++I) { | |||
714 | const MachineOperand &MO = getOperand(I); | |||
715 | // The operands must always be in the following order: | |||
716 | // - explicit reg defs, | |||
717 | // - other explicit operands (reg uses, immediates, etc.), | |||
718 | // - implicit reg defs | |||
719 | // - implicit reg uses | |||
720 | if (MO.isReg() && MO.isImplicit()) | |||
721 | break; | |||
722 | ++NumOperands; | |||
723 | } | |||
724 | return NumOperands; | |||
725 | } | |||
726 | ||||
727 | unsigned MachineInstr::getNumExplicitDefs() const { | |||
728 | unsigned NumDefs = MCID->getNumDefs(); | |||
729 | if (!MCID->isVariadic()) | |||
730 | return NumDefs; | |||
731 | ||||
732 | for (unsigned I = NumDefs, E = getNumOperands(); I != E; ++I) { | |||
733 | const MachineOperand &MO = getOperand(I); | |||
734 | if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) | |||
735 | break; | |||
736 | ++NumDefs; | |||
737 | } | |||
738 | return NumDefs; | |||
739 | } | |||
740 | ||||
741 | void MachineInstr::bundleWithPred() { | |||
742 | assert(!isBundledWithPred() && "MI is already bundled with its predecessor")((!isBundledWithPred() && "MI is already bundled with its predecessor" ) ? static_cast<void> (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 742, __PRETTY_FUNCTION__)); | |||
743 | setFlag(BundledPred); | |||
744 | MachineBasicBlock::instr_iterator Pred = getIterator(); | |||
745 | --Pred; | |||
746 | assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")((!Pred->isBundledWithSucc() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 746, __PRETTY_FUNCTION__)); | |||
747 | Pred->setFlag(BundledSucc); | |||
748 | } | |||
749 | ||||
750 | void MachineInstr::bundleWithSucc() { | |||
751 | assert(!isBundledWithSucc() && "MI is already bundled with its successor")((!isBundledWithSucc() && "MI is already bundled with its successor" ) ? static_cast<void> (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 751, __PRETTY_FUNCTION__)); | |||
752 | setFlag(BundledSucc); | |||
753 | MachineBasicBlock::instr_iterator Succ = getIterator(); | |||
754 | ++Succ; | |||
755 | assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")((!Succ->isBundledWithPred() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 755, __PRETTY_FUNCTION__)); | |||
756 | Succ->setFlag(BundledPred); | |||
757 | } | |||
758 | ||||
759 | void MachineInstr::unbundleFromPred() { | |||
760 | assert(isBundledWithPred() && "MI isn't bundled with its predecessor")((isBundledWithPred() && "MI isn't bundled with its predecessor" ) ? static_cast<void> (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 760, __PRETTY_FUNCTION__)); | |||
761 | clearFlag(BundledPred); | |||
762 | MachineBasicBlock::instr_iterator Pred = getIterator(); | |||
763 | --Pred; | |||
764 | assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")((Pred->isBundledWithSucc() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 764, __PRETTY_FUNCTION__)); | |||
765 | Pred->clearFlag(BundledSucc); | |||
766 | } | |||
767 | ||||
768 | void MachineInstr::unbundleFromSucc() { | |||
769 | assert(isBundledWithSucc() && "MI isn't bundled with its successor")((isBundledWithSucc() && "MI isn't bundled with its successor" ) ? static_cast<void> (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 769, __PRETTY_FUNCTION__)); | |||
770 | clearFlag(BundledSucc); | |||
771 | MachineBasicBlock::instr_iterator Succ = getIterator(); | |||
772 | ++Succ; | |||
773 | assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")((Succ->isBundledWithPred() && "Inconsistent bundle flags" ) ? static_cast<void> (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 773, __PRETTY_FUNCTION__)); | |||
774 | Succ->clearFlag(BundledPred); | |||
775 | } | |||
776 | ||||
777 | bool MachineInstr::isStackAligningInlineAsm() const { | |||
778 | if (isInlineAsm()) { | |||
779 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | |||
780 | if (ExtraInfo & InlineAsm::Extra_IsAlignStack) | |||
781 | return true; | |||
782 | } | |||
783 | return false; | |||
784 | } | |||
785 | ||||
786 | InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const { | |||
787 | assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")((isInlineAsm() && "getInlineAsmDialect() only works for inline asms!" ) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 787, __PRETTY_FUNCTION__)); | |||
788 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | |||
789 | return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0); | |||
790 | } | |||
791 | ||||
792 | int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, | |||
793 | unsigned *GroupNo) const { | |||
794 | assert(isInlineAsm() && "Expected an inline asm instruction")((isInlineAsm() && "Expected an inline asm instruction" ) ? static_cast<void> (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 794, __PRETTY_FUNCTION__)); | |||
795 | assert(OpIdx < getNumOperands() && "OpIdx out of range")((OpIdx < getNumOperands() && "OpIdx out of range" ) ? static_cast<void> (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 795, __PRETTY_FUNCTION__)); | |||
796 | ||||
797 | // Ignore queries about the initial operands. | |||
798 | if (OpIdx < InlineAsm::MIOp_FirstOperand) | |||
799 | return -1; | |||
800 | ||||
801 | unsigned Group = 0; | |||
802 | unsigned NumOps; | |||
803 | for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; | |||
804 | i += NumOps) { | |||
805 | const MachineOperand &FlagMO = getOperand(i); | |||
806 | // If we reach the implicit register operands, stop looking. | |||
807 | if (!FlagMO.isImm()) | |||
808 | return -1; | |||
809 | NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); | |||
810 | if (i + NumOps > OpIdx) { | |||
811 | if (GroupNo) | |||
812 | *GroupNo = Group; | |||
813 | return i; | |||
814 | } | |||
815 | ++Group; | |||
816 | } | |||
817 | return -1; | |||
818 | } | |||
819 | ||||
820 | const DILabel *MachineInstr::getDebugLabel() const { | |||
821 | assert(isDebugLabel() && "not a DBG_LABEL")((isDebugLabel() && "not a DBG_LABEL") ? static_cast< void> (0) : __assert_fail ("isDebugLabel() && \"not a DBG_LABEL\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 821, __PRETTY_FUNCTION__)); | |||
822 | return cast<DILabel>(getOperand(0).getMetadata()); | |||
823 | } | |||
824 | ||||
825 | const DILocalVariable *MachineInstr::getDebugVariable() const { | |||
826 | assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast< void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 826, __PRETTY_FUNCTION__)); | |||
827 | return cast<DILocalVariable>(getOperand(2).getMetadata()); | |||
828 | } | |||
829 | ||||
830 | const DIExpression *MachineInstr::getDebugExpression() const { | |||
831 | assert(isDebugValue() && "not a DBG_VALUE")((isDebugValue() && "not a DBG_VALUE") ? static_cast< void> (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 831, __PRETTY_FUNCTION__)); | |||
832 | return cast<DIExpression>(getOperand(3).getMetadata()); | |||
833 | } | |||
834 | ||||
835 | const TargetRegisterClass* | |||
836 | MachineInstr::getRegClassConstraint(unsigned OpIdx, | |||
837 | const TargetInstrInfo *TII, | |||
838 | const TargetRegisterInfo *TRI) const { | |||
839 | assert(getParent() && "Can't have an MBB reference here!")((getParent() && "Can't have an MBB reference here!") ? static_cast<void> (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 839, __PRETTY_FUNCTION__)); | |||
840 | assert(getMF() && "Can't have an MF reference here!")((getMF() && "Can't have an MF reference here!") ? static_cast <void> (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 840, __PRETTY_FUNCTION__)); | |||
841 | const MachineFunction &MF = *getMF(); | |||
842 | ||||
843 | // Most opcodes have fixed constraints in their MCInstrDesc. | |||
844 | if (!isInlineAsm()) | |||
845 | return TII->getRegClass(getDesc(), OpIdx, TRI, MF); | |||
846 | ||||
847 | if (!getOperand(OpIdx).isReg()) | |||
848 | return nullptr; | |||
849 | ||||
850 | // For tied uses on inline asm, get the constraint from the def. | |||
851 | unsigned DefIdx; | |||
852 | if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) | |||
853 | OpIdx = DefIdx; | |||
854 | ||||
855 | // Inline asm stores register class constraints in the flag word. | |||
856 | int FlagIdx = findInlineAsmFlagIdx(OpIdx); | |||
857 | if (FlagIdx < 0) | |||
858 | return nullptr; | |||
859 | ||||
860 | unsigned Flag = getOperand(FlagIdx).getImm(); | |||
861 | unsigned RCID; | |||
862 | if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse || | |||
863 | InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef || | |||
864 | InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && | |||
865 | InlineAsm::hasRegClassConstraint(Flag, RCID)) | |||
866 | return TRI->getRegClass(RCID); | |||
867 | ||||
868 | // Assume that all registers in a memory operand are pointers. | |||
869 | if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem) | |||
870 | return TRI->getPointerRegClass(MF); | |||
871 | ||||
872 | return nullptr; | |||
873 | } | |||
874 | ||||
875 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg( | |||
876 | unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII, | |||
877 | const TargetRegisterInfo *TRI, bool ExploreBundle) const { | |||
878 | // Check every operands inside the bundle if we have | |||
879 | // been asked to. | |||
880 | if (ExploreBundle) | |||
881 | for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC; | |||
882 | ++OpndIt) | |||
883 | CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl( | |||
884 | OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); | |||
885 | else | |||
886 | // Otherwise, just check the current operands. | |||
887 | for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i) | |||
888 | CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI); | |||
889 | return CurRC; | |||
890 | } | |||
891 | ||||
892 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl( | |||
893 | unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, | |||
894 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { | |||
895 | assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast <void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 895, __PRETTY_FUNCTION__)); | |||
896 | // Check if Reg is constrained by some of its use/def from MI. | |||
897 | const MachineOperand &MO = getOperand(OpIdx); | |||
898 | if (!MO.isReg() || MO.getReg() != Reg) | |||
899 | return CurRC; | |||
900 | // If yes, accumulate the constraints through the operand. | |||
901 | return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI); | |||
902 | } | |||
903 | ||||
904 | const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect( | |||
905 | unsigned OpIdx, const TargetRegisterClass *CurRC, | |||
906 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const { | |||
907 | const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); | |||
908 | const MachineOperand &MO = getOperand(OpIdx); | |||
909 | assert(MO.isReg() &&((MO.isReg() && "Cannot get register constraints for non-register operand" ) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 910, __PRETTY_FUNCTION__)) | |||
910 | "Cannot get register constraints for non-register operand")((MO.isReg() && "Cannot get register constraints for non-register operand" ) ? static_cast<void> (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 910, __PRETTY_FUNCTION__)); | |||
911 | assert(CurRC && "Invalid initial register class")((CurRC && "Invalid initial register class") ? static_cast <void> (0) : __assert_fail ("CurRC && \"Invalid initial register class\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 911, __PRETTY_FUNCTION__)); | |||
912 | if (unsigned SubIdx = MO.getSubReg()) { | |||
913 | if (OpRC) | |||
914 | CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); | |||
915 | else | |||
916 | CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); | |||
917 | } else if (OpRC) | |||
918 | CurRC = TRI->getCommonSubClass(CurRC, OpRC); | |||
919 | return CurRC; | |||
920 | } | |||
921 | ||||
922 | /// Return the number of instructions inside the MI bundle, not counting the | |||
923 | /// header instruction. | |||
924 | unsigned MachineInstr::getBundleSize() const { | |||
925 | MachineBasicBlock::const_instr_iterator I = getIterator(); | |||
926 | unsigned Size = 0; | |||
927 | while (I->isBundledWithSucc()) { | |||
928 | ++Size; | |||
929 | ++I; | |||
930 | } | |||
931 | return Size; | |||
932 | } | |||
933 | ||||
934 | /// Returns true if the MachineInstr has an implicit-use operand of exactly | |||
935 | /// the given register (not considering sub/super-registers). | |||
936 | bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const { | |||
937 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
938 | const MachineOperand &MO = getOperand(i); | |||
939 | if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) | |||
940 | return true; | |||
941 | } | |||
942 | return false; | |||
943 | } | |||
944 | ||||
945 | /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of | |||
946 | /// the specific register or -1 if it is not found. It further tightens | |||
947 | /// the search criteria to a use that kills the register if isKill is true. | |||
948 | int MachineInstr::findRegisterUseOperandIdx( | |||
949 | unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const { | |||
950 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
951 | const MachineOperand &MO = getOperand(i); | |||
952 | if (!MO.isReg() || !MO.isUse()) | |||
953 | continue; | |||
954 | unsigned MOReg = MO.getReg(); | |||
955 | if (!MOReg) | |||
956 | continue; | |||
957 | if (MOReg == Reg || (TRI && Reg && MOReg && TRI->regsOverlap(MOReg, Reg))) | |||
958 | if (!isKill || MO.isKill()) | |||
959 | return i; | |||
960 | } | |||
961 | return -1; | |||
962 | } | |||
963 | ||||
964 | /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) | |||
965 | /// indicating if this instruction reads or writes Reg. This also considers | |||
966 | /// partial defines. | |||
967 | std::pair<bool,bool> | |||
968 | MachineInstr::readsWritesVirtualRegister(unsigned Reg, | |||
969 | SmallVectorImpl<unsigned> *Ops) const { | |||
970 | bool PartDef = false; // Partial redefine. | |||
971 | bool FullDef = false; // Full define. | |||
972 | bool Use = false; | |||
973 | ||||
974 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
975 | const MachineOperand &MO = getOperand(i); | |||
976 | if (!MO.isReg() || MO.getReg() != Reg) | |||
977 | continue; | |||
978 | if (Ops) | |||
979 | Ops->push_back(i); | |||
980 | if (MO.isUse()) | |||
981 | Use |= !MO.isUndef(); | |||
982 | else if (MO.getSubReg() && !MO.isUndef()) | |||
983 | // A partial def undef doesn't count as reading the register. | |||
984 | PartDef = true; | |||
985 | else | |||
986 | FullDef = true; | |||
987 | } | |||
988 | // A partial redefine uses Reg unless there is also a full define. | |||
989 | return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef); | |||
990 | } | |||
991 | ||||
992 | /// findRegisterDefOperandIdx() - Returns the operand index that is a def of | |||
993 | /// the specified register or -1 if it is not found. If isDead is true, defs | |||
994 | /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it | |||
995 | /// also checks if there is a def of a super-register. | |||
996 | int | |||
997 | MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap, | |||
998 | const TargetRegisterInfo *TRI) const { | |||
999 | bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg); | |||
1000 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
1001 | const MachineOperand &MO = getOperand(i); | |||
1002 | // Accept regmask operands when Overlap is set. | |||
1003 | // Ignore them when looking for a specific def operand (Overlap == false). | |||
1004 | if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) | |||
1005 | return i; | |||
1006 | if (!MO.isReg() || !MO.isDef()) | |||
1007 | continue; | |||
1008 | unsigned MOReg = MO.getReg(); | |||
1009 | bool Found = (MOReg == Reg); | |||
1010 | if (!Found && TRI && isPhys && | |||
1011 | TargetRegisterInfo::isPhysicalRegister(MOReg)) { | |||
1012 | if (Overlap) | |||
1013 | Found = TRI->regsOverlap(MOReg, Reg); | |||
1014 | else | |||
1015 | Found = TRI->isSubRegister(MOReg, Reg); | |||
1016 | } | |||
1017 | if (Found && (!isDead || MO.isDead())) | |||
1018 | return i; | |||
1019 | } | |||
1020 | return -1; | |||
1021 | } | |||
1022 | ||||
1023 | /// findFirstPredOperandIdx() - Find the index of the first operand in the | |||
1024 | /// operand list that is used to represent the predicate. It returns -1 if | |||
1025 | /// none is found. | |||
1026 | int MachineInstr::findFirstPredOperandIdx() const { | |||
1027 | // Don't call MCID.findFirstPredOperandIdx() because this variant | |||
1028 | // is sometimes called on an instruction that's not yet complete, and | |||
1029 | // so the number of operands is less than the MCID indicates. In | |||
1030 | // particular, the PTX target does this. | |||
1031 | const MCInstrDesc &MCID = getDesc(); | |||
1032 | if (MCID.isPredicable()) { | |||
1033 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) | |||
1034 | if (MCID.OpInfo[i].isPredicate()) | |||
1035 | return i; | |||
1036 | } | |||
1037 | ||||
1038 | return -1; | |||
1039 | } | |||
1040 | ||||
1041 | // MachineOperand::TiedTo is 4 bits wide. | |||
1042 | const unsigned TiedMax = 15; | |||
1043 | ||||
1044 | /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. | |||
1045 | /// | |||
1046 | /// Use and def operands can be tied together, indicated by a non-zero TiedTo | |||
1047 | /// field. TiedTo can have these values: | |||
1048 | /// | |||
1049 | /// 0: Operand is not tied to anything. | |||
1050 | /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1). | |||
1051 | /// TiedMax: Tied to an operand >= TiedMax-1. | |||
1052 | /// | |||
1053 | /// The tied def must be one of the first TiedMax operands on a normal | |||
1054 | /// instruction. INLINEASM instructions allow more tied defs. | |||
1055 | /// | |||
1056 | void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { | |||
1057 | MachineOperand &DefMO = getOperand(DefIdx); | |||
1058 | MachineOperand &UseMO = getOperand(UseIdx); | |||
1059 | assert(DefMO.isDef() && "DefIdx must be a def operand")((DefMO.isDef() && "DefIdx must be a def operand") ? static_cast <void> (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1059, __PRETTY_FUNCTION__)); | |||
1060 | assert(UseMO.isUse() && "UseIdx must be a use operand")((UseMO.isUse() && "UseIdx must be a use operand") ? static_cast <void> (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1060, __PRETTY_FUNCTION__)); | |||
1061 | assert(!DefMO.isTied() && "Def is already tied to another use")((!DefMO.isTied() && "Def is already tied to another use" ) ? static_cast<void> (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1061, __PRETTY_FUNCTION__)); | |||
1062 | assert(!UseMO.isTied() && "Use is already tied to another def")((!UseMO.isTied() && "Use is already tied to another def" ) ? static_cast<void> (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1062, __PRETTY_FUNCTION__)); | |||
1063 | ||||
1064 | if (DefIdx < TiedMax) | |||
1065 | UseMO.TiedTo = DefIdx + 1; | |||
1066 | else { | |||
1067 | // Inline asm can use the group descriptors to find tied operands, but on | |||
1068 | // normal instruction, the tied def must be within the first TiedMax | |||
1069 | // operands. | |||
1070 | assert(isInlineAsm() && "DefIdx out of range")((isInlineAsm() && "DefIdx out of range") ? static_cast <void> (0) : __assert_fail ("isInlineAsm() && \"DefIdx out of range\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1070, __PRETTY_FUNCTION__)); | |||
1071 | UseMO.TiedTo = TiedMax; | |||
1072 | } | |||
1073 | ||||
1074 | // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). | |||
1075 | DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); | |||
1076 | } | |||
1077 | ||||
1078 | /// Given the index of a tied register operand, find the operand it is tied to. | |||
1079 | /// Defs are tied to uses and vice versa. Returns the index of the tied operand | |||
1080 | /// which must exist. | |||
1081 | unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const { | |||
1082 | const MachineOperand &MO = getOperand(OpIdx); | |||
1083 | assert(MO.isTied() && "Operand isn't tied")((MO.isTied() && "Operand isn't tied") ? static_cast< void> (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1083, __PRETTY_FUNCTION__)); | |||
1084 | ||||
1085 | // Normally TiedTo is in range. | |||
1086 | if (MO.TiedTo < TiedMax) | |||
1087 | return MO.TiedTo - 1; | |||
1088 | ||||
1089 | // Uses on normal instructions can be out of range. | |||
1090 | if (!isInlineAsm()) { | |||
1091 | // Normal tied defs must be in the 0..TiedMax-1 range. | |||
1092 | if (MO.isUse()) | |||
1093 | return TiedMax - 1; | |||
1094 | // MO is a def. Search for the tied use. | |||
1095 | for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) { | |||
1096 | const MachineOperand &UseMO = getOperand(i); | |||
1097 | if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) | |||
1098 | return i; | |||
1099 | } | |||
1100 | llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1100); | |||
1101 | } | |||
1102 | ||||
1103 | // Now deal with inline asm by parsing the operand group descriptor flags. | |||
1104 | // Find the beginning of each operand group. | |||
1105 | SmallVector<unsigned, 8> GroupIdx; | |||
1106 | unsigned OpIdxGroup = ~0u; | |||
1107 | unsigned NumOps; | |||
1108 | for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e; | |||
1109 | i += NumOps) { | |||
1110 | const MachineOperand &FlagMO = getOperand(i); | |||
1111 | assert(FlagMO.isImm() && "Invalid tied operand on inline asm")((FlagMO.isImm() && "Invalid tied operand on inline asm" ) ? static_cast<void> (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1111, __PRETTY_FUNCTION__)); | |||
1112 | unsigned CurGroup = GroupIdx.size(); | |||
1113 | GroupIdx.push_back(i); | |||
1114 | NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm()); | |||
1115 | // OpIdx belongs to this operand group. | |||
1116 | if (OpIdx > i && OpIdx < i + NumOps) | |||
1117 | OpIdxGroup = CurGroup; | |||
1118 | unsigned TiedGroup; | |||
1119 | if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup)) | |||
1120 | continue; | |||
1121 | // Operands in this group are tied to operands in TiedGroup which must be | |||
1122 | // earlier. Find the number of operands between the two groups. | |||
1123 | unsigned Delta = i - GroupIdx[TiedGroup]; | |||
1124 | ||||
1125 | // OpIdx is a use tied to TiedGroup. | |||
1126 | if (OpIdxGroup == CurGroup) | |||
1127 | return OpIdx - Delta; | |||
1128 | ||||
1129 | // OpIdx is a def tied to this use group. | |||
1130 | if (OpIdxGroup == TiedGroup) | |||
1131 | return OpIdx + Delta; | |||
1132 | } | |||
1133 | llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1133); | |||
1134 | } | |||
1135 | ||||
1136 | /// clearKillInfo - Clears kill flags on all operands. | |||
1137 | /// | |||
1138 | void MachineInstr::clearKillInfo() { | |||
1139 | for (MachineOperand &MO : operands()) { | |||
1140 | if (MO.isReg() && MO.isUse()) | |||
1141 | MO.setIsKill(false); | |||
1142 | } | |||
1143 | } | |||
1144 | ||||
1145 | void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg, | |||
1146 | unsigned SubIdx, | |||
1147 | const TargetRegisterInfo &RegInfo) { | |||
1148 | if (TargetRegisterInfo::isPhysicalRegister(ToReg)) { | |||
1149 | if (SubIdx) | |||
1150 | ToReg = RegInfo.getSubReg(ToReg, SubIdx); | |||
1151 | for (MachineOperand &MO : operands()) { | |||
1152 | if (!MO.isReg() || MO.getReg() != FromReg) | |||
1153 | continue; | |||
1154 | MO.substPhysReg(ToReg, RegInfo); | |||
1155 | } | |||
1156 | } else { | |||
1157 | for (MachineOperand &MO : operands()) { | |||
1158 | if (!MO.isReg() || MO.getReg() != FromReg) | |||
1159 | continue; | |||
1160 | MO.substVirtReg(ToReg, SubIdx, RegInfo); | |||
1161 | } | |||
1162 | } | |||
1163 | } | |||
1164 | ||||
1165 | /// isSafeToMove - Return true if it is safe to move this instruction. If | |||
1166 | /// SawStore is set to true, it means that there is a store (or call) between | |||
1167 | /// the instruction's location and its intended destination. | |||
1168 | bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const { | |||
1169 | // Ignore stuff that we obviously can't move. | |||
1170 | // | |||
1171 | // Treat volatile loads as stores. This is not strictly necessary for | |||
1172 | // volatiles, but it is required for atomic loads. It is not allowed to move | |||
1173 | // a load across an atomic load with Ordering > Monotonic. | |||
1174 | if (mayStore() || isCall() || isPHI() || | |||
1175 | (mayLoad() && hasOrderedMemoryRef())) { | |||
1176 | SawStore = true; | |||
1177 | return false; | |||
1178 | } | |||
1179 | ||||
1180 | if (isPosition() || isDebugInstr() || isTerminator() || | |||
1181 | hasUnmodeledSideEffects()) | |||
1182 | return false; | |||
1183 | ||||
1184 | // See if this instruction does a load. If so, we have to guarantee that the | |||
1185 | // loaded value doesn't change between the load and the its intended | |||
1186 | // destination. The check for isInvariantLoad gives the targe the chance to | |||
1187 | // classify the load as always returning a constant, e.g. a constant pool | |||
1188 | // load. | |||
1189 | if (mayLoad() && !isDereferenceableInvariantLoad(AA)) | |||
1190 | // Otherwise, this is a real load. If there is a store between the load and | |||
1191 | // end of block, we can't move it. | |||
1192 | return !SawStore; | |||
1193 | ||||
1194 | return true; | |||
1195 | } | |||
1196 | ||||
1197 | bool MachineInstr::mayAlias(AliasAnalysis *AA, const MachineInstr &Other, | |||
1198 | bool UseTBAA) const { | |||
1199 | const MachineFunction *MF = getMF(); | |||
1200 | const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); | |||
1201 | const MachineFrameInfo &MFI = MF->getFrameInfo(); | |||
1202 | ||||
1203 | // If neither instruction stores to memory, they can't alias in any | |||
1204 | // meaningful way, even if they read from the same address. | |||
1205 | if (!mayStore() && !Other.mayStore()) | |||
1206 | return false; | |||
1207 | ||||
1208 | // Let the target decide if memory accesses cannot possibly overlap. | |||
1209 | if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA)) | |||
1210 | return false; | |||
1211 | ||||
1212 | // FIXME: Need to handle multiple memory operands to support all targets. | |||
1213 | if (!hasOneMemOperand() || !Other.hasOneMemOperand()) | |||
1214 | return true; | |||
1215 | ||||
1216 | MachineMemOperand *MMOa = *memoperands_begin(); | |||
1217 | MachineMemOperand *MMOb = *Other.memoperands_begin(); | |||
1218 | ||||
1219 | // The following interface to AA is fashioned after DAGCombiner::isAlias | |||
1220 | // and operates with MachineMemOperand offset with some important | |||
1221 | // assumptions: | |||
1222 | // - LLVM fundamentally assumes flat address spaces. | |||
1223 | // - MachineOperand offset can *only* result from legalization and | |||
1224 | // cannot affect queries other than the trivial case of overlap | |||
1225 | // checking. | |||
1226 | // - These offsets never wrap and never step outside | |||
1227 | // of allocated objects. | |||
1228 | // - There should never be any negative offsets here. | |||
1229 | // | |||
1230 | // FIXME: Modify API to hide this math from "user" | |||
1231 | // Even before we go to AA we can reason locally about some | |||
1232 | // memory objects. It can save compile time, and possibly catch some | |||
1233 | // corner cases not currently covered. | |||
1234 | ||||
1235 | int64_t OffsetA = MMOa->getOffset(); | |||
1236 | int64_t OffsetB = MMOb->getOffset(); | |||
1237 | int64_t MinOffset = std::min(OffsetA, OffsetB); | |||
1238 | ||||
1239 | uint64_t WidthA = MMOa->getSize(); | |||
1240 | uint64_t WidthB = MMOb->getSize(); | |||
1241 | bool KnownWidthA = WidthA != MemoryLocation::UnknownSize; | |||
1242 | bool KnownWidthB = WidthB != MemoryLocation::UnknownSize; | |||
1243 | ||||
1244 | const Value *ValA = MMOa->getValue(); | |||
1245 | const Value *ValB = MMOb->getValue(); | |||
1246 | bool SameVal = (ValA && ValB && (ValA == ValB)); | |||
1247 | if (!SameVal) { | |||
1248 | const PseudoSourceValue *PSVa = MMOa->getPseudoValue(); | |||
1249 | const PseudoSourceValue *PSVb = MMOb->getPseudoValue(); | |||
1250 | if (PSVa && ValB && !PSVa->mayAlias(&MFI)) | |||
1251 | return false; | |||
1252 | if (PSVb && ValA && !PSVb->mayAlias(&MFI)) | |||
1253 | return false; | |||
1254 | if (PSVa && PSVb && (PSVa == PSVb)) | |||
1255 | SameVal = true; | |||
1256 | } | |||
1257 | ||||
1258 | if (SameVal) { | |||
1259 | if (!KnownWidthA || !KnownWidthB) | |||
1260 | return true; | |||
1261 | int64_t MaxOffset = std::max(OffsetA, OffsetB); | |||
1262 | int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB; | |||
1263 | return (MinOffset + LowWidth > MaxOffset); | |||
1264 | } | |||
1265 | ||||
1266 | if (!AA) | |||
1267 | return true; | |||
1268 | ||||
1269 | if (!ValA || !ValB) | |||
1270 | return true; | |||
1271 | ||||
1272 | assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(((OffsetA >= 0) && "Negative MachineMemOperand offset" ) ? static_cast<void> (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1272, __PRETTY_FUNCTION__)); | |||
1273 | assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(((OffsetB >= 0) && "Negative MachineMemOperand offset" ) ? static_cast<void> (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1273, __PRETTY_FUNCTION__)); | |||
1274 | ||||
1275 | int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset | |||
1276 | : MemoryLocation::UnknownSize; | |||
1277 | int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset | |||
1278 | : MemoryLocation::UnknownSize; | |||
1279 | ||||
1280 | AliasResult AAResult = AA->alias( | |||
1281 | MemoryLocation(ValA, OverlapA, | |||
1282 | UseTBAA ? MMOa->getAAInfo() : AAMDNodes()), | |||
1283 | MemoryLocation(ValB, OverlapB, | |||
1284 | UseTBAA ? MMOb->getAAInfo() : AAMDNodes())); | |||
1285 | ||||
1286 | return (AAResult != NoAlias); | |||
1287 | } | |||
1288 | ||||
1289 | /// hasOrderedMemoryRef - Return true if this instruction may have an ordered | |||
1290 | /// or volatile memory reference, or if the information describing the memory | |||
1291 | /// reference is not available. Return false if it is known to have no ordered | |||
1292 | /// memory references. | |||
1293 | bool MachineInstr::hasOrderedMemoryRef() const { | |||
1294 | // An instruction known never to access memory won't have a volatile access. | |||
1295 | if (!mayStore() && | |||
1296 | !mayLoad() && | |||
1297 | !isCall() && | |||
1298 | !hasUnmodeledSideEffects()) | |||
1299 | return false; | |||
1300 | ||||
1301 | // Otherwise, if the instruction has no memory reference information, | |||
1302 | // conservatively assume it wasn't preserved. | |||
1303 | if (memoperands_empty()) | |||
1304 | return true; | |||
1305 | ||||
1306 | // Check if any of our memory operands are ordered. | |||
1307 | return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) { | |||
1308 | return !MMO->isUnordered(); | |||
1309 | }); | |||
1310 | } | |||
1311 | ||||
1312 | /// isDereferenceableInvariantLoad - Return true if this instruction will never | |||
1313 | /// trap and is loading from a location whose value is invariant across a run of | |||
1314 | /// this function. | |||
1315 | bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const { | |||
1316 | // If the instruction doesn't load at all, it isn't an invariant load. | |||
1317 | if (!mayLoad()) | |||
1318 | return false; | |||
1319 | ||||
1320 | // If the instruction has lost its memoperands, conservatively assume that | |||
1321 | // it may not be an invariant load. | |||
1322 | if (memoperands_empty()) | |||
1323 | return false; | |||
1324 | ||||
1325 | const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo(); | |||
1326 | ||||
1327 | for (MachineMemOperand *MMO : memoperands()) { | |||
1328 | if (!MMO->isUnordered()) | |||
1329 | // If the memory operand has ordering side effects, we can't move the | |||
1330 | // instruction. Such an instruction is technically an invariant load, | |||
1331 | // but the caller code would need updated to expect that. | |||
1332 | return false; | |||
1333 | if (MMO->isStore()) return false; | |||
1334 | if (MMO->isInvariant() && MMO->isDereferenceable()) | |||
1335 | continue; | |||
1336 | ||||
1337 | // A load from a constant PseudoSourceValue is invariant. | |||
1338 | if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) | |||
1339 | if (PSV->isConstant(&MFI)) | |||
1340 | continue; | |||
1341 | ||||
1342 | if (const Value *V = MMO->getValue()) { | |||
1343 | // If we have an AliasAnalysis, ask it whether the memory is constant. | |||
1344 | if (AA && | |||
1345 | AA->pointsToConstantMemory( | |||
1346 | MemoryLocation(V, MMO->getSize(), MMO->getAAInfo()))) | |||
1347 | continue; | |||
1348 | } | |||
1349 | ||||
1350 | // Otherwise assume conservatively. | |||
1351 | return false; | |||
1352 | } | |||
1353 | ||||
1354 | // Everything checks out. | |||
1355 | return true; | |||
1356 | } | |||
1357 | ||||
1358 | /// isConstantValuePHI - If the specified instruction is a PHI that always | |||
1359 | /// merges together the same virtual register, return the register, otherwise | |||
1360 | /// return 0. | |||
1361 | unsigned MachineInstr::isConstantValuePHI() const { | |||
1362 | if (!isPHI()) | |||
1363 | return 0; | |||
1364 | assert(getNumOperands() >= 3 &&((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands" ) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1365, __PRETTY_FUNCTION__)) | |||
1365 | "It's illegal to have a PHI without source operands")((getNumOperands() >= 3 && "It's illegal to have a PHI without source operands" ) ? static_cast<void> (0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1365, __PRETTY_FUNCTION__)); | |||
1366 | ||||
1367 | unsigned Reg = getOperand(1).getReg(); | |||
1368 | for (unsigned i = 3, e = getNumOperands(); i < e; i += 2) | |||
1369 | if (getOperand(i).getReg() != Reg) | |||
1370 | return 0; | |||
1371 | return Reg; | |||
1372 | } | |||
1373 | ||||
1374 | bool MachineInstr::hasUnmodeledSideEffects() const { | |||
1375 | if (hasProperty(MCID::UnmodeledSideEffects)) | |||
1376 | return true; | |||
1377 | if (isInlineAsm()) { | |||
1378 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | |||
1379 | if (ExtraInfo & InlineAsm::Extra_HasSideEffects) | |||
1380 | return true; | |||
1381 | } | |||
1382 | ||||
1383 | return false; | |||
1384 | } | |||
1385 | ||||
1386 | bool MachineInstr::isLoadFoldBarrier() const { | |||
1387 | return mayStore() || isCall() || hasUnmodeledSideEffects(); | |||
1388 | } | |||
1389 | ||||
1390 | /// allDefsAreDead - Return true if all the defs of this instruction are dead. | |||
1391 | /// | |||
1392 | bool MachineInstr::allDefsAreDead() const { | |||
1393 | for (const MachineOperand &MO : operands()) { | |||
1394 | if (!MO.isReg() || MO.isUse()) | |||
1395 | continue; | |||
1396 | if (!MO.isDead()) | |||
1397 | return false; | |||
1398 | } | |||
1399 | return true; | |||
1400 | } | |||
1401 | ||||
1402 | /// copyImplicitOps - Copy implicit register operands from specified | |||
1403 | /// instruction to this instruction. | |||
1404 | void MachineInstr::copyImplicitOps(MachineFunction &MF, | |||
1405 | const MachineInstr &MI) { | |||
1406 | for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands(); | |||
1407 | i != e; ++i) { | |||
1408 | const MachineOperand &MO = MI.getOperand(i); | |||
1409 | if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) | |||
1410 | addOperand(MF, MO); | |||
1411 | } | |||
1412 | } | |||
1413 | ||||
1414 | bool MachineInstr::hasComplexRegisterTies() const { | |||
1415 | const MCInstrDesc &MCID = getDesc(); | |||
1416 | for (unsigned I = 0, E = getNumOperands(); I < E; ++I) { | |||
1417 | const auto &Operand = getOperand(I); | |||
1418 | if (!Operand.isReg() || Operand.isDef()) | |||
1419 | // Ignore the defined registers as MCID marks only the uses as tied. | |||
1420 | continue; | |||
1421 | int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO); | |||
1422 | int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1; | |||
1423 | if (ExpectedTiedIdx != TiedIdx) | |||
1424 | return true; | |||
1425 | } | |||
1426 | return false; | |||
1427 | } | |||
1428 | ||||
1429 | LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, | |||
1430 | const MachineRegisterInfo &MRI) const { | |||
1431 | const MachineOperand &Op = getOperand(OpIdx); | |||
1432 | if (!Op.isReg()) | |||
1433 | return LLT{}; | |||
1434 | ||||
1435 | if (isVariadic() || OpIdx >= getNumExplicitOperands()) | |||
1436 | return MRI.getType(Op.getReg()); | |||
1437 | ||||
1438 | auto &OpInfo = getDesc().OpInfo[OpIdx]; | |||
1439 | if (!OpInfo.isGenericType()) | |||
1440 | return MRI.getType(Op.getReg()); | |||
1441 | ||||
1442 | if (PrintedTypes[OpInfo.getGenericTypeIndex()]) | |||
1443 | return LLT{}; | |||
1444 | ||||
1445 | LLT TypeToPrint = MRI.getType(Op.getReg()); | |||
1446 | // Don't mark the type index printed if it wasn't actually printed: maybe | |||
1447 | // another operand with the same type index has an actual type attached: | |||
1448 | if (TypeToPrint.isValid()) | |||
1449 | PrintedTypes.set(OpInfo.getGenericTypeIndex()); | |||
1450 | return TypeToPrint; | |||
1451 | } | |||
1452 | ||||
1453 | #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) | |||
1454 | LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const { | |||
1455 | dbgs() << " "; | |||
1456 | print(dbgs()); | |||
1457 | } | |||
1458 | #endif | |||
1459 | ||||
1460 | void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers, | |||
1461 | bool SkipDebugLoc, bool AddNewLine, | |||
1462 | const TargetInstrInfo *TII) const { | |||
1463 | const Module *M = nullptr; | |||
1464 | const Function *F = nullptr; | |||
1465 | if (const MachineFunction *MF = getMFIfAvailable(*this)) { | |||
1466 | F = &MF->getFunction(); | |||
1467 | M = F->getParent(); | |||
1468 | if (!TII) | |||
1469 | TII = MF->getSubtarget().getInstrInfo(); | |||
1470 | } | |||
1471 | ||||
1472 | ModuleSlotTracker MST(M); | |||
1473 | if (F) | |||
1474 | MST.incorporateFunction(*F); | |||
1475 | print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, AddNewLine, TII); | |||
1476 | } | |||
1477 | ||||
1478 | void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, | |||
1479 | bool IsStandalone, bool SkipOpers, bool SkipDebugLoc, | |||
1480 | bool AddNewLine, const TargetInstrInfo *TII) const { | |||
1481 | // We can be a bit tidier if we know the MachineFunction. | |||
1482 | const MachineFunction *MF = nullptr; | |||
1483 | const TargetRegisterInfo *TRI = nullptr; | |||
1484 | const MachineRegisterInfo *MRI = nullptr; | |||
1485 | const TargetIntrinsicInfo *IntrinsicInfo = nullptr; | |||
1486 | tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII); | |||
1487 | ||||
1488 | if (isCFIInstruction()) | |||
1489 | assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")((getNumOperands() == 1 && "Expected 1 operand in CFI instruction" ) ? static_cast<void> (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 1489, __PRETTY_FUNCTION__)); | |||
1490 | ||||
1491 | SmallBitVector PrintedTypes(8); | |||
1492 | bool ShouldPrintRegisterTies = IsStandalone || hasComplexRegisterTies(); | |||
1493 | auto getTiedOperandIdx = [&](unsigned OpIdx) { | |||
1494 | if (!ShouldPrintRegisterTies) | |||
1495 | return 0U; | |||
1496 | const MachineOperand &MO = getOperand(OpIdx); | |||
1497 | if (MO.isReg() && MO.isTied() && !MO.isDef()) | |||
1498 | return findTiedOperandIdx(OpIdx); | |||
1499 | return 0U; | |||
1500 | }; | |||
1501 | unsigned StartOp = 0; | |||
1502 | unsigned e = getNumOperands(); | |||
1503 | ||||
1504 | // Print explicitly defined operands on the left of an assignment syntax. | |||
1505 | while (StartOp < e) { | |||
1506 | const MachineOperand &MO = getOperand(StartOp); | |||
1507 | if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) | |||
1508 | break; | |||
1509 | ||||
1510 | if (StartOp != 0) | |||
1511 | OS << ", "; | |||
1512 | ||||
1513 | LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{}; | |||
1514 | unsigned TiedOperandIdx = getTiedOperandIdx(StartOp); | |||
1515 | MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone, | |||
1516 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | |||
1517 | ++StartOp; | |||
1518 | } | |||
1519 | ||||
1520 | if (StartOp != 0) | |||
1521 | OS << " = "; | |||
1522 | ||||
1523 | if (getFlag(MachineInstr::FrameSetup)) | |||
1524 | OS << "frame-setup "; | |||
1525 | if (getFlag(MachineInstr::FrameDestroy)) | |||
1526 | OS << "frame-destroy "; | |||
1527 | if (getFlag(MachineInstr::FmNoNans)) | |||
1528 | OS << "nnan "; | |||
1529 | if (getFlag(MachineInstr::FmNoInfs)) | |||
1530 | OS << "ninf "; | |||
1531 | if (getFlag(MachineInstr::FmNsz)) | |||
1532 | OS << "nsz "; | |||
1533 | if (getFlag(MachineInstr::FmArcp)) | |||
1534 | OS << "arcp "; | |||
1535 | if (getFlag(MachineInstr::FmContract)) | |||
1536 | OS << "contract "; | |||
1537 | if (getFlag(MachineInstr::FmAfn)) | |||
1538 | OS << "afn "; | |||
1539 | if (getFlag(MachineInstr::FmReassoc)) | |||
1540 | OS << "reassoc "; | |||
1541 | if (getFlag(MachineInstr::NoUWrap)) | |||
1542 | OS << "nuw "; | |||
1543 | if (getFlag(MachineInstr::NoSWrap)) | |||
1544 | OS << "nsw "; | |||
1545 | if (getFlag(MachineInstr::IsExact)) | |||
1546 | OS << "exact "; | |||
1547 | ||||
1548 | // Print the opcode name. | |||
1549 | if (TII) | |||
1550 | OS << TII->getName(getOpcode()); | |||
1551 | else | |||
1552 | OS << "UNKNOWN"; | |||
1553 | ||||
1554 | if (SkipOpers) | |||
1555 | return; | |||
1556 | ||||
1557 | // Print the rest of the operands. | |||
1558 | bool FirstOp = true; | |||
1559 | unsigned AsmDescOp = ~0u; | |||
1560 | unsigned AsmOpCount = 0; | |||
1561 | ||||
1562 | if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) { | |||
1563 | // Print asm string. | |||
1564 | OS << " "; | |||
1565 | const unsigned OpIdx = InlineAsm::MIOp_AsmString; | |||
1566 | LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{}; | |||
1567 | unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx); | |||
1568 | getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone, | |||
1569 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, | |||
1570 | IntrinsicInfo); | |||
1571 | ||||
1572 | // Print HasSideEffects, MayLoad, MayStore, IsAlignStack | |||
1573 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); | |||
1574 | if (ExtraInfo & InlineAsm::Extra_HasSideEffects) | |||
1575 | OS << " [sideeffect]"; | |||
1576 | if (ExtraInfo & InlineAsm::Extra_MayLoad) | |||
1577 | OS << " [mayload]"; | |||
1578 | if (ExtraInfo & InlineAsm::Extra_MayStore) | |||
1579 | OS << " [maystore]"; | |||
1580 | if (ExtraInfo & InlineAsm::Extra_IsConvergent) | |||
1581 | OS << " [isconvergent]"; | |||
1582 | if (ExtraInfo & InlineAsm::Extra_IsAlignStack) | |||
1583 | OS << " [alignstack]"; | |||
1584 | if (getInlineAsmDialect() == InlineAsm::AD_ATT) | |||
1585 | OS << " [attdialect]"; | |||
1586 | if (getInlineAsmDialect() == InlineAsm::AD_Intel) | |||
1587 | OS << " [inteldialect]"; | |||
1588 | ||||
1589 | StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand; | |||
1590 | FirstOp = false; | |||
1591 | } | |||
1592 | ||||
1593 | for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { | |||
1594 | const MachineOperand &MO = getOperand(i); | |||
1595 | ||||
1596 | if (FirstOp) FirstOp = false; else OS << ","; | |||
1597 | OS << " "; | |||
1598 | ||||
1599 | if (isDebugValue() && MO.isMetadata()) { | |||
1600 | // Pretty print DBG_VALUE instructions. | |||
1601 | auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); | |||
1602 | if (DIV && !DIV->getName().empty()) | |||
1603 | OS << "!\"" << DIV->getName() << '\"'; | |||
1604 | else { | |||
1605 | LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; | |||
1606 | unsigned TiedOperandIdx = getTiedOperandIdx(i); | |||
1607 | MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone, | |||
1608 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | |||
1609 | } | |||
1610 | } else if (isDebugLabel() && MO.isMetadata()) { | |||
1611 | // Pretty print DBG_LABEL instructions. | |||
1612 | auto *DIL = dyn_cast<DILabel>(MO.getMetadata()); | |||
1613 | if (DIL && !DIL->getName().empty()) | |||
1614 | OS << "\"" << DIL->getName() << '\"'; | |||
1615 | else { | |||
1616 | LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; | |||
1617 | unsigned TiedOperandIdx = getTiedOperandIdx(i); | |||
1618 | MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone, | |||
1619 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | |||
1620 | } | |||
1621 | } else if (i == AsmDescOp && MO.isImm()) { | |||
1622 | // Pretty print the inline asm operand descriptor. | |||
1623 | OS << '$' << AsmOpCount++; | |||
1624 | unsigned Flag = MO.getImm(); | |||
1625 | switch (InlineAsm::getKind(Flag)) { | |||
1626 | case InlineAsm::Kind_RegUse: OS << ":[reguse"; break; | |||
1627 | case InlineAsm::Kind_RegDef: OS << ":[regdef"; break; | |||
1628 | case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; | |||
1629 | case InlineAsm::Kind_Clobber: OS << ":[clobber"; break; | |||
1630 | case InlineAsm::Kind_Imm: OS << ":[imm"; break; | |||
1631 | case InlineAsm::Kind_Mem: OS << ":[mem"; break; | |||
1632 | default: OS << ":[??" << InlineAsm::getKind(Flag); break; | |||
1633 | } | |||
1634 | ||||
1635 | unsigned RCID = 0; | |||
1636 | if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) && | |||
1637 | InlineAsm::hasRegClassConstraint(Flag, RCID)) { | |||
1638 | if (TRI) { | |||
1639 | OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); | |||
1640 | } else | |||
1641 | OS << ":RC" << RCID; | |||
1642 | } | |||
1643 | ||||
1644 | if (InlineAsm::isMemKind(Flag)) { | |||
1645 | unsigned MCID = InlineAsm::getMemoryConstraintID(Flag); | |||
1646 | switch (MCID) { | |||
1647 | case InlineAsm::Constraint_es: OS << ":es"; break; | |||
1648 | case InlineAsm::Constraint_i: OS << ":i"; break; | |||
1649 | case InlineAsm::Constraint_m: OS << ":m"; break; | |||
1650 | case InlineAsm::Constraint_o: OS << ":o"; break; | |||
1651 | case InlineAsm::Constraint_v: OS << ":v"; break; | |||
1652 | case InlineAsm::Constraint_Q: OS << ":Q"; break; | |||
1653 | case InlineAsm::Constraint_R: OS << ":R"; break; | |||
1654 | case InlineAsm::Constraint_S: OS << ":S"; break; | |||
1655 | case InlineAsm::Constraint_T: OS << ":T"; break; | |||
1656 | case InlineAsm::Constraint_Um: OS << ":Um"; break; | |||
1657 | case InlineAsm::Constraint_Un: OS << ":Un"; break; | |||
1658 | case InlineAsm::Constraint_Uq: OS << ":Uq"; break; | |||
1659 | case InlineAsm::Constraint_Us: OS << ":Us"; break; | |||
1660 | case InlineAsm::Constraint_Ut: OS << ":Ut"; break; | |||
1661 | case InlineAsm::Constraint_Uv: OS << ":Uv"; break; | |||
1662 | case InlineAsm::Constraint_Uy: OS << ":Uy"; break; | |||
1663 | case InlineAsm::Constraint_X: OS << ":X"; break; | |||
1664 | case InlineAsm::Constraint_Z: OS << ":Z"; break; | |||
1665 | case InlineAsm::Constraint_ZC: OS << ":ZC"; break; | |||
1666 | case InlineAsm::Constraint_Zy: OS << ":Zy"; break; | |||
1667 | default: OS << ":?"; break; | |||
1668 | } | |||
1669 | } | |||
1670 | ||||
1671 | unsigned TiedTo = 0; | |||
1672 | if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) | |||
1673 | OS << " tiedto:$" << TiedTo; | |||
1674 | ||||
1675 | OS << ']'; | |||
1676 | ||||
1677 | // Compute the index of the next operand descriptor. | |||
1678 | AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag); | |||
1679 | } else { | |||
1680 | LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{}; | |||
1681 | unsigned TiedOperandIdx = getTiedOperandIdx(i); | |||
1682 | if (MO.isImm() && isOperandSubregIdx(i)) | |||
1683 | MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI); | |||
1684 | else | |||
1685 | MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone, | |||
1686 | ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo); | |||
1687 | } | |||
1688 | } | |||
1689 | ||||
1690 | // Print any optional symbols attached to this instruction as-if they were | |||
1691 | // operands. | |||
1692 | if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) { | |||
1693 | if (!FirstOp) { | |||
1694 | FirstOp = false; | |||
1695 | OS << ','; | |||
1696 | } | |||
1697 | OS << " pre-instr-symbol "; | |||
1698 | MachineOperand::printSymbol(OS, *PreInstrSymbol); | |||
1699 | } | |||
1700 | if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) { | |||
1701 | if (!FirstOp) { | |||
1702 | FirstOp = false; | |||
1703 | OS << ','; | |||
1704 | } | |||
1705 | OS << " post-instr-symbol "; | |||
1706 | MachineOperand::printSymbol(OS, *PostInstrSymbol); | |||
1707 | } | |||
1708 | ||||
1709 | if (!SkipDebugLoc) { | |||
1710 | if (const DebugLoc &DL = getDebugLoc()) { | |||
1711 | if (!FirstOp) | |||
1712 | OS << ','; | |||
1713 | OS << " debug-location "; | |||
1714 | DL->printAsOperand(OS, MST); | |||
1715 | } | |||
1716 | } | |||
1717 | ||||
1718 | if (!memoperands_empty()) { | |||
1719 | SmallVector<StringRef, 0> SSNs; | |||
1720 | const LLVMContext *Context = nullptr; | |||
1721 | std::unique_ptr<LLVMContext> CtxPtr; | |||
1722 | const MachineFrameInfo *MFI = nullptr; | |||
1723 | if (const MachineFunction *MF = getMFIfAvailable(*this)) { | |||
1724 | MFI = &MF->getFrameInfo(); | |||
1725 | Context = &MF->getFunction().getContext(); | |||
1726 | } else { | |||
1727 | CtxPtr = llvm::make_unique<LLVMContext>(); | |||
1728 | Context = CtxPtr.get(); | |||
1729 | } | |||
1730 | ||||
1731 | OS << " :: "; | |||
1732 | bool NeedComma = false; | |||
1733 | for (const MachineMemOperand *Op : memoperands()) { | |||
1734 | if (NeedComma) | |||
1735 | OS << ", "; | |||
1736 | Op->print(OS, MST, SSNs, *Context, MFI, TII); | |||
1737 | NeedComma = true; | |||
1738 | } | |||
1739 | } | |||
1740 | ||||
1741 | if (SkipDebugLoc) | |||
1742 | return; | |||
1743 | ||||
1744 | bool HaveSemi = false; | |||
1745 | ||||
1746 | // Print debug location information. | |||
1747 | if (const DebugLoc &DL = getDebugLoc()) { | |||
1748 | if (!HaveSemi) { | |||
1749 | OS << ';'; | |||
1750 | HaveSemi = true; | |||
1751 | } | |||
1752 | OS << ' '; | |||
1753 | DL.print(OS); | |||
1754 | } | |||
1755 | ||||
1756 | // Print extra comments for DEBUG_VALUE. | |||
1757 | if (isDebugValue() && getOperand(e - 2).isMetadata()) { | |||
1758 | if (!HaveSemi) { | |||
1759 | OS << ";"; | |||
1760 | HaveSemi = true; | |||
1761 | } | |||
1762 | auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata()); | |||
1763 | OS << " line no:" << DV->getLine(); | |||
1764 | if (auto *InlinedAt = debugLoc->getInlinedAt()) { | |||
1765 | DebugLoc InlinedAtDL(InlinedAt); | |||
1766 | if (InlinedAtDL && MF) { | |||
1767 | OS << " inlined @[ "; | |||
1768 | InlinedAtDL.print(OS); | |||
1769 | OS << " ]"; | |||
1770 | } | |||
1771 | } | |||
1772 | if (isIndirectDebugValue()) | |||
1773 | OS << " indirect"; | |||
1774 | } | |||
1775 | // TODO: DBG_LABEL | |||
1776 | ||||
1777 | if (AddNewLine) | |||
1778 | OS << '\n'; | |||
1779 | } | |||
1780 | ||||
1781 | bool MachineInstr::addRegisterKilled(unsigned IncomingReg, | |||
1782 | const TargetRegisterInfo *RegInfo, | |||
1783 | bool AddIfNotFound) { | |||
1784 | bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg); | |||
1785 | bool hasAliases = isPhysReg && | |||
1786 | MCRegAliasIterator(IncomingReg, RegInfo, false).isValid(); | |||
1787 | bool Found = false; | |||
1788 | SmallVector<unsigned,4> DeadOps; | |||
1789 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
1790 | MachineOperand &MO = getOperand(i); | |||
1791 | if (!MO.isReg() || !MO.isUse() || MO.isUndef()) | |||
1792 | continue; | |||
1793 | ||||
1794 | // DEBUG_VALUE nodes do not contribute to code generation and should | |||
1795 | // always be ignored. Failure to do so may result in trying to modify | |||
1796 | // KILL flags on DEBUG_VALUE nodes. | |||
1797 | if (MO.isDebug()) | |||
1798 | continue; | |||
1799 | ||||
1800 | unsigned Reg = MO.getReg(); | |||
1801 | if (!Reg) | |||
1802 | continue; | |||
1803 | ||||
1804 | if (Reg == IncomingReg) { | |||
1805 | if (!Found) { | |||
1806 | if (MO.isKill()) | |||
1807 | // The register is already marked kill. | |||
1808 | return true; | |||
1809 | if (isPhysReg && isRegTiedToDefOperand(i)) | |||
1810 | // Two-address uses of physregs must not be marked kill. | |||
1811 | return true; | |||
1812 | MO.setIsKill(); | |||
1813 | Found = true; | |||
1814 | } | |||
1815 | } else if (hasAliases && MO.isKill() && | |||
1816 | TargetRegisterInfo::isPhysicalRegister(Reg)) { | |||
1817 | // A super-register kill already exists. | |||
1818 | if (RegInfo->isSuperRegister(IncomingReg, Reg)) | |||
1819 | return true; | |||
1820 | if (RegInfo->isSubRegister(IncomingReg, Reg)) | |||
1821 | DeadOps.push_back(i); | |||
1822 | } | |||
1823 | } | |||
1824 | ||||
1825 | // Trim unneeded kill operands. | |||
1826 | while (!DeadOps.empty()) { | |||
1827 | unsigned OpIdx = DeadOps.back(); | |||
1828 | if (getOperand(OpIdx).isImplicit() && | |||
1829 | (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) | |||
1830 | RemoveOperand(OpIdx); | |||
1831 | else | |||
1832 | getOperand(OpIdx).setIsKill(false); | |||
1833 | DeadOps.pop_back(); | |||
1834 | } | |||
1835 | ||||
1836 | // If not found, this means an alias of one of the operands is killed. Add a | |||
1837 | // new implicit operand if required. | |||
1838 | if (!Found && AddIfNotFound) { | |||
1839 | addOperand(MachineOperand::CreateReg(IncomingReg, | |||
1840 | false /*IsDef*/, | |||
1841 | true /*IsImp*/, | |||
1842 | true /*IsKill*/)); | |||
1843 | return true; | |||
1844 | } | |||
1845 | return Found; | |||
1846 | } | |||
1847 | ||||
1848 | void MachineInstr::clearRegisterKills(unsigned Reg, | |||
1849 | const TargetRegisterInfo *RegInfo) { | |||
1850 | if (!TargetRegisterInfo::isPhysicalRegister(Reg)) | |||
1851 | RegInfo = nullptr; | |||
1852 | for (MachineOperand &MO : operands()) { | |||
1853 | if (!MO.isReg() || !MO.isUse() || !MO.isKill()) | |||
1854 | continue; | |||
1855 | unsigned OpReg = MO.getReg(); | |||
1856 | if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) | |||
1857 | MO.setIsKill(false); | |||
1858 | } | |||
1859 | } | |||
1860 | ||||
1861 | bool MachineInstr::addRegisterDead(unsigned Reg, | |||
1862 | const TargetRegisterInfo *RegInfo, | |||
1863 | bool AddIfNotFound) { | |||
1864 | bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg); | |||
1865 | bool hasAliases = isPhysReg && | |||
1866 | MCRegAliasIterator(Reg, RegInfo, false).isValid(); | |||
1867 | bool Found = false; | |||
1868 | SmallVector<unsigned,4> DeadOps; | |||
1869 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { | |||
1870 | MachineOperand &MO = getOperand(i); | |||
1871 | if (!MO.isReg() || !MO.isDef()) | |||
1872 | continue; | |||
1873 | unsigned MOReg = MO.getReg(); | |||
1874 | if (!MOReg) | |||
1875 | continue; | |||
1876 | ||||
1877 | if (MOReg == Reg) { | |||
1878 | MO.setIsDead(); | |||
1879 | Found = true; | |||
1880 | } else if (hasAliases && MO.isDead() && | |||
1881 | TargetRegisterInfo::isPhysicalRegister(MOReg)) { | |||
1882 | // There exists a super-register that's marked dead. | |||
1883 | if (RegInfo->isSuperRegister(Reg, MOReg)) | |||
1884 | return true; | |||
1885 | if (RegInfo->isSubRegister(Reg, MOReg)) | |||
1886 | DeadOps.push_back(i); | |||
1887 | } | |||
1888 | } | |||
1889 | ||||
1890 | // Trim unneeded dead operands. | |||
1891 | while (!DeadOps.empty()) { | |||
1892 | unsigned OpIdx = DeadOps.back(); | |||
1893 | if (getOperand(OpIdx).isImplicit() && | |||
1894 | (!isInlineAsm() || findInlineAsmFlagIdx(OpIdx) < 0)) | |||
1895 | RemoveOperand(OpIdx); | |||
1896 | else | |||
1897 | getOperand(OpIdx).setIsDead(false); | |||
1898 | DeadOps.pop_back(); | |||
1899 | } | |||
1900 | ||||
1901 | // If not found, this means an alias of one of the operands is dead. Add a | |||
1902 | // new implicit operand if required. | |||
1903 | if (Found || !AddIfNotFound) | |||
1904 | return Found; | |||
1905 | ||||
1906 | addOperand(MachineOperand::CreateReg(Reg, | |||
1907 | true /*IsDef*/, | |||
1908 | true /*IsImp*/, | |||
1909 | false /*IsKill*/, | |||
1910 | true /*IsDead*/)); | |||
1911 | return true; | |||
1912 | } | |||
1913 | ||||
1914 | void MachineInstr::clearRegisterDeads(unsigned Reg) { | |||
1915 | for (MachineOperand &MO : operands()) { | |||
1916 | if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) | |||
1917 | continue; | |||
1918 | MO.setIsDead(false); | |||
1919 | } | |||
1920 | } | |||
1921 | ||||
1922 | void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) { | |||
1923 | for (MachineOperand &MO : operands()) { | |||
1924 | if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) | |||
1925 | continue; | |||
1926 | MO.setIsUndef(IsUndef); | |||
1927 | } | |||
1928 | } | |||
1929 | ||||
1930 | void MachineInstr::addRegisterDefined(unsigned Reg, | |||
1931 | const TargetRegisterInfo *RegInfo) { | |||
1932 | if (TargetRegisterInfo::isPhysicalRegister(Reg)) { | |||
1933 | MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo); | |||
1934 | if (MO) | |||
1935 | return; | |||
1936 | } else { | |||
1937 | for (const MachineOperand &MO : operands()) { | |||
1938 | if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && | |||
1939 | MO.getSubReg() == 0) | |||
1940 | return; | |||
1941 | } | |||
1942 | } | |||
1943 | addOperand(MachineOperand::CreateReg(Reg, | |||
1944 | true /*IsDef*/, | |||
1945 | true /*IsImp*/)); | |||
1946 | } | |||
1947 | ||||
1948 | void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs, | |||
1949 | const TargetRegisterInfo &TRI) { | |||
1950 | bool HasRegMask = false; | |||
1951 | for (MachineOperand &MO : operands()) { | |||
1952 | if (MO.isRegMask()) { | |||
1953 | HasRegMask = true; | |||
1954 | continue; | |||
1955 | } | |||
1956 | if (!MO.isReg() || !MO.isDef()) continue; | |||
1957 | unsigned Reg = MO.getReg(); | |||
1958 | if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue; | |||
1959 | // If there are no uses, including partial uses, the def is dead. | |||
1960 | if (llvm::none_of(UsedRegs, | |||
1961 | [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); })) | |||
1962 | MO.setIsDead(); | |||
1963 | } | |||
1964 | ||||
1965 | // This is a call with a register mask operand. | |||
1966 | // Mask clobbers are always dead, so add defs for the non-dead defines. | |||
1967 | if (HasRegMask) | |||
1968 | for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end(); | |||
1969 | I != E; ++I) | |||
1970 | addRegisterDefined(*I, &TRI); | |||
1971 | } | |||
1972 | ||||
1973 | unsigned | |||
1974 | MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) { | |||
1975 | // Build up a buffer of hash code components. | |||
1976 | SmallVector<size_t, 8> HashComponents; | |||
1977 | HashComponents.reserve(MI->getNumOperands() + 1); | |||
1978 | HashComponents.push_back(MI->getOpcode()); | |||
1979 | for (const MachineOperand &MO : MI->operands()) { | |||
1980 | if (MO.isReg() && MO.isDef() && | |||
1981 | TargetRegisterInfo::isVirtualRegister(MO.getReg())) | |||
1982 | continue; // Skip virtual register defs. | |||
1983 | ||||
1984 | HashComponents.push_back(hash_value(MO)); | |||
1985 | } | |||
1986 | return hash_combine_range(HashComponents.begin(), HashComponents.end()); | |||
1987 | } | |||
1988 | ||||
1989 | void MachineInstr::emitError(StringRef Msg) const { | |||
1990 | // Find the source location cookie. | |||
1991 | unsigned LocCookie = 0; | |||
1992 | const MDNode *LocMD = nullptr; | |||
1993 | for (unsigned i = getNumOperands(); i != 0; --i) { | |||
1994 | if (getOperand(i-1).isMetadata() && | |||
1995 | (LocMD = getOperand(i-1).getMetadata()) && | |||
1996 | LocMD->getNumOperands() != 0) { | |||
1997 | if (const ConstantInt *CI = | |||
1998 | mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) { | |||
1999 | LocCookie = CI->getZExtValue(); | |||
2000 | break; | |||
2001 | } | |||
2002 | } | |||
2003 | } | |||
2004 | ||||
2005 | if (const MachineBasicBlock *MBB = getParent()) | |||
2006 | if (const MachineFunction *MF = MBB->getParent()) | |||
2007 | return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); | |||
2008 | report_fatal_error(Msg); | |||
2009 | } | |||
2010 | ||||
2011 | MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, | |||
2012 | const MCInstrDesc &MCID, bool IsIndirect, | |||
2013 | unsigned Reg, const MDNode *Variable, | |||
2014 | const MDNode *Expr) { | |||
2015 | assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable" ) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2015, __PRETTY_FUNCTION__)); | |||
2016 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression" ) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2016, __PRETTY_FUNCTION__)); | |||
2017 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2018, __PRETTY_FUNCTION__)) | |||
2018 | "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2018, __PRETTY_FUNCTION__)); | |||
2019 | auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug); | |||
2020 | if (IsIndirect) | |||
2021 | MIB.addImm(0U); | |||
2022 | else | |||
2023 | MIB.addReg(0U, RegState::Debug); | |||
2024 | return MIB.addMetadata(Variable).addMetadata(Expr); | |||
2025 | } | |||
2026 | ||||
2027 | MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, | |||
2028 | const MCInstrDesc &MCID, bool IsIndirect, | |||
2029 | MachineOperand &MO, const MDNode *Variable, | |||
2030 | const MDNode *Expr) { | |||
2031 | assert(isa<DILocalVariable>(Variable) && "not a variable")((isa<DILocalVariable>(Variable) && "not a variable" ) ? static_cast<void> (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2031, __PRETTY_FUNCTION__)); | |||
2032 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression")((cast<DIExpression>(Expr)->isValid() && "not an expression" ) ? static_cast<void> (0) : __assert_fail ("cast<DIExpression>(Expr)->isValid() && \"not an expression\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2032, __PRETTY_FUNCTION__)); | |||
2033 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2034, __PRETTY_FUNCTION__)) | |||
2034 | "Expected inlined-at fields to agree")((cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic (DL) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2034, __PRETTY_FUNCTION__)); | |||
2035 | if (MO.isReg()) | |||
2036 | return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr); | |||
2037 | ||||
2038 | auto MIB = BuildMI(MF, DL, MCID).add(MO); | |||
2039 | if (IsIndirect) | |||
2040 | MIB.addImm(0U); | |||
2041 | else | |||
2042 | MIB.addReg(0U, RegState::Debug); | |||
2043 | return MIB.addMetadata(Variable).addMetadata(Expr); | |||
2044 | } | |||
2045 | ||||
2046 | MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, | |||
2047 | MachineBasicBlock::iterator I, | |||
2048 | const DebugLoc &DL, const MCInstrDesc &MCID, | |||
2049 | bool IsIndirect, unsigned Reg, | |||
2050 | const MDNode *Variable, const MDNode *Expr) { | |||
2051 | MachineFunction &MF = *BB.getParent(); | |||
2052 | MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr); | |||
2053 | BB.insert(I, MI); | |||
2054 | return MachineInstrBuilder(MF, MI); | |||
2055 | } | |||
2056 | ||||
2057 | MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, | |||
2058 | MachineBasicBlock::iterator I, | |||
2059 | const DebugLoc &DL, const MCInstrDesc &MCID, | |||
2060 | bool IsIndirect, MachineOperand &MO, | |||
2061 | const MDNode *Variable, const MDNode *Expr) { | |||
2062 | MachineFunction &MF = *BB.getParent(); | |||
2063 | MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr); | |||
2064 | BB.insert(I, MI); | |||
2065 | return MachineInstrBuilder(MF, *MI); | |||
2066 | } | |||
2067 | ||||
2068 | /// Compute the new DIExpression to use with a DBG_VALUE for a spill slot. | |||
2069 | /// This prepends DW_OP_deref when spilling an indirect DBG_VALUE. | |||
2070 | static const DIExpression *computeExprForSpill(const MachineInstr &MI) { | |||
2071 | assert(MI.getOperand(0).isReg() && "can't spill non-register")((MI.getOperand(0).isReg() && "can't spill non-register" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2071, __PRETTY_FUNCTION__)); | |||
2072 | assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc ()) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2073, __PRETTY_FUNCTION__)) | |||
2073 | "Expected inlined-at fields to agree")((MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc ()) && "Expected inlined-at fields to agree") ? static_cast <void> (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2073, __PRETTY_FUNCTION__)); | |||
2074 | ||||
2075 | const DIExpression *Expr = MI.getDebugExpression(); | |||
2076 | if (MI.isIndirectDebugValue()) { | |||
2077 | assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset")((MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset" ) ? static_cast<void> (0) : __assert_fail ("MI.getOperand(1).getImm() == 0 && \"DBG_VALUE with nonzero offset\"" , "/build/llvm-toolchain-snapshot-9~svn362543/lib/CodeGen/MachineInstr.cpp" , 2077, __PRETTY_FUNCTION__)); | |||
2078 | Expr = DIExpression::prepend(Expr, DIExpression::DerefBefore); | |||
2079 | } | |||
2080 | return Expr; | |||
2081 | } | |||
2082 | ||||
2083 | MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB, | |||
2084 | MachineBasicBlock::iterator I, | |||
2085 | const MachineInstr &Orig, | |||
2086 | int FrameIndex) { | |||
2087 | const DIExpression *Expr = computeExprForSpill(Orig); | |||
2088 | return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc()) | |||
| ||||
2089 | .addFrameIndex(FrameIndex) | |||
2090 | .addImm(0U) | |||
2091 | .addMetadata(Orig.getDebugVariable()) | |||
2092 | .addMetadata(Expr); | |||
2093 | } | |||
2094 | ||||
2095 | void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) { | |||
2096 | const DIExpression *Expr = computeExprForSpill(Orig); | |||
2097 | Orig.getOperand(0).ChangeToFrameIndex(FrameIndex); | |||
2098 | Orig.getOperand(1).ChangeToImmediate(0U); | |||
2099 | Orig.getOperand(3).setMetadata(Expr); | |||
2100 | } | |||
2101 | ||||
2102 | void MachineInstr::collectDebugValues( | |||
2103 | SmallVectorImpl<MachineInstr *> &DbgValues) { | |||
2104 | MachineInstr &MI = *this; | |||
2105 | if (!MI.getOperand(0).isReg()) | |||
2106 | return; | |||
2107 | ||||
2108 | MachineBasicBlock::iterator DI = MI; ++DI; | |||
2109 | for (MachineBasicBlock::iterator DE = MI.getParent()->end(); | |||
2110 | DI != DE; ++DI) { | |||
2111 | if (!DI->isDebugValue()) | |||
2112 | return; | |||
2113 | if (DI->getOperand(0).isReg() && | |||
2114 | DI->getOperand(0).getReg() == MI.getOperand(0).getReg()) | |||
2115 | DbgValues.push_back(&*DI); | |||
2116 | } | |||
2117 | } | |||
2118 | ||||
2119 | void MachineInstr::changeDebugValuesDefReg(unsigned Reg) { | |||
2120 | // Collect matching debug values. | |||
2121 | SmallVector<MachineInstr *, 2> DbgValues; | |||
2122 | collectDebugValues(DbgValues); | |||
2123 | ||||
2124 | // Propagate Reg to debug value instructions. | |||
2125 | for (auto *DBI : DbgValues) | |||
2126 | DBI->getOperand(0).setReg(Reg); | |||
2127 | } | |||
2128 | ||||
2129 | using MMOList = SmallVector<const MachineMemOperand *, 2>; | |||
2130 | ||||
2131 | static unsigned getSpillSlotSize(MMOList &Accesses, | |||
2132 | const MachineFrameInfo &MFI) { | |||
2133 | unsigned Size = 0; | |||
2134 | for (auto A : Accesses) | |||
2135 | if (MFI.isSpillSlotObjectIndex( | |||
2136 | cast<FixedStackPseudoSourceValue>(A->getPseudoValue()) | |||
2137 | ->getFrameIndex())) | |||
2138 | Size += A->getSize(); | |||
2139 | return Size; | |||
2140 | } | |||
2141 | ||||
2142 | Optional<unsigned> | |||
2143 | MachineInstr::getSpillSize(const TargetInstrInfo *TII) const { | |||
2144 | int FI; | |||
2145 | if (TII->isStoreToStackSlotPostFE(*this, FI)) { | |||
2146 | const MachineFrameInfo &MFI = getMF()->getFrameInfo(); | |||
2147 | if (MFI.isSpillSlotObjectIndex(FI)) | |||
2148 | return (*memoperands_begin())->getSize(); | |||
2149 | } | |||
2150 | return None; | |||
2151 | } | |||
2152 | ||||
2153 | Optional<unsigned> | |||
2154 | MachineInstr::getFoldedSpillSize(const TargetInstrInfo *TII) const { | |||
2155 | MMOList Accesses; | |||
2156 | if (TII->hasStoreToStackSlot(*this, Accesses)) | |||
2157 | return getSpillSlotSize(Accesses, getMF()->getFrameInfo()); | |||
2158 | return None; | |||
2159 | } | |||
2160 | ||||
2161 | Optional<unsigned> | |||
2162 | MachineInstr::getRestoreSize(const TargetInstrInfo *TII) const { | |||
2163 | int FI; | |||
2164 | if (TII->isLoadFromStackSlotPostFE(*this, FI)) { | |||
2165 | const MachineFrameInfo &MFI = getMF()->getFrameInfo(); | |||
2166 | if (MFI.isSpillSlotObjectIndex(FI)) | |||
2167 | return (*memoperands_begin())->getSize(); | |||
2168 | } | |||
2169 | return None; | |||
2170 | } | |||
2171 | ||||
2172 | Optional<unsigned> | |||
2173 | MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const { | |||
2174 | MMOList Accesses; | |||
2175 | if (TII->hasLoadFromStackSlot(*this, Accesses)) | |||
2176 | return getSpillSlotSize(Accesses, getMF()->getFrameInfo()); | |||
2177 | return None; | |||
2178 | } |
1 | //===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file exposes a function named BuildMI, which is useful for dramatically |
10 | // simplifying how MachineInstr's are created. It allows use of code like this: |
11 | // |
12 | // M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst) |
13 | // .addReg(argVal1) |
14 | // .addReg(argVal2); |
15 | // |
16 | //===----------------------------------------------------------------------===// |
17 | |
18 | #ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H |
19 | #define LLVM_CODEGEN_MACHINEINSTRBUILDER_H |
20 | |
21 | #include "llvm/ADT/ArrayRef.h" |
22 | #include "llvm/CodeGen/GlobalISel/Utils.h" |
23 | #include "llvm/CodeGen/MachineBasicBlock.h" |
24 | #include "llvm/CodeGen/MachineFunction.h" |
25 | #include "llvm/CodeGen/MachineInstr.h" |
26 | #include "llvm/CodeGen/MachineInstrBundle.h" |
27 | #include "llvm/CodeGen/MachineOperand.h" |
28 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
29 | #include "llvm/IR/InstrTypes.h" |
30 | #include "llvm/IR/Intrinsics.h" |
31 | #include "llvm/Support/ErrorHandling.h" |
32 | #include <cassert> |
33 | #include <cstdint> |
34 | #include <utility> |
35 | |
36 | namespace llvm { |
37 | |
38 | class MCInstrDesc; |
39 | class MDNode; |
40 | |
41 | namespace RegState { |
42 | |
43 | enum { |
44 | Define = 0x2, |
45 | Implicit = 0x4, |
46 | Kill = 0x8, |
47 | Dead = 0x10, |
48 | Undef = 0x20, |
49 | EarlyClobber = 0x40, |
50 | Debug = 0x80, |
51 | InternalRead = 0x100, |
52 | Renamable = 0x200, |
53 | DefineNoRead = Define | Undef, |
54 | ImplicitDefine = Implicit | Define, |
55 | ImplicitKill = Implicit | Kill |
56 | }; |
57 | |
58 | } // end namespace RegState |
59 | |
60 | class MachineInstrBuilder { |
61 | MachineFunction *MF = nullptr; |
62 | MachineInstr *MI = nullptr; |
63 | |
64 | public: |
65 | MachineInstrBuilder() = default; |
66 | |
67 | /// Create a MachineInstrBuilder for manipulating an existing instruction. |
68 | /// F must be the machine function that was used to allocate I. |
69 | MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} |
70 | MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I) |
71 | : MF(&F), MI(&*I) {} |
72 | |
73 | /// Allow automatic conversion to the machine instruction we are working on. |
74 | operator MachineInstr*() const { return MI; } |
75 | MachineInstr *operator->() const { return MI; } |
76 | operator MachineBasicBlock::iterator() const { return MI; } |
77 | |
78 | /// If conversion operators fail, use this method to get the MachineInstr |
79 | /// explicitly. |
80 | MachineInstr *getInstr() const { return MI; } |
81 | |
82 | /// Get the register for the operand index. |
83 | /// The operand at the index should be a register (asserted by |
84 | /// MachineOperand). |
85 | unsigned getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); } |
86 | |
87 | /// Add a new virtual register operand. |
88 | const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0, |
89 | unsigned SubReg = 0) const { |
90 | assert((flags & 0x1) == 0 &&(((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead." ) ? static_cast<void> (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 91, __PRETTY_FUNCTION__)) |
91 | "Passing in 'true' to addReg is forbidden! Use enums instead.")(((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead." ) ? static_cast<void> (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 91, __PRETTY_FUNCTION__)); |
92 | MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, |
93 | flags & RegState::Define, |
94 | flags & RegState::Implicit, |
95 | flags & RegState::Kill, |
96 | flags & RegState::Dead, |
97 | flags & RegState::Undef, |
98 | flags & RegState::EarlyClobber, |
99 | SubReg, |
100 | flags & RegState::Debug, |
101 | flags & RegState::InternalRead, |
102 | flags & RegState::Renamable)); |
103 | return *this; |
104 | } |
105 | |
106 | /// Add a virtual register definition operand. |
107 | const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0, |
108 | unsigned SubReg = 0) const { |
109 | return addReg(RegNo, Flags | RegState::Define, SubReg); |
110 | } |
111 | |
112 | /// Add a virtual register use operand. It is an error for Flags to contain |
113 | /// `RegState::Define` when calling this function. |
114 | const MachineInstrBuilder &addUse(unsigned RegNo, unsigned Flags = 0, |
115 | unsigned SubReg = 0) const { |
116 | assert(!(Flags & RegState::Define) &&((!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead." ) ? static_cast<void> (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 117, __PRETTY_FUNCTION__)) |
117 | "Misleading addUse defines register, use addReg instead.")((!(Flags & RegState::Define) && "Misleading addUse defines register, use addReg instead." ) ? static_cast<void> (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 117, __PRETTY_FUNCTION__)); |
118 | return addReg(RegNo, Flags, SubReg); |
119 | } |
120 | |
121 | /// Add a new immediate operand. |
122 | const MachineInstrBuilder &addImm(int64_t Val) const { |
123 | MI->addOperand(*MF, MachineOperand::CreateImm(Val)); |
124 | return *this; |
125 | } |
126 | |
127 | const MachineInstrBuilder &addCImm(const ConstantInt *Val) const { |
128 | MI->addOperand(*MF, MachineOperand::CreateCImm(Val)); |
129 | return *this; |
130 | } |
131 | |
132 | const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const { |
133 | MI->addOperand(*MF, MachineOperand::CreateFPImm(Val)); |
134 | return *this; |
135 | } |
136 | |
137 | const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, |
138 | unsigned char TargetFlags = 0) const { |
139 | MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags)); |
140 | return *this; |
141 | } |
142 | |
143 | const MachineInstrBuilder &addFrameIndex(int Idx) const { |
144 | MI->addOperand(*MF, MachineOperand::CreateFI(Idx)); |
145 | return *this; |
146 | } |
147 | |
148 | const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx, |
149 | int Offset = 0, |
150 | unsigned char TargetFlags = 0) const { |
151 | MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags)); |
152 | return *this; |
153 | } |
154 | |
155 | const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0, |
156 | unsigned char TargetFlags = 0) const { |
157 | MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset, |
158 | TargetFlags)); |
159 | return *this; |
160 | } |
161 | |
162 | const MachineInstrBuilder &addJumpTableIndex(unsigned Idx, |
163 | unsigned char TargetFlags = 0) const { |
164 | MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags)); |
165 | return *this; |
166 | } |
167 | |
168 | const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV, |
169 | int64_t Offset = 0, |
170 | unsigned char TargetFlags = 0) const { |
171 | MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags)); |
172 | return *this; |
173 | } |
174 | |
175 | const MachineInstrBuilder &addExternalSymbol(const char *FnName, |
176 | unsigned char TargetFlags = 0) const { |
177 | MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags)); |
178 | return *this; |
179 | } |
180 | |
181 | const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA, |
182 | int64_t Offset = 0, |
183 | unsigned char TargetFlags = 0) const { |
184 | MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags)); |
185 | return *this; |
186 | } |
187 | |
188 | const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const { |
189 | MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask)); |
190 | return *this; |
191 | } |
192 | |
193 | const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const { |
194 | MI->addMemOperand(*MF, MMO); |
195 | return *this; |
196 | } |
197 | |
198 | const MachineInstrBuilder & |
199 | setMemRefs(ArrayRef<MachineMemOperand *> MMOs) const { |
200 | MI->setMemRefs(*MF, MMOs); |
201 | return *this; |
202 | } |
203 | |
204 | const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const { |
205 | MI->cloneMemRefs(*MF, OtherMI); |
206 | return *this; |
207 | } |
208 | |
209 | const MachineInstrBuilder & |
210 | cloneMergedMemRefs(ArrayRef<const MachineInstr *> OtherMIs) const { |
211 | MI->cloneMergedMemRefs(*MF, OtherMIs); |
212 | return *this; |
213 | } |
214 | |
215 | const MachineInstrBuilder &add(const MachineOperand &MO) const { |
216 | MI->addOperand(*MF, MO); |
217 | return *this; |
218 | } |
219 | |
220 | const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const { |
221 | for (const MachineOperand &MO : MOs) { |
222 | MI->addOperand(*MF, MO); |
223 | } |
224 | return *this; |
225 | } |
226 | |
227 | const MachineInstrBuilder &addMetadata(const MDNode *MD) const { |
228 | MI->addOperand(*MF, MachineOperand::CreateMetadata(MD)); |
229 | assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable ()) : true) && "first MDNode argument of a DBG_VALUE not a variable" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 231, __PRETTY_FUNCTION__)) |
230 | : true) &&(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable ()) : true) && "first MDNode argument of a DBG_VALUE not a variable" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 231, __PRETTY_FUNCTION__)) |
231 | "first MDNode argument of a DBG_VALUE not a variable")(((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable ()) : true) && "first MDNode argument of a DBG_VALUE not a variable" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 231, __PRETTY_FUNCTION__)); |
232 | assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel ()) : true) && "first MDNode argument of a DBG_LABEL not a label" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 234, __PRETTY_FUNCTION__)) |
233 | : true) &&(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel ()) : true) && "first MDNode argument of a DBG_LABEL not a label" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 234, __PRETTY_FUNCTION__)) |
234 | "first MDNode argument of a DBG_LABEL not a label")(((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel ()) : true) && "first MDNode argument of a DBG_LABEL not a label" ) ? static_cast<void> (0) : __assert_fail ("(MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel()) : true) && \"first MDNode argument of a DBG_LABEL not a label\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 234, __PRETTY_FUNCTION__)); |
235 | return *this; |
236 | } |
237 | |
238 | const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const { |
239 | MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex)); |
240 | return *this; |
241 | } |
242 | |
243 | const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const { |
244 | MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID)); |
245 | return *this; |
246 | } |
247 | |
248 | const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const { |
249 | MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred)); |
250 | return *this; |
251 | } |
252 | |
253 | const MachineInstrBuilder &addSym(MCSymbol *Sym, |
254 | unsigned char TargetFlags = 0) const { |
255 | MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags)); |
256 | return *this; |
257 | } |
258 | |
259 | const MachineInstrBuilder &setMIFlags(unsigned Flags) const { |
260 | MI->setFlags(Flags); |
261 | return *this; |
262 | } |
263 | |
264 | const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const { |
265 | MI->setFlag(Flag); |
266 | return *this; |
267 | } |
268 | |
269 | // Add a displacement from an existing MachineOperand with an added offset. |
270 | const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off, |
271 | unsigned char TargetFlags = 0) const { |
272 | // If caller specifies new TargetFlags then use it, otherwise the |
273 | // default behavior is to copy the target flags from the existing |
274 | // MachineOperand. This means if the caller wants to clear the |
275 | // target flags it needs to do so explicitly. |
276 | if (0 == TargetFlags) |
277 | TargetFlags = Disp.getTargetFlags(); |
278 | |
279 | switch (Disp.getType()) { |
280 | default: |
281 | llvm_unreachable("Unhandled operand type in addDisp()")::llvm::llvm_unreachable_internal("Unhandled operand type in addDisp()" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 281); |
282 | case MachineOperand::MO_Immediate: |
283 | return addImm(Disp.getImm() + off); |
284 | case MachineOperand::MO_ConstantPoolIndex: |
285 | return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off, |
286 | TargetFlags); |
287 | case MachineOperand::MO_GlobalAddress: |
288 | return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off, |
289 | TargetFlags); |
290 | case MachineOperand::MO_BlockAddress: |
291 | return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off, |
292 | TargetFlags); |
293 | } |
294 | } |
295 | |
296 | /// Copy all the implicit operands from OtherMI onto this one. |
297 | const MachineInstrBuilder & |
298 | copyImplicitOps(const MachineInstr &OtherMI) const { |
299 | MI->copyImplicitOps(*MF, OtherMI); |
300 | return *this; |
301 | } |
302 | |
303 | bool constrainAllUses(const TargetInstrInfo &TII, |
304 | const TargetRegisterInfo &TRI, |
305 | const RegisterBankInfo &RBI) const { |
306 | return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); |
307 | } |
308 | }; |
309 | |
310 | /// Builder interface. Specify how to create the initial instruction itself. |
311 | inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
312 | const MCInstrDesc &MCID) { |
313 | return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)); |
314 | } |
315 | |
316 | /// This version of the builder sets up the first operand as a |
317 | /// destination virtual register. |
318 | inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
319 | const MCInstrDesc &MCID, unsigned DestReg) { |
320 | return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL)) |
321 | .addReg(DestReg, RegState::Define); |
322 | } |
323 | |
324 | /// This version of the builder inserts the newly-built instruction before |
325 | /// the given position in the given MachineBasicBlock, and sets up the first |
326 | /// operand as a destination virtual register. |
327 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
328 | MachineBasicBlock::iterator I, |
329 | const DebugLoc &DL, const MCInstrDesc &MCID, |
330 | unsigned DestReg) { |
331 | MachineFunction &MF = *BB.getParent(); |
332 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
333 | BB.insert(I, MI); |
334 | return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); |
335 | } |
336 | |
337 | /// This version of the builder inserts the newly-built instruction before |
338 | /// the given position in the given MachineBasicBlock, and sets up the first |
339 | /// operand as a destination virtual register. |
340 | /// |
341 | /// If \c I is inside a bundle, then the newly inserted \a MachineInstr is |
342 | /// added to the same bundle. |
343 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
344 | MachineBasicBlock::instr_iterator I, |
345 | const DebugLoc &DL, const MCInstrDesc &MCID, |
346 | unsigned DestReg) { |
347 | MachineFunction &MF = *BB.getParent(); |
348 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
349 | BB.insert(I, MI); |
350 | return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); |
351 | } |
352 | |
353 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, |
354 | const DebugLoc &DL, const MCInstrDesc &MCID, |
355 | unsigned DestReg) { |
356 | // Calling the overload for instr_iterator is always correct. However, the |
357 | // definition is not available in headers, so inline the check. |
358 | if (I.isInsideBundle()) |
359 | return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg); |
360 | return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); |
361 | } |
362 | |
363 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, |
364 | const DebugLoc &DL, const MCInstrDesc &MCID, |
365 | unsigned DestReg) { |
366 | return BuildMI(BB, *I, DL, MCID, DestReg); |
367 | } |
368 | |
369 | /// This version of the builder inserts the newly-built instruction before the |
370 | /// given position in the given MachineBasicBlock, and does NOT take a |
371 | /// destination register. |
372 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
373 | MachineBasicBlock::iterator I, |
374 | const DebugLoc &DL, |
375 | const MCInstrDesc &MCID) { |
376 | MachineFunction &MF = *BB.getParent(); |
377 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
378 | BB.insert(I, MI); |
379 | return MachineInstrBuilder(MF, MI); |
380 | } |
381 | |
382 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
383 | MachineBasicBlock::instr_iterator I, |
384 | const DebugLoc &DL, |
385 | const MCInstrDesc &MCID) { |
386 | MachineFunction &MF = *BB.getParent(); |
387 | MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); |
388 | BB.insert(I, MI); |
389 | return MachineInstrBuilder(MF, MI); |
390 | } |
391 | |
392 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, |
393 | const DebugLoc &DL, |
394 | const MCInstrDesc &MCID) { |
395 | // Calling the overload for instr_iterator is always correct. However, the |
396 | // definition is not available in headers, so inline the check. |
397 | if (I.isInsideBundle()) |
398 | return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID); |
399 | return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID); |
400 | } |
401 | |
402 | inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, |
403 | const DebugLoc &DL, |
404 | const MCInstrDesc &MCID) { |
405 | return BuildMI(BB, *I, DL, MCID); |
406 | } |
407 | |
408 | /// This version of the builder inserts the newly-built instruction at the end |
409 | /// of the given MachineBasicBlock, and does NOT take a destination register. |
410 | inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, |
411 | const MCInstrDesc &MCID) { |
412 | return BuildMI(*BB, BB->end(), DL, MCID); |
413 | } |
414 | |
415 | /// This version of the builder inserts the newly-built instruction at the |
416 | /// end of the given MachineBasicBlock, and sets up the first operand as a |
417 | /// destination virtual register. |
418 | inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL, |
419 | const MCInstrDesc &MCID, unsigned DestReg) { |
420 | return BuildMI(*BB, BB->end(), DL, MCID, DestReg); |
421 | } |
422 | |
423 | /// This version of the builder builds a DBG_VALUE intrinsic |
424 | /// for either a value in a register or a register-indirect |
425 | /// address. The convention is that a DBG_VALUE is indirect iff the |
426 | /// second operand is an immediate. |
427 | MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
428 | const MCInstrDesc &MCID, bool IsIndirect, |
429 | unsigned Reg, const MDNode *Variable, |
430 | const MDNode *Expr); |
431 | |
432 | /// This version of the builder builds a DBG_VALUE intrinsic |
433 | /// for a MachineOperand. |
434 | MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL, |
435 | const MCInstrDesc &MCID, bool IsIndirect, |
436 | MachineOperand &MO, const MDNode *Variable, |
437 | const MDNode *Expr); |
438 | |
439 | /// This version of the builder builds a DBG_VALUE intrinsic |
440 | /// for either a value in a register or a register-indirect |
441 | /// address and inserts it at position I. |
442 | MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
443 | MachineBasicBlock::iterator I, const DebugLoc &DL, |
444 | const MCInstrDesc &MCID, bool IsIndirect, |
445 | unsigned Reg, const MDNode *Variable, |
446 | const MDNode *Expr); |
447 | |
448 | /// This version of the builder builds a DBG_VALUE intrinsic |
449 | /// for a machine operand and inserts it at position I. |
450 | MachineInstrBuilder BuildMI(MachineBasicBlock &BB, |
451 | MachineBasicBlock::iterator I, const DebugLoc &DL, |
452 | const MCInstrDesc &MCID, bool IsIndirect, |
453 | MachineOperand &MO, const MDNode *Variable, |
454 | const MDNode *Expr); |
455 | |
456 | /// Clone a DBG_VALUE whose value has been spilled to FrameIndex. |
457 | MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB, |
458 | MachineBasicBlock::iterator I, |
459 | const MachineInstr &Orig, int FrameIndex); |
460 | |
461 | /// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when |
462 | /// modifying an instruction in place while iterating over a basic block. |
463 | void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex); |
464 | |
465 | inline unsigned getDefRegState(bool B) { |
466 | return B ? RegState::Define : 0; |
467 | } |
468 | inline unsigned getImplRegState(bool B) { |
469 | return B ? RegState::Implicit : 0; |
470 | } |
471 | inline unsigned getKillRegState(bool B) { |
472 | return B ? RegState::Kill : 0; |
473 | } |
474 | inline unsigned getDeadRegState(bool B) { |
475 | return B ? RegState::Dead : 0; |
476 | } |
477 | inline unsigned getUndefRegState(bool B) { |
478 | return B ? RegState::Undef : 0; |
479 | } |
480 | inline unsigned getInternalReadRegState(bool B) { |
481 | return B ? RegState::InternalRead : 0; |
482 | } |
483 | inline unsigned getDebugRegState(bool B) { |
484 | return B ? RegState::Debug : 0; |
485 | } |
486 | inline unsigned getRenamableRegState(bool B) { |
487 | return B ? RegState::Renamable : 0; |
488 | } |
489 | |
490 | /// Get all register state flags from machine operand \p RegOp. |
491 | inline unsigned getRegState(const MachineOperand &RegOp) { |
492 | assert(RegOp.isReg() && "Not a register operand")((RegOp.isReg() && "Not a register operand") ? static_cast <void> (0) : __assert_fail ("RegOp.isReg() && \"Not a register operand\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 492, __PRETTY_FUNCTION__)); |
493 | return getDefRegState(RegOp.isDef()) | |
494 | getImplRegState(RegOp.isImplicit()) | |
495 | getKillRegState(RegOp.isKill()) | |
496 | getDeadRegState(RegOp.isDead()) | |
497 | getUndefRegState(RegOp.isUndef()) | |
498 | getInternalReadRegState(RegOp.isInternalRead()) | |
499 | getDebugRegState(RegOp.isDebug()) | |
500 | getRenamableRegState( |
501 | TargetRegisterInfo::isPhysicalRegister(RegOp.getReg()) && |
502 | RegOp.isRenamable()); |
503 | } |
504 | |
505 | /// Helper class for constructing bundles of MachineInstrs. |
506 | /// |
507 | /// MIBundleBuilder can create a bundle from scratch by inserting new |
508 | /// MachineInstrs one at a time, or it can create a bundle from a sequence of |
509 | /// existing MachineInstrs in a basic block. |
510 | class MIBundleBuilder { |
511 | MachineBasicBlock &MBB; |
512 | MachineBasicBlock::instr_iterator Begin; |
513 | MachineBasicBlock::instr_iterator End; |
514 | |
515 | public: |
516 | /// Create an MIBundleBuilder that inserts instructions into a new bundle in |
517 | /// BB above the bundle or instruction at Pos. |
518 | MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos) |
519 | : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {} |
520 | |
521 | /// Create a bundle from the sequence of instructions between B and E. |
522 | MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B, |
523 | MachineBasicBlock::iterator E) |
524 | : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) { |
525 | assert(B != E && "No instructions to bundle")((B != E && "No instructions to bundle") ? static_cast <void> (0) : __assert_fail ("B != E && \"No instructions to bundle\"" , "/build/llvm-toolchain-snapshot-9~svn362543/include/llvm/CodeGen/MachineInstrBuilder.h" , 525, __PRETTY_FUNCTION__)); |
526 | ++B; |
527 | while (B != E) { |
528 | MachineInstr &MI = *B; |
529 | ++B; |
530 | MI.bundleWithPred(); |
531 | } |
532 | } |
533 | |
534 | /// Create an MIBundleBuilder representing an existing instruction or bundle |
535 | /// that has MI as its head. |
536 | explicit MIBundleBuilder(MachineInstr *MI) |
537 | : MBB(*MI->getParent()), Begin(MI), |
538 | End(getBundleEnd(MI->getIterator())) {} |
539 | |
540 | /// Return a reference to the basic block containing this bundle. |
541 | MachineBasicBlock &getMBB() const { return MBB; } |
542 | |
543 | /// Return true if no instructions have been inserted in this bundle yet. |
544 | /// Empty bundles aren't representable in a MachineBasicBlock. |
545 | bool empty() const { return Begin == End; } |
546 | |
547 | /// Return an iterator to the first bundled instruction. |
548 | MachineBasicBlock::instr_iterator begin() const { return Begin; } |
549 | |
550 | /// Return an iterator beyond the last bundled instruction. |
551 | MachineBasicBlock::instr_iterator end() const { return End; } |
552 | |
553 | /// Insert MI into this bundle before I which must point to an instruction in |
554 | /// the bundle, or end(). |
555 | MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I, |
556 | MachineInstr *MI) { |
557 | MBB.insert(I, MI); |
558 | if (I == Begin) { |
559 | if (!empty()) |
560 | MI->bundleWithSucc(); |
561 | Begin = MI->getIterator(); |
562 | return *this; |
563 | } |
564 | if (I == End) { |
565 | MI->bundleWithPred(); |
566 | return *this; |
567 | } |
568 | // MI was inserted in the middle of the bundle, so its neighbors' flags are |
569 | // already fine. Update MI's bundle flags manually. |
570 | MI->setFlag(MachineInstr::BundledPred); |
571 | MI->setFlag(MachineInstr::BundledSucc); |
572 | return *this; |
573 | } |
574 | |
575 | /// Insert MI into MBB by prepending it to the instructions in the bundle. |
576 | /// MI will become the first instruction in the bundle. |
577 | MIBundleBuilder &prepend(MachineInstr *MI) { |
578 | return insert(begin(), MI); |
579 | } |
580 | |
581 | /// Insert MI into MBB by appending it to the instructions in the bundle. |
582 | /// MI will become the last instruction in the bundle. |
583 | MIBundleBuilder &append(MachineInstr *MI) { |
584 | return insert(end(), MI); |
585 | } |
586 | }; |
587 | |
588 | } // end namespace llvm |
589 | |
590 | #endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H |