Bug Summary

File:lib/CodeGen/MachineInstr.cpp
Warning:line 191, column 3
Null pointer passed as an argument to a 'nonnull' parameter

Annotated Source Code

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clang -cc1 -triple x86_64-pc-linux-gnu -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name MachineInstr.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-eagerly-assume -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -mrelocation-model pic -pic-level 2 -mthread-model posix -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -dwarf-column-info -debugger-tuning=gdb -momit-leaf-frame-pointer -ffunction-sections -fdata-sections -resource-dir /usr/lib/llvm-7/lib/clang/7.0.0 -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I /build/llvm-toolchain-snapshot-7~svn324650/build-llvm/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen -I /build/llvm-toolchain-snapshot-7~svn324650/build-llvm/include -I /build/llvm-toolchain-snapshot-7~svn324650/include -U NDEBUG -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/x86_64-linux-gnu/c++/7.3.0 -internal-isystem /usr/lib/gcc/x86_64-linux-gnu/7.3.0/../../../../include/c++/7.3.0/backward -internal-isystem /usr/include/clang/7.0.0/include/ -internal-isystem /usr/local/include -internal-isystem /usr/lib/llvm-7/lib/clang/7.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-maybe-uninitialized -Wno-comment -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /build/llvm-toolchain-snapshot-7~svn324650/build-llvm/lib/CodeGen -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fobjc-runtime=gcc -fdiagnostics-show-option -vectorize-loops -vectorize-slp -analyzer-checker optin.performance.Padding -analyzer-output=html -analyzer-config stable-report-filename=true -o /tmp/scan-build-2018-02-09-212803-22585-1 -x c++ /build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp

/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp

1//===- lib/CodeGen/MachineInstr.cpp ---------------------------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Methods common to all machine instructions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/CodeGen/MachineInstr.h"
15#include "llvm/ADT/APFloat.h"
16#include "llvm/ADT/ArrayRef.h"
17#include "llvm/ADT/FoldingSet.h"
18#include "llvm/ADT/Hashing.h"
19#include "llvm/ADT/None.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/ADT/SmallBitVector.h"
22#include "llvm/ADT/SmallString.h"
23#include "llvm/ADT/SmallVector.h"
24#include "llvm/Analysis/AliasAnalysis.h"
25#include "llvm/Analysis/Loads.h"
26#include "llvm/Analysis/MemoryLocation.h"
27#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
28#include "llvm/CodeGen/MachineBasicBlock.h"
29#include "llvm/CodeGen/MachineFunction.h"
30#include "llvm/CodeGen/MachineInstrBuilder.h"
31#include "llvm/CodeGen/MachineInstrBundle.h"
32#include "llvm/CodeGen/MachineMemOperand.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineOperand.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/CodeGen/PseudoSourceValue.h"
37#include "llvm/CodeGen/TargetInstrInfo.h"
38#include "llvm/CodeGen/TargetRegisterInfo.h"
39#include "llvm/CodeGen/TargetSubtargetInfo.h"
40#include "llvm/IR/Constants.h"
41#include "llvm/IR/DebugInfoMetadata.h"
42#include "llvm/IR/DebugLoc.h"
43#include "llvm/IR/DerivedTypes.h"
44#include "llvm/IR/Function.h"
45#include "llvm/IR/InlineAsm.h"
46#include "llvm/IR/InstrTypes.h"
47#include "llvm/IR/Intrinsics.h"
48#include "llvm/IR/LLVMContext.h"
49#include "llvm/IR/Metadata.h"
50#include "llvm/IR/Module.h"
51#include "llvm/IR/ModuleSlotTracker.h"
52#include "llvm/IR/Type.h"
53#include "llvm/IR/Value.h"
54#include "llvm/MC/MCInstrDesc.h"
55#include "llvm/MC/MCRegisterInfo.h"
56#include "llvm/MC/MCSymbol.h"
57#include "llvm/Support/Casting.h"
58#include "llvm/Support/CommandLine.h"
59#include "llvm/Support/Compiler.h"
60#include "llvm/Support/Debug.h"
61#include "llvm/Support/ErrorHandling.h"
62#include "llvm/Support/LowLevelTypeImpl.h"
63#include "llvm/Support/MathExtras.h"
64#include "llvm/Support/raw_ostream.h"
65#include "llvm/Target/TargetIntrinsicInfo.h"
66#include "llvm/Target/TargetMachine.h"
67#include <algorithm>
68#include <cassert>
69#include <cstddef>
70#include <cstdint>
71#include <cstring>
72#include <iterator>
73#include <utility>
74
75using namespace llvm;
76
77static const MachineFunction *getMFIfAvailable(const MachineInstr &MI) {
78 if (const MachineBasicBlock *MBB = MI.getParent())
79 if (const MachineFunction *MF = MBB->getParent())
80 return MF;
81 return nullptr;
82}
83
84// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
85// it.
86static void tryToGetTargetInfo(const MachineInstr &MI,
87 const TargetRegisterInfo *&TRI,
88 const MachineRegisterInfo *&MRI,
89 const TargetIntrinsicInfo *&IntrinsicInfo,
90 const TargetInstrInfo *&TII) {
91
92 if (const MachineFunction *MF = getMFIfAvailable(MI)) {
93 TRI = MF->getSubtarget().getRegisterInfo();
94 MRI = &MF->getRegInfo();
95 IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
96 TII = MF->getSubtarget().getInstrInfo();
97 }
98}
99
100void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
101 if (MCID->ImplicitDefs)
102 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs;
103 ++ImpDefs)
104 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
105 if (MCID->ImplicitUses)
106 for (const MCPhysReg *ImpUses = MCID->getImplicitUses(); *ImpUses;
107 ++ImpUses)
108 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
109}
110
111/// MachineInstr ctor - This constructor creates a MachineInstr and adds the
112/// implicit operands. It reserves space for the number of operands specified by
113/// the MCInstrDesc.
114MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
115 DebugLoc dl, bool NoImp)
116 : MCID(&tid), debugLoc(std::move(dl)) {
117 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 117, __extension__ __PRETTY_FUNCTION__))
;
118
119 // Reserve space for the expected number of operands.
120 if (unsigned NumOps = MCID->getNumOperands() +
121 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
122 CapOperands = OperandCapacity::get(NumOps);
123 Operands = MF.allocateOperandArray(CapOperands);
124 }
125
126 if (!NoImp)
127 addImplicitDefUseOperands(MF);
128}
129
130/// MachineInstr ctor - Copies MachineInstr arg exactly
131///
132MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
133 : MCID(&MI.getDesc()), NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
134 debugLoc(MI.getDebugLoc()) {
135 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")(static_cast <bool> (debugLoc.hasTrivialDestructor() &&
"Expected trivial destructor") ? void (0) : __assert_fail ("debugLoc.hasTrivialDestructor() && \"Expected trivial destructor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 135, __extension__ __PRETTY_FUNCTION__))
;
136
137 CapOperands = OperandCapacity::get(MI.getNumOperands());
138 Operands = MF.allocateOperandArray(CapOperands);
139
140 // Copy operands.
141 for (const MachineOperand &MO : MI.operands())
142 addOperand(MF, MO);
143
144 // Copy all the sensible flags.
145 setFlags(MI.Flags);
146}
147
148/// getRegInfo - If this instruction is embedded into a MachineFunction,
149/// return the MachineRegisterInfo object for the current function, otherwise
150/// return null.
151MachineRegisterInfo *MachineInstr::getRegInfo() {
152 if (MachineBasicBlock *MBB = getParent())
153 return &MBB->getParent()->getRegInfo();
154 return nullptr;
155}
156
157/// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
158/// this instruction from their respective use lists. This requires that the
159/// operands already be on their use lists.
160void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
161 for (MachineOperand &MO : operands())
162 if (MO.isReg())
163 MRI.removeRegOperandFromUseList(&MO);
164}
165
166/// AddRegOperandsToUseLists - Add all of the register operands in
167/// this instruction from their respective use lists. This requires that the
168/// operands not be on their use lists yet.
169void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
170 for (MachineOperand &MO : operands())
171 if (MO.isReg())
172 MRI.addRegOperandToUseList(&MO);
173}
174
175void MachineInstr::addOperand(const MachineOperand &Op) {
176 MachineBasicBlock *MBB = getParent();
177 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs")(static_cast <bool> (MBB && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? void (0) : __assert_fail ("MBB && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 177, __extension__ __PRETTY_FUNCTION__))
;
178 MachineFunction *MF = MBB->getParent();
179 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs")(static_cast <bool> (MF && "Use MachineInstrBuilder to add operands to dangling instrs"
) ? void (0) : __assert_fail ("MF && \"Use MachineInstrBuilder to add operands to dangling instrs\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 179, __extension__ __PRETTY_FUNCTION__))
;
180 addOperand(*MF, Op);
181}
182
183/// Move NumOps MachineOperands from Src to Dst, with support for overlapping
184/// ranges. If MRI is non-null also update use-def chains.
185static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
186 unsigned NumOps, MachineRegisterInfo *MRI) {
187 if (MRI)
12
Taking false branch
188 return MRI->moveOperands(Dst, Src, NumOps);
189
190 // MachineOperand is a trivially copyable type so we can just use memmove.
191 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
13
Null pointer passed as an argument to a 'nonnull' parameter
192}
193
194/// addOperand - Add the specified operand to the instruction. If it is an
195/// implicit operand, it is added to the end of the operand list. If it is
196/// an explicit operand it is added at the end of the explicit operand list
197/// (before the first implicit operand).
198void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
199 assert(MCID && "Cannot add operands before providing an instr descriptor")(static_cast <bool> (MCID && "Cannot add operands before providing an instr descriptor"
) ? void (0) : __assert_fail ("MCID && \"Cannot add operands before providing an instr descriptor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 199, __extension__ __PRETTY_FUNCTION__))
;
200
201 // Check if we're adding one of our existing operands.
202 if (&Op >= Operands && &Op < Operands + NumOperands) {
203 // This is unusual: MI->addOperand(MI->getOperand(i)).
204 // If adding Op requires reallocating or moving existing operands around,
205 // the Op reference could go stale. Support it by copying Op.
206 MachineOperand CopyOp(Op);
207 return addOperand(MF, CopyOp);
208 }
209
210 // Find the insert location for the new operand. Implicit registers go at
211 // the end, everything else goes before the implicit regs.
212 //
213 // FIXME: Allow mixed explicit and implicit operands on inline asm.
214 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
215 // implicit-defs, but they must not be moved around. See the FIXME in
216 // InstrEmitter.cpp.
217 unsigned OpNo = getNumOperands();
218 bool isImpReg = Op.isReg() && Op.isImplicit();
219 if (!isImpReg && !isInlineAsm()) {
3
Taking false branch
220 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
221 --OpNo;
222 assert(!Operands[OpNo].isTied() && "Cannot move tied operands")(static_cast <bool> (!Operands[OpNo].isTied() &&
"Cannot move tied operands") ? void (0) : __assert_fail ("!Operands[OpNo].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 222, __extension__ __PRETTY_FUNCTION__))
;
223 }
224 }
225
226#ifndef NDEBUG
227 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
228 // OpNo now points as the desired insertion point. Unless this is a variadic
229 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
230 // RegMask operands go between the explicit and implicit operands.
231 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||(static_cast <bool> ((isImpReg || Op.isRegMask() || MCID
->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp
) && "Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 233, __extension__ __PRETTY_FUNCTION__))
232 OpNo < MCID->getNumOperands() || isMetaDataOp) &&(static_cast <bool> ((isImpReg || Op.isRegMask() || MCID
->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp
) && "Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 233, __extension__ __PRETTY_FUNCTION__))
233 "Trying to add an operand to a machine instr that is already done!")(static_cast <bool> ((isImpReg || Op.isRegMask() || MCID
->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp
) && "Trying to add an operand to a machine instr that is already done!"
) ? void (0) : __assert_fail ("(isImpReg || Op.isRegMask() || MCID->isVariadic() || OpNo < MCID->getNumOperands() || isMetaDataOp) && \"Trying to add an operand to a machine instr that is already done!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 233, __extension__ __PRETTY_FUNCTION__))
;
234#endif
235
236 MachineRegisterInfo *MRI = getRegInfo();
237
238 // Determine if the Operands array needs to be reallocated.
239 // Save the old capacity and operand array.
240 OperandCapacity OldCap = CapOperands;
241 MachineOperand *OldOperands = Operands;
4
'OldOperands' initialized here
242 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
5
Assuming pointer value is null
6
Assuming 'OldOperands' is null
243 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
7
'?' condition is false
244 Operands = MF.allocateOperandArray(CapOperands);
245 // Move the operands before the insertion point.
246 if (OpNo)
8
Assuming 'OpNo' is not equal to 0
9
Taking true branch
247 moveOperands(Operands, OldOperands, OpNo, MRI);
10
Passing null pointer value via 2nd parameter 'Src'
11
Calling 'moveOperands'
248 }
249
250 // Move the operands following the insertion point.
251 if (OpNo != NumOperands)
252 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
253 MRI);
254 ++NumOperands;
255
256 // Deallocate the old operand array.
257 if (OldOperands != Operands && OldOperands)
258 MF.deallocateOperandArray(OldCap, OldOperands);
259
260 // Copy Op into place. It still needs to be inserted into the MRI use lists.
261 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
262 NewMO->ParentMI = this;
263
264 // When adding a register operand, tell MRI about it.
265 if (NewMO->isReg()) {
266 // Ensure isOnRegUseList() returns false, regardless of Op's status.
267 NewMO->Contents.Reg.Prev = nullptr;
268 // Ignore existing ties. This is not a property that can be copied.
269 NewMO->TiedTo = 0;
270 // Add the new operand to MRI, but only for instructions in an MBB.
271 if (MRI)
272 MRI->addRegOperandToUseList(NewMO);
273 // The MCID operand information isn't accurate until we start adding
274 // explicit operands. The implicit operands are added first, then the
275 // explicits are inserted before them.
276 if (!isImpReg) {
277 // Tie uses to defs as indicated in MCInstrDesc.
278 if (NewMO->isUse()) {
279 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
280 if (DefIdx != -1)
281 tieOperands(DefIdx, OpNo);
282 }
283 // If the register operand is flagged as early, mark the operand as such.
284 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
285 NewMO->setIsEarlyClobber(true);
286 }
287 }
288}
289
290/// RemoveOperand - Erase an operand from an instruction, leaving it with one
291/// fewer operand than it started with.
292///
293void MachineInstr::RemoveOperand(unsigned OpNo) {
294 assert(OpNo < getNumOperands() && "Invalid operand number")(static_cast <bool> (OpNo < getNumOperands() &&
"Invalid operand number") ? void (0) : __assert_fail ("OpNo < getNumOperands() && \"Invalid operand number\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 294, __extension__ __PRETTY_FUNCTION__))
;
295 untieRegOperand(OpNo);
296
297#ifndef NDEBUG
298 // Moving tied operands would break the ties.
299 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
300 if (Operands[i].isReg())
301 assert(!Operands[i].isTied() && "Cannot move tied operands")(static_cast <bool> (!Operands[i].isTied() && "Cannot move tied operands"
) ? void (0) : __assert_fail ("!Operands[i].isTied() && \"Cannot move tied operands\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 301, __extension__ __PRETTY_FUNCTION__))
;
302#endif
303
304 MachineRegisterInfo *MRI = getRegInfo();
305 if (MRI && Operands[OpNo].isReg())
306 MRI->removeRegOperandFromUseList(Operands + OpNo);
307
308 // Don't call the MachineOperand destructor. A lot of this code depends on
309 // MachineOperand having a trivial destructor anyway, and adding a call here
310 // wouldn't make it 'destructor-correct'.
311
312 if (unsigned N = NumOperands - 1 - OpNo)
313 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
314 --NumOperands;
315}
316
317/// addMemOperand - Add a MachineMemOperand to the machine instruction.
318/// This function should be used only occasionally. The setMemRefs function
319/// is the primary method for setting up a MachineInstr's MemRefs list.
320void MachineInstr::addMemOperand(MachineFunction &MF,
321 MachineMemOperand *MO) {
322 mmo_iterator OldMemRefs = MemRefs;
323 unsigned OldNumMemRefs = NumMemRefs;
324
325 unsigned NewNum = NumMemRefs + 1;
326 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
327
328 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
329 NewMemRefs[NewNum - 1] = MO;
330 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
331}
332
333/// Check to see if the MMOs pointed to by the two MemRefs arrays are
334/// identical.
335static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) {
336 auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end();
337 auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end();
338 if ((E1 - I1) != (E2 - I2))
339 return false;
340 for (; I1 != E1; ++I1, ++I2) {
341 if (**I1 != **I2)
342 return false;
343 }
344 return true;
345}
346
347std::pair<MachineInstr::mmo_iterator, unsigned>
348MachineInstr::mergeMemRefsWith(const MachineInstr& Other) {
349
350 // If either of the incoming memrefs are empty, we must be conservative and
351 // treat this as if we've exhausted our space for memrefs and dropped them.
352 if (memoperands_empty() || Other.memoperands_empty())
353 return std::make_pair(nullptr, 0);
354
355 // If both instructions have identical memrefs, we don't need to merge them.
356 // Since many instructions have a single memref, and we tend to merge things
357 // like pairs of loads from the same location, this catches a large number of
358 // cases in practice.
359 if (hasIdenticalMMOs(*this, Other))
360 return std::make_pair(MemRefs, NumMemRefs);
361
362 // TODO: consider uniquing elements within the operand lists to reduce
363 // space usage and fall back to conservative information less often.
364 size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs;
365
366 // If we don't have enough room to store this many memrefs, be conservative
367 // and drop them. Otherwise, we'd fail asserts when trying to add them to
368 // the new instruction.
369 if (CombinedNumMemRefs != uint8_t(CombinedNumMemRefs))
370 return std::make_pair(nullptr, 0);
371
372 MachineFunction *MF = getMF();
373 mmo_iterator MemBegin = MF->allocateMemRefsArray(CombinedNumMemRefs);
374 mmo_iterator MemEnd = std::copy(memoperands_begin(), memoperands_end(),
375 MemBegin);
376 MemEnd = std::copy(Other.memoperands_begin(), Other.memoperands_end(),
377 MemEnd);
378 assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs &&(static_cast <bool> (MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs
&& "missing memrefs") ? void (0) : __assert_fail ("MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs && \"missing memrefs\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 379, __extension__ __PRETTY_FUNCTION__))
379 "missing memrefs")(static_cast <bool> (MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs
&& "missing memrefs") ? void (0) : __assert_fail ("MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs && \"missing memrefs\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 379, __extension__ __PRETTY_FUNCTION__))
;
380
381 return std::make_pair(MemBegin, CombinedNumMemRefs);
382}
383
384bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
385 assert(!isBundledWithPred() && "Must be called on bundle header")(static_cast <bool> (!isBundledWithPred() && "Must be called on bundle header"
) ? void (0) : __assert_fail ("!isBundledWithPred() && \"Must be called on bundle header\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 385, __extension__ __PRETTY_FUNCTION__))
;
386 for (MachineBasicBlock::const_instr_iterator MII = getIterator();; ++MII) {
387 if (MII->getDesc().getFlags() & Mask) {
388 if (Type == AnyInBundle)
389 return true;
390 } else {
391 if (Type == AllInBundle && !MII->isBundle())
392 return false;
393 }
394 // This was the last instruction in the bundle.
395 if (!MII->isBundledWithSucc())
396 return Type == AllInBundle;
397 }
398}
399
400bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
401 MICheckType Check) const {
402 // If opcodes or number of operands are not the same then the two
403 // instructions are obviously not identical.
404 if (Other.getOpcode() != getOpcode() ||
405 Other.getNumOperands() != getNumOperands())
406 return false;
407
408 if (isBundle()) {
409 // We have passed the test above that both instructions have the same
410 // opcode, so we know that both instructions are bundles here. Let's compare
411 // MIs inside the bundle.
412 assert(Other.isBundle() && "Expected that both instructions are bundles.")(static_cast <bool> (Other.isBundle() && "Expected that both instructions are bundles."
) ? void (0) : __assert_fail ("Other.isBundle() && \"Expected that both instructions are bundles.\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 412, __extension__ __PRETTY_FUNCTION__))
;
413 MachineBasicBlock::const_instr_iterator I1 = getIterator();
414 MachineBasicBlock::const_instr_iterator I2 = Other.getIterator();
415 // Loop until we analysed the last intruction inside at least one of the
416 // bundles.
417 while (I1->isBundledWithSucc() && I2->isBundledWithSucc()) {
418 ++I1;
419 ++I2;
420 if (!I1->isIdenticalTo(*I2, Check))
421 return false;
422 }
423 // If we've reached the end of just one of the two bundles, but not both,
424 // the instructions are not identical.
425 if (I1->isBundledWithSucc() || I2->isBundledWithSucc())
426 return false;
427 }
428
429 // Check operands to make sure they match.
430 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
431 const MachineOperand &MO = getOperand(i);
432 const MachineOperand &OMO = Other.getOperand(i);
433 if (!MO.isReg()) {
434 if (!MO.isIdenticalTo(OMO))
435 return false;
436 continue;
437 }
438
439 // Clients may or may not want to ignore defs when testing for equality.
440 // For example, machine CSE pass only cares about finding common
441 // subexpressions, so it's safe to ignore virtual register defs.
442 if (MO.isDef()) {
443 if (Check == IgnoreDefs)
444 continue;
445 else if (Check == IgnoreVRegDefs) {
446 if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()) ||
447 !TargetRegisterInfo::isVirtualRegister(OMO.getReg()))
448 if (!MO.isIdenticalTo(OMO))
449 return false;
450 } else {
451 if (!MO.isIdenticalTo(OMO))
452 return false;
453 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
454 return false;
455 }
456 } else {
457 if (!MO.isIdenticalTo(OMO))
458 return false;
459 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
460 return false;
461 }
462 }
463 // If DebugLoc does not match then two dbg.values are not identical.
464 if (isDebugValue())
465 if (getDebugLoc() && Other.getDebugLoc() &&
466 getDebugLoc() != Other.getDebugLoc())
467 return false;
468 return true;
469}
470
471const MachineFunction *MachineInstr::getMF() const {
472 return getParent()->getParent();
473}
474
475MachineInstr *MachineInstr::removeFromParent() {
476 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 476, __extension__ __PRETTY_FUNCTION__))
;
477 return getParent()->remove(this);
478}
479
480MachineInstr *MachineInstr::removeFromBundle() {
481 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 481, __extension__ __PRETTY_FUNCTION__))
;
482 return getParent()->remove_instr(this);
483}
484
485void MachineInstr::eraseFromParent() {
486 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 486, __extension__ __PRETTY_FUNCTION__))
;
487 getParent()->erase(this);
488}
489
490void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
491 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 491, __extension__ __PRETTY_FUNCTION__))
;
492 MachineBasicBlock *MBB = getParent();
493 MachineFunction *MF = MBB->getParent();
494 assert(MF && "Not embedded in a function!")(static_cast <bool> (MF && "Not embedded in a function!"
) ? void (0) : __assert_fail ("MF && \"Not embedded in a function!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 494, __extension__ __PRETTY_FUNCTION__))
;
495
496 MachineInstr *MI = (MachineInstr *)this;
497 MachineRegisterInfo &MRI = MF->getRegInfo();
498
499 for (const MachineOperand &MO : MI->operands()) {
500 if (!MO.isReg() || !MO.isDef())
501 continue;
502 unsigned Reg = MO.getReg();
503 if (!TargetRegisterInfo::isVirtualRegister(Reg))
504 continue;
505 MRI.markUsesInDebugValueAsUndef(Reg);
506 }
507 MI->eraseFromParent();
508}
509
510void MachineInstr::eraseFromBundle() {
511 assert(getParent() && "Not embedded in a basic block!")(static_cast <bool> (getParent() && "Not embedded in a basic block!"
) ? void (0) : __assert_fail ("getParent() && \"Not embedded in a basic block!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 511, __extension__ __PRETTY_FUNCTION__))
;
512 getParent()->erase_instr(this);
513}
514
515/// getNumExplicitOperands - Returns the number of non-implicit operands.
516///
517unsigned MachineInstr::getNumExplicitOperands() const {
518 unsigned NumOperands = MCID->getNumOperands();
519 if (!MCID->isVariadic())
520 return NumOperands;
521
522 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
523 const MachineOperand &MO = getOperand(i);
524 if (!MO.isReg() || !MO.isImplicit())
525 NumOperands++;
526 }
527 return NumOperands;
528}
529
530void MachineInstr::bundleWithPred() {
531 assert(!isBundledWithPred() && "MI is already bundled with its predecessor")(static_cast <bool> (!isBundledWithPred() && "MI is already bundled with its predecessor"
) ? void (0) : __assert_fail ("!isBundledWithPred() && \"MI is already bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 531, __extension__ __PRETTY_FUNCTION__))
;
532 setFlag(BundledPred);
533 MachineBasicBlock::instr_iterator Pred = getIterator();
534 --Pred;
535 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags")(static_cast <bool> (!Pred->isBundledWithSucc() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("!Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 535, __extension__ __PRETTY_FUNCTION__))
;
536 Pred->setFlag(BundledSucc);
537}
538
539void MachineInstr::bundleWithSucc() {
540 assert(!isBundledWithSucc() && "MI is already bundled with its successor")(static_cast <bool> (!isBundledWithSucc() && "MI is already bundled with its successor"
) ? void (0) : __assert_fail ("!isBundledWithSucc() && \"MI is already bundled with its successor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 540, __extension__ __PRETTY_FUNCTION__))
;
541 setFlag(BundledSucc);
542 MachineBasicBlock::instr_iterator Succ = getIterator();
543 ++Succ;
544 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags")(static_cast <bool> (!Succ->isBundledWithPred() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("!Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 544, __extension__ __PRETTY_FUNCTION__))
;
545 Succ->setFlag(BundledPred);
546}
547
548void MachineInstr::unbundleFromPred() {
549 assert(isBundledWithPred() && "MI isn't bundled with its predecessor")(static_cast <bool> (isBundledWithPred() && "MI isn't bundled with its predecessor"
) ? void (0) : __assert_fail ("isBundledWithPred() && \"MI isn't bundled with its predecessor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 549, __extension__ __PRETTY_FUNCTION__))
;
550 clearFlag(BundledPred);
551 MachineBasicBlock::instr_iterator Pred = getIterator();
552 --Pred;
553 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags")(static_cast <bool> (Pred->isBundledWithSucc() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("Pred->isBundledWithSucc() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 553, __extension__ __PRETTY_FUNCTION__))
;
554 Pred->clearFlag(BundledSucc);
555}
556
557void MachineInstr::unbundleFromSucc() {
558 assert(isBundledWithSucc() && "MI isn't bundled with its successor")(static_cast <bool> (isBundledWithSucc() && "MI isn't bundled with its successor"
) ? void (0) : __assert_fail ("isBundledWithSucc() && \"MI isn't bundled with its successor\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 558, __extension__ __PRETTY_FUNCTION__))
;
559 clearFlag(BundledSucc);
560 MachineBasicBlock::instr_iterator Succ = getIterator();
561 ++Succ;
562 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags")(static_cast <bool> (Succ->isBundledWithPred() &&
"Inconsistent bundle flags") ? void (0) : __assert_fail ("Succ->isBundledWithPred() && \"Inconsistent bundle flags\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 562, __extension__ __PRETTY_FUNCTION__))
;
563 Succ->clearFlag(BundledPred);
564}
565
566bool MachineInstr::isStackAligningInlineAsm() const {
567 if (isInlineAsm()) {
568 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
569 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
570 return true;
571 }
572 return false;
573}
574
575InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
576 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!")(static_cast <bool> (isInlineAsm() && "getInlineAsmDialect() only works for inline asms!"
) ? void (0) : __assert_fail ("isInlineAsm() && \"getInlineAsmDialect() only works for inline asms!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 576, __extension__ __PRETTY_FUNCTION__))
;
577 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
578 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
579}
580
581int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
582 unsigned *GroupNo) const {
583 assert(isInlineAsm() && "Expected an inline asm instruction")(static_cast <bool> (isInlineAsm() && "Expected an inline asm instruction"
) ? void (0) : __assert_fail ("isInlineAsm() && \"Expected an inline asm instruction\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 583, __extension__ __PRETTY_FUNCTION__))
;
584 assert(OpIdx < getNumOperands() && "OpIdx out of range")(static_cast <bool> (OpIdx < getNumOperands() &&
"OpIdx out of range") ? void (0) : __assert_fail ("OpIdx < getNumOperands() && \"OpIdx out of range\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 584, __extension__ __PRETTY_FUNCTION__))
;
585
586 // Ignore queries about the initial operands.
587 if (OpIdx < InlineAsm::MIOp_FirstOperand)
588 return -1;
589
590 unsigned Group = 0;
591 unsigned NumOps;
592 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
593 i += NumOps) {
594 const MachineOperand &FlagMO = getOperand(i);
595 // If we reach the implicit register operands, stop looking.
596 if (!FlagMO.isImm())
597 return -1;
598 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
599 if (i + NumOps > OpIdx) {
600 if (GroupNo)
601 *GroupNo = Group;
602 return i;
603 }
604 ++Group;
605 }
606 return -1;
607}
608
609const DILocalVariable *MachineInstr::getDebugVariable() const {
610 assert(isDebugValue() && "not a DBG_VALUE")(static_cast <bool> (isDebugValue() && "not a DBG_VALUE"
) ? void (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 610, __extension__ __PRETTY_FUNCTION__))
;
611 return cast<DILocalVariable>(getOperand(2).getMetadata());
612}
613
614const DIExpression *MachineInstr::getDebugExpression() const {
615 assert(isDebugValue() && "not a DBG_VALUE")(static_cast <bool> (isDebugValue() && "not a DBG_VALUE"
) ? void (0) : __assert_fail ("isDebugValue() && \"not a DBG_VALUE\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 615, __extension__ __PRETTY_FUNCTION__))
;
616 return cast<DIExpression>(getOperand(3).getMetadata());
617}
618
619const TargetRegisterClass*
620MachineInstr::getRegClassConstraint(unsigned OpIdx,
621 const TargetInstrInfo *TII,
622 const TargetRegisterInfo *TRI) const {
623 assert(getParent() && "Can't have an MBB reference here!")(static_cast <bool> (getParent() && "Can't have an MBB reference here!"
) ? void (0) : __assert_fail ("getParent() && \"Can't have an MBB reference here!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 623, __extension__ __PRETTY_FUNCTION__))
;
624 assert(getMF() && "Can't have an MF reference here!")(static_cast <bool> (getMF() && "Can't have an MF reference here!"
) ? void (0) : __assert_fail ("getMF() && \"Can't have an MF reference here!\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 624, __extension__ __PRETTY_FUNCTION__))
;
625 const MachineFunction &MF = *getMF();
626
627 // Most opcodes have fixed constraints in their MCInstrDesc.
628 if (!isInlineAsm())
629 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
630
631 if (!getOperand(OpIdx).isReg())
632 return nullptr;
633
634 // For tied uses on inline asm, get the constraint from the def.
635 unsigned DefIdx;
636 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
637 OpIdx = DefIdx;
638
639 // Inline asm stores register class constraints in the flag word.
640 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
641 if (FlagIdx < 0)
642 return nullptr;
643
644 unsigned Flag = getOperand(FlagIdx).getImm();
645 unsigned RCID;
646 if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse ||
647 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef ||
648 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) &&
649 InlineAsm::hasRegClassConstraint(Flag, RCID))
650 return TRI->getRegClass(RCID);
651
652 // Assume that all registers in a memory operand are pointers.
653 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
654 return TRI->getPointerRegClass(MF);
655
656 return nullptr;
657}
658
659const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
660 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
661 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
662 // Check every operands inside the bundle if we have
663 // been asked to.
664 if (ExploreBundle)
665 for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC;
666 ++OpndIt)
667 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
668 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
669 else
670 // Otherwise, just check the current operands.
671 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
672 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
673 return CurRC;
674}
675
676const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
677 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
678 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
679 assert(CurRC && "Invalid initial register class")(static_cast <bool> (CurRC && "Invalid initial register class"
) ? void (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 679, __extension__ __PRETTY_FUNCTION__))
;
680 // Check if Reg is constrained by some of its use/def from MI.
681 const MachineOperand &MO = getOperand(OpIdx);
682 if (!MO.isReg() || MO.getReg() != Reg)
683 return CurRC;
684 // If yes, accumulate the constraints through the operand.
685 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
686}
687
688const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
689 unsigned OpIdx, const TargetRegisterClass *CurRC,
690 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
691 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
692 const MachineOperand &MO = getOperand(OpIdx);
693 assert(MO.isReg() &&(static_cast <bool> (MO.isReg() && "Cannot get register constraints for non-register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 694, __extension__ __PRETTY_FUNCTION__))
694 "Cannot get register constraints for non-register operand")(static_cast <bool> (MO.isReg() && "Cannot get register constraints for non-register operand"
) ? void (0) : __assert_fail ("MO.isReg() && \"Cannot get register constraints for non-register operand\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 694, __extension__ __PRETTY_FUNCTION__))
;
695 assert(CurRC && "Invalid initial register class")(static_cast <bool> (CurRC && "Invalid initial register class"
) ? void (0) : __assert_fail ("CurRC && \"Invalid initial register class\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 695, __extension__ __PRETTY_FUNCTION__))
;
696 if (unsigned SubIdx = MO.getSubReg()) {
697 if (OpRC)
698 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
699 else
700 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
701 } else if (OpRC)
702 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
703 return CurRC;
704}
705
706/// Return the number of instructions inside the MI bundle, not counting the
707/// header instruction.
708unsigned MachineInstr::getBundleSize() const {
709 MachineBasicBlock::const_instr_iterator I = getIterator();
710 unsigned Size = 0;
711 while (I->isBundledWithSucc()) {
712 ++Size;
713 ++I;
714 }
715 return Size;
716}
717
718/// Returns true if the MachineInstr has an implicit-use operand of exactly
719/// the given register (not considering sub/super-registers).
720bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const {
721 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
722 const MachineOperand &MO = getOperand(i);
723 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
724 return true;
725 }
726 return false;
727}
728
729/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
730/// the specific register or -1 if it is not found. It further tightens
731/// the search criteria to a use that kills the register if isKill is true.
732int MachineInstr::findRegisterUseOperandIdx(
733 unsigned Reg, bool isKill, const TargetRegisterInfo *TRI) const {
734 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
735 const MachineOperand &MO = getOperand(i);
736 if (!MO.isReg() || !MO.isUse())
737 continue;
738 unsigned MOReg = MO.getReg();
739 if (!MOReg)
740 continue;
741 if (MOReg == Reg || (TRI && TargetRegisterInfo::isPhysicalRegister(MOReg) &&
742 TargetRegisterInfo::isPhysicalRegister(Reg) &&
743 TRI->isSubRegister(MOReg, Reg)))
744 if (!isKill || MO.isKill())
745 return i;
746 }
747 return -1;
748}
749
750/// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
751/// indicating if this instruction reads or writes Reg. This also considers
752/// partial defines.
753std::pair<bool,bool>
754MachineInstr::readsWritesVirtualRegister(unsigned Reg,
755 SmallVectorImpl<unsigned> *Ops) const {
756 bool PartDef = false; // Partial redefine.
757 bool FullDef = false; // Full define.
758 bool Use = false;
759
760 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
761 const MachineOperand &MO = getOperand(i);
762 if (!MO.isReg() || MO.getReg() != Reg)
763 continue;
764 if (Ops)
765 Ops->push_back(i);
766 if (MO.isUse())
767 Use |= !MO.isUndef();
768 else if (MO.getSubReg() && !MO.isUndef())
769 // A partial def undef doesn't count as reading the register.
770 PartDef = true;
771 else
772 FullDef = true;
773 }
774 // A partial redefine uses Reg unless there is also a full define.
775 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
776}
777
778/// findRegisterDefOperandIdx() - Returns the operand index that is a def of
779/// the specified register or -1 if it is not found. If isDead is true, defs
780/// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
781/// also checks if there is a def of a super-register.
782int
783MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
784 const TargetRegisterInfo *TRI) const {
785 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
786 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
787 const MachineOperand &MO = getOperand(i);
788 // Accept regmask operands when Overlap is set.
789 // Ignore them when looking for a specific def operand (Overlap == false).
790 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
791 return i;
792 if (!MO.isReg() || !MO.isDef())
793 continue;
794 unsigned MOReg = MO.getReg();
795 bool Found = (MOReg == Reg);
796 if (!Found && TRI && isPhys &&
797 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
798 if (Overlap)
799 Found = TRI->regsOverlap(MOReg, Reg);
800 else
801 Found = TRI->isSubRegister(MOReg, Reg);
802 }
803 if (Found && (!isDead || MO.isDead()))
804 return i;
805 }
806 return -1;
807}
808
809/// findFirstPredOperandIdx() - Find the index of the first operand in the
810/// operand list that is used to represent the predicate. It returns -1 if
811/// none is found.
812int MachineInstr::findFirstPredOperandIdx() const {
813 // Don't call MCID.findFirstPredOperandIdx() because this variant
814 // is sometimes called on an instruction that's not yet complete, and
815 // so the number of operands is less than the MCID indicates. In
816 // particular, the PTX target does this.
817 const MCInstrDesc &MCID = getDesc();
818 if (MCID.isPredicable()) {
819 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
820 if (MCID.OpInfo[i].isPredicate())
821 return i;
822 }
823
824 return -1;
825}
826
827// MachineOperand::TiedTo is 4 bits wide.
828const unsigned TiedMax = 15;
829
830/// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
831///
832/// Use and def operands can be tied together, indicated by a non-zero TiedTo
833/// field. TiedTo can have these values:
834///
835/// 0: Operand is not tied to anything.
836/// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
837/// TiedMax: Tied to an operand >= TiedMax-1.
838///
839/// The tied def must be one of the first TiedMax operands on a normal
840/// instruction. INLINEASM instructions allow more tied defs.
841///
842void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
843 MachineOperand &DefMO = getOperand(DefIdx);
844 MachineOperand &UseMO = getOperand(UseIdx);
845 assert(DefMO.isDef() && "DefIdx must be a def operand")(static_cast <bool> (DefMO.isDef() && "DefIdx must be a def operand"
) ? void (0) : __assert_fail ("DefMO.isDef() && \"DefIdx must be a def operand\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 845, __extension__ __PRETTY_FUNCTION__))
;
846 assert(UseMO.isUse() && "UseIdx must be a use operand")(static_cast <bool> (UseMO.isUse() && "UseIdx must be a use operand"
) ? void (0) : __assert_fail ("UseMO.isUse() && \"UseIdx must be a use operand\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 846, __extension__ __PRETTY_FUNCTION__))
;
847 assert(!DefMO.isTied() && "Def is already tied to another use")(static_cast <bool> (!DefMO.isTied() && "Def is already tied to another use"
) ? void (0) : __assert_fail ("!DefMO.isTied() && \"Def is already tied to another use\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 847, __extension__ __PRETTY_FUNCTION__))
;
848 assert(!UseMO.isTied() && "Use is already tied to another def")(static_cast <bool> (!UseMO.isTied() && "Use is already tied to another def"
) ? void (0) : __assert_fail ("!UseMO.isTied() && \"Use is already tied to another def\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 848, __extension__ __PRETTY_FUNCTION__))
;
849
850 if (DefIdx < TiedMax)
851 UseMO.TiedTo = DefIdx + 1;
852 else {
853 // Inline asm can use the group descriptors to find tied operands, but on
854 // normal instruction, the tied def must be within the first TiedMax
855 // operands.
856 assert(isInlineAsm() && "DefIdx out of range")(static_cast <bool> (isInlineAsm() && "DefIdx out of range"
) ? void (0) : __assert_fail ("isInlineAsm() && \"DefIdx out of range\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 856, __extension__ __PRETTY_FUNCTION__))
;
857 UseMO.TiedTo = TiedMax;
858 }
859
860 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
861 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
862}
863
864/// Given the index of a tied register operand, find the operand it is tied to.
865/// Defs are tied to uses and vice versa. Returns the index of the tied operand
866/// which must exist.
867unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
868 const MachineOperand &MO = getOperand(OpIdx);
869 assert(MO.isTied() && "Operand isn't tied")(static_cast <bool> (MO.isTied() && "Operand isn't tied"
) ? void (0) : __assert_fail ("MO.isTied() && \"Operand isn't tied\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 869, __extension__ __PRETTY_FUNCTION__))
;
870
871 // Normally TiedTo is in range.
872 if (MO.TiedTo < TiedMax)
873 return MO.TiedTo - 1;
874
875 // Uses on normal instructions can be out of range.
876 if (!isInlineAsm()) {
877 // Normal tied defs must be in the 0..TiedMax-1 range.
878 if (MO.isUse())
879 return TiedMax - 1;
880 // MO is a def. Search for the tied use.
881 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
882 const MachineOperand &UseMO = getOperand(i);
883 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
884 return i;
885 }
886 llvm_unreachable("Can't find tied use")::llvm::llvm_unreachable_internal("Can't find tied use", "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 886)
;
887 }
888
889 // Now deal with inline asm by parsing the operand group descriptor flags.
890 // Find the beginning of each operand group.
891 SmallVector<unsigned, 8> GroupIdx;
892 unsigned OpIdxGroup = ~0u;
893 unsigned NumOps;
894 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
895 i += NumOps) {
896 const MachineOperand &FlagMO = getOperand(i);
897 assert(FlagMO.isImm() && "Invalid tied operand on inline asm")(static_cast <bool> (FlagMO.isImm() && "Invalid tied operand on inline asm"
) ? void (0) : __assert_fail ("FlagMO.isImm() && \"Invalid tied operand on inline asm\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 897, __extension__ __PRETTY_FUNCTION__))
;
898 unsigned CurGroup = GroupIdx.size();
899 GroupIdx.push_back(i);
900 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
901 // OpIdx belongs to this operand group.
902 if (OpIdx > i && OpIdx < i + NumOps)
903 OpIdxGroup = CurGroup;
904 unsigned TiedGroup;
905 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
906 continue;
907 // Operands in this group are tied to operands in TiedGroup which must be
908 // earlier. Find the number of operands between the two groups.
909 unsigned Delta = i - GroupIdx[TiedGroup];
910
911 // OpIdx is a use tied to TiedGroup.
912 if (OpIdxGroup == CurGroup)
913 return OpIdx - Delta;
914
915 // OpIdx is a def tied to this use group.
916 if (OpIdxGroup == TiedGroup)
917 return OpIdx + Delta;
918 }
919 llvm_unreachable("Invalid tied operand on inline asm")::llvm::llvm_unreachable_internal("Invalid tied operand on inline asm"
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 919)
;
920}
921
922/// clearKillInfo - Clears kill flags on all operands.
923///
924void MachineInstr::clearKillInfo() {
925 for (MachineOperand &MO : operands()) {
926 if (MO.isReg() && MO.isUse())
927 MO.setIsKill(false);
928 }
929}
930
931void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
932 unsigned SubIdx,
933 const TargetRegisterInfo &RegInfo,
934 bool ClearIsRenamable) {
935 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
936 if (SubIdx)
937 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
938 for (MachineOperand &MO : operands()) {
939 if (!MO.isReg() || MO.getReg() != FromReg)
940 continue;
941 MO.substPhysReg(ToReg, RegInfo);
942 if (ClearIsRenamable)
943 MO.setIsRenamable(false);
944 }
945 } else {
946 assert(!ClearIsRenamable && "IsRenamable invalid for virtual registers")(static_cast <bool> (!ClearIsRenamable && "IsRenamable invalid for virtual registers"
) ? void (0) : __assert_fail ("!ClearIsRenamable && \"IsRenamable invalid for virtual registers\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 946, __extension__ __PRETTY_FUNCTION__))
;
947 for (MachineOperand &MO : operands()) {
948 if (!MO.isReg() || MO.getReg() != FromReg)
949 continue;
950 MO.substVirtReg(ToReg, SubIdx, RegInfo);
951 }
952 }
953}
954
955/// isSafeToMove - Return true if it is safe to move this instruction. If
956/// SawStore is set to true, it means that there is a store (or call) between
957/// the instruction's location and its intended destination.
958bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
959 // Ignore stuff that we obviously can't move.
960 //
961 // Treat volatile loads as stores. This is not strictly necessary for
962 // volatiles, but it is required for atomic loads. It is not allowed to move
963 // a load across an atomic load with Ordering > Monotonic.
964 if (mayStore() || isCall() || isPHI() ||
965 (mayLoad() && hasOrderedMemoryRef())) {
966 SawStore = true;
967 return false;
968 }
969
970 if (isPosition() || isDebugValue() || isTerminator() ||
971 hasUnmodeledSideEffects())
972 return false;
973
974 // See if this instruction does a load. If so, we have to guarantee that the
975 // loaded value doesn't change between the load and the its intended
976 // destination. The check for isInvariantLoad gives the targe the chance to
977 // classify the load as always returning a constant, e.g. a constant pool
978 // load.
979 if (mayLoad() && !isDereferenceableInvariantLoad(AA))
980 // Otherwise, this is a real load. If there is a store between the load and
981 // end of block, we can't move it.
982 return !SawStore;
983
984 return true;
985}
986
987bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
988 bool UseTBAA) {
989 const MachineFunction *MF = getMF();
990 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
991 const MachineFrameInfo &MFI = MF->getFrameInfo();
992
993 // If neither instruction stores to memory, they can't alias in any
994 // meaningful way, even if they read from the same address.
995 if (!mayStore() && !Other.mayStore())
996 return false;
997
998 // Let the target decide if memory accesses cannot possibly overlap.
999 if (TII->areMemAccessesTriviallyDisjoint(*this, Other, AA))
1000 return false;
1001
1002 // FIXME: Need to handle multiple memory operands to support all targets.
1003 if (!hasOneMemOperand() || !Other.hasOneMemOperand())
1004 return true;
1005
1006 MachineMemOperand *MMOa = *memoperands_begin();
1007 MachineMemOperand *MMOb = *Other.memoperands_begin();
1008
1009 // The following interface to AA is fashioned after DAGCombiner::isAlias
1010 // and operates with MachineMemOperand offset with some important
1011 // assumptions:
1012 // - LLVM fundamentally assumes flat address spaces.
1013 // - MachineOperand offset can *only* result from legalization and
1014 // cannot affect queries other than the trivial case of overlap
1015 // checking.
1016 // - These offsets never wrap and never step outside
1017 // of allocated objects.
1018 // - There should never be any negative offsets here.
1019 //
1020 // FIXME: Modify API to hide this math from "user"
1021 // Even before we go to AA we can reason locally about some
1022 // memory objects. It can save compile time, and possibly catch some
1023 // corner cases not currently covered.
1024
1025 int64_t OffsetA = MMOa->getOffset();
1026 int64_t OffsetB = MMOb->getOffset();
1027
1028 int64_t MinOffset = std::min(OffsetA, OffsetB);
1029 int64_t WidthA = MMOa->getSize();
1030 int64_t WidthB = MMOb->getSize();
1031 const Value *ValA = MMOa->getValue();
1032 const Value *ValB = MMOb->getValue();
1033 bool SameVal = (ValA && ValB && (ValA == ValB));
1034 if (!SameVal) {
1035 const PseudoSourceValue *PSVa = MMOa->getPseudoValue();
1036 const PseudoSourceValue *PSVb = MMOb->getPseudoValue();
1037 if (PSVa && ValB && !PSVa->mayAlias(&MFI))
1038 return false;
1039 if (PSVb && ValA && !PSVb->mayAlias(&MFI))
1040 return false;
1041 if (PSVa && PSVb && (PSVa == PSVb))
1042 SameVal = true;
1043 }
1044
1045 if (SameVal) {
1046 int64_t MaxOffset = std::max(OffsetA, OffsetB);
1047 int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
1048 return (MinOffset + LowWidth > MaxOffset);
1049 }
1050
1051 if (!AA)
1052 return true;
1053
1054 if (!ValA || !ValB)
1055 return true;
1056
1057 assert((OffsetA >= 0) && "Negative MachineMemOperand offset")(static_cast <bool> ((OffsetA >= 0) && "Negative MachineMemOperand offset"
) ? void (0) : __assert_fail ("(OffsetA >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1057, __extension__ __PRETTY_FUNCTION__))
;
1058 assert((OffsetB >= 0) && "Negative MachineMemOperand offset")(static_cast <bool> ((OffsetB >= 0) && "Negative MachineMemOperand offset"
) ? void (0) : __assert_fail ("(OffsetB >= 0) && \"Negative MachineMemOperand offset\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1058, __extension__ __PRETTY_FUNCTION__))
;
1059
1060 int64_t Overlapa = WidthA + OffsetA - MinOffset;
1061 int64_t Overlapb = WidthB + OffsetB - MinOffset;
1062
1063 AliasResult AAResult = AA->alias(
1064 MemoryLocation(ValA, Overlapa,
1065 UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
1066 MemoryLocation(ValB, Overlapb,
1067 UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
1068
1069 return (AAResult != NoAlias);
1070}
1071
1072/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1073/// or volatile memory reference, or if the information describing the memory
1074/// reference is not available. Return false if it is known to have no ordered
1075/// memory references.
1076bool MachineInstr::hasOrderedMemoryRef() const {
1077 // An instruction known never to access memory won't have a volatile access.
1078 if (!mayStore() &&
1079 !mayLoad() &&
1080 !isCall() &&
1081 !hasUnmodeledSideEffects())
1082 return false;
1083
1084 // Otherwise, if the instruction has no memory reference information,
1085 // conservatively assume it wasn't preserved.
1086 if (memoperands_empty())
1087 return true;
1088
1089 // Check if any of our memory operands are ordered.
1090 return llvm::any_of(memoperands(), [](const MachineMemOperand *MMO) {
1091 return !MMO->isUnordered();
1092 });
1093}
1094
1095/// isDereferenceableInvariantLoad - Return true if this instruction will never
1096/// trap and is loading from a location whose value is invariant across a run of
1097/// this function.
1098bool MachineInstr::isDereferenceableInvariantLoad(AliasAnalysis *AA) const {
1099 // If the instruction doesn't load at all, it isn't an invariant load.
1100 if (!mayLoad())
1101 return false;
1102
1103 // If the instruction has lost its memoperands, conservatively assume that
1104 // it may not be an invariant load.
1105 if (memoperands_empty())
1106 return false;
1107
1108 const MachineFrameInfo &MFI = getParent()->getParent()->getFrameInfo();
1109
1110 for (MachineMemOperand *MMO : memoperands()) {
1111 if (MMO->isVolatile()) return false;
1112 if (MMO->isStore()) return false;
1113 if (MMO->isInvariant() && MMO->isDereferenceable())
1114 continue;
1115
1116 // A load from a constant PseudoSourceValue is invariant.
1117 if (const PseudoSourceValue *PSV = MMO->getPseudoValue())
1118 if (PSV->isConstant(&MFI))
1119 continue;
1120
1121 if (const Value *V = MMO->getValue()) {
1122 // If we have an AliasAnalysis, ask it whether the memory is constant.
1123 if (AA &&
1124 AA->pointsToConstantMemory(
1125 MemoryLocation(V, MMO->getSize(), MMO->getAAInfo())))
1126 continue;
1127 }
1128
1129 // Otherwise assume conservatively.
1130 return false;
1131 }
1132
1133 // Everything checks out.
1134 return true;
1135}
1136
1137/// isConstantValuePHI - If the specified instruction is a PHI that always
1138/// merges together the same virtual register, return the register, otherwise
1139/// return 0.
1140unsigned MachineInstr::isConstantValuePHI() const {
1141 if (!isPHI())
1142 return 0;
1143 assert(getNumOperands() >= 3 &&(static_cast <bool> (getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands") ? void
(0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1144, __extension__ __PRETTY_FUNCTION__))
1144 "It's illegal to have a PHI without source operands")(static_cast <bool> (getNumOperands() >= 3 &&
"It's illegal to have a PHI without source operands") ? void
(0) : __assert_fail ("getNumOperands() >= 3 && \"It's illegal to have a PHI without source operands\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1144, __extension__ __PRETTY_FUNCTION__))
;
1145
1146 unsigned Reg = getOperand(1).getReg();
1147 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1148 if (getOperand(i).getReg() != Reg)
1149 return 0;
1150 return Reg;
1151}
1152
1153bool MachineInstr::hasUnmodeledSideEffects() const {
1154 if (hasProperty(MCID::UnmodeledSideEffects))
1155 return true;
1156 if (isInlineAsm()) {
1157 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1158 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1159 return true;
1160 }
1161
1162 return false;
1163}
1164
1165bool MachineInstr::isLoadFoldBarrier() const {
1166 return mayStore() || isCall() || hasUnmodeledSideEffects();
1167}
1168
1169/// allDefsAreDead - Return true if all the defs of this instruction are dead.
1170///
1171bool MachineInstr::allDefsAreDead() const {
1172 for (const MachineOperand &MO : operands()) {
1173 if (!MO.isReg() || MO.isUse())
1174 continue;
1175 if (!MO.isDead())
1176 return false;
1177 }
1178 return true;
1179}
1180
1181/// copyImplicitOps - Copy implicit register operands from specified
1182/// instruction to this instruction.
1183void MachineInstr::copyImplicitOps(MachineFunction &MF,
1184 const MachineInstr &MI) {
1185 for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands();
1186 i != e; ++i) {
1187 const MachineOperand &MO = MI.getOperand(i);
1188 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1189 addOperand(MF, MO);
1190 }
1191}
1192
1193bool MachineInstr::hasComplexRegisterTies() const {
1194 const MCInstrDesc &MCID = getDesc();
1195 for (unsigned I = 0, E = getNumOperands(); I < E; ++I) {
1196 const auto &Operand = getOperand(I);
1197 if (!Operand.isReg() || Operand.isDef())
1198 // Ignore the defined registers as MCID marks only the uses as tied.
1199 continue;
1200 int ExpectedTiedIdx = MCID.getOperandConstraint(I, MCOI::TIED_TO);
1201 int TiedIdx = Operand.isTied() ? int(findTiedOperandIdx(I)) : -1;
1202 if (ExpectedTiedIdx != TiedIdx)
1203 return true;
1204 }
1205 return false;
1206}
1207
1208LLT MachineInstr::getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes,
1209 const MachineRegisterInfo &MRI) const {
1210 const MachineOperand &Op = getOperand(OpIdx);
1211 if (!Op.isReg())
1212 return LLT{};
1213
1214 if (isVariadic() || OpIdx >= getNumExplicitOperands())
1215 return MRI.getType(Op.getReg());
1216
1217 auto &OpInfo = getDesc().OpInfo[OpIdx];
1218 if (!OpInfo.isGenericType())
1219 return MRI.getType(Op.getReg());
1220
1221 if (PrintedTypes[OpInfo.getGenericTypeIndex()])
1222 return LLT{};
1223
1224 PrintedTypes.set(OpInfo.getGenericTypeIndex());
1225 return MRI.getType(Op.getReg());
1226}
1227
1228#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1229LLVM_DUMP_METHOD__attribute__((noinline)) __attribute__((__used__)) void MachineInstr::dump() const {
1230 dbgs() << " ";
1231 print(dbgs());
1232}
1233#endif
1234
1235void MachineInstr::print(raw_ostream &OS, bool IsStandalone, bool SkipOpers,
1236 bool SkipDebugLoc, const TargetInstrInfo *TII) const {
1237 const Module *M = nullptr;
1238 const Function *F = nullptr;
1239 if (const MachineFunction *MF = getMFIfAvailable(*this)) {
1240 F = &MF->getFunction();
1241 M = F->getParent();
1242 }
1243
1244 ModuleSlotTracker MST(M);
1245 if (F)
1246 MST.incorporateFunction(*F);
1247 print(OS, MST, IsStandalone, SkipOpers, SkipDebugLoc, TII);
1248}
1249
1250void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1251 bool IsStandalone, bool SkipOpers, bool SkipDebugLoc,
1252 const TargetInstrInfo *TII) const {
1253 // We can be a bit tidier if we know the MachineFunction.
1254 const MachineFunction *MF = nullptr;
1255 const TargetRegisterInfo *TRI = nullptr;
1256 const MachineRegisterInfo *MRI = nullptr;
1257 const TargetIntrinsicInfo *IntrinsicInfo = nullptr;
1258 tryToGetTargetInfo(*this, TRI, MRI, IntrinsicInfo, TII);
1259
1260 if (isCFIInstruction())
1261 assert(getNumOperands() == 1 && "Expected 1 operand in CFI instruction")(static_cast <bool> (getNumOperands() == 1 && "Expected 1 operand in CFI instruction"
) ? void (0) : __assert_fail ("getNumOperands() == 1 && \"Expected 1 operand in CFI instruction\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1261, __extension__ __PRETTY_FUNCTION__))
;
1262
1263 SmallBitVector PrintedTypes(8);
1264 bool ShouldPrintRegisterTies = hasComplexRegisterTies();
1265 auto getTiedOperandIdx = [&](unsigned OpIdx) {
1266 if (!ShouldPrintRegisterTies)
1267 return 0U;
1268 const MachineOperand &MO = getOperand(OpIdx);
1269 if (MO.isReg() && MO.isTied() && !MO.isDef())
1270 return findTiedOperandIdx(OpIdx);
1271 return 0U;
1272 };
1273 unsigned StartOp = 0;
1274 unsigned e = getNumOperands();
1275
1276 // Print explicitly defined operands on the left of an assignment syntax.
1277 while (StartOp < e) {
1278 const MachineOperand &MO = getOperand(StartOp);
1279 if (!MO.isReg() || !MO.isDef() || MO.isImplicit())
1280 break;
1281
1282 if (StartOp != 0)
1283 OS << ", ";
1284
1285 LLT TypeToPrint = MRI ? getTypeToPrint(StartOp, PrintedTypes, *MRI) : LLT{};
1286 unsigned TiedOperandIdx = getTiedOperandIdx(StartOp);
1287 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/false, IsStandalone,
1288 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1289 ++StartOp;
1290 }
1291
1292 if (StartOp != 0)
1293 OS << " = ";
1294
1295 if (getFlag(MachineInstr::FrameSetup))
1296 OS << "frame-setup ";
1297 else if (getFlag(MachineInstr::FrameDestroy))
1298 OS << "frame-destroy ";
1299
1300 // Print the opcode name.
1301 if (TII)
1302 OS << TII->getName(getOpcode());
1303 else
1304 OS << "UNKNOWN";
1305
1306 if (SkipOpers)
1307 return;
1308
1309 // Print the rest of the operands.
1310 bool FirstOp = true;
1311 unsigned AsmDescOp = ~0u;
1312 unsigned AsmOpCount = 0;
1313
1314 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1315 // Print asm string.
1316 OS << " ";
1317 const unsigned OpIdx = InlineAsm::MIOp_AsmString;
1318 LLT TypeToPrint = MRI ? getTypeToPrint(OpIdx, PrintedTypes, *MRI) : LLT{};
1319 unsigned TiedOperandIdx = getTiedOperandIdx(OpIdx);
1320 getOperand(OpIdx).print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1321 ShouldPrintRegisterTies, TiedOperandIdx, TRI,
1322 IntrinsicInfo);
1323
1324 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1325 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1326 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1327 OS << " [sideeffect]";
1328 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1329 OS << " [mayload]";
1330 if (ExtraInfo & InlineAsm::Extra_MayStore)
1331 OS << " [maystore]";
1332 if (ExtraInfo & InlineAsm::Extra_IsConvergent)
1333 OS << " [isconvergent]";
1334 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1335 OS << " [alignstack]";
1336 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1337 OS << " [attdialect]";
1338 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1339 OS << " [inteldialect]";
1340
1341 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1342 FirstOp = false;
1343 }
1344
1345 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1346 const MachineOperand &MO = getOperand(i);
1347
1348 if (FirstOp) FirstOp = false; else OS << ",";
1349 OS << " ";
1350
1351 if (isDebugValue() && MO.isMetadata()) {
1352 // Pretty print DBG_VALUE instructions.
1353 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1354 if (DIV && !DIV->getName().empty())
1355 OS << "!\"" << DIV->getName() << '\"';
1356 else {
1357 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1358 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1359 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1360 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1361 }
1362 } else if (i == AsmDescOp && MO.isImm()) {
1363 // Pretty print the inline asm operand descriptor.
1364 OS << '$' << AsmOpCount++;
1365 unsigned Flag = MO.getImm();
1366 switch (InlineAsm::getKind(Flag)) {
1367 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1368 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1369 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1370 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1371 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1372 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1373 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1374 }
1375
1376 unsigned RCID = 0;
1377 if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
1378 InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1379 if (TRI) {
1380 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1381 } else
1382 OS << ":RC" << RCID;
1383 }
1384
1385 if (InlineAsm::isMemKind(Flag)) {
1386 unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
1387 switch (MCID) {
1388 case InlineAsm::Constraint_es: OS << ":es"; break;
1389 case InlineAsm::Constraint_i: OS << ":i"; break;
1390 case InlineAsm::Constraint_m: OS << ":m"; break;
1391 case InlineAsm::Constraint_o: OS << ":o"; break;
1392 case InlineAsm::Constraint_v: OS << ":v"; break;
1393 case InlineAsm::Constraint_Q: OS << ":Q"; break;
1394 case InlineAsm::Constraint_R: OS << ":R"; break;
1395 case InlineAsm::Constraint_S: OS << ":S"; break;
1396 case InlineAsm::Constraint_T: OS << ":T"; break;
1397 case InlineAsm::Constraint_Um: OS << ":Um"; break;
1398 case InlineAsm::Constraint_Un: OS << ":Un"; break;
1399 case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
1400 case InlineAsm::Constraint_Us: OS << ":Us"; break;
1401 case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
1402 case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
1403 case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
1404 case InlineAsm::Constraint_X: OS << ":X"; break;
1405 case InlineAsm::Constraint_Z: OS << ":Z"; break;
1406 case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
1407 case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
1408 default: OS << ":?"; break;
1409 }
1410 }
1411
1412 unsigned TiedTo = 0;
1413 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1414 OS << " tiedto:$" << TiedTo;
1415
1416 OS << ']';
1417
1418 // Compute the index of the next operand descriptor.
1419 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1420 } else {
1421 LLT TypeToPrint = MRI ? getTypeToPrint(i, PrintedTypes, *MRI) : LLT{};
1422 unsigned TiedOperandIdx = getTiedOperandIdx(i);
1423 if (MO.isImm() && isOperandSubregIdx(i))
1424 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI);
1425 else
1426 MO.print(OS, MST, TypeToPrint, /*PrintDef=*/true, IsStandalone,
1427 ShouldPrintRegisterTies, TiedOperandIdx, TRI, IntrinsicInfo);
1428 }
1429 }
1430
1431 if (!SkipDebugLoc) {
1432 if (const DebugLoc &DL = getDebugLoc()) {
1433 if (!FirstOp)
1434 OS << ',';
1435 OS << " debug-location ";
1436 DL->printAsOperand(OS, MST);
1437 }
1438 }
1439
1440 bool HaveSemi = false;
1441 if (!memoperands_empty()) {
1442 if (!HaveSemi) {
1443 OS << ";";
1444 HaveSemi = true;
1445 }
1446
1447 OS << " mem:";
1448 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1449 i != e; ++i) {
1450 (*i)->print(OS, MST);
1451 if (std::next(i) != e)
1452 OS << " ";
1453 }
1454 }
1455
1456 if (SkipDebugLoc)
1457 return;
1458
1459 // Print debug location information.
1460 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1461 if (!HaveSemi)
1462 OS << ";";
1463 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1464 OS << " line no:" << DV->getLine();
1465 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1466 DebugLoc InlinedAtDL(InlinedAt);
1467 if (InlinedAtDL && MF) {
1468 OS << " inlined @[ ";
1469 InlinedAtDL.print(OS);
1470 OS << " ]";
1471 }
1472 }
1473 if (isIndirectDebugValue())
1474 OS << " indirect";
1475 }
1476
1477 OS << '\n';
1478}
1479
1480bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1481 const TargetRegisterInfo *RegInfo,
1482 bool AddIfNotFound) {
1483 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1484 bool hasAliases = isPhysReg &&
1485 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1486 bool Found = false;
1487 SmallVector<unsigned,4> DeadOps;
1488 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1489 MachineOperand &MO = getOperand(i);
1490 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1491 continue;
1492
1493 // DEBUG_VALUE nodes do not contribute to code generation and should
1494 // always be ignored. Failure to do so may result in trying to modify
1495 // KILL flags on DEBUG_VALUE nodes.
1496 if (MO.isDebug())
1497 continue;
1498
1499 unsigned Reg = MO.getReg();
1500 if (!Reg)
1501 continue;
1502
1503 if (Reg == IncomingReg) {
1504 if (!Found) {
1505 if (MO.isKill())
1506 // The register is already marked kill.
1507 return true;
1508 if (isPhysReg && isRegTiedToDefOperand(i))
1509 // Two-address uses of physregs must not be marked kill.
1510 return true;
1511 MO.setIsKill();
1512 Found = true;
1513 }
1514 } else if (hasAliases && MO.isKill() &&
1515 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1516 // A super-register kill already exists.
1517 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1518 return true;
1519 if (RegInfo->isSubRegister(IncomingReg, Reg))
1520 DeadOps.push_back(i);
1521 }
1522 }
1523
1524 // Trim unneeded kill operands.
1525 while (!DeadOps.empty()) {
1526 unsigned OpIdx = DeadOps.back();
1527 if (getOperand(OpIdx).isImplicit())
1528 RemoveOperand(OpIdx);
1529 else
1530 getOperand(OpIdx).setIsKill(false);
1531 DeadOps.pop_back();
1532 }
1533
1534 // If not found, this means an alias of one of the operands is killed. Add a
1535 // new implicit operand if required.
1536 if (!Found && AddIfNotFound) {
1537 addOperand(MachineOperand::CreateReg(IncomingReg,
1538 false /*IsDef*/,
1539 true /*IsImp*/,
1540 true /*IsKill*/));
1541 return true;
1542 }
1543 return Found;
1544}
1545
1546void MachineInstr::clearRegisterKills(unsigned Reg,
1547 const TargetRegisterInfo *RegInfo) {
1548 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1549 RegInfo = nullptr;
1550 for (MachineOperand &MO : operands()) {
1551 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1552 continue;
1553 unsigned OpReg = MO.getReg();
1554 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg)
1555 MO.setIsKill(false);
1556 }
1557}
1558
1559bool MachineInstr::addRegisterDead(unsigned Reg,
1560 const TargetRegisterInfo *RegInfo,
1561 bool AddIfNotFound) {
1562 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1563 bool hasAliases = isPhysReg &&
1564 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1565 bool Found = false;
1566 SmallVector<unsigned,4> DeadOps;
1567 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1568 MachineOperand &MO = getOperand(i);
1569 if (!MO.isReg() || !MO.isDef())
1570 continue;
1571 unsigned MOReg = MO.getReg();
1572 if (!MOReg)
1573 continue;
1574
1575 if (MOReg == Reg) {
1576 MO.setIsDead();
1577 Found = true;
1578 } else if (hasAliases && MO.isDead() &&
1579 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1580 // There exists a super-register that's marked dead.
1581 if (RegInfo->isSuperRegister(Reg, MOReg))
1582 return true;
1583 if (RegInfo->isSubRegister(Reg, MOReg))
1584 DeadOps.push_back(i);
1585 }
1586 }
1587
1588 // Trim unneeded dead operands.
1589 while (!DeadOps.empty()) {
1590 unsigned OpIdx = DeadOps.back();
1591 if (getOperand(OpIdx).isImplicit())
1592 RemoveOperand(OpIdx);
1593 else
1594 getOperand(OpIdx).setIsDead(false);
1595 DeadOps.pop_back();
1596 }
1597
1598 // If not found, this means an alias of one of the operands is dead. Add a
1599 // new implicit operand if required.
1600 if (Found || !AddIfNotFound)
1601 return Found;
1602
1603 addOperand(MachineOperand::CreateReg(Reg,
1604 true /*IsDef*/,
1605 true /*IsImp*/,
1606 false /*IsKill*/,
1607 true /*IsDead*/));
1608 return true;
1609}
1610
1611void MachineInstr::clearRegisterDeads(unsigned Reg) {
1612 for (MachineOperand &MO : operands()) {
1613 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1614 continue;
1615 MO.setIsDead(false);
1616 }
1617}
1618
1619void MachineInstr::setRegisterDefReadUndef(unsigned Reg, bool IsUndef) {
1620 for (MachineOperand &MO : operands()) {
1621 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1622 continue;
1623 MO.setIsUndef(IsUndef);
1624 }
1625}
1626
1627void MachineInstr::addRegisterDefined(unsigned Reg,
1628 const TargetRegisterInfo *RegInfo) {
1629 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1630 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1631 if (MO)
1632 return;
1633 } else {
1634 for (const MachineOperand &MO : operands()) {
1635 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1636 MO.getSubReg() == 0)
1637 return;
1638 }
1639 }
1640 addOperand(MachineOperand::CreateReg(Reg,
1641 true /*IsDef*/,
1642 true /*IsImp*/));
1643}
1644
1645void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1646 const TargetRegisterInfo &TRI) {
1647 bool HasRegMask = false;
1648 for (MachineOperand &MO : operands()) {
1649 if (MO.isRegMask()) {
1650 HasRegMask = true;
1651 continue;
1652 }
1653 if (!MO.isReg() || !MO.isDef()) continue;
1654 unsigned Reg = MO.getReg();
1655 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1656 // If there are no uses, including partial uses, the def is dead.
1657 if (llvm::none_of(UsedRegs,
1658 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1659 MO.setIsDead();
1660 }
1661
1662 // This is a call with a register mask operand.
1663 // Mask clobbers are always dead, so add defs for the non-dead defines.
1664 if (HasRegMask)
1665 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1666 I != E; ++I)
1667 addRegisterDefined(*I, &TRI);
1668}
1669
1670unsigned
1671MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1672 // Build up a buffer of hash code components.
1673 SmallVector<size_t, 8> HashComponents;
1674 HashComponents.reserve(MI->getNumOperands() + 1);
1675 HashComponents.push_back(MI->getOpcode());
1676 for (const MachineOperand &MO : MI->operands()) {
1677 if (MO.isReg() && MO.isDef() &&
1678 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1679 continue; // Skip virtual register defs.
1680
1681 HashComponents.push_back(hash_value(MO));
1682 }
1683 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1684}
1685
1686void MachineInstr::emitError(StringRef Msg) const {
1687 // Find the source location cookie.
1688 unsigned LocCookie = 0;
1689 const MDNode *LocMD = nullptr;
1690 for (unsigned i = getNumOperands(); i != 0; --i) {
1691 if (getOperand(i-1).isMetadata() &&
1692 (LocMD = getOperand(i-1).getMetadata()) &&
1693 LocMD->getNumOperands() != 0) {
1694 if (const ConstantInt *CI =
1695 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1696 LocCookie = CI->getZExtValue();
1697 break;
1698 }
1699 }
1700 }
1701
1702 if (const MachineBasicBlock *MBB = getParent())
1703 if (const MachineFunction *MF = MBB->getParent())
1704 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1705 report_fatal_error(Msg);
1706}
1707
1708MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
1709 const MCInstrDesc &MCID, bool IsIndirect,
1710 unsigned Reg, const MDNode *Variable,
1711 const MDNode *Expr) {
1712 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1712, __extension__ __PRETTY_FUNCTION__))
;
1713 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1713, __extension__ __PRETTY_FUNCTION__))
;
1714 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1715, __extension__ __PRETTY_FUNCTION__))
1715 "Expected inlined-at fields to agree")(static_cast <bool> (cast<DILocalVariable>(Variable
)->isValidLocationForIntrinsic(DL) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1715, __extension__ __PRETTY_FUNCTION__))
;
1716 if (IsIndirect)
1717 return BuildMI(MF, DL, MCID)
1718 .addReg(Reg, RegState::Debug)
1719 .addImm(0U)
1720 .addMetadata(Variable)
1721 .addMetadata(Expr);
1722 else
1723 return BuildMI(MF, DL, MCID)
1724 .addReg(Reg, RegState::Debug)
1725 .addReg(0U, RegState::Debug)
1726 .addMetadata(Variable)
1727 .addMetadata(Expr);
1728}
1729
1730MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
1731 MachineBasicBlock::iterator I,
1732 const DebugLoc &DL, const MCInstrDesc &MCID,
1733 bool IsIndirect, unsigned Reg,
1734 const MDNode *Variable, const MDNode *Expr) {
1735 assert(isa<DILocalVariable>(Variable) && "not a variable")(static_cast <bool> (isa<DILocalVariable>(Variable
) && "not a variable") ? void (0) : __assert_fail ("isa<DILocalVariable>(Variable) && \"not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1735, __extension__ __PRETTY_FUNCTION__))
;
1736 assert(cast<DIExpression>(Expr)->isValid() && "not an expression")(static_cast <bool> (cast<DIExpression>(Expr)->
isValid() && "not an expression") ? void (0) : __assert_fail
("cast<DIExpression>(Expr)->isValid() && \"not an expression\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1736, __extension__ __PRETTY_FUNCTION__))
;
1737 MachineFunction &MF = *BB.getParent();
1738 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Variable, Expr);
1739 BB.insert(I, MI);
1740 return MachineInstrBuilder(MF, MI);
1741}
1742
1743/// Compute the new DIExpression to use with a DBG_VALUE for a spill slot.
1744/// This prepends DW_OP_deref when spilling an indirect DBG_VALUE.
1745static const DIExpression *computeExprForSpill(const MachineInstr &MI) {
1746 assert(MI.getOperand(0).isReg() && "can't spill non-register")(static_cast <bool> (MI.getOperand(0).isReg() &&
"can't spill non-register") ? void (0) : __assert_fail ("MI.getOperand(0).isReg() && \"can't spill non-register\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1746, __extension__ __PRETTY_FUNCTION__))
;
1747 assert(MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) &&(static_cast <bool> (MI.getDebugVariable()->isValidLocationForIntrinsic
(MI.getDebugLoc()) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1748, __extension__ __PRETTY_FUNCTION__))
1748 "Expected inlined-at fields to agree")(static_cast <bool> (MI.getDebugVariable()->isValidLocationForIntrinsic
(MI.getDebugLoc()) && "Expected inlined-at fields to agree"
) ? void (0) : __assert_fail ("MI.getDebugVariable()->isValidLocationForIntrinsic(MI.getDebugLoc()) && \"Expected inlined-at fields to agree\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1748, __extension__ __PRETTY_FUNCTION__))
;
1749
1750 const DIExpression *Expr = MI.getDebugExpression();
1751 if (MI.isIndirectDebugValue()) {
1752 assert(MI.getOperand(1).getImm() == 0 && "DBG_VALUE with nonzero offset")(static_cast <bool> (MI.getOperand(1).getImm() == 0 &&
"DBG_VALUE with nonzero offset") ? void (0) : __assert_fail (
"MI.getOperand(1).getImm() == 0 && \"DBG_VALUE with nonzero offset\""
, "/build/llvm-toolchain-snapshot-7~svn324650/lib/CodeGen/MachineInstr.cpp"
, 1752, __extension__ __PRETTY_FUNCTION__))
;
1753 Expr = DIExpression::prepend(Expr, DIExpression::WithDeref);
1754 }
1755 return Expr;
1756}
1757
1758MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
1759 MachineBasicBlock::iterator I,
1760 const MachineInstr &Orig,
1761 int FrameIndex) {
1762 const DIExpression *Expr = computeExprForSpill(Orig);
1763 return BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc())
1
Calling 'MachineInstrBuilder::addFrameIndex'
1764 .addFrameIndex(FrameIndex)
1765 .addImm(0U)
1766 .addMetadata(Orig.getDebugVariable())
1767 .addMetadata(Expr);
1768}
1769
1770void llvm::updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex) {
1771 const DIExpression *Expr = computeExprForSpill(Orig);
1772 Orig.getOperand(0).ChangeToFrameIndex(FrameIndex);
1773 Orig.getOperand(1).ChangeToImmediate(0U);
1774 Orig.getOperand(3).setMetadata(Expr);
1775}

/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h

1//===- CodeGen/MachineInstrBuilder.h - Simplify creation of MIs --*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file exposes a function named BuildMI, which is useful for dramatically
11// simplifying how MachineInstr's are created. It allows use of code like this:
12//
13// M = BuildMI(MBB, MI, DL, TII.get(X86::ADD8rr), Dst)
14// .addReg(argVal1)
15// .addReg(argVal2);
16//
17//===----------------------------------------------------------------------===//
18
19#ifndef LLVM_CODEGEN_MACHINEINSTRBUILDER_H
20#define LLVM_CODEGEN_MACHINEINSTRBUILDER_H
21
22#include "llvm/ADT/ArrayRef.h"
23#include "llvm/CodeGen/GlobalISel/Utils.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineFunction.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/MachineInstrBundle.h"
28#include "llvm/CodeGen/MachineOperand.h"
29#include "llvm/CodeGen/TargetRegisterInfo.h"
30#include "llvm/IR/InstrTypes.h"
31#include "llvm/IR/Intrinsics.h"
32#include "llvm/Support/ErrorHandling.h"
33#include <cassert>
34#include <cstdint>
35#include <utility>
36
37namespace llvm {
38
39class MCInstrDesc;
40class MDNode;
41
42namespace RegState {
43
44 enum {
45 Define = 0x2,
46 Implicit = 0x4,
47 Kill = 0x8,
48 Dead = 0x10,
49 Undef = 0x20,
50 EarlyClobber = 0x40,
51 Debug = 0x80,
52 InternalRead = 0x100,
53 Renamable = 0x200,
54 DefineNoRead = Define | Undef,
55 ImplicitDefine = Implicit | Define,
56 ImplicitKill = Implicit | Kill
57 };
58
59} // end namespace RegState
60
61class MachineInstrBuilder {
62 MachineFunction *MF = nullptr;
63 MachineInstr *MI = nullptr;
64
65public:
66 MachineInstrBuilder() = default;
67
68 /// Create a MachineInstrBuilder for manipulating an existing instruction.
69 /// F must be the machine function that was used to allocate I.
70 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {}
71 MachineInstrBuilder(MachineFunction &F, MachineBasicBlock::iterator I)
72 : MF(&F), MI(&*I) {}
73
74 /// Allow automatic conversion to the machine instruction we are working on.
75 operator MachineInstr*() const { return MI; }
76 MachineInstr *operator->() const { return MI; }
77 operator MachineBasicBlock::iterator() const { return MI; }
78
79 /// If conversion operators fail, use this method to get the MachineInstr
80 /// explicitly.
81 MachineInstr *getInstr() const { return MI; }
82
83 /// Add a new virtual register operand.
84 const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
85 unsigned SubReg = 0) const {
86 assert((flags & 0x1) == 0 &&(static_cast <bool> ((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."
) ? void (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 87, __extension__ __PRETTY_FUNCTION__))
87 "Passing in 'true' to addReg is forbidden! Use enums instead.")(static_cast <bool> ((flags & 0x1) == 0 && "Passing in 'true' to addReg is forbidden! Use enums instead."
) ? void (0) : __assert_fail ("(flags & 0x1) == 0 && \"Passing in 'true' to addReg is forbidden! Use enums instead.\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 87, __extension__ __PRETTY_FUNCTION__))
;
88 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
89 flags & RegState::Define,
90 flags & RegState::Implicit,
91 flags & RegState::Kill,
92 flags & RegState::Dead,
93 flags & RegState::Undef,
94 flags & RegState::EarlyClobber,
95 SubReg,
96 flags & RegState::Debug,
97 flags & RegState::InternalRead,
98 flags & RegState::Renamable));
99 return *this;
100 }
101
102 /// Add a virtual register definition operand.
103 const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0,
104 unsigned SubReg = 0) const {
105 return addReg(RegNo, Flags | RegState::Define, SubReg);
106 }
107
108 /// Add a virtual register use operand. It is an error for Flags to contain
109 /// `RegState::Define` when calling this function.
110 const MachineInstrBuilder &addUse(unsigned RegNo, unsigned Flags = 0,
111 unsigned SubReg = 0) const {
112 assert(!(Flags & RegState::Define) &&(static_cast <bool> (!(Flags & RegState::Define) &&
"Misleading addUse defines register, use addReg instead.") ?
void (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 113, __extension__ __PRETTY_FUNCTION__))
113 "Misleading addUse defines register, use addReg instead.")(static_cast <bool> (!(Flags & RegState::Define) &&
"Misleading addUse defines register, use addReg instead.") ?
void (0) : __assert_fail ("!(Flags & RegState::Define) && \"Misleading addUse defines register, use addReg instead.\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 113, __extension__ __PRETTY_FUNCTION__))
;
114 return addReg(RegNo, Flags, SubReg);
115 }
116
117 /// Add a new immediate operand.
118 const MachineInstrBuilder &addImm(int64_t Val) const {
119 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
120 return *this;
121 }
122
123 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
124 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
125 return *this;
126 }
127
128 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
129 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
130 return *this;
131 }
132
133 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
134 unsigned char TargetFlags = 0) const {
135 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
136 return *this;
137 }
138
139 const MachineInstrBuilder &addFrameIndex(int Idx) const {
140 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
2
Calling 'MachineInstr::addOperand'
141 return *this;
142 }
143
144 const MachineInstrBuilder &addConstantPoolIndex(unsigned Idx,
145 int Offset = 0,
146 unsigned char TargetFlags = 0) const {
147 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
148 return *this;
149 }
150
151 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
152 unsigned char TargetFlags = 0) const {
153 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
154 TargetFlags));
155 return *this;
156 }
157
158 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
159 unsigned char TargetFlags = 0) const {
160 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
161 return *this;
162 }
163
164 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
165 int64_t Offset = 0,
166 unsigned char TargetFlags = 0) const {
167 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags));
168 return *this;
169 }
170
171 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
172 unsigned char TargetFlags = 0) const {
173 MI->addOperand(*MF, MachineOperand::CreateES(FnName, TargetFlags));
174 return *this;
175 }
176
177 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
178 int64_t Offset = 0,
179 unsigned char TargetFlags = 0) const {
180 MI->addOperand(*MF, MachineOperand::CreateBA(BA, Offset, TargetFlags));
181 return *this;
182 }
183
184 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
185 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
186 return *this;
187 }
188
189 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
190 MI->addMemOperand(*MF, MMO);
191 return *this;
192 }
193
194 const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b,
195 MachineInstr::mmo_iterator e) const {
196 MI->setMemRefs(b, e);
197 return *this;
198 }
199
200 const MachineInstrBuilder &setMemRefs(std::pair<MachineInstr::mmo_iterator,
201 unsigned> MemOperandsRef) const {
202 MI->setMemRefs(MemOperandsRef);
203 return *this;
204 }
205
206 const MachineInstrBuilder &add(const MachineOperand &MO) const {
207 MI->addOperand(*MF, MO);
208 return *this;
209 }
210
211 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
212 for (const MachineOperand &MO : MOs) {
213 MI->addOperand(*MF, MO);
214 }
215 return *this;
216 }
217
218 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
219 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
220 assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())(static_cast <bool> ((MI->isDebugValue() ? static_cast
<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? void (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 222, __extension__ __PRETTY_FUNCTION__))
221 : true) &&(static_cast <bool> ((MI->isDebugValue() ? static_cast
<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? void (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 222, __extension__ __PRETTY_FUNCTION__))
222 "first MDNode argument of a DBG_VALUE not a variable")(static_cast <bool> ((MI->isDebugValue() ? static_cast
<bool>(MI->getDebugVariable()) : true) && "first MDNode argument of a DBG_VALUE not a variable"
) ? void (0) : __assert_fail ("(MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable()) : true) && \"first MDNode argument of a DBG_VALUE not a variable\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 222, __extension__ __PRETTY_FUNCTION__))
;
223 return *this;
224 }
225
226 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
227 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
228 return *this;
229 }
230
231 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
232 MI->addOperand(*MF, MachineOperand::CreateIntrinsicID(ID));
233 return *this;
234 }
235
236 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
237 MI->addOperand(*MF, MachineOperand::CreatePredicate(Pred));
238 return *this;
239 }
240
241 const MachineInstrBuilder &addSym(MCSymbol *Sym,
242 unsigned char TargetFlags = 0) const {
243 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym, TargetFlags));
244 return *this;
245 }
246
247 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
248 MI->setFlags(Flags);
249 return *this;
250 }
251
252 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
253 MI->setFlag(Flag);
254 return *this;
255 }
256
257 // Add a displacement from an existing MachineOperand with an added offset.
258 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
259 unsigned char TargetFlags = 0) const {
260 // If caller specifies new TargetFlags then use it, otherwise the
261 // default behavior is to copy the target flags from the existing
262 // MachineOperand. This means if the caller wants to clear the
263 // target flags it needs to do so explicitly.
264 if (0 == TargetFlags)
265 TargetFlags = Disp.getTargetFlags();
266
267 switch (Disp.getType()) {
268 default:
269 llvm_unreachable("Unhandled operand type in addDisp()")::llvm::llvm_unreachable_internal("Unhandled operand type in addDisp()"
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 269)
;
270 case MachineOperand::MO_Immediate:
271 return addImm(Disp.getImm() + off);
272 case MachineOperand::MO_ConstantPoolIndex:
273 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
274 TargetFlags);
275 case MachineOperand::MO_GlobalAddress:
276 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
277 TargetFlags);
278 }
279 }
280
281 /// Copy all the implicit operands from OtherMI onto this one.
282 const MachineInstrBuilder &
283 copyImplicitOps(const MachineInstr &OtherMI) const {
284 MI->copyImplicitOps(*MF, OtherMI);
285 return *this;
286 }
287
288 bool constrainAllUses(const TargetInstrInfo &TII,
289 const TargetRegisterInfo &TRI,
290 const RegisterBankInfo &RBI) const {
291 return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
292 }
293};
294
295/// Builder interface. Specify how to create the initial instruction itself.
296inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
297 const MCInstrDesc &MCID) {
298 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL));
299}
300
301/// This version of the builder sets up the first operand as a
302/// destination virtual register.
303inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
304 const MCInstrDesc &MCID, unsigned DestReg) {
305 return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, DL))
306 .addReg(DestReg, RegState::Define);
307}
308
309/// This version of the builder inserts the newly-built instruction before
310/// the given position in the given MachineBasicBlock, and sets up the first
311/// operand as a destination virtual register.
312inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
313 MachineBasicBlock::iterator I,
314 const DebugLoc &DL, const MCInstrDesc &MCID,
315 unsigned DestReg) {
316 MachineFunction &MF = *BB.getParent();
317 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
318 BB.insert(I, MI);
319 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
320}
321
322/// This version of the builder inserts the newly-built instruction before
323/// the given position in the given MachineBasicBlock, and sets up the first
324/// operand as a destination virtual register.
325///
326/// If \c I is inside a bundle, then the newly inserted \a MachineInstr is
327/// added to the same bundle.
328inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
329 MachineBasicBlock::instr_iterator I,
330 const DebugLoc &DL, const MCInstrDesc &MCID,
331 unsigned DestReg) {
332 MachineFunction &MF = *BB.getParent();
333 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
334 BB.insert(I, MI);
335 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
336}
337
338inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
339 const DebugLoc &DL, const MCInstrDesc &MCID,
340 unsigned DestReg) {
341 // Calling the overload for instr_iterator is always correct. However, the
342 // definition is not available in headers, so inline the check.
343 if (I.isInsideBundle())
344 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg);
345 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
346}
347
348inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
349 const DebugLoc &DL, const MCInstrDesc &MCID,
350 unsigned DestReg) {
351 return BuildMI(BB, *I, DL, MCID, DestReg);
352}
353
354/// This version of the builder inserts the newly-built instruction before the
355/// given position in the given MachineBasicBlock, and does NOT take a
356/// destination register.
357inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
358 MachineBasicBlock::iterator I,
359 const DebugLoc &DL,
360 const MCInstrDesc &MCID) {
361 MachineFunction &MF = *BB.getParent();
362 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
363 BB.insert(I, MI);
364 return MachineInstrBuilder(MF, MI);
365}
366
367inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
368 MachineBasicBlock::instr_iterator I,
369 const DebugLoc &DL,
370 const MCInstrDesc &MCID) {
371 MachineFunction &MF = *BB.getParent();
372 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL);
373 BB.insert(I, MI);
374 return MachineInstrBuilder(MF, MI);
375}
376
377inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
378 const DebugLoc &DL,
379 const MCInstrDesc &MCID) {
380 // Calling the overload for instr_iterator is always correct. However, the
381 // definition is not available in headers, so inline the check.
382 if (I.isInsideBundle())
383 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID);
384 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID);
385}
386
387inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
388 const DebugLoc &DL,
389 const MCInstrDesc &MCID) {
390 return BuildMI(BB, *I, DL, MCID);
391}
392
393/// This version of the builder inserts the newly-built instruction at the end
394/// of the given MachineBasicBlock, and does NOT take a destination register.
395inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
396 const MCInstrDesc &MCID) {
397 return BuildMI(*BB, BB->end(), DL, MCID);
398}
399
400/// This version of the builder inserts the newly-built instruction at the
401/// end of the given MachineBasicBlock, and sets up the first operand as a
402/// destination virtual register.
403inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
404 const MCInstrDesc &MCID, unsigned DestReg) {
405 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
406}
407
408/// This version of the builder builds a DBG_VALUE intrinsic
409/// for either a value in a register or a register-indirect
410/// address. The convention is that a DBG_VALUE is indirect iff the
411/// second operand is an immediate.
412MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
413 const MCInstrDesc &MCID, bool IsIndirect,
414 unsigned Reg, const MDNode *Variable,
415 const MDNode *Expr);
416
417/// This version of the builder builds a DBG_VALUE intrinsic
418/// for either a value in a register or a register-indirect
419/// address and inserts it at position I.
420MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
421 MachineBasicBlock::iterator I, const DebugLoc &DL,
422 const MCInstrDesc &MCID, bool IsIndirect,
423 unsigned Reg, const MDNode *Variable,
424 const MDNode *Expr);
425
426/// Clone a DBG_VALUE whose value has been spilled to FrameIndex.
427MachineInstr *buildDbgValueForSpill(MachineBasicBlock &BB,
428 MachineBasicBlock::iterator I,
429 const MachineInstr &Orig, int FrameIndex);
430
431/// Update a DBG_VALUE whose value has been spilled to FrameIndex. Useful when
432/// modifying an instruction in place while iterating over a basic block.
433void updateDbgValueForSpill(MachineInstr &Orig, int FrameIndex);
434
435inline unsigned getDefRegState(bool B) {
436 return B ? RegState::Define : 0;
437}
438inline unsigned getImplRegState(bool B) {
439 return B ? RegState::Implicit : 0;
440}
441inline unsigned getKillRegState(bool B) {
442 return B ? RegState::Kill : 0;
443}
444inline unsigned getDeadRegState(bool B) {
445 return B ? RegState::Dead : 0;
446}
447inline unsigned getUndefRegState(bool B) {
448 return B ? RegState::Undef : 0;
449}
450inline unsigned getInternalReadRegState(bool B) {
451 return B ? RegState::InternalRead : 0;
452}
453inline unsigned getDebugRegState(bool B) {
454 return B ? RegState::Debug : 0;
455}
456inline unsigned getRenamableRegState(bool B) {
457 return B ? RegState::Renamable : 0;
458}
459
460/// Get all register state flags from machine operand \p RegOp.
461inline unsigned getRegState(const MachineOperand &RegOp) {
462 assert(RegOp.isReg() && "Not a register operand")(static_cast <bool> (RegOp.isReg() && "Not a register operand"
) ? void (0) : __assert_fail ("RegOp.isReg() && \"Not a register operand\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 462, __extension__ __PRETTY_FUNCTION__))
;
463 return getDefRegState(RegOp.isDef()) |
464 getImplRegState(RegOp.isImplicit()) |
465 getKillRegState(RegOp.isKill()) |
466 getDeadRegState(RegOp.isDead()) |
467 getUndefRegState(RegOp.isUndef()) |
468 getInternalReadRegState(RegOp.isInternalRead()) |
469 getDebugRegState(RegOp.isDebug()) |
470 getRenamableRegState(
471 TargetRegisterInfo::isPhysicalRegister(RegOp.getReg()) &&
472 RegOp.isRenamable());
473}
474
475/// Helper class for constructing bundles of MachineInstrs.
476///
477/// MIBundleBuilder can create a bundle from scratch by inserting new
478/// MachineInstrs one at a time, or it can create a bundle from a sequence of
479/// existing MachineInstrs in a basic block.
480class MIBundleBuilder {
481 MachineBasicBlock &MBB;
482 MachineBasicBlock::instr_iterator Begin;
483 MachineBasicBlock::instr_iterator End;
484
485public:
486 /// Create an MIBundleBuilder that inserts instructions into a new bundle in
487 /// BB above the bundle or instruction at Pos.
488 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator Pos)
489 : MBB(BB), Begin(Pos.getInstrIterator()), End(Begin) {}
490
491 /// Create a bundle from the sequence of instructions between B and E.
492 MIBundleBuilder(MachineBasicBlock &BB, MachineBasicBlock::iterator B,
493 MachineBasicBlock::iterator E)
494 : MBB(BB), Begin(B.getInstrIterator()), End(E.getInstrIterator()) {
495 assert(B != E && "No instructions to bundle")(static_cast <bool> (B != E && "No instructions to bundle"
) ? void (0) : __assert_fail ("B != E && \"No instructions to bundle\""
, "/build/llvm-toolchain-snapshot-7~svn324650/include/llvm/CodeGen/MachineInstrBuilder.h"
, 495, __extension__ __PRETTY_FUNCTION__))
;
496 ++B;
497 while (B != E) {
498 MachineInstr &MI = *B;
499 ++B;
500 MI.bundleWithPred();
501 }
502 }
503
504 /// Create an MIBundleBuilder representing an existing instruction or bundle
505 /// that has MI as its head.
506 explicit MIBundleBuilder(MachineInstr *MI)
507 : MBB(*MI->getParent()), Begin(MI),
508 End(getBundleEnd(MI->getIterator())) {}
509
510 /// Return a reference to the basic block containing this bundle.
511 MachineBasicBlock &getMBB() const { return MBB; }
512
513 /// Return true if no instructions have been inserted in this bundle yet.
514 /// Empty bundles aren't representable in a MachineBasicBlock.
515 bool empty() const { return Begin == End; }
516
517 /// Return an iterator to the first bundled instruction.
518 MachineBasicBlock::instr_iterator begin() const { return Begin; }
519
520 /// Return an iterator beyond the last bundled instruction.
521 MachineBasicBlock::instr_iterator end() const { return End; }
522
523 /// Insert MI into this bundle before I which must point to an instruction in
524 /// the bundle, or end().
525 MIBundleBuilder &insert(MachineBasicBlock::instr_iterator I,
526 MachineInstr *MI) {
527 MBB.insert(I, MI);
528 if (I == Begin) {
529 if (!empty())
530 MI->bundleWithSucc();
531 Begin = MI->getIterator();
532 return *this;
533 }
534 if (I == End) {
535 MI->bundleWithPred();
536 return *this;
537 }
538 // MI was inserted in the middle of the bundle, so its neighbors' flags are
539 // already fine. Update MI's bundle flags manually.
540 MI->setFlag(MachineInstr::BundledPred);
541 MI->setFlag(MachineInstr::BundledSucc);
542 return *this;
543 }
544
545 /// Insert MI into MBB by prepending it to the instructions in the bundle.
546 /// MI will become the first instruction in the bundle.
547 MIBundleBuilder &prepend(MachineInstr *MI) {
548 return insert(begin(), MI);
549 }
550
551 /// Insert MI into MBB by appending it to the instructions in the bundle.
552 /// MI will become the last instruction in the bundle.
553 MIBundleBuilder &append(MachineInstr *MI) {
554 return insert(end(), MI);
555 }
556};
557
558} // end namespace llvm
559
560#endif // LLVM_CODEGEN_MACHINEINSTRBUILDER_H